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drm/i915: use sw tracked state to select shared dplls
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
79e53945
JB		 490{
491 struct drm_device *dev = crtc->dev;
79e53945 492 intel_clock_t clock;
79e53945
JB		 493 int err = target;
494
a210b028 495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 496 /*
a210b028
DV		 497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
79e53945 500 */
1974cad0 501 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
0206e353 512 memset(best_clock, 0, sizeof(*best_clock));
79e53945 513
42158660
ZY		 514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
42158660
ZY		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 524 int this_err;
525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
e72f9fbf 926 bool state)
040484af 927{
040484af 928 bool cur_state;
5358901f 929 struct intel_dpll_hw_state hw_state;
040484af 930
9d82aa17
ED		 931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
92b27b08 936 if (WARN (!pll,
46edb027 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 938 return;
ee7b9f93 939
5358901f 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 941 WARN(cur_state != state,
5358901f
DV		 942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
040484af 944}
e9d6944e
DV		 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
040484af
JB		 947
948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950{
951 int reg;
952 u32 val;
953 bool cur_state;
ad80a810
PZ		 954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
040484af 956
affa9354
PZ		 957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
ad80a810 959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 960 val = I915_READ(reg);
ad80a810 961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
040484af
JB		 967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970}
971#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976{
977 int reg;
978 u32 val;
979 bool cur_state;
980
d63fa0dc
PZ		 981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987}
988#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
bf507ef7 1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1002 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1003 return;
1004
040484af
JB		 1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
19332d7a 1142 val = I915_READ(reg);
20674eef 1143 WARN((val & SPRITE_ENABLE),
06da8da2 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
63d7bbe9
JB		 1304/**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
7434a255
TR		 1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1316 */
1317static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321
58c6eaa2
DV		 1322 assert_pipe_disabled(dev_priv, pipe);
1323
63d7bbe9 1324 /* No really, not for ILK+ */
a0c4da24 1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345}
1346
1347/**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357{
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373}
1374
89b667f8
JB		 1375void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376{
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387}
1388
92f2584a 1389/**
e72f9fbf 1390 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
e2b78267 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1398{
e2b78267
DV		 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1404 if (WARN_ON(pll == NULL))
48da64a8
CW		 1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
ee7b9f93 1409
46edb027
DV		 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
e2b78267 1412 crtc->base.base.id);
92f2584a 1413
cdbd2316
DV		 1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
e9d6944e 1416 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1417 return;
1418 }
f4a091c7 1419 WARN_ON(pll->on);
ee7b9f93 1420
46edb027 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1422 pll->enable(dev_priv, pll);
ee7b9f93 1423 pll->on = true;
92f2584a
JB		 1424}
1425
e2b78267 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1427{
e2b78267
DV		 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1430
92f2584a
JB		 1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1433 if (WARN_ON(pll == NULL))
ee7b9f93 1434 return;
92f2584a 1435
48da64a8
CW		 1436 if (WARN_ON(pll->refcount == 0))
1437 return;
7a419866 1438
46edb027
DV		 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
e2b78267 1441 crtc->base.base.id);
7a419866 1442
48da64a8 1443 if (WARN_ON(pll->active == 0)) {
e9d6944e 1444 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1445 return;
1446 }
1447
e9d6944e 1448 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1449 WARN_ON(!pll->on);
cdbd2316 1450 if (--pll->active)
7a419866 1451 return;
ee7b9f93 1452
46edb027 1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1454 pll->disable(dev_priv, pll);
ee7b9f93 1455 pll->on = false;
92f2584a
JB		 1456}
1457
b8a4f404
PZ		 1458static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
040484af 1460{
23670b32 1461 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1464 uint32_t reg, val, pipeconf_val;
040484af
JB		 1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
e72f9fbf 1470 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1471 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
23670b32
DV		 1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
59c859d6 1484 }
23670b32 1485
ab9412ba 1486 reg = PCH_TRANSCONF(pipe);
040484af 1487 val = I915_READ(reg);
5f7f726d 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
dfd07d72
DV		 1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1497 }
5f7f726d
PZ		 1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
040484af
JB		 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1512}
1513
8fb033d7 1514static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1515 enum transcoder cpu_transcoder)
040484af 1516{
8fb033d7 1517 u32 val, pipeconf_val;
8fb033d7
PZ		 1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
8fb033d7 1522 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1525
223a6fdf
PZ		 1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
25f3ef11 1531 val = TRANS_ENABLE;
937bb610 1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1533
9a76b1c6
PZ		 1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
a35f2679 1536 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
ab9412ba
DV		 1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1542 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1543}
1544
b8a4f404
PZ		 1545static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
040484af 1547{
23670b32
DV		 1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
040484af
JB		 1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
291906f1
JB		 1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
ab9412ba 1558 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
040484af
JB		 1573}
1574
ab4d966c 1575static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1576{
8fb033d7
PZ		 1577 u32 val;
1578
ab9412ba 1579 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1580 val &= ~TRANS_ENABLE;
ab9412ba 1581 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1582 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1584 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1589 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1590}
1591
b24e7179 1592/**
309cfea8 1593 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
040484af 1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
040484af
JB		 1606static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
b24e7179 1608{
702e7a56
PZ		 1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1a240d4d 1611 enum pipe pch_transcoder;
b24e7179
JB		 1612 int reg;
1613 u32 val;
1614
58c6eaa2
DV		 1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
681e5811 1618 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
b24e7179
JB		 1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
cc391bbb 1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
040484af
JB		 1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
b24e7179 1639
702e7a56 1640 reg = PIPECONF(cpu_transcoder);
b24e7179 1641 val = I915_READ(reg);
00d70b15
CW		 1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647}
1648
1649/**
309cfea8 1650 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
b24e7179
JB		 1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
19332d7a 1674 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
702e7a56 1680 reg = PIPECONF(cpu_transcoder);
b24e7179 1681 val = I915_READ(reg);
00d70b15
CW		 1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687}
1688
d74362c9
KP		 1689/*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
6f1d69b0 1693void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1694 enum plane plane)
1695{
14f86147
DL		 1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1700}
1701
b24e7179
JB		 1702/**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712{
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
00d70b15
CW		 1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1725 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727}
1728
b24e7179
JB		 1729/**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739{
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
00d70b15
CW		 1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751}
1752
693db184
CW		 1753static bool need_vtd_wa(struct drm_device *dev)
1754{
1755#ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758#endif
1759 return false;
1760}
1761
127bd2ac 1762int
48b956c5 1763intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1764 struct drm_i915_gem_object *obj,
919926ae 1765 struct intel_ring_buffer *pipelined)
6b95a207 1766{
ce453d81 1767 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1768 u32 alignment;
1769 int ret;
1770
05394f39 1771 switch (obj->tiling_mode) {
6b95a207 1772 case I915_TILING_NONE:
534843da
CW		 1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
a6c45cf0 1775 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
6b95a207
KH		 1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
8bb6e959
DV		 1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
693db184
CW		 1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
ce453d81 1802 dev_priv->mm.interruptible = false;
2da3b9b9 1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1804 if (ret)
ce453d81 1805 goto err_interruptible;
6b95a207
KH		 1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
06d98131 1812 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1813 if (ret)
1814 goto err_unpin;
1690e1eb 1815
9a5a53b3 1816 i915_gem_object_pin_fence(obj);
6b95a207 1817
ce453d81 1818 dev_priv->mm.interruptible = true;
6b95a207 1819 return 0;
48b956c5
CW		 1820
1821err_unpin:
1822 i915_gem_object_unpin(obj);
ce453d81
CW		 1823err_interruptible:
1824 dev_priv->mm.interruptible = true;
48b956c5 1825 return ret;
6b95a207
KH		 1826}
1827
1690e1eb
CW		 1828void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829{
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832}
1833
c2c75131
DV		 1834/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
bc752862
CW		 1836unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
c2c75131 1840{
bc752862
CW		 1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
c2c75131 1843
bc752862
CW		 1844 tile_rows = *y / 8;
1845 *y %= 8;
c2c75131 1846
bc752862
CW		 1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
c2c75131
DV		 1859}
1860
17638cd6
JB		 1861static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
81255565
JB		 1863{
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
05394f39 1868 struct drm_i915_gem_object *obj;
81255565 1869 int plane = intel_crtc->plane;
e506a0c6 1870 unsigned long linear_offset;
81255565 1871 u32 dspcntr;
5eddb70b 1872 u32 reg;
81255565
JB		 1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
84f44ce7 1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
81255565 1885
5eddb70b
CW		 1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
81255565
JB		 1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
81255565
JB		 1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
57779d06
VS		 1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
81255565 1897 break;
57779d06
VS		 1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1916 break;
1917 default:
baba133a 1918 BUG();
81255565 1919 }
57779d06 1920
a6c45cf0 1921 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1922 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
de1aa629
VS		 1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
5eddb70b 1931 I915_WRITE(reg, dspcntr);
81255565 1932
e506a0c6 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1934
c2c75131
DV		 1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
bc752862
CW		 1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
c2c75131
DV		 1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
e506a0c6 1942 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1943 }
e506a0c6
DV		 1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1948 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1953 } else
e506a0c6 1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1955 POSTING_READ(reg);
81255565 1956
17638cd6
JB		 1957 return 0;
1958}
1959
1960static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
17638cd6
JB		 1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
27f8227b 1976 case 2:
17638cd6
JB		 1977 break;
1978 default:
84f44ce7 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
17638cd6
JB		 1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
57779d06
VS		 1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
17638cd6 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2012 break;
2013 default:
baba133a 2014 BUG();
17638cd6
JB		 2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
e506a0c6 2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2028 intel_crtc->dspaddr_offset =
bc752862
CW		 2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
c2c75131 2032 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2033
e506a0c6
DV		 2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
17638cd6
JB		 2045 POSTING_READ(reg);
2046
2047 return 0;
2048}
2049
2050/* Assume fb object is pinned & idle & fenced and just update base pointers */
2051static int
2052intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054{
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2057
6b8e6ed0
CW		 2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
3dec0095 2060 intel_increase_pllclock(crtc);
81255565 2061
6b8e6ed0 2062 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2063}
2064
96a02917
VS		 2065void intel_display_handle_reset(struct drm_device *dev)
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101}
2102
14667a4b
CW		 2103static int
2104intel_finish_fb(struct drm_framebuffer *old_fb)
2105{
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
14667a4b
CW		 2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124}
2125
198598d0
VS		 2126static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151}
2152
5c3b82e2 2153static int
3c4fdcfb 2154intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2155 struct drm_framebuffer *fb)
79e53945
JB		 2156{
2157 struct drm_device *dev = crtc->dev;
6b8e6ed0 2158 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2160 struct drm_framebuffer *old_fb;
5c3b82e2 2161 int ret;
79e53945
JB		 2162
2163 /* no fb bound */
94352cf9 2164 if (!fb) {
a5071c2f 2165 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2166 return 0;
2167 }
2168
7eb552ae 2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2173 return -EINVAL;
79e53945
JB		 2174 }
2175
5c3b82e2 2176 mutex_lock(&dev->struct_mutex);
265db958 2177 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2178 to_intel_framebuffer(fb)->obj,
919926ae 2179 NULL);
5c3b82e2
CW		 2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
a5071c2f 2182 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2183 return ret;
2184 }
79e53945 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28 2199 if (old_fb) {
d7697eea
DV		 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2203 }
652c393a 2204
6b8e6ed0 2205 intel_update_fbc(dev);
5c3b82e2 2206 mutex_unlock(&dev->struct_mutex);
79e53945 2207
198598d0 2208 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2209
2210 return 0;
79e53945
JB		 2211}
2212
5e84e1a4
ZW		 2213static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214{
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
61e499bf 2224 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2230 }
5e84e1a4
ZW		 2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
357555c0
JB		 2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2252}
2253
1e833f40
DV		 2254static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255{
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257}
2258
01a415fd
DV		 2259static void ivb_modeset_global_resources(struct drm_device *dev)
2260{
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
1e833f40
DV		 2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283}
2284
8db9d77b
ZW		 2285/* The FDI link training functions for ILK/Ibexpeak. */
2286static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287{
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
0fc932b8 2292 int plane = intel_crtc->plane;
5eddb70b 2293 u32 reg, temp, tries;
8db9d77b 2294
0fc932b8
JB		 2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
e1a44743
AJ		 2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
5eddb70b
CW		 2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
e1a44743
AJ		 2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
e1a44743
AJ		 2307 udelay(150);
2308
8db9d77b 2309 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
627eb5a3
DV		 2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2317
5eddb70b
CW		 2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
8db9d77b
ZW		 2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
8db9d77b
ZW		 2325 udelay(150);
2326
5b2adf89 2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2331
5eddb70b 2332 reg = FDI_RX_IIR(pipe);
e1a44743 2333 for (tries = 0; tries < 5; tries++) {
5eddb70b 2334 temp = I915_READ(reg);
8db9d77b
ZW		 2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2340 break;
2341 }
8db9d77b 2342 }
e1a44743 2343 if (tries == 5)
5eddb70b 2344 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2345
2346 /* Train 2 */
5eddb70b
CW		 2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
8db9d77b
ZW		 2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2351 I915_WRITE(reg, temp);
8db9d77b 2352
5eddb70b
CW		 2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
8db9d77b
ZW		 2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2357 I915_WRITE(reg, temp);
8db9d77b 2358
5eddb70b
CW		 2359 POSTING_READ(reg);
2360 udelay(150);
8db9d77b 2361
5eddb70b 2362 reg = FDI_RX_IIR(pipe);
e1a44743 2363 for (tries = 0; tries < 5; tries++) {
5eddb70b 2364 temp = I915_READ(reg);
8db9d77b
ZW		 2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
8db9d77b 2372 }
e1a44743 2373 if (tries == 5)
5eddb70b 2374 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2375
2376 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2377
8db9d77b
ZW		 2378}
2379
0206e353 2380static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385};
2386
2387/* The FDI link training functions for SNB/Cougarpoint. */
2388static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389{
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
fa37d39e 2394 u32 reg, temp, i, retry;
8db9d77b 2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
e1a44743
AJ		 2405 udelay(150);
2406
8db9d77b 2407 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
627eb5a3
DV		 2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
d74cf324
DV		 2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
5eddb70b
CW		 2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
5eddb70b
CW		 2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
8db9d77b
ZW		 2434 udelay(150);
2435
0206e353 2436 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(500);
2445
fa37d39e
SP		 2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
8db9d77b 2456 }
fa37d39e
SP		 2457 if (retry < 5)
2458 break;
8db9d77b
ZW		 2459 }
2460 if (i == 4)
5eddb70b 2461 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2462
2463 /* Train 2 */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
5eddb70b 2473 I915_WRITE(reg, temp);
8db9d77b 2474
5eddb70b
CW		 2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
5eddb70b
CW		 2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
8db9d77b
ZW		 2487 udelay(150);
2488
0206e353 2489 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
8db9d77b
ZW		 2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
8db9d77b
ZW		 2497 udelay(500);
2498
fa37d39e
SP		 2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
8db9d77b 2509 }
fa37d39e
SP		 2510 if (retry < 5)
2511 break;
8db9d77b
ZW		 2512 }
2513 if (i == 4)
5eddb70b 2514 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517}
2518
357555c0
JB		 2519/* Manual link training for Ivy Bridge A0 parts */
2520static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
01a415fd
DV		 2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
357555c0
JB		 2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
627eb5a3
DV		 2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2551 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
d74cf324
DV		 2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
357555c0
JB		 2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2562 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
357555c0
JB		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
0206e353 2610 for (i = 0; i < 4; i++) {
357555c0
JB		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
88cefb6c 2636static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2637{
88cefb6c 2638 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2640 int pipe = intel_crtc->pipe;
5eddb70b 2641 u32 reg, temp;
79e53945 2642
c64e311e 2643
c98e9dcf 2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
627eb5a3
DV		 2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
c98e9dcf
JB		 2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
c98e9dcf
JB		 2660 udelay(200);
2661
20749730
PZ		 2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2667
20749730
PZ		 2668 POSTING_READ(reg);
2669 udelay(100);
6be4a607 2670 }
0e23b99d
JB		 2671}
2672
88cefb6c
DV		 2673static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674{
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700}
2701
0fc932b8
JB		 2702static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703{
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
dfd07d72 2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2728 }
0fc932b8
JB		 2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753}
2754
5bb61643
CW		 2755static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2760 unsigned long flags;
2761 bool pending;
2762
10d83730
VS		 2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772}
2773
e6c3a2a6
CW		 2774static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775{
0f91128d 2776 struct drm_device *dev = crtc->dev;
5bb61643 2777 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2c10d571
DV		 2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
5bb61643
CW		 2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
0f91128d
CW		 2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2790}
2791
e615efe4
ED		 2792/* Program iCLKIP clock to the desired frequency */
2793static void lpt_program_iclkip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
09153000
DV		 2800 mutex_lock(&dev_priv->dpio_lock);
2801
e615efe4
ED		 2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
e615efe4
ED		 2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
988d6ee8 2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2860
2861 /* Program SSCAUXDIV */
988d6ee8 2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2866
2867 /* Enable modulator and associated divider */
988d6ee8 2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2869 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2876
2877 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2878}
2879
275f01b2
DV		 2880static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882{
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902}
2903
f67a559d
JB		 2904/*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
ee7b9f93 2918 u32 reg, temp;
2c07245f 2919
ab9412ba 2920 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2921
cd986abb
DV		 2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
c98e9dcf 2927 /* For PCH output, training FDI link */
674cf967 2928 dev_priv->display.fdi_link_train(crtc);
2c07245f 2929
572deb37
DV		 2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
e72f9fbf
DV		 2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2938
303b81e0 2939 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2940 u32 sel;
4b645f14 2941
c98e9dcf 2942 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2946 temp |= sel;
2947 else
2948 temp &= ~sel;
c98e9dcf 2949 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2950 }
5eddb70b 2951
d9b6cb56
JB		 2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2955
303b81e0 2956 intel_fdi_normal_train(crtc);
5e84e1a4 2957
c98e9dcf
JB		 2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
9325c9f0 2970 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
5eddb70b 2979 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2980 break;
2981 case PCH_DP_C:
5eddb70b 2982 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2983 break;
2984 case PCH_DP_D:
5eddb70b 2985 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2986 break;
2987 default:
e95d41e1 2988 BUG();
32f9d658 2989 }
2c07245f 2990
5eddb70b 2991 I915_WRITE(reg, temp);
6be4a607 2992 }
b52eb4dc 2993
b8a4f404 2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 2995}
2996
1507e5bd
PZ		 2997static void lpt_pch_enable(struct drm_crtc *crtc)
2998{
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3003
ab9412ba 3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3005
8c52b5e8 3006 lpt_program_iclkip(crtc);
1507e5bd 3007
0540e488 3008 /* Set transcoder timing. */
275f01b2 3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3010
937bb610 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3012}
3013
e2b78267 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3015{
e2b78267 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
46edb027 3022 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3023 return;
3024 }
3025
f4a091c7
DV		 3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
a43f6e0f 3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3032}
3033
b89a1d39 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3035{
e2b78267
DV		 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
ee7b9f93 3039
ee7b9f93 3040 if (pll) {
46edb027
DV		 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
e2b78267 3043 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3044 }
3045
98b6bd99
DV		 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3048 i = crtc->pipe;
e72f9fbf 3049 pll = &dev_priv->shared_dplls[i];
98b6bd99 3050
46edb027
DV		 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
98b6bd99
DV		 3053
3054 goto found;
3055 }
3056
e72f9fbf
DV		 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
b89a1d39
DV		 3064 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3065 sizeof(pll->hw_state)) == 0) {
46edb027 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3067 crtc->base.base.id,
46edb027 3068 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3077 if (pll->refcount == 0) {
46edb027
DV		 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086found:
a43f6e0f 3087 crtc->config.shared_dpll = i;
46edb027
DV		 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
ee7b9f93 3090
cdbd2316 3091 if (pll->active == 0) {
66e985c0
DV		 3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3094
46edb027 3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3096 WARN_ON(pll->on);
e9d6944e 3097 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3098
15bdd4cf 3099 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3100 }
3101 pll->refcount++;
e04c7350 3102
ee7b9f93
JB		 3103 return pll;
3104}
3105
a1520318 3106static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3107{
3108 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3109 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3110 u32 temp;
3111
3112 temp = I915_READ(dslreg);
3113 udelay(500);
3114 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3115 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3116 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3117 }
3118}
3119
b074cec8
JB		 3120static void ironlake_pfit_enable(struct intel_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->base.dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 int pipe = crtc->pipe;
3125
0ef37f3f 3126 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3127 /* Force use of hard-coded filter coefficients
3128 * as some pre-programmed values are broken,
3129 * e.g. x201.
3130 */
3131 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3132 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3133 PF_PIPE_SEL_IVB(pipe));
3134 else
3135 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3136 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3137 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3138 }
3139}
3140
bb53d4ae
VS		 3141static void intel_enable_planes(struct drm_crtc *crtc)
3142{
3143 struct drm_device *dev = crtc->dev;
3144 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3145 struct intel_plane *intel_plane;
3146
3147 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3148 if (intel_plane->pipe == pipe)
3149 intel_plane_restore(&intel_plane->base);
3150}
3151
3152static void intel_disable_planes(struct drm_crtc *crtc)
3153{
3154 struct drm_device *dev = crtc->dev;
3155 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3156 struct intel_plane *intel_plane;
3157
3158 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3159 if (intel_plane->pipe == pipe)
3160 intel_plane_disable(&intel_plane->base);
3161}
3162
f67a559d
JB		 3163static void ironlake_crtc_enable(struct drm_crtc *crtc)
3164{
3165 struct drm_device *dev = crtc->dev;
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3168 struct intel_encoder *encoder;
f67a559d
JB		 3169 int pipe = intel_crtc->pipe;
3170 int plane = intel_crtc->plane;
f67a559d 3171
08a48469
DV		 3172 WARN_ON(!crtc->enabled);
3173
f67a559d
JB		 3174 if (intel_crtc->active)
3175 return;
3176
3177 intel_crtc->active = true;
8664281b
PZ		 3178
3179 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3180 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3181
f67a559d
JB		 3182 intel_update_watermarks(dev);
3183
15bdd4cf
DV		 3184 for_each_encoder_on_crtc(dev, crtc, encoder)
3185 if (encoder->pre_pll_enable)
3186 encoder->pre_pll_enable(encoder);
f67a559d 3187
5bfe2ac0 3188 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3189 /* Note: FDI PLL enabling _must_ be done before we enable the
3190 * cpu pipes, hence this is separate from all the other fdi/pch
3191 * enabling. */
88cefb6c 3192 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3193 } else {
3194 assert_fdi_tx_disabled(dev_priv, pipe);
3195 assert_fdi_rx_disabled(dev_priv, pipe);
3196 }
f67a559d 3197
bf49ec8c
DV		 3198 for_each_encoder_on_crtc(dev, crtc, encoder)
3199 if (encoder->pre_enable)
3200 encoder->pre_enable(encoder);
f67a559d 3201
b074cec8 3202 ironlake_pfit_enable(intel_crtc);
f67a559d 3203
9c54c0dd
JB		 3204 /*
3205 * On ILK+ LUT must be loaded before the pipe is running but with
3206 * clocks enabled
3207 */
3208 intel_crtc_load_lut(crtc);
3209
5bfe2ac0
DV		 3210 intel_enable_pipe(dev_priv, pipe,
3211 intel_crtc->config.has_pch_encoder);
f67a559d 3212 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3213 intel_enable_planes(crtc);
5c38d48c 3214 intel_crtc_update_cursor(crtc, true);
f67a559d 3215
5bfe2ac0 3216 if (intel_crtc->config.has_pch_encoder)
f67a559d 3217 ironlake_pch_enable(crtc);
c98e9dcf 3218
d1ebd816 3219 mutex_lock(&dev->struct_mutex);
bed4a673 3220 intel_update_fbc(dev);
d1ebd816
BW		 3221 mutex_unlock(&dev->struct_mutex);
3222
fa5c73b1
DV		 3223 for_each_encoder_on_crtc(dev, crtc, encoder)
3224 encoder->enable(encoder);
61b77ddd
DV		 3225
3226 if (HAS_PCH_CPT(dev))
a1520318 3227 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3228
3229 /*
3230 * There seems to be a race in PCH platform hw (at least on some
3231 * outputs) where an enabled pipe still completes any pageflip right
3232 * away (as if the pipe is off) instead of waiting for vblank. As soon
3233 * as the first vblank happend, everything works as expected. Hence just
3234 * wait for one vblank before returning to avoid strange things
3235 * happening.
3236 */
3237 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3238}
3239
42db64ef
PZ		 3240/* IPS only exists on ULT machines and is tied to pipe A. */
3241static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3242{
f5adf94e 3243 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3244}
3245
3246static void hsw_enable_ips(struct intel_crtc *crtc)
3247{
3248 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3249
3250 if (!crtc->config.ips_enabled)
3251 return;
3252
3253 /* We can only enable IPS after we enable a plane and wait for a vblank.
3254 * We guarantee that the plane is enabled by calling intel_enable_ips
3255 * only after intel_enable_plane. And intel_enable_plane already waits
3256 * for a vblank, so all we need to do here is to enable the IPS bit. */
3257 assert_plane_enabled(dev_priv, crtc->plane);
3258 I915_WRITE(IPS_CTL, IPS_ENABLE);
3259}
3260
3261static void hsw_disable_ips(struct intel_crtc *crtc)
3262{
3263 struct drm_device *dev = crtc->base.dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265
3266 if (!crtc->config.ips_enabled)
3267 return;
3268
3269 assert_plane_enabled(dev_priv, crtc->plane);
3270 I915_WRITE(IPS_CTL, 0);
3271
3272 /* We need to wait for a vblank before we can disable the plane. */
3273 intel_wait_for_vblank(dev, crtc->pipe);
3274}
3275
4f771f10
PZ		 3276static void haswell_crtc_enable(struct drm_crtc *crtc)
3277{
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281 struct intel_encoder *encoder;
3282 int pipe = intel_crtc->pipe;
3283 int plane = intel_crtc->plane;
4f771f10
PZ		 3284
3285 WARN_ON(!crtc->enabled);
3286
3287 if (intel_crtc->active)
3288 return;
3289
3290 intel_crtc->active = true;
8664281b
PZ		 3291
3292 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3293 if (intel_crtc->config.has_pch_encoder)
3294 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3295
4f771f10
PZ		 3296 intel_update_watermarks(dev);
3297
5bfe2ac0 3298 if (intel_crtc->config.has_pch_encoder)
04945641 3299 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3300
3301 for_each_encoder_on_crtc(dev, crtc, encoder)
3302 if (encoder->pre_enable)
3303 encoder->pre_enable(encoder);
3304
1f544388 3305 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3306
b074cec8 3307 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3308
3309 /*
3310 * On ILK+ LUT must be loaded before the pipe is running but with
3311 * clocks enabled
3312 */
3313 intel_crtc_load_lut(crtc);
3314
1f544388 3315 intel_ddi_set_pipe_settings(crtc);
8228c251 3316 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3317
5bfe2ac0
DV		 3318 intel_enable_pipe(dev_priv, pipe,
3319 intel_crtc->config.has_pch_encoder);
4f771f10 3320 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3321 intel_enable_planes(crtc);
5c38d48c 3322 intel_crtc_update_cursor(crtc, true);
4f771f10 3323
42db64ef
PZ		 3324 hsw_enable_ips(intel_crtc);
3325
5bfe2ac0 3326 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3327 lpt_pch_enable(crtc);
4f771f10
PZ		 3328
3329 mutex_lock(&dev->struct_mutex);
3330 intel_update_fbc(dev);
3331 mutex_unlock(&dev->struct_mutex);
3332
4f771f10
PZ		 3333 for_each_encoder_on_crtc(dev, crtc, encoder)
3334 encoder->enable(encoder);
3335
4f771f10
PZ		 3336 /*
3337 * There seems to be a race in PCH platform hw (at least on some
3338 * outputs) where an enabled pipe still completes any pageflip right
3339 * away (as if the pipe is off) instead of waiting for vblank. As soon
3340 * as the first vblank happend, everything works as expected. Hence just
3341 * wait for one vblank before returning to avoid strange things
3342 * happening.
3343 */
3344 intel_wait_for_vblank(dev, intel_crtc->pipe);
3345}
3346
3f8dce3a
DV		 3347static void ironlake_pfit_disable(struct intel_crtc *crtc)
3348{
3349 struct drm_device *dev = crtc->base.dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 int pipe = crtc->pipe;
3352
3353 /* To avoid upsetting the power well on haswell only disable the pfit if
3354 * it's in use. The hw state code will make sure we get this right. */
3355 if (crtc->config.pch_pfit.size) {
3356 I915_WRITE(PF_CTL(pipe), 0);
3357 I915_WRITE(PF_WIN_POS(pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(pipe), 0);
3359 }
3360}
3361
6be4a607
JB		 3362static void ironlake_crtc_disable(struct drm_crtc *crtc)
3363{
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3367 struct intel_encoder *encoder;
6be4a607
JB		 3368 int pipe = intel_crtc->pipe;
3369 int plane = intel_crtc->plane;
5eddb70b 3370 u32 reg, temp;
b52eb4dc 3371
ef9c3aee 3372
f7abfe8b
CW		 3373 if (!intel_crtc->active)
3374 return;
3375
ea9d758d
DV		 3376 for_each_encoder_on_crtc(dev, crtc, encoder)
3377 encoder->disable(encoder);
3378
e6c3a2a6 3379 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3380 drm_vblank_off(dev, pipe);
913d8d11 3381
973d04f9
CW		 3382 if (dev_priv->cfb_plane == plane)
3383 intel_disable_fbc(dev);
2c07245f 3384
0d5b8c61 3385 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3386 intel_disable_planes(crtc);
0d5b8c61
VS		 3387 intel_disable_plane(dev_priv, plane, pipe);
3388
d925c59a
DV		 3389 if (intel_crtc->config.has_pch_encoder)
3390 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3391
b24e7179 3392 intel_disable_pipe(dev_priv, pipe);
32f9d658 3393
3f8dce3a 3394 ironlake_pfit_disable(intel_crtc);
2c07245f 3395
bf49ec8c
DV		 3396 for_each_encoder_on_crtc(dev, crtc, encoder)
3397 if (encoder->post_disable)
3398 encoder->post_disable(encoder);
2c07245f 3399
d925c59a
DV		 3400 if (intel_crtc->config.has_pch_encoder) {
3401 ironlake_fdi_disable(crtc);
913d8d11 3402
d925c59a
DV		 3403 ironlake_disable_pch_transcoder(dev_priv, pipe);
3404 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3405
d925c59a
DV		 3406 if (HAS_PCH_CPT(dev)) {
3407 /* disable TRANS_DP_CTL */
3408 reg = TRANS_DP_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3411 TRANS_DP_PORT_SEL_MASK);
3412 temp |= TRANS_DP_PORT_SEL_NONE;
3413 I915_WRITE(reg, temp);
3414
3415 /* disable DPLL_SEL */
3416 temp = I915_READ(PCH_DPLL_SEL);
11887397 3417 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3418 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3419 }
e3421a18 3420
d925c59a 3421 /* disable PCH DPLL */
e72f9fbf 3422 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3423
d925c59a
DV		 3424 ironlake_fdi_pll_disable(intel_crtc);
3425 }
6b383a7f 3426
f7abfe8b 3427 intel_crtc->active = false;
6b383a7f 3428 intel_update_watermarks(dev);
d1ebd816
BW		 3429
3430 mutex_lock(&dev->struct_mutex);
6b383a7f 3431 intel_update_fbc(dev);
d1ebd816 3432 mutex_unlock(&dev->struct_mutex);
6be4a607 3433}
1b3c7a47 3434
4f771f10 3435static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3436{
4f771f10
PZ		 3437 struct drm_device *dev = crtc->dev;
3438 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3440 struct intel_encoder *encoder;
3441 int pipe = intel_crtc->pipe;
3442 int plane = intel_crtc->plane;
3b117c8f 3443 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3444
4f771f10
PZ		 3445 if (!intel_crtc->active)
3446 return;
3447
3448 for_each_encoder_on_crtc(dev, crtc, encoder)
3449 encoder->disable(encoder);
3450
3451 intel_crtc_wait_for_pending_flips(crtc);
3452 drm_vblank_off(dev, pipe);
4f771f10 3453
891348b2 3454 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3455 if (dev_priv->cfb_plane == plane)
3456 intel_disable_fbc(dev);
3457
42db64ef
PZ		 3458 hsw_disable_ips(intel_crtc);
3459
0d5b8c61 3460 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3461 intel_disable_planes(crtc);
891348b2
RV		 3462 intel_disable_plane(dev_priv, plane, pipe);
3463
8664281b
PZ		 3464 if (intel_crtc->config.has_pch_encoder)
3465 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3466 intel_disable_pipe(dev_priv, pipe);
3467
ad80a810 3468 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3469
3f8dce3a 3470 ironlake_pfit_disable(intel_crtc);
4f771f10 3471
1f544388 3472 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3473
3474 for_each_encoder_on_crtc(dev, crtc, encoder)
3475 if (encoder->post_disable)
3476 encoder->post_disable(encoder);
3477
88adfff1 3478 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3479 lpt_disable_pch_transcoder(dev_priv);
8664281b 3480 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3481 intel_ddi_fdi_disable(crtc);
83616634 3482 }
4f771f10
PZ		 3483
3484 intel_crtc->active = false;
3485 intel_update_watermarks(dev);
3486
3487 mutex_lock(&dev->struct_mutex);
3488 intel_update_fbc(dev);
3489 mutex_unlock(&dev->struct_mutex);
3490}
3491
ee7b9f93
JB		 3492static void ironlake_crtc_off(struct drm_crtc *crtc)
3493{
3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3495 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3496}
3497
6441ab5f
PZ		 3498static void haswell_crtc_off(struct drm_crtc *crtc)
3499{
3500 intel_ddi_put_crtc_pll(crtc);
3501}
3502
02e792fb
DV		 3503static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3504{
02e792fb 3505 if (!enable && intel_crtc->overlay) {
23f09ce3 3506 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3507 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3508
23f09ce3 3509 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3510 dev_priv->mm.interruptible = false;
3511 (void) intel_overlay_switch_off(intel_crtc->overlay);
3512 dev_priv->mm.interruptible = true;
23f09ce3 3513 mutex_unlock(&dev->struct_mutex);
02e792fb 3514 }
02e792fb 3515
5dcdbcb0
CW		 3516 /* Let userspace switch the overlay on again. In most cases userspace
3517 * has to recompute where to put it anyway.
3518 */
02e792fb
DV		 3519}
3520
61bc95c1
EE		 3521/**
3522 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3523 * cursor plane briefly if not already running after enabling the display
3524 * plane.
3525 * This workaround avoids occasional blank screens when self refresh is
3526 * enabled.
3527 */
3528static void
3529g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3530{
3531 u32 cntl = I915_READ(CURCNTR(pipe));
3532
3533 if ((cntl & CURSOR_MODE) == 0) {
3534 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3535
3536 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3537 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3538 intel_wait_for_vblank(dev_priv->dev, pipe);
3539 I915_WRITE(CURCNTR(pipe), cntl);
3540 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3541 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3542 }
3543}
3544
2dd24552
JB		 3545static void i9xx_pfit_enable(struct intel_crtc *crtc)
3546{
3547 struct drm_device *dev = crtc->base.dev;
3548 struct drm_i915_private *dev_priv = dev->dev_private;
3549 struct intel_crtc_config *pipe_config = &crtc->config;
3550
328d8e82 3551 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3552 return;
3553
2dd24552 3554 /*
c0b03411
DV		 3555 * The panel fitter should only be adjusted whilst the pipe is disabled,
3556 * according to register description and PRM.
2dd24552 3557 */
c0b03411
DV		 3558 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3559 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3560
b074cec8
JB		 3561 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3562 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3563
3564 /* Border color in case we don't scale up to the full screen. Black by
3565 * default, change to something else for debugging. */
3566 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3567}
3568
89b667f8
JB		 3569static void valleyview_crtc_enable(struct drm_crtc *crtc)
3570{
3571 struct drm_device *dev = crtc->dev;
3572 struct drm_i915_private *dev_priv = dev->dev_private;
3573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574 struct intel_encoder *encoder;
3575 int pipe = intel_crtc->pipe;
3576 int plane = intel_crtc->plane;
3577
3578 WARN_ON(!crtc->enabled);
3579
3580 if (intel_crtc->active)
3581 return;
3582
3583 intel_crtc->active = true;
3584 intel_update_watermarks(dev);
3585
3586 mutex_lock(&dev_priv->dpio_lock);
3587
3588 for_each_encoder_on_crtc(dev, crtc, encoder)
3589 if (encoder->pre_pll_enable)
3590 encoder->pre_pll_enable(encoder);
3591
3592 intel_enable_pll(dev_priv, pipe);
3593
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->pre_enable)
3596 encoder->pre_enable(encoder);
3597
3598 /* VLV wants encoder enabling _before_ the pipe is up. */
3599 for_each_encoder_on_crtc(dev, crtc, encoder)
3600 encoder->enable(encoder);
3601
2dd24552
JB		 3602 i9xx_pfit_enable(intel_crtc);
3603
63cbb074
VS		 3604 intel_crtc_load_lut(crtc);
3605
89b667f8
JB		 3606 intel_enable_pipe(dev_priv, pipe, false);
3607 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3608 intel_enable_planes(crtc);
5c38d48c 3609 intel_crtc_update_cursor(crtc, true);
89b667f8 3610
89b667f8
JB		 3611 intel_update_fbc(dev);
3612
89b667f8
JB		 3613 mutex_unlock(&dev_priv->dpio_lock);
3614}
3615
0b8765c6 3616static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3617{
3618 struct drm_device *dev = crtc->dev;
79e53945
JB		 3619 struct drm_i915_private *dev_priv = dev->dev_private;
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3621 struct intel_encoder *encoder;
79e53945 3622 int pipe = intel_crtc->pipe;
80824003 3623 int plane = intel_crtc->plane;
79e53945 3624
08a48469
DV		 3625 WARN_ON(!crtc->enabled);
3626
f7abfe8b
CW		 3627 if (intel_crtc->active)
3628 return;
3629
3630 intel_crtc->active = true;
6b383a7f
CW		 3631 intel_update_watermarks(dev);
3632
63d7bbe9 3633 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3634
3635 for_each_encoder_on_crtc(dev, crtc, encoder)
3636 if (encoder->pre_enable)
3637 encoder->pre_enable(encoder);
3638
2dd24552
JB		 3639 i9xx_pfit_enable(intel_crtc);
3640
63cbb074
VS		 3641 intel_crtc_load_lut(crtc);
3642
040484af 3643 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3644 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3645 intel_enable_planes(crtc);
22e407d7 3646 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3647 if (IS_G4X(dev))
3648 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3649 intel_crtc_update_cursor(crtc, true);
79e53945 3650
0b8765c6
JB		 3651 /* Give the overlay scaler a chance to enable if it's on this pipe */
3652 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3653
f440eb13 3654 intel_update_fbc(dev);
ef9c3aee 3655
fa5c73b1
DV		 3656 for_each_encoder_on_crtc(dev, crtc, encoder)
3657 encoder->enable(encoder);
0b8765c6 3658}
79e53945 3659
87476d63
DV		 3660static void i9xx_pfit_disable(struct intel_crtc *crtc)
3661{
3662 struct drm_device *dev = crtc->base.dev;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3664
328d8e82
DV		 3665 if (!crtc->config.gmch_pfit.control)
3666 return;
87476d63 3667
328d8e82 3668 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3669
328d8e82
DV		 3670 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3671 I915_READ(PFIT_CONTROL));
3672 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3673}
3674
0b8765c6
JB		 3675static void i9xx_crtc_disable(struct drm_crtc *crtc)
3676{
3677 struct drm_device *dev = crtc->dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3680 struct intel_encoder *encoder;
0b8765c6
JB		 3681 int pipe = intel_crtc->pipe;
3682 int plane = intel_crtc->plane;
ef9c3aee 3683
f7abfe8b
CW		 3684 if (!intel_crtc->active)
3685 return;
3686
ea9d758d
DV		 3687 for_each_encoder_on_crtc(dev, crtc, encoder)
3688 encoder->disable(encoder);
3689
0b8765c6 3690 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3691 intel_crtc_wait_for_pending_flips(crtc);
3692 drm_vblank_off(dev, pipe);
0b8765c6 3693
973d04f9
CW		 3694 if (dev_priv->cfb_plane == plane)
3695 intel_disable_fbc(dev);
79e53945 3696
0d5b8c61
VS		 3697 intel_crtc_dpms_overlay(intel_crtc, false);
3698 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3699 intel_disable_planes(crtc);
b24e7179 3700 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3701
b24e7179 3702 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3703
87476d63 3704 i9xx_pfit_disable(intel_crtc);
24a1f16d 3705
89b667f8
JB		 3706 for_each_encoder_on_crtc(dev, crtc, encoder)
3707 if (encoder->post_disable)
3708 encoder->post_disable(encoder);
3709
63d7bbe9 3710 intel_disable_pll(dev_priv, pipe);
0b8765c6 3711
f7abfe8b 3712 intel_crtc->active = false;
6b383a7f
CW		 3713 intel_update_fbc(dev);
3714 intel_update_watermarks(dev);
0b8765c6
JB		 3715}
3716
ee7b9f93
JB		 3717static void i9xx_crtc_off(struct drm_crtc *crtc)
3718{
3719}
3720
976f8a20
DV		 3721static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3722 bool enabled)
2c07245f
ZW		 3723{
3724 struct drm_device *dev = crtc->dev;
3725 struct drm_i915_master_private *master_priv;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727 int pipe = intel_crtc->pipe;
79e53945
JB		 3728
3729 if (!dev->primary->master)
3730 return;
3731
3732 master_priv = dev->primary->master->driver_priv;
3733 if (!master_priv->sarea_priv)
3734 return;
3735
79e53945
JB		 3736 switch (pipe) {
3737 case 0:
3738 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3739 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3740 break;
3741 case 1:
3742 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3743 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3744 break;
3745 default:
9db4a9c7 3746 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3747 break;
3748 }
79e53945
JB		 3749}
3750
976f8a20
DV		 3751/**
3752 * Sets the power management mode of the pipe and plane.
3753 */
3754void intel_crtc_update_dpms(struct drm_crtc *crtc)
3755{
3756 struct drm_device *dev = crtc->dev;
3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct intel_encoder *intel_encoder;
3759 bool enable = false;
3760
3761 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3762 enable |= intel_encoder->connectors_active;
3763
3764 if (enable)
3765 dev_priv->display.crtc_enable(crtc);
3766 else
3767 dev_priv->display.crtc_disable(crtc);
3768
3769 intel_crtc_update_sarea(crtc, enable);
3770}
3771
cdd59983
CW		 3772static void intel_crtc_disable(struct drm_crtc *crtc)
3773{
cdd59983 3774 struct drm_device *dev = crtc->dev;
976f8a20 3775 struct drm_connector *connector;
ee7b9f93 3776 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3778
976f8a20
DV		 3779 /* crtc should still be enabled when we disable it. */
3780 WARN_ON(!crtc->enabled);
3781
3782 dev_priv->display.crtc_disable(crtc);
c77bf565 3783 intel_crtc->eld_vld = false;
976f8a20 3784 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3785 dev_priv->display.off(crtc);
3786
931872fc
CW		 3787 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3788 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3789
3790 if (crtc->fb) {
3791 mutex_lock(&dev->struct_mutex);
1690e1eb 3792 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3793 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3794 crtc->fb = NULL;
3795 }
3796
3797 /* Update computed state. */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3799 if (!connector->encoder || !connector->encoder->crtc)
3800 continue;
3801
3802 if (connector->encoder->crtc != crtc)
3803 continue;
3804
3805 connector->dpms = DRM_MODE_DPMS_OFF;
3806 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3807 }
3808}
3809
a261b246 3810void intel_modeset_disable(struct drm_device *dev)
79e53945 3811{
a261b246
DV		 3812 struct drm_crtc *crtc;
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled)
3816 intel_crtc_disable(crtc);
3817 }
79e53945
JB		 3818}
3819
ea5b213a 3820void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3821{
4ef69c7a 3822 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3823
ea5b213a
CW		 3824 drm_encoder_cleanup(encoder);
3825 kfree(intel_encoder);
7e7d76c3
JB		 3826}
3827
5ab432ef
DV		 3828/* Simple dpms helper for encodres with just one connector, no cloning and only
3829 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3830 * state of the entire output pipe. */
3831void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3832{
5ab432ef
DV		 3833 if (mode == DRM_MODE_DPMS_ON) {
3834 encoder->connectors_active = true;
3835
b2cabb0e 3836 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3837 } else {
3838 encoder->connectors_active = false;
3839
b2cabb0e 3840 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3841 }
79e53945
JB		 3842}
3843
0a91ca29
DV		 3844/* Cross check the actual hw state with our own modeset state tracking (and it's
3845 * internal consistency). */
b980514c 3846static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3847{
0a91ca29
DV		 3848 if (connector->get_hw_state(connector)) {
3849 struct intel_encoder *encoder = connector->encoder;
3850 struct drm_crtc *crtc;
3851 bool encoder_enabled;
3852 enum pipe pipe;
3853
3854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3855 connector->base.base.id,
3856 drm_get_connector_name(&connector->base));
3857
3858 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3859 "wrong connector dpms state\n");
3860 WARN(connector->base.encoder != &encoder->base,
3861 "active connector not linked to encoder\n");
3862 WARN(!encoder->connectors_active,
3863 "encoder->connectors_active not set\n");
3864
3865 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3866 WARN(!encoder_enabled, "encoder not enabled\n");
3867 if (WARN_ON(!encoder->base.crtc))
3868 return;
3869
3870 crtc = encoder->base.crtc;
3871
3872 WARN(!crtc->enabled, "crtc not enabled\n");
3873 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3874 WARN(pipe != to_intel_crtc(crtc)->pipe,
3875 "encoder active on the wrong pipe\n");
3876 }
79e53945
JB		 3877}
3878
5ab432ef
DV		 3879/* Even simpler default implementation, if there's really no special case to
3880 * consider. */
3881void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3882{
5ab432ef 3883 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3884
5ab432ef
DV		 3885 /* All the simple cases only support two dpms states. */
3886 if (mode != DRM_MODE_DPMS_ON)
3887 mode = DRM_MODE_DPMS_OFF;
d4270e57 3888
5ab432ef
DV		 3889 if (mode == connector->dpms)
3890 return;
3891
3892 connector->dpms = mode;
3893
3894 /* Only need to change hw state when actually enabled */
3895 if (encoder->base.crtc)
3896 intel_encoder_dpms(encoder, mode);
3897 else
8af6cf88 3898 WARN_ON(encoder->connectors_active != false);
0a91ca29 3899
b980514c 3900 intel_modeset_check_state(connector->dev);
79e53945
JB		 3901}
3902
f0947c37
DV		 3903/* Simple connector->get_hw_state implementation for encoders that support only
3904 * one connector and no cloning and hence the encoder state determines the state
3905 * of the connector. */
3906bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3907{
24929352 3908 enum pipe pipe = 0;
f0947c37 3909 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3910
f0947c37 3911 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3912}
3913
1857e1da
DV		 3914static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3915 struct intel_crtc_config *pipe_config)
3916{
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918 struct intel_crtc *pipe_B_crtc =
3919 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3920
3921 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3922 pipe_name(pipe), pipe_config->fdi_lanes);
3923 if (pipe_config->fdi_lanes > 4) {
3924 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3925 pipe_name(pipe), pipe_config->fdi_lanes);
3926 return false;
3927 }
3928
3929 if (IS_HASWELL(dev)) {
3930 if (pipe_config->fdi_lanes > 2) {
3931 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3932 pipe_config->fdi_lanes);
3933 return false;
3934 } else {
3935 return true;
3936 }
3937 }
3938
3939 if (INTEL_INFO(dev)->num_pipes == 2)
3940 return true;
3941
3942 /* Ivybridge 3 pipe is really complicated */
3943 switch (pipe) {
3944 case PIPE_A:
3945 return true;
3946 case PIPE_B:
3947 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3948 pipe_config->fdi_lanes > 2) {
3949 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3950 pipe_name(pipe), pipe_config->fdi_lanes);
3951 return false;
3952 }
3953 return true;
3954 case PIPE_C:
1e833f40 3955 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3956 pipe_B_crtc->config.fdi_lanes <= 2) {
3957 if (pipe_config->fdi_lanes > 2) {
3958 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3959 pipe_name(pipe), pipe_config->fdi_lanes);
3960 return false;
3961 }
3962 } else {
3963 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3964 return false;
3965 }
3966 return true;
3967 default:
3968 BUG();
3969 }
3970}
3971
e29c22c0
DV		 3972#define RETRY 1
3973static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3974 struct intel_crtc_config *pipe_config)
877d48d5 3975{
1857e1da 3976 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3977 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3978 int lane, link_bw, fdi_dotclock;
e29c22c0 3979 bool setup_ok, needs_recompute = false;
877d48d5 3980
e29c22c0 3981retry:
877d48d5
DV		 3982 /* FDI is a binary signal running at ~2.7GHz, encoding
3983 * each output octet as 10 bits. The actual frequency
3984 * is stored as a divider into a 100MHz clock, and the
3985 * mode pixel clock is stored in units of 1KHz.
3986 * Hence the bw of each lane in terms of the mode signal
3987 * is:
3988 */
3989 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3990
ff9a6750 3991 fdi_dotclock = adjusted_mode->clock;
ef1b460d 3992 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 3993
2bd89a07 3994 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 3995 pipe_config->pipe_bpp);
3996
3997 pipe_config->fdi_lanes = lane;
3998
2bd89a07 3999 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4000 link_bw, &pipe_config->fdi_m_n);
1857e1da 4001
e29c22c0
DV		 4002 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4003 intel_crtc->pipe, pipe_config);
4004 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4005 pipe_config->pipe_bpp -= 2*3;
4006 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4007 pipe_config->pipe_bpp);
4008 needs_recompute = true;
4009 pipe_config->bw_constrained = true;
4010
4011 goto retry;
4012 }
4013
4014 if (needs_recompute)
4015 return RETRY;
4016
4017 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4018}
4019
42db64ef
PZ		 4020static void hsw_compute_ips_config(struct intel_crtc *crtc,
4021 struct intel_crtc_config *pipe_config)
4022{
3c4ca58c
PZ		 4023 pipe_config->ips_enabled = i915_enable_ips &&
4024 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4025 pipe_config->pipe_bpp == 24;
4026}
4027
a43f6e0f 4028static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4029 struct intel_crtc_config *pipe_config)
79e53945 4030{
a43f6e0f 4031 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4032 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4033
bad720ff 4034 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4035 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4036 if (pipe_config->requested_mode.clock * 3
4037 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4038 return -EINVAL;
2c07245f 4039 }
89749350 4040
f9bef081
DV		 4041 /* All interlaced capable intel hw wants timings in frames. Note though
4042 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4043 * timings, so we need to be careful not to clobber these.*/
7ae89233 4044 if (!pipe_config->timings_set)
f9bef081 4045 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4046
8693a824
DL		 4047 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4048 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4049 */
4050 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4051 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4052 return -EINVAL;
44f46b42 4053
bd080ee5 4054 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4055 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4056 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4057 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4058 * for lvds. */
4059 pipe_config->pipe_bpp = 8*3;
4060 }
4061
f5adf94e 4062 if (HAS_IPS(dev))
a43f6e0f
DV		 4063 hsw_compute_ips_config(crtc, pipe_config);
4064
4065 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4066 * clock survives for now. */
4067 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4068 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4069
877d48d5 4070 if (pipe_config->has_pch_encoder)
a43f6e0f 4071 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4072
e29c22c0 4073 return 0;
79e53945
JB		 4074}
4075
25eb05fc
JB		 4076static int valleyview_get_display_clock_speed(struct drm_device *dev)
4077{
4078 return 400000; /* FIXME */
4079}
4080
e70236a8
JB		 4081static int i945_get_display_clock_speed(struct drm_device *dev)
4082{
4083 return 400000;
4084}
79e53945 4085
e70236a8 4086static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4087{
e70236a8
JB		 4088 return 333000;
4089}
79e53945 4090
e70236a8
JB		 4091static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4092{
4093 return 200000;
4094}
79e53945 4095
e70236a8
JB		 4096static int i915gm_get_display_clock_speed(struct drm_device *dev)
4097{
4098 u16 gcfgc = 0;
79e53945 4099
e70236a8
JB		 4100 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4101
4102 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4103 return 133000;
4104 else {
4105 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4106 case GC_DISPLAY_CLOCK_333_MHZ:
4107 return 333000;
4108 default:
4109 case GC_DISPLAY_CLOCK_190_200_MHZ:
4110 return 190000;
79e53945 4111 }
e70236a8
JB		 4112 }
4113}
4114
4115static int i865_get_display_clock_speed(struct drm_device *dev)
4116{
4117 return 266000;
4118}
4119
4120static int i855_get_display_clock_speed(struct drm_device *dev)
4121{
4122 u16 hpllcc = 0;
4123 /* Assume that the hardware is in the high speed state. This
4124 * should be the default.
4125 */
4126 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4127 case GC_CLOCK_133_200:
4128 case GC_CLOCK_100_200:
4129 return 200000;
4130 case GC_CLOCK_166_250:
4131 return 250000;
4132 case GC_CLOCK_100_133:
79e53945 4133 return 133000;
e70236a8 4134 }
79e53945 4135
e70236a8
JB		 4136 /* Shouldn't happen */
4137 return 0;
4138}
79e53945 4139
e70236a8
JB		 4140static int i830_get_display_clock_speed(struct drm_device *dev)
4141{
4142 return 133000;
79e53945
JB		 4143}
4144
2c07245f 4145static void
a65851af 4146intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4147{
a65851af
VS		 4148 while (*num > DATA_LINK_M_N_MASK ||
4149 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4150 *num >>= 1;
4151 *den >>= 1;
4152 }
4153}
4154
a65851af
VS		 4155static void compute_m_n(unsigned int m, unsigned int n,
4156 uint32_t *ret_m, uint32_t *ret_n)
4157{
4158 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4159 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4160 intel_reduce_m_n_ratio(ret_m, ret_n);
4161}
4162
e69d0bc1
DV		 4163void
4164intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4165 int pixel_clock, int link_clock,
4166 struct intel_link_m_n *m_n)
2c07245f 4167{
e69d0bc1 4168 m_n->tu = 64;
a65851af
VS		 4169
4170 compute_m_n(bits_per_pixel * pixel_clock,
4171 link_clock * nlanes * 8,
4172 &m_n->gmch_m, &m_n->gmch_n);
4173
4174 compute_m_n(pixel_clock, link_clock,
4175 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4176}
4177
a7615030
CW		 4178static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4179{
72bbe58c
KP		 4180 if (i915_panel_use_ssc >= 0)
4181 return i915_panel_use_ssc != 0;
41aa3448 4182 return dev_priv->vbt.lvds_use_ssc
435793df 4183 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4184}
4185
a0c4da24
JB		 4186static int vlv_get_refclk(struct drm_crtc *crtc)
4187{
4188 struct drm_device *dev = crtc->dev;
4189 struct drm_i915_private *dev_priv = dev->dev_private;
4190 int refclk = 27000; /* for DP & HDMI */
4191
4192 return 100000; /* only one validated so far */
4193
4194 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4195 refclk = 96000;
4196 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4197 if (intel_panel_use_ssc(dev_priv))
4198 refclk = 100000;
4199 else
4200 refclk = 96000;
4201 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4202 refclk = 100000;
4203 }
4204
4205 return refclk;
4206}
4207
c65d77d8
JB		 4208static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4209{
4210 struct drm_device *dev = crtc->dev;
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212 int refclk;
4213
a0c4da24
JB		 4214 if (IS_VALLEYVIEW(dev)) {
4215 refclk = vlv_get_refclk(crtc);
4216 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4217 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4218 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4219 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4220 refclk / 1000);
4221 } else if (!IS_GEN2(dev)) {
4222 refclk = 96000;
4223 } else {
4224 refclk = 48000;
4225 }
4226
4227 return refclk;
4228}
4229
7429e9d4 4230static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4231{
7df00d7a 4232 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4233}
f47709a9 4234
7429e9d4
DV		 4235static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4236{
4237 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4238}
4239
f47709a9 4240static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4241 intel_clock_t *reduced_clock)
4242{
f47709a9 4243 struct drm_device *dev = crtc->base.dev;
a7516a05 4244 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4245 int pipe = crtc->pipe;
a7516a05
JB		 4246 u32 fp, fp2 = 0;
4247
4248 if (IS_PINEVIEW(dev)) {
7429e9d4 4249 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4250 if (reduced_clock)
7429e9d4 4251 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4252 } else {
7429e9d4 4253 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4254 if (reduced_clock)
7429e9d4 4255 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4256 }
4257
4258 I915_WRITE(FP0(pipe), fp);
4259
f47709a9
DV		 4260 crtc->lowfreq_avail = false;
4261 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4262 reduced_clock && i915_powersave) {
4263 I915_WRITE(FP1(pipe), fp2);
f47709a9 4264 crtc->lowfreq_avail = true;
a7516a05
JB		 4265 } else {
4266 I915_WRITE(FP1(pipe), fp);
4267 }
4268}
4269
89b667f8
JB		 4270static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4271{
4272 u32 reg_val;
4273
4274 /*
4275 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4276 * and set it to a reasonable value instead.
4277 */
ae99258f 4278 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4279 reg_val &= 0xffffff00;
4280 reg_val |= 0x00000030;
ae99258f 4281 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4282
ae99258f 4283 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4284 reg_val &= 0x8cffffff;
4285 reg_val = 0x8c000000;
ae99258f 4286 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4287
ae99258f 4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4289 reg_val &= 0xffffff00;
ae99258f 4290 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4291
ae99258f 4292 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4293 reg_val &= 0x00ffffff;
4294 reg_val |= 0xb0000000;
ae99258f 4295 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4296}
4297
b551842d
DV		 4298static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4299 struct intel_link_m_n *m_n)
4300{
4301 struct drm_device *dev = crtc->base.dev;
4302 struct drm_i915_private *dev_priv = dev->dev_private;
4303 int pipe = crtc->pipe;
4304
e3b95f1e
DV		 4305 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4306 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4307 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4308 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4309}
4310
4311static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4312 struct intel_link_m_n *m_n)
4313{
4314 struct drm_device *dev = crtc->base.dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 int pipe = crtc->pipe;
4317 enum transcoder transcoder = crtc->config.cpu_transcoder;
4318
4319 if (INTEL_INFO(dev)->gen >= 5) {
4320 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4321 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4322 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4323 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4324 } else {
e3b95f1e
DV		 4325 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4326 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4327 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4328 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4329 }
4330}
4331
03afc4a2
DV		 4332static void intel_dp_set_m_n(struct intel_crtc *crtc)
4333{
4334 if (crtc->config.has_pch_encoder)
4335 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4336 else
4337 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4338}
4339
f47709a9 4340static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4341{
f47709a9 4342 struct drm_device *dev = crtc->base.dev;
a0c4da24 4343 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4344 struct intel_encoder *encoder;
f47709a9 4345 int pipe = crtc->pipe;
89b667f8 4346 u32 dpll, mdiv;
a0c4da24 4347 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4348 bool is_hdmi;
198a037f 4349 u32 coreclk, reg_val, dpll_md;
a0c4da24 4350
09153000
DV		 4351 mutex_lock(&dev_priv->dpio_lock);
4352
89b667f8 4353 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4354
f47709a9
DV		 4355 bestn = crtc->config.dpll.n;
4356 bestm1 = crtc->config.dpll.m1;
4357 bestm2 = crtc->config.dpll.m2;
4358 bestp1 = crtc->config.dpll.p1;
4359 bestp2 = crtc->config.dpll.p2;
a0c4da24 4360
89b667f8
JB		 4361 /* See eDP HDMI DPIO driver vbios notes doc */
4362
4363 /* PLL B needs special handling */
4364 if (pipe)
4365 vlv_pllb_recal_opamp(dev_priv);
4366
4367 /* Set up Tx target for periodic Rcomp update */
ae99258f 4368 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4369
4370 /* Disable target IRef on PLL */
ae99258f 4371 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4372 reg_val &= 0x00ffffff;
ae99258f 4373 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4374
4375 /* Disable fast lock */
ae99258f 4376 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4377
4378 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4379 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4380 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4381 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4382 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4383
4384 /*
4385 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4386 * but we don't support that).
4387 * Note: don't use the DAC post divider as it seems unstable.
4388 */
4389 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4390 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4391
a0c4da24 4392 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4393 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4394
89b667f8 4395 /* Set HBR and RBR LPF coefficients */
ff9a6750 4396 if (crtc->config.port_clock == 162000 ||
99750bd4 4397 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4398 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4399 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4400 0x005f0021);
4401 else
4abb2c39 4402 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4403 0x00d0000f);
4404
4405 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4406 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4407 /* Use SSC source */
4408 if (!pipe)
ae99258f 4409 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4410 0x0df40000);
4411 else
ae99258f 4412 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4413 0x0df70000);
4414 } else { /* HDMI or VGA */
4415 /* Use bend source */
4416 if (!pipe)
ae99258f 4417 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4418 0x0df70000);
4419 else
ae99258f 4420 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4421 0x0df40000);
4422 }
a0c4da24 4423
ae99258f 4424 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4425 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4426 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4427 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4428 coreclk |= 0x01000000;
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4430
ae99258f 4431 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4432
89b667f8
JB		 4433 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4434 if (encoder->pre_pll_enable)
4435 encoder->pre_pll_enable(encoder);
a0c4da24 4436
89b667f8
JB		 4437 /* Enable DPIO clock input */
4438 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4439 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4440 if (pipe)
4441 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4442
4443 dpll |= DPLL_VCO_ENABLE;
4444 I915_WRITE(DPLL(pipe), dpll);
4445 POSTING_READ(DPLL(pipe));
2a8f64ca 4446 udelay(150);
a0c4da24 4447
a0c4da24
JB		 4448 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4449 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4450
ef1b460d
DV		 4451 dpll_md = (crtc->config.pixel_multiplier - 1)
4452 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4453 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4454 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4455
89b667f8
JB		 4456 if (crtc->config.has_dp_encoder)
4457 intel_dp_set_m_n(crtc);
09153000
DV		 4458
4459 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4460}
4461
f47709a9
DV		 4462static void i9xx_update_pll(struct intel_crtc *crtc,
4463 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4464 int num_connectors)
4465{
f47709a9 4466 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4467 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4468 struct intel_encoder *encoder;
f47709a9 4469 int pipe = crtc->pipe;
eb1cbe48
DV		 4470 u32 dpll;
4471 bool is_sdvo;
f47709a9 4472 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4473
f47709a9 4474 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4475
f47709a9
DV		 4476 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4477 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4478
4479 dpll = DPLL_VGA_MODE_DIS;
4480
f47709a9 4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4482 dpll |= DPLLB_MODE_LVDS;
4483 else
4484 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4485
ef1b460d 4486 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4487 dpll |= (crtc->config.pixel_multiplier - 1)
4488 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4489 }
198a037f
DV		 4490
4491 if (is_sdvo)
4492 dpll |= DPLL_DVO_HIGH_SPEED;
4493
f47709a9 4494 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4495 dpll |= DPLL_DVO_HIGH_SPEED;
4496
4497 /* compute bitmask from p1 value */
4498 if (IS_PINEVIEW(dev))
4499 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4500 else {
4501 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4502 if (IS_G4X(dev) && reduced_clock)
4503 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4504 }
4505 switch (clock->p2) {
4506 case 5:
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4508 break;
4509 case 7:
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4511 break;
4512 case 10:
4513 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4514 break;
4515 case 14:
4516 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4517 break;
4518 }
4519 if (INTEL_INFO(dev)->gen >= 4)
4520 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4521
09ede541 4522 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4523 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4524 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4525 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4526 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4527 else
4528 dpll |= PLL_REF_INPUT_DREFCLK;
4529
4530 dpll |= DPLL_VCO_ENABLE;
4531 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4532 POSTING_READ(DPLL(pipe));
4533 udelay(150);
4534
f47709a9 4535 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4536 if (encoder->pre_pll_enable)
4537 encoder->pre_pll_enable(encoder);
eb1cbe48 4538
f47709a9
DV		 4539 if (crtc->config.has_dp_encoder)
4540 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4541
4542 I915_WRITE(DPLL(pipe), dpll);
4543
4544 /* Wait for the clocks to stabilize. */
4545 POSTING_READ(DPLL(pipe));
4546 udelay(150);
4547
4548 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4549 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4550 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4551 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4552 } else {
4553 /* The pixel multiplier can only be updated once the
4554 * DPLL is enabled and the clocks are stable.
4555 *
4556 * So write it again.
4557 */
4558 I915_WRITE(DPLL(pipe), dpll);
4559 }
4560}
4561
f47709a9 4562static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4563 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4564 int num_connectors)
4565{
f47709a9 4566 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4567 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4568 struct intel_encoder *encoder;
f47709a9 4569 int pipe = crtc->pipe;
eb1cbe48 4570 u32 dpll;
f47709a9 4571 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4572
f47709a9 4573 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4574
eb1cbe48
DV		 4575 dpll = DPLL_VGA_MODE_DIS;
4576
f47709a9 4577 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4578 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4579 } else {
4580 if (clock->p1 == 2)
4581 dpll |= PLL_P1_DIVIDE_BY_TWO;
4582 else
4583 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4584 if (clock->p2 == 4)
4585 dpll |= PLL_P2_DIVIDE_BY_4;
4586 }
4587
f47709a9 4588 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4591 else
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4593
4594 dpll |= DPLL_VCO_ENABLE;
4595 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4596 POSTING_READ(DPLL(pipe));
4597 udelay(150);
4598
f47709a9 4599 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4600 if (encoder->pre_pll_enable)
4601 encoder->pre_pll_enable(encoder);
eb1cbe48 4602
5b5896e4
DV		 4603 I915_WRITE(DPLL(pipe), dpll);
4604
4605 /* Wait for the clocks to stabilize. */
4606 POSTING_READ(DPLL(pipe));
4607 udelay(150);
4608
eb1cbe48
DV		 4609 /* The pixel multiplier can only be updated once the
4610 * DPLL is enabled and the clocks are stable.
4611 *
4612 * So write it again.
4613 */
4614 I915_WRITE(DPLL(pipe), dpll);
4615}
4616
8a654f3b 4617static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4618{
4619 struct drm_device *dev = intel_crtc->base.dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4622 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4623 struct drm_display_mode *adjusted_mode =
4624 &intel_crtc->config.adjusted_mode;
4625 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4626 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4627
4628 /* We need to be careful not to changed the adjusted mode, for otherwise
4629 * the hw state checker will get angry at the mismatch. */
4630 crtc_vtotal = adjusted_mode->crtc_vtotal;
4631 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4632
4633 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4634 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4635 crtc_vtotal -= 1;
4636 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4637 vsyncshift = adjusted_mode->crtc_hsync_start
4638 - adjusted_mode->crtc_htotal / 2;
4639 } else {
4640 vsyncshift = 0;
4641 }
4642
4643 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4644 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4645
fe2b8f9d 4646 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4647 (adjusted_mode->crtc_hdisplay - 1) |
4648 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4649 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4650 (adjusted_mode->crtc_hblank_start - 1) |
4651 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4652 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4653 (adjusted_mode->crtc_hsync_start - 1) |
4654 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4655
fe2b8f9d 4656 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4657 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4658 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4659 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4660 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4661 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4662 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_vsync_start - 1) |
4664 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4665
b5e508d4
PZ		 4666 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4667 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4668 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4669 * bits. */
4670 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4671 (pipe == PIPE_B || pipe == PIPE_C))
4672 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4673
b0e77b9c
PZ		 4674 /* pipesrc controls the size that is scaled from, which should
4675 * always be the user's requested size.
4676 */
4677 I915_WRITE(PIPESRC(pipe),
4678 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4679}
4680
1bd1bd80
DV		 4681static void intel_get_pipe_timings(struct intel_crtc *crtc,
4682 struct intel_crtc_config *pipe_config)
4683{
4684 struct drm_device *dev = crtc->base.dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4687 uint32_t tmp;
4688
4689 tmp = I915_READ(HTOTAL(cpu_transcoder));
4690 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4691 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4692 tmp = I915_READ(HBLANK(cpu_transcoder));
4693 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4694 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4695 tmp = I915_READ(HSYNC(cpu_transcoder));
4696 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4697 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4698
4699 tmp = I915_READ(VTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(VBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(VSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4708
4709 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4710 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4711 pipe_config->adjusted_mode.crtc_vtotal += 1;
4712 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4713 }
4714
4715 tmp = I915_READ(PIPESRC(crtc->pipe));
4716 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4717 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4718}
4719
84b046f3
DV		 4720static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4721{
4722 struct drm_device *dev = intel_crtc->base.dev;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724 uint32_t pipeconf;
4725
9f11a9e4 4726 pipeconf = 0;
84b046f3
DV		 4727
4728 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4729 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4730 * core speed.
4731 *
4732 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4733 * pipe == 0 check?
4734 */
4735 if (intel_crtc->config.requested_mode.clock >
4736 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4737 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4738 }
4739
ff9ce46e
DV		 4740 /* only g4x and later have fancy bpc/dither controls */
4741 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4742 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4743 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4744 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4745 PIPECONF_DITHER_TYPE_SP;
84b046f3 4746
ff9ce46e
DV		 4747 switch (intel_crtc->config.pipe_bpp) {
4748 case 18:
4749 pipeconf |= PIPECONF_6BPC;
4750 break;
4751 case 24:
4752 pipeconf |= PIPECONF_8BPC;
4753 break;
4754 case 30:
4755 pipeconf |= PIPECONF_10BPC;
4756 break;
4757 default:
4758 /* Case prevented by intel_choose_pipe_bpp_dither. */
4759 BUG();
84b046f3
DV		 4760 }
4761 }
4762
4763 if (HAS_PIPE_CXSR(dev)) {
4764 if (intel_crtc->lowfreq_avail) {
4765 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4766 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4767 } else {
4768 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4769 }
4770 }
4771
84b046f3
DV		 4772 if (!IS_GEN2(dev) &&
4773 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4774 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4775 else
4776 pipeconf |= PIPECONF_PROGRESSIVE;
4777
9f11a9e4
DV		 4778 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4779 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4780
84b046f3
DV		 4781 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4782 POSTING_READ(PIPECONF(intel_crtc->pipe));
4783}
4784
f564048e 4785static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4786 int x, int y,
94352cf9 4787 struct drm_framebuffer *fb)
79e53945
JB		 4788{
4789 struct drm_device *dev = crtc->dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4792 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4793 int pipe = intel_crtc->pipe;
80824003 4794 int plane = intel_crtc->plane;
c751ce4f 4795 int refclk, num_connectors = 0;
652c393a 4796 intel_clock_t clock, reduced_clock;
84b046f3 4797 u32 dspcntr;
a16af721
DV		 4798 bool ok, has_reduced_clock = false;
4799 bool is_lvds = false;
5eddb70b 4800 struct intel_encoder *encoder;
d4906093 4801 const intel_limit_t *limit;
5c3b82e2 4802 int ret;
79e53945 4803
6c2b7c12 4804 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4805 switch (encoder->type) {
79e53945
JB		 4806 case INTEL_OUTPUT_LVDS:
4807 is_lvds = true;
4808 break;
79e53945 4809 }
43565a06 4810
c751ce4f 4811 num_connectors++;
79e53945
JB		 4812 }
4813
c65d77d8 4814 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4815
d4906093
ML		 4816 /*
4817 * Returns a set of divisors for the desired target clock with the given
4818 * refclk, or FALSE. The returned values represent the clock equation:
4819 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4820 */
1b894b59 4821 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4822 ok = dev_priv->display.find_dpll(limit, crtc,
4823 intel_crtc->config.port_clock,
ee9300bb
DV		 4824 refclk, NULL, &clock);
4825 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4826 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4827 return -EINVAL;
79e53945
JB		 4828 }
4829
cda4b7d3 4830 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4831 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4832
ddc9003c 4833 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4834 /*
4835 * Ensure we match the reduced clock's P to the target clock.
4836 * If the clocks don't match, we can't switch the display clock
4837 * by using the FP0/FP1. In such case we will disable the LVDS
4838 * downclock feature.
4839 */
ee9300bb
DV		 4840 has_reduced_clock =
4841 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4842 dev_priv->lvds_downclock,
ee9300bb 4843 refclk, &clock,
5eddb70b 4844 &reduced_clock);
7026d4ac 4845 }
f47709a9
DV		 4846 /* Compat-code for transition, will disappear. */
4847 if (!intel_crtc->config.clock_set) {
4848 intel_crtc->config.dpll.n = clock.n;
4849 intel_crtc->config.dpll.m1 = clock.m1;
4850 intel_crtc->config.dpll.m2 = clock.m2;
4851 intel_crtc->config.dpll.p1 = clock.p1;
4852 intel_crtc->config.dpll.p2 = clock.p2;
4853 }
7026d4ac 4854
eb1cbe48 4855 if (IS_GEN2(dev))
8a654f3b 4856 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4857 has_reduced_clock ? &reduced_clock : NULL,
4858 num_connectors);
a0c4da24 4859 else if (IS_VALLEYVIEW(dev))
f47709a9 4860 vlv_update_pll(intel_crtc);
79e53945 4861 else
f47709a9 4862 i9xx_update_pll(intel_crtc,
eb1cbe48 4863 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4864 num_connectors);
79e53945 4865
79e53945
JB		 4866 /* Set up the display plane register */
4867 dspcntr = DISPPLANE_GAMMA_ENABLE;
4868
da6ecc5d
JB		 4869 if (!IS_VALLEYVIEW(dev)) {
4870 if (pipe == 0)
4871 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4872 else
4873 dspcntr |= DISPPLANE_SEL_PIPE_B;
4874 }
79e53945 4875
8a654f3b 4876 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4877
4878 /* pipesrc and dspsize control the size that is scaled from,
4879 * which should always be the user's requested size.
79e53945 4880 */
929c77fb
EA		 4881 I915_WRITE(DSPSIZE(plane),
4882 ((mode->vdisplay - 1) << 16) |
4883 (mode->hdisplay - 1));
4884 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4885
84b046f3
DV		 4886 i9xx_set_pipeconf(intel_crtc);
4887
f564048e
EA		 4888 I915_WRITE(DSPCNTR(plane), dspcntr);
4889 POSTING_READ(DSPCNTR(plane));
4890
94352cf9 4891 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4892
4893 intel_update_watermarks(dev);
4894
f564048e
EA		 4895 return ret;
4896}
4897
2fa2fe9a
DV		 4898static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4899 struct intel_crtc_config *pipe_config)
4900{
4901 struct drm_device *dev = crtc->base.dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903 uint32_t tmp;
4904
4905 tmp = I915_READ(PFIT_CONTROL);
4906
4907 if (INTEL_INFO(dev)->gen < 4) {
4908 if (crtc->pipe != PIPE_B)
4909 return;
4910
4911 /* gen2/3 store dither state in pfit control, needs to match */
4912 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4913 } else {
4914 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4915 return;
4916 }
4917
4918 if (!(tmp & PFIT_ENABLE))
4919 return;
4920
4921 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4922 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4923 if (INTEL_INFO(dev)->gen < 5)
4924 pipe_config->gmch_pfit.lvds_border_bits =
4925 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4926}
4927
0e8ffe1b
DV		 4928static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4929 struct intel_crtc_config *pipe_config)
4930{
4931 struct drm_device *dev = crtc->base.dev;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 uint32_t tmp;
4934
eccb140b 4935 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4936 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4937
0e8ffe1b
DV		 4938 tmp = I915_READ(PIPECONF(crtc->pipe));
4939 if (!(tmp & PIPECONF_ENABLE))
4940 return false;
4941
1bd1bd80
DV		 4942 intel_get_pipe_timings(crtc, pipe_config);
4943
2fa2fe9a
DV		 4944 i9xx_get_pfit_config(crtc, pipe_config);
4945
6c49f241
DV		 4946 if (INTEL_INFO(dev)->gen >= 4) {
4947 tmp = I915_READ(DPLL_MD(crtc->pipe));
4948 pipe_config->pixel_multiplier =
4949 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4950 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4951 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4952 tmp = I915_READ(DPLL(crtc->pipe));
4953 pipe_config->pixel_multiplier =
4954 ((tmp & SDVO_MULTIPLIER_MASK)
4955 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4956 } else {
4957 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4958 * port and will be fixed up in the encoder->get_config
4959 * function. */
4960 pipe_config->pixel_multiplier = 1;
4961 }
4962
0e8ffe1b
DV		 4963 return true;
4964}
4965
dde86e2d 4966static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4967{
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4970 struct intel_encoder *encoder;
74cfd7ac 4971 u32 val, final;
13d83a67 4972 bool has_lvds = false;
199e5d79 4973 bool has_cpu_edp = false;
199e5d79 4974 bool has_panel = false;
99eb6a01
KP		 4975 bool has_ck505 = false;
4976 bool can_ssc = false;
13d83a67
JB		 4977
4978 /* We need to take the global config into account */
199e5d79
KP		 4979 list_for_each_entry(encoder, &mode_config->encoder_list,
4980 base.head) {
4981 switch (encoder->type) {
4982 case INTEL_OUTPUT_LVDS:
4983 has_panel = true;
4984 has_lvds = true;
4985 break;
4986 case INTEL_OUTPUT_EDP:
4987 has_panel = true;
2de6905f 4988 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4989 has_cpu_edp = true;
4990 break;
13d83a67
JB		 4991 }
4992 }
4993
99eb6a01 4994 if (HAS_PCH_IBX(dev)) {
41aa3448 4995 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 4996 can_ssc = has_ck505;
4997 } else {
4998 has_ck505 = false;
4999 can_ssc = true;
5000 }
5001
2de6905f
ID		 5002 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5003 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5004
5005 /* Ironlake: try to setup display ref clock before DPLL
5006 * enabling. This is only under driver's control after
5007 * PCH B stepping, previous chipset stepping should be
5008 * ignoring this setting.
5009 */
74cfd7ac
CW		 5010 val = I915_READ(PCH_DREF_CONTROL);
5011
5012 /* As we must carefully and slowly disable/enable each source in turn,
5013 * compute the final state we want first and check if we need to
5014 * make any changes at all.
5015 */
5016 final = val;
5017 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5018 if (has_ck505)
5019 final |= DREF_NONSPREAD_CK505_ENABLE;
5020 else
5021 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5022
5023 final &= ~DREF_SSC_SOURCE_MASK;
5024 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5025 final &= ~DREF_SSC1_ENABLE;
5026
5027 if (has_panel) {
5028 final |= DREF_SSC_SOURCE_ENABLE;
5029
5030 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5031 final |= DREF_SSC1_ENABLE;
5032
5033 if (has_cpu_edp) {
5034 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5035 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5036 else
5037 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5038 } else
5039 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5040 } else {
5041 final |= DREF_SSC_SOURCE_DISABLE;
5042 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5043 }
5044
5045 if (final == val)
5046 return;
5047
13d83a67 5048 /* Always enable nonspread source */
74cfd7ac 5049 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5050
99eb6a01 5051 if (has_ck505)
74cfd7ac 5052 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5053 else
74cfd7ac 5054 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5055
199e5d79 5056 if (has_panel) {
74cfd7ac
CW		 5057 val &= ~DREF_SSC_SOURCE_MASK;
5058 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5059
199e5d79 5060 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5061 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5062 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5063 val |= DREF_SSC1_ENABLE;
e77166b5 5064 } else
74cfd7ac 5065 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5066
5067 /* Get SSC going before enabling the outputs */
74cfd7ac 5068 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5069 POSTING_READ(PCH_DREF_CONTROL);
5070 udelay(200);
5071
74cfd7ac 5072 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5073
5074 /* Enable CPU source on CPU attached eDP */
199e5d79 5075 if (has_cpu_edp) {
99eb6a01 5076 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5077 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5078 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5079 }
13d83a67 5080 else
74cfd7ac 5081 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5082 } else
74cfd7ac 5083 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5084
74cfd7ac 5085 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5086 POSTING_READ(PCH_DREF_CONTROL);
5087 udelay(200);
5088 } else {
5089 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5090
74cfd7ac 5091 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5092
5093 /* Turn off CPU output */
74cfd7ac 5094 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5095
74cfd7ac 5096 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5097 POSTING_READ(PCH_DREF_CONTROL);
5098 udelay(200);
5099
5100 /* Turn off the SSC source */
74cfd7ac
CW		 5101 val &= ~DREF_SSC_SOURCE_MASK;
5102 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5103
5104 /* Turn off SSC1 */
74cfd7ac 5105 val &= ~DREF_SSC1_ENABLE;
199e5d79 5106
74cfd7ac 5107 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5108 POSTING_READ(PCH_DREF_CONTROL);
5109 udelay(200);
5110 }
74cfd7ac
CW		 5111
5112 BUG_ON(val != final);
13d83a67
JB		 5113}
5114
dde86e2d
PZ		 5115/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5116static void lpt_init_pch_refclk(struct drm_device *dev)
5117{
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct drm_mode_config *mode_config = &dev->mode_config;
5120 struct intel_encoder *encoder;
5121 bool has_vga = false;
5122 bool is_sdv = false;
5123 u32 tmp;
5124
5125 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5126 switch (encoder->type) {
5127 case INTEL_OUTPUT_ANALOG:
5128 has_vga = true;
5129 break;
5130 }
5131 }
5132
5133 if (!has_vga)
5134 return;
5135
c00db246
DV		 5136 mutex_lock(&dev_priv->dpio_lock);
5137
dde86e2d
PZ		 5138 /* XXX: Rip out SDV support once Haswell ships for real. */
5139 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5140 is_sdv = true;
5141
5142 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5143 tmp &= ~SBI_SSCCTL_DISABLE;
5144 tmp |= SBI_SSCCTL_PATHALT;
5145 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5146
5147 udelay(24);
5148
5149 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5150 tmp &= ~SBI_SSCCTL_PATHALT;
5151 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5152
5153 if (!is_sdv) {
5154 tmp = I915_READ(SOUTH_CHICKEN2);
5155 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5156 I915_WRITE(SOUTH_CHICKEN2, tmp);
5157
5158 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5159 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5160 DRM_ERROR("FDI mPHY reset assert timeout\n");
5161
5162 tmp = I915_READ(SOUTH_CHICKEN2);
5163 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5164 I915_WRITE(SOUTH_CHICKEN2, tmp);
5165
5166 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5167 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5168 100))
5169 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5170 }
5171
5172 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5173 tmp &= ~(0xFF << 24);
5174 tmp |= (0x12 << 24);
5175 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5176
dde86e2d
PZ		 5177 if (is_sdv) {
5178 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5179 tmp |= 0x7FFF;
5180 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5181 }
5182
5183 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5184 tmp |= (1 << 11);
5185 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5186
5187 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5188 tmp |= (1 << 11);
5189 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5190
5191 if (is_sdv) {
5192 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5193 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5194 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5195
5196 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5197 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5198 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5199
5200 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5201 tmp |= (0x3F << 8);
5202 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5203
5204 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5205 tmp |= (0x3F << 8);
5206 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5207 }
5208
5209 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5210 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5211 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5214 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216
5217 if (!is_sdv) {
5218 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5219 tmp &= ~(7 << 13);
5220 tmp |= (5 << 13);
5221 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5224 tmp &= ~(7 << 13);
5225 tmp |= (5 << 13);
5226 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5227 }
5228
5229 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5230 tmp &= ~0xFF;
5231 tmp |= 0x1C;
5232 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5235 tmp &= ~0xFF;
5236 tmp |= 0x1C;
5237 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5240 tmp &= ~(0xFF << 16);
5241 tmp |= (0x1C << 16);
5242 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5245 tmp &= ~(0xFF << 16);
5246 tmp |= (0x1C << 16);
5247 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5248
5249 if (!is_sdv) {
5250 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5251 tmp |= (1 << 27);
5252 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5255 tmp |= (1 << 27);
5256 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5259 tmp &= ~(0xF << 28);
5260 tmp |= (4 << 28);
5261 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5264 tmp &= ~(0xF << 28);
5265 tmp |= (4 << 28);
5266 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5267 }
5268
5269 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5270 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5271 tmp |= SBI_DBUFF0_ENABLE;
5272 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5273
5274 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5275}
5276
5277/*
5278 * Initialize reference clocks when the driver loads
5279 */
5280void intel_init_pch_refclk(struct drm_device *dev)
5281{
5282 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5283 ironlake_init_pch_refclk(dev);
5284 else if (HAS_PCH_LPT(dev))
5285 lpt_init_pch_refclk(dev);
5286}
5287
d9d444cb
JB		 5288static int ironlake_get_refclk(struct drm_crtc *crtc)
5289{
5290 struct drm_device *dev = crtc->dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292 struct intel_encoder *encoder;
d9d444cb
JB		 5293 int num_connectors = 0;
5294 bool is_lvds = false;
5295
6c2b7c12 5296 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5297 switch (encoder->type) {
5298 case INTEL_OUTPUT_LVDS:
5299 is_lvds = true;
5300 break;
d9d444cb
JB		 5301 }
5302 num_connectors++;
5303 }
5304
5305 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5306 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5307 dev_priv->vbt.lvds_ssc_freq);
5308 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5309 }
5310
5311 return 120000;
5312}
5313
6ff93609 5314static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5315{
c8203565 5316 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 int pipe = intel_crtc->pipe;
c8203565
PZ		 5319 uint32_t val;
5320
78114071 5321 val = 0;
c8203565 5322
965e0c48 5323 switch (intel_crtc->config.pipe_bpp) {
c8203565 5324 case 18:
dfd07d72 5325 val |= PIPECONF_6BPC;
c8203565
PZ		 5326 break;
5327 case 24:
dfd07d72 5328 val |= PIPECONF_8BPC;
c8203565
PZ		 5329 break;
5330 case 30:
dfd07d72 5331 val |= PIPECONF_10BPC;
c8203565
PZ		 5332 break;
5333 case 36:
dfd07d72 5334 val |= PIPECONF_12BPC;
c8203565
PZ		 5335 break;
5336 default:
cc769b62
PZ		 5337 /* Case prevented by intel_choose_pipe_bpp_dither. */
5338 BUG();
c8203565
PZ		 5339 }
5340
d8b32247 5341 if (intel_crtc->config.dither)
c8203565
PZ		 5342 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5343
6ff93609 5344 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5345 val |= PIPECONF_INTERLACED_ILK;
5346 else
5347 val |= PIPECONF_PROGRESSIVE;
5348
50f3b016 5349 if (intel_crtc->config.limited_color_range)
3685a8f3 5350 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5351
c8203565
PZ		 5352 I915_WRITE(PIPECONF(pipe), val);
5353 POSTING_READ(PIPECONF(pipe));
5354}
5355
86d3efce
VS		 5356/*
5357 * Set up the pipe CSC unit.
5358 *
5359 * Currently only full range RGB to limited range RGB conversion
5360 * is supported, but eventually this should handle various
5361 * RGB<->YCbCr scenarios as well.
5362 */
50f3b016 5363static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5364{
5365 struct drm_device *dev = crtc->dev;
5366 struct drm_i915_private *dev_priv = dev->dev_private;
5367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5368 int pipe = intel_crtc->pipe;
5369 uint16_t coeff = 0x7800; /* 1.0 */
5370
5371 /*
5372 * TODO: Check what kind of values actually come out of the pipe
5373 * with these coeff/postoff values and adjust to get the best
5374 * accuracy. Perhaps we even need to take the bpc value into
5375 * consideration.
5376 */
5377
50f3b016 5378 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5379 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5380
5381 /*
5382 * GY/GU and RY/RU should be the other way around according
5383 * to BSpec, but reality doesn't agree. Just set them up in
5384 * a way that results in the correct picture.
5385 */
5386 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5387 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5388
5389 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5390 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5391
5392 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5393 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5394
5395 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5396 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5397 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5398
5399 if (INTEL_INFO(dev)->gen > 6) {
5400 uint16_t postoff = 0;
5401
50f3b016 5402 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5403 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5404
5405 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5406 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5407 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5408
5409 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5410 } else {
5411 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5412
50f3b016 5413 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5414 mode |= CSC_BLACK_SCREEN_OFFSET;
5415
5416 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5417 }
5418}
5419
6ff93609 5420static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5421{
5422 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5424 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5425 uint32_t val;
5426
3eff4faa 5427 val = 0;
ee2b0b38 5428
d8b32247 5429 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5430 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5431
6ff93609 5432 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5433 val |= PIPECONF_INTERLACED_ILK;
5434 else
5435 val |= PIPECONF_PROGRESSIVE;
5436
702e7a56
PZ		 5437 I915_WRITE(PIPECONF(cpu_transcoder), val);
5438 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5439
5440 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5441 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5442}
5443
6591c6e4 5444static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5445 intel_clock_t *clock,
5446 bool *has_reduced_clock,
5447 intel_clock_t *reduced_clock)
5448{
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct intel_encoder *intel_encoder;
5452 int refclk;
d4906093 5453 const intel_limit_t *limit;
a16af721 5454 bool ret, is_lvds = false;
79e53945 5455
6591c6e4
PZ		 5456 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5457 switch (intel_encoder->type) {
79e53945
JB		 5458 case INTEL_OUTPUT_LVDS:
5459 is_lvds = true;
5460 break;
79e53945
JB		 5461 }
5462 }
5463
d9d444cb 5464 refclk = ironlake_get_refclk(crtc);
79e53945 5465
d4906093
ML		 5466 /*
5467 * Returns a set of divisors for the desired target clock with the given
5468 * refclk, or FALSE. The returned values represent the clock equation:
5469 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5470 */
1b894b59 5471 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5472 ret = dev_priv->display.find_dpll(limit, crtc,
5473 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5474 refclk, NULL, clock);
6591c6e4
PZ		 5475 if (!ret)
5476 return false;
cda4b7d3 5477
ddc9003c 5478 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5479 /*
5480 * Ensure we match the reduced clock's P to the target clock.
5481 * If the clocks don't match, we can't switch the display clock
5482 * by using the FP0/FP1. In such case we will disable the LVDS
5483 * downclock feature.
5484 */
ee9300bb
DV		 5485 *has_reduced_clock =
5486 dev_priv->display.find_dpll(limit, crtc,
5487 dev_priv->lvds_downclock,
5488 refclk, clock,
5489 reduced_clock);
652c393a 5490 }
61e9653f 5491
6591c6e4
PZ		 5492 return true;
5493}
5494
01a415fd
DV		 5495static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5496{
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 uint32_t temp;
5499
5500 temp = I915_READ(SOUTH_CHICKEN1);
5501 if (temp & FDI_BC_BIFURCATION_SELECT)
5502 return;
5503
5504 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5505 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5506
5507 temp |= FDI_BC_BIFURCATION_SELECT;
5508 DRM_DEBUG_KMS("enabling fdi C rx\n");
5509 I915_WRITE(SOUTH_CHICKEN1, temp);
5510 POSTING_READ(SOUTH_CHICKEN1);
5511}
5512
ebfd86fd 5513static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5514{
5515 struct drm_device *dev = intel_crtc->base.dev;
5516 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5517
5518 switch (intel_crtc->pipe) {
5519 case PIPE_A:
ebfd86fd 5520 break;
01a415fd 5521 case PIPE_B:
ebfd86fd 5522 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5523 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5524 else
5525 cpt_enable_fdi_bc_bifurcation(dev);
5526
ebfd86fd 5527 break;
01a415fd 5528 case PIPE_C:
01a415fd
DV		 5529 cpt_enable_fdi_bc_bifurcation(dev);
5530
ebfd86fd 5531 break;
01a415fd
DV		 5532 default:
5533 BUG();
5534 }
5535}
5536
d4b1931c
PZ		 5537int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5538{
5539 /*
5540 * Account for spread spectrum to avoid
5541 * oversubscribing the link. Max center spread
5542 * is 2.5%; use 5% for safety's sake.
5543 */
5544 u32 bps = target_clock * bpp * 21 / 20;
5545 return bps / (link_bw * 8) + 1;
5546}
5547
7429e9d4 5548static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5549{
7429e9d4 5550 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5551}
5552
de13a2e3 5553static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5554 u32 *fp,
9a7c7890 5555 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5556{
de13a2e3 5557 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5558 struct drm_device *dev = crtc->dev;
5559 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5560 struct intel_encoder *intel_encoder;
5561 uint32_t dpll;
6cc5f341 5562 int factor, num_connectors = 0;
09ede541 5563 bool is_lvds = false, is_sdvo = false;
79e53945 5564
de13a2e3
PZ		 5565 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5566 switch (intel_encoder->type) {
79e53945
JB		 5567 case INTEL_OUTPUT_LVDS:
5568 is_lvds = true;
5569 break;
5570 case INTEL_OUTPUT_SDVO:
7d57382e 5571 case INTEL_OUTPUT_HDMI:
79e53945 5572 is_sdvo = true;
79e53945 5573 break;
79e53945 5574 }
43565a06 5575
c751ce4f 5576 num_connectors++;
79e53945 5577 }
79e53945 5578
c1858123 5579 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5580 factor = 21;
5581 if (is_lvds) {
5582 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5583 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5584 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5585 factor = 25;
09ede541 5586 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5587 factor = 20;
c1858123 5588
7429e9d4 5589 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5590 *fp |= FP_CB_TUNE;
2c07245f 5591
9a7c7890
DV		 5592 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5593 *fp2 |= FP_CB_TUNE;
5594
5eddb70b 5595 dpll = 0;
2c07245f 5596
a07d6787
EA		 5597 if (is_lvds)
5598 dpll |= DPLLB_MODE_LVDS;
5599 else
5600 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5601
ef1b460d
DV		 5602 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5603 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5604
5605 if (is_sdvo)
5606 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5607 if (intel_crtc->config.has_dp_encoder)
a07d6787 5608 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5609
a07d6787 5610 /* compute bitmask from p1 value */
7429e9d4 5611 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5612 /* also FPA1 */
7429e9d4 5613 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5614
7429e9d4 5615 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5616 case 5:
5617 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5618 break;
5619 case 7:
5620 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5621 break;
5622 case 10:
5623 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5624 break;
5625 case 14:
5626 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5627 break;
79e53945
JB		 5628 }
5629
b4c09f3b 5630 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5631 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5632 else
5633 dpll |= PLL_REF_INPUT_DREFCLK;
5634
959e16d6 5635 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5636}
5637
5638static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5639 int x, int y,
5640 struct drm_framebuffer *fb)
5641{
5642 struct drm_device *dev = crtc->dev;
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5645 int pipe = intel_crtc->pipe;
5646 int plane = intel_crtc->plane;
5647 int num_connectors = 0;
5648 intel_clock_t clock, reduced_clock;
cbbab5bd 5649 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5650 bool ok, has_reduced_clock = false;
8b47047b 5651 bool is_lvds = false;
de13a2e3 5652 struct intel_encoder *encoder;
e2b78267 5653 struct intel_shared_dpll *pll;
de13a2e3 5654 int ret;
de13a2e3
PZ		 5655
5656 for_each_encoder_on_crtc(dev, crtc, encoder) {
5657 switch (encoder->type) {
5658 case INTEL_OUTPUT_LVDS:
5659 is_lvds = true;
5660 break;
de13a2e3
PZ		 5661 }
5662
5663 num_connectors++;
a07d6787 5664 }
79e53945 5665
5dc5298b
PZ		 5666 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5667 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5668
ff9a6750 5669 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5670 &has_reduced_clock, &reduced_clock);
ee9300bb 5671 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5672 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5673 return -EINVAL;
79e53945 5674 }
f47709a9
DV		 5675 /* Compat-code for transition, will disappear. */
5676 if (!intel_crtc->config.clock_set) {
5677 intel_crtc->config.dpll.n = clock.n;
5678 intel_crtc->config.dpll.m1 = clock.m1;
5679 intel_crtc->config.dpll.m2 = clock.m2;
5680 intel_crtc->config.dpll.p1 = clock.p1;
5681 intel_crtc->config.dpll.p2 = clock.p2;
5682 }
79e53945 5683
de13a2e3
PZ		 5684 /* Ensure that the cursor is valid for the new mode before changing... */
5685 intel_crtc_update_cursor(crtc, true);
5686
5dc5298b 5687 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5688 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5689 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5690 if (has_reduced_clock)
7429e9d4 5691 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5692
7429e9d4 5693 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5694 &fp, &reduced_clock,
5695 has_reduced_clock ? &fp2 : NULL);
5696
959e16d6 5697 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5698 intel_crtc->config.dpll_hw_state.fp0 = fp;
5699 if (has_reduced_clock)
5700 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5701 else
5702 intel_crtc->config.dpll_hw_state.fp1 = fp;
5703
b89a1d39 5704 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5705 if (pll == NULL) {
84f44ce7
VS		 5706 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5707 pipe_name(pipe));
4b645f14
JB		 5708 return -EINVAL;
5709 }
ee7b9f93 5710 } else
e72f9fbf 5711 intel_put_shared_dpll(intel_crtc);
79e53945 5712
03afc4a2
DV		 5713 if (intel_crtc->config.has_dp_encoder)
5714 intel_dp_set_m_n(intel_crtc);
79e53945 5715
bcd644e0
DV		 5716 if (is_lvds && has_reduced_clock && i915_powersave)
5717 intel_crtc->lowfreq_avail = true;
5718 else
5719 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5720
5721 if (intel_crtc->config.has_pch_encoder) {
5722 pll = intel_crtc_to_shared_dpll(intel_crtc);
5723
652c393a
JB		 5724 }
5725
8a654f3b 5726 intel_set_pipe_timings(intel_crtc);
5eddb70b 5727
ca3a0ff8 5728 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5729 intel_cpu_transcoder_set_m_n(intel_crtc,
5730 &intel_crtc->config.fdi_m_n);
5731 }
2c07245f 5732
ebfd86fd
DV		 5733 if (IS_IVYBRIDGE(dev))
5734 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5735
6ff93609 5736 ironlake_set_pipeconf(crtc);
79e53945 5737
a1f9e77e
PZ		 5738 /* Set up the display plane register */
5739 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5740 POSTING_READ(DSPCNTR(plane));
79e53945 5741
94352cf9 5742 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5743
5744 intel_update_watermarks(dev);
5745
1857e1da 5746 return ret;
79e53945
JB		 5747}
5748
72419203
DV		 5749static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5750 struct intel_crtc_config *pipe_config)
5751{
5752 struct drm_device *dev = crtc->base.dev;
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 enum transcoder transcoder = pipe_config->cpu_transcoder;
5755
5756 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5757 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5758 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5759 & ~TU_SIZE_MASK;
5760 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5761 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5762 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5763}
5764
2fa2fe9a
DV		 5765static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5766 struct intel_crtc_config *pipe_config)
5767{
5768 struct drm_device *dev = crtc->base.dev;
5769 struct drm_i915_private *dev_priv = dev->dev_private;
5770 uint32_t tmp;
5771
5772 tmp = I915_READ(PF_CTL(crtc->pipe));
5773
5774 if (tmp & PF_ENABLE) {
5775 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5776 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5777
5778 /* We currently do not free assignements of panel fitters on
5779 * ivb/hsw (since we don't use the higher upscaling modes which
5780 * differentiates them) so just WARN about this case for now. */
5781 if (IS_GEN7(dev)) {
5782 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5783 PF_PIPE_SEL_IVB(crtc->pipe));
5784 }
2fa2fe9a 5785 }
79e53945
JB		 5786}
5787
0e8ffe1b
DV		 5788static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5789 struct intel_crtc_config *pipe_config)
5790{
5791 struct drm_device *dev = crtc->base.dev;
5792 struct drm_i915_private *dev_priv = dev->dev_private;
5793 uint32_t tmp;
5794
eccb140b 5795 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5796 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5797
0e8ffe1b
DV		 5798 tmp = I915_READ(PIPECONF(crtc->pipe));
5799 if (!(tmp & PIPECONF_ENABLE))
5800 return false;
5801
ab9412ba 5802 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5803 struct intel_shared_dpll *pll;
5804
88adfff1
DV		 5805 pipe_config->has_pch_encoder = true;
5806
627eb5a3
DV		 5807 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5808 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5809 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5810
5811 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5812
5813 /* XXX: Can't properly read out the pch dpll pixel multiplier
5814 * since we don't have state tracking for pch clocks yet. */
5815 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5816
5817 if (HAS_PCH_IBX(dev_priv->dev)) {
5818 pipe_config->shared_dpll = crtc->pipe;
5819 } else {
5820 tmp = I915_READ(PCH_DPLL_SEL);
5821 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5822 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5823 else
5824 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5825 }
66e985c0
DV		 5826
5827 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5828
5829 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5830 &pipe_config->dpll_hw_state));
6c49f241
DV		 5831 } else {
5832 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5833 }
5834
1bd1bd80
DV		 5835 intel_get_pipe_timings(crtc, pipe_config);
5836
2fa2fe9a
DV		 5837 ironlake_get_pfit_config(crtc, pipe_config);
5838
0e8ffe1b
DV		 5839 return true;
5840}
5841
d6dd9eb1
DV		 5842static void haswell_modeset_global_resources(struct drm_device *dev)
5843{
d6dd9eb1
DV		 5844 bool enable = false;
5845 struct intel_crtc *crtc;
d6dd9eb1
DV		 5846
5847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5848 if (!crtc->base.enabled)
5849 continue;
d6dd9eb1 5850
e7a639c4
DV		 5851 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5852 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5853 enable = true;
5854 }
5855
d6dd9eb1
DV		 5856 intel_set_power_well(dev, enable);
5857}
5858
09b4ddf9 5859static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5860 int x, int y,
5861 struct drm_framebuffer *fb)
5862{
5863 struct drm_device *dev = crtc->dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5866 int plane = intel_crtc->plane;
09b4ddf9 5867 int ret;
09b4ddf9 5868
ff9a6750 5869 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5870 return -EINVAL;
5871
09b4ddf9
PZ		 5872 /* Ensure that the cursor is valid for the new mode before changing... */
5873 intel_crtc_update_cursor(crtc, true);
5874
03afc4a2
DV		 5875 if (intel_crtc->config.has_dp_encoder)
5876 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5877
5878 intel_crtc->lowfreq_avail = false;
09b4ddf9 5879
8a654f3b 5880 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5881
ca3a0ff8 5882 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5883 intel_cpu_transcoder_set_m_n(intel_crtc,
5884 &intel_crtc->config.fdi_m_n);
5885 }
09b4ddf9 5886
6ff93609 5887 haswell_set_pipeconf(crtc);
09b4ddf9 5888
50f3b016 5889 intel_set_pipe_csc(crtc);
86d3efce 5890
09b4ddf9 5891 /* Set up the display plane register */
86d3efce 5892 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5893 POSTING_READ(DSPCNTR(plane));
5894
5895 ret = intel_pipe_set_base(crtc, x, y, fb);
5896
5897 intel_update_watermarks(dev);
5898
1f803ee5 5899 return ret;
79e53945
JB		 5900}
5901
0e8ffe1b
DV		 5902static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5903 struct intel_crtc_config *pipe_config)
5904{
5905 struct drm_device *dev = crtc->base.dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5907 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5908 uint32_t tmp;
5909
eccb140b 5910 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5911 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5912
eccb140b
DV		 5913 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5914 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5915 enum pipe trans_edp_pipe;
5916 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5917 default:
5918 WARN(1, "unknown pipe linked to edp transcoder\n");
5919 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5920 case TRANS_DDI_EDP_INPUT_A_ON:
5921 trans_edp_pipe = PIPE_A;
5922 break;
5923 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5924 trans_edp_pipe = PIPE_B;
5925 break;
5926 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5927 trans_edp_pipe = PIPE_C;
5928 break;
5929 }
5930
5931 if (trans_edp_pipe == crtc->pipe)
5932 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5933 }
5934
b97186f0 5935 if (!intel_display_power_enabled(dev,
eccb140b 5936 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5937 return false;
5938
eccb140b 5939 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5940 if (!(tmp & PIPECONF_ENABLE))
5941 return false;
5942
88adfff1 5943 /*
f196e6be 5944 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5945 * DDI E. So just check whether this pipe is wired to DDI E and whether
5946 * the PCH transcoder is on.
5947 */
eccb140b 5948 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5949 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5950 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5951 pipe_config->has_pch_encoder = true;
5952
627eb5a3
DV		 5953 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5954 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5955 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5956
5957 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5958 }
5959
1bd1bd80
DV		 5960 intel_get_pipe_timings(crtc, pipe_config);
5961
2fa2fe9a
DV		 5962 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5963 if (intel_display_power_enabled(dev, pfit_domain))
5964 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5965
42db64ef
PZ		 5966 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5967 (I915_READ(IPS_CTL) & IPS_ENABLE);
5968
6c49f241
DV		 5969 pipe_config->pixel_multiplier = 1;
5970
0e8ffe1b
DV		 5971 return true;
5972}
5973
f564048e 5974static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5975 int x, int y,
94352cf9 5976 struct drm_framebuffer *fb)
f564048e
EA		 5977{
5978 struct drm_device *dev = crtc->dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5980 struct drm_encoder_helper_funcs *encoder_funcs;
5981 struct intel_encoder *encoder;
0b701d27 5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5983 struct drm_display_mode *adjusted_mode =
5984 &intel_crtc->config.adjusted_mode;
5985 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5986 int pipe = intel_crtc->pipe;
f564048e
EA		 5987 int ret;
5988
0b701d27 5989 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5990
b8cecdf5
DV		 5991 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5992
79e53945 5993 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5994
9256aa19
DV		 5995 if (ret != 0)
5996 return ret;
5997
5998 for_each_encoder_on_crtc(dev, crtc, encoder) {
5999 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6000 encoder->base.base.id,
6001 drm_get_encoder_name(&encoder->base),
6002 mode->base.id, mode->name);
6cc5f341
DV		 6003 if (encoder->mode_set) {
6004 encoder->mode_set(encoder);
6005 } else {
6006 encoder_funcs = encoder->base.helper_private;
6007 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6008 }
9256aa19
DV		 6009 }
6010
6011 return 0;
79e53945
JB		 6012}
6013
3a9627f4
WF		 6014static bool intel_eld_uptodate(struct drm_connector *connector,
6015 int reg_eldv, uint32_t bits_eldv,
6016 int reg_elda, uint32_t bits_elda,
6017 int reg_edid)
6018{
6019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6020 uint8_t *eld = connector->eld;
6021 uint32_t i;
6022
6023 i = I915_READ(reg_eldv);
6024 i &= bits_eldv;
6025
6026 if (!eld[0])
6027 return !i;
6028
6029 if (!i)
6030 return false;
6031
6032 i = I915_READ(reg_elda);
6033 i &= ~bits_elda;
6034 I915_WRITE(reg_elda, i);
6035
6036 for (i = 0; i < eld[2]; i++)
6037 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6038 return false;
6039
6040 return true;
6041}
6042
e0dac65e
WF		 6043static void g4x_write_eld(struct drm_connector *connector,
6044 struct drm_crtc *crtc)
6045{
6046 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6047 uint8_t *eld = connector->eld;
6048 uint32_t eldv;
6049 uint32_t len;
6050 uint32_t i;
6051
6052 i = I915_READ(G4X_AUD_VID_DID);
6053
6054 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6055 eldv = G4X_ELDV_DEVCL_DEVBLC;
6056 else
6057 eldv = G4X_ELDV_DEVCTG;
6058
3a9627f4
WF		 6059 if (intel_eld_uptodate(connector,
6060 G4X_AUD_CNTL_ST, eldv,
6061 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6062 G4X_HDMIW_HDMIEDID))
6063 return;
6064
e0dac65e
WF		 6065 i = I915_READ(G4X_AUD_CNTL_ST);
6066 i &= ~(eldv | G4X_ELD_ADDR);
6067 len = (i >> 9) & 0x1f; /* ELD buffer size */
6068 I915_WRITE(G4X_AUD_CNTL_ST, i);
6069
6070 if (!eld[0])
6071 return;
6072
6073 len = min_t(uint8_t, eld[2], len);
6074 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6075 for (i = 0; i < len; i++)
6076 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6077
6078 i = I915_READ(G4X_AUD_CNTL_ST);
6079 i |= eldv;
6080 I915_WRITE(G4X_AUD_CNTL_ST, i);
6081}
6082
83358c85
WX		 6083static void haswell_write_eld(struct drm_connector *connector,
6084 struct drm_crtc *crtc)
6085{
6086 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6087 uint8_t *eld = connector->eld;
6088 struct drm_device *dev = crtc->dev;
7b9f35a6 6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6090 uint32_t eldv;
6091 uint32_t i;
6092 int len;
6093 int pipe = to_intel_crtc(crtc)->pipe;
6094 int tmp;
6095
6096 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6097 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6098 int aud_config = HSW_AUD_CFG(pipe);
6099 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6100
6101
6102 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6103
6104 /* Audio output enable */
6105 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6106 tmp = I915_READ(aud_cntrl_st2);
6107 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6108 I915_WRITE(aud_cntrl_st2, tmp);
6109
6110 /* Wait for 1 vertical blank */
6111 intel_wait_for_vblank(dev, pipe);
6112
6113 /* Set ELD valid state */
6114 tmp = I915_READ(aud_cntrl_st2);
6115 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6116 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6117 I915_WRITE(aud_cntrl_st2, tmp);
6118 tmp = I915_READ(aud_cntrl_st2);
6119 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6120
6121 /* Enable HDMI mode */
6122 tmp = I915_READ(aud_config);
6123 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6124 /* clear N_programing_enable and N_value_index */
6125 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6126 I915_WRITE(aud_config, tmp);
6127
6128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6129
6130 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6131 intel_crtc->eld_vld = true;
83358c85
WX		 6132
6133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6134 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6135 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6136 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6137 } else
6138 I915_WRITE(aud_config, 0);
6139
6140 if (intel_eld_uptodate(connector,
6141 aud_cntrl_st2, eldv,
6142 aud_cntl_st, IBX_ELD_ADDRESS,
6143 hdmiw_hdmiedid))
6144 return;
6145
6146 i = I915_READ(aud_cntrl_st2);
6147 i &= ~eldv;
6148 I915_WRITE(aud_cntrl_st2, i);
6149
6150 if (!eld[0])
6151 return;
6152
6153 i = I915_READ(aud_cntl_st);
6154 i &= ~IBX_ELD_ADDRESS;
6155 I915_WRITE(aud_cntl_st, i);
6156 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6157 DRM_DEBUG_DRIVER("port num:%d\n", i);
6158
6159 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6161 for (i = 0; i < len; i++)
6162 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6163
6164 i = I915_READ(aud_cntrl_st2);
6165 i |= eldv;
6166 I915_WRITE(aud_cntrl_st2, i);
6167
6168}
6169
e0dac65e
WF		 6170static void ironlake_write_eld(struct drm_connector *connector,
6171 struct drm_crtc *crtc)
6172{
6173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6174 uint8_t *eld = connector->eld;
6175 uint32_t eldv;
6176 uint32_t i;
6177 int len;
6178 int hdmiw_hdmiedid;
b6daa025 6179 int aud_config;
e0dac65e
WF		 6180 int aud_cntl_st;
6181 int aud_cntrl_st2;
9b138a83 6182 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6183
b3f33cbf 6184 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6185 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6186 aud_config = IBX_AUD_CFG(pipe);
6187 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6188 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6189 } else {
9b138a83
WX		 6190 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6191 aud_config = CPT_AUD_CFG(pipe);
6192 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6193 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6194 }
6195
9b138a83 6196 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6197
6198 i = I915_READ(aud_cntl_st);
9b138a83 6199 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6200 if (!i) {
6201 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6202 /* operate blindly on all ports */
1202b4c6
WF		 6203 eldv = IBX_ELD_VALIDB;
6204 eldv |= IBX_ELD_VALIDB << 4;
6205 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6206 } else {
2582a850 6207 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6208 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6209 }
6210
3a9627f4
WF		 6211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6212 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6213 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6214 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6215 } else
6216 I915_WRITE(aud_config, 0);
e0dac65e 6217
3a9627f4
WF		 6218 if (intel_eld_uptodate(connector,
6219 aud_cntrl_st2, eldv,
6220 aud_cntl_st, IBX_ELD_ADDRESS,
6221 hdmiw_hdmiedid))
6222 return;
6223
e0dac65e
WF		 6224 i = I915_READ(aud_cntrl_st2);
6225 i &= ~eldv;
6226 I915_WRITE(aud_cntrl_st2, i);
6227
6228 if (!eld[0])
6229 return;
6230
e0dac65e 6231 i = I915_READ(aud_cntl_st);
1202b4c6 6232 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6233 I915_WRITE(aud_cntl_st, i);
6234
6235 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6236 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6237 for (i = 0; i < len; i++)
6238 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6239
6240 i = I915_READ(aud_cntrl_st2);
6241 i |= eldv;
6242 I915_WRITE(aud_cntrl_st2, i);
6243}
6244
6245void intel_write_eld(struct drm_encoder *encoder,
6246 struct drm_display_mode *mode)
6247{
6248 struct drm_crtc *crtc = encoder->crtc;
6249 struct drm_connector *connector;
6250 struct drm_device *dev = encoder->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252
6253 connector = drm_select_eld(encoder, mode);
6254 if (!connector)
6255 return;
6256
6257 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6258 connector->base.id,
6259 drm_get_connector_name(connector),
6260 connector->encoder->base.id,
6261 drm_get_encoder_name(connector->encoder));
6262
6263 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6264
6265 if (dev_priv->display.write_eld)
6266 dev_priv->display.write_eld(connector, crtc);
6267}
6268
79e53945
JB		 6269/** Loads the palette/gamma unit for the CRTC with the prepared values */
6270void intel_crtc_load_lut(struct drm_crtc *crtc)
6271{
6272 struct drm_device *dev = crtc->dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6275 enum pipe pipe = intel_crtc->pipe;
6276 int palreg = PALETTE(pipe);
79e53945 6277 int i;
42db64ef 6278 bool reenable_ips = false;
79e53945
JB		 6279
6280 /* The clocks have to be on to load the palette. */
aed3f09d 6281 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6282 return;
6283
14420bd0
VS		 6284 if (!HAS_PCH_SPLIT(dev_priv->dev))
6285 assert_pll_enabled(dev_priv, pipe);
6286
f2b115e6 6287 /* use legacy palette for Ironlake */
bad720ff 6288 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6289 palreg = LGC_PALETTE(pipe);
6290
6291 /* Workaround : Do not read or write the pipe palette/gamma data while
6292 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6293 */
6294 if (intel_crtc->config.ips_enabled &&
6295 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6296 GAMMA_MODE_MODE_SPLIT)) {
6297 hsw_disable_ips(intel_crtc);
6298 reenable_ips = true;
6299 }
2c07245f 6300
79e53945
JB		 6301 for (i = 0; i < 256; i++) {
6302 I915_WRITE(palreg + 4 * i,
6303 (intel_crtc->lut_r[i] << 16) |
6304 (intel_crtc->lut_g[i] << 8) |
6305 intel_crtc->lut_b[i]);
6306 }
42db64ef
PZ		 6307
6308 if (reenable_ips)
6309 hsw_enable_ips(intel_crtc);
79e53945
JB		 6310}
6311
560b85bb
CW		 6312static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6313{
6314 struct drm_device *dev = crtc->dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6317 bool visible = base != 0;
6318 u32 cntl;
6319
6320 if (intel_crtc->cursor_visible == visible)
6321 return;
6322
9db4a9c7 6323 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6324 if (visible) {
6325 /* On these chipsets we can only modify the base whilst
6326 * the cursor is disabled.
6327 */
9db4a9c7 6328 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6329
6330 cntl &= ~(CURSOR_FORMAT_MASK);
6331 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6332 cntl |= CURSOR_ENABLE |
6333 CURSOR_GAMMA_ENABLE |
6334 CURSOR_FORMAT_ARGB;
6335 } else
6336 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6337 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6338
6339 intel_crtc->cursor_visible = visible;
6340}
6341
6342static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6343{
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 int pipe = intel_crtc->pipe;
6348 bool visible = base != 0;
6349
6350 if (intel_crtc->cursor_visible != visible) {
548f245b 6351 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6352 if (base) {
6353 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6354 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6355 cntl |= pipe << 28; /* Connect to correct pipe */
6356 } else {
6357 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6358 cntl |= CURSOR_MODE_DISABLE;
6359 }
9db4a9c7 6360 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6361
6362 intel_crtc->cursor_visible = visible;
6363 }
6364 /* and commit changes on next vblank */
9db4a9c7 6365 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6366}
6367
65a21cd6
JB		 6368static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6369{
6370 struct drm_device *dev = crtc->dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6373 int pipe = intel_crtc->pipe;
6374 bool visible = base != 0;
6375
6376 if (intel_crtc->cursor_visible != visible) {
6377 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6378 if (base) {
6379 cntl &= ~CURSOR_MODE;
6380 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6381 } else {
6382 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6383 cntl |= CURSOR_MODE_DISABLE;
6384 }
86d3efce
VS		 6385 if (IS_HASWELL(dev))
6386 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6387 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6388
6389 intel_crtc->cursor_visible = visible;
6390 }
6391 /* and commit changes on next vblank */
6392 I915_WRITE(CURBASE_IVB(pipe), base);
6393}
6394
cda4b7d3 6395/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6396static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6397 bool on)
cda4b7d3
CW		 6398{
6399 struct drm_device *dev = crtc->dev;
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6402 int pipe = intel_crtc->pipe;
6403 int x = intel_crtc->cursor_x;
6404 int y = intel_crtc->cursor_y;
560b85bb 6405 u32 base, pos;
cda4b7d3
CW		 6406 bool visible;
6407
6408 pos = 0;
6409
6b383a7f 6410 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6411 base = intel_crtc->cursor_addr;
6412 if (x > (int) crtc->fb->width)
6413 base = 0;
6414
6415 if (y > (int) crtc->fb->height)
6416 base = 0;
6417 } else
6418 base = 0;
6419
6420 if (x < 0) {
6421 if (x + intel_crtc->cursor_width < 0)
6422 base = 0;
6423
6424 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6425 x = -x;
6426 }
6427 pos |= x << CURSOR_X_SHIFT;
6428
6429 if (y < 0) {
6430 if (y + intel_crtc->cursor_height < 0)
6431 base = 0;
6432
6433 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6434 y = -y;
6435 }
6436 pos |= y << CURSOR_Y_SHIFT;
6437
6438 visible = base != 0;
560b85bb 6439 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6440 return;
6441
0cd83aa9 6442 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6443 I915_WRITE(CURPOS_IVB(pipe), pos);
6444 ivb_update_cursor(crtc, base);
6445 } else {
6446 I915_WRITE(CURPOS(pipe), pos);
6447 if (IS_845G(dev) || IS_I865G(dev))
6448 i845_update_cursor(crtc, base);
6449 else
6450 i9xx_update_cursor(crtc, base);
6451 }
cda4b7d3
CW		 6452}
6453
79e53945 6454static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6455 struct drm_file *file,
79e53945
JB		 6456 uint32_t handle,
6457 uint32_t width, uint32_t height)
6458{
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6462 struct drm_i915_gem_object *obj;
cda4b7d3 6463 uint32_t addr;
3f8bc370 6464 int ret;
79e53945 6465
79e53945
JB		 6466 /* if we want to turn off the cursor ignore width and height */
6467 if (!handle) {
28c97730 6468 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6469 addr = 0;
05394f39 6470 obj = NULL;
5004417d 6471 mutex_lock(&dev->struct_mutex);
3f8bc370 6472 goto finish;
79e53945
JB		 6473 }
6474
6475 /* Currently we only support 64x64 cursors */
6476 if (width != 64 || height != 64) {
6477 DRM_ERROR("we currently only support 64x64 cursors\n");
6478 return -EINVAL;
6479 }
6480
05394f39 6481 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6482 if (&obj->base == NULL)
79e53945
JB		 6483 return -ENOENT;
6484
05394f39 6485 if (obj->base.size < width * height * 4) {
79e53945 6486 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6487 ret = -ENOMEM;
6488 goto fail;
79e53945
JB		 6489 }
6490
71acb5eb 6491 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6492 mutex_lock(&dev->struct_mutex);
b295d1b6 6493 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6494 unsigned alignment;
6495
d9e86c0e
CW		 6496 if (obj->tiling_mode) {
6497 DRM_ERROR("cursor cannot be tiled\n");
6498 ret = -EINVAL;
6499 goto fail_locked;
6500 }
6501
693db184
CW		 6502 /* Note that the w/a also requires 2 PTE of padding following
6503 * the bo. We currently fill all unused PTE with the shadow
6504 * page and so we should always have valid PTE following the
6505 * cursor preventing the VT-d warning.
6506 */
6507 alignment = 0;
6508 if (need_vtd_wa(dev))
6509 alignment = 64*1024;
6510
6511 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6512 if (ret) {
6513 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6514 goto fail_locked;
e7b526bb
CW		 6515 }
6516
d9e86c0e
CW		 6517 ret = i915_gem_object_put_fence(obj);
6518 if (ret) {
2da3b9b9 6519 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6520 goto fail_unpin;
6521 }
6522
05394f39 6523 addr = obj->gtt_offset;
71acb5eb 6524 } else {
6eeefaf3 6525 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6526 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6527 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6528 align);
71acb5eb
DA		 6529 if (ret) {
6530 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6531 goto fail_locked;
71acb5eb 6532 }
05394f39 6533 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6534 }
6535
a6c45cf0 6536 if (IS_GEN2(dev))
14b60391
JB		 6537 I915_WRITE(CURSIZE, (height << 12) | width);
6538
3f8bc370 6539 finish:
3f8bc370 6540 if (intel_crtc->cursor_bo) {
b295d1b6 6541 if (dev_priv->info->cursor_needs_physical) {
05394f39 6542 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6543 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6544 } else
6545 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6546 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6547 }
80824003 6548
7f9872e0 6549 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6550
6551 intel_crtc->cursor_addr = addr;
05394f39 6552 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6553 intel_crtc->cursor_width = width;
6554 intel_crtc->cursor_height = height;
6555
40ccc72b 6556 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6557
79e53945 6558 return 0;
e7b526bb 6559fail_unpin:
05394f39 6560 i915_gem_object_unpin(obj);
7f9872e0 6561fail_locked:
34b8686e 6562 mutex_unlock(&dev->struct_mutex);
bc9025bd 6563fail:
05394f39 6564 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6565 return ret;
79e53945
JB		 6566}
6567
6568static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6569{
79e53945 6570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6571
cda4b7d3
CW		 6572 intel_crtc->cursor_x = x;
6573 intel_crtc->cursor_y = y;
652c393a 6574
40ccc72b 6575 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6576
6577 return 0;
6578}
6579
6580/** Sets the color ramps on behalf of RandR */
6581void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6582 u16 blue, int regno)
6583{
6584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6585
6586 intel_crtc->lut_r[regno] = red >> 8;
6587 intel_crtc->lut_g[regno] = green >> 8;
6588 intel_crtc->lut_b[regno] = blue >> 8;
6589}
6590
b8c00ac5
DA		 6591void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6592 u16 *blue, int regno)
6593{
6594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6595
6596 *red = intel_crtc->lut_r[regno] << 8;
6597 *green = intel_crtc->lut_g[regno] << 8;
6598 *blue = intel_crtc->lut_b[regno] << 8;
6599}
6600
79e53945 6601static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6602 u16 *blue, uint32_t start, uint32_t size)
79e53945 6603{
7203425a 6604 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6606
7203425a 6607 for (i = start; i < end; i++) {
79e53945
JB		 6608 intel_crtc->lut_r[i] = red[i] >> 8;
6609 intel_crtc->lut_g[i] = green[i] >> 8;
6610 intel_crtc->lut_b[i] = blue[i] >> 8;
6611 }
6612
6613 intel_crtc_load_lut(crtc);
6614}
6615
79e53945
JB		 6616/* VESA 640x480x72Hz mode to set on the pipe */
6617static struct drm_display_mode load_detect_mode = {
6618 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6619 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6620};
6621
d2dff872
CW		 6622static struct drm_framebuffer *
6623intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6624 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6625 struct drm_i915_gem_object *obj)
6626{
6627 struct intel_framebuffer *intel_fb;
6628 int ret;
6629
6630 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6631 if (!intel_fb) {
6632 drm_gem_object_unreference_unlocked(&obj->base);
6633 return ERR_PTR(-ENOMEM);
6634 }
6635
6636 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6637 if (ret) {
6638 drm_gem_object_unreference_unlocked(&obj->base);
6639 kfree(intel_fb);
6640 return ERR_PTR(ret);
6641 }
6642
6643 return &intel_fb->base;
6644}
6645
6646static u32
6647intel_framebuffer_pitch_for_width(int width, int bpp)
6648{
6649 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6650 return ALIGN(pitch, 64);
6651}
6652
6653static u32
6654intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6655{
6656 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6657 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6658}
6659
6660static struct drm_framebuffer *
6661intel_framebuffer_create_for_mode(struct drm_device *dev,
6662 struct drm_display_mode *mode,
6663 int depth, int bpp)
6664{
6665 struct drm_i915_gem_object *obj;
0fed39bd 6666 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6667
6668 obj = i915_gem_alloc_object(dev,
6669 intel_framebuffer_size_for_mode(mode, bpp));
6670 if (obj == NULL)
6671 return ERR_PTR(-ENOMEM);
6672
6673 mode_cmd.width = mode->hdisplay;
6674 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6675 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6676 bpp);
5ca0c34a 6677 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6678
6679 return intel_framebuffer_create(dev, &mode_cmd, obj);
6680}
6681
6682static struct drm_framebuffer *
6683mode_fits_in_fbdev(struct drm_device *dev,
6684 struct drm_display_mode *mode)
6685{
6686 struct drm_i915_private *dev_priv = dev->dev_private;
6687 struct drm_i915_gem_object *obj;
6688 struct drm_framebuffer *fb;
6689
6690 if (dev_priv->fbdev == NULL)
6691 return NULL;
6692
6693 obj = dev_priv->fbdev->ifb.obj;
6694 if (obj == NULL)
6695 return NULL;
6696
6697 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6698 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6699 fb->bits_per_pixel))
d2dff872
CW		 6700 return NULL;
6701
01f2c773 6702 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6703 return NULL;
6704
6705 return fb;
6706}
6707
d2434ab7 6708bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6709 struct drm_display_mode *mode,
8261b191 6710 struct intel_load_detect_pipe *old)
79e53945
JB		 6711{
6712 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6713 struct intel_encoder *intel_encoder =
6714 intel_attached_encoder(connector);
79e53945 6715 struct drm_crtc *possible_crtc;
4ef69c7a 6716 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6717 struct drm_crtc *crtc = NULL;
6718 struct drm_device *dev = encoder->dev;
94352cf9 6719 struct drm_framebuffer *fb;
79e53945
JB		 6720 int i = -1;
6721
d2dff872
CW		 6722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6723 connector->base.id, drm_get_connector_name(connector),
6724 encoder->base.id, drm_get_encoder_name(encoder));
6725
79e53945
JB		 6726 /*
6727 * Algorithm gets a little messy:
7a5e4805 6728 *
79e53945
JB		 6729 * - if the connector already has an assigned crtc, use it (but make
6730 * sure it's on first)
7a5e4805 6731 *
79e53945
JB		 6732 * - try to find the first unused crtc that can drive this connector,
6733 * and use that if we find one
79e53945
JB		 6734 */
6735
6736 /* See if we already have a CRTC for this connector */
6737 if (encoder->crtc) {
6738 crtc = encoder->crtc;
8261b191 6739
7b24056b
DV		 6740 mutex_lock(&crtc->mutex);
6741
24218aac 6742 old->dpms_mode = connector->dpms;
8261b191
CW		 6743 old->load_detect_temp = false;
6744
6745 /* Make sure the crtc and connector are running */
24218aac
DV		 6746 if (connector->dpms != DRM_MODE_DPMS_ON)
6747 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6748
7173188d 6749 return true;
79e53945
JB		 6750 }
6751
6752 /* Find an unused one (if possible) */
6753 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6754 i++;
6755 if (!(encoder->possible_crtcs & (1 << i)))
6756 continue;
6757 if (!possible_crtc->enabled) {
6758 crtc = possible_crtc;
6759 break;
6760 }
79e53945
JB		 6761 }
6762
6763 /*
6764 * If we didn't find an unused CRTC, don't use any.
6765 */
6766 if (!crtc) {
7173188d
CW		 6767 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6768 return false;
79e53945
JB		 6769 }
6770
7b24056b 6771 mutex_lock(&crtc->mutex);
fc303101
DV		 6772 intel_encoder->new_crtc = to_intel_crtc(crtc);
6773 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6774
6775 intel_crtc = to_intel_crtc(crtc);
24218aac 6776 old->dpms_mode = connector->dpms;
8261b191 6777 old->load_detect_temp = true;
d2dff872 6778 old->release_fb = NULL;
79e53945 6779
6492711d
CW		 6780 if (!mode)
6781 mode = &load_detect_mode;
79e53945 6782
d2dff872
CW		 6783 /* We need a framebuffer large enough to accommodate all accesses
6784 * that the plane may generate whilst we perform load detection.
6785 * We can not rely on the fbcon either being present (we get called
6786 * during its initialisation to detect all boot displays, or it may
6787 * not even exist) or that it is large enough to satisfy the
6788 * requested mode.
6789 */
94352cf9
DV		 6790 fb = mode_fits_in_fbdev(dev, mode);
6791 if (fb == NULL) {
d2dff872 6792 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6793 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6794 old->release_fb = fb;
d2dff872
CW		 6795 } else
6796 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6797 if (IS_ERR(fb)) {
d2dff872 6798 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6799 mutex_unlock(&crtc->mutex);
0e8b3d3e 6800 return false;
79e53945 6801 }
79e53945 6802
c0c36b94 6803 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6804 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6805 if (old->release_fb)
6806 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6807 mutex_unlock(&crtc->mutex);
0e8b3d3e 6808 return false;
79e53945 6809 }
7173188d 6810
79e53945 6811 /* let the connector get through one full cycle before testing */
9d0498a2 6812 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6813 return true;
79e53945
JB		 6814}
6815
d2434ab7 6816void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6817 struct intel_load_detect_pipe *old)
79e53945 6818{
d2434ab7
DV		 6819 struct intel_encoder *intel_encoder =
6820 intel_attached_encoder(connector);
4ef69c7a 6821 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6822 struct drm_crtc *crtc = encoder->crtc;
79e53945 6823
d2dff872
CW		 6824 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6825 connector->base.id, drm_get_connector_name(connector),
6826 encoder->base.id, drm_get_encoder_name(encoder));
6827
8261b191 6828 if (old->load_detect_temp) {
fc303101
DV		 6829 to_intel_connector(connector)->new_encoder = NULL;
6830 intel_encoder->new_crtc = NULL;
6831 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6832
36206361
DV		 6833 if (old->release_fb) {
6834 drm_framebuffer_unregister_private(old->release_fb);
6835 drm_framebuffer_unreference(old->release_fb);
6836 }
d2dff872 6837
67c96400 6838 mutex_unlock(&crtc->mutex);
0622a53c 6839 return;
79e53945
JB		 6840 }
6841
c751ce4f 6842 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6843 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6844 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6845
6846 mutex_unlock(&crtc->mutex);
79e53945
JB		 6847}
6848
6849/* Returns the clock of the currently programmed mode of the given pipe. */
6850static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6851{
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6854 int pipe = intel_crtc->pipe;
548f245b 6855 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6856 u32 fp;
6857 intel_clock_t clock;
6858
6859 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6860 fp = I915_READ(FP0(pipe));
79e53945 6861 else
39adb7a5 6862 fp = I915_READ(FP1(pipe));
79e53945
JB		 6863
6864 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6865 if (IS_PINEVIEW(dev)) {
6866 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6867 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6868 } else {
6869 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6870 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6871 }
6872
a6c45cf0 6873 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6874 if (IS_PINEVIEW(dev))
6875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6876 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6877 else
6878 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6879 DPLL_FPA01_P1_POST_DIV_SHIFT);
6880
6881 switch (dpll & DPLL_MODE_MASK) {
6882 case DPLLB_MODE_DAC_SERIAL:
6883 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6884 5 : 10;
6885 break;
6886 case DPLLB_MODE_LVDS:
6887 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6888 7 : 14;
6889 break;
6890 default:
28c97730 6891 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6892 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6893 return 0;
6894 }
6895
ac58c3f0
DV		 6896 if (IS_PINEVIEW(dev))
6897 pineview_clock(96000, &clock);
6898 else
6899 i9xx_clock(96000, &clock);
79e53945
JB		 6900 } else {
6901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6902
6903 if (is_lvds) {
6904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6905 DPLL_FPA01_P1_POST_DIV_SHIFT);
6906 clock.p2 = 14;
6907
6908 if ((dpll & PLL_REF_INPUT_MASK) ==
6909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6910 /* XXX: might not be 66MHz */
ac58c3f0 6911 i9xx_clock(66000, &clock);
79e53945 6912 } else
ac58c3f0 6913 i9xx_clock(48000, &clock);
79e53945
JB		 6914 } else {
6915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6916 clock.p1 = 2;
6917 else {
6918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6920 }
6921 if (dpll & PLL_P2_DIVIDE_BY_4)
6922 clock.p2 = 4;
6923 else
6924 clock.p2 = 2;
6925
ac58c3f0 6926 i9xx_clock(48000, &clock);
79e53945
JB		 6927 }
6928 }
6929
6930 /* XXX: It would be nice to validate the clocks, but we can't reuse
6931 * i830PllIsValid() because it relies on the xf86_config connector
6932 * configuration being accurate, which it isn't necessarily.
6933 */
6934
6935 return clock.dot;
6936}
6937
6938/** Returns the currently programmed mode of the given pipe. */
6939struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6940 struct drm_crtc *crtc)
6941{
548f245b 6942 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6944 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6945 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6946 int htot = I915_READ(HTOTAL(cpu_transcoder));
6947 int hsync = I915_READ(HSYNC(cpu_transcoder));
6948 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6949 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6950
6951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6952 if (!mode)
6953 return NULL;
6954
6955 mode->clock = intel_crtc_clock_get(dev, crtc);
6956 mode->hdisplay = (htot & 0xffff) + 1;
6957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6958 mode->hsync_start = (hsync & 0xffff) + 1;
6959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6960 mode->vdisplay = (vtot & 0xffff) + 1;
6961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6962 mode->vsync_start = (vsync & 0xffff) + 1;
6963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6964
6965 drm_mode_set_name(mode);
79e53945
JB		 6966
6967 return mode;
6968}
6969
3dec0095 6970static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6971{
6972 struct drm_device *dev = crtc->dev;
6973 drm_i915_private_t *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6976 int dpll_reg = DPLL(pipe);
6977 int dpll;
652c393a 6978
bad720ff 6979 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6980 return;
6981
6982 if (!dev_priv->lvds_downclock_avail)
6983 return;
6984
dbdc6479 6985 dpll = I915_READ(dpll_reg);
652c393a 6986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6988
8ac5a6d5 6989 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6990
6991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6992 I915_WRITE(dpll_reg, dpll);
9d0498a2 6993 intel_wait_for_vblank(dev, pipe);
dbdc6479 6994
652c393a
JB		 6995 dpll = I915_READ(dpll_reg);
6996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6998 }
652c393a
JB		 6999}
7000
7001static void intel_decrease_pllclock(struct drm_crtc *crtc)
7002{
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7006
bad720ff 7007 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7008 return;
7009
7010 if (!dev_priv->lvds_downclock_avail)
7011 return;
7012
7013 /*
7014 * Since this is called by a timer, we should never get here in
7015 * the manual case.
7016 */
7017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7018 int pipe = intel_crtc->pipe;
7019 int dpll_reg = DPLL(pipe);
7020 int dpll;
f6e5b160 7021
44d98a61 7022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7023
8ac5a6d5 7024 assert_panel_unlocked(dev_priv, pipe);
652c393a 7025
dc257cf1 7026 dpll = I915_READ(dpll_reg);
652c393a
JB		 7027 dpll |= DISPLAY_RATE_SELECT_FPA1;
7028 I915_WRITE(dpll_reg, dpll);
9d0498a2 7029 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7030 dpll = I915_READ(dpll_reg);
7031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7033 }
7034
7035}
7036
f047e395
CW		 7037void intel_mark_busy(struct drm_device *dev)
7038{
f047e395
CW		 7039 i915_update_gfx_val(dev->dev_private);
7040}
7041
7042void intel_mark_idle(struct drm_device *dev)
652c393a 7043{
652c393a 7044 struct drm_crtc *crtc;
652c393a
JB		 7045
7046 if (!i915_powersave)
7047 return;
7048
652c393a 7049 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7050 if (!crtc->fb)
7051 continue;
7052
725a5b54 7053 intel_decrease_pllclock(crtc);
652c393a 7054 }
652c393a
JB		 7055}
7056
c65355bb
CW		 7057void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7058 struct intel_ring_buffer *ring)
652c393a 7059{
f047e395
CW		 7060 struct drm_device *dev = obj->base.dev;
7061 struct drm_crtc *crtc;
652c393a 7062
f047e395 7063 if (!i915_powersave)
acb87dfb
CW		 7064 return;
7065
652c393a
JB		 7066 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7067 if (!crtc->fb)
7068 continue;
7069
c65355bb
CW		 7070 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7071 continue;
7072
7073 intel_increase_pllclock(crtc);
7074 if (ring && intel_fbc_enabled(dev))
7075 ring->fbc_dirty = true;
652c393a
JB		 7076 }
7077}
7078
79e53945
JB		 7079static void intel_crtc_destroy(struct drm_crtc *crtc)
7080{
7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7082 struct drm_device *dev = crtc->dev;
7083 struct intel_unpin_work *work;
7084 unsigned long flags;
7085
7086 spin_lock_irqsave(&dev->event_lock, flags);
7087 work = intel_crtc->unpin_work;
7088 intel_crtc->unpin_work = NULL;
7089 spin_unlock_irqrestore(&dev->event_lock, flags);
7090
7091 if (work) {
7092 cancel_work_sync(&work->work);
7093 kfree(work);
7094 }
79e53945 7095
40ccc72b
MK		 7096 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7097
79e53945 7098 drm_crtc_cleanup(crtc);
67e77c5a 7099
79e53945
JB		 7100 kfree(intel_crtc);
7101}
7102
6b95a207
KH		 7103static void intel_unpin_work_fn(struct work_struct *__work)
7104{
7105 struct intel_unpin_work *work =
7106 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7107 struct drm_device *dev = work->crtc->dev;
6b95a207 7108
b4a98e57 7109 mutex_lock(&dev->struct_mutex);
1690e1eb 7110 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7111 drm_gem_object_unreference(&work->pending_flip_obj->base);
7112 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7113
b4a98e57
CW		 7114 intel_update_fbc(dev);
7115 mutex_unlock(&dev->struct_mutex);
7116
7117 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7118 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7119
6b95a207
KH		 7120 kfree(work);
7121}
7122
1afe3e9d 7123static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7124 struct drm_crtc *crtc)
6b95a207
KH		 7125{
7126 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128 struct intel_unpin_work *work;
6b95a207
KH		 7129 unsigned long flags;
7130
7131 /* Ignore early vblank irqs */
7132 if (intel_crtc == NULL)
7133 return;
7134
7135 spin_lock_irqsave(&dev->event_lock, flags);
7136 work = intel_crtc->unpin_work;
e7d841ca
CW		 7137
7138 /* Ensure we don't miss a work->pending update ... */
7139 smp_rmb();
7140
7141 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7142 spin_unlock_irqrestore(&dev->event_lock, flags);
7143 return;
7144 }
7145
e7d841ca
CW		 7146 /* and that the unpin work is consistent wrt ->pending. */
7147 smp_rmb();
7148
6b95a207 7149 intel_crtc->unpin_work = NULL;
6b95a207 7150
45a066eb
RC		 7151 if (work->event)
7152 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7153
0af7e4df
MK		 7154 drm_vblank_put(dev, intel_crtc->pipe);
7155
6b95a207
KH		 7156 spin_unlock_irqrestore(&dev->event_lock, flags);
7157
2c10d571 7158 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7159
7160 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7161
7162 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7163}
7164
1afe3e9d
JB		 7165void intel_finish_page_flip(struct drm_device *dev, int pipe)
7166{
7167 drm_i915_private_t *dev_priv = dev->dev_private;
7168 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7169
49b14a5c 7170 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7171}
7172
7173void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7174{
7175 drm_i915_private_t *dev_priv = dev->dev_private;
7176 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7177
49b14a5c 7178 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7179}
7180
6b95a207
KH		 7181void intel_prepare_page_flip(struct drm_device *dev, int plane)
7182{
7183 drm_i915_private_t *dev_priv = dev->dev_private;
7184 struct intel_crtc *intel_crtc =
7185 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7186 unsigned long flags;
7187
e7d841ca
CW		 7188 /* NB: An MMIO update of the plane base pointer will also
7189 * generate a page-flip completion irq, i.e. every modeset
7190 * is also accompanied by a spurious intel_prepare_page_flip().
7191 */
6b95a207 7192 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7193 if (intel_crtc->unpin_work)
7194 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7195 spin_unlock_irqrestore(&dev->event_lock, flags);
7196}
7197
e7d841ca
CW		 7198inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7199{
7200 /* Ensure that the work item is consistent when activating it ... */
7201 smp_wmb();
7202 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7203 /* and that it is marked active as soon as the irq could fire. */
7204 smp_wmb();
7205}
7206
8c9f3aaf
JB		 7207static int intel_gen2_queue_flip(struct drm_device *dev,
7208 struct drm_crtc *crtc,
7209 struct drm_framebuffer *fb,
7210 struct drm_i915_gem_object *obj)
7211{
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7214 u32 flip_mask;
6d90c952 7215 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7216 int ret;
7217
6d90c952 7218 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7219 if (ret)
83d4092b 7220 goto err;
8c9f3aaf 7221
6d90c952 7222 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7223 if (ret)
83d4092b 7224 goto err_unpin;
8c9f3aaf
JB		 7225
7226 /* Can't queue multiple flips, so wait for the previous
7227 * one to finish before executing the next.
7228 */
7229 if (intel_crtc->plane)
7230 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7231 else
7232 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7233 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7234 intel_ring_emit(ring, MI_NOOP);
7235 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7236 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7237 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7238 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7239 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7240
7241 intel_mark_page_flip_active(intel_crtc);
6d90c952 7242 intel_ring_advance(ring);
83d4092b
CW		 7243 return 0;
7244
7245err_unpin:
7246 intel_unpin_fb_obj(obj);
7247err:
8c9f3aaf
JB		 7248 return ret;
7249}
7250
7251static int intel_gen3_queue_flip(struct drm_device *dev,
7252 struct drm_crtc *crtc,
7253 struct drm_framebuffer *fb,
7254 struct drm_i915_gem_object *obj)
7255{
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7258 u32 flip_mask;
6d90c952 7259 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7260 int ret;
7261
6d90c952 7262 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7263 if (ret)
83d4092b 7264 goto err;
8c9f3aaf 7265
6d90c952 7266 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7267 if (ret)
83d4092b 7268 goto err_unpin;
8c9f3aaf
JB		 7269
7270 if (intel_crtc->plane)
7271 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7272 else
7273 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7274 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7275 intel_ring_emit(ring, MI_NOOP);
7276 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7277 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7278 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7279 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7280 intel_ring_emit(ring, MI_NOOP);
7281
e7d841ca 7282 intel_mark_page_flip_active(intel_crtc);
6d90c952 7283 intel_ring_advance(ring);
83d4092b
CW		 7284 return 0;
7285
7286err_unpin:
7287 intel_unpin_fb_obj(obj);
7288err:
8c9f3aaf
JB		 7289 return ret;
7290}
7291
7292static int intel_gen4_queue_flip(struct drm_device *dev,
7293 struct drm_crtc *crtc,
7294 struct drm_framebuffer *fb,
7295 struct drm_i915_gem_object *obj)
7296{
7297 struct drm_i915_private *dev_priv = dev->dev_private;
7298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7299 uint32_t pf, pipesrc;
6d90c952 7300 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7301 int ret;
7302
6d90c952 7303 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7304 if (ret)
83d4092b 7305 goto err;
8c9f3aaf 7306
6d90c952 7307 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7308 if (ret)
83d4092b 7309 goto err_unpin;
8c9f3aaf
JB		 7310
7311 /* i965+ uses the linear or tiled offsets from the
7312 * Display Registers (which do not change across a page-flip)
7313 * so we need only reprogram the base address.
7314 */
6d90c952
DV		 7315 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7316 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7317 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7318 intel_ring_emit(ring,
7319 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7320 obj->tiling_mode);
8c9f3aaf
JB		 7321
7322 /* XXX Enabling the panel-fitter across page-flip is so far
7323 * untested on non-native modes, so ignore it for now.
7324 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7325 */
7326 pf = 0;
7327 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7328 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7329
7330 intel_mark_page_flip_active(intel_crtc);
6d90c952 7331 intel_ring_advance(ring);
83d4092b
CW		 7332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
8c9f3aaf
JB		 7337 return ret;
7338}
7339
7340static int intel_gen6_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344{
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7347 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7348 uint32_t pf, pipesrc;
7349 int ret;
7350
6d90c952 7351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7352 if (ret)
83d4092b 7353 goto err;
8c9f3aaf 7354
6d90c952 7355 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7356 if (ret)
83d4092b 7357 goto err_unpin;
8c9f3aaf 7358
6d90c952
DV		 7359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7361 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7362 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7363
dc257cf1
DV		 7364 /* Contrary to the suggestions in the documentation,
7365 * "Enable Panel Fitter" does not seem to be required when page
7366 * flipping with a non-native mode, and worse causes a normal
7367 * modeset to fail.
7368 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7369 */
7370 pf = 0;
8c9f3aaf 7371 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7372 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7373
7374 intel_mark_page_flip_active(intel_crtc);
6d90c952 7375 intel_ring_advance(ring);
83d4092b
CW		 7376 return 0;
7377
7378err_unpin:
7379 intel_unpin_fb_obj(obj);
7380err:
8c9f3aaf
JB		 7381 return ret;
7382}
7383
7c9017e5
JB		 7384/*
7385 * On gen7 we currently use the blit ring because (in early silicon at least)
7386 * the render ring doesn't give us interrpts for page flip completion, which
7387 * means clients will hang after the first flip is queued. Fortunately the
7388 * blit ring generates interrupts properly, so use it instead.
7389 */
7390static int intel_gen7_queue_flip(struct drm_device *dev,
7391 struct drm_crtc *crtc,
7392 struct drm_framebuffer *fb,
7393 struct drm_i915_gem_object *obj)
7394{
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7397 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7398 uint32_t plane_bit = 0;
7c9017e5
JB		 7399 int ret;
7400
7401 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7402 if (ret)
83d4092b 7403 goto err;
7c9017e5 7404
cb05d8de
DV		 7405 switch(intel_crtc->plane) {
7406 case PLANE_A:
7407 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7408 break;
7409 case PLANE_B:
7410 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7411 break;
7412 case PLANE_C:
7413 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7414 break;
7415 default:
7416 WARN_ONCE(1, "unknown plane in flip command\n");
7417 ret = -ENODEV;
ab3951eb 7418 goto err_unpin;
cb05d8de
DV		 7419 }
7420
7c9017e5
JB		 7421 ret = intel_ring_begin(ring, 4);
7422 if (ret)
83d4092b 7423 goto err_unpin;
7c9017e5 7424
cb05d8de 7425 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7426 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7427 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7428 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7429
7430 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7431 intel_ring_advance(ring);
83d4092b
CW		 7432 return 0;
7433
7434err_unpin:
7435 intel_unpin_fb_obj(obj);
7436err:
7c9017e5
JB		 7437 return ret;
7438}
7439
8c9f3aaf
JB		 7440static int intel_default_queue_flip(struct drm_device *dev,
7441 struct drm_crtc *crtc,
7442 struct drm_framebuffer *fb,
7443 struct drm_i915_gem_object *obj)
7444{
7445 return -ENODEV;
7446}
7447
6b95a207
KH		 7448static int intel_crtc_page_flip(struct drm_crtc *crtc,
7449 struct drm_framebuffer *fb,
7450 struct drm_pending_vblank_event *event)
7451{
7452 struct drm_device *dev = crtc->dev;
7453 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7454 struct drm_framebuffer *old_fb = crtc->fb;
7455 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 struct intel_unpin_work *work;
8c9f3aaf 7458 unsigned long flags;
52e68630 7459 int ret;
6b95a207 7460
e6a595d2
VS		 7461 /* Can't change pixel format via MI display flips. */
7462 if (fb->pixel_format != crtc->fb->pixel_format)
7463 return -EINVAL;
7464
7465 /*
7466 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7467 * Note that pitch changes could also affect these register.
7468 */
7469 if (INTEL_INFO(dev)->gen > 3 &&
7470 (fb->offsets[0] != crtc->fb->offsets[0] ||
7471 fb->pitches[0] != crtc->fb->pitches[0]))
7472 return -EINVAL;
7473
6b95a207
KH		 7474 work = kzalloc(sizeof *work, GFP_KERNEL);
7475 if (work == NULL)
7476 return -ENOMEM;
7477
6b95a207 7478 work->event = event;
b4a98e57 7479 work->crtc = crtc;
4a35f83b 7480 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7481 INIT_WORK(&work->work, intel_unpin_work_fn);
7482
7317c75e
JB		 7483 ret = drm_vblank_get(dev, intel_crtc->pipe);
7484 if (ret)
7485 goto free_work;
7486
6b95a207
KH		 7487 /* We borrow the event spin lock for protecting unpin_work */
7488 spin_lock_irqsave(&dev->event_lock, flags);
7489 if (intel_crtc->unpin_work) {
7490 spin_unlock_irqrestore(&dev->event_lock, flags);
7491 kfree(work);
7317c75e 7492 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7493
7494 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7495 return -EBUSY;
7496 }
7497 intel_crtc->unpin_work = work;
7498 spin_unlock_irqrestore(&dev->event_lock, flags);
7499
b4a98e57
CW		 7500 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7501 flush_workqueue(dev_priv->wq);
7502
79158103
CW		 7503 ret = i915_mutex_lock_interruptible(dev);
7504 if (ret)
7505 goto cleanup;
6b95a207 7506
75dfca80 7507 /* Reference the objects for the scheduled work. */
05394f39
CW		 7508 drm_gem_object_reference(&work->old_fb_obj->base);
7509 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7510
7511 crtc->fb = fb;
96b099fd 7512
e1f99ce6 7513 work->pending_flip_obj = obj;
e1f99ce6 7514
4e5359cd
SF		 7515 work->enable_stall_check = true;
7516
b4a98e57 7517 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7518 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7519
8c9f3aaf
JB		 7520 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7521 if (ret)
7522 goto cleanup_pending;
6b95a207 7523
7782de3b 7524 intel_disable_fbc(dev);
c65355bb 7525 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7526 mutex_unlock(&dev->struct_mutex);
7527
e5510fac
JB		 7528 trace_i915_flip_request(intel_crtc->plane, obj);
7529
6b95a207 7530 return 0;
96b099fd 7531
8c9f3aaf 7532cleanup_pending:
b4a98e57 7533 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7534 crtc->fb = old_fb;
05394f39
CW		 7535 drm_gem_object_unreference(&work->old_fb_obj->base);
7536 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7537 mutex_unlock(&dev->struct_mutex);
7538
79158103 7539cleanup:
96b099fd
CW		 7540 spin_lock_irqsave(&dev->event_lock, flags);
7541 intel_crtc->unpin_work = NULL;
7542 spin_unlock_irqrestore(&dev->event_lock, flags);
7543
7317c75e
JB		 7544 drm_vblank_put(dev, intel_crtc->pipe);
7545free_work:
96b099fd
CW		 7546 kfree(work);
7547
7548 return ret;
6b95a207
KH		 7549}
7550
f6e5b160 7551static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7552 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7553 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7554};
7555
50f56119
DV		 7556static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7557 struct drm_crtc *crtc)
7558{
7559 struct drm_device *dev;
7560 struct drm_crtc *tmp;
7561 int crtc_mask = 1;
47f1c6c9 7562
50f56119 7563 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7564
50f56119 7565 dev = crtc->dev;
47f1c6c9 7566
50f56119
DV		 7567 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7568 if (tmp == crtc)
7569 break;
7570 crtc_mask <<= 1;
7571 }
47f1c6c9 7572
50f56119
DV		 7573 if (encoder->possible_crtcs & crtc_mask)
7574 return true;
7575 return false;
47f1c6c9 7576}
79e53945 7577
9a935856
DV		 7578/**
7579 * intel_modeset_update_staged_output_state
7580 *
7581 * Updates the staged output configuration state, e.g. after we've read out the
7582 * current hw state.
7583 */
7584static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7585{
9a935856
DV		 7586 struct intel_encoder *encoder;
7587 struct intel_connector *connector;
f6e5b160 7588
9a935856
DV		 7589 list_for_each_entry(connector, &dev->mode_config.connector_list,
7590 base.head) {
7591 connector->new_encoder =
7592 to_intel_encoder(connector->base.encoder);
7593 }
f6e5b160 7594
9a935856
DV		 7595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7596 base.head) {
7597 encoder->new_crtc =
7598 to_intel_crtc(encoder->base.crtc);
7599 }
f6e5b160
CW		 7600}
7601
9a935856
DV		 7602/**
7603 * intel_modeset_commit_output_state
7604 *
7605 * This function copies the stage display pipe configuration to the real one.
7606 */
7607static void intel_modeset_commit_output_state(struct drm_device *dev)
7608{
7609 struct intel_encoder *encoder;
7610 struct intel_connector *connector;
f6e5b160 7611
9a935856
DV		 7612 list_for_each_entry(connector, &dev->mode_config.connector_list,
7613 base.head) {
7614 connector->base.encoder = &connector->new_encoder->base;
7615 }
f6e5b160 7616
9a935856
DV		 7617 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7618 base.head) {
7619 encoder->base.crtc = &encoder->new_crtc->base;
7620 }
7621}
7622
050f7aeb
DV		 7623static void
7624connected_sink_compute_bpp(struct intel_connector * connector,
7625 struct intel_crtc_config *pipe_config)
7626{
7627 int bpp = pipe_config->pipe_bpp;
7628
7629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7630 connector->base.base.id,
7631 drm_get_connector_name(&connector->base));
7632
7633 /* Don't use an invalid EDID bpc value */
7634 if (connector->base.display_info.bpc &&
7635 connector->base.display_info.bpc * 3 < bpp) {
7636 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7637 bpp, connector->base.display_info.bpc*3);
7638 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7639 }
7640
7641 /* Clamp bpp to 8 on screens without EDID 1.4 */
7642 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7643 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7644 bpp);
7645 pipe_config->pipe_bpp = 24;
7646 }
7647}
7648
4e53c2e0 7649static int
050f7aeb
DV		 7650compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7651 struct drm_framebuffer *fb,
7652 struct intel_crtc_config *pipe_config)
4e53c2e0 7653{
050f7aeb
DV		 7654 struct drm_device *dev = crtc->base.dev;
7655 struct intel_connector *connector;
4e53c2e0
DV		 7656 int bpp;
7657
d42264b1
DV		 7658 switch (fb->pixel_format) {
7659 case DRM_FORMAT_C8:
4e53c2e0
DV		 7660 bpp = 8*3; /* since we go through a colormap */
7661 break;
d42264b1
DV		 7662 case DRM_FORMAT_XRGB1555:
7663 case DRM_FORMAT_ARGB1555:
7664 /* checked in intel_framebuffer_init already */
7665 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7666 return -EINVAL;
7667 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7668 bpp = 6*3; /* min is 18bpp */
7669 break;
d42264b1
DV		 7670 case DRM_FORMAT_XBGR8888:
7671 case DRM_FORMAT_ABGR8888:
7672 /* checked in intel_framebuffer_init already */
7673 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7674 return -EINVAL;
7675 case DRM_FORMAT_XRGB8888:
7676 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7677 bpp = 8*3;
7678 break;
d42264b1
DV		 7679 case DRM_FORMAT_XRGB2101010:
7680 case DRM_FORMAT_ARGB2101010:
7681 case DRM_FORMAT_XBGR2101010:
7682 case DRM_FORMAT_ABGR2101010:
7683 /* checked in intel_framebuffer_init already */
7684 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7685 return -EINVAL;
4e53c2e0
DV		 7686 bpp = 10*3;
7687 break;
baba133a 7688 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7689 default:
7690 DRM_DEBUG_KMS("unsupported depth\n");
7691 return -EINVAL;
7692 }
7693
4e53c2e0
DV		 7694 pipe_config->pipe_bpp = bpp;
7695
7696 /* Clamp display bpp to EDID value */
7697 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7698 base.head) {
1b829e05
DV		 7699 if (!connector->new_encoder ||
7700 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7701 continue;
7702
050f7aeb 7703 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7704 }
7705
7706 return bpp;
7707}
7708
c0b03411
DV		 7709static void intel_dump_pipe_config(struct intel_crtc *crtc,
7710 struct intel_crtc_config *pipe_config,
7711 const char *context)
7712{
7713 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7714 context, pipe_name(crtc->pipe));
7715
7716 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7717 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7718 pipe_config->pipe_bpp, pipe_config->dither);
7719 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7720 pipe_config->has_pch_encoder,
7721 pipe_config->fdi_lanes,
7722 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7723 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7724 pipe_config->fdi_m_n.tu);
7725 DRM_DEBUG_KMS("requested mode:\n");
7726 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7727 DRM_DEBUG_KMS("adjusted mode:\n");
7728 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7729 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7730 pipe_config->gmch_pfit.control,
7731 pipe_config->gmch_pfit.pgm_ratios,
7732 pipe_config->gmch_pfit.lvds_border_bits);
7733 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7734 pipe_config->pch_pfit.pos,
7735 pipe_config->pch_pfit.size);
42db64ef 7736 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7737}
7738
accfc0c5
DV		 7739static bool check_encoder_cloning(struct drm_crtc *crtc)
7740{
7741 int num_encoders = 0;
7742 bool uncloneable_encoders = false;
7743 struct intel_encoder *encoder;
7744
7745 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7746 base.head) {
7747 if (&encoder->new_crtc->base != crtc)
7748 continue;
7749
7750 num_encoders++;
7751 if (!encoder->cloneable)
7752 uncloneable_encoders = true;
7753 }
7754
7755 return !(num_encoders > 1 && uncloneable_encoders);
7756}
7757
b8cecdf5
DV		 7758static struct intel_crtc_config *
7759intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7760 struct drm_framebuffer *fb,
b8cecdf5 7761 struct drm_display_mode *mode)
ee7b9f93 7762{
7758a113 7763 struct drm_device *dev = crtc->dev;
7758a113
DV		 7764 struct drm_encoder_helper_funcs *encoder_funcs;
7765 struct intel_encoder *encoder;
b8cecdf5 7766 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7767 int plane_bpp, ret = -EINVAL;
7768 bool retry = true;
ee7b9f93 7769
accfc0c5
DV		 7770 if (!check_encoder_cloning(crtc)) {
7771 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7772 return ERR_PTR(-EINVAL);
7773 }
7774
b8cecdf5
DV		 7775 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7776 if (!pipe_config)
7758a113
DV		 7777 return ERR_PTR(-ENOMEM);
7778
b8cecdf5
DV		 7779 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7780 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7781 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7782 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7783
050f7aeb
DV		 7784 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7785 * plane pixel format and any sink constraints into account. Returns the
7786 * source plane bpp so that dithering can be selected on mismatches
7787 * after encoders and crtc also have had their say. */
7788 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7789 fb, pipe_config);
4e53c2e0
DV		 7790 if (plane_bpp < 0)
7791 goto fail;
7792
e29c22c0 7793encoder_retry:
ef1b460d 7794 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7795 pipe_config->port_clock = 0;
ef1b460d 7796 pipe_config->pixel_multiplier = 1;
ff9a6750 7797
7758a113
DV		 7798 /* Pass our mode to the connectors and the CRTC to give them a chance to
7799 * adjust it according to limitations or connector properties, and also
7800 * a chance to reject the mode entirely.
47f1c6c9 7801 */
7758a113
DV		 7802 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7803 base.head) {
47f1c6c9 7804
7758a113
DV		 7805 if (&encoder->new_crtc->base != crtc)
7806 continue;
7ae89233
DV		 7807
7808 if (encoder->compute_config) {
7809 if (!(encoder->compute_config(encoder, pipe_config))) {
7810 DRM_DEBUG_KMS("Encoder config failure\n");
7811 goto fail;
7812 }
7813
7814 continue;
7815 }
7816
7758a113 7817 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7818 if (!(encoder_funcs->mode_fixup(&encoder->base,
7819 &pipe_config->requested_mode,
7820 &pipe_config->adjusted_mode))) {
7758a113
DV		 7821 DRM_DEBUG_KMS("Encoder fixup failed\n");
7822 goto fail;
7823 }
ee7b9f93 7824 }
47f1c6c9 7825
ff9a6750
DV		 7826 /* Set default port clock if not overwritten by the encoder. Needs to be
7827 * done afterwards in case the encoder adjusts the mode. */
7828 if (!pipe_config->port_clock)
7829 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7830
a43f6e0f 7831 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7832 if (ret < 0) {
7758a113
DV		 7833 DRM_DEBUG_KMS("CRTC fixup failed\n");
7834 goto fail;
ee7b9f93 7835 }
e29c22c0
DV		 7836
7837 if (ret == RETRY) {
7838 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7839 ret = -EINVAL;
7840 goto fail;
7841 }
7842
7843 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7844 retry = false;
7845 goto encoder_retry;
7846 }
7847
4e53c2e0
DV		 7848 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7849 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7850 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7851
b8cecdf5 7852 return pipe_config;
7758a113 7853fail:
b8cecdf5 7854 kfree(pipe_config);
e29c22c0 7855 return ERR_PTR(ret);
ee7b9f93 7856}
47f1c6c9 7857
e2e1ed41
DV		 7858/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7859 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7860static void
7861intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7862 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7863{
7864 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7865 struct drm_device *dev = crtc->dev;
7866 struct intel_encoder *encoder;
7867 struct intel_connector *connector;
7868 struct drm_crtc *tmp_crtc;
79e53945 7869
e2e1ed41 7870 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7871
e2e1ed41
DV		 7872 /* Check which crtcs have changed outputs connected to them, these need
7873 * to be part of the prepare_pipes mask. We don't (yet) support global
7874 * modeset across multiple crtcs, so modeset_pipes will only have one
7875 * bit set at most. */
7876 list_for_each_entry(connector, &dev->mode_config.connector_list,
7877 base.head) {
7878 if (connector->base.encoder == &connector->new_encoder->base)
7879 continue;
79e53945 7880
e2e1ed41
DV		 7881 if (connector->base.encoder) {
7882 tmp_crtc = connector->base.encoder->crtc;
7883
7884 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7885 }
7886
7887 if (connector->new_encoder)
7888 *prepare_pipes |=
7889 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7890 }
7891
e2e1ed41
DV		 7892 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7893 base.head) {
7894 if (encoder->base.crtc == &encoder->new_crtc->base)
7895 continue;
7896
7897 if (encoder->base.crtc) {
7898 tmp_crtc = encoder->base.crtc;
7899
7900 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7901 }
7902
7903 if (encoder->new_crtc)
7904 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7905 }
7906
e2e1ed41
DV		 7907 /* Check for any pipes that will be fully disabled ... */
7908 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7909 base.head) {
7910 bool used = false;
22fd0fab 7911
e2e1ed41
DV		 7912 /* Don't try to disable disabled crtcs. */
7913 if (!intel_crtc->base.enabled)
7914 continue;
7e7d76c3 7915
e2e1ed41
DV		 7916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7917 base.head) {
7918 if (encoder->new_crtc == intel_crtc)
7919 used = true;
7920 }
7921
7922 if (!used)
7923 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7924 }
7925
e2e1ed41
DV		 7926
7927 /* set_mode is also used to update properties on life display pipes. */
7928 intel_crtc = to_intel_crtc(crtc);
7929 if (crtc->enabled)
7930 *prepare_pipes |= 1 << intel_crtc->pipe;
7931
b6c5164d
DV		 7932 /*
7933 * For simplicity do a full modeset on any pipe where the output routing
7934 * changed. We could be more clever, but that would require us to be
7935 * more careful with calling the relevant encoder->mode_set functions.
7936 */
e2e1ed41
DV		 7937 if (*prepare_pipes)
7938 *modeset_pipes = *prepare_pipes;
7939
7940 /* ... and mask these out. */
7941 *modeset_pipes &= ~(*disable_pipes);
7942 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7943
7944 /*
7945 * HACK: We don't (yet) fully support global modesets. intel_set_config
7946 * obies this rule, but the modeset restore mode of
7947 * intel_modeset_setup_hw_state does not.
7948 */
7949 *modeset_pipes &= 1 << intel_crtc->pipe;
7950 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7951
7952 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7953 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7954}
79e53945 7955
ea9d758d 7956static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7957{
ea9d758d 7958 struct drm_encoder *encoder;
f6e5b160 7959 struct drm_device *dev = crtc->dev;
f6e5b160 7960
ea9d758d
DV		 7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7962 if (encoder->crtc == crtc)
7963 return true;
7964
7965 return false;
7966}
7967
7968static void
7969intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7970{
7971 struct intel_encoder *intel_encoder;
7972 struct intel_crtc *intel_crtc;
7973 struct drm_connector *connector;
7974
7975 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7976 base.head) {
7977 if (!intel_encoder->base.crtc)
7978 continue;
7979
7980 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7981
7982 if (prepare_pipes & (1 << intel_crtc->pipe))
7983 intel_encoder->connectors_active = false;
7984 }
7985
7986 intel_modeset_commit_output_state(dev);
7987
7988 /* Update computed state. */
7989 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7990 base.head) {
7991 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7992 }
7993
7994 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7995 if (!connector->encoder || !connector->encoder->crtc)
7996 continue;
7997
7998 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7999
8000 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8001 struct drm_property *dpms_property =
8002 dev->mode_config.dpms_property;
8003
ea9d758d 8004 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8005 drm_object_property_set_value(&connector->base,
68d34720
DV		 8006 dpms_property,
8007 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8008
8009 intel_encoder = to_intel_encoder(connector->encoder);
8010 intel_encoder->connectors_active = true;
8011 }
8012 }
8013
8014}
8015
25c5b266
DV		 8016#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8017 list_for_each_entry((intel_crtc), \
8018 &(dev)->mode_config.crtc_list, \
8019 base.head) \
0973f18f 8020 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8021
0e8ffe1b 8022static bool
2fa2fe9a
DV		 8023intel_pipe_config_compare(struct drm_device *dev,
8024 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8025 struct intel_crtc_config *pipe_config)
8026{
66e985c0
DV		 8027#define PIPE_CONF_CHECK_X(name) \
8028 if (current_config->name != pipe_config->name) { \
8029 DRM_ERROR("mismatch in " #name " " \
8030 "(expected 0x%08x, found 0x%08x)\n", \
8031 current_config->name, \
8032 pipe_config->name); \
8033 return false; \
8034 }
8035
08a24034
DV		 8036#define PIPE_CONF_CHECK_I(name) \
8037 if (current_config->name != pipe_config->name) { \
8038 DRM_ERROR("mismatch in " #name " " \
8039 "(expected %i, found %i)\n", \
8040 current_config->name, \
8041 pipe_config->name); \
8042 return false; \
88adfff1
DV		 8043 }
8044
1bd1bd80
DV		 8045#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8046 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8047 DRM_ERROR("mismatch in " #name " " \
8048 "(expected %i, found %i)\n", \
8049 current_config->name & (mask), \
8050 pipe_config->name & (mask)); \
8051 return false; \
8052 }
8053
bb760063
DV		 8054#define PIPE_CONF_QUIRK(quirk) \
8055 ((current_config->quirks | pipe_config->quirks) & (quirk))
8056
eccb140b
DV		 8057 PIPE_CONF_CHECK_I(cpu_transcoder);
8058
08a24034
DV		 8059 PIPE_CONF_CHECK_I(has_pch_encoder);
8060 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8061 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8062 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8063 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8064 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8065 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8066
1bd1bd80
DV		 8067 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8068 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8069 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8070 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8071 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8072 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8073
8074 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8075 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8076 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8077 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8078 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8079 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8080
6c49f241
DV		 8081 if (!HAS_PCH_SPLIT(dev))
8082 PIPE_CONF_CHECK_I(pixel_multiplier);
8083
1bd1bd80
DV		 8084 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8085 DRM_MODE_FLAG_INTERLACE);
8086
bb760063
DV		 8087 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8088 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8089 DRM_MODE_FLAG_PHSYNC);
8090 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8091 DRM_MODE_FLAG_NHSYNC);
8092 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8093 DRM_MODE_FLAG_PVSYNC);
8094 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8095 DRM_MODE_FLAG_NVSYNC);
8096 }
045ac3b5 8097
1bd1bd80
DV		 8098 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8099 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8100
2fa2fe9a
DV		 8101 PIPE_CONF_CHECK_I(gmch_pfit.control);
8102 /* pfit ratios are autocomputed by the hw on gen4+ */
8103 if (INTEL_INFO(dev)->gen < 4)
8104 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8105 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8106 PIPE_CONF_CHECK_I(pch_pfit.pos);
8107 PIPE_CONF_CHECK_I(pch_pfit.size);
8108
42db64ef
PZ		 8109 PIPE_CONF_CHECK_I(ips_enabled);
8110
c0d43d62 8111 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0
DV		 8112 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8113 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8114 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8115
66e985c0 8116#undef PIPE_CONF_CHECK_X
08a24034 8117#undef PIPE_CONF_CHECK_I
1bd1bd80 8118#undef PIPE_CONF_CHECK_FLAGS
bb760063 8119#undef PIPE_CONF_QUIRK
88adfff1 8120
0e8ffe1b
DV		 8121 return true;
8122}
8123
91d1b4bd
DV		 8124static void
8125check_connector_state(struct drm_device *dev)
8af6cf88 8126{
8af6cf88
DV		 8127 struct intel_connector *connector;
8128
8129 list_for_each_entry(connector, &dev->mode_config.connector_list,
8130 base.head) {
8131 /* This also checks the encoder/connector hw state with the
8132 * ->get_hw_state callbacks. */
8133 intel_connector_check_state(connector);
8134
8135 WARN(&connector->new_encoder->base != connector->base.encoder,
8136 "connector's staged encoder doesn't match current encoder\n");
8137 }
91d1b4bd
DV		 8138}
8139
8140static void
8141check_encoder_state(struct drm_device *dev)
8142{
8143 struct intel_encoder *encoder;
8144 struct intel_connector *connector;
8af6cf88
DV		 8145
8146 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8147 base.head) {
8148 bool enabled = false;
8149 bool active = false;
8150 enum pipe pipe, tracked_pipe;
8151
8152 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8153 encoder->base.base.id,
8154 drm_get_encoder_name(&encoder->base));
8155
8156 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8157 "encoder's stage crtc doesn't match current crtc\n");
8158 WARN(encoder->connectors_active && !encoder->base.crtc,
8159 "encoder's active_connectors set, but no crtc\n");
8160
8161 list_for_each_entry(connector, &dev->mode_config.connector_list,
8162 base.head) {
8163 if (connector->base.encoder != &encoder->base)
8164 continue;
8165 enabled = true;
8166 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8167 active = true;
8168 }
8169 WARN(!!encoder->base.crtc != enabled,
8170 "encoder's enabled state mismatch "
8171 "(expected %i, found %i)\n",
8172 !!encoder->base.crtc, enabled);
8173 WARN(active && !encoder->base.crtc,
8174 "active encoder with no crtc\n");
8175
8176 WARN(encoder->connectors_active != active,
8177 "encoder's computed active state doesn't match tracked active state "
8178 "(expected %i, found %i)\n", active, encoder->connectors_active);
8179
8180 active = encoder->get_hw_state(encoder, &pipe);
8181 WARN(active != encoder->connectors_active,
8182 "encoder's hw state doesn't match sw tracking "
8183 "(expected %i, found %i)\n",
8184 encoder->connectors_active, active);
8185
8186 if (!encoder->base.crtc)
8187 continue;
8188
8189 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8190 WARN(active && pipe != tracked_pipe,
8191 "active encoder's pipe doesn't match"
8192 "(expected %i, found %i)\n",
8193 tracked_pipe, pipe);
8194
8195 }
91d1b4bd
DV		 8196}
8197
8198static void
8199check_crtc_state(struct drm_device *dev)
8200{
8201 drm_i915_private_t *dev_priv = dev->dev_private;
8202 struct intel_crtc *crtc;
8203 struct intel_encoder *encoder;
8204 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8205
8206 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8207 base.head) {
8208 bool enabled = false;
8209 bool active = false;
8210
045ac3b5
JB		 8211 memset(&pipe_config, 0, sizeof(pipe_config));
8212
8af6cf88
DV		 8213 DRM_DEBUG_KMS("[CRTC:%d]\n",
8214 crtc->base.base.id);
8215
8216 WARN(crtc->active && !crtc->base.enabled,
8217 "active crtc, but not enabled in sw tracking\n");
8218
8219 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8220 base.head) {
8221 if (encoder->base.crtc != &crtc->base)
8222 continue;
8223 enabled = true;
8224 if (encoder->connectors_active)
8225 active = true;
8226 }
6c49f241 8227
8af6cf88
DV		 8228 WARN(active != crtc->active,
8229 "crtc's computed active state doesn't match tracked active state "
8230 "(expected %i, found %i)\n", active, crtc->active);
8231 WARN(enabled != crtc->base.enabled,
8232 "crtc's computed enabled state doesn't match tracked enabled state "
8233 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8234
0e8ffe1b
DV		 8235 active = dev_priv->display.get_pipe_config(crtc,
8236 &pipe_config);
d62cf62a
DV		 8237
8238 /* hw state is inconsistent with the pipe A quirk */
8239 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8240 active = crtc->active;
8241
6c49f241
DV		 8242 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8243 base.head) {
8244 if (encoder->base.crtc != &crtc->base)
8245 continue;
8246 if (encoder->get_config)
8247 encoder->get_config(encoder, &pipe_config);
8248 }
8249
0e8ffe1b
DV		 8250 WARN(crtc->active != active,
8251 "crtc active state doesn't match with hw state "
8252 "(expected %i, found %i)\n", crtc->active, active);
8253
c0b03411
DV		 8254 if (active &&
8255 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8256 WARN(1, "pipe state doesn't match!\n");
8257 intel_dump_pipe_config(crtc, &pipe_config,
8258 "[hw state]");
8259 intel_dump_pipe_config(crtc, &crtc->config,
8260 "[sw state]");
8261 }
8af6cf88
DV		 8262 }
8263}
8264
91d1b4bd
DV		 8265static void
8266check_shared_dpll_state(struct drm_device *dev)
8267{
8268 drm_i915_private_t *dev_priv = dev->dev_private;
8269 struct intel_crtc *crtc;
8270 struct intel_dpll_hw_state dpll_hw_state;
8271 int i;
5358901f
DV		 8272
8273 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8274 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8275 int enabled_crtcs = 0, active_crtcs = 0;
8276 bool active;
8277
8278 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8279
8280 DRM_DEBUG_KMS("%s\n", pll->name);
8281
8282 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8283
8284 WARN(pll->active > pll->refcount,
8285 "more active pll users than references: %i vs %i\n",
8286 pll->active, pll->refcount);
8287 WARN(pll->active && !pll->on,
8288 "pll in active use but not on in sw tracking\n");
8289 WARN(pll->on != active,
8290 "pll on state mismatch (expected %i, found %i)\n",
8291 pll->on, active);
8292
8293 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8294 base.head) {
8295 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8296 enabled_crtcs++;
8297 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8298 active_crtcs++;
8299 }
8300 WARN(pll->active != active_crtcs,
8301 "pll active crtcs mismatch (expected %i, found %i)\n",
8302 pll->active, active_crtcs);
8303 WARN(pll->refcount != enabled_crtcs,
8304 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8305 pll->refcount, enabled_crtcs);
66e985c0
DV		 8306
8307 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8308 sizeof(dpll_hw_state)),
8309 "pll hw state mismatch\n");
5358901f 8310 }
8af6cf88
DV		 8311}
8312
91d1b4bd
DV		 8313void
8314intel_modeset_check_state(struct drm_device *dev)
8315{
8316 check_connector_state(dev);
8317 check_encoder_state(dev);
8318 check_crtc_state(dev);
8319 check_shared_dpll_state(dev);
8320}
8321
f30da187
DV		 8322static int __intel_set_mode(struct drm_crtc *crtc,
8323 struct drm_display_mode *mode,
8324 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8325{
8326 struct drm_device *dev = crtc->dev;
dbf2b54e 8327 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8328 struct drm_display_mode *saved_mode, *saved_hwmode;
8329 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8330 struct intel_crtc *intel_crtc;
8331 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8332 int ret = 0;
a6778b3c 8333
3ac18232 8334 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8335 if (!saved_mode)
8336 return -ENOMEM;
3ac18232 8337 saved_hwmode = saved_mode + 1;
a6778b3c 8338
e2e1ed41 8339 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8340 &prepare_pipes, &disable_pipes);
8341
3ac18232
TG		 8342 *saved_hwmode = crtc->hwmode;
8343 *saved_mode = crtc->mode;
a6778b3c 8344
25c5b266
DV		 8345 /* Hack: Because we don't (yet) support global modeset on multiple
8346 * crtcs, we don't keep track of the new mode for more than one crtc.
8347 * Hence simply check whether any bit is set in modeset_pipes in all the
8348 * pieces of code that are not yet converted to deal with mutliple crtcs
8349 * changing their mode at the same time. */
25c5b266 8350 if (modeset_pipes) {
4e53c2e0 8351 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8352 if (IS_ERR(pipe_config)) {
8353 ret = PTR_ERR(pipe_config);
8354 pipe_config = NULL;
8355
3ac18232 8356 goto out;
25c5b266 8357 }
c0b03411
DV		 8358 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8359 "[modeset]");
25c5b266 8360 }
a6778b3c 8361
460da916
DV		 8362 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8363 intel_crtc_disable(&intel_crtc->base);
8364
ea9d758d
DV		 8365 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8366 if (intel_crtc->base.enabled)
8367 dev_priv->display.crtc_disable(&intel_crtc->base);
8368 }
a6778b3c 8369
6c4c86f5
DV		 8370 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8371 * to set it here already despite that we pass it down the callchain.
f6e5b160 8372 */
b8cecdf5 8373 if (modeset_pipes) {
25c5b266 8374 crtc->mode = *mode;
b8cecdf5
DV		 8375 /* mode_set/enable/disable functions rely on a correct pipe
8376 * config. */
8377 to_intel_crtc(crtc)->config = *pipe_config;
8378 }
7758a113 8379
ea9d758d
DV		 8380 /* Only after disabling all output pipelines that will be changed can we
8381 * update the the output configuration. */
8382 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8383
47fab737
DV		 8384 if (dev_priv->display.modeset_global_resources)
8385 dev_priv->display.modeset_global_resources(dev);
8386
a6778b3c
DV		 8387 /* Set up the DPLL and any encoders state that needs to adjust or depend
8388 * on the DPLL.
f6e5b160 8389 */
25c5b266 8390 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8391 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8392 x, y, fb);
8393 if (ret)
8394 goto done;
a6778b3c
DV		 8395 }
8396
8397 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8398 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8399 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8400
25c5b266
DV		 8401 if (modeset_pipes) {
8402 /* Store real post-adjustment hardware mode. */
b8cecdf5 8403 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8404
25c5b266
DV		 8405 /* Calculate and store various constants which
8406 * are later needed by vblank and swap-completion
8407 * timestamping. They are derived from true hwmode.
8408 */
8409 drm_calc_timestamping_constants(crtc);
8410 }
a6778b3c
DV		 8411
8412 /* FIXME: add subpixel order */
8413done:
c0c36b94 8414 if (ret && crtc->enabled) {
3ac18232
TG		 8415 crtc->hwmode = *saved_hwmode;
8416 crtc->mode = *saved_mode;
a6778b3c
DV		 8417 }
8418
3ac18232 8419out:
b8cecdf5 8420 kfree(pipe_config);
3ac18232 8421 kfree(saved_mode);
a6778b3c 8422 return ret;
f6e5b160
CW		 8423}
8424
f30da187
DV		 8425int intel_set_mode(struct drm_crtc *crtc,
8426 struct drm_display_mode *mode,
8427 int x, int y, struct drm_framebuffer *fb)
8428{
8429 int ret;
8430
8431 ret = __intel_set_mode(crtc, mode, x, y, fb);
8432
8433 if (ret == 0)
8434 intel_modeset_check_state(crtc->dev);
8435
8436 return ret;
8437}
8438
c0c36b94
CW		 8439void intel_crtc_restore_mode(struct drm_crtc *crtc)
8440{
8441 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8442}
8443
25c5b266
DV		 8444#undef for_each_intel_crtc_masked
8445
d9e55608
DV		 8446static void intel_set_config_free(struct intel_set_config *config)
8447{
8448 if (!config)
8449 return;
8450
1aa4b628
DV		 8451 kfree(config->save_connector_encoders);
8452 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8453 kfree(config);
8454}
8455
85f9eb71
DV		 8456static int intel_set_config_save_state(struct drm_device *dev,
8457 struct intel_set_config *config)
8458{
85f9eb71
DV		 8459 struct drm_encoder *encoder;
8460 struct drm_connector *connector;
8461 int count;
8462
1aa4b628
DV		 8463 config->save_encoder_crtcs =
8464 kcalloc(dev->mode_config.num_encoder,
8465 sizeof(struct drm_crtc *), GFP_KERNEL);
8466 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8467 return -ENOMEM;
8468
1aa4b628
DV		 8469 config->save_connector_encoders =
8470 kcalloc(dev->mode_config.num_connector,
8471 sizeof(struct drm_encoder *), GFP_KERNEL);
8472 if (!config->save_connector_encoders)
85f9eb71
DV		 8473 return -ENOMEM;
8474
8475 /* Copy data. Note that driver private data is not affected.
8476 * Should anything bad happen only the expected state is
8477 * restored, not the drivers personal bookkeeping.
8478 */
85f9eb71
DV		 8479 count = 0;
8480 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8481 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8482 }
8483
8484 count = 0;
8485 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8486 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8487 }
8488
8489 return 0;
8490}
8491
8492static void intel_set_config_restore_state(struct drm_device *dev,
8493 struct intel_set_config *config)
8494{
9a935856
DV		 8495 struct intel_encoder *encoder;
8496 struct intel_connector *connector;
85f9eb71
DV		 8497 int count;
8498
85f9eb71 8499 count = 0;
9a935856
DV		 8500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8501 encoder->new_crtc =
8502 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8503 }
8504
8505 count = 0;
9a935856
DV		 8506 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8507 connector->new_encoder =
8508 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8509 }
8510}
8511
e3de42b6
ID		 8512static bool
8513is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8514 int num_connectors)
8515{
8516 int i;
8517
8518 for (i = 0; i < num_connectors; i++)
8519 if (connectors[i].encoder &&
8520 connectors[i].encoder->crtc == crtc &&
8521 connectors[i].dpms != DRM_MODE_DPMS_ON)
8522 return true;
8523
8524 return false;
8525}
8526
5e2b584e
DV		 8527static void
8528intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8529 struct intel_set_config *config)
8530{
8531
8532 /* We should be able to check here if the fb has the same properties
8533 * and then just flip_or_move it */
e3de42b6
ID		 8534 if (set->connectors != NULL &&
8535 is_crtc_connector_off(set->crtc, *set->connectors,
8536 set->num_connectors)) {
8537 config->mode_changed = true;
8538 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8539 /* If we have no fb then treat it as a full mode set */
8540 if (set->crtc->fb == NULL) {
8541 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8542 config->mode_changed = true;
8543 } else if (set->fb == NULL) {
8544 config->mode_changed = true;
72f4901e
DV		 8545 } else if (set->fb->pixel_format !=
8546 set->crtc->fb->pixel_format) {
5e2b584e 8547 config->mode_changed = true;
e3de42b6 8548 } else {
5e2b584e 8549 config->fb_changed = true;
e3de42b6 8550 }
5e2b584e
DV		 8551 }
8552
835c5873 8553 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8554 config->fb_changed = true;
8555
8556 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8557 DRM_DEBUG_KMS("modes are different, full mode set\n");
8558 drm_mode_debug_printmodeline(&set->crtc->mode);
8559 drm_mode_debug_printmodeline(set->mode);
8560 config->mode_changed = true;
8561 }
8562}
8563
2e431051 8564static int
9a935856
DV		 8565intel_modeset_stage_output_state(struct drm_device *dev,
8566 struct drm_mode_set *set,
8567 struct intel_set_config *config)
50f56119 8568{
85f9eb71 8569 struct drm_crtc *new_crtc;
9a935856
DV		 8570 struct intel_connector *connector;
8571 struct intel_encoder *encoder;
2e431051 8572 int count, ro;
50f56119 8573
9abdda74 8574 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8575 * of connectors. For paranoia, double-check this. */
8576 WARN_ON(!set->fb && (set->num_connectors != 0));
8577 WARN_ON(set->fb && (set->num_connectors == 0));
8578
50f56119 8579 count = 0;
9a935856
DV		 8580 list_for_each_entry(connector, &dev->mode_config.connector_list,
8581 base.head) {
8582 /* Otherwise traverse passed in connector list and get encoders
8583 * for them. */
50f56119 8584 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8585 if (set->connectors[ro] == &connector->base) {
8586 connector->new_encoder = connector->encoder;
50f56119
DV		 8587 break;
8588 }
8589 }
8590
9a935856
DV		 8591 /* If we disable the crtc, disable all its connectors. Also, if
8592 * the connector is on the changing crtc but not on the new
8593 * connector list, disable it. */
8594 if ((!set->fb || ro == set->num_connectors) &&
8595 connector->base.encoder &&
8596 connector->base.encoder->crtc == set->crtc) {
8597 connector->new_encoder = NULL;
8598
8599 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8600 connector->base.base.id,
8601 drm_get_connector_name(&connector->base));
8602 }
8603
8604
8605 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8606 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8607 config->mode_changed = true;
50f56119
DV		 8608 }
8609 }
9a935856 8610 /* connector->new_encoder is now updated for all connectors. */
50f56119 8611
9a935856 8612 /* Update crtc of enabled connectors. */
50f56119 8613 count = 0;
9a935856
DV		 8614 list_for_each_entry(connector, &dev->mode_config.connector_list,
8615 base.head) {
8616 if (!connector->new_encoder)
50f56119
DV		 8617 continue;
8618
9a935856 8619 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8620
8621 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8622 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8623 new_crtc = set->crtc;
8624 }
8625
8626 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8627 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8628 new_crtc)) {
5e2b584e 8629 return -EINVAL;
50f56119 8630 }
9a935856
DV		 8631 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8632
8633 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8634 connector->base.base.id,
8635 drm_get_connector_name(&connector->base),
8636 new_crtc->base.id);
8637 }
8638
8639 /* Check for any encoders that needs to be disabled. */
8640 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8641 base.head) {
8642 list_for_each_entry(connector,
8643 &dev->mode_config.connector_list,
8644 base.head) {
8645 if (connector->new_encoder == encoder) {
8646 WARN_ON(!connector->new_encoder->new_crtc);
8647
8648 goto next_encoder;
8649 }
8650 }
8651 encoder->new_crtc = NULL;
8652next_encoder:
8653 /* Only now check for crtc changes so we don't miss encoders
8654 * that will be disabled. */
8655 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8656 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8657 config->mode_changed = true;
50f56119
DV		 8658 }
8659 }
9a935856 8660 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8661
2e431051
DV		 8662 return 0;
8663}
8664
8665static int intel_crtc_set_config(struct drm_mode_set *set)
8666{
8667 struct drm_device *dev;
2e431051
DV		 8668 struct drm_mode_set save_set;
8669 struct intel_set_config *config;
8670 int ret;
2e431051 8671
8d3e375e
DV		 8672 BUG_ON(!set);
8673 BUG_ON(!set->crtc);
8674 BUG_ON(!set->crtc->helper_private);
2e431051 8675
7e53f3a4
DV		 8676 /* Enforce sane interface api - has been abused by the fb helper. */
8677 BUG_ON(!set->mode && set->fb);
8678 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8679
2e431051
DV		 8680 if (set->fb) {
8681 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8682 set->crtc->base.id, set->fb->base.id,
8683 (int)set->num_connectors, set->x, set->y);
8684 } else {
8685 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8686 }
8687
8688 dev = set->crtc->dev;
8689
8690 ret = -ENOMEM;
8691 config = kzalloc(sizeof(*config), GFP_KERNEL);
8692 if (!config)
8693 goto out_config;
8694
8695 ret = intel_set_config_save_state(dev, config);
8696 if (ret)
8697 goto out_config;
8698
8699 save_set.crtc = set->crtc;
8700 save_set.mode = &set->crtc->mode;
8701 save_set.x = set->crtc->x;
8702 save_set.y = set->crtc->y;
8703 save_set.fb = set->crtc->fb;
8704
8705 /* Compute whether we need a full modeset, only an fb base update or no
8706 * change at all. In the future we might also check whether only the
8707 * mode changed, e.g. for LVDS where we only change the panel fitter in
8708 * such cases. */
8709 intel_set_config_compute_mode_changes(set, config);
8710
9a935856 8711 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8712 if (ret)
8713 goto fail;
8714
5e2b584e 8715 if (config->mode_changed) {
c0c36b94
CW		 8716 ret = intel_set_mode(set->crtc, set->mode,
8717 set->x, set->y, set->fb);
5e2b584e 8718 } else if (config->fb_changed) {
4878cae2
VS		 8719 intel_crtc_wait_for_pending_flips(set->crtc);
8720
4f660f49 8721 ret = intel_pipe_set_base(set->crtc,
94352cf9 8722 set->x, set->y, set->fb);
50f56119
DV		 8723 }
8724
2d05eae1 8725 if (ret) {
bf67dfeb
DV		 8726 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8727 set->crtc->base.id, ret);
50f56119 8728fail:
2d05eae1 8729 intel_set_config_restore_state(dev, config);
50f56119 8730
2d05eae1
CW		 8731 /* Try to restore the config */
8732 if (config->mode_changed &&
8733 intel_set_mode(save_set.crtc, save_set.mode,
8734 save_set.x, save_set.y, save_set.fb))
8735 DRM_ERROR("failed to restore config after modeset failure\n");
8736 }
50f56119 8737
d9e55608
DV		 8738out_config:
8739 intel_set_config_free(config);
50f56119
DV		 8740 return ret;
8741}
f6e5b160
CW		 8742
8743static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8744 .cursor_set = intel_crtc_cursor_set,
8745 .cursor_move = intel_crtc_cursor_move,
8746 .gamma_set = intel_crtc_gamma_set,
50f56119 8747 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8748 .destroy = intel_crtc_destroy,
8749 .page_flip = intel_crtc_page_flip,
8750};
8751
79f689aa
PZ		 8752static void intel_cpu_pll_init(struct drm_device *dev)
8753{
affa9354 8754 if (HAS_DDI(dev))
79f689aa
PZ		 8755 intel_ddi_pll_init(dev);
8756}
8757
5358901f
DV		 8758static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8759 struct intel_shared_dpll *pll,
8760 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8761{
5358901f 8762 uint32_t val;
ee7b9f93 8763
5358901f 8764 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8765 hw_state->dpll = val;
8766 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8767 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8768
8769 return val & DPLL_VCO_ENABLE;
8770}
8771
15bdd4cf
DV		 8772static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8773 struct intel_shared_dpll *pll)
8774{
8775 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8776 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8777}
8778
e7b903d2
DV		 8779static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8780 struct intel_shared_dpll *pll)
8781{
e7b903d2
DV		 8782 /* PCH refclock must be enabled first */
8783 assert_pch_refclk_enabled(dev_priv);
8784
15bdd4cf
DV		 8785 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8786
8787 /* Wait for the clocks to stabilize. */
8788 POSTING_READ(PCH_DPLL(pll->id));
8789 udelay(150);
8790
8791 /* The pixel multiplier can only be updated once the
8792 * DPLL is enabled and the clocks are stable.
8793 *
8794 * So write it again.
8795 */
8796 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8797 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8798 udelay(200);
8799}
8800
8801static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8802 struct intel_shared_dpll *pll)
8803{
8804 struct drm_device *dev = dev_priv->dev;
8805 struct intel_crtc *crtc;
e7b903d2
DV		 8806
8807 /* Make sure no transcoder isn't still depending on us. */
8808 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8809 if (intel_crtc_to_shared_dpll(crtc) == pll)
8810 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8811 }
8812
15bdd4cf
DV		 8813 I915_WRITE(PCH_DPLL(pll->id), 0);
8814 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8815 udelay(200);
8816}
8817
46edb027
DV		 8818static char *ibx_pch_dpll_names[] = {
8819 "PCH DPLL A",
8820 "PCH DPLL B",
8821};
8822
7c74ade1 8823static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8824{
e7b903d2 8825 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8826 int i;
8827
7c74ade1 8828 dev_priv->num_shared_dpll = 2;
ee7b9f93 8829
e72f9fbf 8830 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8831 dev_priv->shared_dplls[i].id = i;
8832 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8833 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8834 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8835 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8836 dev_priv->shared_dplls[i].get_hw_state =
8837 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8838 }
8839}
8840
7c74ade1
DV		 8841static void intel_shared_dpll_init(struct drm_device *dev)
8842{
e7b903d2 8843 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8844
8845 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8846 ibx_pch_dpll_init(dev);
8847 else
8848 dev_priv->num_shared_dpll = 0;
8849
8850 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8851 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8852 dev_priv->num_shared_dpll);
8853}
8854
b358d0a6 8855static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8856{
22fd0fab 8857 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8858 struct intel_crtc *intel_crtc;
8859 int i;
8860
8861 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8862 if (intel_crtc == NULL)
8863 return;
8864
8865 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8866
8867 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8868 for (i = 0; i < 256; i++) {
8869 intel_crtc->lut_r[i] = i;
8870 intel_crtc->lut_g[i] = i;
8871 intel_crtc->lut_b[i] = i;
8872 }
8873
80824003
JB		 8874 /* Swap pipes & planes for FBC on pre-965 */
8875 intel_crtc->pipe = pipe;
8876 intel_crtc->plane = pipe;
e2e767ab 8877 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8878 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8879 intel_crtc->plane = !pipe;
80824003
JB		 8880 }
8881
22fd0fab
JB		 8882 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8883 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8884 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8885 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8886
79e53945 8887 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8888}
8889
08d7b3d1 8890int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8891 struct drm_file *file)
08d7b3d1 8892{
08d7b3d1 8893 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8894 struct drm_mode_object *drmmode_obj;
8895 struct intel_crtc *crtc;
08d7b3d1 8896
1cff8f6b
DV		 8897 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8898 return -ENODEV;
08d7b3d1 8899
c05422d5
DV		 8900 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8901 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8902
c05422d5 8903 if (!drmmode_obj) {
08d7b3d1
CW		 8904 DRM_ERROR("no such CRTC id\n");
8905 return -EINVAL;
8906 }
8907
c05422d5
DV		 8908 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8909 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8910
c05422d5 8911 return 0;
08d7b3d1
CW		 8912}
8913
66a9278e 8914static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8915{
66a9278e
DV		 8916 struct drm_device *dev = encoder->base.dev;
8917 struct intel_encoder *source_encoder;
79e53945 8918 int index_mask = 0;
79e53945
JB		 8919 int entry = 0;
8920
66a9278e
DV		 8921 list_for_each_entry(source_encoder,
8922 &dev->mode_config.encoder_list, base.head) {
8923
8924 if (encoder == source_encoder)
79e53945 8925 index_mask |= (1 << entry);
66a9278e
DV		 8926
8927 /* Intel hw has only one MUX where enocoders could be cloned. */
8928 if (encoder->cloneable && source_encoder->cloneable)
8929 index_mask |= (1 << entry);
8930
79e53945
JB		 8931 entry++;
8932 }
4ef69c7a 8933
79e53945
JB		 8934 return index_mask;
8935}
8936
4d302442
CW		 8937static bool has_edp_a(struct drm_device *dev)
8938{
8939 struct drm_i915_private *dev_priv = dev->dev_private;
8940
8941 if (!IS_MOBILE(dev))
8942 return false;
8943
8944 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8945 return false;
8946
8947 if (IS_GEN5(dev) &&
8948 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8949 return false;
8950
8951 return true;
8952}
8953
79e53945
JB		 8954static void intel_setup_outputs(struct drm_device *dev)
8955{
725e30ad 8956 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8957 struct intel_encoder *encoder;
cb0953d7 8958 bool dpd_is_edp = false;
79e53945 8959
c9093354 8960 intel_lvds_init(dev);
79e53945 8961
c40c0f5b 8962 if (!IS_ULT(dev))
79935fca 8963 intel_crt_init(dev);
cb0953d7 8964
affa9354 8965 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8966 int found;
8967
8968 /* Haswell uses DDI functions to detect digital outputs */
8969 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8970 /* DDI A only supports eDP */
8971 if (found)
8972 intel_ddi_init(dev, PORT_A);
8973
8974 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8975 * register */
8976 found = I915_READ(SFUSE_STRAP);
8977
8978 if (found & SFUSE_STRAP_DDIB_DETECTED)
8979 intel_ddi_init(dev, PORT_B);
8980 if (found & SFUSE_STRAP_DDIC_DETECTED)
8981 intel_ddi_init(dev, PORT_C);
8982 if (found & SFUSE_STRAP_DDID_DETECTED)
8983 intel_ddi_init(dev, PORT_D);
8984 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8985 int found;
270b3042
DV		 8986 dpd_is_edp = intel_dpd_is_edp(dev);
8987
8988 if (has_edp_a(dev))
8989 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8990
dc0fa718 8991 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8992 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8993 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8994 if (!found)
e2debe91 8995 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8996 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8997 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8998 }
8999
dc0fa718 9000 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9001 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9002
dc0fa718 9003 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9004 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9005
5eb08b69 9006 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9007 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9008
270b3042 9009 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9010 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9011 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9012 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9013 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9014 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9015
dc0fa718 9016 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9017 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9018 PORT_B);
67cfc203
VS		 9019 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9020 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9021 }
103a196f 9022 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9023 bool found = false;
7d57382e 9024
e2debe91 9025 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9026 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9027 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9028 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9029 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9030 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9031 }
27185ae1 9032
e7281eab 9033 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9034 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9035 }
13520b05
KH		 9036
9037 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9038
e2debe91 9039 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9040 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9041 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9042 }
27185ae1 9043
e2debe91 9044 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9045
b01f2c3a
JB		 9046 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9047 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9048 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9049 }
e7281eab 9050 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9051 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9052 }
27185ae1 9053
b01f2c3a 9054 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9055 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9056 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9057 } else if (IS_GEN2(dev))
79e53945
JB		 9058 intel_dvo_init(dev);
9059
103a196f 9060 if (SUPPORTS_TV(dev))
79e53945
JB		 9061 intel_tv_init(dev);
9062
4ef69c7a
CW		 9063 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9064 encoder->base.possible_crtcs = encoder->crtc_mask;
9065 encoder->base.possible_clones =
66a9278e 9066 intel_encoder_clones(encoder);
79e53945 9067 }
47356eb6 9068
dde86e2d 9069 intel_init_pch_refclk(dev);
270b3042
DV		 9070
9071 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9072}
9073
9074static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9075{
9076 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9077
9078 drm_framebuffer_cleanup(fb);
05394f39 9079 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9080
9081 kfree(intel_fb);
9082}
9083
9084static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9085 struct drm_file *file,
79e53945
JB		 9086 unsigned int *handle)
9087{
9088 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9089 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9090
05394f39 9091 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9092}
9093
9094static const struct drm_framebuffer_funcs intel_fb_funcs = {
9095 .destroy = intel_user_framebuffer_destroy,
9096 .create_handle = intel_user_framebuffer_create_handle,
9097};
9098
38651674
DA		 9099int intel_framebuffer_init(struct drm_device *dev,
9100 struct intel_framebuffer *intel_fb,
308e5bcb 9101 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9102 struct drm_i915_gem_object *obj)
79e53945 9103{
a35cdaa0 9104 int pitch_limit;
79e53945
JB		 9105 int ret;
9106
c16ed4be
CW		 9107 if (obj->tiling_mode == I915_TILING_Y) {
9108 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9109 return -EINVAL;
c16ed4be 9110 }
57cd6508 9111
c16ed4be
CW		 9112 if (mode_cmd->pitches[0] & 63) {
9113 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9114 mode_cmd->pitches[0]);
57cd6508 9115 return -EINVAL;
c16ed4be 9116 }
57cd6508 9117
a35cdaa0
CW		 9118 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9119 pitch_limit = 32*1024;
9120 } else if (INTEL_INFO(dev)->gen >= 4) {
9121 if (obj->tiling_mode)
9122 pitch_limit = 16*1024;
9123 else
9124 pitch_limit = 32*1024;
9125 } else if (INTEL_INFO(dev)->gen >= 3) {
9126 if (obj->tiling_mode)
9127 pitch_limit = 8*1024;
9128 else
9129 pitch_limit = 16*1024;
9130 } else
9131 /* XXX DSPC is limited to 4k tiled */
9132 pitch_limit = 8*1024;
9133
9134 if (mode_cmd->pitches[0] > pitch_limit) {
9135 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9136 obj->tiling_mode ? "tiled" : "linear",
9137 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9138 return -EINVAL;
c16ed4be 9139 }
5d7bd705
VS		 9140
9141 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9142 mode_cmd->pitches[0] != obj->stride) {
9143 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9144 mode_cmd->pitches[0], obj->stride);
5d7bd705 9145 return -EINVAL;
c16ed4be 9146 }
5d7bd705 9147
57779d06 9148 /* Reject formats not supported by any plane early. */
308e5bcb 9149 switch (mode_cmd->pixel_format) {
57779d06 9150 case DRM_FORMAT_C8:
04b3924d
VS		 9151 case DRM_FORMAT_RGB565:
9152 case DRM_FORMAT_XRGB8888:
9153 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9154 break;
9155 case DRM_FORMAT_XRGB1555:
9156 case DRM_FORMAT_ARGB1555:
c16ed4be 9157 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9158 DRM_DEBUG("unsupported pixel format: %s\n",
9159 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9160 return -EINVAL;
c16ed4be 9161 }
57779d06
VS		 9162 break;
9163 case DRM_FORMAT_XBGR8888:
9164 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9165 case DRM_FORMAT_XRGB2101010:
9166 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9167 case DRM_FORMAT_XBGR2101010:
9168 case DRM_FORMAT_ABGR2101010:
c16ed4be 9169 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9170 DRM_DEBUG("unsupported pixel format: %s\n",
9171 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9172 return -EINVAL;
c16ed4be 9173 }
b5626747 9174 break;
04b3924d
VS		 9175 case DRM_FORMAT_YUYV:
9176 case DRM_FORMAT_UYVY:
9177 case DRM_FORMAT_YVYU:
9178 case DRM_FORMAT_VYUY:
c16ed4be 9179 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9180 DRM_DEBUG("unsupported pixel format: %s\n",
9181 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9182 return -EINVAL;
c16ed4be 9183 }
57cd6508
CW		 9184 break;
9185 default:
4ee62c76
VS		 9186 DRM_DEBUG("unsupported pixel format: %s\n",
9187 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9188 return -EINVAL;
9189 }
9190
90f9a336
VS		 9191 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9192 if (mode_cmd->offsets[0] != 0)
9193 return -EINVAL;
9194
c7d73f6a
DV		 9195 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9196 intel_fb->obj = obj;
9197
79e53945
JB		 9198 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9199 if (ret) {
9200 DRM_ERROR("framebuffer init failed %d\n", ret);
9201 return ret;
9202 }
9203
79e53945
JB		 9204 return 0;
9205}
9206
79e53945
JB		 9207static struct drm_framebuffer *
9208intel_user_framebuffer_create(struct drm_device *dev,
9209 struct drm_file *filp,
308e5bcb 9210 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9211{
05394f39 9212 struct drm_i915_gem_object *obj;
79e53945 9213
308e5bcb
JB		 9214 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9215 mode_cmd->handles[0]));
c8725226 9216 if (&obj->base == NULL)
cce13ff7 9217 return ERR_PTR(-ENOENT);
79e53945 9218
d2dff872 9219 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9220}
9221
79e53945 9222static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9223 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9224 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9225};
9226
e70236a8
JB		 9227/* Set up chip specific display functions */
9228static void intel_init_display(struct drm_device *dev)
9229{
9230 struct drm_i915_private *dev_priv = dev->dev_private;
9231
ee9300bb
DV		 9232 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9233 dev_priv->display.find_dpll = g4x_find_best_dpll;
9234 else if (IS_VALLEYVIEW(dev))
9235 dev_priv->display.find_dpll = vlv_find_best_dpll;
9236 else if (IS_PINEVIEW(dev))
9237 dev_priv->display.find_dpll = pnv_find_best_dpll;
9238 else
9239 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9240
affa9354 9241 if (HAS_DDI(dev)) {
0e8ffe1b 9242 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9243 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9244 dev_priv->display.crtc_enable = haswell_crtc_enable;
9245 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9246 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9247 dev_priv->display.update_plane = ironlake_update_plane;
9248 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9249 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9250 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9251 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9252 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9253 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9254 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9255 } else if (IS_VALLEYVIEW(dev)) {
9256 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9257 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9258 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9259 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9260 dev_priv->display.off = i9xx_crtc_off;
9261 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9262 } else {
0e8ffe1b 9263 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9264 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9265 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9266 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9267 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9268 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9269 }
e70236a8 9270
e70236a8 9271 /* Returns the core display clock speed */
25eb05fc
JB		 9272 if (IS_VALLEYVIEW(dev))
9273 dev_priv->display.get_display_clock_speed =
9274 valleyview_get_display_clock_speed;
9275 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9276 dev_priv->display.get_display_clock_speed =
9277 i945_get_display_clock_speed;
9278 else if (IS_I915G(dev))
9279 dev_priv->display.get_display_clock_speed =
9280 i915_get_display_clock_speed;
f2b115e6 9281 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9282 dev_priv->display.get_display_clock_speed =
9283 i9xx_misc_get_display_clock_speed;
9284 else if (IS_I915GM(dev))
9285 dev_priv->display.get_display_clock_speed =
9286 i915gm_get_display_clock_speed;
9287 else if (IS_I865G(dev))
9288 dev_priv->display.get_display_clock_speed =
9289 i865_get_display_clock_speed;
f0f8a9ce 9290 else if (IS_I85X(dev))
e70236a8
JB		 9291 dev_priv->display.get_display_clock_speed =
9292 i855_get_display_clock_speed;
9293 else /* 852, 830 */
9294 dev_priv->display.get_display_clock_speed =
9295 i830_get_display_clock_speed;
9296
7f8a8569 9297 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9298 if (IS_GEN5(dev)) {
674cf967 9299 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9300 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9301 } else if (IS_GEN6(dev)) {
674cf967 9302 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9303 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9304 } else if (IS_IVYBRIDGE(dev)) {
9305 /* FIXME: detect B0+ stepping and use auto training */
9306 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9307 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9308 dev_priv->display.modeset_global_resources =
9309 ivb_modeset_global_resources;
c82e4d26
ED		 9310 } else if (IS_HASWELL(dev)) {
9311 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9312 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9313 dev_priv->display.modeset_global_resources =
9314 haswell_modeset_global_resources;
a0e63c22 9315 }
6067aaea 9316 } else if (IS_G4X(dev)) {
e0dac65e 9317 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9318 }
8c9f3aaf
JB		 9319
9320 /* Default just returns -ENODEV to indicate unsupported */
9321 dev_priv->display.queue_flip = intel_default_queue_flip;
9322
9323 switch (INTEL_INFO(dev)->gen) {
9324 case 2:
9325 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9326 break;
9327
9328 case 3:
9329 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9330 break;
9331
9332 case 4:
9333 case 5:
9334 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9335 break;
9336
9337 case 6:
9338 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9339 break;
7c9017e5
JB		 9340 case 7:
9341 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9342 break;
8c9f3aaf 9343 }
e70236a8
JB		 9344}
9345
b690e96c
JB		 9346/*
9347 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9348 * resume, or other times. This quirk makes sure that's the case for
9349 * affected systems.
9350 */
0206e353 9351static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9352{
9353 struct drm_i915_private *dev_priv = dev->dev_private;
9354
9355 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9356 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9357}
9358
435793df
KP		 9359/*
9360 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9361 */
9362static void quirk_ssc_force_disable(struct drm_device *dev)
9363{
9364 struct drm_i915_private *dev_priv = dev->dev_private;
9365 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9366 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9367}
9368
4dca20ef 9369/*
5a15ab5b
CE		 9370 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9371 * brightness value
4dca20ef
CE		 9372 */
9373static void quirk_invert_brightness(struct drm_device *dev)
9374{
9375 struct drm_i915_private *dev_priv = dev->dev_private;
9376 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9377 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9378}
9379
b690e96c
JB		 9380struct intel_quirk {
9381 int device;
9382 int subsystem_vendor;
9383 int subsystem_device;
9384 void (*hook)(struct drm_device *dev);
9385};
9386
5f85f176
EE		 9387/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9388struct intel_dmi_quirk {
9389 void (*hook)(struct drm_device *dev);
9390 const struct dmi_system_id (*dmi_id_list)[];
9391};
9392
9393static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9394{
9395 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9396 return 1;
9397}
9398
9399static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9400 {
9401 .dmi_id_list = &(const struct dmi_system_id[]) {
9402 {
9403 .callback = intel_dmi_reverse_brightness,
9404 .ident = "NCR Corporation",
9405 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9406 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9407 },
9408 },
9409 { } /* terminating entry */
9410 },
9411 .hook = quirk_invert_brightness,
9412 },
9413};
9414
c43b5634 9415static struct intel_quirk intel_quirks[] = {
b690e96c 9416 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9417 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9418
b690e96c
JB		 9419 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9420 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9421
b690e96c
JB		 9422 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9423 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9424
ccd0d36e 9425 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9426 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9427 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9428
9429 /* Lenovo U160 cannot use SSC on LVDS */
9430 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9431
9432 /* Sony Vaio Y cannot use SSC on LVDS */
9433 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9434
9435 /* Acer Aspire 5734Z must invert backlight brightness */
9436 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9437
9438 /* Acer/eMachines G725 */
9439 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9440
9441 /* Acer/eMachines e725 */
9442 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9443
9444 /* Acer/Packard Bell NCL20 */
9445 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9446
9447 /* Acer Aspire 4736Z */
9448 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9449};
9450
9451static void intel_init_quirks(struct drm_device *dev)
9452{
9453 struct pci_dev *d = dev->pdev;
9454 int i;
9455
9456 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9457 struct intel_quirk *q = &intel_quirks[i];
9458
9459 if (d->device == q->device &&
9460 (d->subsystem_vendor == q->subsystem_vendor ||
9461 q->subsystem_vendor == PCI_ANY_ID) &&
9462 (d->subsystem_device == q->subsystem_device ||
9463 q->subsystem_device == PCI_ANY_ID))
9464 q->hook(dev);
9465 }
5f85f176
EE		 9466 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9467 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9468 intel_dmi_quirks[i].hook(dev);
9469 }
b690e96c
JB		 9470}
9471
9cce37f4
JB		 9472/* Disable the VGA plane that we never use */
9473static void i915_disable_vga(struct drm_device *dev)
9474{
9475 struct drm_i915_private *dev_priv = dev->dev_private;
9476 u8 sr1;
766aa1c4 9477 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9478
9479 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9480 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9481 sr1 = inb(VGA_SR_DATA);
9482 outb(sr1 | 1<<5, VGA_SR_DATA);
9483 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9484 udelay(300);
9485
9486 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9487 POSTING_READ(vga_reg);
9488}
9489
f817586c
DV		 9490void intel_modeset_init_hw(struct drm_device *dev)
9491{
fa42e23c 9492 intel_init_power_well(dev);
0232e927 9493
a8f78b58
ED		 9494 intel_prepare_ddi(dev);
9495
f817586c
DV		 9496 intel_init_clock_gating(dev);
9497
79f5b2c7 9498 mutex_lock(&dev->struct_mutex);
8090c6b9 9499 intel_enable_gt_powersave(dev);
79f5b2c7 9500 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9501}
9502
7d708ee4
ID		 9503void intel_modeset_suspend_hw(struct drm_device *dev)
9504{
9505 intel_suspend_hw(dev);
9506}
9507
79e53945
JB		 9508void intel_modeset_init(struct drm_device *dev)
9509{
652c393a 9510 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9511 int i, j, ret;
79e53945
JB		 9512
9513 drm_mode_config_init(dev);
9514
9515 dev->mode_config.min_width = 0;
9516 dev->mode_config.min_height = 0;
9517
019d96cb
DA		 9518 dev->mode_config.preferred_depth = 24;
9519 dev->mode_config.prefer_shadow = 1;
9520
e6ecefaa 9521 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9522
b690e96c
JB		 9523 intel_init_quirks(dev);
9524
1fa61106
ED		 9525 intel_init_pm(dev);
9526
e3c74757
BW		 9527 if (INTEL_INFO(dev)->num_pipes == 0)
9528 return;
9529
e70236a8
JB		 9530 intel_init_display(dev);
9531
a6c45cf0
CW		 9532 if (IS_GEN2(dev)) {
9533 dev->mode_config.max_width = 2048;
9534 dev->mode_config.max_height = 2048;
9535 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9536 dev->mode_config.max_width = 4096;
9537 dev->mode_config.max_height = 4096;
79e53945 9538 } else {
a6c45cf0
CW		 9539 dev->mode_config.max_width = 8192;
9540 dev->mode_config.max_height = 8192;
79e53945 9541 }
5d4545ae 9542 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9543
28c97730 9544 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9545 INTEL_INFO(dev)->num_pipes,
9546 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9547
7eb552ae 9548 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9549 intel_crtc_init(dev, i);
7f1f3851
JB		 9550 for (j = 0; j < dev_priv->num_plane; j++) {
9551 ret = intel_plane_init(dev, i, j);
9552 if (ret)
06da8da2
VS		 9553 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9554 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9555 }
79e53945
JB		 9556 }
9557
79f689aa 9558 intel_cpu_pll_init(dev);
e72f9fbf 9559 intel_shared_dpll_init(dev);
ee7b9f93 9560
9cce37f4
JB		 9561 /* Just disable it once at startup */
9562 i915_disable_vga(dev);
79e53945 9563 intel_setup_outputs(dev);
11be49eb
CW		 9564
9565 /* Just in case the BIOS is doing something questionable. */
9566 intel_disable_fbc(dev);
2c7111db
CW		 9567}
9568
24929352
DV		 9569static void
9570intel_connector_break_all_links(struct intel_connector *connector)
9571{
9572 connector->base.dpms = DRM_MODE_DPMS_OFF;
9573 connector->base.encoder = NULL;
9574 connector->encoder->connectors_active = false;
9575 connector->encoder->base.crtc = NULL;
9576}
9577
7fad798e
DV		 9578static void intel_enable_pipe_a(struct drm_device *dev)
9579{
9580 struct intel_connector *connector;
9581 struct drm_connector *crt = NULL;
9582 struct intel_load_detect_pipe load_detect_temp;
9583
9584 /* We can't just switch on the pipe A, we need to set things up with a
9585 * proper mode and output configuration. As a gross hack, enable pipe A
9586 * by enabling the load detect pipe once. */
9587 list_for_each_entry(connector,
9588 &dev->mode_config.connector_list,
9589 base.head) {
9590 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9591 crt = &connector->base;
9592 break;
9593 }
9594 }
9595
9596 if (!crt)
9597 return;
9598
9599 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9600 intel_release_load_detect_pipe(crt, &load_detect_temp);
9601
652c393a 9602
7fad798e
DV		 9603}
9604
fa555837
DV		 9605static bool
9606intel_check_plane_mapping(struct intel_crtc *crtc)
9607{
7eb552ae
BW		 9608 struct drm_device *dev = crtc->base.dev;
9609 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9610 u32 reg, val;
9611
7eb552ae 9612 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9613 return true;
9614
9615 reg = DSPCNTR(!crtc->plane);
9616 val = I915_READ(reg);
9617
9618 if ((val & DISPLAY_PLANE_ENABLE) &&
9619 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9620 return false;
9621
9622 return true;
9623}
9624
24929352
DV		 9625static void intel_sanitize_crtc(struct intel_crtc *crtc)
9626{
9627 struct drm_device *dev = crtc->base.dev;
9628 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9629 u32 reg;
24929352 9630
24929352 9631 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9632 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9633 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9634
9635 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9636 * disable the crtc (and hence change the state) if it is wrong. Note
9637 * that gen4+ has a fixed plane -> pipe mapping. */
9638 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9639 struct intel_connector *connector;
9640 bool plane;
9641
24929352
DV		 9642 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9643 crtc->base.base.id);
9644
9645 /* Pipe has the wrong plane attached and the plane is active.
9646 * Temporarily change the plane mapping and disable everything
9647 * ... */
9648 plane = crtc->plane;
9649 crtc->plane = !plane;
9650 dev_priv->display.crtc_disable(&crtc->base);
9651 crtc->plane = plane;
9652
9653 /* ... and break all links. */
9654 list_for_each_entry(connector, &dev->mode_config.connector_list,
9655 base.head) {
9656 if (connector->encoder->base.crtc != &crtc->base)
9657 continue;
9658
9659 intel_connector_break_all_links(connector);
9660 }
9661
9662 WARN_ON(crtc->active);
9663 crtc->base.enabled = false;
9664 }
24929352 9665
7fad798e
DV		 9666 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9667 crtc->pipe == PIPE_A && !crtc->active) {
9668 /* BIOS forgot to enable pipe A, this mostly happens after
9669 * resume. Force-enable the pipe to fix this, the update_dpms
9670 * call below we restore the pipe to the right state, but leave
9671 * the required bits on. */
9672 intel_enable_pipe_a(dev);
9673 }
9674
24929352
DV		 9675 /* Adjust the state of the output pipe according to whether we
9676 * have active connectors/encoders. */
9677 intel_crtc_update_dpms(&crtc->base);
9678
9679 if (crtc->active != crtc->base.enabled) {
9680 struct intel_encoder *encoder;
9681
9682 /* This can happen either due to bugs in the get_hw_state
9683 * functions or because the pipe is force-enabled due to the
9684 * pipe A quirk. */
9685 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9686 crtc->base.base.id,
9687 crtc->base.enabled ? "enabled" : "disabled",
9688 crtc->active ? "enabled" : "disabled");
9689
9690 crtc->base.enabled = crtc->active;
9691
9692 /* Because we only establish the connector -> encoder ->
9693 * crtc links if something is active, this means the
9694 * crtc is now deactivated. Break the links. connector
9695 * -> encoder links are only establish when things are
9696 * actually up, hence no need to break them. */
9697 WARN_ON(crtc->active);
9698
9699 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9700 WARN_ON(encoder->connectors_active);
9701 encoder->base.crtc = NULL;
9702 }
9703 }
9704}
9705
9706static void intel_sanitize_encoder(struct intel_encoder *encoder)
9707{
9708 struct intel_connector *connector;
9709 struct drm_device *dev = encoder->base.dev;
9710
9711 /* We need to check both for a crtc link (meaning that the
9712 * encoder is active and trying to read from a pipe) and the
9713 * pipe itself being active. */
9714 bool has_active_crtc = encoder->base.crtc &&
9715 to_intel_crtc(encoder->base.crtc)->active;
9716
9717 if (encoder->connectors_active && !has_active_crtc) {
9718 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9719 encoder->base.base.id,
9720 drm_get_encoder_name(&encoder->base));
9721
9722 /* Connector is active, but has no active pipe. This is
9723 * fallout from our resume register restoring. Disable
9724 * the encoder manually again. */
9725 if (encoder->base.crtc) {
9726 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9727 encoder->base.base.id,
9728 drm_get_encoder_name(&encoder->base));
9729 encoder->disable(encoder);
9730 }
9731
9732 /* Inconsistent output/port/pipe state happens presumably due to
9733 * a bug in one of the get_hw_state functions. Or someplace else
9734 * in our code, like the register restore mess on resume. Clamp
9735 * things to off as a safer default. */
9736 list_for_each_entry(connector,
9737 &dev->mode_config.connector_list,
9738 base.head) {
9739 if (connector->encoder != encoder)
9740 continue;
9741
9742 intel_connector_break_all_links(connector);
9743 }
9744 }
9745 /* Enabled encoders without active connectors will be fixed in
9746 * the crtc fixup. */
9747}
9748
44cec740 9749void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9750{
9751 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9752 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9753
9754 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9755 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9756 i915_disable_vga(dev);
0fde901f
KM		 9757 }
9758}
9759
30e984df 9760static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9761{
9762 struct drm_i915_private *dev_priv = dev->dev_private;
9763 enum pipe pipe;
24929352
DV		 9764 struct intel_crtc *crtc;
9765 struct intel_encoder *encoder;
9766 struct intel_connector *connector;
5358901f 9767 int i;
24929352 9768
0e8ffe1b
DV		 9769 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9770 base.head) {
88adfff1 9771 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9772
0e8ffe1b
DV		 9773 crtc->active = dev_priv->display.get_pipe_config(crtc,
9774 &crtc->config);
24929352
DV		 9775
9776 crtc->base.enabled = crtc->active;
9777
9778 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9779 crtc->base.base.id,
9780 crtc->active ? "enabled" : "disabled");
9781 }
9782
5358901f 9783 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9784 if (HAS_DDI(dev))
6441ab5f
PZ		 9785 intel_ddi_setup_hw_pll_state(dev);
9786
5358901f
DV		 9787 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9788 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9789
9790 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9791 pll->active = 0;
9792 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9793 base.head) {
9794 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9795 pll->active++;
9796 }
9797 pll->refcount = pll->active;
9798
9799 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9800 pll->name, pll->refcount);
9801 }
9802
24929352
DV		 9803 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9804 base.head) {
9805 pipe = 0;
9806
9807 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9808 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9809 encoder->base.crtc = &crtc->base;
9810 if (encoder->get_config)
9811 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9812 } else {
9813 encoder->base.crtc = NULL;
9814 }
9815
9816 encoder->connectors_active = false;
9817 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9818 encoder->base.base.id,
9819 drm_get_encoder_name(&encoder->base),
9820 encoder->base.crtc ? "enabled" : "disabled",
9821 pipe);
9822 }
9823
9824 list_for_each_entry(connector, &dev->mode_config.connector_list,
9825 base.head) {
9826 if (connector->get_hw_state(connector)) {
9827 connector->base.dpms = DRM_MODE_DPMS_ON;
9828 connector->encoder->connectors_active = true;
9829 connector->base.encoder = &connector->encoder->base;
9830 } else {
9831 connector->base.dpms = DRM_MODE_DPMS_OFF;
9832 connector->base.encoder = NULL;
9833 }
9834 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9835 connector->base.base.id,
9836 drm_get_connector_name(&connector->base),
9837 connector->base.encoder ? "enabled" : "disabled");
9838 }
30e984df
DV		 9839}
9840
9841/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9842 * and i915 state tracking structures. */
9843void intel_modeset_setup_hw_state(struct drm_device *dev,
9844 bool force_restore)
9845{
9846 struct drm_i915_private *dev_priv = dev->dev_private;
9847 enum pipe pipe;
9848 struct drm_plane *plane;
9849 struct intel_crtc *crtc;
9850 struct intel_encoder *encoder;
9851
9852 intel_modeset_readout_hw_state(dev);
24929352
DV		 9853
9854 /* HW state is read out, now we need to sanitize this mess. */
9855 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9856 base.head) {
9857 intel_sanitize_encoder(encoder);
9858 }
9859
9860 for_each_pipe(pipe) {
9861 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9862 intel_sanitize_crtc(crtc);
c0b03411 9863 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9864 }
9a935856 9865
45e2b5f6 9866 if (force_restore) {
f30da187
DV		 9867 /*
9868 * We need to use raw interfaces for restoring state to avoid
9869 * checking (bogus) intermediate states.
9870 */
45e2b5f6 9871 for_each_pipe(pipe) {
b5644d05
JB		 9872 struct drm_crtc *crtc =
9873 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9874
9875 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9876 crtc->fb);
45e2b5f6 9877 }
b5644d05
JB		 9878 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9879 intel_plane_restore(plane);
0fde901f
KM		 9880
9881 i915_redisable_vga(dev);
45e2b5f6
DV		 9882 } else {
9883 intel_modeset_update_staged_output_state(dev);
9884 }
8af6cf88
DV		 9885
9886 intel_modeset_check_state(dev);
2e938892
DV		 9887
9888 drm_mode_config_reset(dev);
2c7111db
CW		 9889}
9890
9891void intel_modeset_gem_init(struct drm_device *dev)
9892{
1833b134 9893 intel_modeset_init_hw(dev);
02e792fb
DV		 9894
9895 intel_setup_overlay(dev);
24929352 9896
45e2b5f6 9897 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9898}
9899
9900void intel_modeset_cleanup(struct drm_device *dev)
9901{
652c393a
JB		 9902 struct drm_i915_private *dev_priv = dev->dev_private;
9903 struct drm_crtc *crtc;
9904 struct intel_crtc *intel_crtc;
9905
fd0c0642
DV		 9906 /*
9907 * Interrupts and polling as the first thing to avoid creating havoc.
9908 * Too much stuff here (turning of rps, connectors, ...) would
9909 * experience fancy races otherwise.
9910 */
9911 drm_irq_uninstall(dev);
9912 cancel_work_sync(&dev_priv->hotplug_work);
9913 /*
9914 * Due to the hpd irq storm handling the hotplug work can re-arm the
9915 * poll handlers. Hence disable polling after hpd handling is shut down.
9916 */
f87ea761 9917 drm_kms_helper_poll_fini(dev);
fd0c0642 9918
652c393a
JB		 9919 mutex_lock(&dev->struct_mutex);
9920
723bfd70
JB		 9921 intel_unregister_dsm_handler();
9922
652c393a
JB		 9923 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9924 /* Skip inactive CRTCs */
9925 if (!crtc->fb)
9926 continue;
9927
9928 intel_crtc = to_intel_crtc(crtc);
3dec0095 9929 intel_increase_pllclock(crtc);
652c393a
JB		 9930 }
9931
973d04f9 9932 intel_disable_fbc(dev);
e70236a8 9933
8090c6b9 9934 intel_disable_gt_powersave(dev);
0cdab21f 9935
930ebb46
DV		 9936 ironlake_teardown_rc6(dev);
9937
69341a5e
KH		 9938 mutex_unlock(&dev->struct_mutex);
9939
1630fe75
CW		 9940 /* flush any delayed tasks or pending work */
9941 flush_scheduled_work();
9942
dc652f90
JN		 9943 /* destroy backlight, if any, before the connectors */
9944 intel_panel_destroy_backlight(dev);
9945
79e53945 9946 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9947
9948 intel_cleanup_overlay(dev);
79e53945
JB		 9949}
9950
f1c79df3
ZW		 9951/*
9952 * Return which encoder is currently attached for connector.
9953 */
df0e9248 9954struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9955{
df0e9248
CW		 9956 return &intel_attached_encoder(connector)->base;
9957}
f1c79df3 9958
df0e9248
CW		 9959void intel_connector_attach_encoder(struct intel_connector *connector,
9960 struct intel_encoder *encoder)
9961{
9962 connector->encoder = encoder;
9963 drm_mode_connector_attach_encoder(&connector->base,
9964 &encoder->base);
79e53945 9965}
28d52043
DA		 9966
9967/*
9968 * set vga decode state - true == enable VGA decode
9969 */
9970int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9971{
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9973 u16 gmch_ctrl;
9974
9975 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9976 if (state)
9977 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9978 else
9979 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9980 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9981 return 0;
9982}
c4a1d9e4
CW		 9983
9984#ifdef CONFIG_DEBUG_FS
9985#include <linux/seq_file.h>
9986
9987struct intel_display_error_state {
ff57f1b0
PZ		 9988
9989 u32 power_well_driver;
9990
c4a1d9e4
CW		 9991 struct intel_cursor_error_state {
9992 u32 control;
9993 u32 position;
9994 u32 base;
9995 u32 size;
52331309 9996 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9997
9998 struct intel_pipe_error_state {
ff57f1b0 9999 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10000 u32 conf;
10001 u32 source;
10002
10003 u32 htotal;
10004 u32 hblank;
10005 u32 hsync;
10006 u32 vtotal;
10007 u32 vblank;
10008 u32 vsync;
52331309 10009 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10010
10011 struct intel_plane_error_state {
10012 u32 control;
10013 u32 stride;
10014 u32 size;
10015 u32 pos;
10016 u32 addr;
10017 u32 surface;
10018 u32 tile_offset;
52331309 10019 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10020};
10021
10022struct intel_display_error_state *
10023intel_display_capture_error_state(struct drm_device *dev)
10024{
0206e353 10025 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10026 struct intel_display_error_state *error;
702e7a56 10027 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10028 int i;
10029
10030 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10031 if (error == NULL)
10032 return NULL;
10033
ff57f1b0
PZ		 10034 if (HAS_POWER_WELL(dev))
10035 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10036
52331309 10037 for_each_pipe(i) {
702e7a56 10038 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10039 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10040
a18c4c3d
PZ		 10041 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10042 error->cursor[i].control = I915_READ(CURCNTR(i));
10043 error->cursor[i].position = I915_READ(CURPOS(i));
10044 error->cursor[i].base = I915_READ(CURBASE(i));
10045 } else {
10046 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10047 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10048 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10049 }
c4a1d9e4
CW		 10050
10051 error->plane[i].control = I915_READ(DSPCNTR(i));
10052 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10053 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10054 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10055 error->plane[i].pos = I915_READ(DSPPOS(i));
10056 }
ca291363
PZ		 10057 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10058 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10059 if (INTEL_INFO(dev)->gen >= 4) {
10060 error->plane[i].surface = I915_READ(DSPSURF(i));
10061 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10062 }
10063
702e7a56 10064 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10065 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10066 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10067 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10068 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10069 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10070 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10071 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10072 }
10073
12d217c7
PZ		 10074 /* In the code above we read the registers without checking if the power
10075 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10076 * prevent the next I915_WRITE from detecting it and printing an error
10077 * message. */
10078 if (HAS_POWER_WELL(dev))
10079 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10080
c4a1d9e4
CW		 10081 return error;
10082}
10083
edc3d884
MK		 10084#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10085
c4a1d9e4 10086void
edc3d884 10087intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10088 struct drm_device *dev,
10089 struct intel_display_error_state *error)
10090{
10091 int i;
10092
edc3d884 10093 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10094 if (HAS_POWER_WELL(dev))
edc3d884 10095 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10096 error->power_well_driver);
52331309 10097 for_each_pipe(i) {
edc3d884
MK		 10098 err_printf(m, "Pipe [%d]:\n", i);
10099 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10100 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10101 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10102 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10103 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10104 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10105 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10106 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10107 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10108 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10109
10110 err_printf(m, "Plane [%d]:\n", i);
10111 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10112 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10113 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10114 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10115 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10116 }
4b71a570 10117 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10118 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10119 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10120 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10121 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10122 }
10123
edc3d884
MK		 10124 err_printf(m, "Cursor [%d]:\n", i);
10125 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10126 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10127 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10128 }
10129}
10130#endif
Linux kernel - Deliverables
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