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drm/i915: Embed drm_mm_node in i915 gem obj
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
e4b36699 92static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
105static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
e4b36699 116};
273e27ca 117
e4b36699 118static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 129};
130
131static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 142};
143
273e27ca 144
e4b36699 145static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
044c7c41 157 },
e4b36699
KP		 158};
159
160static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
044c7c41 184 },
e4b36699
KP		 185};
186
187static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
044c7c41 198 },
e4b36699
KP		 199};
200
f2b115e6 201static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 204 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
273e27ca 207 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 214};
215
f2b115e6 216static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 227};
228
273e27ca
EA		 229/* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
b91ad0ec 234static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 245};
246
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 258};
259
260static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 271};
272
273e27ca 273/* LVDS 100mhz refclk limits. */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
0206e353 282 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
0206e353 295 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 298};
299
a0c4da24
JB		 300static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
75e53986 308 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 311};
312
313static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 329 .n = { .min = 1, .max = 7 },
74a4dd2e 330 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
75e53986 334 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 412 limit = &intel_limits_i8xx_lvds;
79e53945 413 else
e4b36699 414 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
a4fc5ed6 736
a5c961d1
PZ		 737enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739{
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
3b117c8f 743 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 744}
745
a928d536
PZ		 746static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755}
756
9d0498a2
JB		 757/**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 766{
9d0498a2 767 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 768 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 769
a928d536
PZ		 770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
300387c0
CW		 775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
9d0498a2 791 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
9d0498a2
JB		 795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
ab7ad7f6
KP		 798/*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
ab7ad7f6
KP		 807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
58e10eb9 813 *
9d0498a2 814 */
58e10eb9 815void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
ab7ad7f6
KP		 820
821 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 822 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 823
824 /* Wait for the Pipe State to go off */
58e10eb9
CW		 825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
284637d9 827 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 828 } else {
837ba00f 829 u32 last_line, line_mask;
58e10eb9 830 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
837ba00f
PZ		 833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
ab7ad7f6
KP		 838 /* Wait for the display line to settle */
839 do {
837ba00f 840 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 841 mdelay(5);
837ba00f 842 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
284637d9 845 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 846 }
79e53945
JB		 847}
848
b0ea7d37
DL		 849/*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858{
859 u32 bit;
860
c36346e3
DL		 861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
b0ea7d37
DL		 889 }
890
891 return I915_READ(SDEISR) & bit;
892}
893
b24e7179
JB		 894static const char *state_string(bool enabled)
895{
896 return enabled ? "on" : "off";
897}
898
899/* Only for pre-ILK configs */
55607e8a
DV		 900void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
b24e7179
JB		 902{
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913}
b24e7179 914
55607e8a 915struct intel_shared_dpll *
e2b78267
DV		 916intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
917{
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
a43f6e0f 920 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 921 return NULL;
922
a43f6e0f 923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 924}
925
040484af 926/* For ILK+ */
55607e8a
DV		 927void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
040484af 930{
040484af 931 bool cur_state;
5358901f 932 struct intel_dpll_hw_state hw_state;
040484af 933
9d82aa17
ED		 934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
92b27b08 939 if (WARN (!pll,
46edb027 940 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 941 return;
ee7b9f93 942
5358901f 943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 944 WARN(cur_state != state,
5358901f
DV		 945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
040484af 947}
040484af
JB		 948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
ad80a810
PZ		 955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
040484af 957
affa9354
PZ		 958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
ad80a810 960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 961 val = I915_READ(reg);
ad80a810 962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
040484af
JB		 968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
d63fa0dc
PZ		 982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
bf507ef7 1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1003 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1004 return;
1005
040484af
JB		 1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
55607e8a
DV		 1011void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
040484af
JB		 1013{
1014 int reg;
1015 u32 val;
55607e8a 1016 bool cur_state;
040484af
JB		 1017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
55607e8a
DV		 1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
040484af
JB		 1024}
1025
ea0760cf
JB		 1026static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
0de3b485 1032 bool locked = true;
ea0760cf
JB		 1033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1052 pipe_name(pipe));
ea0760cf
JB		 1053}
1054
b840d907
JB		 1055void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
b24e7179
JB		 1057{
1058 int reg;
1059 u32 val;
63d7bbe9 1060 bool cur_state;
702e7a56
PZ		 1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
b24e7179 1063
8e636784
DV		 1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
b97186f0
PZ		 1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
63d7bbe9
JB		 1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1079 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1080}
1081
931872fc
CW		 1082static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
b24e7179
JB		 1084{
1085 int reg;
1086 u32 val;
931872fc 1087 bool cur_state;
b24e7179
JB		 1088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
931872fc
CW		 1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
b24e7179
JB		 1100static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
653e1026 1103 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
653e1026
VS		 1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
19ec1358 1115 return;
28c05794 1116 }
19ec1358 1117
b24e7179 1118 /* Need to check both planes against the pipe */
653e1026 1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1127 }
1128}
1129
19332d7a
JB		 1130static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132{
20674eef 1133 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1134 int reg, i;
1135 u32 val;
1136
20674eef
VS		 1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
19332d7a 1147 val = I915_READ(reg);
20674eef 1148 WARN((val & SPRITE_ENABLE),
06da8da2 1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
19332d7a 1153 val = I915_READ(reg);
20674eef 1154 WARN((val & DVS_ENABLE),
06da8da2 1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1156 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1157 }
1158}
1159
92f2584a
JB		 1160static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161{
1162 u32 val;
1163 bool enabled;
1164
9d82aa17
ED		 1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
92f2584a
JB		 1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174}
1175
ab9412ba
DV		 1176static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
92f2584a
JB		 1178{
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
ab9412ba 1183 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
92f2584a
JB		 1189}
1190
4e634389
KP		 1191static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1193{
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207}
1208
1519b995
KP		 1209static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211{
dc0fa718 1212 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1217 return false;
1218 } else {
dc0fa718 1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1220 return false;
1221 }
1222 return true;
1223}
1224
1225static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
291906f1 1256static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1257 enum pipe pipe, int reg, u32 port_sel)
291906f1 1258{
47a05eca 1259 u32 val = I915_READ(reg);
4e634389 1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1262 reg, pipe_name(pipe));
de9a35ab 1263
75c5da27
DV		 1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
de9a35ab 1266 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1267}
1268
1269static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271{
47a05eca 1272 u32 val = I915_READ(reg);
b70ad586 1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1275 reg, pipe_name(pipe));
de9a35ab 1276
dc0fa718 1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1278 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1279 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1280}
1281
1282static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
291906f1 1287
f0575e92
KP		 1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
b70ad586 1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1296 pipe_name(pipe));
291906f1
JB		 1297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
b70ad586 1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 pipe_name(pipe));
291906f1 1303
e2debe91
PZ		 1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1307}
1308
87442f73
DV		 1309static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310{
1311 int reg;
1312 u32 val;
1313
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337}
1338
66e3d5c0 1339static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1340{
66e3d5c0
DV		 1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1345
66e3d5c0 1346 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1347
63d7bbe9 1348 /* No really, not for ILK+ */
87442f73 1349 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1350
1351 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1354
66e3d5c0
DV		 1355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
63d7bbe9
JB		 1372
1373 /* We do this three times for luck */
66e3d5c0 1374 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
66e3d5c0 1377 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
66e3d5c0 1380 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
89b667f8
JB		 1413void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414{
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425}
1426
92f2584a 1427/**
e72f9fbf 1428 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
e2b78267 1435static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1436{
e2b78267
DV		 1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1439
48da64a8 1440 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1441 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1442 if (WARN_ON(pll == NULL))
48da64a8
CW		 1443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
ee7b9f93 1447
46edb027
DV		 1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
e2b78267 1450 crtc->base.base.id);
92f2584a 1451
cdbd2316
DV		 1452 if (pll->active++) {
1453 WARN_ON(!pll->on);
e9d6944e 1454 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1455 return;
1456 }
f4a091c7 1457 WARN_ON(pll->on);
ee7b9f93 1458
46edb027 1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1460 pll->enable(dev_priv, pll);
ee7b9f93 1461 pll->on = true;
92f2584a
JB		 1462}
1463
e2b78267 1464static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1465{
e2b78267
DV		 1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1468
92f2584a
JB		 1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1471 if (WARN_ON(pll == NULL))
ee7b9f93 1472 return;
92f2584a 1473
48da64a8
CW		 1474 if (WARN_ON(pll->refcount == 0))
1475 return;
7a419866 1476
46edb027
DV		 1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
e2b78267 1479 crtc->base.base.id);
7a419866 1480
48da64a8 1481 if (WARN_ON(pll->active == 0)) {
e9d6944e 1482 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1483 return;
1484 }
1485
e9d6944e 1486 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1487 WARN_ON(!pll->on);
cdbd2316 1488 if (--pll->active)
7a419866 1489 return;
ee7b9f93 1490
46edb027 1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1492 pll->disable(dev_priv, pll);
ee7b9f93 1493 pll->on = false;
92f2584a
JB		 1494}
1495
b8a4f404
PZ		 1496static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
040484af 1498{
23670b32 1499 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1502 uint32_t reg, val, pipeconf_val;
040484af
JB		 1503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
e72f9fbf 1508 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1509 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
23670b32
DV		 1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
59c859d6 1522 }
23670b32 1523
ab9412ba 1524 reg = PCH_TRANSCONF(pipe);
040484af 1525 val = I915_READ(reg);
5f7f726d 1526 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
dfd07d72
DV		 1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1535 }
5f7f726d
PZ		 1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
040484af
JB		 1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1550}
1551
8fb033d7 1552static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1553 enum transcoder cpu_transcoder)
040484af 1554{
8fb033d7 1555 u32 val, pipeconf_val;
8fb033d7
PZ		 1556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
8fb033d7 1560 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1563
223a6fdf
PZ		 1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
25f3ef11 1569 val = TRANS_ENABLE;
937bb610 1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1571
9a76b1c6
PZ		 1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
a35f2679 1574 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1575 else
1576 val |= TRANS_PROGRESSIVE;
1577
ab9412ba
DV		 1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1580 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1581}
1582
b8a4f404
PZ		 1583static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
040484af 1585{
23670b32
DV		 1586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
040484af
JB		 1588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
291906f1
JB		 1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
ab9412ba 1596 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
040484af
JB		 1611}
1612
ab4d966c 1613static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1614{
8fb033d7
PZ		 1615 u32 val;
1616
ab9412ba 1617 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1618 val &= ~TRANS_ENABLE;
ab9412ba 1619 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1620 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1622 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1627 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1628}
1629
b24e7179 1630/**
309cfea8 1631 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
040484af 1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
040484af
JB		 1644static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
b24e7179 1646{
702e7a56
PZ		 1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
1a240d4d 1649 enum pipe pch_transcoder;
b24e7179
JB		 1650 int reg;
1651 u32 val;
1652
58c6eaa2
DV		 1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
681e5811 1656 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
b24e7179
JB		 1661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
cc391bbb 1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
040484af
JB		 1674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
b24e7179 1677
702e7a56 1678 reg = PIPECONF(cpu_transcoder);
b24e7179 1679 val = I915_READ(reg);
00d70b15
CW		 1680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685}
1686
1687/**
309cfea8 1688 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
702e7a56
PZ		 1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
b24e7179
JB		 1704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
19332d7a 1712 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725}
1726
d74362c9
KP		 1727/*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
6f1d69b0 1731void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1732 enum plane plane)
1733{
14f86147
DL		 1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1738}
1739
b24e7179
JB		 1740/**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750{
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1763 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765}
1766
b24e7179
JB		 1767/**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
00d70b15
CW		 1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789}
1790
693db184
CW		 1791static bool need_vtd_wa(struct drm_device *dev)
1792{
1793#ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796#endif
1797 return false;
1798}
1799
127bd2ac 1800int
48b956c5 1801intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1802 struct drm_i915_gem_object *obj,
919926ae 1803 struct intel_ring_buffer *pipelined)
6b95a207 1804{
ce453d81 1805 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1806 u32 alignment;
1807 int ret;
1808
05394f39 1809 switch (obj->tiling_mode) {
6b95a207 1810 case I915_TILING_NONE:
534843da
CW		 1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
a6c45cf0 1813 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
6b95a207
KH		 1817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
8bb6e959
DV		 1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
693db184
CW		 1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
ce453d81 1840 dev_priv->mm.interruptible = false;
2da3b9b9 1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1842 if (ret)
ce453d81 1843 goto err_interruptible;
6b95a207
KH		 1844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
06d98131 1850 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1851 if (ret)
1852 goto err_unpin;
1690e1eb 1853
9a5a53b3 1854 i915_gem_object_pin_fence(obj);
6b95a207 1855
ce453d81 1856 dev_priv->mm.interruptible = true;
6b95a207 1857 return 0;
48b956c5
CW		 1858
1859err_unpin:
1860 i915_gem_object_unpin(obj);
ce453d81
CW		 1861err_interruptible:
1862 dev_priv->mm.interruptible = true;
48b956c5 1863 return ret;
6b95a207
KH		 1864}
1865
1690e1eb
CW		 1866void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867{
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870}
1871
c2c75131
DV		 1872/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
bc752862
CW		 1874unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
c2c75131 1878{
bc752862
CW		 1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
c2c75131 1881
bc752862
CW		 1882 tile_rows = *y / 8;
1883 *y %= 8;
c2c75131 1884
bc752862
CW		 1885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
c2c75131
DV		 1897}
1898
17638cd6
JB		 1899static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
81255565
JB		 1901{
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
05394f39 1906 struct drm_i915_gem_object *obj;
81255565 1907 int plane = intel_crtc->plane;
e506a0c6 1908 unsigned long linear_offset;
81255565 1909 u32 dspcntr;
5eddb70b 1910 u32 reg;
81255565
JB		 1911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
84f44ce7 1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
81255565 1923
5eddb70b
CW		 1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
81255565
JB		 1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
81255565
JB		 1930 dspcntr |= DISPPLANE_8BPP;
1931 break;
57779d06
VS		 1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
81255565 1935 break;
57779d06
VS		 1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1954 break;
1955 default:
baba133a 1956 BUG();
81255565 1957 }
57779d06 1958
a6c45cf0 1959 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1960 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
de1aa629
VS		 1966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
5eddb70b 1969 I915_WRITE(reg, dspcntr);
81255565 1970
e506a0c6 1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1972
c2c75131
DV		 1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
bc752862
CW		 1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
c2c75131
DV		 1978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
e506a0c6 1980 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1981 }
e506a0c6 1982
f343c5f6
BW		 1983 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1984 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
1985 fb->pitches[0]);
01f2c773 1986 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1987 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 1988 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 1989 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 1990 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1991 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1992 } else
f343c5f6 1993 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 1994 POSTING_READ(reg);
81255565 1995
17638cd6
JB		 1996 return 0;
1997}
1998
1999static int ironlake_update_plane(struct drm_crtc *crtc,
2000 struct drm_framebuffer *fb, int x, int y)
2001{
2002 struct drm_device *dev = crtc->dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2005 struct intel_framebuffer *intel_fb;
2006 struct drm_i915_gem_object *obj;
2007 int plane = intel_crtc->plane;
e506a0c6 2008 unsigned long linear_offset;
17638cd6
JB		 2009 u32 dspcntr;
2010 u32 reg;
2011
2012 switch (plane) {
2013 case 0:
2014 case 1:
27f8227b 2015 case 2:
17638cd6
JB		 2016 break;
2017 default:
84f44ce7 2018 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2019 return -EINVAL;
2020 }
2021
2022 intel_fb = to_intel_framebuffer(fb);
2023 obj = intel_fb->obj;
2024
2025 reg = DSPCNTR(plane);
2026 dspcntr = I915_READ(reg);
2027 /* Mask out pixel format bits in case we change it */
2028 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2029 switch (fb->pixel_format) {
2030 case DRM_FORMAT_C8:
17638cd6
JB		 2031 dspcntr |= DISPPLANE_8BPP;
2032 break;
57779d06
VS		 2033 case DRM_FORMAT_RGB565:
2034 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2035 break;
57779d06
VS		 2036 case DRM_FORMAT_XRGB8888:
2037 case DRM_FORMAT_ARGB8888:
2038 dspcntr |= DISPPLANE_BGRX888;
2039 break;
2040 case DRM_FORMAT_XBGR8888:
2041 case DRM_FORMAT_ABGR8888:
2042 dspcntr |= DISPPLANE_RGBX888;
2043 break;
2044 case DRM_FORMAT_XRGB2101010:
2045 case DRM_FORMAT_ARGB2101010:
2046 dspcntr |= DISPPLANE_BGRX101010;
2047 break;
2048 case DRM_FORMAT_XBGR2101010:
2049 case DRM_FORMAT_ABGR2101010:
2050 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2051 break;
2052 default:
baba133a 2053 BUG();
17638cd6
JB		 2054 }
2055
2056 if (obj->tiling_mode != I915_TILING_NONE)
2057 dspcntr |= DISPPLANE_TILED;
2058 else
2059 dspcntr &= ~DISPPLANE_TILED;
2060
2061 /* must disable */
2062 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063
2064 I915_WRITE(reg, dspcntr);
2065
e506a0c6 2066 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2067 intel_crtc->dspaddr_offset =
bc752862
CW		 2068 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2069 fb->bits_per_pixel / 8,
2070 fb->pitches[0]);
c2c75131 2071 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2072
f343c5f6
BW		 2073 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2074 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2075 fb->pitches[0]);
01f2c773 2076 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2077 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2078 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2079 if (IS_HASWELL(dev)) {
2080 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2081 } else {
2082 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2083 I915_WRITE(DSPLINOFF(plane), linear_offset);
2084 }
17638cd6
JB		 2085 POSTING_READ(reg);
2086
2087 return 0;
2088}
2089
2090/* Assume fb object is pinned & idle & fenced and just update base pointers */
2091static int
2092intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2093 int x, int y, enum mode_set_atomic state)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2097
6b8e6ed0
CW		 2098 if (dev_priv->display.disable_fbc)
2099 dev_priv->display.disable_fbc(dev);
3dec0095 2100 intel_increase_pllclock(crtc);
81255565 2101
6b8e6ed0 2102 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2103}
2104
96a02917
VS		 2105void intel_display_handle_reset(struct drm_device *dev)
2106{
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 struct drm_crtc *crtc;
2109
2110 /*
2111 * Flips in the rings have been nuked by the reset,
2112 * so complete all pending flips so that user space
2113 * will get its events and not get stuck.
2114 *
2115 * Also update the base address of all primary
2116 * planes to the the last fb to make sure we're
2117 * showing the correct fb after a reset.
2118 *
2119 * Need to make two loops over the crtcs so that we
2120 * don't try to grab a crtc mutex before the
2121 * pending_flip_queue really got woken up.
2122 */
2123
2124 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126 enum plane plane = intel_crtc->plane;
2127
2128 intel_prepare_page_flip(dev, plane);
2129 intel_finish_page_flip_plane(dev, plane);
2130 }
2131
2132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2134
2135 mutex_lock(&crtc->mutex);
2136 if (intel_crtc->active)
2137 dev_priv->display.update_plane(crtc, crtc->fb,
2138 crtc->x, crtc->y);
2139 mutex_unlock(&crtc->mutex);
2140 }
2141}
2142
14667a4b
CW		 2143static int
2144intel_finish_fb(struct drm_framebuffer *old_fb)
2145{
2146 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2147 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2148 bool was_interruptible = dev_priv->mm.interruptible;
2149 int ret;
2150
14667a4b
CW		 2151 /* Big Hammer, we also need to ensure that any pending
2152 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2153 * current scanout is retired before unpinning the old
2154 * framebuffer.
2155 *
2156 * This should only fail upon a hung GPU, in which case we
2157 * can safely continue.
2158 */
2159 dev_priv->mm.interruptible = false;
2160 ret = i915_gem_object_finish_gpu(obj);
2161 dev_priv->mm.interruptible = was_interruptible;
2162
2163 return ret;
2164}
2165
198598d0
VS		 2166static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2167{
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_master_private *master_priv;
2170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2171
2172 if (!dev->primary->master)
2173 return;
2174
2175 master_priv = dev->primary->master->driver_priv;
2176 if (!master_priv->sarea_priv)
2177 return;
2178
2179 switch (intel_crtc->pipe) {
2180 case 0:
2181 master_priv->sarea_priv->pipeA_x = x;
2182 master_priv->sarea_priv->pipeA_y = y;
2183 break;
2184 case 1:
2185 master_priv->sarea_priv->pipeB_x = x;
2186 master_priv->sarea_priv->pipeB_y = y;
2187 break;
2188 default:
2189 break;
2190 }
2191}
2192
5c3b82e2 2193static int
3c4fdcfb 2194intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2195 struct drm_framebuffer *fb)
79e53945
JB		 2196{
2197 struct drm_device *dev = crtc->dev;
6b8e6ed0 2198 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2200 struct drm_framebuffer *old_fb;
5c3b82e2 2201 int ret;
79e53945
JB		 2202
2203 /* no fb bound */
94352cf9 2204 if (!fb) {
a5071c2f 2205 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2206 return 0;
2207 }
2208
7eb552ae 2209 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2210 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2211 plane_name(intel_crtc->plane),
2212 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2213 return -EINVAL;
79e53945
JB		 2214 }
2215
5c3b82e2 2216 mutex_lock(&dev->struct_mutex);
265db958 2217 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2218 to_intel_framebuffer(fb)->obj,
919926ae 2219 NULL);
5c3b82e2
CW		 2220 if (ret != 0) {
2221 mutex_unlock(&dev->struct_mutex);
a5071c2f 2222 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2223 return ret;
2224 }
79e53945 2225
4d6a3e63
JB		 2226 /* Update pipe size and adjust fitter if needed */
2227 if (i915_fastboot) {
2228 I915_WRITE(PIPESRC(intel_crtc->pipe),
2229 ((crtc->mode.hdisplay - 1) << 16) |
2230 (crtc->mode.vdisplay - 1));
2231 if (!intel_crtc->config.pch_pfit.size &&
2232 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2233 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2234 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2235 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2236 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2237 }
2238 }
2239
94352cf9 2240 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2241 if (ret) {
94352cf9 2242 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2243 mutex_unlock(&dev->struct_mutex);
a5071c2f 2244 DRM_ERROR("failed to update base address\n");
4e6cfefc 2245 return ret;
79e53945 2246 }
3c4fdcfb 2247
94352cf9
DV		 2248 old_fb = crtc->fb;
2249 crtc->fb = fb;
6c4c86f5
DV		 2250 crtc->x = x;
2251 crtc->y = y;
94352cf9 2252
b7f1de28 2253 if (old_fb) {
d7697eea
DV		 2254 if (intel_crtc->active && old_fb != fb)
2255 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2256 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2257 }
652c393a 2258
6b8e6ed0 2259 intel_update_fbc(dev);
5c3b82e2 2260 mutex_unlock(&dev->struct_mutex);
79e53945 2261
198598d0 2262 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2263
2264 return 0;
79e53945
JB		 2265}
2266
5e84e1a4
ZW		 2267static void intel_fdi_normal_train(struct drm_crtc *crtc)
2268{
2269 struct drm_device *dev = crtc->dev;
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2272 int pipe = intel_crtc->pipe;
2273 u32 reg, temp;
2274
2275 /* enable normal train */
2276 reg = FDI_TX_CTL(pipe);
2277 temp = I915_READ(reg);
61e499bf 2278 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2279 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2280 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2281 } else {
2282 temp &= ~FDI_LINK_TRAIN_NONE;
2283 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2284 }
5e84e1a4
ZW		 2285 I915_WRITE(reg, temp);
2286
2287 reg = FDI_RX_CTL(pipe);
2288 temp = I915_READ(reg);
2289 if (HAS_PCH_CPT(dev)) {
2290 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2291 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2292 } else {
2293 temp &= ~FDI_LINK_TRAIN_NONE;
2294 temp |= FDI_LINK_TRAIN_NONE;
2295 }
2296 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2297
2298 /* wait one idle pattern time */
2299 POSTING_READ(reg);
2300 udelay(1000);
357555c0
JB		 2301
2302 /* IVB wants error correction enabled */
2303 if (IS_IVYBRIDGE(dev))
2304 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2305 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2306}
2307
1e833f40
DV		 2308static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2309{
2310 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2311}
2312
01a415fd
DV		 2313static void ivb_modeset_global_resources(struct drm_device *dev)
2314{
2315 struct drm_i915_private *dev_priv = dev->dev_private;
2316 struct intel_crtc *pipe_B_crtc =
2317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2318 struct intel_crtc *pipe_C_crtc =
2319 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2320 uint32_t temp;
2321
1e833f40
DV		 2322 /*
2323 * When everything is off disable fdi C so that we could enable fdi B
2324 * with all lanes. Note that we don't care about enabled pipes without
2325 * an enabled pch encoder.
2326 */
2327 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2328 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2329 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2330 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2331
2332 temp = I915_READ(SOUTH_CHICKEN1);
2333 temp &= ~FDI_BC_BIFURCATION_SELECT;
2334 DRM_DEBUG_KMS("disabling fdi C rx\n");
2335 I915_WRITE(SOUTH_CHICKEN1, temp);
2336 }
2337}
2338
8db9d77b
ZW		 2339/* The FDI link training functions for ILK/Ibexpeak. */
2340static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2341{
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
0fc932b8 2346 int plane = intel_crtc->plane;
5eddb70b 2347 u32 reg, temp, tries;
8db9d77b 2348
0fc932b8
JB		 2349 /* FDI needs bits from pipe & plane first */
2350 assert_pipe_enabled(dev_priv, pipe);
2351 assert_plane_enabled(dev_priv, plane);
2352
e1a44743
AJ		 2353 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2354 for train result */
5eddb70b
CW		 2355 reg = FDI_RX_IMR(pipe);
2356 temp = I915_READ(reg);
e1a44743
AJ		 2357 temp &= ~FDI_RX_SYMBOL_LOCK;
2358 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2359 I915_WRITE(reg, temp);
2360 I915_READ(reg);
e1a44743
AJ		 2361 udelay(150);
2362
8db9d77b 2363 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2364 reg = FDI_TX_CTL(pipe);
2365 temp = I915_READ(reg);
627eb5a3
DV		 2366 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2367 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2368 temp &= ~FDI_LINK_TRAIN_NONE;
2369 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2370 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2371
5eddb70b
CW		 2372 reg = FDI_RX_CTL(pipe);
2373 temp = I915_READ(reg);
8db9d77b
ZW		 2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2376 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2377
2378 POSTING_READ(reg);
8db9d77b
ZW		 2379 udelay(150);
2380
5b2adf89 2381 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2382 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2383 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2384 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2385
5eddb70b 2386 reg = FDI_RX_IIR(pipe);
e1a44743 2387 for (tries = 0; tries < 5; tries++) {
5eddb70b 2388 temp = I915_READ(reg);
8db9d77b
ZW		 2389 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2390
2391 if ((temp & FDI_RX_BIT_LOCK)) {
2392 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2393 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2394 break;
2395 }
8db9d77b 2396 }
e1a44743 2397 if (tries == 5)
5eddb70b 2398 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2399
2400 /* Train 2 */
5eddb70b
CW		 2401 reg = FDI_TX_CTL(pipe);
2402 temp = I915_READ(reg);
8db9d77b
ZW		 2403 temp &= ~FDI_LINK_TRAIN_NONE;
2404 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2405 I915_WRITE(reg, temp);
8db9d77b 2406
5eddb70b
CW		 2407 reg = FDI_RX_CTL(pipe);
2408 temp = I915_READ(reg);
8db9d77b
ZW		 2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2411 I915_WRITE(reg, temp);
8db9d77b 2412
5eddb70b
CW		 2413 POSTING_READ(reg);
2414 udelay(150);
8db9d77b 2415
5eddb70b 2416 reg = FDI_RX_IIR(pipe);
e1a44743 2417 for (tries = 0; tries < 5; tries++) {
5eddb70b 2418 temp = I915_READ(reg);
8db9d77b
ZW		 2419 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2420
2421 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2422 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2423 DRM_DEBUG_KMS("FDI train 2 done.\n");
2424 break;
2425 }
8db9d77b 2426 }
e1a44743 2427 if (tries == 5)
5eddb70b 2428 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2429
2430 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2431
8db9d77b
ZW		 2432}
2433
0206e353 2434static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2435 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2436 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2437 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2438 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2439};
2440
2441/* The FDI link training functions for SNB/Cougarpoint. */
2442static void gen6_fdi_link_train(struct drm_crtc *crtc)
2443{
2444 struct drm_device *dev = crtc->dev;
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447 int pipe = intel_crtc->pipe;
fa37d39e 2448 u32 reg, temp, i, retry;
8db9d77b 2449
e1a44743
AJ		 2450 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2451 for train result */
5eddb70b
CW		 2452 reg = FDI_RX_IMR(pipe);
2453 temp = I915_READ(reg);
e1a44743
AJ		 2454 temp &= ~FDI_RX_SYMBOL_LOCK;
2455 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
e1a44743
AJ		 2459 udelay(150);
2460
8db9d77b 2461 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2462 reg = FDI_TX_CTL(pipe);
2463 temp = I915_READ(reg);
627eb5a3
DV		 2464 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2465 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_1;
2468 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2469 /* SNB-B */
2470 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2471 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2472
d74cf324
DV		 2473 I915_WRITE(FDI_RX_MISC(pipe),
2474 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 if (HAS_PCH_CPT(dev)) {
2479 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2480 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2481 } else {
2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_1;
2484 }
5eddb70b
CW		 2485 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2486
2487 POSTING_READ(reg);
8db9d77b
ZW		 2488 udelay(150);
2489
0206e353 2490 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
8db9d77b
ZW		 2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2495 I915_WRITE(reg, temp);
2496
2497 POSTING_READ(reg);
8db9d77b
ZW		 2498 udelay(500);
2499
fa37d39e
SP		 2500 for (retry = 0; retry < 5; retry++) {
2501 reg = FDI_RX_IIR(pipe);
2502 temp = I915_READ(reg);
2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2504 if (temp & FDI_RX_BIT_LOCK) {
2505 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2506 DRM_DEBUG_KMS("FDI train 1 done.\n");
2507 break;
2508 }
2509 udelay(50);
8db9d77b 2510 }
fa37d39e
SP		 2511 if (retry < 5)
2512 break;
8db9d77b
ZW		 2513 }
2514 if (i == 4)
5eddb70b 2515 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2516
2517 /* Train 2 */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_2;
2522 if (IS_GEN6(dev)) {
2523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2524 /* SNB-B */
2525 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2526 }
5eddb70b 2527 I915_WRITE(reg, temp);
8db9d77b 2528
5eddb70b
CW		 2529 reg = FDI_RX_CTL(pipe);
2530 temp = I915_READ(reg);
8db9d77b
ZW		 2531 if (HAS_PCH_CPT(dev)) {
2532 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2534 } else {
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 }
5eddb70b
CW		 2538 I915_WRITE(reg, temp);
2539
2540 POSTING_READ(reg);
8db9d77b
ZW		 2541 udelay(150);
2542
0206e353 2543 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2544 reg = FDI_TX_CTL(pipe);
2545 temp = I915_READ(reg);
8db9d77b
ZW		 2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
8db9d77b
ZW		 2551 udelay(500);
2552
fa37d39e
SP		 2553 for (retry = 0; retry < 5; retry++) {
2554 reg = FDI_RX_IIR(pipe);
2555 temp = I915_READ(reg);
2556 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2557 if (temp & FDI_RX_SYMBOL_LOCK) {
2558 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2559 DRM_DEBUG_KMS("FDI train 2 done.\n");
2560 break;
2561 }
2562 udelay(50);
8db9d77b 2563 }
fa37d39e
SP		 2564 if (retry < 5)
2565 break;
8db9d77b
ZW		 2566 }
2567 if (i == 4)
5eddb70b 2568 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2569
2570 DRM_DEBUG_KMS("FDI train done.\n");
2571}
2572
357555c0
JB		 2573/* Manual link training for Ivy Bridge A0 parts */
2574static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2575{
2576 struct drm_device *dev = crtc->dev;
2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2579 int pipe = intel_crtc->pipe;
2580 u32 reg, temp, i;
2581
2582 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2583 for train result */
2584 reg = FDI_RX_IMR(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_RX_SYMBOL_LOCK;
2587 temp &= ~FDI_RX_BIT_LOCK;
2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
2591 udelay(150);
2592
01a415fd
DV		 2593 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2594 I915_READ(FDI_RX_IIR(pipe)));
2595
357555c0
JB		 2596 /* enable CPU FDI TX and PCH FDI RX */
2597 reg = FDI_TX_CTL(pipe);
2598 temp = I915_READ(reg);
627eb5a3
DV		 2599 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2600 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2601 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2602 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2604 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2605 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2606 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2607
d74cf324
DV		 2608 I915_WRITE(FDI_RX_MISC(pipe),
2609 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2610
357555c0
JB		 2611 reg = FDI_RX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_AUTO;
2614 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2615 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2616 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2617 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2618
2619 POSTING_READ(reg);
2620 udelay(150);
2621
0206e353 2622 for (i = 0; i < 4; i++) {
357555c0
JB		 2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= snb_b_fdi_train_param[i];
2627 I915_WRITE(reg, temp);
2628
2629 POSTING_READ(reg);
2630 udelay(500);
2631
2632 reg = FDI_RX_IIR(pipe);
2633 temp = I915_READ(reg);
2634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635
2636 if (temp & FDI_RX_BIT_LOCK ||
2637 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2638 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2639 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2640 break;
2641 }
2642 }
2643 if (i == 4)
2644 DRM_ERROR("FDI train 1 fail!\n");
2645
2646 /* Train 2 */
2647 reg = FDI_TX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2653 I915_WRITE(reg, temp);
2654
2655 reg = FDI_RX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
0206e353 2664 for (i = 0; i < 4; i++) {
357555c0
JB		 2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= snb_b_fdi_train_param[i];
2669 I915_WRITE(reg, temp);
2670
2671 POSTING_READ(reg);
2672 udelay(500);
2673
2674 reg = FDI_RX_IIR(pipe);
2675 temp = I915_READ(reg);
2676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2677
2678 if (temp & FDI_RX_SYMBOL_LOCK) {
2679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2680 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2681 break;
2682 }
2683 }
2684 if (i == 4)
2685 DRM_ERROR("FDI train 2 fail!\n");
2686
2687 DRM_DEBUG_KMS("FDI train done.\n");
2688}
2689
88cefb6c 2690static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2691{
88cefb6c 2692 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2693 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2694 int pipe = intel_crtc->pipe;
5eddb70b 2695 u32 reg, temp;
79e53945 2696
c64e311e 2697
c98e9dcf 2698 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
627eb5a3
DV		 2701 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2702 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2703 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2704 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2705
2706 POSTING_READ(reg);
c98e9dcf
JB		 2707 udelay(200);
2708
2709 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2710 temp = I915_READ(reg);
2711 I915_WRITE(reg, temp | FDI_PCDCLK);
2712
2713 POSTING_READ(reg);
c98e9dcf
JB		 2714 udelay(200);
2715
20749730
PZ		 2716 /* Enable CPU FDI TX PLL, always on for Ironlake */
2717 reg = FDI_TX_CTL(pipe);
2718 temp = I915_READ(reg);
2719 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2720 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2721
20749730
PZ		 2722 POSTING_READ(reg);
2723 udelay(100);
6be4a607 2724 }
0e23b99d
JB		 2725}
2726
88cefb6c
DV		 2727static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2728{
2729 struct drm_device *dev = intel_crtc->base.dev;
2730 struct drm_i915_private *dev_priv = dev->dev_private;
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp;
2733
2734 /* Switch from PCDclk to Rawclk */
2735 reg = FDI_RX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2738
2739 /* Disable CPU FDI TX PLL */
2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2743
2744 POSTING_READ(reg);
2745 udelay(100);
2746
2747 reg = FDI_RX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2750
2751 /* Wait for the clocks to turn off. */
2752 POSTING_READ(reg);
2753 udelay(100);
2754}
2755
0fc932b8
JB		 2756static void ironlake_fdi_disable(struct drm_crtc *crtc)
2757{
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int pipe = intel_crtc->pipe;
2762 u32 reg, temp;
2763
2764 /* disable CPU FDI tx and PCH FDI rx */
2765 reg = FDI_TX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2768 POSTING_READ(reg);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 temp &= ~(0x7 << 16);
dfd07d72 2773 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2774 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2775
2776 POSTING_READ(reg);
2777 udelay(100);
2778
2779 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2780 if (HAS_PCH_IBX(dev)) {
2781 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2782 }
0fc932b8
JB		 2783
2784 /* still set train pattern 1 */
2785 reg = FDI_TX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_PATTERN_1;
2789 I915_WRITE(reg, temp);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 if (HAS_PCH_CPT(dev)) {
2794 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2795 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2796 } else {
2797 temp &= ~FDI_LINK_TRAIN_NONE;
2798 temp |= FDI_LINK_TRAIN_PATTERN_1;
2799 }
2800 /* BPC in FDI rx is consistent with that in PIPECONF */
2801 temp &= ~(0x07 << 16);
dfd07d72 2802 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2803 I915_WRITE(reg, temp);
2804
2805 POSTING_READ(reg);
2806 udelay(100);
2807}
2808
5bb61643
CW		 2809static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2810{
2811 struct drm_device *dev = crtc->dev;
2812 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2814 unsigned long flags;
2815 bool pending;
2816
10d83730
VS		 2817 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2818 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2819 return false;
2820
2821 spin_lock_irqsave(&dev->event_lock, flags);
2822 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2823 spin_unlock_irqrestore(&dev->event_lock, flags);
2824
2825 return pending;
2826}
2827
e6c3a2a6
CW		 2828static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2829{
0f91128d 2830 struct drm_device *dev = crtc->dev;
5bb61643 2831 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2832
2833 if (crtc->fb == NULL)
2834 return;
2835
2c10d571
DV		 2836 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2837
5bb61643
CW		 2838 wait_event(dev_priv->pending_flip_queue,
2839 !intel_crtc_has_pending_flip(crtc));
2840
0f91128d
CW		 2841 mutex_lock(&dev->struct_mutex);
2842 intel_finish_fb(crtc->fb);
2843 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2844}
2845
e615efe4
ED		 2846/* Program iCLKIP clock to the desired frequency */
2847static void lpt_program_iclkip(struct drm_crtc *crtc)
2848{
2849 struct drm_device *dev = crtc->dev;
2850 struct drm_i915_private *dev_priv = dev->dev_private;
2851 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2852 u32 temp;
2853
09153000
DV		 2854 mutex_lock(&dev_priv->dpio_lock);
2855
e615efe4
ED		 2856 /* It is necessary to ungate the pixclk gate prior to programming
2857 * the divisors, and gate it back when it is done.
2858 */
2859 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2860
2861 /* Disable SSCCTL */
2862 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2863 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2864 SBI_SSCCTL_DISABLE,
2865 SBI_ICLK);
e615efe4
ED		 2866
2867 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2868 if (crtc->mode.clock == 20000) {
2869 auxdiv = 1;
2870 divsel = 0x41;
2871 phaseinc = 0x20;
2872 } else {
2873 /* The iCLK virtual clock root frequency is in MHz,
2874 * but the crtc->mode.clock in in KHz. To get the divisors,
2875 * it is necessary to divide one by another, so we
2876 * convert the virtual clock precision to KHz here for higher
2877 * precision.
2878 */
2879 u32 iclk_virtual_root_freq = 172800 * 1000;
2880 u32 iclk_pi_range = 64;
2881 u32 desired_divisor, msb_divisor_value, pi_value;
2882
2883 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2884 msb_divisor_value = desired_divisor / iclk_pi_range;
2885 pi_value = desired_divisor % iclk_pi_range;
2886
2887 auxdiv = 0;
2888 divsel = msb_divisor_value - 2;
2889 phaseinc = pi_value;
2890 }
2891
2892 /* This should not happen with any sane values */
2893 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2894 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2895 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2896 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2897
2898 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2899 crtc->mode.clock,
2900 auxdiv,
2901 divsel,
2902 phasedir,
2903 phaseinc);
2904
2905 /* Program SSCDIVINTPHASE6 */
988d6ee8 2906 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2907 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2908 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2909 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2910 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2911 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2912 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2913 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2914
2915 /* Program SSCAUXDIV */
988d6ee8 2916 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2917 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2918 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2919 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2920
2921 /* Enable modulator and associated divider */
988d6ee8 2922 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2923 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2924 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2925
2926 /* Wait for initialization time */
2927 udelay(24);
2928
2929 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2930
2931 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2932}
2933
275f01b2
DV		 2934static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2935 enum pipe pch_transcoder)
2936{
2937 struct drm_device *dev = crtc->base.dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2940
2941 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2942 I915_READ(HTOTAL(cpu_transcoder)));
2943 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2944 I915_READ(HBLANK(cpu_transcoder)));
2945 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2946 I915_READ(HSYNC(cpu_transcoder)));
2947
2948 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2949 I915_READ(VTOTAL(cpu_transcoder)));
2950 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2951 I915_READ(VBLANK(cpu_transcoder)));
2952 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2953 I915_READ(VSYNC(cpu_transcoder)));
2954 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2955 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2956}
2957
f67a559d
JB		 2958/*
2959 * Enable PCH resources required for PCH ports:
2960 * - PCH PLLs
2961 * - FDI training & RX/TX
2962 * - update transcoder timings
2963 * - DP transcoding bits
2964 * - transcoder
2965 */
2966static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2967{
2968 struct drm_device *dev = crtc->dev;
2969 struct drm_i915_private *dev_priv = dev->dev_private;
2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 int pipe = intel_crtc->pipe;
ee7b9f93 2972 u32 reg, temp;
2c07245f 2973
ab9412ba 2974 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2975
cd986abb
DV		 2976 /* Write the TU size bits before fdi link training, so that error
2977 * detection works. */
2978 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2979 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2980
c98e9dcf 2981 /* For PCH output, training FDI link */
674cf967 2982 dev_priv->display.fdi_link_train(crtc);
2c07245f 2983
572deb37
DV		 2984 /* XXX: pch pll's can be enabled any time before we enable the PCH
2985 * transcoder, and we actually should do this to not upset any PCH
2986 * transcoder that already use the clock when we share it.
2987 *
e72f9fbf
DV		 2988 * Note that enable_shared_dpll tries to do the right thing, but
2989 * get_shared_dpll unconditionally resets the pll - we need that to have
2990 * the right LVDS enable sequence. */
2991 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2992
303b81e0 2993 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2994 u32 sel;
4b645f14 2995
c98e9dcf 2996 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2997 temp |= TRANS_DPLL_ENABLE(pipe);
2998 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2999 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3000 temp |= sel;
3001 else
3002 temp &= ~sel;
c98e9dcf 3003 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3004 }
5eddb70b 3005
d9b6cb56
JB		 3006 /* set transcoder timing, panel must allow it */
3007 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3008 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3009
303b81e0 3010 intel_fdi_normal_train(crtc);
5e84e1a4 3011
c98e9dcf
JB		 3012 /* For PCH DP, enable TRANS_DP_CTL */
3013 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3014 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3015 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3016 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3017 reg = TRANS_DP_CTL(pipe);
3018 temp = I915_READ(reg);
3019 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3020 TRANS_DP_SYNC_MASK |
3021 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3022 temp |= (TRANS_DP_OUTPUT_ENABLE |
3023 TRANS_DP_ENH_FRAMING);
9325c9f0 3024 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3025
3026 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3027 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3028 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3029 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3030
3031 switch (intel_trans_dp_port_sel(crtc)) {
3032 case PCH_DP_B:
5eddb70b 3033 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3034 break;
3035 case PCH_DP_C:
5eddb70b 3036 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3037 break;
3038 case PCH_DP_D:
5eddb70b 3039 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3040 break;
3041 default:
e95d41e1 3042 BUG();
32f9d658 3043 }
2c07245f 3044
5eddb70b 3045 I915_WRITE(reg, temp);
6be4a607 3046 }
b52eb4dc 3047
b8a4f404 3048 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3049}
3050
1507e5bd
PZ		 3051static void lpt_pch_enable(struct drm_crtc *crtc)
3052{
3053 struct drm_device *dev = crtc->dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3056 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3057
ab9412ba 3058 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3059
8c52b5e8 3060 lpt_program_iclkip(crtc);
1507e5bd 3061
0540e488 3062 /* Set transcoder timing. */
275f01b2 3063 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3064
937bb610 3065 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3066}
3067
e2b78267 3068static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3069{
e2b78267 3070 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3071
3072 if (pll == NULL)
3073 return;
3074
3075 if (pll->refcount == 0) {
46edb027 3076 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3077 return;
3078 }
3079
f4a091c7
DV		 3080 if (--pll->refcount == 0) {
3081 WARN_ON(pll->on);
3082 WARN_ON(pll->active);
3083 }
3084
a43f6e0f 3085 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3086}
3087
b89a1d39 3088static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3089{
e2b78267
DV		 3090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3091 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3092 enum intel_dpll_id i;
ee7b9f93 3093
ee7b9f93 3094 if (pll) {
46edb027
DV		 3095 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3096 crtc->base.base.id, pll->name);
e2b78267 3097 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3098 }
3099
98b6bd99
DV		 3100 if (HAS_PCH_IBX(dev_priv->dev)) {
3101 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3102 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3103 pll = &dev_priv->shared_dplls[i];
98b6bd99 3104
46edb027
DV		 3105 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3106 crtc->base.base.id, pll->name);
98b6bd99
DV		 3107
3108 goto found;
3109 }
3110
e72f9fbf
DV		 3111 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3112 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3113
3114 /* Only want to check enabled timings first */
3115 if (pll->refcount == 0)
3116 continue;
3117
b89a1d39
DV		 3118 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3119 sizeof(pll->hw_state)) == 0) {
46edb027 3120 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3121 crtc->base.base.id,
46edb027 3122 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3123
3124 goto found;
3125 }
3126 }
3127
3128 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3130 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3131 if (pll->refcount == 0) {
46edb027
DV		 3132 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3133 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3134 goto found;
3135 }
3136 }
3137
3138 return NULL;
3139
3140found:
a43f6e0f 3141 crtc->config.shared_dpll = i;
46edb027
DV		 3142 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3143 pipe_name(crtc->pipe));
ee7b9f93 3144
cdbd2316 3145 if (pll->active == 0) {
66e985c0
DV		 3146 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3147 sizeof(pll->hw_state));
3148
46edb027 3149 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3150 WARN_ON(pll->on);
e9d6944e 3151 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3152
15bdd4cf 3153 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3154 }
3155 pll->refcount++;
e04c7350 3156
ee7b9f93
JB		 3157 return pll;
3158}
3159
a1520318 3160static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3161{
3162 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3163 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3164 u32 temp;
3165
3166 temp = I915_READ(dslreg);
3167 udelay(500);
3168 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3169 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3170 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3171 }
3172}
3173
b074cec8
JB		 3174static void ironlake_pfit_enable(struct intel_crtc *crtc)
3175{
3176 struct drm_device *dev = crtc->base.dev;
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3178 int pipe = crtc->pipe;
3179
0ef37f3f 3180 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3181 /* Force use of hard-coded filter coefficients
3182 * as some pre-programmed values are broken,
3183 * e.g. x201.
3184 */
3185 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3186 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3187 PF_PIPE_SEL_IVB(pipe));
3188 else
3189 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3190 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3191 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3192 }
3193}
3194
bb53d4ae
VS		 3195static void intel_enable_planes(struct drm_crtc *crtc)
3196{
3197 struct drm_device *dev = crtc->dev;
3198 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3199 struct intel_plane *intel_plane;
3200
3201 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3202 if (intel_plane->pipe == pipe)
3203 intel_plane_restore(&intel_plane->base);
3204}
3205
3206static void intel_disable_planes(struct drm_crtc *crtc)
3207{
3208 struct drm_device *dev = crtc->dev;
3209 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3210 struct intel_plane *intel_plane;
3211
3212 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3213 if (intel_plane->pipe == pipe)
3214 intel_plane_disable(&intel_plane->base);
3215}
3216
f67a559d
JB		 3217static void ironlake_crtc_enable(struct drm_crtc *crtc)
3218{
3219 struct drm_device *dev = crtc->dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3222 struct intel_encoder *encoder;
f67a559d
JB		 3223 int pipe = intel_crtc->pipe;
3224 int plane = intel_crtc->plane;
f67a559d 3225
08a48469
DV		 3226 WARN_ON(!crtc->enabled);
3227
f67a559d
JB		 3228 if (intel_crtc->active)
3229 return;
3230
3231 intel_crtc->active = true;
8664281b
PZ		 3232
3233 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3234 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3235
f67a559d
JB		 3236 intel_update_watermarks(dev);
3237
f6736a1a 3238 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3239 if (encoder->pre_enable)
3240 encoder->pre_enable(encoder);
f67a559d 3241
5bfe2ac0 3242 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3243 /* Note: FDI PLL enabling _must_ be done before we enable the
3244 * cpu pipes, hence this is separate from all the other fdi/pch
3245 * enabling. */
88cefb6c 3246 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3247 } else {
3248 assert_fdi_tx_disabled(dev_priv, pipe);
3249 assert_fdi_rx_disabled(dev_priv, pipe);
3250 }
f67a559d 3251
b074cec8 3252 ironlake_pfit_enable(intel_crtc);
f67a559d 3253
9c54c0dd
JB		 3254 /*
3255 * On ILK+ LUT must be loaded before the pipe is running but with
3256 * clocks enabled
3257 */
3258 intel_crtc_load_lut(crtc);
3259
5bfe2ac0
DV		 3260 intel_enable_pipe(dev_priv, pipe,
3261 intel_crtc->config.has_pch_encoder);
f67a559d 3262 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3263 intel_enable_planes(crtc);
5c38d48c 3264 intel_crtc_update_cursor(crtc, true);
f67a559d 3265
5bfe2ac0 3266 if (intel_crtc->config.has_pch_encoder)
f67a559d 3267 ironlake_pch_enable(crtc);
c98e9dcf 3268
d1ebd816 3269 mutex_lock(&dev->struct_mutex);
bed4a673 3270 intel_update_fbc(dev);
d1ebd816
BW		 3271 mutex_unlock(&dev->struct_mutex);
3272
fa5c73b1
DV		 3273 for_each_encoder_on_crtc(dev, crtc, encoder)
3274 encoder->enable(encoder);
61b77ddd
DV		 3275
3276 if (HAS_PCH_CPT(dev))
a1520318 3277 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3278
3279 /*
3280 * There seems to be a race in PCH platform hw (at least on some
3281 * outputs) where an enabled pipe still completes any pageflip right
3282 * away (as if the pipe is off) instead of waiting for vblank. As soon
3283 * as the first vblank happend, everything works as expected. Hence just
3284 * wait for one vblank before returning to avoid strange things
3285 * happening.
3286 */
3287 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3288}
3289
42db64ef
PZ		 3290/* IPS only exists on ULT machines and is tied to pipe A. */
3291static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3292{
f5adf94e 3293 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3294}
3295
3296static void hsw_enable_ips(struct intel_crtc *crtc)
3297{
3298 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3299
3300 if (!crtc->config.ips_enabled)
3301 return;
3302
3303 /* We can only enable IPS after we enable a plane and wait for a vblank.
3304 * We guarantee that the plane is enabled by calling intel_enable_ips
3305 * only after intel_enable_plane. And intel_enable_plane already waits
3306 * for a vblank, so all we need to do here is to enable the IPS bit. */
3307 assert_plane_enabled(dev_priv, crtc->plane);
3308 I915_WRITE(IPS_CTL, IPS_ENABLE);
3309}
3310
3311static void hsw_disable_ips(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315
3316 if (!crtc->config.ips_enabled)
3317 return;
3318
3319 assert_plane_enabled(dev_priv, crtc->plane);
3320 I915_WRITE(IPS_CTL, 0);
3321
3322 /* We need to wait for a vblank before we can disable the plane. */
3323 intel_wait_for_vblank(dev, crtc->pipe);
3324}
3325
4f771f10
PZ		 3326static void haswell_crtc_enable(struct drm_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331 struct intel_encoder *encoder;
3332 int pipe = intel_crtc->pipe;
3333 int plane = intel_crtc->plane;
4f771f10
PZ		 3334
3335 WARN_ON(!crtc->enabled);
3336
3337 if (intel_crtc->active)
3338 return;
3339
3340 intel_crtc->active = true;
8664281b
PZ		 3341
3342 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3343 if (intel_crtc->config.has_pch_encoder)
3344 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3345
4f771f10
PZ		 3346 intel_update_watermarks(dev);
3347
5bfe2ac0 3348 if (intel_crtc->config.has_pch_encoder)
04945641 3349 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3350
3351 for_each_encoder_on_crtc(dev, crtc, encoder)
3352 if (encoder->pre_enable)
3353 encoder->pre_enable(encoder);
3354
1f544388 3355 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3356
b074cec8 3357 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3358
3359 /*
3360 * On ILK+ LUT must be loaded before the pipe is running but with
3361 * clocks enabled
3362 */
3363 intel_crtc_load_lut(crtc);
3364
1f544388 3365 intel_ddi_set_pipe_settings(crtc);
8228c251 3366 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3367
5bfe2ac0
DV		 3368 intel_enable_pipe(dev_priv, pipe,
3369 intel_crtc->config.has_pch_encoder);
4f771f10 3370 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3371 intel_enable_planes(crtc);
5c38d48c 3372 intel_crtc_update_cursor(crtc, true);
4f771f10 3373
42db64ef
PZ		 3374 hsw_enable_ips(intel_crtc);
3375
5bfe2ac0 3376 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3377 lpt_pch_enable(crtc);
4f771f10
PZ		 3378
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3382
4f771f10
PZ		 3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->enable(encoder);
3385
4f771f10
PZ		 3386 /*
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3392 * happening.
3393 */
3394 intel_wait_for_vblank(dev, intel_crtc->pipe);
3395}
3396
3f8dce3a
DV		 3397static void ironlake_pfit_disable(struct intel_crtc *crtc)
3398{
3399 struct drm_device *dev = crtc->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 int pipe = crtc->pipe;
3402
3403 /* To avoid upsetting the power well on haswell only disable the pfit if
3404 * it's in use. The hw state code will make sure we get this right. */
3405 if (crtc->config.pch_pfit.size) {
3406 I915_WRITE(PF_CTL(pipe), 0);
3407 I915_WRITE(PF_WIN_POS(pipe), 0);
3408 I915_WRITE(PF_WIN_SZ(pipe), 0);
3409 }
3410}
3411
6be4a607
JB		 3412static void ironlake_crtc_disable(struct drm_crtc *crtc)
3413{
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3417 struct intel_encoder *encoder;
6be4a607
JB		 3418 int pipe = intel_crtc->pipe;
3419 int plane = intel_crtc->plane;
5eddb70b 3420 u32 reg, temp;
b52eb4dc 3421
ef9c3aee 3422
f7abfe8b
CW		 3423 if (!intel_crtc->active)
3424 return;
3425
ea9d758d
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->disable(encoder);
3428
e6c3a2a6 3429 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3430 drm_vblank_off(dev, pipe);
913d8d11 3431
5c3fe8b0 3432 if (dev_priv->fbc.plane == plane)
973d04f9 3433 intel_disable_fbc(dev);
2c07245f 3434
0d5b8c61 3435 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3436 intel_disable_planes(crtc);
0d5b8c61
VS		 3437 intel_disable_plane(dev_priv, plane, pipe);
3438
d925c59a
DV		 3439 if (intel_crtc->config.has_pch_encoder)
3440 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3441
b24e7179 3442 intel_disable_pipe(dev_priv, pipe);
32f9d658 3443
3f8dce3a 3444 ironlake_pfit_disable(intel_crtc);
2c07245f 3445
bf49ec8c
DV		 3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 if (encoder->post_disable)
3448 encoder->post_disable(encoder);
2c07245f 3449
d925c59a
DV		 3450 if (intel_crtc->config.has_pch_encoder) {
3451 ironlake_fdi_disable(crtc);
913d8d11 3452
d925c59a
DV		 3453 ironlake_disable_pch_transcoder(dev_priv, pipe);
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3455
d925c59a
DV		 3456 if (HAS_PCH_CPT(dev)) {
3457 /* disable TRANS_DP_CTL */
3458 reg = TRANS_DP_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3461 TRANS_DP_PORT_SEL_MASK);
3462 temp |= TRANS_DP_PORT_SEL_NONE;
3463 I915_WRITE(reg, temp);
3464
3465 /* disable DPLL_SEL */
3466 temp = I915_READ(PCH_DPLL_SEL);
11887397 3467 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3468 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3469 }
e3421a18 3470
d925c59a 3471 /* disable PCH DPLL */
e72f9fbf 3472 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3473
d925c59a
DV		 3474 ironlake_fdi_pll_disable(intel_crtc);
3475 }
6b383a7f 3476
f7abfe8b 3477 intel_crtc->active = false;
6b383a7f 3478 intel_update_watermarks(dev);
d1ebd816
BW		 3479
3480 mutex_lock(&dev->struct_mutex);
6b383a7f 3481 intel_update_fbc(dev);
d1ebd816 3482 mutex_unlock(&dev->struct_mutex);
6be4a607 3483}
1b3c7a47 3484
4f771f10 3485static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3486{
4f771f10
PZ		 3487 struct drm_device *dev = crtc->dev;
3488 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3490 struct intel_encoder *encoder;
3491 int pipe = intel_crtc->pipe;
3492 int plane = intel_crtc->plane;
3b117c8f 3493 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3494
4f771f10
PZ		 3495 if (!intel_crtc->active)
3496 return;
3497
3498 for_each_encoder_on_crtc(dev, crtc, encoder)
3499 encoder->disable(encoder);
3500
3501 intel_crtc_wait_for_pending_flips(crtc);
3502 drm_vblank_off(dev, pipe);
4f771f10 3503
891348b2 3504 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3505 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3506 intel_disable_fbc(dev);
3507
42db64ef
PZ		 3508 hsw_disable_ips(intel_crtc);
3509
0d5b8c61 3510 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3511 intel_disable_planes(crtc);
891348b2
RV		 3512 intel_disable_plane(dev_priv, plane, pipe);
3513
8664281b
PZ		 3514 if (intel_crtc->config.has_pch_encoder)
3515 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3516 intel_disable_pipe(dev_priv, pipe);
3517
ad80a810 3518 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3519
3f8dce3a 3520 ironlake_pfit_disable(intel_crtc);
4f771f10 3521
1f544388 3522 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3523
3524 for_each_encoder_on_crtc(dev, crtc, encoder)
3525 if (encoder->post_disable)
3526 encoder->post_disable(encoder);
3527
88adfff1 3528 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3529 lpt_disable_pch_transcoder(dev_priv);
8664281b 3530 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3531 intel_ddi_fdi_disable(crtc);
83616634 3532 }
4f771f10
PZ		 3533
3534 intel_crtc->active = false;
3535 intel_update_watermarks(dev);
3536
3537 mutex_lock(&dev->struct_mutex);
3538 intel_update_fbc(dev);
3539 mutex_unlock(&dev->struct_mutex);
3540}
3541
ee7b9f93
JB		 3542static void ironlake_crtc_off(struct drm_crtc *crtc)
3543{
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3545 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3546}
3547
6441ab5f
PZ		 3548static void haswell_crtc_off(struct drm_crtc *crtc)
3549{
3550 intel_ddi_put_crtc_pll(crtc);
3551}
3552
02e792fb
DV		 3553static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3554{
02e792fb 3555 if (!enable && intel_crtc->overlay) {
23f09ce3 3556 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3557 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3558
23f09ce3 3559 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3560 dev_priv->mm.interruptible = false;
3561 (void) intel_overlay_switch_off(intel_crtc->overlay);
3562 dev_priv->mm.interruptible = true;
23f09ce3 3563 mutex_unlock(&dev->struct_mutex);
02e792fb 3564 }
02e792fb 3565
5dcdbcb0
CW		 3566 /* Let userspace switch the overlay on again. In most cases userspace
3567 * has to recompute where to put it anyway.
3568 */
02e792fb
DV		 3569}
3570
61bc95c1
EE		 3571/**
3572 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3573 * cursor plane briefly if not already running after enabling the display
3574 * plane.
3575 * This workaround avoids occasional blank screens when self refresh is
3576 * enabled.
3577 */
3578static void
3579g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3580{
3581 u32 cntl = I915_READ(CURCNTR(pipe));
3582
3583 if ((cntl & CURSOR_MODE) == 0) {
3584 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3585
3586 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3587 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3588 intel_wait_for_vblank(dev_priv->dev, pipe);
3589 I915_WRITE(CURCNTR(pipe), cntl);
3590 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3591 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3592 }
3593}
3594
2dd24552
JB		 3595static void i9xx_pfit_enable(struct intel_crtc *crtc)
3596{
3597 struct drm_device *dev = crtc->base.dev;
3598 struct drm_i915_private *dev_priv = dev->dev_private;
3599 struct intel_crtc_config *pipe_config = &crtc->config;
3600
328d8e82 3601 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3602 return;
3603
2dd24552 3604 /*
c0b03411
DV		 3605 * The panel fitter should only be adjusted whilst the pipe is disabled,
3606 * according to register description and PRM.
2dd24552 3607 */
c0b03411
DV		 3608 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3609 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3610
b074cec8
JB		 3611 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3612 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3613
3614 /* Border color in case we don't scale up to the full screen. Black by
3615 * default, change to something else for debugging. */
3616 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3617}
3618
89b667f8
JB		 3619static void valleyview_crtc_enable(struct drm_crtc *crtc)
3620{
3621 struct drm_device *dev = crtc->dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 struct intel_encoder *encoder;
3625 int pipe = intel_crtc->pipe;
3626 int plane = intel_crtc->plane;
3627
3628 WARN_ON(!crtc->enabled);
3629
3630 if (intel_crtc->active)
3631 return;
3632
3633 intel_crtc->active = true;
3634 intel_update_watermarks(dev);
3635
3636 mutex_lock(&dev_priv->dpio_lock);
3637
3638 for_each_encoder_on_crtc(dev, crtc, encoder)
3639 if (encoder->pre_pll_enable)
3640 encoder->pre_pll_enable(encoder);
3641
87442f73 3642 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3643
3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 if (encoder->pre_enable)
3646 encoder->pre_enable(encoder);
3647
3648 /* VLV wants encoder enabling _before_ the pipe is up. */
3649 for_each_encoder_on_crtc(dev, crtc, encoder)
3650 encoder->enable(encoder);
3651
2dd24552
JB		 3652 i9xx_pfit_enable(intel_crtc);
3653
63cbb074
VS		 3654 intel_crtc_load_lut(crtc);
3655
89b667f8
JB		 3656 intel_enable_pipe(dev_priv, pipe, false);
3657 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3658 intel_enable_planes(crtc);
5c38d48c 3659 intel_crtc_update_cursor(crtc, true);
89b667f8 3660
89b667f8
JB		 3661 intel_update_fbc(dev);
3662
89b667f8
JB		 3663 mutex_unlock(&dev_priv->dpio_lock);
3664}
3665
0b8765c6 3666static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3667{
3668 struct drm_device *dev = crtc->dev;
79e53945
JB		 3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3671 struct intel_encoder *encoder;
79e53945 3672 int pipe = intel_crtc->pipe;
80824003 3673 int plane = intel_crtc->plane;
79e53945 3674
08a48469
DV		 3675 WARN_ON(!crtc->enabled);
3676
f7abfe8b
CW		 3677 if (intel_crtc->active)
3678 return;
3679
3680 intel_crtc->active = true;
6b383a7f
CW		 3681 intel_update_watermarks(dev);
3682
9d6d9f19
MK		 3683 for_each_encoder_on_crtc(dev, crtc, encoder)
3684 if (encoder->pre_enable)
3685 encoder->pre_enable(encoder);
3686
f6736a1a
DV		 3687 i9xx_enable_pll(intel_crtc);
3688
2dd24552
JB		 3689 i9xx_pfit_enable(intel_crtc);
3690
63cbb074
VS		 3691 intel_crtc_load_lut(crtc);
3692
040484af 3693 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3694 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3695 intel_enable_planes(crtc);
22e407d7 3696 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3697 if (IS_G4X(dev))
3698 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3699 intel_crtc_update_cursor(crtc, true);
79e53945 3700
0b8765c6
JB		 3701 /* Give the overlay scaler a chance to enable if it's on this pipe */
3702 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3703
f440eb13 3704 intel_update_fbc(dev);
ef9c3aee 3705
fa5c73b1
DV		 3706 for_each_encoder_on_crtc(dev, crtc, encoder)
3707 encoder->enable(encoder);
0b8765c6 3708}
79e53945 3709
87476d63
DV		 3710static void i9xx_pfit_disable(struct intel_crtc *crtc)
3711{
3712 struct drm_device *dev = crtc->base.dev;
3713 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3714
328d8e82
DV		 3715 if (!crtc->config.gmch_pfit.control)
3716 return;
87476d63 3717
328d8e82 3718 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3719
328d8e82
DV		 3720 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3721 I915_READ(PFIT_CONTROL));
3722 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3723}
3724
0b8765c6
JB		 3725static void i9xx_crtc_disable(struct drm_crtc *crtc)
3726{
3727 struct drm_device *dev = crtc->dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3730 struct intel_encoder *encoder;
0b8765c6
JB		 3731 int pipe = intel_crtc->pipe;
3732 int plane = intel_crtc->plane;
ef9c3aee 3733
f7abfe8b
CW		 3734 if (!intel_crtc->active)
3735 return;
3736
ea9d758d
DV		 3737 for_each_encoder_on_crtc(dev, crtc, encoder)
3738 encoder->disable(encoder);
3739
0b8765c6 3740 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3741 intel_crtc_wait_for_pending_flips(crtc);
3742 drm_vblank_off(dev, pipe);
0b8765c6 3743
5c3fe8b0 3744 if (dev_priv->fbc.plane == plane)
973d04f9 3745 intel_disable_fbc(dev);
79e53945 3746
0d5b8c61
VS		 3747 intel_crtc_dpms_overlay(intel_crtc, false);
3748 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3749 intel_disable_planes(crtc);
b24e7179 3750 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3751
b24e7179 3752 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3753
87476d63 3754 i9xx_pfit_disable(intel_crtc);
24a1f16d 3755
89b667f8
JB		 3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 if (encoder->post_disable)
3758 encoder->post_disable(encoder);
3759
63d7bbe9 3760 intel_disable_pll(dev_priv, pipe);
0b8765c6 3761
f7abfe8b 3762 intel_crtc->active = false;
6b383a7f
CW		 3763 intel_update_fbc(dev);
3764 intel_update_watermarks(dev);
0b8765c6
JB		 3765}
3766
ee7b9f93
JB		 3767static void i9xx_crtc_off(struct drm_crtc *crtc)
3768{
3769}
3770
976f8a20
DV		 3771static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3772 bool enabled)
2c07245f
ZW		 3773{
3774 struct drm_device *dev = crtc->dev;
3775 struct drm_i915_master_private *master_priv;
3776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777 int pipe = intel_crtc->pipe;
79e53945
JB		 3778
3779 if (!dev->primary->master)
3780 return;
3781
3782 master_priv = dev->primary->master->driver_priv;
3783 if (!master_priv->sarea_priv)
3784 return;
3785
79e53945
JB		 3786 switch (pipe) {
3787 case 0:
3788 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3789 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3790 break;
3791 case 1:
3792 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3793 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3794 break;
3795 default:
9db4a9c7 3796 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3797 break;
3798 }
79e53945
JB		 3799}
3800
976f8a20
DV		 3801/**
3802 * Sets the power management mode of the pipe and plane.
3803 */
3804void intel_crtc_update_dpms(struct drm_crtc *crtc)
3805{
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_encoder *intel_encoder;
3809 bool enable = false;
3810
3811 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3812 enable |= intel_encoder->connectors_active;
3813
3814 if (enable)
3815 dev_priv->display.crtc_enable(crtc);
3816 else
3817 dev_priv->display.crtc_disable(crtc);
3818
3819 intel_crtc_update_sarea(crtc, enable);
3820}
3821
cdd59983
CW		 3822static void intel_crtc_disable(struct drm_crtc *crtc)
3823{
cdd59983 3824 struct drm_device *dev = crtc->dev;
976f8a20 3825 struct drm_connector *connector;
ee7b9f93 3826 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3828
976f8a20
DV		 3829 /* crtc should still be enabled when we disable it. */
3830 WARN_ON(!crtc->enabled);
3831
3832 dev_priv->display.crtc_disable(crtc);
c77bf565 3833 intel_crtc->eld_vld = false;
976f8a20 3834 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3835 dev_priv->display.off(crtc);
3836
931872fc
CW		 3837 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3838 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3839
3840 if (crtc->fb) {
3841 mutex_lock(&dev->struct_mutex);
1690e1eb 3842 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3843 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3844 crtc->fb = NULL;
3845 }
3846
3847 /* Update computed state. */
3848 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3849 if (!connector->encoder || !connector->encoder->crtc)
3850 continue;
3851
3852 if (connector->encoder->crtc != crtc)
3853 continue;
3854
3855 connector->dpms = DRM_MODE_DPMS_OFF;
3856 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3857 }
3858}
3859
a261b246 3860void intel_modeset_disable(struct drm_device *dev)
79e53945 3861{
a261b246
DV		 3862 struct drm_crtc *crtc;
3863
3864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3865 if (crtc->enabled)
3866 intel_crtc_disable(crtc);
3867 }
79e53945
JB		 3868}
3869
ea5b213a 3870void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3871{
4ef69c7a 3872 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3873
ea5b213a
CW		 3874 drm_encoder_cleanup(encoder);
3875 kfree(intel_encoder);
7e7d76c3
JB		 3876}
3877
5ab432ef
DV		 3878/* Simple dpms helper for encodres with just one connector, no cloning and only
3879 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3880 * state of the entire output pipe. */
3881void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3882{
5ab432ef
DV		 3883 if (mode == DRM_MODE_DPMS_ON) {
3884 encoder->connectors_active = true;
3885
b2cabb0e 3886 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3887 } else {
3888 encoder->connectors_active = false;
3889
b2cabb0e 3890 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3891 }
79e53945
JB		 3892}
3893
0a91ca29
DV		 3894/* Cross check the actual hw state with our own modeset state tracking (and it's
3895 * internal consistency). */
b980514c 3896static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3897{
0a91ca29
DV		 3898 if (connector->get_hw_state(connector)) {
3899 struct intel_encoder *encoder = connector->encoder;
3900 struct drm_crtc *crtc;
3901 bool encoder_enabled;
3902 enum pipe pipe;
3903
3904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3905 connector->base.base.id,
3906 drm_get_connector_name(&connector->base));
3907
3908 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3909 "wrong connector dpms state\n");
3910 WARN(connector->base.encoder != &encoder->base,
3911 "active connector not linked to encoder\n");
3912 WARN(!encoder->connectors_active,
3913 "encoder->connectors_active not set\n");
3914
3915 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3916 WARN(!encoder_enabled, "encoder not enabled\n");
3917 if (WARN_ON(!encoder->base.crtc))
3918 return;
3919
3920 crtc = encoder->base.crtc;
3921
3922 WARN(!crtc->enabled, "crtc not enabled\n");
3923 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3924 WARN(pipe != to_intel_crtc(crtc)->pipe,
3925 "encoder active on the wrong pipe\n");
3926 }
79e53945
JB		 3927}
3928
5ab432ef
DV		 3929/* Even simpler default implementation, if there's really no special case to
3930 * consider. */
3931void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3932{
5ab432ef 3933 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3934
5ab432ef
DV		 3935 /* All the simple cases only support two dpms states. */
3936 if (mode != DRM_MODE_DPMS_ON)
3937 mode = DRM_MODE_DPMS_OFF;
d4270e57 3938
5ab432ef
DV		 3939 if (mode == connector->dpms)
3940 return;
3941
3942 connector->dpms = mode;
3943
3944 /* Only need to change hw state when actually enabled */
3945 if (encoder->base.crtc)
3946 intel_encoder_dpms(encoder, mode);
3947 else
8af6cf88 3948 WARN_ON(encoder->connectors_active != false);
0a91ca29 3949
b980514c 3950 intel_modeset_check_state(connector->dev);
79e53945
JB		 3951}
3952
f0947c37
DV		 3953/* Simple connector->get_hw_state implementation for encoders that support only
3954 * one connector and no cloning and hence the encoder state determines the state
3955 * of the connector. */
3956bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3957{
24929352 3958 enum pipe pipe = 0;
f0947c37 3959 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3960
f0947c37 3961 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3962}
3963
1857e1da
DV		 3964static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3965 struct intel_crtc_config *pipe_config)
3966{
3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968 struct intel_crtc *pipe_B_crtc =
3969 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3970
3971 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3972 pipe_name(pipe), pipe_config->fdi_lanes);
3973 if (pipe_config->fdi_lanes > 4) {
3974 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3975 pipe_name(pipe), pipe_config->fdi_lanes);
3976 return false;
3977 }
3978
3979 if (IS_HASWELL(dev)) {
3980 if (pipe_config->fdi_lanes > 2) {
3981 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3982 pipe_config->fdi_lanes);
3983 return false;
3984 } else {
3985 return true;
3986 }
3987 }
3988
3989 if (INTEL_INFO(dev)->num_pipes == 2)
3990 return true;
3991
3992 /* Ivybridge 3 pipe is really complicated */
3993 switch (pipe) {
3994 case PIPE_A:
3995 return true;
3996 case PIPE_B:
3997 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3998 pipe_config->fdi_lanes > 2) {
3999 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4000 pipe_name(pipe), pipe_config->fdi_lanes);
4001 return false;
4002 }
4003 return true;
4004 case PIPE_C:
1e833f40 4005 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4006 pipe_B_crtc->config.fdi_lanes <= 2) {
4007 if (pipe_config->fdi_lanes > 2) {
4008 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4009 pipe_name(pipe), pipe_config->fdi_lanes);
4010 return false;
4011 }
4012 } else {
4013 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4014 return false;
4015 }
4016 return true;
4017 default:
4018 BUG();
4019 }
4020}
4021
e29c22c0
DV		 4022#define RETRY 1
4023static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4024 struct intel_crtc_config *pipe_config)
877d48d5 4025{
1857e1da 4026 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4027 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4028 int lane, link_bw, fdi_dotclock;
e29c22c0 4029 bool setup_ok, needs_recompute = false;
877d48d5 4030
e29c22c0 4031retry:
877d48d5
DV		 4032 /* FDI is a binary signal running at ~2.7GHz, encoding
4033 * each output octet as 10 bits. The actual frequency
4034 * is stored as a divider into a 100MHz clock, and the
4035 * mode pixel clock is stored in units of 1KHz.
4036 * Hence the bw of each lane in terms of the mode signal
4037 * is:
4038 */
4039 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4040
ff9a6750 4041 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4042 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4043
2bd89a07 4044 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4045 pipe_config->pipe_bpp);
4046
4047 pipe_config->fdi_lanes = lane;
4048
2bd89a07 4049 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4050 link_bw, &pipe_config->fdi_m_n);
1857e1da 4051
e29c22c0
DV		 4052 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4053 intel_crtc->pipe, pipe_config);
4054 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4055 pipe_config->pipe_bpp -= 2*3;
4056 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4057 pipe_config->pipe_bpp);
4058 needs_recompute = true;
4059 pipe_config->bw_constrained = true;
4060
4061 goto retry;
4062 }
4063
4064 if (needs_recompute)
4065 return RETRY;
4066
4067 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4068}
4069
42db64ef
PZ		 4070static void hsw_compute_ips_config(struct intel_crtc *crtc,
4071 struct intel_crtc_config *pipe_config)
4072{
3c4ca58c
PZ		 4073 pipe_config->ips_enabled = i915_enable_ips &&
4074 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4075 pipe_config->pipe_bpp == 24;
4076}
4077
a43f6e0f 4078static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4079 struct intel_crtc_config *pipe_config)
79e53945 4080{
a43f6e0f 4081 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4082 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4083
bad720ff 4084 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4085 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4086 if (pipe_config->requested_mode.clock * 3
4087 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4088 return -EINVAL;
2c07245f 4089 }
89749350 4090
f9bef081
DV		 4091 /* All interlaced capable intel hw wants timings in frames. Note though
4092 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4093 * timings, so we need to be careful not to clobber these.*/
7ae89233 4094 if (!pipe_config->timings_set)
f9bef081 4095 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4096
8693a824
DL		 4097 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4098 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4099 */
4100 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4101 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4102 return -EINVAL;
44f46b42 4103
bd080ee5 4104 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4105 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4106 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4107 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4108 * for lvds. */
4109 pipe_config->pipe_bpp = 8*3;
4110 }
4111
f5adf94e 4112 if (HAS_IPS(dev))
a43f6e0f
DV		 4113 hsw_compute_ips_config(crtc, pipe_config);
4114
4115 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4116 * clock survives for now. */
4117 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4118 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4119
877d48d5 4120 if (pipe_config->has_pch_encoder)
a43f6e0f 4121 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4122
e29c22c0 4123 return 0;
79e53945
JB		 4124}
4125
25eb05fc
JB		 4126static int valleyview_get_display_clock_speed(struct drm_device *dev)
4127{
4128 return 400000; /* FIXME */
4129}
4130
e70236a8
JB		 4131static int i945_get_display_clock_speed(struct drm_device *dev)
4132{
4133 return 400000;
4134}
79e53945 4135
e70236a8 4136static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4137{
e70236a8
JB		 4138 return 333000;
4139}
79e53945 4140
e70236a8
JB		 4141static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4142{
4143 return 200000;
4144}
79e53945 4145
e70236a8
JB		 4146static int i915gm_get_display_clock_speed(struct drm_device *dev)
4147{
4148 u16 gcfgc = 0;
79e53945 4149
e70236a8
JB		 4150 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4151
4152 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4153 return 133000;
4154 else {
4155 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4156 case GC_DISPLAY_CLOCK_333_MHZ:
4157 return 333000;
4158 default:
4159 case GC_DISPLAY_CLOCK_190_200_MHZ:
4160 return 190000;
79e53945 4161 }
e70236a8
JB		 4162 }
4163}
4164
4165static int i865_get_display_clock_speed(struct drm_device *dev)
4166{
4167 return 266000;
4168}
4169
4170static int i855_get_display_clock_speed(struct drm_device *dev)
4171{
4172 u16 hpllcc = 0;
4173 /* Assume that the hardware is in the high speed state. This
4174 * should be the default.
4175 */
4176 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4177 case GC_CLOCK_133_200:
4178 case GC_CLOCK_100_200:
4179 return 200000;
4180 case GC_CLOCK_166_250:
4181 return 250000;
4182 case GC_CLOCK_100_133:
79e53945 4183 return 133000;
e70236a8 4184 }
79e53945 4185
e70236a8
JB		 4186 /* Shouldn't happen */
4187 return 0;
4188}
79e53945 4189
e70236a8
JB		 4190static int i830_get_display_clock_speed(struct drm_device *dev)
4191{
4192 return 133000;
79e53945
JB		 4193}
4194
2c07245f 4195static void
a65851af 4196intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4197{
a65851af
VS		 4198 while (*num > DATA_LINK_M_N_MASK ||
4199 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4200 *num >>= 1;
4201 *den >>= 1;
4202 }
4203}
4204
a65851af
VS		 4205static void compute_m_n(unsigned int m, unsigned int n,
4206 uint32_t *ret_m, uint32_t *ret_n)
4207{
4208 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4209 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4210 intel_reduce_m_n_ratio(ret_m, ret_n);
4211}
4212
e69d0bc1
DV		 4213void
4214intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4215 int pixel_clock, int link_clock,
4216 struct intel_link_m_n *m_n)
2c07245f 4217{
e69d0bc1 4218 m_n->tu = 64;
a65851af
VS		 4219
4220 compute_m_n(bits_per_pixel * pixel_clock,
4221 link_clock * nlanes * 8,
4222 &m_n->gmch_m, &m_n->gmch_n);
4223
4224 compute_m_n(pixel_clock, link_clock,
4225 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4226}
4227
a7615030
CW		 4228static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4229{
72bbe58c
KP		 4230 if (i915_panel_use_ssc >= 0)
4231 return i915_panel_use_ssc != 0;
41aa3448 4232 return dev_priv->vbt.lvds_use_ssc
435793df 4233 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4234}
4235
a0c4da24
JB		 4236static int vlv_get_refclk(struct drm_crtc *crtc)
4237{
4238 struct drm_device *dev = crtc->dev;
4239 struct drm_i915_private *dev_priv = dev->dev_private;
4240 int refclk = 27000; /* for DP & HDMI */
4241
4242 return 100000; /* only one validated so far */
4243
4244 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4245 refclk = 96000;
4246 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4247 if (intel_panel_use_ssc(dev_priv))
4248 refclk = 100000;
4249 else
4250 refclk = 96000;
4251 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4252 refclk = 100000;
4253 }
4254
4255 return refclk;
4256}
4257
c65d77d8
JB		 4258static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4259{
4260 struct drm_device *dev = crtc->dev;
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 int refclk;
4263
a0c4da24
JB		 4264 if (IS_VALLEYVIEW(dev)) {
4265 refclk = vlv_get_refclk(crtc);
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4267 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4268 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4269 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4270 refclk / 1000);
4271 } else if (!IS_GEN2(dev)) {
4272 refclk = 96000;
4273 } else {
4274 refclk = 48000;
4275 }
4276
4277 return refclk;
4278}
4279
7429e9d4 4280static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4281{
7df00d7a 4282 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4283}
f47709a9 4284
7429e9d4
DV		 4285static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4286{
4287 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4288}
4289
f47709a9 4290static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4291 intel_clock_t *reduced_clock)
4292{
f47709a9 4293 struct drm_device *dev = crtc->base.dev;
a7516a05 4294 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4295 int pipe = crtc->pipe;
a7516a05
JB		 4296 u32 fp, fp2 = 0;
4297
4298 if (IS_PINEVIEW(dev)) {
7429e9d4 4299 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4300 if (reduced_clock)
7429e9d4 4301 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4302 } else {
7429e9d4 4303 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4304 if (reduced_clock)
7429e9d4 4305 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4306 }
4307
4308 I915_WRITE(FP0(pipe), fp);
8bcc2795 4309 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4310
f47709a9
DV		 4311 crtc->lowfreq_avail = false;
4312 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4313 reduced_clock && i915_powersave) {
4314 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4315 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4316 crtc->lowfreq_avail = true;
a7516a05
JB		 4317 } else {
4318 I915_WRITE(FP1(pipe), fp);
8bcc2795 4319 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4320 }
4321}
4322
89b667f8
JB		 4323static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4324{
4325 u32 reg_val;
4326
4327 /*
4328 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4329 * and set it to a reasonable value instead.
4330 */
ae99258f 4331 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4332 reg_val &= 0xffffff00;
4333 reg_val |= 0x00000030;
ae99258f 4334 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4335
ae99258f 4336 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4337 reg_val &= 0x8cffffff;
4338 reg_val = 0x8c000000;
ae99258f 4339 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4340
ae99258f 4341 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4342 reg_val &= 0xffffff00;
ae99258f 4343 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4344
ae99258f 4345 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4346 reg_val &= 0x00ffffff;
4347 reg_val |= 0xb0000000;
ae99258f 4348 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4349}
4350
b551842d
DV		 4351static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4352 struct intel_link_m_n *m_n)
4353{
4354 struct drm_device *dev = crtc->base.dev;
4355 struct drm_i915_private *dev_priv = dev->dev_private;
4356 int pipe = crtc->pipe;
4357
e3b95f1e
DV		 4358 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4359 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4360 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4361 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4362}
4363
4364static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4365 struct intel_link_m_n *m_n)
4366{
4367 struct drm_device *dev = crtc->base.dev;
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 int pipe = crtc->pipe;
4370 enum transcoder transcoder = crtc->config.cpu_transcoder;
4371
4372 if (INTEL_INFO(dev)->gen >= 5) {
4373 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4375 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4376 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4377 } else {
e3b95f1e
DV		 4378 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4380 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4381 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4382 }
4383}
4384
03afc4a2
DV		 4385static void intel_dp_set_m_n(struct intel_crtc *crtc)
4386{
4387 if (crtc->config.has_pch_encoder)
4388 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389 else
4390 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4391}
4392
f47709a9 4393static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4394{
f47709a9 4395 struct drm_device *dev = crtc->base.dev;
a0c4da24 4396 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4397 struct intel_encoder *encoder;
f47709a9 4398 int pipe = crtc->pipe;
89b667f8 4399 u32 dpll, mdiv;
a0c4da24 4400 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4401 bool is_hdmi;
198a037f 4402 u32 coreclk, reg_val, dpll_md;
a0c4da24 4403
09153000
DV		 4404 mutex_lock(&dev_priv->dpio_lock);
4405
89b667f8 4406 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4407
f47709a9
DV		 4408 bestn = crtc->config.dpll.n;
4409 bestm1 = crtc->config.dpll.m1;
4410 bestm2 = crtc->config.dpll.m2;
4411 bestp1 = crtc->config.dpll.p1;
4412 bestp2 = crtc->config.dpll.p2;
a0c4da24 4413
89b667f8
JB		 4414 /* See eDP HDMI DPIO driver vbios notes doc */
4415
4416 /* PLL B needs special handling */
4417 if (pipe)
4418 vlv_pllb_recal_opamp(dev_priv);
4419
4420 /* Set up Tx target for periodic Rcomp update */
ae99258f 4421 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4422
4423 /* Disable target IRef on PLL */
ae99258f 4424 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4425 reg_val &= 0x00ffffff;
ae99258f 4426 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4427
4428 /* Disable fast lock */
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4430
4431 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4432 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4433 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4434 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4435 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4436
4437 /*
4438 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4439 * but we don't support that).
4440 * Note: don't use the DAC post divider as it seems unstable.
4441 */
4442 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4443 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4444
a0c4da24 4445 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4447
89b667f8 4448 /* Set HBR and RBR LPF coefficients */
ff9a6750 4449 if (crtc->config.port_clock == 162000 ||
99750bd4 4450 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4451 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4452 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4453 0x005f0021);
4454 else
4abb2c39 4455 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4456 0x00d0000f);
4457
4458 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4460 /* Use SSC source */
4461 if (!pipe)
ae99258f 4462 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4463 0x0df40000);
4464 else
ae99258f 4465 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4466 0x0df70000);
4467 } else { /* HDMI or VGA */
4468 /* Use bend source */
4469 if (!pipe)
ae99258f 4470 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4471 0x0df70000);
4472 else
ae99258f 4473 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4474 0x0df40000);
4475 }
a0c4da24 4476
ae99258f 4477 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4478 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4479 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4481 coreclk |= 0x01000000;
ae99258f 4482 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4483
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4485
89b667f8
JB		 4486 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4487 if (encoder->pre_pll_enable)
4488 encoder->pre_pll_enable(encoder);
a0c4da24 4489
89b667f8
JB		 4490 /* Enable DPIO clock input */
4491 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4492 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4493 if (pipe)
4494 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4495
4496 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4497 crtc->config.dpll_hw_state.dpll = dpll;
4498
a0c4da24
JB		 4499 I915_WRITE(DPLL(pipe), dpll);
4500 POSTING_READ(DPLL(pipe));
2a8f64ca 4501 udelay(150);
a0c4da24 4502
a0c4da24
JB		 4503 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4504 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4505
ef1b460d
DV		 4506 dpll_md = (crtc->config.pixel_multiplier - 1)
4507 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4508 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4509
198a037f 4510 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4511 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4512
89b667f8
JB		 4513 if (crtc->config.has_dp_encoder)
4514 intel_dp_set_m_n(crtc);
09153000
DV		 4515
4516 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4517}
4518
f47709a9
DV		 4519static void i9xx_update_pll(struct intel_crtc *crtc,
4520 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4521 int num_connectors)
4522{
f47709a9 4523 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4524 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4525 u32 dpll;
4526 bool is_sdvo;
f47709a9 4527 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4528
f47709a9 4529 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4530
f47709a9
DV		 4531 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4533
4534 dpll = DPLL_VGA_MODE_DIS;
4535
f47709a9 4536 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4537 dpll |= DPLLB_MODE_LVDS;
4538 else
4539 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4540
ef1b460d 4541 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4542 dpll |= (crtc->config.pixel_multiplier - 1)
4543 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4544 }
198a037f
DV		 4545
4546 if (is_sdvo)
4547 dpll |= DPLL_DVO_HIGH_SPEED;
4548
f47709a9 4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4550 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552 /* compute bitmask from p1 value */
4553 if (IS_PINEVIEW(dev))
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4555 else {
4556 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557 if (IS_G4X(dev) && reduced_clock)
4558 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559 }
4560 switch (clock->p2) {
4561 case 5:
4562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563 break;
4564 case 7:
4565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566 break;
4567 case 10:
4568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569 break;
4570 case 14:
4571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572 break;
4573 }
4574 if (INTEL_INFO(dev)->gen >= 4)
4575 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4576
09ede541 4577 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4578 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4579 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4580 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4581 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4582 else
4583 dpll |= PLL_REF_INPUT_DREFCLK;
4584
4585 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4586 crtc->config.dpll_hw_state.dpll = dpll;
4587
eb1cbe48 4588 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4589 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4590 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4591 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4592 }
66e3d5c0
DV		 4593
4594 if (crtc->config.has_dp_encoder)
4595 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4596}
4597
f47709a9 4598static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4599 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4600 int num_connectors)
4601{
f47709a9 4602 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4603 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4604 u32 dpll;
f47709a9 4605 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4606
f47709a9 4607 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4608
eb1cbe48
DV		 4609 dpll = DPLL_VGA_MODE_DIS;
4610
f47709a9 4611 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4613 } else {
4614 if (clock->p1 == 2)
4615 dpll |= PLL_P1_DIVIDE_BY_TWO;
4616 else
4617 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4618 if (clock->p2 == 4)
4619 dpll |= PLL_P2_DIVIDE_BY_4;
4620 }
4621
f47709a9 4622 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4623 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4624 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4625 else
4626 dpll |= PLL_REF_INPUT_DREFCLK;
4627
4628 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4629 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4630}
4631
8a654f3b 4632static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4633{
4634 struct drm_device *dev = intel_crtc->base.dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4637 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4638 struct drm_display_mode *adjusted_mode =
4639 &intel_crtc->config.adjusted_mode;
4640 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4641 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4642
4643 /* We need to be careful not to changed the adjusted mode, for otherwise
4644 * the hw state checker will get angry at the mismatch. */
4645 crtc_vtotal = adjusted_mode->crtc_vtotal;
4646 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4647
4648 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4649 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4650 crtc_vtotal -= 1;
4651 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4652 vsyncshift = adjusted_mode->crtc_hsync_start
4653 - adjusted_mode->crtc_htotal / 2;
4654 } else {
4655 vsyncshift = 0;
4656 }
4657
4658 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4659 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4660
fe2b8f9d 4661 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4662 (adjusted_mode->crtc_hdisplay - 1) |
4663 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4664 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4665 (adjusted_mode->crtc_hblank_start - 1) |
4666 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4667 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4668 (adjusted_mode->crtc_hsync_start - 1) |
4669 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4670
fe2b8f9d 4671 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4672 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4673 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4674 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4675 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4676 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4677 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4678 (adjusted_mode->crtc_vsync_start - 1) |
4679 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4680
b5e508d4
PZ		 4681 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4682 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4683 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4684 * bits. */
4685 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4686 (pipe == PIPE_B || pipe == PIPE_C))
4687 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4688
b0e77b9c
PZ		 4689 /* pipesrc controls the size that is scaled from, which should
4690 * always be the user's requested size.
4691 */
4692 I915_WRITE(PIPESRC(pipe),
4693 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4694}
4695
1bd1bd80
DV		 4696static void intel_get_pipe_timings(struct intel_crtc *crtc,
4697 struct intel_crtc_config *pipe_config)
4698{
4699 struct drm_device *dev = crtc->base.dev;
4700 struct drm_i915_private *dev_priv = dev->dev_private;
4701 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4702 uint32_t tmp;
4703
4704 tmp = I915_READ(HTOTAL(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4707 tmp = I915_READ(HBLANK(cpu_transcoder));
4708 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4709 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4710 tmp = I915_READ(HSYNC(cpu_transcoder));
4711 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4712 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4713
4714 tmp = I915_READ(VTOTAL(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4717 tmp = I915_READ(VBLANK(cpu_transcoder));
4718 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4719 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4720 tmp = I915_READ(VSYNC(cpu_transcoder));
4721 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4722 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4723
4724 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4725 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4726 pipe_config->adjusted_mode.crtc_vtotal += 1;
4727 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4728 }
4729
4730 tmp = I915_READ(PIPESRC(crtc->pipe));
4731 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4732 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4733}
4734
babea61d
JB		 4735static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4736 struct intel_crtc_config *pipe_config)
4737{
4738 struct drm_crtc *crtc = &intel_crtc->base;
4739
4740 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4741 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4742 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4743 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4744
4745 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4746 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4747 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4748 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4749
4750 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4751
4752 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4753 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4754}
4755
84b046f3
DV		 4756static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4757{
4758 struct drm_device *dev = intel_crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 uint32_t pipeconf;
4761
9f11a9e4 4762 pipeconf = 0;
84b046f3
DV		 4763
4764 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4765 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4766 * core speed.
4767 *
4768 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4769 * pipe == 0 check?
4770 */
4771 if (intel_crtc->config.requested_mode.clock >
4772 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4773 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4774 }
4775
ff9ce46e
DV		 4776 /* only g4x and later have fancy bpc/dither controls */
4777 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4778 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4779 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4780 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4781 PIPECONF_DITHER_TYPE_SP;
84b046f3 4782
ff9ce46e
DV		 4783 switch (intel_crtc->config.pipe_bpp) {
4784 case 18:
4785 pipeconf |= PIPECONF_6BPC;
4786 break;
4787 case 24:
4788 pipeconf |= PIPECONF_8BPC;
4789 break;
4790 case 30:
4791 pipeconf |= PIPECONF_10BPC;
4792 break;
4793 default:
4794 /* Case prevented by intel_choose_pipe_bpp_dither. */
4795 BUG();
84b046f3
DV		 4796 }
4797 }
4798
4799 if (HAS_PIPE_CXSR(dev)) {
4800 if (intel_crtc->lowfreq_avail) {
4801 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4802 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4803 } else {
4804 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4805 }
4806 }
4807
84b046f3
DV		 4808 if (!IS_GEN2(dev) &&
4809 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4810 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4811 else
4812 pipeconf |= PIPECONF_PROGRESSIVE;
4813
9f11a9e4
DV		 4814 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4815 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4816
84b046f3
DV		 4817 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4818 POSTING_READ(PIPECONF(intel_crtc->pipe));
4819}
4820
f564048e 4821static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4822 int x, int y,
94352cf9 4823 struct drm_framebuffer *fb)
79e53945
JB		 4824{
4825 struct drm_device *dev = crtc->dev;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4828 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4829 int pipe = intel_crtc->pipe;
80824003 4830 int plane = intel_crtc->plane;
c751ce4f 4831 int refclk, num_connectors = 0;
652c393a 4832 intel_clock_t clock, reduced_clock;
84b046f3 4833 u32 dspcntr;
a16af721
DV		 4834 bool ok, has_reduced_clock = false;
4835 bool is_lvds = false;
5eddb70b 4836 struct intel_encoder *encoder;
d4906093 4837 const intel_limit_t *limit;
5c3b82e2 4838 int ret;
79e53945 4839
6c2b7c12 4840 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4841 switch (encoder->type) {
79e53945
JB		 4842 case INTEL_OUTPUT_LVDS:
4843 is_lvds = true;
4844 break;
79e53945 4845 }
43565a06 4846
c751ce4f 4847 num_connectors++;
79e53945
JB		 4848 }
4849
c65d77d8 4850 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4851
d4906093
ML		 4852 /*
4853 * Returns a set of divisors for the desired target clock with the given
4854 * refclk, or FALSE. The returned values represent the clock equation:
4855 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4856 */
1b894b59 4857 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4858 ok = dev_priv->display.find_dpll(limit, crtc,
4859 intel_crtc->config.port_clock,
ee9300bb
DV		 4860 refclk, NULL, &clock);
4861 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4862 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4863 return -EINVAL;
79e53945
JB		 4864 }
4865
cda4b7d3 4866 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4867 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4868
ddc9003c 4869 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4870 /*
4871 * Ensure we match the reduced clock's P to the target clock.
4872 * If the clocks don't match, we can't switch the display clock
4873 * by using the FP0/FP1. In such case we will disable the LVDS
4874 * downclock feature.
4875 */
ee9300bb
DV		 4876 has_reduced_clock =
4877 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4878 dev_priv->lvds_downclock,
ee9300bb 4879 refclk, &clock,
5eddb70b 4880 &reduced_clock);
7026d4ac 4881 }
f47709a9
DV		 4882 /* Compat-code for transition, will disappear. */
4883 if (!intel_crtc->config.clock_set) {
4884 intel_crtc->config.dpll.n = clock.n;
4885 intel_crtc->config.dpll.m1 = clock.m1;
4886 intel_crtc->config.dpll.m2 = clock.m2;
4887 intel_crtc->config.dpll.p1 = clock.p1;
4888 intel_crtc->config.dpll.p2 = clock.p2;
4889 }
7026d4ac 4890
eb1cbe48 4891 if (IS_GEN2(dev))
8a654f3b 4892 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4893 has_reduced_clock ? &reduced_clock : NULL,
4894 num_connectors);
a0c4da24 4895 else if (IS_VALLEYVIEW(dev))
f47709a9 4896 vlv_update_pll(intel_crtc);
79e53945 4897 else
f47709a9 4898 i9xx_update_pll(intel_crtc,
eb1cbe48 4899 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4900 num_connectors);
79e53945 4901
79e53945
JB		 4902 /* Set up the display plane register */
4903 dspcntr = DISPPLANE_GAMMA_ENABLE;
4904
da6ecc5d
JB		 4905 if (!IS_VALLEYVIEW(dev)) {
4906 if (pipe == 0)
4907 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4908 else
4909 dspcntr |= DISPPLANE_SEL_PIPE_B;
4910 }
79e53945 4911
8a654f3b 4912 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4913
4914 /* pipesrc and dspsize control the size that is scaled from,
4915 * which should always be the user's requested size.
79e53945 4916 */
929c77fb
EA		 4917 I915_WRITE(DSPSIZE(plane),
4918 ((mode->vdisplay - 1) << 16) |
4919 (mode->hdisplay - 1));
4920 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4921
84b046f3
DV		 4922 i9xx_set_pipeconf(intel_crtc);
4923
f564048e
EA		 4924 I915_WRITE(DSPCNTR(plane), dspcntr);
4925 POSTING_READ(DSPCNTR(plane));
4926
94352cf9 4927 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4928
4929 intel_update_watermarks(dev);
4930
f564048e
EA		 4931 return ret;
4932}
4933
2fa2fe9a
DV		 4934static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4935 struct intel_crtc_config *pipe_config)
4936{
4937 struct drm_device *dev = crtc->base.dev;
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 uint32_t tmp;
4940
4941 tmp = I915_READ(PFIT_CONTROL);
4942
4943 if (INTEL_INFO(dev)->gen < 4) {
4944 if (crtc->pipe != PIPE_B)
4945 return;
4946
4947 /* gen2/3 store dither state in pfit control, needs to match */
4948 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4949 } else {
4950 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4951 return;
4952 }
4953
4954 if (!(tmp & PFIT_ENABLE))
4955 return;
4956
4957 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4958 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4959 if (INTEL_INFO(dev)->gen < 5)
4960 pipe_config->gmch_pfit.lvds_border_bits =
4961 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4962}
4963
0e8ffe1b
DV		 4964static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4965 struct intel_crtc_config *pipe_config)
4966{
4967 struct drm_device *dev = crtc->base.dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 uint32_t tmp;
4970
e143a21c 4971 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4972 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4973
0e8ffe1b
DV		 4974 tmp = I915_READ(PIPECONF(crtc->pipe));
4975 if (!(tmp & PIPECONF_ENABLE))
4976 return false;
4977
1bd1bd80
DV		 4978 intel_get_pipe_timings(crtc, pipe_config);
4979
2fa2fe9a
DV		 4980 i9xx_get_pfit_config(crtc, pipe_config);
4981
6c49f241
DV		 4982 if (INTEL_INFO(dev)->gen >= 4) {
4983 tmp = I915_READ(DPLL_MD(crtc->pipe));
4984 pipe_config->pixel_multiplier =
4985 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4986 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4987 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4988 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4989 tmp = I915_READ(DPLL(crtc->pipe));
4990 pipe_config->pixel_multiplier =
4991 ((tmp & SDVO_MULTIPLIER_MASK)
4992 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4993 } else {
4994 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4995 * port and will be fixed up in the encoder->get_config
4996 * function. */
4997 pipe_config->pixel_multiplier = 1;
4998 }
8bcc2795
DV		 4999 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5000 if (!IS_VALLEYVIEW(dev)) {
5001 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5002 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5003 } else {
5004 /* Mask out read-only status bits. */
5005 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5006 DPLL_PORTC_READY_MASK |
5007 DPLL_PORTB_READY_MASK);
8bcc2795 5008 }
6c49f241 5009
0e8ffe1b
DV		 5010 return true;
5011}
5012
dde86e2d 5013static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5014{
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5017 struct intel_encoder *encoder;
74cfd7ac 5018 u32 val, final;
13d83a67 5019 bool has_lvds = false;
199e5d79 5020 bool has_cpu_edp = false;
199e5d79 5021 bool has_panel = false;
99eb6a01
KP		 5022 bool has_ck505 = false;
5023 bool can_ssc = false;
13d83a67
JB		 5024
5025 /* We need to take the global config into account */
199e5d79
KP		 5026 list_for_each_entry(encoder, &mode_config->encoder_list,
5027 base.head) {
5028 switch (encoder->type) {
5029 case INTEL_OUTPUT_LVDS:
5030 has_panel = true;
5031 has_lvds = true;
5032 break;
5033 case INTEL_OUTPUT_EDP:
5034 has_panel = true;
2de6905f 5035 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5036 has_cpu_edp = true;
5037 break;
13d83a67
JB		 5038 }
5039 }
5040
99eb6a01 5041 if (HAS_PCH_IBX(dev)) {
41aa3448 5042 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5043 can_ssc = has_ck505;
5044 } else {
5045 has_ck505 = false;
5046 can_ssc = true;
5047 }
5048
2de6905f
ID		 5049 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5050 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5051
5052 /* Ironlake: try to setup display ref clock before DPLL
5053 * enabling. This is only under driver's control after
5054 * PCH B stepping, previous chipset stepping should be
5055 * ignoring this setting.
5056 */
74cfd7ac
CW		 5057 val = I915_READ(PCH_DREF_CONTROL);
5058
5059 /* As we must carefully and slowly disable/enable each source in turn,
5060 * compute the final state we want first and check if we need to
5061 * make any changes at all.
5062 */
5063 final = val;
5064 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5065 if (has_ck505)
5066 final |= DREF_NONSPREAD_CK505_ENABLE;
5067 else
5068 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5069
5070 final &= ~DREF_SSC_SOURCE_MASK;
5071 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5072 final &= ~DREF_SSC1_ENABLE;
5073
5074 if (has_panel) {
5075 final |= DREF_SSC_SOURCE_ENABLE;
5076
5077 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5078 final |= DREF_SSC1_ENABLE;
5079
5080 if (has_cpu_edp) {
5081 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5082 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5083 else
5084 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5085 } else
5086 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5087 } else {
5088 final |= DREF_SSC_SOURCE_DISABLE;
5089 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5090 }
5091
5092 if (final == val)
5093 return;
5094
13d83a67 5095 /* Always enable nonspread source */
74cfd7ac 5096 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5097
99eb6a01 5098 if (has_ck505)
74cfd7ac 5099 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5100 else
74cfd7ac 5101 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5102
199e5d79 5103 if (has_panel) {
74cfd7ac
CW		 5104 val &= ~DREF_SSC_SOURCE_MASK;
5105 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5106
199e5d79 5107 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5108 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5109 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5110 val |= DREF_SSC1_ENABLE;
e77166b5 5111 } else
74cfd7ac 5112 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5113
5114 /* Get SSC going before enabling the outputs */
74cfd7ac 5115 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5116 POSTING_READ(PCH_DREF_CONTROL);
5117 udelay(200);
5118
74cfd7ac 5119 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5120
5121 /* Enable CPU source on CPU attached eDP */
199e5d79 5122 if (has_cpu_edp) {
99eb6a01 5123 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5124 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5125 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5126 }
13d83a67 5127 else
74cfd7ac 5128 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5129 } else
74cfd7ac 5130 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5131
74cfd7ac 5132 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5133 POSTING_READ(PCH_DREF_CONTROL);
5134 udelay(200);
5135 } else {
5136 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5137
74cfd7ac 5138 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5139
5140 /* Turn off CPU output */
74cfd7ac 5141 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5142
74cfd7ac 5143 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5144 POSTING_READ(PCH_DREF_CONTROL);
5145 udelay(200);
5146
5147 /* Turn off the SSC source */
74cfd7ac
CW		 5148 val &= ~DREF_SSC_SOURCE_MASK;
5149 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5150
5151 /* Turn off SSC1 */
74cfd7ac 5152 val &= ~DREF_SSC1_ENABLE;
199e5d79 5153
74cfd7ac 5154 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5155 POSTING_READ(PCH_DREF_CONTROL);
5156 udelay(200);
5157 }
74cfd7ac
CW		 5158
5159 BUG_ON(val != final);
13d83a67
JB		 5160}
5161
dde86e2d
PZ		 5162/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5163static void lpt_init_pch_refclk(struct drm_device *dev)
5164{
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 struct drm_mode_config *mode_config = &dev->mode_config;
5167 struct intel_encoder *encoder;
5168 bool has_vga = false;
5169 bool is_sdv = false;
5170 u32 tmp;
5171
5172 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5173 switch (encoder->type) {
5174 case INTEL_OUTPUT_ANALOG:
5175 has_vga = true;
5176 break;
5177 }
5178 }
5179
5180 if (!has_vga)
5181 return;
5182
c00db246
DV		 5183 mutex_lock(&dev_priv->dpio_lock);
5184
dde86e2d
PZ		 5185 /* XXX: Rip out SDV support once Haswell ships for real. */
5186 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5187 is_sdv = true;
5188
5189 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5190 tmp &= ~SBI_SSCCTL_DISABLE;
5191 tmp |= SBI_SSCCTL_PATHALT;
5192 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5193
5194 udelay(24);
5195
5196 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5197 tmp &= ~SBI_SSCCTL_PATHALT;
5198 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5199
5200 if (!is_sdv) {
5201 tmp = I915_READ(SOUTH_CHICKEN2);
5202 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5203 I915_WRITE(SOUTH_CHICKEN2, tmp);
5204
5205 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5206 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5207 DRM_ERROR("FDI mPHY reset assert timeout\n");
5208
5209 tmp = I915_READ(SOUTH_CHICKEN2);
5210 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5211 I915_WRITE(SOUTH_CHICKEN2, tmp);
5212
5213 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5214 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5215 100))
5216 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5217 }
5218
5219 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5220 tmp &= ~(0xFF << 24);
5221 tmp |= (0x12 << 24);
5222 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5223
dde86e2d
PZ		 5224 if (is_sdv) {
5225 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5226 tmp |= 0x7FFF;
5227 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5228 }
5229
5230 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5231 tmp |= (1 << 11);
5232 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5233
5234 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5235 tmp |= (1 << 11);
5236 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5237
5238 if (is_sdv) {
5239 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5240 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5241 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5242
5243 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5244 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5245 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5248 tmp |= (0x3F << 8);
5249 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5250
5251 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5252 tmp |= (0x3F << 8);
5253 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5254 }
5255
5256 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5257 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5258 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5261 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5262 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5263
5264 if (!is_sdv) {
5265 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5266 tmp &= ~(7 << 13);
5267 tmp |= (5 << 13);
5268 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5271 tmp &= ~(7 << 13);
5272 tmp |= (5 << 13);
5273 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5274 }
5275
5276 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5277 tmp &= ~0xFF;
5278 tmp |= 0x1C;
5279 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5280
5281 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5282 tmp &= ~0xFF;
5283 tmp |= 0x1C;
5284 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5285
5286 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5287 tmp &= ~(0xFF << 16);
5288 tmp |= (0x1C << 16);
5289 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5290
5291 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5292 tmp &= ~(0xFF << 16);
5293 tmp |= (0x1C << 16);
5294 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5295
5296 if (!is_sdv) {
5297 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5298 tmp |= (1 << 27);
5299 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5300
5301 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5302 tmp |= (1 << 27);
5303 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5306 tmp &= ~(0xF << 28);
5307 tmp |= (4 << 28);
5308 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5311 tmp &= ~(0xF << 28);
5312 tmp |= (4 << 28);
5313 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5314 }
5315
5316 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5317 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5318 tmp |= SBI_DBUFF0_ENABLE;
5319 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5320
5321 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5322}
5323
5324/*
5325 * Initialize reference clocks when the driver loads
5326 */
5327void intel_init_pch_refclk(struct drm_device *dev)
5328{
5329 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5330 ironlake_init_pch_refclk(dev);
5331 else if (HAS_PCH_LPT(dev))
5332 lpt_init_pch_refclk(dev);
5333}
5334
d9d444cb
JB		 5335static int ironlake_get_refclk(struct drm_crtc *crtc)
5336{
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_encoder *encoder;
d9d444cb
JB		 5340 int num_connectors = 0;
5341 bool is_lvds = false;
5342
6c2b7c12 5343 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5344 switch (encoder->type) {
5345 case INTEL_OUTPUT_LVDS:
5346 is_lvds = true;
5347 break;
d9d444cb
JB		 5348 }
5349 num_connectors++;
5350 }
5351
5352 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5353 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5354 dev_priv->vbt.lvds_ssc_freq);
5355 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5356 }
5357
5358 return 120000;
5359}
5360
6ff93609 5361static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5362{
c8203565 5363 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5365 int pipe = intel_crtc->pipe;
c8203565
PZ		 5366 uint32_t val;
5367
78114071 5368 val = 0;
c8203565 5369
965e0c48 5370 switch (intel_crtc->config.pipe_bpp) {
c8203565 5371 case 18:
dfd07d72 5372 val |= PIPECONF_6BPC;
c8203565
PZ		 5373 break;
5374 case 24:
dfd07d72 5375 val |= PIPECONF_8BPC;
c8203565
PZ		 5376 break;
5377 case 30:
dfd07d72 5378 val |= PIPECONF_10BPC;
c8203565
PZ		 5379 break;
5380 case 36:
dfd07d72 5381 val |= PIPECONF_12BPC;
c8203565
PZ		 5382 break;
5383 default:
cc769b62
PZ		 5384 /* Case prevented by intel_choose_pipe_bpp_dither. */
5385 BUG();
c8203565
PZ		 5386 }
5387
d8b32247 5388 if (intel_crtc->config.dither)
c8203565
PZ		 5389 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5390
6ff93609 5391 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5392 val |= PIPECONF_INTERLACED_ILK;
5393 else
5394 val |= PIPECONF_PROGRESSIVE;
5395
50f3b016 5396 if (intel_crtc->config.limited_color_range)
3685a8f3 5397 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5398
c8203565
PZ		 5399 I915_WRITE(PIPECONF(pipe), val);
5400 POSTING_READ(PIPECONF(pipe));
5401}
5402
86d3efce
VS		 5403/*
5404 * Set up the pipe CSC unit.
5405 *
5406 * Currently only full range RGB to limited range RGB conversion
5407 * is supported, but eventually this should handle various
5408 * RGB<->YCbCr scenarios as well.
5409 */
50f3b016 5410static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5411{
5412 struct drm_device *dev = crtc->dev;
5413 struct drm_i915_private *dev_priv = dev->dev_private;
5414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5415 int pipe = intel_crtc->pipe;
5416 uint16_t coeff = 0x7800; /* 1.0 */
5417
5418 /*
5419 * TODO: Check what kind of values actually come out of the pipe
5420 * with these coeff/postoff values and adjust to get the best
5421 * accuracy. Perhaps we even need to take the bpc value into
5422 * consideration.
5423 */
5424
50f3b016 5425 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5426 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5427
5428 /*
5429 * GY/GU and RY/RU should be the other way around according
5430 * to BSpec, but reality doesn't agree. Just set them up in
5431 * a way that results in the correct picture.
5432 */
5433 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5434 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5435
5436 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5437 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5438
5439 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5440 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5441
5442 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5443 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5444 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5445
5446 if (INTEL_INFO(dev)->gen > 6) {
5447 uint16_t postoff = 0;
5448
50f3b016 5449 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5450 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5451
5452 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5453 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5454 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5455
5456 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5457 } else {
5458 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5459
50f3b016 5460 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5461 mode |= CSC_BLACK_SCREEN_OFFSET;
5462
5463 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5464 }
5465}
5466
6ff93609 5467static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5468{
5469 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5471 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5472 uint32_t val;
5473
3eff4faa 5474 val = 0;
ee2b0b38 5475
d8b32247 5476 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5477 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5478
6ff93609 5479 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5480 val |= PIPECONF_INTERLACED_ILK;
5481 else
5482 val |= PIPECONF_PROGRESSIVE;
5483
702e7a56
PZ		 5484 I915_WRITE(PIPECONF(cpu_transcoder), val);
5485 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5486
5487 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5488 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5489}
5490
6591c6e4 5491static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5492 intel_clock_t *clock,
5493 bool *has_reduced_clock,
5494 intel_clock_t *reduced_clock)
5495{
5496 struct drm_device *dev = crtc->dev;
5497 struct drm_i915_private *dev_priv = dev->dev_private;
5498 struct intel_encoder *intel_encoder;
5499 int refclk;
d4906093 5500 const intel_limit_t *limit;
a16af721 5501 bool ret, is_lvds = false;
79e53945 5502
6591c6e4
PZ		 5503 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5504 switch (intel_encoder->type) {
79e53945
JB		 5505 case INTEL_OUTPUT_LVDS:
5506 is_lvds = true;
5507 break;
79e53945
JB		 5508 }
5509 }
5510
d9d444cb 5511 refclk = ironlake_get_refclk(crtc);
79e53945 5512
d4906093
ML		 5513 /*
5514 * Returns a set of divisors for the desired target clock with the given
5515 * refclk, or FALSE. The returned values represent the clock equation:
5516 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5517 */
1b894b59 5518 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5519 ret = dev_priv->display.find_dpll(limit, crtc,
5520 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5521 refclk, NULL, clock);
6591c6e4
PZ		 5522 if (!ret)
5523 return false;
cda4b7d3 5524
ddc9003c 5525 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5526 /*
5527 * Ensure we match the reduced clock's P to the target clock.
5528 * If the clocks don't match, we can't switch the display clock
5529 * by using the FP0/FP1. In such case we will disable the LVDS
5530 * downclock feature.
5531 */
ee9300bb
DV		 5532 *has_reduced_clock =
5533 dev_priv->display.find_dpll(limit, crtc,
5534 dev_priv->lvds_downclock,
5535 refclk, clock,
5536 reduced_clock);
652c393a 5537 }
61e9653f 5538
6591c6e4
PZ		 5539 return true;
5540}
5541
01a415fd
DV		 5542static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5543{
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545 uint32_t temp;
5546
5547 temp = I915_READ(SOUTH_CHICKEN1);
5548 if (temp & FDI_BC_BIFURCATION_SELECT)
5549 return;
5550
5551 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5552 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5553
5554 temp |= FDI_BC_BIFURCATION_SELECT;
5555 DRM_DEBUG_KMS("enabling fdi C rx\n");
5556 I915_WRITE(SOUTH_CHICKEN1, temp);
5557 POSTING_READ(SOUTH_CHICKEN1);
5558}
5559
ebfd86fd 5560static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5561{
5562 struct drm_device *dev = intel_crtc->base.dev;
5563 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5564
5565 switch (intel_crtc->pipe) {
5566 case PIPE_A:
ebfd86fd 5567 break;
01a415fd 5568 case PIPE_B:
ebfd86fd 5569 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5570 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5571 else
5572 cpt_enable_fdi_bc_bifurcation(dev);
5573
ebfd86fd 5574 break;
01a415fd 5575 case PIPE_C:
01a415fd
DV		 5576 cpt_enable_fdi_bc_bifurcation(dev);
5577
ebfd86fd 5578 break;
01a415fd
DV		 5579 default:
5580 BUG();
5581 }
5582}
5583
d4b1931c
PZ		 5584int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5585{
5586 /*
5587 * Account for spread spectrum to avoid
5588 * oversubscribing the link. Max center spread
5589 * is 2.5%; use 5% for safety's sake.
5590 */
5591 u32 bps = target_clock * bpp * 21 / 20;
5592 return bps / (link_bw * 8) + 1;
5593}
5594
7429e9d4 5595static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5596{
7429e9d4 5597 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5598}
5599
de13a2e3 5600static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5601 u32 *fp,
9a7c7890 5602 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5603{
de13a2e3 5604 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5605 struct drm_device *dev = crtc->dev;
5606 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5607 struct intel_encoder *intel_encoder;
5608 uint32_t dpll;
6cc5f341 5609 int factor, num_connectors = 0;
09ede541 5610 bool is_lvds = false, is_sdvo = false;
79e53945 5611
de13a2e3
PZ		 5612 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5613 switch (intel_encoder->type) {
79e53945
JB		 5614 case INTEL_OUTPUT_LVDS:
5615 is_lvds = true;
5616 break;
5617 case INTEL_OUTPUT_SDVO:
7d57382e 5618 case INTEL_OUTPUT_HDMI:
79e53945 5619 is_sdvo = true;
79e53945 5620 break;
79e53945 5621 }
43565a06 5622
c751ce4f 5623 num_connectors++;
79e53945 5624 }
79e53945 5625
c1858123 5626 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5627 factor = 21;
5628 if (is_lvds) {
5629 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5630 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5631 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5632 factor = 25;
09ede541 5633 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5634 factor = 20;
c1858123 5635
7429e9d4 5636 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5637 *fp |= FP_CB_TUNE;
2c07245f 5638
9a7c7890
DV		 5639 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5640 *fp2 |= FP_CB_TUNE;
5641
5eddb70b 5642 dpll = 0;
2c07245f 5643
a07d6787
EA		 5644 if (is_lvds)
5645 dpll |= DPLLB_MODE_LVDS;
5646 else
5647 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5648
ef1b460d
DV		 5649 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5650 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5651
5652 if (is_sdvo)
5653 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5654 if (intel_crtc->config.has_dp_encoder)
a07d6787 5655 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5656
a07d6787 5657 /* compute bitmask from p1 value */
7429e9d4 5658 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5659 /* also FPA1 */
7429e9d4 5660 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5661
7429e9d4 5662 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5663 case 5:
5664 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5665 break;
5666 case 7:
5667 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5668 break;
5669 case 10:
5670 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5671 break;
5672 case 14:
5673 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5674 break;
79e53945
JB		 5675 }
5676
b4c09f3b 5677 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5678 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5679 else
5680 dpll |= PLL_REF_INPUT_DREFCLK;
5681
959e16d6 5682 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5683}
5684
5685static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5686 int x, int y,
5687 struct drm_framebuffer *fb)
5688{
5689 struct drm_device *dev = crtc->dev;
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692 int pipe = intel_crtc->pipe;
5693 int plane = intel_crtc->plane;
5694 int num_connectors = 0;
5695 intel_clock_t clock, reduced_clock;
cbbab5bd 5696 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5697 bool ok, has_reduced_clock = false;
8b47047b 5698 bool is_lvds = false;
de13a2e3 5699 struct intel_encoder *encoder;
e2b78267 5700 struct intel_shared_dpll *pll;
de13a2e3 5701 int ret;
de13a2e3
PZ		 5702
5703 for_each_encoder_on_crtc(dev, crtc, encoder) {
5704 switch (encoder->type) {
5705 case INTEL_OUTPUT_LVDS:
5706 is_lvds = true;
5707 break;
de13a2e3
PZ		 5708 }
5709
5710 num_connectors++;
a07d6787 5711 }
79e53945 5712
5dc5298b
PZ		 5713 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5714 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5715
ff9a6750 5716 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5717 &has_reduced_clock, &reduced_clock);
ee9300bb 5718 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5719 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5720 return -EINVAL;
79e53945 5721 }
f47709a9
DV		 5722 /* Compat-code for transition, will disappear. */
5723 if (!intel_crtc->config.clock_set) {
5724 intel_crtc->config.dpll.n = clock.n;
5725 intel_crtc->config.dpll.m1 = clock.m1;
5726 intel_crtc->config.dpll.m2 = clock.m2;
5727 intel_crtc->config.dpll.p1 = clock.p1;
5728 intel_crtc->config.dpll.p2 = clock.p2;
5729 }
79e53945 5730
de13a2e3
PZ		 5731 /* Ensure that the cursor is valid for the new mode before changing... */
5732 intel_crtc_update_cursor(crtc, true);
5733
5dc5298b 5734 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5735 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5736 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5737 if (has_reduced_clock)
7429e9d4 5738 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5739
7429e9d4 5740 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5741 &fp, &reduced_clock,
5742 has_reduced_clock ? &fp2 : NULL);
5743
959e16d6 5744 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5745 intel_crtc->config.dpll_hw_state.fp0 = fp;
5746 if (has_reduced_clock)
5747 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5748 else
5749 intel_crtc->config.dpll_hw_state.fp1 = fp;
5750
b89a1d39 5751 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5752 if (pll == NULL) {
84f44ce7
VS		 5753 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5754 pipe_name(pipe));
4b645f14
JB		 5755 return -EINVAL;
5756 }
ee7b9f93 5757 } else
e72f9fbf 5758 intel_put_shared_dpll(intel_crtc);
79e53945 5759
03afc4a2
DV		 5760 if (intel_crtc->config.has_dp_encoder)
5761 intel_dp_set_m_n(intel_crtc);
79e53945 5762
bcd644e0
DV		 5763 if (is_lvds && has_reduced_clock && i915_powersave)
5764 intel_crtc->lowfreq_avail = true;
5765 else
5766 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5767
5768 if (intel_crtc->config.has_pch_encoder) {
5769 pll = intel_crtc_to_shared_dpll(intel_crtc);
5770
652c393a
JB		 5771 }
5772
8a654f3b 5773 intel_set_pipe_timings(intel_crtc);
5eddb70b 5774
ca3a0ff8 5775 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5776 intel_cpu_transcoder_set_m_n(intel_crtc,
5777 &intel_crtc->config.fdi_m_n);
5778 }
2c07245f 5779
ebfd86fd
DV		 5780 if (IS_IVYBRIDGE(dev))
5781 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5782
6ff93609 5783 ironlake_set_pipeconf(crtc);
79e53945 5784
a1f9e77e
PZ		 5785 /* Set up the display plane register */
5786 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5787 POSTING_READ(DSPCNTR(plane));
79e53945 5788
94352cf9 5789 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5790
5791 intel_update_watermarks(dev);
5792
1857e1da 5793 return ret;
79e53945
JB		 5794}
5795
72419203
DV		 5796static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5798{
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 enum transcoder transcoder = pipe_config->cpu_transcoder;
5802
5803 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5804 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5805 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5806 & ~TU_SIZE_MASK;
5807 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5808 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5809 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5810}
5811
2fa2fe9a
DV		 5812static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5813 struct intel_crtc_config *pipe_config)
5814{
5815 struct drm_device *dev = crtc->base.dev;
5816 struct drm_i915_private *dev_priv = dev->dev_private;
5817 uint32_t tmp;
5818
5819 tmp = I915_READ(PF_CTL(crtc->pipe));
5820
5821 if (tmp & PF_ENABLE) {
5822 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5823 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5824
5825 /* We currently do not free assignements of panel fitters on
5826 * ivb/hsw (since we don't use the higher upscaling modes which
5827 * differentiates them) so just WARN about this case for now. */
5828 if (IS_GEN7(dev)) {
5829 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5830 PF_PIPE_SEL_IVB(crtc->pipe));
5831 }
2fa2fe9a 5832 }
79e53945
JB		 5833}
5834
0e8ffe1b
DV		 5835static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5836 struct intel_crtc_config *pipe_config)
5837{
5838 struct drm_device *dev = crtc->base.dev;
5839 struct drm_i915_private *dev_priv = dev->dev_private;
5840 uint32_t tmp;
5841
e143a21c 5842 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5843 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5844
0e8ffe1b
DV		 5845 tmp = I915_READ(PIPECONF(crtc->pipe));
5846 if (!(tmp & PIPECONF_ENABLE))
5847 return false;
5848
ab9412ba 5849 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5850 struct intel_shared_dpll *pll;
5851
88adfff1
DV		 5852 pipe_config->has_pch_encoder = true;
5853
627eb5a3
DV		 5854 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5855 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5856 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5857
5858 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5859
c0d43d62 5860 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5861 pipe_config->shared_dpll =
5862 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5863 } else {
5864 tmp = I915_READ(PCH_DPLL_SEL);
5865 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5866 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5867 else
5868 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5869 }
66e985c0
DV		 5870
5871 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5872
5873 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5874 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5875
5876 tmp = pipe_config->dpll_hw_state.dpll;
5877 pipe_config->pixel_multiplier =
5878 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5879 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5880 } else {
5881 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5882 }
5883
1bd1bd80
DV		 5884 intel_get_pipe_timings(crtc, pipe_config);
5885
2fa2fe9a
DV		 5886 ironlake_get_pfit_config(crtc, pipe_config);
5887
0e8ffe1b
DV		 5888 return true;
5889}
5890
d6dd9eb1
DV		 5891static void haswell_modeset_global_resources(struct drm_device *dev)
5892{
d6dd9eb1
DV		 5893 bool enable = false;
5894 struct intel_crtc *crtc;
d6dd9eb1
DV		 5895
5896 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5897 if (!crtc->base.enabled)
5898 continue;
d6dd9eb1 5899
e7a639c4
DV		 5900 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5901 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5902 enable = true;
5903 }
5904
d6dd9eb1
DV		 5905 intel_set_power_well(dev, enable);
5906}
5907
09b4ddf9 5908static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5909 int x, int y,
5910 struct drm_framebuffer *fb)
5911{
5912 struct drm_device *dev = crtc->dev;
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5915 int plane = intel_crtc->plane;
09b4ddf9 5916 int ret;
09b4ddf9 5917
ff9a6750 5918 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5919 return -EINVAL;
5920
09b4ddf9
PZ		 5921 /* Ensure that the cursor is valid for the new mode before changing... */
5922 intel_crtc_update_cursor(crtc, true);
5923
03afc4a2
DV		 5924 if (intel_crtc->config.has_dp_encoder)
5925 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5926
5927 intel_crtc->lowfreq_avail = false;
09b4ddf9 5928
8a654f3b 5929 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5930
ca3a0ff8 5931 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5932 intel_cpu_transcoder_set_m_n(intel_crtc,
5933 &intel_crtc->config.fdi_m_n);
5934 }
09b4ddf9 5935
6ff93609 5936 haswell_set_pipeconf(crtc);
09b4ddf9 5937
50f3b016 5938 intel_set_pipe_csc(crtc);
86d3efce 5939
09b4ddf9 5940 /* Set up the display plane register */
86d3efce 5941 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5942 POSTING_READ(DSPCNTR(plane));
5943
5944 ret = intel_pipe_set_base(crtc, x, y, fb);
5945
5946 intel_update_watermarks(dev);
5947
1f803ee5 5948 return ret;
79e53945
JB		 5949}
5950
0e8ffe1b
DV		 5951static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5952 struct intel_crtc_config *pipe_config)
5953{
5954 struct drm_device *dev = crtc->base.dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5956 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5957 uint32_t tmp;
5958
e143a21c 5959 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 5960 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5961
eccb140b
DV		 5962 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5963 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5964 enum pipe trans_edp_pipe;
5965 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5966 default:
5967 WARN(1, "unknown pipe linked to edp transcoder\n");
5968 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5969 case TRANS_DDI_EDP_INPUT_A_ON:
5970 trans_edp_pipe = PIPE_A;
5971 break;
5972 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5973 trans_edp_pipe = PIPE_B;
5974 break;
5975 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5976 trans_edp_pipe = PIPE_C;
5977 break;
5978 }
5979
5980 if (trans_edp_pipe == crtc->pipe)
5981 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5982 }
5983
b97186f0 5984 if (!intel_display_power_enabled(dev,
eccb140b 5985 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5986 return false;
5987
eccb140b 5988 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5989 if (!(tmp & PIPECONF_ENABLE))
5990 return false;
5991
88adfff1 5992 /*
f196e6be 5993 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5994 * DDI E. So just check whether this pipe is wired to DDI E and whether
5995 * the PCH transcoder is on.
5996 */
eccb140b 5997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5998 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5999 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6000 pipe_config->has_pch_encoder = true;
6001
627eb5a3
DV		 6002 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6003 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6004 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6005
6006 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6007 }
6008
1bd1bd80
DV		 6009 intel_get_pipe_timings(crtc, pipe_config);
6010
2fa2fe9a
DV		 6011 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6012 if (intel_display_power_enabled(dev, pfit_domain))
6013 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6014
42db64ef
PZ		 6015 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6016 (I915_READ(IPS_CTL) & IPS_ENABLE);
6017
6c49f241
DV		 6018 pipe_config->pixel_multiplier = 1;
6019
0e8ffe1b
DV		 6020 return true;
6021}
6022
f564048e 6023static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6024 int x, int y,
94352cf9 6025 struct drm_framebuffer *fb)
f564048e
EA		 6026{
6027 struct drm_device *dev = crtc->dev;
6028 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6029 struct drm_encoder_helper_funcs *encoder_funcs;
6030 struct intel_encoder *encoder;
0b701d27 6031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6032 struct drm_display_mode *adjusted_mode =
6033 &intel_crtc->config.adjusted_mode;
6034 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6035 int pipe = intel_crtc->pipe;
f564048e
EA		 6036 int ret;
6037
0b701d27 6038 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6039
b8cecdf5
DV		 6040 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6041
79e53945 6042 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6043
9256aa19
DV		 6044 if (ret != 0)
6045 return ret;
6046
6047 for_each_encoder_on_crtc(dev, crtc, encoder) {
6048 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6049 encoder->base.base.id,
6050 drm_get_encoder_name(&encoder->base),
6051 mode->base.id, mode->name);
6cc5f341
DV		 6052 if (encoder->mode_set) {
6053 encoder->mode_set(encoder);
6054 } else {
6055 encoder_funcs = encoder->base.helper_private;
6056 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6057 }
9256aa19
DV		 6058 }
6059
6060 return 0;
79e53945
JB		 6061}
6062
3a9627f4
WF		 6063static bool intel_eld_uptodate(struct drm_connector *connector,
6064 int reg_eldv, uint32_t bits_eldv,
6065 int reg_elda, uint32_t bits_elda,
6066 int reg_edid)
6067{
6068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6069 uint8_t *eld = connector->eld;
6070 uint32_t i;
6071
6072 i = I915_READ(reg_eldv);
6073 i &= bits_eldv;
6074
6075 if (!eld[0])
6076 return !i;
6077
6078 if (!i)
6079 return false;
6080
6081 i = I915_READ(reg_elda);
6082 i &= ~bits_elda;
6083 I915_WRITE(reg_elda, i);
6084
6085 for (i = 0; i < eld[2]; i++)
6086 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6087 return false;
6088
6089 return true;
6090}
6091
e0dac65e
WF		 6092static void g4x_write_eld(struct drm_connector *connector,
6093 struct drm_crtc *crtc)
6094{
6095 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6096 uint8_t *eld = connector->eld;
6097 uint32_t eldv;
6098 uint32_t len;
6099 uint32_t i;
6100
6101 i = I915_READ(G4X_AUD_VID_DID);
6102
6103 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6104 eldv = G4X_ELDV_DEVCL_DEVBLC;
6105 else
6106 eldv = G4X_ELDV_DEVCTG;
6107
3a9627f4
WF		 6108 if (intel_eld_uptodate(connector,
6109 G4X_AUD_CNTL_ST, eldv,
6110 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6111 G4X_HDMIW_HDMIEDID))
6112 return;
6113
e0dac65e
WF		 6114 i = I915_READ(G4X_AUD_CNTL_ST);
6115 i &= ~(eldv | G4X_ELD_ADDR);
6116 len = (i >> 9) & 0x1f; /* ELD buffer size */
6117 I915_WRITE(G4X_AUD_CNTL_ST, i);
6118
6119 if (!eld[0])
6120 return;
6121
6122 len = min_t(uint8_t, eld[2], len);
6123 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6124 for (i = 0; i < len; i++)
6125 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6126
6127 i = I915_READ(G4X_AUD_CNTL_ST);
6128 i |= eldv;
6129 I915_WRITE(G4X_AUD_CNTL_ST, i);
6130}
6131
83358c85
WX		 6132static void haswell_write_eld(struct drm_connector *connector,
6133 struct drm_crtc *crtc)
6134{
6135 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6136 uint8_t *eld = connector->eld;
6137 struct drm_device *dev = crtc->dev;
7b9f35a6 6138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6139 uint32_t eldv;
6140 uint32_t i;
6141 int len;
6142 int pipe = to_intel_crtc(crtc)->pipe;
6143 int tmp;
6144
6145 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6146 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6147 int aud_config = HSW_AUD_CFG(pipe);
6148 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6149
6150
6151 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6152
6153 /* Audio output enable */
6154 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6155 tmp = I915_READ(aud_cntrl_st2);
6156 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6157 I915_WRITE(aud_cntrl_st2, tmp);
6158
6159 /* Wait for 1 vertical blank */
6160 intel_wait_for_vblank(dev, pipe);
6161
6162 /* Set ELD valid state */
6163 tmp = I915_READ(aud_cntrl_st2);
6164 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6165 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6166 I915_WRITE(aud_cntrl_st2, tmp);
6167 tmp = I915_READ(aud_cntrl_st2);
6168 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6169
6170 /* Enable HDMI mode */
6171 tmp = I915_READ(aud_config);
6172 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6173 /* clear N_programing_enable and N_value_index */
6174 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6175 I915_WRITE(aud_config, tmp);
6176
6177 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6178
6179 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6180 intel_crtc->eld_vld = true;
83358c85
WX		 6181
6182 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6183 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6184 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6185 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6186 } else
6187 I915_WRITE(aud_config, 0);
6188
6189 if (intel_eld_uptodate(connector,
6190 aud_cntrl_st2, eldv,
6191 aud_cntl_st, IBX_ELD_ADDRESS,
6192 hdmiw_hdmiedid))
6193 return;
6194
6195 i = I915_READ(aud_cntrl_st2);
6196 i &= ~eldv;
6197 I915_WRITE(aud_cntrl_st2, i);
6198
6199 if (!eld[0])
6200 return;
6201
6202 i = I915_READ(aud_cntl_st);
6203 i &= ~IBX_ELD_ADDRESS;
6204 I915_WRITE(aud_cntl_st, i);
6205 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6206 DRM_DEBUG_DRIVER("port num:%d\n", i);
6207
6208 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6209 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6210 for (i = 0; i < len; i++)
6211 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6212
6213 i = I915_READ(aud_cntrl_st2);
6214 i |= eldv;
6215 I915_WRITE(aud_cntrl_st2, i);
6216
6217}
6218
e0dac65e
WF		 6219static void ironlake_write_eld(struct drm_connector *connector,
6220 struct drm_crtc *crtc)
6221{
6222 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6223 uint8_t *eld = connector->eld;
6224 uint32_t eldv;
6225 uint32_t i;
6226 int len;
6227 int hdmiw_hdmiedid;
b6daa025 6228 int aud_config;
e0dac65e
WF		 6229 int aud_cntl_st;
6230 int aud_cntrl_st2;
9b138a83 6231 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6232
b3f33cbf 6233 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6234 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6235 aud_config = IBX_AUD_CFG(pipe);
6236 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6237 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6238 } else {
9b138a83
WX		 6239 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6240 aud_config = CPT_AUD_CFG(pipe);
6241 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6242 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6243 }
6244
9b138a83 6245 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6246
6247 i = I915_READ(aud_cntl_st);
9b138a83 6248 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6249 if (!i) {
6250 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6251 /* operate blindly on all ports */
1202b4c6
WF		 6252 eldv = IBX_ELD_VALIDB;
6253 eldv |= IBX_ELD_VALIDB << 4;
6254 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6255 } else {
2582a850 6256 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6257 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6258 }
6259
3a9627f4
WF		 6260 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6261 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6262 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6263 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6264 } else
6265 I915_WRITE(aud_config, 0);
e0dac65e 6266
3a9627f4
WF		 6267 if (intel_eld_uptodate(connector,
6268 aud_cntrl_st2, eldv,
6269 aud_cntl_st, IBX_ELD_ADDRESS,
6270 hdmiw_hdmiedid))
6271 return;
6272
e0dac65e
WF		 6273 i = I915_READ(aud_cntrl_st2);
6274 i &= ~eldv;
6275 I915_WRITE(aud_cntrl_st2, i);
6276
6277 if (!eld[0])
6278 return;
6279
e0dac65e 6280 i = I915_READ(aud_cntl_st);
1202b4c6 6281 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6282 I915_WRITE(aud_cntl_st, i);
6283
6284 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6285 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6286 for (i = 0; i < len; i++)
6287 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6288
6289 i = I915_READ(aud_cntrl_st2);
6290 i |= eldv;
6291 I915_WRITE(aud_cntrl_st2, i);
6292}
6293
6294void intel_write_eld(struct drm_encoder *encoder,
6295 struct drm_display_mode *mode)
6296{
6297 struct drm_crtc *crtc = encoder->crtc;
6298 struct drm_connector *connector;
6299 struct drm_device *dev = encoder->dev;
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301
6302 connector = drm_select_eld(encoder, mode);
6303 if (!connector)
6304 return;
6305
6306 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6307 connector->base.id,
6308 drm_get_connector_name(connector),
6309 connector->encoder->base.id,
6310 drm_get_encoder_name(connector->encoder));
6311
6312 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6313
6314 if (dev_priv->display.write_eld)
6315 dev_priv->display.write_eld(connector, crtc);
6316}
6317
79e53945
JB		 6318/** Loads the palette/gamma unit for the CRTC with the prepared values */
6319void intel_crtc_load_lut(struct drm_crtc *crtc)
6320{
6321 struct drm_device *dev = crtc->dev;
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6324 enum pipe pipe = intel_crtc->pipe;
6325 int palreg = PALETTE(pipe);
79e53945 6326 int i;
42db64ef 6327 bool reenable_ips = false;
79e53945
JB		 6328
6329 /* The clocks have to be on to load the palette. */
aed3f09d 6330 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6331 return;
6332
14420bd0
VS		 6333 if (!HAS_PCH_SPLIT(dev_priv->dev))
6334 assert_pll_enabled(dev_priv, pipe);
6335
f2b115e6 6336 /* use legacy palette for Ironlake */
bad720ff 6337 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6338 palreg = LGC_PALETTE(pipe);
6339
6340 /* Workaround : Do not read or write the pipe palette/gamma data while
6341 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6342 */
6343 if (intel_crtc->config.ips_enabled &&
6344 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6345 GAMMA_MODE_MODE_SPLIT)) {
6346 hsw_disable_ips(intel_crtc);
6347 reenable_ips = true;
6348 }
2c07245f 6349
79e53945
JB		 6350 for (i = 0; i < 256; i++) {
6351 I915_WRITE(palreg + 4 * i,
6352 (intel_crtc->lut_r[i] << 16) |
6353 (intel_crtc->lut_g[i] << 8) |
6354 intel_crtc->lut_b[i]);
6355 }
42db64ef
PZ		 6356
6357 if (reenable_ips)
6358 hsw_enable_ips(intel_crtc);
79e53945
JB		 6359}
6360
560b85bb
CW		 6361static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6362{
6363 struct drm_device *dev = crtc->dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 bool visible = base != 0;
6367 u32 cntl;
6368
6369 if (intel_crtc->cursor_visible == visible)
6370 return;
6371
9db4a9c7 6372 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6373 if (visible) {
6374 /* On these chipsets we can only modify the base whilst
6375 * the cursor is disabled.
6376 */
9db4a9c7 6377 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6378
6379 cntl &= ~(CURSOR_FORMAT_MASK);
6380 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6381 cntl |= CURSOR_ENABLE |
6382 CURSOR_GAMMA_ENABLE |
6383 CURSOR_FORMAT_ARGB;
6384 } else
6385 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6386 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6387
6388 intel_crtc->cursor_visible = visible;
6389}
6390
6391static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6392{
6393 struct drm_device *dev = crtc->dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396 int pipe = intel_crtc->pipe;
6397 bool visible = base != 0;
6398
6399 if (intel_crtc->cursor_visible != visible) {
548f245b 6400 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6401 if (base) {
6402 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6403 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6404 cntl |= pipe << 28; /* Connect to correct pipe */
6405 } else {
6406 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6407 cntl |= CURSOR_MODE_DISABLE;
6408 }
9db4a9c7 6409 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6410
6411 intel_crtc->cursor_visible = visible;
6412 }
6413 /* and commit changes on next vblank */
9db4a9c7 6414 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6415}
6416
65a21cd6
JB		 6417static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6418{
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 int pipe = intel_crtc->pipe;
6423 bool visible = base != 0;
6424
6425 if (intel_crtc->cursor_visible != visible) {
6426 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6427 if (base) {
6428 cntl &= ~CURSOR_MODE;
6429 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6430 } else {
6431 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6432 cntl |= CURSOR_MODE_DISABLE;
6433 }
86d3efce
VS		 6434 if (IS_HASWELL(dev))
6435 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6436 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6437
6438 intel_crtc->cursor_visible = visible;
6439 }
6440 /* and commit changes on next vblank */
6441 I915_WRITE(CURBASE_IVB(pipe), base);
6442}
6443
cda4b7d3 6444/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6445static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6446 bool on)
cda4b7d3
CW		 6447{
6448 struct drm_device *dev = crtc->dev;
6449 struct drm_i915_private *dev_priv = dev->dev_private;
6450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6451 int pipe = intel_crtc->pipe;
6452 int x = intel_crtc->cursor_x;
6453 int y = intel_crtc->cursor_y;
560b85bb 6454 u32 base, pos;
cda4b7d3
CW		 6455 bool visible;
6456
6457 pos = 0;
6458
6b383a7f 6459 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6460 base = intel_crtc->cursor_addr;
6461 if (x > (int) crtc->fb->width)
6462 base = 0;
6463
6464 if (y > (int) crtc->fb->height)
6465 base = 0;
6466 } else
6467 base = 0;
6468
6469 if (x < 0) {
6470 if (x + intel_crtc->cursor_width < 0)
6471 base = 0;
6472
6473 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6474 x = -x;
6475 }
6476 pos |= x << CURSOR_X_SHIFT;
6477
6478 if (y < 0) {
6479 if (y + intel_crtc->cursor_height < 0)
6480 base = 0;
6481
6482 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6483 y = -y;
6484 }
6485 pos |= y << CURSOR_Y_SHIFT;
6486
6487 visible = base != 0;
560b85bb 6488 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6489 return;
6490
0cd83aa9 6491 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6492 I915_WRITE(CURPOS_IVB(pipe), pos);
6493 ivb_update_cursor(crtc, base);
6494 } else {
6495 I915_WRITE(CURPOS(pipe), pos);
6496 if (IS_845G(dev) || IS_I865G(dev))
6497 i845_update_cursor(crtc, base);
6498 else
6499 i9xx_update_cursor(crtc, base);
6500 }
cda4b7d3
CW		 6501}
6502
79e53945 6503static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6504 struct drm_file *file,
79e53945
JB		 6505 uint32_t handle,
6506 uint32_t width, uint32_t height)
6507{
6508 struct drm_device *dev = crtc->dev;
6509 struct drm_i915_private *dev_priv = dev->dev_private;
6510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6511 struct drm_i915_gem_object *obj;
cda4b7d3 6512 uint32_t addr;
3f8bc370 6513 int ret;
79e53945 6514
79e53945
JB		 6515 /* if we want to turn off the cursor ignore width and height */
6516 if (!handle) {
28c97730 6517 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6518 addr = 0;
05394f39 6519 obj = NULL;
5004417d 6520 mutex_lock(&dev->struct_mutex);
3f8bc370 6521 goto finish;
79e53945
JB		 6522 }
6523
6524 /* Currently we only support 64x64 cursors */
6525 if (width != 64 || height != 64) {
6526 DRM_ERROR("we currently only support 64x64 cursors\n");
6527 return -EINVAL;
6528 }
6529
05394f39 6530 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6531 if (&obj->base == NULL)
79e53945
JB		 6532 return -ENOENT;
6533
05394f39 6534 if (obj->base.size < width * height * 4) {
79e53945 6535 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6536 ret = -ENOMEM;
6537 goto fail;
79e53945
JB		 6538 }
6539
71acb5eb 6540 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6541 mutex_lock(&dev->struct_mutex);
b295d1b6 6542 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6543 unsigned alignment;
6544
d9e86c0e
CW		 6545 if (obj->tiling_mode) {
6546 DRM_ERROR("cursor cannot be tiled\n");
6547 ret = -EINVAL;
6548 goto fail_locked;
6549 }
6550
693db184
CW		 6551 /* Note that the w/a also requires 2 PTE of padding following
6552 * the bo. We currently fill all unused PTE with the shadow
6553 * page and so we should always have valid PTE following the
6554 * cursor preventing the VT-d warning.
6555 */
6556 alignment = 0;
6557 if (need_vtd_wa(dev))
6558 alignment = 64*1024;
6559
6560 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6561 if (ret) {
6562 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6563 goto fail_locked;
e7b526bb
CW		 6564 }
6565
d9e86c0e
CW		 6566 ret = i915_gem_object_put_fence(obj);
6567 if (ret) {
2da3b9b9 6568 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6569 goto fail_unpin;
6570 }
6571
f343c5f6 6572 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6573 } else {
6eeefaf3 6574 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6575 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6576 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6577 align);
71acb5eb
DA		 6578 if (ret) {
6579 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6580 goto fail_locked;
71acb5eb 6581 }
05394f39 6582 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6583 }
6584
a6c45cf0 6585 if (IS_GEN2(dev))
14b60391
JB		 6586 I915_WRITE(CURSIZE, (height << 12) | width);
6587
3f8bc370 6588 finish:
3f8bc370 6589 if (intel_crtc->cursor_bo) {
b295d1b6 6590 if (dev_priv->info->cursor_needs_physical) {
05394f39 6591 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6592 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6593 } else
6594 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6595 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6596 }
80824003 6597
7f9872e0 6598 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6599
6600 intel_crtc->cursor_addr = addr;
05394f39 6601 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6602 intel_crtc->cursor_width = width;
6603 intel_crtc->cursor_height = height;
6604
40ccc72b 6605 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6606
79e53945 6607 return 0;
e7b526bb 6608fail_unpin:
05394f39 6609 i915_gem_object_unpin(obj);
7f9872e0 6610fail_locked:
34b8686e 6611 mutex_unlock(&dev->struct_mutex);
bc9025bd 6612fail:
05394f39 6613 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6614 return ret;
79e53945
JB		 6615}
6616
6617static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6618{
79e53945 6619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6620
cda4b7d3
CW		 6621 intel_crtc->cursor_x = x;
6622 intel_crtc->cursor_y = y;
652c393a 6623
40ccc72b 6624 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6625
6626 return 0;
6627}
6628
6629/** Sets the color ramps on behalf of RandR */
6630void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6631 u16 blue, int regno)
6632{
6633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6634
6635 intel_crtc->lut_r[regno] = red >> 8;
6636 intel_crtc->lut_g[regno] = green >> 8;
6637 intel_crtc->lut_b[regno] = blue >> 8;
6638}
6639
b8c00ac5
DA		 6640void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6641 u16 *blue, int regno)
6642{
6643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6644
6645 *red = intel_crtc->lut_r[regno] << 8;
6646 *green = intel_crtc->lut_g[regno] << 8;
6647 *blue = intel_crtc->lut_b[regno] << 8;
6648}
6649
79e53945 6650static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6651 u16 *blue, uint32_t start, uint32_t size)
79e53945 6652{
7203425a 6653 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6655
7203425a 6656 for (i = start; i < end; i++) {
79e53945
JB		 6657 intel_crtc->lut_r[i] = red[i] >> 8;
6658 intel_crtc->lut_g[i] = green[i] >> 8;
6659 intel_crtc->lut_b[i] = blue[i] >> 8;
6660 }
6661
6662 intel_crtc_load_lut(crtc);
6663}
6664
79e53945
JB		 6665/* VESA 640x480x72Hz mode to set on the pipe */
6666static struct drm_display_mode load_detect_mode = {
6667 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6668 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6669};
6670
d2dff872
CW		 6671static struct drm_framebuffer *
6672intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6673 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6674 struct drm_i915_gem_object *obj)
6675{
6676 struct intel_framebuffer *intel_fb;
6677 int ret;
6678
6679 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6680 if (!intel_fb) {
6681 drm_gem_object_unreference_unlocked(&obj->base);
6682 return ERR_PTR(-ENOMEM);
6683 }
6684
6685 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6686 if (ret) {
6687 drm_gem_object_unreference_unlocked(&obj->base);
6688 kfree(intel_fb);
6689 return ERR_PTR(ret);
6690 }
6691
6692 return &intel_fb->base;
6693}
6694
6695static u32
6696intel_framebuffer_pitch_for_width(int width, int bpp)
6697{
6698 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6699 return ALIGN(pitch, 64);
6700}
6701
6702static u32
6703intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6704{
6705 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6706 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6707}
6708
6709static struct drm_framebuffer *
6710intel_framebuffer_create_for_mode(struct drm_device *dev,
6711 struct drm_display_mode *mode,
6712 int depth, int bpp)
6713{
6714 struct drm_i915_gem_object *obj;
0fed39bd 6715 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6716
6717 obj = i915_gem_alloc_object(dev,
6718 intel_framebuffer_size_for_mode(mode, bpp));
6719 if (obj == NULL)
6720 return ERR_PTR(-ENOMEM);
6721
6722 mode_cmd.width = mode->hdisplay;
6723 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6724 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6725 bpp);
5ca0c34a 6726 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6727
6728 return intel_framebuffer_create(dev, &mode_cmd, obj);
6729}
6730
6731static struct drm_framebuffer *
6732mode_fits_in_fbdev(struct drm_device *dev,
6733 struct drm_display_mode *mode)
6734{
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct drm_i915_gem_object *obj;
6737 struct drm_framebuffer *fb;
6738
6739 if (dev_priv->fbdev == NULL)
6740 return NULL;
6741
6742 obj = dev_priv->fbdev->ifb.obj;
6743 if (obj == NULL)
6744 return NULL;
6745
6746 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6747 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6748 fb->bits_per_pixel))
d2dff872
CW		 6749 return NULL;
6750
01f2c773 6751 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6752 return NULL;
6753
6754 return fb;
6755}
6756
d2434ab7 6757bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6758 struct drm_display_mode *mode,
8261b191 6759 struct intel_load_detect_pipe *old)
79e53945
JB		 6760{
6761 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6762 struct intel_encoder *intel_encoder =
6763 intel_attached_encoder(connector);
79e53945 6764 struct drm_crtc *possible_crtc;
4ef69c7a 6765 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6766 struct drm_crtc *crtc = NULL;
6767 struct drm_device *dev = encoder->dev;
94352cf9 6768 struct drm_framebuffer *fb;
79e53945
JB		 6769 int i = -1;
6770
d2dff872
CW		 6771 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6772 connector->base.id, drm_get_connector_name(connector),
6773 encoder->base.id, drm_get_encoder_name(encoder));
6774
79e53945
JB		 6775 /*
6776 * Algorithm gets a little messy:
7a5e4805 6777 *
79e53945
JB		 6778 * - if the connector already has an assigned crtc, use it (but make
6779 * sure it's on first)
7a5e4805 6780 *
79e53945
JB		 6781 * - try to find the first unused crtc that can drive this connector,
6782 * and use that if we find one
79e53945
JB		 6783 */
6784
6785 /* See if we already have a CRTC for this connector */
6786 if (encoder->crtc) {
6787 crtc = encoder->crtc;
8261b191 6788
7b24056b
DV		 6789 mutex_lock(&crtc->mutex);
6790
24218aac 6791 old->dpms_mode = connector->dpms;
8261b191
CW		 6792 old->load_detect_temp = false;
6793
6794 /* Make sure the crtc and connector are running */
24218aac
DV		 6795 if (connector->dpms != DRM_MODE_DPMS_ON)
6796 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6797
7173188d 6798 return true;
79e53945
JB		 6799 }
6800
6801 /* Find an unused one (if possible) */
6802 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6803 i++;
6804 if (!(encoder->possible_crtcs & (1 << i)))
6805 continue;
6806 if (!possible_crtc->enabled) {
6807 crtc = possible_crtc;
6808 break;
6809 }
79e53945
JB		 6810 }
6811
6812 /*
6813 * If we didn't find an unused CRTC, don't use any.
6814 */
6815 if (!crtc) {
7173188d
CW		 6816 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6817 return false;
79e53945
JB		 6818 }
6819
7b24056b 6820 mutex_lock(&crtc->mutex);
fc303101
DV		 6821 intel_encoder->new_crtc = to_intel_crtc(crtc);
6822 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6823
6824 intel_crtc = to_intel_crtc(crtc);
24218aac 6825 old->dpms_mode = connector->dpms;
8261b191 6826 old->load_detect_temp = true;
d2dff872 6827 old->release_fb = NULL;
79e53945 6828
6492711d
CW		 6829 if (!mode)
6830 mode = &load_detect_mode;
79e53945 6831
d2dff872
CW		 6832 /* We need a framebuffer large enough to accommodate all accesses
6833 * that the plane may generate whilst we perform load detection.
6834 * We can not rely on the fbcon either being present (we get called
6835 * during its initialisation to detect all boot displays, or it may
6836 * not even exist) or that it is large enough to satisfy the
6837 * requested mode.
6838 */
94352cf9
DV		 6839 fb = mode_fits_in_fbdev(dev, mode);
6840 if (fb == NULL) {
d2dff872 6841 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6842 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6843 old->release_fb = fb;
d2dff872
CW		 6844 } else
6845 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6846 if (IS_ERR(fb)) {
d2dff872 6847 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6848 mutex_unlock(&crtc->mutex);
0e8b3d3e 6849 return false;
79e53945 6850 }
79e53945 6851
c0c36b94 6852 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6853 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6854 if (old->release_fb)
6855 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6856 mutex_unlock(&crtc->mutex);
0e8b3d3e 6857 return false;
79e53945 6858 }
7173188d 6859
79e53945 6860 /* let the connector get through one full cycle before testing */
9d0498a2 6861 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6862 return true;
79e53945
JB		 6863}
6864
d2434ab7 6865void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6866 struct intel_load_detect_pipe *old)
79e53945 6867{
d2434ab7
DV		 6868 struct intel_encoder *intel_encoder =
6869 intel_attached_encoder(connector);
4ef69c7a 6870 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6871 struct drm_crtc *crtc = encoder->crtc;
79e53945 6872
d2dff872
CW		 6873 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6874 connector->base.id, drm_get_connector_name(connector),
6875 encoder->base.id, drm_get_encoder_name(encoder));
6876
8261b191 6877 if (old->load_detect_temp) {
fc303101
DV		 6878 to_intel_connector(connector)->new_encoder = NULL;
6879 intel_encoder->new_crtc = NULL;
6880 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6881
36206361
DV		 6882 if (old->release_fb) {
6883 drm_framebuffer_unregister_private(old->release_fb);
6884 drm_framebuffer_unreference(old->release_fb);
6885 }
d2dff872 6886
67c96400 6887 mutex_unlock(&crtc->mutex);
0622a53c 6888 return;
79e53945
JB		 6889 }
6890
c751ce4f 6891 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6892 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6893 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6894
6895 mutex_unlock(&crtc->mutex);
79e53945
JB		 6896}
6897
6898/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6899static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6900 struct intel_crtc_config *pipe_config)
79e53945 6901{
f1f644dc 6902 struct drm_device *dev = crtc->base.dev;
79e53945 6903 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6904 int pipe = pipe_config->cpu_transcoder;
548f245b 6905 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6906 u32 fp;
6907 intel_clock_t clock;
6908
6909 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6910 fp = I915_READ(FP0(pipe));
79e53945 6911 else
39adb7a5 6912 fp = I915_READ(FP1(pipe));
79e53945
JB		 6913
6914 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6915 if (IS_PINEVIEW(dev)) {
6916 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6917 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6918 } else {
6919 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6920 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6921 }
6922
a6c45cf0 6923 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6924 if (IS_PINEVIEW(dev))
6925 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6926 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6927 else
6928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6929 DPLL_FPA01_P1_POST_DIV_SHIFT);
6930
6931 switch (dpll & DPLL_MODE_MASK) {
6932 case DPLLB_MODE_DAC_SERIAL:
6933 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6934 5 : 10;
6935 break;
6936 case DPLLB_MODE_LVDS:
6937 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6938 7 : 14;
6939 break;
6940 default:
28c97730 6941 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6942 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6943 pipe_config->adjusted_mode.clock = 0;
6944 return;
79e53945
JB		 6945 }
6946
ac58c3f0
DV		 6947 if (IS_PINEVIEW(dev))
6948 pineview_clock(96000, &clock);
6949 else
6950 i9xx_clock(96000, &clock);
79e53945
JB		 6951 } else {
6952 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6953
6954 if (is_lvds) {
6955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6956 DPLL_FPA01_P1_POST_DIV_SHIFT);
6957 clock.p2 = 14;
6958
6959 if ((dpll & PLL_REF_INPUT_MASK) ==
6960 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6961 /* XXX: might not be 66MHz */
ac58c3f0 6962 i9xx_clock(66000, &clock);
79e53945 6963 } else
ac58c3f0 6964 i9xx_clock(48000, &clock);
79e53945
JB		 6965 } else {
6966 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6967 clock.p1 = 2;
6968 else {
6969 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6970 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6971 }
6972 if (dpll & PLL_P2_DIVIDE_BY_4)
6973 clock.p2 = 4;
6974 else
6975 clock.p2 = 2;
6976
ac58c3f0 6977 i9xx_clock(48000, &clock);
79e53945
JB		 6978 }
6979 }
6980
f1f644dc
JB		 6981 pipe_config->adjusted_mode.clock = clock.dot *
6982 pipe_config->pixel_multiplier;
6983}
6984
6985static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6986 struct intel_crtc_config *pipe_config)
6987{
6988 struct drm_device *dev = crtc->base.dev;
6989 struct drm_i915_private *dev_priv = dev->dev_private;
6990 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6991 int link_freq, repeat;
6992 u64 clock;
6993 u32 link_m, link_n;
6994
6995 repeat = pipe_config->pixel_multiplier;
6996
6997 /*
6998 * The calculation for the data clock is:
6999 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7000 * But we want to avoid losing precison if possible, so:
7001 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7002 *
7003 * and the link clock is simpler:
7004 * link_clock = (m * link_clock * repeat) / n
7005 */
7006
7007 /*
7008 * We need to get the FDI or DP link clock here to derive
7009 * the M/N dividers.
7010 *
7011 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7012 * For DP, it's either 1.62GHz or 2.7GHz.
7013 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7014 */
f1f644dc
JB		 7015 if (pipe_config->has_pch_encoder)
7016 link_freq = intel_fdi_link_freq(dev) * 10000;
7017 else
7018 link_freq = pipe_config->port_clock;
7019
7020 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7021 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7022
7023 if (!link_m || !link_n)
7024 return;
79e53945 7025
f1f644dc
JB		 7026 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7027 do_div(clock, link_n);
7028
7029 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7030}
7031
7032/** Returns the currently programmed mode of the given pipe. */
7033struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7034 struct drm_crtc *crtc)
7035{
548f245b 7036 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7038 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7039 struct drm_display_mode *mode;
f1f644dc 7040 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7041 int htot = I915_READ(HTOTAL(cpu_transcoder));
7042 int hsync = I915_READ(HSYNC(cpu_transcoder));
7043 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7044 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7045
7046 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7047 if (!mode)
7048 return NULL;
7049
f1f644dc
JB		 7050 /*
7051 * Construct a pipe_config sufficient for getting the clock info
7052 * back out of crtc_clock_get.
7053 *
7054 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7055 * to use a real value here instead.
7056 */
e143a21c 7057 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7058 pipe_config.pixel_multiplier = 1;
7059 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7060
7061 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7062 mode->hdisplay = (htot & 0xffff) + 1;
7063 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7064 mode->hsync_start = (hsync & 0xffff) + 1;
7065 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7066 mode->vdisplay = (vtot & 0xffff) + 1;
7067 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7068 mode->vsync_start = (vsync & 0xffff) + 1;
7069 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7070
7071 drm_mode_set_name(mode);
79e53945
JB		 7072
7073 return mode;
7074}
7075
3dec0095 7076static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7077{
7078 struct drm_device *dev = crtc->dev;
7079 drm_i915_private_t *dev_priv = dev->dev_private;
7080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7082 int dpll_reg = DPLL(pipe);
7083 int dpll;
652c393a 7084
bad720ff 7085 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7086 return;
7087
7088 if (!dev_priv->lvds_downclock_avail)
7089 return;
7090
dbdc6479 7091 dpll = I915_READ(dpll_reg);
652c393a 7092 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7093 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7094
8ac5a6d5 7095 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7096
7097 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7098 I915_WRITE(dpll_reg, dpll);
9d0498a2 7099 intel_wait_for_vblank(dev, pipe);
dbdc6479 7100
652c393a
JB		 7101 dpll = I915_READ(dpll_reg);
7102 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7103 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7104 }
652c393a
JB		 7105}
7106
7107static void intel_decrease_pllclock(struct drm_crtc *crtc)
7108{
7109 struct drm_device *dev = crtc->dev;
7110 drm_i915_private_t *dev_priv = dev->dev_private;
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7112
bad720ff 7113 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7114 return;
7115
7116 if (!dev_priv->lvds_downclock_avail)
7117 return;
7118
7119 /*
7120 * Since this is called by a timer, we should never get here in
7121 * the manual case.
7122 */
7123 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7124 int pipe = intel_crtc->pipe;
7125 int dpll_reg = DPLL(pipe);
7126 int dpll;
f6e5b160 7127
44d98a61 7128 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7129
8ac5a6d5 7130 assert_panel_unlocked(dev_priv, pipe);
652c393a 7131
dc257cf1 7132 dpll = I915_READ(dpll_reg);
652c393a
JB		 7133 dpll |= DISPLAY_RATE_SELECT_FPA1;
7134 I915_WRITE(dpll_reg, dpll);
9d0498a2 7135 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7136 dpll = I915_READ(dpll_reg);
7137 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7138 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7139 }
7140
7141}
7142
f047e395
CW		 7143void intel_mark_busy(struct drm_device *dev)
7144{
f047e395
CW		 7145 i915_update_gfx_val(dev->dev_private);
7146}
7147
7148void intel_mark_idle(struct drm_device *dev)
652c393a 7149{
652c393a 7150 struct drm_crtc *crtc;
652c393a
JB		 7151
7152 if (!i915_powersave)
7153 return;
7154
652c393a 7155 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7156 if (!crtc->fb)
7157 continue;
7158
725a5b54 7159 intel_decrease_pllclock(crtc);
652c393a 7160 }
652c393a
JB		 7161}
7162
c65355bb
CW		 7163void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7164 struct intel_ring_buffer *ring)
652c393a 7165{
f047e395
CW		 7166 struct drm_device *dev = obj->base.dev;
7167 struct drm_crtc *crtc;
652c393a 7168
f047e395 7169 if (!i915_powersave)
acb87dfb
CW		 7170 return;
7171
652c393a
JB		 7172 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7173 if (!crtc->fb)
7174 continue;
7175
c65355bb
CW		 7176 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7177 continue;
7178
7179 intel_increase_pllclock(crtc);
7180 if (ring && intel_fbc_enabled(dev))
7181 ring->fbc_dirty = true;
652c393a
JB		 7182 }
7183}
7184
79e53945
JB		 7185static void intel_crtc_destroy(struct drm_crtc *crtc)
7186{
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7188 struct drm_device *dev = crtc->dev;
7189 struct intel_unpin_work *work;
7190 unsigned long flags;
7191
7192 spin_lock_irqsave(&dev->event_lock, flags);
7193 work = intel_crtc->unpin_work;
7194 intel_crtc->unpin_work = NULL;
7195 spin_unlock_irqrestore(&dev->event_lock, flags);
7196
7197 if (work) {
7198 cancel_work_sync(&work->work);
7199 kfree(work);
7200 }
79e53945 7201
40ccc72b
MK		 7202 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7203
79e53945 7204 drm_crtc_cleanup(crtc);
67e77c5a 7205
79e53945
JB		 7206 kfree(intel_crtc);
7207}
7208
6b95a207
KH		 7209static void intel_unpin_work_fn(struct work_struct *__work)
7210{
7211 struct intel_unpin_work *work =
7212 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7213 struct drm_device *dev = work->crtc->dev;
6b95a207 7214
b4a98e57 7215 mutex_lock(&dev->struct_mutex);
1690e1eb 7216 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7217 drm_gem_object_unreference(&work->pending_flip_obj->base);
7218 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7219
b4a98e57
CW		 7220 intel_update_fbc(dev);
7221 mutex_unlock(&dev->struct_mutex);
7222
7223 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7224 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7225
6b95a207
KH		 7226 kfree(work);
7227}
7228
1afe3e9d 7229static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7230 struct drm_crtc *crtc)
6b95a207
KH		 7231{
7232 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7234 struct intel_unpin_work *work;
6b95a207
KH		 7235 unsigned long flags;
7236
7237 /* Ignore early vblank irqs */
7238 if (intel_crtc == NULL)
7239 return;
7240
7241 spin_lock_irqsave(&dev->event_lock, flags);
7242 work = intel_crtc->unpin_work;
e7d841ca
CW		 7243
7244 /* Ensure we don't miss a work->pending update ... */
7245 smp_rmb();
7246
7247 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7248 spin_unlock_irqrestore(&dev->event_lock, flags);
7249 return;
7250 }
7251
e7d841ca
CW		 7252 /* and that the unpin work is consistent wrt ->pending. */
7253 smp_rmb();
7254
6b95a207 7255 intel_crtc->unpin_work = NULL;
6b95a207 7256
45a066eb
RC		 7257 if (work->event)
7258 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7259
0af7e4df
MK		 7260 drm_vblank_put(dev, intel_crtc->pipe);
7261
6b95a207
KH		 7262 spin_unlock_irqrestore(&dev->event_lock, flags);
7263
2c10d571 7264 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7265
7266 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7267
7268 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7269}
7270
1afe3e9d
JB		 7271void intel_finish_page_flip(struct drm_device *dev, int pipe)
7272{
7273 drm_i915_private_t *dev_priv = dev->dev_private;
7274 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7275
49b14a5c 7276 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7277}
7278
7279void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7280{
7281 drm_i915_private_t *dev_priv = dev->dev_private;
7282 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7283
49b14a5c 7284 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7285}
7286
6b95a207
KH		 7287void intel_prepare_page_flip(struct drm_device *dev, int plane)
7288{
7289 drm_i915_private_t *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc =
7291 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7292 unsigned long flags;
7293
e7d841ca
CW		 7294 /* NB: An MMIO update of the plane base pointer will also
7295 * generate a page-flip completion irq, i.e. every modeset
7296 * is also accompanied by a spurious intel_prepare_page_flip().
7297 */
6b95a207 7298 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7299 if (intel_crtc->unpin_work)
7300 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7301 spin_unlock_irqrestore(&dev->event_lock, flags);
7302}
7303
e7d841ca
CW		 7304inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7305{
7306 /* Ensure that the work item is consistent when activating it ... */
7307 smp_wmb();
7308 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7309 /* and that it is marked active as soon as the irq could fire. */
7310 smp_wmb();
7311}
7312
8c9f3aaf
JB		 7313static int intel_gen2_queue_flip(struct drm_device *dev,
7314 struct drm_crtc *crtc,
7315 struct drm_framebuffer *fb,
7316 struct drm_i915_gem_object *obj)
7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7320 u32 flip_mask;
6d90c952 7321 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7322 int ret;
7323
6d90c952 7324 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7325 if (ret)
83d4092b 7326 goto err;
8c9f3aaf 7327
6d90c952 7328 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7329 if (ret)
83d4092b 7330 goto err_unpin;
8c9f3aaf
JB		 7331
7332 /* Can't queue multiple flips, so wait for the previous
7333 * one to finish before executing the next.
7334 */
7335 if (intel_crtc->plane)
7336 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7337 else
7338 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7339 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7340 intel_ring_emit(ring, MI_NOOP);
7341 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7343 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7344 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7345 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7346
7347 intel_mark_page_flip_active(intel_crtc);
6d90c952 7348 intel_ring_advance(ring);
83d4092b
CW		 7349 return 0;
7350
7351err_unpin:
7352 intel_unpin_fb_obj(obj);
7353err:
8c9f3aaf
JB		 7354 return ret;
7355}
7356
7357static int intel_gen3_queue_flip(struct drm_device *dev,
7358 struct drm_crtc *crtc,
7359 struct drm_framebuffer *fb,
7360 struct drm_i915_gem_object *obj)
7361{
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7364 u32 flip_mask;
6d90c952 7365 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7366 int ret;
7367
6d90c952 7368 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7369 if (ret)
83d4092b 7370 goto err;
8c9f3aaf 7371
6d90c952 7372 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7373 if (ret)
83d4092b 7374 goto err_unpin;
8c9f3aaf
JB		 7375
7376 if (intel_crtc->plane)
7377 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7378 else
7379 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7380 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7381 intel_ring_emit(ring, MI_NOOP);
7382 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7383 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7384 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7385 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7386 intel_ring_emit(ring, MI_NOOP);
7387
e7d841ca 7388 intel_mark_page_flip_active(intel_crtc);
6d90c952 7389 intel_ring_advance(ring);
83d4092b
CW		 7390 return 0;
7391
7392err_unpin:
7393 intel_unpin_fb_obj(obj);
7394err:
8c9f3aaf
JB		 7395 return ret;
7396}
7397
7398static int intel_gen4_queue_flip(struct drm_device *dev,
7399 struct drm_crtc *crtc,
7400 struct drm_framebuffer *fb,
7401 struct drm_i915_gem_object *obj)
7402{
7403 struct drm_i915_private *dev_priv = dev->dev_private;
7404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7405 uint32_t pf, pipesrc;
6d90c952 7406 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7407 int ret;
7408
6d90c952 7409 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7410 if (ret)
83d4092b 7411 goto err;
8c9f3aaf 7412
6d90c952 7413 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7414 if (ret)
83d4092b 7415 goto err_unpin;
8c9f3aaf
JB		 7416
7417 /* i965+ uses the linear or tiled offsets from the
7418 * Display Registers (which do not change across a page-flip)
7419 * so we need only reprogram the base address.
7420 */
6d90c952
DV		 7421 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7422 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7423 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7424 intel_ring_emit(ring,
f343c5f6 7425 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7426 obj->tiling_mode);
8c9f3aaf
JB		 7427
7428 /* XXX Enabling the panel-fitter across page-flip is so far
7429 * untested on non-native modes, so ignore it for now.
7430 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7431 */
7432 pf = 0;
7433 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7434 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7435
7436 intel_mark_page_flip_active(intel_crtc);
6d90c952 7437 intel_ring_advance(ring);
83d4092b
CW		 7438 return 0;
7439
7440err_unpin:
7441 intel_unpin_fb_obj(obj);
7442err:
8c9f3aaf
JB		 7443 return ret;
7444}
7445
7446static int intel_gen6_queue_flip(struct drm_device *dev,
7447 struct drm_crtc *crtc,
7448 struct drm_framebuffer *fb,
7449 struct drm_i915_gem_object *obj)
7450{
7451 struct drm_i915_private *dev_priv = dev->dev_private;
7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7453 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7454 uint32_t pf, pipesrc;
7455 int ret;
7456
6d90c952 7457 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7458 if (ret)
83d4092b 7459 goto err;
8c9f3aaf 7460
6d90c952 7461 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7462 if (ret)
83d4092b 7463 goto err_unpin;
8c9f3aaf 7464
6d90c952
DV		 7465 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7466 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7467 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7468 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7469
dc257cf1
DV		 7470 /* Contrary to the suggestions in the documentation,
7471 * "Enable Panel Fitter" does not seem to be required when page
7472 * flipping with a non-native mode, and worse causes a normal
7473 * modeset to fail.
7474 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7475 */
7476 pf = 0;
8c9f3aaf 7477 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7478 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7479
7480 intel_mark_page_flip_active(intel_crtc);
6d90c952 7481 intel_ring_advance(ring);
83d4092b
CW		 7482 return 0;
7483
7484err_unpin:
7485 intel_unpin_fb_obj(obj);
7486err:
8c9f3aaf
JB		 7487 return ret;
7488}
7489
7c9017e5
JB		 7490/*
7491 * On gen7 we currently use the blit ring because (in early silicon at least)
7492 * the render ring doesn't give us interrpts for page flip completion, which
7493 * means clients will hang after the first flip is queued. Fortunately the
7494 * blit ring generates interrupts properly, so use it instead.
7495 */
7496static int intel_gen7_queue_flip(struct drm_device *dev,
7497 struct drm_crtc *crtc,
7498 struct drm_framebuffer *fb,
7499 struct drm_i915_gem_object *obj)
7500{
7501 struct drm_i915_private *dev_priv = dev->dev_private;
7502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7503 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7504 uint32_t plane_bit = 0;
7c9017e5
JB		 7505 int ret;
7506
7507 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7508 if (ret)
83d4092b 7509 goto err;
7c9017e5 7510
cb05d8de
DV		 7511 switch(intel_crtc->plane) {
7512 case PLANE_A:
7513 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7514 break;
7515 case PLANE_B:
7516 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7517 break;
7518 case PLANE_C:
7519 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7520 break;
7521 default:
7522 WARN_ONCE(1, "unknown plane in flip command\n");
7523 ret = -ENODEV;
ab3951eb 7524 goto err_unpin;
cb05d8de
DV		 7525 }
7526
7c9017e5
JB		 7527 ret = intel_ring_begin(ring, 4);
7528 if (ret)
83d4092b 7529 goto err_unpin;
7c9017e5 7530
cb05d8de 7531 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7532 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7533 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7534 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7535
7536 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7537 intel_ring_advance(ring);
83d4092b
CW		 7538 return 0;
7539
7540err_unpin:
7541 intel_unpin_fb_obj(obj);
7542err:
7c9017e5
JB		 7543 return ret;
7544}
7545
8c9f3aaf
JB		 7546static int intel_default_queue_flip(struct drm_device *dev,
7547 struct drm_crtc *crtc,
7548 struct drm_framebuffer *fb,
7549 struct drm_i915_gem_object *obj)
7550{
7551 return -ENODEV;
7552}
7553
6b95a207
KH		 7554static int intel_crtc_page_flip(struct drm_crtc *crtc,
7555 struct drm_framebuffer *fb,
7556 struct drm_pending_vblank_event *event)
7557{
7558 struct drm_device *dev = crtc->dev;
7559 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7560 struct drm_framebuffer *old_fb = crtc->fb;
7561 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7563 struct intel_unpin_work *work;
8c9f3aaf 7564 unsigned long flags;
52e68630 7565 int ret;
6b95a207 7566
e6a595d2
VS		 7567 /* Can't change pixel format via MI display flips. */
7568 if (fb->pixel_format != crtc->fb->pixel_format)
7569 return -EINVAL;
7570
7571 /*
7572 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7573 * Note that pitch changes could also affect these register.
7574 */
7575 if (INTEL_INFO(dev)->gen > 3 &&
7576 (fb->offsets[0] != crtc->fb->offsets[0] ||
7577 fb->pitches[0] != crtc->fb->pitches[0]))
7578 return -EINVAL;
7579
6b95a207
KH		 7580 work = kzalloc(sizeof *work, GFP_KERNEL);
7581 if (work == NULL)
7582 return -ENOMEM;
7583
6b95a207 7584 work->event = event;
b4a98e57 7585 work->crtc = crtc;
4a35f83b 7586 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7587 INIT_WORK(&work->work, intel_unpin_work_fn);
7588
7317c75e
JB		 7589 ret = drm_vblank_get(dev, intel_crtc->pipe);
7590 if (ret)
7591 goto free_work;
7592
6b95a207
KH		 7593 /* We borrow the event spin lock for protecting unpin_work */
7594 spin_lock_irqsave(&dev->event_lock, flags);
7595 if (intel_crtc->unpin_work) {
7596 spin_unlock_irqrestore(&dev->event_lock, flags);
7597 kfree(work);
7317c75e 7598 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7599
7600 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7601 return -EBUSY;
7602 }
7603 intel_crtc->unpin_work = work;
7604 spin_unlock_irqrestore(&dev->event_lock, flags);
7605
b4a98e57
CW		 7606 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7607 flush_workqueue(dev_priv->wq);
7608
79158103
CW		 7609 ret = i915_mutex_lock_interruptible(dev);
7610 if (ret)
7611 goto cleanup;
6b95a207 7612
75dfca80 7613 /* Reference the objects for the scheduled work. */
05394f39
CW		 7614 drm_gem_object_reference(&work->old_fb_obj->base);
7615 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7616
7617 crtc->fb = fb;
96b099fd 7618
e1f99ce6 7619 work->pending_flip_obj = obj;
e1f99ce6 7620
4e5359cd
SF		 7621 work->enable_stall_check = true;
7622
b4a98e57 7623 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7624 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7625
8c9f3aaf
JB		 7626 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7627 if (ret)
7628 goto cleanup_pending;
6b95a207 7629
7782de3b 7630 intel_disable_fbc(dev);
c65355bb 7631 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7632 mutex_unlock(&dev->struct_mutex);
7633
e5510fac
JB		 7634 trace_i915_flip_request(intel_crtc->plane, obj);
7635
6b95a207 7636 return 0;
96b099fd 7637
8c9f3aaf 7638cleanup_pending:
b4a98e57 7639 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7640 crtc->fb = old_fb;
05394f39
CW		 7641 drm_gem_object_unreference(&work->old_fb_obj->base);
7642 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7643 mutex_unlock(&dev->struct_mutex);
7644
79158103 7645cleanup:
96b099fd
CW		 7646 spin_lock_irqsave(&dev->event_lock, flags);
7647 intel_crtc->unpin_work = NULL;
7648 spin_unlock_irqrestore(&dev->event_lock, flags);
7649
7317c75e
JB		 7650 drm_vblank_put(dev, intel_crtc->pipe);
7651free_work:
96b099fd
CW		 7652 kfree(work);
7653
7654 return ret;
6b95a207
KH		 7655}
7656
f6e5b160 7657static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7658 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7659 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7660};
7661
50f56119
DV		 7662static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7663 struct drm_crtc *crtc)
7664{
7665 struct drm_device *dev;
7666 struct drm_crtc *tmp;
7667 int crtc_mask = 1;
47f1c6c9 7668
50f56119 7669 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7670
50f56119 7671 dev = crtc->dev;
47f1c6c9 7672
50f56119
DV		 7673 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7674 if (tmp == crtc)
7675 break;
7676 crtc_mask <<= 1;
7677 }
47f1c6c9 7678
50f56119
DV		 7679 if (encoder->possible_crtcs & crtc_mask)
7680 return true;
7681 return false;
47f1c6c9 7682}
79e53945 7683
9a935856
DV		 7684/**
7685 * intel_modeset_update_staged_output_state
7686 *
7687 * Updates the staged output configuration state, e.g. after we've read out the
7688 * current hw state.
7689 */
7690static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7691{
9a935856
DV		 7692 struct intel_encoder *encoder;
7693 struct intel_connector *connector;
f6e5b160 7694
9a935856
DV		 7695 list_for_each_entry(connector, &dev->mode_config.connector_list,
7696 base.head) {
7697 connector->new_encoder =
7698 to_intel_encoder(connector->base.encoder);
7699 }
f6e5b160 7700
9a935856
DV		 7701 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7702 base.head) {
7703 encoder->new_crtc =
7704 to_intel_crtc(encoder->base.crtc);
7705 }
f6e5b160
CW		 7706}
7707
9a935856
DV		 7708/**
7709 * intel_modeset_commit_output_state
7710 *
7711 * This function copies the stage display pipe configuration to the real one.
7712 */
7713static void intel_modeset_commit_output_state(struct drm_device *dev)
7714{
7715 struct intel_encoder *encoder;
7716 struct intel_connector *connector;
f6e5b160 7717
9a935856
DV		 7718 list_for_each_entry(connector, &dev->mode_config.connector_list,
7719 base.head) {
7720 connector->base.encoder = &connector->new_encoder->base;
7721 }
f6e5b160 7722
9a935856
DV		 7723 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7724 base.head) {
7725 encoder->base.crtc = &encoder->new_crtc->base;
7726 }
7727}
7728
050f7aeb
DV		 7729static void
7730connected_sink_compute_bpp(struct intel_connector * connector,
7731 struct intel_crtc_config *pipe_config)
7732{
7733 int bpp = pipe_config->pipe_bpp;
7734
7735 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7736 connector->base.base.id,
7737 drm_get_connector_name(&connector->base));
7738
7739 /* Don't use an invalid EDID bpc value */
7740 if (connector->base.display_info.bpc &&
7741 connector->base.display_info.bpc * 3 < bpp) {
7742 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7743 bpp, connector->base.display_info.bpc*3);
7744 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7745 }
7746
7747 /* Clamp bpp to 8 on screens without EDID 1.4 */
7748 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7749 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7750 bpp);
7751 pipe_config->pipe_bpp = 24;
7752 }
7753}
7754
4e53c2e0 7755static int
050f7aeb
DV		 7756compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7757 struct drm_framebuffer *fb,
7758 struct intel_crtc_config *pipe_config)
4e53c2e0 7759{
050f7aeb
DV		 7760 struct drm_device *dev = crtc->base.dev;
7761 struct intel_connector *connector;
4e53c2e0
DV		 7762 int bpp;
7763
d42264b1
DV		 7764 switch (fb->pixel_format) {
7765 case DRM_FORMAT_C8:
4e53c2e0
DV		 7766 bpp = 8*3; /* since we go through a colormap */
7767 break;
d42264b1
DV		 7768 case DRM_FORMAT_XRGB1555:
7769 case DRM_FORMAT_ARGB1555:
7770 /* checked in intel_framebuffer_init already */
7771 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7772 return -EINVAL;
7773 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7774 bpp = 6*3; /* min is 18bpp */
7775 break;
d42264b1
DV		 7776 case DRM_FORMAT_XBGR8888:
7777 case DRM_FORMAT_ABGR8888:
7778 /* checked in intel_framebuffer_init already */
7779 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7780 return -EINVAL;
7781 case DRM_FORMAT_XRGB8888:
7782 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7783 bpp = 8*3;
7784 break;
d42264b1
DV		 7785 case DRM_FORMAT_XRGB2101010:
7786 case DRM_FORMAT_ARGB2101010:
7787 case DRM_FORMAT_XBGR2101010:
7788 case DRM_FORMAT_ABGR2101010:
7789 /* checked in intel_framebuffer_init already */
7790 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7791 return -EINVAL;
4e53c2e0
DV		 7792 bpp = 10*3;
7793 break;
baba133a 7794 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7795 default:
7796 DRM_DEBUG_KMS("unsupported depth\n");
7797 return -EINVAL;
7798 }
7799
4e53c2e0
DV		 7800 pipe_config->pipe_bpp = bpp;
7801
7802 /* Clamp display bpp to EDID value */
7803 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7804 base.head) {
1b829e05
DV		 7805 if (!connector->new_encoder ||
7806 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7807 continue;
7808
050f7aeb 7809 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7810 }
7811
7812 return bpp;
7813}
7814
c0b03411
DV		 7815static void intel_dump_pipe_config(struct intel_crtc *crtc,
7816 struct intel_crtc_config *pipe_config,
7817 const char *context)
7818{
7819 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7820 context, pipe_name(crtc->pipe));
7821
7822 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7823 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7824 pipe_config->pipe_bpp, pipe_config->dither);
7825 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7826 pipe_config->has_pch_encoder,
7827 pipe_config->fdi_lanes,
7828 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7829 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7830 pipe_config->fdi_m_n.tu);
7831 DRM_DEBUG_KMS("requested mode:\n");
7832 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7833 DRM_DEBUG_KMS("adjusted mode:\n");
7834 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7835 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7836 pipe_config->gmch_pfit.control,
7837 pipe_config->gmch_pfit.pgm_ratios,
7838 pipe_config->gmch_pfit.lvds_border_bits);
7839 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7840 pipe_config->pch_pfit.pos,
7841 pipe_config->pch_pfit.size);
42db64ef 7842 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7843}
7844
accfc0c5
DV		 7845static bool check_encoder_cloning(struct drm_crtc *crtc)
7846{
7847 int num_encoders = 0;
7848 bool uncloneable_encoders = false;
7849 struct intel_encoder *encoder;
7850
7851 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7852 base.head) {
7853 if (&encoder->new_crtc->base != crtc)
7854 continue;
7855
7856 num_encoders++;
7857 if (!encoder->cloneable)
7858 uncloneable_encoders = true;
7859 }
7860
7861 return !(num_encoders > 1 && uncloneable_encoders);
7862}
7863
b8cecdf5
DV		 7864static struct intel_crtc_config *
7865intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7866 struct drm_framebuffer *fb,
b8cecdf5 7867 struct drm_display_mode *mode)
ee7b9f93 7868{
7758a113 7869 struct drm_device *dev = crtc->dev;
7758a113
DV		 7870 struct drm_encoder_helper_funcs *encoder_funcs;
7871 struct intel_encoder *encoder;
b8cecdf5 7872 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7873 int plane_bpp, ret = -EINVAL;
7874 bool retry = true;
ee7b9f93 7875
accfc0c5
DV		 7876 if (!check_encoder_cloning(crtc)) {
7877 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7878 return ERR_PTR(-EINVAL);
7879 }
7880
b8cecdf5
DV		 7881 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7882 if (!pipe_config)
7758a113
DV		 7883 return ERR_PTR(-ENOMEM);
7884
b8cecdf5
DV		 7885 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7886 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 7887 pipe_config->cpu_transcoder =
7888 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 7889 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7890
050f7aeb
DV		 7891 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7892 * plane pixel format and any sink constraints into account. Returns the
7893 * source plane bpp so that dithering can be selected on mismatches
7894 * after encoders and crtc also have had their say. */
7895 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7896 fb, pipe_config);
4e53c2e0
DV		 7897 if (plane_bpp < 0)
7898 goto fail;
7899
e29c22c0 7900encoder_retry:
ef1b460d 7901 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7902 pipe_config->port_clock = 0;
ef1b460d 7903 pipe_config->pixel_multiplier = 1;
ff9a6750 7904
7758a113
DV		 7905 /* Pass our mode to the connectors and the CRTC to give them a chance to
7906 * adjust it according to limitations or connector properties, and also
7907 * a chance to reject the mode entirely.
47f1c6c9 7908 */
7758a113
DV		 7909 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7910 base.head) {
47f1c6c9 7911
7758a113
DV		 7912 if (&encoder->new_crtc->base != crtc)
7913 continue;
7ae89233
DV		 7914
7915 if (encoder->compute_config) {
7916 if (!(encoder->compute_config(encoder, pipe_config))) {
7917 DRM_DEBUG_KMS("Encoder config failure\n");
7918 goto fail;
7919 }
7920
7921 continue;
7922 }
7923
7758a113 7924 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7925 if (!(encoder_funcs->mode_fixup(&encoder->base,
7926 &pipe_config->requested_mode,
7927 &pipe_config->adjusted_mode))) {
7758a113
DV		 7928 DRM_DEBUG_KMS("Encoder fixup failed\n");
7929 goto fail;
7930 }
ee7b9f93 7931 }
47f1c6c9 7932
ff9a6750
DV		 7933 /* Set default port clock if not overwritten by the encoder. Needs to be
7934 * done afterwards in case the encoder adjusts the mode. */
7935 if (!pipe_config->port_clock)
7936 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7937
a43f6e0f 7938 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7939 if (ret < 0) {
7758a113
DV		 7940 DRM_DEBUG_KMS("CRTC fixup failed\n");
7941 goto fail;
ee7b9f93 7942 }
e29c22c0
DV		 7943
7944 if (ret == RETRY) {
7945 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7946 ret = -EINVAL;
7947 goto fail;
7948 }
7949
7950 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7951 retry = false;
7952 goto encoder_retry;
7953 }
7954
4e53c2e0
DV		 7955 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7956 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7957 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7958
b8cecdf5 7959 return pipe_config;
7758a113 7960fail:
b8cecdf5 7961 kfree(pipe_config);
e29c22c0 7962 return ERR_PTR(ret);
ee7b9f93 7963}
47f1c6c9 7964
e2e1ed41
DV		 7965/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7966 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7967static void
7968intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7969 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7970{
7971 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7972 struct drm_device *dev = crtc->dev;
7973 struct intel_encoder *encoder;
7974 struct intel_connector *connector;
7975 struct drm_crtc *tmp_crtc;
79e53945 7976
e2e1ed41 7977 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7978
e2e1ed41
DV		 7979 /* Check which crtcs have changed outputs connected to them, these need
7980 * to be part of the prepare_pipes mask. We don't (yet) support global
7981 * modeset across multiple crtcs, so modeset_pipes will only have one
7982 * bit set at most. */
7983 list_for_each_entry(connector, &dev->mode_config.connector_list,
7984 base.head) {
7985 if (connector->base.encoder == &connector->new_encoder->base)
7986 continue;
79e53945 7987
e2e1ed41
DV		 7988 if (connector->base.encoder) {
7989 tmp_crtc = connector->base.encoder->crtc;
7990
7991 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7992 }
7993
7994 if (connector->new_encoder)
7995 *prepare_pipes |=
7996 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7997 }
7998
e2e1ed41
DV		 7999 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8000 base.head) {
8001 if (encoder->base.crtc == &encoder->new_crtc->base)
8002 continue;
8003
8004 if (encoder->base.crtc) {
8005 tmp_crtc = encoder->base.crtc;
8006
8007 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8008 }
8009
8010 if (encoder->new_crtc)
8011 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8012 }
8013
e2e1ed41
DV		 8014 /* Check for any pipes that will be fully disabled ... */
8015 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8016 base.head) {
8017 bool used = false;
22fd0fab 8018
e2e1ed41
DV		 8019 /* Don't try to disable disabled crtcs. */
8020 if (!intel_crtc->base.enabled)
8021 continue;
7e7d76c3 8022
e2e1ed41
DV		 8023 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8024 base.head) {
8025 if (encoder->new_crtc == intel_crtc)
8026 used = true;
8027 }
8028
8029 if (!used)
8030 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8031 }
8032
e2e1ed41
DV		 8033
8034 /* set_mode is also used to update properties on life display pipes. */
8035 intel_crtc = to_intel_crtc(crtc);
8036 if (crtc->enabled)
8037 *prepare_pipes |= 1 << intel_crtc->pipe;
8038
b6c5164d
DV		 8039 /*
8040 * For simplicity do a full modeset on any pipe where the output routing
8041 * changed. We could be more clever, but that would require us to be
8042 * more careful with calling the relevant encoder->mode_set functions.
8043 */
e2e1ed41
DV		 8044 if (*prepare_pipes)
8045 *modeset_pipes = *prepare_pipes;
8046
8047 /* ... and mask these out. */
8048 *modeset_pipes &= ~(*disable_pipes);
8049 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8050
8051 /*
8052 * HACK: We don't (yet) fully support global modesets. intel_set_config
8053 * obies this rule, but the modeset restore mode of
8054 * intel_modeset_setup_hw_state does not.
8055 */
8056 *modeset_pipes &= 1 << intel_crtc->pipe;
8057 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8058
8059 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8060 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8061}
79e53945 8062
ea9d758d 8063static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8064{
ea9d758d 8065 struct drm_encoder *encoder;
f6e5b160 8066 struct drm_device *dev = crtc->dev;
f6e5b160 8067
ea9d758d
DV		 8068 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8069 if (encoder->crtc == crtc)
8070 return true;
8071
8072 return false;
8073}
8074
8075static void
8076intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8077{
8078 struct intel_encoder *intel_encoder;
8079 struct intel_crtc *intel_crtc;
8080 struct drm_connector *connector;
8081
8082 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8083 base.head) {
8084 if (!intel_encoder->base.crtc)
8085 continue;
8086
8087 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8088
8089 if (prepare_pipes & (1 << intel_crtc->pipe))
8090 intel_encoder->connectors_active = false;
8091 }
8092
8093 intel_modeset_commit_output_state(dev);
8094
8095 /* Update computed state. */
8096 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8097 base.head) {
8098 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8099 }
8100
8101 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8102 if (!connector->encoder || !connector->encoder->crtc)
8103 continue;
8104
8105 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8106
8107 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8108 struct drm_property *dpms_property =
8109 dev->mode_config.dpms_property;
8110
ea9d758d 8111 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8112 drm_object_property_set_value(&connector->base,
68d34720
DV		 8113 dpms_property,
8114 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8115
8116 intel_encoder = to_intel_encoder(connector->encoder);
8117 intel_encoder->connectors_active = true;
8118 }
8119 }
8120
8121}
8122
f1f644dc
JB		 8123static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8124 struct intel_crtc_config *new)
8125{
8126 int clock1, clock2, diff;
8127
8128 clock1 = cur->adjusted_mode.clock;
8129 clock2 = new->adjusted_mode.clock;
8130
8131 if (clock1 == clock2)
8132 return true;
8133
8134 if (!clock1 || !clock2)
8135 return false;
8136
8137 diff = abs(clock1 - clock2);
8138
8139 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8140 return true;
8141
8142 return false;
8143}
8144
25c5b266
DV		 8145#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8146 list_for_each_entry((intel_crtc), \
8147 &(dev)->mode_config.crtc_list, \
8148 base.head) \
0973f18f 8149 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8150
0e8ffe1b 8151static bool
2fa2fe9a
DV		 8152intel_pipe_config_compare(struct drm_device *dev,
8153 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8154 struct intel_crtc_config *pipe_config)
8155{
66e985c0
DV		 8156#define PIPE_CONF_CHECK_X(name) \
8157 if (current_config->name != pipe_config->name) { \
8158 DRM_ERROR("mismatch in " #name " " \
8159 "(expected 0x%08x, found 0x%08x)\n", \
8160 current_config->name, \
8161 pipe_config->name); \
8162 return false; \
8163 }
8164
08a24034
DV		 8165#define PIPE_CONF_CHECK_I(name) \
8166 if (current_config->name != pipe_config->name) { \
8167 DRM_ERROR("mismatch in " #name " " \
8168 "(expected %i, found %i)\n", \
8169 current_config->name, \
8170 pipe_config->name); \
8171 return false; \
88adfff1
DV		 8172 }
8173
1bd1bd80
DV		 8174#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8175 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8176 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8177 "(expected %i, found %i)\n", \
8178 current_config->name & (mask), \
8179 pipe_config->name & (mask)); \
8180 return false; \
8181 }
8182
bb760063
DV		 8183#define PIPE_CONF_QUIRK(quirk) \
8184 ((current_config->quirks | pipe_config->quirks) & (quirk))
8185
eccb140b
DV		 8186 PIPE_CONF_CHECK_I(cpu_transcoder);
8187
08a24034
DV		 8188 PIPE_CONF_CHECK_I(has_pch_encoder);
8189 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8190 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8191 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8192 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8193 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8194 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8195
1bd1bd80
DV		 8196 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8197 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8198 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8199 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8200 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8201 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8202
8203 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8204 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8205 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8206 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8207 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8208 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8209
c93f54cf 8210 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8211
1bd1bd80
DV		 8212 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8213 DRM_MODE_FLAG_INTERLACE);
8214
bb760063
DV		 8215 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8216 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8217 DRM_MODE_FLAG_PHSYNC);
8218 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8219 DRM_MODE_FLAG_NHSYNC);
8220 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8221 DRM_MODE_FLAG_PVSYNC);
8222 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8223 DRM_MODE_FLAG_NVSYNC);
8224 }
045ac3b5 8225
1bd1bd80
DV		 8226 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8227 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8228
2fa2fe9a
DV		 8229 PIPE_CONF_CHECK_I(gmch_pfit.control);
8230 /* pfit ratios are autocomputed by the hw on gen4+ */
8231 if (INTEL_INFO(dev)->gen < 4)
8232 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8233 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8234 PIPE_CONF_CHECK_I(pch_pfit.pos);
8235 PIPE_CONF_CHECK_I(pch_pfit.size);
8236
42db64ef
PZ		 8237 PIPE_CONF_CHECK_I(ips_enabled);
8238
c0d43d62 8239 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8240 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8241 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8242 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8243 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8244
66e985c0 8245#undef PIPE_CONF_CHECK_X
08a24034 8246#undef PIPE_CONF_CHECK_I
1bd1bd80 8247#undef PIPE_CONF_CHECK_FLAGS
bb760063 8248#undef PIPE_CONF_QUIRK
88adfff1 8249
f1f644dc
JB		 8250 if (!IS_HASWELL(dev)) {
8251 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8252 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8253 current_config->adjusted_mode.clock,
8254 pipe_config->adjusted_mode.clock);
8255 return false;
8256 }
8257 }
8258
0e8ffe1b
DV		 8259 return true;
8260}
8261
91d1b4bd
DV		 8262static void
8263check_connector_state(struct drm_device *dev)
8af6cf88 8264{
8af6cf88
DV		 8265 struct intel_connector *connector;
8266
8267 list_for_each_entry(connector, &dev->mode_config.connector_list,
8268 base.head) {
8269 /* This also checks the encoder/connector hw state with the
8270 * ->get_hw_state callbacks. */
8271 intel_connector_check_state(connector);
8272
8273 WARN(&connector->new_encoder->base != connector->base.encoder,
8274 "connector's staged encoder doesn't match current encoder\n");
8275 }
91d1b4bd
DV		 8276}
8277
8278static void
8279check_encoder_state(struct drm_device *dev)
8280{
8281 struct intel_encoder *encoder;
8282 struct intel_connector *connector;
8af6cf88
DV		 8283
8284 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8285 base.head) {
8286 bool enabled = false;
8287 bool active = false;
8288 enum pipe pipe, tracked_pipe;
8289
8290 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8291 encoder->base.base.id,
8292 drm_get_encoder_name(&encoder->base));
8293
8294 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8295 "encoder's stage crtc doesn't match current crtc\n");
8296 WARN(encoder->connectors_active && !encoder->base.crtc,
8297 "encoder's active_connectors set, but no crtc\n");
8298
8299 list_for_each_entry(connector, &dev->mode_config.connector_list,
8300 base.head) {
8301 if (connector->base.encoder != &encoder->base)
8302 continue;
8303 enabled = true;
8304 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8305 active = true;
8306 }
8307 WARN(!!encoder->base.crtc != enabled,
8308 "encoder's enabled state mismatch "
8309 "(expected %i, found %i)\n",
8310 !!encoder->base.crtc, enabled);
8311 WARN(active && !encoder->base.crtc,
8312 "active encoder with no crtc\n");
8313
8314 WARN(encoder->connectors_active != active,
8315 "encoder's computed active state doesn't match tracked active state "
8316 "(expected %i, found %i)\n", active, encoder->connectors_active);
8317
8318 active = encoder->get_hw_state(encoder, &pipe);
8319 WARN(active != encoder->connectors_active,
8320 "encoder's hw state doesn't match sw tracking "
8321 "(expected %i, found %i)\n",
8322 encoder->connectors_active, active);
8323
8324 if (!encoder->base.crtc)
8325 continue;
8326
8327 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8328 WARN(active && pipe != tracked_pipe,
8329 "active encoder's pipe doesn't match"
8330 "(expected %i, found %i)\n",
8331 tracked_pipe, pipe);
8332
8333 }
91d1b4bd
DV		 8334}
8335
8336static void
8337check_crtc_state(struct drm_device *dev)
8338{
8339 drm_i915_private_t *dev_priv = dev->dev_private;
8340 struct intel_crtc *crtc;
8341 struct intel_encoder *encoder;
8342 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8343
8344 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8345 base.head) {
8346 bool enabled = false;
8347 bool active = false;
8348
045ac3b5
JB		 8349 memset(&pipe_config, 0, sizeof(pipe_config));
8350
8af6cf88
DV		 8351 DRM_DEBUG_KMS("[CRTC:%d]\n",
8352 crtc->base.base.id);
8353
8354 WARN(crtc->active && !crtc->base.enabled,
8355 "active crtc, but not enabled in sw tracking\n");
8356
8357 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8358 base.head) {
8359 if (encoder->base.crtc != &crtc->base)
8360 continue;
8361 enabled = true;
8362 if (encoder->connectors_active)
8363 active = true;
8364 }
6c49f241 8365
8af6cf88
DV		 8366 WARN(active != crtc->active,
8367 "crtc's computed active state doesn't match tracked active state "
8368 "(expected %i, found %i)\n", active, crtc->active);
8369 WARN(enabled != crtc->base.enabled,
8370 "crtc's computed enabled state doesn't match tracked enabled state "
8371 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8372
0e8ffe1b
DV		 8373 active = dev_priv->display.get_pipe_config(crtc,
8374 &pipe_config);
d62cf62a
DV		 8375
8376 /* hw state is inconsistent with the pipe A quirk */
8377 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8378 active = crtc->active;
8379
6c49f241
DV		 8380 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8381 base.head) {
8382 if (encoder->base.crtc != &crtc->base)
8383 continue;
510d5f2f 8384 if (encoder->get_config)
6c49f241
DV		 8385 encoder->get_config(encoder, &pipe_config);
8386 }
8387
510d5f2f
JB		 8388 if (dev_priv->display.get_clock)
8389 dev_priv->display.get_clock(crtc, &pipe_config);
8390
0e8ffe1b
DV		 8391 WARN(crtc->active != active,
8392 "crtc active state doesn't match with hw state "
8393 "(expected %i, found %i)\n", crtc->active, active);
8394
c0b03411
DV		 8395 if (active &&
8396 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8397 WARN(1, "pipe state doesn't match!\n");
8398 intel_dump_pipe_config(crtc, &pipe_config,
8399 "[hw state]");
8400 intel_dump_pipe_config(crtc, &crtc->config,
8401 "[sw state]");
8402 }
8af6cf88
DV		 8403 }
8404}
8405
91d1b4bd
DV		 8406static void
8407check_shared_dpll_state(struct drm_device *dev)
8408{
8409 drm_i915_private_t *dev_priv = dev->dev_private;
8410 struct intel_crtc *crtc;
8411 struct intel_dpll_hw_state dpll_hw_state;
8412 int i;
5358901f
DV		 8413
8414 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8415 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8416 int enabled_crtcs = 0, active_crtcs = 0;
8417 bool active;
8418
8419 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8420
8421 DRM_DEBUG_KMS("%s\n", pll->name);
8422
8423 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8424
8425 WARN(pll->active > pll->refcount,
8426 "more active pll users than references: %i vs %i\n",
8427 pll->active, pll->refcount);
8428 WARN(pll->active && !pll->on,
8429 "pll in active use but not on in sw tracking\n");
8430 WARN(pll->on != active,
8431 "pll on state mismatch (expected %i, found %i)\n",
8432 pll->on, active);
8433
8434 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8435 base.head) {
8436 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8437 enabled_crtcs++;
8438 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8439 active_crtcs++;
8440 }
8441 WARN(pll->active != active_crtcs,
8442 "pll active crtcs mismatch (expected %i, found %i)\n",
8443 pll->active, active_crtcs);
8444 WARN(pll->refcount != enabled_crtcs,
8445 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8446 pll->refcount, enabled_crtcs);
66e985c0
DV		 8447
8448 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8449 sizeof(dpll_hw_state)),
8450 "pll hw state mismatch\n");
5358901f 8451 }
8af6cf88
DV		 8452}
8453
91d1b4bd
DV		 8454void
8455intel_modeset_check_state(struct drm_device *dev)
8456{
8457 check_connector_state(dev);
8458 check_encoder_state(dev);
8459 check_crtc_state(dev);
8460 check_shared_dpll_state(dev);
8461}
8462
f30da187
DV		 8463static int __intel_set_mode(struct drm_crtc *crtc,
8464 struct drm_display_mode *mode,
8465 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8466{
8467 struct drm_device *dev = crtc->dev;
dbf2b54e 8468 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8469 struct drm_display_mode *saved_mode, *saved_hwmode;
8470 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8471 struct intel_crtc *intel_crtc;
8472 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8473 int ret = 0;
a6778b3c 8474
3ac18232 8475 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8476 if (!saved_mode)
8477 return -ENOMEM;
3ac18232 8478 saved_hwmode = saved_mode + 1;
a6778b3c 8479
e2e1ed41 8480 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8481 &prepare_pipes, &disable_pipes);
8482
3ac18232
TG		 8483 *saved_hwmode = crtc->hwmode;
8484 *saved_mode = crtc->mode;
a6778b3c 8485
25c5b266
DV		 8486 /* Hack: Because we don't (yet) support global modeset on multiple
8487 * crtcs, we don't keep track of the new mode for more than one crtc.
8488 * Hence simply check whether any bit is set in modeset_pipes in all the
8489 * pieces of code that are not yet converted to deal with mutliple crtcs
8490 * changing their mode at the same time. */
25c5b266 8491 if (modeset_pipes) {
4e53c2e0 8492 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8493 if (IS_ERR(pipe_config)) {
8494 ret = PTR_ERR(pipe_config);
8495 pipe_config = NULL;
8496
3ac18232 8497 goto out;
25c5b266 8498 }
c0b03411
DV		 8499 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8500 "[modeset]");
25c5b266 8501 }
a6778b3c 8502
460da916
DV		 8503 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8504 intel_crtc_disable(&intel_crtc->base);
8505
ea9d758d
DV		 8506 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8507 if (intel_crtc->base.enabled)
8508 dev_priv->display.crtc_disable(&intel_crtc->base);
8509 }
a6778b3c 8510
6c4c86f5
DV		 8511 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8512 * to set it here already despite that we pass it down the callchain.
f6e5b160 8513 */
b8cecdf5 8514 if (modeset_pipes) {
25c5b266 8515 crtc->mode = *mode;
b8cecdf5
DV		 8516 /* mode_set/enable/disable functions rely on a correct pipe
8517 * config. */
8518 to_intel_crtc(crtc)->config = *pipe_config;
8519 }
7758a113 8520
ea9d758d
DV		 8521 /* Only after disabling all output pipelines that will be changed can we
8522 * update the the output configuration. */
8523 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8524
47fab737
DV		 8525 if (dev_priv->display.modeset_global_resources)
8526 dev_priv->display.modeset_global_resources(dev);
8527
a6778b3c
DV		 8528 /* Set up the DPLL and any encoders state that needs to adjust or depend
8529 * on the DPLL.
f6e5b160 8530 */
25c5b266 8531 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8532 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8533 x, y, fb);
8534 if (ret)
8535 goto done;
a6778b3c
DV		 8536 }
8537
8538 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8539 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8540 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8541
25c5b266
DV		 8542 if (modeset_pipes) {
8543 /* Store real post-adjustment hardware mode. */
b8cecdf5 8544 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8545
25c5b266
DV		 8546 /* Calculate and store various constants which
8547 * are later needed by vblank and swap-completion
8548 * timestamping. They are derived from true hwmode.
8549 */
8550 drm_calc_timestamping_constants(crtc);
8551 }
a6778b3c
DV		 8552
8553 /* FIXME: add subpixel order */
8554done:
c0c36b94 8555 if (ret && crtc->enabled) {
3ac18232
TG		 8556 crtc->hwmode = *saved_hwmode;
8557 crtc->mode = *saved_mode;
a6778b3c
DV		 8558 }
8559
3ac18232 8560out:
b8cecdf5 8561 kfree(pipe_config);
3ac18232 8562 kfree(saved_mode);
a6778b3c 8563 return ret;
f6e5b160
CW		 8564}
8565
f30da187
DV		 8566int intel_set_mode(struct drm_crtc *crtc,
8567 struct drm_display_mode *mode,
8568 int x, int y, struct drm_framebuffer *fb)
8569{
8570 int ret;
8571
8572 ret = __intel_set_mode(crtc, mode, x, y, fb);
8573
8574 if (ret == 0)
8575 intel_modeset_check_state(crtc->dev);
8576
8577 return ret;
8578}
8579
c0c36b94
CW		 8580void intel_crtc_restore_mode(struct drm_crtc *crtc)
8581{
8582 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8583}
8584
25c5b266
DV		 8585#undef for_each_intel_crtc_masked
8586
d9e55608
DV		 8587static void intel_set_config_free(struct intel_set_config *config)
8588{
8589 if (!config)
8590 return;
8591
1aa4b628
DV		 8592 kfree(config->save_connector_encoders);
8593 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8594 kfree(config);
8595}
8596
85f9eb71
DV		 8597static int intel_set_config_save_state(struct drm_device *dev,
8598 struct intel_set_config *config)
8599{
85f9eb71
DV		 8600 struct drm_encoder *encoder;
8601 struct drm_connector *connector;
8602 int count;
8603
1aa4b628
DV		 8604 config->save_encoder_crtcs =
8605 kcalloc(dev->mode_config.num_encoder,
8606 sizeof(struct drm_crtc *), GFP_KERNEL);
8607 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8608 return -ENOMEM;
8609
1aa4b628
DV		 8610 config->save_connector_encoders =
8611 kcalloc(dev->mode_config.num_connector,
8612 sizeof(struct drm_encoder *), GFP_KERNEL);
8613 if (!config->save_connector_encoders)
85f9eb71
DV		 8614 return -ENOMEM;
8615
8616 /* Copy data. Note that driver private data is not affected.
8617 * Should anything bad happen only the expected state is
8618 * restored, not the drivers personal bookkeeping.
8619 */
85f9eb71
DV		 8620 count = 0;
8621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8622 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8623 }
8624
8625 count = 0;
8626 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8627 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8628 }
8629
8630 return 0;
8631}
8632
8633static void intel_set_config_restore_state(struct drm_device *dev,
8634 struct intel_set_config *config)
8635{
9a935856
DV		 8636 struct intel_encoder *encoder;
8637 struct intel_connector *connector;
85f9eb71
DV		 8638 int count;
8639
85f9eb71 8640 count = 0;
9a935856
DV		 8641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8642 encoder->new_crtc =
8643 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8644 }
8645
8646 count = 0;
9a935856
DV		 8647 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8648 connector->new_encoder =
8649 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8650 }
8651}
8652
e3de42b6
ID		 8653static bool
8654is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8655 int num_connectors)
8656{
8657 int i;
8658
8659 for (i = 0; i < num_connectors; i++)
8660 if (connectors[i].encoder &&
8661 connectors[i].encoder->crtc == crtc &&
8662 connectors[i].dpms != DRM_MODE_DPMS_ON)
8663 return true;
8664
8665 return false;
8666}
8667
5e2b584e
DV		 8668static void
8669intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8670 struct intel_set_config *config)
8671{
8672
8673 /* We should be able to check here if the fb has the same properties
8674 * and then just flip_or_move it */
e3de42b6
ID		 8675 if (set->connectors != NULL &&
8676 is_crtc_connector_off(set->crtc, *set->connectors,
8677 set->num_connectors)) {
8678 config->mode_changed = true;
8679 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8680 /* If we have no fb then treat it as a full mode set */
8681 if (set->crtc->fb == NULL) {
319d9827
JB		 8682 struct intel_crtc *intel_crtc =
8683 to_intel_crtc(set->crtc);
8684
8685 if (intel_crtc->active && i915_fastboot) {
8686 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8687 config->fb_changed = true;
8688 } else {
8689 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8690 config->mode_changed = true;
8691 }
5e2b584e
DV		 8692 } else if (set->fb == NULL) {
8693 config->mode_changed = true;
72f4901e
DV		 8694 } else if (set->fb->pixel_format !=
8695 set->crtc->fb->pixel_format) {
5e2b584e 8696 config->mode_changed = true;
e3de42b6 8697 } else {
5e2b584e 8698 config->fb_changed = true;
e3de42b6 8699 }
5e2b584e
DV		 8700 }
8701
835c5873 8702 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8703 config->fb_changed = true;
8704
8705 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8706 DRM_DEBUG_KMS("modes are different, full mode set\n");
8707 drm_mode_debug_printmodeline(&set->crtc->mode);
8708 drm_mode_debug_printmodeline(set->mode);
8709 config->mode_changed = true;
8710 }
8711}
8712
2e431051 8713static int
9a935856
DV		 8714intel_modeset_stage_output_state(struct drm_device *dev,
8715 struct drm_mode_set *set,
8716 struct intel_set_config *config)
50f56119 8717{
85f9eb71 8718 struct drm_crtc *new_crtc;
9a935856
DV		 8719 struct intel_connector *connector;
8720 struct intel_encoder *encoder;
2e431051 8721 int count, ro;
50f56119 8722
9abdda74 8723 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8724 * of connectors. For paranoia, double-check this. */
8725 WARN_ON(!set->fb && (set->num_connectors != 0));
8726 WARN_ON(set->fb && (set->num_connectors == 0));
8727
50f56119 8728 count = 0;
9a935856
DV		 8729 list_for_each_entry(connector, &dev->mode_config.connector_list,
8730 base.head) {
8731 /* Otherwise traverse passed in connector list and get encoders
8732 * for them. */
50f56119 8733 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8734 if (set->connectors[ro] == &connector->base) {
8735 connector->new_encoder = connector->encoder;
50f56119
DV		 8736 break;
8737 }
8738 }
8739
9a935856
DV		 8740 /* If we disable the crtc, disable all its connectors. Also, if
8741 * the connector is on the changing crtc but not on the new
8742 * connector list, disable it. */
8743 if ((!set->fb || ro == set->num_connectors) &&
8744 connector->base.encoder &&
8745 connector->base.encoder->crtc == set->crtc) {
8746 connector->new_encoder = NULL;
8747
8748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8749 connector->base.base.id,
8750 drm_get_connector_name(&connector->base));
8751 }
8752
8753
8754 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8755 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8756 config->mode_changed = true;
50f56119
DV		 8757 }
8758 }
9a935856 8759 /* connector->new_encoder is now updated for all connectors. */
50f56119 8760
9a935856 8761 /* Update crtc of enabled connectors. */
50f56119 8762 count = 0;
9a935856
DV		 8763 list_for_each_entry(connector, &dev->mode_config.connector_list,
8764 base.head) {
8765 if (!connector->new_encoder)
50f56119
DV		 8766 continue;
8767
9a935856 8768 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8769
8770 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8771 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8772 new_crtc = set->crtc;
8773 }
8774
8775 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8776 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8777 new_crtc)) {
5e2b584e 8778 return -EINVAL;
50f56119 8779 }
9a935856
DV		 8780 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8781
8782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8783 connector->base.base.id,
8784 drm_get_connector_name(&connector->base),
8785 new_crtc->base.id);
8786 }
8787
8788 /* Check for any encoders that needs to be disabled. */
8789 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8790 base.head) {
8791 list_for_each_entry(connector,
8792 &dev->mode_config.connector_list,
8793 base.head) {
8794 if (connector->new_encoder == encoder) {
8795 WARN_ON(!connector->new_encoder->new_crtc);
8796
8797 goto next_encoder;
8798 }
8799 }
8800 encoder->new_crtc = NULL;
8801next_encoder:
8802 /* Only now check for crtc changes so we don't miss encoders
8803 * that will be disabled. */
8804 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8805 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8806 config->mode_changed = true;
50f56119
DV		 8807 }
8808 }
9a935856 8809 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8810
2e431051
DV		 8811 return 0;
8812}
8813
8814static int intel_crtc_set_config(struct drm_mode_set *set)
8815{
8816 struct drm_device *dev;
2e431051
DV		 8817 struct drm_mode_set save_set;
8818 struct intel_set_config *config;
8819 int ret;
2e431051 8820
8d3e375e
DV		 8821 BUG_ON(!set);
8822 BUG_ON(!set->crtc);
8823 BUG_ON(!set->crtc->helper_private);
2e431051 8824
7e53f3a4
DV		 8825 /* Enforce sane interface api - has been abused by the fb helper. */
8826 BUG_ON(!set->mode && set->fb);
8827 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8828
2e431051
DV		 8829 if (set->fb) {
8830 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8831 set->crtc->base.id, set->fb->base.id,
8832 (int)set->num_connectors, set->x, set->y);
8833 } else {
8834 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8835 }
8836
8837 dev = set->crtc->dev;
8838
8839 ret = -ENOMEM;
8840 config = kzalloc(sizeof(*config), GFP_KERNEL);
8841 if (!config)
8842 goto out_config;
8843
8844 ret = intel_set_config_save_state(dev, config);
8845 if (ret)
8846 goto out_config;
8847
8848 save_set.crtc = set->crtc;
8849 save_set.mode = &set->crtc->mode;
8850 save_set.x = set->crtc->x;
8851 save_set.y = set->crtc->y;
8852 save_set.fb = set->crtc->fb;
8853
8854 /* Compute whether we need a full modeset, only an fb base update or no
8855 * change at all. In the future we might also check whether only the
8856 * mode changed, e.g. for LVDS where we only change the panel fitter in
8857 * such cases. */
8858 intel_set_config_compute_mode_changes(set, config);
8859
9a935856 8860 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8861 if (ret)
8862 goto fail;
8863
5e2b584e 8864 if (config->mode_changed) {
c0c36b94
CW		 8865 ret = intel_set_mode(set->crtc, set->mode,
8866 set->x, set->y, set->fb);
5e2b584e 8867 } else if (config->fb_changed) {
4878cae2
VS		 8868 intel_crtc_wait_for_pending_flips(set->crtc);
8869
4f660f49 8870 ret = intel_pipe_set_base(set->crtc,
94352cf9 8871 set->x, set->y, set->fb);
50f56119
DV		 8872 }
8873
2d05eae1 8874 if (ret) {
bf67dfeb
DV		 8875 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8876 set->crtc->base.id, ret);
50f56119 8877fail:
2d05eae1 8878 intel_set_config_restore_state(dev, config);
50f56119 8879
2d05eae1
CW		 8880 /* Try to restore the config */
8881 if (config->mode_changed &&
8882 intel_set_mode(save_set.crtc, save_set.mode,
8883 save_set.x, save_set.y, save_set.fb))
8884 DRM_ERROR("failed to restore config after modeset failure\n");
8885 }
50f56119 8886
d9e55608
DV		 8887out_config:
8888 intel_set_config_free(config);
50f56119
DV		 8889 return ret;
8890}
f6e5b160
CW		 8891
8892static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8893 .cursor_set = intel_crtc_cursor_set,
8894 .cursor_move = intel_crtc_cursor_move,
8895 .gamma_set = intel_crtc_gamma_set,
50f56119 8896 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8897 .destroy = intel_crtc_destroy,
8898 .page_flip = intel_crtc_page_flip,
8899};
8900
79f689aa
PZ		 8901static void intel_cpu_pll_init(struct drm_device *dev)
8902{
affa9354 8903 if (HAS_DDI(dev))
79f689aa
PZ		 8904 intel_ddi_pll_init(dev);
8905}
8906
5358901f
DV		 8907static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8908 struct intel_shared_dpll *pll,
8909 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8910{
5358901f 8911 uint32_t val;
ee7b9f93 8912
5358901f 8913 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8914 hw_state->dpll = val;
8915 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8916 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8917
8918 return val & DPLL_VCO_ENABLE;
8919}
8920
15bdd4cf
DV		 8921static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8922 struct intel_shared_dpll *pll)
8923{
8924 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8925 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8926}
8927
e7b903d2
DV		 8928static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8929 struct intel_shared_dpll *pll)
8930{
e7b903d2
DV		 8931 /* PCH refclock must be enabled first */
8932 assert_pch_refclk_enabled(dev_priv);
8933
15bdd4cf
DV		 8934 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8935
8936 /* Wait for the clocks to stabilize. */
8937 POSTING_READ(PCH_DPLL(pll->id));
8938 udelay(150);
8939
8940 /* The pixel multiplier can only be updated once the
8941 * DPLL is enabled and the clocks are stable.
8942 *
8943 * So write it again.
8944 */
8945 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8946 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8947 udelay(200);
8948}
8949
8950static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8951 struct intel_shared_dpll *pll)
8952{
8953 struct drm_device *dev = dev_priv->dev;
8954 struct intel_crtc *crtc;
e7b903d2
DV		 8955
8956 /* Make sure no transcoder isn't still depending on us. */
8957 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8958 if (intel_crtc_to_shared_dpll(crtc) == pll)
8959 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8960 }
8961
15bdd4cf
DV		 8962 I915_WRITE(PCH_DPLL(pll->id), 0);
8963 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8964 udelay(200);
8965}
8966
46edb027
DV		 8967static char *ibx_pch_dpll_names[] = {
8968 "PCH DPLL A",
8969 "PCH DPLL B",
8970};
8971
7c74ade1 8972static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8973{
e7b903d2 8974 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8975 int i;
8976
7c74ade1 8977 dev_priv->num_shared_dpll = 2;
ee7b9f93 8978
e72f9fbf 8979 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8980 dev_priv->shared_dplls[i].id = i;
8981 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8982 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8983 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8984 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8985 dev_priv->shared_dplls[i].get_hw_state =
8986 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8987 }
8988}
8989
7c74ade1
DV		 8990static void intel_shared_dpll_init(struct drm_device *dev)
8991{
e7b903d2 8992 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8993
8994 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8995 ibx_pch_dpll_init(dev);
8996 else
8997 dev_priv->num_shared_dpll = 0;
8998
8999 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9000 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9001 dev_priv->num_shared_dpll);
9002}
9003
b358d0a6 9004static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9005{
22fd0fab 9006 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9007 struct intel_crtc *intel_crtc;
9008 int i;
9009
9010 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9011 if (intel_crtc == NULL)
9012 return;
9013
9014 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9015
9016 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9017 for (i = 0; i < 256; i++) {
9018 intel_crtc->lut_r[i] = i;
9019 intel_crtc->lut_g[i] = i;
9020 intel_crtc->lut_b[i] = i;
9021 }
9022
80824003
JB		 9023 /* Swap pipes & planes for FBC on pre-965 */
9024 intel_crtc->pipe = pipe;
9025 intel_crtc->plane = pipe;
e2e767ab 9026 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9027 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9028 intel_crtc->plane = !pipe;
80824003
JB		 9029 }
9030
22fd0fab
JB		 9031 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9032 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9033 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9034 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9035
79e53945 9036 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9037}
9038
08d7b3d1 9039int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9040 struct drm_file *file)
08d7b3d1 9041{
08d7b3d1 9042 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9043 struct drm_mode_object *drmmode_obj;
9044 struct intel_crtc *crtc;
08d7b3d1 9045
1cff8f6b
DV		 9046 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9047 return -ENODEV;
08d7b3d1 9048
c05422d5
DV		 9049 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9050 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9051
c05422d5 9052 if (!drmmode_obj) {
08d7b3d1
CW		 9053 DRM_ERROR("no such CRTC id\n");
9054 return -EINVAL;
9055 }
9056
c05422d5
DV		 9057 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9058 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9059
c05422d5 9060 return 0;
08d7b3d1
CW		 9061}
9062
66a9278e 9063static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9064{
66a9278e
DV		 9065 struct drm_device *dev = encoder->base.dev;
9066 struct intel_encoder *source_encoder;
79e53945 9067 int index_mask = 0;
79e53945
JB		 9068 int entry = 0;
9069
66a9278e
DV		 9070 list_for_each_entry(source_encoder,
9071 &dev->mode_config.encoder_list, base.head) {
9072
9073 if (encoder == source_encoder)
79e53945 9074 index_mask |= (1 << entry);
66a9278e
DV		 9075
9076 /* Intel hw has only one MUX where enocoders could be cloned. */
9077 if (encoder->cloneable && source_encoder->cloneable)
9078 index_mask |= (1 << entry);
9079
79e53945
JB		 9080 entry++;
9081 }
4ef69c7a 9082
79e53945
JB		 9083 return index_mask;
9084}
9085
4d302442
CW		 9086static bool has_edp_a(struct drm_device *dev)
9087{
9088 struct drm_i915_private *dev_priv = dev->dev_private;
9089
9090 if (!IS_MOBILE(dev))
9091 return false;
9092
9093 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9094 return false;
9095
9096 if (IS_GEN5(dev) &&
9097 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9098 return false;
9099
9100 return true;
9101}
9102
79e53945
JB		 9103static void intel_setup_outputs(struct drm_device *dev)
9104{
725e30ad 9105 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9106 struct intel_encoder *encoder;
cb0953d7 9107 bool dpd_is_edp = false;
79e53945 9108
c9093354 9109 intel_lvds_init(dev);
79e53945 9110
c40c0f5b 9111 if (!IS_ULT(dev))
79935fca 9112 intel_crt_init(dev);
cb0953d7 9113
affa9354 9114 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9115 int found;
9116
9117 /* Haswell uses DDI functions to detect digital outputs */
9118 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9119 /* DDI A only supports eDP */
9120 if (found)
9121 intel_ddi_init(dev, PORT_A);
9122
9123 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9124 * register */
9125 found = I915_READ(SFUSE_STRAP);
9126
9127 if (found & SFUSE_STRAP_DDIB_DETECTED)
9128 intel_ddi_init(dev, PORT_B);
9129 if (found & SFUSE_STRAP_DDIC_DETECTED)
9130 intel_ddi_init(dev, PORT_C);
9131 if (found & SFUSE_STRAP_DDID_DETECTED)
9132 intel_ddi_init(dev, PORT_D);
9133 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9134 int found;
270b3042
DV		 9135 dpd_is_edp = intel_dpd_is_edp(dev);
9136
9137 if (has_edp_a(dev))
9138 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9139
dc0fa718 9140 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9141 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9142 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9143 if (!found)
e2debe91 9144 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9145 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9146 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9147 }
9148
dc0fa718 9149 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9150 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9151
dc0fa718 9152 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9153 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9154
5eb08b69 9155 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9156 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9157
270b3042 9158 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9159 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9160 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9161 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9162 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9163 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9164
dc0fa718 9165 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9166 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9167 PORT_B);
67cfc203
VS		 9168 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9169 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9170 }
103a196f 9171 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9172 bool found = false;
7d57382e 9173
e2debe91 9174 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9175 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9176 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9177 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9178 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9179 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9180 }
27185ae1 9181
e7281eab 9182 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9183 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9184 }
13520b05
KH		 9185
9186 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9187
e2debe91 9188 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9189 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9190 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9191 }
27185ae1 9192
e2debe91 9193 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9194
b01f2c3a
JB		 9195 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9196 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9197 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9198 }
e7281eab 9199 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9200 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9201 }
27185ae1 9202
b01f2c3a 9203 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9204 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9205 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9206 } else if (IS_GEN2(dev))
79e53945
JB		 9207 intel_dvo_init(dev);
9208
103a196f 9209 if (SUPPORTS_TV(dev))
79e53945
JB		 9210 intel_tv_init(dev);
9211
4ef69c7a
CW		 9212 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9213 encoder->base.possible_crtcs = encoder->crtc_mask;
9214 encoder->base.possible_clones =
66a9278e 9215 intel_encoder_clones(encoder);
79e53945 9216 }
47356eb6 9217
dde86e2d 9218 intel_init_pch_refclk(dev);
270b3042
DV		 9219
9220 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9221}
9222
9223static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9224{
9225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9226
9227 drm_framebuffer_cleanup(fb);
05394f39 9228 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9229
9230 kfree(intel_fb);
9231}
9232
9233static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9234 struct drm_file *file,
79e53945
JB		 9235 unsigned int *handle)
9236{
9237 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9238 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9239
05394f39 9240 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9241}
9242
9243static const struct drm_framebuffer_funcs intel_fb_funcs = {
9244 .destroy = intel_user_framebuffer_destroy,
9245 .create_handle = intel_user_framebuffer_create_handle,
9246};
9247
38651674
DA		 9248int intel_framebuffer_init(struct drm_device *dev,
9249 struct intel_framebuffer *intel_fb,
308e5bcb 9250 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9251 struct drm_i915_gem_object *obj)
79e53945 9252{
a35cdaa0 9253 int pitch_limit;
79e53945
JB		 9254 int ret;
9255
c16ed4be
CW		 9256 if (obj->tiling_mode == I915_TILING_Y) {
9257 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9258 return -EINVAL;
c16ed4be 9259 }
57cd6508 9260
c16ed4be
CW		 9261 if (mode_cmd->pitches[0] & 63) {
9262 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9263 mode_cmd->pitches[0]);
57cd6508 9264 return -EINVAL;
c16ed4be 9265 }
57cd6508 9266
a35cdaa0
CW		 9267 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9268 pitch_limit = 32*1024;
9269 } else if (INTEL_INFO(dev)->gen >= 4) {
9270 if (obj->tiling_mode)
9271 pitch_limit = 16*1024;
9272 else
9273 pitch_limit = 32*1024;
9274 } else if (INTEL_INFO(dev)->gen >= 3) {
9275 if (obj->tiling_mode)
9276 pitch_limit = 8*1024;
9277 else
9278 pitch_limit = 16*1024;
9279 } else
9280 /* XXX DSPC is limited to 4k tiled */
9281 pitch_limit = 8*1024;
9282
9283 if (mode_cmd->pitches[0] > pitch_limit) {
9284 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9285 obj->tiling_mode ? "tiled" : "linear",
9286 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9287 return -EINVAL;
c16ed4be 9288 }
5d7bd705
VS		 9289
9290 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9291 mode_cmd->pitches[0] != obj->stride) {
9292 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9293 mode_cmd->pitches[0], obj->stride);
5d7bd705 9294 return -EINVAL;
c16ed4be 9295 }
5d7bd705 9296
57779d06 9297 /* Reject formats not supported by any plane early. */
308e5bcb 9298 switch (mode_cmd->pixel_format) {
57779d06 9299 case DRM_FORMAT_C8:
04b3924d
VS		 9300 case DRM_FORMAT_RGB565:
9301 case DRM_FORMAT_XRGB8888:
9302 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9303 break;
9304 case DRM_FORMAT_XRGB1555:
9305 case DRM_FORMAT_ARGB1555:
c16ed4be 9306 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9307 DRM_DEBUG("unsupported pixel format: %s\n",
9308 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9309 return -EINVAL;
c16ed4be 9310 }
57779d06
VS		 9311 break;
9312 case DRM_FORMAT_XBGR8888:
9313 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9314 case DRM_FORMAT_XRGB2101010:
9315 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9316 case DRM_FORMAT_XBGR2101010:
9317 case DRM_FORMAT_ABGR2101010:
c16ed4be 9318 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9319 DRM_DEBUG("unsupported pixel format: %s\n",
9320 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9321 return -EINVAL;
c16ed4be 9322 }
b5626747 9323 break;
04b3924d
VS		 9324 case DRM_FORMAT_YUYV:
9325 case DRM_FORMAT_UYVY:
9326 case DRM_FORMAT_YVYU:
9327 case DRM_FORMAT_VYUY:
c16ed4be 9328 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9329 DRM_DEBUG("unsupported pixel format: %s\n",
9330 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9331 return -EINVAL;
c16ed4be 9332 }
57cd6508
CW		 9333 break;
9334 default:
4ee62c76
VS		 9335 DRM_DEBUG("unsupported pixel format: %s\n",
9336 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9337 return -EINVAL;
9338 }
9339
90f9a336
VS		 9340 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9341 if (mode_cmd->offsets[0] != 0)
9342 return -EINVAL;
9343
c7d73f6a
DV		 9344 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9345 intel_fb->obj = obj;
9346
79e53945
JB		 9347 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9348 if (ret) {
9349 DRM_ERROR("framebuffer init failed %d\n", ret);
9350 return ret;
9351 }
9352
79e53945
JB		 9353 return 0;
9354}
9355
79e53945
JB		 9356static struct drm_framebuffer *
9357intel_user_framebuffer_create(struct drm_device *dev,
9358 struct drm_file *filp,
308e5bcb 9359 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9360{
05394f39 9361 struct drm_i915_gem_object *obj;
79e53945 9362
308e5bcb
JB		 9363 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9364 mode_cmd->handles[0]));
c8725226 9365 if (&obj->base == NULL)
cce13ff7 9366 return ERR_PTR(-ENOENT);
79e53945 9367
d2dff872 9368 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9369}
9370
79e53945 9371static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9372 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9373 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9374};
9375
e70236a8
JB		 9376/* Set up chip specific display functions */
9377static void intel_init_display(struct drm_device *dev)
9378{
9379 struct drm_i915_private *dev_priv = dev->dev_private;
9380
ee9300bb
DV		 9381 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9382 dev_priv->display.find_dpll = g4x_find_best_dpll;
9383 else if (IS_VALLEYVIEW(dev))
9384 dev_priv->display.find_dpll = vlv_find_best_dpll;
9385 else if (IS_PINEVIEW(dev))
9386 dev_priv->display.find_dpll = pnv_find_best_dpll;
9387 else
9388 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9389
affa9354 9390 if (HAS_DDI(dev)) {
0e8ffe1b 9391 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9392 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9393 dev_priv->display.crtc_enable = haswell_crtc_enable;
9394 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9395 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9396 dev_priv->display.update_plane = ironlake_update_plane;
9397 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9398 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9399 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9400 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9401 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9402 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9403 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9404 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9405 } else if (IS_VALLEYVIEW(dev)) {
9406 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9407 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9408 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9409 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9410 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9411 dev_priv->display.off = i9xx_crtc_off;
9412 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9413 } else {
0e8ffe1b 9414 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9415 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9416 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9417 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9418 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9419 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9420 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9421 }
e70236a8 9422
e70236a8 9423 /* Returns the core display clock speed */
25eb05fc
JB		 9424 if (IS_VALLEYVIEW(dev))
9425 dev_priv->display.get_display_clock_speed =
9426 valleyview_get_display_clock_speed;
9427 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9428 dev_priv->display.get_display_clock_speed =
9429 i945_get_display_clock_speed;
9430 else if (IS_I915G(dev))
9431 dev_priv->display.get_display_clock_speed =
9432 i915_get_display_clock_speed;
f2b115e6 9433 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9434 dev_priv->display.get_display_clock_speed =
9435 i9xx_misc_get_display_clock_speed;
9436 else if (IS_I915GM(dev))
9437 dev_priv->display.get_display_clock_speed =
9438 i915gm_get_display_clock_speed;
9439 else if (IS_I865G(dev))
9440 dev_priv->display.get_display_clock_speed =
9441 i865_get_display_clock_speed;
f0f8a9ce 9442 else if (IS_I85X(dev))
e70236a8
JB		 9443 dev_priv->display.get_display_clock_speed =
9444 i855_get_display_clock_speed;
9445 else /* 852, 830 */
9446 dev_priv->display.get_display_clock_speed =
9447 i830_get_display_clock_speed;
9448
7f8a8569 9449 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9450 if (IS_GEN5(dev)) {
674cf967 9451 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9452 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9453 } else if (IS_GEN6(dev)) {
674cf967 9454 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9455 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9456 } else if (IS_IVYBRIDGE(dev)) {
9457 /* FIXME: detect B0+ stepping and use auto training */
9458 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9459 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9460 dev_priv->display.modeset_global_resources =
9461 ivb_modeset_global_resources;
c82e4d26
ED		 9462 } else if (IS_HASWELL(dev)) {
9463 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9464 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9465 dev_priv->display.modeset_global_resources =
9466 haswell_modeset_global_resources;
a0e63c22 9467 }
6067aaea 9468 } else if (IS_G4X(dev)) {
e0dac65e 9469 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9470 }
8c9f3aaf
JB		 9471
9472 /* Default just returns -ENODEV to indicate unsupported */
9473 dev_priv->display.queue_flip = intel_default_queue_flip;
9474
9475 switch (INTEL_INFO(dev)->gen) {
9476 case 2:
9477 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9478 break;
9479
9480 case 3:
9481 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9482 break;
9483
9484 case 4:
9485 case 5:
9486 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9487 break;
9488
9489 case 6:
9490 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9491 break;
7c9017e5
JB		 9492 case 7:
9493 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9494 break;
8c9f3aaf 9495 }
e70236a8
JB		 9496}
9497
b690e96c
JB		 9498/*
9499 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9500 * resume, or other times. This quirk makes sure that's the case for
9501 * affected systems.
9502 */
0206e353 9503static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9504{
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506
9507 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9508 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9509}
9510
435793df
KP		 9511/*
9512 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9513 */
9514static void quirk_ssc_force_disable(struct drm_device *dev)
9515{
9516 struct drm_i915_private *dev_priv = dev->dev_private;
9517 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9518 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9519}
9520
4dca20ef 9521/*
5a15ab5b
CE		 9522 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9523 * brightness value
4dca20ef
CE		 9524 */
9525static void quirk_invert_brightness(struct drm_device *dev)
9526{
9527 struct drm_i915_private *dev_priv = dev->dev_private;
9528 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9529 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9530}
9531
b690e96c
JB		 9532struct intel_quirk {
9533 int device;
9534 int subsystem_vendor;
9535 int subsystem_device;
9536 void (*hook)(struct drm_device *dev);
9537};
9538
5f85f176
EE		 9539/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9540struct intel_dmi_quirk {
9541 void (*hook)(struct drm_device *dev);
9542 const struct dmi_system_id (*dmi_id_list)[];
9543};
9544
9545static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9546{
9547 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9548 return 1;
9549}
9550
9551static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9552 {
9553 .dmi_id_list = &(const struct dmi_system_id[]) {
9554 {
9555 .callback = intel_dmi_reverse_brightness,
9556 .ident = "NCR Corporation",
9557 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9558 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9559 },
9560 },
9561 { } /* terminating entry */
9562 },
9563 .hook = quirk_invert_brightness,
9564 },
9565};
9566
c43b5634 9567static struct intel_quirk intel_quirks[] = {
b690e96c 9568 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9569 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9570
b690e96c
JB		 9571 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9572 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9573
b690e96c
JB		 9574 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9575 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9576
ccd0d36e 9577 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9578 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9579 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9580
9581 /* Lenovo U160 cannot use SSC on LVDS */
9582 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9583
9584 /* Sony Vaio Y cannot use SSC on LVDS */
9585 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9586
9587 /* Acer Aspire 5734Z must invert backlight brightness */
9588 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9589
9590 /* Acer/eMachines G725 */
9591 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9592
9593 /* Acer/eMachines e725 */
9594 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9595
9596 /* Acer/Packard Bell NCL20 */
9597 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9598
9599 /* Acer Aspire 4736Z */
9600 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9601};
9602
9603static void intel_init_quirks(struct drm_device *dev)
9604{
9605 struct pci_dev *d = dev->pdev;
9606 int i;
9607
9608 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9609 struct intel_quirk *q = &intel_quirks[i];
9610
9611 if (d->device == q->device &&
9612 (d->subsystem_vendor == q->subsystem_vendor ||
9613 q->subsystem_vendor == PCI_ANY_ID) &&
9614 (d->subsystem_device == q->subsystem_device ||
9615 q->subsystem_device == PCI_ANY_ID))
9616 q->hook(dev);
9617 }
5f85f176
EE		 9618 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9619 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9620 intel_dmi_quirks[i].hook(dev);
9621 }
b690e96c
JB		 9622}
9623
9cce37f4
JB		 9624/* Disable the VGA plane that we never use */
9625static void i915_disable_vga(struct drm_device *dev)
9626{
9627 struct drm_i915_private *dev_priv = dev->dev_private;
9628 u8 sr1;
766aa1c4 9629 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9630
9631 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9632 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9633 sr1 = inb(VGA_SR_DATA);
9634 outb(sr1 | 1<<5, VGA_SR_DATA);
9635 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9636 udelay(300);
9637
9638 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9639 POSTING_READ(vga_reg);
9640}
9641
f817586c
DV		 9642void intel_modeset_init_hw(struct drm_device *dev)
9643{
fa42e23c 9644 intel_init_power_well(dev);
0232e927 9645
a8f78b58
ED		 9646 intel_prepare_ddi(dev);
9647
f817586c
DV		 9648 intel_init_clock_gating(dev);
9649
79f5b2c7 9650 mutex_lock(&dev->struct_mutex);
8090c6b9 9651 intel_enable_gt_powersave(dev);
79f5b2c7 9652 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9653}
9654
7d708ee4
ID		 9655void intel_modeset_suspend_hw(struct drm_device *dev)
9656{
9657 intel_suspend_hw(dev);
9658}
9659
79e53945
JB		 9660void intel_modeset_init(struct drm_device *dev)
9661{
652c393a 9662 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9663 int i, j, ret;
79e53945
JB		 9664
9665 drm_mode_config_init(dev);
9666
9667 dev->mode_config.min_width = 0;
9668 dev->mode_config.min_height = 0;
9669
019d96cb
DA		 9670 dev->mode_config.preferred_depth = 24;
9671 dev->mode_config.prefer_shadow = 1;
9672
e6ecefaa 9673 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9674
b690e96c
JB		 9675 intel_init_quirks(dev);
9676
1fa61106
ED		 9677 intel_init_pm(dev);
9678
e3c74757
BW		 9679 if (INTEL_INFO(dev)->num_pipes == 0)
9680 return;
9681
e70236a8
JB		 9682 intel_init_display(dev);
9683
a6c45cf0
CW		 9684 if (IS_GEN2(dev)) {
9685 dev->mode_config.max_width = 2048;
9686 dev->mode_config.max_height = 2048;
9687 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9688 dev->mode_config.max_width = 4096;
9689 dev->mode_config.max_height = 4096;
79e53945 9690 } else {
a6c45cf0
CW		 9691 dev->mode_config.max_width = 8192;
9692 dev->mode_config.max_height = 8192;
79e53945 9693 }
5d4545ae 9694 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9695
28c97730 9696 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9697 INTEL_INFO(dev)->num_pipes,
9698 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9699
7eb552ae 9700 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9701 intel_crtc_init(dev, i);
7f1f3851
JB		 9702 for (j = 0; j < dev_priv->num_plane; j++) {
9703 ret = intel_plane_init(dev, i, j);
9704 if (ret)
06da8da2
VS		 9705 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9706 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9707 }
79e53945
JB		 9708 }
9709
79f689aa 9710 intel_cpu_pll_init(dev);
e72f9fbf 9711 intel_shared_dpll_init(dev);
ee7b9f93 9712
9cce37f4
JB		 9713 /* Just disable it once at startup */
9714 i915_disable_vga(dev);
79e53945 9715 intel_setup_outputs(dev);
11be49eb
CW		 9716
9717 /* Just in case the BIOS is doing something questionable. */
9718 intel_disable_fbc(dev);
2c7111db
CW		 9719}
9720
24929352
DV		 9721static void
9722intel_connector_break_all_links(struct intel_connector *connector)
9723{
9724 connector->base.dpms = DRM_MODE_DPMS_OFF;
9725 connector->base.encoder = NULL;
9726 connector->encoder->connectors_active = false;
9727 connector->encoder->base.crtc = NULL;
9728}
9729
7fad798e
DV		 9730static void intel_enable_pipe_a(struct drm_device *dev)
9731{
9732 struct intel_connector *connector;
9733 struct drm_connector *crt = NULL;
9734 struct intel_load_detect_pipe load_detect_temp;
9735
9736 /* We can't just switch on the pipe A, we need to set things up with a
9737 * proper mode and output configuration. As a gross hack, enable pipe A
9738 * by enabling the load detect pipe once. */
9739 list_for_each_entry(connector,
9740 &dev->mode_config.connector_list,
9741 base.head) {
9742 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9743 crt = &connector->base;
9744 break;
9745 }
9746 }
9747
9748 if (!crt)
9749 return;
9750
9751 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9752 intel_release_load_detect_pipe(crt, &load_detect_temp);
9753
652c393a 9754
7fad798e
DV		 9755}
9756
fa555837
DV		 9757static bool
9758intel_check_plane_mapping(struct intel_crtc *crtc)
9759{
7eb552ae
BW		 9760 struct drm_device *dev = crtc->base.dev;
9761 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9762 u32 reg, val;
9763
7eb552ae 9764 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9765 return true;
9766
9767 reg = DSPCNTR(!crtc->plane);
9768 val = I915_READ(reg);
9769
9770 if ((val & DISPLAY_PLANE_ENABLE) &&
9771 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9772 return false;
9773
9774 return true;
9775}
9776
24929352
DV		 9777static void intel_sanitize_crtc(struct intel_crtc *crtc)
9778{
9779 struct drm_device *dev = crtc->base.dev;
9780 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9781 u32 reg;
24929352 9782
24929352 9783 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9784 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9785 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9786
9787 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9788 * disable the crtc (and hence change the state) if it is wrong. Note
9789 * that gen4+ has a fixed plane -> pipe mapping. */
9790 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9791 struct intel_connector *connector;
9792 bool plane;
9793
24929352
DV		 9794 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9795 crtc->base.base.id);
9796
9797 /* Pipe has the wrong plane attached and the plane is active.
9798 * Temporarily change the plane mapping and disable everything
9799 * ... */
9800 plane = crtc->plane;
9801 crtc->plane = !plane;
9802 dev_priv->display.crtc_disable(&crtc->base);
9803 crtc->plane = plane;
9804
9805 /* ... and break all links. */
9806 list_for_each_entry(connector, &dev->mode_config.connector_list,
9807 base.head) {
9808 if (connector->encoder->base.crtc != &crtc->base)
9809 continue;
9810
9811 intel_connector_break_all_links(connector);
9812 }
9813
9814 WARN_ON(crtc->active);
9815 crtc->base.enabled = false;
9816 }
24929352 9817
7fad798e
DV		 9818 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9819 crtc->pipe == PIPE_A && !crtc->active) {
9820 /* BIOS forgot to enable pipe A, this mostly happens after
9821 * resume. Force-enable the pipe to fix this, the update_dpms
9822 * call below we restore the pipe to the right state, but leave
9823 * the required bits on. */
9824 intel_enable_pipe_a(dev);
9825 }
9826
24929352
DV		 9827 /* Adjust the state of the output pipe according to whether we
9828 * have active connectors/encoders. */
9829 intel_crtc_update_dpms(&crtc->base);
9830
9831 if (crtc->active != crtc->base.enabled) {
9832 struct intel_encoder *encoder;
9833
9834 /* This can happen either due to bugs in the get_hw_state
9835 * functions or because the pipe is force-enabled due to the
9836 * pipe A quirk. */
9837 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9838 crtc->base.base.id,
9839 crtc->base.enabled ? "enabled" : "disabled",
9840 crtc->active ? "enabled" : "disabled");
9841
9842 crtc->base.enabled = crtc->active;
9843
9844 /* Because we only establish the connector -> encoder ->
9845 * crtc links if something is active, this means the
9846 * crtc is now deactivated. Break the links. connector
9847 * -> encoder links are only establish when things are
9848 * actually up, hence no need to break them. */
9849 WARN_ON(crtc->active);
9850
9851 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9852 WARN_ON(encoder->connectors_active);
9853 encoder->base.crtc = NULL;
9854 }
9855 }
9856}
9857
9858static void intel_sanitize_encoder(struct intel_encoder *encoder)
9859{
9860 struct intel_connector *connector;
9861 struct drm_device *dev = encoder->base.dev;
9862
9863 /* We need to check both for a crtc link (meaning that the
9864 * encoder is active and trying to read from a pipe) and the
9865 * pipe itself being active. */
9866 bool has_active_crtc = encoder->base.crtc &&
9867 to_intel_crtc(encoder->base.crtc)->active;
9868
9869 if (encoder->connectors_active && !has_active_crtc) {
9870 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9871 encoder->base.base.id,
9872 drm_get_encoder_name(&encoder->base));
9873
9874 /* Connector is active, but has no active pipe. This is
9875 * fallout from our resume register restoring. Disable
9876 * the encoder manually again. */
9877 if (encoder->base.crtc) {
9878 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9879 encoder->base.base.id,
9880 drm_get_encoder_name(&encoder->base));
9881 encoder->disable(encoder);
9882 }
9883
9884 /* Inconsistent output/port/pipe state happens presumably due to
9885 * a bug in one of the get_hw_state functions. Or someplace else
9886 * in our code, like the register restore mess on resume. Clamp
9887 * things to off as a safer default. */
9888 list_for_each_entry(connector,
9889 &dev->mode_config.connector_list,
9890 base.head) {
9891 if (connector->encoder != encoder)
9892 continue;
9893
9894 intel_connector_break_all_links(connector);
9895 }
9896 }
9897 /* Enabled encoders without active connectors will be fixed in
9898 * the crtc fixup. */
9899}
9900
44cec740 9901void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9902{
9903 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9904 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9905
9906 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9907 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9908 i915_disable_vga(dev);
0fde901f
KM		 9909 }
9910}
9911
30e984df 9912static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9913{
9914 struct drm_i915_private *dev_priv = dev->dev_private;
9915 enum pipe pipe;
24929352
DV		 9916 struct intel_crtc *crtc;
9917 struct intel_encoder *encoder;
9918 struct intel_connector *connector;
5358901f 9919 int i;
24929352 9920
0e8ffe1b
DV		 9921 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9922 base.head) {
88adfff1 9923 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9924
0e8ffe1b
DV		 9925 crtc->active = dev_priv->display.get_pipe_config(crtc,
9926 &crtc->config);
24929352
DV		 9927
9928 crtc->base.enabled = crtc->active;
9929
9930 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9931 crtc->base.base.id,
9932 crtc->active ? "enabled" : "disabled");
9933 }
9934
5358901f 9935 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9936 if (HAS_DDI(dev))
6441ab5f
PZ		 9937 intel_ddi_setup_hw_pll_state(dev);
9938
5358901f
DV		 9939 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9940 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9941
9942 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9943 pll->active = 0;
9944 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9945 base.head) {
9946 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9947 pll->active++;
9948 }
9949 pll->refcount = pll->active;
9950
9951 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9952 pll->name, pll->refcount);
9953 }
9954
24929352
DV		 9955 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9956 base.head) {
9957 pipe = 0;
9958
9959 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9960 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9961 encoder->base.crtc = &crtc->base;
510d5f2f 9962 if (encoder->get_config)
045ac3b5 9963 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9964 } else {
9965 encoder->base.crtc = NULL;
9966 }
9967
9968 encoder->connectors_active = false;
9969 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9970 encoder->base.base.id,
9971 drm_get_encoder_name(&encoder->base),
9972 encoder->base.crtc ? "enabled" : "disabled",
9973 pipe);
9974 }
9975
510d5f2f
JB		 9976 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9977 base.head) {
9978 if (!crtc->active)
9979 continue;
9980 if (dev_priv->display.get_clock)
9981 dev_priv->display.get_clock(crtc,
9982 &crtc->config);
9983 }
9984
24929352
DV		 9985 list_for_each_entry(connector, &dev->mode_config.connector_list,
9986 base.head) {
9987 if (connector->get_hw_state(connector)) {
9988 connector->base.dpms = DRM_MODE_DPMS_ON;
9989 connector->encoder->connectors_active = true;
9990 connector->base.encoder = &connector->encoder->base;
9991 } else {
9992 connector->base.dpms = DRM_MODE_DPMS_OFF;
9993 connector->base.encoder = NULL;
9994 }
9995 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9996 connector->base.base.id,
9997 drm_get_connector_name(&connector->base),
9998 connector->base.encoder ? "enabled" : "disabled");
9999 }
30e984df
DV		 10000}
10001
10002/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10003 * and i915 state tracking structures. */
10004void intel_modeset_setup_hw_state(struct drm_device *dev,
10005 bool force_restore)
10006{
10007 struct drm_i915_private *dev_priv = dev->dev_private;
10008 enum pipe pipe;
10009 struct drm_plane *plane;
10010 struct intel_crtc *crtc;
10011 struct intel_encoder *encoder;
10012
10013 intel_modeset_readout_hw_state(dev);
24929352 10014
babea61d
JB		 10015 /*
10016 * Now that we have the config, copy it to each CRTC struct
10017 * Note that this could go away if we move to using crtc_config
10018 * checking everywhere.
10019 */
10020 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10021 base.head) {
10022 if (crtc->active && i915_fastboot) {
10023 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10024
10025 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10026 crtc->base.base.id);
10027 drm_mode_debug_printmodeline(&crtc->base.mode);
10028 }
10029 }
10030
24929352
DV		 10031 /* HW state is read out, now we need to sanitize this mess. */
10032 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10033 base.head) {
10034 intel_sanitize_encoder(encoder);
10035 }
10036
10037 for_each_pipe(pipe) {
10038 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10039 intel_sanitize_crtc(crtc);
c0b03411 10040 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10041 }
9a935856 10042
45e2b5f6 10043 if (force_restore) {
f30da187
DV		 10044 /*
10045 * We need to use raw interfaces for restoring state to avoid
10046 * checking (bogus) intermediate states.
10047 */
45e2b5f6 10048 for_each_pipe(pipe) {
b5644d05
JB		 10049 struct drm_crtc *crtc =
10050 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10051
10052 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10053 crtc->fb);
45e2b5f6 10054 }
b5644d05
JB		 10055 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10056 intel_plane_restore(plane);
0fde901f
KM		 10057
10058 i915_redisable_vga(dev);
45e2b5f6
DV		 10059 } else {
10060 intel_modeset_update_staged_output_state(dev);
10061 }
8af6cf88
DV		 10062
10063 intel_modeset_check_state(dev);
2e938892
DV		 10064
10065 drm_mode_config_reset(dev);
2c7111db
CW		 10066}
10067
10068void intel_modeset_gem_init(struct drm_device *dev)
10069{
1833b134 10070 intel_modeset_init_hw(dev);
02e792fb
DV		 10071
10072 intel_setup_overlay(dev);
24929352 10073
45e2b5f6 10074 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10075}
10076
10077void intel_modeset_cleanup(struct drm_device *dev)
10078{
652c393a
JB		 10079 struct drm_i915_private *dev_priv = dev->dev_private;
10080 struct drm_crtc *crtc;
10081 struct intel_crtc *intel_crtc;
10082
fd0c0642
DV		 10083 /*
10084 * Interrupts and polling as the first thing to avoid creating havoc.
10085 * Too much stuff here (turning of rps, connectors, ...) would
10086 * experience fancy races otherwise.
10087 */
10088 drm_irq_uninstall(dev);
10089 cancel_work_sync(&dev_priv->hotplug_work);
10090 /*
10091 * Due to the hpd irq storm handling the hotplug work can re-arm the
10092 * poll handlers. Hence disable polling after hpd handling is shut down.
10093 */
f87ea761 10094 drm_kms_helper_poll_fini(dev);
fd0c0642 10095
652c393a
JB		 10096 mutex_lock(&dev->struct_mutex);
10097
723bfd70
JB		 10098 intel_unregister_dsm_handler();
10099
652c393a
JB		 10100 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10101 /* Skip inactive CRTCs */
10102 if (!crtc->fb)
10103 continue;
10104
10105 intel_crtc = to_intel_crtc(crtc);
3dec0095 10106 intel_increase_pllclock(crtc);
652c393a
JB		 10107 }
10108
973d04f9 10109 intel_disable_fbc(dev);
e70236a8 10110
8090c6b9 10111 intel_disable_gt_powersave(dev);
0cdab21f 10112
930ebb46
DV		 10113 ironlake_teardown_rc6(dev);
10114
69341a5e
KH		 10115 mutex_unlock(&dev->struct_mutex);
10116
1630fe75
CW		 10117 /* flush any delayed tasks or pending work */
10118 flush_scheduled_work();
10119
dc652f90
JN		 10120 /* destroy backlight, if any, before the connectors */
10121 intel_panel_destroy_backlight(dev);
10122
79e53945 10123 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10124
10125 intel_cleanup_overlay(dev);
79e53945
JB		 10126}
10127
f1c79df3
ZW		 10128/*
10129 * Return which encoder is currently attached for connector.
10130 */
df0e9248 10131struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10132{
df0e9248
CW		 10133 return &intel_attached_encoder(connector)->base;
10134}
f1c79df3 10135
df0e9248
CW		 10136void intel_connector_attach_encoder(struct intel_connector *connector,
10137 struct intel_encoder *encoder)
10138{
10139 connector->encoder = encoder;
10140 drm_mode_connector_attach_encoder(&connector->base,
10141 &encoder->base);
79e53945 10142}
28d52043
DA		 10143
10144/*
10145 * set vga decode state - true == enable VGA decode
10146 */
10147int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10148{
10149 struct drm_i915_private *dev_priv = dev->dev_private;
10150 u16 gmch_ctrl;
10151
10152 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10153 if (state)
10154 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10155 else
10156 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10157 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10158 return 0;
10159}
c4a1d9e4
CW		 10160
10161#ifdef CONFIG_DEBUG_FS
10162#include <linux/seq_file.h>
10163
10164struct intel_display_error_state {
ff57f1b0
PZ		 10165
10166 u32 power_well_driver;
10167
c4a1d9e4
CW		 10168 struct intel_cursor_error_state {
10169 u32 control;
10170 u32 position;
10171 u32 base;
10172 u32 size;
52331309 10173 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10174
10175 struct intel_pipe_error_state {
ff57f1b0 10176 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10177 u32 conf;
10178 u32 source;
10179
10180 u32 htotal;
10181 u32 hblank;
10182 u32 hsync;
10183 u32 vtotal;
10184 u32 vblank;
10185 u32 vsync;
52331309 10186 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10187
10188 struct intel_plane_error_state {
10189 u32 control;
10190 u32 stride;
10191 u32 size;
10192 u32 pos;
10193 u32 addr;
10194 u32 surface;
10195 u32 tile_offset;
52331309 10196 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10197};
10198
10199struct intel_display_error_state *
10200intel_display_capture_error_state(struct drm_device *dev)
10201{
0206e353 10202 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10203 struct intel_display_error_state *error;
702e7a56 10204 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10205 int i;
10206
10207 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10208 if (error == NULL)
10209 return NULL;
10210
ff57f1b0
PZ		 10211 if (HAS_POWER_WELL(dev))
10212 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10213
52331309 10214 for_each_pipe(i) {
702e7a56 10215 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10216 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10217
a18c4c3d
PZ		 10218 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10219 error->cursor[i].control = I915_READ(CURCNTR(i));
10220 error->cursor[i].position = I915_READ(CURPOS(i));
10221 error->cursor[i].base = I915_READ(CURBASE(i));
10222 } else {
10223 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10224 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10225 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10226 }
c4a1d9e4
CW		 10227
10228 error->plane[i].control = I915_READ(DSPCNTR(i));
10229 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10230 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10231 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10232 error->plane[i].pos = I915_READ(DSPPOS(i));
10233 }
ca291363
PZ		 10234 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10235 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10236 if (INTEL_INFO(dev)->gen >= 4) {
10237 error->plane[i].surface = I915_READ(DSPSURF(i));
10238 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10239 }
10240
702e7a56 10241 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10242 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10243 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10244 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10245 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10246 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10247 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10248 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10249 }
10250
12d217c7
PZ		 10251 /* In the code above we read the registers without checking if the power
10252 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10253 * prevent the next I915_WRITE from detecting it and printing an error
10254 * message. */
10255 if (HAS_POWER_WELL(dev))
10256 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10257
c4a1d9e4
CW		 10258 return error;
10259}
10260
edc3d884
MK		 10261#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10262
c4a1d9e4 10263void
edc3d884 10264intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10265 struct drm_device *dev,
10266 struct intel_display_error_state *error)
10267{
10268 int i;
10269
edc3d884 10270 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10271 if (HAS_POWER_WELL(dev))
edc3d884 10272 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10273 error->power_well_driver);
52331309 10274 for_each_pipe(i) {
edc3d884
MK		 10275 err_printf(m, "Pipe [%d]:\n", i);
10276 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10277 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10278 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10279 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10280 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10281 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10282 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10283 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10284 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10285 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10286
10287 err_printf(m, "Plane [%d]:\n", i);
10288 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10289 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10290 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10291 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10292 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10293 }
4b71a570 10294 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10295 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10296 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10297 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10298 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10299 }
10300
edc3d884
MK		 10301 err_printf(m, "Cursor [%d]:\n", i);
10302 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10303 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10304 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10305 }
10306}
10307#endif
Linux kernel - Deliverables
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