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drm/i915: Rename intel_{enable, disable}_plane to intel_{enable, disable}_primary_plane
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 clock->vco = refclk * clock->m / clock->n;
333 clock->dot = clock->vco / clock->p;
334}
335
e0638cdf
PZ		 336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
1b894b59
CW		 351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
2c07245f 353{
b91ad0ec 354 struct drm_device *dev = crtc->dev;
2c07245f 355 const intel_limit_t *limit;
b91ad0ec
ZW		 356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 358 if (intel_is_dual_link_lvds(dev)) {
1b894b59 359 if (refclk == 100000)
b91ad0ec
ZW		 360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
1b894b59 364 if (refclk == 100000)
b91ad0ec
ZW		 365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
c6bb3538 369 } else
b91ad0ec 370 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 371
372 return limit;
373}
374
044c7c41
ML		 375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
044c7c41
ML		 378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 381 if (intel_is_dual_link_lvds(dev))
e4b36699 382 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 383 else
e4b36699 384 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 387 limit = &intel_limits_g4x_hdmi;
044c7c41 388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 389 limit = &intel_limits_g4x_sdvo;
044c7c41 390 } else /* The option is for other outputs */
e4b36699 391 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 392
393 return limit;
394}
395
1b894b59 396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
bad720ff 401 if (HAS_PCH_SPLIT(dev))
1b894b59 402 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 403 else if (IS_G4X(dev)) {
044c7c41 404 limit = intel_g4x_limit(crtc);
f2b115e6 405 } else if (IS_PINEVIEW(dev)) {
2177832f 406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 407 limit = &intel_limits_pineview_lvds;
2177832f 408 else
f2b115e6 409 limit = &intel_limits_pineview_sdvo;
a0c4da24 410 } else if (IS_VALLEYVIEW(dev)) {
dc730512 411 limit = &intel_limits_vlv;
a6c45cf0
CW		 412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 419 limit = &intel_limits_i8xx_lvds;
5d536e28 420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 421 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 422 else
423 limit = &intel_limits_i8xx_dac;
79e53945
JB		 424 }
425 return limit;
426}
427
f2b115e6
AJ		 428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 430{
2177832f
SL		 431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
433 clock->vco = refclk * clock->m / clock->n;
434 clock->dot = clock->vco / clock->p;
435}
436
7429e9d4
DV		 437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
ac58c3f0 442static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 443{
7429e9d4 444 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 445 clock->p = clock->p1 * clock->p2;
446 clock->vco = refclk * clock->m / (clock->n + 2);
447 clock->dot = clock->vco / clock->p;
448}
449
7c04d1d9 450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
1b894b59
CW		 456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
79e53945 459{
f01b7962
VS		 460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
79e53945 462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 463 INTELPllInvalid("p1 out of range\n");
79e53945 464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 465 INTELPllInvalid("m2 out of range\n");
79e53945 466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 467 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24 672{
f01b7962 673 struct drm_device *dev = crtc->dev;
6b4bf1c4 674 intel_clock_t clock;
69e4f900 675 unsigned int bestppm = 1000000;
27e639bf
VS		 676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 678 bool found = false;
a0c4da24 679
6b4bf1c4
VS		 680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 683
684 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 689 clock.p = clock.p1 * clock.p2;
a0c4da24 690 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 692 unsigned int ppm, diff;
693
6b4bf1c4
VS		 694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
43b0ac53 698
f01b7962
VS		 699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
43b0ac53
VS		 701 continue;
702
6b4bf1c4
VS		 703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 707 bestppm = 0;
6b4bf1c4 708 *best_clock = clock;
49e497ef 709 found = true;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
a0c4da24
JB		 716 }
717 }
718 }
719 }
720 }
a0c4da24 721
49e497ef 722 return found;
a0c4da24 723}
a4fc5ed6 724
20ddf665
VS		 725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
241bfc38 732 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
241bfc38 739 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 740}
741
a5c961d1
PZ		 742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
3b117c8f 748 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 749}
750
a928d536
PZ		 751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
9d0498a2
JB		 762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 771{
9d0498a2 772 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 773 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 774
a928d536
PZ		 775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
300387c0
CW		 780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
9d0498a2 796 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
9d0498a2
JB		 800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
ab7ad7f6
KP		 803/*
804 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 805 * @dev: drm device
806 * @pipe: pipe to wait for
807 *
808 * After disabling a pipe, we can't wait for vblank in the usual way,
809 * spinning on the vblank interrupt status bit, since we won't actually
810 * see an interrupt when the pipe is disabled.
811 *
ab7ad7f6
KP		 812 * On Gen4 and above:
813 * wait for the pipe register state bit to turn off
814 *
815 * Otherwise:
816 * wait for the display line value to settle (it usually
817 * ends up stopping at the start of the next frame).
58e10eb9 818 *
9d0498a2 819 */
58e10eb9 820void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 821{
822 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 823 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
824 pipe);
ab7ad7f6
KP		 825
826 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 827 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 828
829 /* Wait for the Pipe State to go off */
58e10eb9
CW		 830 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
831 100))
284637d9 832 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 833 } else {
837ba00f 834 u32 last_line, line_mask;
58e10eb9 835 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 836 unsigned long timeout = jiffies + msecs_to_jiffies(100);
837
837ba00f
PZ		 838 if (IS_GEN2(dev))
839 line_mask = DSL_LINEMASK_GEN2;
840 else
841 line_mask = DSL_LINEMASK_GEN3;
842
ab7ad7f6
KP		 843 /* Wait for the display line to settle */
844 do {
837ba00f 845 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 846 mdelay(5);
837ba00f 847 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 848 time_after(timeout, jiffies));
849 if (time_after(jiffies, timeout))
284637d9 850 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 851 }
79e53945
JB		 852}
853
b0ea7d37
DL		 854/*
855 * ibx_digital_port_connected - is the specified port connected?
856 * @dev_priv: i915 private structure
857 * @port: the port to test
858 *
859 * Returns true if @port is connected, false otherwise.
860 */
861bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
862 struct intel_digital_port *port)
863{
864 u32 bit;
865
c36346e3
DL		 866 if (HAS_PCH_IBX(dev_priv->dev)) {
867 switch(port->port) {
868 case PORT_B:
869 bit = SDE_PORTB_HOTPLUG;
870 break;
871 case PORT_C:
872 bit = SDE_PORTC_HOTPLUG;
873 break;
874 case PORT_D:
875 bit = SDE_PORTD_HOTPLUG;
876 break;
877 default:
878 return true;
879 }
880 } else {
881 switch(port->port) {
882 case PORT_B:
883 bit = SDE_PORTB_HOTPLUG_CPT;
884 break;
885 case PORT_C:
886 bit = SDE_PORTC_HOTPLUG_CPT;
887 break;
888 case PORT_D:
889 bit = SDE_PORTD_HOTPLUG_CPT;
890 break;
891 default:
892 return true;
893 }
b0ea7d37
DL		 894 }
895
896 return I915_READ(SDEISR) & bit;
897}
898
b24e7179
JB		 899static const char *state_string(bool enabled)
900{
901 return enabled ? "on" : "off";
902}
903
904/* Only for pre-ILK configs */
55607e8a
DV		 905void assert_pll(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
b24e7179
JB		 907{
908 int reg;
909 u32 val;
910 bool cur_state;
911
912 reg = DPLL(pipe);
913 val = I915_READ(reg);
914 cur_state = !!(val & DPLL_VCO_ENABLE);
915 WARN(cur_state != state,
916 "PLL state assertion failure (expected %s, current %s)\n",
917 state_string(state), state_string(cur_state));
918}
b24e7179 919
23538ef1
JN		 920/* XXX: the dsi pll is shared between MIPI DSI ports */
921static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
922{
923 u32 val;
924 bool cur_state;
925
926 mutex_lock(&dev_priv->dpio_lock);
927 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
928 mutex_unlock(&dev_priv->dpio_lock);
929
930 cur_state = val & DSI_PLL_VCO_EN;
931 WARN(cur_state != state,
932 "DSI PLL state assertion failure (expected %s, current %s)\n",
933 state_string(state), state_string(cur_state));
934}
935#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
936#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
937
55607e8a 938struct intel_shared_dpll *
e2b78267
DV		 939intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
940{
941 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
942
a43f6e0f 943 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 944 return NULL;
945
a43f6e0f 946 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 947}
948
040484af 949/* For ILK+ */
55607e8a
DV		 950void assert_shared_dpll(struct drm_i915_private *dev_priv,
951 struct intel_shared_dpll *pll,
952 bool state)
040484af 953{
040484af 954 bool cur_state;
5358901f 955 struct intel_dpll_hw_state hw_state;
040484af 956
9d82aa17
ED		 957 if (HAS_PCH_LPT(dev_priv->dev)) {
958 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
959 return;
960 }
961
92b27b08 962 if (WARN (!pll,
46edb027 963 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 964 return;
ee7b9f93 965
5358901f 966 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 967 WARN(cur_state != state,
5358901f
DV		 968 "%s assertion failure (expected %s, current %s)\n",
969 pll->name, state_string(state), state_string(cur_state));
040484af 970}
040484af
JB		 971
972static void assert_fdi_tx(struct drm_i915_private *dev_priv,
973 enum pipe pipe, bool state)
974{
975 int reg;
976 u32 val;
977 bool cur_state;
ad80a810
PZ		 978 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
979 pipe);
040484af 980
affa9354
PZ		 981 if (HAS_DDI(dev_priv->dev)) {
982 /* DDI does not have a specific FDI_TX register */
ad80a810 983 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 984 val = I915_READ(reg);
ad80a810 985 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 986 } else {
987 reg = FDI_TX_CTL(pipe);
988 val = I915_READ(reg);
989 cur_state = !!(val & FDI_TX_ENABLE);
990 }
040484af
JB		 991 WARN(cur_state != state,
992 "FDI TX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
994}
995#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
996#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
997
998static void assert_fdi_rx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
1004
d63fa0dc
PZ		 1005 reg = FDI_RX_CTL(pipe);
1006 val = I915_READ(reg);
1007 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1008 WARN(cur_state != state,
1009 "FDI RX state assertion failure (expected %s, current %s)\n",
1010 state_string(state), state_string(cur_state));
1011}
1012#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe)
1017{
1018 int reg;
1019 u32 val;
1020
1021 /* ILK FDI PLL is always enabled */
1022 if (dev_priv->info->gen == 5)
1023 return;
1024
bf507ef7 1025 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1026 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1027 return;
1028
040484af
JB		 1029 reg = FDI_TX_CTL(pipe);
1030 val = I915_READ(reg);
1031 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1032}
1033
55607e8a
DV		 1034void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
040484af
JB		 1036{
1037 int reg;
1038 u32 val;
55607e8a 1039 bool cur_state;
040484af
JB		 1040
1041 reg = FDI_RX_CTL(pipe);
1042 val = I915_READ(reg);
55607e8a
DV		 1043 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1044 WARN(cur_state != state,
1045 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046 state_string(state), state_string(cur_state));
040484af
JB		 1047}
1048
ea0760cf
JB		 1049static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1050 enum pipe pipe)
1051{
1052 int pp_reg, lvds_reg;
1053 u32 val;
1054 enum pipe panel_pipe = PIPE_A;
0de3b485 1055 bool locked = true;
ea0760cf
JB		 1056
1057 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058 pp_reg = PCH_PP_CONTROL;
1059 lvds_reg = PCH_LVDS;
1060 } else {
1061 pp_reg = PP_CONTROL;
1062 lvds_reg = LVDS;
1063 }
1064
1065 val = I915_READ(pp_reg);
1066 if (!(val & PANEL_POWER_ON) ||
1067 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1068 locked = false;
1069
1070 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1071 panel_pipe = PIPE_B;
1072
1073 WARN(panel_pipe == pipe && locked,
1074 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1075 pipe_name(pipe));
ea0760cf
JB		 1076}
1077
93ce0ba6
JN		 1078static void assert_cursor(struct drm_i915_private *dev_priv,
1079 enum pipe pipe, bool state)
1080{
1081 struct drm_device *dev = dev_priv->dev;
1082 bool cur_state;
1083
1084 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1085 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1086 else if (IS_845G(dev) || IS_I865G(dev))
1087 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1088 else
1089 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1090
1091 WARN(cur_state != state,
1092 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093 pipe_name(pipe), state_string(state), state_string(cur_state));
1094}
1095#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1097
b840d907
JB		 1098void assert_pipe(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, bool state)
b24e7179
JB		 1100{
1101 int reg;
1102 u32 val;
63d7bbe9 1103 bool cur_state;
702e7a56
PZ		 1104 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1105 pipe);
b24e7179 1106
8e636784
DV		 1107 /* if we need the pipe A quirk it must be always on */
1108 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1109 state = true;
1110
b97186f0
PZ		 1111 if (!intel_display_power_enabled(dev_priv->dev,
1112 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1113 cur_state = false;
1114 } else {
1115 reg = PIPECONF(cpu_transcoder);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & PIPECONF_ENABLE);
1118 }
1119
63d7bbe9
JB		 1120 WARN(cur_state != state,
1121 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1122 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1123}
1124
931872fc
CW		 1125static void assert_plane(struct drm_i915_private *dev_priv,
1126 enum plane plane, bool state)
b24e7179
JB		 1127{
1128 int reg;
1129 u32 val;
931872fc 1130 bool cur_state;
b24e7179
JB		 1131
1132 reg = DSPCNTR(plane);
1133 val = I915_READ(reg);
931872fc
CW		 1134 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1135 WARN(cur_state != state,
1136 "plane %c assertion failure (expected %s, current %s)\n",
1137 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1138}
1139
931872fc
CW		 1140#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1142
b24e7179
JB		 1143static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
653e1026 1146 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1147 int reg, i;
1148 u32 val;
1149 int cur_pipe;
1150
653e1026
VS		 1151 /* Primary planes are fixed to pipes on gen4+ */
1152 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1153 reg = DSPCNTR(pipe);
1154 val = I915_READ(reg);
1155 WARN((val & DISPLAY_PLANE_ENABLE),
1156 "plane %c assertion failure, should be disabled but not\n",
1157 plane_name(pipe));
19ec1358 1158 return;
28c05794 1159 }
19ec1358 1160
b24e7179 1161 /* Need to check both planes against the pipe */
08e2a7de 1162 for_each_pipe(i) {
b24e7179
JB		 1163 reg = DSPCNTR(i);
1164 val = I915_READ(reg);
1165 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1166 DISPPLANE_SEL_PIPE_SHIFT;
1167 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1168 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1170 }
1171}
1172
19332d7a
JB		 1173static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1174 enum pipe pipe)
1175{
20674eef 1176 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1177 int reg, i;
1178 u32 val;
1179
20674eef
VS		 1180 if (IS_VALLEYVIEW(dev)) {
1181 for (i = 0; i < dev_priv->num_plane; i++) {
1182 reg = SPCNTR(pipe, i);
1183 val = I915_READ(reg);
1184 WARN((val & SP_ENABLE),
1185 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186 sprite_name(pipe, i), pipe_name(pipe));
1187 }
1188 } else if (INTEL_INFO(dev)->gen >= 7) {
1189 reg = SPRCTL(pipe);
19332d7a 1190 val = I915_READ(reg);
20674eef 1191 WARN((val & SPRITE_ENABLE),
06da8da2 1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1193 plane_name(pipe), pipe_name(pipe));
1194 } else if (INTEL_INFO(dev)->gen >= 5) {
1195 reg = DVSCNTR(pipe);
19332d7a 1196 val = I915_READ(reg);
20674eef 1197 WARN((val & DVS_ENABLE),
06da8da2 1198 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1199 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1200 }
1201}
1202
92f2584a
JB		 1203static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1204{
1205 u32 val;
1206 bool enabled;
1207
9d82aa17
ED		 1208 if (HAS_PCH_LPT(dev_priv->dev)) {
1209 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1210 return;
1211 }
1212
92f2584a
JB		 1213 val = I915_READ(PCH_DREF_CONTROL);
1214 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1215 DREF_SUPERSPREAD_SOURCE_MASK));
1216 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1217}
1218
ab9412ba
DV		 1219static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1220 enum pipe pipe)
92f2584a
JB		 1221{
1222 int reg;
1223 u32 val;
1224 bool enabled;
1225
ab9412ba 1226 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1227 val = I915_READ(reg);
1228 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1229 WARN(enabled,
1230 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1231 pipe_name(pipe));
92f2584a
JB		 1232}
1233
4e634389
KP		 1234static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1236{
1237 if ((val & DP_PORT_EN) == 0)
1238 return false;
1239
1240 if (HAS_PCH_CPT(dev_priv->dev)) {
1241 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1242 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1243 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1244 return false;
1245 } else {
1246 if ((val & DP_PIPE_MASK) != (pipe << 30))
1247 return false;
1248 }
1249 return true;
1250}
1251
1519b995
KP		 1252static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254{
dc0fa718 1255 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1259 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1260 return false;
1261 } else {
dc0fa718 1262 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1263 return false;
1264 }
1265 return true;
1266}
1267
1268static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270{
1271 if ((val & LVDS_PORT_EN) == 0)
1272 return false;
1273
1274 if (HAS_PCH_CPT(dev_priv->dev)) {
1275 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1276 return false;
1277 } else {
1278 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1279 return false;
1280 }
1281 return true;
1282}
1283
1284static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, u32 val)
1286{
1287 if ((val & ADPA_DAC_ENABLE) == 0)
1288 return false;
1289 if (HAS_PCH_CPT(dev_priv->dev)) {
1290 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1291 return false;
1292 } else {
1293 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1294 return false;
1295 }
1296 return true;
1297}
1298
291906f1 1299static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1300 enum pipe pipe, int reg, u32 port_sel)
291906f1 1301{
47a05eca 1302 u32 val = I915_READ(reg);
4e634389 1303 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1304 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1305 reg, pipe_name(pipe));
de9a35ab 1306
75c5da27
DV		 1307 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1308 && (val & DP_PIPEB_SELECT),
de9a35ab 1309 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1310}
1311
1312static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, int reg)
1314{
47a05eca 1315 u32 val = I915_READ(reg);
b70ad586 1316 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1317 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1318 reg, pipe_name(pipe));
de9a35ab 1319
dc0fa718 1320 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1321 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1322 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1323}
1324
1325static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1326 enum pipe pipe)
1327{
1328 int reg;
1329 u32 val;
291906f1 1330
f0575e92
KP		 1331 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1332 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1333 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1334
1335 reg = PCH_ADPA;
1336 val = I915_READ(reg);
b70ad586 1337 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1338 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1339 pipe_name(pipe));
291906f1
JB		 1340
1341 reg = PCH_LVDS;
1342 val = I915_READ(reg);
b70ad586 1343 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1344 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1345 pipe_name(pipe));
291906f1 1346
e2debe91
PZ		 1347 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1348 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1349 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1350}
1351
40e9cf64
JB		 1352static void intel_init_dpio(struct drm_device *dev)
1353{
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355
1356 if (!IS_VALLEYVIEW(dev))
1357 return;
1358
1359 /*
1360 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1362 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363 * b. The other bits such as sfr settings / modesel may all be set
1364 * to 0.
1365 *
1366 * This should only be done on init and resume from S3 with both
1367 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1368 */
1369 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1370}
1371
426115cf 1372static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1373{
426115cf
DV		 1374 struct drm_device *dev = crtc->base.dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int reg = DPLL(crtc->pipe);
1377 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1378
426115cf 1379 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1380
1381 /* No really, not for ILK+ */
1382 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1383
1384 /* PLL is protected by panel, make sure we can write it */
1385 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1386 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1387
426115cf
DV		 1388 I915_WRITE(reg, dpll);
1389 POSTING_READ(reg);
1390 udelay(150);
1391
1392 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1393 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1394
1395 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1396 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1397
1398 /* We do this three times for luck */
426115cf 1399 I915_WRITE(reg, dpll);
87442f73
DV		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
426115cf 1402 I915_WRITE(reg, dpll);
87442f73
DV		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
426115cf 1405 I915_WRITE(reg, dpll);
87442f73
DV		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
66e3d5c0 1410static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1411{
66e3d5c0
DV		 1412 struct drm_device *dev = crtc->base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 int reg = DPLL(crtc->pipe);
1415 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1416
66e3d5c0 1417 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1418
63d7bbe9 1419 /* No really, not for ILK+ */
87442f73 1420 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1421
1422 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1423 if (IS_MOBILE(dev) && !IS_I830(dev))
1424 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1425
66e3d5c0
DV		 1426 I915_WRITE(reg, dpll);
1427
1428 /* Wait for the clocks to stabilize. */
1429 POSTING_READ(reg);
1430 udelay(150);
1431
1432 if (INTEL_INFO(dev)->gen >= 4) {
1433 I915_WRITE(DPLL_MD(crtc->pipe),
1434 crtc->config.dpll_hw_state.dpll_md);
1435 } else {
1436 /* The pixel multiplier can only be updated once the
1437 * DPLL is enabled and the clocks are stable.
1438 *
1439 * So write it again.
1440 */
1441 I915_WRITE(reg, dpll);
1442 }
63d7bbe9
JB		 1443
1444 /* We do this three times for luck */
66e3d5c0 1445 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1446 POSTING_READ(reg);
1447 udelay(150); /* wait for warmup */
66e3d5c0 1448 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1449 POSTING_READ(reg);
1450 udelay(150); /* wait for warmup */
66e3d5c0 1451 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454}
1455
1456/**
50b44a44 1457 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1458 * @dev_priv: i915 private structure
1459 * @pipe: pipe PLL to disable
1460 *
1461 * Disable the PLL for @pipe, making sure the pipe is off first.
1462 *
1463 * Note! This is for pre-ILK only.
1464 */
50b44a44 1465static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1466{
63d7bbe9
JB		 1467 /* Don't disable pipe A or pipe A PLLs if needed */
1468 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1469 return;
1470
1471 /* Make sure the pipe isn't still relying on us */
1472 assert_pipe_disabled(dev_priv, pipe);
1473
50b44a44
DV		 1474 I915_WRITE(DPLL(pipe), 0);
1475 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1476}
1477
f6071166
JB		 1478static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479{
1480 u32 val = 0;
1481
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv, pipe);
1484
1485 /* Leave integrated clock source enabled */
1486 if (pipe == PIPE_B)
1487 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1488 I915_WRITE(DPLL(pipe), val);
1489 POSTING_READ(DPLL(pipe));
1490}
1491
89b667f8
JB		 1492void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1493{
1494 u32 port_mask;
1495
1496 if (!port)
1497 port_mask = DPLL_PORTB_READY_MASK;
1498 else
1499 port_mask = DPLL_PORTC_READY_MASK;
1500
1501 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1502 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503 'B' + port, I915_READ(DPLL(0)));
1504}
1505
92f2584a 1506/**
e72f9fbf 1507 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1508 * @dev_priv: i915 private structure
1509 * @pipe: pipe PLL to enable
1510 *
1511 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512 * drives the transcoder clock.
1513 */
e2b78267 1514static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1515{
e2b78267
DV		 1516 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1517 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1518
48da64a8 1519 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1520 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1521 if (WARN_ON(pll == NULL))
48da64a8
CW		 1522 return;
1523
1524 if (WARN_ON(pll->refcount == 0))
1525 return;
ee7b9f93 1526
46edb027
DV		 1527 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528 pll->name, pll->active, pll->on,
e2b78267 1529 crtc->base.base.id);
92f2584a 1530
cdbd2316
DV		 1531 if (pll->active++) {
1532 WARN_ON(!pll->on);
e9d6944e 1533 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1534 return;
1535 }
f4a091c7 1536 WARN_ON(pll->on);
ee7b9f93 1537
46edb027 1538 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1539 pll->enable(dev_priv, pll);
ee7b9f93 1540 pll->on = true;
92f2584a
JB		 1541}
1542
e2b78267 1543static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1544{
e2b78267
DV		 1545 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1547
92f2584a
JB		 1548 /* PCH only available on ILK+ */
1549 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1550 if (WARN_ON(pll == NULL))
ee7b9f93 1551 return;
92f2584a 1552
48da64a8
CW		 1553 if (WARN_ON(pll->refcount == 0))
1554 return;
7a419866 1555
46edb027
DV		 1556 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557 pll->name, pll->active, pll->on,
e2b78267 1558 crtc->base.base.id);
7a419866 1559
48da64a8 1560 if (WARN_ON(pll->active == 0)) {
e9d6944e 1561 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1562 return;
1563 }
1564
e9d6944e 1565 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1566 WARN_ON(!pll->on);
cdbd2316 1567 if (--pll->active)
7a419866 1568 return;
ee7b9f93 1569
46edb027 1570 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1571 pll->disable(dev_priv, pll);
ee7b9f93 1572 pll->on = false;
92f2584a
JB		 1573}
1574
b8a4f404
PZ		 1575static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1576 enum pipe pipe)
040484af 1577{
23670b32 1578 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1579 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1581 uint32_t reg, val, pipeconf_val;
040484af
JB		 1582
1583 /* PCH only available on ILK+ */
1584 BUG_ON(dev_priv->info->gen < 5);
1585
1586 /* Make sure PCH DPLL is enabled */
e72f9fbf 1587 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1588 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1589
1590 /* FDI must be feeding us bits for PCH ports */
1591 assert_fdi_tx_enabled(dev_priv, pipe);
1592 assert_fdi_rx_enabled(dev_priv, pipe);
1593
23670b32
DV		 1594 if (HAS_PCH_CPT(dev)) {
1595 /* Workaround: Set the timing override bit before enabling the
1596 * pch transcoder. */
1597 reg = TRANS_CHICKEN2(pipe);
1598 val = I915_READ(reg);
1599 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600 I915_WRITE(reg, val);
59c859d6 1601 }
23670b32 1602
ab9412ba 1603 reg = PCH_TRANSCONF(pipe);
040484af 1604 val = I915_READ(reg);
5f7f726d 1605 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1606
1607 if (HAS_PCH_IBX(dev_priv->dev)) {
1608 /*
1609 * make the BPC in transcoder be consistent with
1610 * that in pipeconf reg.
1611 */
dfd07d72
DV		 1612 val &= ~PIPECONF_BPC_MASK;
1613 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1614 }
5f7f726d
PZ		 1615
1616 val &= ~TRANS_INTERLACE_MASK;
1617 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1618 if (HAS_PCH_IBX(dev_priv->dev) &&
1619 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1620 val |= TRANS_LEGACY_INTERLACED_ILK;
1621 else
1622 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1623 else
1624 val |= TRANS_PROGRESSIVE;
1625
040484af
JB		 1626 I915_WRITE(reg, val | TRANS_ENABLE);
1627 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1628 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1629}
1630
8fb033d7 1631static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1632 enum transcoder cpu_transcoder)
040484af 1633{
8fb033d7 1634 u32 val, pipeconf_val;
8fb033d7
PZ		 1635
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1638
8fb033d7 1639 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1640 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1641 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1642
223a6fdf
PZ		 1643 /* Workaround: set timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1647
25f3ef11 1648 val = TRANS_ENABLE;
937bb610 1649 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1650
9a76b1c6
PZ		 1651 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1652 PIPECONF_INTERLACED_ILK)
a35f2679 1653 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1654 else
1655 val |= TRANS_PROGRESSIVE;
1656
ab9412ba
DV		 1657 I915_WRITE(LPT_TRANSCONF, val);
1658 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1659 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32
DV		 1665 struct drm_device *dev = dev_priv->dev;
1666 uint32_t reg, val;
040484af
JB		 1667
1668 /* FDI relies on the transcoder */
1669 assert_fdi_tx_disabled(dev_priv, pipe);
1670 assert_fdi_rx_disabled(dev_priv, pipe);
1671
291906f1
JB		 1672 /* Ports must be off as well */
1673 assert_pch_ports_disabled(dev_priv, pipe);
1674
ab9412ba 1675 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1676 val = I915_READ(reg);
1677 val &= ~TRANS_ENABLE;
1678 I915_WRITE(reg, val);
1679 /* wait for PCH transcoder off, transcoder state */
1680 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1681 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1682
1683 if (!HAS_PCH_IBX(dev)) {
1684 /* Workaround: Clear the timing override chicken bit again. */
1685 reg = TRANS_CHICKEN2(pipe);
1686 val = I915_READ(reg);
1687 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1688 I915_WRITE(reg, val);
1689 }
040484af
JB		 1690}
1691
ab4d966c 1692static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1693{
8fb033d7
PZ		 1694 u32 val;
1695
ab9412ba 1696 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1697 val &= ~TRANS_ENABLE;
ab9412ba 1698 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1699 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1700 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1701 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1702
1703 /* Workaround: clear timing override bit. */
1704 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1705 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1706 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1707}
1708
b24e7179 1709/**
309cfea8 1710 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to enable
040484af 1713 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1714 *
1715 * Enable @pipe, making sure that various hardware specific requirements
1716 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1717 *
1718 * @pipe should be %PIPE_A or %PIPE_B.
1719 *
1720 * Will wait until the pipe is actually running (i.e. first vblank) before
1721 * returning.
1722 */
040484af 1723static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1724 bool pch_port, bool dsi)
b24e7179 1725{
702e7a56
PZ		 1726 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 pipe);
1a240d4d 1728 enum pipe pch_transcoder;
b24e7179
JB		 1729 int reg;
1730 u32 val;
1731
58c6eaa2 1732 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1733 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1734 assert_sprites_disabled(dev_priv, pipe);
1735
681e5811 1736 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1737 pch_transcoder = TRANSCODER_A;
1738 else
1739 pch_transcoder = pipe;
1740
b24e7179
JB		 1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1747 if (dsi)
1748 assert_dsi_pll_enabled(dev_priv);
1749 else
1750 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1751 else {
1752 if (pch_port) {
1753 /* if driving the PCH, we need FDI enabled */
cc391bbb 1754 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1755 assert_fdi_tx_pll_enabled(dev_priv,
1756 (enum pipe) cpu_transcoder);
040484af
JB		 1757 }
1758 /* FIXME: assert CPU port conditions for SNB+ */
1759 }
b24e7179 1760
702e7a56 1761 reg = PIPECONF(cpu_transcoder);
b24e7179 1762 val = I915_READ(reg);
00d70b15
CW		 1763 if (val & PIPECONF_ENABLE)
1764 return;
1765
1766 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1767 intel_wait_for_vblank(dev_priv->dev, pipe);
1768}
1769
1770/**
309cfea8 1771 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1772 * @dev_priv: i915 private structure
1773 * @pipe: pipe to disable
1774 *
1775 * Disable @pipe, making sure that various hardware specific requirements
1776 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1777 *
1778 * @pipe should be %PIPE_A or %PIPE_B.
1779 *
1780 * Will wait until the pipe has shut down before returning.
1781 */
1782static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783 enum pipe pipe)
1784{
702e7a56
PZ		 1785 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1786 pipe);
b24e7179
JB		 1787 int reg;
1788 u32 val;
1789
1790 /*
1791 * Make sure planes won't keep trying to pump pixels to us,
1792 * or we might hang the display.
1793 */
1794 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1795 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
1dba99f4
VS		 1815void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1816 enum plane plane)
d74362c9 1817{
1dba99f4
VS		 1818 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1819
1820 I915_WRITE(reg, I915_READ(reg));
1821 POSTING_READ(reg);
d74362c9
KP		 1822}
1823
b24e7179 1824/**
d1de00ef 1825 * intel_enable_primary_plane - enable the primary plane on a given pipe
b24e7179
JB		 1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
d1de00ef
VS		 1832static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
b24e7179 1834{
939c2fe8
VS		 1835 struct intel_crtc *intel_crtc =
1836 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1837 int reg;
1838 u32 val;
1839
1840 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841 assert_pipe_enabled(dev_priv, pipe);
1842
939c2fe8
VS		 1843 intel_crtc->primary_disabled = false;
1844
b24e7179
JB		 1845 reg = DSPCNTR(plane);
1846 val = I915_READ(reg);
00d70b15
CW		 1847 if (val & DISPLAY_PLANE_ENABLE)
1848 return;
1849
1850 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1dba99f4 1851 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1852 intel_wait_for_vblank(dev_priv->dev, pipe);
1853}
1854
b24e7179 1855/**
d1de00ef 1856 * intel_disable_primary_plane - disable the primary plane
b24e7179
JB		 1857 * @dev_priv: i915 private structure
1858 * @plane: plane to disable
1859 * @pipe: pipe consuming the data
1860 *
1861 * Disable @plane; should be an independent operation.
1862 */
d1de00ef
VS		 1863static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1864 enum plane plane, enum pipe pipe)
b24e7179 1865{
939c2fe8
VS		 1866 struct intel_crtc *intel_crtc =
1867 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1868 int reg;
1869 u32 val;
1870
939c2fe8
VS		 1871 intel_crtc->primary_disabled = true;
1872
b24e7179
JB		 1873 reg = DSPCNTR(plane);
1874 val = I915_READ(reg);
00d70b15
CW		 1875 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1876 return;
1877
1878 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1879 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1880 intel_wait_for_vblank(dev_priv->dev, pipe);
1881}
1882
693db184
CW		 1883static bool need_vtd_wa(struct drm_device *dev)
1884{
1885#ifdef CONFIG_INTEL_IOMMU
1886 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1887 return true;
1888#endif
1889 return false;
1890}
1891
127bd2ac 1892int
48b956c5 1893intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1894 struct drm_i915_gem_object *obj,
919926ae 1895 struct intel_ring_buffer *pipelined)
6b95a207 1896{
ce453d81 1897 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1898 u32 alignment;
1899 int ret;
1900
05394f39 1901 switch (obj->tiling_mode) {
6b95a207 1902 case I915_TILING_NONE:
534843da
CW		 1903 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1904 alignment = 128 * 1024;
a6c45cf0 1905 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1906 alignment = 4 * 1024;
1907 else
1908 alignment = 64 * 1024;
6b95a207
KH		 1909 break;
1910 case I915_TILING_X:
1911 /* pin() will align the object as required by fence */
1912 alignment = 0;
1913 break;
1914 case I915_TILING_Y:
8bb6e959
DV		 1915 /* Despite that we check this in framebuffer_init userspace can
1916 * screw us over and change the tiling after the fact. Only
1917 * pinned buffers can't change their tiling. */
1918 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1919 return -EINVAL;
1920 default:
1921 BUG();
1922 }
1923
693db184
CW		 1924 /* Note that the w/a also requires 64 PTE of padding following the
1925 * bo. We currently fill all unused PTE with the shadow page and so
1926 * we should always have valid PTE following the scanout preventing
1927 * the VT-d warning.
1928 */
1929 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1930 alignment = 256 * 1024;
1931
ce453d81 1932 dev_priv->mm.interruptible = false;
2da3b9b9 1933 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1934 if (ret)
ce453d81 1935 goto err_interruptible;
6b95a207
KH		 1936
1937 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1938 * fence, whereas 965+ only requires a fence if using
1939 * framebuffer compression. For simplicity, we always install
1940 * a fence as the cost is not that onerous.
1941 */
06d98131 1942 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1943 if (ret)
1944 goto err_unpin;
1690e1eb 1945
9a5a53b3 1946 i915_gem_object_pin_fence(obj);
6b95a207 1947
ce453d81 1948 dev_priv->mm.interruptible = true;
6b95a207 1949 return 0;
48b956c5
CW		 1950
1951err_unpin:
cc98b413 1952 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1953err_interruptible:
1954 dev_priv->mm.interruptible = true;
48b956c5 1955 return ret;
6b95a207
KH		 1956}
1957
1690e1eb
CW		 1958void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1959{
1960 i915_gem_object_unpin_fence(obj);
cc98b413 1961 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1962}
1963
c2c75131
DV		 1964/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1965 * is assumed to be a power-of-two. */
bc752862
CW		 1966unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1967 unsigned int tiling_mode,
1968 unsigned int cpp,
1969 unsigned int pitch)
c2c75131 1970{
bc752862
CW		 1971 if (tiling_mode != I915_TILING_NONE) {
1972 unsigned int tile_rows, tiles;
c2c75131 1973
bc752862
CW		 1974 tile_rows = *y / 8;
1975 *y %= 8;
c2c75131 1976
bc752862
CW		 1977 tiles = *x / (512/cpp);
1978 *x %= 512/cpp;
1979
1980 return tile_rows * pitch * 8 + tiles * 4096;
1981 } else {
1982 unsigned int offset;
1983
1984 offset = *y * pitch + *x * cpp;
1985 *y = 0;
1986 *x = (offset & 4095) / cpp;
1987 return offset & -4096;
1988 }
c2c75131
DV		 1989}
1990
17638cd6
JB		 1991static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1992 int x, int y)
81255565
JB		 1993{
1994 struct drm_device *dev = crtc->dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1997 struct intel_framebuffer *intel_fb;
05394f39 1998 struct drm_i915_gem_object *obj;
81255565 1999 int plane = intel_crtc->plane;
e506a0c6 2000 unsigned long linear_offset;
81255565 2001 u32 dspcntr;
5eddb70b 2002 u32 reg;
81255565
JB		 2003
2004 switch (plane) {
2005 case 0:
2006 case 1:
2007 break;
2008 default:
84f44ce7 2009 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2010 return -EINVAL;
2011 }
2012
2013 intel_fb = to_intel_framebuffer(fb);
2014 obj = intel_fb->obj;
81255565 2015
5eddb70b
CW		 2016 reg = DSPCNTR(plane);
2017 dspcntr = I915_READ(reg);
81255565
JB		 2018 /* Mask out pixel format bits in case we change it */
2019 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2020 switch (fb->pixel_format) {
2021 case DRM_FORMAT_C8:
81255565
JB		 2022 dspcntr |= DISPPLANE_8BPP;
2023 break;
57779d06
VS		 2024 case DRM_FORMAT_XRGB1555:
2025 case DRM_FORMAT_ARGB1555:
2026 dspcntr |= DISPPLANE_BGRX555;
81255565 2027 break;
57779d06
VS		 2028 case DRM_FORMAT_RGB565:
2029 dspcntr |= DISPPLANE_BGRX565;
2030 break;
2031 case DRM_FORMAT_XRGB8888:
2032 case DRM_FORMAT_ARGB8888:
2033 dspcntr |= DISPPLANE_BGRX888;
2034 break;
2035 case DRM_FORMAT_XBGR8888:
2036 case DRM_FORMAT_ABGR8888:
2037 dspcntr |= DISPPLANE_RGBX888;
2038 break;
2039 case DRM_FORMAT_XRGB2101010:
2040 case DRM_FORMAT_ARGB2101010:
2041 dspcntr |= DISPPLANE_BGRX101010;
2042 break;
2043 case DRM_FORMAT_XBGR2101010:
2044 case DRM_FORMAT_ABGR2101010:
2045 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2046 break;
2047 default:
baba133a 2048 BUG();
81255565 2049 }
57779d06 2050
a6c45cf0 2051 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2052 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2053 dspcntr |= DISPPLANE_TILED;
2054 else
2055 dspcntr &= ~DISPPLANE_TILED;
2056 }
2057
de1aa629
VS		 2058 if (IS_G4X(dev))
2059 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2060
5eddb70b 2061 I915_WRITE(reg, dspcntr);
81255565 2062
e506a0c6 2063 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2064
c2c75131
DV		 2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 intel_crtc->dspaddr_offset =
bc752862
CW		 2067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2069 fb->pitches[0]);
c2c75131
DV		 2070 linear_offset -= intel_crtc->dspaddr_offset;
2071 } else {
e506a0c6 2072 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2073 }
e506a0c6 2074
f343c5f6
BW		 2075 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2076 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2077 fb->pitches[0]);
01f2c773 2078 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2080 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2081 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2082 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2083 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2084 } else
f343c5f6 2085 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2086 POSTING_READ(reg);
81255565 2087
17638cd6
JB		 2088 return 0;
2089}
2090
2091static int ironlake_update_plane(struct drm_crtc *crtc,
2092 struct drm_framebuffer *fb, int x, int y)
2093{
2094 struct drm_device *dev = crtc->dev;
2095 struct drm_i915_private *dev_priv = dev->dev_private;
2096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2097 struct intel_framebuffer *intel_fb;
2098 struct drm_i915_gem_object *obj;
2099 int plane = intel_crtc->plane;
e506a0c6 2100 unsigned long linear_offset;
17638cd6
JB		 2101 u32 dspcntr;
2102 u32 reg;
2103
2104 switch (plane) {
2105 case 0:
2106 case 1:
27f8227b 2107 case 2:
17638cd6
JB		 2108 break;
2109 default:
84f44ce7 2110 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2111 return -EINVAL;
2112 }
2113
2114 intel_fb = to_intel_framebuffer(fb);
2115 obj = intel_fb->obj;
2116
2117 reg = DSPCNTR(plane);
2118 dspcntr = I915_READ(reg);
2119 /* Mask out pixel format bits in case we change it */
2120 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2121 switch (fb->pixel_format) {
2122 case DRM_FORMAT_C8:
17638cd6
JB		 2123 dspcntr |= DISPPLANE_8BPP;
2124 break;
57779d06
VS		 2125 case DRM_FORMAT_RGB565:
2126 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2127 break;
57779d06
VS		 2128 case DRM_FORMAT_XRGB8888:
2129 case DRM_FORMAT_ARGB8888:
2130 dspcntr |= DISPPLANE_BGRX888;
2131 break;
2132 case DRM_FORMAT_XBGR8888:
2133 case DRM_FORMAT_ABGR8888:
2134 dspcntr |= DISPPLANE_RGBX888;
2135 break;
2136 case DRM_FORMAT_XRGB2101010:
2137 case DRM_FORMAT_ARGB2101010:
2138 dspcntr |= DISPPLANE_BGRX101010;
2139 break;
2140 case DRM_FORMAT_XBGR2101010:
2141 case DRM_FORMAT_ABGR2101010:
2142 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2143 break;
2144 default:
baba133a 2145 BUG();
17638cd6
JB		 2146 }
2147
2148 if (obj->tiling_mode != I915_TILING_NONE)
2149 dspcntr |= DISPPLANE_TILED;
2150 else
2151 dspcntr &= ~DISPPLANE_TILED;
2152
1f5d76db
PZ		 2153 if (IS_HASWELL(dev))
2154 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2155 else
2156 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2157
2158 I915_WRITE(reg, dspcntr);
2159
e506a0c6 2160 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2161 intel_crtc->dspaddr_offset =
bc752862
CW		 2162 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2163 fb->bits_per_pixel / 8,
2164 fb->pitches[0]);
c2c75131 2165 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2166
f343c5f6
BW		 2167 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2168 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2169 fb->pitches[0]);
01f2c773 2170 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2171 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2172 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2173 if (IS_HASWELL(dev)) {
2174 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2175 } else {
2176 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2177 I915_WRITE(DSPLINOFF(plane), linear_offset);
2178 }
17638cd6
JB		 2179 POSTING_READ(reg);
2180
2181 return 0;
2182}
2183
2184/* Assume fb object is pinned & idle & fenced and just update base pointers */
2185static int
2186intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2187 int x, int y, enum mode_set_atomic state)
2188{
2189 struct drm_device *dev = crtc->dev;
2190 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2191
6b8e6ed0
CW		 2192 if (dev_priv->display.disable_fbc)
2193 dev_priv->display.disable_fbc(dev);
3dec0095 2194 intel_increase_pllclock(crtc);
81255565 2195
6b8e6ed0 2196 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2197}
2198
96a02917
VS		 2199void intel_display_handle_reset(struct drm_device *dev)
2200{
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202 struct drm_crtc *crtc;
2203
2204 /*
2205 * Flips in the rings have been nuked by the reset,
2206 * so complete all pending flips so that user space
2207 * will get its events and not get stuck.
2208 *
2209 * Also update the base address of all primary
2210 * planes to the the last fb to make sure we're
2211 * showing the correct fb after a reset.
2212 *
2213 * Need to make two loops over the crtcs so that we
2214 * don't try to grab a crtc mutex before the
2215 * pending_flip_queue really got woken up.
2216 */
2217
2218 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2220 enum plane plane = intel_crtc->plane;
2221
2222 intel_prepare_page_flip(dev, plane);
2223 intel_finish_page_flip_plane(dev, plane);
2224 }
2225
2226 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228
2229 mutex_lock(&crtc->mutex);
2230 if (intel_crtc->active)
2231 dev_priv->display.update_plane(crtc, crtc->fb,
2232 crtc->x, crtc->y);
2233 mutex_unlock(&crtc->mutex);
2234 }
2235}
2236
14667a4b
CW		 2237static int
2238intel_finish_fb(struct drm_framebuffer *old_fb)
2239{
2240 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2241 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2242 bool was_interruptible = dev_priv->mm.interruptible;
2243 int ret;
2244
14667a4b
CW		 2245 /* Big Hammer, we also need to ensure that any pending
2246 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247 * current scanout is retired before unpinning the old
2248 * framebuffer.
2249 *
2250 * This should only fail upon a hung GPU, in which case we
2251 * can safely continue.
2252 */
2253 dev_priv->mm.interruptible = false;
2254 ret = i915_gem_object_finish_gpu(obj);
2255 dev_priv->mm.interruptible = was_interruptible;
2256
2257 return ret;
2258}
2259
198598d0
VS		 2260static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2261{
2262 struct drm_device *dev = crtc->dev;
2263 struct drm_i915_master_private *master_priv;
2264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265
2266 if (!dev->primary->master)
2267 return;
2268
2269 master_priv = dev->primary->master->driver_priv;
2270 if (!master_priv->sarea_priv)
2271 return;
2272
2273 switch (intel_crtc->pipe) {
2274 case 0:
2275 master_priv->sarea_priv->pipeA_x = x;
2276 master_priv->sarea_priv->pipeA_y = y;
2277 break;
2278 case 1:
2279 master_priv->sarea_priv->pipeB_x = x;
2280 master_priv->sarea_priv->pipeB_y = y;
2281 break;
2282 default:
2283 break;
2284 }
2285}
2286
5c3b82e2 2287static int
3c4fdcfb 2288intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2289 struct drm_framebuffer *fb)
79e53945
JB		 2290{
2291 struct drm_device *dev = crtc->dev;
6b8e6ed0 2292 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2294 struct drm_framebuffer *old_fb;
5c3b82e2 2295 int ret;
79e53945
JB		 2296
2297 /* no fb bound */
94352cf9 2298 if (!fb) {
a5071c2f 2299 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2300 return 0;
2301 }
2302
7eb552ae 2303 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2304 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2305 plane_name(intel_crtc->plane),
2306 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2307 return -EINVAL;
79e53945
JB		 2308 }
2309
5c3b82e2 2310 mutex_lock(&dev->struct_mutex);
265db958 2311 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2312 to_intel_framebuffer(fb)->obj,
919926ae 2313 NULL);
5c3b82e2
CW		 2314 if (ret != 0) {
2315 mutex_unlock(&dev->struct_mutex);
a5071c2f 2316 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2317 return ret;
2318 }
79e53945 2319
bb2043de
DL		 2320 /*
2321 * Update pipe size and adjust fitter if needed: the reason for this is
2322 * that in compute_mode_changes we check the native mode (not the pfit
2323 * mode) to see if we can flip rather than do a full mode set. In the
2324 * fastboot case, we'll flip, but if we don't update the pipesrc and
2325 * pfit state, we'll end up with a big fb scanned out into the wrong
2326 * sized surface.
2327 *
2328 * To fix this properly, we need to hoist the checks up into
2329 * compute_mode_changes (or above), check the actual pfit state and
2330 * whether the platform allows pfit disable with pipe active, and only
2331 * then update the pipesrc and pfit state, even on the flip path.
2332 */
4d6a3e63 2333 if (i915_fastboot) {
d7bf63f2
DL		 2334 const struct drm_display_mode *adjusted_mode =
2335 &intel_crtc->config.adjusted_mode;
2336
4d6a3e63 2337 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2338 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2339 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2340 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2341 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2342 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2343 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2344 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2345 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2346 }
2347 }
2348
94352cf9 2349 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2350 if (ret) {
94352cf9 2351 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2352 mutex_unlock(&dev->struct_mutex);
a5071c2f 2353 DRM_ERROR("failed to update base address\n");
4e6cfefc 2354 return ret;
79e53945 2355 }
3c4fdcfb 2356
94352cf9
DV		 2357 old_fb = crtc->fb;
2358 crtc->fb = fb;
6c4c86f5
DV		 2359 crtc->x = x;
2360 crtc->y = y;
94352cf9 2361
b7f1de28 2362 if (old_fb) {
d7697eea
DV		 2363 if (intel_crtc->active && old_fb != fb)
2364 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2365 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2366 }
652c393a 2367
6b8e6ed0 2368 intel_update_fbc(dev);
4906557e 2369 intel_edp_psr_update(dev);
5c3b82e2 2370 mutex_unlock(&dev->struct_mutex);
79e53945 2371
198598d0 2372 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2373
2374 return 0;
79e53945
JB		 2375}
2376
5e84e1a4
ZW		 2377static void intel_fdi_normal_train(struct drm_crtc *crtc)
2378{
2379 struct drm_device *dev = crtc->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2382 int pipe = intel_crtc->pipe;
2383 u32 reg, temp;
2384
2385 /* enable normal train */
2386 reg = FDI_TX_CTL(pipe);
2387 temp = I915_READ(reg);
61e499bf 2388 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2389 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2390 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2391 } else {
2392 temp &= ~FDI_LINK_TRAIN_NONE;
2393 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2394 }
5e84e1a4
ZW		 2395 I915_WRITE(reg, temp);
2396
2397 reg = FDI_RX_CTL(pipe);
2398 temp = I915_READ(reg);
2399 if (HAS_PCH_CPT(dev)) {
2400 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2401 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2402 } else {
2403 temp &= ~FDI_LINK_TRAIN_NONE;
2404 temp |= FDI_LINK_TRAIN_NONE;
2405 }
2406 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2407
2408 /* wait one idle pattern time */
2409 POSTING_READ(reg);
2410 udelay(1000);
357555c0
JB		 2411
2412 /* IVB wants error correction enabled */
2413 if (IS_IVYBRIDGE(dev))
2414 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2415 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2416}
2417
1e833f40
DV		 2418static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2419{
2420 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2421}
2422
01a415fd
DV		 2423static void ivb_modeset_global_resources(struct drm_device *dev)
2424{
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 struct intel_crtc *pipe_B_crtc =
2427 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2428 struct intel_crtc *pipe_C_crtc =
2429 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2430 uint32_t temp;
2431
1e833f40
DV		 2432 /*
2433 * When everything is off disable fdi C so that we could enable fdi B
2434 * with all lanes. Note that we don't care about enabled pipes without
2435 * an enabled pch encoder.
2436 */
2437 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2438 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2439 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2440 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2441
2442 temp = I915_READ(SOUTH_CHICKEN1);
2443 temp &= ~FDI_BC_BIFURCATION_SELECT;
2444 DRM_DEBUG_KMS("disabling fdi C rx\n");
2445 I915_WRITE(SOUTH_CHICKEN1, temp);
2446 }
2447}
2448
8db9d77b
ZW		 2449/* The FDI link training functions for ILK/Ibexpeak. */
2450static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2451{
2452 struct drm_device *dev = crtc->dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455 int pipe = intel_crtc->pipe;
0fc932b8 2456 int plane = intel_crtc->plane;
5eddb70b 2457 u32 reg, temp, tries;
8db9d77b 2458
0fc932b8
JB		 2459 /* FDI needs bits from pipe & plane first */
2460 assert_pipe_enabled(dev_priv, pipe);
2461 assert_plane_enabled(dev_priv, plane);
2462
e1a44743
AJ		 2463 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2464 for train result */
5eddb70b
CW		 2465 reg = FDI_RX_IMR(pipe);
2466 temp = I915_READ(reg);
e1a44743
AJ		 2467 temp &= ~FDI_RX_SYMBOL_LOCK;
2468 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2469 I915_WRITE(reg, temp);
2470 I915_READ(reg);
e1a44743
AJ		 2471 udelay(150);
2472
8db9d77b 2473 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2474 reg = FDI_TX_CTL(pipe);
2475 temp = I915_READ(reg);
627eb5a3
DV		 2476 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2477 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2480 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2481
5eddb70b
CW		 2482 reg = FDI_RX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2486 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2487
2488 POSTING_READ(reg);
8db9d77b
ZW		 2489 udelay(150);
2490
5b2adf89 2491 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2492 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2493 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2494 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2495
5eddb70b 2496 reg = FDI_RX_IIR(pipe);
e1a44743 2497 for (tries = 0; tries < 5; tries++) {
5eddb70b 2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2500
2501 if ((temp & FDI_RX_BIT_LOCK)) {
2502 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2503 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2504 break;
2505 }
8db9d77b 2506 }
e1a44743 2507 if (tries == 5)
5eddb70b 2508 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2509
2510 /* Train 2 */
5eddb70b
CW		 2511 reg = FDI_TX_CTL(pipe);
2512 temp = I915_READ(reg);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2515 I915_WRITE(reg, temp);
8db9d77b 2516
5eddb70b
CW		 2517 reg = FDI_RX_CTL(pipe);
2518 temp = I915_READ(reg);
8db9d77b
ZW		 2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2521 I915_WRITE(reg, temp);
8db9d77b 2522
5eddb70b
CW		 2523 POSTING_READ(reg);
2524 udelay(150);
8db9d77b 2525
5eddb70b 2526 reg = FDI_RX_IIR(pipe);
e1a44743 2527 for (tries = 0; tries < 5; tries++) {
5eddb70b 2528 temp = I915_READ(reg);
8db9d77b
ZW		 2529 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2530
2531 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2532 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2533 DRM_DEBUG_KMS("FDI train 2 done.\n");
2534 break;
2535 }
8db9d77b 2536 }
e1a44743 2537 if (tries == 5)
5eddb70b 2538 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2539
2540 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2541
8db9d77b
ZW		 2542}
2543
0206e353 2544static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2545 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2546 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2547 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2548 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2549};
2550
2551/* The FDI link training functions for SNB/Cougarpoint. */
2552static void gen6_fdi_link_train(struct drm_crtc *crtc)
2553{
2554 struct drm_device *dev = crtc->dev;
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2557 int pipe = intel_crtc->pipe;
fa37d39e 2558 u32 reg, temp, i, retry;
8db9d77b 2559
e1a44743
AJ		 2560 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2561 for train result */
5eddb70b
CW		 2562 reg = FDI_RX_IMR(pipe);
2563 temp = I915_READ(reg);
e1a44743
AJ		 2564 temp &= ~FDI_RX_SYMBOL_LOCK;
2565 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
e1a44743
AJ		 2569 udelay(150);
2570
8db9d77b 2571 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2572 reg = FDI_TX_CTL(pipe);
2573 temp = I915_READ(reg);
627eb5a3
DV		 2574 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2575 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_1;
2578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579 /* SNB-B */
2580 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2581 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2582
d74cf324
DV		 2583 I915_WRITE(FDI_RX_MISC(pipe),
2584 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2585
5eddb70b
CW		 2586 reg = FDI_RX_CTL(pipe);
2587 temp = I915_READ(reg);
8db9d77b
ZW		 2588 if (HAS_PCH_CPT(dev)) {
2589 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2590 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2591 } else {
2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 }
5eddb70b
CW		 2595 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2596
2597 POSTING_READ(reg);
8db9d77b
ZW		 2598 udelay(150);
2599
0206e353 2600 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2601 reg = FDI_TX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2604 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
8db9d77b
ZW		 2608 udelay(500);
2609
fa37d39e
SP		 2610 for (retry = 0; retry < 5; retry++) {
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614 if (temp & FDI_RX_BIT_LOCK) {
2615 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2616 DRM_DEBUG_KMS("FDI train 1 done.\n");
2617 break;
2618 }
2619 udelay(50);
8db9d77b 2620 }
fa37d39e
SP		 2621 if (retry < 5)
2622 break;
8db9d77b
ZW		 2623 }
2624 if (i == 4)
5eddb70b 2625 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2626
2627 /* Train 2 */
5eddb70b
CW		 2628 reg = FDI_TX_CTL(pipe);
2629 temp = I915_READ(reg);
8db9d77b
ZW		 2630 temp &= ~FDI_LINK_TRAIN_NONE;
2631 temp |= FDI_LINK_TRAIN_PATTERN_2;
2632 if (IS_GEN6(dev)) {
2633 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2634 /* SNB-B */
2635 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2636 }
5eddb70b 2637 I915_WRITE(reg, temp);
8db9d77b 2638
5eddb70b
CW		 2639 reg = FDI_RX_CTL(pipe);
2640 temp = I915_READ(reg);
8db9d77b
ZW		 2641 if (HAS_PCH_CPT(dev)) {
2642 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2643 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2644 } else {
2645 temp &= ~FDI_LINK_TRAIN_NONE;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2;
2647 }
5eddb70b
CW		 2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
8db9d77b
ZW		 2651 udelay(150);
2652
0206e353 2653 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
8db9d77b
ZW		 2656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2658 I915_WRITE(reg, temp);
2659
2660 POSTING_READ(reg);
8db9d77b
ZW		 2661 udelay(500);
2662
fa37d39e
SP		 2663 for (retry = 0; retry < 5; retry++) {
2664 reg = FDI_RX_IIR(pipe);
2665 temp = I915_READ(reg);
2666 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2667 if (temp & FDI_RX_SYMBOL_LOCK) {
2668 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2669 DRM_DEBUG_KMS("FDI train 2 done.\n");
2670 break;
2671 }
2672 udelay(50);
8db9d77b 2673 }
fa37d39e
SP		 2674 if (retry < 5)
2675 break;
8db9d77b
ZW		 2676 }
2677 if (i == 4)
5eddb70b 2678 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2679
2680 DRM_DEBUG_KMS("FDI train done.\n");
2681}
2682
357555c0
JB		 2683/* Manual link training for Ivy Bridge A0 parts */
2684static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2685{
2686 struct drm_device *dev = crtc->dev;
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2689 int pipe = intel_crtc->pipe;
139ccd3f 2690 u32 reg, temp, i, j;
357555c0
JB		 2691
2692 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2693 for train result */
2694 reg = FDI_RX_IMR(pipe);
2695 temp = I915_READ(reg);
2696 temp &= ~FDI_RX_SYMBOL_LOCK;
2697 temp &= ~FDI_RX_BIT_LOCK;
2698 I915_WRITE(reg, temp);
2699
2700 POSTING_READ(reg);
2701 udelay(150);
2702
01a415fd
DV		 2703 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2704 I915_READ(FDI_RX_IIR(pipe)));
2705
139ccd3f
JB		 2706 /* Try each vswing and preemphasis setting twice before moving on */
2707 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2708 /* disable first in case we need to retry */
2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2712 temp &= ~FDI_TX_ENABLE;
2713 I915_WRITE(reg, temp);
357555c0 2714
139ccd3f
JB		 2715 reg = FDI_RX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_AUTO;
2718 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2719 temp &= ~FDI_RX_ENABLE;
2720 I915_WRITE(reg, temp);
357555c0 2721
139ccd3f 2722 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
139ccd3f
JB		 2725 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2726 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2727 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2728 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2729 temp |= snb_b_fdi_train_param[j/2];
2730 temp |= FDI_COMPOSITE_SYNC;
2731 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2732
139ccd3f
JB		 2733 I915_WRITE(FDI_RX_MISC(pipe),
2734 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2735
139ccd3f 2736 reg = FDI_RX_CTL(pipe);
357555c0 2737 temp = I915_READ(reg);
139ccd3f
JB		 2738 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2739 temp |= FDI_COMPOSITE_SYNC;
2740 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2741
139ccd3f
JB		 2742 POSTING_READ(reg);
2743 udelay(1); /* should be 0.5us */
357555c0 2744
139ccd3f
JB		 2745 for (i = 0; i < 4; i++) {
2746 reg = FDI_RX_IIR(pipe);
2747 temp = I915_READ(reg);
2748 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2749
139ccd3f
JB		 2750 if (temp & FDI_RX_BIT_LOCK ||
2751 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2752 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2753 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2754 i);
2755 break;
2756 }
2757 udelay(1); /* should be 0.5us */
2758 }
2759 if (i == 4) {
2760 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2761 continue;
2762 }
357555c0 2763
139ccd3f 2764 /* Train 2 */
357555c0
JB		 2765 reg = FDI_TX_CTL(pipe);
2766 temp = I915_READ(reg);
139ccd3f
JB		 2767 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2768 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2769 I915_WRITE(reg, temp);
2770
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2775 I915_WRITE(reg, temp);
2776
2777 POSTING_READ(reg);
139ccd3f 2778 udelay(2); /* should be 1.5us */
357555c0 2779
139ccd3f
JB		 2780 for (i = 0; i < 4; i++) {
2781 reg = FDI_RX_IIR(pipe);
2782 temp = I915_READ(reg);
2783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2784
139ccd3f
JB		 2785 if (temp & FDI_RX_SYMBOL_LOCK ||
2786 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2787 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2788 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2789 i);
2790 goto train_done;
2791 }
2792 udelay(2); /* should be 1.5us */
357555c0 2793 }
139ccd3f
JB		 2794 if (i == 4)
2795 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2796 }
357555c0 2797
139ccd3f 2798train_done:
357555c0
JB		 2799 DRM_DEBUG_KMS("FDI train done.\n");
2800}
2801
88cefb6c 2802static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2803{
88cefb6c 2804 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2805 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2806 int pipe = intel_crtc->pipe;
5eddb70b 2807 u32 reg, temp;
79e53945 2808
c64e311e 2809
c98e9dcf 2810 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
627eb5a3
DV		 2813 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2814 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2815 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2816 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2817
2818 POSTING_READ(reg);
c98e9dcf
JB		 2819 udelay(200);
2820
2821 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp | FDI_PCDCLK);
2824
2825 POSTING_READ(reg);
c98e9dcf
JB		 2826 udelay(200);
2827
20749730
PZ		 2828 /* Enable CPU FDI TX PLL, always on for Ironlake */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2832 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2833
20749730
PZ		 2834 POSTING_READ(reg);
2835 udelay(100);
6be4a607 2836 }
0e23b99d
JB		 2837}
2838
88cefb6c
DV		 2839static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2840{
2841 struct drm_device *dev = intel_crtc->base.dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 int pipe = intel_crtc->pipe;
2844 u32 reg, temp;
2845
2846 /* Switch from PCDclk to Rawclk */
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2850
2851 /* Disable CPU FDI TX PLL */
2852 reg = FDI_TX_CTL(pipe);
2853 temp = I915_READ(reg);
2854 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858
2859 reg = FDI_RX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2862
2863 /* Wait for the clocks to turn off. */
2864 POSTING_READ(reg);
2865 udelay(100);
2866}
2867
0fc932b8
JB		 2868static void ironlake_fdi_disable(struct drm_crtc *crtc)
2869{
2870 struct drm_device *dev = crtc->dev;
2871 struct drm_i915_private *dev_priv = dev->dev_private;
2872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2873 int pipe = intel_crtc->pipe;
2874 u32 reg, temp;
2875
2876 /* disable CPU FDI tx and PCH FDI rx */
2877 reg = FDI_TX_CTL(pipe);
2878 temp = I915_READ(reg);
2879 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2880 POSTING_READ(reg);
2881
2882 reg = FDI_RX_CTL(pipe);
2883 temp = I915_READ(reg);
2884 temp &= ~(0x7 << 16);
dfd07d72 2885 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2886 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2887
2888 POSTING_READ(reg);
2889 udelay(100);
2890
2891 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2892 if (HAS_PCH_IBX(dev)) {
2893 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2894 }
0fc932b8
JB		 2895
2896 /* still set train pattern 1 */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_1;
2901 I915_WRITE(reg, temp);
2902
2903 reg = FDI_RX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 if (HAS_PCH_CPT(dev)) {
2906 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2907 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2908 } else {
2909 temp &= ~FDI_LINK_TRAIN_NONE;
2910 temp |= FDI_LINK_TRAIN_PATTERN_1;
2911 }
2912 /* BPC in FDI rx is consistent with that in PIPECONF */
2913 temp &= ~(0x07 << 16);
dfd07d72 2914 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2915 I915_WRITE(reg, temp);
2916
2917 POSTING_READ(reg);
2918 udelay(100);
2919}
2920
5bb61643
CW		 2921static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2922{
2923 struct drm_device *dev = crtc->dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2926 unsigned long flags;
2927 bool pending;
2928
10d83730
VS		 2929 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2930 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2931 return false;
2932
2933 spin_lock_irqsave(&dev->event_lock, flags);
2934 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2935 spin_unlock_irqrestore(&dev->event_lock, flags);
2936
2937 return pending;
2938}
2939
e6c3a2a6
CW		 2940static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2941{
0f91128d 2942 struct drm_device *dev = crtc->dev;
5bb61643 2943 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2944
2945 if (crtc->fb == NULL)
2946 return;
2947
2c10d571
DV		 2948 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2949
5bb61643
CW		 2950 wait_event(dev_priv->pending_flip_queue,
2951 !intel_crtc_has_pending_flip(crtc));
2952
0f91128d
CW		 2953 mutex_lock(&dev->struct_mutex);
2954 intel_finish_fb(crtc->fb);
2955 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2956}
2957
e615efe4
ED		 2958/* Program iCLKIP clock to the desired frequency */
2959static void lpt_program_iclkip(struct drm_crtc *crtc)
2960{
2961 struct drm_device *dev = crtc->dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2963 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2964 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2965 u32 temp;
2966
09153000
DV		 2967 mutex_lock(&dev_priv->dpio_lock);
2968
e615efe4
ED		 2969 /* It is necessary to ungate the pixclk gate prior to programming
2970 * the divisors, and gate it back when it is done.
2971 */
2972 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2973
2974 /* Disable SSCCTL */
2975 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2976 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2977 SBI_SSCCTL_DISABLE,
2978 SBI_ICLK);
e615efe4
ED		 2979
2980 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2981 if (clock == 20000) {
e615efe4
ED		 2982 auxdiv = 1;
2983 divsel = 0x41;
2984 phaseinc = 0x20;
2985 } else {
2986 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2987 * but the adjusted_mode->crtc_clock in in KHz. To get the
2988 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2989 * convert the virtual clock precision to KHz here for higher
2990 * precision.
2991 */
2992 u32 iclk_virtual_root_freq = 172800 * 1000;
2993 u32 iclk_pi_range = 64;
2994 u32 desired_divisor, msb_divisor_value, pi_value;
2995
12d7ceed 2996 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2997 msb_divisor_value = desired_divisor / iclk_pi_range;
2998 pi_value = desired_divisor % iclk_pi_range;
2999
3000 auxdiv = 0;
3001 divsel = msb_divisor_value - 2;
3002 phaseinc = pi_value;
3003 }
3004
3005 /* This should not happen with any sane values */
3006 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3007 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3008 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3009 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3010
3011 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3012 clock,
e615efe4
ED		 3013 auxdiv,
3014 divsel,
3015 phasedir,
3016 phaseinc);
3017
3018 /* Program SSCDIVINTPHASE6 */
988d6ee8 3019 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3020 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3021 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3022 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3023 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3024 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3025 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3026 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3027
3028 /* Program SSCAUXDIV */
988d6ee8 3029 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3030 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3031 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3032 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3033
3034 /* Enable modulator and associated divider */
988d6ee8 3035 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3036 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3037 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3038
3039 /* Wait for initialization time */
3040 udelay(24);
3041
3042 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3043
3044 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3045}
3046
275f01b2
DV		 3047static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3048 enum pipe pch_transcoder)
3049{
3050 struct drm_device *dev = crtc->base.dev;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3053
3054 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3055 I915_READ(HTOTAL(cpu_transcoder)));
3056 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3057 I915_READ(HBLANK(cpu_transcoder)));
3058 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3059 I915_READ(HSYNC(cpu_transcoder)));
3060
3061 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3062 I915_READ(VTOTAL(cpu_transcoder)));
3063 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3064 I915_READ(VBLANK(cpu_transcoder)));
3065 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3066 I915_READ(VSYNC(cpu_transcoder)));
3067 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3068 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3069}
3070
f67a559d
JB		 3071/*
3072 * Enable PCH resources required for PCH ports:
3073 * - PCH PLLs
3074 * - FDI training & RX/TX
3075 * - update transcoder timings
3076 * - DP transcoding bits
3077 * - transcoder
3078 */
3079static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3080{
3081 struct drm_device *dev = crtc->dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3084 int pipe = intel_crtc->pipe;
ee7b9f93 3085 u32 reg, temp;
2c07245f 3086
ab9412ba 3087 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3088
cd986abb
DV		 3089 /* Write the TU size bits before fdi link training, so that error
3090 * detection works. */
3091 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3092 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3093
c98e9dcf 3094 /* For PCH output, training FDI link */
674cf967 3095 dev_priv->display.fdi_link_train(crtc);
2c07245f 3096
3ad8a208
DV		 3097 /* We need to program the right clock selection before writing the pixel
3098 * mutliplier into the DPLL. */
303b81e0 3099 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3100 u32 sel;
4b645f14 3101
c98e9dcf 3102 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3103 temp |= TRANS_DPLL_ENABLE(pipe);
3104 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3105 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3106 temp |= sel;
3107 else
3108 temp &= ~sel;
c98e9dcf 3109 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3110 }
5eddb70b 3111
3ad8a208
DV		 3112 /* XXX: pch pll's can be enabled any time before we enable the PCH
3113 * transcoder, and we actually should do this to not upset any PCH
3114 * transcoder that already use the clock when we share it.
3115 *
3116 * Note that enable_shared_dpll tries to do the right thing, but
3117 * get_shared_dpll unconditionally resets the pll - we need that to have
3118 * the right LVDS enable sequence. */
3119 ironlake_enable_shared_dpll(intel_crtc);
3120
d9b6cb56
JB		 3121 /* set transcoder timing, panel must allow it */
3122 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3123 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3124
303b81e0 3125 intel_fdi_normal_train(crtc);
5e84e1a4 3126
c98e9dcf
JB		 3127 /* For PCH DP, enable TRANS_DP_CTL */
3128 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3129 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3130 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3131 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3132 reg = TRANS_DP_CTL(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3135 TRANS_DP_SYNC_MASK |
3136 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3137 temp |= (TRANS_DP_OUTPUT_ENABLE |
3138 TRANS_DP_ENH_FRAMING);
9325c9f0 3139 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3140
3141 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3142 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3143 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3144 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3145
3146 switch (intel_trans_dp_port_sel(crtc)) {
3147 case PCH_DP_B:
5eddb70b 3148 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3149 break;
3150 case PCH_DP_C:
5eddb70b 3151 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3152 break;
3153 case PCH_DP_D:
5eddb70b 3154 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3155 break;
3156 default:
e95d41e1 3157 BUG();
32f9d658 3158 }
2c07245f 3159
5eddb70b 3160 I915_WRITE(reg, temp);
6be4a607 3161 }
b52eb4dc 3162
b8a4f404 3163 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3164}
3165
1507e5bd
PZ		 3166static void lpt_pch_enable(struct drm_crtc *crtc)
3167{
3168 struct drm_device *dev = crtc->dev;
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3171 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3172
ab9412ba 3173 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3174
8c52b5e8 3175 lpt_program_iclkip(crtc);
1507e5bd 3176
0540e488 3177 /* Set transcoder timing. */
275f01b2 3178 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3179
937bb610 3180 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3181}
3182
e2b78267 3183static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3184{
e2b78267 3185 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3186
3187 if (pll == NULL)
3188 return;
3189
3190 if (pll->refcount == 0) {
46edb027 3191 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3192 return;
3193 }
3194
f4a091c7
DV		 3195 if (--pll->refcount == 0) {
3196 WARN_ON(pll->on);
3197 WARN_ON(pll->active);
3198 }
3199
a43f6e0f 3200 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3201}
3202
b89a1d39 3203static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3204{
e2b78267
DV		 3205 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3206 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3207 enum intel_dpll_id i;
ee7b9f93 3208
ee7b9f93 3209 if (pll) {
46edb027
DV		 3210 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3211 crtc->base.base.id, pll->name);
e2b78267 3212 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3213 }
3214
98b6bd99
DV		 3215 if (HAS_PCH_IBX(dev_priv->dev)) {
3216 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3217 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3218 pll = &dev_priv->shared_dplls[i];
98b6bd99 3219
46edb027
DV		 3220 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3221 crtc->base.base.id, pll->name);
98b6bd99
DV		 3222
3223 goto found;
3224 }
3225
e72f9fbf
DV		 3226 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3227 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3228
3229 /* Only want to check enabled timings first */
3230 if (pll->refcount == 0)
3231 continue;
3232
b89a1d39
DV		 3233 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3234 sizeof(pll->hw_state)) == 0) {
46edb027 3235 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3236 crtc->base.base.id,
46edb027 3237 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3238
3239 goto found;
3240 }
3241 }
3242
3243 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3245 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3246 if (pll->refcount == 0) {
46edb027
DV		 3247 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3248 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3249 goto found;
3250 }
3251 }
3252
3253 return NULL;
3254
3255found:
a43f6e0f 3256 crtc->config.shared_dpll = i;
46edb027
DV		 3257 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3258 pipe_name(crtc->pipe));
ee7b9f93 3259
cdbd2316 3260 if (pll->active == 0) {
66e985c0
DV		 3261 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3262 sizeof(pll->hw_state));
3263
46edb027 3264 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3265 WARN_ON(pll->on);
e9d6944e 3266 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3267
15bdd4cf 3268 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3269 }
3270 pll->refcount++;
e04c7350 3271
ee7b9f93
JB		 3272 return pll;
3273}
3274
a1520318 3275static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3276{
3277 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3278 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3279 u32 temp;
3280
3281 temp = I915_READ(dslreg);
3282 udelay(500);
3283 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3284 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3285 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3286 }
3287}
3288
b074cec8
JB		 3289static void ironlake_pfit_enable(struct intel_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->base.dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 int pipe = crtc->pipe;
3294
fd4daa9c 3295 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3296 /* Force use of hard-coded filter coefficients
3297 * as some pre-programmed values are broken,
3298 * e.g. x201.
3299 */
3300 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3301 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3302 PF_PIPE_SEL_IVB(pipe));
3303 else
3304 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3305 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3306 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3307 }
3308}
3309
bb53d4ae
VS		 3310static void intel_enable_planes(struct drm_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->dev;
3313 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3314 struct intel_plane *intel_plane;
3315
3316 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3317 if (intel_plane->pipe == pipe)
3318 intel_plane_restore(&intel_plane->base);
3319}
3320
3321static void intel_disable_planes(struct drm_crtc *crtc)
3322{
3323 struct drm_device *dev = crtc->dev;
3324 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3325 struct intel_plane *intel_plane;
3326
3327 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3328 if (intel_plane->pipe == pipe)
3329 intel_plane_disable(&intel_plane->base);
3330}
3331
20bc8673 3332void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3333{
3334 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3335
3336 if (!crtc->config.ips_enabled)
3337 return;
3338
3339 /* We can only enable IPS after we enable a plane and wait for a vblank.
3340 * We guarantee that the plane is enabled by calling intel_enable_ips
3341 * only after intel_enable_plane. And intel_enable_plane already waits
3342 * for a vblank, so all we need to do here is to enable the IPS bit. */
3343 assert_plane_enabled(dev_priv, crtc->plane);
3344 I915_WRITE(IPS_CTL, IPS_ENABLE);
3345}
3346
20bc8673 3347void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3348{
3349 struct drm_device *dev = crtc->base.dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351
3352 if (!crtc->config.ips_enabled)
3353 return;
3354
3355 assert_plane_enabled(dev_priv, crtc->plane);
3356 I915_WRITE(IPS_CTL, 0);
3357 POSTING_READ(IPS_CTL);
3358
3359 /* We need to wait for a vblank before we can disable the plane. */
3360 intel_wait_for_vblank(dev, crtc->pipe);
3361}
3362
3363/** Loads the palette/gamma unit for the CRTC with the prepared values */
3364static void intel_crtc_load_lut(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 enum pipe pipe = intel_crtc->pipe;
3370 int palreg = PALETTE(pipe);
3371 int i;
3372 bool reenable_ips = false;
3373
3374 /* The clocks have to be on to load the palette. */
3375 if (!crtc->enabled || !intel_crtc->active)
3376 return;
3377
3378 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3379 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3380 assert_dsi_pll_enabled(dev_priv);
3381 else
3382 assert_pll_enabled(dev_priv, pipe);
3383 }
3384
3385 /* use legacy palette for Ironlake */
3386 if (HAS_PCH_SPLIT(dev))
3387 palreg = LGC_PALETTE(pipe);
3388
3389 /* Workaround : Do not read or write the pipe palette/gamma data while
3390 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3391 */
3392 if (intel_crtc->config.ips_enabled &&
3393 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3394 GAMMA_MODE_MODE_SPLIT)) {
3395 hsw_disable_ips(intel_crtc);
3396 reenable_ips = true;
3397 }
3398
3399 for (i = 0; i < 256; i++) {
3400 I915_WRITE(palreg + 4 * i,
3401 (intel_crtc->lut_r[i] << 16) |
3402 (intel_crtc->lut_g[i] << 8) |
3403 intel_crtc->lut_b[i]);
3404 }
3405
3406 if (reenable_ips)
3407 hsw_enable_ips(intel_crtc);
3408}
3409
f67a559d
JB		 3410static void ironlake_crtc_enable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3415 struct intel_encoder *encoder;
f67a559d
JB		 3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
f67a559d 3418
08a48469
DV		 3419 WARN_ON(!crtc->enabled);
3420
f67a559d
JB		 3421 if (intel_crtc->active)
3422 return;
3423
3424 intel_crtc->active = true;
8664281b
PZ		 3425
3426 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3427 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3428
f6736a1a 3429 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3430 if (encoder->pre_enable)
3431 encoder->pre_enable(encoder);
f67a559d 3432
5bfe2ac0 3433 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3434 /* Note: FDI PLL enabling _must_ be done before we enable the
3435 * cpu pipes, hence this is separate from all the other fdi/pch
3436 * enabling. */
88cefb6c 3437 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3438 } else {
3439 assert_fdi_tx_disabled(dev_priv, pipe);
3440 assert_fdi_rx_disabled(dev_priv, pipe);
3441 }
f67a559d 3442
b074cec8 3443 ironlake_pfit_enable(intel_crtc);
f67a559d 3444
9c54c0dd
JB		 3445 /*
3446 * On ILK+ LUT must be loaded before the pipe is running but with
3447 * clocks enabled
3448 */
3449 intel_crtc_load_lut(crtc);
3450
f37fcc2a 3451 intel_update_watermarks(crtc);
5bfe2ac0 3452 intel_enable_pipe(dev_priv, pipe,
23538ef1 3453 intel_crtc->config.has_pch_encoder, false);
d1de00ef 3454 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3455 intel_enable_planes(crtc);
5c38d48c 3456 intel_crtc_update_cursor(crtc, true);
f67a559d 3457
5bfe2ac0 3458 if (intel_crtc->config.has_pch_encoder)
f67a559d 3459 ironlake_pch_enable(crtc);
c98e9dcf 3460
d1ebd816 3461 mutex_lock(&dev->struct_mutex);
bed4a673 3462 intel_update_fbc(dev);
d1ebd816
BW		 3463 mutex_unlock(&dev->struct_mutex);
3464
fa5c73b1
DV		 3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->enable(encoder);
61b77ddd
DV		 3467
3468 if (HAS_PCH_CPT(dev))
a1520318 3469 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3470
3471 /*
3472 * There seems to be a race in PCH platform hw (at least on some
3473 * outputs) where an enabled pipe still completes any pageflip right
3474 * away (as if the pipe is off) instead of waiting for vblank. As soon
3475 * as the first vblank happend, everything works as expected. Hence just
3476 * wait for one vblank before returning to avoid strange things
3477 * happening.
3478 */
3479 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3480}
3481
42db64ef
PZ		 3482/* IPS only exists on ULT machines and is tied to pipe A. */
3483static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3484{
f5adf94e 3485 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3486}
3487
dda9a66a
VS		 3488static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3489{
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493 int pipe = intel_crtc->pipe;
3494 int plane = intel_crtc->plane;
3495
d1de00ef 3496 intel_enable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3497 intel_enable_planes(crtc);
3498 intel_crtc_update_cursor(crtc, true);
3499
3500 hsw_enable_ips(intel_crtc);
3501
3502 mutex_lock(&dev->struct_mutex);
3503 intel_update_fbc(dev);
3504 mutex_unlock(&dev->struct_mutex);
3505}
3506
3507static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3508{
3509 struct drm_device *dev = crtc->dev;
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3512 int pipe = intel_crtc->pipe;
3513 int plane = intel_crtc->plane;
3514
3515 intel_crtc_wait_for_pending_flips(crtc);
3516 drm_vblank_off(dev, pipe);
3517
3518 /* FBC must be disabled before disabling the plane on HSW. */
3519 if (dev_priv->fbc.plane == plane)
3520 intel_disable_fbc(dev);
3521
3522 hsw_disable_ips(intel_crtc);
3523
3524 intel_crtc_update_cursor(crtc, false);
3525 intel_disable_planes(crtc);
d1de00ef 3526 intel_disable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3527}
3528
e4916946
PZ		 3529/*
3530 * This implements the workaround described in the "notes" section of the mode
3531 * set sequence documentation. When going from no pipes or single pipe to
3532 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3533 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3534 */
3535static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3536{
3537 struct drm_device *dev = crtc->base.dev;
3538 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3539
3540 /* We want to get the other_active_crtc only if there's only 1 other
3541 * active crtc. */
3542 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3543 if (!crtc_it->active || crtc_it == crtc)
3544 continue;
3545
3546 if (other_active_crtc)
3547 return;
3548
3549 other_active_crtc = crtc_it;
3550 }
3551 if (!other_active_crtc)
3552 return;
3553
3554 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3555 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3556}
3557
4f771f10
PZ		 3558static void haswell_crtc_enable(struct drm_crtc *crtc)
3559{
3560 struct drm_device *dev = crtc->dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3563 struct intel_encoder *encoder;
3564 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3565
3566 WARN_ON(!crtc->enabled);
3567
3568 if (intel_crtc->active)
3569 return;
3570
3571 intel_crtc->active = true;
8664281b
PZ		 3572
3573 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3574 if (intel_crtc->config.has_pch_encoder)
3575 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3576
5bfe2ac0 3577 if (intel_crtc->config.has_pch_encoder)
04945641 3578 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3579
3580 for_each_encoder_on_crtc(dev, crtc, encoder)
3581 if (encoder->pre_enable)
3582 encoder->pre_enable(encoder);
3583
1f544388 3584 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3585
b074cec8 3586 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3587
3588 /*
3589 * On ILK+ LUT must be loaded before the pipe is running but with
3590 * clocks enabled
3591 */
3592 intel_crtc_load_lut(crtc);
3593
1f544388 3594 intel_ddi_set_pipe_settings(crtc);
8228c251 3595 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3596
f37fcc2a 3597 intel_update_watermarks(crtc);
5bfe2ac0 3598 intel_enable_pipe(dev_priv, pipe,
23538ef1 3599 intel_crtc->config.has_pch_encoder, false);
42db64ef 3600
5bfe2ac0 3601 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3602 lpt_pch_enable(crtc);
4f771f10 3603
8807e55b 3604 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3605 encoder->enable(encoder);
8807e55b
JN		 3606 intel_opregion_notify_encoder(encoder, true);
3607 }
4f771f10 3608
e4916946
PZ		 3609 /* If we change the relative order between pipe/planes enabling, we need
3610 * to change the workaround. */
3611 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3612 haswell_crtc_enable_planes(crtc);
3613
4f771f10
PZ		 3614 /*
3615 * There seems to be a race in PCH platform hw (at least on some
3616 * outputs) where an enabled pipe still completes any pageflip right
3617 * away (as if the pipe is off) instead of waiting for vblank. As soon
3618 * as the first vblank happend, everything works as expected. Hence just
3619 * wait for one vblank before returning to avoid strange things
3620 * happening.
3621 */
3622 intel_wait_for_vblank(dev, intel_crtc->pipe);
3623}
3624
3f8dce3a
DV		 3625static void ironlake_pfit_disable(struct intel_crtc *crtc)
3626{
3627 struct drm_device *dev = crtc->base.dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 int pipe = crtc->pipe;
3630
3631 /* To avoid upsetting the power well on haswell only disable the pfit if
3632 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3633 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3634 I915_WRITE(PF_CTL(pipe), 0);
3635 I915_WRITE(PF_WIN_POS(pipe), 0);
3636 I915_WRITE(PF_WIN_SZ(pipe), 0);
3637 }
3638}
3639
6be4a607
JB		 3640static void ironlake_crtc_disable(struct drm_crtc *crtc)
3641{
3642 struct drm_device *dev = crtc->dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3645 struct intel_encoder *encoder;
6be4a607
JB		 3646 int pipe = intel_crtc->pipe;
3647 int plane = intel_crtc->plane;
5eddb70b 3648 u32 reg, temp;
b52eb4dc 3649
ef9c3aee 3650
f7abfe8b
CW		 3651 if (!intel_crtc->active)
3652 return;
3653
ea9d758d
DV		 3654 for_each_encoder_on_crtc(dev, crtc, encoder)
3655 encoder->disable(encoder);
3656
e6c3a2a6 3657 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3658 drm_vblank_off(dev, pipe);
913d8d11 3659
5c3fe8b0 3660 if (dev_priv->fbc.plane == plane)
973d04f9 3661 intel_disable_fbc(dev);
2c07245f 3662
0d5b8c61 3663 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3664 intel_disable_planes(crtc);
d1de00ef 3665 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3666
d925c59a
DV		 3667 if (intel_crtc->config.has_pch_encoder)
3668 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3669
b24e7179 3670 intel_disable_pipe(dev_priv, pipe);
32f9d658 3671
3f8dce3a 3672 ironlake_pfit_disable(intel_crtc);
2c07245f 3673
bf49ec8c
DV		 3674 for_each_encoder_on_crtc(dev, crtc, encoder)
3675 if (encoder->post_disable)
3676 encoder->post_disable(encoder);
2c07245f 3677
d925c59a
DV		 3678 if (intel_crtc->config.has_pch_encoder) {
3679 ironlake_fdi_disable(crtc);
913d8d11 3680
d925c59a
DV		 3681 ironlake_disable_pch_transcoder(dev_priv, pipe);
3682 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3683
d925c59a
DV		 3684 if (HAS_PCH_CPT(dev)) {
3685 /* disable TRANS_DP_CTL */
3686 reg = TRANS_DP_CTL(pipe);
3687 temp = I915_READ(reg);
3688 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3689 TRANS_DP_PORT_SEL_MASK);
3690 temp |= TRANS_DP_PORT_SEL_NONE;
3691 I915_WRITE(reg, temp);
3692
3693 /* disable DPLL_SEL */
3694 temp = I915_READ(PCH_DPLL_SEL);
11887397 3695 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3696 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3697 }
e3421a18 3698
d925c59a 3699 /* disable PCH DPLL */
e72f9fbf 3700 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3701
d925c59a
DV		 3702 ironlake_fdi_pll_disable(intel_crtc);
3703 }
6b383a7f 3704
f7abfe8b 3705 intel_crtc->active = false;
46ba614c 3706 intel_update_watermarks(crtc);
d1ebd816
BW		 3707
3708 mutex_lock(&dev->struct_mutex);
6b383a7f 3709 intel_update_fbc(dev);
d1ebd816 3710 mutex_unlock(&dev->struct_mutex);
6be4a607 3711}
1b3c7a47 3712
4f771f10 3713static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3714{
4f771f10
PZ		 3715 struct drm_device *dev = crtc->dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3718 struct intel_encoder *encoder;
3719 int pipe = intel_crtc->pipe;
3b117c8f 3720 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3721
4f771f10
PZ		 3722 if (!intel_crtc->active)
3723 return;
3724
dda9a66a
VS		 3725 haswell_crtc_disable_planes(crtc);
3726
8807e55b
JN		 3727 for_each_encoder_on_crtc(dev, crtc, encoder) {
3728 intel_opregion_notify_encoder(encoder, false);
4f771f10 3729 encoder->disable(encoder);
8807e55b 3730 }
4f771f10 3731
8664281b
PZ		 3732 if (intel_crtc->config.has_pch_encoder)
3733 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3734 intel_disable_pipe(dev_priv, pipe);
3735
ad80a810 3736 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3737
3f8dce3a 3738 ironlake_pfit_disable(intel_crtc);
4f771f10 3739
1f544388 3740 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3741
3742 for_each_encoder_on_crtc(dev, crtc, encoder)
3743 if (encoder->post_disable)
3744 encoder->post_disable(encoder);
3745
88adfff1 3746 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3747 lpt_disable_pch_transcoder(dev_priv);
8664281b 3748 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3749 intel_ddi_fdi_disable(crtc);
83616634 3750 }
4f771f10
PZ		 3751
3752 intel_crtc->active = false;
46ba614c 3753 intel_update_watermarks(crtc);
4f771f10
PZ		 3754
3755 mutex_lock(&dev->struct_mutex);
3756 intel_update_fbc(dev);
3757 mutex_unlock(&dev->struct_mutex);
3758}
3759
ee7b9f93
JB		 3760static void ironlake_crtc_off(struct drm_crtc *crtc)
3761{
3762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3763 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3764}
3765
6441ab5f
PZ		 3766static void haswell_crtc_off(struct drm_crtc *crtc)
3767{
3768 intel_ddi_put_crtc_pll(crtc);
3769}
3770
02e792fb
DV		 3771static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3772{
02e792fb 3773 if (!enable && intel_crtc->overlay) {
23f09ce3 3774 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3775 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3776
23f09ce3 3777 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3778 dev_priv->mm.interruptible = false;
3779 (void) intel_overlay_switch_off(intel_crtc->overlay);
3780 dev_priv->mm.interruptible = true;
23f09ce3 3781 mutex_unlock(&dev->struct_mutex);
02e792fb 3782 }
02e792fb 3783
5dcdbcb0
CW		 3784 /* Let userspace switch the overlay on again. In most cases userspace
3785 * has to recompute where to put it anyway.
3786 */
02e792fb
DV		 3787}
3788
61bc95c1
EE		 3789/**
3790 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3791 * cursor plane briefly if not already running after enabling the display
3792 * plane.
3793 * This workaround avoids occasional blank screens when self refresh is
3794 * enabled.
3795 */
3796static void
3797g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3798{
3799 u32 cntl = I915_READ(CURCNTR(pipe));
3800
3801 if ((cntl & CURSOR_MODE) == 0) {
3802 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3803
3804 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3805 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3806 intel_wait_for_vblank(dev_priv->dev, pipe);
3807 I915_WRITE(CURCNTR(pipe), cntl);
3808 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3809 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3810 }
3811}
3812
2dd24552
JB		 3813static void i9xx_pfit_enable(struct intel_crtc *crtc)
3814{
3815 struct drm_device *dev = crtc->base.dev;
3816 struct drm_i915_private *dev_priv = dev->dev_private;
3817 struct intel_crtc_config *pipe_config = &crtc->config;
3818
328d8e82 3819 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3820 return;
3821
2dd24552 3822 /*
c0b03411
DV		 3823 * The panel fitter should only be adjusted whilst the pipe is disabled,
3824 * according to register description and PRM.
2dd24552 3825 */
c0b03411
DV		 3826 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3827 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3828
b074cec8
JB		 3829 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3830 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3831
3832 /* Border color in case we don't scale up to the full screen. Black by
3833 * default, change to something else for debugging. */
3834 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3835}
3836
89b667f8
JB		 3837static void valleyview_crtc_enable(struct drm_crtc *crtc)
3838{
3839 struct drm_device *dev = crtc->dev;
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3842 struct intel_encoder *encoder;
3843 int pipe = intel_crtc->pipe;
3844 int plane = intel_crtc->plane;
23538ef1 3845 bool is_dsi;
89b667f8
JB		 3846
3847 WARN_ON(!crtc->enabled);
3848
3849 if (intel_crtc->active)
3850 return;
3851
3852 intel_crtc->active = true;
89b667f8 3853
89b667f8
JB		 3854 for_each_encoder_on_crtc(dev, crtc, encoder)
3855 if (encoder->pre_pll_enable)
3856 encoder->pre_pll_enable(encoder);
3857
23538ef1
JN		 3858 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3859
e9fd1c02
JN		 3860 if (!is_dsi)
3861 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3862
3863 for_each_encoder_on_crtc(dev, crtc, encoder)
3864 if (encoder->pre_enable)
3865 encoder->pre_enable(encoder);
3866
2dd24552
JB		 3867 i9xx_pfit_enable(intel_crtc);
3868
63cbb074
VS		 3869 intel_crtc_load_lut(crtc);
3870
f37fcc2a 3871 intel_update_watermarks(crtc);
23538ef1 3872 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
d1de00ef 3873 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3874 intel_enable_planes(crtc);
5c38d48c 3875 intel_crtc_update_cursor(crtc, true);
89b667f8 3876
89b667f8 3877 intel_update_fbc(dev);
5004945f
JN		 3878
3879 for_each_encoder_on_crtc(dev, crtc, encoder)
3880 encoder->enable(encoder);
89b667f8
JB		 3881}
3882
0b8765c6 3883static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3884{
3885 struct drm_device *dev = crtc->dev;
79e53945
JB		 3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3888 struct intel_encoder *encoder;
79e53945 3889 int pipe = intel_crtc->pipe;
80824003 3890 int plane = intel_crtc->plane;
79e53945 3891
08a48469
DV		 3892 WARN_ON(!crtc->enabled);
3893
f7abfe8b
CW		 3894 if (intel_crtc->active)
3895 return;
3896
3897 intel_crtc->active = true;
6b383a7f 3898
9d6d9f19
MK		 3899 for_each_encoder_on_crtc(dev, crtc, encoder)
3900 if (encoder->pre_enable)
3901 encoder->pre_enable(encoder);
3902
f6736a1a
DV		 3903 i9xx_enable_pll(intel_crtc);
3904
2dd24552
JB		 3905 i9xx_pfit_enable(intel_crtc);
3906
63cbb074
VS		 3907 intel_crtc_load_lut(crtc);
3908
f37fcc2a 3909 intel_update_watermarks(crtc);
23538ef1 3910 intel_enable_pipe(dev_priv, pipe, false, false);
d1de00ef 3911 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3912 intel_enable_planes(crtc);
22e407d7 3913 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3914 if (IS_G4X(dev))
3915 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3916 intel_crtc_update_cursor(crtc, true);
79e53945 3917
0b8765c6
JB		 3918 /* Give the overlay scaler a chance to enable if it's on this pipe */
3919 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3920
f440eb13 3921 intel_update_fbc(dev);
ef9c3aee 3922
fa5c73b1
DV		 3923 for_each_encoder_on_crtc(dev, crtc, encoder)
3924 encoder->enable(encoder);
0b8765c6 3925}
79e53945 3926
87476d63
DV		 3927static void i9xx_pfit_disable(struct intel_crtc *crtc)
3928{
3929 struct drm_device *dev = crtc->base.dev;
3930 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3931
328d8e82
DV		 3932 if (!crtc->config.gmch_pfit.control)
3933 return;
87476d63 3934
328d8e82 3935 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3936
328d8e82
DV		 3937 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3938 I915_READ(PFIT_CONTROL));
3939 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3940}
3941
0b8765c6
JB		 3942static void i9xx_crtc_disable(struct drm_crtc *crtc)
3943{
3944 struct drm_device *dev = crtc->dev;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3947 struct intel_encoder *encoder;
0b8765c6
JB		 3948 int pipe = intel_crtc->pipe;
3949 int plane = intel_crtc->plane;
ef9c3aee 3950
f7abfe8b
CW		 3951 if (!intel_crtc->active)
3952 return;
3953
ea9d758d
DV		 3954 for_each_encoder_on_crtc(dev, crtc, encoder)
3955 encoder->disable(encoder);
3956
0b8765c6 3957 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3958 intel_crtc_wait_for_pending_flips(crtc);
3959 drm_vblank_off(dev, pipe);
0b8765c6 3960
5c3fe8b0 3961 if (dev_priv->fbc.plane == plane)
973d04f9 3962 intel_disable_fbc(dev);
79e53945 3963
0d5b8c61
VS		 3964 intel_crtc_dpms_overlay(intel_crtc, false);
3965 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3966 intel_disable_planes(crtc);
d1de00ef 3967 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3968
b24e7179 3969 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3970
87476d63 3971 i9xx_pfit_disable(intel_crtc);
24a1f16d 3972
89b667f8
JB		 3973 for_each_encoder_on_crtc(dev, crtc, encoder)
3974 if (encoder->post_disable)
3975 encoder->post_disable(encoder);
3976
f6071166
JB		 3977 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3978 vlv_disable_pll(dev_priv, pipe);
3979 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3980 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3981
f7abfe8b 3982 intel_crtc->active = false;
46ba614c 3983 intel_update_watermarks(crtc);
f37fcc2a 3984
6b383a7f 3985 intel_update_fbc(dev);
0b8765c6
JB		 3986}
3987
ee7b9f93
JB		 3988static void i9xx_crtc_off(struct drm_crtc *crtc)
3989{
3990}
3991
976f8a20
DV		 3992static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3993 bool enabled)
2c07245f
ZW		 3994{
3995 struct drm_device *dev = crtc->dev;
3996 struct drm_i915_master_private *master_priv;
3997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3998 int pipe = intel_crtc->pipe;
79e53945
JB		 3999
4000 if (!dev->primary->master)
4001 return;
4002
4003 master_priv = dev->primary->master->driver_priv;
4004 if (!master_priv->sarea_priv)
4005 return;
4006
79e53945
JB		 4007 switch (pipe) {
4008 case 0:
4009 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4010 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4011 break;
4012 case 1:
4013 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4014 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4015 break;
4016 default:
9db4a9c7 4017 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4018 break;
4019 }
79e53945
JB		 4020}
4021
976f8a20
DV		 4022/**
4023 * Sets the power management mode of the pipe and plane.
4024 */
4025void intel_crtc_update_dpms(struct drm_crtc *crtc)
4026{
4027 struct drm_device *dev = crtc->dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 struct intel_encoder *intel_encoder;
4030 bool enable = false;
4031
4032 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4033 enable |= intel_encoder->connectors_active;
4034
4035 if (enable)
4036 dev_priv->display.crtc_enable(crtc);
4037 else
4038 dev_priv->display.crtc_disable(crtc);
4039
4040 intel_crtc_update_sarea(crtc, enable);
4041}
4042
cdd59983
CW		 4043static void intel_crtc_disable(struct drm_crtc *crtc)
4044{
cdd59983 4045 struct drm_device *dev = crtc->dev;
976f8a20 4046 struct drm_connector *connector;
ee7b9f93 4047 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4049
976f8a20
DV		 4050 /* crtc should still be enabled when we disable it. */
4051 WARN_ON(!crtc->enabled);
4052
4053 dev_priv->display.crtc_disable(crtc);
c77bf565 4054 intel_crtc->eld_vld = false;
976f8a20 4055 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4056 dev_priv->display.off(crtc);
4057
931872fc 4058 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4059 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4060 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4061
4062 if (crtc->fb) {
4063 mutex_lock(&dev->struct_mutex);
1690e1eb 4064 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4065 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4066 crtc->fb = NULL;
4067 }
4068
4069 /* Update computed state. */
4070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4071 if (!connector->encoder || !connector->encoder->crtc)
4072 continue;
4073
4074 if (connector->encoder->crtc != crtc)
4075 continue;
4076
4077 connector->dpms = DRM_MODE_DPMS_OFF;
4078 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4079 }
4080}
4081
ea5b213a 4082void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4083{
4ef69c7a 4084 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4085
ea5b213a
CW		 4086 drm_encoder_cleanup(encoder);
4087 kfree(intel_encoder);
7e7d76c3
JB		 4088}
4089
9237329d 4090/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4091 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4092 * state of the entire output pipe. */
9237329d 4093static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4094{
5ab432ef
DV		 4095 if (mode == DRM_MODE_DPMS_ON) {
4096 encoder->connectors_active = true;
4097
b2cabb0e 4098 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4099 } else {
4100 encoder->connectors_active = false;
4101
b2cabb0e 4102 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4103 }
79e53945
JB		 4104}
4105
0a91ca29
DV		 4106/* Cross check the actual hw state with our own modeset state tracking (and it's
4107 * internal consistency). */
b980514c 4108static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4109{
0a91ca29
DV		 4110 if (connector->get_hw_state(connector)) {
4111 struct intel_encoder *encoder = connector->encoder;
4112 struct drm_crtc *crtc;
4113 bool encoder_enabled;
4114 enum pipe pipe;
4115
4116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4117 connector->base.base.id,
4118 drm_get_connector_name(&connector->base));
4119
4120 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4121 "wrong connector dpms state\n");
4122 WARN(connector->base.encoder != &encoder->base,
4123 "active connector not linked to encoder\n");
4124 WARN(!encoder->connectors_active,
4125 "encoder->connectors_active not set\n");
4126
4127 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4128 WARN(!encoder_enabled, "encoder not enabled\n");
4129 if (WARN_ON(!encoder->base.crtc))
4130 return;
4131
4132 crtc = encoder->base.crtc;
4133
4134 WARN(!crtc->enabled, "crtc not enabled\n");
4135 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4136 WARN(pipe != to_intel_crtc(crtc)->pipe,
4137 "encoder active on the wrong pipe\n");
4138 }
79e53945
JB		 4139}
4140
5ab432ef
DV		 4141/* Even simpler default implementation, if there's really no special case to
4142 * consider. */
4143void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4144{
5ab432ef 4145 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4146
5ab432ef
DV		 4147 /* All the simple cases only support two dpms states. */
4148 if (mode != DRM_MODE_DPMS_ON)
4149 mode = DRM_MODE_DPMS_OFF;
d4270e57 4150
5ab432ef
DV		 4151 if (mode == connector->dpms)
4152 return;
4153
4154 connector->dpms = mode;
4155
4156 /* Only need to change hw state when actually enabled */
4157 if (encoder->base.crtc)
4158 intel_encoder_dpms(encoder, mode);
4159 else
8af6cf88 4160 WARN_ON(encoder->connectors_active != false);
0a91ca29 4161
b980514c 4162 intel_modeset_check_state(connector->dev);
79e53945
JB		 4163}
4164
f0947c37
DV		 4165/* Simple connector->get_hw_state implementation for encoders that support only
4166 * one connector and no cloning and hence the encoder state determines the state
4167 * of the connector. */
4168bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4169{
24929352 4170 enum pipe pipe = 0;
f0947c37 4171 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4172
f0947c37 4173 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4174}
4175
1857e1da
DV		 4176static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4177 struct intel_crtc_config *pipe_config)
4178{
4179 struct drm_i915_private *dev_priv = dev->dev_private;
4180 struct intel_crtc *pipe_B_crtc =
4181 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4182
4183 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4184 pipe_name(pipe), pipe_config->fdi_lanes);
4185 if (pipe_config->fdi_lanes > 4) {
4186 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4187 pipe_name(pipe), pipe_config->fdi_lanes);
4188 return false;
4189 }
4190
4191 if (IS_HASWELL(dev)) {
4192 if (pipe_config->fdi_lanes > 2) {
4193 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4194 pipe_config->fdi_lanes);
4195 return false;
4196 } else {
4197 return true;
4198 }
4199 }
4200
4201 if (INTEL_INFO(dev)->num_pipes == 2)
4202 return true;
4203
4204 /* Ivybridge 3 pipe is really complicated */
4205 switch (pipe) {
4206 case PIPE_A:
4207 return true;
4208 case PIPE_B:
4209 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4210 pipe_config->fdi_lanes > 2) {
4211 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4212 pipe_name(pipe), pipe_config->fdi_lanes);
4213 return false;
4214 }
4215 return true;
4216 case PIPE_C:
1e833f40 4217 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4218 pipe_B_crtc->config.fdi_lanes <= 2) {
4219 if (pipe_config->fdi_lanes > 2) {
4220 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4221 pipe_name(pipe), pipe_config->fdi_lanes);
4222 return false;
4223 }
4224 } else {
4225 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4226 return false;
4227 }
4228 return true;
4229 default:
4230 BUG();
4231 }
4232}
4233
e29c22c0
DV		 4234#define RETRY 1
4235static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4236 struct intel_crtc_config *pipe_config)
877d48d5 4237{
1857e1da 4238 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4239 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4240 int lane, link_bw, fdi_dotclock;
e29c22c0 4241 bool setup_ok, needs_recompute = false;
877d48d5 4242
e29c22c0 4243retry:
877d48d5
DV		 4244 /* FDI is a binary signal running at ~2.7GHz, encoding
4245 * each output octet as 10 bits. The actual frequency
4246 * is stored as a divider into a 100MHz clock, and the
4247 * mode pixel clock is stored in units of 1KHz.
4248 * Hence the bw of each lane in terms of the mode signal
4249 * is:
4250 */
4251 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4252
241bfc38 4253 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4254
2bd89a07 4255 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4256 pipe_config->pipe_bpp);
4257
4258 pipe_config->fdi_lanes = lane;
4259
2bd89a07 4260 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4261 link_bw, &pipe_config->fdi_m_n);
1857e1da 4262
e29c22c0
DV		 4263 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4264 intel_crtc->pipe, pipe_config);
4265 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4266 pipe_config->pipe_bpp -= 2*3;
4267 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4268 pipe_config->pipe_bpp);
4269 needs_recompute = true;
4270 pipe_config->bw_constrained = true;
4271
4272 goto retry;
4273 }
4274
4275 if (needs_recompute)
4276 return RETRY;
4277
4278 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4279}
4280
42db64ef
PZ		 4281static void hsw_compute_ips_config(struct intel_crtc *crtc,
4282 struct intel_crtc_config *pipe_config)
4283{
3c4ca58c
PZ		 4284 pipe_config->ips_enabled = i915_enable_ips &&
4285 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4286 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4287}
4288
a43f6e0f 4289static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4290 struct intel_crtc_config *pipe_config)
79e53945 4291{
a43f6e0f 4292 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4293 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4294
ad3a4479 4295 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4296 if (INTEL_INFO(dev)->gen < 4) {
4297 struct drm_i915_private *dev_priv = dev->dev_private;
4298 int clock_limit =
4299 dev_priv->display.get_display_clock_speed(dev);
4300
4301 /*
4302 * Enable pixel doubling when the dot clock
4303 * is > 90% of the (display) core speed.
4304 *
b397c96b
VS		 4305 * GDG double wide on either pipe,
4306 * otherwise pipe A only.
cf532bb2 4307 */
b397c96b 4308 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4309 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4310 clock_limit *= 2;
cf532bb2 4311 pipe_config->double_wide = true;
ad3a4479
VS		 4312 }
4313
241bfc38 4314 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4315 return -EINVAL;
2c07245f 4316 }
89749350 4317
1d1d0e27
VS		 4318 /*
4319 * Pipe horizontal size must be even in:
4320 * - DVO ganged mode
4321 * - LVDS dual channel mode
4322 * - Double wide pipe
4323 */
4324 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4325 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4326 pipe_config->pipe_src_w &= ~1;
4327
8693a824
DL		 4328 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4329 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4330 */
4331 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4332 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4333 return -EINVAL;
44f46b42 4334
bd080ee5 4335 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4336 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4337 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4338 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4339 * for lvds. */
4340 pipe_config->pipe_bpp = 8*3;
4341 }
4342
f5adf94e 4343 if (HAS_IPS(dev))
a43f6e0f
DV		 4344 hsw_compute_ips_config(crtc, pipe_config);
4345
4346 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4347 * clock survives for now. */
4348 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4349 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4350
877d48d5 4351 if (pipe_config->has_pch_encoder)
a43f6e0f 4352 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4353
e29c22c0 4354 return 0;
79e53945
JB		 4355}
4356
25eb05fc
JB		 4357static int valleyview_get_display_clock_speed(struct drm_device *dev)
4358{
4359 return 400000; /* FIXME */
4360}
4361
e70236a8
JB		 4362static int i945_get_display_clock_speed(struct drm_device *dev)
4363{
4364 return 400000;
4365}
79e53945 4366
e70236a8 4367static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4368{
e70236a8
JB		 4369 return 333000;
4370}
79e53945 4371
e70236a8
JB		 4372static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4373{
4374 return 200000;
4375}
79e53945 4376
257a7ffc
DV		 4377static int pnv_get_display_clock_speed(struct drm_device *dev)
4378{
4379 u16 gcfgc = 0;
4380
4381 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4382
4383 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4384 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4385 return 267000;
4386 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4387 return 333000;
4388 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4389 return 444000;
4390 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4391 return 200000;
4392 default:
4393 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4394 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4395 return 133000;
4396 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4397 return 167000;
4398 }
4399}
4400
e70236a8
JB		 4401static int i915gm_get_display_clock_speed(struct drm_device *dev)
4402{
4403 u16 gcfgc = 0;
79e53945 4404
e70236a8
JB		 4405 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4406
4407 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4408 return 133000;
4409 else {
4410 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4411 case GC_DISPLAY_CLOCK_333_MHZ:
4412 return 333000;
4413 default:
4414 case GC_DISPLAY_CLOCK_190_200_MHZ:
4415 return 190000;
79e53945 4416 }
e70236a8
JB		 4417 }
4418}
4419
4420static int i865_get_display_clock_speed(struct drm_device *dev)
4421{
4422 return 266000;
4423}
4424
4425static int i855_get_display_clock_speed(struct drm_device *dev)
4426{
4427 u16 hpllcc = 0;
4428 /* Assume that the hardware is in the high speed state. This
4429 * should be the default.
4430 */
4431 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4432 case GC_CLOCK_133_200:
4433 case GC_CLOCK_100_200:
4434 return 200000;
4435 case GC_CLOCK_166_250:
4436 return 250000;
4437 case GC_CLOCK_100_133:
79e53945 4438 return 133000;
e70236a8 4439 }
79e53945 4440
e70236a8
JB		 4441 /* Shouldn't happen */
4442 return 0;
4443}
79e53945 4444
e70236a8
JB		 4445static int i830_get_display_clock_speed(struct drm_device *dev)
4446{
4447 return 133000;
79e53945
JB		 4448}
4449
2c07245f 4450static void
a65851af 4451intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4452{
a65851af
VS		 4453 while (*num > DATA_LINK_M_N_MASK ||
4454 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4455 *num >>= 1;
4456 *den >>= 1;
4457 }
4458}
4459
a65851af
VS		 4460static void compute_m_n(unsigned int m, unsigned int n,
4461 uint32_t *ret_m, uint32_t *ret_n)
4462{
4463 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4464 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4465 intel_reduce_m_n_ratio(ret_m, ret_n);
4466}
4467
e69d0bc1
DV		 4468void
4469intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4470 int pixel_clock, int link_clock,
4471 struct intel_link_m_n *m_n)
2c07245f 4472{
e69d0bc1 4473 m_n->tu = 64;
a65851af
VS		 4474
4475 compute_m_n(bits_per_pixel * pixel_clock,
4476 link_clock * nlanes * 8,
4477 &m_n->gmch_m, &m_n->gmch_n);
4478
4479 compute_m_n(pixel_clock, link_clock,
4480 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4481}
4482
a7615030
CW		 4483static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4484{
72bbe58c
KP		 4485 if (i915_panel_use_ssc >= 0)
4486 return i915_panel_use_ssc != 0;
41aa3448 4487 return dev_priv->vbt.lvds_use_ssc
435793df 4488 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4489}
4490
c65d77d8
JB		 4491static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4492{
4493 struct drm_device *dev = crtc->dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 int refclk;
4496
a0c4da24 4497 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4498 refclk = 100000;
a0c4da24 4499 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4500 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4501 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4502 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4503 refclk / 1000);
4504 } else if (!IS_GEN2(dev)) {
4505 refclk = 96000;
4506 } else {
4507 refclk = 48000;
4508 }
4509
4510 return refclk;
4511}
4512
7429e9d4 4513static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4514{
7df00d7a 4515 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4516}
f47709a9 4517
7429e9d4
DV		 4518static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4519{
4520 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4521}
4522
f47709a9 4523static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4524 intel_clock_t *reduced_clock)
4525{
f47709a9 4526 struct drm_device *dev = crtc->base.dev;
a7516a05 4527 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4528 int pipe = crtc->pipe;
a7516a05
JB		 4529 u32 fp, fp2 = 0;
4530
4531 if (IS_PINEVIEW(dev)) {
7429e9d4 4532 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4533 if (reduced_clock)
7429e9d4 4534 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4535 } else {
7429e9d4 4536 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4537 if (reduced_clock)
7429e9d4 4538 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4539 }
4540
4541 I915_WRITE(FP0(pipe), fp);
8bcc2795 4542 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4543
f47709a9
DV		 4544 crtc->lowfreq_avail = false;
4545 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4546 reduced_clock && i915_powersave) {
4547 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4548 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4549 crtc->lowfreq_avail = true;
a7516a05
JB		 4550 } else {
4551 I915_WRITE(FP1(pipe), fp);
8bcc2795 4552 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4553 }
4554}
4555
5e69f97f
CML		 4556static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4557 pipe)
89b667f8
JB		 4558{
4559 u32 reg_val;
4560
4561 /*
4562 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4563 * and set it to a reasonable value instead.
4564 */
5e69f97f 4565 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4566 reg_val &= 0xffffff00;
4567 reg_val |= 0x00000030;
5e69f97f 4568 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4569
5e69f97f 4570 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4571 reg_val &= 0x8cffffff;
4572 reg_val = 0x8c000000;
5e69f97f 4573 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4574
5e69f97f 4575 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4576 reg_val &= 0xffffff00;
5e69f97f 4577 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4578
5e69f97f 4579 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4580 reg_val &= 0x00ffffff;
4581 reg_val |= 0xb0000000;
5e69f97f 4582 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4583}
4584
b551842d
DV		 4585static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4586 struct intel_link_m_n *m_n)
4587{
4588 struct drm_device *dev = crtc->base.dev;
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 int pipe = crtc->pipe;
4591
e3b95f1e
DV		 4592 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4593 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4594 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4595 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4596}
4597
4598static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4599 struct intel_link_m_n *m_n)
4600{
4601 struct drm_device *dev = crtc->base.dev;
4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 int pipe = crtc->pipe;
4604 enum transcoder transcoder = crtc->config.cpu_transcoder;
4605
4606 if (INTEL_INFO(dev)->gen >= 5) {
4607 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4608 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4609 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4610 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4611 } else {
e3b95f1e
DV		 4612 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4613 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4614 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4615 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4616 }
4617}
4618
03afc4a2
DV		 4619static void intel_dp_set_m_n(struct intel_crtc *crtc)
4620{
4621 if (crtc->config.has_pch_encoder)
4622 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4623 else
4624 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4625}
4626
f47709a9 4627static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4628{
f47709a9 4629 struct drm_device *dev = crtc->base.dev;
a0c4da24 4630 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4631 int pipe = crtc->pipe;
89b667f8 4632 u32 dpll, mdiv;
a0c4da24 4633 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4634 u32 coreclk, reg_val, dpll_md;
a0c4da24 4635
09153000
DV		 4636 mutex_lock(&dev_priv->dpio_lock);
4637
f47709a9
DV		 4638 bestn = crtc->config.dpll.n;
4639 bestm1 = crtc->config.dpll.m1;
4640 bestm2 = crtc->config.dpll.m2;
4641 bestp1 = crtc->config.dpll.p1;
4642 bestp2 = crtc->config.dpll.p2;
a0c4da24 4643
89b667f8
JB		 4644 /* See eDP HDMI DPIO driver vbios notes doc */
4645
4646 /* PLL B needs special handling */
4647 if (pipe)
5e69f97f 4648 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4649
4650 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4651 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4652
4653 /* Disable target IRef on PLL */
5e69f97f 4654 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4655 reg_val &= 0x00ffffff;
5e69f97f 4656 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4657
4658 /* Disable fast lock */
5e69f97f 4659 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4660
4661 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4662 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4663 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4664 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4665 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4666
4667 /*
4668 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4669 * but we don't support that).
4670 * Note: don't use the DAC post divider as it seems unstable.
4671 */
4672 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4673 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4674
a0c4da24 4675 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4676 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4677
89b667f8 4678 /* Set HBR and RBR LPF coefficients */
ff9a6750 4679 if (crtc->config.port_clock == 162000 ||
99750bd4 4680 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4681 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4682 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4683 0x009f0003);
89b667f8 4684 else
5e69f97f 4685 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4686 0x00d0000f);
4687
4688 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4689 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4690 /* Use SSC source */
4691 if (!pipe)
5e69f97f 4692 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4693 0x0df40000);
4694 else
5e69f97f 4695 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4696 0x0df70000);
4697 } else { /* HDMI or VGA */
4698 /* Use bend source */
4699 if (!pipe)
5e69f97f 4700 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4701 0x0df70000);
4702 else
5e69f97f 4703 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4704 0x0df40000);
4705 }
a0c4da24 4706
5e69f97f 4707 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4708 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4709 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4710 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4711 coreclk |= 0x01000000;
5e69f97f 4712 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4713
5e69f97f 4714 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4715
89b667f8
JB		 4716 /* Enable DPIO clock input */
4717 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4718 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4719 /* We should never disable this, set it here for state tracking */
4720 if (pipe == PIPE_B)
89b667f8 4721 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4722 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4723 crtc->config.dpll_hw_state.dpll = dpll;
4724
ef1b460d
DV		 4725 dpll_md = (crtc->config.pixel_multiplier - 1)
4726 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4727 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4728
89b667f8
JB		 4729 if (crtc->config.has_dp_encoder)
4730 intel_dp_set_m_n(crtc);
09153000
DV		 4731
4732 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4733}
4734
f47709a9
DV		 4735static void i9xx_update_pll(struct intel_crtc *crtc,
4736 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4737 int num_connectors)
4738{
f47709a9 4739 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4740 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4741 u32 dpll;
4742 bool is_sdvo;
f47709a9 4743 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4744
f47709a9 4745 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4746
f47709a9
DV		 4747 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4748 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4749
4750 dpll = DPLL_VGA_MODE_DIS;
4751
f47709a9 4752 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4753 dpll |= DPLLB_MODE_LVDS;
4754 else
4755 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4756
ef1b460d 4757 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4758 dpll |= (crtc->config.pixel_multiplier - 1)
4759 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4760 }
198a037f
DV		 4761
4762 if (is_sdvo)
4a33e48d 4763 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4764
f47709a9 4765 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4766 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4767
4768 /* compute bitmask from p1 value */
4769 if (IS_PINEVIEW(dev))
4770 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4771 else {
4772 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4773 if (IS_G4X(dev) && reduced_clock)
4774 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4775 }
4776 switch (clock->p2) {
4777 case 5:
4778 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4779 break;
4780 case 7:
4781 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4782 break;
4783 case 10:
4784 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4785 break;
4786 case 14:
4787 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4788 break;
4789 }
4790 if (INTEL_INFO(dev)->gen >= 4)
4791 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4792
09ede541 4793 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4794 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4795 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4796 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4797 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4798 else
4799 dpll |= PLL_REF_INPUT_DREFCLK;
4800
4801 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4802 crtc->config.dpll_hw_state.dpll = dpll;
4803
eb1cbe48 4804 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4805 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4806 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4807 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4808 }
66e3d5c0
DV		 4809
4810 if (crtc->config.has_dp_encoder)
4811 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4812}
4813
f47709a9 4814static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4815 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4816 int num_connectors)
4817{
f47709a9 4818 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4819 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4820 u32 dpll;
f47709a9 4821 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4822
f47709a9 4823 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4824
eb1cbe48
DV		 4825 dpll = DPLL_VGA_MODE_DIS;
4826
f47709a9 4827 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4828 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4829 } else {
4830 if (clock->p1 == 2)
4831 dpll |= PLL_P1_DIVIDE_BY_TWO;
4832 else
4833 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4834 if (clock->p2 == 4)
4835 dpll |= PLL_P2_DIVIDE_BY_4;
4836 }
4837
4a33e48d
DV		 4838 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4839 dpll |= DPLL_DVO_2X_MODE;
4840
f47709a9 4841 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4842 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4843 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4844 else
4845 dpll |= PLL_REF_INPUT_DREFCLK;
4846
4847 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4848 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4849}
4850
8a654f3b 4851static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4852{
4853 struct drm_device *dev = intel_crtc->base.dev;
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4856 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4857 struct drm_display_mode *adjusted_mode =
4858 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4859 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4860
4861 /* We need to be careful not to changed the adjusted mode, for otherwise
4862 * the hw state checker will get angry at the mismatch. */
4863 crtc_vtotal = adjusted_mode->crtc_vtotal;
4864 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4865
4866 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4867 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4868 crtc_vtotal -= 1;
4869 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4870 vsyncshift = adjusted_mode->crtc_hsync_start
4871 - adjusted_mode->crtc_htotal / 2;
4872 } else {
4873 vsyncshift = 0;
4874 }
4875
4876 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4877 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4878
fe2b8f9d 4879 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4880 (adjusted_mode->crtc_hdisplay - 1) |
4881 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4882 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4883 (adjusted_mode->crtc_hblank_start - 1) |
4884 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4885 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4886 (adjusted_mode->crtc_hsync_start - 1) |
4887 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4888
fe2b8f9d 4889 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4890 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4891 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4892 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4893 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4894 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4895 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4896 (adjusted_mode->crtc_vsync_start - 1) |
4897 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4898
b5e508d4
PZ		 4899 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4900 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4901 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4902 * bits. */
4903 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4904 (pipe == PIPE_B || pipe == PIPE_C))
4905 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4906
b0e77b9c
PZ		 4907 /* pipesrc controls the size that is scaled from, which should
4908 * always be the user's requested size.
4909 */
4910 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4911 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4912 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4913}
4914
1bd1bd80
DV		 4915static void intel_get_pipe_timings(struct intel_crtc *crtc,
4916 struct intel_crtc_config *pipe_config)
4917{
4918 struct drm_device *dev = crtc->base.dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4921 uint32_t tmp;
4922
4923 tmp = I915_READ(HTOTAL(cpu_transcoder));
4924 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4925 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4926 tmp = I915_READ(HBLANK(cpu_transcoder));
4927 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4928 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4929 tmp = I915_READ(HSYNC(cpu_transcoder));
4930 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4931 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4932
4933 tmp = I915_READ(VTOTAL(cpu_transcoder));
4934 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4935 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4936 tmp = I915_READ(VBLANK(cpu_transcoder));
4937 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4938 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4939 tmp = I915_READ(VSYNC(cpu_transcoder));
4940 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4941 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4942
4943 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4944 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4945 pipe_config->adjusted_mode.crtc_vtotal += 1;
4946 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4947 }
4948
4949 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4950 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4951 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4952
4953 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4954 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4955}
4956
babea61d
JB		 4957static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4958 struct intel_crtc_config *pipe_config)
4959{
4960 struct drm_crtc *crtc = &intel_crtc->base;
4961
4962 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4963 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4964 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4965 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4966
4967 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4968 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4969 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4970 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4971
4972 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4973
241bfc38 4974 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4975 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4976}
4977
84b046f3
DV		 4978static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4979{
4980 struct drm_device *dev = intel_crtc->base.dev;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 uint32_t pipeconf;
4983
9f11a9e4 4984 pipeconf = 0;
84b046f3 4985
67c72a12
DV		 4986 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4987 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4988 pipeconf |= PIPECONF_ENABLE;
4989
cf532bb2
VS		 4990 if (intel_crtc->config.double_wide)
4991 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4992
ff9ce46e
DV		 4993 /* only g4x and later have fancy bpc/dither controls */
4994 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4995 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4996 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4997 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4998 PIPECONF_DITHER_TYPE_SP;
84b046f3 4999
ff9ce46e
DV		 5000 switch (intel_crtc->config.pipe_bpp) {
5001 case 18:
5002 pipeconf |= PIPECONF_6BPC;
5003 break;
5004 case 24:
5005 pipeconf |= PIPECONF_8BPC;
5006 break;
5007 case 30:
5008 pipeconf |= PIPECONF_10BPC;
5009 break;
5010 default:
5011 /* Case prevented by intel_choose_pipe_bpp_dither. */
5012 BUG();
84b046f3
DV		 5013 }
5014 }
5015
5016 if (HAS_PIPE_CXSR(dev)) {
5017 if (intel_crtc->lowfreq_avail) {
5018 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5019 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5020 } else {
5021 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5022 }
5023 }
5024
84b046f3
DV		 5025 if (!IS_GEN2(dev) &&
5026 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5027 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5028 else
5029 pipeconf |= PIPECONF_PROGRESSIVE;
5030
9f11a9e4
DV		 5031 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5032 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5033
84b046f3
DV		 5034 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5035 POSTING_READ(PIPECONF(intel_crtc->pipe));
5036}
5037
f564048e 5038static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5039 int x, int y,
94352cf9 5040 struct drm_framebuffer *fb)
79e53945
JB		 5041{
5042 struct drm_device *dev = crtc->dev;
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5045 int pipe = intel_crtc->pipe;
80824003 5046 int plane = intel_crtc->plane;
c751ce4f 5047 int refclk, num_connectors = 0;
652c393a 5048 intel_clock_t clock, reduced_clock;
84b046f3 5049 u32 dspcntr;
a16af721 5050 bool ok, has_reduced_clock = false;
e9fd1c02 5051 bool is_lvds = false, is_dsi = false;
5eddb70b 5052 struct intel_encoder *encoder;
d4906093 5053 const intel_limit_t *limit;
5c3b82e2 5054 int ret;
79e53945 5055
6c2b7c12 5056 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5057 switch (encoder->type) {
79e53945
JB		 5058 case INTEL_OUTPUT_LVDS:
5059 is_lvds = true;
5060 break;
e9fd1c02
JN		 5061 case INTEL_OUTPUT_DSI:
5062 is_dsi = true;
5063 break;
79e53945 5064 }
43565a06 5065
c751ce4f 5066 num_connectors++;
79e53945
JB		 5067 }
5068
f2335330
JN		 5069 if (is_dsi)
5070 goto skip_dpll;
5071
5072 if (!intel_crtc->config.clock_set) {
5073 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5074
e9fd1c02
JN		 5075 /*
5076 * Returns a set of divisors for the desired target clock with
5077 * the given refclk, or FALSE. The returned values represent
5078 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5079 * 2) / p1 / p2.
5080 */
5081 limit = intel_limit(crtc, refclk);
5082 ok = dev_priv->display.find_dpll(limit, crtc,
5083 intel_crtc->config.port_clock,
5084 refclk, NULL, &clock);
f2335330 5085 if (!ok) {
e9fd1c02
JN		 5086 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5087 return -EINVAL;
5088 }
79e53945 5089
f2335330
JN		 5090 if (is_lvds && dev_priv->lvds_downclock_avail) {
5091 /*
5092 * Ensure we match the reduced clock's P to the target
5093 * clock. If the clocks don't match, we can't switch
5094 * the display clock by using the FP0/FP1. In such case
5095 * we will disable the LVDS downclock feature.
5096 */
5097 has_reduced_clock =
5098 dev_priv->display.find_dpll(limit, crtc,
5099 dev_priv->lvds_downclock,
5100 refclk, &clock,
5101 &reduced_clock);
5102 }
5103 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5104 intel_crtc->config.dpll.n = clock.n;
5105 intel_crtc->config.dpll.m1 = clock.m1;
5106 intel_crtc->config.dpll.m2 = clock.m2;
5107 intel_crtc->config.dpll.p1 = clock.p1;
5108 intel_crtc->config.dpll.p2 = clock.p2;
5109 }
7026d4ac 5110
e9fd1c02 5111 if (IS_GEN2(dev)) {
8a654f3b 5112 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5113 has_reduced_clock ? &reduced_clock : NULL,
5114 num_connectors);
e9fd1c02 5115 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5116 vlv_update_pll(intel_crtc);
e9fd1c02 5117 } else {
f47709a9 5118 i9xx_update_pll(intel_crtc,
eb1cbe48 5119 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5120 num_connectors);
e9fd1c02 5121 }
79e53945 5122
f2335330 5123skip_dpll:
79e53945
JB		 5124 /* Set up the display plane register */
5125 dspcntr = DISPPLANE_GAMMA_ENABLE;
5126
da6ecc5d
JB		 5127 if (!IS_VALLEYVIEW(dev)) {
5128 if (pipe == 0)
5129 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5130 else
5131 dspcntr |= DISPPLANE_SEL_PIPE_B;
5132 }
79e53945 5133
8a654f3b 5134 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5135
5136 /* pipesrc and dspsize control the size that is scaled from,
5137 * which should always be the user's requested size.
79e53945 5138 */
929c77fb 5139 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5140 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5141 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5142 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5143
84b046f3
DV		 5144 i9xx_set_pipeconf(intel_crtc);
5145
f564048e
EA		 5146 I915_WRITE(DSPCNTR(plane), dspcntr);
5147 POSTING_READ(DSPCNTR(plane));
5148
94352cf9 5149 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5150
f564048e
EA		 5151 return ret;
5152}
5153
2fa2fe9a
DV		 5154static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5155 struct intel_crtc_config *pipe_config)
5156{
5157 struct drm_device *dev = crtc->base.dev;
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5159 uint32_t tmp;
5160
5161 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5162 if (!(tmp & PFIT_ENABLE))
5163 return;
2fa2fe9a 5164
06922821 5165 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5166 if (INTEL_INFO(dev)->gen < 4) {
5167 if (crtc->pipe != PIPE_B)
5168 return;
2fa2fe9a
DV		 5169 } else {
5170 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5171 return;
5172 }
5173
06922821 5174 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5175 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5176 if (INTEL_INFO(dev)->gen < 5)
5177 pipe_config->gmch_pfit.lvds_border_bits =
5178 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5179}
5180
acbec814
JB		 5181static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5182 struct intel_crtc_config *pipe_config)
5183{
5184 struct drm_device *dev = crtc->base.dev;
5185 struct drm_i915_private *dev_priv = dev->dev_private;
5186 int pipe = pipe_config->cpu_transcoder;
5187 intel_clock_t clock;
5188 u32 mdiv;
662c6ecb 5189 int refclk = 100000;
acbec814
JB		 5190
5191 mutex_lock(&dev_priv->dpio_lock);
5192 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5193 mutex_unlock(&dev_priv->dpio_lock);
5194
5195 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5196 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5197 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5198 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5199 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5200
662c6ecb
CW		 5201 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5202 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5203
5204 pipe_config->port_clock = clock.dot / 10;
5205}
5206
0e8ffe1b
DV		 5207static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5208 struct intel_crtc_config *pipe_config)
5209{
5210 struct drm_device *dev = crtc->base.dev;
5211 struct drm_i915_private *dev_priv = dev->dev_private;
5212 uint32_t tmp;
5213
e143a21c 5214 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5215 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5216
0e8ffe1b
DV		 5217 tmp = I915_READ(PIPECONF(crtc->pipe));
5218 if (!(tmp & PIPECONF_ENABLE))
5219 return false;
5220
42571aef
VS		 5221 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5222 switch (tmp & PIPECONF_BPC_MASK) {
5223 case PIPECONF_6BPC:
5224 pipe_config->pipe_bpp = 18;
5225 break;
5226 case PIPECONF_8BPC:
5227 pipe_config->pipe_bpp = 24;
5228 break;
5229 case PIPECONF_10BPC:
5230 pipe_config->pipe_bpp = 30;
5231 break;
5232 default:
5233 break;
5234 }
5235 }
5236
282740f7
VS		 5237 if (INTEL_INFO(dev)->gen < 4)
5238 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5239
1bd1bd80
DV		 5240 intel_get_pipe_timings(crtc, pipe_config);
5241
2fa2fe9a
DV		 5242 i9xx_get_pfit_config(crtc, pipe_config);
5243
6c49f241
DV		 5244 if (INTEL_INFO(dev)->gen >= 4) {
5245 tmp = I915_READ(DPLL_MD(crtc->pipe));
5246 pipe_config->pixel_multiplier =
5247 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5248 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5249 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5250 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5251 tmp = I915_READ(DPLL(crtc->pipe));
5252 pipe_config->pixel_multiplier =
5253 ((tmp & SDVO_MULTIPLIER_MASK)
5254 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5255 } else {
5256 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5257 * port and will be fixed up in the encoder->get_config
5258 * function. */
5259 pipe_config->pixel_multiplier = 1;
5260 }
8bcc2795
DV		 5261 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5262 if (!IS_VALLEYVIEW(dev)) {
5263 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5264 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5265 } else {
5266 /* Mask out read-only status bits. */
5267 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5268 DPLL_PORTC_READY_MASK |
5269 DPLL_PORTB_READY_MASK);
8bcc2795 5270 }
6c49f241 5271
acbec814
JB		 5272 if (IS_VALLEYVIEW(dev))
5273 vlv_crtc_clock_get(crtc, pipe_config);
5274 else
5275 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5276
0e8ffe1b
DV		 5277 return true;
5278}
5279
dde86e2d 5280static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5281{
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5284 struct intel_encoder *encoder;
74cfd7ac 5285 u32 val, final;
13d83a67 5286 bool has_lvds = false;
199e5d79 5287 bool has_cpu_edp = false;
199e5d79 5288 bool has_panel = false;
99eb6a01
KP		 5289 bool has_ck505 = false;
5290 bool can_ssc = false;
13d83a67
JB		 5291
5292 /* We need to take the global config into account */
199e5d79
KP		 5293 list_for_each_entry(encoder, &mode_config->encoder_list,
5294 base.head) {
5295 switch (encoder->type) {
5296 case INTEL_OUTPUT_LVDS:
5297 has_panel = true;
5298 has_lvds = true;
5299 break;
5300 case INTEL_OUTPUT_EDP:
5301 has_panel = true;
2de6905f 5302 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5303 has_cpu_edp = true;
5304 break;
13d83a67
JB		 5305 }
5306 }
5307
99eb6a01 5308 if (HAS_PCH_IBX(dev)) {
41aa3448 5309 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5310 can_ssc = has_ck505;
5311 } else {
5312 has_ck505 = false;
5313 can_ssc = true;
5314 }
5315
2de6905f
ID		 5316 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5317 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5318
5319 /* Ironlake: try to setup display ref clock before DPLL
5320 * enabling. This is only under driver's control after
5321 * PCH B stepping, previous chipset stepping should be
5322 * ignoring this setting.
5323 */
74cfd7ac
CW		 5324 val = I915_READ(PCH_DREF_CONTROL);
5325
5326 /* As we must carefully and slowly disable/enable each source in turn,
5327 * compute the final state we want first and check if we need to
5328 * make any changes at all.
5329 */
5330 final = val;
5331 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5332 if (has_ck505)
5333 final |= DREF_NONSPREAD_CK505_ENABLE;
5334 else
5335 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5336
5337 final &= ~DREF_SSC_SOURCE_MASK;
5338 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5339 final &= ~DREF_SSC1_ENABLE;
5340
5341 if (has_panel) {
5342 final |= DREF_SSC_SOURCE_ENABLE;
5343
5344 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5345 final |= DREF_SSC1_ENABLE;
5346
5347 if (has_cpu_edp) {
5348 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5349 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5350 else
5351 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5352 } else
5353 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5354 } else {
5355 final |= DREF_SSC_SOURCE_DISABLE;
5356 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5357 }
5358
5359 if (final == val)
5360 return;
5361
13d83a67 5362 /* Always enable nonspread source */
74cfd7ac 5363 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5364
99eb6a01 5365 if (has_ck505)
74cfd7ac 5366 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5367 else
74cfd7ac 5368 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5369
199e5d79 5370 if (has_panel) {
74cfd7ac
CW		 5371 val &= ~DREF_SSC_SOURCE_MASK;
5372 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5373
199e5d79 5374 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5375 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5376 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5377 val |= DREF_SSC1_ENABLE;
e77166b5 5378 } else
74cfd7ac 5379 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5380
5381 /* Get SSC going before enabling the outputs */
74cfd7ac 5382 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5383 POSTING_READ(PCH_DREF_CONTROL);
5384 udelay(200);
5385
74cfd7ac 5386 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5387
5388 /* Enable CPU source on CPU attached eDP */
199e5d79 5389 if (has_cpu_edp) {
99eb6a01 5390 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5391 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5392 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5393 }
13d83a67 5394 else
74cfd7ac 5395 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5396 } else
74cfd7ac 5397 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5398
74cfd7ac 5399 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5400 POSTING_READ(PCH_DREF_CONTROL);
5401 udelay(200);
5402 } else {
5403 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5404
74cfd7ac 5405 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5406
5407 /* Turn off CPU output */
74cfd7ac 5408 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5409
74cfd7ac 5410 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5411 POSTING_READ(PCH_DREF_CONTROL);
5412 udelay(200);
5413
5414 /* Turn off the SSC source */
74cfd7ac
CW		 5415 val &= ~DREF_SSC_SOURCE_MASK;
5416 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5417
5418 /* Turn off SSC1 */
74cfd7ac 5419 val &= ~DREF_SSC1_ENABLE;
199e5d79 5420
74cfd7ac 5421 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5422 POSTING_READ(PCH_DREF_CONTROL);
5423 udelay(200);
5424 }
74cfd7ac
CW		 5425
5426 BUG_ON(val != final);
13d83a67
JB		 5427}
5428
f31f2d55 5429static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5430{
f31f2d55 5431 uint32_t tmp;
dde86e2d 5432
0ff066a9
PZ		 5433 tmp = I915_READ(SOUTH_CHICKEN2);
5434 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5435 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5436
0ff066a9
PZ		 5437 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5438 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5439 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5440
0ff066a9
PZ		 5441 tmp = I915_READ(SOUTH_CHICKEN2);
5442 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5443 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5444
0ff066a9
PZ		 5445 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5446 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5447 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5448}
5449
5450/* WaMPhyProgramming:hsw */
5451static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5452{
5453 uint32_t tmp;
dde86e2d
PZ		 5454
5455 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5456 tmp &= ~(0xFF << 24);
5457 tmp |= (0x12 << 24);
5458 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5459
dde86e2d
PZ		 5460 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5461 tmp |= (1 << 11);
5462 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5463
5464 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5465 tmp |= (1 << 11);
5466 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5467
dde86e2d
PZ		 5468 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5469 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5470 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5471
5472 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5473 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5474 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5475
0ff066a9
PZ		 5476 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5477 tmp &= ~(7 << 13);
5478 tmp |= (5 << 13);
5479 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5480
0ff066a9
PZ		 5481 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5482 tmp &= ~(7 << 13);
5483 tmp |= (5 << 13);
5484 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5485
5486 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5487 tmp &= ~0xFF;
5488 tmp |= 0x1C;
5489 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5490
5491 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5492 tmp &= ~0xFF;
5493 tmp |= 0x1C;
5494 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5495
5496 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5497 tmp &= ~(0xFF << 16);
5498 tmp |= (0x1C << 16);
5499 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5500
5501 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5502 tmp &= ~(0xFF << 16);
5503 tmp |= (0x1C << 16);
5504 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5505
0ff066a9
PZ		 5506 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5507 tmp |= (1 << 27);
5508 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5509
0ff066a9
PZ		 5510 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5511 tmp |= (1 << 27);
5512 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5513
0ff066a9
PZ		 5514 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5515 tmp &= ~(0xF << 28);
5516 tmp |= (4 << 28);
5517 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5518
0ff066a9
PZ		 5519 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5520 tmp &= ~(0xF << 28);
5521 tmp |= (4 << 28);
5522 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5523}
5524
2fa86a1f
PZ		 5525/* Implements 3 different sequences from BSpec chapter "Display iCLK
5526 * Programming" based on the parameters passed:
5527 * - Sequence to enable CLKOUT_DP
5528 * - Sequence to enable CLKOUT_DP without spread
5529 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5530 */
5531static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5532 bool with_fdi)
f31f2d55
PZ		 5533{
5534 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5535 uint32_t reg, tmp;
5536
5537 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5538 with_spread = true;
5539 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5540 with_fdi, "LP PCH doesn't have FDI\n"))
5541 with_fdi = false;
f31f2d55
PZ		 5542
5543 mutex_lock(&dev_priv->dpio_lock);
5544
5545 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5546 tmp &= ~SBI_SSCCTL_DISABLE;
5547 tmp |= SBI_SSCCTL_PATHALT;
5548 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5549
5550 udelay(24);
5551
2fa86a1f
PZ		 5552 if (with_spread) {
5553 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5554 tmp &= ~SBI_SSCCTL_PATHALT;
5555 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5556
2fa86a1f
PZ		 5557 if (with_fdi) {
5558 lpt_reset_fdi_mphy(dev_priv);
5559 lpt_program_fdi_mphy(dev_priv);
5560 }
5561 }
dde86e2d 5562
2fa86a1f
PZ		 5563 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5564 SBI_GEN0 : SBI_DBUFF0;
5565 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5566 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5567 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5568
5569 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5570}
5571
47701c3b
PZ		 5572/* Sequence to disable CLKOUT_DP */
5573static void lpt_disable_clkout_dp(struct drm_device *dev)
5574{
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 uint32_t reg, tmp;
5577
5578 mutex_lock(&dev_priv->dpio_lock);
5579
5580 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5581 SBI_GEN0 : SBI_DBUFF0;
5582 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5583 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5584 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5585
5586 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5587 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5588 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5589 tmp |= SBI_SSCCTL_PATHALT;
5590 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5591 udelay(32);
5592 }
5593 tmp |= SBI_SSCCTL_DISABLE;
5594 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5595 }
5596
5597 mutex_unlock(&dev_priv->dpio_lock);
5598}
5599
bf8fa3d3
PZ		 5600static void lpt_init_pch_refclk(struct drm_device *dev)
5601{
5602 struct drm_mode_config *mode_config = &dev->mode_config;
5603 struct intel_encoder *encoder;
5604 bool has_vga = false;
5605
5606 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5607 switch (encoder->type) {
5608 case INTEL_OUTPUT_ANALOG:
5609 has_vga = true;
5610 break;
5611 }
5612 }
5613
47701c3b
PZ		 5614 if (has_vga)
5615 lpt_enable_clkout_dp(dev, true, true);
5616 else
5617 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5618}
5619
dde86e2d
PZ		 5620/*
5621 * Initialize reference clocks when the driver loads
5622 */
5623void intel_init_pch_refclk(struct drm_device *dev)
5624{
5625 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5626 ironlake_init_pch_refclk(dev);
5627 else if (HAS_PCH_LPT(dev))
5628 lpt_init_pch_refclk(dev);
5629}
5630
d9d444cb
JB		 5631static int ironlake_get_refclk(struct drm_crtc *crtc)
5632{
5633 struct drm_device *dev = crtc->dev;
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 struct intel_encoder *encoder;
d9d444cb
JB		 5636 int num_connectors = 0;
5637 bool is_lvds = false;
5638
6c2b7c12 5639 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5640 switch (encoder->type) {
5641 case INTEL_OUTPUT_LVDS:
5642 is_lvds = true;
5643 break;
d9d444cb
JB		 5644 }
5645 num_connectors++;
5646 }
5647
5648 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5649 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5650 dev_priv->vbt.lvds_ssc_freq);
5651 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5652 }
5653
5654 return 120000;
5655}
5656
6ff93609 5657static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5658{
c8203565 5659 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5661 int pipe = intel_crtc->pipe;
c8203565
PZ		 5662 uint32_t val;
5663
78114071 5664 val = 0;
c8203565 5665
965e0c48 5666 switch (intel_crtc->config.pipe_bpp) {
c8203565 5667 case 18:
dfd07d72 5668 val |= PIPECONF_6BPC;
c8203565
PZ		 5669 break;
5670 case 24:
dfd07d72 5671 val |= PIPECONF_8BPC;
c8203565
PZ		 5672 break;
5673 case 30:
dfd07d72 5674 val |= PIPECONF_10BPC;
c8203565
PZ		 5675 break;
5676 case 36:
dfd07d72 5677 val |= PIPECONF_12BPC;
c8203565
PZ		 5678 break;
5679 default:
cc769b62
PZ		 5680 /* Case prevented by intel_choose_pipe_bpp_dither. */
5681 BUG();
c8203565
PZ		 5682 }
5683
d8b32247 5684 if (intel_crtc->config.dither)
c8203565
PZ		 5685 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5686
6ff93609 5687 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5688 val |= PIPECONF_INTERLACED_ILK;
5689 else
5690 val |= PIPECONF_PROGRESSIVE;
5691
50f3b016 5692 if (intel_crtc->config.limited_color_range)
3685a8f3 5693 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5694
c8203565
PZ		 5695 I915_WRITE(PIPECONF(pipe), val);
5696 POSTING_READ(PIPECONF(pipe));
5697}
5698
86d3efce
VS		 5699/*
5700 * Set up the pipe CSC unit.
5701 *
5702 * Currently only full range RGB to limited range RGB conversion
5703 * is supported, but eventually this should handle various
5704 * RGB<->YCbCr scenarios as well.
5705 */
50f3b016 5706static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5707{
5708 struct drm_device *dev = crtc->dev;
5709 struct drm_i915_private *dev_priv = dev->dev_private;
5710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5711 int pipe = intel_crtc->pipe;
5712 uint16_t coeff = 0x7800; /* 1.0 */
5713
5714 /*
5715 * TODO: Check what kind of values actually come out of the pipe
5716 * with these coeff/postoff values and adjust to get the best
5717 * accuracy. Perhaps we even need to take the bpc value into
5718 * consideration.
5719 */
5720
50f3b016 5721 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5722 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5723
5724 /*
5725 * GY/GU and RY/RU should be the other way around according
5726 * to BSpec, but reality doesn't agree. Just set them up in
5727 * a way that results in the correct picture.
5728 */
5729 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5730 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5731
5732 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5733 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5734
5735 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5736 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5737
5738 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5739 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5740 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5741
5742 if (INTEL_INFO(dev)->gen > 6) {
5743 uint16_t postoff = 0;
5744
50f3b016 5745 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5746 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5747
5748 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5749 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5750 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5751
5752 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5753 } else {
5754 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5755
50f3b016 5756 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5757 mode |= CSC_BLACK_SCREEN_OFFSET;
5758
5759 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5760 }
5761}
5762
6ff93609 5763static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5764{
5765 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5767 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5768 uint32_t val;
5769
3eff4faa 5770 val = 0;
ee2b0b38 5771
d8b32247 5772 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5773 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5774
6ff93609 5775 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5776 val |= PIPECONF_INTERLACED_ILK;
5777 else
5778 val |= PIPECONF_PROGRESSIVE;
5779
702e7a56
PZ		 5780 I915_WRITE(PIPECONF(cpu_transcoder), val);
5781 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5782
5783 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5784 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5785}
5786
6591c6e4 5787static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5788 intel_clock_t *clock,
5789 bool *has_reduced_clock,
5790 intel_clock_t *reduced_clock)
5791{
5792 struct drm_device *dev = crtc->dev;
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794 struct intel_encoder *intel_encoder;
5795 int refclk;
d4906093 5796 const intel_limit_t *limit;
a16af721 5797 bool ret, is_lvds = false;
79e53945 5798
6591c6e4
PZ		 5799 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5800 switch (intel_encoder->type) {
79e53945
JB		 5801 case INTEL_OUTPUT_LVDS:
5802 is_lvds = true;
5803 break;
79e53945
JB		 5804 }
5805 }
5806
d9d444cb 5807 refclk = ironlake_get_refclk(crtc);
79e53945 5808
d4906093
ML		 5809 /*
5810 * Returns a set of divisors for the desired target clock with the given
5811 * refclk, or FALSE. The returned values represent the clock equation:
5812 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5813 */
1b894b59 5814 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5815 ret = dev_priv->display.find_dpll(limit, crtc,
5816 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5817 refclk, NULL, clock);
6591c6e4
PZ		 5818 if (!ret)
5819 return false;
cda4b7d3 5820
ddc9003c 5821 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5822 /*
5823 * Ensure we match the reduced clock's P to the target clock.
5824 * If the clocks don't match, we can't switch the display clock
5825 * by using the FP0/FP1. In such case we will disable the LVDS
5826 * downclock feature.
5827 */
ee9300bb
DV		 5828 *has_reduced_clock =
5829 dev_priv->display.find_dpll(limit, crtc,
5830 dev_priv->lvds_downclock,
5831 refclk, clock,
5832 reduced_clock);
652c393a 5833 }
61e9653f 5834
6591c6e4
PZ		 5835 return true;
5836}
5837
01a415fd
DV		 5838static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5839{
5840 struct drm_i915_private *dev_priv = dev->dev_private;
5841 uint32_t temp;
5842
5843 temp = I915_READ(SOUTH_CHICKEN1);
5844 if (temp & FDI_BC_BIFURCATION_SELECT)
5845 return;
5846
5847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5849
5850 temp |= FDI_BC_BIFURCATION_SELECT;
5851 DRM_DEBUG_KMS("enabling fdi C rx\n");
5852 I915_WRITE(SOUTH_CHICKEN1, temp);
5853 POSTING_READ(SOUTH_CHICKEN1);
5854}
5855
ebfd86fd 5856static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5857{
5858 struct drm_device *dev = intel_crtc->base.dev;
5859 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5860
5861 switch (intel_crtc->pipe) {
5862 case PIPE_A:
ebfd86fd 5863 break;
01a415fd 5864 case PIPE_B:
ebfd86fd 5865 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5866 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5867 else
5868 cpt_enable_fdi_bc_bifurcation(dev);
5869
ebfd86fd 5870 break;
01a415fd 5871 case PIPE_C:
01a415fd
DV		 5872 cpt_enable_fdi_bc_bifurcation(dev);
5873
ebfd86fd 5874 break;
01a415fd
DV		 5875 default:
5876 BUG();
5877 }
5878}
5879
d4b1931c
PZ		 5880int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5881{
5882 /*
5883 * Account for spread spectrum to avoid
5884 * oversubscribing the link. Max center spread
5885 * is 2.5%; use 5% for safety's sake.
5886 */
5887 u32 bps = target_clock * bpp * 21 / 20;
5888 return bps / (link_bw * 8) + 1;
5889}
5890
7429e9d4 5891static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5892{
7429e9d4 5893 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5894}
5895
de13a2e3 5896static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5897 u32 *fp,
9a7c7890 5898 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5899{
de13a2e3 5900 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5901 struct drm_device *dev = crtc->dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5903 struct intel_encoder *intel_encoder;
5904 uint32_t dpll;
6cc5f341 5905 int factor, num_connectors = 0;
09ede541 5906 bool is_lvds = false, is_sdvo = false;
79e53945 5907
de13a2e3
PZ		 5908 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5909 switch (intel_encoder->type) {
79e53945
JB		 5910 case INTEL_OUTPUT_LVDS:
5911 is_lvds = true;
5912 break;
5913 case INTEL_OUTPUT_SDVO:
7d57382e 5914 case INTEL_OUTPUT_HDMI:
79e53945 5915 is_sdvo = true;
79e53945 5916 break;
79e53945 5917 }
43565a06 5918
c751ce4f 5919 num_connectors++;
79e53945 5920 }
79e53945 5921
c1858123 5922 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5923 factor = 21;
5924 if (is_lvds) {
5925 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5926 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5927 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5928 factor = 25;
09ede541 5929 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5930 factor = 20;
c1858123 5931
7429e9d4 5932 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5933 *fp |= FP_CB_TUNE;
2c07245f 5934
9a7c7890
DV		 5935 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5936 *fp2 |= FP_CB_TUNE;
5937
5eddb70b 5938 dpll = 0;
2c07245f 5939
a07d6787
EA		 5940 if (is_lvds)
5941 dpll |= DPLLB_MODE_LVDS;
5942 else
5943 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5944
ef1b460d
DV		 5945 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5946 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5947
5948 if (is_sdvo)
4a33e48d 5949 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5950 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5951 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5952
a07d6787 5953 /* compute bitmask from p1 value */
7429e9d4 5954 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5955 /* also FPA1 */
7429e9d4 5956 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5957
7429e9d4 5958 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5959 case 5:
5960 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5961 break;
5962 case 7:
5963 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5964 break;
5965 case 10:
5966 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5967 break;
5968 case 14:
5969 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5970 break;
79e53945
JB		 5971 }
5972
b4c09f3b 5973 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5974 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5975 else
5976 dpll |= PLL_REF_INPUT_DREFCLK;
5977
959e16d6 5978 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5979}
5980
5981static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5982 int x, int y,
5983 struct drm_framebuffer *fb)
5984{
5985 struct drm_device *dev = crtc->dev;
5986 struct drm_i915_private *dev_priv = dev->dev_private;
5987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5988 int pipe = intel_crtc->pipe;
5989 int plane = intel_crtc->plane;
5990 int num_connectors = 0;
5991 intel_clock_t clock, reduced_clock;
cbbab5bd 5992 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5993 bool ok, has_reduced_clock = false;
8b47047b 5994 bool is_lvds = false;
de13a2e3 5995 struct intel_encoder *encoder;
e2b78267 5996 struct intel_shared_dpll *pll;
de13a2e3 5997 int ret;
de13a2e3
PZ		 5998
5999 for_each_encoder_on_crtc(dev, crtc, encoder) {
6000 switch (encoder->type) {
6001 case INTEL_OUTPUT_LVDS:
6002 is_lvds = true;
6003 break;
de13a2e3
PZ		 6004 }
6005
6006 num_connectors++;
a07d6787 6007 }
79e53945 6008
5dc5298b
PZ		 6009 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6010 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6011
ff9a6750 6012 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6013 &has_reduced_clock, &reduced_clock);
ee9300bb 6014 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6015 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6016 return -EINVAL;
79e53945 6017 }
f47709a9
DV		 6018 /* Compat-code for transition, will disappear. */
6019 if (!intel_crtc->config.clock_set) {
6020 intel_crtc->config.dpll.n = clock.n;
6021 intel_crtc->config.dpll.m1 = clock.m1;
6022 intel_crtc->config.dpll.m2 = clock.m2;
6023 intel_crtc->config.dpll.p1 = clock.p1;
6024 intel_crtc->config.dpll.p2 = clock.p2;
6025 }
79e53945 6026
5dc5298b 6027 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6028 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6029 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6030 if (has_reduced_clock)
7429e9d4 6031 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6032
7429e9d4 6033 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6034 &fp, &reduced_clock,
6035 has_reduced_clock ? &fp2 : NULL);
6036
959e16d6 6037 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6038 intel_crtc->config.dpll_hw_state.fp0 = fp;
6039 if (has_reduced_clock)
6040 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6041 else
6042 intel_crtc->config.dpll_hw_state.fp1 = fp;
6043
b89a1d39 6044 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6045 if (pll == NULL) {
84f44ce7
VS		 6046 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6047 pipe_name(pipe));
4b645f14
JB		 6048 return -EINVAL;
6049 }
ee7b9f93 6050 } else
e72f9fbf 6051 intel_put_shared_dpll(intel_crtc);
79e53945 6052
03afc4a2
DV		 6053 if (intel_crtc->config.has_dp_encoder)
6054 intel_dp_set_m_n(intel_crtc);
79e53945 6055
bcd644e0
DV		 6056 if (is_lvds && has_reduced_clock && i915_powersave)
6057 intel_crtc->lowfreq_avail = true;
6058 else
6059 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6060
6061 if (intel_crtc->config.has_pch_encoder) {
6062 pll = intel_crtc_to_shared_dpll(intel_crtc);
6063
652c393a
JB		 6064 }
6065
8a654f3b 6066 intel_set_pipe_timings(intel_crtc);
5eddb70b 6067
ca3a0ff8 6068 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6069 intel_cpu_transcoder_set_m_n(intel_crtc,
6070 &intel_crtc->config.fdi_m_n);
6071 }
2c07245f 6072
ebfd86fd
DV		 6073 if (IS_IVYBRIDGE(dev))
6074 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6075
6ff93609 6076 ironlake_set_pipeconf(crtc);
79e53945 6077
a1f9e77e
PZ		 6078 /* Set up the display plane register */
6079 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6080 POSTING_READ(DSPCNTR(plane));
79e53945 6081
94352cf9 6082 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6083
1857e1da 6084 return ret;
79e53945
JB		 6085}
6086
eb14cb74
VS		 6087static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6088 struct intel_link_m_n *m_n)
6089{
6090 struct drm_device *dev = crtc->base.dev;
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092 enum pipe pipe = crtc->pipe;
6093
6094 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6095 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6096 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6097 & ~TU_SIZE_MASK;
6098 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6099 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6100 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6101}
6102
6103static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6104 enum transcoder transcoder,
6105 struct intel_link_m_n *m_n)
72419203
DV		 6106{
6107 struct drm_device *dev = crtc->base.dev;
6108 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6109 enum pipe pipe = crtc->pipe;
72419203 6110
eb14cb74
VS		 6111 if (INTEL_INFO(dev)->gen >= 5) {
6112 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6113 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6114 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6115 & ~TU_SIZE_MASK;
6116 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6117 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6118 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6119 } else {
6120 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6121 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6122 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6123 & ~TU_SIZE_MASK;
6124 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6125 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6126 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6127 }
6128}
6129
6130void intel_dp_get_m_n(struct intel_crtc *crtc,
6131 struct intel_crtc_config *pipe_config)
6132{
6133 if (crtc->config.has_pch_encoder)
6134 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6135 else
6136 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6137 &pipe_config->dp_m_n);
6138}
72419203 6139
eb14cb74
VS		 6140static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6141 struct intel_crtc_config *pipe_config)
6142{
6143 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6144 &pipe_config->fdi_m_n);
72419203
DV		 6145}
6146
2fa2fe9a
DV		 6147static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6148 struct intel_crtc_config *pipe_config)
6149{
6150 struct drm_device *dev = crtc->base.dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 uint32_t tmp;
6153
6154 tmp = I915_READ(PF_CTL(crtc->pipe));
6155
6156 if (tmp & PF_ENABLE) {
fd4daa9c 6157 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6158 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6159 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6160
6161 /* We currently do not free assignements of panel fitters on
6162 * ivb/hsw (since we don't use the higher upscaling modes which
6163 * differentiates them) so just WARN about this case for now. */
6164 if (IS_GEN7(dev)) {
6165 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6166 PF_PIPE_SEL_IVB(crtc->pipe));
6167 }
2fa2fe9a 6168 }
79e53945
JB		 6169}
6170
0e8ffe1b
DV		 6171static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6172 struct intel_crtc_config *pipe_config)
6173{
6174 struct drm_device *dev = crtc->base.dev;
6175 struct drm_i915_private *dev_priv = dev->dev_private;
6176 uint32_t tmp;
6177
e143a21c 6178 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6179 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6180
0e8ffe1b
DV		 6181 tmp = I915_READ(PIPECONF(crtc->pipe));
6182 if (!(tmp & PIPECONF_ENABLE))
6183 return false;
6184
42571aef
VS		 6185 switch (tmp & PIPECONF_BPC_MASK) {
6186 case PIPECONF_6BPC:
6187 pipe_config->pipe_bpp = 18;
6188 break;
6189 case PIPECONF_8BPC:
6190 pipe_config->pipe_bpp = 24;
6191 break;
6192 case PIPECONF_10BPC:
6193 pipe_config->pipe_bpp = 30;
6194 break;
6195 case PIPECONF_12BPC:
6196 pipe_config->pipe_bpp = 36;
6197 break;
6198 default:
6199 break;
6200 }
6201
ab9412ba 6202 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6203 struct intel_shared_dpll *pll;
6204
88adfff1
DV		 6205 pipe_config->has_pch_encoder = true;
6206
627eb5a3
DV		 6207 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6208 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6209 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6210
6211 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6212
c0d43d62 6213 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6214 pipe_config->shared_dpll =
6215 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6216 } else {
6217 tmp = I915_READ(PCH_DPLL_SEL);
6218 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6219 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6220 else
6221 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6222 }
66e985c0
DV		 6223
6224 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6225
6226 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6227 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6228
6229 tmp = pipe_config->dpll_hw_state.dpll;
6230 pipe_config->pixel_multiplier =
6231 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6232 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6233
6234 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6235 } else {
6236 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6237 }
6238
1bd1bd80
DV		 6239 intel_get_pipe_timings(crtc, pipe_config);
6240
2fa2fe9a
DV		 6241 ironlake_get_pfit_config(crtc, pipe_config);
6242
0e8ffe1b
DV		 6243 return true;
6244}
6245
be256dc7
PZ		 6246static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6247{
6248 struct drm_device *dev = dev_priv->dev;
6249 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6250 struct intel_crtc *crtc;
6251 unsigned long irqflags;
bd633a7c 6252 uint32_t val;
be256dc7
PZ		 6253
6254 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6255 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6256 pipe_name(crtc->pipe));
6257
6258 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6259 WARN(plls->spll_refcount, "SPLL enabled\n");
6260 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6261 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6262 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6263 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6264 "CPU PWM1 enabled\n");
6265 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6266 "CPU PWM2 enabled\n");
6267 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6268 "PCH PWM1 enabled\n");
6269 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6270 "Utility pin enabled\n");
6271 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6272
6273 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6274 val = I915_READ(DEIMR);
6275 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6276 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6277 val = I915_READ(SDEIMR);
bd633a7c 6278 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6279 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6280 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6281}
6282
6283/*
6284 * This function implements pieces of two sequences from BSpec:
6285 * - Sequence for display software to disable LCPLL
6286 * - Sequence for display software to allow package C8+
6287 * The steps implemented here are just the steps that actually touch the LCPLL
6288 * register. Callers should take care of disabling all the display engine
6289 * functions, doing the mode unset, fixing interrupts, etc.
6290 */
6ff58d53
PZ		 6291static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6292 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6293{
6294 uint32_t val;
6295
6296 assert_can_disable_lcpll(dev_priv);
6297
6298 val = I915_READ(LCPLL_CTL);
6299
6300 if (switch_to_fclk) {
6301 val |= LCPLL_CD_SOURCE_FCLK;
6302 I915_WRITE(LCPLL_CTL, val);
6303
6304 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6305 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6306 DRM_ERROR("Switching to FCLK failed\n");
6307
6308 val = I915_READ(LCPLL_CTL);
6309 }
6310
6311 val |= LCPLL_PLL_DISABLE;
6312 I915_WRITE(LCPLL_CTL, val);
6313 POSTING_READ(LCPLL_CTL);
6314
6315 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6316 DRM_ERROR("LCPLL still locked\n");
6317
6318 val = I915_READ(D_COMP);
6319 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6320 mutex_lock(&dev_priv->rps.hw_lock);
6321 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6322 DRM_ERROR("Failed to disable D_COMP\n");
6323 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6324 POSTING_READ(D_COMP);
6325 ndelay(100);
6326
6327 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6328 DRM_ERROR("D_COMP RCOMP still in progress\n");
6329
6330 if (allow_power_down) {
6331 val = I915_READ(LCPLL_CTL);
6332 val |= LCPLL_POWER_DOWN_ALLOW;
6333 I915_WRITE(LCPLL_CTL, val);
6334 POSTING_READ(LCPLL_CTL);
6335 }
6336}
6337
6338/*
6339 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6340 * source.
6341 */
6ff58d53 6342static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6343{
6344 uint32_t val;
6345
6346 val = I915_READ(LCPLL_CTL);
6347
6348 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6349 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6350 return;
6351
215733fa
PZ		 6352 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6353 * we'll hang the machine! */
6354 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6355
be256dc7
PZ		 6356 if (val & LCPLL_POWER_DOWN_ALLOW) {
6357 val &= ~LCPLL_POWER_DOWN_ALLOW;
6358 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6359 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6360 }
6361
6362 val = I915_READ(D_COMP);
6363 val |= D_COMP_COMP_FORCE;
6364 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6365 mutex_lock(&dev_priv->rps.hw_lock);
6366 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6367 DRM_ERROR("Failed to enable D_COMP\n");
6368 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6369 POSTING_READ(D_COMP);
be256dc7
PZ		 6370
6371 val = I915_READ(LCPLL_CTL);
6372 val &= ~LCPLL_PLL_DISABLE;
6373 I915_WRITE(LCPLL_CTL, val);
6374
6375 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6376 DRM_ERROR("LCPLL not locked yet\n");
6377
6378 if (val & LCPLL_CD_SOURCE_FCLK) {
6379 val = I915_READ(LCPLL_CTL);
6380 val &= ~LCPLL_CD_SOURCE_FCLK;
6381 I915_WRITE(LCPLL_CTL, val);
6382
6383 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6384 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6385 DRM_ERROR("Switching back to LCPLL failed\n");
6386 }
215733fa
PZ		 6387
6388 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6389}
6390
c67a470b
PZ		 6391void hsw_enable_pc8_work(struct work_struct *__work)
6392{
6393 struct drm_i915_private *dev_priv =
6394 container_of(to_delayed_work(__work), struct drm_i915_private,
6395 pc8.enable_work);
6396 struct drm_device *dev = dev_priv->dev;
6397 uint32_t val;
6398
6399 if (dev_priv->pc8.enabled)
6400 return;
6401
6402 DRM_DEBUG_KMS("Enabling package C8+\n");
6403
6404 dev_priv->pc8.enabled = true;
6405
6406 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6407 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6408 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6409 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6410 }
6411
6412 lpt_disable_clkout_dp(dev);
6413 hsw_pc8_disable_interrupts(dev);
6414 hsw_disable_lcpll(dev_priv, true, true);
6415}
6416
6417static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6418{
6419 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6420 WARN(dev_priv->pc8.disable_count < 1,
6421 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6422
6423 dev_priv->pc8.disable_count--;
6424 if (dev_priv->pc8.disable_count != 0)
6425 return;
6426
6427 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6428 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6429}
6430
6431static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6432{
6433 struct drm_device *dev = dev_priv->dev;
6434 uint32_t val;
6435
6436 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6437 WARN(dev_priv->pc8.disable_count < 0,
6438 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6439
6440 dev_priv->pc8.disable_count++;
6441 if (dev_priv->pc8.disable_count != 1)
6442 return;
6443
6444 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6445 if (!dev_priv->pc8.enabled)
6446 return;
6447
6448 DRM_DEBUG_KMS("Disabling package C8+\n");
6449
6450 hsw_restore_lcpll(dev_priv);
6451 hsw_pc8_restore_interrupts(dev);
6452 lpt_init_pch_refclk(dev);
6453
6454 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6455 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6456 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6457 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6458 }
6459
6460 intel_prepare_ddi(dev);
6461 i915_gem_init_swizzling(dev);
6462 mutex_lock(&dev_priv->rps.hw_lock);
6463 gen6_update_ring_freq(dev);
6464 mutex_unlock(&dev_priv->rps.hw_lock);
6465 dev_priv->pc8.enabled = false;
6466}
6467
6468void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6469{
6470 mutex_lock(&dev_priv->pc8.lock);
6471 __hsw_enable_package_c8(dev_priv);
6472 mutex_unlock(&dev_priv->pc8.lock);
6473}
6474
6475void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6476{
6477 mutex_lock(&dev_priv->pc8.lock);
6478 __hsw_disable_package_c8(dev_priv);
6479 mutex_unlock(&dev_priv->pc8.lock);
6480}
6481
6482static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6483{
6484 struct drm_device *dev = dev_priv->dev;
6485 struct intel_crtc *crtc;
6486 uint32_t val;
6487
6488 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6489 if (crtc->base.enabled)
6490 return false;
6491
6492 /* This case is still possible since we have the i915.disable_power_well
6493 * parameter and also the KVMr or something else might be requesting the
6494 * power well. */
6495 val = I915_READ(HSW_PWR_WELL_DRIVER);
6496 if (val != 0) {
6497 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6498 return false;
6499 }
6500
6501 return true;
6502}
6503
6504/* Since we're called from modeset_global_resources there's no way to
6505 * symmetrically increase and decrease the refcount, so we use
6506 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6507 * or not.
6508 */
6509static void hsw_update_package_c8(struct drm_device *dev)
6510{
6511 struct drm_i915_private *dev_priv = dev->dev_private;
6512 bool allow;
6513
6514 if (!i915_enable_pc8)
6515 return;
6516
6517 mutex_lock(&dev_priv->pc8.lock);
6518
6519 allow = hsw_can_enable_package_c8(dev_priv);
6520
6521 if (allow == dev_priv->pc8.requirements_met)
6522 goto done;
6523
6524 dev_priv->pc8.requirements_met = allow;
6525
6526 if (allow)
6527 __hsw_enable_package_c8(dev_priv);
6528 else
6529 __hsw_disable_package_c8(dev_priv);
6530
6531done:
6532 mutex_unlock(&dev_priv->pc8.lock);
6533}
6534
6535static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6536{
6537 if (!dev_priv->pc8.gpu_idle) {
6538 dev_priv->pc8.gpu_idle = true;
6539 hsw_enable_package_c8(dev_priv);
6540 }
6541}
6542
6543static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6544{
6545 if (dev_priv->pc8.gpu_idle) {
6546 dev_priv->pc8.gpu_idle = false;
6547 hsw_disable_package_c8(dev_priv);
6548 }
be256dc7
PZ		 6549}
6550
d6dd9eb1
DV		 6551static void haswell_modeset_global_resources(struct drm_device *dev)
6552{
d6dd9eb1
DV		 6553 bool enable = false;
6554 struct intel_crtc *crtc;
d6dd9eb1
DV		 6555
6556 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6557 if (!crtc->base.enabled)
6558 continue;
d6dd9eb1 6559
fd4daa9c 6560 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6561 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6562 enable = true;
6563 }
6564
d6dd9eb1 6565 intel_set_power_well(dev, enable);
c67a470b
PZ		 6566
6567 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6568}
6569
09b4ddf9 6570static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6571 int x, int y,
6572 struct drm_framebuffer *fb)
6573{
6574 struct drm_device *dev = crtc->dev;
6575 struct drm_i915_private *dev_priv = dev->dev_private;
6576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6577 int plane = intel_crtc->plane;
09b4ddf9 6578 int ret;
09b4ddf9 6579
ff9a6750 6580 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6581 return -EINVAL;
6582
03afc4a2
DV		 6583 if (intel_crtc->config.has_dp_encoder)
6584 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6585
6586 intel_crtc->lowfreq_avail = false;
09b4ddf9 6587
8a654f3b 6588 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6589
ca3a0ff8 6590 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6591 intel_cpu_transcoder_set_m_n(intel_crtc,
6592 &intel_crtc->config.fdi_m_n);
6593 }
09b4ddf9 6594
6ff93609 6595 haswell_set_pipeconf(crtc);
09b4ddf9 6596
50f3b016 6597 intel_set_pipe_csc(crtc);
86d3efce 6598
09b4ddf9 6599 /* Set up the display plane register */
86d3efce 6600 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6601 POSTING_READ(DSPCNTR(plane));
6602
6603 ret = intel_pipe_set_base(crtc, x, y, fb);
6604
1f803ee5 6605 return ret;
79e53945
JB		 6606}
6607
0e8ffe1b
DV		 6608static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6609 struct intel_crtc_config *pipe_config)
6610{
6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6613 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6614 uint32_t tmp;
6615
e143a21c 6616 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6617 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6618
eccb140b
DV		 6619 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6620 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6621 enum pipe trans_edp_pipe;
6622 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6623 default:
6624 WARN(1, "unknown pipe linked to edp transcoder\n");
6625 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6626 case TRANS_DDI_EDP_INPUT_A_ON:
6627 trans_edp_pipe = PIPE_A;
6628 break;
6629 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6630 trans_edp_pipe = PIPE_B;
6631 break;
6632 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6633 trans_edp_pipe = PIPE_C;
6634 break;
6635 }
6636
6637 if (trans_edp_pipe == crtc->pipe)
6638 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6639 }
6640
b97186f0 6641 if (!intel_display_power_enabled(dev,
eccb140b 6642 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6643 return false;
6644
eccb140b 6645 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6646 if (!(tmp & PIPECONF_ENABLE))
6647 return false;
6648
88adfff1 6649 /*
f196e6be 6650 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6651 * DDI E. So just check whether this pipe is wired to DDI E and whether
6652 * the PCH transcoder is on.
6653 */
eccb140b 6654 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6655 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6656 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6657 pipe_config->has_pch_encoder = true;
6658
627eb5a3
DV		 6659 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6660 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6661 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6662
6663 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6664 }
6665
1bd1bd80
DV		 6666 intel_get_pipe_timings(crtc, pipe_config);
6667
2fa2fe9a
DV		 6668 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6669 if (intel_display_power_enabled(dev, pfit_domain))
6670 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6671
42db64ef
PZ		 6672 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6673 (I915_READ(IPS_CTL) & IPS_ENABLE);
6674
6c49f241
DV		 6675 pipe_config->pixel_multiplier = 1;
6676
0e8ffe1b
DV		 6677 return true;
6678}
6679
f564048e 6680static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6681 int x, int y,
94352cf9 6682 struct drm_framebuffer *fb)
f564048e
EA		 6683{
6684 struct drm_device *dev = crtc->dev;
6685 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6686 struct intel_encoder *encoder;
0b701d27 6687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6688 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6689 int pipe = intel_crtc->pipe;
f564048e
EA		 6690 int ret;
6691
0b701d27 6692 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6693
b8cecdf5
DV		 6694 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6695
79e53945 6696 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6697
9256aa19
DV		 6698 if (ret != 0)
6699 return ret;
6700
6701 for_each_encoder_on_crtc(dev, crtc, encoder) {
6702 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6703 encoder->base.base.id,
6704 drm_get_encoder_name(&encoder->base),
6705 mode->base.id, mode->name);
36f2d1f1 6706 encoder->mode_set(encoder);
9256aa19
DV		 6707 }
6708
6709 return 0;
79e53945
JB		 6710}
6711
3a9627f4
WF		 6712static bool intel_eld_uptodate(struct drm_connector *connector,
6713 int reg_eldv, uint32_t bits_eldv,
6714 int reg_elda, uint32_t bits_elda,
6715 int reg_edid)
6716{
6717 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6718 uint8_t *eld = connector->eld;
6719 uint32_t i;
6720
6721 i = I915_READ(reg_eldv);
6722 i &= bits_eldv;
6723
6724 if (!eld[0])
6725 return !i;
6726
6727 if (!i)
6728 return false;
6729
6730 i = I915_READ(reg_elda);
6731 i &= ~bits_elda;
6732 I915_WRITE(reg_elda, i);
6733
6734 for (i = 0; i < eld[2]; i++)
6735 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6736 return false;
6737
6738 return true;
6739}
6740
e0dac65e
WF		 6741static void g4x_write_eld(struct drm_connector *connector,
6742 struct drm_crtc *crtc)
6743{
6744 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6745 uint8_t *eld = connector->eld;
6746 uint32_t eldv;
6747 uint32_t len;
6748 uint32_t i;
6749
6750 i = I915_READ(G4X_AUD_VID_DID);
6751
6752 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6753 eldv = G4X_ELDV_DEVCL_DEVBLC;
6754 else
6755 eldv = G4X_ELDV_DEVCTG;
6756
3a9627f4
WF		 6757 if (intel_eld_uptodate(connector,
6758 G4X_AUD_CNTL_ST, eldv,
6759 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6760 G4X_HDMIW_HDMIEDID))
6761 return;
6762
e0dac65e
WF		 6763 i = I915_READ(G4X_AUD_CNTL_ST);
6764 i &= ~(eldv | G4X_ELD_ADDR);
6765 len = (i >> 9) & 0x1f; /* ELD buffer size */
6766 I915_WRITE(G4X_AUD_CNTL_ST, i);
6767
6768 if (!eld[0])
6769 return;
6770
6771 len = min_t(uint8_t, eld[2], len);
6772 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6773 for (i = 0; i < len; i++)
6774 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6775
6776 i = I915_READ(G4X_AUD_CNTL_ST);
6777 i |= eldv;
6778 I915_WRITE(G4X_AUD_CNTL_ST, i);
6779}
6780
83358c85
WX		 6781static void haswell_write_eld(struct drm_connector *connector,
6782 struct drm_crtc *crtc)
6783{
6784 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6785 uint8_t *eld = connector->eld;
6786 struct drm_device *dev = crtc->dev;
7b9f35a6 6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6788 uint32_t eldv;
6789 uint32_t i;
6790 int len;
6791 int pipe = to_intel_crtc(crtc)->pipe;
6792 int tmp;
6793
6794 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6795 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6796 int aud_config = HSW_AUD_CFG(pipe);
6797 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6798
6799
6800 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6801
6802 /* Audio output enable */
6803 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6804 tmp = I915_READ(aud_cntrl_st2);
6805 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6806 I915_WRITE(aud_cntrl_st2, tmp);
6807
6808 /* Wait for 1 vertical blank */
6809 intel_wait_for_vblank(dev, pipe);
6810
6811 /* Set ELD valid state */
6812 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6813 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6814 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6815 I915_WRITE(aud_cntrl_st2, tmp);
6816 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6817 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6818
6819 /* Enable HDMI mode */
6820 tmp = I915_READ(aud_config);
7e7cb34f 6821 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6822 /* clear N_programing_enable and N_value_index */
6823 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6824 I915_WRITE(aud_config, tmp);
6825
6826 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6827
6828 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6829 intel_crtc->eld_vld = true;
83358c85
WX		 6830
6831 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6832 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6833 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6834 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6835 } else
6836 I915_WRITE(aud_config, 0);
6837
6838 if (intel_eld_uptodate(connector,
6839 aud_cntrl_st2, eldv,
6840 aud_cntl_st, IBX_ELD_ADDRESS,
6841 hdmiw_hdmiedid))
6842 return;
6843
6844 i = I915_READ(aud_cntrl_st2);
6845 i &= ~eldv;
6846 I915_WRITE(aud_cntrl_st2, i);
6847
6848 if (!eld[0])
6849 return;
6850
6851 i = I915_READ(aud_cntl_st);
6852 i &= ~IBX_ELD_ADDRESS;
6853 I915_WRITE(aud_cntl_st, i);
6854 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6855 DRM_DEBUG_DRIVER("port num:%d\n", i);
6856
6857 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6858 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6859 for (i = 0; i < len; i++)
6860 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6861
6862 i = I915_READ(aud_cntrl_st2);
6863 i |= eldv;
6864 I915_WRITE(aud_cntrl_st2, i);
6865
6866}
6867
e0dac65e
WF		 6868static void ironlake_write_eld(struct drm_connector *connector,
6869 struct drm_crtc *crtc)
6870{
6871 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6872 uint8_t *eld = connector->eld;
6873 uint32_t eldv;
6874 uint32_t i;
6875 int len;
6876 int hdmiw_hdmiedid;
b6daa025 6877 int aud_config;
e0dac65e
WF		 6878 int aud_cntl_st;
6879 int aud_cntrl_st2;
9b138a83 6880 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6881
b3f33cbf 6882 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6883 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6884 aud_config = IBX_AUD_CFG(pipe);
6885 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6886 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6887 } else {
9b138a83
WX		 6888 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6889 aud_config = CPT_AUD_CFG(pipe);
6890 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6891 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6892 }
6893
9b138a83 6894 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6895
6896 i = I915_READ(aud_cntl_st);
9b138a83 6897 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6898 if (!i) {
6899 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6900 /* operate blindly on all ports */
1202b4c6
WF		 6901 eldv = IBX_ELD_VALIDB;
6902 eldv |= IBX_ELD_VALIDB << 4;
6903 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6904 } else {
2582a850 6905 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6906 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6907 }
6908
3a9627f4
WF		 6909 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6910 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6911 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6912 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6913 } else
6914 I915_WRITE(aud_config, 0);
e0dac65e 6915
3a9627f4
WF		 6916 if (intel_eld_uptodate(connector,
6917 aud_cntrl_st2, eldv,
6918 aud_cntl_st, IBX_ELD_ADDRESS,
6919 hdmiw_hdmiedid))
6920 return;
6921
e0dac65e
WF		 6922 i = I915_READ(aud_cntrl_st2);
6923 i &= ~eldv;
6924 I915_WRITE(aud_cntrl_st2, i);
6925
6926 if (!eld[0])
6927 return;
6928
e0dac65e 6929 i = I915_READ(aud_cntl_st);
1202b4c6 6930 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6931 I915_WRITE(aud_cntl_st, i);
6932
6933 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6934 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6935 for (i = 0; i < len; i++)
6936 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6937
6938 i = I915_READ(aud_cntrl_st2);
6939 i |= eldv;
6940 I915_WRITE(aud_cntrl_st2, i);
6941}
6942
6943void intel_write_eld(struct drm_encoder *encoder,
6944 struct drm_display_mode *mode)
6945{
6946 struct drm_crtc *crtc = encoder->crtc;
6947 struct drm_connector *connector;
6948 struct drm_device *dev = encoder->dev;
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950
6951 connector = drm_select_eld(encoder, mode);
6952 if (!connector)
6953 return;
6954
6955 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6956 connector->base.id,
6957 drm_get_connector_name(connector),
6958 connector->encoder->base.id,
6959 drm_get_encoder_name(connector->encoder));
6960
6961 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6962
6963 if (dev_priv->display.write_eld)
6964 dev_priv->display.write_eld(connector, crtc);
6965}
6966
560b85bb
CW		 6967static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6968{
6969 struct drm_device *dev = crtc->dev;
6970 struct drm_i915_private *dev_priv = dev->dev_private;
6971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6972 bool visible = base != 0;
6973 u32 cntl;
6974
6975 if (intel_crtc->cursor_visible == visible)
6976 return;
6977
9db4a9c7 6978 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6979 if (visible) {
6980 /* On these chipsets we can only modify the base whilst
6981 * the cursor is disabled.
6982 */
9db4a9c7 6983 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6984
6985 cntl &= ~(CURSOR_FORMAT_MASK);
6986 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6987 cntl |= CURSOR_ENABLE |
6988 CURSOR_GAMMA_ENABLE |
6989 CURSOR_FORMAT_ARGB;
6990 } else
6991 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6992 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6993
6994 intel_crtc->cursor_visible = visible;
6995}
6996
6997static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6998{
6999 struct drm_device *dev = crtc->dev;
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002 int pipe = intel_crtc->pipe;
7003 bool visible = base != 0;
7004
7005 if (intel_crtc->cursor_visible != visible) {
548f245b 7006 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7007 if (base) {
7008 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7009 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7010 cntl |= pipe << 28; /* Connect to correct pipe */
7011 } else {
7012 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7013 cntl |= CURSOR_MODE_DISABLE;
7014 }
9db4a9c7 7015 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7016
7017 intel_crtc->cursor_visible = visible;
7018 }
7019 /* and commit changes on next vblank */
9db4a9c7 7020 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7021}
7022
65a21cd6
JB		 7023static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7024{
7025 struct drm_device *dev = crtc->dev;
7026 struct drm_i915_private *dev_priv = dev->dev_private;
7027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7028 int pipe = intel_crtc->pipe;
7029 bool visible = base != 0;
7030
7031 if (intel_crtc->cursor_visible != visible) {
7032 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7033 if (base) {
7034 cntl &= ~CURSOR_MODE;
7035 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7036 } else {
7037 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7038 cntl |= CURSOR_MODE_DISABLE;
7039 }
1f5d76db 7040 if (IS_HASWELL(dev)) {
86d3efce 7041 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7042 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7043 }
65a21cd6
JB		 7044 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7045
7046 intel_crtc->cursor_visible = visible;
7047 }
7048 /* and commit changes on next vblank */
7049 I915_WRITE(CURBASE_IVB(pipe), base);
7050}
7051
cda4b7d3 7052/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7053static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7054 bool on)
cda4b7d3
CW		 7055{
7056 struct drm_device *dev = crtc->dev;
7057 struct drm_i915_private *dev_priv = dev->dev_private;
7058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7059 int pipe = intel_crtc->pipe;
7060 int x = intel_crtc->cursor_x;
7061 int y = intel_crtc->cursor_y;
d6e4db15 7062 u32 base = 0, pos = 0;
cda4b7d3
CW		 7063 bool visible;
7064
d6e4db15 7065 if (on)
cda4b7d3 7066 base = intel_crtc->cursor_addr;
cda4b7d3 7067
d6e4db15
VS		 7068 if (x >= intel_crtc->config.pipe_src_w)
7069 base = 0;
7070
7071 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7072 base = 0;
7073
7074 if (x < 0) {
efc9064e 7075 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7076 base = 0;
7077
7078 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7079 x = -x;
7080 }
7081 pos |= x << CURSOR_X_SHIFT;
7082
7083 if (y < 0) {
efc9064e 7084 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7085 base = 0;
7086
7087 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7088 y = -y;
7089 }
7090 pos |= y << CURSOR_Y_SHIFT;
7091
7092 visible = base != 0;
560b85bb 7093 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7094 return;
7095
0cd83aa9 7096 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7097 I915_WRITE(CURPOS_IVB(pipe), pos);
7098 ivb_update_cursor(crtc, base);
7099 } else {
7100 I915_WRITE(CURPOS(pipe), pos);
7101 if (IS_845G(dev) || IS_I865G(dev))
7102 i845_update_cursor(crtc, base);
7103 else
7104 i9xx_update_cursor(crtc, base);
7105 }
cda4b7d3
CW		 7106}
7107
79e53945 7108static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7109 struct drm_file *file,
79e53945
JB		 7110 uint32_t handle,
7111 uint32_t width, uint32_t height)
7112{
7113 struct drm_device *dev = crtc->dev;
7114 struct drm_i915_private *dev_priv = dev->dev_private;
7115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7116 struct drm_i915_gem_object *obj;
cda4b7d3 7117 uint32_t addr;
3f8bc370 7118 int ret;
79e53945 7119
79e53945
JB		 7120 /* if we want to turn off the cursor ignore width and height */
7121 if (!handle) {
28c97730 7122 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7123 addr = 0;
05394f39 7124 obj = NULL;
5004417d 7125 mutex_lock(&dev->struct_mutex);
3f8bc370 7126 goto finish;
79e53945
JB		 7127 }
7128
7129 /* Currently we only support 64x64 cursors */
7130 if (width != 64 || height != 64) {
7131 DRM_ERROR("we currently only support 64x64 cursors\n");
7132 return -EINVAL;
7133 }
7134
05394f39 7135 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7136 if (&obj->base == NULL)
79e53945
JB		 7137 return -ENOENT;
7138
05394f39 7139 if (obj->base.size < width * height * 4) {
79e53945 7140 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7141 ret = -ENOMEM;
7142 goto fail;
79e53945
JB		 7143 }
7144
71acb5eb 7145 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7146 mutex_lock(&dev->struct_mutex);
b295d1b6 7147 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7148 unsigned alignment;
7149
d9e86c0e
CW		 7150 if (obj->tiling_mode) {
7151 DRM_ERROR("cursor cannot be tiled\n");
7152 ret = -EINVAL;
7153 goto fail_locked;
7154 }
7155
693db184
CW		 7156 /* Note that the w/a also requires 2 PTE of padding following
7157 * the bo. We currently fill all unused PTE with the shadow
7158 * page and so we should always have valid PTE following the
7159 * cursor preventing the VT-d warning.
7160 */
7161 alignment = 0;
7162 if (need_vtd_wa(dev))
7163 alignment = 64*1024;
7164
7165 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7166 if (ret) {
7167 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7168 goto fail_locked;
e7b526bb
CW		 7169 }
7170
d9e86c0e
CW		 7171 ret = i915_gem_object_put_fence(obj);
7172 if (ret) {
2da3b9b9 7173 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7174 goto fail_unpin;
7175 }
7176
f343c5f6 7177 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7178 } else {
6eeefaf3 7179 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7180 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7181 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7182 align);
71acb5eb
DA		 7183 if (ret) {
7184 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7185 goto fail_locked;
71acb5eb 7186 }
05394f39 7187 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7188 }
7189
a6c45cf0 7190 if (IS_GEN2(dev))
14b60391
JB		 7191 I915_WRITE(CURSIZE, (height << 12) | width);
7192
3f8bc370 7193 finish:
3f8bc370 7194 if (intel_crtc->cursor_bo) {
b295d1b6 7195 if (dev_priv->info->cursor_needs_physical) {
05394f39 7196 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7197 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7198 } else
cc98b413 7199 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7200 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7201 }
80824003 7202
7f9872e0 7203 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7204
7205 intel_crtc->cursor_addr = addr;
05394f39 7206 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7207 intel_crtc->cursor_width = width;
7208 intel_crtc->cursor_height = height;
7209
f2f5f771
VS		 7210 if (intel_crtc->active)
7211 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7212
79e53945 7213 return 0;
e7b526bb 7214fail_unpin:
cc98b413 7215 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7216fail_locked:
34b8686e 7217 mutex_unlock(&dev->struct_mutex);
bc9025bd 7218fail:
05394f39 7219 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7220 return ret;
79e53945
JB		 7221}
7222
7223static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7224{
79e53945 7225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7226
cda4b7d3
CW		 7227 intel_crtc->cursor_x = x;
7228 intel_crtc->cursor_y = y;
652c393a 7229
f2f5f771
VS		 7230 if (intel_crtc->active)
7231 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7232
7233 return 0;
b8c00ac5
DA		 7234}
7235
79e53945 7236static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7237 u16 *blue, uint32_t start, uint32_t size)
79e53945 7238{
7203425a 7239 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7241
7203425a 7242 for (i = start; i < end; i++) {
79e53945
JB		 7243 intel_crtc->lut_r[i] = red[i] >> 8;
7244 intel_crtc->lut_g[i] = green[i] >> 8;
7245 intel_crtc->lut_b[i] = blue[i] >> 8;
7246 }
7247
7248 intel_crtc_load_lut(crtc);
7249}
7250
79e53945
JB		 7251/* VESA 640x480x72Hz mode to set on the pipe */
7252static struct drm_display_mode load_detect_mode = {
7253 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7254 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7255};
7256
d2dff872
CW		 7257static struct drm_framebuffer *
7258intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7259 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7260 struct drm_i915_gem_object *obj)
7261{
7262 struct intel_framebuffer *intel_fb;
7263 int ret;
7264
7265 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7266 if (!intel_fb) {
7267 drm_gem_object_unreference_unlocked(&obj->base);
7268 return ERR_PTR(-ENOMEM);
7269 }
7270
7271 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7272 if (ret) {
7273 drm_gem_object_unreference_unlocked(&obj->base);
7274 kfree(intel_fb);
7275 return ERR_PTR(ret);
7276 }
7277
7278 return &intel_fb->base;
7279}
7280
7281static u32
7282intel_framebuffer_pitch_for_width(int width, int bpp)
7283{
7284 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7285 return ALIGN(pitch, 64);
7286}
7287
7288static u32
7289intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7290{
7291 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7292 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7293}
7294
7295static struct drm_framebuffer *
7296intel_framebuffer_create_for_mode(struct drm_device *dev,
7297 struct drm_display_mode *mode,
7298 int depth, int bpp)
7299{
7300 struct drm_i915_gem_object *obj;
0fed39bd 7301 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7302
7303 obj = i915_gem_alloc_object(dev,
7304 intel_framebuffer_size_for_mode(mode, bpp));
7305 if (obj == NULL)
7306 return ERR_PTR(-ENOMEM);
7307
7308 mode_cmd.width = mode->hdisplay;
7309 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7310 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7311 bpp);
5ca0c34a 7312 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7313
7314 return intel_framebuffer_create(dev, &mode_cmd, obj);
7315}
7316
7317static struct drm_framebuffer *
7318mode_fits_in_fbdev(struct drm_device *dev,
7319 struct drm_display_mode *mode)
7320{
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322 struct drm_i915_gem_object *obj;
7323 struct drm_framebuffer *fb;
7324
7325 if (dev_priv->fbdev == NULL)
7326 return NULL;
7327
7328 obj = dev_priv->fbdev->ifb.obj;
7329 if (obj == NULL)
7330 return NULL;
7331
7332 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7333 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7334 fb->bits_per_pixel))
d2dff872
CW		 7335 return NULL;
7336
01f2c773 7337 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7338 return NULL;
7339
7340 return fb;
7341}
7342
d2434ab7 7343bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7344 struct drm_display_mode *mode,
8261b191 7345 struct intel_load_detect_pipe *old)
79e53945
JB		 7346{
7347 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7348 struct intel_encoder *intel_encoder =
7349 intel_attached_encoder(connector);
79e53945 7350 struct drm_crtc *possible_crtc;
4ef69c7a 7351 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7352 struct drm_crtc *crtc = NULL;
7353 struct drm_device *dev = encoder->dev;
94352cf9 7354 struct drm_framebuffer *fb;
79e53945
JB		 7355 int i = -1;
7356
d2dff872
CW		 7357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7358 connector->base.id, drm_get_connector_name(connector),
7359 encoder->base.id, drm_get_encoder_name(encoder));
7360
79e53945
JB		 7361 /*
7362 * Algorithm gets a little messy:
7a5e4805 7363 *
79e53945
JB		 7364 * - if the connector already has an assigned crtc, use it (but make
7365 * sure it's on first)
7a5e4805 7366 *
79e53945
JB		 7367 * - try to find the first unused crtc that can drive this connector,
7368 * and use that if we find one
79e53945
JB		 7369 */
7370
7371 /* See if we already have a CRTC for this connector */
7372 if (encoder->crtc) {
7373 crtc = encoder->crtc;
8261b191 7374
7b24056b
DV		 7375 mutex_lock(&crtc->mutex);
7376
24218aac 7377 old->dpms_mode = connector->dpms;
8261b191
CW		 7378 old->load_detect_temp = false;
7379
7380 /* Make sure the crtc and connector are running */
24218aac
DV		 7381 if (connector->dpms != DRM_MODE_DPMS_ON)
7382 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7383
7173188d 7384 return true;
79e53945
JB		 7385 }
7386
7387 /* Find an unused one (if possible) */
7388 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7389 i++;
7390 if (!(encoder->possible_crtcs & (1 << i)))
7391 continue;
7392 if (!possible_crtc->enabled) {
7393 crtc = possible_crtc;
7394 break;
7395 }
79e53945
JB		 7396 }
7397
7398 /*
7399 * If we didn't find an unused CRTC, don't use any.
7400 */
7401 if (!crtc) {
7173188d
CW		 7402 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7403 return false;
79e53945
JB		 7404 }
7405
7b24056b 7406 mutex_lock(&crtc->mutex);
fc303101
DV		 7407 intel_encoder->new_crtc = to_intel_crtc(crtc);
7408 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7409
7410 intel_crtc = to_intel_crtc(crtc);
24218aac 7411 old->dpms_mode = connector->dpms;
8261b191 7412 old->load_detect_temp = true;
d2dff872 7413 old->release_fb = NULL;
79e53945 7414
6492711d
CW		 7415 if (!mode)
7416 mode = &load_detect_mode;
79e53945 7417
d2dff872
CW		 7418 /* We need a framebuffer large enough to accommodate all accesses
7419 * that the plane may generate whilst we perform load detection.
7420 * We can not rely on the fbcon either being present (we get called
7421 * during its initialisation to detect all boot displays, or it may
7422 * not even exist) or that it is large enough to satisfy the
7423 * requested mode.
7424 */
94352cf9
DV		 7425 fb = mode_fits_in_fbdev(dev, mode);
7426 if (fb == NULL) {
d2dff872 7427 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7428 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7429 old->release_fb = fb;
d2dff872
CW		 7430 } else
7431 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7432 if (IS_ERR(fb)) {
d2dff872 7433 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7434 mutex_unlock(&crtc->mutex);
0e8b3d3e 7435 return false;
79e53945 7436 }
79e53945 7437
c0c36b94 7438 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7439 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7440 if (old->release_fb)
7441 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7442 mutex_unlock(&crtc->mutex);
0e8b3d3e 7443 return false;
79e53945 7444 }
7173188d 7445
79e53945 7446 /* let the connector get through one full cycle before testing */
9d0498a2 7447 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7448 return true;
79e53945
JB		 7449}
7450
d2434ab7 7451void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7452 struct intel_load_detect_pipe *old)
79e53945 7453{
d2434ab7
DV		 7454 struct intel_encoder *intel_encoder =
7455 intel_attached_encoder(connector);
4ef69c7a 7456 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7457 struct drm_crtc *crtc = encoder->crtc;
79e53945 7458
d2dff872
CW		 7459 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7460 connector->base.id, drm_get_connector_name(connector),
7461 encoder->base.id, drm_get_encoder_name(encoder));
7462
8261b191 7463 if (old->load_detect_temp) {
fc303101
DV		 7464 to_intel_connector(connector)->new_encoder = NULL;
7465 intel_encoder->new_crtc = NULL;
7466 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7467
36206361
DV		 7468 if (old->release_fb) {
7469 drm_framebuffer_unregister_private(old->release_fb);
7470 drm_framebuffer_unreference(old->release_fb);
7471 }
d2dff872 7472
67c96400 7473 mutex_unlock(&crtc->mutex);
0622a53c 7474 return;
79e53945
JB		 7475 }
7476
c751ce4f 7477 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7478 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7479 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7480
7481 mutex_unlock(&crtc->mutex);
79e53945
JB		 7482}
7483
da4a1efa
VS		 7484static int i9xx_pll_refclk(struct drm_device *dev,
7485 const struct intel_crtc_config *pipe_config)
7486{
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 u32 dpll = pipe_config->dpll_hw_state.dpll;
7489
7490 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7491 return dev_priv->vbt.lvds_ssc_freq * 1000;
7492 else if (HAS_PCH_SPLIT(dev))
7493 return 120000;
7494 else if (!IS_GEN2(dev))
7495 return 96000;
7496 else
7497 return 48000;
7498}
7499
79e53945 7500/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7501static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7502 struct intel_crtc_config *pipe_config)
79e53945 7503{
f1f644dc 7504 struct drm_device *dev = crtc->base.dev;
79e53945 7505 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7506 int pipe = pipe_config->cpu_transcoder;
293623f7 7507 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7508 u32 fp;
7509 intel_clock_t clock;
da4a1efa 7510 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7511
7512 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7513 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7514 else
293623f7 7515 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7516
7517 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7518 if (IS_PINEVIEW(dev)) {
7519 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7520 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7521 } else {
7522 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7523 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7524 }
7525
a6c45cf0 7526 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7527 if (IS_PINEVIEW(dev))
7528 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7529 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7530 else
7531 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7532 DPLL_FPA01_P1_POST_DIV_SHIFT);
7533
7534 switch (dpll & DPLL_MODE_MASK) {
7535 case DPLLB_MODE_DAC_SERIAL:
7536 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7537 5 : 10;
7538 break;
7539 case DPLLB_MODE_LVDS:
7540 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7541 7 : 14;
7542 break;
7543 default:
28c97730 7544 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7545 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7546 return;
79e53945
JB		 7547 }
7548
ac58c3f0 7549 if (IS_PINEVIEW(dev))
da4a1efa 7550 pineview_clock(refclk, &clock);
ac58c3f0 7551 else
da4a1efa 7552 i9xx_clock(refclk, &clock);
79e53945
JB		 7553 } else {
7554 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7555
7556 if (is_lvds) {
7557 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7558 DPLL_FPA01_P1_POST_DIV_SHIFT);
7559 clock.p2 = 14;
79e53945
JB		 7560 } else {
7561 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7562 clock.p1 = 2;
7563 else {
7564 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7565 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7566 }
7567 if (dpll & PLL_P2_DIVIDE_BY_4)
7568 clock.p2 = 4;
7569 else
7570 clock.p2 = 2;
79e53945 7571 }
da4a1efa
VS		 7572
7573 i9xx_clock(refclk, &clock);
79e53945
JB		 7574 }
7575
18442d08
VS		 7576 /*
7577 * This value includes pixel_multiplier. We will use
241bfc38 7578 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7579 * encoder's get_config() function.
7580 */
7581 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7582}
7583
6878da05
VS		 7584int intel_dotclock_calculate(int link_freq,
7585 const struct intel_link_m_n *m_n)
f1f644dc 7586{
f1f644dc
JB		 7587 /*
7588 * The calculation for the data clock is:
1041a02f 7589 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7590 * But we want to avoid losing precison if possible, so:
1041a02f 7591 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7592 *
7593 * and the link clock is simpler:
1041a02f 7594 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7595 */
7596
6878da05
VS		 7597 if (!m_n->link_n)
7598 return 0;
f1f644dc 7599
6878da05
VS		 7600 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7601}
f1f644dc 7602
18442d08
VS		 7603static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7604 struct intel_crtc_config *pipe_config)
6878da05
VS		 7605{
7606 struct drm_device *dev = crtc->base.dev;
79e53945 7607
18442d08
VS		 7608 /* read out port_clock from the DPLL */
7609 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7610
f1f644dc 7611 /*
18442d08 7612 * This value does not include pixel_multiplier.
241bfc38 7613 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7614 * agree once we know their relationship in the encoder's
7615 * get_config() function.
79e53945 7616 */
241bfc38 7617 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7618 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7619 &pipe_config->fdi_m_n);
79e53945
JB		 7620}
7621
7622/** Returns the currently programmed mode of the given pipe. */
7623struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7624 struct drm_crtc *crtc)
7625{
548f245b 7626 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7628 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7629 struct drm_display_mode *mode;
f1f644dc 7630 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7631 int htot = I915_READ(HTOTAL(cpu_transcoder));
7632 int hsync = I915_READ(HSYNC(cpu_transcoder));
7633 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7634 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7635 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7636
7637 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7638 if (!mode)
7639 return NULL;
7640
f1f644dc
JB		 7641 /*
7642 * Construct a pipe_config sufficient for getting the clock info
7643 * back out of crtc_clock_get.
7644 *
7645 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7646 * to use a real value here instead.
7647 */
293623f7 7648 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7649 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7650 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7651 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7652 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7653 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7654
773ae034 7655 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7656 mode->hdisplay = (htot & 0xffff) + 1;
7657 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7658 mode->hsync_start = (hsync & 0xffff) + 1;
7659 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7660 mode->vdisplay = (vtot & 0xffff) + 1;
7661 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7662 mode->vsync_start = (vsync & 0xffff) + 1;
7663 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7664
7665 drm_mode_set_name(mode);
79e53945
JB		 7666
7667 return mode;
7668}
7669
3dec0095 7670static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7671{
7672 struct drm_device *dev = crtc->dev;
7673 drm_i915_private_t *dev_priv = dev->dev_private;
7674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7675 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7676 int dpll_reg = DPLL(pipe);
7677 int dpll;
652c393a 7678
bad720ff 7679 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7680 return;
7681
7682 if (!dev_priv->lvds_downclock_avail)
7683 return;
7684
dbdc6479 7685 dpll = I915_READ(dpll_reg);
652c393a 7686 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7687 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7688
8ac5a6d5 7689 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7690
7691 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7692 I915_WRITE(dpll_reg, dpll);
9d0498a2 7693 intel_wait_for_vblank(dev, pipe);
dbdc6479 7694
652c393a
JB		 7695 dpll = I915_READ(dpll_reg);
7696 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7697 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7698 }
652c393a
JB		 7699}
7700
7701static void intel_decrease_pllclock(struct drm_crtc *crtc)
7702{
7703 struct drm_device *dev = crtc->dev;
7704 drm_i915_private_t *dev_priv = dev->dev_private;
7705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7706
bad720ff 7707 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7708 return;
7709
7710 if (!dev_priv->lvds_downclock_avail)
7711 return;
7712
7713 /*
7714 * Since this is called by a timer, we should never get here in
7715 * the manual case.
7716 */
7717 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7718 int pipe = intel_crtc->pipe;
7719 int dpll_reg = DPLL(pipe);
7720 int dpll;
f6e5b160 7721
44d98a61 7722 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7723
8ac5a6d5 7724 assert_panel_unlocked(dev_priv, pipe);
652c393a 7725
dc257cf1 7726 dpll = I915_READ(dpll_reg);
652c393a
JB		 7727 dpll |= DISPLAY_RATE_SELECT_FPA1;
7728 I915_WRITE(dpll_reg, dpll);
9d0498a2 7729 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7730 dpll = I915_READ(dpll_reg);
7731 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7732 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7733 }
7734
7735}
7736
f047e395
CW		 7737void intel_mark_busy(struct drm_device *dev)
7738{
c67a470b
PZ		 7739 struct drm_i915_private *dev_priv = dev->dev_private;
7740
7741 hsw_package_c8_gpu_busy(dev_priv);
7742 i915_update_gfx_val(dev_priv);
f047e395
CW		 7743}
7744
7745void intel_mark_idle(struct drm_device *dev)
652c393a 7746{
c67a470b 7747 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7748 struct drm_crtc *crtc;
652c393a 7749
c67a470b
PZ		 7750 hsw_package_c8_gpu_idle(dev_priv);
7751
652c393a
JB		 7752 if (!i915_powersave)
7753 return;
7754
652c393a 7755 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7756 if (!crtc->fb)
7757 continue;
7758
725a5b54 7759 intel_decrease_pllclock(crtc);
652c393a 7760 }
b29c19b6
CW		 7761
7762 if (dev_priv->info->gen >= 6)
7763 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7764}
7765
c65355bb
CW		 7766void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7767 struct intel_ring_buffer *ring)
652c393a 7768{
f047e395
CW		 7769 struct drm_device *dev = obj->base.dev;
7770 struct drm_crtc *crtc;
652c393a 7771
f047e395 7772 if (!i915_powersave)
acb87dfb
CW		 7773 return;
7774
652c393a
JB		 7775 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7776 if (!crtc->fb)
7777 continue;
7778
c65355bb
CW		 7779 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7780 continue;
7781
7782 intel_increase_pllclock(crtc);
7783 if (ring && intel_fbc_enabled(dev))
7784 ring->fbc_dirty = true;
652c393a
JB		 7785 }
7786}
7787
79e53945
JB		 7788static void intel_crtc_destroy(struct drm_crtc *crtc)
7789{
7790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7791 struct drm_device *dev = crtc->dev;
7792 struct intel_unpin_work *work;
7793 unsigned long flags;
7794
7795 spin_lock_irqsave(&dev->event_lock, flags);
7796 work = intel_crtc->unpin_work;
7797 intel_crtc->unpin_work = NULL;
7798 spin_unlock_irqrestore(&dev->event_lock, flags);
7799
7800 if (work) {
7801 cancel_work_sync(&work->work);
7802 kfree(work);
7803 }
79e53945 7804
40ccc72b
MK		 7805 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7806
79e53945 7807 drm_crtc_cleanup(crtc);
67e77c5a 7808
79e53945
JB		 7809 kfree(intel_crtc);
7810}
7811
6b95a207
KH		 7812static void intel_unpin_work_fn(struct work_struct *__work)
7813{
7814 struct intel_unpin_work *work =
7815 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7816 struct drm_device *dev = work->crtc->dev;
6b95a207 7817
b4a98e57 7818 mutex_lock(&dev->struct_mutex);
1690e1eb 7819 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7820 drm_gem_object_unreference(&work->pending_flip_obj->base);
7821 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7822
b4a98e57
CW		 7823 intel_update_fbc(dev);
7824 mutex_unlock(&dev->struct_mutex);
7825
7826 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7827 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7828
6b95a207
KH		 7829 kfree(work);
7830}
7831
1afe3e9d 7832static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7833 struct drm_crtc *crtc)
6b95a207
KH		 7834{
7835 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7837 struct intel_unpin_work *work;
6b95a207
KH		 7838 unsigned long flags;
7839
7840 /* Ignore early vblank irqs */
7841 if (intel_crtc == NULL)
7842 return;
7843
7844 spin_lock_irqsave(&dev->event_lock, flags);
7845 work = intel_crtc->unpin_work;
e7d841ca
CW		 7846
7847 /* Ensure we don't miss a work->pending update ... */
7848 smp_rmb();
7849
7850 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7851 spin_unlock_irqrestore(&dev->event_lock, flags);
7852 return;
7853 }
7854
e7d841ca
CW		 7855 /* and that the unpin work is consistent wrt ->pending. */
7856 smp_rmb();
7857
6b95a207 7858 intel_crtc->unpin_work = NULL;
6b95a207 7859
45a066eb
RC		 7860 if (work->event)
7861 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7862
0af7e4df
MK		 7863 drm_vblank_put(dev, intel_crtc->pipe);
7864
6b95a207
KH		 7865 spin_unlock_irqrestore(&dev->event_lock, flags);
7866
2c10d571 7867 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7868
7869 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7870
7871 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7872}
7873
1afe3e9d
JB		 7874void intel_finish_page_flip(struct drm_device *dev, int pipe)
7875{
7876 drm_i915_private_t *dev_priv = dev->dev_private;
7877 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7878
49b14a5c 7879 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7880}
7881
7882void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7883{
7884 drm_i915_private_t *dev_priv = dev->dev_private;
7885 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7886
49b14a5c 7887 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7888}
7889
6b95a207
KH		 7890void intel_prepare_page_flip(struct drm_device *dev, int plane)
7891{
7892 drm_i915_private_t *dev_priv = dev->dev_private;
7893 struct intel_crtc *intel_crtc =
7894 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7895 unsigned long flags;
7896
e7d841ca
CW		 7897 /* NB: An MMIO update of the plane base pointer will also
7898 * generate a page-flip completion irq, i.e. every modeset
7899 * is also accompanied by a spurious intel_prepare_page_flip().
7900 */
6b95a207 7901 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7902 if (intel_crtc->unpin_work)
7903 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7904 spin_unlock_irqrestore(&dev->event_lock, flags);
7905}
7906
e7d841ca
CW		 7907inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7908{
7909 /* Ensure that the work item is consistent when activating it ... */
7910 smp_wmb();
7911 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7912 /* and that it is marked active as soon as the irq could fire. */
7913 smp_wmb();
7914}
7915
8c9f3aaf
JB		 7916static int intel_gen2_queue_flip(struct drm_device *dev,
7917 struct drm_crtc *crtc,
7918 struct drm_framebuffer *fb,
ed8d1975
KP		 7919 struct drm_i915_gem_object *obj,
7920 uint32_t flags)
8c9f3aaf
JB		 7921{
7922 struct drm_i915_private *dev_priv = dev->dev_private;
7923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7924 u32 flip_mask;
6d90c952 7925 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7926 int ret;
7927
6d90c952 7928 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7929 if (ret)
83d4092b 7930 goto err;
8c9f3aaf 7931
6d90c952 7932 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7933 if (ret)
83d4092b 7934 goto err_unpin;
8c9f3aaf
JB		 7935
7936 /* Can't queue multiple flips, so wait for the previous
7937 * one to finish before executing the next.
7938 */
7939 if (intel_crtc->plane)
7940 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7941 else
7942 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7943 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7944 intel_ring_emit(ring, MI_NOOP);
7945 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7946 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7947 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7948 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7949 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7950
7951 intel_mark_page_flip_active(intel_crtc);
09246732 7952 __intel_ring_advance(ring);
83d4092b
CW		 7953 return 0;
7954
7955err_unpin:
7956 intel_unpin_fb_obj(obj);
7957err:
8c9f3aaf
JB		 7958 return ret;
7959}
7960
7961static int intel_gen3_queue_flip(struct drm_device *dev,
7962 struct drm_crtc *crtc,
7963 struct drm_framebuffer *fb,
ed8d1975
KP		 7964 struct drm_i915_gem_object *obj,
7965 uint32_t flags)
8c9f3aaf
JB		 7966{
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7969 u32 flip_mask;
6d90c952 7970 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7971 int ret;
7972
6d90c952 7973 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7974 if (ret)
83d4092b 7975 goto err;
8c9f3aaf 7976
6d90c952 7977 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7978 if (ret)
83d4092b 7979 goto err_unpin;
8c9f3aaf
JB		 7980
7981 if (intel_crtc->plane)
7982 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7983 else
7984 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7985 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7986 intel_ring_emit(ring, MI_NOOP);
7987 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7988 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7989 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7990 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7991 intel_ring_emit(ring, MI_NOOP);
7992
e7d841ca 7993 intel_mark_page_flip_active(intel_crtc);
09246732 7994 __intel_ring_advance(ring);
83d4092b
CW		 7995 return 0;
7996
7997err_unpin:
7998 intel_unpin_fb_obj(obj);
7999err:
8c9f3aaf
JB		 8000 return ret;
8001}
8002
8003static int intel_gen4_queue_flip(struct drm_device *dev,
8004 struct drm_crtc *crtc,
8005 struct drm_framebuffer *fb,
ed8d1975
KP		 8006 struct drm_i915_gem_object *obj,
8007 uint32_t flags)
8c9f3aaf
JB		 8008{
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8011 uint32_t pf, pipesrc;
6d90c952 8012 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8013 int ret;
8014
6d90c952 8015 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8016 if (ret)
83d4092b 8017 goto err;
8c9f3aaf 8018
6d90c952 8019 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8020 if (ret)
83d4092b 8021 goto err_unpin;
8c9f3aaf
JB		 8022
8023 /* i965+ uses the linear or tiled offsets from the
8024 * Display Registers (which do not change across a page-flip)
8025 * so we need only reprogram the base address.
8026 */
6d90c952
DV		 8027 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8029 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8030 intel_ring_emit(ring,
f343c5f6 8031 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8032 obj->tiling_mode);
8c9f3aaf
JB		 8033
8034 /* XXX Enabling the panel-fitter across page-flip is so far
8035 * untested on non-native modes, so ignore it for now.
8036 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8037 */
8038 pf = 0;
8039 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8040 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8041
8042 intel_mark_page_flip_active(intel_crtc);
09246732 8043 __intel_ring_advance(ring);
83d4092b
CW		 8044 return 0;
8045
8046err_unpin:
8047 intel_unpin_fb_obj(obj);
8048err:
8c9f3aaf
JB		 8049 return ret;
8050}
8051
8052static int intel_gen6_queue_flip(struct drm_device *dev,
8053 struct drm_crtc *crtc,
8054 struct drm_framebuffer *fb,
ed8d1975
KP		 8055 struct drm_i915_gem_object *obj,
8056 uint32_t flags)
8c9f3aaf
JB		 8057{
8058 struct drm_i915_private *dev_priv = dev->dev_private;
8059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8060 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8061 uint32_t pf, pipesrc;
8062 int ret;
8063
6d90c952 8064 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8065 if (ret)
83d4092b 8066 goto err;
8c9f3aaf 8067
6d90c952 8068 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8069 if (ret)
83d4092b 8070 goto err_unpin;
8c9f3aaf 8071
6d90c952
DV		 8072 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8073 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8074 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8075 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8076
dc257cf1
DV		 8077 /* Contrary to the suggestions in the documentation,
8078 * "Enable Panel Fitter" does not seem to be required when page
8079 * flipping with a non-native mode, and worse causes a normal
8080 * modeset to fail.
8081 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8082 */
8083 pf = 0;
8c9f3aaf 8084 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8085 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8086
8087 intel_mark_page_flip_active(intel_crtc);
09246732 8088 __intel_ring_advance(ring);
83d4092b
CW		 8089 return 0;
8090
8091err_unpin:
8092 intel_unpin_fb_obj(obj);
8093err:
8c9f3aaf
JB		 8094 return ret;
8095}
8096
7c9017e5
JB		 8097static int intel_gen7_queue_flip(struct drm_device *dev,
8098 struct drm_crtc *crtc,
8099 struct drm_framebuffer *fb,
ed8d1975
KP		 8100 struct drm_i915_gem_object *obj,
8101 uint32_t flags)
7c9017e5
JB		 8102{
8103 struct drm_i915_private *dev_priv = dev->dev_private;
8104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8105 struct intel_ring_buffer *ring;
cb05d8de 8106 uint32_t plane_bit = 0;
ffe74d75
CW		 8107 int len, ret;
8108
8109 ring = obj->ring;
1c5fd085 8110 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8111 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8112
8113 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8114 if (ret)
83d4092b 8115 goto err;
7c9017e5 8116
cb05d8de
DV		 8117 switch(intel_crtc->plane) {
8118 case PLANE_A:
8119 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8120 break;
8121 case PLANE_B:
8122 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8123 break;
8124 case PLANE_C:
8125 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8126 break;
8127 default:
8128 WARN_ONCE(1, "unknown plane in flip command\n");
8129 ret = -ENODEV;
ab3951eb 8130 goto err_unpin;
cb05d8de
DV		 8131 }
8132
ffe74d75
CW		 8133 len = 4;
8134 if (ring->id == RCS)
8135 len += 6;
8136
8137 ret = intel_ring_begin(ring, len);
7c9017e5 8138 if (ret)
83d4092b 8139 goto err_unpin;
7c9017e5 8140
ffe74d75
CW		 8141 /* Unmask the flip-done completion message. Note that the bspec says that
8142 * we should do this for both the BCS and RCS, and that we must not unmask
8143 * more than one flip event at any time (or ensure that one flip message
8144 * can be sent by waiting for flip-done prior to queueing new flips).
8145 * Experimentation says that BCS works despite DERRMR masking all
8146 * flip-done completion events and that unmasking all planes at once
8147 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8148 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8149 */
8150 if (ring->id == RCS) {
8151 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8152 intel_ring_emit(ring, DERRMR);
8153 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8154 DERRMR_PIPEB_PRI_FLIP_DONE |
8155 DERRMR_PIPEC_PRI_FLIP_DONE));
8156 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8157 intel_ring_emit(ring, DERRMR);
8158 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8159 }
8160
cb05d8de 8161 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8162 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8163 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8164 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8165
8166 intel_mark_page_flip_active(intel_crtc);
09246732 8167 __intel_ring_advance(ring);
83d4092b
CW		 8168 return 0;
8169
8170err_unpin:
8171 intel_unpin_fb_obj(obj);
8172err:
7c9017e5
JB		 8173 return ret;
8174}
8175
8c9f3aaf
JB		 8176static int intel_default_queue_flip(struct drm_device *dev,
8177 struct drm_crtc *crtc,
8178 struct drm_framebuffer *fb,
ed8d1975
KP		 8179 struct drm_i915_gem_object *obj,
8180 uint32_t flags)
8c9f3aaf
JB		 8181{
8182 return -ENODEV;
8183}
8184
6b95a207
KH		 8185static int intel_crtc_page_flip(struct drm_crtc *crtc,
8186 struct drm_framebuffer *fb,
ed8d1975
KP		 8187 struct drm_pending_vblank_event *event,
8188 uint32_t page_flip_flags)
6b95a207
KH		 8189{
8190 struct drm_device *dev = crtc->dev;
8191 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8192 struct drm_framebuffer *old_fb = crtc->fb;
8193 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8195 struct intel_unpin_work *work;
8c9f3aaf 8196 unsigned long flags;
52e68630 8197 int ret;
6b95a207 8198
e6a595d2
VS		 8199 /* Can't change pixel format via MI display flips. */
8200 if (fb->pixel_format != crtc->fb->pixel_format)
8201 return -EINVAL;
8202
8203 /*
8204 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8205 * Note that pitch changes could also affect these register.
8206 */
8207 if (INTEL_INFO(dev)->gen > 3 &&
8208 (fb->offsets[0] != crtc->fb->offsets[0] ||
8209 fb->pitches[0] != crtc->fb->pitches[0]))
8210 return -EINVAL;
8211
b14c5679 8212 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8213 if (work == NULL)
8214 return -ENOMEM;
8215
6b95a207 8216 work->event = event;
b4a98e57 8217 work->crtc = crtc;
4a35f83b 8218 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8219 INIT_WORK(&work->work, intel_unpin_work_fn);
8220
7317c75e
JB		 8221 ret = drm_vblank_get(dev, intel_crtc->pipe);
8222 if (ret)
8223 goto free_work;
8224
6b95a207
KH		 8225 /* We borrow the event spin lock for protecting unpin_work */
8226 spin_lock_irqsave(&dev->event_lock, flags);
8227 if (intel_crtc->unpin_work) {
8228 spin_unlock_irqrestore(&dev->event_lock, flags);
8229 kfree(work);
7317c75e 8230 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8231
8232 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8233 return -EBUSY;
8234 }
8235 intel_crtc->unpin_work = work;
8236 spin_unlock_irqrestore(&dev->event_lock, flags);
8237
b4a98e57
CW		 8238 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8239 flush_workqueue(dev_priv->wq);
8240
79158103
CW		 8241 ret = i915_mutex_lock_interruptible(dev);
8242 if (ret)
8243 goto cleanup;
6b95a207 8244
75dfca80 8245 /* Reference the objects for the scheduled work. */
05394f39
CW		 8246 drm_gem_object_reference(&work->old_fb_obj->base);
8247 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8248
8249 crtc->fb = fb;
96b099fd 8250
e1f99ce6 8251 work->pending_flip_obj = obj;
e1f99ce6 8252
4e5359cd
SF		 8253 work->enable_stall_check = true;
8254
b4a98e57 8255 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8256 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8257
ed8d1975 8258 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8259 if (ret)
8260 goto cleanup_pending;
6b95a207 8261
7782de3b 8262 intel_disable_fbc(dev);
c65355bb 8263 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8264 mutex_unlock(&dev->struct_mutex);
8265
e5510fac
JB		 8266 trace_i915_flip_request(intel_crtc->plane, obj);
8267
6b95a207 8268 return 0;
96b099fd 8269
8c9f3aaf 8270cleanup_pending:
b4a98e57 8271 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8272 crtc->fb = old_fb;
05394f39
CW		 8273 drm_gem_object_unreference(&work->old_fb_obj->base);
8274 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8275 mutex_unlock(&dev->struct_mutex);
8276
79158103 8277cleanup:
96b099fd
CW		 8278 spin_lock_irqsave(&dev->event_lock, flags);
8279 intel_crtc->unpin_work = NULL;
8280 spin_unlock_irqrestore(&dev->event_lock, flags);
8281
7317c75e
JB		 8282 drm_vblank_put(dev, intel_crtc->pipe);
8283free_work:
96b099fd
CW		 8284 kfree(work);
8285
8286 return ret;
6b95a207
KH		 8287}
8288
f6e5b160 8289static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8290 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8291 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8292};
8293
50f56119
DV		 8294static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8295 struct drm_crtc *crtc)
8296{
8297 struct drm_device *dev;
8298 struct drm_crtc *tmp;
8299 int crtc_mask = 1;
47f1c6c9 8300
50f56119 8301 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8302
50f56119 8303 dev = crtc->dev;
47f1c6c9 8304
50f56119
DV		 8305 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8306 if (tmp == crtc)
8307 break;
8308 crtc_mask <<= 1;
8309 }
47f1c6c9 8310
50f56119
DV		 8311 if (encoder->possible_crtcs & crtc_mask)
8312 return true;
8313 return false;
47f1c6c9 8314}
79e53945 8315
9a935856
DV		 8316/**
8317 * intel_modeset_update_staged_output_state
8318 *
8319 * Updates the staged output configuration state, e.g. after we've read out the
8320 * current hw state.
8321 */
8322static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8323{
9a935856
DV		 8324 struct intel_encoder *encoder;
8325 struct intel_connector *connector;
f6e5b160 8326
9a935856
DV		 8327 list_for_each_entry(connector, &dev->mode_config.connector_list,
8328 base.head) {
8329 connector->new_encoder =
8330 to_intel_encoder(connector->base.encoder);
8331 }
f6e5b160 8332
9a935856
DV		 8333 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8334 base.head) {
8335 encoder->new_crtc =
8336 to_intel_crtc(encoder->base.crtc);
8337 }
f6e5b160
CW		 8338}
8339
9a935856
DV		 8340/**
8341 * intel_modeset_commit_output_state
8342 *
8343 * This function copies the stage display pipe configuration to the real one.
8344 */
8345static void intel_modeset_commit_output_state(struct drm_device *dev)
8346{
8347 struct intel_encoder *encoder;
8348 struct intel_connector *connector;
f6e5b160 8349
9a935856
DV		 8350 list_for_each_entry(connector, &dev->mode_config.connector_list,
8351 base.head) {
8352 connector->base.encoder = &connector->new_encoder->base;
8353 }
f6e5b160 8354
9a935856
DV		 8355 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8356 base.head) {
8357 encoder->base.crtc = &encoder->new_crtc->base;
8358 }
8359}
8360
050f7aeb
DV		 8361static void
8362connected_sink_compute_bpp(struct intel_connector * connector,
8363 struct intel_crtc_config *pipe_config)
8364{
8365 int bpp = pipe_config->pipe_bpp;
8366
8367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8368 connector->base.base.id,
8369 drm_get_connector_name(&connector->base));
8370
8371 /* Don't use an invalid EDID bpc value */
8372 if (connector->base.display_info.bpc &&
8373 connector->base.display_info.bpc * 3 < bpp) {
8374 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8375 bpp, connector->base.display_info.bpc*3);
8376 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8377 }
8378
8379 /* Clamp bpp to 8 on screens without EDID 1.4 */
8380 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8381 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8382 bpp);
8383 pipe_config->pipe_bpp = 24;
8384 }
8385}
8386
4e53c2e0 8387static int
050f7aeb
DV		 8388compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8389 struct drm_framebuffer *fb,
8390 struct intel_crtc_config *pipe_config)
4e53c2e0 8391{
050f7aeb
DV		 8392 struct drm_device *dev = crtc->base.dev;
8393 struct intel_connector *connector;
4e53c2e0
DV		 8394 int bpp;
8395
d42264b1
DV		 8396 switch (fb->pixel_format) {
8397 case DRM_FORMAT_C8:
4e53c2e0
DV		 8398 bpp = 8*3; /* since we go through a colormap */
8399 break;
d42264b1
DV		 8400 case DRM_FORMAT_XRGB1555:
8401 case DRM_FORMAT_ARGB1555:
8402 /* checked in intel_framebuffer_init already */
8403 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8404 return -EINVAL;
8405 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8406 bpp = 6*3; /* min is 18bpp */
8407 break;
d42264b1
DV		 8408 case DRM_FORMAT_XBGR8888:
8409 case DRM_FORMAT_ABGR8888:
8410 /* checked in intel_framebuffer_init already */
8411 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8412 return -EINVAL;
8413 case DRM_FORMAT_XRGB8888:
8414 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8415 bpp = 8*3;
8416 break;
d42264b1
DV		 8417 case DRM_FORMAT_XRGB2101010:
8418 case DRM_FORMAT_ARGB2101010:
8419 case DRM_FORMAT_XBGR2101010:
8420 case DRM_FORMAT_ABGR2101010:
8421 /* checked in intel_framebuffer_init already */
8422 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8423 return -EINVAL;
4e53c2e0
DV		 8424 bpp = 10*3;
8425 break;
baba133a 8426 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8427 default:
8428 DRM_DEBUG_KMS("unsupported depth\n");
8429 return -EINVAL;
8430 }
8431
4e53c2e0
DV		 8432 pipe_config->pipe_bpp = bpp;
8433
8434 /* Clamp display bpp to EDID value */
8435 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8436 base.head) {
1b829e05
DV		 8437 if (!connector->new_encoder ||
8438 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8439 continue;
8440
050f7aeb 8441 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8442 }
8443
8444 return bpp;
8445}
8446
644db711
DV		 8447static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8448{
8449 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8450 "type: 0x%x flags: 0x%x\n",
1342830c 8451 mode->crtc_clock,
644db711
DV		 8452 mode->crtc_hdisplay, mode->crtc_hsync_start,
8453 mode->crtc_hsync_end, mode->crtc_htotal,
8454 mode->crtc_vdisplay, mode->crtc_vsync_start,
8455 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8456}
8457
c0b03411
DV		 8458static void intel_dump_pipe_config(struct intel_crtc *crtc,
8459 struct intel_crtc_config *pipe_config,
8460 const char *context)
8461{
8462 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8463 context, pipe_name(crtc->pipe));
8464
8465 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8466 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8467 pipe_config->pipe_bpp, pipe_config->dither);
8468 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8469 pipe_config->has_pch_encoder,
8470 pipe_config->fdi_lanes,
8471 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8472 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8473 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8474 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8475 pipe_config->has_dp_encoder,
8476 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8477 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8478 pipe_config->dp_m_n.tu);
c0b03411
DV		 8479 DRM_DEBUG_KMS("requested mode:\n");
8480 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8481 DRM_DEBUG_KMS("adjusted mode:\n");
8482 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8483 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8484 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8485 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8486 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8487 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8488 pipe_config->gmch_pfit.control,
8489 pipe_config->gmch_pfit.pgm_ratios,
8490 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8491 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8492 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8493 pipe_config->pch_pfit.size,
8494 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8495 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8496 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8497}
8498
accfc0c5
DV		 8499static bool check_encoder_cloning(struct drm_crtc *crtc)
8500{
8501 int num_encoders = 0;
8502 bool uncloneable_encoders = false;
8503 struct intel_encoder *encoder;
8504
8505 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8506 base.head) {
8507 if (&encoder->new_crtc->base != crtc)
8508 continue;
8509
8510 num_encoders++;
8511 if (!encoder->cloneable)
8512 uncloneable_encoders = true;
8513 }
8514
8515 return !(num_encoders > 1 && uncloneable_encoders);
8516}
8517
b8cecdf5
DV		 8518static struct intel_crtc_config *
8519intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8520 struct drm_framebuffer *fb,
b8cecdf5 8521 struct drm_display_mode *mode)
ee7b9f93 8522{
7758a113 8523 struct drm_device *dev = crtc->dev;
7758a113 8524 struct intel_encoder *encoder;
b8cecdf5 8525 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8526 int plane_bpp, ret = -EINVAL;
8527 bool retry = true;
ee7b9f93 8528
accfc0c5
DV		 8529 if (!check_encoder_cloning(crtc)) {
8530 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8531 return ERR_PTR(-EINVAL);
8532 }
8533
b8cecdf5
DV		 8534 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8535 if (!pipe_config)
7758a113
DV		 8536 return ERR_PTR(-ENOMEM);
8537
b8cecdf5
DV		 8538 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8539 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8540
e143a21c
DV		 8541 pipe_config->cpu_transcoder =
8542 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8543 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8544
2960bc9c
ID		 8545 /*
8546 * Sanitize sync polarity flags based on requested ones. If neither
8547 * positive or negative polarity is requested, treat this as meaning
8548 * negative polarity.
8549 */
8550 if (!(pipe_config->adjusted_mode.flags &
8551 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8552 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8553
8554 if (!(pipe_config->adjusted_mode.flags &
8555 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8556 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8557
050f7aeb
DV		 8558 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8559 * plane pixel format and any sink constraints into account. Returns the
8560 * source plane bpp so that dithering can be selected on mismatches
8561 * after encoders and crtc also have had their say. */
8562 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8563 fb, pipe_config);
4e53c2e0
DV		 8564 if (plane_bpp < 0)
8565 goto fail;
8566
e41a56be
VS		 8567 /*
8568 * Determine the real pipe dimensions. Note that stereo modes can
8569 * increase the actual pipe size due to the frame doubling and
8570 * insertion of additional space for blanks between the frame. This
8571 * is stored in the crtc timings. We use the requested mode to do this
8572 * computation to clearly distinguish it from the adjusted mode, which
8573 * can be changed by the connectors in the below retry loop.
8574 */
8575 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8576 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8577 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8578
e29c22c0 8579encoder_retry:
ef1b460d 8580 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8581 pipe_config->port_clock = 0;
ef1b460d 8582 pipe_config->pixel_multiplier = 1;
ff9a6750 8583
135c81b8 8584 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8585 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8586
7758a113
DV		 8587 /* Pass our mode to the connectors and the CRTC to give them a chance to
8588 * adjust it according to limitations or connector properties, and also
8589 * a chance to reject the mode entirely.
47f1c6c9 8590 */
7758a113
DV		 8591 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8592 base.head) {
47f1c6c9 8593
7758a113
DV		 8594 if (&encoder->new_crtc->base != crtc)
8595 continue;
7ae89233 8596
efea6e8e
DV		 8597 if (!(encoder->compute_config(encoder, pipe_config))) {
8598 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8599 goto fail;
8600 }
ee7b9f93 8601 }
47f1c6c9 8602
ff9a6750
DV		 8603 /* Set default port clock if not overwritten by the encoder. Needs to be
8604 * done afterwards in case the encoder adjusts the mode. */
8605 if (!pipe_config->port_clock)
241bfc38
DL		 8606 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8607 * pipe_config->pixel_multiplier;
ff9a6750 8608
a43f6e0f 8609 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8610 if (ret < 0) {
7758a113
DV		 8611 DRM_DEBUG_KMS("CRTC fixup failed\n");
8612 goto fail;
ee7b9f93 8613 }
e29c22c0
DV		 8614
8615 if (ret == RETRY) {
8616 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8617 ret = -EINVAL;
8618 goto fail;
8619 }
8620
8621 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8622 retry = false;
8623 goto encoder_retry;
8624 }
8625
4e53c2e0
DV		 8626 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8627 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8628 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8629
b8cecdf5 8630 return pipe_config;
7758a113 8631fail:
b8cecdf5 8632 kfree(pipe_config);
e29c22c0 8633 return ERR_PTR(ret);
ee7b9f93 8634}
47f1c6c9 8635
e2e1ed41
DV		 8636/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8637 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8638static void
8639intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8640 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8641{
8642 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8643 struct drm_device *dev = crtc->dev;
8644 struct intel_encoder *encoder;
8645 struct intel_connector *connector;
8646 struct drm_crtc *tmp_crtc;
79e53945 8647
e2e1ed41 8648 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8649
e2e1ed41
DV		 8650 /* Check which crtcs have changed outputs connected to them, these need
8651 * to be part of the prepare_pipes mask. We don't (yet) support global
8652 * modeset across multiple crtcs, so modeset_pipes will only have one
8653 * bit set at most. */
8654 list_for_each_entry(connector, &dev->mode_config.connector_list,
8655 base.head) {
8656 if (connector->base.encoder == &connector->new_encoder->base)
8657 continue;
79e53945 8658
e2e1ed41
DV		 8659 if (connector->base.encoder) {
8660 tmp_crtc = connector->base.encoder->crtc;
8661
8662 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8663 }
8664
8665 if (connector->new_encoder)
8666 *prepare_pipes |=
8667 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8668 }
8669
e2e1ed41
DV		 8670 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8671 base.head) {
8672 if (encoder->base.crtc == &encoder->new_crtc->base)
8673 continue;
8674
8675 if (encoder->base.crtc) {
8676 tmp_crtc = encoder->base.crtc;
8677
8678 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8679 }
8680
8681 if (encoder->new_crtc)
8682 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8683 }
8684
e2e1ed41
DV		 8685 /* Check for any pipes that will be fully disabled ... */
8686 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8687 base.head) {
8688 bool used = false;
22fd0fab 8689
e2e1ed41
DV		 8690 /* Don't try to disable disabled crtcs. */
8691 if (!intel_crtc->base.enabled)
8692 continue;
7e7d76c3 8693
e2e1ed41
DV		 8694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8695 base.head) {
8696 if (encoder->new_crtc == intel_crtc)
8697 used = true;
8698 }
8699
8700 if (!used)
8701 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8702 }
8703
e2e1ed41
DV		 8704
8705 /* set_mode is also used to update properties on life display pipes. */
8706 intel_crtc = to_intel_crtc(crtc);
8707 if (crtc->enabled)
8708 *prepare_pipes |= 1 << intel_crtc->pipe;
8709
b6c5164d
DV		 8710 /*
8711 * For simplicity do a full modeset on any pipe where the output routing
8712 * changed. We could be more clever, but that would require us to be
8713 * more careful with calling the relevant encoder->mode_set functions.
8714 */
e2e1ed41
DV		 8715 if (*prepare_pipes)
8716 *modeset_pipes = *prepare_pipes;
8717
8718 /* ... and mask these out. */
8719 *modeset_pipes &= ~(*disable_pipes);
8720 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8721
8722 /*
8723 * HACK: We don't (yet) fully support global modesets. intel_set_config
8724 * obies this rule, but the modeset restore mode of
8725 * intel_modeset_setup_hw_state does not.
8726 */
8727 *modeset_pipes &= 1 << intel_crtc->pipe;
8728 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8729
8730 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8731 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8732}
79e53945 8733
ea9d758d 8734static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8735{
ea9d758d 8736 struct drm_encoder *encoder;
f6e5b160 8737 struct drm_device *dev = crtc->dev;
f6e5b160 8738
ea9d758d
DV		 8739 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8740 if (encoder->crtc == crtc)
8741 return true;
8742
8743 return false;
8744}
8745
8746static void
8747intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8748{
8749 struct intel_encoder *intel_encoder;
8750 struct intel_crtc *intel_crtc;
8751 struct drm_connector *connector;
8752
8753 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8754 base.head) {
8755 if (!intel_encoder->base.crtc)
8756 continue;
8757
8758 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8759
8760 if (prepare_pipes & (1 << intel_crtc->pipe))
8761 intel_encoder->connectors_active = false;
8762 }
8763
8764 intel_modeset_commit_output_state(dev);
8765
8766 /* Update computed state. */
8767 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8768 base.head) {
8769 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8770 }
8771
8772 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8773 if (!connector->encoder || !connector->encoder->crtc)
8774 continue;
8775
8776 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8777
8778 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8779 struct drm_property *dpms_property =
8780 dev->mode_config.dpms_property;
8781
ea9d758d 8782 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8783 drm_object_property_set_value(&connector->base,
68d34720
DV		 8784 dpms_property,
8785 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8786
8787 intel_encoder = to_intel_encoder(connector->encoder);
8788 intel_encoder->connectors_active = true;
8789 }
8790 }
8791
8792}
8793
3bd26263 8794static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8795{
3bd26263 8796 int diff;
f1f644dc
JB		 8797
8798 if (clock1 == clock2)
8799 return true;
8800
8801 if (!clock1 || !clock2)
8802 return false;
8803
8804 diff = abs(clock1 - clock2);
8805
8806 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8807 return true;
8808
8809 return false;
8810}
8811
25c5b266
DV		 8812#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8813 list_for_each_entry((intel_crtc), \
8814 &(dev)->mode_config.crtc_list, \
8815 base.head) \
0973f18f 8816 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8817
0e8ffe1b 8818static bool
2fa2fe9a
DV		 8819intel_pipe_config_compare(struct drm_device *dev,
8820 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8821 struct intel_crtc_config *pipe_config)
8822{
66e985c0
DV		 8823#define PIPE_CONF_CHECK_X(name) \
8824 if (current_config->name != pipe_config->name) { \
8825 DRM_ERROR("mismatch in " #name " " \
8826 "(expected 0x%08x, found 0x%08x)\n", \
8827 current_config->name, \
8828 pipe_config->name); \
8829 return false; \
8830 }
8831
08a24034
DV		 8832#define PIPE_CONF_CHECK_I(name) \
8833 if (current_config->name != pipe_config->name) { \
8834 DRM_ERROR("mismatch in " #name " " \
8835 "(expected %i, found %i)\n", \
8836 current_config->name, \
8837 pipe_config->name); \
8838 return false; \
88adfff1
DV		 8839 }
8840
1bd1bd80
DV		 8841#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8842 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8843 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8844 "(expected %i, found %i)\n", \
8845 current_config->name & (mask), \
8846 pipe_config->name & (mask)); \
8847 return false; \
8848 }
8849
5e550656
VS		 8850#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8851 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8852 DRM_ERROR("mismatch in " #name " " \
8853 "(expected %i, found %i)\n", \
8854 current_config->name, \
8855 pipe_config->name); \
8856 return false; \
8857 }
8858
bb760063
DV		 8859#define PIPE_CONF_QUIRK(quirk) \
8860 ((current_config->quirks | pipe_config->quirks) & (quirk))
8861
eccb140b
DV		 8862 PIPE_CONF_CHECK_I(cpu_transcoder);
8863
08a24034
DV		 8864 PIPE_CONF_CHECK_I(has_pch_encoder);
8865 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8866 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8867 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8868 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8869 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8870 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8871
eb14cb74
VS		 8872 PIPE_CONF_CHECK_I(has_dp_encoder);
8873 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8874 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8875 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8876 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8877 PIPE_CONF_CHECK_I(dp_m_n.tu);
8878
1bd1bd80
DV		 8879 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8880 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8885
8886 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8887 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8888 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8889 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8890 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8891 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8892
c93f54cf 8893 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8894
1bd1bd80
DV		 8895 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8896 DRM_MODE_FLAG_INTERLACE);
8897
bb760063
DV		 8898 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8899 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8900 DRM_MODE_FLAG_PHSYNC);
8901 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8902 DRM_MODE_FLAG_NHSYNC);
8903 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8904 DRM_MODE_FLAG_PVSYNC);
8905 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8906 DRM_MODE_FLAG_NVSYNC);
8907 }
045ac3b5 8908
37327abd
VS		 8909 PIPE_CONF_CHECK_I(pipe_src_w);
8910 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8911
2fa2fe9a
DV		 8912 PIPE_CONF_CHECK_I(gmch_pfit.control);
8913 /* pfit ratios are autocomputed by the hw on gen4+ */
8914 if (INTEL_INFO(dev)->gen < 4)
8915 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8916 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8917 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8918 if (current_config->pch_pfit.enabled) {
8919 PIPE_CONF_CHECK_I(pch_pfit.pos);
8920 PIPE_CONF_CHECK_I(pch_pfit.size);
8921 }
2fa2fe9a 8922
42db64ef
PZ		 8923 PIPE_CONF_CHECK_I(ips_enabled);
8924
282740f7
VS		 8925 PIPE_CONF_CHECK_I(double_wide);
8926
c0d43d62 8927 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8928 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8929 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8930 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8931 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8932
42571aef
VS		 8933 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8934 PIPE_CONF_CHECK_I(pipe_bpp);
8935
d71b8d4a 8936 if (!IS_HASWELL(dev)) {
241bfc38 8937 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8938 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8939 }
5e550656 8940
66e985c0 8941#undef PIPE_CONF_CHECK_X
08a24034 8942#undef PIPE_CONF_CHECK_I
1bd1bd80 8943#undef PIPE_CONF_CHECK_FLAGS
5e550656 8944#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8945#undef PIPE_CONF_QUIRK
88adfff1 8946
0e8ffe1b
DV		 8947 return true;
8948}
8949
91d1b4bd
DV		 8950static void
8951check_connector_state(struct drm_device *dev)
8af6cf88 8952{
8af6cf88
DV		 8953 struct intel_connector *connector;
8954
8955 list_for_each_entry(connector, &dev->mode_config.connector_list,
8956 base.head) {
8957 /* This also checks the encoder/connector hw state with the
8958 * ->get_hw_state callbacks. */
8959 intel_connector_check_state(connector);
8960
8961 WARN(&connector->new_encoder->base != connector->base.encoder,
8962 "connector's staged encoder doesn't match current encoder\n");
8963 }
91d1b4bd
DV		 8964}
8965
8966static void
8967check_encoder_state(struct drm_device *dev)
8968{
8969 struct intel_encoder *encoder;
8970 struct intel_connector *connector;
8af6cf88
DV		 8971
8972 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8973 base.head) {
8974 bool enabled = false;
8975 bool active = false;
8976 enum pipe pipe, tracked_pipe;
8977
8978 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8979 encoder->base.base.id,
8980 drm_get_encoder_name(&encoder->base));
8981
8982 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8983 "encoder's stage crtc doesn't match current crtc\n");
8984 WARN(encoder->connectors_active && !encoder->base.crtc,
8985 "encoder's active_connectors set, but no crtc\n");
8986
8987 list_for_each_entry(connector, &dev->mode_config.connector_list,
8988 base.head) {
8989 if (connector->base.encoder != &encoder->base)
8990 continue;
8991 enabled = true;
8992 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8993 active = true;
8994 }
8995 WARN(!!encoder->base.crtc != enabled,
8996 "encoder's enabled state mismatch "
8997 "(expected %i, found %i)\n",
8998 !!encoder->base.crtc, enabled);
8999 WARN(active && !encoder->base.crtc,
9000 "active encoder with no crtc\n");
9001
9002 WARN(encoder->connectors_active != active,
9003 "encoder's computed active state doesn't match tracked active state "
9004 "(expected %i, found %i)\n", active, encoder->connectors_active);
9005
9006 active = encoder->get_hw_state(encoder, &pipe);
9007 WARN(active != encoder->connectors_active,
9008 "encoder's hw state doesn't match sw tracking "
9009 "(expected %i, found %i)\n",
9010 encoder->connectors_active, active);
9011
9012 if (!encoder->base.crtc)
9013 continue;
9014
9015 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9016 WARN(active && pipe != tracked_pipe,
9017 "active encoder's pipe doesn't match"
9018 "(expected %i, found %i)\n",
9019 tracked_pipe, pipe);
9020
9021 }
91d1b4bd
DV		 9022}
9023
9024static void
9025check_crtc_state(struct drm_device *dev)
9026{
9027 drm_i915_private_t *dev_priv = dev->dev_private;
9028 struct intel_crtc *crtc;
9029 struct intel_encoder *encoder;
9030 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9031
9032 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9033 base.head) {
9034 bool enabled = false;
9035 bool active = false;
9036
045ac3b5
JB		 9037 memset(&pipe_config, 0, sizeof(pipe_config));
9038
8af6cf88
DV		 9039 DRM_DEBUG_KMS("[CRTC:%d]\n",
9040 crtc->base.base.id);
9041
9042 WARN(crtc->active && !crtc->base.enabled,
9043 "active crtc, but not enabled in sw tracking\n");
9044
9045 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9046 base.head) {
9047 if (encoder->base.crtc != &crtc->base)
9048 continue;
9049 enabled = true;
9050 if (encoder->connectors_active)
9051 active = true;
9052 }
6c49f241 9053
8af6cf88
DV		 9054 WARN(active != crtc->active,
9055 "crtc's computed active state doesn't match tracked active state "
9056 "(expected %i, found %i)\n", active, crtc->active);
9057 WARN(enabled != crtc->base.enabled,
9058 "crtc's computed enabled state doesn't match tracked enabled state "
9059 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9060
0e8ffe1b
DV		 9061 active = dev_priv->display.get_pipe_config(crtc,
9062 &pipe_config);
d62cf62a
DV		 9063
9064 /* hw state is inconsistent with the pipe A quirk */
9065 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9066 active = crtc->active;
9067
6c49f241
DV		 9068 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9069 base.head) {
3eaba51c 9070 enum pipe pipe;
6c49f241
DV		 9071 if (encoder->base.crtc != &crtc->base)
9072 continue;
3eaba51c
VS		 9073 if (encoder->get_config &&
9074 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9075 encoder->get_config(encoder, &pipe_config);
9076 }
9077
0e8ffe1b
DV		 9078 WARN(crtc->active != active,
9079 "crtc active state doesn't match with hw state "
9080 "(expected %i, found %i)\n", crtc->active, active);
9081
c0b03411
DV		 9082 if (active &&
9083 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9084 WARN(1, "pipe state doesn't match!\n");
9085 intel_dump_pipe_config(crtc, &pipe_config,
9086 "[hw state]");
9087 intel_dump_pipe_config(crtc, &crtc->config,
9088 "[sw state]");
9089 }
8af6cf88
DV		 9090 }
9091}
9092
91d1b4bd
DV		 9093static void
9094check_shared_dpll_state(struct drm_device *dev)
9095{
9096 drm_i915_private_t *dev_priv = dev->dev_private;
9097 struct intel_crtc *crtc;
9098 struct intel_dpll_hw_state dpll_hw_state;
9099 int i;
5358901f
DV		 9100
9101 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9102 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9103 int enabled_crtcs = 0, active_crtcs = 0;
9104 bool active;
9105
9106 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9107
9108 DRM_DEBUG_KMS("%s\n", pll->name);
9109
9110 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9111
9112 WARN(pll->active > pll->refcount,
9113 "more active pll users than references: %i vs %i\n",
9114 pll->active, pll->refcount);
9115 WARN(pll->active && !pll->on,
9116 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9117 WARN(pll->on && !pll->active,
9118 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9119 WARN(pll->on != active,
9120 "pll on state mismatch (expected %i, found %i)\n",
9121 pll->on, active);
9122
9123 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9124 base.head) {
9125 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9126 enabled_crtcs++;
9127 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9128 active_crtcs++;
9129 }
9130 WARN(pll->active != active_crtcs,
9131 "pll active crtcs mismatch (expected %i, found %i)\n",
9132 pll->active, active_crtcs);
9133 WARN(pll->refcount != enabled_crtcs,
9134 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9135 pll->refcount, enabled_crtcs);
66e985c0
DV		 9136
9137 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9138 sizeof(dpll_hw_state)),
9139 "pll hw state mismatch\n");
5358901f 9140 }
8af6cf88
DV		 9141}
9142
91d1b4bd
DV		 9143void
9144intel_modeset_check_state(struct drm_device *dev)
9145{
9146 check_connector_state(dev);
9147 check_encoder_state(dev);
9148 check_crtc_state(dev);
9149 check_shared_dpll_state(dev);
9150}
9151
18442d08
VS		 9152void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9153 int dotclock)
9154{
9155 /*
9156 * FDI already provided one idea for the dotclock.
9157 * Yell if the encoder disagrees.
9158 */
241bfc38 9159 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9160 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9161 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9162}
9163
f30da187
DV		 9164static int __intel_set_mode(struct drm_crtc *crtc,
9165 struct drm_display_mode *mode,
9166 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9167{
9168 struct drm_device *dev = crtc->dev;
dbf2b54e 9169 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9170 struct drm_display_mode *saved_mode, *saved_hwmode;
9171 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9172 struct intel_crtc *intel_crtc;
9173 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9174 int ret = 0;
a6778b3c 9175
a1e22653 9176 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9177 if (!saved_mode)
9178 return -ENOMEM;
3ac18232 9179 saved_hwmode = saved_mode + 1;
a6778b3c 9180
e2e1ed41 9181 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9182 &prepare_pipes, &disable_pipes);
9183
3ac18232
TG		 9184 *saved_hwmode = crtc->hwmode;
9185 *saved_mode = crtc->mode;
a6778b3c 9186
25c5b266
DV		 9187 /* Hack: Because we don't (yet) support global modeset on multiple
9188 * crtcs, we don't keep track of the new mode for more than one crtc.
9189 * Hence simply check whether any bit is set in modeset_pipes in all the
9190 * pieces of code that are not yet converted to deal with mutliple crtcs
9191 * changing their mode at the same time. */
25c5b266 9192 if (modeset_pipes) {
4e53c2e0 9193 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9194 if (IS_ERR(pipe_config)) {
9195 ret = PTR_ERR(pipe_config);
9196 pipe_config = NULL;
9197
3ac18232 9198 goto out;
25c5b266 9199 }
c0b03411
DV		 9200 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9201 "[modeset]");
25c5b266 9202 }
a6778b3c 9203
460da916
DV		 9204 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9205 intel_crtc_disable(&intel_crtc->base);
9206
ea9d758d
DV		 9207 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9208 if (intel_crtc->base.enabled)
9209 dev_priv->display.crtc_disable(&intel_crtc->base);
9210 }
a6778b3c 9211
6c4c86f5
DV		 9212 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9213 * to set it here already despite that we pass it down the callchain.
f6e5b160 9214 */
b8cecdf5 9215 if (modeset_pipes) {
25c5b266 9216 crtc->mode = *mode;
b8cecdf5
DV		 9217 /* mode_set/enable/disable functions rely on a correct pipe
9218 * config. */
9219 to_intel_crtc(crtc)->config = *pipe_config;
9220 }
7758a113 9221
ea9d758d
DV		 9222 /* Only after disabling all output pipelines that will be changed can we
9223 * update the the output configuration. */
9224 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9225
47fab737
DV		 9226 if (dev_priv->display.modeset_global_resources)
9227 dev_priv->display.modeset_global_resources(dev);
9228
a6778b3c
DV		 9229 /* Set up the DPLL and any encoders state that needs to adjust or depend
9230 * on the DPLL.
f6e5b160 9231 */
25c5b266 9232 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9233 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9234 x, y, fb);
9235 if (ret)
9236 goto done;
a6778b3c
DV		 9237 }
9238
9239 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9240 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9241 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9242
25c5b266
DV		 9243 if (modeset_pipes) {
9244 /* Store real post-adjustment hardware mode. */
b8cecdf5 9245 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9246
25c5b266
DV		 9247 /* Calculate and store various constants which
9248 * are later needed by vblank and swap-completion
9249 * timestamping. They are derived from true hwmode.
9250 */
9251 drm_calc_timestamping_constants(crtc);
9252 }
a6778b3c
DV		 9253
9254 /* FIXME: add subpixel order */
9255done:
c0c36b94 9256 if (ret && crtc->enabled) {
3ac18232
TG		 9257 crtc->hwmode = *saved_hwmode;
9258 crtc->mode = *saved_mode;
a6778b3c
DV		 9259 }
9260
3ac18232 9261out:
b8cecdf5 9262 kfree(pipe_config);
3ac18232 9263 kfree(saved_mode);
a6778b3c 9264 return ret;
f6e5b160
CW		 9265}
9266
e7457a9a
DL		 9267static int intel_set_mode(struct drm_crtc *crtc,
9268 struct drm_display_mode *mode,
9269 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9270{
9271 int ret;
9272
9273 ret = __intel_set_mode(crtc, mode, x, y, fb);
9274
9275 if (ret == 0)
9276 intel_modeset_check_state(crtc->dev);
9277
9278 return ret;
9279}
9280
c0c36b94
CW		 9281void intel_crtc_restore_mode(struct drm_crtc *crtc)
9282{
9283 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9284}
9285
25c5b266
DV		 9286#undef for_each_intel_crtc_masked
9287
d9e55608
DV		 9288static void intel_set_config_free(struct intel_set_config *config)
9289{
9290 if (!config)
9291 return;
9292
1aa4b628
DV		 9293 kfree(config->save_connector_encoders);
9294 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9295 kfree(config);
9296}
9297
85f9eb71
DV		 9298static int intel_set_config_save_state(struct drm_device *dev,
9299 struct intel_set_config *config)
9300{
85f9eb71
DV		 9301 struct drm_encoder *encoder;
9302 struct drm_connector *connector;
9303 int count;
9304
1aa4b628
DV		 9305 config->save_encoder_crtcs =
9306 kcalloc(dev->mode_config.num_encoder,
9307 sizeof(struct drm_crtc *), GFP_KERNEL);
9308 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9309 return -ENOMEM;
9310
1aa4b628
DV		 9311 config->save_connector_encoders =
9312 kcalloc(dev->mode_config.num_connector,
9313 sizeof(struct drm_encoder *), GFP_KERNEL);
9314 if (!config->save_connector_encoders)
85f9eb71
DV		 9315 return -ENOMEM;
9316
9317 /* Copy data. Note that driver private data is not affected.
9318 * Should anything bad happen only the expected state is
9319 * restored, not the drivers personal bookkeeping.
9320 */
85f9eb71
DV		 9321 count = 0;
9322 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9323 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9324 }
9325
9326 count = 0;
9327 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9328 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9329 }
9330
9331 return 0;
9332}
9333
9334static void intel_set_config_restore_state(struct drm_device *dev,
9335 struct intel_set_config *config)
9336{
9a935856
DV		 9337 struct intel_encoder *encoder;
9338 struct intel_connector *connector;
85f9eb71
DV		 9339 int count;
9340
85f9eb71 9341 count = 0;
9a935856
DV		 9342 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9343 encoder->new_crtc =
9344 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9345 }
9346
9347 count = 0;
9a935856
DV		 9348 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9349 connector->new_encoder =
9350 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9351 }
9352}
9353
e3de42b6 9354static bool
2e57f47d 9355is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9356{
9357 int i;
9358
2e57f47d
CW		 9359 if (set->num_connectors == 0)
9360 return false;
9361
9362 if (WARN_ON(set->connectors == NULL))
9363 return false;
9364
9365 for (i = 0; i < set->num_connectors; i++)
9366 if (set->connectors[i]->encoder &&
9367 set->connectors[i]->encoder->crtc == set->crtc &&
9368 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9369 return true;
9370
9371 return false;
9372}
9373
5e2b584e
DV		 9374static void
9375intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9376 struct intel_set_config *config)
9377{
9378
9379 /* We should be able to check here if the fb has the same properties
9380 * and then just flip_or_move it */
2e57f47d
CW		 9381 if (is_crtc_connector_off(set)) {
9382 config->mode_changed = true;
e3de42b6 9383 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9384 /* If we have no fb then treat it as a full mode set */
9385 if (set->crtc->fb == NULL) {
319d9827
JB		 9386 struct intel_crtc *intel_crtc =
9387 to_intel_crtc(set->crtc);
9388
9389 if (intel_crtc->active && i915_fastboot) {
9390 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9391 config->fb_changed = true;
9392 } else {
9393 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9394 config->mode_changed = true;
9395 }
5e2b584e
DV		 9396 } else if (set->fb == NULL) {
9397 config->mode_changed = true;
72f4901e
DV		 9398 } else if (set->fb->pixel_format !=
9399 set->crtc->fb->pixel_format) {
5e2b584e 9400 config->mode_changed = true;
e3de42b6 9401 } else {
5e2b584e 9402 config->fb_changed = true;
e3de42b6 9403 }
5e2b584e
DV		 9404 }
9405
835c5873 9406 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9407 config->fb_changed = true;
9408
9409 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9410 DRM_DEBUG_KMS("modes are different, full mode set\n");
9411 drm_mode_debug_printmodeline(&set->crtc->mode);
9412 drm_mode_debug_printmodeline(set->mode);
9413 config->mode_changed = true;
9414 }
a1d95703
CW		 9415
9416 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9417 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9418}
9419
2e431051 9420static int
9a935856
DV		 9421intel_modeset_stage_output_state(struct drm_device *dev,
9422 struct drm_mode_set *set,
9423 struct intel_set_config *config)
50f56119 9424{
85f9eb71 9425 struct drm_crtc *new_crtc;
9a935856
DV		 9426 struct intel_connector *connector;
9427 struct intel_encoder *encoder;
f3f08572 9428 int ro;
50f56119 9429
9abdda74 9430 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9431 * of connectors. For paranoia, double-check this. */
9432 WARN_ON(!set->fb && (set->num_connectors != 0));
9433 WARN_ON(set->fb && (set->num_connectors == 0));
9434
9a935856
DV		 9435 list_for_each_entry(connector, &dev->mode_config.connector_list,
9436 base.head) {
9437 /* Otherwise traverse passed in connector list and get encoders
9438 * for them. */
50f56119 9439 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9440 if (set->connectors[ro] == &connector->base) {
9441 connector->new_encoder = connector->encoder;
50f56119
DV		 9442 break;
9443 }
9444 }
9445
9a935856
DV		 9446 /* If we disable the crtc, disable all its connectors. Also, if
9447 * the connector is on the changing crtc but not on the new
9448 * connector list, disable it. */
9449 if ((!set->fb || ro == set->num_connectors) &&
9450 connector->base.encoder &&
9451 connector->base.encoder->crtc == set->crtc) {
9452 connector->new_encoder = NULL;
9453
9454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9455 connector->base.base.id,
9456 drm_get_connector_name(&connector->base));
9457 }
9458
9459
9460 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9461 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9462 config->mode_changed = true;
50f56119
DV		 9463 }
9464 }
9a935856 9465 /* connector->new_encoder is now updated for all connectors. */
50f56119 9466
9a935856 9467 /* Update crtc of enabled connectors. */
9a935856
DV		 9468 list_for_each_entry(connector, &dev->mode_config.connector_list,
9469 base.head) {
9470 if (!connector->new_encoder)
50f56119
DV		 9471 continue;
9472
9a935856 9473 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9474
9475 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9476 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9477 new_crtc = set->crtc;
9478 }
9479
9480 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9481 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9482 new_crtc)) {
5e2b584e 9483 return -EINVAL;
50f56119 9484 }
9a935856
DV		 9485 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9486
9487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9488 connector->base.base.id,
9489 drm_get_connector_name(&connector->base),
9490 new_crtc->base.id);
9491 }
9492
9493 /* Check for any encoders that needs to be disabled. */
9494 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9495 base.head) {
9496 list_for_each_entry(connector,
9497 &dev->mode_config.connector_list,
9498 base.head) {
9499 if (connector->new_encoder == encoder) {
9500 WARN_ON(!connector->new_encoder->new_crtc);
9501
9502 goto next_encoder;
9503 }
9504 }
9505 encoder->new_crtc = NULL;
9506next_encoder:
9507 /* Only now check for crtc changes so we don't miss encoders
9508 * that will be disabled. */
9509 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9510 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9511 config->mode_changed = true;
50f56119
DV		 9512 }
9513 }
9a935856 9514 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9515
2e431051
DV		 9516 return 0;
9517}
9518
9519static int intel_crtc_set_config(struct drm_mode_set *set)
9520{
9521 struct drm_device *dev;
2e431051
DV		 9522 struct drm_mode_set save_set;
9523 struct intel_set_config *config;
9524 int ret;
2e431051 9525
8d3e375e
DV		 9526 BUG_ON(!set);
9527 BUG_ON(!set->crtc);
9528 BUG_ON(!set->crtc->helper_private);
2e431051 9529
7e53f3a4
DV		 9530 /* Enforce sane interface api - has been abused by the fb helper. */
9531 BUG_ON(!set->mode && set->fb);
9532 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9533
2e431051
DV		 9534 if (set->fb) {
9535 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9536 set->crtc->base.id, set->fb->base.id,
9537 (int)set->num_connectors, set->x, set->y);
9538 } else {
9539 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9540 }
9541
9542 dev = set->crtc->dev;
9543
9544 ret = -ENOMEM;
9545 config = kzalloc(sizeof(*config), GFP_KERNEL);
9546 if (!config)
9547 goto out_config;
9548
9549 ret = intel_set_config_save_state(dev, config);
9550 if (ret)
9551 goto out_config;
9552
9553 save_set.crtc = set->crtc;
9554 save_set.mode = &set->crtc->mode;
9555 save_set.x = set->crtc->x;
9556 save_set.y = set->crtc->y;
9557 save_set.fb = set->crtc->fb;
9558
9559 /* Compute whether we need a full modeset, only an fb base update or no
9560 * change at all. In the future we might also check whether only the
9561 * mode changed, e.g. for LVDS where we only change the panel fitter in
9562 * such cases. */
9563 intel_set_config_compute_mode_changes(set, config);
9564
9a935856 9565 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9566 if (ret)
9567 goto fail;
9568
5e2b584e 9569 if (config->mode_changed) {
c0c36b94
CW		 9570 ret = intel_set_mode(set->crtc, set->mode,
9571 set->x, set->y, set->fb);
5e2b584e 9572 } else if (config->fb_changed) {
4878cae2
VS		 9573 intel_crtc_wait_for_pending_flips(set->crtc);
9574
4f660f49 9575 ret = intel_pipe_set_base(set->crtc,
94352cf9 9576 set->x, set->y, set->fb);
50f56119
DV		 9577 }
9578
2d05eae1 9579 if (ret) {
bf67dfeb
DV		 9580 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9581 set->crtc->base.id, ret);
50f56119 9582fail:
2d05eae1 9583 intel_set_config_restore_state(dev, config);
50f56119 9584
2d05eae1
CW		 9585 /* Try to restore the config */
9586 if (config->mode_changed &&
9587 intel_set_mode(save_set.crtc, save_set.mode,
9588 save_set.x, save_set.y, save_set.fb))
9589 DRM_ERROR("failed to restore config after modeset failure\n");
9590 }
50f56119 9591
d9e55608
DV		 9592out_config:
9593 intel_set_config_free(config);
50f56119
DV		 9594 return ret;
9595}
f6e5b160
CW		 9596
9597static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9598 .cursor_set = intel_crtc_cursor_set,
9599 .cursor_move = intel_crtc_cursor_move,
9600 .gamma_set = intel_crtc_gamma_set,
50f56119 9601 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9602 .destroy = intel_crtc_destroy,
9603 .page_flip = intel_crtc_page_flip,
9604};
9605
79f689aa
PZ		 9606static void intel_cpu_pll_init(struct drm_device *dev)
9607{
affa9354 9608 if (HAS_DDI(dev))
79f689aa
PZ		 9609 intel_ddi_pll_init(dev);
9610}
9611
5358901f
DV		 9612static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9613 struct intel_shared_dpll *pll,
9614 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9615{
5358901f 9616 uint32_t val;
ee7b9f93 9617
5358901f 9618 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9619 hw_state->dpll = val;
9620 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9621 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9622
9623 return val & DPLL_VCO_ENABLE;
9624}
9625
15bdd4cf
DV		 9626static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9627 struct intel_shared_dpll *pll)
9628{
9629 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9630 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9631}
9632
e7b903d2
DV		 9633static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9634 struct intel_shared_dpll *pll)
9635{
e7b903d2
DV		 9636 /* PCH refclock must be enabled first */
9637 assert_pch_refclk_enabled(dev_priv);
9638
15bdd4cf
DV		 9639 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9640
9641 /* Wait for the clocks to stabilize. */
9642 POSTING_READ(PCH_DPLL(pll->id));
9643 udelay(150);
9644
9645 /* The pixel multiplier can only be updated once the
9646 * DPLL is enabled and the clocks are stable.
9647 *
9648 * So write it again.
9649 */
9650 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9651 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9652 udelay(200);
9653}
9654
9655static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9656 struct intel_shared_dpll *pll)
9657{
9658 struct drm_device *dev = dev_priv->dev;
9659 struct intel_crtc *crtc;
e7b903d2
DV		 9660
9661 /* Make sure no transcoder isn't still depending on us. */
9662 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9663 if (intel_crtc_to_shared_dpll(crtc) == pll)
9664 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9665 }
9666
15bdd4cf
DV		 9667 I915_WRITE(PCH_DPLL(pll->id), 0);
9668 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9669 udelay(200);
9670}
9671
46edb027
DV		 9672static char *ibx_pch_dpll_names[] = {
9673 "PCH DPLL A",
9674 "PCH DPLL B",
9675};
9676
7c74ade1 9677static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9678{
e7b903d2 9679 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9680 int i;
9681
7c74ade1 9682 dev_priv->num_shared_dpll = 2;
ee7b9f93 9683
e72f9fbf 9684 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9685 dev_priv->shared_dplls[i].id = i;
9686 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9687 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9688 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9689 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9690 dev_priv->shared_dplls[i].get_hw_state =
9691 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9692 }
9693}
9694
7c74ade1
DV		 9695static void intel_shared_dpll_init(struct drm_device *dev)
9696{
e7b903d2 9697 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9698
9699 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9700 ibx_pch_dpll_init(dev);
9701 else
9702 dev_priv->num_shared_dpll = 0;
9703
9704 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9705 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9706 dev_priv->num_shared_dpll);
9707}
9708
b358d0a6 9709static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9710{
22fd0fab 9711 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9712 struct intel_crtc *intel_crtc;
9713 int i;
9714
955382f3 9715 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9716 if (intel_crtc == NULL)
9717 return;
9718
9719 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9720
9721 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9722 for (i = 0; i < 256; i++) {
9723 intel_crtc->lut_r[i] = i;
9724 intel_crtc->lut_g[i] = i;
9725 intel_crtc->lut_b[i] = i;
9726 }
9727
80824003
JB		 9728 /* Swap pipes & planes for FBC on pre-965 */
9729 intel_crtc->pipe = pipe;
9730 intel_crtc->plane = pipe;
e2e767ab 9731 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9732 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9733 intel_crtc->plane = !pipe;
80824003
JB		 9734 }
9735
22fd0fab
JB		 9736 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9737 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9738 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9739 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9740
79e53945 9741 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9742}
9743
08d7b3d1 9744int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9745 struct drm_file *file)
08d7b3d1 9746{
08d7b3d1 9747 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9748 struct drm_mode_object *drmmode_obj;
9749 struct intel_crtc *crtc;
08d7b3d1 9750
1cff8f6b
DV		 9751 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9752 return -ENODEV;
08d7b3d1 9753
c05422d5
DV		 9754 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9755 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9756
c05422d5 9757 if (!drmmode_obj) {
08d7b3d1
CW		 9758 DRM_ERROR("no such CRTC id\n");
9759 return -EINVAL;
9760 }
9761
c05422d5
DV		 9762 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9763 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9764
c05422d5 9765 return 0;
08d7b3d1
CW		 9766}
9767
66a9278e 9768static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9769{
66a9278e
DV		 9770 struct drm_device *dev = encoder->base.dev;
9771 struct intel_encoder *source_encoder;
79e53945 9772 int index_mask = 0;
79e53945
JB		 9773 int entry = 0;
9774
66a9278e
DV		 9775 list_for_each_entry(source_encoder,
9776 &dev->mode_config.encoder_list, base.head) {
9777
9778 if (encoder == source_encoder)
79e53945 9779 index_mask |= (1 << entry);
66a9278e
DV		 9780
9781 /* Intel hw has only one MUX where enocoders could be cloned. */
9782 if (encoder->cloneable && source_encoder->cloneable)
9783 index_mask |= (1 << entry);
9784
79e53945
JB		 9785 entry++;
9786 }
4ef69c7a 9787
79e53945
JB		 9788 return index_mask;
9789}
9790
4d302442
CW		 9791static bool has_edp_a(struct drm_device *dev)
9792{
9793 struct drm_i915_private *dev_priv = dev->dev_private;
9794
9795 if (!IS_MOBILE(dev))
9796 return false;
9797
9798 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9799 return false;
9800
9801 if (IS_GEN5(dev) &&
9802 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9803 return false;
9804
9805 return true;
9806}
9807
79e53945
JB		 9808static void intel_setup_outputs(struct drm_device *dev)
9809{
725e30ad 9810 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9811 struct intel_encoder *encoder;
cb0953d7 9812 bool dpd_is_edp = false;
79e53945 9813
c9093354 9814 intel_lvds_init(dev);
79e53945 9815
c40c0f5b 9816 if (!IS_ULT(dev))
79935fca 9817 intel_crt_init(dev);
cb0953d7 9818
affa9354 9819 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9820 int found;
9821
9822 /* Haswell uses DDI functions to detect digital outputs */
9823 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9824 /* DDI A only supports eDP */
9825 if (found)
9826 intel_ddi_init(dev, PORT_A);
9827
9828 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9829 * register */
9830 found = I915_READ(SFUSE_STRAP);
9831
9832 if (found & SFUSE_STRAP_DDIB_DETECTED)
9833 intel_ddi_init(dev, PORT_B);
9834 if (found & SFUSE_STRAP_DDIC_DETECTED)
9835 intel_ddi_init(dev, PORT_C);
9836 if (found & SFUSE_STRAP_DDID_DETECTED)
9837 intel_ddi_init(dev, PORT_D);
9838 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9839 int found;
270b3042
DV		 9840 dpd_is_edp = intel_dpd_is_edp(dev);
9841
9842 if (has_edp_a(dev))
9843 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9844
dc0fa718 9845 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9846 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9847 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9848 if (!found)
e2debe91 9849 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9850 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9851 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9852 }
9853
dc0fa718 9854 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9855 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9856
dc0fa718 9857 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9858 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9859
5eb08b69 9860 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9861 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9862
270b3042 9863 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9864 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9865 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9866 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9867 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9868 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9869 PORT_C);
9870 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9871 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9872 PORT_C);
9873 }
19c03924 9874
dc0fa718 9875 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9876 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9877 PORT_B);
67cfc203
VS		 9878 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9879 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9880 }
3cfca973
JN		 9881
9882 intel_dsi_init(dev);
103a196f 9883 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9884 bool found = false;
7d57382e 9885
e2debe91 9886 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9887 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9888 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9889 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9890 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9891 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9892 }
27185ae1 9893
e7281eab 9894 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9895 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9896 }
13520b05
KH		 9897
9898 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9899
e2debe91 9900 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9901 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9902 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9903 }
27185ae1 9904
e2debe91 9905 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9906
b01f2c3a
JB		 9907 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9908 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9909 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9910 }
e7281eab 9911 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9912 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9913 }
27185ae1 9914
b01f2c3a 9915 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9916 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9917 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9918 } else if (IS_GEN2(dev))
79e53945
JB		 9919 intel_dvo_init(dev);
9920
103a196f 9921 if (SUPPORTS_TV(dev))
79e53945
JB		 9922 intel_tv_init(dev);
9923
4ef69c7a
CW		 9924 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9925 encoder->base.possible_crtcs = encoder->crtc_mask;
9926 encoder->base.possible_clones =
66a9278e 9927 intel_encoder_clones(encoder);
79e53945 9928 }
47356eb6 9929
dde86e2d 9930 intel_init_pch_refclk(dev);
270b3042
DV		 9931
9932 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9933}
9934
ddfe1567
CW		 9935void intel_framebuffer_fini(struct intel_framebuffer *fb)
9936{
9937 drm_framebuffer_cleanup(&fb->base);
9938 drm_gem_object_unreference_unlocked(&fb->obj->base);
9939}
9940
79e53945
JB		 9941static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9942{
9943 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9944
ddfe1567 9945 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9946 kfree(intel_fb);
9947}
9948
9949static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9950 struct drm_file *file,
79e53945
JB		 9951 unsigned int *handle)
9952{
9953 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9954 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9955
05394f39 9956 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9957}
9958
9959static const struct drm_framebuffer_funcs intel_fb_funcs = {
9960 .destroy = intel_user_framebuffer_destroy,
9961 .create_handle = intel_user_framebuffer_create_handle,
9962};
9963
38651674
DA		 9964int intel_framebuffer_init(struct drm_device *dev,
9965 struct intel_framebuffer *intel_fb,
308e5bcb 9966 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9967 struct drm_i915_gem_object *obj)
79e53945 9968{
a35cdaa0 9969 int pitch_limit;
79e53945
JB		 9970 int ret;
9971
c16ed4be
CW		 9972 if (obj->tiling_mode == I915_TILING_Y) {
9973 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9974 return -EINVAL;
c16ed4be 9975 }
57cd6508 9976
c16ed4be
CW		 9977 if (mode_cmd->pitches[0] & 63) {
9978 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9979 mode_cmd->pitches[0]);
57cd6508 9980 return -EINVAL;
c16ed4be 9981 }
57cd6508 9982
a35cdaa0
CW		 9983 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9984 pitch_limit = 32*1024;
9985 } else if (INTEL_INFO(dev)->gen >= 4) {
9986 if (obj->tiling_mode)
9987 pitch_limit = 16*1024;
9988 else
9989 pitch_limit = 32*1024;
9990 } else if (INTEL_INFO(dev)->gen >= 3) {
9991 if (obj->tiling_mode)
9992 pitch_limit = 8*1024;
9993 else
9994 pitch_limit = 16*1024;
9995 } else
9996 /* XXX DSPC is limited to 4k tiled */
9997 pitch_limit = 8*1024;
9998
9999 if (mode_cmd->pitches[0] > pitch_limit) {
10000 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10001 obj->tiling_mode ? "tiled" : "linear",
10002 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10003 return -EINVAL;
c16ed4be 10004 }
5d7bd705
VS		 10005
10006 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10007 mode_cmd->pitches[0] != obj->stride) {
10008 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10009 mode_cmd->pitches[0], obj->stride);
5d7bd705 10010 return -EINVAL;
c16ed4be 10011 }
5d7bd705 10012
57779d06 10013 /* Reject formats not supported by any plane early. */
308e5bcb 10014 switch (mode_cmd->pixel_format) {
57779d06 10015 case DRM_FORMAT_C8:
04b3924d
VS		 10016 case DRM_FORMAT_RGB565:
10017 case DRM_FORMAT_XRGB8888:
10018 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10019 break;
10020 case DRM_FORMAT_XRGB1555:
10021 case DRM_FORMAT_ARGB1555:
c16ed4be 10022 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10023 DRM_DEBUG("unsupported pixel format: %s\n",
10024 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10025 return -EINVAL;
c16ed4be 10026 }
57779d06
VS		 10027 break;
10028 case DRM_FORMAT_XBGR8888:
10029 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10030 case DRM_FORMAT_XRGB2101010:
10031 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10032 case DRM_FORMAT_XBGR2101010:
10033 case DRM_FORMAT_ABGR2101010:
c16ed4be 10034 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10035 DRM_DEBUG("unsupported pixel format: %s\n",
10036 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10037 return -EINVAL;
c16ed4be 10038 }
b5626747 10039 break;
04b3924d
VS		 10040 case DRM_FORMAT_YUYV:
10041 case DRM_FORMAT_UYVY:
10042 case DRM_FORMAT_YVYU:
10043 case DRM_FORMAT_VYUY:
c16ed4be 10044 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10045 DRM_DEBUG("unsupported pixel format: %s\n",
10046 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10047 return -EINVAL;
c16ed4be 10048 }
57cd6508
CW		 10049 break;
10050 default:
4ee62c76
VS		 10051 DRM_DEBUG("unsupported pixel format: %s\n",
10052 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10053 return -EINVAL;
10054 }
10055
90f9a336
VS		 10056 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10057 if (mode_cmd->offsets[0] != 0)
10058 return -EINVAL;
10059
c7d73f6a
DV		 10060 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10061 intel_fb->obj = obj;
10062
79e53945
JB		 10063 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10064 if (ret) {
10065 DRM_ERROR("framebuffer init failed %d\n", ret);
10066 return ret;
10067 }
10068
79e53945
JB		 10069 return 0;
10070}
10071
79e53945
JB		 10072static struct drm_framebuffer *
10073intel_user_framebuffer_create(struct drm_device *dev,
10074 struct drm_file *filp,
308e5bcb 10075 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10076{
05394f39 10077 struct drm_i915_gem_object *obj;
79e53945 10078
308e5bcb
JB		 10079 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10080 mode_cmd->handles[0]));
c8725226 10081 if (&obj->base == NULL)
cce13ff7 10082 return ERR_PTR(-ENOENT);
79e53945 10083
d2dff872 10084 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10085}
10086
79e53945 10087static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10088 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10089 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10090};
10091
e70236a8
JB		 10092/* Set up chip specific display functions */
10093static void intel_init_display(struct drm_device *dev)
10094{
10095 struct drm_i915_private *dev_priv = dev->dev_private;
10096
ee9300bb
DV		 10097 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10098 dev_priv->display.find_dpll = g4x_find_best_dpll;
10099 else if (IS_VALLEYVIEW(dev))
10100 dev_priv->display.find_dpll = vlv_find_best_dpll;
10101 else if (IS_PINEVIEW(dev))
10102 dev_priv->display.find_dpll = pnv_find_best_dpll;
10103 else
10104 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10105
affa9354 10106 if (HAS_DDI(dev)) {
0e8ffe1b 10107 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10108 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10109 dev_priv->display.crtc_enable = haswell_crtc_enable;
10110 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10111 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10112 dev_priv->display.update_plane = ironlake_update_plane;
10113 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10114 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10115 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10116 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10117 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10118 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10119 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10120 } else if (IS_VALLEYVIEW(dev)) {
10121 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10122 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10123 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10124 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10125 dev_priv->display.off = i9xx_crtc_off;
10126 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10127 } else {
0e8ffe1b 10128 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10129 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10130 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10131 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10132 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10133 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10134 }
e70236a8 10135
e70236a8 10136 /* Returns the core display clock speed */
25eb05fc
JB		 10137 if (IS_VALLEYVIEW(dev))
10138 dev_priv->display.get_display_clock_speed =
10139 valleyview_get_display_clock_speed;
10140 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10141 dev_priv->display.get_display_clock_speed =
10142 i945_get_display_clock_speed;
10143 else if (IS_I915G(dev))
10144 dev_priv->display.get_display_clock_speed =
10145 i915_get_display_clock_speed;
257a7ffc 10146 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10147 dev_priv->display.get_display_clock_speed =
10148 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10149 else if (IS_PINEVIEW(dev))
10150 dev_priv->display.get_display_clock_speed =
10151 pnv_get_display_clock_speed;
e70236a8
JB		 10152 else if (IS_I915GM(dev))
10153 dev_priv->display.get_display_clock_speed =
10154 i915gm_get_display_clock_speed;
10155 else if (IS_I865G(dev))
10156 dev_priv->display.get_display_clock_speed =
10157 i865_get_display_clock_speed;
f0f8a9ce 10158 else if (IS_I85X(dev))
e70236a8
JB		 10159 dev_priv->display.get_display_clock_speed =
10160 i855_get_display_clock_speed;
10161 else /* 852, 830 */
10162 dev_priv->display.get_display_clock_speed =
10163 i830_get_display_clock_speed;
10164
7f8a8569 10165 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10166 if (IS_GEN5(dev)) {
674cf967 10167 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10168 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10169 } else if (IS_GEN6(dev)) {
674cf967 10170 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10171 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10172 } else if (IS_IVYBRIDGE(dev)) {
10173 /* FIXME: detect B0+ stepping and use auto training */
10174 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10175 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10176 dev_priv->display.modeset_global_resources =
10177 ivb_modeset_global_resources;
c82e4d26
ED		 10178 } else if (IS_HASWELL(dev)) {
10179 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10180 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10181 dev_priv->display.modeset_global_resources =
10182 haswell_modeset_global_resources;
a0e63c22 10183 }
6067aaea 10184 } else if (IS_G4X(dev)) {
e0dac65e 10185 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10186 }
8c9f3aaf
JB		 10187
10188 /* Default just returns -ENODEV to indicate unsupported */
10189 dev_priv->display.queue_flip = intel_default_queue_flip;
10190
10191 switch (INTEL_INFO(dev)->gen) {
10192 case 2:
10193 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10194 break;
10195
10196 case 3:
10197 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10198 break;
10199
10200 case 4:
10201 case 5:
10202 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10203 break;
10204
10205 case 6:
10206 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10207 break;
7c9017e5
JB		 10208 case 7:
10209 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10210 break;
8c9f3aaf 10211 }
e70236a8
JB		 10212}
10213
b690e96c
JB		 10214/*
10215 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10216 * resume, or other times. This quirk makes sure that's the case for
10217 * affected systems.
10218 */
0206e353 10219static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10220{
10221 struct drm_i915_private *dev_priv = dev->dev_private;
10222
10223 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10224 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10225}
10226
435793df
KP		 10227/*
10228 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10229 */
10230static void quirk_ssc_force_disable(struct drm_device *dev)
10231{
10232 struct drm_i915_private *dev_priv = dev->dev_private;
10233 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10234 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10235}
10236
4dca20ef 10237/*
5a15ab5b
CE		 10238 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10239 * brightness value
4dca20ef
CE		 10240 */
10241static void quirk_invert_brightness(struct drm_device *dev)
10242{
10243 struct drm_i915_private *dev_priv = dev->dev_private;
10244 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10245 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10246}
10247
e85843be
KM		 10248/*
10249 * Some machines (Dell XPS13) suffer broken backlight controls if
10250 * BLM_PCH_PWM_ENABLE is set.
10251 */
10252static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10253{
10254 struct drm_i915_private *dev_priv = dev->dev_private;
10255 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10256 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10257}
10258
b690e96c
JB		 10259struct intel_quirk {
10260 int device;
10261 int subsystem_vendor;
10262 int subsystem_device;
10263 void (*hook)(struct drm_device *dev);
10264};
10265
5f85f176
EE		 10266/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10267struct intel_dmi_quirk {
10268 void (*hook)(struct drm_device *dev);
10269 const struct dmi_system_id (*dmi_id_list)[];
10270};
10271
10272static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10273{
10274 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10275 return 1;
10276}
10277
10278static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10279 {
10280 .dmi_id_list = &(const struct dmi_system_id[]) {
10281 {
10282 .callback = intel_dmi_reverse_brightness,
10283 .ident = "NCR Corporation",
10284 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10285 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10286 },
10287 },
10288 { } /* terminating entry */
10289 },
10290 .hook = quirk_invert_brightness,
10291 },
10292};
10293
c43b5634 10294static struct intel_quirk intel_quirks[] = {
b690e96c 10295 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10296 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10297
b690e96c
JB		 10298 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10299 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10300
b690e96c
JB		 10301 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10302 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10303
ccd0d36e 10304 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10305 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10306 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10307
10308 /* Lenovo U160 cannot use SSC on LVDS */
10309 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10310
10311 /* Sony Vaio Y cannot use SSC on LVDS */
10312 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10313
ee1452d7
JN		 10314 /*
10315 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10316 * seem to use inverted backlight PWM.
10317 */
10318 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10319
10320 /* Dell XPS13 HD Sandy Bridge */
10321 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10322 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10323 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10324};
10325
10326static void intel_init_quirks(struct drm_device *dev)
10327{
10328 struct pci_dev *d = dev->pdev;
10329 int i;
10330
10331 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10332 struct intel_quirk *q = &intel_quirks[i];
10333
10334 if (d->device == q->device &&
10335 (d->subsystem_vendor == q->subsystem_vendor ||
10336 q->subsystem_vendor == PCI_ANY_ID) &&
10337 (d->subsystem_device == q->subsystem_device ||
10338 q->subsystem_device == PCI_ANY_ID))
10339 q->hook(dev);
10340 }
5f85f176
EE		 10341 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10342 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10343 intel_dmi_quirks[i].hook(dev);
10344 }
b690e96c
JB		 10345}
10346
9cce37f4
JB		 10347/* Disable the VGA plane that we never use */
10348static void i915_disable_vga(struct drm_device *dev)
10349{
10350 struct drm_i915_private *dev_priv = dev->dev_private;
10351 u8 sr1;
766aa1c4 10352 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10353
10354 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10355 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10356 sr1 = inb(VGA_SR_DATA);
10357 outb(sr1 | 1<<5, VGA_SR_DATA);
10358 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10359 udelay(300);
10360
10361 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10362 POSTING_READ(vga_reg);
10363}
10364
6e1b4fda 10365static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10366{
10367 /* Enable VGA memory on Intel HD */
10368 if (HAS_PCH_SPLIT(dev)) {
10369 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10370 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10371 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10372 VGA_RSRC_LEGACY_MEM |
10373 VGA_RSRC_NORMAL_IO |
10374 VGA_RSRC_NORMAL_MEM);
10375 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10376 }
10377}
10378
6e1b4fda
VS		 10379void i915_disable_vga_mem(struct drm_device *dev)
10380{
10381 /* Disable VGA memory on Intel HD */
10382 if (HAS_PCH_SPLIT(dev)) {
10383 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10384 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10385 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10386 VGA_RSRC_NORMAL_IO |
10387 VGA_RSRC_NORMAL_MEM);
10388 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10389 }
10390}
10391
f817586c
DV		 10392void intel_modeset_init_hw(struct drm_device *dev)
10393{
f6071166
JB		 10394 struct drm_i915_private *dev_priv = dev->dev_private;
10395
a8f78b58
ED		 10396 intel_prepare_ddi(dev);
10397
f817586c
DV		 10398 intel_init_clock_gating(dev);
10399
f6071166
JB		 10400 /* Enable the CRI clock source so we can get at the display */
10401 if (IS_VALLEYVIEW(dev))
10402 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10403 DPLL_INTEGRATED_CRI_CLK_VLV);
10404
40e9cf64
JB		 10405 intel_init_dpio(dev);
10406
79f5b2c7 10407 mutex_lock(&dev->struct_mutex);
8090c6b9 10408 intel_enable_gt_powersave(dev);
79f5b2c7 10409 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10410}
10411
7d708ee4
ID		 10412void intel_modeset_suspend_hw(struct drm_device *dev)
10413{
10414 intel_suspend_hw(dev);
10415}
10416
79e53945
JB		 10417void intel_modeset_init(struct drm_device *dev)
10418{
652c393a 10419 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10420 int i, j, ret;
79e53945
JB		 10421
10422 drm_mode_config_init(dev);
10423
10424 dev->mode_config.min_width = 0;
10425 dev->mode_config.min_height = 0;
10426
019d96cb
DA		 10427 dev->mode_config.preferred_depth = 24;
10428 dev->mode_config.prefer_shadow = 1;
10429
e6ecefaa 10430 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10431
b690e96c
JB		 10432 intel_init_quirks(dev);
10433
1fa61106
ED		 10434 intel_init_pm(dev);
10435
e3c74757
BW		 10436 if (INTEL_INFO(dev)->num_pipes == 0)
10437 return;
10438
e70236a8
JB		 10439 intel_init_display(dev);
10440
a6c45cf0
CW		 10441 if (IS_GEN2(dev)) {
10442 dev->mode_config.max_width = 2048;
10443 dev->mode_config.max_height = 2048;
10444 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10445 dev->mode_config.max_width = 4096;
10446 dev->mode_config.max_height = 4096;
79e53945 10447 } else {
a6c45cf0
CW		 10448 dev->mode_config.max_width = 8192;
10449 dev->mode_config.max_height = 8192;
79e53945 10450 }
5d4545ae 10451 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10452
28c97730 10453 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10454 INTEL_INFO(dev)->num_pipes,
10455 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10456
08e2a7de 10457 for_each_pipe(i) {
79e53945 10458 intel_crtc_init(dev, i);
7f1f3851
JB		 10459 for (j = 0; j < dev_priv->num_plane; j++) {
10460 ret = intel_plane_init(dev, i, j);
10461 if (ret)
06da8da2
VS		 10462 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10463 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10464 }
79e53945
JB		 10465 }
10466
79f689aa 10467 intel_cpu_pll_init(dev);
e72f9fbf 10468 intel_shared_dpll_init(dev);
ee7b9f93 10469
9cce37f4
JB		 10470 /* Just disable it once at startup */
10471 i915_disable_vga(dev);
79e53945 10472 intel_setup_outputs(dev);
11be49eb
CW		 10473
10474 /* Just in case the BIOS is doing something questionable. */
10475 intel_disable_fbc(dev);
2c7111db
CW		 10476}
10477
24929352
DV		 10478static void
10479intel_connector_break_all_links(struct intel_connector *connector)
10480{
10481 connector->base.dpms = DRM_MODE_DPMS_OFF;
10482 connector->base.encoder = NULL;
10483 connector->encoder->connectors_active = false;
10484 connector->encoder->base.crtc = NULL;
10485}
10486
7fad798e
DV		 10487static void intel_enable_pipe_a(struct drm_device *dev)
10488{
10489 struct intel_connector *connector;
10490 struct drm_connector *crt = NULL;
10491 struct intel_load_detect_pipe load_detect_temp;
10492
10493 /* We can't just switch on the pipe A, we need to set things up with a
10494 * proper mode and output configuration. As a gross hack, enable pipe A
10495 * by enabling the load detect pipe once. */
10496 list_for_each_entry(connector,
10497 &dev->mode_config.connector_list,
10498 base.head) {
10499 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10500 crt = &connector->base;
10501 break;
10502 }
10503 }
10504
10505 if (!crt)
10506 return;
10507
10508 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10509 intel_release_load_detect_pipe(crt, &load_detect_temp);
10510
652c393a 10511
7fad798e
DV		 10512}
10513
fa555837
DV		 10514static bool
10515intel_check_plane_mapping(struct intel_crtc *crtc)
10516{
7eb552ae
BW		 10517 struct drm_device *dev = crtc->base.dev;
10518 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10519 u32 reg, val;
10520
7eb552ae 10521 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10522 return true;
10523
10524 reg = DSPCNTR(!crtc->plane);
10525 val = I915_READ(reg);
10526
10527 if ((val & DISPLAY_PLANE_ENABLE) &&
10528 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10529 return false;
10530
10531 return true;
10532}
10533
24929352
DV		 10534static void intel_sanitize_crtc(struct intel_crtc *crtc)
10535{
10536 struct drm_device *dev = crtc->base.dev;
10537 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10538 u32 reg;
24929352 10539
24929352 10540 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10541 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10542 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10543
10544 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10545 * disable the crtc (and hence change the state) if it is wrong. Note
10546 * that gen4+ has a fixed plane -> pipe mapping. */
10547 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10548 struct intel_connector *connector;
10549 bool plane;
10550
24929352
DV		 10551 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10552 crtc->base.base.id);
10553
10554 /* Pipe has the wrong plane attached and the plane is active.
10555 * Temporarily change the plane mapping and disable everything
10556 * ... */
10557 plane = crtc->plane;
10558 crtc->plane = !plane;
10559 dev_priv->display.crtc_disable(&crtc->base);
10560 crtc->plane = plane;
10561
10562 /* ... and break all links. */
10563 list_for_each_entry(connector, &dev->mode_config.connector_list,
10564 base.head) {
10565 if (connector->encoder->base.crtc != &crtc->base)
10566 continue;
10567
10568 intel_connector_break_all_links(connector);
10569 }
10570
10571 WARN_ON(crtc->active);
10572 crtc->base.enabled = false;
10573 }
24929352 10574
7fad798e
DV		 10575 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10576 crtc->pipe == PIPE_A && !crtc->active) {
10577 /* BIOS forgot to enable pipe A, this mostly happens after
10578 * resume. Force-enable the pipe to fix this, the update_dpms
10579 * call below we restore the pipe to the right state, but leave
10580 * the required bits on. */
10581 intel_enable_pipe_a(dev);
10582 }
10583
24929352
DV		 10584 /* Adjust the state of the output pipe according to whether we
10585 * have active connectors/encoders. */
10586 intel_crtc_update_dpms(&crtc->base);
10587
10588 if (crtc->active != crtc->base.enabled) {
10589 struct intel_encoder *encoder;
10590
10591 /* This can happen either due to bugs in the get_hw_state
10592 * functions or because the pipe is force-enabled due to the
10593 * pipe A quirk. */
10594 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10595 crtc->base.base.id,
10596 crtc->base.enabled ? "enabled" : "disabled",
10597 crtc->active ? "enabled" : "disabled");
10598
10599 crtc->base.enabled = crtc->active;
10600
10601 /* Because we only establish the connector -> encoder ->
10602 * crtc links if something is active, this means the
10603 * crtc is now deactivated. Break the links. connector
10604 * -> encoder links are only establish when things are
10605 * actually up, hence no need to break them. */
10606 WARN_ON(crtc->active);
10607
10608 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10609 WARN_ON(encoder->connectors_active);
10610 encoder->base.crtc = NULL;
10611 }
10612 }
10613}
10614
10615static void intel_sanitize_encoder(struct intel_encoder *encoder)
10616{
10617 struct intel_connector *connector;
10618 struct drm_device *dev = encoder->base.dev;
10619
10620 /* We need to check both for a crtc link (meaning that the
10621 * encoder is active and trying to read from a pipe) and the
10622 * pipe itself being active. */
10623 bool has_active_crtc = encoder->base.crtc &&
10624 to_intel_crtc(encoder->base.crtc)->active;
10625
10626 if (encoder->connectors_active && !has_active_crtc) {
10627 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10628 encoder->base.base.id,
10629 drm_get_encoder_name(&encoder->base));
10630
10631 /* Connector is active, but has no active pipe. This is
10632 * fallout from our resume register restoring. Disable
10633 * the encoder manually again. */
10634 if (encoder->base.crtc) {
10635 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10636 encoder->base.base.id,
10637 drm_get_encoder_name(&encoder->base));
10638 encoder->disable(encoder);
10639 }
10640
10641 /* Inconsistent output/port/pipe state happens presumably due to
10642 * a bug in one of the get_hw_state functions. Or someplace else
10643 * in our code, like the register restore mess on resume. Clamp
10644 * things to off as a safer default. */
10645 list_for_each_entry(connector,
10646 &dev->mode_config.connector_list,
10647 base.head) {
10648 if (connector->encoder != encoder)
10649 continue;
10650
10651 intel_connector_break_all_links(connector);
10652 }
10653 }
10654 /* Enabled encoders without active connectors will be fixed in
10655 * the crtc fixup. */
10656}
10657
44cec740 10658void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10659{
10660 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10661 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10662
8dc8a27c
PZ		 10663 /* This function can be called both from intel_modeset_setup_hw_state or
10664 * at a very early point in our resume sequence, where the power well
10665 * structures are not yet restored. Since this function is at a very
10666 * paranoid "someone might have enabled VGA while we were not looking"
10667 * level, just check if the power well is enabled instead of trying to
10668 * follow the "don't touch the power well if we don't need it" policy
10669 * the rest of the driver uses. */
10670 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10671 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10672 return;
10673
e1553faa 10674 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 10675 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10676 i915_disable_vga(dev);
6e1b4fda 10677 i915_disable_vga_mem(dev);
0fde901f
KM		 10678 }
10679}
10680
30e984df 10681static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10682{
10683 struct drm_i915_private *dev_priv = dev->dev_private;
10684 enum pipe pipe;
24929352
DV		 10685 struct intel_crtc *crtc;
10686 struct intel_encoder *encoder;
10687 struct intel_connector *connector;
5358901f 10688 int i;
24929352 10689
0e8ffe1b
DV		 10690 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10691 base.head) {
88adfff1 10692 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10693
0e8ffe1b
DV		 10694 crtc->active = dev_priv->display.get_pipe_config(crtc,
10695 &crtc->config);
24929352
DV		 10696
10697 crtc->base.enabled = crtc->active;
10698
10699 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10700 crtc->base.base.id,
10701 crtc->active ? "enabled" : "disabled");
10702 }
10703
5358901f 10704 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10705 if (HAS_DDI(dev))
6441ab5f
PZ		 10706 intel_ddi_setup_hw_pll_state(dev);
10707
5358901f
DV		 10708 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10709 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10710
10711 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10712 pll->active = 0;
10713 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10714 base.head) {
10715 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10716 pll->active++;
10717 }
10718 pll->refcount = pll->active;
10719
35c95375
DV		 10720 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10721 pll->name, pll->refcount, pll->on);
5358901f
DV		 10722 }
10723
24929352
DV		 10724 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10725 base.head) {
10726 pipe = 0;
10727
10728 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10729 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10730 encoder->base.crtc = &crtc->base;
510d5f2f 10731 if (encoder->get_config)
045ac3b5 10732 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10733 } else {
10734 encoder->base.crtc = NULL;
10735 }
10736
10737 encoder->connectors_active = false;
10738 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10739 encoder->base.base.id,
10740 drm_get_encoder_name(&encoder->base),
10741 encoder->base.crtc ? "enabled" : "disabled",
10742 pipe);
10743 }
10744
10745 list_for_each_entry(connector, &dev->mode_config.connector_list,
10746 base.head) {
10747 if (connector->get_hw_state(connector)) {
10748 connector->base.dpms = DRM_MODE_DPMS_ON;
10749 connector->encoder->connectors_active = true;
10750 connector->base.encoder = &connector->encoder->base;
10751 } else {
10752 connector->base.dpms = DRM_MODE_DPMS_OFF;
10753 connector->base.encoder = NULL;
10754 }
10755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10756 connector->base.base.id,
10757 drm_get_connector_name(&connector->base),
10758 connector->base.encoder ? "enabled" : "disabled");
10759 }
30e984df
DV		 10760}
10761
10762/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10763 * and i915 state tracking structures. */
10764void intel_modeset_setup_hw_state(struct drm_device *dev,
10765 bool force_restore)
10766{
10767 struct drm_i915_private *dev_priv = dev->dev_private;
10768 enum pipe pipe;
30e984df
DV		 10769 struct intel_crtc *crtc;
10770 struct intel_encoder *encoder;
35c95375 10771 int i;
30e984df
DV		 10772
10773 intel_modeset_readout_hw_state(dev);
24929352 10774
babea61d
JB		 10775 /*
10776 * Now that we have the config, copy it to each CRTC struct
10777 * Note that this could go away if we move to using crtc_config
10778 * checking everywhere.
10779 */
10780 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10781 base.head) {
10782 if (crtc->active && i915_fastboot) {
10783 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10784
10785 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10786 crtc->base.base.id);
10787 drm_mode_debug_printmodeline(&crtc->base.mode);
10788 }
10789 }
10790
24929352
DV		 10791 /* HW state is read out, now we need to sanitize this mess. */
10792 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10793 base.head) {
10794 intel_sanitize_encoder(encoder);
10795 }
10796
10797 for_each_pipe(pipe) {
10798 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10799 intel_sanitize_crtc(crtc);
c0b03411 10800 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10801 }
9a935856 10802
35c95375
DV		 10803 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10804 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10805
10806 if (!pll->on || pll->active)
10807 continue;
10808
10809 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10810
10811 pll->disable(dev_priv, pll);
10812 pll->on = false;
10813 }
10814
45e2b5f6 10815 if (force_restore) {
7d0bc1ea
VS		 10816 i915_redisable_vga(dev);
10817
f30da187
DV		 10818 /*
10819 * We need to use raw interfaces for restoring state to avoid
10820 * checking (bogus) intermediate states.
10821 */
45e2b5f6 10822 for_each_pipe(pipe) {
b5644d05
JB		 10823 struct drm_crtc *crtc =
10824 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10825
10826 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10827 crtc->fb);
45e2b5f6
DV		 10828 }
10829 } else {
10830 intel_modeset_update_staged_output_state(dev);
10831 }
8af6cf88
DV		 10832
10833 intel_modeset_check_state(dev);
2e938892
DV		 10834
10835 drm_mode_config_reset(dev);
2c7111db
CW		 10836}
10837
10838void intel_modeset_gem_init(struct drm_device *dev)
10839{
1833b134 10840 intel_modeset_init_hw(dev);
02e792fb
DV		 10841
10842 intel_setup_overlay(dev);
24929352 10843
45e2b5f6 10844 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10845}
10846
10847void intel_modeset_cleanup(struct drm_device *dev)
10848{
652c393a
JB		 10849 struct drm_i915_private *dev_priv = dev->dev_private;
10850 struct drm_crtc *crtc;
d9255d57 10851 struct drm_connector *connector;
652c393a 10852
fd0c0642
DV		 10853 /*
10854 * Interrupts and polling as the first thing to avoid creating havoc.
10855 * Too much stuff here (turning of rps, connectors, ...) would
10856 * experience fancy races otherwise.
10857 */
10858 drm_irq_uninstall(dev);
10859 cancel_work_sync(&dev_priv->hotplug_work);
10860 /*
10861 * Due to the hpd irq storm handling the hotplug work can re-arm the
10862 * poll handlers. Hence disable polling after hpd handling is shut down.
10863 */
f87ea761 10864 drm_kms_helper_poll_fini(dev);
fd0c0642 10865
652c393a
JB		 10866 mutex_lock(&dev->struct_mutex);
10867
723bfd70
JB		 10868 intel_unregister_dsm_handler();
10869
652c393a
JB		 10870 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10871 /* Skip inactive CRTCs */
10872 if (!crtc->fb)
10873 continue;
10874
3dec0095 10875 intel_increase_pllclock(crtc);
652c393a
JB		 10876 }
10877
973d04f9 10878 intel_disable_fbc(dev);
e70236a8 10879
6e1b4fda 10880 i915_enable_vga_mem(dev);
81b5c7bc 10881
8090c6b9 10882 intel_disable_gt_powersave(dev);
0cdab21f 10883
930ebb46
DV		 10884 ironlake_teardown_rc6(dev);
10885
69341a5e
KH		 10886 mutex_unlock(&dev->struct_mutex);
10887
1630fe75
CW		 10888 /* flush any delayed tasks or pending work */
10889 flush_scheduled_work();
10890
dc652f90
JN		 10891 /* destroy backlight, if any, before the connectors */
10892 intel_panel_destroy_backlight(dev);
10893
d9255d57
PZ		 10894 /* destroy the sysfs files before encoders/connectors */
10895 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10896 drm_sysfs_connector_remove(connector);
10897
79e53945 10898 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10899
10900 intel_cleanup_overlay(dev);
79e53945
JB		 10901}
10902
f1c79df3
ZW		 10903/*
10904 * Return which encoder is currently attached for connector.
10905 */
df0e9248 10906struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10907{
df0e9248
CW		 10908 return &intel_attached_encoder(connector)->base;
10909}
f1c79df3 10910
df0e9248
CW		 10911void intel_connector_attach_encoder(struct intel_connector *connector,
10912 struct intel_encoder *encoder)
10913{
10914 connector->encoder = encoder;
10915 drm_mode_connector_attach_encoder(&connector->base,
10916 &encoder->base);
79e53945 10917}
28d52043
DA		 10918
10919/*
10920 * set vga decode state - true == enable VGA decode
10921 */
10922int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10923{
10924 struct drm_i915_private *dev_priv = dev->dev_private;
10925 u16 gmch_ctrl;
10926
10927 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10928 if (state)
10929 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10930 else
10931 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10932 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10933 return 0;
10934}
c4a1d9e4 10935
c4a1d9e4 10936struct intel_display_error_state {
ff57f1b0
PZ		 10937
10938 u32 power_well_driver;
10939
63b66e5b
CW		 10940 int num_transcoders;
10941
c4a1d9e4
CW		 10942 struct intel_cursor_error_state {
10943 u32 control;
10944 u32 position;
10945 u32 base;
10946 u32 size;
52331309 10947 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10948
10949 struct intel_pipe_error_state {
c4a1d9e4 10950 u32 source;
52331309 10951 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10952
10953 struct intel_plane_error_state {
10954 u32 control;
10955 u32 stride;
10956 u32 size;
10957 u32 pos;
10958 u32 addr;
10959 u32 surface;
10960 u32 tile_offset;
52331309 10961 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10962
10963 struct intel_transcoder_error_state {
10964 enum transcoder cpu_transcoder;
10965
10966 u32 conf;
10967
10968 u32 htotal;
10969 u32 hblank;
10970 u32 hsync;
10971 u32 vtotal;
10972 u32 vblank;
10973 u32 vsync;
10974 } transcoder[4];
c4a1d9e4
CW		 10975};
10976
10977struct intel_display_error_state *
10978intel_display_capture_error_state(struct drm_device *dev)
10979{
0206e353 10980 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10981 struct intel_display_error_state *error;
63b66e5b
CW		 10982 int transcoders[] = {
10983 TRANSCODER_A,
10984 TRANSCODER_B,
10985 TRANSCODER_C,
10986 TRANSCODER_EDP,
10987 };
c4a1d9e4
CW		 10988 int i;
10989
63b66e5b
CW		 10990 if (INTEL_INFO(dev)->num_pipes == 0)
10991 return NULL;
10992
c4a1d9e4
CW		 10993 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10994 if (error == NULL)
10995 return NULL;
10996
ff57f1b0
PZ		 10997 if (HAS_POWER_WELL(dev))
10998 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10999
52331309 11000 for_each_pipe(i) {
a18c4c3d
PZ		 11001 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11002 error->cursor[i].control = I915_READ(CURCNTR(i));
11003 error->cursor[i].position = I915_READ(CURPOS(i));
11004 error->cursor[i].base = I915_READ(CURBASE(i));
11005 } else {
11006 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11007 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11008 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11009 }
c4a1d9e4
CW		 11010
11011 error->plane[i].control = I915_READ(DSPCNTR(i));
11012 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11013 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11014 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11015 error->plane[i].pos = I915_READ(DSPPOS(i));
11016 }
ca291363
PZ		 11017 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11018 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11019 if (INTEL_INFO(dev)->gen >= 4) {
11020 error->plane[i].surface = I915_READ(DSPSURF(i));
11021 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11022 }
11023
c4a1d9e4 11024 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11025 }
11026
11027 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11028 if (HAS_DDI(dev_priv->dev))
11029 error->num_transcoders++; /* Account for eDP. */
11030
11031 for (i = 0; i < error->num_transcoders; i++) {
11032 enum transcoder cpu_transcoder = transcoders[i];
11033
11034 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11035
11036 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11037 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11038 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11039 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11040 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11041 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11042 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11043 }
11044
12d217c7
PZ		 11045 /* In the code above we read the registers without checking if the power
11046 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11047 * prevent the next I915_WRITE from detecting it and printing an error
11048 * message. */
907b28c5 11049 intel_uncore_clear_errors(dev);
12d217c7 11050
c4a1d9e4
CW		 11051 return error;
11052}
11053
edc3d884
MK		 11054#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11055
c4a1d9e4 11056void
edc3d884 11057intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11058 struct drm_device *dev,
11059 struct intel_display_error_state *error)
11060{
11061 int i;
11062
63b66e5b
CW		 11063 if (!error)
11064 return;
11065
edc3d884 11066 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11067 if (HAS_POWER_WELL(dev))
edc3d884 11068 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11069 error->power_well_driver);
52331309 11070 for_each_pipe(i) {
edc3d884 11071 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11072 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11073
11074 err_printf(m, "Plane [%d]:\n", i);
11075 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11076 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11077 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11078 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11079 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11080 }
4b71a570 11081 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11082 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11083 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11084 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11085 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11086 }
11087
edc3d884
MK		 11088 err_printf(m, "Cursor [%d]:\n", i);
11089 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11090 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11091 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11092 }
63b66e5b
CW		 11093
11094 for (i = 0; i < error->num_transcoders; i++) {
11095 err_printf(m, " CPU transcoder: %c\n",
11096 transcoder_name(error->transcoder[i].cpu_transcoder));
11097 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11098 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11099 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11100 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11101 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11102 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11103 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11104 }
c4a1d9e4 11105}
Linux kernel - Deliverables
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