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drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
a5c961d1
PZ		 736enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
737 enum pipe pipe)
738{
739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741
3b117c8f 742 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 743}
744
a928d536
PZ		 745static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 frame, frame_reg = PIPEFRAME(pipe);
749
750 frame = I915_READ(frame_reg);
751
752 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
754}
755
9d0498a2
JB		 756/**
757 * intel_wait_for_vblank - wait for vblank on a given pipe
758 * @dev: drm device
759 * @pipe: pipe to wait for
760 *
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
762 * mode setting code.
763 */
764void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 765{
9d0498a2 766 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 767 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 768
a928d536
PZ		 769 if (INTEL_INFO(dev)->gen >= 5) {
770 ironlake_wait_for_vblank(dev, pipe);
771 return;
772 }
773
300387c0
CW		 774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
776 *
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
783 * vblanks...
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
786 */
787 I915_WRITE(pipestat_reg,
788 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
789
9d0498a2 790 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 791 if (wait_for(I915_READ(pipestat_reg) &
792 PIPE_VBLANK_INTERRUPT_STATUS,
793 50))
9d0498a2
JB		 794 DRM_DEBUG_KMS("vblank wait timed out\n");
795}
796
ab7ad7f6
KP		 797/*
798 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 799 * @dev: drm device
800 * @pipe: pipe to wait for
801 *
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
805 *
ab7ad7f6
KP		 806 * On Gen4 and above:
807 * wait for the pipe register state bit to turn off
808 *
809 * Otherwise:
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
58e10eb9 812 *
9d0498a2 813 */
58e10eb9 814void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
818 pipe);
ab7ad7f6
KP		 819
820 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 821 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 822
823 /* Wait for the Pipe State to go off */
58e10eb9
CW		 824 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
825 100))
284637d9 826 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 827 } else {
837ba00f 828 u32 last_line, line_mask;
58e10eb9 829 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 830 unsigned long timeout = jiffies + msecs_to_jiffies(100);
831
837ba00f
PZ		 832 if (IS_GEN2(dev))
833 line_mask = DSL_LINEMASK_GEN2;
834 else
835 line_mask = DSL_LINEMASK_GEN3;
836
ab7ad7f6
KP		 837 /* Wait for the display line to settle */
838 do {
837ba00f 839 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 840 mdelay(5);
837ba00f 841 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 842 time_after(timeout, jiffies));
843 if (time_after(jiffies, timeout))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 }
79e53945
JB		 846}
847
b0ea7d37
DL		 848/*
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
852 *
853 * Returns true if @port is connected, false otherwise.
854 */
855bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
856 struct intel_digital_port *port)
857{
858 u32 bit;
859
c36346e3
DL		 860 if (HAS_PCH_IBX(dev_priv->dev)) {
861 switch(port->port) {
862 case PORT_B:
863 bit = SDE_PORTB_HOTPLUG;
864 break;
865 case PORT_C:
866 bit = SDE_PORTC_HOTPLUG;
867 break;
868 case PORT_D:
869 bit = SDE_PORTD_HOTPLUG;
870 break;
871 default:
872 return true;
873 }
874 } else {
875 switch(port->port) {
876 case PORT_B:
877 bit = SDE_PORTB_HOTPLUG_CPT;
878 break;
879 case PORT_C:
880 bit = SDE_PORTC_HOTPLUG_CPT;
881 break;
882 case PORT_D:
883 bit = SDE_PORTD_HOTPLUG_CPT;
884 break;
885 default:
886 return true;
887 }
b0ea7d37
DL		 888 }
889
890 return I915_READ(SDEISR) & bit;
891}
892
b24e7179
JB		 893static const char *state_string(bool enabled)
894{
895 return enabled ? "on" : "off";
896}
897
898/* Only for pre-ILK configs */
55607e8a
DV		 899void assert_pll(struct drm_i915_private *dev_priv,
900 enum pipe pipe, bool state)
b24e7179
JB		 901{
902 int reg;
903 u32 val;
904 bool cur_state;
905
906 reg = DPLL(pipe);
907 val = I915_READ(reg);
908 cur_state = !!(val & DPLL_VCO_ENABLE);
909 WARN(cur_state != state,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state), state_string(cur_state));
912}
b24e7179 913
23538ef1
JN		 914/* XXX: the dsi pll is shared between MIPI DSI ports */
915static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
916{
917 u32 val;
918 bool cur_state;
919
920 mutex_lock(&dev_priv->dpio_lock);
921 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
922 mutex_unlock(&dev_priv->dpio_lock);
923
924 cur_state = val & DSI_PLL_VCO_EN;
925 WARN(cur_state != state,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
929#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
93ce0ba6
JN		 1072static void assert_cursor(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1074{
1075 struct drm_device *dev = dev_priv->dev;
1076 bool cur_state;
1077
1078 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1079 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1080 else if (IS_845G(dev) || IS_I865G(dev))
1081 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1082 else
1083 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1084
1085 WARN(cur_state != state,
1086 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1087 pipe_name(pipe), state_string(state), state_string(cur_state));
1088}
1089#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1090#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1091
b840d907
JB		 1092void assert_pipe(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
b24e7179
JB		 1094{
1095 int reg;
1096 u32 val;
63d7bbe9 1097 bool cur_state;
702e7a56
PZ		 1098 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1099 pipe);
b24e7179 1100
8e636784
DV		 1101 /* if we need the pipe A quirk it must be always on */
1102 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1103 state = true;
1104
b97186f0
PZ		 1105 if (!intel_display_power_enabled(dev_priv->dev,
1106 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1107 cur_state = false;
1108 } else {
1109 reg = PIPECONF(cpu_transcoder);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPECONF_ENABLE);
1112 }
1113
63d7bbe9
JB		 1114 WARN(cur_state != state,
1115 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1116 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1117}
1118
931872fc
CW		 1119static void assert_plane(struct drm_i915_private *dev_priv,
1120 enum plane plane, bool state)
b24e7179
JB		 1121{
1122 int reg;
1123 u32 val;
931872fc 1124 bool cur_state;
b24e7179
JB		 1125
1126 reg = DSPCNTR(plane);
1127 val = I915_READ(reg);
931872fc
CW		 1128 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1129 WARN(cur_state != state,
1130 "plane %c assertion failure (expected %s, current %s)\n",
1131 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1132}
1133
931872fc
CW		 1134#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1135#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1136
b24e7179
JB		 1137static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1138 enum pipe pipe)
1139{
653e1026 1140 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1141 int reg, i;
1142 u32 val;
1143 int cur_pipe;
1144
653e1026
VS		 1145 /* Primary planes are fixed to pipes on gen4+ */
1146 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1147 reg = DSPCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DISPLAY_PLANE_ENABLE),
1150 "plane %c assertion failure, should be disabled but not\n",
1151 plane_name(pipe));
19ec1358 1152 return;
28c05794 1153 }
19ec1358 1154
b24e7179 1155 /* Need to check both planes against the pipe */
08e2a7de 1156 for_each_pipe(i) {
b24e7179
JB		 1157 reg = DSPCNTR(i);
1158 val = I915_READ(reg);
1159 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1160 DISPPLANE_SEL_PIPE_SHIFT;
1161 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1162 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1163 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1164 }
1165}
1166
19332d7a
JB		 1167static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1168 enum pipe pipe)
1169{
20674eef 1170 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1171 int reg, i;
1172 u32 val;
1173
20674eef
VS		 1174 if (IS_VALLEYVIEW(dev)) {
1175 for (i = 0; i < dev_priv->num_plane; i++) {
1176 reg = SPCNTR(pipe, i);
1177 val = I915_READ(reg);
1178 WARN((val & SP_ENABLE),
1179 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1180 sprite_name(pipe, i), pipe_name(pipe));
1181 }
1182 } else if (INTEL_INFO(dev)->gen >= 7) {
1183 reg = SPRCTL(pipe);
19332d7a 1184 val = I915_READ(reg);
20674eef 1185 WARN((val & SPRITE_ENABLE),
06da8da2 1186 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1187 plane_name(pipe), pipe_name(pipe));
1188 } else if (INTEL_INFO(dev)->gen >= 5) {
1189 reg = DVSCNTR(pipe);
19332d7a 1190 val = I915_READ(reg);
20674eef 1191 WARN((val & DVS_ENABLE),
06da8da2 1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1193 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1194 }
1195}
1196
92f2584a
JB		 1197static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198{
1199 u32 val;
1200 bool enabled;
1201
9d82aa17
ED		 1202 if (HAS_PCH_LPT(dev_priv->dev)) {
1203 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1204 return;
1205 }
1206
92f2584a
JB		 1207 val = I915_READ(PCH_DREF_CONTROL);
1208 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1209 DREF_SUPERSPREAD_SOURCE_MASK));
1210 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1211}
1212
ab9412ba
DV		 1213static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1214 enum pipe pipe)
92f2584a
JB		 1215{
1216 int reg;
1217 u32 val;
1218 bool enabled;
1219
ab9412ba 1220 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1221 val = I915_READ(reg);
1222 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1223 WARN(enabled,
1224 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1225 pipe_name(pipe));
92f2584a
JB		 1226}
1227
4e634389
KP		 1228static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1230{
1231 if ((val & DP_PORT_EN) == 0)
1232 return false;
1233
1234 if (HAS_PCH_CPT(dev_priv->dev)) {
1235 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1236 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1237 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1238 return false;
1239 } else {
1240 if ((val & DP_PIPE_MASK) != (pipe << 30))
1241 return false;
1242 }
1243 return true;
1244}
1245
1519b995
KP		 1246static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
dc0fa718 1249 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1250 return false;
1251
1252 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1253 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1254 return false;
1255 } else {
dc0fa718 1256 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1257 return false;
1258 }
1259 return true;
1260}
1261
1262static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, u32 val)
1264{
1265 if ((val & LVDS_PORT_EN) == 0)
1266 return false;
1267
1268 if (HAS_PCH_CPT(dev_priv->dev)) {
1269 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1270 return false;
1271 } else {
1272 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1273 return false;
1274 }
1275 return true;
1276}
1277
1278static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe, u32 val)
1280{
1281 if ((val & ADPA_DAC_ENABLE) == 0)
1282 return false;
1283 if (HAS_PCH_CPT(dev_priv->dev)) {
1284 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1285 return false;
1286 } else {
1287 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1288 return false;
1289 }
1290 return true;
1291}
1292
291906f1 1293static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1294 enum pipe pipe, int reg, u32 port_sel)
291906f1 1295{
47a05eca 1296 u32 val = I915_READ(reg);
4e634389 1297 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1298 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1299 reg, pipe_name(pipe));
de9a35ab 1300
75c5da27
DV		 1301 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1302 && (val & DP_PIPEB_SELECT),
de9a35ab 1303 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1304}
1305
1306static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, int reg)
1308{
47a05eca 1309 u32 val = I915_READ(reg);
b70ad586 1310 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1311 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 reg, pipe_name(pipe));
de9a35ab 1313
dc0fa718 1314 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1315 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1316 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1317}
1318
1319static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321{
1322 int reg;
1323 u32 val;
291906f1 1324
f0575e92
KP		 1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1326 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1327 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1328
1329 reg = PCH_ADPA;
1330 val = I915_READ(reg);
b70ad586 1331 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1332 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1333 pipe_name(pipe));
291906f1
JB		 1334
1335 reg = PCH_LVDS;
1336 val = I915_READ(reg);
b70ad586 1337 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1338 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1339 pipe_name(pipe));
291906f1 1340
e2debe91
PZ		 1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1342 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1343 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1344}
1345
426115cf 1346static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1347{
426115cf
DV		 1348 struct drm_device *dev = crtc->base.dev;
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 int reg = DPLL(crtc->pipe);
1351 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1352
426115cf 1353 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1354
1355 /* No really, not for ILK+ */
1356 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1357
1358 /* PLL is protected by panel, make sure we can write it */
1359 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1360 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1361
426115cf
DV		 1362 I915_WRITE(reg, dpll);
1363 POSTING_READ(reg);
1364 udelay(150);
1365
1366 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1367 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1368
1369 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1370 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1371
1372 /* We do this three times for luck */
426115cf 1373 I915_WRITE(reg, dpll);
87442f73
DV		 1374 POSTING_READ(reg);
1375 udelay(150); /* wait for warmup */
426115cf 1376 I915_WRITE(reg, dpll);
87442f73
DV		 1377 POSTING_READ(reg);
1378 udelay(150); /* wait for warmup */
426115cf 1379 I915_WRITE(reg, dpll);
87442f73
DV		 1380 POSTING_READ(reg);
1381 udelay(150); /* wait for warmup */
1382}
1383
66e3d5c0 1384static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1385{
66e3d5c0
DV		 1386 struct drm_device *dev = crtc->base.dev;
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 int reg = DPLL(crtc->pipe);
1389 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1390
66e3d5c0 1391 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1392
63d7bbe9 1393 /* No really, not for ILK+ */
87442f73 1394 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1395
1396 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1397 if (IS_MOBILE(dev) && !IS_I830(dev))
1398 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1399
66e3d5c0
DV		 1400 I915_WRITE(reg, dpll);
1401
1402 /* Wait for the clocks to stabilize. */
1403 POSTING_READ(reg);
1404 udelay(150);
1405
1406 if (INTEL_INFO(dev)->gen >= 4) {
1407 I915_WRITE(DPLL_MD(crtc->pipe),
1408 crtc->config.dpll_hw_state.dpll_md);
1409 } else {
1410 /* The pixel multiplier can only be updated once the
1411 * DPLL is enabled and the clocks are stable.
1412 *
1413 * So write it again.
1414 */
1415 I915_WRITE(reg, dpll);
1416 }
63d7bbe9
JB		 1417
1418 /* We do this three times for luck */
66e3d5c0 1419 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1420 POSTING_READ(reg);
1421 udelay(150); /* wait for warmup */
66e3d5c0 1422 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1423 POSTING_READ(reg);
1424 udelay(150); /* wait for warmup */
66e3d5c0 1425 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1426 POSTING_READ(reg);
1427 udelay(150); /* wait for warmup */
1428}
1429
1430/**
50b44a44 1431 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1432 * @dev_priv: i915 private structure
1433 * @pipe: pipe PLL to disable
1434 *
1435 * Disable the PLL for @pipe, making sure the pipe is off first.
1436 *
1437 * Note! This is for pre-ILK only.
1438 */
50b44a44 1439static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1440{
63d7bbe9
JB		 1441 /* Don't disable pipe A or pipe A PLLs if needed */
1442 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1443 return;
1444
1445 /* Make sure the pipe isn't still relying on us */
1446 assert_pipe_disabled(dev_priv, pipe);
1447
50b44a44
DV		 1448 I915_WRITE(DPLL(pipe), 0);
1449 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1450}
1451
89b667f8
JB		 1452void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1453{
1454 u32 port_mask;
1455
1456 if (!port)
1457 port_mask = DPLL_PORTB_READY_MASK;
1458 else
1459 port_mask = DPLL_PORTC_READY_MASK;
1460
1461 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1462 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1463 'B' + port, I915_READ(DPLL(0)));
1464}
1465
92f2584a 1466/**
e72f9fbf 1467 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1468 * @dev_priv: i915 private structure
1469 * @pipe: pipe PLL to enable
1470 *
1471 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1472 * drives the transcoder clock.
1473 */
e2b78267 1474static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1475{
e2b78267
DV		 1476 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1477 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1478
48da64a8 1479 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1480 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1481 if (WARN_ON(pll == NULL))
48da64a8
CW		 1482 return;
1483
1484 if (WARN_ON(pll->refcount == 0))
1485 return;
ee7b9f93 1486
46edb027
DV		 1487 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1488 pll->name, pll->active, pll->on,
e2b78267 1489 crtc->base.base.id);
92f2584a 1490
cdbd2316
DV		 1491 if (pll->active++) {
1492 WARN_ON(!pll->on);
e9d6944e 1493 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1494 return;
1495 }
f4a091c7 1496 WARN_ON(pll->on);
ee7b9f93 1497
46edb027 1498 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1499 pll->enable(dev_priv, pll);
ee7b9f93 1500 pll->on = true;
92f2584a
JB		 1501}
1502
e2b78267 1503static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1504{
e2b78267
DV		 1505 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1506 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1507
92f2584a
JB		 1508 /* PCH only available on ILK+ */
1509 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1510 if (WARN_ON(pll == NULL))
ee7b9f93 1511 return;
92f2584a 1512
48da64a8
CW		 1513 if (WARN_ON(pll->refcount == 0))
1514 return;
7a419866 1515
46edb027
DV		 1516 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1517 pll->name, pll->active, pll->on,
e2b78267 1518 crtc->base.base.id);
7a419866 1519
48da64a8 1520 if (WARN_ON(pll->active == 0)) {
e9d6944e 1521 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1522 return;
1523 }
1524
e9d6944e 1525 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1526 WARN_ON(!pll->on);
cdbd2316 1527 if (--pll->active)
7a419866 1528 return;
ee7b9f93 1529
46edb027 1530 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1531 pll->disable(dev_priv, pll);
ee7b9f93 1532 pll->on = false;
92f2584a
JB		 1533}
1534
b8a4f404
PZ		 1535static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536 enum pipe pipe)
040484af 1537{
23670b32 1538 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1539 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1541 uint32_t reg, val, pipeconf_val;
040484af
JB		 1542
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1545
1546 /* Make sure PCH DPLL is enabled */
e72f9fbf 1547 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1548 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1549
1550 /* FDI must be feeding us bits for PCH ports */
1551 assert_fdi_tx_enabled(dev_priv, pipe);
1552 assert_fdi_rx_enabled(dev_priv, pipe);
1553
23670b32
DV		 1554 if (HAS_PCH_CPT(dev)) {
1555 /* Workaround: Set the timing override bit before enabling the
1556 * pch transcoder. */
1557 reg = TRANS_CHICKEN2(pipe);
1558 val = I915_READ(reg);
1559 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1560 I915_WRITE(reg, val);
59c859d6 1561 }
23670b32 1562
ab9412ba 1563 reg = PCH_TRANSCONF(pipe);
040484af 1564 val = I915_READ(reg);
5f7f726d 1565 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1566
1567 if (HAS_PCH_IBX(dev_priv->dev)) {
1568 /*
1569 * make the BPC in transcoder be consistent with
1570 * that in pipeconf reg.
1571 */
dfd07d72
DV		 1572 val &= ~PIPECONF_BPC_MASK;
1573 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1574 }
5f7f726d
PZ		 1575
1576 val &= ~TRANS_INTERLACE_MASK;
1577 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1578 if (HAS_PCH_IBX(dev_priv->dev) &&
1579 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1580 val |= TRANS_LEGACY_INTERLACED_ILK;
1581 else
1582 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1583 else
1584 val |= TRANS_PROGRESSIVE;
1585
040484af
JB		 1586 I915_WRITE(reg, val | TRANS_ENABLE);
1587 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1588 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1589}
1590
8fb033d7 1591static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1592 enum transcoder cpu_transcoder)
040484af 1593{
8fb033d7 1594 u32 val, pipeconf_val;
8fb033d7
PZ		 1595
1596 /* PCH only available on ILK+ */
1597 BUG_ON(dev_priv->info->gen < 5);
1598
8fb033d7 1599 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1600 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1601 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1602
223a6fdf
PZ		 1603 /* Workaround: set timing override bit. */
1604 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1605 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1606 I915_WRITE(_TRANSA_CHICKEN2, val);
1607
25f3ef11 1608 val = TRANS_ENABLE;
937bb610 1609 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1610
9a76b1c6
PZ		 1611 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1612 PIPECONF_INTERLACED_ILK)
a35f2679 1613 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
ab9412ba
DV		 1617 I915_WRITE(LPT_TRANSCONF, val);
1618 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1619 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1620}
1621
b8a4f404
PZ		 1622static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
040484af 1624{
23670b32
DV		 1625 struct drm_device *dev = dev_priv->dev;
1626 uint32_t reg, val;
040484af
JB		 1627
1628 /* FDI relies on the transcoder */
1629 assert_fdi_tx_disabled(dev_priv, pipe);
1630 assert_fdi_rx_disabled(dev_priv, pipe);
1631
291906f1
JB		 1632 /* Ports must be off as well */
1633 assert_pch_ports_disabled(dev_priv, pipe);
1634
ab9412ba 1635 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1636 val = I915_READ(reg);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(reg, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1641 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1642
1643 if (!HAS_PCH_IBX(dev)) {
1644 /* Workaround: Clear the timing override chicken bit again. */
1645 reg = TRANS_CHICKEN2(pipe);
1646 val = I915_READ(reg);
1647 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1648 I915_WRITE(reg, val);
1649 }
040484af
JB		 1650}
1651
ab4d966c 1652static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1653{
8fb033d7
PZ		 1654 u32 val;
1655
ab9412ba 1656 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1657 val &= ~TRANS_ENABLE;
ab9412ba 1658 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1659 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1660 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1661 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1662
1663 /* Workaround: clear timing override bit. */
1664 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1665 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1666 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1667}
1668
b24e7179 1669/**
309cfea8 1670 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe to enable
040484af 1673 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1674 *
1675 * Enable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe is actually running (i.e. first vblank) before
1681 * returning.
1682 */
040484af 1683static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1684 bool pch_port, bool dsi)
b24e7179 1685{
702e7a56
PZ		 1686 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1687 pipe);
1a240d4d 1688 enum pipe pch_transcoder;
b24e7179
JB		 1689 int reg;
1690 u32 val;
1691
58c6eaa2 1692 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1693 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1694 assert_sprites_disabled(dev_priv, pipe);
1695
681e5811 1696 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1697 pch_transcoder = TRANSCODER_A;
1698 else
1699 pch_transcoder = pipe;
1700
b24e7179
JB		 1701 /*
1702 * A pipe without a PLL won't actually be able to drive bits from
1703 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1704 * need the check.
1705 */
1706 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1707 if (dsi)
1708 assert_dsi_pll_enabled(dev_priv);
1709 else
1710 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1711 else {
1712 if (pch_port) {
1713 /* if driving the PCH, we need FDI enabled */
cc391bbb 1714 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1715 assert_fdi_tx_pll_enabled(dev_priv,
1716 (enum pipe) cpu_transcoder);
040484af
JB		 1717 }
1718 /* FIXME: assert CPU port conditions for SNB+ */
1719 }
b24e7179 1720
702e7a56 1721 reg = PIPECONF(cpu_transcoder);
b24e7179 1722 val = I915_READ(reg);
00d70b15
CW		 1723 if (val & PIPECONF_ENABLE)
1724 return;
1725
1726 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1727 intel_wait_for_vblank(dev_priv->dev, pipe);
1728}
1729
1730/**
309cfea8 1731 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe to disable
1734 *
1735 * Disable @pipe, making sure that various hardware specific requirements
1736 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1737 *
1738 * @pipe should be %PIPE_A or %PIPE_B.
1739 *
1740 * Will wait until the pipe has shut down before returning.
1741 */
1742static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1743 enum pipe pipe)
1744{
702e7a56
PZ		 1745 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1746 pipe);
b24e7179
JB		 1747 int reg;
1748 u32 val;
1749
1750 /*
1751 * Make sure planes won't keep trying to pump pixels to us,
1752 * or we might hang the display.
1753 */
1754 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1755 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1756 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1757
1758 /* Don't disable pipe A or pipe A PLLs if needed */
1759 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1760 return;
1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if ((val & PIPECONF_ENABLE) == 0)
1765 return;
1766
1767 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1769}
1770
d74362c9
KP		 1771/*
1772 * Plane regs are double buffered, going from enabled->disabled needs a
1773 * trigger in order to latch. The display address reg provides this.
1774 */
6f1d69b0 1775void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1776 enum plane plane)
1777{
14f86147
DL		 1778 if (dev_priv->info->gen >= 4)
1779 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1780 else
1781 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1782}
1783
b24e7179
JB		 1784/**
1785 * intel_enable_plane - enable a display plane on a given pipe
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to enable
1788 * @pipe: pipe being fed
1789 *
1790 * Enable @plane on @pipe, making sure that @pipe is running first.
1791 */
1792static void intel_enable_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane, enum pipe pipe)
1794{
1795 int reg;
1796 u32 val;
1797
1798 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1799 assert_pipe_enabled(dev_priv, pipe);
1800
1801 reg = DSPCNTR(plane);
1802 val = I915_READ(reg);
00d70b15
CW		 1803 if (val & DISPLAY_PLANE_ENABLE)
1804 return;
1805
1806 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1807 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1808 intel_wait_for_vblank(dev_priv->dev, pipe);
1809}
1810
b24e7179
JB		 1811/**
1812 * intel_disable_plane - disable a display plane
1813 * @dev_priv: i915 private structure
1814 * @plane: plane to disable
1815 * @pipe: pipe consuming the data
1816 *
1817 * Disable @plane; should be an independent operation.
1818 */
1819static void intel_disable_plane(struct drm_i915_private *dev_priv,
1820 enum plane plane, enum pipe pipe)
1821{
1822 int reg;
1823 u32 val;
1824
1825 reg = DSPCNTR(plane);
1826 val = I915_READ(reg);
00d70b15
CW		 1827 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1828 return;
1829
1830 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1831 intel_flush_display_plane(dev_priv, plane);
1832 intel_wait_for_vblank(dev_priv->dev, pipe);
1833}
1834
693db184
CW		 1835static bool need_vtd_wa(struct drm_device *dev)
1836{
1837#ifdef CONFIG_INTEL_IOMMU
1838 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1839 return true;
1840#endif
1841 return false;
1842}
1843
127bd2ac 1844int
48b956c5 1845intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1846 struct drm_i915_gem_object *obj,
919926ae 1847 struct intel_ring_buffer *pipelined)
6b95a207 1848{
ce453d81 1849 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1850 u32 alignment;
1851 int ret;
1852
05394f39 1853 switch (obj->tiling_mode) {
6b95a207 1854 case I915_TILING_NONE:
534843da
CW		 1855 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1856 alignment = 128 * 1024;
a6c45cf0 1857 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1858 alignment = 4 * 1024;
1859 else
1860 alignment = 64 * 1024;
6b95a207
KH		 1861 break;
1862 case I915_TILING_X:
1863 /* pin() will align the object as required by fence */
1864 alignment = 0;
1865 break;
1866 case I915_TILING_Y:
8bb6e959
DV		 1867 /* Despite that we check this in framebuffer_init userspace can
1868 * screw us over and change the tiling after the fact. Only
1869 * pinned buffers can't change their tiling. */
1870 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1871 return -EINVAL;
1872 default:
1873 BUG();
1874 }
1875
693db184
CW		 1876 /* Note that the w/a also requires 64 PTE of padding following the
1877 * bo. We currently fill all unused PTE with the shadow page and so
1878 * we should always have valid PTE following the scanout preventing
1879 * the VT-d warning.
1880 */
1881 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1882 alignment = 256 * 1024;
1883
ce453d81 1884 dev_priv->mm.interruptible = false;
2da3b9b9 1885 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1886 if (ret)
ce453d81 1887 goto err_interruptible;
6b95a207
KH		 1888
1889 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1890 * fence, whereas 965+ only requires a fence if using
1891 * framebuffer compression. For simplicity, we always install
1892 * a fence as the cost is not that onerous.
1893 */
06d98131 1894 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1895 if (ret)
1896 goto err_unpin;
1690e1eb 1897
9a5a53b3 1898 i915_gem_object_pin_fence(obj);
6b95a207 1899
ce453d81 1900 dev_priv->mm.interruptible = true;
6b95a207 1901 return 0;
48b956c5
CW		 1902
1903err_unpin:
cc98b413 1904 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1905err_interruptible:
1906 dev_priv->mm.interruptible = true;
48b956c5 1907 return ret;
6b95a207
KH		 1908}
1909
1690e1eb
CW		 1910void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1911{
1912 i915_gem_object_unpin_fence(obj);
cc98b413 1913 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1914}
1915
c2c75131
DV		 1916/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1917 * is assumed to be a power-of-two. */
bc752862
CW		 1918unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1919 unsigned int tiling_mode,
1920 unsigned int cpp,
1921 unsigned int pitch)
c2c75131 1922{
bc752862
CW		 1923 if (tiling_mode != I915_TILING_NONE) {
1924 unsigned int tile_rows, tiles;
c2c75131 1925
bc752862
CW		 1926 tile_rows = *y / 8;
1927 *y %= 8;
c2c75131 1928
bc752862
CW		 1929 tiles = *x / (512/cpp);
1930 *x %= 512/cpp;
1931
1932 return tile_rows * pitch * 8 + tiles * 4096;
1933 } else {
1934 unsigned int offset;
1935
1936 offset = *y * pitch + *x * cpp;
1937 *y = 0;
1938 *x = (offset & 4095) / cpp;
1939 return offset & -4096;
1940 }
c2c75131
DV		 1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
84f44ce7 1961 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1972 switch (fb->pixel_format) {
1973 case DRM_FORMAT_C8:
81255565
JB		 1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
57779d06
VS		 1976 case DRM_FORMAT_XRGB1555:
1977 case DRM_FORMAT_ARGB1555:
1978 dspcntr |= DISPPLANE_BGRX555;
81255565 1979 break;
57779d06
VS		 1980 case DRM_FORMAT_RGB565:
1981 dspcntr |= DISPPLANE_BGRX565;
1982 break;
1983 case DRM_FORMAT_XRGB8888:
1984 case DRM_FORMAT_ARGB8888:
1985 dspcntr |= DISPPLANE_BGRX888;
1986 break;
1987 case DRM_FORMAT_XBGR8888:
1988 case DRM_FORMAT_ABGR8888:
1989 dspcntr |= DISPPLANE_RGBX888;
1990 break;
1991 case DRM_FORMAT_XRGB2101010:
1992 case DRM_FORMAT_ARGB2101010:
1993 dspcntr |= DISPPLANE_BGRX101010;
1994 break;
1995 case DRM_FORMAT_XBGR2101010:
1996 case DRM_FORMAT_ABGR2101010:
1997 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1998 break;
1999 default:
baba133a 2000 BUG();
81255565 2001 }
57779d06 2002
a6c45cf0 2003 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2004 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2005 dspcntr |= DISPPLANE_TILED;
2006 else
2007 dspcntr &= ~DISPPLANE_TILED;
2008 }
2009
de1aa629
VS		 2010 if (IS_G4X(dev))
2011 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2012
5eddb70b 2013 I915_WRITE(reg, dspcntr);
81255565 2014
e506a0c6 2015 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2016
c2c75131
DV		 2017 if (INTEL_INFO(dev)->gen >= 4) {
2018 intel_crtc->dspaddr_offset =
bc752862
CW		 2019 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2020 fb->bits_per_pixel / 8,
2021 fb->pitches[0]);
c2c75131
DV		 2022 linear_offset -= intel_crtc->dspaddr_offset;
2023 } else {
e506a0c6 2024 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2025 }
e506a0c6 2026
f343c5f6
BW		 2027 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2028 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2029 fb->pitches[0]);
01f2c773 2030 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2031 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2032 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2033 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2034 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2035 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2036 } else
f343c5f6 2037 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2038 POSTING_READ(reg);
81255565 2039
17638cd6
JB		 2040 return 0;
2041}
2042
2043static int ironlake_update_plane(struct drm_crtc *crtc,
2044 struct drm_framebuffer *fb, int x, int y)
2045{
2046 struct drm_device *dev = crtc->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049 struct intel_framebuffer *intel_fb;
2050 struct drm_i915_gem_object *obj;
2051 int plane = intel_crtc->plane;
e506a0c6 2052 unsigned long linear_offset;
17638cd6
JB		 2053 u32 dspcntr;
2054 u32 reg;
2055
2056 switch (plane) {
2057 case 0:
2058 case 1:
27f8227b 2059 case 2:
17638cd6
JB		 2060 break;
2061 default:
84f44ce7 2062 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2063 return -EINVAL;
2064 }
2065
2066 intel_fb = to_intel_framebuffer(fb);
2067 obj = intel_fb->obj;
2068
2069 reg = DSPCNTR(plane);
2070 dspcntr = I915_READ(reg);
2071 /* Mask out pixel format bits in case we change it */
2072 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2073 switch (fb->pixel_format) {
2074 case DRM_FORMAT_C8:
17638cd6
JB		 2075 dspcntr |= DISPPLANE_8BPP;
2076 break;
57779d06
VS		 2077 case DRM_FORMAT_RGB565:
2078 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2079 break;
57779d06
VS		 2080 case DRM_FORMAT_XRGB8888:
2081 case DRM_FORMAT_ARGB8888:
2082 dspcntr |= DISPPLANE_BGRX888;
2083 break;
2084 case DRM_FORMAT_XBGR8888:
2085 case DRM_FORMAT_ABGR8888:
2086 dspcntr |= DISPPLANE_RGBX888;
2087 break;
2088 case DRM_FORMAT_XRGB2101010:
2089 case DRM_FORMAT_ARGB2101010:
2090 dspcntr |= DISPPLANE_BGRX101010;
2091 break;
2092 case DRM_FORMAT_XBGR2101010:
2093 case DRM_FORMAT_ABGR2101010:
2094 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2095 break;
2096 default:
baba133a 2097 BUG();
17638cd6
JB		 2098 }
2099
2100 if (obj->tiling_mode != I915_TILING_NONE)
2101 dspcntr |= DISPPLANE_TILED;
2102 else
2103 dspcntr &= ~DISPPLANE_TILED;
2104
1f5d76db
PZ		 2105 if (IS_HASWELL(dev))
2106 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2107 else
2108 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2109
2110 I915_WRITE(reg, dspcntr);
2111
e506a0c6 2112 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2113 intel_crtc->dspaddr_offset =
bc752862
CW		 2114 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2115 fb->bits_per_pixel / 8,
2116 fb->pitches[0]);
c2c75131 2117 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2118
f343c5f6
BW		 2119 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2120 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2121 fb->pitches[0]);
01f2c773 2122 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2123 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2124 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2125 if (IS_HASWELL(dev)) {
2126 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2127 } else {
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPLINOFF(plane), linear_offset);
2130 }
17638cd6
JB		 2131 POSTING_READ(reg);
2132
2133 return 0;
2134}
2135
2136/* Assume fb object is pinned & idle & fenced and just update base pointers */
2137static int
2138intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2139 int x, int y, enum mode_set_atomic state)
2140{
2141 struct drm_device *dev = crtc->dev;
2142 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2143
6b8e6ed0
CW		 2144 if (dev_priv->display.disable_fbc)
2145 dev_priv->display.disable_fbc(dev);
3dec0095 2146 intel_increase_pllclock(crtc);
81255565 2147
6b8e6ed0 2148 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2149}
2150
96a02917
VS		 2151void intel_display_handle_reset(struct drm_device *dev)
2152{
2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 struct drm_crtc *crtc;
2155
2156 /*
2157 * Flips in the rings have been nuked by the reset,
2158 * so complete all pending flips so that user space
2159 * will get its events and not get stuck.
2160 *
2161 * Also update the base address of all primary
2162 * planes to the the last fb to make sure we're
2163 * showing the correct fb after a reset.
2164 *
2165 * Need to make two loops over the crtcs so that we
2166 * don't try to grab a crtc mutex before the
2167 * pending_flip_queue really got woken up.
2168 */
2169
2170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2172 enum plane plane = intel_crtc->plane;
2173
2174 intel_prepare_page_flip(dev, plane);
2175 intel_finish_page_flip_plane(dev, plane);
2176 }
2177
2178 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 mutex_lock(&crtc->mutex);
2182 if (intel_crtc->active)
2183 dev_priv->display.update_plane(crtc, crtc->fb,
2184 crtc->x, crtc->y);
2185 mutex_unlock(&crtc->mutex);
2186 }
2187}
2188
14667a4b
CW		 2189static int
2190intel_finish_fb(struct drm_framebuffer *old_fb)
2191{
2192 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194 bool was_interruptible = dev_priv->mm.interruptible;
2195 int ret;
2196
14667a4b
CW		 2197 /* Big Hammer, we also need to ensure that any pending
2198 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2199 * current scanout is retired before unpinning the old
2200 * framebuffer.
2201 *
2202 * This should only fail upon a hung GPU, in which case we
2203 * can safely continue.
2204 */
2205 dev_priv->mm.interruptible = false;
2206 ret = i915_gem_object_finish_gpu(obj);
2207 dev_priv->mm.interruptible = was_interruptible;
2208
2209 return ret;
2210}
2211
198598d0
VS		 2212static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2213{
2214 struct drm_device *dev = crtc->dev;
2215 struct drm_i915_master_private *master_priv;
2216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217
2218 if (!dev->primary->master)
2219 return;
2220
2221 master_priv = dev->primary->master->driver_priv;
2222 if (!master_priv->sarea_priv)
2223 return;
2224
2225 switch (intel_crtc->pipe) {
2226 case 0:
2227 master_priv->sarea_priv->pipeA_x = x;
2228 master_priv->sarea_priv->pipeA_y = y;
2229 break;
2230 case 1:
2231 master_priv->sarea_priv->pipeB_x = x;
2232 master_priv->sarea_priv->pipeB_y = y;
2233 break;
2234 default:
2235 break;
2236 }
2237}
2238
5c3b82e2 2239static int
3c4fdcfb 2240intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2241 struct drm_framebuffer *fb)
79e53945
JB		 2242{
2243 struct drm_device *dev = crtc->dev;
6b8e6ed0 2244 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2246 struct drm_framebuffer *old_fb;
5c3b82e2 2247 int ret;
79e53945
JB		 2248
2249 /* no fb bound */
94352cf9 2250 if (!fb) {
a5071c2f 2251 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2252 return 0;
2253 }
2254
7eb552ae 2255 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2256 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2257 plane_name(intel_crtc->plane),
2258 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2259 return -EINVAL;
79e53945
JB		 2260 }
2261
5c3b82e2 2262 mutex_lock(&dev->struct_mutex);
265db958 2263 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2264 to_intel_framebuffer(fb)->obj,
919926ae 2265 NULL);
5c3b82e2
CW		 2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2269 return ret;
2270 }
79e53945 2271
4d6a3e63
JB		 2272 /* Update pipe size and adjust fitter if needed */
2273 if (i915_fastboot) {
2274 I915_WRITE(PIPESRC(intel_crtc->pipe),
2275 ((crtc->mode.hdisplay - 1) << 16) |
2276 (crtc->mode.vdisplay - 1));
2277 if (!intel_crtc->config.pch_pfit.size &&
2278 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2279 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2280 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2281 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2282 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2283 }
2284 }
2285
94352cf9 2286 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2287 if (ret) {
94352cf9 2288 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2289 mutex_unlock(&dev->struct_mutex);
a5071c2f 2290 DRM_ERROR("failed to update base address\n");
4e6cfefc 2291 return ret;
79e53945 2292 }
3c4fdcfb 2293
94352cf9
DV		 2294 old_fb = crtc->fb;
2295 crtc->fb = fb;
6c4c86f5
DV		 2296 crtc->x = x;
2297 crtc->y = y;
94352cf9 2298
b7f1de28 2299 if (old_fb) {
d7697eea
DV		 2300 if (intel_crtc->active && old_fb != fb)
2301 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2302 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2303 }
652c393a 2304
6b8e6ed0 2305 intel_update_fbc(dev);
4906557e 2306 intel_edp_psr_update(dev);
5c3b82e2 2307 mutex_unlock(&dev->struct_mutex);
79e53945 2308
198598d0 2309 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2310
2311 return 0;
79e53945
JB		 2312}
2313
5e84e1a4
ZW		 2314static void intel_fdi_normal_train(struct drm_crtc *crtc)
2315{
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319 int pipe = intel_crtc->pipe;
2320 u32 reg, temp;
2321
2322 /* enable normal train */
2323 reg = FDI_TX_CTL(pipe);
2324 temp = I915_READ(reg);
61e499bf 2325 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2326 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2327 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2328 } else {
2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2331 }
5e84e1a4
ZW		 2332 I915_WRITE(reg, temp);
2333
2334 reg = FDI_RX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (HAS_PCH_CPT(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2338 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE;
2342 }
2343 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2344
2345 /* wait one idle pattern time */
2346 POSTING_READ(reg);
2347 udelay(1000);
357555c0
JB		 2348
2349 /* IVB wants error correction enabled */
2350 if (IS_IVYBRIDGE(dev))
2351 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2352 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2353}
2354
1e833f40
DV		 2355static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2356{
2357 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2358}
2359
01a415fd
DV		 2360static void ivb_modeset_global_resources(struct drm_device *dev)
2361{
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *pipe_B_crtc =
2364 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2365 struct intel_crtc *pipe_C_crtc =
2366 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2367 uint32_t temp;
2368
1e833f40
DV		 2369 /*
2370 * When everything is off disable fdi C so that we could enable fdi B
2371 * with all lanes. Note that we don't care about enabled pipes without
2372 * an enabled pch encoder.
2373 */
2374 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2375 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2376 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2378
2379 temp = I915_READ(SOUTH_CHICKEN1);
2380 temp &= ~FDI_BC_BIFURCATION_SELECT;
2381 DRM_DEBUG_KMS("disabling fdi C rx\n");
2382 I915_WRITE(SOUTH_CHICKEN1, temp);
2383 }
2384}
2385
8db9d77b
ZW		 2386/* The FDI link training functions for ILK/Ibexpeak. */
2387static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2388{
2389 struct drm_device *dev = crtc->dev;
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2392 int pipe = intel_crtc->pipe;
0fc932b8 2393 int plane = intel_crtc->plane;
5eddb70b 2394 u32 reg, temp, tries;
8db9d77b 2395
0fc932b8
JB		 2396 /* FDI needs bits from pipe & plane first */
2397 assert_pipe_enabled(dev_priv, pipe);
2398 assert_plane_enabled(dev_priv, plane);
2399
e1a44743
AJ		 2400 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2401 for train result */
5eddb70b
CW		 2402 reg = FDI_RX_IMR(pipe);
2403 temp = I915_READ(reg);
e1a44743
AJ		 2404 temp &= ~FDI_RX_SYMBOL_LOCK;
2405 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2406 I915_WRITE(reg, temp);
2407 I915_READ(reg);
e1a44743
AJ		 2408 udelay(150);
2409
8db9d77b 2410 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2411 reg = FDI_TX_CTL(pipe);
2412 temp = I915_READ(reg);
627eb5a3
DV		 2413 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2414 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
5eddb70b
CW		 2419 reg = FDI_RX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2423 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2424
2425 POSTING_READ(reg);
8db9d77b
ZW		 2426 udelay(150);
2427
5b2adf89 2428 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2431 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2432
5eddb70b 2433 reg = FDI_RX_IIR(pipe);
e1a44743 2434 for (tries = 0; tries < 5; tries++) {
5eddb70b 2435 temp = I915_READ(reg);
8db9d77b
ZW		 2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438 if ((temp & FDI_RX_BIT_LOCK)) {
2439 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2441 break;
2442 }
8db9d77b 2443 }
e1a44743 2444 if (tries == 5)
5eddb70b 2445 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2446
2447 /* Train 2 */
5eddb70b
CW		 2448 reg = FDI_TX_CTL(pipe);
2449 temp = I915_READ(reg);
8db9d77b
ZW		 2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2452 I915_WRITE(reg, temp);
8db9d77b 2453
5eddb70b
CW		 2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 temp &= ~FDI_LINK_TRAIN_NONE;
2457 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2458 I915_WRITE(reg, temp);
8db9d77b 2459
5eddb70b
CW		 2460 POSTING_READ(reg);
2461 udelay(150);
8db9d77b 2462
5eddb70b 2463 reg = FDI_RX_IIR(pipe);
e1a44743 2464 for (tries = 0; tries < 5; tries++) {
5eddb70b 2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467
2468 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2469 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2470 DRM_DEBUG_KMS("FDI train 2 done.\n");
2471 break;
2472 }
8db9d77b 2473 }
e1a44743 2474 if (tries == 5)
5eddb70b 2475 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2476
2477 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2478
8db9d77b
ZW		 2479}
2480
0206e353 2481static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2482 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2483 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2484 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2485 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2486};
2487
2488/* The FDI link training functions for SNB/Cougarpoint. */
2489static void gen6_fdi_link_train(struct drm_crtc *crtc)
2490{
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
fa37d39e 2495 u32 reg, temp, i, retry;
8db9d77b 2496
e1a44743
AJ		 2497 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2498 for train result */
5eddb70b
CW		 2499 reg = FDI_RX_IMR(pipe);
2500 temp = I915_READ(reg);
e1a44743
AJ		 2501 temp &= ~FDI_RX_SYMBOL_LOCK;
2502 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2503 I915_WRITE(reg, temp);
2504
2505 POSTING_READ(reg);
e1a44743
AJ		 2506 udelay(150);
2507
8db9d77b 2508 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2509 reg = FDI_TX_CTL(pipe);
2510 temp = I915_READ(reg);
627eb5a3
DV		 2511 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2512 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 /* SNB-B */
2517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2518 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2519
d74cf324
DV		 2520 I915_WRITE(FDI_RX_MISC(pipe),
2521 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2522
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 if (HAS_PCH_CPT(dev)) {
2526 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2528 } else {
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 }
5eddb70b
CW		 2532 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2533
2534 POSTING_READ(reg);
8db9d77b
ZW		 2535 udelay(150);
2536
0206e353 2537 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
8db9d77b
ZW		 2540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2542 I915_WRITE(reg, temp);
2543
2544 POSTING_READ(reg);
8db9d77b
ZW		 2545 udelay(500);
2546
fa37d39e
SP		 2547 for (retry = 0; retry < 5; retry++) {
2548 reg = FDI_RX_IIR(pipe);
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551 if (temp & FDI_RX_BIT_LOCK) {
2552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
2554 break;
2555 }
2556 udelay(50);
8db9d77b 2557 }
fa37d39e
SP		 2558 if (retry < 5)
2559 break;
8db9d77b
ZW		 2560 }
2561 if (i == 4)
5eddb70b 2562 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2563
2564 /* Train 2 */
5eddb70b
CW		 2565 reg = FDI_TX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 temp &= ~FDI_LINK_TRAIN_NONE;
2568 temp |= FDI_LINK_TRAIN_PATTERN_2;
2569 if (IS_GEN6(dev)) {
2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 /* SNB-B */
2572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573 }
5eddb70b 2574 I915_WRITE(reg, temp);
8db9d77b 2575
5eddb70b
CW		 2576 reg = FDI_RX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 if (HAS_PCH_CPT(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2580 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2581 } else {
2582 temp &= ~FDI_LINK_TRAIN_NONE;
2583 temp |= FDI_LINK_TRAIN_PATTERN_2;
2584 }
5eddb70b
CW		 2585 I915_WRITE(reg, temp);
2586
2587 POSTING_READ(reg);
8db9d77b
ZW		 2588 udelay(150);
2589
0206e353 2590 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2591 reg = FDI_TX_CTL(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2595 I915_WRITE(reg, temp);
2596
2597 POSTING_READ(reg);
8db9d77b
ZW		 2598 udelay(500);
2599
fa37d39e
SP		 2600 for (retry = 0; retry < 5; retry++) {
2601 reg = FDI_RX_IIR(pipe);
2602 temp = I915_READ(reg);
2603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2604 if (temp & FDI_RX_SYMBOL_LOCK) {
2605 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2606 DRM_DEBUG_KMS("FDI train 2 done.\n");
2607 break;
2608 }
2609 udelay(50);
8db9d77b 2610 }
fa37d39e
SP		 2611 if (retry < 5)
2612 break;
8db9d77b
ZW		 2613 }
2614 if (i == 4)
5eddb70b 2615 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2616
2617 DRM_DEBUG_KMS("FDI train done.\n");
2618}
2619
357555c0
JB		 2620/* Manual link training for Ivy Bridge A0 parts */
2621static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2622{
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626 int pipe = intel_crtc->pipe;
139ccd3f 2627 u32 reg, temp, i, j;
357555c0
JB		 2628
2629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2630 for train result */
2631 reg = FDI_RX_IMR(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_RX_SYMBOL_LOCK;
2634 temp &= ~FDI_RX_BIT_LOCK;
2635 I915_WRITE(reg, temp);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
01a415fd
DV		 2640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2641 I915_READ(FDI_RX_IIR(pipe)));
2642
139ccd3f
JB		 2643 /* Try each vswing and preemphasis setting twice before moving on */
2644 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2645 /* disable first in case we need to retry */
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2649 temp &= ~FDI_TX_ENABLE;
2650 I915_WRITE(reg, temp);
357555c0 2651
139ccd3f
JB		 2652 reg = FDI_RX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_AUTO;
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp &= ~FDI_RX_ENABLE;
2657 I915_WRITE(reg, temp);
357555c0 2658
139ccd3f 2659 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
139ccd3f
JB		 2662 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2666 temp |= snb_b_fdi_train_param[j/2];
2667 temp |= FDI_COMPOSITE_SYNC;
2668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2669
139ccd3f
JB		 2670 I915_WRITE(FDI_RX_MISC(pipe),
2671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2672
139ccd3f 2673 reg = FDI_RX_CTL(pipe);
357555c0 2674 temp = I915_READ(reg);
139ccd3f
JB		 2675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2676 temp |= FDI_COMPOSITE_SYNC;
2677 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2678
139ccd3f
JB		 2679 POSTING_READ(reg);
2680 udelay(1); /* should be 0.5us */
357555c0 2681
139ccd3f
JB		 2682 for (i = 0; i < 4; i++) {
2683 reg = FDI_RX_IIR(pipe);
2684 temp = I915_READ(reg);
2685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2686
139ccd3f
JB		 2687 if (temp & FDI_RX_BIT_LOCK ||
2688 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2689 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2691 i);
2692 break;
2693 }
2694 udelay(1); /* should be 0.5us */
2695 }
2696 if (i == 4) {
2697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2698 continue;
2699 }
357555c0 2700
139ccd3f 2701 /* Train 2 */
357555c0
JB		 2702 reg = FDI_TX_CTL(pipe);
2703 temp = I915_READ(reg);
139ccd3f
JB		 2704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2706 I915_WRITE(reg, temp);
2707
2708 reg = FDI_RX_CTL(pipe);
2709 temp = I915_READ(reg);
2710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2712 I915_WRITE(reg, temp);
2713
2714 POSTING_READ(reg);
139ccd3f 2715 udelay(2); /* should be 1.5us */
357555c0 2716
139ccd3f
JB		 2717 for (i = 0; i < 4; i++) {
2718 reg = FDI_RX_IIR(pipe);
2719 temp = I915_READ(reg);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2721
139ccd3f
JB		 2722 if (temp & FDI_RX_SYMBOL_LOCK ||
2723 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2726 i);
2727 goto train_done;
2728 }
2729 udelay(2); /* should be 1.5us */
357555c0 2730 }
139ccd3f
JB		 2731 if (i == 4)
2732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2733 }
357555c0 2734
139ccd3f 2735train_done:
357555c0
JB		 2736 DRM_DEBUG_KMS("FDI train done.\n");
2737}
2738
88cefb6c 2739static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2740{
88cefb6c 2741 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2742 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2743 int pipe = intel_crtc->pipe;
5eddb70b 2744 u32 reg, temp;
79e53945 2745
c64e311e 2746
c98e9dcf 2747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
627eb5a3
DV		 2750 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2751 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2754
2755 POSTING_READ(reg);
c98e9dcf
JB		 2756 udelay(200);
2757
2758 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp | FDI_PCDCLK);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
20749730
PZ		 2765 /* Enable CPU FDI TX PLL, always on for Ironlake */
2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2770
20749730
PZ		 2771 POSTING_READ(reg);
2772 udelay(100);
6be4a607 2773 }
0e23b99d
JB		 2774}
2775
88cefb6c
DV		 2776static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2777{
2778 struct drm_device *dev = intel_crtc->base.dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 int pipe = intel_crtc->pipe;
2781 u32 reg, temp;
2782
2783 /* Switch from PCDclk to Rawclk */
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787
2788 /* Disable CPU FDI TX PLL */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2792
2793 POSTING_READ(reg);
2794 udelay(100);
2795
2796 reg = FDI_RX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799
2800 /* Wait for the clocks to turn off. */
2801 POSTING_READ(reg);
2802 udelay(100);
2803}
2804
0fc932b8
JB		 2805static void ironlake_fdi_disable(struct drm_crtc *crtc)
2806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* disable CPU FDI tx and PCH FDI rx */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2817 POSTING_READ(reg);
2818
2819 reg = FDI_RX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~(0x7 << 16);
dfd07d72 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2823 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2824
2825 POSTING_READ(reg);
2826 udelay(100);
2827
2828 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2829 if (HAS_PCH_IBX(dev)) {
2830 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2831 }
0fc932b8
JB		 2832
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845 } else {
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 }
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
dfd07d72 2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2852 I915_WRITE(reg, temp);
2853
2854 POSTING_READ(reg);
2855 udelay(100);
2856}
2857
5bb61643
CW		 2858static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2859{
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2863 unsigned long flags;
2864 bool pending;
2865
10d83730
VS		 2866 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2867 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2868 return false;
2869
2870 spin_lock_irqsave(&dev->event_lock, flags);
2871 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2872 spin_unlock_irqrestore(&dev->event_lock, flags);
2873
2874 return pending;
2875}
2876
e6c3a2a6
CW		 2877static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878{
0f91128d 2879 struct drm_device *dev = crtc->dev;
5bb61643 2880 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2881
2882 if (crtc->fb == NULL)
2883 return;
2884
2c10d571
DV		 2885 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2886
5bb61643
CW		 2887 wait_event(dev_priv->pending_flip_queue,
2888 !intel_crtc_has_pending_flip(crtc));
2889
0f91128d
CW		 2890 mutex_lock(&dev->struct_mutex);
2891 intel_finish_fb(crtc->fb);
2892 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2893}
2894
e615efe4
ED		 2895/* Program iCLKIP clock to the desired frequency */
2896static void lpt_program_iclkip(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2901 u32 temp;
2902
09153000
DV		 2903 mutex_lock(&dev_priv->dpio_lock);
2904
e615efe4
ED		 2905 /* It is necessary to ungate the pixclk gate prior to programming
2906 * the divisors, and gate it back when it is done.
2907 */
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2909
2910 /* Disable SSCCTL */
2911 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2912 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2913 SBI_SSCCTL_DISABLE,
2914 SBI_ICLK);
e615efe4
ED		 2915
2916 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2917 if (crtc->mode.clock == 20000) {
2918 auxdiv = 1;
2919 divsel = 0x41;
2920 phaseinc = 0x20;
2921 } else {
2922 /* The iCLK virtual clock root frequency is in MHz,
2923 * but the crtc->mode.clock in in KHz. To get the divisors,
2924 * it is necessary to divide one by another, so we
2925 * convert the virtual clock precision to KHz here for higher
2926 * precision.
2927 */
2928 u32 iclk_virtual_root_freq = 172800 * 1000;
2929 u32 iclk_pi_range = 64;
2930 u32 desired_divisor, msb_divisor_value, pi_value;
2931
2932 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2933 msb_divisor_value = desired_divisor / iclk_pi_range;
2934 pi_value = desired_divisor % iclk_pi_range;
2935
2936 auxdiv = 0;
2937 divsel = msb_divisor_value - 2;
2938 phaseinc = pi_value;
2939 }
2940
2941 /* This should not happen with any sane values */
2942 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2943 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2944 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2945 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2946
2947 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2948 crtc->mode.clock,
2949 auxdiv,
2950 divsel,
2951 phasedir,
2952 phaseinc);
2953
2954 /* Program SSCDIVINTPHASE6 */
988d6ee8 2955 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2956 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2957 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2958 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2959 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2960 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2961 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2962 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2963
2964 /* Program SSCAUXDIV */
988d6ee8 2965 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2966 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2967 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2968 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2969
2970 /* Enable modulator and associated divider */
988d6ee8 2971 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2972 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2973 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2974
2975 /* Wait for initialization time */
2976 udelay(24);
2977
2978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2979
2980 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2981}
2982
275f01b2
DV		 2983static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2984 enum pipe pch_transcoder)
2985{
2986 struct drm_device *dev = crtc->base.dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2989
2990 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2991 I915_READ(HTOTAL(cpu_transcoder)));
2992 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2993 I915_READ(HBLANK(cpu_transcoder)));
2994 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2995 I915_READ(HSYNC(cpu_transcoder)));
2996
2997 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2998 I915_READ(VTOTAL(cpu_transcoder)));
2999 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3000 I915_READ(VBLANK(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3002 I915_READ(VSYNC(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3004 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3005}
3006
f67a559d
JB		 3007/*
3008 * Enable PCH resources required for PCH ports:
3009 * - PCH PLLs
3010 * - FDI training & RX/TX
3011 * - update transcoder timings
3012 * - DP transcoding bits
3013 * - transcoder
3014 */
3015static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3016{
3017 struct drm_device *dev = crtc->dev;
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020 int pipe = intel_crtc->pipe;
ee7b9f93 3021 u32 reg, temp;
2c07245f 3022
ab9412ba 3023 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3024
cd986abb
DV		 3025 /* Write the TU size bits before fdi link training, so that error
3026 * detection works. */
3027 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3028 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3029
c98e9dcf 3030 /* For PCH output, training FDI link */
674cf967 3031 dev_priv->display.fdi_link_train(crtc);
2c07245f 3032
3ad8a208
DV		 3033 /* We need to program the right clock selection before writing the pixel
3034 * mutliplier into the DPLL. */
303b81e0 3035 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3036 u32 sel;
4b645f14 3037
c98e9dcf 3038 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3039 temp |= TRANS_DPLL_ENABLE(pipe);
3040 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3041 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3042 temp |= sel;
3043 else
3044 temp &= ~sel;
c98e9dcf 3045 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3046 }
5eddb70b 3047
3ad8a208
DV		 3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3051 *
3052 * Note that enable_shared_dpll tries to do the right thing, but
3053 * get_shared_dpll unconditionally resets the pll - we need that to have
3054 * the right LVDS enable sequence. */
3055 ironlake_enable_shared_dpll(intel_crtc);
3056
d9b6cb56
JB		 3057 /* set transcoder timing, panel must allow it */
3058 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3059 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3060
303b81e0 3061 intel_fdi_normal_train(crtc);
5e84e1a4 3062
c98e9dcf
JB		 3063 /* For PCH DP, enable TRANS_DP_CTL */
3064 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3065 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3066 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3067 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3068 reg = TRANS_DP_CTL(pipe);
3069 temp = I915_READ(reg);
3070 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3071 TRANS_DP_SYNC_MASK |
3072 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3073 temp |= (TRANS_DP_OUTPUT_ENABLE |
3074 TRANS_DP_ENH_FRAMING);
9325c9f0 3075 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3076
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3078 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3079 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3080 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3081
3082 switch (intel_trans_dp_port_sel(crtc)) {
3083 case PCH_DP_B:
5eddb70b 3084 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3085 break;
3086 case PCH_DP_C:
5eddb70b 3087 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3088 break;
3089 case PCH_DP_D:
5eddb70b 3090 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3091 break;
3092 default:
e95d41e1 3093 BUG();
32f9d658 3094 }
2c07245f 3095
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607 3097 }
b52eb4dc 3098
b8a4f404 3099 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3100}
3101
1507e5bd
PZ		 3102static void lpt_pch_enable(struct drm_crtc *crtc)
3103{
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3107 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3108
ab9412ba 3109 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3110
8c52b5e8 3111 lpt_program_iclkip(crtc);
1507e5bd 3112
0540e488 3113 /* Set transcoder timing. */
275f01b2 3114 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3115
937bb610 3116 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3117}
3118
e2b78267 3119static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3120{
e2b78267 3121 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3122
3123 if (pll == NULL)
3124 return;
3125
3126 if (pll->refcount == 0) {
46edb027 3127 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3128 return;
3129 }
3130
f4a091c7
DV		 3131 if (--pll->refcount == 0) {
3132 WARN_ON(pll->on);
3133 WARN_ON(pll->active);
3134 }
3135
a43f6e0f 3136 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3137}
3138
b89a1d39 3139static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3140{
e2b78267
DV		 3141 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3142 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3143 enum intel_dpll_id i;
ee7b9f93 3144
ee7b9f93 3145 if (pll) {
46edb027
DV		 3146 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3147 crtc->base.base.id, pll->name);
e2b78267 3148 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3149 }
3150
98b6bd99
DV		 3151 if (HAS_PCH_IBX(dev_priv->dev)) {
3152 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3153 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3154 pll = &dev_priv->shared_dplls[i];
98b6bd99 3155
46edb027
DV		 3156 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3157 crtc->base.base.id, pll->name);
98b6bd99
DV		 3158
3159 goto found;
3160 }
3161
e72f9fbf
DV		 3162 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3163 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3164
3165 /* Only want to check enabled timings first */
3166 if (pll->refcount == 0)
3167 continue;
3168
b89a1d39
DV		 3169 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3170 sizeof(pll->hw_state)) == 0) {
46edb027 3171 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3172 crtc->base.base.id,
46edb027 3173 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3174
3175 goto found;
3176 }
3177 }
3178
3179 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3182 if (pll->refcount == 0) {
46edb027
DV		 3183 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3184 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3185 goto found;
3186 }
3187 }
3188
3189 return NULL;
3190
3191found:
a43f6e0f 3192 crtc->config.shared_dpll = i;
46edb027
DV		 3193 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3194 pipe_name(crtc->pipe));
ee7b9f93 3195
cdbd2316 3196 if (pll->active == 0) {
66e985c0
DV		 3197 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3198 sizeof(pll->hw_state));
3199
46edb027 3200 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3201 WARN_ON(pll->on);
e9d6944e 3202 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3203
15bdd4cf 3204 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3205 }
3206 pll->refcount++;
e04c7350 3207
ee7b9f93
JB		 3208 return pll;
3209}
3210
a1520318 3211static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3212{
3213 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3214 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3215 u32 temp;
3216
3217 temp = I915_READ(dslreg);
3218 udelay(500);
3219 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3220 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3221 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3222 }
3223}
3224
b074cec8
JB		 3225static void ironlake_pfit_enable(struct intel_crtc *crtc)
3226{
3227 struct drm_device *dev = crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int pipe = crtc->pipe;
3230
0ef37f3f 3231 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3232 /* Force use of hard-coded filter coefficients
3233 * as some pre-programmed values are broken,
3234 * e.g. x201.
3235 */
3236 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3237 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3238 PF_PIPE_SEL_IVB(pipe));
3239 else
3240 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3241 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3242 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3243 }
3244}
3245
bb53d4ae
VS		 3246static void intel_enable_planes(struct drm_crtc *crtc)
3247{
3248 struct drm_device *dev = crtc->dev;
3249 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3250 struct intel_plane *intel_plane;
3251
3252 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3253 if (intel_plane->pipe == pipe)
3254 intel_plane_restore(&intel_plane->base);
3255}
3256
3257static void intel_disable_planes(struct drm_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->dev;
3260 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3261 struct intel_plane *intel_plane;
3262
3263 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3264 if (intel_plane->pipe == pipe)
3265 intel_plane_disable(&intel_plane->base);
3266}
3267
f67a559d
JB		 3268static void ironlake_crtc_enable(struct drm_crtc *crtc)
3269{
3270 struct drm_device *dev = crtc->dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3273 struct intel_encoder *encoder;
f67a559d
JB		 3274 int pipe = intel_crtc->pipe;
3275 int plane = intel_crtc->plane;
f67a559d 3276
08a48469
DV		 3277 WARN_ON(!crtc->enabled);
3278
f67a559d
JB		 3279 if (intel_crtc->active)
3280 return;
3281
3282 intel_crtc->active = true;
8664281b
PZ		 3283
3284 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
f6736a1a 3287 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3288 if (encoder->pre_enable)
3289 encoder->pre_enable(encoder);
f67a559d 3290
5bfe2ac0 3291 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3292 /* Note: FDI PLL enabling _must_ be done before we enable the
3293 * cpu pipes, hence this is separate from all the other fdi/pch
3294 * enabling. */
88cefb6c 3295 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3296 } else {
3297 assert_fdi_tx_disabled(dev_priv, pipe);
3298 assert_fdi_rx_disabled(dev_priv, pipe);
3299 }
f67a559d 3300
b074cec8 3301 ironlake_pfit_enable(intel_crtc);
f67a559d 3302
9c54c0dd
JB		 3303 /*
3304 * On ILK+ LUT must be loaded before the pipe is running but with
3305 * clocks enabled
3306 */
3307 intel_crtc_load_lut(crtc);
3308
f37fcc2a 3309 intel_update_watermarks(crtc);
5bfe2ac0 3310 intel_enable_pipe(dev_priv, pipe,
23538ef1 3311 intel_crtc->config.has_pch_encoder, false);
f67a559d 3312 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3313 intel_enable_planes(crtc);
5c38d48c 3314 intel_crtc_update_cursor(crtc, true);
f67a559d 3315
5bfe2ac0 3316 if (intel_crtc->config.has_pch_encoder)
f67a559d 3317 ironlake_pch_enable(crtc);
c98e9dcf 3318
d1ebd816 3319 mutex_lock(&dev->struct_mutex);
bed4a673 3320 intel_update_fbc(dev);
d1ebd816
BW		 3321 mutex_unlock(&dev->struct_mutex);
3322
fa5c73b1
DV		 3323 for_each_encoder_on_crtc(dev, crtc, encoder)
3324 encoder->enable(encoder);
61b77ddd
DV		 3325
3326 if (HAS_PCH_CPT(dev))
a1520318 3327 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3328
3329 /*
3330 * There seems to be a race in PCH platform hw (at least on some
3331 * outputs) where an enabled pipe still completes any pageflip right
3332 * away (as if the pipe is off) instead of waiting for vblank. As soon
3333 * as the first vblank happend, everything works as expected. Hence just
3334 * wait for one vblank before returning to avoid strange things
3335 * happening.
3336 */
3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3338}
3339
42db64ef
PZ		 3340/* IPS only exists on ULT machines and is tied to pipe A. */
3341static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3342{
f5adf94e 3343 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3344}
3345
3346static void hsw_enable_ips(struct intel_crtc *crtc)
3347{
3348 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3349
3350 if (!crtc->config.ips_enabled)
3351 return;
3352
3353 /* We can only enable IPS after we enable a plane and wait for a vblank.
3354 * We guarantee that the plane is enabled by calling intel_enable_ips
3355 * only after intel_enable_plane. And intel_enable_plane already waits
3356 * for a vblank, so all we need to do here is to enable the IPS bit. */
3357 assert_plane_enabled(dev_priv, crtc->plane);
3358 I915_WRITE(IPS_CTL, IPS_ENABLE);
3359}
3360
3361static void hsw_disable_ips(struct intel_crtc *crtc)
3362{
3363 struct drm_device *dev = crtc->base.dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366 if (!crtc->config.ips_enabled)
3367 return;
3368
3369 assert_plane_enabled(dev_priv, crtc->plane);
3370 I915_WRITE(IPS_CTL, 0);
3371
3372 /* We need to wait for a vblank before we can disable the plane. */
3373 intel_wait_for_vblank(dev, crtc->pipe);
3374}
3375
4f771f10
PZ		 3376static void haswell_crtc_enable(struct drm_crtc *crtc)
3377{
3378 struct drm_device *dev = crtc->dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381 struct intel_encoder *encoder;
3382 int pipe = intel_crtc->pipe;
3383 int plane = intel_crtc->plane;
4f771f10
PZ		 3384
3385 WARN_ON(!crtc->enabled);
3386
3387 if (intel_crtc->active)
3388 return;
3389
3390 intel_crtc->active = true;
8664281b
PZ		 3391
3392 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3393 if (intel_crtc->config.has_pch_encoder)
3394 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
04945641 3397 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 if (encoder->pre_enable)
3401 encoder->pre_enable(encoder);
3402
1f544388 3403 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3404
b074cec8 3405 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3406
3407 /*
3408 * On ILK+ LUT must be loaded before the pipe is running but with
3409 * clocks enabled
3410 */
3411 intel_crtc_load_lut(crtc);
3412
1f544388 3413 intel_ddi_set_pipe_settings(crtc);
8228c251 3414 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3415
f37fcc2a 3416 intel_update_watermarks(crtc);
5bfe2ac0 3417 intel_enable_pipe(dev_priv, pipe,
23538ef1 3418 intel_crtc->config.has_pch_encoder, false);
4f771f10 3419 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3420 intel_enable_planes(crtc);
5c38d48c 3421 intel_crtc_update_cursor(crtc, true);
4f771f10 3422
42db64ef
PZ		 3423 hsw_enable_ips(intel_crtc);
3424
5bfe2ac0 3425 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3426 lpt_pch_enable(crtc);
4f771f10
PZ		 3427
3428 mutex_lock(&dev->struct_mutex);
3429 intel_update_fbc(dev);
3430 mutex_unlock(&dev->struct_mutex);
3431
8807e55b 3432 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3433 encoder->enable(encoder);
8807e55b
JN		 3434 intel_opregion_notify_encoder(encoder, true);
3435 }
4f771f10 3436
4f771f10
PZ		 3437 /*
3438 * There seems to be a race in PCH platform hw (at least on some
3439 * outputs) where an enabled pipe still completes any pageflip right
3440 * away (as if the pipe is off) instead of waiting for vblank. As soon
3441 * as the first vblank happend, everything works as expected. Hence just
3442 * wait for one vblank before returning to avoid strange things
3443 * happening.
3444 */
3445 intel_wait_for_vblank(dev, intel_crtc->pipe);
3446}
3447
3f8dce3a
DV		 3448static void ironlake_pfit_disable(struct intel_crtc *crtc)
3449{
3450 struct drm_device *dev = crtc->base.dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 int pipe = crtc->pipe;
3453
3454 /* To avoid upsetting the power well on haswell only disable the pfit if
3455 * it's in use. The hw state code will make sure we get this right. */
3456 if (crtc->config.pch_pfit.size) {
3457 I915_WRITE(PF_CTL(pipe), 0);
3458 I915_WRITE(PF_WIN_POS(pipe), 0);
3459 I915_WRITE(PF_WIN_SZ(pipe), 0);
3460 }
3461}
3462
6be4a607
JB		 3463static void ironlake_crtc_disable(struct drm_crtc *crtc)
3464{
3465 struct drm_device *dev = crtc->dev;
3466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3468 struct intel_encoder *encoder;
6be4a607
JB		 3469 int pipe = intel_crtc->pipe;
3470 int plane = intel_crtc->plane;
5eddb70b 3471 u32 reg, temp;
b52eb4dc 3472
ef9c3aee 3473
f7abfe8b
CW		 3474 if (!intel_crtc->active)
3475 return;
3476
ea9d758d
DV		 3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->disable(encoder);
3479
e6c3a2a6 3480 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3481 drm_vblank_off(dev, pipe);
913d8d11 3482
5c3fe8b0 3483 if (dev_priv->fbc.plane == plane)
973d04f9 3484 intel_disable_fbc(dev);
2c07245f 3485
0d5b8c61 3486 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3487 intel_disable_planes(crtc);
0d5b8c61
VS		 3488 intel_disable_plane(dev_priv, plane, pipe);
3489
d925c59a
DV		 3490 if (intel_crtc->config.has_pch_encoder)
3491 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3492
b24e7179 3493 intel_disable_pipe(dev_priv, pipe);
32f9d658 3494
3f8dce3a 3495 ironlake_pfit_disable(intel_crtc);
2c07245f 3496
bf49ec8c
DV		 3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 if (encoder->post_disable)
3499 encoder->post_disable(encoder);
2c07245f 3500
d925c59a
DV		 3501 if (intel_crtc->config.has_pch_encoder) {
3502 ironlake_fdi_disable(crtc);
913d8d11 3503
d925c59a
DV		 3504 ironlake_disable_pch_transcoder(dev_priv, pipe);
3505 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3506
d925c59a
DV		 3507 if (HAS_PCH_CPT(dev)) {
3508 /* disable TRANS_DP_CTL */
3509 reg = TRANS_DP_CTL(pipe);
3510 temp = I915_READ(reg);
3511 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3512 TRANS_DP_PORT_SEL_MASK);
3513 temp |= TRANS_DP_PORT_SEL_NONE;
3514 I915_WRITE(reg, temp);
3515
3516 /* disable DPLL_SEL */
3517 temp = I915_READ(PCH_DPLL_SEL);
11887397 3518 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3519 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3520 }
e3421a18 3521
d925c59a 3522 /* disable PCH DPLL */
e72f9fbf 3523 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3524
d925c59a
DV		 3525 ironlake_fdi_pll_disable(intel_crtc);
3526 }
6b383a7f 3527
f7abfe8b 3528 intel_crtc->active = false;
46ba614c 3529 intel_update_watermarks(crtc);
d1ebd816
BW		 3530
3531 mutex_lock(&dev->struct_mutex);
6b383a7f 3532 intel_update_fbc(dev);
d1ebd816 3533 mutex_unlock(&dev->struct_mutex);
6be4a607 3534}
1b3c7a47 3535
4f771f10 3536static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3537{
4f771f10
PZ		 3538 struct drm_device *dev = crtc->dev;
3539 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3541 struct intel_encoder *encoder;
3542 int pipe = intel_crtc->pipe;
3543 int plane = intel_crtc->plane;
3b117c8f 3544 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3545
4f771f10
PZ		 3546 if (!intel_crtc->active)
3547 return;
3548
8807e55b
JN		 3549 for_each_encoder_on_crtc(dev, crtc, encoder) {
3550 intel_opregion_notify_encoder(encoder, false);
4f771f10 3551 encoder->disable(encoder);
8807e55b 3552 }
4f771f10
PZ		 3553
3554 intel_crtc_wait_for_pending_flips(crtc);
3555 drm_vblank_off(dev, pipe);
4f771f10 3556
891348b2 3557 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3558 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3559 intel_disable_fbc(dev);
3560
42db64ef
PZ		 3561 hsw_disable_ips(intel_crtc);
3562
0d5b8c61 3563 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3564 intel_disable_planes(crtc);
891348b2
RV		 3565 intel_disable_plane(dev_priv, plane, pipe);
3566
8664281b
PZ		 3567 if (intel_crtc->config.has_pch_encoder)
3568 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3569 intel_disable_pipe(dev_priv, pipe);
3570
ad80a810 3571 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3572
3f8dce3a 3573 ironlake_pfit_disable(intel_crtc);
4f771f10 3574
1f544388 3575 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3576
3577 for_each_encoder_on_crtc(dev, crtc, encoder)
3578 if (encoder->post_disable)
3579 encoder->post_disable(encoder);
3580
88adfff1 3581 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3582 lpt_disable_pch_transcoder(dev_priv);
8664281b 3583 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3584 intel_ddi_fdi_disable(crtc);
83616634 3585 }
4f771f10
PZ		 3586
3587 intel_crtc->active = false;
46ba614c 3588 intel_update_watermarks(crtc);
4f771f10
PZ		 3589
3590 mutex_lock(&dev->struct_mutex);
3591 intel_update_fbc(dev);
3592 mutex_unlock(&dev->struct_mutex);
3593}
3594
ee7b9f93
JB		 3595static void ironlake_crtc_off(struct drm_crtc *crtc)
3596{
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3598 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3599}
3600
6441ab5f
PZ		 3601static void haswell_crtc_off(struct drm_crtc *crtc)
3602{
3603 intel_ddi_put_crtc_pll(crtc);
3604}
3605
02e792fb
DV		 3606static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3607{
02e792fb 3608 if (!enable && intel_crtc->overlay) {
23f09ce3 3609 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3610 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3611
23f09ce3 3612 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3613 dev_priv->mm.interruptible = false;
3614 (void) intel_overlay_switch_off(intel_crtc->overlay);
3615 dev_priv->mm.interruptible = true;
23f09ce3 3616 mutex_unlock(&dev->struct_mutex);
02e792fb 3617 }
02e792fb 3618
5dcdbcb0
CW		 3619 /* Let userspace switch the overlay on again. In most cases userspace
3620 * has to recompute where to put it anyway.
3621 */
02e792fb
DV		 3622}
3623
61bc95c1
EE		 3624/**
3625 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3626 * cursor plane briefly if not already running after enabling the display
3627 * plane.
3628 * This workaround avoids occasional blank screens when self refresh is
3629 * enabled.
3630 */
3631static void
3632g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3633{
3634 u32 cntl = I915_READ(CURCNTR(pipe));
3635
3636 if ((cntl & CURSOR_MODE) == 0) {
3637 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3638
3639 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3640 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3641 intel_wait_for_vblank(dev_priv->dev, pipe);
3642 I915_WRITE(CURCNTR(pipe), cntl);
3643 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3644 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3645 }
3646}
3647
2dd24552
JB		 3648static void i9xx_pfit_enable(struct intel_crtc *crtc)
3649{
3650 struct drm_device *dev = crtc->base.dev;
3651 struct drm_i915_private *dev_priv = dev->dev_private;
3652 struct intel_crtc_config *pipe_config = &crtc->config;
3653
328d8e82 3654 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3655 return;
3656
2dd24552 3657 /*
c0b03411
DV		 3658 * The panel fitter should only be adjusted whilst the pipe is disabled,
3659 * according to register description and PRM.
2dd24552 3660 */
c0b03411
DV		 3661 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3662 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3663
b074cec8
JB		 3664 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3665 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3666
3667 /* Border color in case we don't scale up to the full screen. Black by
3668 * default, change to something else for debugging. */
3669 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3670}
3671
89b667f8
JB		 3672static void valleyview_crtc_enable(struct drm_crtc *crtc)
3673{
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct intel_encoder *encoder;
3678 int pipe = intel_crtc->pipe;
3679 int plane = intel_crtc->plane;
23538ef1 3680 bool is_dsi;
89b667f8
JB		 3681
3682 WARN_ON(!crtc->enabled);
3683
3684 if (intel_crtc->active)
3685 return;
3686
3687 intel_crtc->active = true;
89b667f8 3688
89b667f8
JB		 3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_pll_enable)
3691 encoder->pre_pll_enable(encoder);
3692
23538ef1
JN		 3693 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3694
e9fd1c02
JN		 3695 if (!is_dsi)
3696 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3697
3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 if (encoder->pre_enable)
3700 encoder->pre_enable(encoder);
3701
2dd24552
JB		 3702 i9xx_pfit_enable(intel_crtc);
3703
63cbb074
VS		 3704 intel_crtc_load_lut(crtc);
3705
f37fcc2a 3706 intel_update_watermarks(crtc);
23538ef1 3707 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3708 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3709 intel_enable_planes(crtc);
5c38d48c 3710 intel_crtc_update_cursor(crtc, true);
89b667f8 3711
89b667f8 3712 intel_update_fbc(dev);
5004945f
JN		 3713
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->enable(encoder);
89b667f8
JB		 3716}
3717
0b8765c6 3718static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3719{
3720 struct drm_device *dev = crtc->dev;
79e53945
JB		 3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3723 struct intel_encoder *encoder;
79e53945 3724 int pipe = intel_crtc->pipe;
80824003 3725 int plane = intel_crtc->plane;
79e53945 3726
08a48469
DV		 3727 WARN_ON(!crtc->enabled);
3728
f7abfe8b
CW		 3729 if (intel_crtc->active)
3730 return;
3731
3732 intel_crtc->active = true;
6b383a7f 3733
9d6d9f19
MK		 3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->pre_enable)
3736 encoder->pre_enable(encoder);
3737
f6736a1a
DV		 3738 i9xx_enable_pll(intel_crtc);
3739
2dd24552
JB		 3740 i9xx_pfit_enable(intel_crtc);
3741
63cbb074
VS		 3742 intel_crtc_load_lut(crtc);
3743
f37fcc2a 3744 intel_update_watermarks(crtc);
23538ef1 3745 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3746 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3747 intel_enable_planes(crtc);
22e407d7 3748 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3749 if (IS_G4X(dev))
3750 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3751 intel_crtc_update_cursor(crtc, true);
79e53945 3752
0b8765c6
JB		 3753 /* Give the overlay scaler a chance to enable if it's on this pipe */
3754 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3755
f440eb13 3756 intel_update_fbc(dev);
ef9c3aee 3757
fa5c73b1
DV		 3758 for_each_encoder_on_crtc(dev, crtc, encoder)
3759 encoder->enable(encoder);
0b8765c6 3760}
79e53945 3761
87476d63
DV		 3762static void i9xx_pfit_disable(struct intel_crtc *crtc)
3763{
3764 struct drm_device *dev = crtc->base.dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3766
328d8e82
DV		 3767 if (!crtc->config.gmch_pfit.control)
3768 return;
87476d63 3769
328d8e82 3770 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3771
328d8e82
DV		 3772 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3773 I915_READ(PFIT_CONTROL));
3774 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3775}
3776
0b8765c6
JB		 3777static void i9xx_crtc_disable(struct drm_crtc *crtc)
3778{
3779 struct drm_device *dev = crtc->dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3782 struct intel_encoder *encoder;
0b8765c6
JB		 3783 int pipe = intel_crtc->pipe;
3784 int plane = intel_crtc->plane;
ef9c3aee 3785
f7abfe8b
CW		 3786 if (!intel_crtc->active)
3787 return;
3788
ea9d758d
DV		 3789 for_each_encoder_on_crtc(dev, crtc, encoder)
3790 encoder->disable(encoder);
3791
0b8765c6 3792 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3793 intel_crtc_wait_for_pending_flips(crtc);
3794 drm_vblank_off(dev, pipe);
0b8765c6 3795
5c3fe8b0 3796 if (dev_priv->fbc.plane == plane)
973d04f9 3797 intel_disable_fbc(dev);
79e53945 3798
0d5b8c61
VS		 3799 intel_crtc_dpms_overlay(intel_crtc, false);
3800 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3801 intel_disable_planes(crtc);
b24e7179 3802 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3803
b24e7179 3804 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3805
87476d63 3806 i9xx_pfit_disable(intel_crtc);
24a1f16d 3807
89b667f8
JB		 3808 for_each_encoder_on_crtc(dev, crtc, encoder)
3809 if (encoder->post_disable)
3810 encoder->post_disable(encoder);
3811
e9fd1c02
JN		 3812 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3813 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3814
f7abfe8b 3815 intel_crtc->active = false;
46ba614c 3816 intel_update_watermarks(crtc);
f37fcc2a
VS		 3817
3818 intel_update_fbc(dev);
0b8765c6
JB		 3819}
3820
ee7b9f93
JB		 3821static void i9xx_crtc_off(struct drm_crtc *crtc)
3822{
3823}
3824
976f8a20
DV		 3825static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3826 bool enabled)
2c07245f
ZW		 3827{
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_master_private *master_priv;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
79e53945
JB		 3832
3833 if (!dev->primary->master)
3834 return;
3835
3836 master_priv = dev->primary->master->driver_priv;
3837 if (!master_priv->sarea_priv)
3838 return;
3839
79e53945
JB		 3840 switch (pipe) {
3841 case 0:
3842 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3843 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3844 break;
3845 case 1:
3846 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3847 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3848 break;
3849 default:
9db4a9c7 3850 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3851 break;
3852 }
79e53945
JB		 3853}
3854
976f8a20
DV		 3855/**
3856 * Sets the power management mode of the pipe and plane.
3857 */
3858void intel_crtc_update_dpms(struct drm_crtc *crtc)
3859{
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 struct intel_encoder *intel_encoder;
3863 bool enable = false;
3864
3865 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3866 enable |= intel_encoder->connectors_active;
3867
3868 if (enable)
3869 dev_priv->display.crtc_enable(crtc);
3870 else
3871 dev_priv->display.crtc_disable(crtc);
3872
3873 intel_crtc_update_sarea(crtc, enable);
3874}
3875
cdd59983
CW		 3876static void intel_crtc_disable(struct drm_crtc *crtc)
3877{
cdd59983 3878 struct drm_device *dev = crtc->dev;
976f8a20 3879 struct drm_connector *connector;
ee7b9f93 3880 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3882
976f8a20
DV		 3883 /* crtc should still be enabled when we disable it. */
3884 WARN_ON(!crtc->enabled);
3885
3886 dev_priv->display.crtc_disable(crtc);
c77bf565 3887 intel_crtc->eld_vld = false;
976f8a20 3888 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3889 dev_priv->display.off(crtc);
3890
931872fc 3891 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3892 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3893 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3894
3895 if (crtc->fb) {
3896 mutex_lock(&dev->struct_mutex);
1690e1eb 3897 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3898 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3899 crtc->fb = NULL;
3900 }
3901
3902 /* Update computed state. */
3903 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3904 if (!connector->encoder || !connector->encoder->crtc)
3905 continue;
3906
3907 if (connector->encoder->crtc != crtc)
3908 continue;
3909
3910 connector->dpms = DRM_MODE_DPMS_OFF;
3911 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3912 }
3913}
3914
ea5b213a 3915void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3916{
4ef69c7a 3917 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3918
ea5b213a
CW		 3919 drm_encoder_cleanup(encoder);
3920 kfree(intel_encoder);
7e7d76c3
JB		 3921}
3922
9237329d 3923/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3924 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3925 * state of the entire output pipe. */
9237329d 3926static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3927{
5ab432ef
DV		 3928 if (mode == DRM_MODE_DPMS_ON) {
3929 encoder->connectors_active = true;
3930
b2cabb0e 3931 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3932 } else {
3933 encoder->connectors_active = false;
3934
b2cabb0e 3935 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3936 }
79e53945
JB		 3937}
3938
0a91ca29
DV		 3939/* Cross check the actual hw state with our own modeset state tracking (and it's
3940 * internal consistency). */
b980514c 3941static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3942{
0a91ca29
DV		 3943 if (connector->get_hw_state(connector)) {
3944 struct intel_encoder *encoder = connector->encoder;
3945 struct drm_crtc *crtc;
3946 bool encoder_enabled;
3947 enum pipe pipe;
3948
3949 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3950 connector->base.base.id,
3951 drm_get_connector_name(&connector->base));
3952
3953 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3954 "wrong connector dpms state\n");
3955 WARN(connector->base.encoder != &encoder->base,
3956 "active connector not linked to encoder\n");
3957 WARN(!encoder->connectors_active,
3958 "encoder->connectors_active not set\n");
3959
3960 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3961 WARN(!encoder_enabled, "encoder not enabled\n");
3962 if (WARN_ON(!encoder->base.crtc))
3963 return;
3964
3965 crtc = encoder->base.crtc;
3966
3967 WARN(!crtc->enabled, "crtc not enabled\n");
3968 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3969 WARN(pipe != to_intel_crtc(crtc)->pipe,
3970 "encoder active on the wrong pipe\n");
3971 }
79e53945
JB		 3972}
3973
5ab432ef
DV		 3974/* Even simpler default implementation, if there's really no special case to
3975 * consider. */
3976void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3977{
5ab432ef 3978 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3979
5ab432ef
DV		 3980 /* All the simple cases only support two dpms states. */
3981 if (mode != DRM_MODE_DPMS_ON)
3982 mode = DRM_MODE_DPMS_OFF;
d4270e57 3983
5ab432ef
DV		 3984 if (mode == connector->dpms)
3985 return;
3986
3987 connector->dpms = mode;
3988
3989 /* Only need to change hw state when actually enabled */
3990 if (encoder->base.crtc)
3991 intel_encoder_dpms(encoder, mode);
3992 else
8af6cf88 3993 WARN_ON(encoder->connectors_active != false);
0a91ca29 3994
b980514c 3995 intel_modeset_check_state(connector->dev);
79e53945
JB		 3996}
3997
f0947c37
DV		 3998/* Simple connector->get_hw_state implementation for encoders that support only
3999 * one connector and no cloning and hence the encoder state determines the state
4000 * of the connector. */
4001bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4002{
24929352 4003 enum pipe pipe = 0;
f0947c37 4004 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4005
f0947c37 4006 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4007}
4008
1857e1da
DV		 4009static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4010 struct intel_crtc_config *pipe_config)
4011{
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 struct intel_crtc *pipe_B_crtc =
4014 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4015
4016 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4017 pipe_name(pipe), pipe_config->fdi_lanes);
4018 if (pipe_config->fdi_lanes > 4) {
4019 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4020 pipe_name(pipe), pipe_config->fdi_lanes);
4021 return false;
4022 }
4023
4024 if (IS_HASWELL(dev)) {
4025 if (pipe_config->fdi_lanes > 2) {
4026 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4027 pipe_config->fdi_lanes);
4028 return false;
4029 } else {
4030 return true;
4031 }
4032 }
4033
4034 if (INTEL_INFO(dev)->num_pipes == 2)
4035 return true;
4036
4037 /* Ivybridge 3 pipe is really complicated */
4038 switch (pipe) {
4039 case PIPE_A:
4040 return true;
4041 case PIPE_B:
4042 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4043 pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4045 pipe_name(pipe), pipe_config->fdi_lanes);
4046 return false;
4047 }
4048 return true;
4049 case PIPE_C:
1e833f40 4050 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4051 pipe_B_crtc->config.fdi_lanes <= 2) {
4052 if (pipe_config->fdi_lanes > 2) {
4053 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4054 pipe_name(pipe), pipe_config->fdi_lanes);
4055 return false;
4056 }
4057 } else {
4058 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4059 return false;
4060 }
4061 return true;
4062 default:
4063 BUG();
4064 }
4065}
4066
e29c22c0
DV		 4067#define RETRY 1
4068static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4069 struct intel_crtc_config *pipe_config)
877d48d5 4070{
1857e1da 4071 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4072 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4073 int lane, link_bw, fdi_dotclock;
e29c22c0 4074 bool setup_ok, needs_recompute = false;
877d48d5 4075
e29c22c0 4076retry:
877d48d5
DV		 4077 /* FDI is a binary signal running at ~2.7GHz, encoding
4078 * each output octet as 10 bits. The actual frequency
4079 * is stored as a divider into a 100MHz clock, and the
4080 * mode pixel clock is stored in units of 1KHz.
4081 * Hence the bw of each lane in terms of the mode signal
4082 * is:
4083 */
4084 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4085
ff9a6750 4086 fdi_dotclock = adjusted_mode->clock;
877d48d5 4087
2bd89a07 4088 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4089 pipe_config->pipe_bpp);
4090
4091 pipe_config->fdi_lanes = lane;
4092
2bd89a07 4093 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4094 link_bw, &pipe_config->fdi_m_n);
1857e1da 4095
e29c22c0
DV		 4096 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4097 intel_crtc->pipe, pipe_config);
4098 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4099 pipe_config->pipe_bpp -= 2*3;
4100 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4101 pipe_config->pipe_bpp);
4102 needs_recompute = true;
4103 pipe_config->bw_constrained = true;
4104
4105 goto retry;
4106 }
4107
4108 if (needs_recompute)
4109 return RETRY;
4110
4111 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4112}
4113
42db64ef
PZ		 4114static void hsw_compute_ips_config(struct intel_crtc *crtc,
4115 struct intel_crtc_config *pipe_config)
4116{
3c4ca58c
PZ		 4117 pipe_config->ips_enabled = i915_enable_ips &&
4118 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4119 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4120}
4121
a43f6e0f 4122static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4123 struct intel_crtc_config *pipe_config)
79e53945 4124{
a43f6e0f 4125 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4126 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4127
8693a824
DL		 4128 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4130 */
4131 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4133 return -EINVAL;
44f46b42 4134
bd080ee5 4135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4136 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4137 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4138 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139 * for lvds. */
4140 pipe_config->pipe_bpp = 8*3;
4141 }
4142
f5adf94e 4143 if (HAS_IPS(dev))
a43f6e0f
DV		 4144 hsw_compute_ips_config(crtc, pipe_config);
4145
4146 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4147 * clock survives for now. */
4148 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4149 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4150
877d48d5 4151 if (pipe_config->has_pch_encoder)
a43f6e0f 4152 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4153
e29c22c0 4154 return 0;
79e53945
JB		 4155}
4156
25eb05fc
JB		 4157static int valleyview_get_display_clock_speed(struct drm_device *dev)
4158{
4159 return 400000; /* FIXME */
4160}
4161
e70236a8
JB		 4162static int i945_get_display_clock_speed(struct drm_device *dev)
4163{
4164 return 400000;
4165}
79e53945 4166
e70236a8 4167static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4168{
e70236a8
JB		 4169 return 333000;
4170}
79e53945 4171
e70236a8
JB		 4172static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4173{
4174 return 200000;
4175}
79e53945 4176
257a7ffc
DV		 4177static int pnv_get_display_clock_speed(struct drm_device *dev)
4178{
4179 u16 gcfgc = 0;
4180
4181 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4182
4183 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4184 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4185 return 267000;
4186 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4187 return 333000;
4188 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4189 return 444000;
4190 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4191 return 200000;
4192 default:
4193 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4194 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4195 return 133000;
4196 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4197 return 167000;
4198 }
4199}
4200
e70236a8
JB		 4201static int i915gm_get_display_clock_speed(struct drm_device *dev)
4202{
4203 u16 gcfgc = 0;
79e53945 4204
e70236a8
JB		 4205 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4206
4207 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4208 return 133000;
4209 else {
4210 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4211 case GC_DISPLAY_CLOCK_333_MHZ:
4212 return 333000;
4213 default:
4214 case GC_DISPLAY_CLOCK_190_200_MHZ:
4215 return 190000;
79e53945 4216 }
e70236a8
JB		 4217 }
4218}
4219
4220static int i865_get_display_clock_speed(struct drm_device *dev)
4221{
4222 return 266000;
4223}
4224
4225static int i855_get_display_clock_speed(struct drm_device *dev)
4226{
4227 u16 hpllcc = 0;
4228 /* Assume that the hardware is in the high speed state. This
4229 * should be the default.
4230 */
4231 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4232 case GC_CLOCK_133_200:
4233 case GC_CLOCK_100_200:
4234 return 200000;
4235 case GC_CLOCK_166_250:
4236 return 250000;
4237 case GC_CLOCK_100_133:
79e53945 4238 return 133000;
e70236a8 4239 }
79e53945 4240
e70236a8
JB		 4241 /* Shouldn't happen */
4242 return 0;
4243}
79e53945 4244
e70236a8
JB		 4245static int i830_get_display_clock_speed(struct drm_device *dev)
4246{
4247 return 133000;
79e53945
JB		 4248}
4249
2c07245f 4250static void
a65851af 4251intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4252{
a65851af
VS		 4253 while (*num > DATA_LINK_M_N_MASK ||
4254 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4255 *num >>= 1;
4256 *den >>= 1;
4257 }
4258}
4259
a65851af
VS		 4260static void compute_m_n(unsigned int m, unsigned int n,
4261 uint32_t *ret_m, uint32_t *ret_n)
4262{
4263 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4264 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4265 intel_reduce_m_n_ratio(ret_m, ret_n);
4266}
4267
e69d0bc1
DV		 4268void
4269intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4270 int pixel_clock, int link_clock,
4271 struct intel_link_m_n *m_n)
2c07245f 4272{
e69d0bc1 4273 m_n->tu = 64;
a65851af
VS		 4274
4275 compute_m_n(bits_per_pixel * pixel_clock,
4276 link_clock * nlanes * 8,
4277 &m_n->gmch_m, &m_n->gmch_n);
4278
4279 compute_m_n(pixel_clock, link_clock,
4280 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4281}
4282
a7615030
CW		 4283static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4284{
72bbe58c
KP		 4285 if (i915_panel_use_ssc >= 0)
4286 return i915_panel_use_ssc != 0;
41aa3448 4287 return dev_priv->vbt.lvds_use_ssc
435793df 4288 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4289}
4290
a0c4da24
JB		 4291static int vlv_get_refclk(struct drm_crtc *crtc)
4292{
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int refclk = 27000; /* for DP & HDMI */
4296
4297 return 100000; /* only one validated so far */
4298
4299 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4300 refclk = 96000;
4301 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4302 if (intel_panel_use_ssc(dev_priv))
4303 refclk = 100000;
4304 else
4305 refclk = 96000;
4306 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4307 refclk = 100000;
4308 }
4309
4310 return refclk;
4311}
4312
c65d77d8
JB		 4313static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4314{
4315 struct drm_device *dev = crtc->dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int refclk;
4318
a0c4da24
JB		 4319 if (IS_VALLEYVIEW(dev)) {
4320 refclk = vlv_get_refclk(crtc);
4321 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4322 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4323 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4324 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4325 refclk / 1000);
4326 } else if (!IS_GEN2(dev)) {
4327 refclk = 96000;
4328 } else {
4329 refclk = 48000;
4330 }
4331
4332 return refclk;
4333}
4334
7429e9d4 4335static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4336{
7df00d7a 4337 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4338}
f47709a9 4339
7429e9d4
DV		 4340static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4341{
4342 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4343}
4344
f47709a9 4345static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4346 intel_clock_t *reduced_clock)
4347{
f47709a9 4348 struct drm_device *dev = crtc->base.dev;
a7516a05 4349 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4350 int pipe = crtc->pipe;
a7516a05
JB		 4351 u32 fp, fp2 = 0;
4352
4353 if (IS_PINEVIEW(dev)) {
7429e9d4 4354 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4355 if (reduced_clock)
7429e9d4 4356 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4357 } else {
7429e9d4 4358 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4359 if (reduced_clock)
7429e9d4 4360 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4361 }
4362
4363 I915_WRITE(FP0(pipe), fp);
8bcc2795 4364 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4365
f47709a9
DV		 4366 crtc->lowfreq_avail = false;
4367 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4368 reduced_clock && i915_powersave) {
4369 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4370 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4371 crtc->lowfreq_avail = true;
a7516a05
JB		 4372 } else {
4373 I915_WRITE(FP1(pipe), fp);
8bcc2795 4374 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4375 }
4376}
4377
5e69f97f
CML		 4378static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4379 pipe)
89b667f8
JB		 4380{
4381 u32 reg_val;
4382
4383 /*
4384 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4385 * and set it to a reasonable value instead.
4386 */
5e69f97f 4387 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4388 reg_val &= 0xffffff00;
4389 reg_val |= 0x00000030;
5e69f97f 4390 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4391
5e69f97f 4392 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4393 reg_val &= 0x8cffffff;
4394 reg_val = 0x8c000000;
5e69f97f 4395 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4396
5e69f97f 4397 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4398 reg_val &= 0xffffff00;
5e69f97f 4399 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4400
5e69f97f 4401 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4402 reg_val &= 0x00ffffff;
4403 reg_val |= 0xb0000000;
5e69f97f 4404 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4405}
4406
b551842d
DV		 4407static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4408 struct intel_link_m_n *m_n)
4409{
4410 struct drm_device *dev = crtc->base.dev;
4411 struct drm_i915_private *dev_priv = dev->dev_private;
4412 int pipe = crtc->pipe;
4413
e3b95f1e
DV		 4414 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4415 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4416 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4417 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4418}
4419
4420static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4421 struct intel_link_m_n *m_n)
4422{
4423 struct drm_device *dev = crtc->base.dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 int pipe = crtc->pipe;
4426 enum transcoder transcoder = crtc->config.cpu_transcoder;
4427
4428 if (INTEL_INFO(dev)->gen >= 5) {
4429 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4430 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4431 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4432 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4433 } else {
e3b95f1e
DV		 4434 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4435 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4436 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4437 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4438 }
4439}
4440
03afc4a2
DV		 4441static void intel_dp_set_m_n(struct intel_crtc *crtc)
4442{
4443 if (crtc->config.has_pch_encoder)
4444 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4445 else
4446 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4447}
4448
f47709a9 4449static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4450{
f47709a9 4451 struct drm_device *dev = crtc->base.dev;
a0c4da24 4452 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4453 int pipe = crtc->pipe;
89b667f8 4454 u32 dpll, mdiv;
a0c4da24 4455 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4456 u32 coreclk, reg_val, dpll_md;
a0c4da24 4457
09153000
DV		 4458 mutex_lock(&dev_priv->dpio_lock);
4459
f47709a9
DV		 4460 bestn = crtc->config.dpll.n;
4461 bestm1 = crtc->config.dpll.m1;
4462 bestm2 = crtc->config.dpll.m2;
4463 bestp1 = crtc->config.dpll.p1;
4464 bestp2 = crtc->config.dpll.p2;
a0c4da24 4465
89b667f8
JB		 4466 /* See eDP HDMI DPIO driver vbios notes doc */
4467
4468 /* PLL B needs special handling */
4469 if (pipe)
5e69f97f 4470 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4471
4472 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4473 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4474
4475 /* Disable target IRef on PLL */
5e69f97f 4476 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4477 reg_val &= 0x00ffffff;
5e69f97f 4478 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4479
4480 /* Disable fast lock */
5e69f97f 4481 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4482
4483 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4484 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4485 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4486 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4487 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4488
4489 /*
4490 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4491 * but we don't support that).
4492 * Note: don't use the DAC post divider as it seems unstable.
4493 */
4494 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4495 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4496
a0c4da24 4497 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4498 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4499
89b667f8 4500 /* Set HBR and RBR LPF coefficients */
ff9a6750 4501 if (crtc->config.port_clock == 162000 ||
99750bd4 4502 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4503 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4504 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4505 0x009f0003);
89b667f8 4506 else
5e69f97f 4507 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4508 0x00d0000f);
4509
4510 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4511 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4512 /* Use SSC source */
4513 if (!pipe)
5e69f97f 4514 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4515 0x0df40000);
4516 else
5e69f97f 4517 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4518 0x0df70000);
4519 } else { /* HDMI or VGA */
4520 /* Use bend source */
4521 if (!pipe)
5e69f97f 4522 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4523 0x0df70000);
4524 else
5e69f97f 4525 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4526 0x0df40000);
4527 }
a0c4da24 4528
5e69f97f 4529 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4530 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4531 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4533 coreclk |= 0x01000000;
5e69f97f 4534 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4535
5e69f97f 4536 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4537
89b667f8
JB		 4538 /* Enable DPIO clock input */
4539 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4540 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4541 if (pipe)
4542 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4543
4544 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4545 crtc->config.dpll_hw_state.dpll = dpll;
4546
ef1b460d
DV		 4547 dpll_md = (crtc->config.pixel_multiplier - 1)
4548 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4549 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4550
89b667f8
JB		 4551 if (crtc->config.has_dp_encoder)
4552 intel_dp_set_m_n(crtc);
09153000
DV		 4553
4554 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4555}
4556
f47709a9
DV		 4557static void i9xx_update_pll(struct intel_crtc *crtc,
4558 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4559 int num_connectors)
4560{
f47709a9 4561 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4562 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4563 u32 dpll;
4564 bool is_sdvo;
f47709a9 4565 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4566
f47709a9 4567 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4568
f47709a9
DV		 4569 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4570 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4571
4572 dpll = DPLL_VGA_MODE_DIS;
4573
f47709a9 4574 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4575 dpll |= DPLLB_MODE_LVDS;
4576 else
4577 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4578
ef1b460d 4579 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4580 dpll |= (crtc->config.pixel_multiplier - 1)
4581 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4582 }
198a037f
DV		 4583
4584 if (is_sdvo)
4a33e48d 4585 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4586
f47709a9 4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4588 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4589
4590 /* compute bitmask from p1 value */
4591 if (IS_PINEVIEW(dev))
4592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4593 else {
4594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595 if (IS_G4X(dev) && reduced_clock)
4596 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4597 }
4598 switch (clock->p2) {
4599 case 5:
4600 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4601 break;
4602 case 7:
4603 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4604 break;
4605 case 10:
4606 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4607 break;
4608 case 14:
4609 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4610 break;
4611 }
4612 if (INTEL_INFO(dev)->gen >= 4)
4613 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4614
09ede541 4615 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4616 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4617 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4618 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4619 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4620 else
4621 dpll |= PLL_REF_INPUT_DREFCLK;
4622
4623 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4624 crtc->config.dpll_hw_state.dpll = dpll;
4625
eb1cbe48 4626 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4627 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4628 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4629 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4630 }
66e3d5c0
DV		 4631
4632 if (crtc->config.has_dp_encoder)
4633 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4634}
4635
f47709a9 4636static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4637 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4638 int num_connectors)
4639{
f47709a9 4640 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4641 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4642 u32 dpll;
f47709a9 4643 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4644
f47709a9 4645 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4646
eb1cbe48
DV		 4647 dpll = DPLL_VGA_MODE_DIS;
4648
f47709a9 4649 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4650 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651 } else {
4652 if (clock->p1 == 2)
4653 dpll |= PLL_P1_DIVIDE_BY_TWO;
4654 else
4655 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656 if (clock->p2 == 4)
4657 dpll |= PLL_P2_DIVIDE_BY_4;
4658 }
4659
4a33e48d
DV		 4660 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4661 dpll |= DPLL_DVO_2X_MODE;
4662
f47709a9 4663 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4664 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4665 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4666 else
4667 dpll |= PLL_REF_INPUT_DREFCLK;
4668
4669 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4670 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4671}
4672
8a654f3b 4673static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4674{
4675 struct drm_device *dev = intel_crtc->base.dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4678 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4679 struct drm_display_mode *adjusted_mode =
4680 &intel_crtc->config.adjusted_mode;
4681 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4682 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4683
4684 /* We need to be careful not to changed the adjusted mode, for otherwise
4685 * the hw state checker will get angry at the mismatch. */
4686 crtc_vtotal = adjusted_mode->crtc_vtotal;
4687 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4688
4689 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4690 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4691 crtc_vtotal -= 1;
4692 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4693 vsyncshift = adjusted_mode->crtc_hsync_start
4694 - adjusted_mode->crtc_htotal / 2;
4695 } else {
4696 vsyncshift = 0;
4697 }
4698
4699 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4700 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4701
fe2b8f9d 4702 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4703 (adjusted_mode->crtc_hdisplay - 1) |
4704 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4705 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_hblank_start - 1) |
4707 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4708 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4709 (adjusted_mode->crtc_hsync_start - 1) |
4710 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4711
fe2b8f9d 4712 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4713 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4714 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4715 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4716 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4717 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4718 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4719 (adjusted_mode->crtc_vsync_start - 1) |
4720 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4721
b5e508d4
PZ		 4722 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4723 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4724 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4725 * bits. */
4726 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4727 (pipe == PIPE_B || pipe == PIPE_C))
4728 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4729
b0e77b9c
PZ		 4730 /* pipesrc controls the size that is scaled from, which should
4731 * always be the user's requested size.
4732 */
4733 I915_WRITE(PIPESRC(pipe),
4734 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4735}
4736
1bd1bd80
DV		 4737static void intel_get_pipe_timings(struct intel_crtc *crtc,
4738 struct intel_crtc_config *pipe_config)
4739{
4740 struct drm_device *dev = crtc->base.dev;
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4743 uint32_t tmp;
4744
4745 tmp = I915_READ(HTOTAL(cpu_transcoder));
4746 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4747 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4748 tmp = I915_READ(HBLANK(cpu_transcoder));
4749 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4750 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4751 tmp = I915_READ(HSYNC(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4754
4755 tmp = I915_READ(VTOTAL(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4758 tmp = I915_READ(VBLANK(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(VSYNC(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4766 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4767 pipe_config->adjusted_mode.crtc_vtotal += 1;
4768 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4769 }
4770
4771 tmp = I915_READ(PIPESRC(crtc->pipe));
4772 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4773 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4774}
4775
babea61d
JB		 4776static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4777 struct intel_crtc_config *pipe_config)
4778{
4779 struct drm_crtc *crtc = &intel_crtc->base;
4780
4781 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4782 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4783 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4784 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4785
4786 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4787 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4788 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4789 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4790
4791 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4792
4793 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4794 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4795}
4796
84b046f3
DV		 4797static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4798{
4799 struct drm_device *dev = intel_crtc->base.dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 uint32_t pipeconf;
4802
9f11a9e4 4803 pipeconf = 0;
84b046f3
DV		 4804
4805 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4806 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4807 * core speed.
4808 *
4809 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4810 * pipe == 0 check?
4811 */
4812 if (intel_crtc->config.requested_mode.clock >
4813 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4814 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4815 }
4816
ff9ce46e
DV		 4817 /* only g4x and later have fancy bpc/dither controls */
4818 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4819 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4820 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4821 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4822 PIPECONF_DITHER_TYPE_SP;
84b046f3 4823
ff9ce46e
DV		 4824 switch (intel_crtc->config.pipe_bpp) {
4825 case 18:
4826 pipeconf |= PIPECONF_6BPC;
4827 break;
4828 case 24:
4829 pipeconf |= PIPECONF_8BPC;
4830 break;
4831 case 30:
4832 pipeconf |= PIPECONF_10BPC;
4833 break;
4834 default:
4835 /* Case prevented by intel_choose_pipe_bpp_dither. */
4836 BUG();
84b046f3
DV		 4837 }
4838 }
4839
4840 if (HAS_PIPE_CXSR(dev)) {
4841 if (intel_crtc->lowfreq_avail) {
4842 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4843 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4844 } else {
4845 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4846 }
4847 }
4848
84b046f3
DV		 4849 if (!IS_GEN2(dev) &&
4850 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4851 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4852 else
4853 pipeconf |= PIPECONF_PROGRESSIVE;
4854
9f11a9e4
DV		 4855 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4856 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4857
84b046f3
DV		 4858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859 POSTING_READ(PIPECONF(intel_crtc->pipe));
4860}
4861
f564048e 4862static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4863 int x, int y,
94352cf9 4864 struct drm_framebuffer *fb)
79e53945
JB		 4865{
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4869 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4870 int pipe = intel_crtc->pipe;
80824003 4871 int plane = intel_crtc->plane;
c751ce4f 4872 int refclk, num_connectors = 0;
652c393a 4873 intel_clock_t clock, reduced_clock;
84b046f3 4874 u32 dspcntr;
a16af721 4875 bool ok, has_reduced_clock = false;
e9fd1c02 4876 bool is_lvds = false, is_dsi = false;
5eddb70b 4877 struct intel_encoder *encoder;
d4906093 4878 const intel_limit_t *limit;
5c3b82e2 4879 int ret;
79e53945 4880
6c2b7c12 4881 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4882 switch (encoder->type) {
79e53945
JB		 4883 case INTEL_OUTPUT_LVDS:
4884 is_lvds = true;
4885 break;
e9fd1c02
JN		 4886 case INTEL_OUTPUT_DSI:
4887 is_dsi = true;
4888 break;
79e53945 4889 }
43565a06 4890
c751ce4f 4891 num_connectors++;
79e53945
JB		 4892 }
4893
c65d77d8 4894 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4895
65ce4bf5 4896 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4897 /*
4898 * Returns a set of divisors for the desired target clock with
4899 * the given refclk, or FALSE. The returned values represent
4900 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4901 * 2) / p1 / p2.
4902 */
4903 limit = intel_limit(crtc, refclk);
4904 ok = dev_priv->display.find_dpll(limit, crtc,
4905 intel_crtc->config.port_clock,
4906 refclk, NULL, &clock);
4907 if (!ok && !intel_crtc->config.clock_set) {
4908 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4909 return -EINVAL;
4910 }
79e53945
JB		 4911 }
4912
cda4b7d3 4913 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4914 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4915
e9fd1c02 4916 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4917 /*
4918 * Ensure we match the reduced clock's P to the target clock.
4919 * If the clocks don't match, we can't switch the display clock
4920 * by using the FP0/FP1. In such case we will disable the LVDS
4921 * downclock feature.
4922 */
65ce4bf5 4923 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4924 has_reduced_clock =
4925 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4926 dev_priv->lvds_downclock,
ee9300bb 4927 refclk, &clock,
5eddb70b 4928 &reduced_clock);
7026d4ac 4929 }
f47709a9
DV		 4930 /* Compat-code for transition, will disappear. */
4931 if (!intel_crtc->config.clock_set) {
4932 intel_crtc->config.dpll.n = clock.n;
4933 intel_crtc->config.dpll.m1 = clock.m1;
4934 intel_crtc->config.dpll.m2 = clock.m2;
4935 intel_crtc->config.dpll.p1 = clock.p1;
4936 intel_crtc->config.dpll.p2 = clock.p2;
4937 }
7026d4ac 4938
e9fd1c02 4939 if (IS_GEN2(dev)) {
8a654f3b 4940 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4941 has_reduced_clock ? &reduced_clock : NULL,
4942 num_connectors);
e9fd1c02
JN		 4943 } else if (IS_VALLEYVIEW(dev)) {
4944 if (!is_dsi)
4945 vlv_update_pll(intel_crtc);
4946 } else {
f47709a9 4947 i9xx_update_pll(intel_crtc,
eb1cbe48 4948 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4949 num_connectors);
e9fd1c02 4950 }
79e53945 4951
79e53945
JB		 4952 /* Set up the display plane register */
4953 dspcntr = DISPPLANE_GAMMA_ENABLE;
4954
da6ecc5d
JB		 4955 if (!IS_VALLEYVIEW(dev)) {
4956 if (pipe == 0)
4957 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4958 else
4959 dspcntr |= DISPPLANE_SEL_PIPE_B;
4960 }
79e53945 4961
8a654f3b 4962 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4963
4964 /* pipesrc and dspsize control the size that is scaled from,
4965 * which should always be the user's requested size.
79e53945 4966 */
929c77fb
EA		 4967 I915_WRITE(DSPSIZE(plane),
4968 ((mode->vdisplay - 1) << 16) |
4969 (mode->hdisplay - 1));
4970 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4971
84b046f3
DV		 4972 i9xx_set_pipeconf(intel_crtc);
4973
f564048e
EA		 4974 I915_WRITE(DSPCNTR(plane), dspcntr);
4975 POSTING_READ(DSPCNTR(plane));
4976
94352cf9 4977 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4978
f564048e
EA		 4979 return ret;
4980}
4981
2fa2fe9a
DV		 4982static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4983 struct intel_crtc_config *pipe_config)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 uint32_t tmp;
4988
4989 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4990 if (!(tmp & PFIT_ENABLE))
4991 return;
2fa2fe9a 4992
06922821 4993 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4994 if (INTEL_INFO(dev)->gen < 4) {
4995 if (crtc->pipe != PIPE_B)
4996 return;
2fa2fe9a
DV		 4997 } else {
4998 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4999 return;
5000 }
5001
06922821 5002 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5003 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004 if (INTEL_INFO(dev)->gen < 5)
5005 pipe_config->gmch_pfit.lvds_border_bits =
5006 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007}
5008
0e8ffe1b
DV		 5009static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010 struct intel_crtc_config *pipe_config)
5011{
5012 struct drm_device *dev = crtc->base.dev;
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 uint32_t tmp;
5015
e143a21c 5016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5017 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5018
0e8ffe1b
DV		 5019 tmp = I915_READ(PIPECONF(crtc->pipe));
5020 if (!(tmp & PIPECONF_ENABLE))
5021 return false;
5022
42571aef
VS		 5023 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5024 switch (tmp & PIPECONF_BPC_MASK) {
5025 case PIPECONF_6BPC:
5026 pipe_config->pipe_bpp = 18;
5027 break;
5028 case PIPECONF_8BPC:
5029 pipe_config->pipe_bpp = 24;
5030 break;
5031 case PIPECONF_10BPC:
5032 pipe_config->pipe_bpp = 30;
5033 break;
5034 default:
5035 break;
5036 }
5037 }
5038
1bd1bd80
DV		 5039 intel_get_pipe_timings(crtc, pipe_config);
5040
2fa2fe9a
DV		 5041 i9xx_get_pfit_config(crtc, pipe_config);
5042
6c49f241
DV		 5043 if (INTEL_INFO(dev)->gen >= 4) {
5044 tmp = I915_READ(DPLL_MD(crtc->pipe));
5045 pipe_config->pixel_multiplier =
5046 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5047 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5048 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5049 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5050 tmp = I915_READ(DPLL(crtc->pipe));
5051 pipe_config->pixel_multiplier =
5052 ((tmp & SDVO_MULTIPLIER_MASK)
5053 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5054 } else {
5055 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5056 * port and will be fixed up in the encoder->get_config
5057 * function. */
5058 pipe_config->pixel_multiplier = 1;
5059 }
8bcc2795
DV		 5060 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5061 if (!IS_VALLEYVIEW(dev)) {
5062 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5063 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5064 } else {
5065 /* Mask out read-only status bits. */
5066 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5067 DPLL_PORTC_READY_MASK |
5068 DPLL_PORTB_READY_MASK);
8bcc2795 5069 }
6c49f241 5070
0e8ffe1b
DV		 5071 return true;
5072}
5073
dde86e2d 5074static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5075{
5076 struct drm_i915_private *dev_priv = dev->dev_private;
5077 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5078 struct intel_encoder *encoder;
74cfd7ac 5079 u32 val, final;
13d83a67 5080 bool has_lvds = false;
199e5d79 5081 bool has_cpu_edp = false;
199e5d79 5082 bool has_panel = false;
99eb6a01
KP		 5083 bool has_ck505 = false;
5084 bool can_ssc = false;
13d83a67
JB		 5085
5086 /* We need to take the global config into account */
199e5d79
KP		 5087 list_for_each_entry(encoder, &mode_config->encoder_list,
5088 base.head) {
5089 switch (encoder->type) {
5090 case INTEL_OUTPUT_LVDS:
5091 has_panel = true;
5092 has_lvds = true;
5093 break;
5094 case INTEL_OUTPUT_EDP:
5095 has_panel = true;
2de6905f 5096 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5097 has_cpu_edp = true;
5098 break;
13d83a67
JB		 5099 }
5100 }
5101
99eb6a01 5102 if (HAS_PCH_IBX(dev)) {
41aa3448 5103 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5104 can_ssc = has_ck505;
5105 } else {
5106 has_ck505 = false;
5107 can_ssc = true;
5108 }
5109
2de6905f
ID		 5110 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5111 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5112
5113 /* Ironlake: try to setup display ref clock before DPLL
5114 * enabling. This is only under driver's control after
5115 * PCH B stepping, previous chipset stepping should be
5116 * ignoring this setting.
5117 */
74cfd7ac
CW		 5118 val = I915_READ(PCH_DREF_CONTROL);
5119
5120 /* As we must carefully and slowly disable/enable each source in turn,
5121 * compute the final state we want first and check if we need to
5122 * make any changes at all.
5123 */
5124 final = val;
5125 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5126 if (has_ck505)
5127 final |= DREF_NONSPREAD_CK505_ENABLE;
5128 else
5129 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5130
5131 final &= ~DREF_SSC_SOURCE_MASK;
5132 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133 final &= ~DREF_SSC1_ENABLE;
5134
5135 if (has_panel) {
5136 final |= DREF_SSC_SOURCE_ENABLE;
5137
5138 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5139 final |= DREF_SSC1_ENABLE;
5140
5141 if (has_cpu_edp) {
5142 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5143 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5144 else
5145 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5146 } else
5147 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5148 } else {
5149 final |= DREF_SSC_SOURCE_DISABLE;
5150 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5151 }
5152
5153 if (final == val)
5154 return;
5155
13d83a67 5156 /* Always enable nonspread source */
74cfd7ac 5157 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5158
99eb6a01 5159 if (has_ck505)
74cfd7ac 5160 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5161 else
74cfd7ac 5162 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5163
199e5d79 5164 if (has_panel) {
74cfd7ac
CW		 5165 val &= ~DREF_SSC_SOURCE_MASK;
5166 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5167
199e5d79 5168 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5169 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5170 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5171 val |= DREF_SSC1_ENABLE;
e77166b5 5172 } else
74cfd7ac 5173 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5174
5175 /* Get SSC going before enabling the outputs */
74cfd7ac 5176 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5177 POSTING_READ(PCH_DREF_CONTROL);
5178 udelay(200);
5179
74cfd7ac 5180 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5181
5182 /* Enable CPU source on CPU attached eDP */
199e5d79 5183 if (has_cpu_edp) {
99eb6a01 5184 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5185 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5186 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5187 }
13d83a67 5188 else
74cfd7ac 5189 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5190 } else
74cfd7ac 5191 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5192
74cfd7ac 5193 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5194 POSTING_READ(PCH_DREF_CONTROL);
5195 udelay(200);
5196 } else {
5197 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5198
74cfd7ac 5199 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5200
5201 /* Turn off CPU output */
74cfd7ac 5202 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5203
74cfd7ac 5204 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5205 POSTING_READ(PCH_DREF_CONTROL);
5206 udelay(200);
5207
5208 /* Turn off the SSC source */
74cfd7ac
CW		 5209 val &= ~DREF_SSC_SOURCE_MASK;
5210 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5211
5212 /* Turn off SSC1 */
74cfd7ac 5213 val &= ~DREF_SSC1_ENABLE;
199e5d79 5214
74cfd7ac 5215 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5216 POSTING_READ(PCH_DREF_CONTROL);
5217 udelay(200);
5218 }
74cfd7ac
CW		 5219
5220 BUG_ON(val != final);
13d83a67
JB		 5221}
5222
f31f2d55 5223static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5224{
f31f2d55 5225 uint32_t tmp;
dde86e2d 5226
0ff066a9
PZ		 5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5230
0ff066a9
PZ		 5231 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5233 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5234
0ff066a9
PZ		 5235 tmp = I915_READ(SOUTH_CHICKEN2);
5236 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5237 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5238
0ff066a9
PZ		 5239 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5240 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5241 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5242}
5243
5244/* WaMPhyProgramming:hsw */
5245static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5246{
5247 uint32_t tmp;
dde86e2d
PZ		 5248
5249 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5250 tmp &= ~(0xFF << 24);
5251 tmp |= (0x12 << 24);
5252 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5253
dde86e2d
PZ		 5254 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5255 tmp |= (1 << 11);
5256 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5259 tmp |= (1 << 11);
5260 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5261
dde86e2d
PZ		 5262 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5263 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5264 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5265
5266 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5267 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5268 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5269
0ff066a9
PZ		 5270 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5271 tmp &= ~(7 << 13);
5272 tmp |= (5 << 13);
5273 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5274
0ff066a9
PZ		 5275 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5276 tmp &= ~(7 << 13);
5277 tmp |= (5 << 13);
5278 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5279
5280 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5281 tmp &= ~0xFF;
5282 tmp |= 0x1C;
5283 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5284
5285 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5286 tmp &= ~0xFF;
5287 tmp |= 0x1C;
5288 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5289
5290 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5291 tmp &= ~(0xFF << 16);
5292 tmp |= (0x1C << 16);
5293 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5294
5295 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5296 tmp &= ~(0xFF << 16);
5297 tmp |= (0x1C << 16);
5298 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5299
0ff066a9
PZ		 5300 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5301 tmp |= (1 << 27);
5302 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5303
0ff066a9
PZ		 5304 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5305 tmp |= (1 << 27);
5306 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5307
0ff066a9
PZ		 5308 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5309 tmp &= ~(0xF << 28);
5310 tmp |= (4 << 28);
5311 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5312
0ff066a9
PZ		 5313 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5314 tmp &= ~(0xF << 28);
5315 tmp |= (4 << 28);
5316 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5317}
5318
2fa86a1f
PZ		 5319/* Implements 3 different sequences from BSpec chapter "Display iCLK
5320 * Programming" based on the parameters passed:
5321 * - Sequence to enable CLKOUT_DP
5322 * - Sequence to enable CLKOUT_DP without spread
5323 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5324 */
5325static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5326 bool with_fdi)
f31f2d55
PZ		 5327{
5328 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5329 uint32_t reg, tmp;
5330
5331 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5332 with_spread = true;
5333 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5334 with_fdi, "LP PCH doesn't have FDI\n"))
5335 with_fdi = false;
f31f2d55
PZ		 5336
5337 mutex_lock(&dev_priv->dpio_lock);
5338
5339 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5340 tmp &= ~SBI_SSCCTL_DISABLE;
5341 tmp |= SBI_SSCCTL_PATHALT;
5342 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5343
5344 udelay(24);
5345
2fa86a1f
PZ		 5346 if (with_spread) {
5347 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5348 tmp &= ~SBI_SSCCTL_PATHALT;
5349 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5350
2fa86a1f
PZ		 5351 if (with_fdi) {
5352 lpt_reset_fdi_mphy(dev_priv);
5353 lpt_program_fdi_mphy(dev_priv);
5354 }
5355 }
dde86e2d 5356
2fa86a1f
PZ		 5357 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5358 SBI_GEN0 : SBI_DBUFF0;
5359 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5360 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5361 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5362
5363 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5364}
5365
47701c3b
PZ		 5366/* Sequence to disable CLKOUT_DP */
5367static void lpt_disable_clkout_dp(struct drm_device *dev)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t reg, tmp;
5371
5372 mutex_lock(&dev_priv->dpio_lock);
5373
5374 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5375 SBI_GEN0 : SBI_DBUFF0;
5376 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5377 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5378 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5379
5380 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5381 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5382 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5383 tmp |= SBI_SSCCTL_PATHALT;
5384 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5385 udelay(32);
5386 }
5387 tmp |= SBI_SSCCTL_DISABLE;
5388 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5389 }
5390
5391 mutex_unlock(&dev_priv->dpio_lock);
5392}
5393
bf8fa3d3
PZ		 5394static void lpt_init_pch_refclk(struct drm_device *dev)
5395{
5396 struct drm_mode_config *mode_config = &dev->mode_config;
5397 struct intel_encoder *encoder;
5398 bool has_vga = false;
5399
5400 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5401 switch (encoder->type) {
5402 case INTEL_OUTPUT_ANALOG:
5403 has_vga = true;
5404 break;
5405 }
5406 }
5407
47701c3b
PZ		 5408 if (has_vga)
5409 lpt_enable_clkout_dp(dev, true, true);
5410 else
5411 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5412}
5413
dde86e2d
PZ		 5414/*
5415 * Initialize reference clocks when the driver loads
5416 */
5417void intel_init_pch_refclk(struct drm_device *dev)
5418{
5419 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5420 ironlake_init_pch_refclk(dev);
5421 else if (HAS_PCH_LPT(dev))
5422 lpt_init_pch_refclk(dev);
5423}
5424
d9d444cb
JB		 5425static int ironlake_get_refclk(struct drm_crtc *crtc)
5426{
5427 struct drm_device *dev = crtc->dev;
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct intel_encoder *encoder;
d9d444cb
JB		 5430 int num_connectors = 0;
5431 bool is_lvds = false;
5432
6c2b7c12 5433 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5434 switch (encoder->type) {
5435 case INTEL_OUTPUT_LVDS:
5436 is_lvds = true;
5437 break;
d9d444cb
JB		 5438 }
5439 num_connectors++;
5440 }
5441
5442 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5443 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5444 dev_priv->vbt.lvds_ssc_freq);
5445 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5446 }
5447
5448 return 120000;
5449}
5450
6ff93609 5451static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5452{
c8203565 5453 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5455 int pipe = intel_crtc->pipe;
c8203565
PZ		 5456 uint32_t val;
5457
78114071 5458 val = 0;
c8203565 5459
965e0c48 5460 switch (intel_crtc->config.pipe_bpp) {
c8203565 5461 case 18:
dfd07d72 5462 val |= PIPECONF_6BPC;
c8203565
PZ		 5463 break;
5464 case 24:
dfd07d72 5465 val |= PIPECONF_8BPC;
c8203565
PZ		 5466 break;
5467 case 30:
dfd07d72 5468 val |= PIPECONF_10BPC;
c8203565
PZ		 5469 break;
5470 case 36:
dfd07d72 5471 val |= PIPECONF_12BPC;
c8203565
PZ		 5472 break;
5473 default:
cc769b62
PZ		 5474 /* Case prevented by intel_choose_pipe_bpp_dither. */
5475 BUG();
c8203565
PZ		 5476 }
5477
d8b32247 5478 if (intel_crtc->config.dither)
c8203565
PZ		 5479 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5480
6ff93609 5481 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5482 val |= PIPECONF_INTERLACED_ILK;
5483 else
5484 val |= PIPECONF_PROGRESSIVE;
5485
50f3b016 5486 if (intel_crtc->config.limited_color_range)
3685a8f3 5487 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5488
c8203565
PZ		 5489 I915_WRITE(PIPECONF(pipe), val);
5490 POSTING_READ(PIPECONF(pipe));
5491}
5492
86d3efce
VS		 5493/*
5494 * Set up the pipe CSC unit.
5495 *
5496 * Currently only full range RGB to limited range RGB conversion
5497 * is supported, but eventually this should handle various
5498 * RGB<->YCbCr scenarios as well.
5499 */
50f3b016 5500static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5501{
5502 struct drm_device *dev = crtc->dev;
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5505 int pipe = intel_crtc->pipe;
5506 uint16_t coeff = 0x7800; /* 1.0 */
5507
5508 /*
5509 * TODO: Check what kind of values actually come out of the pipe
5510 * with these coeff/postoff values and adjust to get the best
5511 * accuracy. Perhaps we even need to take the bpc value into
5512 * consideration.
5513 */
5514
50f3b016 5515 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5516 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5517
5518 /*
5519 * GY/GU and RY/RU should be the other way around according
5520 * to BSpec, but reality doesn't agree. Just set them up in
5521 * a way that results in the correct picture.
5522 */
5523 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5524 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5525
5526 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5527 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5528
5529 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5530 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5531
5532 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5533 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5534 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5535
5536 if (INTEL_INFO(dev)->gen > 6) {
5537 uint16_t postoff = 0;
5538
50f3b016 5539 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5540 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5541
5542 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5543 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5544 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5545
5546 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5547 } else {
5548 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5549
50f3b016 5550 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5551 mode |= CSC_BLACK_SCREEN_OFFSET;
5552
5553 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5554 }
5555}
5556
6ff93609 5557static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5558{
5559 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5561 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5562 uint32_t val;
5563
3eff4faa 5564 val = 0;
ee2b0b38 5565
d8b32247 5566 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5567 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5568
6ff93609 5569 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5570 val |= PIPECONF_INTERLACED_ILK;
5571 else
5572 val |= PIPECONF_PROGRESSIVE;
5573
702e7a56
PZ		 5574 I915_WRITE(PIPECONF(cpu_transcoder), val);
5575 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5576
5577 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5578 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5579}
5580
6591c6e4 5581static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5582 intel_clock_t *clock,
5583 bool *has_reduced_clock,
5584 intel_clock_t *reduced_clock)
5585{
5586 struct drm_device *dev = crtc->dev;
5587 struct drm_i915_private *dev_priv = dev->dev_private;
5588 struct intel_encoder *intel_encoder;
5589 int refclk;
d4906093 5590 const intel_limit_t *limit;
a16af721 5591 bool ret, is_lvds = false;
79e53945 5592
6591c6e4
PZ		 5593 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5594 switch (intel_encoder->type) {
79e53945
JB		 5595 case INTEL_OUTPUT_LVDS:
5596 is_lvds = true;
5597 break;
79e53945
JB		 5598 }
5599 }
5600
d9d444cb 5601 refclk = ironlake_get_refclk(crtc);
79e53945 5602
d4906093
ML		 5603 /*
5604 * Returns a set of divisors for the desired target clock with the given
5605 * refclk, or FALSE. The returned values represent the clock equation:
5606 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5607 */
1b894b59 5608 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5609 ret = dev_priv->display.find_dpll(limit, crtc,
5610 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5611 refclk, NULL, clock);
6591c6e4
PZ		 5612 if (!ret)
5613 return false;
cda4b7d3 5614
ddc9003c 5615 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5616 /*
5617 * Ensure we match the reduced clock's P to the target clock.
5618 * If the clocks don't match, we can't switch the display clock
5619 * by using the FP0/FP1. In such case we will disable the LVDS
5620 * downclock feature.
5621 */
ee9300bb
DV		 5622 *has_reduced_clock =
5623 dev_priv->display.find_dpll(limit, crtc,
5624 dev_priv->lvds_downclock,
5625 refclk, clock,
5626 reduced_clock);
652c393a 5627 }
61e9653f 5628
6591c6e4
PZ		 5629 return true;
5630}
5631
01a415fd
DV		 5632static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5633{
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 uint32_t temp;
5636
5637 temp = I915_READ(SOUTH_CHICKEN1);
5638 if (temp & FDI_BC_BIFURCATION_SELECT)
5639 return;
5640
5641 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5642 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5643
5644 temp |= FDI_BC_BIFURCATION_SELECT;
5645 DRM_DEBUG_KMS("enabling fdi C rx\n");
5646 I915_WRITE(SOUTH_CHICKEN1, temp);
5647 POSTING_READ(SOUTH_CHICKEN1);
5648}
5649
ebfd86fd 5650static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5651{
5652 struct drm_device *dev = intel_crtc->base.dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5654
5655 switch (intel_crtc->pipe) {
5656 case PIPE_A:
ebfd86fd 5657 break;
01a415fd 5658 case PIPE_B:
ebfd86fd 5659 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5660 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5661 else
5662 cpt_enable_fdi_bc_bifurcation(dev);
5663
ebfd86fd 5664 break;
01a415fd 5665 case PIPE_C:
01a415fd
DV		 5666 cpt_enable_fdi_bc_bifurcation(dev);
5667
ebfd86fd 5668 break;
01a415fd
DV		 5669 default:
5670 BUG();
5671 }
5672}
5673
d4b1931c
PZ		 5674int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5675{
5676 /*
5677 * Account for spread spectrum to avoid
5678 * oversubscribing the link. Max center spread
5679 * is 2.5%; use 5% for safety's sake.
5680 */
5681 u32 bps = target_clock * bpp * 21 / 20;
5682 return bps / (link_bw * 8) + 1;
5683}
5684
7429e9d4 5685static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5686{
7429e9d4 5687 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5688}
5689
de13a2e3 5690static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5691 u32 *fp,
9a7c7890 5692 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5693{
de13a2e3 5694 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5695 struct drm_device *dev = crtc->dev;
5696 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5697 struct intel_encoder *intel_encoder;
5698 uint32_t dpll;
6cc5f341 5699 int factor, num_connectors = 0;
09ede541 5700 bool is_lvds = false, is_sdvo = false;
79e53945 5701
de13a2e3
PZ		 5702 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5703 switch (intel_encoder->type) {
79e53945
JB		 5704 case INTEL_OUTPUT_LVDS:
5705 is_lvds = true;
5706 break;
5707 case INTEL_OUTPUT_SDVO:
7d57382e 5708 case INTEL_OUTPUT_HDMI:
79e53945 5709 is_sdvo = true;
79e53945 5710 break;
79e53945 5711 }
43565a06 5712
c751ce4f 5713 num_connectors++;
79e53945 5714 }
79e53945 5715
c1858123 5716 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5717 factor = 21;
5718 if (is_lvds) {
5719 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5720 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5721 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5722 factor = 25;
09ede541 5723 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5724 factor = 20;
c1858123 5725
7429e9d4 5726 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5727 *fp |= FP_CB_TUNE;
2c07245f 5728
9a7c7890
DV		 5729 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5730 *fp2 |= FP_CB_TUNE;
5731
5eddb70b 5732 dpll = 0;
2c07245f 5733
a07d6787
EA		 5734 if (is_lvds)
5735 dpll |= DPLLB_MODE_LVDS;
5736 else
5737 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5738
ef1b460d
DV		 5739 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5740 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5741
5742 if (is_sdvo)
4a33e48d 5743 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5744 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5745 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5746
a07d6787 5747 /* compute bitmask from p1 value */
7429e9d4 5748 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5749 /* also FPA1 */
7429e9d4 5750 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5751
7429e9d4 5752 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5753 case 5:
5754 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5755 break;
5756 case 7:
5757 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5758 break;
5759 case 10:
5760 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5761 break;
5762 case 14:
5763 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5764 break;
79e53945
JB		 5765 }
5766
b4c09f3b 5767 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5768 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5769 else
5770 dpll |= PLL_REF_INPUT_DREFCLK;
5771
959e16d6 5772 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5773}
5774
5775static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5776 int x, int y,
5777 struct drm_framebuffer *fb)
5778{
5779 struct drm_device *dev = crtc->dev;
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5782 int pipe = intel_crtc->pipe;
5783 int plane = intel_crtc->plane;
5784 int num_connectors = 0;
5785 intel_clock_t clock, reduced_clock;
cbbab5bd 5786 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5787 bool ok, has_reduced_clock = false;
8b47047b 5788 bool is_lvds = false;
de13a2e3 5789 struct intel_encoder *encoder;
e2b78267 5790 struct intel_shared_dpll *pll;
de13a2e3 5791 int ret;
de13a2e3
PZ		 5792
5793 for_each_encoder_on_crtc(dev, crtc, encoder) {
5794 switch (encoder->type) {
5795 case INTEL_OUTPUT_LVDS:
5796 is_lvds = true;
5797 break;
de13a2e3
PZ		 5798 }
5799
5800 num_connectors++;
a07d6787 5801 }
79e53945 5802
5dc5298b
PZ		 5803 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5804 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5805
ff9a6750 5806 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5807 &has_reduced_clock, &reduced_clock);
ee9300bb 5808 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5809 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5810 return -EINVAL;
79e53945 5811 }
f47709a9
DV		 5812 /* Compat-code for transition, will disappear. */
5813 if (!intel_crtc->config.clock_set) {
5814 intel_crtc->config.dpll.n = clock.n;
5815 intel_crtc->config.dpll.m1 = clock.m1;
5816 intel_crtc->config.dpll.m2 = clock.m2;
5817 intel_crtc->config.dpll.p1 = clock.p1;
5818 intel_crtc->config.dpll.p2 = clock.p2;
5819 }
79e53945 5820
de13a2e3
PZ		 5821 /* Ensure that the cursor is valid for the new mode before changing... */
5822 intel_crtc_update_cursor(crtc, true);
5823
5dc5298b 5824 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5825 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5826 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5827 if (has_reduced_clock)
7429e9d4 5828 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5829
7429e9d4 5830 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5831 &fp, &reduced_clock,
5832 has_reduced_clock ? &fp2 : NULL);
5833
959e16d6 5834 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5835 intel_crtc->config.dpll_hw_state.fp0 = fp;
5836 if (has_reduced_clock)
5837 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5838 else
5839 intel_crtc->config.dpll_hw_state.fp1 = fp;
5840
b89a1d39 5841 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5842 if (pll == NULL) {
84f44ce7
VS		 5843 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5844 pipe_name(pipe));
4b645f14
JB		 5845 return -EINVAL;
5846 }
ee7b9f93 5847 } else
e72f9fbf 5848 intel_put_shared_dpll(intel_crtc);
79e53945 5849
03afc4a2
DV		 5850 if (intel_crtc->config.has_dp_encoder)
5851 intel_dp_set_m_n(intel_crtc);
79e53945 5852
bcd644e0
DV		 5853 if (is_lvds && has_reduced_clock && i915_powersave)
5854 intel_crtc->lowfreq_avail = true;
5855 else
5856 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5857
5858 if (intel_crtc->config.has_pch_encoder) {
5859 pll = intel_crtc_to_shared_dpll(intel_crtc);
5860
652c393a
JB		 5861 }
5862
8a654f3b 5863 intel_set_pipe_timings(intel_crtc);
5eddb70b 5864
ca3a0ff8 5865 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5866 intel_cpu_transcoder_set_m_n(intel_crtc,
5867 &intel_crtc->config.fdi_m_n);
5868 }
2c07245f 5869
ebfd86fd
DV		 5870 if (IS_IVYBRIDGE(dev))
5871 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5872
6ff93609 5873 ironlake_set_pipeconf(crtc);
79e53945 5874
a1f9e77e
PZ		 5875 /* Set up the display plane register */
5876 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5877 POSTING_READ(DSPCNTR(plane));
79e53945 5878
94352cf9 5879 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5880
1857e1da 5881 return ret;
79e53945
JB		 5882}
5883
eb14cb74
VS		 5884static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5885 struct intel_link_m_n *m_n)
5886{
5887 struct drm_device *dev = crtc->base.dev;
5888 struct drm_i915_private *dev_priv = dev->dev_private;
5889 enum pipe pipe = crtc->pipe;
5890
5891 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5892 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5893 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5894 & ~TU_SIZE_MASK;
5895 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5896 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5897 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5898}
5899
5900static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5901 enum transcoder transcoder,
5902 struct intel_link_m_n *m_n)
72419203
DV		 5903{
5904 struct drm_device *dev = crtc->base.dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5906 enum pipe pipe = crtc->pipe;
5907
5908 if (INTEL_INFO(dev)->gen >= 5) {
5909 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5910 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5911 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5912 & ~TU_SIZE_MASK;
5913 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5914 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5915 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5916 } else {
5917 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5918 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5919 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5920 & ~TU_SIZE_MASK;
5921 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5922 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5924 }
5925}
5926
5927void intel_dp_get_m_n(struct intel_crtc *crtc,
5928 struct intel_crtc_config *pipe_config)
5929{
5930 if (crtc->config.has_pch_encoder)
5931 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5932 else
5933 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5934 &pipe_config->dp_m_n);
5935}
72419203 5936
eb14cb74
VS		 5937static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5938 struct intel_crtc_config *pipe_config)
5939{
5940 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5941 &pipe_config->fdi_m_n);
72419203
DV		 5942}
5943
2fa2fe9a
DV		 5944static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5945 struct intel_crtc_config *pipe_config)
5946{
5947 struct drm_device *dev = crtc->base.dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 uint32_t tmp;
5950
5951 tmp = I915_READ(PF_CTL(crtc->pipe));
5952
5953 if (tmp & PF_ENABLE) {
5954 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5955 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5956
5957 /* We currently do not free assignements of panel fitters on
5958 * ivb/hsw (since we don't use the higher upscaling modes which
5959 * differentiates them) so just WARN about this case for now. */
5960 if (IS_GEN7(dev)) {
5961 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5962 PF_PIPE_SEL_IVB(crtc->pipe));
5963 }
2fa2fe9a 5964 }
79e53945
JB		 5965}
5966
0e8ffe1b
DV		 5967static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5968 struct intel_crtc_config *pipe_config)
5969{
5970 struct drm_device *dev = crtc->base.dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 uint32_t tmp;
5973
e143a21c 5974 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5975 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5976
0e8ffe1b
DV		 5977 tmp = I915_READ(PIPECONF(crtc->pipe));
5978 if (!(tmp & PIPECONF_ENABLE))
5979 return false;
5980
42571aef
VS		 5981 switch (tmp & PIPECONF_BPC_MASK) {
5982 case PIPECONF_6BPC:
5983 pipe_config->pipe_bpp = 18;
5984 break;
5985 case PIPECONF_8BPC:
5986 pipe_config->pipe_bpp = 24;
5987 break;
5988 case PIPECONF_10BPC:
5989 pipe_config->pipe_bpp = 30;
5990 break;
5991 case PIPECONF_12BPC:
5992 pipe_config->pipe_bpp = 36;
5993 break;
5994 default:
5995 break;
5996 }
5997
ab9412ba 5998 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5999 struct intel_shared_dpll *pll;
6000
88adfff1
DV		 6001 pipe_config->has_pch_encoder = true;
6002
627eb5a3
DV		 6003 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6004 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6005 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6006
6007 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6008
c0d43d62 6009 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6010 pipe_config->shared_dpll =
6011 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6012 } else {
6013 tmp = I915_READ(PCH_DPLL_SEL);
6014 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6015 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6016 else
6017 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6018 }
66e985c0
DV		 6019
6020 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6021
6022 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6023 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6024
6025 tmp = pipe_config->dpll_hw_state.dpll;
6026 pipe_config->pixel_multiplier =
6027 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6028 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 6029 } else {
6030 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6031 }
6032
1bd1bd80
DV		 6033 intel_get_pipe_timings(crtc, pipe_config);
6034
2fa2fe9a
DV		 6035 ironlake_get_pfit_config(crtc, pipe_config);
6036
0e8ffe1b
DV		 6037 return true;
6038}
6039
be256dc7
PZ		 6040static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6041{
6042 struct drm_device *dev = dev_priv->dev;
6043 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6044 struct intel_crtc *crtc;
6045 unsigned long irqflags;
bd633a7c 6046 uint32_t val;
be256dc7
PZ		 6047
6048 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6049 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6050 pipe_name(crtc->pipe));
6051
6052 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6053 WARN(plls->spll_refcount, "SPLL enabled\n");
6054 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6055 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6056 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6057 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6058 "CPU PWM1 enabled\n");
6059 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6060 "CPU PWM2 enabled\n");
6061 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6062 "PCH PWM1 enabled\n");
6063 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6064 "Utility pin enabled\n");
6065 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6066
6067 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6068 val = I915_READ(DEIMR);
6069 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6070 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6071 val = I915_READ(SDEIMR);
bd633a7c 6072 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6073 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6074 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6075}
6076
6077/*
6078 * This function implements pieces of two sequences from BSpec:
6079 * - Sequence for display software to disable LCPLL
6080 * - Sequence for display software to allow package C8+
6081 * The steps implemented here are just the steps that actually touch the LCPLL
6082 * register. Callers should take care of disabling all the display engine
6083 * functions, doing the mode unset, fixing interrupts, etc.
6084 */
6085void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6086 bool switch_to_fclk, bool allow_power_down)
6087{
6088 uint32_t val;
6089
6090 assert_can_disable_lcpll(dev_priv);
6091
6092 val = I915_READ(LCPLL_CTL);
6093
6094 if (switch_to_fclk) {
6095 val |= LCPLL_CD_SOURCE_FCLK;
6096 I915_WRITE(LCPLL_CTL, val);
6097
6098 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6099 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6100 DRM_ERROR("Switching to FCLK failed\n");
6101
6102 val = I915_READ(LCPLL_CTL);
6103 }
6104
6105 val |= LCPLL_PLL_DISABLE;
6106 I915_WRITE(LCPLL_CTL, val);
6107 POSTING_READ(LCPLL_CTL);
6108
6109 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6110 DRM_ERROR("LCPLL still locked\n");
6111
6112 val = I915_READ(D_COMP);
6113 val |= D_COMP_COMP_DISABLE;
6114 I915_WRITE(D_COMP, val);
6115 POSTING_READ(D_COMP);
6116 ndelay(100);
6117
6118 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6119 DRM_ERROR("D_COMP RCOMP still in progress\n");
6120
6121 if (allow_power_down) {
6122 val = I915_READ(LCPLL_CTL);
6123 val |= LCPLL_POWER_DOWN_ALLOW;
6124 I915_WRITE(LCPLL_CTL, val);
6125 POSTING_READ(LCPLL_CTL);
6126 }
6127}
6128
6129/*
6130 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6131 * source.
6132 */
6133void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6134{
6135 uint32_t val;
6136
6137 val = I915_READ(LCPLL_CTL);
6138
6139 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6140 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6141 return;
6142
215733fa
PZ		 6143 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6144 * we'll hang the machine! */
6145 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6146
be256dc7
PZ		 6147 if (val & LCPLL_POWER_DOWN_ALLOW) {
6148 val &= ~LCPLL_POWER_DOWN_ALLOW;
6149 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6150 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6151 }
6152
6153 val = I915_READ(D_COMP);
6154 val |= D_COMP_COMP_FORCE;
6155 val &= ~D_COMP_COMP_DISABLE;
6156 I915_WRITE(D_COMP, val);
35d8f2eb 6157 POSTING_READ(D_COMP);
be256dc7
PZ		 6158
6159 val = I915_READ(LCPLL_CTL);
6160 val &= ~LCPLL_PLL_DISABLE;
6161 I915_WRITE(LCPLL_CTL, val);
6162
6163 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6164 DRM_ERROR("LCPLL not locked yet\n");
6165
6166 if (val & LCPLL_CD_SOURCE_FCLK) {
6167 val = I915_READ(LCPLL_CTL);
6168 val &= ~LCPLL_CD_SOURCE_FCLK;
6169 I915_WRITE(LCPLL_CTL, val);
6170
6171 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6172 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6173 DRM_ERROR("Switching back to LCPLL failed\n");
6174 }
215733fa
PZ		 6175
6176 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6177}
6178
c67a470b
PZ		 6179void hsw_enable_pc8_work(struct work_struct *__work)
6180{
6181 struct drm_i915_private *dev_priv =
6182 container_of(to_delayed_work(__work), struct drm_i915_private,
6183 pc8.enable_work);
6184 struct drm_device *dev = dev_priv->dev;
6185 uint32_t val;
6186
6187 if (dev_priv->pc8.enabled)
6188 return;
6189
6190 DRM_DEBUG_KMS("Enabling package C8+\n");
6191
6192 dev_priv->pc8.enabled = true;
6193
6194 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6195 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6196 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6197 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6198 }
6199
6200 lpt_disable_clkout_dp(dev);
6201 hsw_pc8_disable_interrupts(dev);
6202 hsw_disable_lcpll(dev_priv, true, true);
6203}
6204
6205static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6206{
6207 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6208 WARN(dev_priv->pc8.disable_count < 1,
6209 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6210
6211 dev_priv->pc8.disable_count--;
6212 if (dev_priv->pc8.disable_count != 0)
6213 return;
6214
6215 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6216 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6217}
6218
6219static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6220{
6221 struct drm_device *dev = dev_priv->dev;
6222 uint32_t val;
6223
6224 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6225 WARN(dev_priv->pc8.disable_count < 0,
6226 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6227
6228 dev_priv->pc8.disable_count++;
6229 if (dev_priv->pc8.disable_count != 1)
6230 return;
6231
6232 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6233 if (!dev_priv->pc8.enabled)
6234 return;
6235
6236 DRM_DEBUG_KMS("Disabling package C8+\n");
6237
6238 hsw_restore_lcpll(dev_priv);
6239 hsw_pc8_restore_interrupts(dev);
6240 lpt_init_pch_refclk(dev);
6241
6242 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6243 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6244 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6245 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6246 }
6247
6248 intel_prepare_ddi(dev);
6249 i915_gem_init_swizzling(dev);
6250 mutex_lock(&dev_priv->rps.hw_lock);
6251 gen6_update_ring_freq(dev);
6252 mutex_unlock(&dev_priv->rps.hw_lock);
6253 dev_priv->pc8.enabled = false;
6254}
6255
6256void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6257{
6258 mutex_lock(&dev_priv->pc8.lock);
6259 __hsw_enable_package_c8(dev_priv);
6260 mutex_unlock(&dev_priv->pc8.lock);
6261}
6262
6263void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6264{
6265 mutex_lock(&dev_priv->pc8.lock);
6266 __hsw_disable_package_c8(dev_priv);
6267 mutex_unlock(&dev_priv->pc8.lock);
6268}
6269
6270static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6271{
6272 struct drm_device *dev = dev_priv->dev;
6273 struct intel_crtc *crtc;
6274 uint32_t val;
6275
6276 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6277 if (crtc->base.enabled)
6278 return false;
6279
6280 /* This case is still possible since we have the i915.disable_power_well
6281 * parameter and also the KVMr or something else might be requesting the
6282 * power well. */
6283 val = I915_READ(HSW_PWR_WELL_DRIVER);
6284 if (val != 0) {
6285 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6286 return false;
6287 }
6288
6289 return true;
6290}
6291
6292/* Since we're called from modeset_global_resources there's no way to
6293 * symmetrically increase and decrease the refcount, so we use
6294 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6295 * or not.
6296 */
6297static void hsw_update_package_c8(struct drm_device *dev)
6298{
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300 bool allow;
6301
6302 if (!i915_enable_pc8)
6303 return;
6304
6305 mutex_lock(&dev_priv->pc8.lock);
6306
6307 allow = hsw_can_enable_package_c8(dev_priv);
6308
6309 if (allow == dev_priv->pc8.requirements_met)
6310 goto done;
6311
6312 dev_priv->pc8.requirements_met = allow;
6313
6314 if (allow)
6315 __hsw_enable_package_c8(dev_priv);
6316 else
6317 __hsw_disable_package_c8(dev_priv);
6318
6319done:
6320 mutex_unlock(&dev_priv->pc8.lock);
6321}
6322
6323static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6324{
6325 if (!dev_priv->pc8.gpu_idle) {
6326 dev_priv->pc8.gpu_idle = true;
6327 hsw_enable_package_c8(dev_priv);
6328 }
6329}
6330
6331static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6332{
6333 if (dev_priv->pc8.gpu_idle) {
6334 dev_priv->pc8.gpu_idle = false;
6335 hsw_disable_package_c8(dev_priv);
6336 }
be256dc7
PZ		 6337}
6338
d6dd9eb1
DV		 6339static void haswell_modeset_global_resources(struct drm_device *dev)
6340{
d6dd9eb1
DV		 6341 bool enable = false;
6342 struct intel_crtc *crtc;
d6dd9eb1
DV		 6343
6344 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6345 if (!crtc->base.enabled)
6346 continue;
d6dd9eb1 6347
e7a639c4
DV		 6348 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6349 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6350 enable = true;
6351 }
6352
d6dd9eb1 6353 intel_set_power_well(dev, enable);
c67a470b
PZ		 6354
6355 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6356}
6357
09b4ddf9 6358static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6359 int x, int y,
6360 struct drm_framebuffer *fb)
6361{
6362 struct drm_device *dev = crtc->dev;
6363 struct drm_i915_private *dev_priv = dev->dev_private;
6364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6365 int plane = intel_crtc->plane;
09b4ddf9 6366 int ret;
09b4ddf9 6367
ff9a6750 6368 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6369 return -EINVAL;
6370
09b4ddf9
PZ		 6371 /* Ensure that the cursor is valid for the new mode before changing... */
6372 intel_crtc_update_cursor(crtc, true);
6373
03afc4a2
DV		 6374 if (intel_crtc->config.has_dp_encoder)
6375 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6376
6377 intel_crtc->lowfreq_avail = false;
09b4ddf9 6378
8a654f3b 6379 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6380
ca3a0ff8 6381 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6382 intel_cpu_transcoder_set_m_n(intel_crtc,
6383 &intel_crtc->config.fdi_m_n);
6384 }
09b4ddf9 6385
6ff93609 6386 haswell_set_pipeconf(crtc);
09b4ddf9 6387
50f3b016 6388 intel_set_pipe_csc(crtc);
86d3efce 6389
09b4ddf9 6390 /* Set up the display plane register */
86d3efce 6391 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6392 POSTING_READ(DSPCNTR(plane));
6393
6394 ret = intel_pipe_set_base(crtc, x, y, fb);
6395
1f803ee5 6396 return ret;
79e53945
JB		 6397}
6398
0e8ffe1b
DV		 6399static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6400 struct intel_crtc_config *pipe_config)
6401{
6402 struct drm_device *dev = crtc->base.dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6404 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6405 uint32_t tmp;
6406
e143a21c 6407 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6408 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6409
eccb140b
DV		 6410 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6411 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6412 enum pipe trans_edp_pipe;
6413 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6414 default:
6415 WARN(1, "unknown pipe linked to edp transcoder\n");
6416 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6417 case TRANS_DDI_EDP_INPUT_A_ON:
6418 trans_edp_pipe = PIPE_A;
6419 break;
6420 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6421 trans_edp_pipe = PIPE_B;
6422 break;
6423 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6424 trans_edp_pipe = PIPE_C;
6425 break;
6426 }
6427
6428 if (trans_edp_pipe == crtc->pipe)
6429 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6430 }
6431
b97186f0 6432 if (!intel_display_power_enabled(dev,
eccb140b 6433 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6434 return false;
6435
eccb140b 6436 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6437 if (!(tmp & PIPECONF_ENABLE))
6438 return false;
6439
88adfff1 6440 /*
f196e6be 6441 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6442 * DDI E. So just check whether this pipe is wired to DDI E and whether
6443 * the PCH transcoder is on.
6444 */
eccb140b 6445 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6446 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6447 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6448 pipe_config->has_pch_encoder = true;
6449
627eb5a3
DV		 6450 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6451 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6452 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6453
6454 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6455 }
6456
1bd1bd80
DV		 6457 intel_get_pipe_timings(crtc, pipe_config);
6458
2fa2fe9a
DV		 6459 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6460 if (intel_display_power_enabled(dev, pfit_domain))
6461 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6462
42db64ef
PZ		 6463 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6464 (I915_READ(IPS_CTL) & IPS_ENABLE);
6465
6c49f241
DV		 6466 pipe_config->pixel_multiplier = 1;
6467
0e8ffe1b
DV		 6468 return true;
6469}
6470
f564048e 6471static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6472 int x, int y,
94352cf9 6473 struct drm_framebuffer *fb)
f564048e
EA		 6474{
6475 struct drm_device *dev = crtc->dev;
6476 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6477 struct intel_encoder *encoder;
0b701d27 6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6479 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6480 int pipe = intel_crtc->pipe;
f564048e
EA		 6481 int ret;
6482
0b701d27 6483 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6484
b8cecdf5
DV		 6485 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6486
79e53945 6487 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6488
9256aa19
DV		 6489 if (ret != 0)
6490 return ret;
6491
6492 for_each_encoder_on_crtc(dev, crtc, encoder) {
6493 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6494 encoder->base.base.id,
6495 drm_get_encoder_name(&encoder->base),
6496 mode->base.id, mode->name);
36f2d1f1 6497 encoder->mode_set(encoder);
9256aa19
DV		 6498 }
6499
6500 return 0;
79e53945
JB		 6501}
6502
3a9627f4
WF		 6503static bool intel_eld_uptodate(struct drm_connector *connector,
6504 int reg_eldv, uint32_t bits_eldv,
6505 int reg_elda, uint32_t bits_elda,
6506 int reg_edid)
6507{
6508 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6509 uint8_t *eld = connector->eld;
6510 uint32_t i;
6511
6512 i = I915_READ(reg_eldv);
6513 i &= bits_eldv;
6514
6515 if (!eld[0])
6516 return !i;
6517
6518 if (!i)
6519 return false;
6520
6521 i = I915_READ(reg_elda);
6522 i &= ~bits_elda;
6523 I915_WRITE(reg_elda, i);
6524
6525 for (i = 0; i < eld[2]; i++)
6526 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6527 return false;
6528
6529 return true;
6530}
6531
e0dac65e
WF		 6532static void g4x_write_eld(struct drm_connector *connector,
6533 struct drm_crtc *crtc)
6534{
6535 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6536 uint8_t *eld = connector->eld;
6537 uint32_t eldv;
6538 uint32_t len;
6539 uint32_t i;
6540
6541 i = I915_READ(G4X_AUD_VID_DID);
6542
6543 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6544 eldv = G4X_ELDV_DEVCL_DEVBLC;
6545 else
6546 eldv = G4X_ELDV_DEVCTG;
6547
3a9627f4
WF		 6548 if (intel_eld_uptodate(connector,
6549 G4X_AUD_CNTL_ST, eldv,
6550 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6551 G4X_HDMIW_HDMIEDID))
6552 return;
6553
e0dac65e
WF		 6554 i = I915_READ(G4X_AUD_CNTL_ST);
6555 i &= ~(eldv | G4X_ELD_ADDR);
6556 len = (i >> 9) & 0x1f; /* ELD buffer size */
6557 I915_WRITE(G4X_AUD_CNTL_ST, i);
6558
6559 if (!eld[0])
6560 return;
6561
6562 len = min_t(uint8_t, eld[2], len);
6563 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6564 for (i = 0; i < len; i++)
6565 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6566
6567 i = I915_READ(G4X_AUD_CNTL_ST);
6568 i |= eldv;
6569 I915_WRITE(G4X_AUD_CNTL_ST, i);
6570}
6571
83358c85
WX		 6572static void haswell_write_eld(struct drm_connector *connector,
6573 struct drm_crtc *crtc)
6574{
6575 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6576 uint8_t *eld = connector->eld;
6577 struct drm_device *dev = crtc->dev;
7b9f35a6 6578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6579 uint32_t eldv;
6580 uint32_t i;
6581 int len;
6582 int pipe = to_intel_crtc(crtc)->pipe;
6583 int tmp;
6584
6585 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6586 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6587 int aud_config = HSW_AUD_CFG(pipe);
6588 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6589
6590
6591 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6592
6593 /* Audio output enable */
6594 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6595 tmp = I915_READ(aud_cntrl_st2);
6596 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6597 I915_WRITE(aud_cntrl_st2, tmp);
6598
6599 /* Wait for 1 vertical blank */
6600 intel_wait_for_vblank(dev, pipe);
6601
6602 /* Set ELD valid state */
6603 tmp = I915_READ(aud_cntrl_st2);
6604 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6605 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6606 I915_WRITE(aud_cntrl_st2, tmp);
6607 tmp = I915_READ(aud_cntrl_st2);
6608 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6609
6610 /* Enable HDMI mode */
6611 tmp = I915_READ(aud_config);
6612 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6613 /* clear N_programing_enable and N_value_index */
6614 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6615 I915_WRITE(aud_config, tmp);
6616
6617 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6618
6619 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6620 intel_crtc->eld_vld = true;
83358c85
WX		 6621
6622 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6623 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6624 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6625 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6626 } else
6627 I915_WRITE(aud_config, 0);
6628
6629 if (intel_eld_uptodate(connector,
6630 aud_cntrl_st2, eldv,
6631 aud_cntl_st, IBX_ELD_ADDRESS,
6632 hdmiw_hdmiedid))
6633 return;
6634
6635 i = I915_READ(aud_cntrl_st2);
6636 i &= ~eldv;
6637 I915_WRITE(aud_cntrl_st2, i);
6638
6639 if (!eld[0])
6640 return;
6641
6642 i = I915_READ(aud_cntl_st);
6643 i &= ~IBX_ELD_ADDRESS;
6644 I915_WRITE(aud_cntl_st, i);
6645 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6646 DRM_DEBUG_DRIVER("port num:%d\n", i);
6647
6648 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6649 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6650 for (i = 0; i < len; i++)
6651 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6652
6653 i = I915_READ(aud_cntrl_st2);
6654 i |= eldv;
6655 I915_WRITE(aud_cntrl_st2, i);
6656
6657}
6658
e0dac65e
WF		 6659static void ironlake_write_eld(struct drm_connector *connector,
6660 struct drm_crtc *crtc)
6661{
6662 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6663 uint8_t *eld = connector->eld;
6664 uint32_t eldv;
6665 uint32_t i;
6666 int len;
6667 int hdmiw_hdmiedid;
b6daa025 6668 int aud_config;
e0dac65e
WF		 6669 int aud_cntl_st;
6670 int aud_cntrl_st2;
9b138a83 6671 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6672
b3f33cbf 6673 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6674 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6675 aud_config = IBX_AUD_CFG(pipe);
6676 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6677 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6678 } else {
9b138a83
WX		 6679 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6680 aud_config = CPT_AUD_CFG(pipe);
6681 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6682 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6683 }
6684
9b138a83 6685 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6686
6687 i = I915_READ(aud_cntl_st);
9b138a83 6688 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6689 if (!i) {
6690 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6691 /* operate blindly on all ports */
1202b4c6
WF		 6692 eldv = IBX_ELD_VALIDB;
6693 eldv |= IBX_ELD_VALIDB << 4;
6694 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6695 } else {
2582a850 6696 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6697 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6698 }
6699
3a9627f4
WF		 6700 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6701 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6702 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6703 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6704 } else
6705 I915_WRITE(aud_config, 0);
e0dac65e 6706
3a9627f4
WF		 6707 if (intel_eld_uptodate(connector,
6708 aud_cntrl_st2, eldv,
6709 aud_cntl_st, IBX_ELD_ADDRESS,
6710 hdmiw_hdmiedid))
6711 return;
6712
e0dac65e
WF		 6713 i = I915_READ(aud_cntrl_st2);
6714 i &= ~eldv;
6715 I915_WRITE(aud_cntrl_st2, i);
6716
6717 if (!eld[0])
6718 return;
6719
e0dac65e 6720 i = I915_READ(aud_cntl_st);
1202b4c6 6721 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6722 I915_WRITE(aud_cntl_st, i);
6723
6724 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6725 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6726 for (i = 0; i < len; i++)
6727 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6728
6729 i = I915_READ(aud_cntrl_st2);
6730 i |= eldv;
6731 I915_WRITE(aud_cntrl_st2, i);
6732}
6733
6734void intel_write_eld(struct drm_encoder *encoder,
6735 struct drm_display_mode *mode)
6736{
6737 struct drm_crtc *crtc = encoder->crtc;
6738 struct drm_connector *connector;
6739 struct drm_device *dev = encoder->dev;
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741
6742 connector = drm_select_eld(encoder, mode);
6743 if (!connector)
6744 return;
6745
6746 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6747 connector->base.id,
6748 drm_get_connector_name(connector),
6749 connector->encoder->base.id,
6750 drm_get_encoder_name(connector->encoder));
6751
6752 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6753
6754 if (dev_priv->display.write_eld)
6755 dev_priv->display.write_eld(connector, crtc);
6756}
6757
79e53945
JB		 6758/** Loads the palette/gamma unit for the CRTC with the prepared values */
6759void intel_crtc_load_lut(struct drm_crtc *crtc)
6760{
6761 struct drm_device *dev = crtc->dev;
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6764 enum pipe pipe = intel_crtc->pipe;
6765 int palreg = PALETTE(pipe);
79e53945 6766 int i;
42db64ef 6767 bool reenable_ips = false;
79e53945
JB		 6768
6769 /* The clocks have to be on to load the palette. */
aed3f09d 6770 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6771 return;
6772
23538ef1
JN		 6773 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6774 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6775 assert_dsi_pll_enabled(dev_priv);
6776 else
6777 assert_pll_enabled(dev_priv, pipe);
6778 }
14420bd0 6779
f2b115e6 6780 /* use legacy palette for Ironlake */
bad720ff 6781 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6782 palreg = LGC_PALETTE(pipe);
6783
6784 /* Workaround : Do not read or write the pipe palette/gamma data while
6785 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6786 */
6787 if (intel_crtc->config.ips_enabled &&
6788 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6789 GAMMA_MODE_MODE_SPLIT)) {
6790 hsw_disable_ips(intel_crtc);
6791 reenable_ips = true;
6792 }
2c07245f 6793
79e53945
JB		 6794 for (i = 0; i < 256; i++) {
6795 I915_WRITE(palreg + 4 * i,
6796 (intel_crtc->lut_r[i] << 16) |
6797 (intel_crtc->lut_g[i] << 8) |
6798 intel_crtc->lut_b[i]);
6799 }
42db64ef
PZ		 6800
6801 if (reenable_ips)
6802 hsw_enable_ips(intel_crtc);
79e53945
JB		 6803}
6804
560b85bb
CW		 6805static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6806{
6807 struct drm_device *dev = crtc->dev;
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6810 bool visible = base != 0;
6811 u32 cntl;
6812
6813 if (intel_crtc->cursor_visible == visible)
6814 return;
6815
9db4a9c7 6816 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6817 if (visible) {
6818 /* On these chipsets we can only modify the base whilst
6819 * the cursor is disabled.
6820 */
9db4a9c7 6821 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6822
6823 cntl &= ~(CURSOR_FORMAT_MASK);
6824 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6825 cntl |= CURSOR_ENABLE |
6826 CURSOR_GAMMA_ENABLE |
6827 CURSOR_FORMAT_ARGB;
6828 } else
6829 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6830 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6831
6832 intel_crtc->cursor_visible = visible;
6833}
6834
6835static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6836{
6837 struct drm_device *dev = crtc->dev;
6838 struct drm_i915_private *dev_priv = dev->dev_private;
6839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840 int pipe = intel_crtc->pipe;
6841 bool visible = base != 0;
6842
6843 if (intel_crtc->cursor_visible != visible) {
548f245b 6844 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6845 if (base) {
6846 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6847 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6848 cntl |= pipe << 28; /* Connect to correct pipe */
6849 } else {
6850 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6851 cntl |= CURSOR_MODE_DISABLE;
6852 }
9db4a9c7 6853 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6854
6855 intel_crtc->cursor_visible = visible;
6856 }
6857 /* and commit changes on next vblank */
9db4a9c7 6858 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6859}
6860
65a21cd6
JB		 6861static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6862{
6863 struct drm_device *dev = crtc->dev;
6864 struct drm_i915_private *dev_priv = dev->dev_private;
6865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6866 int pipe = intel_crtc->pipe;
6867 bool visible = base != 0;
6868
6869 if (intel_crtc->cursor_visible != visible) {
6870 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6871 if (base) {
6872 cntl &= ~CURSOR_MODE;
6873 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6874 } else {
6875 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6876 cntl |= CURSOR_MODE_DISABLE;
6877 }
1f5d76db 6878 if (IS_HASWELL(dev)) {
86d3efce 6879 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6880 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6881 }
65a21cd6
JB		 6882 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6883
6884 intel_crtc->cursor_visible = visible;
6885 }
6886 /* and commit changes on next vblank */
6887 I915_WRITE(CURBASE_IVB(pipe), base);
6888}
6889
cda4b7d3 6890/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6891static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6892 bool on)
cda4b7d3
CW		 6893{
6894 struct drm_device *dev = crtc->dev;
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6897 int pipe = intel_crtc->pipe;
6898 int x = intel_crtc->cursor_x;
6899 int y = intel_crtc->cursor_y;
560b85bb 6900 u32 base, pos;
cda4b7d3
CW		 6901 bool visible;
6902
6903 pos = 0;
6904
6b383a7f 6905 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6906 base = intel_crtc->cursor_addr;
6907 if (x > (int) crtc->fb->width)
6908 base = 0;
6909
6910 if (y > (int) crtc->fb->height)
6911 base = 0;
6912 } else
6913 base = 0;
6914
6915 if (x < 0) {
6916 if (x + intel_crtc->cursor_width < 0)
6917 base = 0;
6918
6919 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6920 x = -x;
6921 }
6922 pos |= x << CURSOR_X_SHIFT;
6923
6924 if (y < 0) {
6925 if (y + intel_crtc->cursor_height < 0)
6926 base = 0;
6927
6928 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6929 y = -y;
6930 }
6931 pos |= y << CURSOR_Y_SHIFT;
6932
6933 visible = base != 0;
560b85bb 6934 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6935 return;
6936
0cd83aa9 6937 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6938 I915_WRITE(CURPOS_IVB(pipe), pos);
6939 ivb_update_cursor(crtc, base);
6940 } else {
6941 I915_WRITE(CURPOS(pipe), pos);
6942 if (IS_845G(dev) || IS_I865G(dev))
6943 i845_update_cursor(crtc, base);
6944 else
6945 i9xx_update_cursor(crtc, base);
6946 }
cda4b7d3
CW		 6947}
6948
79e53945 6949static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6950 struct drm_file *file,
79e53945
JB		 6951 uint32_t handle,
6952 uint32_t width, uint32_t height)
6953{
6954 struct drm_device *dev = crtc->dev;
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6957 struct drm_i915_gem_object *obj;
cda4b7d3 6958 uint32_t addr;
3f8bc370 6959 int ret;
79e53945 6960
79e53945
JB		 6961 /* if we want to turn off the cursor ignore width and height */
6962 if (!handle) {
28c97730 6963 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6964 addr = 0;
05394f39 6965 obj = NULL;
5004417d 6966 mutex_lock(&dev->struct_mutex);
3f8bc370 6967 goto finish;
79e53945
JB		 6968 }
6969
6970 /* Currently we only support 64x64 cursors */
6971 if (width != 64 || height != 64) {
6972 DRM_ERROR("we currently only support 64x64 cursors\n");
6973 return -EINVAL;
6974 }
6975
05394f39 6976 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6977 if (&obj->base == NULL)
79e53945
JB		 6978 return -ENOENT;
6979
05394f39 6980 if (obj->base.size < width * height * 4) {
79e53945 6981 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6982 ret = -ENOMEM;
6983 goto fail;
79e53945
JB		 6984 }
6985
71acb5eb 6986 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6987 mutex_lock(&dev->struct_mutex);
b295d1b6 6988 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6989 unsigned alignment;
6990
d9e86c0e
CW		 6991 if (obj->tiling_mode) {
6992 DRM_ERROR("cursor cannot be tiled\n");
6993 ret = -EINVAL;
6994 goto fail_locked;
6995 }
6996
693db184
CW		 6997 /* Note that the w/a also requires 2 PTE of padding following
6998 * the bo. We currently fill all unused PTE with the shadow
6999 * page and so we should always have valid PTE following the
7000 * cursor preventing the VT-d warning.
7001 */
7002 alignment = 0;
7003 if (need_vtd_wa(dev))
7004 alignment = 64*1024;
7005
7006 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7007 if (ret) {
7008 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7009 goto fail_locked;
e7b526bb
CW		 7010 }
7011
d9e86c0e
CW		 7012 ret = i915_gem_object_put_fence(obj);
7013 if (ret) {
2da3b9b9 7014 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7015 goto fail_unpin;
7016 }
7017
f343c5f6 7018 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7019 } else {
6eeefaf3 7020 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7021 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7022 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7023 align);
71acb5eb
DA		 7024 if (ret) {
7025 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7026 goto fail_locked;
71acb5eb 7027 }
05394f39 7028 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7029 }
7030
a6c45cf0 7031 if (IS_GEN2(dev))
14b60391
JB		 7032 I915_WRITE(CURSIZE, (height << 12) | width);
7033
3f8bc370 7034 finish:
3f8bc370 7035 if (intel_crtc->cursor_bo) {
b295d1b6 7036 if (dev_priv->info->cursor_needs_physical) {
05394f39 7037 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7038 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7039 } else
cc98b413 7040 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7041 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7042 }
80824003 7043
7f9872e0 7044 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7045
7046 intel_crtc->cursor_addr = addr;
05394f39 7047 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7048 intel_crtc->cursor_width = width;
7049 intel_crtc->cursor_height = height;
7050
40ccc72b 7051 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7052
79e53945 7053 return 0;
e7b526bb 7054fail_unpin:
cc98b413 7055 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7056fail_locked:
34b8686e 7057 mutex_unlock(&dev->struct_mutex);
bc9025bd 7058fail:
05394f39 7059 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7060 return ret;
79e53945
JB		 7061}
7062
7063static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7064{
79e53945 7065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7066
cda4b7d3
CW		 7067 intel_crtc->cursor_x = x;
7068 intel_crtc->cursor_y = y;
652c393a 7069
40ccc72b 7070 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7071
7072 return 0;
7073}
7074
7075/** Sets the color ramps on behalf of RandR */
7076void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7077 u16 blue, int regno)
7078{
7079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7080
7081 intel_crtc->lut_r[regno] = red >> 8;
7082 intel_crtc->lut_g[regno] = green >> 8;
7083 intel_crtc->lut_b[regno] = blue >> 8;
7084}
7085
b8c00ac5
DA		 7086void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7087 u16 *blue, int regno)
7088{
7089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7090
7091 *red = intel_crtc->lut_r[regno] << 8;
7092 *green = intel_crtc->lut_g[regno] << 8;
7093 *blue = intel_crtc->lut_b[regno] << 8;
7094}
7095
79e53945 7096static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7097 u16 *blue, uint32_t start, uint32_t size)
79e53945 7098{
7203425a 7099 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7101
7203425a 7102 for (i = start; i < end; i++) {
79e53945
JB		 7103 intel_crtc->lut_r[i] = red[i] >> 8;
7104 intel_crtc->lut_g[i] = green[i] >> 8;
7105 intel_crtc->lut_b[i] = blue[i] >> 8;
7106 }
7107
7108 intel_crtc_load_lut(crtc);
7109}
7110
79e53945
JB		 7111/* VESA 640x480x72Hz mode to set on the pipe */
7112static struct drm_display_mode load_detect_mode = {
7113 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7114 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7115};
7116
d2dff872
CW		 7117static struct drm_framebuffer *
7118intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7119 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7120 struct drm_i915_gem_object *obj)
7121{
7122 struct intel_framebuffer *intel_fb;
7123 int ret;
7124
7125 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7126 if (!intel_fb) {
7127 drm_gem_object_unreference_unlocked(&obj->base);
7128 return ERR_PTR(-ENOMEM);
7129 }
7130
7131 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7132 if (ret) {
7133 drm_gem_object_unreference_unlocked(&obj->base);
7134 kfree(intel_fb);
7135 return ERR_PTR(ret);
7136 }
7137
7138 return &intel_fb->base;
7139}
7140
7141static u32
7142intel_framebuffer_pitch_for_width(int width, int bpp)
7143{
7144 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7145 return ALIGN(pitch, 64);
7146}
7147
7148static u32
7149intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7150{
7151 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7152 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7153}
7154
7155static struct drm_framebuffer *
7156intel_framebuffer_create_for_mode(struct drm_device *dev,
7157 struct drm_display_mode *mode,
7158 int depth, int bpp)
7159{
7160 struct drm_i915_gem_object *obj;
0fed39bd 7161 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7162
7163 obj = i915_gem_alloc_object(dev,
7164 intel_framebuffer_size_for_mode(mode, bpp));
7165 if (obj == NULL)
7166 return ERR_PTR(-ENOMEM);
7167
7168 mode_cmd.width = mode->hdisplay;
7169 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7170 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7171 bpp);
5ca0c34a 7172 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7173
7174 return intel_framebuffer_create(dev, &mode_cmd, obj);
7175}
7176
7177static struct drm_framebuffer *
7178mode_fits_in_fbdev(struct drm_device *dev,
7179 struct drm_display_mode *mode)
7180{
7181 struct drm_i915_private *dev_priv = dev->dev_private;
7182 struct drm_i915_gem_object *obj;
7183 struct drm_framebuffer *fb;
7184
7185 if (dev_priv->fbdev == NULL)
7186 return NULL;
7187
7188 obj = dev_priv->fbdev->ifb.obj;
7189 if (obj == NULL)
7190 return NULL;
7191
7192 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7193 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7194 fb->bits_per_pixel))
d2dff872
CW		 7195 return NULL;
7196
01f2c773 7197 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7198 return NULL;
7199
7200 return fb;
7201}
7202
d2434ab7 7203bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7204 struct drm_display_mode *mode,
8261b191 7205 struct intel_load_detect_pipe *old)
79e53945
JB		 7206{
7207 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7208 struct intel_encoder *intel_encoder =
7209 intel_attached_encoder(connector);
79e53945 7210 struct drm_crtc *possible_crtc;
4ef69c7a 7211 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7212 struct drm_crtc *crtc = NULL;
7213 struct drm_device *dev = encoder->dev;
94352cf9 7214 struct drm_framebuffer *fb;
79e53945
JB		 7215 int i = -1;
7216
d2dff872
CW		 7217 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7218 connector->base.id, drm_get_connector_name(connector),
7219 encoder->base.id, drm_get_encoder_name(encoder));
7220
79e53945
JB		 7221 /*
7222 * Algorithm gets a little messy:
7a5e4805 7223 *
79e53945
JB		 7224 * - if the connector already has an assigned crtc, use it (but make
7225 * sure it's on first)
7a5e4805 7226 *
79e53945
JB		 7227 * - try to find the first unused crtc that can drive this connector,
7228 * and use that if we find one
79e53945
JB		 7229 */
7230
7231 /* See if we already have a CRTC for this connector */
7232 if (encoder->crtc) {
7233 crtc = encoder->crtc;
8261b191 7234
7b24056b
DV		 7235 mutex_lock(&crtc->mutex);
7236
24218aac 7237 old->dpms_mode = connector->dpms;
8261b191
CW		 7238 old->load_detect_temp = false;
7239
7240 /* Make sure the crtc and connector are running */
24218aac
DV		 7241 if (connector->dpms != DRM_MODE_DPMS_ON)
7242 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7243
7173188d 7244 return true;
79e53945
JB		 7245 }
7246
7247 /* Find an unused one (if possible) */
7248 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7249 i++;
7250 if (!(encoder->possible_crtcs & (1 << i)))
7251 continue;
7252 if (!possible_crtc->enabled) {
7253 crtc = possible_crtc;
7254 break;
7255 }
79e53945
JB		 7256 }
7257
7258 /*
7259 * If we didn't find an unused CRTC, don't use any.
7260 */
7261 if (!crtc) {
7173188d
CW		 7262 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7263 return false;
79e53945
JB		 7264 }
7265
7b24056b 7266 mutex_lock(&crtc->mutex);
fc303101
DV		 7267 intel_encoder->new_crtc = to_intel_crtc(crtc);
7268 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7269
7270 intel_crtc = to_intel_crtc(crtc);
24218aac 7271 old->dpms_mode = connector->dpms;
8261b191 7272 old->load_detect_temp = true;
d2dff872 7273 old->release_fb = NULL;
79e53945 7274
6492711d
CW		 7275 if (!mode)
7276 mode = &load_detect_mode;
79e53945 7277
d2dff872
CW		 7278 /* We need a framebuffer large enough to accommodate all accesses
7279 * that the plane may generate whilst we perform load detection.
7280 * We can not rely on the fbcon either being present (we get called
7281 * during its initialisation to detect all boot displays, or it may
7282 * not even exist) or that it is large enough to satisfy the
7283 * requested mode.
7284 */
94352cf9
DV		 7285 fb = mode_fits_in_fbdev(dev, mode);
7286 if (fb == NULL) {
d2dff872 7287 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7288 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7289 old->release_fb = fb;
d2dff872
CW		 7290 } else
7291 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7292 if (IS_ERR(fb)) {
d2dff872 7293 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7294 mutex_unlock(&crtc->mutex);
0e8b3d3e 7295 return false;
79e53945 7296 }
79e53945 7297
c0c36b94 7298 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7299 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7300 if (old->release_fb)
7301 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7302 mutex_unlock(&crtc->mutex);
0e8b3d3e 7303 return false;
79e53945 7304 }
7173188d 7305
79e53945 7306 /* let the connector get through one full cycle before testing */
9d0498a2 7307 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7308 return true;
79e53945
JB		 7309}
7310
d2434ab7 7311void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7312 struct intel_load_detect_pipe *old)
79e53945 7313{
d2434ab7
DV		 7314 struct intel_encoder *intel_encoder =
7315 intel_attached_encoder(connector);
4ef69c7a 7316 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7317 struct drm_crtc *crtc = encoder->crtc;
79e53945 7318
d2dff872
CW		 7319 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7320 connector->base.id, drm_get_connector_name(connector),
7321 encoder->base.id, drm_get_encoder_name(encoder));
7322
8261b191 7323 if (old->load_detect_temp) {
fc303101
DV		 7324 to_intel_connector(connector)->new_encoder = NULL;
7325 intel_encoder->new_crtc = NULL;
7326 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7327
36206361
DV		 7328 if (old->release_fb) {
7329 drm_framebuffer_unregister_private(old->release_fb);
7330 drm_framebuffer_unreference(old->release_fb);
7331 }
d2dff872 7332
67c96400 7333 mutex_unlock(&crtc->mutex);
0622a53c 7334 return;
79e53945
JB		 7335 }
7336
c751ce4f 7337 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7338 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7339 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7340
7341 mutex_unlock(&crtc->mutex);
79e53945
JB		 7342}
7343
da4a1efa
VS		 7344static int i9xx_pll_refclk(struct drm_device *dev,
7345 const struct intel_crtc_config *pipe_config)
7346{
7347 struct drm_i915_private *dev_priv = dev->dev_private;
7348 u32 dpll = pipe_config->dpll_hw_state.dpll;
7349
7350 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7351 return dev_priv->vbt.lvds_ssc_freq * 1000;
7352 else if (HAS_PCH_SPLIT(dev))
7353 return 120000;
7354 else if (!IS_GEN2(dev))
7355 return 96000;
7356 else
7357 return 48000;
7358}
7359
79e53945 7360/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7361static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7362 struct intel_crtc_config *pipe_config)
79e53945 7363{
f1f644dc 7364 struct drm_device *dev = crtc->base.dev;
79e53945 7365 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7366 int pipe = pipe_config->cpu_transcoder;
293623f7 7367 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7368 u32 fp;
7369 intel_clock_t clock;
da4a1efa 7370 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7371
7372 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7373 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7374 else
293623f7 7375 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7376
7377 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7378 if (IS_PINEVIEW(dev)) {
7379 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7380 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7381 } else {
7382 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7383 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7384 }
7385
a6c45cf0 7386 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7387 if (IS_PINEVIEW(dev))
7388 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7389 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7390 else
7391 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7392 DPLL_FPA01_P1_POST_DIV_SHIFT);
7393
7394 switch (dpll & DPLL_MODE_MASK) {
7395 case DPLLB_MODE_DAC_SERIAL:
7396 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7397 5 : 10;
7398 break;
7399 case DPLLB_MODE_LVDS:
7400 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7401 7 : 14;
7402 break;
7403 default:
28c97730 7404 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7405 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7406 return;
79e53945
JB		 7407 }
7408
ac58c3f0 7409 if (IS_PINEVIEW(dev))
da4a1efa 7410 pineview_clock(refclk, &clock);
ac58c3f0 7411 else
da4a1efa 7412 i9xx_clock(refclk, &clock);
79e53945
JB		 7413 } else {
7414 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7415
7416 if (is_lvds) {
7417 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7418 DPLL_FPA01_P1_POST_DIV_SHIFT);
7419 clock.p2 = 14;
79e53945
JB		 7420 } else {
7421 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7422 clock.p1 = 2;
7423 else {
7424 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7425 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7426 }
7427 if (dpll & PLL_P2_DIVIDE_BY_4)
7428 clock.p2 = 4;
7429 else
7430 clock.p2 = 2;
79e53945 7431 }
da4a1efa
VS		 7432
7433 i9xx_clock(refclk, &clock);
79e53945
JB		 7434 }
7435
a2dc53e7 7436 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7437}
7438
6878da05
VS		 7439int intel_dotclock_calculate(int link_freq,
7440 const struct intel_link_m_n *m_n)
f1f644dc 7441{
f1f644dc
JB		 7442 /*
7443 * The calculation for the data clock is:
1041a02f 7444 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7445 * But we want to avoid losing precison if possible, so:
1041a02f 7446 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7447 *
7448 * and the link clock is simpler:
1041a02f 7449 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7450 */
7451
6878da05
VS		 7452 if (!m_n->link_n)
7453 return 0;
7454
7455 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7456}
7457
7458static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7459 struct intel_crtc_config *pipe_config)
7460{
7461 struct drm_device *dev = crtc->base.dev;
7462 int link_freq;
7463
f1f644dc
JB		 7464 /*
7465 * We need to get the FDI or DP link clock here to derive
7466 * the M/N dividers.
7467 *
7468 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7469 * For DP, it's either 1.62GHz or 2.7GHz.
7470 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7471 */
6878da05 7472 if (pipe_config->has_pch_encoder) {
f1f644dc 7473 link_freq = intel_fdi_link_freq(dev) * 10000;
f1f644dc 7474
6878da05
VS		 7475 pipe_config->adjusted_mode.clock =
7476 intel_dotclock_calculate(link_freq, &pipe_config->fdi_m_n);
7477 } else {
7478 link_freq = pipe_config->port_clock;
f1f644dc 7479
6878da05
VS		 7480 pipe_config->adjusted_mode.clock =
7481 intel_dotclock_calculate(link_freq, &pipe_config->dp_m_n);
7482 }
79e53945
JB		 7483}
7484
7485/** Returns the currently programmed mode of the given pipe. */
7486struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7487 struct drm_crtc *crtc)
7488{
548f245b 7489 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7491 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7492 struct drm_display_mode *mode;
f1f644dc 7493 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7494 int htot = I915_READ(HTOTAL(cpu_transcoder));
7495 int hsync = I915_READ(HSYNC(cpu_transcoder));
7496 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7497 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7498 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7499
7500 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7501 if (!mode)
7502 return NULL;
7503
f1f644dc
JB		 7504 /*
7505 * Construct a pipe_config sufficient for getting the clock info
7506 * back out of crtc_clock_get.
7507 *
7508 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7509 * to use a real value here instead.
7510 */
293623f7 7511 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7512 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7513 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7514 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7515 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7516 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7517
7518 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7519 mode->hdisplay = (htot & 0xffff) + 1;
7520 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7521 mode->hsync_start = (hsync & 0xffff) + 1;
7522 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7523 mode->vdisplay = (vtot & 0xffff) + 1;
7524 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7525 mode->vsync_start = (vsync & 0xffff) + 1;
7526 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7527
7528 drm_mode_set_name(mode);
79e53945
JB		 7529
7530 return mode;
7531}
7532
3dec0095 7533static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7534{
7535 struct drm_device *dev = crtc->dev;
7536 drm_i915_private_t *dev_priv = dev->dev_private;
7537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7538 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7539 int dpll_reg = DPLL(pipe);
7540 int dpll;
652c393a 7541
bad720ff 7542 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7543 return;
7544
7545 if (!dev_priv->lvds_downclock_avail)
7546 return;
7547
dbdc6479 7548 dpll = I915_READ(dpll_reg);
652c393a 7549 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7550 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7551
8ac5a6d5 7552 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7553
7554 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7555 I915_WRITE(dpll_reg, dpll);
9d0498a2 7556 intel_wait_for_vblank(dev, pipe);
dbdc6479 7557
652c393a
JB		 7558 dpll = I915_READ(dpll_reg);
7559 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7560 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7561 }
652c393a
JB		 7562}
7563
7564static void intel_decrease_pllclock(struct drm_crtc *crtc)
7565{
7566 struct drm_device *dev = crtc->dev;
7567 drm_i915_private_t *dev_priv = dev->dev_private;
7568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7569
bad720ff 7570 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7571 return;
7572
7573 if (!dev_priv->lvds_downclock_avail)
7574 return;
7575
7576 /*
7577 * Since this is called by a timer, we should never get here in
7578 * the manual case.
7579 */
7580 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7581 int pipe = intel_crtc->pipe;
7582 int dpll_reg = DPLL(pipe);
7583 int dpll;
f6e5b160 7584
44d98a61 7585 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7586
8ac5a6d5 7587 assert_panel_unlocked(dev_priv, pipe);
652c393a 7588
dc257cf1 7589 dpll = I915_READ(dpll_reg);
652c393a
JB		 7590 dpll |= DISPLAY_RATE_SELECT_FPA1;
7591 I915_WRITE(dpll_reg, dpll);
9d0498a2 7592 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7593 dpll = I915_READ(dpll_reg);
7594 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7595 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7596 }
7597
7598}
7599
f047e395
CW		 7600void intel_mark_busy(struct drm_device *dev)
7601{
c67a470b
PZ		 7602 struct drm_i915_private *dev_priv = dev->dev_private;
7603
7604 hsw_package_c8_gpu_busy(dev_priv);
7605 i915_update_gfx_val(dev_priv);
f047e395
CW		 7606}
7607
7608void intel_mark_idle(struct drm_device *dev)
652c393a 7609{
c67a470b 7610 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7611 struct drm_crtc *crtc;
652c393a 7612
c67a470b
PZ		 7613 hsw_package_c8_gpu_idle(dev_priv);
7614
652c393a
JB		 7615 if (!i915_powersave)
7616 return;
7617
652c393a 7618 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7619 if (!crtc->fb)
7620 continue;
7621
725a5b54 7622 intel_decrease_pllclock(crtc);
652c393a 7623 }
652c393a
JB		 7624}
7625
c65355bb
CW		 7626void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7627 struct intel_ring_buffer *ring)
652c393a 7628{
f047e395
CW		 7629 struct drm_device *dev = obj->base.dev;
7630 struct drm_crtc *crtc;
652c393a 7631
f047e395 7632 if (!i915_powersave)
acb87dfb
CW		 7633 return;
7634
652c393a
JB		 7635 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7636 if (!crtc->fb)
7637 continue;
7638
c65355bb
CW		 7639 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7640 continue;
7641
7642 intel_increase_pllclock(crtc);
7643 if (ring && intel_fbc_enabled(dev))
7644 ring->fbc_dirty = true;
652c393a
JB		 7645 }
7646}
7647
79e53945
JB		 7648static void intel_crtc_destroy(struct drm_crtc *crtc)
7649{
7650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7651 struct drm_device *dev = crtc->dev;
7652 struct intel_unpin_work *work;
7653 unsigned long flags;
7654
7655 spin_lock_irqsave(&dev->event_lock, flags);
7656 work = intel_crtc->unpin_work;
7657 intel_crtc->unpin_work = NULL;
7658 spin_unlock_irqrestore(&dev->event_lock, flags);
7659
7660 if (work) {
7661 cancel_work_sync(&work->work);
7662 kfree(work);
7663 }
79e53945 7664
40ccc72b
MK		 7665 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7666
79e53945 7667 drm_crtc_cleanup(crtc);
67e77c5a 7668
79e53945
JB		 7669 kfree(intel_crtc);
7670}
7671
6b95a207
KH		 7672static void intel_unpin_work_fn(struct work_struct *__work)
7673{
7674 struct intel_unpin_work *work =
7675 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7676 struct drm_device *dev = work->crtc->dev;
6b95a207 7677
b4a98e57 7678 mutex_lock(&dev->struct_mutex);
1690e1eb 7679 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7680 drm_gem_object_unreference(&work->pending_flip_obj->base);
7681 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7682
b4a98e57
CW		 7683 intel_update_fbc(dev);
7684 mutex_unlock(&dev->struct_mutex);
7685
7686 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7687 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7688
6b95a207
KH		 7689 kfree(work);
7690}
7691
1afe3e9d 7692static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7693 struct drm_crtc *crtc)
6b95a207
KH		 7694{
7695 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7697 struct intel_unpin_work *work;
6b95a207
KH		 7698 unsigned long flags;
7699
7700 /* Ignore early vblank irqs */
7701 if (intel_crtc == NULL)
7702 return;
7703
7704 spin_lock_irqsave(&dev->event_lock, flags);
7705 work = intel_crtc->unpin_work;
e7d841ca
CW		 7706
7707 /* Ensure we don't miss a work->pending update ... */
7708 smp_rmb();
7709
7710 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7711 spin_unlock_irqrestore(&dev->event_lock, flags);
7712 return;
7713 }
7714
e7d841ca
CW		 7715 /* and that the unpin work is consistent wrt ->pending. */
7716 smp_rmb();
7717
6b95a207 7718 intel_crtc->unpin_work = NULL;
6b95a207 7719
45a066eb
RC		 7720 if (work->event)
7721 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7722
0af7e4df
MK		 7723 drm_vblank_put(dev, intel_crtc->pipe);
7724
6b95a207
KH		 7725 spin_unlock_irqrestore(&dev->event_lock, flags);
7726
2c10d571 7727 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7728
7729 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7730
7731 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7732}
7733
1afe3e9d
JB		 7734void intel_finish_page_flip(struct drm_device *dev, int pipe)
7735{
7736 drm_i915_private_t *dev_priv = dev->dev_private;
7737 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7738
49b14a5c 7739 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7740}
7741
7742void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7743{
7744 drm_i915_private_t *dev_priv = dev->dev_private;
7745 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7746
49b14a5c 7747 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7748}
7749
6b95a207
KH		 7750void intel_prepare_page_flip(struct drm_device *dev, int plane)
7751{
7752 drm_i915_private_t *dev_priv = dev->dev_private;
7753 struct intel_crtc *intel_crtc =
7754 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7755 unsigned long flags;
7756
e7d841ca
CW		 7757 /* NB: An MMIO update of the plane base pointer will also
7758 * generate a page-flip completion irq, i.e. every modeset
7759 * is also accompanied by a spurious intel_prepare_page_flip().
7760 */
6b95a207 7761 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7762 if (intel_crtc->unpin_work)
7763 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7764 spin_unlock_irqrestore(&dev->event_lock, flags);
7765}
7766
e7d841ca
CW		 7767inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7768{
7769 /* Ensure that the work item is consistent when activating it ... */
7770 smp_wmb();
7771 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7772 /* and that it is marked active as soon as the irq could fire. */
7773 smp_wmb();
7774}
7775
8c9f3aaf
JB		 7776static int intel_gen2_queue_flip(struct drm_device *dev,
7777 struct drm_crtc *crtc,
7778 struct drm_framebuffer *fb,
ed8d1975
KP		 7779 struct drm_i915_gem_object *obj,
7780 uint32_t flags)
8c9f3aaf
JB		 7781{
7782 struct drm_i915_private *dev_priv = dev->dev_private;
7783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7784 u32 flip_mask;
6d90c952 7785 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7786 int ret;
7787
6d90c952 7788 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7789 if (ret)
83d4092b 7790 goto err;
8c9f3aaf 7791
6d90c952 7792 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7793 if (ret)
83d4092b 7794 goto err_unpin;
8c9f3aaf
JB		 7795
7796 /* Can't queue multiple flips, so wait for the previous
7797 * one to finish before executing the next.
7798 */
7799 if (intel_crtc->plane)
7800 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7801 else
7802 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7803 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7804 intel_ring_emit(ring, MI_NOOP);
7805 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7806 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7807 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7808 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7809 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7810
7811 intel_mark_page_flip_active(intel_crtc);
09246732 7812 __intel_ring_advance(ring);
83d4092b
CW		 7813 return 0;
7814
7815err_unpin:
7816 intel_unpin_fb_obj(obj);
7817err:
8c9f3aaf
JB		 7818 return ret;
7819}
7820
7821static int intel_gen3_queue_flip(struct drm_device *dev,
7822 struct drm_crtc *crtc,
7823 struct drm_framebuffer *fb,
ed8d1975
KP		 7824 struct drm_i915_gem_object *obj,
7825 uint32_t flags)
8c9f3aaf
JB		 7826{
7827 struct drm_i915_private *dev_priv = dev->dev_private;
7828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7829 u32 flip_mask;
6d90c952 7830 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7831 int ret;
7832
6d90c952 7833 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7834 if (ret)
83d4092b 7835 goto err;
8c9f3aaf 7836
6d90c952 7837 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7838 if (ret)
83d4092b 7839 goto err_unpin;
8c9f3aaf
JB		 7840
7841 if (intel_crtc->plane)
7842 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7843 else
7844 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7845 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7846 intel_ring_emit(ring, MI_NOOP);
7847 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7848 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7849 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7850 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7851 intel_ring_emit(ring, MI_NOOP);
7852
e7d841ca 7853 intel_mark_page_flip_active(intel_crtc);
09246732 7854 __intel_ring_advance(ring);
83d4092b
CW		 7855 return 0;
7856
7857err_unpin:
7858 intel_unpin_fb_obj(obj);
7859err:
8c9f3aaf
JB		 7860 return ret;
7861}
7862
7863static int intel_gen4_queue_flip(struct drm_device *dev,
7864 struct drm_crtc *crtc,
7865 struct drm_framebuffer *fb,
ed8d1975
KP		 7866 struct drm_i915_gem_object *obj,
7867 uint32_t flags)
8c9f3aaf
JB		 7868{
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871 uint32_t pf, pipesrc;
6d90c952 7872 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7873 int ret;
7874
6d90c952 7875 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7876 if (ret)
83d4092b 7877 goto err;
8c9f3aaf 7878
6d90c952 7879 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7880 if (ret)
83d4092b 7881 goto err_unpin;
8c9f3aaf
JB		 7882
7883 /* i965+ uses the linear or tiled offsets from the
7884 * Display Registers (which do not change across a page-flip)
7885 * so we need only reprogram the base address.
7886 */
6d90c952
DV		 7887 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7888 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7889 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7890 intel_ring_emit(ring,
f343c5f6 7891 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7892 obj->tiling_mode);
8c9f3aaf
JB		 7893
7894 /* XXX Enabling the panel-fitter across page-flip is so far
7895 * untested on non-native modes, so ignore it for now.
7896 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7897 */
7898 pf = 0;
7899 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7900 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7901
7902 intel_mark_page_flip_active(intel_crtc);
09246732 7903 __intel_ring_advance(ring);
83d4092b
CW		 7904 return 0;
7905
7906err_unpin:
7907 intel_unpin_fb_obj(obj);
7908err:
8c9f3aaf
JB		 7909 return ret;
7910}
7911
7912static int intel_gen6_queue_flip(struct drm_device *dev,
7913 struct drm_crtc *crtc,
7914 struct drm_framebuffer *fb,
ed8d1975
KP		 7915 struct drm_i915_gem_object *obj,
7916 uint32_t flags)
8c9f3aaf
JB		 7917{
7918 struct drm_i915_private *dev_priv = dev->dev_private;
7919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7920 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7921 uint32_t pf, pipesrc;
7922 int ret;
7923
6d90c952 7924 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7925 if (ret)
83d4092b 7926 goto err;
8c9f3aaf 7927
6d90c952 7928 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7929 if (ret)
83d4092b 7930 goto err_unpin;
8c9f3aaf 7931
6d90c952
DV		 7932 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7933 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7934 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7935 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7936
dc257cf1
DV		 7937 /* Contrary to the suggestions in the documentation,
7938 * "Enable Panel Fitter" does not seem to be required when page
7939 * flipping with a non-native mode, and worse causes a normal
7940 * modeset to fail.
7941 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7942 */
7943 pf = 0;
8c9f3aaf 7944 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7945 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7946
7947 intel_mark_page_flip_active(intel_crtc);
09246732 7948 __intel_ring_advance(ring);
83d4092b
CW		 7949 return 0;
7950
7951err_unpin:
7952 intel_unpin_fb_obj(obj);
7953err:
8c9f3aaf
JB		 7954 return ret;
7955}
7956
7c9017e5
JB		 7957static int intel_gen7_queue_flip(struct drm_device *dev,
7958 struct drm_crtc *crtc,
7959 struct drm_framebuffer *fb,
ed8d1975
KP		 7960 struct drm_i915_gem_object *obj,
7961 uint32_t flags)
7c9017e5
JB		 7962{
7963 struct drm_i915_private *dev_priv = dev->dev_private;
7964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7965 struct intel_ring_buffer *ring;
cb05d8de 7966 uint32_t plane_bit = 0;
ffe74d75
CW		 7967 int len, ret;
7968
7969 ring = obj->ring;
7970 if (ring == NULL || ring->id != RCS)
7971 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7972
7973 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7974 if (ret)
83d4092b 7975 goto err;
7c9017e5 7976
cb05d8de
DV		 7977 switch(intel_crtc->plane) {
7978 case PLANE_A:
7979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7980 break;
7981 case PLANE_B:
7982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7983 break;
7984 case PLANE_C:
7985 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7986 break;
7987 default:
7988 WARN_ONCE(1, "unknown plane in flip command\n");
7989 ret = -ENODEV;
ab3951eb 7990 goto err_unpin;
cb05d8de
DV		 7991 }
7992
ffe74d75
CW		 7993 len = 4;
7994 if (ring->id == RCS)
7995 len += 6;
7996
7997 ret = intel_ring_begin(ring, len);
7c9017e5 7998 if (ret)
83d4092b 7999 goto err_unpin;
7c9017e5 8000
ffe74d75
CW		 8001 /* Unmask the flip-done completion message. Note that the bspec says that
8002 * we should do this for both the BCS and RCS, and that we must not unmask
8003 * more than one flip event at any time (or ensure that one flip message
8004 * can be sent by waiting for flip-done prior to queueing new flips).
8005 * Experimentation says that BCS works despite DERRMR masking all
8006 * flip-done completion events and that unmasking all planes at once
8007 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8008 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8009 */
8010 if (ring->id == RCS) {
8011 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8012 intel_ring_emit(ring, DERRMR);
8013 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8014 DERRMR_PIPEB_PRI_FLIP_DONE |
8015 DERRMR_PIPEC_PRI_FLIP_DONE));
8016 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8017 intel_ring_emit(ring, DERRMR);
8018 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8019 }
8020
cb05d8de 8021 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8022 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8023 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8024 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8025
8026 intel_mark_page_flip_active(intel_crtc);
09246732 8027 __intel_ring_advance(ring);
83d4092b
CW		 8028 return 0;
8029
8030err_unpin:
8031 intel_unpin_fb_obj(obj);
8032err:
7c9017e5
JB		 8033 return ret;
8034}
8035
8c9f3aaf
JB		 8036static int intel_default_queue_flip(struct drm_device *dev,
8037 struct drm_crtc *crtc,
8038 struct drm_framebuffer *fb,
ed8d1975
KP		 8039 struct drm_i915_gem_object *obj,
8040 uint32_t flags)
8c9f3aaf
JB		 8041{
8042 return -ENODEV;
8043}
8044
6b95a207
KH		 8045static int intel_crtc_page_flip(struct drm_crtc *crtc,
8046 struct drm_framebuffer *fb,
ed8d1975
KP		 8047 struct drm_pending_vblank_event *event,
8048 uint32_t page_flip_flags)
6b95a207
KH		 8049{
8050 struct drm_device *dev = crtc->dev;
8051 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8052 struct drm_framebuffer *old_fb = crtc->fb;
8053 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8055 struct intel_unpin_work *work;
8c9f3aaf 8056 unsigned long flags;
52e68630 8057 int ret;
6b95a207 8058
e6a595d2
VS		 8059 /* Can't change pixel format via MI display flips. */
8060 if (fb->pixel_format != crtc->fb->pixel_format)
8061 return -EINVAL;
8062
8063 /*
8064 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8065 * Note that pitch changes could also affect these register.
8066 */
8067 if (INTEL_INFO(dev)->gen > 3 &&
8068 (fb->offsets[0] != crtc->fb->offsets[0] ||
8069 fb->pitches[0] != crtc->fb->pitches[0]))
8070 return -EINVAL;
8071
6b95a207
KH		 8072 work = kzalloc(sizeof *work, GFP_KERNEL);
8073 if (work == NULL)
8074 return -ENOMEM;
8075
6b95a207 8076 work->event = event;
b4a98e57 8077 work->crtc = crtc;
4a35f83b 8078 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8079 INIT_WORK(&work->work, intel_unpin_work_fn);
8080
7317c75e
JB		 8081 ret = drm_vblank_get(dev, intel_crtc->pipe);
8082 if (ret)
8083 goto free_work;
8084
6b95a207
KH		 8085 /* We borrow the event spin lock for protecting unpin_work */
8086 spin_lock_irqsave(&dev->event_lock, flags);
8087 if (intel_crtc->unpin_work) {
8088 spin_unlock_irqrestore(&dev->event_lock, flags);
8089 kfree(work);
7317c75e 8090 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8091
8092 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8093 return -EBUSY;
8094 }
8095 intel_crtc->unpin_work = work;
8096 spin_unlock_irqrestore(&dev->event_lock, flags);
8097
b4a98e57
CW		 8098 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8099 flush_workqueue(dev_priv->wq);
8100
79158103
CW		 8101 ret = i915_mutex_lock_interruptible(dev);
8102 if (ret)
8103 goto cleanup;
6b95a207 8104
75dfca80 8105 /* Reference the objects for the scheduled work. */
05394f39
CW		 8106 drm_gem_object_reference(&work->old_fb_obj->base);
8107 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8108
8109 crtc->fb = fb;
96b099fd 8110
e1f99ce6 8111 work->pending_flip_obj = obj;
e1f99ce6 8112
4e5359cd
SF		 8113 work->enable_stall_check = true;
8114
b4a98e57 8115 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8116 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8117
ed8d1975 8118 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8119 if (ret)
8120 goto cleanup_pending;
6b95a207 8121
7782de3b 8122 intel_disable_fbc(dev);
c65355bb 8123 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8124 mutex_unlock(&dev->struct_mutex);
8125
e5510fac
JB		 8126 trace_i915_flip_request(intel_crtc->plane, obj);
8127
6b95a207 8128 return 0;
96b099fd 8129
8c9f3aaf 8130cleanup_pending:
b4a98e57 8131 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8132 crtc->fb = old_fb;
05394f39
CW		 8133 drm_gem_object_unreference(&work->old_fb_obj->base);
8134 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8135 mutex_unlock(&dev->struct_mutex);
8136
79158103 8137cleanup:
96b099fd
CW		 8138 spin_lock_irqsave(&dev->event_lock, flags);
8139 intel_crtc->unpin_work = NULL;
8140 spin_unlock_irqrestore(&dev->event_lock, flags);
8141
7317c75e
JB		 8142 drm_vblank_put(dev, intel_crtc->pipe);
8143free_work:
96b099fd
CW		 8144 kfree(work);
8145
8146 return ret;
6b95a207
KH		 8147}
8148
f6e5b160 8149static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8150 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8151 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8152};
8153
50f56119
DV		 8154static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8155 struct drm_crtc *crtc)
8156{
8157 struct drm_device *dev;
8158 struct drm_crtc *tmp;
8159 int crtc_mask = 1;
47f1c6c9 8160
50f56119 8161 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8162
50f56119 8163 dev = crtc->dev;
47f1c6c9 8164
50f56119
DV		 8165 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8166 if (tmp == crtc)
8167 break;
8168 crtc_mask <<= 1;
8169 }
47f1c6c9 8170
50f56119
DV		 8171 if (encoder->possible_crtcs & crtc_mask)
8172 return true;
8173 return false;
47f1c6c9 8174}
79e53945 8175
9a935856
DV		 8176/**
8177 * intel_modeset_update_staged_output_state
8178 *
8179 * Updates the staged output configuration state, e.g. after we've read out the
8180 * current hw state.
8181 */
8182static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8183{
9a935856
DV		 8184 struct intel_encoder *encoder;
8185 struct intel_connector *connector;
f6e5b160 8186
9a935856
DV		 8187 list_for_each_entry(connector, &dev->mode_config.connector_list,
8188 base.head) {
8189 connector->new_encoder =
8190 to_intel_encoder(connector->base.encoder);
8191 }
f6e5b160 8192
9a935856
DV		 8193 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8194 base.head) {
8195 encoder->new_crtc =
8196 to_intel_crtc(encoder->base.crtc);
8197 }
f6e5b160
CW		 8198}
8199
9a935856
DV		 8200/**
8201 * intel_modeset_commit_output_state
8202 *
8203 * This function copies the stage display pipe configuration to the real one.
8204 */
8205static void intel_modeset_commit_output_state(struct drm_device *dev)
8206{
8207 struct intel_encoder *encoder;
8208 struct intel_connector *connector;
f6e5b160 8209
9a935856
DV		 8210 list_for_each_entry(connector, &dev->mode_config.connector_list,
8211 base.head) {
8212 connector->base.encoder = &connector->new_encoder->base;
8213 }
f6e5b160 8214
9a935856
DV		 8215 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8216 base.head) {
8217 encoder->base.crtc = &encoder->new_crtc->base;
8218 }
8219}
8220
050f7aeb
DV		 8221static void
8222connected_sink_compute_bpp(struct intel_connector * connector,
8223 struct intel_crtc_config *pipe_config)
8224{
8225 int bpp = pipe_config->pipe_bpp;
8226
8227 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8228 connector->base.base.id,
8229 drm_get_connector_name(&connector->base));
8230
8231 /* Don't use an invalid EDID bpc value */
8232 if (connector->base.display_info.bpc &&
8233 connector->base.display_info.bpc * 3 < bpp) {
8234 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8235 bpp, connector->base.display_info.bpc*3);
8236 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8237 }
8238
8239 /* Clamp bpp to 8 on screens without EDID 1.4 */
8240 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8241 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8242 bpp);
8243 pipe_config->pipe_bpp = 24;
8244 }
8245}
8246
4e53c2e0 8247static int
050f7aeb
DV		 8248compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8249 struct drm_framebuffer *fb,
8250 struct intel_crtc_config *pipe_config)
4e53c2e0 8251{
050f7aeb
DV		 8252 struct drm_device *dev = crtc->base.dev;
8253 struct intel_connector *connector;
4e53c2e0
DV		 8254 int bpp;
8255
d42264b1
DV		 8256 switch (fb->pixel_format) {
8257 case DRM_FORMAT_C8:
4e53c2e0
DV		 8258 bpp = 8*3; /* since we go through a colormap */
8259 break;
d42264b1
DV		 8260 case DRM_FORMAT_XRGB1555:
8261 case DRM_FORMAT_ARGB1555:
8262 /* checked in intel_framebuffer_init already */
8263 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8264 return -EINVAL;
8265 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8266 bpp = 6*3; /* min is 18bpp */
8267 break;
d42264b1
DV		 8268 case DRM_FORMAT_XBGR8888:
8269 case DRM_FORMAT_ABGR8888:
8270 /* checked in intel_framebuffer_init already */
8271 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8272 return -EINVAL;
8273 case DRM_FORMAT_XRGB8888:
8274 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8275 bpp = 8*3;
8276 break;
d42264b1
DV		 8277 case DRM_FORMAT_XRGB2101010:
8278 case DRM_FORMAT_ARGB2101010:
8279 case DRM_FORMAT_XBGR2101010:
8280 case DRM_FORMAT_ABGR2101010:
8281 /* checked in intel_framebuffer_init already */
8282 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8283 return -EINVAL;
4e53c2e0
DV		 8284 bpp = 10*3;
8285 break;
baba133a 8286 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8287 default:
8288 DRM_DEBUG_KMS("unsupported depth\n");
8289 return -EINVAL;
8290 }
8291
4e53c2e0
DV		 8292 pipe_config->pipe_bpp = bpp;
8293
8294 /* Clamp display bpp to EDID value */
8295 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8296 base.head) {
1b829e05
DV		 8297 if (!connector->new_encoder ||
8298 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8299 continue;
8300
050f7aeb 8301 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8302 }
8303
8304 return bpp;
8305}
8306
c0b03411
DV		 8307static void intel_dump_pipe_config(struct intel_crtc *crtc,
8308 struct intel_crtc_config *pipe_config,
8309 const char *context)
8310{
8311 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8312 context, pipe_name(crtc->pipe));
8313
8314 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8315 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8316 pipe_config->pipe_bpp, pipe_config->dither);
8317 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8318 pipe_config->has_pch_encoder,
8319 pipe_config->fdi_lanes,
8320 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8321 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8322 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8323 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8324 pipe_config->has_dp_encoder,
8325 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8326 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8327 pipe_config->dp_m_n.tu);
c0b03411
DV		 8328 DRM_DEBUG_KMS("requested mode:\n");
8329 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8330 DRM_DEBUG_KMS("adjusted mode:\n");
8331 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8332 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8333 pipe_config->gmch_pfit.control,
8334 pipe_config->gmch_pfit.pgm_ratios,
8335 pipe_config->gmch_pfit.lvds_border_bits);
8336 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8337 pipe_config->pch_pfit.pos,
8338 pipe_config->pch_pfit.size);
42db64ef 8339 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8340}
8341
accfc0c5
DV		 8342static bool check_encoder_cloning(struct drm_crtc *crtc)
8343{
8344 int num_encoders = 0;
8345 bool uncloneable_encoders = false;
8346 struct intel_encoder *encoder;
8347
8348 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8349 base.head) {
8350 if (&encoder->new_crtc->base != crtc)
8351 continue;
8352
8353 num_encoders++;
8354 if (!encoder->cloneable)
8355 uncloneable_encoders = true;
8356 }
8357
8358 return !(num_encoders > 1 && uncloneable_encoders);
8359}
8360
b8cecdf5
DV		 8361static struct intel_crtc_config *
8362intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8363 struct drm_framebuffer *fb,
b8cecdf5 8364 struct drm_display_mode *mode)
ee7b9f93 8365{
7758a113 8366 struct drm_device *dev = crtc->dev;
7758a113 8367 struct intel_encoder *encoder;
b8cecdf5 8368 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8369 int plane_bpp, ret = -EINVAL;
8370 bool retry = true;
ee7b9f93 8371
accfc0c5
DV		 8372 if (!check_encoder_cloning(crtc)) {
8373 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8374 return ERR_PTR(-EINVAL);
8375 }
8376
b8cecdf5
DV		 8377 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8378 if (!pipe_config)
7758a113
DV		 8379 return ERR_PTR(-ENOMEM);
8380
b8cecdf5
DV		 8381 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8382 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8383 pipe_config->cpu_transcoder =
8384 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8385 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8386
2960bc9c
ID		 8387 /*
8388 * Sanitize sync polarity flags based on requested ones. If neither
8389 * positive or negative polarity is requested, treat this as meaning
8390 * negative polarity.
8391 */
8392 if (!(pipe_config->adjusted_mode.flags &
8393 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8394 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8395
8396 if (!(pipe_config->adjusted_mode.flags &
8397 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8398 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8399
050f7aeb
DV		 8400 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8401 * plane pixel format and any sink constraints into account. Returns the
8402 * source plane bpp so that dithering can be selected on mismatches
8403 * after encoders and crtc also have had their say. */
8404 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8405 fb, pipe_config);
4e53c2e0
DV		 8406 if (plane_bpp < 0)
8407 goto fail;
8408
e29c22c0 8409encoder_retry:
ef1b460d 8410 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8411 pipe_config->port_clock = 0;
ef1b460d 8412 pipe_config->pixel_multiplier = 1;
ff9a6750 8413
135c81b8
DV		 8414 /* Fill in default crtc timings, allow encoders to overwrite them. */
8415 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8416
7758a113
DV		 8417 /* Pass our mode to the connectors and the CRTC to give them a chance to
8418 * adjust it according to limitations or connector properties, and also
8419 * a chance to reject the mode entirely.
47f1c6c9 8420 */
7758a113
DV		 8421 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8422 base.head) {
47f1c6c9 8423
7758a113
DV		 8424 if (&encoder->new_crtc->base != crtc)
8425 continue;
7ae89233 8426
efea6e8e
DV		 8427 if (!(encoder->compute_config(encoder, pipe_config))) {
8428 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8429 goto fail;
8430 }
ee7b9f93 8431 }
47f1c6c9 8432
ff9a6750
DV		 8433 /* Set default port clock if not overwritten by the encoder. Needs to be
8434 * done afterwards in case the encoder adjusts the mode. */
8435 if (!pipe_config->port_clock)
3c52f4eb
VS		 8436 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8437 pipe_config->pixel_multiplier;
ff9a6750 8438
a43f6e0f 8439 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8440 if (ret < 0) {
7758a113
DV		 8441 DRM_DEBUG_KMS("CRTC fixup failed\n");
8442 goto fail;
ee7b9f93 8443 }
e29c22c0
DV		 8444
8445 if (ret == RETRY) {
8446 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8447 ret = -EINVAL;
8448 goto fail;
8449 }
8450
8451 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8452 retry = false;
8453 goto encoder_retry;
8454 }
8455
4e53c2e0
DV		 8456 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8457 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8458 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8459
b8cecdf5 8460 return pipe_config;
7758a113 8461fail:
b8cecdf5 8462 kfree(pipe_config);
e29c22c0 8463 return ERR_PTR(ret);
ee7b9f93 8464}
47f1c6c9 8465
e2e1ed41
DV		 8466/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8467 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8468static void
8469intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8470 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8471{
8472 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8473 struct drm_device *dev = crtc->dev;
8474 struct intel_encoder *encoder;
8475 struct intel_connector *connector;
8476 struct drm_crtc *tmp_crtc;
79e53945 8477
e2e1ed41 8478 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8479
e2e1ed41
DV		 8480 /* Check which crtcs have changed outputs connected to them, these need
8481 * to be part of the prepare_pipes mask. We don't (yet) support global
8482 * modeset across multiple crtcs, so modeset_pipes will only have one
8483 * bit set at most. */
8484 list_for_each_entry(connector, &dev->mode_config.connector_list,
8485 base.head) {
8486 if (connector->base.encoder == &connector->new_encoder->base)
8487 continue;
79e53945 8488
e2e1ed41
DV		 8489 if (connector->base.encoder) {
8490 tmp_crtc = connector->base.encoder->crtc;
8491
8492 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8493 }
8494
8495 if (connector->new_encoder)
8496 *prepare_pipes |=
8497 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8498 }
8499
e2e1ed41
DV		 8500 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8501 base.head) {
8502 if (encoder->base.crtc == &encoder->new_crtc->base)
8503 continue;
8504
8505 if (encoder->base.crtc) {
8506 tmp_crtc = encoder->base.crtc;
8507
8508 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8509 }
8510
8511 if (encoder->new_crtc)
8512 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8513 }
8514
e2e1ed41
DV		 8515 /* Check for any pipes that will be fully disabled ... */
8516 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8517 base.head) {
8518 bool used = false;
22fd0fab 8519
e2e1ed41
DV		 8520 /* Don't try to disable disabled crtcs. */
8521 if (!intel_crtc->base.enabled)
8522 continue;
7e7d76c3 8523
e2e1ed41
DV		 8524 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8525 base.head) {
8526 if (encoder->new_crtc == intel_crtc)
8527 used = true;
8528 }
8529
8530 if (!used)
8531 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8532 }
8533
e2e1ed41
DV		 8534
8535 /* set_mode is also used to update properties on life display pipes. */
8536 intel_crtc = to_intel_crtc(crtc);
8537 if (crtc->enabled)
8538 *prepare_pipes |= 1 << intel_crtc->pipe;
8539
b6c5164d
DV		 8540 /*
8541 * For simplicity do a full modeset on any pipe where the output routing
8542 * changed. We could be more clever, but that would require us to be
8543 * more careful with calling the relevant encoder->mode_set functions.
8544 */
e2e1ed41
DV		 8545 if (*prepare_pipes)
8546 *modeset_pipes = *prepare_pipes;
8547
8548 /* ... and mask these out. */
8549 *modeset_pipes &= ~(*disable_pipes);
8550 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8551
8552 /*
8553 * HACK: We don't (yet) fully support global modesets. intel_set_config
8554 * obies this rule, but the modeset restore mode of
8555 * intel_modeset_setup_hw_state does not.
8556 */
8557 *modeset_pipes &= 1 << intel_crtc->pipe;
8558 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8559
8560 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8561 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8562}
79e53945 8563
ea9d758d 8564static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8565{
ea9d758d 8566 struct drm_encoder *encoder;
f6e5b160 8567 struct drm_device *dev = crtc->dev;
f6e5b160 8568
ea9d758d
DV		 8569 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8570 if (encoder->crtc == crtc)
8571 return true;
8572
8573 return false;
8574}
8575
8576static void
8577intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8578{
8579 struct intel_encoder *intel_encoder;
8580 struct intel_crtc *intel_crtc;
8581 struct drm_connector *connector;
8582
8583 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8584 base.head) {
8585 if (!intel_encoder->base.crtc)
8586 continue;
8587
8588 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8589
8590 if (prepare_pipes & (1 << intel_crtc->pipe))
8591 intel_encoder->connectors_active = false;
8592 }
8593
8594 intel_modeset_commit_output_state(dev);
8595
8596 /* Update computed state. */
8597 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8598 base.head) {
8599 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8600 }
8601
8602 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8603 if (!connector->encoder || !connector->encoder->crtc)
8604 continue;
8605
8606 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8607
8608 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8609 struct drm_property *dpms_property =
8610 dev->mode_config.dpms_property;
8611
ea9d758d 8612 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8613 drm_object_property_set_value(&connector->base,
68d34720
DV		 8614 dpms_property,
8615 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8616
8617 intel_encoder = to_intel_encoder(connector->encoder);
8618 intel_encoder->connectors_active = true;
8619 }
8620 }
8621
8622}
8623
3bd26263 8624static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8625{
3bd26263 8626 int diff;
f1f644dc
JB		 8627
8628 if (clock1 == clock2)
8629 return true;
8630
8631 if (!clock1 || !clock2)
8632 return false;
8633
8634 diff = abs(clock1 - clock2);
8635
8636 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8637 return true;
8638
8639 return false;
8640}
8641
25c5b266
DV		 8642#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8643 list_for_each_entry((intel_crtc), \
8644 &(dev)->mode_config.crtc_list, \
8645 base.head) \
0973f18f 8646 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8647
0e8ffe1b 8648static bool
2fa2fe9a
DV		 8649intel_pipe_config_compare(struct drm_device *dev,
8650 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8651 struct intel_crtc_config *pipe_config)
8652{
66e985c0
DV		 8653#define PIPE_CONF_CHECK_X(name) \
8654 if (current_config->name != pipe_config->name) { \
8655 DRM_ERROR("mismatch in " #name " " \
8656 "(expected 0x%08x, found 0x%08x)\n", \
8657 current_config->name, \
8658 pipe_config->name); \
8659 return false; \
8660 }
8661
08a24034
DV		 8662#define PIPE_CONF_CHECK_I(name) \
8663 if (current_config->name != pipe_config->name) { \
8664 DRM_ERROR("mismatch in " #name " " \
8665 "(expected %i, found %i)\n", \
8666 current_config->name, \
8667 pipe_config->name); \
8668 return false; \
88adfff1
DV		 8669 }
8670
1bd1bd80
DV		 8671#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8672 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8673 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8674 "(expected %i, found %i)\n", \
8675 current_config->name & (mask), \
8676 pipe_config->name & (mask)); \
8677 return false; \
8678 }
8679
bb760063
DV		 8680#define PIPE_CONF_QUIRK(quirk) \
8681 ((current_config->quirks | pipe_config->quirks) & (quirk))
8682
eccb140b
DV		 8683 PIPE_CONF_CHECK_I(cpu_transcoder);
8684
08a24034
DV		 8685 PIPE_CONF_CHECK_I(has_pch_encoder);
8686 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8687 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8688 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8689 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8690 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8691 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8692
eb14cb74
VS		 8693 PIPE_CONF_CHECK_I(has_dp_encoder);
8694 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8695 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8696 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8697 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8698 PIPE_CONF_CHECK_I(dp_m_n.tu);
8699
1bd1bd80
DV		 8700 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8701 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8702 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8703 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8704 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8705 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8706
8707 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8708 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8709 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8710 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8711 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8713
c93f54cf 8714 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8715
1bd1bd80
DV		 8716 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8717 DRM_MODE_FLAG_INTERLACE);
8718
bb760063
DV		 8719 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8720 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8721 DRM_MODE_FLAG_PHSYNC);
8722 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8723 DRM_MODE_FLAG_NHSYNC);
8724 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8725 DRM_MODE_FLAG_PVSYNC);
8726 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8727 DRM_MODE_FLAG_NVSYNC);
8728 }
045ac3b5 8729
1bd1bd80
DV		 8730 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8731 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8732
2fa2fe9a
DV		 8733 PIPE_CONF_CHECK_I(gmch_pfit.control);
8734 /* pfit ratios are autocomputed by the hw on gen4+ */
8735 if (INTEL_INFO(dev)->gen < 4)
8736 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8737 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8738 PIPE_CONF_CHECK_I(pch_pfit.pos);
8739 PIPE_CONF_CHECK_I(pch_pfit.size);
8740
42db64ef
PZ		 8741 PIPE_CONF_CHECK_I(ips_enabled);
8742
c0d43d62 8743 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8744 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8745 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8746 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8747 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8748
42571aef
VS		 8749 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8750 PIPE_CONF_CHECK_I(pipe_bpp);
8751
66e985c0 8752#undef PIPE_CONF_CHECK_X
08a24034 8753#undef PIPE_CONF_CHECK_I
1bd1bd80 8754#undef PIPE_CONF_CHECK_FLAGS
bb760063 8755#undef PIPE_CONF_QUIRK
88adfff1 8756
f1f644dc 8757 if (!IS_HASWELL(dev)) {
3bd26263
VS		 8758 if (!intel_fuzzy_clock_check(current_config->adjusted_mode.clock,
8759 pipe_config->adjusted_mode.clock)) {
6f02488e 8760 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8761 current_config->adjusted_mode.clock,
8762 pipe_config->adjusted_mode.clock);
8763 return false;
8764 }
8765 }
8766
0e8ffe1b
DV		 8767 return true;
8768}
8769
91d1b4bd
DV		 8770static void
8771check_connector_state(struct drm_device *dev)
8af6cf88 8772{
8af6cf88
DV		 8773 struct intel_connector *connector;
8774
8775 list_for_each_entry(connector, &dev->mode_config.connector_list,
8776 base.head) {
8777 /* This also checks the encoder/connector hw state with the
8778 * ->get_hw_state callbacks. */
8779 intel_connector_check_state(connector);
8780
8781 WARN(&connector->new_encoder->base != connector->base.encoder,
8782 "connector's staged encoder doesn't match current encoder\n");
8783 }
91d1b4bd
DV		 8784}
8785
8786static void
8787check_encoder_state(struct drm_device *dev)
8788{
8789 struct intel_encoder *encoder;
8790 struct intel_connector *connector;
8af6cf88
DV		 8791
8792 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8793 base.head) {
8794 bool enabled = false;
8795 bool active = false;
8796 enum pipe pipe, tracked_pipe;
8797
8798 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8799 encoder->base.base.id,
8800 drm_get_encoder_name(&encoder->base));
8801
8802 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8803 "encoder's stage crtc doesn't match current crtc\n");
8804 WARN(encoder->connectors_active && !encoder->base.crtc,
8805 "encoder's active_connectors set, but no crtc\n");
8806
8807 list_for_each_entry(connector, &dev->mode_config.connector_list,
8808 base.head) {
8809 if (connector->base.encoder != &encoder->base)
8810 continue;
8811 enabled = true;
8812 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8813 active = true;
8814 }
8815 WARN(!!encoder->base.crtc != enabled,
8816 "encoder's enabled state mismatch "
8817 "(expected %i, found %i)\n",
8818 !!encoder->base.crtc, enabled);
8819 WARN(active && !encoder->base.crtc,
8820 "active encoder with no crtc\n");
8821
8822 WARN(encoder->connectors_active != active,
8823 "encoder's computed active state doesn't match tracked active state "
8824 "(expected %i, found %i)\n", active, encoder->connectors_active);
8825
8826 active = encoder->get_hw_state(encoder, &pipe);
8827 WARN(active != encoder->connectors_active,
8828 "encoder's hw state doesn't match sw tracking "
8829 "(expected %i, found %i)\n",
8830 encoder->connectors_active, active);
8831
8832 if (!encoder->base.crtc)
8833 continue;
8834
8835 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8836 WARN(active && pipe != tracked_pipe,
8837 "active encoder's pipe doesn't match"
8838 "(expected %i, found %i)\n",
8839 tracked_pipe, pipe);
8840
8841 }
91d1b4bd
DV		 8842}
8843
8844static void
8845check_crtc_state(struct drm_device *dev)
8846{
8847 drm_i915_private_t *dev_priv = dev->dev_private;
8848 struct intel_crtc *crtc;
8849 struct intel_encoder *encoder;
8850 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8851
8852 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8853 base.head) {
8854 bool enabled = false;
8855 bool active = false;
8856
045ac3b5
JB		 8857 memset(&pipe_config, 0, sizeof(pipe_config));
8858
8af6cf88
DV		 8859 DRM_DEBUG_KMS("[CRTC:%d]\n",
8860 crtc->base.base.id);
8861
8862 WARN(crtc->active && !crtc->base.enabled,
8863 "active crtc, but not enabled in sw tracking\n");
8864
8865 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8866 base.head) {
8867 if (encoder->base.crtc != &crtc->base)
8868 continue;
8869 enabled = true;
8870 if (encoder->connectors_active)
8871 active = true;
8872 }
6c49f241 8873
8af6cf88
DV		 8874 WARN(active != crtc->active,
8875 "crtc's computed active state doesn't match tracked active state "
8876 "(expected %i, found %i)\n", active, crtc->active);
8877 WARN(enabled != crtc->base.enabled,
8878 "crtc's computed enabled state doesn't match tracked enabled state "
8879 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8880
0e8ffe1b
DV		 8881 active = dev_priv->display.get_pipe_config(crtc,
8882 &pipe_config);
d62cf62a
DV		 8883
8884 /* hw state is inconsistent with the pipe A quirk */
8885 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8886 active = crtc->active;
8887
6c49f241
DV		 8888 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8889 base.head) {
3eaba51c 8890 enum pipe pipe;
6c49f241
DV		 8891 if (encoder->base.crtc != &crtc->base)
8892 continue;
3eaba51c
VS		 8893 if (encoder->get_config &&
8894 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8895 encoder->get_config(encoder, &pipe_config);
8896 }
8897
510d5f2f
JB		 8898 if (dev_priv->display.get_clock)
8899 dev_priv->display.get_clock(crtc, &pipe_config);
8900
0e8ffe1b
DV		 8901 WARN(crtc->active != active,
8902 "crtc active state doesn't match with hw state "
8903 "(expected %i, found %i)\n", crtc->active, active);
8904
c0b03411
DV		 8905 if (active &&
8906 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8907 WARN(1, "pipe state doesn't match!\n");
8908 intel_dump_pipe_config(crtc, &pipe_config,
8909 "[hw state]");
8910 intel_dump_pipe_config(crtc, &crtc->config,
8911 "[sw state]");
8912 }
8af6cf88
DV		 8913 }
8914}
8915
91d1b4bd
DV		 8916static void
8917check_shared_dpll_state(struct drm_device *dev)
8918{
8919 drm_i915_private_t *dev_priv = dev->dev_private;
8920 struct intel_crtc *crtc;
8921 struct intel_dpll_hw_state dpll_hw_state;
8922 int i;
5358901f
DV		 8923
8924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8925 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8926 int enabled_crtcs = 0, active_crtcs = 0;
8927 bool active;
8928
8929 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8930
8931 DRM_DEBUG_KMS("%s\n", pll->name);
8932
8933 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8934
8935 WARN(pll->active > pll->refcount,
8936 "more active pll users than references: %i vs %i\n",
8937 pll->active, pll->refcount);
8938 WARN(pll->active && !pll->on,
8939 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8940 WARN(pll->on && !pll->active,
8941 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8942 WARN(pll->on != active,
8943 "pll on state mismatch (expected %i, found %i)\n",
8944 pll->on, active);
8945
8946 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8947 base.head) {
8948 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8949 enabled_crtcs++;
8950 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8951 active_crtcs++;
8952 }
8953 WARN(pll->active != active_crtcs,
8954 "pll active crtcs mismatch (expected %i, found %i)\n",
8955 pll->active, active_crtcs);
8956 WARN(pll->refcount != enabled_crtcs,
8957 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8958 pll->refcount, enabled_crtcs);
66e985c0
DV		 8959
8960 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8961 sizeof(dpll_hw_state)),
8962 "pll hw state mismatch\n");
5358901f 8963 }
8af6cf88
DV		 8964}
8965
91d1b4bd
DV		 8966void
8967intel_modeset_check_state(struct drm_device *dev)
8968{
8969 check_connector_state(dev);
8970 check_encoder_state(dev);
8971 check_crtc_state(dev);
8972 check_shared_dpll_state(dev);
8973}
8974
f30da187
DV		 8975static int __intel_set_mode(struct drm_crtc *crtc,
8976 struct drm_display_mode *mode,
8977 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8978{
8979 struct drm_device *dev = crtc->dev;
dbf2b54e 8980 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8981 struct drm_display_mode *saved_mode, *saved_hwmode;
8982 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8983 struct intel_crtc *intel_crtc;
8984 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8985 int ret = 0;
a6778b3c 8986
3ac18232 8987 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8988 if (!saved_mode)
8989 return -ENOMEM;
3ac18232 8990 saved_hwmode = saved_mode + 1;
a6778b3c 8991
e2e1ed41 8992 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8993 &prepare_pipes, &disable_pipes);
8994
3ac18232
TG		 8995 *saved_hwmode = crtc->hwmode;
8996 *saved_mode = crtc->mode;
a6778b3c 8997
25c5b266
DV		 8998 /* Hack: Because we don't (yet) support global modeset on multiple
8999 * crtcs, we don't keep track of the new mode for more than one crtc.
9000 * Hence simply check whether any bit is set in modeset_pipes in all the
9001 * pieces of code that are not yet converted to deal with mutliple crtcs
9002 * changing their mode at the same time. */
25c5b266 9003 if (modeset_pipes) {
4e53c2e0 9004 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9005 if (IS_ERR(pipe_config)) {
9006 ret = PTR_ERR(pipe_config);
9007 pipe_config = NULL;
9008
3ac18232 9009 goto out;
25c5b266 9010 }
c0b03411
DV		 9011 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9012 "[modeset]");
25c5b266 9013 }
a6778b3c 9014
460da916
DV		 9015 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9016 intel_crtc_disable(&intel_crtc->base);
9017
ea9d758d
DV		 9018 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9019 if (intel_crtc->base.enabled)
9020 dev_priv->display.crtc_disable(&intel_crtc->base);
9021 }
a6778b3c 9022
6c4c86f5
DV		 9023 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9024 * to set it here already despite that we pass it down the callchain.
f6e5b160 9025 */
b8cecdf5 9026 if (modeset_pipes) {
25c5b266 9027 crtc->mode = *mode;
b8cecdf5
DV		 9028 /* mode_set/enable/disable functions rely on a correct pipe
9029 * config. */
9030 to_intel_crtc(crtc)->config = *pipe_config;
9031 }
7758a113 9032
ea9d758d
DV		 9033 /* Only after disabling all output pipelines that will be changed can we
9034 * update the the output configuration. */
9035 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9036
47fab737
DV		 9037 if (dev_priv->display.modeset_global_resources)
9038 dev_priv->display.modeset_global_resources(dev);
9039
a6778b3c
DV		 9040 /* Set up the DPLL and any encoders state that needs to adjust or depend
9041 * on the DPLL.
f6e5b160 9042 */
25c5b266 9043 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9044 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9045 x, y, fb);
9046 if (ret)
9047 goto done;
a6778b3c
DV		 9048 }
9049
9050 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9051 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9052 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9053
25c5b266
DV		 9054 if (modeset_pipes) {
9055 /* Store real post-adjustment hardware mode. */
b8cecdf5 9056 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9057
25c5b266
DV		 9058 /* Calculate and store various constants which
9059 * are later needed by vblank and swap-completion
9060 * timestamping. They are derived from true hwmode.
9061 */
9062 drm_calc_timestamping_constants(crtc);
9063 }
a6778b3c
DV		 9064
9065 /* FIXME: add subpixel order */
9066done:
c0c36b94 9067 if (ret && crtc->enabled) {
3ac18232
TG		 9068 crtc->hwmode = *saved_hwmode;
9069 crtc->mode = *saved_mode;
a6778b3c
DV		 9070 }
9071
3ac18232 9072out:
b8cecdf5 9073 kfree(pipe_config);
3ac18232 9074 kfree(saved_mode);
a6778b3c 9075 return ret;
f6e5b160
CW		 9076}
9077
e7457a9a
DL		 9078static int intel_set_mode(struct drm_crtc *crtc,
9079 struct drm_display_mode *mode,
9080 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9081{
9082 int ret;
9083
9084 ret = __intel_set_mode(crtc, mode, x, y, fb);
9085
9086 if (ret == 0)
9087 intel_modeset_check_state(crtc->dev);
9088
9089 return ret;
9090}
9091
c0c36b94
CW		 9092void intel_crtc_restore_mode(struct drm_crtc *crtc)
9093{
9094 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9095}
9096
25c5b266
DV		 9097#undef for_each_intel_crtc_masked
9098
d9e55608
DV		 9099static void intel_set_config_free(struct intel_set_config *config)
9100{
9101 if (!config)
9102 return;
9103
1aa4b628
DV		 9104 kfree(config->save_connector_encoders);
9105 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9106 kfree(config);
9107}
9108
85f9eb71
DV		 9109static int intel_set_config_save_state(struct drm_device *dev,
9110 struct intel_set_config *config)
9111{
85f9eb71
DV		 9112 struct drm_encoder *encoder;
9113 struct drm_connector *connector;
9114 int count;
9115
1aa4b628
DV		 9116 config->save_encoder_crtcs =
9117 kcalloc(dev->mode_config.num_encoder,
9118 sizeof(struct drm_crtc *), GFP_KERNEL);
9119 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9120 return -ENOMEM;
9121
1aa4b628
DV		 9122 config->save_connector_encoders =
9123 kcalloc(dev->mode_config.num_connector,
9124 sizeof(struct drm_encoder *), GFP_KERNEL);
9125 if (!config->save_connector_encoders)
85f9eb71
DV		 9126 return -ENOMEM;
9127
9128 /* Copy data. Note that driver private data is not affected.
9129 * Should anything bad happen only the expected state is
9130 * restored, not the drivers personal bookkeeping.
9131 */
85f9eb71
DV		 9132 count = 0;
9133 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9134 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9135 }
9136
9137 count = 0;
9138 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9139 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9140 }
9141
9142 return 0;
9143}
9144
9145static void intel_set_config_restore_state(struct drm_device *dev,
9146 struct intel_set_config *config)
9147{
9a935856
DV		 9148 struct intel_encoder *encoder;
9149 struct intel_connector *connector;
85f9eb71
DV		 9150 int count;
9151
85f9eb71 9152 count = 0;
9a935856
DV		 9153 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9154 encoder->new_crtc =
9155 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9156 }
9157
9158 count = 0;
9a935856
DV		 9159 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9160 connector->new_encoder =
9161 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9162 }
9163}
9164
e3de42b6 9165static bool
2e57f47d 9166is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9167{
9168 int i;
9169
2e57f47d
CW		 9170 if (set->num_connectors == 0)
9171 return false;
9172
9173 if (WARN_ON(set->connectors == NULL))
9174 return false;
9175
9176 for (i = 0; i < set->num_connectors; i++)
9177 if (set->connectors[i]->encoder &&
9178 set->connectors[i]->encoder->crtc == set->crtc &&
9179 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9180 return true;
9181
9182 return false;
9183}
9184
5e2b584e
DV		 9185static void
9186intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9187 struct intel_set_config *config)
9188{
9189
9190 /* We should be able to check here if the fb has the same properties
9191 * and then just flip_or_move it */
2e57f47d
CW		 9192 if (is_crtc_connector_off(set)) {
9193 config->mode_changed = true;
e3de42b6 9194 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9195 /* If we have no fb then treat it as a full mode set */
9196 if (set->crtc->fb == NULL) {
319d9827
JB		 9197 struct intel_crtc *intel_crtc =
9198 to_intel_crtc(set->crtc);
9199
9200 if (intel_crtc->active && i915_fastboot) {
9201 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9202 config->fb_changed = true;
9203 } else {
9204 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9205 config->mode_changed = true;
9206 }
5e2b584e
DV		 9207 } else if (set->fb == NULL) {
9208 config->mode_changed = true;
72f4901e
DV		 9209 } else if (set->fb->pixel_format !=
9210 set->crtc->fb->pixel_format) {
5e2b584e 9211 config->mode_changed = true;
e3de42b6 9212 } else {
5e2b584e 9213 config->fb_changed = true;
e3de42b6 9214 }
5e2b584e
DV		 9215 }
9216
835c5873 9217 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9218 config->fb_changed = true;
9219
9220 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9221 DRM_DEBUG_KMS("modes are different, full mode set\n");
9222 drm_mode_debug_printmodeline(&set->crtc->mode);
9223 drm_mode_debug_printmodeline(set->mode);
9224 config->mode_changed = true;
9225 }
a1d95703
CW		 9226
9227 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9228 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9229}
9230
2e431051 9231static int
9a935856
DV		 9232intel_modeset_stage_output_state(struct drm_device *dev,
9233 struct drm_mode_set *set,
9234 struct intel_set_config *config)
50f56119 9235{
85f9eb71 9236 struct drm_crtc *new_crtc;
9a935856
DV		 9237 struct intel_connector *connector;
9238 struct intel_encoder *encoder;
f3f08572 9239 int ro;
50f56119 9240
9abdda74 9241 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9242 * of connectors. For paranoia, double-check this. */
9243 WARN_ON(!set->fb && (set->num_connectors != 0));
9244 WARN_ON(set->fb && (set->num_connectors == 0));
9245
9a935856
DV		 9246 list_for_each_entry(connector, &dev->mode_config.connector_list,
9247 base.head) {
9248 /* Otherwise traverse passed in connector list and get encoders
9249 * for them. */
50f56119 9250 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9251 if (set->connectors[ro] == &connector->base) {
9252 connector->new_encoder = connector->encoder;
50f56119
DV		 9253 break;
9254 }
9255 }
9256
9a935856
DV		 9257 /* If we disable the crtc, disable all its connectors. Also, if
9258 * the connector is on the changing crtc but not on the new
9259 * connector list, disable it. */
9260 if ((!set->fb || ro == set->num_connectors) &&
9261 connector->base.encoder &&
9262 connector->base.encoder->crtc == set->crtc) {
9263 connector->new_encoder = NULL;
9264
9265 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9266 connector->base.base.id,
9267 drm_get_connector_name(&connector->base));
9268 }
9269
9270
9271 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9272 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9273 config->mode_changed = true;
50f56119
DV		 9274 }
9275 }
9a935856 9276 /* connector->new_encoder is now updated for all connectors. */
50f56119 9277
9a935856 9278 /* Update crtc of enabled connectors. */
9a935856
DV		 9279 list_for_each_entry(connector, &dev->mode_config.connector_list,
9280 base.head) {
9281 if (!connector->new_encoder)
50f56119
DV		 9282 continue;
9283
9a935856 9284 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9285
9286 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9287 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9288 new_crtc = set->crtc;
9289 }
9290
9291 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9292 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9293 new_crtc)) {
5e2b584e 9294 return -EINVAL;
50f56119 9295 }
9a935856
DV		 9296 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9297
9298 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9299 connector->base.base.id,
9300 drm_get_connector_name(&connector->base),
9301 new_crtc->base.id);
9302 }
9303
9304 /* Check for any encoders that needs to be disabled. */
9305 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9306 base.head) {
9307 list_for_each_entry(connector,
9308 &dev->mode_config.connector_list,
9309 base.head) {
9310 if (connector->new_encoder == encoder) {
9311 WARN_ON(!connector->new_encoder->new_crtc);
9312
9313 goto next_encoder;
9314 }
9315 }
9316 encoder->new_crtc = NULL;
9317next_encoder:
9318 /* Only now check for crtc changes so we don't miss encoders
9319 * that will be disabled. */
9320 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9321 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9322 config->mode_changed = true;
50f56119
DV		 9323 }
9324 }
9a935856 9325 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9326
2e431051
DV		 9327 return 0;
9328}
9329
9330static int intel_crtc_set_config(struct drm_mode_set *set)
9331{
9332 struct drm_device *dev;
2e431051
DV		 9333 struct drm_mode_set save_set;
9334 struct intel_set_config *config;
9335 int ret;
2e431051 9336
8d3e375e
DV		 9337 BUG_ON(!set);
9338 BUG_ON(!set->crtc);
9339 BUG_ON(!set->crtc->helper_private);
2e431051 9340
7e53f3a4
DV		 9341 /* Enforce sane interface api - has been abused by the fb helper. */
9342 BUG_ON(!set->mode && set->fb);
9343 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9344
2e431051
DV		 9345 if (set->fb) {
9346 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9347 set->crtc->base.id, set->fb->base.id,
9348 (int)set->num_connectors, set->x, set->y);
9349 } else {
9350 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9351 }
9352
9353 dev = set->crtc->dev;
9354
9355 ret = -ENOMEM;
9356 config = kzalloc(sizeof(*config), GFP_KERNEL);
9357 if (!config)
9358 goto out_config;
9359
9360 ret = intel_set_config_save_state(dev, config);
9361 if (ret)
9362 goto out_config;
9363
9364 save_set.crtc = set->crtc;
9365 save_set.mode = &set->crtc->mode;
9366 save_set.x = set->crtc->x;
9367 save_set.y = set->crtc->y;
9368 save_set.fb = set->crtc->fb;
9369
9370 /* Compute whether we need a full modeset, only an fb base update or no
9371 * change at all. In the future we might also check whether only the
9372 * mode changed, e.g. for LVDS where we only change the panel fitter in
9373 * such cases. */
9374 intel_set_config_compute_mode_changes(set, config);
9375
9a935856 9376 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9377 if (ret)
9378 goto fail;
9379
5e2b584e 9380 if (config->mode_changed) {
c0c36b94
CW		 9381 ret = intel_set_mode(set->crtc, set->mode,
9382 set->x, set->y, set->fb);
5e2b584e 9383 } else if (config->fb_changed) {
4878cae2
VS		 9384 intel_crtc_wait_for_pending_flips(set->crtc);
9385
4f660f49 9386 ret = intel_pipe_set_base(set->crtc,
94352cf9 9387 set->x, set->y, set->fb);
50f56119
DV		 9388 }
9389
2d05eae1 9390 if (ret) {
bf67dfeb
DV		 9391 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9392 set->crtc->base.id, ret);
50f56119 9393fail:
2d05eae1 9394 intel_set_config_restore_state(dev, config);
50f56119 9395
2d05eae1
CW		 9396 /* Try to restore the config */
9397 if (config->mode_changed &&
9398 intel_set_mode(save_set.crtc, save_set.mode,
9399 save_set.x, save_set.y, save_set.fb))
9400 DRM_ERROR("failed to restore config after modeset failure\n");
9401 }
50f56119 9402
d9e55608
DV		 9403out_config:
9404 intel_set_config_free(config);
50f56119
DV		 9405 return ret;
9406}
f6e5b160
CW		 9407
9408static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9409 .cursor_set = intel_crtc_cursor_set,
9410 .cursor_move = intel_crtc_cursor_move,
9411 .gamma_set = intel_crtc_gamma_set,
50f56119 9412 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9413 .destroy = intel_crtc_destroy,
9414 .page_flip = intel_crtc_page_flip,
9415};
9416
79f689aa
PZ		 9417static void intel_cpu_pll_init(struct drm_device *dev)
9418{
affa9354 9419 if (HAS_DDI(dev))
79f689aa
PZ		 9420 intel_ddi_pll_init(dev);
9421}
9422
5358901f
DV		 9423static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9424 struct intel_shared_dpll *pll,
9425 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9426{
5358901f 9427 uint32_t val;
ee7b9f93 9428
5358901f 9429 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9430 hw_state->dpll = val;
9431 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9432 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9433
9434 return val & DPLL_VCO_ENABLE;
9435}
9436
15bdd4cf
DV		 9437static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9438 struct intel_shared_dpll *pll)
9439{
9440 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9441 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9442}
9443
e7b903d2
DV		 9444static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9445 struct intel_shared_dpll *pll)
9446{
e7b903d2
DV		 9447 /* PCH refclock must be enabled first */
9448 assert_pch_refclk_enabled(dev_priv);
9449
15bdd4cf
DV		 9450 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9451
9452 /* Wait for the clocks to stabilize. */
9453 POSTING_READ(PCH_DPLL(pll->id));
9454 udelay(150);
9455
9456 /* The pixel multiplier can only be updated once the
9457 * DPLL is enabled and the clocks are stable.
9458 *
9459 * So write it again.
9460 */
9461 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9462 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9463 udelay(200);
9464}
9465
9466static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9467 struct intel_shared_dpll *pll)
9468{
9469 struct drm_device *dev = dev_priv->dev;
9470 struct intel_crtc *crtc;
e7b903d2
DV		 9471
9472 /* Make sure no transcoder isn't still depending on us. */
9473 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9474 if (intel_crtc_to_shared_dpll(crtc) == pll)
9475 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9476 }
9477
15bdd4cf
DV		 9478 I915_WRITE(PCH_DPLL(pll->id), 0);
9479 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9480 udelay(200);
9481}
9482
46edb027
DV		 9483static char *ibx_pch_dpll_names[] = {
9484 "PCH DPLL A",
9485 "PCH DPLL B",
9486};
9487
7c74ade1 9488static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9489{
e7b903d2 9490 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9491 int i;
9492
7c74ade1 9493 dev_priv->num_shared_dpll = 2;
ee7b9f93 9494
e72f9fbf 9495 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9496 dev_priv->shared_dplls[i].id = i;
9497 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9498 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9499 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9500 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9501 dev_priv->shared_dplls[i].get_hw_state =
9502 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9503 }
9504}
9505
7c74ade1
DV		 9506static void intel_shared_dpll_init(struct drm_device *dev)
9507{
e7b903d2 9508 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9509
9510 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9511 ibx_pch_dpll_init(dev);
9512 else
9513 dev_priv->num_shared_dpll = 0;
9514
9515 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9516 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9517 dev_priv->num_shared_dpll);
9518}
9519
b358d0a6 9520static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9521{
22fd0fab 9522 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9523 struct intel_crtc *intel_crtc;
9524 int i;
9525
9526 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9527 if (intel_crtc == NULL)
9528 return;
9529
9530 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9531
9532 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9533 for (i = 0; i < 256; i++) {
9534 intel_crtc->lut_r[i] = i;
9535 intel_crtc->lut_g[i] = i;
9536 intel_crtc->lut_b[i] = i;
9537 }
9538
80824003
JB		 9539 /* Swap pipes & planes for FBC on pre-965 */
9540 intel_crtc->pipe = pipe;
9541 intel_crtc->plane = pipe;
e2e767ab 9542 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9543 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9544 intel_crtc->plane = !pipe;
80824003
JB		 9545 }
9546
22fd0fab
JB		 9547 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9548 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9549 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9550 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9551
79e53945 9552 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9553}
9554
08d7b3d1 9555int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9556 struct drm_file *file)
08d7b3d1 9557{
08d7b3d1 9558 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9559 struct drm_mode_object *drmmode_obj;
9560 struct intel_crtc *crtc;
08d7b3d1 9561
1cff8f6b
DV		 9562 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9563 return -ENODEV;
08d7b3d1 9564
c05422d5
DV		 9565 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9566 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9567
c05422d5 9568 if (!drmmode_obj) {
08d7b3d1
CW		 9569 DRM_ERROR("no such CRTC id\n");
9570 return -EINVAL;
9571 }
9572
c05422d5
DV		 9573 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9574 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9575
c05422d5 9576 return 0;
08d7b3d1
CW		 9577}
9578
66a9278e 9579static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9580{
66a9278e
DV		 9581 struct drm_device *dev = encoder->base.dev;
9582 struct intel_encoder *source_encoder;
79e53945 9583 int index_mask = 0;
79e53945
JB		 9584 int entry = 0;
9585
66a9278e
DV		 9586 list_for_each_entry(source_encoder,
9587 &dev->mode_config.encoder_list, base.head) {
9588
9589 if (encoder == source_encoder)
79e53945 9590 index_mask |= (1 << entry);
66a9278e
DV		 9591
9592 /* Intel hw has only one MUX where enocoders could be cloned. */
9593 if (encoder->cloneable && source_encoder->cloneable)
9594 index_mask |= (1 << entry);
9595
79e53945
JB		 9596 entry++;
9597 }
4ef69c7a 9598
79e53945
JB		 9599 return index_mask;
9600}
9601
4d302442
CW		 9602static bool has_edp_a(struct drm_device *dev)
9603{
9604 struct drm_i915_private *dev_priv = dev->dev_private;
9605
9606 if (!IS_MOBILE(dev))
9607 return false;
9608
9609 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9610 return false;
9611
9612 if (IS_GEN5(dev) &&
9613 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9614 return false;
9615
9616 return true;
9617}
9618
79e53945
JB		 9619static void intel_setup_outputs(struct drm_device *dev)
9620{
725e30ad 9621 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9622 struct intel_encoder *encoder;
cb0953d7 9623 bool dpd_is_edp = false;
79e53945 9624
c9093354 9625 intel_lvds_init(dev);
79e53945 9626
c40c0f5b 9627 if (!IS_ULT(dev))
79935fca 9628 intel_crt_init(dev);
cb0953d7 9629
affa9354 9630 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9631 int found;
9632
9633 /* Haswell uses DDI functions to detect digital outputs */
9634 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9635 /* DDI A only supports eDP */
9636 if (found)
9637 intel_ddi_init(dev, PORT_A);
9638
9639 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9640 * register */
9641 found = I915_READ(SFUSE_STRAP);
9642
9643 if (found & SFUSE_STRAP_DDIB_DETECTED)
9644 intel_ddi_init(dev, PORT_B);
9645 if (found & SFUSE_STRAP_DDIC_DETECTED)
9646 intel_ddi_init(dev, PORT_C);
9647 if (found & SFUSE_STRAP_DDID_DETECTED)
9648 intel_ddi_init(dev, PORT_D);
9649 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9650 int found;
270b3042
DV		 9651 dpd_is_edp = intel_dpd_is_edp(dev);
9652
9653 if (has_edp_a(dev))
9654 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9655
dc0fa718 9656 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9657 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9658 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9659 if (!found)
e2debe91 9660 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9661 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9662 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9663 }
9664
dc0fa718 9665 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9666 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9667
dc0fa718 9668 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9669 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9670
5eb08b69 9671 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9672 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9673
270b3042 9674 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9675 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9676 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9677 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9678 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9679 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9680 PORT_C);
9681 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9682 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9683 PORT_C);
9684 }
19c03924 9685
dc0fa718 9686 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9687 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9688 PORT_B);
67cfc203
VS		 9689 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9690 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9691 }
3cfca973
JN		 9692
9693 intel_dsi_init(dev);
103a196f 9694 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9695 bool found = false;
7d57382e 9696
e2debe91 9697 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9698 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9699 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9700 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9701 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9702 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9703 }
27185ae1 9704
e7281eab 9705 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9706 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9707 }
13520b05
KH		 9708
9709 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9710
e2debe91 9711 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9712 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9713 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9714 }
27185ae1 9715
e2debe91 9716 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9717
b01f2c3a
JB		 9718 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9719 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9720 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9721 }
e7281eab 9722 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9723 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9724 }
27185ae1 9725
b01f2c3a 9726 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9727 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9728 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9729 } else if (IS_GEN2(dev))
79e53945
JB		 9730 intel_dvo_init(dev);
9731
103a196f 9732 if (SUPPORTS_TV(dev))
79e53945
JB		 9733 intel_tv_init(dev);
9734
4ef69c7a
CW		 9735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9736 encoder->base.possible_crtcs = encoder->crtc_mask;
9737 encoder->base.possible_clones =
66a9278e 9738 intel_encoder_clones(encoder);
79e53945 9739 }
47356eb6 9740
dde86e2d 9741 intel_init_pch_refclk(dev);
270b3042
DV		 9742
9743 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9744}
9745
ddfe1567
CW		 9746void intel_framebuffer_fini(struct intel_framebuffer *fb)
9747{
9748 drm_framebuffer_cleanup(&fb->base);
9749 drm_gem_object_unreference_unlocked(&fb->obj->base);
9750}
9751
79e53945
JB		 9752static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9753{
9754 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9755
ddfe1567 9756 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9757 kfree(intel_fb);
9758}
9759
9760static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9761 struct drm_file *file,
79e53945
JB		 9762 unsigned int *handle)
9763{
9764 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9765 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9766
05394f39 9767 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9768}
9769
9770static const struct drm_framebuffer_funcs intel_fb_funcs = {
9771 .destroy = intel_user_framebuffer_destroy,
9772 .create_handle = intel_user_framebuffer_create_handle,
9773};
9774
38651674
DA		 9775int intel_framebuffer_init(struct drm_device *dev,
9776 struct intel_framebuffer *intel_fb,
308e5bcb 9777 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9778 struct drm_i915_gem_object *obj)
79e53945 9779{
a35cdaa0 9780 int pitch_limit;
79e53945
JB		 9781 int ret;
9782
c16ed4be
CW		 9783 if (obj->tiling_mode == I915_TILING_Y) {
9784 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9785 return -EINVAL;
c16ed4be 9786 }
57cd6508 9787
c16ed4be
CW		 9788 if (mode_cmd->pitches[0] & 63) {
9789 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9790 mode_cmd->pitches[0]);
57cd6508 9791 return -EINVAL;
c16ed4be 9792 }
57cd6508 9793
a35cdaa0
CW		 9794 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9795 pitch_limit = 32*1024;
9796 } else if (INTEL_INFO(dev)->gen >= 4) {
9797 if (obj->tiling_mode)
9798 pitch_limit = 16*1024;
9799 else
9800 pitch_limit = 32*1024;
9801 } else if (INTEL_INFO(dev)->gen >= 3) {
9802 if (obj->tiling_mode)
9803 pitch_limit = 8*1024;
9804 else
9805 pitch_limit = 16*1024;
9806 } else
9807 /* XXX DSPC is limited to 4k tiled */
9808 pitch_limit = 8*1024;
9809
9810 if (mode_cmd->pitches[0] > pitch_limit) {
9811 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9812 obj->tiling_mode ? "tiled" : "linear",
9813 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9814 return -EINVAL;
c16ed4be 9815 }
5d7bd705
VS		 9816
9817 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9818 mode_cmd->pitches[0] != obj->stride) {
9819 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9820 mode_cmd->pitches[0], obj->stride);
5d7bd705 9821 return -EINVAL;
c16ed4be 9822 }
5d7bd705 9823
57779d06 9824 /* Reject formats not supported by any plane early. */
308e5bcb 9825 switch (mode_cmd->pixel_format) {
57779d06 9826 case DRM_FORMAT_C8:
04b3924d
VS		 9827 case DRM_FORMAT_RGB565:
9828 case DRM_FORMAT_XRGB8888:
9829 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9830 break;
9831 case DRM_FORMAT_XRGB1555:
9832 case DRM_FORMAT_ARGB1555:
c16ed4be 9833 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9834 DRM_DEBUG("unsupported pixel format: %s\n",
9835 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9836 return -EINVAL;
c16ed4be 9837 }
57779d06
VS		 9838 break;
9839 case DRM_FORMAT_XBGR8888:
9840 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9841 case DRM_FORMAT_XRGB2101010:
9842 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9843 case DRM_FORMAT_XBGR2101010:
9844 case DRM_FORMAT_ABGR2101010:
c16ed4be 9845 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9846 DRM_DEBUG("unsupported pixel format: %s\n",
9847 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9848 return -EINVAL;
c16ed4be 9849 }
b5626747 9850 break;
04b3924d
VS		 9851 case DRM_FORMAT_YUYV:
9852 case DRM_FORMAT_UYVY:
9853 case DRM_FORMAT_YVYU:
9854 case DRM_FORMAT_VYUY:
c16ed4be 9855 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9856 DRM_DEBUG("unsupported pixel format: %s\n",
9857 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9858 return -EINVAL;
c16ed4be 9859 }
57cd6508
CW		 9860 break;
9861 default:
4ee62c76
VS		 9862 DRM_DEBUG("unsupported pixel format: %s\n",
9863 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9864 return -EINVAL;
9865 }
9866
90f9a336
VS		 9867 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9868 if (mode_cmd->offsets[0] != 0)
9869 return -EINVAL;
9870
c7d73f6a
DV		 9871 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9872 intel_fb->obj = obj;
9873
79e53945
JB		 9874 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9875 if (ret) {
9876 DRM_ERROR("framebuffer init failed %d\n", ret);
9877 return ret;
9878 }
9879
79e53945
JB		 9880 return 0;
9881}
9882
79e53945
JB		 9883static struct drm_framebuffer *
9884intel_user_framebuffer_create(struct drm_device *dev,
9885 struct drm_file *filp,
308e5bcb 9886 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9887{
05394f39 9888 struct drm_i915_gem_object *obj;
79e53945 9889
308e5bcb
JB		 9890 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9891 mode_cmd->handles[0]));
c8725226 9892 if (&obj->base == NULL)
cce13ff7 9893 return ERR_PTR(-ENOENT);
79e53945 9894
d2dff872 9895 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9896}
9897
79e53945 9898static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9899 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9900 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9901};
9902
e70236a8
JB		 9903/* Set up chip specific display functions */
9904static void intel_init_display(struct drm_device *dev)
9905{
9906 struct drm_i915_private *dev_priv = dev->dev_private;
9907
ee9300bb
DV		 9908 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9909 dev_priv->display.find_dpll = g4x_find_best_dpll;
9910 else if (IS_VALLEYVIEW(dev))
9911 dev_priv->display.find_dpll = vlv_find_best_dpll;
9912 else if (IS_PINEVIEW(dev))
9913 dev_priv->display.find_dpll = pnv_find_best_dpll;
9914 else
9915 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9916
affa9354 9917 if (HAS_DDI(dev)) {
0e8ffe1b 9918 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9919 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9920 dev_priv->display.crtc_enable = haswell_crtc_enable;
9921 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9922 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9923 dev_priv->display.update_plane = ironlake_update_plane;
9924 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9925 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9926 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9927 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9928 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9929 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9930 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9931 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9932 } else if (IS_VALLEYVIEW(dev)) {
9933 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9934 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9935 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9936 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9937 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9938 dev_priv->display.off = i9xx_crtc_off;
9939 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9940 } else {
0e8ffe1b 9941 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9942 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9943 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9944 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9945 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9946 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9947 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9948 }
e70236a8 9949
e70236a8 9950 /* Returns the core display clock speed */
25eb05fc
JB		 9951 if (IS_VALLEYVIEW(dev))
9952 dev_priv->display.get_display_clock_speed =
9953 valleyview_get_display_clock_speed;
9954 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9955 dev_priv->display.get_display_clock_speed =
9956 i945_get_display_clock_speed;
9957 else if (IS_I915G(dev))
9958 dev_priv->display.get_display_clock_speed =
9959 i915_get_display_clock_speed;
257a7ffc 9960 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9961 dev_priv->display.get_display_clock_speed =
9962 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9963 else if (IS_PINEVIEW(dev))
9964 dev_priv->display.get_display_clock_speed =
9965 pnv_get_display_clock_speed;
e70236a8
JB		 9966 else if (IS_I915GM(dev))
9967 dev_priv->display.get_display_clock_speed =
9968 i915gm_get_display_clock_speed;
9969 else if (IS_I865G(dev))
9970 dev_priv->display.get_display_clock_speed =
9971 i865_get_display_clock_speed;
f0f8a9ce 9972 else if (IS_I85X(dev))
e70236a8
JB		 9973 dev_priv->display.get_display_clock_speed =
9974 i855_get_display_clock_speed;
9975 else /* 852, 830 */
9976 dev_priv->display.get_display_clock_speed =
9977 i830_get_display_clock_speed;
9978
7f8a8569 9979 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9980 if (IS_GEN5(dev)) {
674cf967 9981 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9982 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9983 } else if (IS_GEN6(dev)) {
674cf967 9984 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9985 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9986 } else if (IS_IVYBRIDGE(dev)) {
9987 /* FIXME: detect B0+ stepping and use auto training */
9988 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9989 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9990 dev_priv->display.modeset_global_resources =
9991 ivb_modeset_global_resources;
c82e4d26
ED		 9992 } else if (IS_HASWELL(dev)) {
9993 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9994 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9995 dev_priv->display.modeset_global_resources =
9996 haswell_modeset_global_resources;
a0e63c22 9997 }
6067aaea 9998 } else if (IS_G4X(dev)) {
e0dac65e 9999 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10000 }
8c9f3aaf
JB		 10001
10002 /* Default just returns -ENODEV to indicate unsupported */
10003 dev_priv->display.queue_flip = intel_default_queue_flip;
10004
10005 switch (INTEL_INFO(dev)->gen) {
10006 case 2:
10007 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10008 break;
10009
10010 case 3:
10011 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10012 break;
10013
10014 case 4:
10015 case 5:
10016 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10017 break;
10018
10019 case 6:
10020 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10021 break;
7c9017e5
JB		 10022 case 7:
10023 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10024 break;
8c9f3aaf 10025 }
e70236a8
JB		 10026}
10027
b690e96c
JB		 10028/*
10029 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10030 * resume, or other times. This quirk makes sure that's the case for
10031 * affected systems.
10032 */
0206e353 10033static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10034{
10035 struct drm_i915_private *dev_priv = dev->dev_private;
10036
10037 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10038 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10039}
10040
435793df
KP		 10041/*
10042 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10043 */
10044static void quirk_ssc_force_disable(struct drm_device *dev)
10045{
10046 struct drm_i915_private *dev_priv = dev->dev_private;
10047 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10048 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10049}
10050
4dca20ef 10051/*
5a15ab5b
CE		 10052 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10053 * brightness value
4dca20ef
CE		 10054 */
10055static void quirk_invert_brightness(struct drm_device *dev)
10056{
10057 struct drm_i915_private *dev_priv = dev->dev_private;
10058 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10059 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10060}
10061
e85843be
KM		 10062/*
10063 * Some machines (Dell XPS13) suffer broken backlight controls if
10064 * BLM_PCH_PWM_ENABLE is set.
10065 */
10066static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10067{
10068 struct drm_i915_private *dev_priv = dev->dev_private;
10069 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10070 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10071}
10072
b690e96c
JB		 10073struct intel_quirk {
10074 int device;
10075 int subsystem_vendor;
10076 int subsystem_device;
10077 void (*hook)(struct drm_device *dev);
10078};
10079
5f85f176
EE		 10080/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10081struct intel_dmi_quirk {
10082 void (*hook)(struct drm_device *dev);
10083 const struct dmi_system_id (*dmi_id_list)[];
10084};
10085
10086static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10087{
10088 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10089 return 1;
10090}
10091
10092static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10093 {
10094 .dmi_id_list = &(const struct dmi_system_id[]) {
10095 {
10096 .callback = intel_dmi_reverse_brightness,
10097 .ident = "NCR Corporation",
10098 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10099 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10100 },
10101 },
10102 { } /* terminating entry */
10103 },
10104 .hook = quirk_invert_brightness,
10105 },
10106};
10107
c43b5634 10108static struct intel_quirk intel_quirks[] = {
b690e96c 10109 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10110 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10111
b690e96c
JB		 10112 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10113 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10114
b690e96c
JB		 10115 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10116 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10117
ccd0d36e 10118 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10119 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10120 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10121
10122 /* Lenovo U160 cannot use SSC on LVDS */
10123 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10124
10125 /* Sony Vaio Y cannot use SSC on LVDS */
10126 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10127
10128 /* Acer Aspire 5734Z must invert backlight brightness */
10129 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10130
10131 /* Acer/eMachines G725 */
10132 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10133
10134 /* Acer/eMachines e725 */
10135 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10136
10137 /* Acer/Packard Bell NCL20 */
10138 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10139
10140 /* Acer Aspire 4736Z */
10141 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10142
10143 /* Dell XPS13 HD Sandy Bridge */
10144 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10145 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10146 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10147};
10148
10149static void intel_init_quirks(struct drm_device *dev)
10150{
10151 struct pci_dev *d = dev->pdev;
10152 int i;
10153
10154 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10155 struct intel_quirk *q = &intel_quirks[i];
10156
10157 if (d->device == q->device &&
10158 (d->subsystem_vendor == q->subsystem_vendor ||
10159 q->subsystem_vendor == PCI_ANY_ID) &&
10160 (d->subsystem_device == q->subsystem_device ||
10161 q->subsystem_device == PCI_ANY_ID))
10162 q->hook(dev);
10163 }
5f85f176
EE		 10164 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10165 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10166 intel_dmi_quirks[i].hook(dev);
10167 }
b690e96c
JB		 10168}
10169
9cce37f4
JB		 10170/* Disable the VGA plane that we never use */
10171static void i915_disable_vga(struct drm_device *dev)
10172{
10173 struct drm_i915_private *dev_priv = dev->dev_private;
10174 u8 sr1;
766aa1c4 10175 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10176
10177 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10178 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10179 sr1 = inb(VGA_SR_DATA);
10180 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10181
10182 /* Disable VGA memory on Intel HD */
10183 if (HAS_PCH_SPLIT(dev)) {
10184 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10185 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10186 VGA_RSRC_NORMAL_IO |
10187 VGA_RSRC_NORMAL_MEM);
10188 }
10189
9cce37f4
JB		 10190 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10191 udelay(300);
10192
10193 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10194 POSTING_READ(vga_reg);
10195}
10196
81b5c7bc
AW		 10197static void i915_enable_vga(struct drm_device *dev)
10198{
10199 /* Enable VGA memory on Intel HD */
10200 if (HAS_PCH_SPLIT(dev)) {
10201 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10202 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10203 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10204 VGA_RSRC_LEGACY_MEM |
10205 VGA_RSRC_NORMAL_IO |
10206 VGA_RSRC_NORMAL_MEM);
10207 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10208 }
10209}
10210
f817586c
DV		 10211void intel_modeset_init_hw(struct drm_device *dev)
10212{
fa42e23c 10213 intel_init_power_well(dev);
0232e927 10214
a8f78b58
ED		 10215 intel_prepare_ddi(dev);
10216
f817586c
DV		 10217 intel_init_clock_gating(dev);
10218
79f5b2c7 10219 mutex_lock(&dev->struct_mutex);
8090c6b9 10220 intel_enable_gt_powersave(dev);
79f5b2c7 10221 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10222}
10223
7d708ee4
ID		 10224void intel_modeset_suspend_hw(struct drm_device *dev)
10225{
10226 intel_suspend_hw(dev);
10227}
10228
79e53945
JB		 10229void intel_modeset_init(struct drm_device *dev)
10230{
652c393a 10231 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10232 int i, j, ret;
79e53945
JB		 10233
10234 drm_mode_config_init(dev);
10235
10236 dev->mode_config.min_width = 0;
10237 dev->mode_config.min_height = 0;
10238
019d96cb
DA		 10239 dev->mode_config.preferred_depth = 24;
10240 dev->mode_config.prefer_shadow = 1;
10241
e6ecefaa 10242 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10243
b690e96c
JB		 10244 intel_init_quirks(dev);
10245
1fa61106
ED		 10246 intel_init_pm(dev);
10247
e3c74757
BW		 10248 if (INTEL_INFO(dev)->num_pipes == 0)
10249 return;
10250
e70236a8
JB		 10251 intel_init_display(dev);
10252
a6c45cf0
CW		 10253 if (IS_GEN2(dev)) {
10254 dev->mode_config.max_width = 2048;
10255 dev->mode_config.max_height = 2048;
10256 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10257 dev->mode_config.max_width = 4096;
10258 dev->mode_config.max_height = 4096;
79e53945 10259 } else {
a6c45cf0
CW		 10260 dev->mode_config.max_width = 8192;
10261 dev->mode_config.max_height = 8192;
79e53945 10262 }
5d4545ae 10263 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10264
28c97730 10265 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10266 INTEL_INFO(dev)->num_pipes,
10267 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10268
08e2a7de 10269 for_each_pipe(i) {
79e53945 10270 intel_crtc_init(dev, i);
7f1f3851
JB		 10271 for (j = 0; j < dev_priv->num_plane; j++) {
10272 ret = intel_plane_init(dev, i, j);
10273 if (ret)
06da8da2
VS		 10274 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10275 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10276 }
79e53945
JB		 10277 }
10278
79f689aa 10279 intel_cpu_pll_init(dev);
e72f9fbf 10280 intel_shared_dpll_init(dev);
ee7b9f93 10281
9cce37f4
JB		 10282 /* Just disable it once at startup */
10283 i915_disable_vga(dev);
79e53945 10284 intel_setup_outputs(dev);
11be49eb
CW		 10285
10286 /* Just in case the BIOS is doing something questionable. */
10287 intel_disable_fbc(dev);
2c7111db
CW		 10288}
10289
24929352
DV		 10290static void
10291intel_connector_break_all_links(struct intel_connector *connector)
10292{
10293 connector->base.dpms = DRM_MODE_DPMS_OFF;
10294 connector->base.encoder = NULL;
10295 connector->encoder->connectors_active = false;
10296 connector->encoder->base.crtc = NULL;
10297}
10298
7fad798e
DV		 10299static void intel_enable_pipe_a(struct drm_device *dev)
10300{
10301 struct intel_connector *connector;
10302 struct drm_connector *crt = NULL;
10303 struct intel_load_detect_pipe load_detect_temp;
10304
10305 /* We can't just switch on the pipe A, we need to set things up with a
10306 * proper mode and output configuration. As a gross hack, enable pipe A
10307 * by enabling the load detect pipe once. */
10308 list_for_each_entry(connector,
10309 &dev->mode_config.connector_list,
10310 base.head) {
10311 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10312 crt = &connector->base;
10313 break;
10314 }
10315 }
10316
10317 if (!crt)
10318 return;
10319
10320 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10321 intel_release_load_detect_pipe(crt, &load_detect_temp);
10322
652c393a 10323
7fad798e
DV		 10324}
10325
fa555837
DV		 10326static bool
10327intel_check_plane_mapping(struct intel_crtc *crtc)
10328{
7eb552ae
BW		 10329 struct drm_device *dev = crtc->base.dev;
10330 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10331 u32 reg, val;
10332
7eb552ae 10333 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10334 return true;
10335
10336 reg = DSPCNTR(!crtc->plane);
10337 val = I915_READ(reg);
10338
10339 if ((val & DISPLAY_PLANE_ENABLE) &&
10340 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10341 return false;
10342
10343 return true;
10344}
10345
24929352
DV		 10346static void intel_sanitize_crtc(struct intel_crtc *crtc)
10347{
10348 struct drm_device *dev = crtc->base.dev;
10349 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10350 u32 reg;
24929352 10351
24929352 10352 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10353 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10354 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10355
10356 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10357 * disable the crtc (and hence change the state) if it is wrong. Note
10358 * that gen4+ has a fixed plane -> pipe mapping. */
10359 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10360 struct intel_connector *connector;
10361 bool plane;
10362
24929352
DV		 10363 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10364 crtc->base.base.id);
10365
10366 /* Pipe has the wrong plane attached and the plane is active.
10367 * Temporarily change the plane mapping and disable everything
10368 * ... */
10369 plane = crtc->plane;
10370 crtc->plane = !plane;
10371 dev_priv->display.crtc_disable(&crtc->base);
10372 crtc->plane = plane;
10373
10374 /* ... and break all links. */
10375 list_for_each_entry(connector, &dev->mode_config.connector_list,
10376 base.head) {
10377 if (connector->encoder->base.crtc != &crtc->base)
10378 continue;
10379
10380 intel_connector_break_all_links(connector);
10381 }
10382
10383 WARN_ON(crtc->active);
10384 crtc->base.enabled = false;
10385 }
24929352 10386
7fad798e
DV		 10387 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10388 crtc->pipe == PIPE_A && !crtc->active) {
10389 /* BIOS forgot to enable pipe A, this mostly happens after
10390 * resume. Force-enable the pipe to fix this, the update_dpms
10391 * call below we restore the pipe to the right state, but leave
10392 * the required bits on. */
10393 intel_enable_pipe_a(dev);
10394 }
10395
24929352
DV		 10396 /* Adjust the state of the output pipe according to whether we
10397 * have active connectors/encoders. */
10398 intel_crtc_update_dpms(&crtc->base);
10399
10400 if (crtc->active != crtc->base.enabled) {
10401 struct intel_encoder *encoder;
10402
10403 /* This can happen either due to bugs in the get_hw_state
10404 * functions or because the pipe is force-enabled due to the
10405 * pipe A quirk. */
10406 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10407 crtc->base.base.id,
10408 crtc->base.enabled ? "enabled" : "disabled",
10409 crtc->active ? "enabled" : "disabled");
10410
10411 crtc->base.enabled = crtc->active;
10412
10413 /* Because we only establish the connector -> encoder ->
10414 * crtc links if something is active, this means the
10415 * crtc is now deactivated. Break the links. connector
10416 * -> encoder links are only establish when things are
10417 * actually up, hence no need to break them. */
10418 WARN_ON(crtc->active);
10419
10420 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10421 WARN_ON(encoder->connectors_active);
10422 encoder->base.crtc = NULL;
10423 }
10424 }
10425}
10426
10427static void intel_sanitize_encoder(struct intel_encoder *encoder)
10428{
10429 struct intel_connector *connector;
10430 struct drm_device *dev = encoder->base.dev;
10431
10432 /* We need to check both for a crtc link (meaning that the
10433 * encoder is active and trying to read from a pipe) and the
10434 * pipe itself being active. */
10435 bool has_active_crtc = encoder->base.crtc &&
10436 to_intel_crtc(encoder->base.crtc)->active;
10437
10438 if (encoder->connectors_active && !has_active_crtc) {
10439 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10440 encoder->base.base.id,
10441 drm_get_encoder_name(&encoder->base));
10442
10443 /* Connector is active, but has no active pipe. This is
10444 * fallout from our resume register restoring. Disable
10445 * the encoder manually again. */
10446 if (encoder->base.crtc) {
10447 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10448 encoder->base.base.id,
10449 drm_get_encoder_name(&encoder->base));
10450 encoder->disable(encoder);
10451 }
10452
10453 /* Inconsistent output/port/pipe state happens presumably due to
10454 * a bug in one of the get_hw_state functions. Or someplace else
10455 * in our code, like the register restore mess on resume. Clamp
10456 * things to off as a safer default. */
10457 list_for_each_entry(connector,
10458 &dev->mode_config.connector_list,
10459 base.head) {
10460 if (connector->encoder != encoder)
10461 continue;
10462
10463 intel_connector_break_all_links(connector);
10464 }
10465 }
10466 /* Enabled encoders without active connectors will be fixed in
10467 * the crtc fixup. */
10468}
10469
44cec740 10470void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10471{
10472 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10473 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10474
8dc8a27c
PZ		 10475 /* This function can be called both from intel_modeset_setup_hw_state or
10476 * at a very early point in our resume sequence, where the power well
10477 * structures are not yet restored. Since this function is at a very
10478 * paranoid "someone might have enabled VGA while we were not looking"
10479 * level, just check if the power well is enabled instead of trying to
10480 * follow the "don't touch the power well if we don't need it" policy
10481 * the rest of the driver uses. */
10482 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10483 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10484 return;
10485
0fde901f
KM		 10486 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10487 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10488 i915_disable_vga(dev);
0fde901f
KM		 10489 }
10490}
10491
30e984df 10492static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10493{
10494 struct drm_i915_private *dev_priv = dev->dev_private;
10495 enum pipe pipe;
24929352
DV		 10496 struct intel_crtc *crtc;
10497 struct intel_encoder *encoder;
10498 struct intel_connector *connector;
5358901f 10499 int i;
24929352 10500
0e8ffe1b
DV		 10501 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10502 base.head) {
88adfff1 10503 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10504
0e8ffe1b
DV		 10505 crtc->active = dev_priv->display.get_pipe_config(crtc,
10506 &crtc->config);
24929352
DV		 10507
10508 crtc->base.enabled = crtc->active;
10509
10510 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10511 crtc->base.base.id,
10512 crtc->active ? "enabled" : "disabled");
10513 }
10514
5358901f 10515 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10516 if (HAS_DDI(dev))
6441ab5f
PZ		 10517 intel_ddi_setup_hw_pll_state(dev);
10518
5358901f
DV		 10519 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10520 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10521
10522 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10523 pll->active = 0;
10524 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10525 base.head) {
10526 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10527 pll->active++;
10528 }
10529 pll->refcount = pll->active;
10530
35c95375
DV		 10531 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10532 pll->name, pll->refcount, pll->on);
5358901f
DV		 10533 }
10534
24929352
DV		 10535 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10536 base.head) {
10537 pipe = 0;
10538
10539 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10540 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10541 encoder->base.crtc = &crtc->base;
510d5f2f 10542 if (encoder->get_config)
045ac3b5 10543 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10544 } else {
10545 encoder->base.crtc = NULL;
10546 }
10547
10548 encoder->connectors_active = false;
10549 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10550 encoder->base.base.id,
10551 drm_get_encoder_name(&encoder->base),
10552 encoder->base.crtc ? "enabled" : "disabled",
10553 pipe);
10554 }
10555
510d5f2f
JB		 10556 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10557 base.head) {
10558 if (!crtc->active)
10559 continue;
10560 if (dev_priv->display.get_clock)
10561 dev_priv->display.get_clock(crtc,
10562 &crtc->config);
10563 }
10564
24929352
DV		 10565 list_for_each_entry(connector, &dev->mode_config.connector_list,
10566 base.head) {
10567 if (connector->get_hw_state(connector)) {
10568 connector->base.dpms = DRM_MODE_DPMS_ON;
10569 connector->encoder->connectors_active = true;
10570 connector->base.encoder = &connector->encoder->base;
10571 } else {
10572 connector->base.dpms = DRM_MODE_DPMS_OFF;
10573 connector->base.encoder = NULL;
10574 }
10575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10576 connector->base.base.id,
10577 drm_get_connector_name(&connector->base),
10578 connector->base.encoder ? "enabled" : "disabled");
10579 }
30e984df
DV		 10580}
10581
10582/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10583 * and i915 state tracking structures. */
10584void intel_modeset_setup_hw_state(struct drm_device *dev,
10585 bool force_restore)
10586{
10587 struct drm_i915_private *dev_priv = dev->dev_private;
10588 enum pipe pipe;
10589 struct drm_plane *plane;
10590 struct intel_crtc *crtc;
10591 struct intel_encoder *encoder;
35c95375 10592 int i;
30e984df
DV		 10593
10594 intel_modeset_readout_hw_state(dev);
24929352 10595
babea61d
JB		 10596 /*
10597 * Now that we have the config, copy it to each CRTC struct
10598 * Note that this could go away if we move to using crtc_config
10599 * checking everywhere.
10600 */
10601 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10602 base.head) {
10603 if (crtc->active && i915_fastboot) {
10604 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10605
10606 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10607 crtc->base.base.id);
10608 drm_mode_debug_printmodeline(&crtc->base.mode);
10609 }
10610 }
10611
24929352
DV		 10612 /* HW state is read out, now we need to sanitize this mess. */
10613 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10614 base.head) {
10615 intel_sanitize_encoder(encoder);
10616 }
10617
10618 for_each_pipe(pipe) {
10619 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10620 intel_sanitize_crtc(crtc);
c0b03411 10621 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10622 }
9a935856 10623
35c95375
DV		 10624 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10625 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10626
10627 if (!pll->on || pll->active)
10628 continue;
10629
10630 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10631
10632 pll->disable(dev_priv, pll);
10633 pll->on = false;
10634 }
10635
45e2b5f6 10636 if (force_restore) {
f30da187
DV		 10637 /*
10638 * We need to use raw interfaces for restoring state to avoid
10639 * checking (bogus) intermediate states.
10640 */
45e2b5f6 10641 for_each_pipe(pipe) {
b5644d05
JB		 10642 struct drm_crtc *crtc =
10643 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10644
10645 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10646 crtc->fb);
45e2b5f6 10647 }
b5644d05
JB		 10648 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10649 intel_plane_restore(plane);
0fde901f
KM		 10650
10651 i915_redisable_vga(dev);
45e2b5f6
DV		 10652 } else {
10653 intel_modeset_update_staged_output_state(dev);
10654 }
8af6cf88
DV		 10655
10656 intel_modeset_check_state(dev);
2e938892
DV		 10657
10658 drm_mode_config_reset(dev);
2c7111db
CW		 10659}
10660
10661void intel_modeset_gem_init(struct drm_device *dev)
10662{
1833b134 10663 intel_modeset_init_hw(dev);
02e792fb
DV		 10664
10665 intel_setup_overlay(dev);
24929352 10666
45e2b5f6 10667 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10668}
10669
10670void intel_modeset_cleanup(struct drm_device *dev)
10671{
652c393a
JB		 10672 struct drm_i915_private *dev_priv = dev->dev_private;
10673 struct drm_crtc *crtc;
652c393a 10674
fd0c0642
DV		 10675 /*
10676 * Interrupts and polling as the first thing to avoid creating havoc.
10677 * Too much stuff here (turning of rps, connectors, ...) would
10678 * experience fancy races otherwise.
10679 */
10680 drm_irq_uninstall(dev);
10681 cancel_work_sync(&dev_priv->hotplug_work);
10682 /*
10683 * Due to the hpd irq storm handling the hotplug work can re-arm the
10684 * poll handlers. Hence disable polling after hpd handling is shut down.
10685 */
f87ea761 10686 drm_kms_helper_poll_fini(dev);
fd0c0642 10687
652c393a
JB		 10688 mutex_lock(&dev->struct_mutex);
10689
723bfd70
JB		 10690 intel_unregister_dsm_handler();
10691
652c393a
JB		 10692 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10693 /* Skip inactive CRTCs */
10694 if (!crtc->fb)
10695 continue;
10696
3dec0095 10697 intel_increase_pllclock(crtc);
652c393a
JB		 10698 }
10699
973d04f9 10700 intel_disable_fbc(dev);
e70236a8 10701
81b5c7bc
AW		 10702 i915_enable_vga(dev);
10703
8090c6b9 10704 intel_disable_gt_powersave(dev);
0cdab21f 10705
930ebb46
DV		 10706 ironlake_teardown_rc6(dev);
10707
69341a5e
KH		 10708 mutex_unlock(&dev->struct_mutex);
10709
1630fe75
CW		 10710 /* flush any delayed tasks or pending work */
10711 flush_scheduled_work();
10712
dc652f90
JN		 10713 /* destroy backlight, if any, before the connectors */
10714 intel_panel_destroy_backlight(dev);
10715
79e53945 10716 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10717
10718 intel_cleanup_overlay(dev);
79e53945
JB		 10719}
10720
f1c79df3
ZW		 10721/*
10722 * Return which encoder is currently attached for connector.
10723 */
df0e9248 10724struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10725{
df0e9248
CW		 10726 return &intel_attached_encoder(connector)->base;
10727}
f1c79df3 10728
df0e9248
CW		 10729void intel_connector_attach_encoder(struct intel_connector *connector,
10730 struct intel_encoder *encoder)
10731{
10732 connector->encoder = encoder;
10733 drm_mode_connector_attach_encoder(&connector->base,
10734 &encoder->base);
79e53945 10735}
28d52043
DA		 10736
10737/*
10738 * set vga decode state - true == enable VGA decode
10739 */
10740int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10741{
10742 struct drm_i915_private *dev_priv = dev->dev_private;
10743 u16 gmch_ctrl;
10744
10745 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10746 if (state)
10747 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10748 else
10749 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10750 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10751 return 0;
10752}
c4a1d9e4 10753
c4a1d9e4 10754struct intel_display_error_state {
ff57f1b0
PZ		 10755
10756 u32 power_well_driver;
10757
63b66e5b
CW		 10758 int num_transcoders;
10759
c4a1d9e4
CW		 10760 struct intel_cursor_error_state {
10761 u32 control;
10762 u32 position;
10763 u32 base;
10764 u32 size;
52331309 10765 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10766
10767 struct intel_pipe_error_state {
c4a1d9e4 10768 u32 source;
52331309 10769 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10770
10771 struct intel_plane_error_state {
10772 u32 control;
10773 u32 stride;
10774 u32 size;
10775 u32 pos;
10776 u32 addr;
10777 u32 surface;
10778 u32 tile_offset;
52331309 10779 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10780
10781 struct intel_transcoder_error_state {
10782 enum transcoder cpu_transcoder;
10783
10784 u32 conf;
10785
10786 u32 htotal;
10787 u32 hblank;
10788 u32 hsync;
10789 u32 vtotal;
10790 u32 vblank;
10791 u32 vsync;
10792 } transcoder[4];
c4a1d9e4
CW		 10793};
10794
10795struct intel_display_error_state *
10796intel_display_capture_error_state(struct drm_device *dev)
10797{
0206e353 10798 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10799 struct intel_display_error_state *error;
63b66e5b
CW		 10800 int transcoders[] = {
10801 TRANSCODER_A,
10802 TRANSCODER_B,
10803 TRANSCODER_C,
10804 TRANSCODER_EDP,
10805 };
c4a1d9e4
CW		 10806 int i;
10807
63b66e5b
CW		 10808 if (INTEL_INFO(dev)->num_pipes == 0)
10809 return NULL;
10810
c4a1d9e4
CW		 10811 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10812 if (error == NULL)
10813 return NULL;
10814
ff57f1b0
PZ		 10815 if (HAS_POWER_WELL(dev))
10816 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10817
52331309 10818 for_each_pipe(i) {
a18c4c3d
PZ		 10819 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10820 error->cursor[i].control = I915_READ(CURCNTR(i));
10821 error->cursor[i].position = I915_READ(CURPOS(i));
10822 error->cursor[i].base = I915_READ(CURBASE(i));
10823 } else {
10824 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10825 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10826 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10827 }
c4a1d9e4
CW		 10828
10829 error->plane[i].control = I915_READ(DSPCNTR(i));
10830 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10831 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10832 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10833 error->plane[i].pos = I915_READ(DSPPOS(i));
10834 }
ca291363
PZ		 10835 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10836 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10837 if (INTEL_INFO(dev)->gen >= 4) {
10838 error->plane[i].surface = I915_READ(DSPSURF(i));
10839 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10840 }
10841
c4a1d9e4 10842 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10843 }
10844
10845 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10846 if (HAS_DDI(dev_priv->dev))
10847 error->num_transcoders++; /* Account for eDP. */
10848
10849 for (i = 0; i < error->num_transcoders; i++) {
10850 enum transcoder cpu_transcoder = transcoders[i];
10851
10852 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10853
10854 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10855 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10856 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10857 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10858 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10859 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10860 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10861 }
10862
12d217c7
PZ		 10863 /* In the code above we read the registers without checking if the power
10864 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10865 * prevent the next I915_WRITE from detecting it and printing an error
10866 * message. */
907b28c5 10867 intel_uncore_clear_errors(dev);
12d217c7 10868
c4a1d9e4
CW		 10869 return error;
10870}
10871
edc3d884
MK		 10872#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10873
c4a1d9e4 10874void
edc3d884 10875intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10876 struct drm_device *dev,
10877 struct intel_display_error_state *error)
10878{
10879 int i;
10880
63b66e5b
CW		 10881 if (!error)
10882 return;
10883
edc3d884 10884 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10885 if (HAS_POWER_WELL(dev))
edc3d884 10886 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10887 error->power_well_driver);
52331309 10888 for_each_pipe(i) {
edc3d884 10889 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10890 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10891
10892 err_printf(m, "Plane [%d]:\n", i);
10893 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10894 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10895 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10896 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10897 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10898 }
4b71a570 10899 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10900 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10901 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10902 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10903 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10904 }
10905
edc3d884
MK		 10906 err_printf(m, "Cursor [%d]:\n", i);
10907 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10908 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10909 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10910 }
63b66e5b
CW		 10911
10912 for (i = 0; i < error->num_transcoders; i++) {
10913 err_printf(m, " CPU transcoder: %c\n",
10914 transcoder_name(error->transcoder[i].cpu_transcoder));
10915 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10916 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10917 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10918 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10919 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10920 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10921 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10922 }
c4a1d9e4 10923}
Linux kernel - Deliverables
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