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drm/i915: scrap register address storage
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
926 struct intel_crtc *crtc,
927 bool state)
040484af 928{
040484af
JB		 929 u32 val;
930 bool cur_state;
931
9d82aa17
ED		 932 if (HAS_PCH_LPT(dev_priv->dev)) {
933 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
934 return;
935 }
936
92b27b08 937 if (WARN (!pll,
46edb027 938 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 939 return;
ee7b9f93 940
e9a632a5 941 val = I915_READ(PCH_DPLL(pll->id));
92b27b08
CW		 942 cur_state = !!(val & DPLL_VCO_ENABLE);
943 WARN(cur_state != state,
46edb027
DV		 944 "%s assertion failure (expected %s, current %s), val=%08x\n",
945 pll->name, state_string(state), state_string(cur_state), val);
92b27b08
CW		 946
947 /* Make sure the selected PLL is correctly attached to the transcoder */
948 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 949 u32 pch_dpll;
950
951 pch_dpll = I915_READ(PCH_DPLL_SEL);
e9a632a5 952 cur_state = pll->id == DPLL_ID_PCH_PLL_B;
92b27b08 953 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 954 "PLL[%d] not attached to this transcoder %c: %08x\n",
955 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 956 cur_state = !!(val >> (4*crtc->pipe + 3));
957 WARN(cur_state != state,
4bb6f1f3 958 "PLL[%d] not %s on this transcoder %c: %08x\n",
e9a632a5 959 pll->id == DPLL_ID_PCH_PLL_B,
92b27b08 960 state_string(state),
4bb6f1f3 961 pipe_name(crtc->pipe),
92b27b08
CW		 962 val);
963 }
d3ccbe86 964 }
040484af 965}
e72f9fbf
DV		 966#define assert_shared_dpll_enabled(d, p, c) assert_shared_dpll(d, p, c, true)
967#define assert_shared_dpll_disabled(d, p, c) assert_shared_dpll(d, p, c, false)
040484af
JB		 968
969static void assert_fdi_tx(struct drm_i915_private *dev_priv,
970 enum pipe pipe, bool state)
971{
972 int reg;
973 u32 val;
974 bool cur_state;
ad80a810
PZ		 975 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
976 pipe);
040484af 977
affa9354
PZ		 978 if (HAS_DDI(dev_priv->dev)) {
979 /* DDI does not have a specific FDI_TX register */
ad80a810 980 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 981 val = I915_READ(reg);
ad80a810 982 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 983 } else {
984 reg = FDI_TX_CTL(pipe);
985 val = I915_READ(reg);
986 cur_state = !!(val & FDI_TX_ENABLE);
987 }
040484af
JB		 988 WARN(cur_state != state,
989 "FDI TX state assertion failure (expected %s, current %s)\n",
990 state_string(state), state_string(cur_state));
991}
992#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
993#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
994
995static void assert_fdi_rx(struct drm_i915_private *dev_priv,
996 enum pipe pipe, bool state)
997{
998 int reg;
999 u32 val;
1000 bool cur_state;
1001
d63fa0dc
PZ		 1002 reg = FDI_RX_CTL(pipe);
1003 val = I915_READ(reg);
1004 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1005 WARN(cur_state != state,
1006 "FDI RX state assertion failure (expected %s, current %s)\n",
1007 state_string(state), state_string(cur_state));
1008}
1009#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1010#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1011
1012static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1013 enum pipe pipe)
1014{
1015 int reg;
1016 u32 val;
1017
1018 /* ILK FDI PLL is always enabled */
1019 if (dev_priv->info->gen == 5)
1020 return;
1021
bf507ef7 1022 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1023 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1024 return;
1025
040484af
JB		 1026 reg = FDI_TX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1029}
1030
1031static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int reg;
1035 u32 val;
1036
1037 reg = FDI_RX_CTL(pipe);
1038 val = I915_READ(reg);
1039 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1040}
1041
ea0760cf
JB		 1042static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1043 enum pipe pipe)
1044{
1045 int pp_reg, lvds_reg;
1046 u32 val;
1047 enum pipe panel_pipe = PIPE_A;
0de3b485 1048 bool locked = true;
ea0760cf
JB		 1049
1050 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1051 pp_reg = PCH_PP_CONTROL;
1052 lvds_reg = PCH_LVDS;
1053 } else {
1054 pp_reg = PP_CONTROL;
1055 lvds_reg = LVDS;
1056 }
1057
1058 val = I915_READ(pp_reg);
1059 if (!(val & PANEL_POWER_ON) ||
1060 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1061 locked = false;
1062
1063 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1064 panel_pipe = PIPE_B;
1065
1066 WARN(panel_pipe == pipe && locked,
1067 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1068 pipe_name(pipe));
ea0760cf
JB		 1069}
1070
b840d907
JB		 1071void assert_pipe(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, bool state)
b24e7179
JB		 1073{
1074 int reg;
1075 u32 val;
63d7bbe9 1076 bool cur_state;
702e7a56
PZ		 1077 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1078 pipe);
b24e7179 1079
8e636784
DV		 1080 /* if we need the pipe A quirk it must be always on */
1081 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1082 state = true;
1083
b97186f0
PZ		 1084 if (!intel_display_power_enabled(dev_priv->dev,
1085 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1086 cur_state = false;
1087 } else {
1088 reg = PIPECONF(cpu_transcoder);
1089 val = I915_READ(reg);
1090 cur_state = !!(val & PIPECONF_ENABLE);
1091 }
1092
63d7bbe9
JB		 1093 WARN(cur_state != state,
1094 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1095 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1096}
1097
931872fc
CW		 1098static void assert_plane(struct drm_i915_private *dev_priv,
1099 enum plane plane, bool state)
b24e7179
JB		 1100{
1101 int reg;
1102 u32 val;
931872fc 1103 bool cur_state;
b24e7179
JB		 1104
1105 reg = DSPCNTR(plane);
1106 val = I915_READ(reg);
931872fc
CW		 1107 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1108 WARN(cur_state != state,
1109 "plane %c assertion failure (expected %s, current %s)\n",
1110 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1111}
1112
931872fc
CW		 1113#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1114#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1115
b24e7179
JB		 1116static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1117 enum pipe pipe)
1118{
653e1026 1119 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1120 int reg, i;
1121 u32 val;
1122 int cur_pipe;
1123
653e1026
VS		 1124 /* Primary planes are fixed to pipes on gen4+ */
1125 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1126 reg = DSPCNTR(pipe);
1127 val = I915_READ(reg);
1128 WARN((val & DISPLAY_PLANE_ENABLE),
1129 "plane %c assertion failure, should be disabled but not\n",
1130 plane_name(pipe));
19ec1358 1131 return;
28c05794 1132 }
19ec1358 1133
b24e7179 1134 /* Need to check both planes against the pipe */
653e1026 1135 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1136 reg = DSPCNTR(i);
1137 val = I915_READ(reg);
1138 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1139 DISPPLANE_SEL_PIPE_SHIFT;
1140 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1141 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1142 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1143 }
1144}
1145
19332d7a
JB		 1146static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
20674eef 1149 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1150 int reg, i;
1151 u32 val;
1152
20674eef
VS		 1153 if (IS_VALLEYVIEW(dev)) {
1154 for (i = 0; i < dev_priv->num_plane; i++) {
1155 reg = SPCNTR(pipe, i);
1156 val = I915_READ(reg);
1157 WARN((val & SP_ENABLE),
1158 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1159 sprite_name(pipe, i), pipe_name(pipe));
1160 }
1161 } else if (INTEL_INFO(dev)->gen >= 7) {
1162 reg = SPRCTL(pipe);
1163 val = I915_READ(reg);
1164 WARN((val & SPRITE_ENABLE),
1165 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1166 plane_name(pipe), pipe_name(pipe));
1167 } else if (INTEL_INFO(dev)->gen >= 5) {
1168 reg = DVSCNTR(pipe);
19332d7a 1169 val = I915_READ(reg);
20674eef 1170 WARN((val & DVS_ENABLE),
06da8da2 1171 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1172 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1173 }
1174}
1175
92f2584a
JB		 1176static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1177{
1178 u32 val;
1179 bool enabled;
1180
9d82aa17
ED		 1181 if (HAS_PCH_LPT(dev_priv->dev)) {
1182 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1183 return;
1184 }
1185
92f2584a
JB		 1186 val = I915_READ(PCH_DREF_CONTROL);
1187 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1188 DREF_SUPERSPREAD_SOURCE_MASK));
1189 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1190}
1191
ab9412ba
DV		 1192static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1193 enum pipe pipe)
92f2584a
JB		 1194{
1195 int reg;
1196 u32 val;
1197 bool enabled;
1198
ab9412ba 1199 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1200 val = I915_READ(reg);
1201 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1202 WARN(enabled,
1203 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1204 pipe_name(pipe));
92f2584a
JB		 1205}
1206
4e634389
KP		 1207static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1209{
1210 if ((val & DP_PORT_EN) == 0)
1211 return false;
1212
1213 if (HAS_PCH_CPT(dev_priv->dev)) {
1214 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1215 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1216 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1217 return false;
1218 } else {
1219 if ((val & DP_PIPE_MASK) != (pipe << 30))
1220 return false;
1221 }
1222 return true;
1223}
1224
1519b995
KP		 1225static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
dc0fa718 1228 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1232 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1233 return false;
1234 } else {
dc0fa718 1235 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & LVDS_PORT_EN) == 0)
1245 return false;
1246
1247 if (HAS_PCH_CPT(dev_priv->dev)) {
1248 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1249 return false;
1250 } else {
1251 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1252 return false;
1253 }
1254 return true;
1255}
1256
1257static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
1260 if ((val & ADPA_DAC_ENABLE) == 0)
1261 return false;
1262 if (HAS_PCH_CPT(dev_priv->dev)) {
1263 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1264 return false;
1265 } else {
1266 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1267 return false;
1268 }
1269 return true;
1270}
1271
291906f1 1272static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1273 enum pipe pipe, int reg, u32 port_sel)
291906f1 1274{
47a05eca 1275 u32 val = I915_READ(reg);
4e634389 1276 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1277 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1278 reg, pipe_name(pipe));
de9a35ab 1279
75c5da27
DV		 1280 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1281 && (val & DP_PIPEB_SELECT),
de9a35ab 1282 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1283}
1284
1285static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe, int reg)
1287{
47a05eca 1288 u32 val = I915_READ(reg);
b70ad586 1289 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1290 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 reg, pipe_name(pipe));
de9a35ab 1292
dc0fa718 1293 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1294 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1295 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1296}
1297
1298static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1299 enum pipe pipe)
1300{
1301 int reg;
1302 u32 val;
291906f1 1303
f0575e92
KP		 1304 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1307
1308 reg = PCH_ADPA;
1309 val = I915_READ(reg);
b70ad586 1310 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1311 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 pipe_name(pipe));
291906f1
JB		 1313
1314 reg = PCH_LVDS;
1315 val = I915_READ(reg);
b70ad586 1316 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1317 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1318 pipe_name(pipe));
291906f1 1319
e2debe91
PZ		 1320 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1323}
1324
63d7bbe9
JB		 1325/**
1326 * intel_enable_pll - enable a PLL
1327 * @dev_priv: i915 private structure
1328 * @pipe: pipe PLL to enable
1329 *
1330 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1331 * make sure the PLL reg is writable first though, since the panel write
1332 * protect mechanism may be enabled.
1333 *
1334 * Note! This is for pre-ILK only.
7434a255
TR		 1335 *
1336 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1337 */
1338static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1339{
1340 int reg;
1341 u32 val;
1342
58c6eaa2
DV		 1343 assert_pipe_disabled(dev_priv, pipe);
1344
63d7bbe9 1345 /* No really, not for ILK+ */
a0c4da24 1346 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1347
1348 /* PLL is protected by panel, make sure we can write it */
1349 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1350 assert_panel_unlocked(dev_priv, pipe);
1351
1352 reg = DPLL(pipe);
1353 val = I915_READ(reg);
1354 val |= DPLL_VCO_ENABLE;
1355
1356 /* We do this three times for luck */
1357 I915_WRITE(reg, val);
1358 POSTING_READ(reg);
1359 udelay(150); /* wait for warmup */
1360 I915_WRITE(reg, val);
1361 POSTING_READ(reg);
1362 udelay(150); /* wait for warmup */
1363 I915_WRITE(reg, val);
1364 POSTING_READ(reg);
1365 udelay(150); /* wait for warmup */
1366}
1367
1368/**
1369 * intel_disable_pll - disable a PLL
1370 * @dev_priv: i915 private structure
1371 * @pipe: pipe PLL to disable
1372 *
1373 * Disable the PLL for @pipe, making sure the pipe is off first.
1374 *
1375 * Note! This is for pre-ILK only.
1376 */
1377static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1378{
1379 int reg;
1380 u32 val;
1381
1382 /* Don't disable pipe A or pipe A PLLs if needed */
1383 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1384 return;
1385
1386 /* Make sure the pipe isn't still relying on us */
1387 assert_pipe_disabled(dev_priv, pipe);
1388
1389 reg = DPLL(pipe);
1390 val = I915_READ(reg);
1391 val &= ~DPLL_VCO_ENABLE;
1392 I915_WRITE(reg, val);
1393 POSTING_READ(reg);
1394}
1395
89b667f8
JB		 1396void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1397{
1398 u32 port_mask;
1399
1400 if (!port)
1401 port_mask = DPLL_PORTB_READY_MASK;
1402 else
1403 port_mask = DPLL_PORTC_READY_MASK;
1404
1405 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1406 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1407 'B' + port, I915_READ(DPLL(0)));
1408}
1409
92f2584a 1410/**
e72f9fbf 1411 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to enable
1414 *
1415 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1416 * drives the transcoder clock.
1417 */
e2b78267 1418static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1419{
e2b78267
DV		 1420 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1421 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a
JB		 1422 int reg;
1423 u32 val;
1424
48da64a8 1425 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1426 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1427 if (pll == NULL)
1428 return;
1429
1430 if (WARN_ON(pll->refcount == 0))
1431 return;
ee7b9f93 1432
46edb027
DV		 1433 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1434 pll->name, pll->active, pll->on,
e2b78267 1435 crtc->base.base.id);
92f2584a
JB		 1436
1437 /* PCH refclock must be enabled first */
1438 assert_pch_refclk_enabled(dev_priv);
1439
cdbd2316
DV		 1440 if (pll->active++) {
1441 WARN_ON(!pll->on);
e72f9fbf 1442 assert_shared_dpll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1443 return;
1444 }
f4a091c7 1445 WARN_ON(pll->on);
ee7b9f93 1446
46edb027 1447 DRM_DEBUG_KMS("enabling %s\n", pll->name);
ee7b9f93 1448
e9a632a5 1449 reg = PCH_DPLL(pll->id);
92f2584a
JB		 1450 val = I915_READ(reg);
1451 val |= DPLL_VCO_ENABLE;
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(200);
ee7b9f93
JB		 1455
1456 pll->on = true;
92f2584a
JB		 1457}
1458
e2b78267 1459static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1460{
e2b78267
DV		 1461 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1462 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1463 int reg;
ee7b9f93 1464 u32 val;
4c609cb8 1465
92f2584a
JB		 1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1468 if (pll == NULL)
1469 return;
92f2584a 1470
48da64a8
CW		 1471 if (WARN_ON(pll->refcount == 0))
1472 return;
7a419866 1473
46edb027
DV		 1474 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1475 pll->name, pll->active, pll->on,
e2b78267 1476 crtc->base.base.id);
7a419866 1477
48da64a8 1478 if (WARN_ON(pll->active == 0)) {
e72f9fbf 1479 assert_shared_dpll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1480 return;
1481 }
1482
e72f9fbf 1483 assert_shared_dpll_enabled(dev_priv, pll, NULL);
f4a091c7 1484 WARN_ON(!pll->on);
cdbd2316 1485 if (--pll->active)
7a419866 1486 return;
ee7b9f93 1487
46edb027 1488 DRM_DEBUG_KMS("disabling %s\n", pll->name);
ee7b9f93
JB		 1489
1490 /* Make sure transcoder isn't still depending on us */
e2b78267 1491 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
7a419866 1492
e9a632a5 1493 reg = PCH_DPLL(pll->id);
92f2584a
JB		 1494 val = I915_READ(reg);
1495 val &= ~DPLL_VCO_ENABLE;
1496 I915_WRITE(reg, val);
1497 POSTING_READ(reg);
1498 udelay(200);
ee7b9f93
JB		 1499
1500 pll->on = false;
92f2584a
JB		 1501}
1502
b8a4f404
PZ		 1503static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1504 enum pipe pipe)
040484af 1505{
23670b32 1506 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1507 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1509 uint32_t reg, val, pipeconf_val;
040484af
JB		 1510
1511 /* PCH only available on ILK+ */
1512 BUG_ON(dev_priv->info->gen < 5);
1513
1514 /* Make sure PCH DPLL is enabled */
e72f9fbf 1515 assert_shared_dpll_enabled(dev_priv,
e2b78267
DV		 1516 intel_crtc_to_shared_dpll(intel_crtc),
1517 intel_crtc);
040484af
JB		 1518
1519 /* FDI must be feeding us bits for PCH ports */
1520 assert_fdi_tx_enabled(dev_priv, pipe);
1521 assert_fdi_rx_enabled(dev_priv, pipe);
1522
23670b32
DV		 1523 if (HAS_PCH_CPT(dev)) {
1524 /* Workaround: Set the timing override bit before enabling the
1525 * pch transcoder. */
1526 reg = TRANS_CHICKEN2(pipe);
1527 val = I915_READ(reg);
1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1529 I915_WRITE(reg, val);
59c859d6 1530 }
23670b32 1531
ab9412ba 1532 reg = PCH_TRANSCONF(pipe);
040484af 1533 val = I915_READ(reg);
5f7f726d 1534 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1535
1536 if (HAS_PCH_IBX(dev_priv->dev)) {
1537 /*
1538 * make the BPC in transcoder be consistent with
1539 * that in pipeconf reg.
1540 */
dfd07d72
DV		 1541 val &= ~PIPECONF_BPC_MASK;
1542 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1543 }
5f7f726d
PZ		 1544
1545 val &= ~TRANS_INTERLACE_MASK;
1546 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1547 if (HAS_PCH_IBX(dev_priv->dev) &&
1548 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1549 val |= TRANS_LEGACY_INTERLACED_ILK;
1550 else
1551 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1552 else
1553 val |= TRANS_PROGRESSIVE;
1554
040484af
JB		 1555 I915_WRITE(reg, val | TRANS_ENABLE);
1556 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1557 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1558}
1559
8fb033d7 1560static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1561 enum transcoder cpu_transcoder)
040484af 1562{
8fb033d7 1563 u32 val, pipeconf_val;
8fb033d7
PZ		 1564
1565 /* PCH only available on ILK+ */
1566 BUG_ON(dev_priv->info->gen < 5);
1567
8fb033d7 1568 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1569 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1570 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1571
223a6fdf
PZ		 1572 /* Workaround: set timing override bit. */
1573 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1574 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1575 I915_WRITE(_TRANSA_CHICKEN2, val);
1576
25f3ef11 1577 val = TRANS_ENABLE;
937bb610 1578 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1579
9a76b1c6
PZ		 1580 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1581 PIPECONF_INTERLACED_ILK)
a35f2679 1582 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1583 else
1584 val |= TRANS_PROGRESSIVE;
1585
ab9412ba
DV		 1586 I915_WRITE(LPT_TRANSCONF, val);
1587 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1588 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1589}
1590
b8a4f404
PZ		 1591static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1592 enum pipe pipe)
040484af 1593{
23670b32
DV		 1594 struct drm_device *dev = dev_priv->dev;
1595 uint32_t reg, val;
040484af
JB		 1596
1597 /* FDI relies on the transcoder */
1598 assert_fdi_tx_disabled(dev_priv, pipe);
1599 assert_fdi_rx_disabled(dev_priv, pipe);
1600
291906f1
JB		 1601 /* Ports must be off as well */
1602 assert_pch_ports_disabled(dev_priv, pipe);
1603
ab9412ba 1604 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1605 val = I915_READ(reg);
1606 val &= ~TRANS_ENABLE;
1607 I915_WRITE(reg, val);
1608 /* wait for PCH transcoder off, transcoder state */
1609 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1610 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1611
1612 if (!HAS_PCH_IBX(dev)) {
1613 /* Workaround: Clear the timing override chicken bit again. */
1614 reg = TRANS_CHICKEN2(pipe);
1615 val = I915_READ(reg);
1616 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1617 I915_WRITE(reg, val);
1618 }
040484af
JB		 1619}
1620
ab4d966c 1621static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1622{
8fb033d7
PZ		 1623 u32 val;
1624
ab9412ba 1625 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1626 val &= ~TRANS_ENABLE;
ab9412ba 1627 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1628 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1629 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1630 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1631
1632 /* Workaround: clear timing override bit. */
1633 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1634 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1635 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1636}
1637
b24e7179 1638/**
309cfea8 1639 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1640 * @dev_priv: i915 private structure
1641 * @pipe: pipe to enable
040484af 1642 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1643 *
1644 * Enable @pipe, making sure that various hardware specific requirements
1645 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1646 *
1647 * @pipe should be %PIPE_A or %PIPE_B.
1648 *
1649 * Will wait until the pipe is actually running (i.e. first vblank) before
1650 * returning.
1651 */
040484af
JB		 1652static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1653 bool pch_port)
b24e7179 1654{
702e7a56
PZ		 1655 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1656 pipe);
1a240d4d 1657 enum pipe pch_transcoder;
b24e7179
JB		 1658 int reg;
1659 u32 val;
1660
58c6eaa2
DV		 1661 assert_planes_disabled(dev_priv, pipe);
1662 assert_sprites_disabled(dev_priv, pipe);
1663
681e5811 1664 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1665 pch_transcoder = TRANSCODER_A;
1666 else
1667 pch_transcoder = pipe;
1668
b24e7179
JB		 1669 /*
1670 * A pipe without a PLL won't actually be able to drive bits from
1671 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1672 * need the check.
1673 */
1674 if (!HAS_PCH_SPLIT(dev_priv->dev))
1675 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1676 else {
1677 if (pch_port) {
1678 /* if driving the PCH, we need FDI enabled */
cc391bbb 1679 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1680 assert_fdi_tx_pll_enabled(dev_priv,
1681 (enum pipe) cpu_transcoder);
040484af
JB		 1682 }
1683 /* FIXME: assert CPU port conditions for SNB+ */
1684 }
b24e7179 1685
702e7a56 1686 reg = PIPECONF(cpu_transcoder);
b24e7179 1687 val = I915_READ(reg);
00d70b15
CW		 1688 if (val & PIPECONF_ENABLE)
1689 return;
1690
1691 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1692 intel_wait_for_vblank(dev_priv->dev, pipe);
1693}
1694
1695/**
309cfea8 1696 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1697 * @dev_priv: i915 private structure
1698 * @pipe: pipe to disable
1699 *
1700 * Disable @pipe, making sure that various hardware specific requirements
1701 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1702 *
1703 * @pipe should be %PIPE_A or %PIPE_B.
1704 *
1705 * Will wait until the pipe has shut down before returning.
1706 */
1707static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1708 enum pipe pipe)
1709{
702e7a56
PZ		 1710 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1711 pipe);
b24e7179
JB		 1712 int reg;
1713 u32 val;
1714
1715 /*
1716 * Make sure planes won't keep trying to pump pixels to us,
1717 * or we might hang the display.
1718 */
1719 assert_planes_disabled(dev_priv, pipe);
19332d7a 1720 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1721
1722 /* Don't disable pipe A or pipe A PLLs if needed */
1723 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1724 return;
1725
702e7a56 1726 reg = PIPECONF(cpu_transcoder);
b24e7179 1727 val = I915_READ(reg);
00d70b15
CW		 1728 if ((val & PIPECONF_ENABLE) == 0)
1729 return;
1730
1731 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1732 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1733}
1734
d74362c9
KP		 1735/*
1736 * Plane regs are double buffered, going from enabled->disabled needs a
1737 * trigger in order to latch. The display address reg provides this.
1738 */
6f1d69b0 1739void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1740 enum plane plane)
1741{
14f86147
DL		 1742 if (dev_priv->info->gen >= 4)
1743 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1744 else
1745 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1746}
1747
b24e7179
JB		 1748/**
1749 * intel_enable_plane - enable a display plane on a given pipe
1750 * @dev_priv: i915 private structure
1751 * @plane: plane to enable
1752 * @pipe: pipe being fed
1753 *
1754 * Enable @plane on @pipe, making sure that @pipe is running first.
1755 */
1756static void intel_enable_plane(struct drm_i915_private *dev_priv,
1757 enum plane plane, enum pipe pipe)
1758{
1759 int reg;
1760 u32 val;
1761
1762 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1763 assert_pipe_enabled(dev_priv, pipe);
1764
1765 reg = DSPCNTR(plane);
1766 val = I915_READ(reg);
00d70b15
CW		 1767 if (val & DISPLAY_PLANE_ENABLE)
1768 return;
1769
1770 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1771 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
b24e7179
JB		 1775/**
1776 * intel_disable_plane - disable a display plane
1777 * @dev_priv: i915 private structure
1778 * @plane: plane to disable
1779 * @pipe: pipe consuming the data
1780 *
1781 * Disable @plane; should be an independent operation.
1782 */
1783static void intel_disable_plane(struct drm_i915_private *dev_priv,
1784 enum plane plane, enum pipe pipe)
1785{
1786 int reg;
1787 u32 val;
1788
1789 reg = DSPCNTR(plane);
1790 val = I915_READ(reg);
00d70b15
CW		 1791 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1792 return;
1793
1794 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1795 intel_flush_display_plane(dev_priv, plane);
1796 intel_wait_for_vblank(dev_priv->dev, pipe);
1797}
1798
693db184
CW		 1799static bool need_vtd_wa(struct drm_device *dev)
1800{
1801#ifdef CONFIG_INTEL_IOMMU
1802 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1803 return true;
1804#endif
1805 return false;
1806}
1807
127bd2ac 1808int
48b956c5 1809intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1810 struct drm_i915_gem_object *obj,
919926ae 1811 struct intel_ring_buffer *pipelined)
6b95a207 1812{
ce453d81 1813 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1814 u32 alignment;
1815 int ret;
1816
05394f39 1817 switch (obj->tiling_mode) {
6b95a207 1818 case I915_TILING_NONE:
534843da
CW		 1819 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1820 alignment = 128 * 1024;
a6c45cf0 1821 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1822 alignment = 4 * 1024;
1823 else
1824 alignment = 64 * 1024;
6b95a207
KH		 1825 break;
1826 case I915_TILING_X:
1827 /* pin() will align the object as required by fence */
1828 alignment = 0;
1829 break;
1830 case I915_TILING_Y:
8bb6e959
DV		 1831 /* Despite that we check this in framebuffer_init userspace can
1832 * screw us over and change the tiling after the fact. Only
1833 * pinned buffers can't change their tiling. */
1834 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1835 return -EINVAL;
1836 default:
1837 BUG();
1838 }
1839
693db184
CW		 1840 /* Note that the w/a also requires 64 PTE of padding following the
1841 * bo. We currently fill all unused PTE with the shadow page and so
1842 * we should always have valid PTE following the scanout preventing
1843 * the VT-d warning.
1844 */
1845 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1846 alignment = 256 * 1024;
1847
ce453d81 1848 dev_priv->mm.interruptible = false;
2da3b9b9 1849 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1850 if (ret)
ce453d81 1851 goto err_interruptible;
6b95a207
KH		 1852
1853 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1854 * fence, whereas 965+ only requires a fence if using
1855 * framebuffer compression. For simplicity, we always install
1856 * a fence as the cost is not that onerous.
1857 */
06d98131 1858 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1859 if (ret)
1860 goto err_unpin;
1690e1eb 1861
9a5a53b3 1862 i915_gem_object_pin_fence(obj);
6b95a207 1863
ce453d81 1864 dev_priv->mm.interruptible = true;
6b95a207 1865 return 0;
48b956c5
CW		 1866
1867err_unpin:
1868 i915_gem_object_unpin(obj);
ce453d81
CW		 1869err_interruptible:
1870 dev_priv->mm.interruptible = true;
48b956c5 1871 return ret;
6b95a207
KH		 1872}
1873
1690e1eb
CW		 1874void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1875{
1876 i915_gem_object_unpin_fence(obj);
1877 i915_gem_object_unpin(obj);
1878}
1879
c2c75131
DV		 1880/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1881 * is assumed to be a power-of-two. */
bc752862
CW		 1882unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1883 unsigned int tiling_mode,
1884 unsigned int cpp,
1885 unsigned int pitch)
c2c75131 1886{
bc752862
CW		 1887 if (tiling_mode != I915_TILING_NONE) {
1888 unsigned int tile_rows, tiles;
c2c75131 1889
bc752862
CW		 1890 tile_rows = *y / 8;
1891 *y %= 8;
c2c75131 1892
bc752862
CW		 1893 tiles = *x / (512/cpp);
1894 *x %= 512/cpp;
1895
1896 return tile_rows * pitch * 8 + tiles * 4096;
1897 } else {
1898 unsigned int offset;
1899
1900 offset = *y * pitch + *x * cpp;
1901 *y = 0;
1902 *x = (offset & 4095) / cpp;
1903 return offset & -4096;
1904 }
c2c75131
DV		 1905}
1906
17638cd6
JB		 1907static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1908 int x, int y)
81255565
JB		 1909{
1910 struct drm_device *dev = crtc->dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
1912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1913 struct intel_framebuffer *intel_fb;
05394f39 1914 struct drm_i915_gem_object *obj;
81255565 1915 int plane = intel_crtc->plane;
e506a0c6 1916 unsigned long linear_offset;
81255565 1917 u32 dspcntr;
5eddb70b 1918 u32 reg;
81255565
JB		 1919
1920 switch (plane) {
1921 case 0:
1922 case 1:
1923 break;
1924 default:
84f44ce7 1925 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1926 return -EINVAL;
1927 }
1928
1929 intel_fb = to_intel_framebuffer(fb);
1930 obj = intel_fb->obj;
81255565 1931
5eddb70b
CW		 1932 reg = DSPCNTR(plane);
1933 dspcntr = I915_READ(reg);
81255565
JB		 1934 /* Mask out pixel format bits in case we change it */
1935 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1936 switch (fb->pixel_format) {
1937 case DRM_FORMAT_C8:
81255565
JB		 1938 dspcntr |= DISPPLANE_8BPP;
1939 break;
57779d06
VS		 1940 case DRM_FORMAT_XRGB1555:
1941 case DRM_FORMAT_ARGB1555:
1942 dspcntr |= DISPPLANE_BGRX555;
81255565 1943 break;
57779d06
VS		 1944 case DRM_FORMAT_RGB565:
1945 dspcntr |= DISPPLANE_BGRX565;
1946 break;
1947 case DRM_FORMAT_XRGB8888:
1948 case DRM_FORMAT_ARGB8888:
1949 dspcntr |= DISPPLANE_BGRX888;
1950 break;
1951 case DRM_FORMAT_XBGR8888:
1952 case DRM_FORMAT_ABGR8888:
1953 dspcntr |= DISPPLANE_RGBX888;
1954 break;
1955 case DRM_FORMAT_XRGB2101010:
1956 case DRM_FORMAT_ARGB2101010:
1957 dspcntr |= DISPPLANE_BGRX101010;
1958 break;
1959 case DRM_FORMAT_XBGR2101010:
1960 case DRM_FORMAT_ABGR2101010:
1961 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1962 break;
1963 default:
baba133a 1964 BUG();
81255565 1965 }
57779d06 1966
a6c45cf0 1967 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1968 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1969 dspcntr |= DISPPLANE_TILED;
1970 else
1971 dspcntr &= ~DISPPLANE_TILED;
1972 }
1973
de1aa629
VS		 1974 if (IS_G4X(dev))
1975 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1976
5eddb70b 1977 I915_WRITE(reg, dspcntr);
81255565 1978
e506a0c6 1979 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1980
c2c75131
DV		 1981 if (INTEL_INFO(dev)->gen >= 4) {
1982 intel_crtc->dspaddr_offset =
bc752862
CW		 1983 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1984 fb->bits_per_pixel / 8,
1985 fb->pitches[0]);
c2c75131
DV		 1986 linear_offset -= intel_crtc->dspaddr_offset;
1987 } else {
e506a0c6 1988 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1989 }
e506a0c6
DV		 1990
1991 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1992 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1993 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1994 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1995 I915_MODIFY_DISPBASE(DSPSURF(plane),
1996 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1997 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1998 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1999 } else
e506a0c6 2000 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2001 POSTING_READ(reg);
81255565 2002
17638cd6
JB		 2003 return 0;
2004}
2005
2006static int ironlake_update_plane(struct drm_crtc *crtc,
2007 struct drm_framebuffer *fb, int x, int y)
2008{
2009 struct drm_device *dev = crtc->dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2012 struct intel_framebuffer *intel_fb;
2013 struct drm_i915_gem_object *obj;
2014 int plane = intel_crtc->plane;
e506a0c6 2015 unsigned long linear_offset;
17638cd6
JB		 2016 u32 dspcntr;
2017 u32 reg;
2018
2019 switch (plane) {
2020 case 0:
2021 case 1:
27f8227b 2022 case 2:
17638cd6
JB		 2023 break;
2024 default:
84f44ce7 2025 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2026 return -EINVAL;
2027 }
2028
2029 intel_fb = to_intel_framebuffer(fb);
2030 obj = intel_fb->obj;
2031
2032 reg = DSPCNTR(plane);
2033 dspcntr = I915_READ(reg);
2034 /* Mask out pixel format bits in case we change it */
2035 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2036 switch (fb->pixel_format) {
2037 case DRM_FORMAT_C8:
17638cd6
JB		 2038 dspcntr |= DISPPLANE_8BPP;
2039 break;
57779d06
VS		 2040 case DRM_FORMAT_RGB565:
2041 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2042 break;
57779d06
VS		 2043 case DRM_FORMAT_XRGB8888:
2044 case DRM_FORMAT_ARGB8888:
2045 dspcntr |= DISPPLANE_BGRX888;
2046 break;
2047 case DRM_FORMAT_XBGR8888:
2048 case DRM_FORMAT_ABGR8888:
2049 dspcntr |= DISPPLANE_RGBX888;
2050 break;
2051 case DRM_FORMAT_XRGB2101010:
2052 case DRM_FORMAT_ARGB2101010:
2053 dspcntr |= DISPPLANE_BGRX101010;
2054 break;
2055 case DRM_FORMAT_XBGR2101010:
2056 case DRM_FORMAT_ABGR2101010:
2057 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2058 break;
2059 default:
baba133a 2060 BUG();
17638cd6
JB		 2061 }
2062
2063 if (obj->tiling_mode != I915_TILING_NONE)
2064 dspcntr |= DISPPLANE_TILED;
2065 else
2066 dspcntr &= ~DISPPLANE_TILED;
2067
2068 /* must disable */
2069 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2070
2071 I915_WRITE(reg, dspcntr);
2072
e506a0c6 2073 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2074 intel_crtc->dspaddr_offset =
bc752862
CW		 2075 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2076 fb->bits_per_pixel / 8,
2077 fb->pitches[0]);
c2c75131 2078 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2079
e506a0c6
DV		 2080 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2081 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2082 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2083 I915_MODIFY_DISPBASE(DSPSURF(plane),
2084 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2085 if (IS_HASWELL(dev)) {
2086 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2087 } else {
2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090 }
17638cd6
JB		 2091 POSTING_READ(reg);
2092
2093 return 0;
2094}
2095
2096/* Assume fb object is pinned & idle & fenced and just update base pointers */
2097static int
2098intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2099 int x, int y, enum mode_set_atomic state)
2100{
2101 struct drm_device *dev = crtc->dev;
2102 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2103
6b8e6ed0
CW		 2104 if (dev_priv->display.disable_fbc)
2105 dev_priv->display.disable_fbc(dev);
3dec0095 2106 intel_increase_pllclock(crtc);
81255565 2107
6b8e6ed0 2108 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2109}
2110
96a02917
VS		 2111void intel_display_handle_reset(struct drm_device *dev)
2112{
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct drm_crtc *crtc;
2115
2116 /*
2117 * Flips in the rings have been nuked by the reset,
2118 * so complete all pending flips so that user space
2119 * will get its events and not get stuck.
2120 *
2121 * Also update the base address of all primary
2122 * planes to the the last fb to make sure we're
2123 * showing the correct fb after a reset.
2124 *
2125 * Need to make two loops over the crtcs so that we
2126 * don't try to grab a crtc mutex before the
2127 * pending_flip_queue really got woken up.
2128 */
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132 enum plane plane = intel_crtc->plane;
2133
2134 intel_prepare_page_flip(dev, plane);
2135 intel_finish_page_flip_plane(dev, plane);
2136 }
2137
2138 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 mutex_lock(&crtc->mutex);
2142 if (intel_crtc->active)
2143 dev_priv->display.update_plane(crtc, crtc->fb,
2144 crtc->x, crtc->y);
2145 mutex_unlock(&crtc->mutex);
2146 }
2147}
2148
14667a4b
CW		 2149static int
2150intel_finish_fb(struct drm_framebuffer *old_fb)
2151{
2152 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2153 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2154 bool was_interruptible = dev_priv->mm.interruptible;
2155 int ret;
2156
14667a4b
CW		 2157 /* Big Hammer, we also need to ensure that any pending
2158 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2159 * current scanout is retired before unpinning the old
2160 * framebuffer.
2161 *
2162 * This should only fail upon a hung GPU, in which case we
2163 * can safely continue.
2164 */
2165 dev_priv->mm.interruptible = false;
2166 ret = i915_gem_object_finish_gpu(obj);
2167 dev_priv->mm.interruptible = was_interruptible;
2168
2169 return ret;
2170}
2171
198598d0
VS		 2172static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_master_private *master_priv;
2176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2177
2178 if (!dev->primary->master)
2179 return;
2180
2181 master_priv = dev->primary->master->driver_priv;
2182 if (!master_priv->sarea_priv)
2183 return;
2184
2185 switch (intel_crtc->pipe) {
2186 case 0:
2187 master_priv->sarea_priv->pipeA_x = x;
2188 master_priv->sarea_priv->pipeA_y = y;
2189 break;
2190 case 1:
2191 master_priv->sarea_priv->pipeB_x = x;
2192 master_priv->sarea_priv->pipeB_y = y;
2193 break;
2194 default:
2195 break;
2196 }
2197}
2198
5c3b82e2 2199static int
3c4fdcfb 2200intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2201 struct drm_framebuffer *fb)
79e53945
JB		 2202{
2203 struct drm_device *dev = crtc->dev;
6b8e6ed0 2204 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2206 struct drm_framebuffer *old_fb;
5c3b82e2 2207 int ret;
79e53945
JB		 2208
2209 /* no fb bound */
94352cf9 2210 if (!fb) {
a5071c2f 2211 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2212 return 0;
2213 }
2214
7eb552ae 2215 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2216 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2217 plane_name(intel_crtc->plane),
2218 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2219 return -EINVAL;
79e53945
JB		 2220 }
2221
5c3b82e2 2222 mutex_lock(&dev->struct_mutex);
265db958 2223 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2224 to_intel_framebuffer(fb)->obj,
919926ae 2225 NULL);
5c3b82e2
CW		 2226 if (ret != 0) {
2227 mutex_unlock(&dev->struct_mutex);
a5071c2f 2228 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2229 return ret;
2230 }
79e53945 2231
94352cf9 2232 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2233 if (ret) {
94352cf9 2234 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2235 mutex_unlock(&dev->struct_mutex);
a5071c2f 2236 DRM_ERROR("failed to update base address\n");
4e6cfefc 2237 return ret;
79e53945 2238 }
3c4fdcfb 2239
94352cf9
DV		 2240 old_fb = crtc->fb;
2241 crtc->fb = fb;
6c4c86f5
DV		 2242 crtc->x = x;
2243 crtc->y = y;
94352cf9 2244
b7f1de28 2245 if (old_fb) {
d7697eea
DV		 2246 if (intel_crtc->active && old_fb != fb)
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2249 }
652c393a 2250
6b8e6ed0 2251 intel_update_fbc(dev);
5c3b82e2 2252 mutex_unlock(&dev->struct_mutex);
79e53945 2253
198598d0 2254 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2255
2256 return 0;
79e53945
JB		 2257}
2258
5e84e1a4
ZW		 2259static void intel_fdi_normal_train(struct drm_crtc *crtc)
2260{
2261 struct drm_device *dev = crtc->dev;
2262 struct drm_i915_private *dev_priv = dev->dev_private;
2263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2264 int pipe = intel_crtc->pipe;
2265 u32 reg, temp;
2266
2267 /* enable normal train */
2268 reg = FDI_TX_CTL(pipe);
2269 temp = I915_READ(reg);
61e499bf 2270 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2271 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2272 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2273 } else {
2274 temp &= ~FDI_LINK_TRAIN_NONE;
2275 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2276 }
5e84e1a4
ZW		 2277 I915_WRITE(reg, temp);
2278
2279 reg = FDI_RX_CTL(pipe);
2280 temp = I915_READ(reg);
2281 if (HAS_PCH_CPT(dev)) {
2282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2283 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2284 } else {
2285 temp &= ~FDI_LINK_TRAIN_NONE;
2286 temp |= FDI_LINK_TRAIN_NONE;
2287 }
2288 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2289
2290 /* wait one idle pattern time */
2291 POSTING_READ(reg);
2292 udelay(1000);
357555c0
JB		 2293
2294 /* IVB wants error correction enabled */
2295 if (IS_IVYBRIDGE(dev))
2296 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2297 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2298}
2299
1e833f40
DV		 2300static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2301{
2302 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2303}
2304
01a415fd
DV		 2305static void ivb_modeset_global_resources(struct drm_device *dev)
2306{
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *pipe_B_crtc =
2309 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2310 struct intel_crtc *pipe_C_crtc =
2311 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2312 uint32_t temp;
2313
1e833f40
DV		 2314 /*
2315 * When everything is off disable fdi C so that we could enable fdi B
2316 * with all lanes. Note that we don't care about enabled pipes without
2317 * an enabled pch encoder.
2318 */
2319 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2320 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2321 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2322 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2323
2324 temp = I915_READ(SOUTH_CHICKEN1);
2325 temp &= ~FDI_BC_BIFURCATION_SELECT;
2326 DRM_DEBUG_KMS("disabling fdi C rx\n");
2327 I915_WRITE(SOUTH_CHICKEN1, temp);
2328 }
2329}
2330
8db9d77b
ZW		 2331/* The FDI link training functions for ILK/Ibexpeak. */
2332static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2333{
2334 struct drm_device *dev = crtc->dev;
2335 struct drm_i915_private *dev_priv = dev->dev_private;
2336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2337 int pipe = intel_crtc->pipe;
0fc932b8 2338 int plane = intel_crtc->plane;
5eddb70b 2339 u32 reg, temp, tries;
8db9d77b 2340
0fc932b8
JB		 2341 /* FDI needs bits from pipe & plane first */
2342 assert_pipe_enabled(dev_priv, pipe);
2343 assert_plane_enabled(dev_priv, plane);
2344
e1a44743
AJ		 2345 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2346 for train result */
5eddb70b
CW		 2347 reg = FDI_RX_IMR(pipe);
2348 temp = I915_READ(reg);
e1a44743
AJ		 2349 temp &= ~FDI_RX_SYMBOL_LOCK;
2350 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2351 I915_WRITE(reg, temp);
2352 I915_READ(reg);
e1a44743
AJ		 2353 udelay(150);
2354
8db9d77b 2355 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
627eb5a3
DV		 2358 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2359 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2362 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2363
5eddb70b
CW		 2364 reg = FDI_RX_CTL(pipe);
2365 temp = I915_READ(reg);
8db9d77b
ZW		 2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2368 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2369
2370 POSTING_READ(reg);
8db9d77b
ZW		 2371 udelay(150);
2372
5b2adf89 2373 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2374 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2375 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2376 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2377
5eddb70b 2378 reg = FDI_RX_IIR(pipe);
e1a44743 2379 for (tries = 0; tries < 5; tries++) {
5eddb70b 2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2382
2383 if ((temp & FDI_RX_BIT_LOCK)) {
2384 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2385 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2386 break;
2387 }
8db9d77b 2388 }
e1a44743 2389 if (tries == 5)
5eddb70b 2390 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2391
2392 /* Train 2 */
5eddb70b
CW		 2393 reg = FDI_TX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2397 I915_WRITE(reg, temp);
8db9d77b 2398
5eddb70b
CW		 2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
8db9d77b
ZW		 2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2403 I915_WRITE(reg, temp);
8db9d77b 2404
5eddb70b
CW		 2405 POSTING_READ(reg);
2406 udelay(150);
8db9d77b 2407
5eddb70b 2408 reg = FDI_RX_IIR(pipe);
e1a44743 2409 for (tries = 0; tries < 5; tries++) {
5eddb70b 2410 temp = I915_READ(reg);
8db9d77b
ZW		 2411 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2414 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2415 DRM_DEBUG_KMS("FDI train 2 done.\n");
2416 break;
2417 }
8db9d77b 2418 }
e1a44743 2419 if (tries == 5)
5eddb70b 2420 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2421
2422 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2423
8db9d77b
ZW		 2424}
2425
0206e353 2426static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2427 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2428 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2429 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2430 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2431};
2432
2433/* The FDI link training functions for SNB/Cougarpoint. */
2434static void gen6_fdi_link_train(struct drm_crtc *crtc)
2435{
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 int pipe = intel_crtc->pipe;
fa37d39e 2440 u32 reg, temp, i, retry;
8db9d77b 2441
e1a44743
AJ		 2442 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2443 for train result */
5eddb70b
CW		 2444 reg = FDI_RX_IMR(pipe);
2445 temp = I915_READ(reg);
e1a44743
AJ		 2446 temp &= ~FDI_RX_SYMBOL_LOCK;
2447 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2448 I915_WRITE(reg, temp);
2449
2450 POSTING_READ(reg);
e1a44743
AJ		 2451 udelay(150);
2452
8db9d77b 2453 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
627eb5a3
DV		 2456 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2457 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1;
2460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2461 /* SNB-B */
2462 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2464
d74cf324
DV		 2465 I915_WRITE(FDI_RX_MISC(pipe),
2466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2467
5eddb70b
CW		 2468 reg = FDI_RX_CTL(pipe);
2469 temp = I915_READ(reg);
8db9d77b
ZW		 2470 if (HAS_PCH_CPT(dev)) {
2471 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2472 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2473 } else {
2474 temp &= ~FDI_LINK_TRAIN_NONE;
2475 temp |= FDI_LINK_TRAIN_PATTERN_1;
2476 }
5eddb70b
CW		 2477 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2478
2479 POSTING_READ(reg);
8db9d77b
ZW		 2480 udelay(150);
2481
0206e353 2482 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2483 reg = FDI_TX_CTL(pipe);
2484 temp = I915_READ(reg);
8db9d77b
ZW		 2485 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2486 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2487 I915_WRITE(reg, temp);
2488
2489 POSTING_READ(reg);
8db9d77b
ZW		 2490 udelay(500);
2491
fa37d39e
SP		 2492 for (retry = 0; retry < 5; retry++) {
2493 reg = FDI_RX_IIR(pipe);
2494 temp = I915_READ(reg);
2495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2496 if (temp & FDI_RX_BIT_LOCK) {
2497 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2498 DRM_DEBUG_KMS("FDI train 1 done.\n");
2499 break;
2500 }
2501 udelay(50);
8db9d77b 2502 }
fa37d39e
SP		 2503 if (retry < 5)
2504 break;
8db9d77b
ZW		 2505 }
2506 if (i == 4)
5eddb70b 2507 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2508
2509 /* Train 2 */
5eddb70b
CW		 2510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 temp &= ~FDI_LINK_TRAIN_NONE;
2513 temp |= FDI_LINK_TRAIN_PATTERN_2;
2514 if (IS_GEN6(dev)) {
2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 /* SNB-B */
2517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2518 }
5eddb70b 2519 I915_WRITE(reg, temp);
8db9d77b 2520
5eddb70b
CW		 2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 if (HAS_PCH_CPT(dev)) {
2524 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2526 } else {
2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_2;
2529 }
5eddb70b
CW		 2530 I915_WRITE(reg, temp);
2531
2532 POSTING_READ(reg);
8db9d77b
ZW		 2533 udelay(150);
2534
0206e353 2535 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2540 I915_WRITE(reg, temp);
2541
2542 POSTING_READ(reg);
8db9d77b
ZW		 2543 udelay(500);
2544
fa37d39e
SP		 2545 for (retry = 0; retry < 5; retry++) {
2546 reg = FDI_RX_IIR(pipe);
2547 temp = I915_READ(reg);
2548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549 if (temp & FDI_RX_SYMBOL_LOCK) {
2550 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2551 DRM_DEBUG_KMS("FDI train 2 done.\n");
2552 break;
2553 }
2554 udelay(50);
8db9d77b 2555 }
fa37d39e
SP		 2556 if (retry < 5)
2557 break;
8db9d77b
ZW		 2558 }
2559 if (i == 4)
5eddb70b 2560 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2561
2562 DRM_DEBUG_KMS("FDI train done.\n");
2563}
2564
357555c0
JB		 2565/* Manual link training for Ivy Bridge A0 parts */
2566static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2567{
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2571 int pipe = intel_crtc->pipe;
2572 u32 reg, temp, i;
2573
2574 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2575 for train result */
2576 reg = FDI_RX_IMR(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_RX_SYMBOL_LOCK;
2579 temp &= ~FDI_RX_BIT_LOCK;
2580 I915_WRITE(reg, temp);
2581
2582 POSTING_READ(reg);
2583 udelay(150);
2584
01a415fd
DV		 2585 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2586 I915_READ(FDI_RX_IIR(pipe)));
2587
357555c0
JB		 2588 /* enable CPU FDI TX and PCH FDI RX */
2589 reg = FDI_TX_CTL(pipe);
2590 temp = I915_READ(reg);
627eb5a3
DV		 2591 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2592 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2593 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2597 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2598 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2599
d74cf324
DV		 2600 I915_WRITE(FDI_RX_MISC(pipe),
2601 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2602
357555c0
JB		 2603 reg = FDI_RX_CTL(pipe);
2604 temp = I915_READ(reg);
2605 temp &= ~FDI_LINK_TRAIN_AUTO;
2606 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2607 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2608 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2609 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2610
2611 POSTING_READ(reg);
2612 udelay(150);
2613
0206e353 2614 for (i = 0; i < 4; i++) {
357555c0
JB		 2615 reg = FDI_TX_CTL(pipe);
2616 temp = I915_READ(reg);
2617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2618 temp |= snb_b_fdi_train_param[i];
2619 I915_WRITE(reg, temp);
2620
2621 POSTING_READ(reg);
2622 udelay(500);
2623
2624 reg = FDI_RX_IIR(pipe);
2625 temp = I915_READ(reg);
2626 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2627
2628 if (temp & FDI_RX_BIT_LOCK ||
2629 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2630 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2631 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2632 break;
2633 }
2634 }
2635 if (i == 4)
2636 DRM_ERROR("FDI train 1 fail!\n");
2637
2638 /* Train 2 */
2639 reg = FDI_TX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2645 I915_WRITE(reg, temp);
2646
2647 reg = FDI_RX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2650 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
2654 udelay(150);
2655
0206e353 2656 for (i = 0; i < 4; i++) {
357555c0
JB		 2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= snb_b_fdi_train_param[i];
2661 I915_WRITE(reg, temp);
2662
2663 POSTING_READ(reg);
2664 udelay(500);
2665
2666 reg = FDI_RX_IIR(pipe);
2667 temp = I915_READ(reg);
2668 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2669
2670 if (temp & FDI_RX_SYMBOL_LOCK) {
2671 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2672 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2673 break;
2674 }
2675 }
2676 if (i == 4)
2677 DRM_ERROR("FDI train 2 fail!\n");
2678
2679 DRM_DEBUG_KMS("FDI train done.\n");
2680}
2681
88cefb6c 2682static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2683{
88cefb6c 2684 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2685 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2686 int pipe = intel_crtc->pipe;
5eddb70b 2687 u32 reg, temp;
79e53945 2688
c64e311e 2689
c98e9dcf 2690 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2691 reg = FDI_RX_CTL(pipe);
2692 temp = I915_READ(reg);
627eb5a3
DV		 2693 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2695 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2696 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2697
2698 POSTING_READ(reg);
c98e9dcf
JB		 2699 udelay(200);
2700
2701 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp | FDI_PCDCLK);
2704
2705 POSTING_READ(reg);
c98e9dcf
JB		 2706 udelay(200);
2707
20749730
PZ		 2708 /* Enable CPU FDI TX PLL, always on for Ironlake */
2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2712 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2713
20749730
PZ		 2714 POSTING_READ(reg);
2715 udelay(100);
6be4a607 2716 }
0e23b99d
JB		 2717}
2718
88cefb6c
DV		 2719static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2720{
2721 struct drm_device *dev = intel_crtc->base.dev;
2722 struct drm_i915_private *dev_priv = dev->dev_private;
2723 int pipe = intel_crtc->pipe;
2724 u32 reg, temp;
2725
2726 /* Switch from PCDclk to Rawclk */
2727 reg = FDI_RX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2730
2731 /* Disable CPU FDI TX PLL */
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2735
2736 POSTING_READ(reg);
2737 udelay(100);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2742
2743 /* Wait for the clocks to turn off. */
2744 POSTING_READ(reg);
2745 udelay(100);
2746}
2747
0fc932b8
JB		 2748static void ironlake_fdi_disable(struct drm_crtc *crtc)
2749{
2750 struct drm_device *dev = crtc->dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2753 int pipe = intel_crtc->pipe;
2754 u32 reg, temp;
2755
2756 /* disable CPU FDI tx and PCH FDI rx */
2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2760 POSTING_READ(reg);
2761
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~(0x7 << 16);
dfd07d72 2765 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2766 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2767
2768 POSTING_READ(reg);
2769 udelay(100);
2770
2771 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2772 if (HAS_PCH_IBX(dev)) {
2773 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2774 }
0fc932b8
JB		 2775
2776 /* still set train pattern 1 */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE;
2780 temp |= FDI_LINK_TRAIN_PATTERN_1;
2781 I915_WRITE(reg, temp);
2782
2783 reg = FDI_RX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if (HAS_PCH_CPT(dev)) {
2786 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2787 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2788 } else {
2789 temp &= ~FDI_LINK_TRAIN_NONE;
2790 temp |= FDI_LINK_TRAIN_PATTERN_1;
2791 }
2792 /* BPC in FDI rx is consistent with that in PIPECONF */
2793 temp &= ~(0x07 << 16);
dfd07d72 2794 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2795 I915_WRITE(reg, temp);
2796
2797 POSTING_READ(reg);
2798 udelay(100);
2799}
2800
5bb61643
CW		 2801static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2802{
2803 struct drm_device *dev = crtc->dev;
2804 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2806 unsigned long flags;
2807 bool pending;
2808
10d83730
VS		 2809 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2810 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2811 return false;
2812
2813 spin_lock_irqsave(&dev->event_lock, flags);
2814 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2815 spin_unlock_irqrestore(&dev->event_lock, flags);
2816
2817 return pending;
2818}
2819
e6c3a2a6
CW		 2820static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2821{
0f91128d 2822 struct drm_device *dev = crtc->dev;
5bb61643 2823 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2824
2825 if (crtc->fb == NULL)
2826 return;
2827
2c10d571
DV		 2828 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2829
5bb61643
CW		 2830 wait_event(dev_priv->pending_flip_queue,
2831 !intel_crtc_has_pending_flip(crtc));
2832
0f91128d
CW		 2833 mutex_lock(&dev->struct_mutex);
2834 intel_finish_fb(crtc->fb);
2835 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2836}
2837
e615efe4
ED		 2838/* Program iCLKIP clock to the desired frequency */
2839static void lpt_program_iclkip(struct drm_crtc *crtc)
2840{
2841 struct drm_device *dev = crtc->dev;
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2844 u32 temp;
2845
09153000
DV		 2846 mutex_lock(&dev_priv->dpio_lock);
2847
e615efe4
ED		 2848 /* It is necessary to ungate the pixclk gate prior to programming
2849 * the divisors, and gate it back when it is done.
2850 */
2851 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2852
2853 /* Disable SSCCTL */
2854 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2855 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2856 SBI_SSCCTL_DISABLE,
2857 SBI_ICLK);
e615efe4
ED		 2858
2859 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2860 if (crtc->mode.clock == 20000) {
2861 auxdiv = 1;
2862 divsel = 0x41;
2863 phaseinc = 0x20;
2864 } else {
2865 /* The iCLK virtual clock root frequency is in MHz,
2866 * but the crtc->mode.clock in in KHz. To get the divisors,
2867 * it is necessary to divide one by another, so we
2868 * convert the virtual clock precision to KHz here for higher
2869 * precision.
2870 */
2871 u32 iclk_virtual_root_freq = 172800 * 1000;
2872 u32 iclk_pi_range = 64;
2873 u32 desired_divisor, msb_divisor_value, pi_value;
2874
2875 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2876 msb_divisor_value = desired_divisor / iclk_pi_range;
2877 pi_value = desired_divisor % iclk_pi_range;
2878
2879 auxdiv = 0;
2880 divsel = msb_divisor_value - 2;
2881 phaseinc = pi_value;
2882 }
2883
2884 /* This should not happen with any sane values */
2885 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2886 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2887 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2888 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2889
2890 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2891 crtc->mode.clock,
2892 auxdiv,
2893 divsel,
2894 phasedir,
2895 phaseinc);
2896
2897 /* Program SSCDIVINTPHASE6 */
988d6ee8 2898 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2899 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2900 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2901 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2902 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2903 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2904 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2905 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2906
2907 /* Program SSCAUXDIV */
988d6ee8 2908 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2909 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2910 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2911 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2912
2913 /* Enable modulator and associated divider */
988d6ee8 2914 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2915 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2916 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2917
2918 /* Wait for initialization time */
2919 udelay(24);
2920
2921 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2922
2923 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2924}
2925
275f01b2
DV		 2926static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2927 enum pipe pch_transcoder)
2928{
2929 struct drm_device *dev = crtc->base.dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2932
2933 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2934 I915_READ(HTOTAL(cpu_transcoder)));
2935 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2936 I915_READ(HBLANK(cpu_transcoder)));
2937 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2938 I915_READ(HSYNC(cpu_transcoder)));
2939
2940 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2941 I915_READ(VTOTAL(cpu_transcoder)));
2942 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2943 I915_READ(VBLANK(cpu_transcoder)));
2944 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2945 I915_READ(VSYNC(cpu_transcoder)));
2946 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2947 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2948}
2949
f67a559d
JB		 2950/*
2951 * Enable PCH resources required for PCH ports:
2952 * - PCH PLLs
2953 * - FDI training & RX/TX
2954 * - update transcoder timings
2955 * - DP transcoding bits
2956 * - transcoder
2957 */
2958static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2959{
2960 struct drm_device *dev = crtc->dev;
2961 struct drm_i915_private *dev_priv = dev->dev_private;
2962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2963 int pipe = intel_crtc->pipe;
ee7b9f93 2964 u32 reg, temp;
2c07245f 2965
ab9412ba 2966 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2967
cd986abb
DV		 2968 /* Write the TU size bits before fdi link training, so that error
2969 * detection works. */
2970 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2971 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2972
c98e9dcf 2973 /* For PCH output, training FDI link */
674cf967 2974 dev_priv->display.fdi_link_train(crtc);
2c07245f 2975
572deb37
DV		 2976 /* XXX: pch pll's can be enabled any time before we enable the PCH
2977 * transcoder, and we actually should do this to not upset any PCH
2978 * transcoder that already use the clock when we share it.
2979 *
e72f9fbf
DV		 2980 * Note that enable_shared_dpll tries to do the right thing, but
2981 * get_shared_dpll unconditionally resets the pll - we need that to have
2982 * the right LVDS enable sequence. */
2983 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2984
303b81e0 2985 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2986 u32 sel;
4b645f14 2987
c98e9dcf 2988 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2989 temp |= TRANS_DPLL_ENABLE(pipe);
2990 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2991 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2992 temp |= sel;
2993 else
2994 temp &= ~sel;
c98e9dcf 2995 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2996 }
5eddb70b 2997
d9b6cb56
JB		 2998 /* set transcoder timing, panel must allow it */
2999 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3000 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3001
303b81e0 3002 intel_fdi_normal_train(crtc);
5e84e1a4 3003
c98e9dcf
JB		 3004 /* For PCH DP, enable TRANS_DP_CTL */
3005 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3006 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3008 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3009 reg = TRANS_DP_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3012 TRANS_DP_SYNC_MASK |
3013 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3014 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015 TRANS_DP_ENH_FRAMING);
9325c9f0 3016 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3017
3018 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3019 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3020 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3021 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3022
3023 switch (intel_trans_dp_port_sel(crtc)) {
3024 case PCH_DP_B:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_C:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3029 break;
3030 case PCH_DP_D:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3032 break;
3033 default:
e95d41e1 3034 BUG();
32f9d658 3035 }
2c07245f 3036
5eddb70b 3037 I915_WRITE(reg, temp);
6be4a607 3038 }
b52eb4dc 3039
b8a4f404 3040 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3041}
3042
1507e5bd
PZ		 3043static void lpt_pch_enable(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3049
ab9412ba 3050 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3051
8c52b5e8 3052 lpt_program_iclkip(crtc);
1507e5bd 3053
0540e488 3054 /* Set transcoder timing. */
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3056
937bb610 3057 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3058}
3059
e2b78267 3060static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3061{
e2b78267 3062 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3063
3064 if (pll == NULL)
3065 return;
3066
3067 if (pll->refcount == 0) {
46edb027 3068 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3069 return;
3070 }
3071
f4a091c7
DV		 3072 if (--pll->refcount == 0) {
3073 WARN_ON(pll->on);
3074 WARN_ON(pll->active);
3075 }
3076
a43f6e0f 3077 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3078}
3079
e2b78267 3080static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3081{
e2b78267
DV		 3082 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3083 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3084 enum intel_dpll_id i;
ee7b9f93 3085
ee7b9f93 3086 if (pll) {
46edb027
DV		 3087 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3088 crtc->base.base.id, pll->name);
e2b78267 3089 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3090 }
3091
98b6bd99
DV		 3092 if (HAS_PCH_IBX(dev_priv->dev)) {
3093 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3094 i = crtc->pipe;
e72f9fbf 3095 pll = &dev_priv->shared_dplls[i];
98b6bd99 3096
46edb027
DV		 3097 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3098 crtc->base.base.id, pll->name);
98b6bd99
DV		 3099
3100 goto found;
3101 }
3102
e72f9fbf
DV		 3103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3104 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3105
3106 /* Only want to check enabled timings first */
3107 if (pll->refcount == 0)
3108 continue;
3109
e9a632a5
DV		 3110 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3111 fp == I915_READ(PCH_FP0(pll->id))) {
46edb027 3112 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3113 crtc->base.base.id,
46edb027 3114 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3115
3116 goto found;
3117 }
3118 }
3119
3120 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3121 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3122 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3123 if (pll->refcount == 0) {
46edb027
DV		 3124 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3125 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3126 goto found;
3127 }
3128 }
3129
3130 return NULL;
3131
3132found:
a43f6e0f 3133 crtc->config.shared_dpll = i;
46edb027
DV		 3134 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3135 pipe_name(crtc->pipe));
cdbd2316 3136 if (pll->active == 0) {
46edb027 3137 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3138 WARN_ON(pll->on);
e72f9fbf 3139 assert_shared_dpll_disabled(dev_priv, pll, NULL);
ee7b9f93 3140
cdbd2316 3141 /* Wait for the clocks to stabilize before rewriting the regs */
e9a632a5
DV		 3142 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3143 POSTING_READ(PCH_DPLL(pll->id));
cdbd2316
DV		 3144 udelay(150);
3145
e9a632a5
DV		 3146 I915_WRITE(PCH_FP0(pll->id), fp);
3147 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
cdbd2316
DV		 3148 }
3149 pll->refcount++;
e04c7350 3150
ee7b9f93
JB		 3151 return pll;
3152}
3153
a1520318 3154static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3155{
3156 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3157 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3158 u32 temp;
3159
3160 temp = I915_READ(dslreg);
3161 udelay(500);
3162 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3163 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3164 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3165 }
3166}
3167
b074cec8
JB		 3168static void ironlake_pfit_enable(struct intel_crtc *crtc)
3169{
3170 struct drm_device *dev = crtc->base.dev;
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 int pipe = crtc->pipe;
3173
0ef37f3f 3174 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3175 /* Force use of hard-coded filter coefficients
3176 * as some pre-programmed values are broken,
3177 * e.g. x201.
3178 */
3179 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3180 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3181 PF_PIPE_SEL_IVB(pipe));
3182 else
3183 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3184 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3185 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3186 }
3187}
3188
bb53d4ae
VS		 3189static void intel_enable_planes(struct drm_crtc *crtc)
3190{
3191 struct drm_device *dev = crtc->dev;
3192 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3193 struct intel_plane *intel_plane;
3194
3195 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3196 if (intel_plane->pipe == pipe)
3197 intel_plane_restore(&intel_plane->base);
3198}
3199
3200static void intel_disable_planes(struct drm_crtc *crtc)
3201{
3202 struct drm_device *dev = crtc->dev;
3203 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3204 struct intel_plane *intel_plane;
3205
3206 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3207 if (intel_plane->pipe == pipe)
3208 intel_plane_disable(&intel_plane->base);
3209}
3210
f67a559d
JB		 3211static void ironlake_crtc_enable(struct drm_crtc *crtc)
3212{
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3216 struct intel_encoder *encoder;
f67a559d
JB		 3217 int pipe = intel_crtc->pipe;
3218 int plane = intel_crtc->plane;
3219 u32 temp;
f67a559d 3220
08a48469
DV		 3221 WARN_ON(!crtc->enabled);
3222
f67a559d
JB		 3223 if (intel_crtc->active)
3224 return;
3225
3226 intel_crtc->active = true;
8664281b
PZ		 3227
3228 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3229 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3230
f67a559d
JB		 3231 intel_update_watermarks(dev);
3232
3233 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3234 temp = I915_READ(PCH_LVDS);
3235 if ((temp & LVDS_PORT_EN) == 0)
3236 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3237 }
3238
f67a559d 3239
5bfe2ac0 3240 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3241 /* Note: FDI PLL enabling _must_ be done before we enable the
3242 * cpu pipes, hence this is separate from all the other fdi/pch
3243 * enabling. */
88cefb6c 3244 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3245 } else {
3246 assert_fdi_tx_disabled(dev_priv, pipe);
3247 assert_fdi_rx_disabled(dev_priv, pipe);
3248 }
f67a559d 3249
bf49ec8c
DV		 3250 for_each_encoder_on_crtc(dev, crtc, encoder)
3251 if (encoder->pre_enable)
3252 encoder->pre_enable(encoder);
f67a559d
JB		 3253
3254 /* Enable panel fitting for LVDS */
b074cec8 3255 ironlake_pfit_enable(intel_crtc);
f67a559d 3256
9c54c0dd
JB		 3257 /*
3258 * On ILK+ LUT must be loaded before the pipe is running but with
3259 * clocks enabled
3260 */
3261 intel_crtc_load_lut(crtc);
3262
5bfe2ac0
DV		 3263 intel_enable_pipe(dev_priv, pipe,
3264 intel_crtc->config.has_pch_encoder);
f67a559d 3265 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3266 intel_enable_planes(crtc);
5c38d48c 3267 intel_crtc_update_cursor(crtc, true);
f67a559d 3268
5bfe2ac0 3269 if (intel_crtc->config.has_pch_encoder)
f67a559d 3270 ironlake_pch_enable(crtc);
c98e9dcf 3271
d1ebd816 3272 mutex_lock(&dev->struct_mutex);
bed4a673 3273 intel_update_fbc(dev);
d1ebd816
BW		 3274 mutex_unlock(&dev->struct_mutex);
3275
fa5c73b1
DV		 3276 for_each_encoder_on_crtc(dev, crtc, encoder)
3277 encoder->enable(encoder);
61b77ddd
DV		 3278
3279 if (HAS_PCH_CPT(dev))
a1520318 3280 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3281
3282 /*
3283 * There seems to be a race in PCH platform hw (at least on some
3284 * outputs) where an enabled pipe still completes any pageflip right
3285 * away (as if the pipe is off) instead of waiting for vblank. As soon
3286 * as the first vblank happend, everything works as expected. Hence just
3287 * wait for one vblank before returning to avoid strange things
3288 * happening.
3289 */
3290 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3291}
3292
42db64ef
PZ		 3293/* IPS only exists on ULT machines and is tied to pipe A. */
3294static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3295{
3296 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3297}
3298
3299static void hsw_enable_ips(struct intel_crtc *crtc)
3300{
3301 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3302
3303 if (!crtc->config.ips_enabled)
3304 return;
3305
3306 /* We can only enable IPS after we enable a plane and wait for a vblank.
3307 * We guarantee that the plane is enabled by calling intel_enable_ips
3308 * only after intel_enable_plane. And intel_enable_plane already waits
3309 * for a vblank, so all we need to do here is to enable the IPS bit. */
3310 assert_plane_enabled(dev_priv, crtc->plane);
3311 I915_WRITE(IPS_CTL, IPS_ENABLE);
3312}
3313
3314static void hsw_disable_ips(struct intel_crtc *crtc)
3315{
3316 struct drm_device *dev = crtc->base.dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318
3319 if (!crtc->config.ips_enabled)
3320 return;
3321
3322 assert_plane_enabled(dev_priv, crtc->plane);
3323 I915_WRITE(IPS_CTL, 0);
3324
3325 /* We need to wait for a vblank before we can disable the plane. */
3326 intel_wait_for_vblank(dev, crtc->pipe);
3327}
3328
4f771f10
PZ		 3329static void haswell_crtc_enable(struct drm_crtc *crtc)
3330{
3331 struct drm_device *dev = crtc->dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334 struct intel_encoder *encoder;
3335 int pipe = intel_crtc->pipe;
3336 int plane = intel_crtc->plane;
4f771f10
PZ		 3337
3338 WARN_ON(!crtc->enabled);
3339
3340 if (intel_crtc->active)
3341 return;
3342
3343 intel_crtc->active = true;
8664281b
PZ		 3344
3345 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3346 if (intel_crtc->config.has_pch_encoder)
3347 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3348
4f771f10
PZ		 3349 intel_update_watermarks(dev);
3350
5bfe2ac0 3351 if (intel_crtc->config.has_pch_encoder)
04945641 3352 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3353
3354 for_each_encoder_on_crtc(dev, crtc, encoder)
3355 if (encoder->pre_enable)
3356 encoder->pre_enable(encoder);
3357
1f544388 3358 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3359
1f544388 3360 /* Enable panel fitting for eDP */
b074cec8 3361 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3362
3363 /*
3364 * On ILK+ LUT must be loaded before the pipe is running but with
3365 * clocks enabled
3366 */
3367 intel_crtc_load_lut(crtc);
3368
1f544388 3369 intel_ddi_set_pipe_settings(crtc);
8228c251 3370 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3371
5bfe2ac0
DV		 3372 intel_enable_pipe(dev_priv, pipe,
3373 intel_crtc->config.has_pch_encoder);
4f771f10 3374 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3375 intel_enable_planes(crtc);
5c38d48c 3376 intel_crtc_update_cursor(crtc, true);
4f771f10 3377
42db64ef
PZ		 3378 hsw_enable_ips(intel_crtc);
3379
5bfe2ac0 3380 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3381 lpt_pch_enable(crtc);
4f771f10
PZ		 3382
3383 mutex_lock(&dev->struct_mutex);
3384 intel_update_fbc(dev);
3385 mutex_unlock(&dev->struct_mutex);
3386
4f771f10
PZ		 3387 for_each_encoder_on_crtc(dev, crtc, encoder)
3388 encoder->enable(encoder);
3389
4f771f10
PZ		 3390 /*
3391 * There seems to be a race in PCH platform hw (at least on some
3392 * outputs) where an enabled pipe still completes any pageflip right
3393 * away (as if the pipe is off) instead of waiting for vblank. As soon
3394 * as the first vblank happend, everything works as expected. Hence just
3395 * wait for one vblank before returning to avoid strange things
3396 * happening.
3397 */
3398 intel_wait_for_vblank(dev, intel_crtc->pipe);
3399}
3400
3f8dce3a
DV		 3401static void ironlake_pfit_disable(struct intel_crtc *crtc)
3402{
3403 struct drm_device *dev = crtc->base.dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 int pipe = crtc->pipe;
3406
3407 /* To avoid upsetting the power well on haswell only disable the pfit if
3408 * it's in use. The hw state code will make sure we get this right. */
3409 if (crtc->config.pch_pfit.size) {
3410 I915_WRITE(PF_CTL(pipe), 0);
3411 I915_WRITE(PF_WIN_POS(pipe), 0);
3412 I915_WRITE(PF_WIN_SZ(pipe), 0);
3413 }
3414}
3415
6be4a607
JB		 3416static void ironlake_crtc_disable(struct drm_crtc *crtc)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3421 struct intel_encoder *encoder;
6be4a607
JB		 3422 int pipe = intel_crtc->pipe;
3423 int plane = intel_crtc->plane;
5eddb70b 3424 u32 reg, temp;
b52eb4dc 3425
ef9c3aee 3426
f7abfe8b
CW		 3427 if (!intel_crtc->active)
3428 return;
3429
ea9d758d
DV		 3430 for_each_encoder_on_crtc(dev, crtc, encoder)
3431 encoder->disable(encoder);
3432
e6c3a2a6 3433 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3434 drm_vblank_off(dev, pipe);
913d8d11 3435
973d04f9
CW		 3436 if (dev_priv->cfb_plane == plane)
3437 intel_disable_fbc(dev);
2c07245f 3438
0d5b8c61 3439 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3440 intel_disable_planes(crtc);
0d5b8c61
VS		 3441 intel_disable_plane(dev_priv, plane, pipe);
3442
d925c59a
DV		 3443 if (intel_crtc->config.has_pch_encoder)
3444 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3445
b24e7179 3446 intel_disable_pipe(dev_priv, pipe);
32f9d658 3447
3f8dce3a 3448 ironlake_pfit_disable(intel_crtc);
2c07245f 3449
bf49ec8c
DV		 3450 for_each_encoder_on_crtc(dev, crtc, encoder)
3451 if (encoder->post_disable)
3452 encoder->post_disable(encoder);
2c07245f 3453
d925c59a
DV		 3454 if (intel_crtc->config.has_pch_encoder) {
3455 ironlake_fdi_disable(crtc);
249c0e64 3456
d925c59a
DV		 3457 ironlake_disable_pch_transcoder(dev_priv, pipe);
3458 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3459
d925c59a
DV		 3460 if (HAS_PCH_CPT(dev)) {
3461 /* disable TRANS_DP_CTL */
3462 reg = TRANS_DP_CTL(pipe);
3463 temp = I915_READ(reg);
3464 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3465 TRANS_DP_PORT_SEL_MASK);
3466 temp |= TRANS_DP_PORT_SEL_NONE;
3467 I915_WRITE(reg, temp);
3468
3469 /* disable DPLL_SEL */
3470 temp = I915_READ(PCH_DPLL_SEL);
11887397 3471 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3472 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3473 }
e3421a18 3474
d925c59a 3475 /* disable PCH DPLL */
e72f9fbf 3476 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3477
d925c59a
DV		 3478 ironlake_fdi_pll_disable(intel_crtc);
3479 }
6b383a7f 3480
f7abfe8b 3481 intel_crtc->active = false;
6b383a7f 3482 intel_update_watermarks(dev);
d1ebd816
BW		 3483
3484 mutex_lock(&dev->struct_mutex);
6b383a7f 3485 intel_update_fbc(dev);
d1ebd816 3486 mutex_unlock(&dev->struct_mutex);
6be4a607 3487}
1b3c7a47 3488
4f771f10 3489static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3490{
4f771f10
PZ		 3491 struct drm_device *dev = crtc->dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3494 struct intel_encoder *encoder;
3495 int pipe = intel_crtc->pipe;
3496 int plane = intel_crtc->plane;
3b117c8f 3497 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3498
4f771f10
PZ		 3499 if (!intel_crtc->active)
3500 return;
3501
3502 for_each_encoder_on_crtc(dev, crtc, encoder)
3503 encoder->disable(encoder);
3504
3505 intel_crtc_wait_for_pending_flips(crtc);
3506 drm_vblank_off(dev, pipe);
4f771f10 3507
891348b2 3508 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3509 if (dev_priv->cfb_plane == plane)
3510 intel_disable_fbc(dev);
3511
42db64ef
PZ		 3512 hsw_disable_ips(intel_crtc);
3513
0d5b8c61 3514 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3515 intel_disable_planes(crtc);
891348b2
RV		 3516 intel_disable_plane(dev_priv, plane, pipe);
3517
8664281b
PZ		 3518 if (intel_crtc->config.has_pch_encoder)
3519 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3520 intel_disable_pipe(dev_priv, pipe);
3521
ad80a810 3522 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3523
3f8dce3a 3524 ironlake_pfit_disable(intel_crtc);
4f771f10 3525
1f544388 3526 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3527
3528 for_each_encoder_on_crtc(dev, crtc, encoder)
3529 if (encoder->post_disable)
3530 encoder->post_disable(encoder);
3531
88adfff1 3532 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3533 lpt_disable_pch_transcoder(dev_priv);
8664281b 3534 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3535 intel_ddi_fdi_disable(crtc);
83616634 3536 }
4f771f10
PZ		 3537
3538 intel_crtc->active = false;
3539 intel_update_watermarks(dev);
3540
3541 mutex_lock(&dev->struct_mutex);
3542 intel_update_fbc(dev);
3543 mutex_unlock(&dev->struct_mutex);
3544}
3545
ee7b9f93
JB		 3546static void ironlake_crtc_off(struct drm_crtc *crtc)
3547{
3548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3549 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3550}
3551
6441ab5f
PZ		 3552static void haswell_crtc_off(struct drm_crtc *crtc)
3553{
3554 intel_ddi_put_crtc_pll(crtc);
3555}
3556
02e792fb
DV		 3557static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3558{
02e792fb 3559 if (!enable && intel_crtc->overlay) {
23f09ce3 3560 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3561 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3562
23f09ce3 3563 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3564 dev_priv->mm.interruptible = false;
3565 (void) intel_overlay_switch_off(intel_crtc->overlay);
3566 dev_priv->mm.interruptible = true;
23f09ce3 3567 mutex_unlock(&dev->struct_mutex);
02e792fb 3568 }
02e792fb 3569
5dcdbcb0
CW		 3570 /* Let userspace switch the overlay on again. In most cases userspace
3571 * has to recompute where to put it anyway.
3572 */
02e792fb
DV		 3573}
3574
61bc95c1
EE		 3575/**
3576 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3577 * cursor plane briefly if not already running after enabling the display
3578 * plane.
3579 * This workaround avoids occasional blank screens when self refresh is
3580 * enabled.
3581 */
3582static void
3583g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3584{
3585 u32 cntl = I915_READ(CURCNTR(pipe));
3586
3587 if ((cntl & CURSOR_MODE) == 0) {
3588 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3589
3590 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3591 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3592 intel_wait_for_vblank(dev_priv->dev, pipe);
3593 I915_WRITE(CURCNTR(pipe), cntl);
3594 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3595 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3596 }
3597}
3598
2dd24552
JB		 3599static void i9xx_pfit_enable(struct intel_crtc *crtc)
3600{
3601 struct drm_device *dev = crtc->base.dev;
3602 struct drm_i915_private *dev_priv = dev->dev_private;
3603 struct intel_crtc_config *pipe_config = &crtc->config;
3604
328d8e82 3605 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3606 return;
3607
2dd24552 3608 /*
c0b03411
DV		 3609 * The panel fitter should only be adjusted whilst the pipe is disabled,
3610 * according to register description and PRM.
2dd24552 3611 */
c0b03411
DV		 3612 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3613 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3614
b074cec8
JB		 3615 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3616 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3617
3618 /* Border color in case we don't scale up to the full screen. Black by
3619 * default, change to something else for debugging. */
3620 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3621}
3622
89b667f8
JB		 3623static void valleyview_crtc_enable(struct drm_crtc *crtc)
3624{
3625 struct drm_device *dev = crtc->dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 struct intel_encoder *encoder;
3629 int pipe = intel_crtc->pipe;
3630 int plane = intel_crtc->plane;
3631
3632 WARN_ON(!crtc->enabled);
3633
3634 if (intel_crtc->active)
3635 return;
3636
3637 intel_crtc->active = true;
3638 intel_update_watermarks(dev);
3639
3640 mutex_lock(&dev_priv->dpio_lock);
3641
3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->pre_pll_enable)
3644 encoder->pre_pll_enable(encoder);
3645
3646 intel_enable_pll(dev_priv, pipe);
3647
3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 if (encoder->pre_enable)
3650 encoder->pre_enable(encoder);
3651
3652 /* VLV wants encoder enabling _before_ the pipe is up. */
3653 for_each_encoder_on_crtc(dev, crtc, encoder)
3654 encoder->enable(encoder);
3655
2dd24552
JB		 3656 /* Enable panel fitting for eDP */
3657 i9xx_pfit_enable(intel_crtc);
3658
63cbb074
VS		 3659 intel_crtc_load_lut(crtc);
3660
89b667f8
JB		 3661 intel_enable_pipe(dev_priv, pipe, false);
3662 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3663 intel_enable_planes(crtc);
5c38d48c 3664 intel_crtc_update_cursor(crtc, true);
89b667f8 3665
f440eb13
VS		 3666 intel_update_fbc(dev);
3667
89b667f8
JB		 3668 mutex_unlock(&dev_priv->dpio_lock);
3669}
3670
0b8765c6 3671static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3672{
3673 struct drm_device *dev = crtc->dev;
79e53945
JB		 3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3676 struct intel_encoder *encoder;
79e53945 3677 int pipe = intel_crtc->pipe;
80824003 3678 int plane = intel_crtc->plane;
79e53945 3679
08a48469
DV		 3680 WARN_ON(!crtc->enabled);
3681
f7abfe8b
CW		 3682 if (intel_crtc->active)
3683 return;
3684
3685 intel_crtc->active = true;
6b383a7f
CW		 3686 intel_update_watermarks(dev);
3687
63d7bbe9 3688 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3689
3690 for_each_encoder_on_crtc(dev, crtc, encoder)
3691 if (encoder->pre_enable)
3692 encoder->pre_enable(encoder);
3693
2dd24552
JB		 3694 /* Enable panel fitting for LVDS */
3695 i9xx_pfit_enable(intel_crtc);
3696
63cbb074
VS		 3697 intel_crtc_load_lut(crtc);
3698
040484af 3699 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3700 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3701 intel_enable_planes(crtc);
22e407d7 3702 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3703 if (IS_G4X(dev))
3704 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3705 intel_crtc_update_cursor(crtc, true);
79e53945 3706
0b8765c6
JB		 3707 /* Give the overlay scaler a chance to enable if it's on this pipe */
3708 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3709
f440eb13
VS		 3710 intel_update_fbc(dev);
3711
fa5c73b1
DV		 3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->enable(encoder);
0b8765c6 3714}
79e53945 3715
87476d63
DV		 3716static void i9xx_pfit_disable(struct intel_crtc *crtc)
3717{
3718 struct drm_device *dev = crtc->base.dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3720
328d8e82
DV		 3721 if (!crtc->config.gmch_pfit.control)
3722 return;
87476d63 3723
328d8e82 3724 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3725
328d8e82
DV		 3726 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3727 I915_READ(PFIT_CONTROL));
3728 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3729}
3730
0b8765c6
JB		 3731static void i9xx_crtc_disable(struct drm_crtc *crtc)
3732{
3733 struct drm_device *dev = crtc->dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3736 struct intel_encoder *encoder;
0b8765c6
JB		 3737 int pipe = intel_crtc->pipe;
3738 int plane = intel_crtc->plane;
ef9c3aee 3739
f7abfe8b
CW		 3740 if (!intel_crtc->active)
3741 return;
3742
ea9d758d
DV		 3743 for_each_encoder_on_crtc(dev, crtc, encoder)
3744 encoder->disable(encoder);
3745
0b8765c6 3746 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3747 intel_crtc_wait_for_pending_flips(crtc);
3748 drm_vblank_off(dev, pipe);
0b8765c6 3749
973d04f9
CW		 3750 if (dev_priv->cfb_plane == plane)
3751 intel_disable_fbc(dev);
79e53945 3752
0d5b8c61
VS		 3753 intel_crtc_dpms_overlay(intel_crtc, false);
3754 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3755 intel_disable_planes(crtc);
b24e7179 3756 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3757
b24e7179 3758 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3759
87476d63 3760 i9xx_pfit_disable(intel_crtc);
24a1f16d 3761
89b667f8
JB		 3762 for_each_encoder_on_crtc(dev, crtc, encoder)
3763 if (encoder->post_disable)
3764 encoder->post_disable(encoder);
3765
63d7bbe9 3766 intel_disable_pll(dev_priv, pipe);
0b8765c6 3767
f7abfe8b 3768 intel_crtc->active = false;
6b383a7f
CW		 3769 intel_update_fbc(dev);
3770 intel_update_watermarks(dev);
0b8765c6
JB		 3771}
3772
ee7b9f93
JB		 3773static void i9xx_crtc_off(struct drm_crtc *crtc)
3774{
3775}
3776
976f8a20
DV		 3777static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3778 bool enabled)
2c07245f
ZW		 3779{
3780 struct drm_device *dev = crtc->dev;
3781 struct drm_i915_master_private *master_priv;
3782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3783 int pipe = intel_crtc->pipe;
79e53945
JB		 3784
3785 if (!dev->primary->master)
3786 return;
3787
3788 master_priv = dev->primary->master->driver_priv;
3789 if (!master_priv->sarea_priv)
3790 return;
3791
79e53945
JB		 3792 switch (pipe) {
3793 case 0:
3794 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3795 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3796 break;
3797 case 1:
3798 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3799 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3800 break;
3801 default:
9db4a9c7 3802 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3803 break;
3804 }
79e53945
JB		 3805}
3806
976f8a20
DV		 3807/**
3808 * Sets the power management mode of the pipe and plane.
3809 */
3810void intel_crtc_update_dpms(struct drm_crtc *crtc)
3811{
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_encoder *intel_encoder;
3815 bool enable = false;
3816
3817 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3818 enable |= intel_encoder->connectors_active;
3819
3820 if (enable)
3821 dev_priv->display.crtc_enable(crtc);
3822 else
3823 dev_priv->display.crtc_disable(crtc);
3824
3825 intel_crtc_update_sarea(crtc, enable);
3826}
3827
cdd59983
CW		 3828static void intel_crtc_disable(struct drm_crtc *crtc)
3829{
cdd59983 3830 struct drm_device *dev = crtc->dev;
976f8a20 3831 struct drm_connector *connector;
ee7b9f93 3832 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3834
976f8a20
DV		 3835 /* crtc should still be enabled when we disable it. */
3836 WARN_ON(!crtc->enabled);
3837
3838 dev_priv->display.crtc_disable(crtc);
c77bf565 3839 intel_crtc->eld_vld = false;
976f8a20 3840 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3841 dev_priv->display.off(crtc);
3842
931872fc
CW		 3843 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3844 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3845
3846 if (crtc->fb) {
3847 mutex_lock(&dev->struct_mutex);
1690e1eb 3848 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3849 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3850 crtc->fb = NULL;
3851 }
3852
3853 /* Update computed state. */
3854 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3855 if (!connector->encoder || !connector->encoder->crtc)
3856 continue;
3857
3858 if (connector->encoder->crtc != crtc)
3859 continue;
3860
3861 connector->dpms = DRM_MODE_DPMS_OFF;
3862 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3863 }
3864}
3865
a261b246 3866void intel_modeset_disable(struct drm_device *dev)
79e53945 3867{
a261b246
DV		 3868 struct drm_crtc *crtc;
3869
3870 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3871 if (crtc->enabled)
3872 intel_crtc_disable(crtc);
3873 }
79e53945
JB		 3874}
3875
ea5b213a 3876void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3877{
4ef69c7a 3878 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3879
ea5b213a
CW		 3880 drm_encoder_cleanup(encoder);
3881 kfree(intel_encoder);
7e7d76c3
JB		 3882}
3883
5ab432ef
DV		 3884/* Simple dpms helper for encodres with just one connector, no cloning and only
3885 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3886 * state of the entire output pipe. */
3887void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3888{
5ab432ef
DV		 3889 if (mode == DRM_MODE_DPMS_ON) {
3890 encoder->connectors_active = true;
3891
b2cabb0e 3892 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3893 } else {
3894 encoder->connectors_active = false;
3895
b2cabb0e 3896 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3897 }
79e53945
JB		 3898}
3899
0a91ca29
DV		 3900/* Cross check the actual hw state with our own modeset state tracking (and it's
3901 * internal consistency). */
b980514c 3902static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3903{
0a91ca29
DV		 3904 if (connector->get_hw_state(connector)) {
3905 struct intel_encoder *encoder = connector->encoder;
3906 struct drm_crtc *crtc;
3907 bool encoder_enabled;
3908 enum pipe pipe;
3909
3910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3911 connector->base.base.id,
3912 drm_get_connector_name(&connector->base));
3913
3914 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3915 "wrong connector dpms state\n");
3916 WARN(connector->base.encoder != &encoder->base,
3917 "active connector not linked to encoder\n");
3918 WARN(!encoder->connectors_active,
3919 "encoder->connectors_active not set\n");
3920
3921 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3922 WARN(!encoder_enabled, "encoder not enabled\n");
3923 if (WARN_ON(!encoder->base.crtc))
3924 return;
3925
3926 crtc = encoder->base.crtc;
3927
3928 WARN(!crtc->enabled, "crtc not enabled\n");
3929 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3930 WARN(pipe != to_intel_crtc(crtc)->pipe,
3931 "encoder active on the wrong pipe\n");
3932 }
79e53945
JB		 3933}
3934
5ab432ef
DV		 3935/* Even simpler default implementation, if there's really no special case to
3936 * consider. */
3937void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3938{
5ab432ef 3939 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3940
5ab432ef
DV		 3941 /* All the simple cases only support two dpms states. */
3942 if (mode != DRM_MODE_DPMS_ON)
3943 mode = DRM_MODE_DPMS_OFF;
d4270e57 3944
5ab432ef
DV		 3945 if (mode == connector->dpms)
3946 return;
3947
3948 connector->dpms = mode;
3949
3950 /* Only need to change hw state when actually enabled */
3951 if (encoder->base.crtc)
3952 intel_encoder_dpms(encoder, mode);
3953 else
8af6cf88 3954 WARN_ON(encoder->connectors_active != false);
0a91ca29 3955
b980514c 3956 intel_modeset_check_state(connector->dev);
79e53945
JB		 3957}
3958
f0947c37
DV		 3959/* Simple connector->get_hw_state implementation for encoders that support only
3960 * one connector and no cloning and hence the encoder state determines the state
3961 * of the connector. */
3962bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3963{
24929352 3964 enum pipe pipe = 0;
f0947c37 3965 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3966
f0947c37 3967 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3968}
3969
1857e1da
DV		 3970static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3971 struct intel_crtc_config *pipe_config)
3972{
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 struct intel_crtc *pipe_B_crtc =
3975 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3976
3977 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3978 pipe_name(pipe), pipe_config->fdi_lanes);
3979 if (pipe_config->fdi_lanes > 4) {
3980 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3982 return false;
3983 }
3984
3985 if (IS_HASWELL(dev)) {
3986 if (pipe_config->fdi_lanes > 2) {
3987 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3988 pipe_config->fdi_lanes);
3989 return false;
3990 } else {
3991 return true;
3992 }
3993 }
3994
3995 if (INTEL_INFO(dev)->num_pipes == 2)
3996 return true;
3997
3998 /* Ivybridge 3 pipe is really complicated */
3999 switch (pipe) {
4000 case PIPE_A:
4001 return true;
4002 case PIPE_B:
4003 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4004 pipe_config->fdi_lanes > 2) {
4005 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4006 pipe_name(pipe), pipe_config->fdi_lanes);
4007 return false;
4008 }
4009 return true;
4010 case PIPE_C:
1e833f40 4011 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4012 pipe_B_crtc->config.fdi_lanes <= 2) {
4013 if (pipe_config->fdi_lanes > 2) {
4014 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015 pipe_name(pipe), pipe_config->fdi_lanes);
4016 return false;
4017 }
4018 } else {
4019 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4020 return false;
4021 }
4022 return true;
4023 default:
4024 BUG();
4025 }
4026}
4027
e29c22c0
DV		 4028#define RETRY 1
4029static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4030 struct intel_crtc_config *pipe_config)
877d48d5 4031{
1857e1da 4032 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4033 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4034 int lane, link_bw, fdi_dotclock;
e29c22c0 4035 bool setup_ok, needs_recompute = false;
877d48d5 4036
e29c22c0 4037retry:
877d48d5
DV		 4038 /* FDI is a binary signal running at ~2.7GHz, encoding
4039 * each output octet as 10 bits. The actual frequency
4040 * is stored as a divider into a 100MHz clock, and the
4041 * mode pixel clock is stored in units of 1KHz.
4042 * Hence the bw of each lane in terms of the mode signal
4043 * is:
4044 */
4045 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4046
ff9a6750 4047 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4048 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4049
4050 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4051 pipe_config->pipe_bpp);
4052
4053 pipe_config->fdi_lanes = lane;
4054
2bd89a07 4055 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4056 link_bw, &pipe_config->fdi_m_n);
1857e1da 4057
e29c22c0
DV		 4058 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4059 intel_crtc->pipe, pipe_config);
4060 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4061 pipe_config->pipe_bpp -= 2*3;
4062 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4063 pipe_config->pipe_bpp);
4064 needs_recompute = true;
4065 pipe_config->bw_constrained = true;
4066
4067 goto retry;
4068 }
4069
4070 if (needs_recompute)
4071 return RETRY;
4072
4073 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4074}
4075
42db64ef
PZ		 4076static void hsw_compute_ips_config(struct intel_crtc *crtc,
4077 struct intel_crtc_config *pipe_config)
4078{
3c4ca58c
PZ		 4079 pipe_config->ips_enabled = i915_enable_ips &&
4080 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4081 pipe_config->pipe_bpp == 24;
4082}
4083
a43f6e0f 4084static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4085 struct intel_crtc_config *pipe_config)
79e53945 4086{
a43f6e0f 4087 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4089
bad720ff 4090 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4091 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4092 if (pipe_config->requested_mode.clock * 3
4093 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4094 return -EINVAL;
2c07245f 4095 }
89749350 4096
f9bef081
DV		 4097 /* All interlaced capable intel hw wants timings in frames. Note though
4098 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4099 * timings, so we need to be careful not to clobber these.*/
7ae89233 4100 if (!pipe_config->timings_set)
f9bef081 4101 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4102
8693a824
DL		 4103 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4104 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4105 */
4106 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4107 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4108 return -EINVAL;
44f46b42 4109
bd080ee5 4110 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4111 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4112 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4113 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4114 * for lvds. */
4115 pipe_config->pipe_bpp = 8*3;
4116 }
4117
42db64ef 4118 if (IS_HASWELL(dev))
a43f6e0f
DV		 4119 hsw_compute_ips_config(crtc, pipe_config);
4120
4121 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4122 * clock survives for now. */
4123 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4124 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4125
877d48d5 4126 if (pipe_config->has_pch_encoder)
a43f6e0f 4127 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4128
e29c22c0 4129 return 0;
79e53945
JB		 4130}
4131
25eb05fc
JB		 4132static int valleyview_get_display_clock_speed(struct drm_device *dev)
4133{
4134 return 400000; /* FIXME */
4135}
4136
e70236a8
JB		 4137static int i945_get_display_clock_speed(struct drm_device *dev)
4138{
4139 return 400000;
4140}
79e53945 4141
e70236a8 4142static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4143{
e70236a8
JB		 4144 return 333000;
4145}
79e53945 4146
e70236a8
JB		 4147static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4148{
4149 return 200000;
4150}
79e53945 4151
e70236a8
JB		 4152static int i915gm_get_display_clock_speed(struct drm_device *dev)
4153{
4154 u16 gcfgc = 0;
79e53945 4155
e70236a8
JB		 4156 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4157
4158 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4159 return 133000;
4160 else {
4161 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4162 case GC_DISPLAY_CLOCK_333_MHZ:
4163 return 333000;
4164 default:
4165 case GC_DISPLAY_CLOCK_190_200_MHZ:
4166 return 190000;
79e53945 4167 }
e70236a8
JB		 4168 }
4169}
4170
4171static int i865_get_display_clock_speed(struct drm_device *dev)
4172{
4173 return 266000;
4174}
4175
4176static int i855_get_display_clock_speed(struct drm_device *dev)
4177{
4178 u16 hpllcc = 0;
4179 /* Assume that the hardware is in the high speed state. This
4180 * should be the default.
4181 */
4182 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4183 case GC_CLOCK_133_200:
4184 case GC_CLOCK_100_200:
4185 return 200000;
4186 case GC_CLOCK_166_250:
4187 return 250000;
4188 case GC_CLOCK_100_133:
79e53945 4189 return 133000;
e70236a8 4190 }
79e53945 4191
e70236a8
JB		 4192 /* Shouldn't happen */
4193 return 0;
4194}
79e53945 4195
e70236a8
JB		 4196static int i830_get_display_clock_speed(struct drm_device *dev)
4197{
4198 return 133000;
79e53945
JB		 4199}
4200
2c07245f 4201static void
a65851af 4202intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4203{
a65851af
VS		 4204 while (*num > DATA_LINK_M_N_MASK ||
4205 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4206 *num >>= 1;
4207 *den >>= 1;
4208 }
4209}
4210
a65851af
VS		 4211static void compute_m_n(unsigned int m, unsigned int n,
4212 uint32_t *ret_m, uint32_t *ret_n)
4213{
4214 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4215 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4216 intel_reduce_m_n_ratio(ret_m, ret_n);
4217}
4218
e69d0bc1
DV		 4219void
4220intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4221 int pixel_clock, int link_clock,
4222 struct intel_link_m_n *m_n)
2c07245f 4223{
e69d0bc1 4224 m_n->tu = 64;
a65851af
VS		 4225
4226 compute_m_n(bits_per_pixel * pixel_clock,
4227 link_clock * nlanes * 8,
4228 &m_n->gmch_m, &m_n->gmch_n);
4229
4230 compute_m_n(pixel_clock, link_clock,
4231 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4232}
4233
a7615030
CW		 4234static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4235{
72bbe58c
KP		 4236 if (i915_panel_use_ssc >= 0)
4237 return i915_panel_use_ssc != 0;
41aa3448 4238 return dev_priv->vbt.lvds_use_ssc
435793df 4239 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4240}
4241
a0c4da24
JB		 4242static int vlv_get_refclk(struct drm_crtc *crtc)
4243{
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 int refclk = 27000; /* for DP & HDMI */
4247
4248 return 100000; /* only one validated so far */
4249
4250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4251 refclk = 96000;
4252 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4253 if (intel_panel_use_ssc(dev_priv))
4254 refclk = 100000;
4255 else
4256 refclk = 96000;
4257 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4258 refclk = 100000;
4259 }
4260
4261 return refclk;
4262}
4263
c65d77d8
JB		 4264static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4265{
4266 struct drm_device *dev = crtc->dev;
4267 struct drm_i915_private *dev_priv = dev->dev_private;
4268 int refclk;
4269
a0c4da24
JB		 4270 if (IS_VALLEYVIEW(dev)) {
4271 refclk = vlv_get_refclk(crtc);
4272 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4273 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4274 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4275 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4276 refclk / 1000);
4277 } else if (!IS_GEN2(dev)) {
4278 refclk = 96000;
4279 } else {
4280 refclk = 48000;
4281 }
4282
4283 return refclk;
4284}
4285
7429e9d4
DV		 4286static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4287{
4288 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4289}
4290
4291static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4292{
4293 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4294}
4295
f47709a9 4296static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4297 intel_clock_t *reduced_clock)
4298{
f47709a9 4299 struct drm_device *dev = crtc->base.dev;
a7516a05 4300 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4301 int pipe = crtc->pipe;
a7516a05
JB		 4302 u32 fp, fp2 = 0;
4303
4304 if (IS_PINEVIEW(dev)) {
7429e9d4 4305 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4306 if (reduced_clock)
7429e9d4 4307 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4308 } else {
7429e9d4 4309 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4310 if (reduced_clock)
7429e9d4 4311 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4312 }
4313
4314 I915_WRITE(FP0(pipe), fp);
4315
f47709a9
DV		 4316 crtc->lowfreq_avail = false;
4317 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4318 reduced_clock && i915_powersave) {
4319 I915_WRITE(FP1(pipe), fp2);
f47709a9 4320 crtc->lowfreq_avail = true;
a7516a05
JB		 4321 } else {
4322 I915_WRITE(FP1(pipe), fp);
4323 }
4324}
4325
89b667f8
JB		 4326static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4327{
4328 u32 reg_val;
4329
4330 /*
4331 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4332 * and set it to a reasonable value instead.
4333 */
ae99258f 4334 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4335 reg_val &= 0xffffff00;
4336 reg_val |= 0x00000030;
ae99258f 4337 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4338
ae99258f 4339 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4340 reg_val &= 0x8cffffff;
4341 reg_val = 0x8c000000;
ae99258f 4342 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4343
ae99258f 4344 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4345 reg_val &= 0xffffff00;
ae99258f 4346 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4347
ae99258f 4348 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4349 reg_val &= 0x00ffffff;
4350 reg_val |= 0xb0000000;
ae99258f 4351 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4352}
4353
b551842d
DV		 4354static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4355 struct intel_link_m_n *m_n)
4356{
4357 struct drm_device *dev = crtc->base.dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 int pipe = crtc->pipe;
4360
e3b95f1e
DV		 4361 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4362 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4363 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4364 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4365}
4366
4367static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4368 struct intel_link_m_n *m_n)
4369{
4370 struct drm_device *dev = crtc->base.dev;
4371 struct drm_i915_private *dev_priv = dev->dev_private;
4372 int pipe = crtc->pipe;
4373 enum transcoder transcoder = crtc->config.cpu_transcoder;
4374
4375 if (INTEL_INFO(dev)->gen >= 5) {
4376 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4378 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4379 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4380 } else {
e3b95f1e
DV		 4381 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4382 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4383 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4384 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4385 }
4386}
4387
03afc4a2
DV		 4388static void intel_dp_set_m_n(struct intel_crtc *crtc)
4389{
4390 if (crtc->config.has_pch_encoder)
4391 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4392 else
4393 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4394}
4395
f47709a9 4396static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4397{
f47709a9 4398 struct drm_device *dev = crtc->base.dev;
a0c4da24 4399 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4400 struct intel_encoder *encoder;
f47709a9 4401 int pipe = crtc->pipe;
89b667f8 4402 u32 dpll, mdiv;
a0c4da24 4403 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4404 bool is_hdmi;
198a037f 4405 u32 coreclk, reg_val, dpll_md;
a0c4da24 4406
09153000
DV		 4407 mutex_lock(&dev_priv->dpio_lock);
4408
89b667f8 4409 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4410
f47709a9
DV		 4411 bestn = crtc->config.dpll.n;
4412 bestm1 = crtc->config.dpll.m1;
4413 bestm2 = crtc->config.dpll.m2;
4414 bestp1 = crtc->config.dpll.p1;
4415 bestp2 = crtc->config.dpll.p2;
a0c4da24 4416
89b667f8
JB		 4417 /* See eDP HDMI DPIO driver vbios notes doc */
4418
4419 /* PLL B needs special handling */
4420 if (pipe)
4421 vlv_pllb_recal_opamp(dev_priv);
4422
4423 /* Set up Tx target for periodic Rcomp update */
ae99258f 4424 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4425
4426 /* Disable target IRef on PLL */
ae99258f 4427 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4428 reg_val &= 0x00ffffff;
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4430
4431 /* Disable fast lock */
ae99258f 4432 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4433
4434 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4435 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4436 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4437 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4438 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4439
4440 /*
4441 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4442 * but we don't support that).
4443 * Note: don't use the DAC post divider as it seems unstable.
4444 */
4445 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4447
89b667f8 4448 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4450
89b667f8 4451 /* Set HBR and RBR LPF coefficients */
ff9a6750 4452 if (crtc->config.port_clock == 162000 ||
89b667f8 4453 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4454 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4455 0x005f0021);
4456 else
ae99258f 4457 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4458 0x00d0000f);
4459
4460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4461 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4462 /* Use SSC source */
4463 if (!pipe)
ae99258f 4464 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4465 0x0df40000);
4466 else
ae99258f 4467 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4468 0x0df70000);
4469 } else { /* HDMI or VGA */
4470 /* Use bend source */
4471 if (!pipe)
ae99258f 4472 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4473 0x0df70000);
4474 else
ae99258f 4475 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4476 0x0df40000);
4477 }
a0c4da24 4478
ae99258f 4479 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4480 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4482 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4483 coreclk |= 0x01000000;
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4485
ae99258f 4486 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4487
89b667f8
JB		 4488 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4489 if (encoder->pre_pll_enable)
4490 encoder->pre_pll_enable(encoder);
2a8f64ca 4491
89b667f8
JB		 4492 /* Enable DPIO clock input */
4493 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4494 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4495 if (pipe)
4496 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4497
89b667f8 4498 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4499 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
a0c4da24 4502
89b667f8
JB		 4503 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4504 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4505
ef1b460d
DV		 4506 dpll_md = (crtc->config.pixel_multiplier - 1)
4507 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4508 I915_WRITE(DPLL_MD(pipe), dpll_md);
4509 POSTING_READ(DPLL_MD(pipe));
f47709a9 4510
89b667f8
JB		 4511 if (crtc->config.has_dp_encoder)
4512 intel_dp_set_m_n(crtc);
09153000
DV		 4513
4514 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4515}
4516
f47709a9
DV		 4517static void i9xx_update_pll(struct intel_crtc *crtc,
4518 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4519 int num_connectors)
4520{
f47709a9 4521 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4522 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4523 struct intel_encoder *encoder;
f47709a9 4524 int pipe = crtc->pipe;
eb1cbe48
DV		 4525 u32 dpll;
4526 bool is_sdvo;
f47709a9 4527 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4528
f47709a9 4529 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4530
f47709a9
DV		 4531 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4533
4534 dpll = DPLL_VGA_MODE_DIS;
4535
f47709a9 4536 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4537 dpll |= DPLLB_MODE_LVDS;
4538 else
4539 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4540
ef1b460d 4541 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4542 dpll |= (crtc->config.pixel_multiplier - 1)
4543 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4544 }
198a037f
DV		 4545
4546 if (is_sdvo)
4547 dpll |= DPLL_DVO_HIGH_SPEED;
4548
f47709a9 4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4550 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552 /* compute bitmask from p1 value */
4553 if (IS_PINEVIEW(dev))
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4555 else {
4556 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557 if (IS_G4X(dev) && reduced_clock)
4558 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559 }
4560 switch (clock->p2) {
4561 case 5:
4562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563 break;
4564 case 7:
4565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566 break;
4567 case 10:
4568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569 break;
4570 case 14:
4571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572 break;
4573 }
4574 if (INTEL_INFO(dev)->gen >= 4)
4575 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4576
09ede541 4577 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4578 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4579 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4580 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4581 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4582 else
4583 dpll |= PLL_REF_INPUT_DREFCLK;
4584
4585 dpll |= DPLL_VCO_ENABLE;
4586 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4587 POSTING_READ(DPLL(pipe));
4588 udelay(150);
4589
f47709a9 4590 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4591 if (encoder->pre_pll_enable)
4592 encoder->pre_pll_enable(encoder);
eb1cbe48 4593
f47709a9
DV		 4594 if (crtc->config.has_dp_encoder)
4595 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4596
4597 I915_WRITE(DPLL(pipe), dpll);
4598
4599 /* Wait for the clocks to stabilize. */
4600 POSTING_READ(DPLL(pipe));
4601 udelay(150);
4602
4603 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4604 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4605 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4606 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4607 } else {
4608 /* The pixel multiplier can only be updated once the
4609 * DPLL is enabled and the clocks are stable.
4610 *
4611 * So write it again.
4612 */
4613 I915_WRITE(DPLL(pipe), dpll);
4614 }
4615}
4616
f47709a9 4617static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4618 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4619 int num_connectors)
4620{
f47709a9 4621 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4622 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4623 struct intel_encoder *encoder;
f47709a9 4624 int pipe = crtc->pipe;
eb1cbe48 4625 u32 dpll;
f47709a9 4626 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4627
f47709a9 4628 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4629
eb1cbe48
DV		 4630 dpll = DPLL_VGA_MODE_DIS;
4631
f47709a9 4632 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4633 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4634 } else {
4635 if (clock->p1 == 2)
4636 dpll |= PLL_P1_DIVIDE_BY_TWO;
4637 else
4638 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4639 if (clock->p2 == 4)
4640 dpll |= PLL_P2_DIVIDE_BY_4;
4641 }
4642
f47709a9 4643 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4644 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4645 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4646 else
4647 dpll |= PLL_REF_INPUT_DREFCLK;
4648
4649 dpll |= DPLL_VCO_ENABLE;
4650 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4651 POSTING_READ(DPLL(pipe));
4652 udelay(150);
4653
f47709a9 4654 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4655 if (encoder->pre_pll_enable)
4656 encoder->pre_pll_enable(encoder);
eb1cbe48 4657
5b5896e4
DV		 4658 I915_WRITE(DPLL(pipe), dpll);
4659
4660 /* Wait for the clocks to stabilize. */
4661 POSTING_READ(DPLL(pipe));
4662 udelay(150);
4663
eb1cbe48
DV		 4664 /* The pixel multiplier can only be updated once the
4665 * DPLL is enabled and the clocks are stable.
4666 *
4667 * So write it again.
4668 */
4669 I915_WRITE(DPLL(pipe), dpll);
4670}
4671
8a654f3b 4672static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4673{
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4677 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4678 struct drm_display_mode *adjusted_mode =
4679 &intel_crtc->config.adjusted_mode;
4680 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4681 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4682
4683 /* We need to be careful not to changed the adjusted mode, for otherwise
4684 * the hw state checker will get angry at the mismatch. */
4685 crtc_vtotal = adjusted_mode->crtc_vtotal;
4686 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4687
4688 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4689 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4690 crtc_vtotal -= 1;
4691 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4692 vsyncshift = adjusted_mode->crtc_hsync_start
4693 - adjusted_mode->crtc_htotal / 2;
4694 } else {
4695 vsyncshift = 0;
4696 }
4697
4698 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4699 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4700
fe2b8f9d 4701 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4702 (adjusted_mode->crtc_hdisplay - 1) |
4703 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4704 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4705 (adjusted_mode->crtc_hblank_start - 1) |
4706 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4707 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4708 (adjusted_mode->crtc_hsync_start - 1) |
4709 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4710
fe2b8f9d 4711 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4712 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4713 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4714 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4715 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4716 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4717 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4718 (adjusted_mode->crtc_vsync_start - 1) |
4719 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4720
b5e508d4
PZ		 4721 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4722 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4723 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4724 * bits. */
4725 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4726 (pipe == PIPE_B || pipe == PIPE_C))
4727 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4728
b0e77b9c
PZ		 4729 /* pipesrc controls the size that is scaled from, which should
4730 * always be the user's requested size.
4731 */
4732 I915_WRITE(PIPESRC(pipe),
4733 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4734}
4735
1bd1bd80
DV		 4736static void intel_get_pipe_timings(struct intel_crtc *crtc,
4737 struct intel_crtc_config *pipe_config)
4738{
4739 struct drm_device *dev = crtc->base.dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4742 uint32_t tmp;
4743
4744 tmp = I915_READ(HTOTAL(cpu_transcoder));
4745 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4746 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4747 tmp = I915_READ(HBLANK(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4750 tmp = I915_READ(HSYNC(cpu_transcoder));
4751 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4752 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4753
4754 tmp = I915_READ(VTOTAL(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(VBLANK(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4760 tmp = I915_READ(VSYNC(cpu_transcoder));
4761 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4763
4764 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4765 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4766 pipe_config->adjusted_mode.crtc_vtotal += 1;
4767 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4768 }
4769
4770 tmp = I915_READ(PIPESRC(crtc->pipe));
4771 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4772 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4773}
4774
84b046f3
DV		 4775static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4776{
4777 struct drm_device *dev = intel_crtc->base.dev;
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 uint32_t pipeconf;
4780
4781 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4782
4783 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4784 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4785 * core speed.
4786 *
4787 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4788 * pipe == 0 check?
4789 */
4790 if (intel_crtc->config.requested_mode.clock >
4791 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4792 pipeconf |= PIPECONF_DOUBLE_WIDE;
4793 else
4794 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4795 }
4796
ff9ce46e
DV		 4797 /* only g4x and later have fancy bpc/dither controls */
4798 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4799 pipeconf &= ~(PIPECONF_BPC_MASK |
4800 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4801
4802 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4803 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4804 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4805 PIPECONF_DITHER_TYPE_SP;
84b046f3 4806
ff9ce46e
DV		 4807 switch (intel_crtc->config.pipe_bpp) {
4808 case 18:
4809 pipeconf |= PIPECONF_6BPC;
4810 break;
4811 case 24:
4812 pipeconf |= PIPECONF_8BPC;
4813 break;
4814 case 30:
4815 pipeconf |= PIPECONF_10BPC;
4816 break;
4817 default:
4818 /* Case prevented by intel_choose_pipe_bpp_dither. */
4819 BUG();
84b046f3
DV		 4820 }
4821 }
4822
4823 if (HAS_PIPE_CXSR(dev)) {
4824 if (intel_crtc->lowfreq_avail) {
4825 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4826 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4827 } else {
4828 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4829 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4830 }
4831 }
4832
4833 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4834 if (!IS_GEN2(dev) &&
4835 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4836 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4837 else
4838 pipeconf |= PIPECONF_PROGRESSIVE;
4839
9c8e09b7
VS		 4840 if (IS_VALLEYVIEW(dev)) {
4841 if (intel_crtc->config.limited_color_range)
4842 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4843 else
4844 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4845 }
4846
84b046f3
DV		 4847 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4848 POSTING_READ(PIPECONF(intel_crtc->pipe));
4849}
4850
f564048e 4851static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4852 int x, int y,
94352cf9 4853 struct drm_framebuffer *fb)
79e53945
JB		 4854{
4855 struct drm_device *dev = crtc->dev;
4856 struct drm_i915_private *dev_priv = dev->dev_private;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4858 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4859 int pipe = intel_crtc->pipe;
80824003 4860 int plane = intel_crtc->plane;
c751ce4f 4861 int refclk, num_connectors = 0;
652c393a 4862 intel_clock_t clock, reduced_clock;
84b046f3 4863 u32 dspcntr;
a16af721
DV		 4864 bool ok, has_reduced_clock = false;
4865 bool is_lvds = false;
5eddb70b 4866 struct intel_encoder *encoder;
d4906093 4867 const intel_limit_t *limit;
5c3b82e2 4868 int ret;
79e53945 4869
6c2b7c12 4870 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4871 switch (encoder->type) {
79e53945
JB		 4872 case INTEL_OUTPUT_LVDS:
4873 is_lvds = true;
4874 break;
79e53945 4875 }
43565a06 4876
c751ce4f 4877 num_connectors++;
79e53945
JB		 4878 }
4879
c65d77d8 4880 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4881
d4906093
ML		 4882 /*
4883 * Returns a set of divisors for the desired target clock with the given
4884 * refclk, or FALSE. The returned values represent the clock equation:
4885 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4886 */
1b894b59 4887 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4888 ok = dev_priv->display.find_dpll(limit, crtc,
4889 intel_crtc->config.port_clock,
ee9300bb
DV		 4890 refclk, NULL, &clock);
4891 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4892 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4893 return -EINVAL;
79e53945
JB		 4894 }
4895
cda4b7d3 4896 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4897 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4898
ddc9003c 4899 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4900 /*
4901 * Ensure we match the reduced clock's P to the target clock.
4902 * If the clocks don't match, we can't switch the display clock
4903 * by using the FP0/FP1. In such case we will disable the LVDS
4904 * downclock feature.
4905 */
ee9300bb
DV		 4906 has_reduced_clock =
4907 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4908 dev_priv->lvds_downclock,
ee9300bb 4909 refclk, &clock,
5eddb70b 4910 &reduced_clock);
7026d4ac 4911 }
f47709a9
DV		 4912 /* Compat-code for transition, will disappear. */
4913 if (!intel_crtc->config.clock_set) {
4914 intel_crtc->config.dpll.n = clock.n;
4915 intel_crtc->config.dpll.m1 = clock.m1;
4916 intel_crtc->config.dpll.m2 = clock.m2;
4917 intel_crtc->config.dpll.p1 = clock.p1;
4918 intel_crtc->config.dpll.p2 = clock.p2;
4919 }
7026d4ac 4920
eb1cbe48 4921 if (IS_GEN2(dev))
8a654f3b 4922 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4923 has_reduced_clock ? &reduced_clock : NULL,
4924 num_connectors);
a0c4da24 4925 else if (IS_VALLEYVIEW(dev))
f47709a9 4926 vlv_update_pll(intel_crtc);
79e53945 4927 else
f47709a9 4928 i9xx_update_pll(intel_crtc,
eb1cbe48 4929 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4930 num_connectors);
79e53945 4931
79e53945
JB		 4932 /* Set up the display plane register */
4933 dspcntr = DISPPLANE_GAMMA_ENABLE;
4934
da6ecc5d
JB		 4935 if (!IS_VALLEYVIEW(dev)) {
4936 if (pipe == 0)
4937 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4938 else
4939 dspcntr |= DISPPLANE_SEL_PIPE_B;
4940 }
79e53945 4941
8a654f3b 4942 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4943
4944 /* pipesrc and dspsize control the size that is scaled from,
4945 * which should always be the user's requested size.
79e53945 4946 */
929c77fb
EA		 4947 I915_WRITE(DSPSIZE(plane),
4948 ((mode->vdisplay - 1) << 16) |
4949 (mode->hdisplay - 1));
4950 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4951
84b046f3
DV		 4952 i9xx_set_pipeconf(intel_crtc);
4953
f564048e
EA		 4954 I915_WRITE(DSPCNTR(plane), dspcntr);
4955 POSTING_READ(DSPCNTR(plane));
4956
94352cf9 4957 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4958
4959 intel_update_watermarks(dev);
4960
f564048e
EA		 4961 return ret;
4962}
4963
2fa2fe9a
DV		 4964static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4965 struct intel_crtc_config *pipe_config)
4966{
4967 struct drm_device *dev = crtc->base.dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 uint32_t tmp;
4970
4971 tmp = I915_READ(PFIT_CONTROL);
4972
4973 if (INTEL_INFO(dev)->gen < 4) {
4974 if (crtc->pipe != PIPE_B)
4975 return;
4976
4977 /* gen2/3 store dither state in pfit control, needs to match */
4978 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4979 } else {
4980 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4981 return;
4982 }
4983
4984 if (!(tmp & PFIT_ENABLE))
4985 return;
4986
4987 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4988 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4989 if (INTEL_INFO(dev)->gen < 5)
4990 pipe_config->gmch_pfit.lvds_border_bits =
4991 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4992}
4993
0e8ffe1b
DV		 4994static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4995 struct intel_crtc_config *pipe_config)
4996{
4997 struct drm_device *dev = crtc->base.dev;
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 uint32_t tmp;
5000
eccb140b 5001 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5002 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5003
0e8ffe1b
DV		 5004 tmp = I915_READ(PIPECONF(crtc->pipe));
5005 if (!(tmp & PIPECONF_ENABLE))
5006 return false;
5007
1bd1bd80
DV		 5008 intel_get_pipe_timings(crtc, pipe_config);
5009
2fa2fe9a
DV		 5010 i9xx_get_pfit_config(crtc, pipe_config);
5011
6c49f241
DV		 5012 if (INTEL_INFO(dev)->gen >= 4) {
5013 tmp = I915_READ(DPLL_MD(crtc->pipe));
5014 pipe_config->pixel_multiplier =
5015 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5016 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5017 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5018 tmp = I915_READ(DPLL(crtc->pipe));
5019 pipe_config->pixel_multiplier =
5020 ((tmp & SDVO_MULTIPLIER_MASK)
5021 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5022 } else {
5023 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5024 * port and will be fixed up in the encoder->get_config
5025 * function. */
5026 pipe_config->pixel_multiplier = 1;
5027 }
5028
0e8ffe1b
DV		 5029 return true;
5030}
5031
dde86e2d 5032static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5033{
5034 struct drm_i915_private *dev_priv = dev->dev_private;
5035 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5036 struct intel_encoder *encoder;
74cfd7ac 5037 u32 val, final;
13d83a67 5038 bool has_lvds = false;
199e5d79 5039 bool has_cpu_edp = false;
199e5d79 5040 bool has_panel = false;
99eb6a01
KP		 5041 bool has_ck505 = false;
5042 bool can_ssc = false;
13d83a67
JB		 5043
5044 /* We need to take the global config into account */
199e5d79
KP		 5045 list_for_each_entry(encoder, &mode_config->encoder_list,
5046 base.head) {
5047 switch (encoder->type) {
5048 case INTEL_OUTPUT_LVDS:
5049 has_panel = true;
5050 has_lvds = true;
5051 break;
5052 case INTEL_OUTPUT_EDP:
5053 has_panel = true;
2de6905f 5054 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5055 has_cpu_edp = true;
5056 break;
13d83a67
JB		 5057 }
5058 }
5059
99eb6a01 5060 if (HAS_PCH_IBX(dev)) {
41aa3448 5061 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5062 can_ssc = has_ck505;
5063 } else {
5064 has_ck505 = false;
5065 can_ssc = true;
5066 }
5067
2de6905f
ID		 5068 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5069 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5070
5071 /* Ironlake: try to setup display ref clock before DPLL
5072 * enabling. This is only under driver's control after
5073 * PCH B stepping, previous chipset stepping should be
5074 * ignoring this setting.
5075 */
74cfd7ac
CW		 5076 val = I915_READ(PCH_DREF_CONTROL);
5077
5078 /* As we must carefully and slowly disable/enable each source in turn,
5079 * compute the final state we want first and check if we need to
5080 * make any changes at all.
5081 */
5082 final = val;
5083 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5084 if (has_ck505)
5085 final |= DREF_NONSPREAD_CK505_ENABLE;
5086 else
5087 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5088
5089 final &= ~DREF_SSC_SOURCE_MASK;
5090 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5091 final &= ~DREF_SSC1_ENABLE;
5092
5093 if (has_panel) {
5094 final |= DREF_SSC_SOURCE_ENABLE;
5095
5096 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5097 final |= DREF_SSC1_ENABLE;
5098
5099 if (has_cpu_edp) {
5100 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5101 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5102 else
5103 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5104 } else
5105 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5106 } else {
5107 final |= DREF_SSC_SOURCE_DISABLE;
5108 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5109 }
5110
5111 if (final == val)
5112 return;
5113
13d83a67 5114 /* Always enable nonspread source */
74cfd7ac 5115 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5116
99eb6a01 5117 if (has_ck505)
74cfd7ac 5118 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5119 else
74cfd7ac 5120 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5121
199e5d79 5122 if (has_panel) {
74cfd7ac
CW		 5123 val &= ~DREF_SSC_SOURCE_MASK;
5124 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5125
199e5d79 5126 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5127 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5128 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5129 val |= DREF_SSC1_ENABLE;
e77166b5 5130 } else
74cfd7ac 5131 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5132
5133 /* Get SSC going before enabling the outputs */
74cfd7ac 5134 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5135 POSTING_READ(PCH_DREF_CONTROL);
5136 udelay(200);
5137
74cfd7ac 5138 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5139
5140 /* Enable CPU source on CPU attached eDP */
199e5d79 5141 if (has_cpu_edp) {
99eb6a01 5142 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5143 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5144 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5145 }
13d83a67 5146 else
74cfd7ac 5147 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5148 } else
74cfd7ac 5149 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5150
74cfd7ac 5151 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5152 POSTING_READ(PCH_DREF_CONTROL);
5153 udelay(200);
5154 } else {
5155 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5156
74cfd7ac 5157 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5158
5159 /* Turn off CPU output */
74cfd7ac 5160 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5161
74cfd7ac 5162 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5163 POSTING_READ(PCH_DREF_CONTROL);
5164 udelay(200);
5165
5166 /* Turn off the SSC source */
74cfd7ac
CW		 5167 val &= ~DREF_SSC_SOURCE_MASK;
5168 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5169
5170 /* Turn off SSC1 */
74cfd7ac 5171 val &= ~DREF_SSC1_ENABLE;
199e5d79 5172
74cfd7ac 5173 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5174 POSTING_READ(PCH_DREF_CONTROL);
5175 udelay(200);
5176 }
74cfd7ac
CW		 5177
5178 BUG_ON(val != final);
13d83a67
JB		 5179}
5180
dde86e2d
PZ		 5181/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5182static void lpt_init_pch_refclk(struct drm_device *dev)
5183{
5184 struct drm_i915_private *dev_priv = dev->dev_private;
5185 struct drm_mode_config *mode_config = &dev->mode_config;
5186 struct intel_encoder *encoder;
5187 bool has_vga = false;
5188 bool is_sdv = false;
5189 u32 tmp;
5190
5191 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5192 switch (encoder->type) {
5193 case INTEL_OUTPUT_ANALOG:
5194 has_vga = true;
5195 break;
5196 }
5197 }
5198
5199 if (!has_vga)
5200 return;
5201
c00db246
DV		 5202 mutex_lock(&dev_priv->dpio_lock);
5203
dde86e2d
PZ		 5204 /* XXX: Rip out SDV support once Haswell ships for real. */
5205 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5206 is_sdv = true;
5207
5208 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5209 tmp &= ~SBI_SSCCTL_DISABLE;
5210 tmp |= SBI_SSCCTL_PATHALT;
5211 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5212
5213 udelay(24);
5214
5215 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5216 tmp &= ~SBI_SSCCTL_PATHALT;
5217 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5218
5219 if (!is_sdv) {
5220 tmp = I915_READ(SOUTH_CHICKEN2);
5221 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5222 I915_WRITE(SOUTH_CHICKEN2, tmp);
5223
5224 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5225 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5226 DRM_ERROR("FDI mPHY reset assert timeout\n");
5227
5228 tmp = I915_READ(SOUTH_CHICKEN2);
5229 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5230 I915_WRITE(SOUTH_CHICKEN2, tmp);
5231
5232 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5233 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5234 100))
5235 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5236 }
5237
5238 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5239 tmp &= ~(0xFF << 24);
5240 tmp |= (0x12 << 24);
5241 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5242
dde86e2d
PZ		 5243 if (is_sdv) {
5244 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5245 tmp |= 0x7FFF;
5246 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5247 }
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5250 tmp |= (1 << 11);
5251 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5252
5253 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5254 tmp |= (1 << 11);
5255 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5256
5257 if (is_sdv) {
5258 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5259 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5260 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5261
5262 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5263 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5264 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5265
5266 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5267 tmp |= (0x3F << 8);
5268 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5271 tmp |= (0x3F << 8);
5272 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5273 }
5274
5275 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5276 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5277 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5280 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5281 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5282
5283 if (!is_sdv) {
5284 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5285 tmp &= ~(7 << 13);
5286 tmp |= (5 << 13);
5287 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5290 tmp &= ~(7 << 13);
5291 tmp |= (5 << 13);
5292 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5293 }
5294
5295 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5296 tmp &= ~0xFF;
5297 tmp |= 0x1C;
5298 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5299
5300 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5301 tmp &= ~0xFF;
5302 tmp |= 0x1C;
5303 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5306 tmp &= ~(0xFF << 16);
5307 tmp |= (0x1C << 16);
5308 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5311 tmp &= ~(0xFF << 16);
5312 tmp |= (0x1C << 16);
5313 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5314
5315 if (!is_sdv) {
5316 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5317 tmp |= (1 << 27);
5318 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5319
5320 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5321 tmp |= (1 << 27);
5322 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5323
5324 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5325 tmp &= ~(0xF << 28);
5326 tmp |= (4 << 28);
5327 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5328
5329 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5330 tmp &= ~(0xF << 28);
5331 tmp |= (4 << 28);
5332 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5333 }
5334
5335 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5336 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5337 tmp |= SBI_DBUFF0_ENABLE;
5338 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5339
5340 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5341}
5342
5343/*
5344 * Initialize reference clocks when the driver loads
5345 */
5346void intel_init_pch_refclk(struct drm_device *dev)
5347{
5348 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5349 ironlake_init_pch_refclk(dev);
5350 else if (HAS_PCH_LPT(dev))
5351 lpt_init_pch_refclk(dev);
5352}
5353
d9d444cb
JB		 5354static int ironlake_get_refclk(struct drm_crtc *crtc)
5355{
5356 struct drm_device *dev = crtc->dev;
5357 struct drm_i915_private *dev_priv = dev->dev_private;
5358 struct intel_encoder *encoder;
d9d444cb
JB		 5359 int num_connectors = 0;
5360 bool is_lvds = false;
5361
6c2b7c12 5362 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5363 switch (encoder->type) {
5364 case INTEL_OUTPUT_LVDS:
5365 is_lvds = true;
5366 break;
d9d444cb
JB		 5367 }
5368 num_connectors++;
5369 }
5370
5371 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5372 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5373 dev_priv->vbt.lvds_ssc_freq);
5374 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5375 }
5376
5377 return 120000;
5378}
5379
6ff93609 5380static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5381{
c8203565 5382 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384 int pipe = intel_crtc->pipe;
c8203565
PZ		 5385 uint32_t val;
5386
5387 val = I915_READ(PIPECONF(pipe));
5388
dfd07d72 5389 val &= ~PIPECONF_BPC_MASK;
965e0c48 5390 switch (intel_crtc->config.pipe_bpp) {
c8203565 5391 case 18:
dfd07d72 5392 val |= PIPECONF_6BPC;
c8203565
PZ		 5393 break;
5394 case 24:
dfd07d72 5395 val |= PIPECONF_8BPC;
c8203565
PZ		 5396 break;
5397 case 30:
dfd07d72 5398 val |= PIPECONF_10BPC;
c8203565
PZ		 5399 break;
5400 case 36:
dfd07d72 5401 val |= PIPECONF_12BPC;
c8203565
PZ		 5402 break;
5403 default:
cc769b62
PZ		 5404 /* Case prevented by intel_choose_pipe_bpp_dither. */
5405 BUG();
c8203565
PZ		 5406 }
5407
5408 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5409 if (intel_crtc->config.dither)
c8203565
PZ		 5410 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5411
5412 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5413 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5414 val |= PIPECONF_INTERLACED_ILK;
5415 else
5416 val |= PIPECONF_PROGRESSIVE;
5417
50f3b016 5418 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5419 val |= PIPECONF_COLOR_RANGE_SELECT;
5420 else
5421 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5422
c8203565
PZ		 5423 I915_WRITE(PIPECONF(pipe), val);
5424 POSTING_READ(PIPECONF(pipe));
5425}
5426
86d3efce
VS		 5427/*
5428 * Set up the pipe CSC unit.
5429 *
5430 * Currently only full range RGB to limited range RGB conversion
5431 * is supported, but eventually this should handle various
5432 * RGB<->YCbCr scenarios as well.
5433 */
50f3b016 5434static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5435{
5436 struct drm_device *dev = crtc->dev;
5437 struct drm_i915_private *dev_priv = dev->dev_private;
5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439 int pipe = intel_crtc->pipe;
5440 uint16_t coeff = 0x7800; /* 1.0 */
5441
5442 /*
5443 * TODO: Check what kind of values actually come out of the pipe
5444 * with these coeff/postoff values and adjust to get the best
5445 * accuracy. Perhaps we even need to take the bpc value into
5446 * consideration.
5447 */
5448
50f3b016 5449 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5450 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5451
5452 /*
5453 * GY/GU and RY/RU should be the other way around according
5454 * to BSpec, but reality doesn't agree. Just set them up in
5455 * a way that results in the correct picture.
5456 */
5457 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5458 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5459
5460 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5461 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5462
5463 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5464 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5465
5466 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5467 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5468 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5469
5470 if (INTEL_INFO(dev)->gen > 6) {
5471 uint16_t postoff = 0;
5472
50f3b016 5473 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5474 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5475
5476 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5477 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5478 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5479
5480 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5481 } else {
5482 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5483
50f3b016 5484 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5485 mode |= CSC_BLACK_SCREEN_OFFSET;
5486
5487 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5488 }
5489}
5490
6ff93609 5491static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5492{
5493 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5495 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5496 uint32_t val;
5497
702e7a56 5498 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5499
5500 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5501 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5502 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5503
5504 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5505 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5506 val |= PIPECONF_INTERLACED_ILK;
5507 else
5508 val |= PIPECONF_PROGRESSIVE;
5509
702e7a56
PZ		 5510 I915_WRITE(PIPECONF(cpu_transcoder), val);
5511 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5512}
5513
6591c6e4 5514static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5515 intel_clock_t *clock,
5516 bool *has_reduced_clock,
5517 intel_clock_t *reduced_clock)
5518{
5519 struct drm_device *dev = crtc->dev;
5520 struct drm_i915_private *dev_priv = dev->dev_private;
5521 struct intel_encoder *intel_encoder;
5522 int refclk;
d4906093 5523 const intel_limit_t *limit;
a16af721 5524 bool ret, is_lvds = false;
79e53945 5525
6591c6e4
PZ		 5526 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5527 switch (intel_encoder->type) {
79e53945
JB		 5528 case INTEL_OUTPUT_LVDS:
5529 is_lvds = true;
5530 break;
79e53945
JB		 5531 }
5532 }
5533
d9d444cb 5534 refclk = ironlake_get_refclk(crtc);
79e53945 5535
d4906093
ML		 5536 /*
5537 * Returns a set of divisors for the desired target clock with the given
5538 * refclk, or FALSE. The returned values represent the clock equation:
5539 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5540 */
1b894b59 5541 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5542 ret = dev_priv->display.find_dpll(limit, crtc,
5543 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5544 refclk, NULL, clock);
6591c6e4
PZ		 5545 if (!ret)
5546 return false;
cda4b7d3 5547
ddc9003c 5548 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5549 /*
5550 * Ensure we match the reduced clock's P to the target clock.
5551 * If the clocks don't match, we can't switch the display clock
5552 * by using the FP0/FP1. In such case we will disable the LVDS
5553 * downclock feature.
5554 */
ee9300bb
DV		 5555 *has_reduced_clock =
5556 dev_priv->display.find_dpll(limit, crtc,
5557 dev_priv->lvds_downclock,
5558 refclk, clock,
5559 reduced_clock);
652c393a 5560 }
61e9653f 5561
6591c6e4
PZ		 5562 return true;
5563}
5564
01a415fd
DV		 5565static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5566{
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 uint32_t temp;
5569
5570 temp = I915_READ(SOUTH_CHICKEN1);
5571 if (temp & FDI_BC_BIFURCATION_SELECT)
5572 return;
5573
5574 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5575 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5576
5577 temp |= FDI_BC_BIFURCATION_SELECT;
5578 DRM_DEBUG_KMS("enabling fdi C rx\n");
5579 I915_WRITE(SOUTH_CHICKEN1, temp);
5580 POSTING_READ(SOUTH_CHICKEN1);
5581}
5582
ebfd86fd
DV		 5583static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5584{
5585 struct drm_device *dev = intel_crtc->base.dev;
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587
5588 switch (intel_crtc->pipe) {
5589 case PIPE_A:
5590 break;
5591 case PIPE_B:
5592 if (intel_crtc->config.fdi_lanes > 2)
5593 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5594 else
5595 cpt_enable_fdi_bc_bifurcation(dev);
5596
5597 break;
5598 case PIPE_C:
01a415fd
DV		 5599 cpt_enable_fdi_bc_bifurcation(dev);
5600
ebfd86fd 5601 break;
01a415fd
DV		 5602 default:
5603 BUG();
5604 }
5605}
5606
d4b1931c
PZ		 5607int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5608{
5609 /*
5610 * Account for spread spectrum to avoid
5611 * oversubscribing the link. Max center spread
5612 * is 2.5%; use 5% for safety's sake.
5613 */
5614 u32 bps = target_clock * bpp * 21 / 20;
5615 return bps / (link_bw * 8) + 1;
5616}
5617
7429e9d4
DV		 5618static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5619{
5620 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5621}
5622
de13a2e3 5623static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5624 u32 *fp,
9a7c7890 5625 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5626{
de13a2e3 5627 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5628 struct drm_device *dev = crtc->dev;
5629 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5630 struct intel_encoder *intel_encoder;
5631 uint32_t dpll;
6cc5f341 5632 int factor, num_connectors = 0;
09ede541 5633 bool is_lvds = false, is_sdvo = false;
79e53945 5634
de13a2e3
PZ		 5635 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5636 switch (intel_encoder->type) {
79e53945
JB		 5637 case INTEL_OUTPUT_LVDS:
5638 is_lvds = true;
5639 break;
5640 case INTEL_OUTPUT_SDVO:
7d57382e 5641 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5642 is_sdvo = true;
5643 break;
79e53945 5644 }
43565a06 5645
c751ce4f 5646 num_connectors++;
79e53945 5647 }
79e53945 5648
c1858123 5649 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5650 factor = 21;
5651 if (is_lvds) {
5652 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5653 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5654 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5655 factor = 25;
09ede541 5656 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5657 factor = 20;
c1858123 5658
7429e9d4 5659 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5660 *fp |= FP_CB_TUNE;
2c07245f 5661
9a7c7890
DV		 5662 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5663 *fp2 |= FP_CB_TUNE;
5664
5eddb70b 5665 dpll = 0;
2c07245f 5666
a07d6787
EA		 5667 if (is_lvds)
5668 dpll |= DPLLB_MODE_LVDS;
5669 else
5670 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5671
ef1b460d
DV		 5672 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5673 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5674
5675 if (is_sdvo)
5676 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5677 if (intel_crtc->config.has_dp_encoder)
a07d6787 5678 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5679
a07d6787 5680 /* compute bitmask from p1 value */
7429e9d4 5681 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5682 /* also FPA1 */
7429e9d4 5683 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5684
7429e9d4 5685 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5686 case 5:
5687 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5688 break;
5689 case 7:
5690 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5691 break;
5692 case 10:
5693 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5694 break;
5695 case 14:
5696 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5697 break;
79e53945
JB		 5698 }
5699
b4c09f3b 5700 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5701 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5702 else
5703 dpll |= PLL_REF_INPUT_DREFCLK;
5704
de13a2e3
PZ		 5705 return dpll;
5706}
5707
5708static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5709 int x, int y,
5710 struct drm_framebuffer *fb)
5711{
5712 struct drm_device *dev = crtc->dev;
5713 struct drm_i915_private *dev_priv = dev->dev_private;
5714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5715 int pipe = intel_crtc->pipe;
5716 int plane = intel_crtc->plane;
5717 int num_connectors = 0;
5718 intel_clock_t clock, reduced_clock;
cbbab5bd 5719 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5720 bool ok, has_reduced_clock = false;
8b47047b 5721 bool is_lvds = false;
de13a2e3 5722 struct intel_encoder *encoder;
e2b78267 5723 struct intel_shared_dpll *pll;
de13a2e3 5724 int ret;
de13a2e3
PZ		 5725
5726 for_each_encoder_on_crtc(dev, crtc, encoder) {
5727 switch (encoder->type) {
5728 case INTEL_OUTPUT_LVDS:
5729 is_lvds = true;
5730 break;
de13a2e3
PZ		 5731 }
5732
5733 num_connectors++;
a07d6787 5734 }
79e53945 5735
5dc5298b
PZ		 5736 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5737 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5738
ff9a6750 5739 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5740 &has_reduced_clock, &reduced_clock);
ee9300bb 5741 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5742 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5743 return -EINVAL;
79e53945 5744 }
f47709a9
DV		 5745 /* Compat-code for transition, will disappear. */
5746 if (!intel_crtc->config.clock_set) {
5747 intel_crtc->config.dpll.n = clock.n;
5748 intel_crtc->config.dpll.m1 = clock.m1;
5749 intel_crtc->config.dpll.m2 = clock.m2;
5750 intel_crtc->config.dpll.p1 = clock.p1;
5751 intel_crtc->config.dpll.p2 = clock.p2;
5752 }
79e53945 5753
de13a2e3
PZ		 5754 /* Ensure that the cursor is valid for the new mode before changing... */
5755 intel_crtc_update_cursor(crtc, true);
5756
5dc5298b 5757 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5758 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5759 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5760 if (has_reduced_clock)
7429e9d4 5761 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5762
7429e9d4 5763 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5764 &fp, &reduced_clock,
5765 has_reduced_clock ? &fp2 : NULL);
5766
e72f9fbf 5767 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5768 if (pll == NULL) {
84f44ce7
VS		 5769 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5770 pipe_name(pipe));
4b645f14
JB		 5771 return -EINVAL;
5772 }
ee7b9f93 5773 } else
e72f9fbf 5774 intel_put_shared_dpll(intel_crtc);
79e53945 5775
03afc4a2
DV		 5776 if (intel_crtc->config.has_dp_encoder)
5777 intel_dp_set_m_n(intel_crtc);
79e53945 5778
dafd226c
DV		 5779 for_each_encoder_on_crtc(dev, crtc, encoder)
5780 if (encoder->pre_pll_enable)
5781 encoder->pre_pll_enable(encoder);
79e53945 5782
e2b78267
DV		 5783 intel_crtc->lowfreq_avail = false;
5784
5785 if (intel_crtc->config.has_pch_encoder) {
5786 pll = intel_crtc_to_shared_dpll(intel_crtc);
5787
e9a632a5 5788 I915_WRITE(PCH_DPLL(pll->id), dpll);
5eddb70b 5789
32f9d658 5790 /* Wait for the clocks to stabilize. */
e9a632a5 5791 POSTING_READ(PCH_DPLL(pll->id));
32f9d658
ZW		 5792 udelay(150);
5793
8febb297
EA		 5794 /* The pixel multiplier can only be updated once the
5795 * DPLL is enabled and the clocks are stable.
5796 *
5797 * So write it again.
5798 */
e9a632a5 5799 I915_WRITE(PCH_DPLL(pll->id), dpll);
79e53945 5800
4b645f14 5801 if (is_lvds && has_reduced_clock && i915_powersave) {
e9a632a5 5802 I915_WRITE(PCH_FP1(pll->id), fp2);
4b645f14 5803 intel_crtc->lowfreq_avail = true;
4b645f14 5804 } else {
e9a632a5 5805 I915_WRITE(PCH_FP1(pll->id), fp);
652c393a
JB		 5806 }
5807 }
5808
8a654f3b 5809 intel_set_pipe_timings(intel_crtc);
5eddb70b 5810
ca3a0ff8 5811 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5812 intel_cpu_transcoder_set_m_n(intel_crtc,
5813 &intel_crtc->config.fdi_m_n);
5814 }
2c07245f 5815
ebfd86fd
DV		 5816 if (IS_IVYBRIDGE(dev))
5817 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5818
6ff93609 5819 ironlake_set_pipeconf(crtc);
79e53945 5820
a1f9e77e
PZ		 5821 /* Set up the display plane register */
5822 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5823 POSTING_READ(DSPCNTR(plane));
79e53945 5824
94352cf9 5825 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5826
5827 intel_update_watermarks(dev);
5828
1857e1da 5829 return ret;
79e53945
JB		 5830}
5831
72419203
DV		 5832static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5833 struct intel_crtc_config *pipe_config)
5834{
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 enum transcoder transcoder = pipe_config->cpu_transcoder;
5838
5839 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5840 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5841 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5842 & ~TU_SIZE_MASK;
5843 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5844 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5845 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5846}
5847
2fa2fe9a
DV		 5848static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5849 struct intel_crtc_config *pipe_config)
5850{
5851 struct drm_device *dev = crtc->base.dev;
5852 struct drm_i915_private *dev_priv = dev->dev_private;
5853 uint32_t tmp;
5854
5855 tmp = I915_READ(PF_CTL(crtc->pipe));
5856
5857 if (tmp & PF_ENABLE) {
5858 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5859 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5860
5861 /* We currently do not free assignements of panel fitters on
5862 * ivb/hsw (since we don't use the higher upscaling modes which
5863 * differentiates them) so just WARN about this case for now. */
5864 if (IS_GEN7(dev)) {
5865 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5866 PF_PIPE_SEL_IVB(crtc->pipe));
5867 }
2fa2fe9a
DV		 5868 }
5869}
5870
0e8ffe1b
DV		 5871static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5872 struct intel_crtc_config *pipe_config)
5873{
5874 struct drm_device *dev = crtc->base.dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 uint32_t tmp;
5877
eccb140b 5878 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5879 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5880
0e8ffe1b
DV		 5881 tmp = I915_READ(PIPECONF(crtc->pipe));
5882 if (!(tmp & PIPECONF_ENABLE))
5883 return false;
5884
ab9412ba 5885 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5886 pipe_config->has_pch_encoder = true;
5887
627eb5a3
DV		 5888 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5889 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5890 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5891
5892 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5893
5894 /* XXX: Can't properly read out the pch dpll pixel multiplier
5895 * since we don't have state tracking for pch clocks yet. */
5896 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5897
5898 if (HAS_PCH_IBX(dev_priv->dev)) {
5899 pipe_config->shared_dpll = crtc->pipe;
5900 } else {
5901 tmp = I915_READ(PCH_DPLL_SEL);
5902 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5903 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5904 else
5905 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5906 }
6c49f241
DV		 5907 } else {
5908 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5909 }
5910
1bd1bd80
DV		 5911 intel_get_pipe_timings(crtc, pipe_config);
5912
2fa2fe9a
DV		 5913 ironlake_get_pfit_config(crtc, pipe_config);
5914
0e8ffe1b
DV		 5915 return true;
5916}
5917
d6dd9eb1
DV		 5918static void haswell_modeset_global_resources(struct drm_device *dev)
5919{
d6dd9eb1
DV		 5920 bool enable = false;
5921 struct intel_crtc *crtc;
d6dd9eb1
DV		 5922
5923 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5924 if (!crtc->base.enabled)
5925 continue;
d6dd9eb1 5926
e7a639c4
DV		 5927 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5928 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5929 enable = true;
5930 }
5931
d6dd9eb1
DV		 5932 intel_set_power_well(dev, enable);
5933}
5934
09b4ddf9 5935static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5936 int x, int y,
5937 struct drm_framebuffer *fb)
5938{
5939 struct drm_device *dev = crtc->dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5942 int plane = intel_crtc->plane;
09b4ddf9 5943 int ret;
09b4ddf9 5944
ff9a6750 5945 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5946 return -EINVAL;
5947
09b4ddf9
PZ		 5948 /* Ensure that the cursor is valid for the new mode before changing... */
5949 intel_crtc_update_cursor(crtc, true);
5950
03afc4a2
DV		 5951 if (intel_crtc->config.has_dp_encoder)
5952 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5953
5954 intel_crtc->lowfreq_avail = false;
09b4ddf9 5955
8a654f3b 5956 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5957
ca3a0ff8 5958 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5959 intel_cpu_transcoder_set_m_n(intel_crtc,
5960 &intel_crtc->config.fdi_m_n);
5961 }
09b4ddf9 5962
6ff93609 5963 haswell_set_pipeconf(crtc);
09b4ddf9 5964
50f3b016 5965 intel_set_pipe_csc(crtc);
86d3efce 5966
09b4ddf9 5967 /* Set up the display plane register */
86d3efce 5968 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5969 POSTING_READ(DSPCNTR(plane));
5970
5971 ret = intel_pipe_set_base(crtc, x, y, fb);
5972
5973 intel_update_watermarks(dev);
5974
1f803ee5 5975 return ret;
79e53945
JB		 5976}
5977
0e8ffe1b
DV		 5978static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5979 struct intel_crtc_config *pipe_config)
5980{
5981 struct drm_device *dev = crtc->base.dev;
5982 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5983 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5984 uint32_t tmp;
5985
eccb140b 5986 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5987 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5988
eccb140b
DV		 5989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5990 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5991 enum pipe trans_edp_pipe;
5992 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5993 default:
5994 WARN(1, "unknown pipe linked to edp transcoder\n");
5995 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5996 case TRANS_DDI_EDP_INPUT_A_ON:
5997 trans_edp_pipe = PIPE_A;
5998 break;
5999 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6000 trans_edp_pipe = PIPE_B;
6001 break;
6002 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6003 trans_edp_pipe = PIPE_C;
6004 break;
6005 }
6006
6007 if (trans_edp_pipe == crtc->pipe)
6008 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6009 }
6010
b97186f0 6011 if (!intel_display_power_enabled(dev,
eccb140b 6012 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6013 return false;
6014
eccb140b 6015 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6016 if (!(tmp & PIPECONF_ENABLE))
6017 return false;
6018
88adfff1 6019 /*
f196e6be 6020 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6021 * DDI E. So just check whether this pipe is wired to DDI E and whether
6022 * the PCH transcoder is on.
6023 */
eccb140b 6024 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6025 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6026 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6027 pipe_config->has_pch_encoder = true;
6028
627eb5a3
DV		 6029 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6030 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6031 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6032
6033 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6034 }
6035
1bd1bd80
DV		 6036 intel_get_pipe_timings(crtc, pipe_config);
6037
2fa2fe9a
DV		 6038 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6039 if (intel_display_power_enabled(dev, pfit_domain))
6040 ironlake_get_pfit_config(crtc, pipe_config);
6041
42db64ef
PZ		 6042 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6043 (I915_READ(IPS_CTL) & IPS_ENABLE);
6044
6c49f241
DV		 6045 pipe_config->pixel_multiplier = 1;
6046
0e8ffe1b
DV		 6047 return true;
6048}
6049
f564048e 6050static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6051 int x, int y,
94352cf9 6052 struct drm_framebuffer *fb)
f564048e
EA		 6053{
6054 struct drm_device *dev = crtc->dev;
6055 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6056 struct drm_encoder_helper_funcs *encoder_funcs;
6057 struct intel_encoder *encoder;
0b701d27 6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6059 struct drm_display_mode *adjusted_mode =
6060 &intel_crtc->config.adjusted_mode;
6061 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6062 int pipe = intel_crtc->pipe;
f564048e
EA		 6063 int ret;
6064
0b701d27 6065 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6066
b8cecdf5
DV		 6067 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6068
79e53945 6069 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6070
9256aa19
DV		 6071 if (ret != 0)
6072 return ret;
6073
6074 for_each_encoder_on_crtc(dev, crtc, encoder) {
6075 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6076 encoder->base.base.id,
6077 drm_get_encoder_name(&encoder->base),
6078 mode->base.id, mode->name);
6cc5f341
DV		 6079 if (encoder->mode_set) {
6080 encoder->mode_set(encoder);
6081 } else {
6082 encoder_funcs = encoder->base.helper_private;
6083 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6084 }
9256aa19
DV		 6085 }
6086
6087 return 0;
79e53945
JB		 6088}
6089
3a9627f4
WF		 6090static bool intel_eld_uptodate(struct drm_connector *connector,
6091 int reg_eldv, uint32_t bits_eldv,
6092 int reg_elda, uint32_t bits_elda,
6093 int reg_edid)
6094{
6095 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6096 uint8_t *eld = connector->eld;
6097 uint32_t i;
6098
6099 i = I915_READ(reg_eldv);
6100 i &= bits_eldv;
6101
6102 if (!eld[0])
6103 return !i;
6104
6105 if (!i)
6106 return false;
6107
6108 i = I915_READ(reg_elda);
6109 i &= ~bits_elda;
6110 I915_WRITE(reg_elda, i);
6111
6112 for (i = 0; i < eld[2]; i++)
6113 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6114 return false;
6115
6116 return true;
6117}
6118
e0dac65e
WF		 6119static void g4x_write_eld(struct drm_connector *connector,
6120 struct drm_crtc *crtc)
6121{
6122 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6123 uint8_t *eld = connector->eld;
6124 uint32_t eldv;
6125 uint32_t len;
6126 uint32_t i;
6127
6128 i = I915_READ(G4X_AUD_VID_DID);
6129
6130 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6131 eldv = G4X_ELDV_DEVCL_DEVBLC;
6132 else
6133 eldv = G4X_ELDV_DEVCTG;
6134
3a9627f4
WF		 6135 if (intel_eld_uptodate(connector,
6136 G4X_AUD_CNTL_ST, eldv,
6137 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6138 G4X_HDMIW_HDMIEDID))
6139 return;
6140
e0dac65e
WF		 6141 i = I915_READ(G4X_AUD_CNTL_ST);
6142 i &= ~(eldv | G4X_ELD_ADDR);
6143 len = (i >> 9) & 0x1f; /* ELD buffer size */
6144 I915_WRITE(G4X_AUD_CNTL_ST, i);
6145
6146 if (!eld[0])
6147 return;
6148
6149 len = min_t(uint8_t, eld[2], len);
6150 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6151 for (i = 0; i < len; i++)
6152 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6153
6154 i = I915_READ(G4X_AUD_CNTL_ST);
6155 i |= eldv;
6156 I915_WRITE(G4X_AUD_CNTL_ST, i);
6157}
6158
83358c85
WX		 6159static void haswell_write_eld(struct drm_connector *connector,
6160 struct drm_crtc *crtc)
6161{
6162 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6163 uint8_t *eld = connector->eld;
6164 struct drm_device *dev = crtc->dev;
7b9f35a6 6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6166 uint32_t eldv;
6167 uint32_t i;
6168 int len;
6169 int pipe = to_intel_crtc(crtc)->pipe;
6170 int tmp;
6171
6172 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6173 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6174 int aud_config = HSW_AUD_CFG(pipe);
6175 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6176
6177
6178 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6179
6180 /* Audio output enable */
6181 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6182 tmp = I915_READ(aud_cntrl_st2);
6183 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6184 I915_WRITE(aud_cntrl_st2, tmp);
6185
6186 /* Wait for 1 vertical blank */
6187 intel_wait_for_vblank(dev, pipe);
6188
6189 /* Set ELD valid state */
6190 tmp = I915_READ(aud_cntrl_st2);
6191 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6192 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6193 I915_WRITE(aud_cntrl_st2, tmp);
6194 tmp = I915_READ(aud_cntrl_st2);
6195 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6196
6197 /* Enable HDMI mode */
6198 tmp = I915_READ(aud_config);
6199 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6200 /* clear N_programing_enable and N_value_index */
6201 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6202 I915_WRITE(aud_config, tmp);
6203
6204 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6205
6206 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6207 intel_crtc->eld_vld = true;
83358c85
WX		 6208
6209 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6210 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6211 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6212 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6213 } else
6214 I915_WRITE(aud_config, 0);
6215
6216 if (intel_eld_uptodate(connector,
6217 aud_cntrl_st2, eldv,
6218 aud_cntl_st, IBX_ELD_ADDRESS,
6219 hdmiw_hdmiedid))
6220 return;
6221
6222 i = I915_READ(aud_cntrl_st2);
6223 i &= ~eldv;
6224 I915_WRITE(aud_cntrl_st2, i);
6225
6226 if (!eld[0])
6227 return;
6228
6229 i = I915_READ(aud_cntl_st);
6230 i &= ~IBX_ELD_ADDRESS;
6231 I915_WRITE(aud_cntl_st, i);
6232 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6233 DRM_DEBUG_DRIVER("port num:%d\n", i);
6234
6235 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6236 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6237 for (i = 0; i < len; i++)
6238 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6239
6240 i = I915_READ(aud_cntrl_st2);
6241 i |= eldv;
6242 I915_WRITE(aud_cntrl_st2, i);
6243
6244}
6245
e0dac65e
WF		 6246static void ironlake_write_eld(struct drm_connector *connector,
6247 struct drm_crtc *crtc)
6248{
6249 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6250 uint8_t *eld = connector->eld;
6251 uint32_t eldv;
6252 uint32_t i;
6253 int len;
6254 int hdmiw_hdmiedid;
b6daa025 6255 int aud_config;
e0dac65e
WF		 6256 int aud_cntl_st;
6257 int aud_cntrl_st2;
9b138a83 6258 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6259
b3f33cbf 6260 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6261 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6262 aud_config = IBX_AUD_CFG(pipe);
6263 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6264 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6265 } else {
9b138a83
WX		 6266 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6267 aud_config = CPT_AUD_CFG(pipe);
6268 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6269 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6270 }
6271
9b138a83 6272 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6273
6274 i = I915_READ(aud_cntl_st);
9b138a83 6275 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6276 if (!i) {
6277 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6278 /* operate blindly on all ports */
1202b4c6
WF		 6279 eldv = IBX_ELD_VALIDB;
6280 eldv |= IBX_ELD_VALIDB << 4;
6281 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6282 } else {
2582a850 6283 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6284 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6285 }
6286
3a9627f4
WF		 6287 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6288 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6289 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6290 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6291 } else
6292 I915_WRITE(aud_config, 0);
e0dac65e 6293
3a9627f4
WF		 6294 if (intel_eld_uptodate(connector,
6295 aud_cntrl_st2, eldv,
6296 aud_cntl_st, IBX_ELD_ADDRESS,
6297 hdmiw_hdmiedid))
6298 return;
6299
e0dac65e
WF		 6300 i = I915_READ(aud_cntrl_st2);
6301 i &= ~eldv;
6302 I915_WRITE(aud_cntrl_st2, i);
6303
6304 if (!eld[0])
6305 return;
6306
e0dac65e 6307 i = I915_READ(aud_cntl_st);
1202b4c6 6308 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6309 I915_WRITE(aud_cntl_st, i);
6310
6311 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6312 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6313 for (i = 0; i < len; i++)
6314 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6315
6316 i = I915_READ(aud_cntrl_st2);
6317 i |= eldv;
6318 I915_WRITE(aud_cntrl_st2, i);
6319}
6320
6321void intel_write_eld(struct drm_encoder *encoder,
6322 struct drm_display_mode *mode)
6323{
6324 struct drm_crtc *crtc = encoder->crtc;
6325 struct drm_connector *connector;
6326 struct drm_device *dev = encoder->dev;
6327 struct drm_i915_private *dev_priv = dev->dev_private;
6328
6329 connector = drm_select_eld(encoder, mode);
6330 if (!connector)
6331 return;
6332
6333 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6334 connector->base.id,
6335 drm_get_connector_name(connector),
6336 connector->encoder->base.id,
6337 drm_get_encoder_name(connector->encoder));
6338
6339 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6340
6341 if (dev_priv->display.write_eld)
6342 dev_priv->display.write_eld(connector, crtc);
6343}
6344
79e53945
JB		 6345/** Loads the palette/gamma unit for the CRTC with the prepared values */
6346void intel_crtc_load_lut(struct drm_crtc *crtc)
6347{
6348 struct drm_device *dev = crtc->dev;
6349 struct drm_i915_private *dev_priv = dev->dev_private;
6350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6351 enum pipe pipe = intel_crtc->pipe;
6352 int palreg = PALETTE(pipe);
79e53945 6353 int i;
42db64ef 6354 bool reenable_ips = false;
79e53945
JB		 6355
6356 /* The clocks have to be on to load the palette. */
aed3f09d 6357 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6358 return;
6359
14420bd0
VS		 6360 if (!HAS_PCH_SPLIT(dev_priv->dev))
6361 assert_pll_enabled(dev_priv, pipe);
6362
f2b115e6 6363 /* use legacy palette for Ironlake */
bad720ff 6364 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6365 palreg = LGC_PALETTE(pipe);
6366
6367 /* Workaround : Do not read or write the pipe palette/gamma data while
6368 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6369 */
6370 if (intel_crtc->config.ips_enabled &&
6371 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6372 GAMMA_MODE_MODE_SPLIT)) {
6373 hsw_disable_ips(intel_crtc);
6374 reenable_ips = true;
6375 }
2c07245f 6376
79e53945
JB		 6377 for (i = 0; i < 256; i++) {
6378 I915_WRITE(palreg + 4 * i,
6379 (intel_crtc->lut_r[i] << 16) |
6380 (intel_crtc->lut_g[i] << 8) |
6381 intel_crtc->lut_b[i]);
6382 }
42db64ef
PZ		 6383
6384 if (reenable_ips)
6385 hsw_enable_ips(intel_crtc);
79e53945
JB		 6386}
6387
560b85bb
CW		 6388static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6389{
6390 struct drm_device *dev = crtc->dev;
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6393 bool visible = base != 0;
6394 u32 cntl;
6395
6396 if (intel_crtc->cursor_visible == visible)
6397 return;
6398
9db4a9c7 6399 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6400 if (visible) {
6401 /* On these chipsets we can only modify the base whilst
6402 * the cursor is disabled.
6403 */
9db4a9c7 6404 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6405
6406 cntl &= ~(CURSOR_FORMAT_MASK);
6407 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6408 cntl |= CURSOR_ENABLE |
6409 CURSOR_GAMMA_ENABLE |
6410 CURSOR_FORMAT_ARGB;
6411 } else
6412 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6413 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6414
6415 intel_crtc->cursor_visible = visible;
6416}
6417
6418static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6419{
6420 struct drm_device *dev = crtc->dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6423 int pipe = intel_crtc->pipe;
6424 bool visible = base != 0;
6425
6426 if (intel_crtc->cursor_visible != visible) {
548f245b 6427 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6428 if (base) {
6429 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6430 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6431 cntl |= pipe << 28; /* Connect to correct pipe */
6432 } else {
6433 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6434 cntl |= CURSOR_MODE_DISABLE;
6435 }
9db4a9c7 6436 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6437
6438 intel_crtc->cursor_visible = visible;
6439 }
6440 /* and commit changes on next vblank */
9db4a9c7 6441 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6442}
6443
65a21cd6
JB		 6444static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6445{
6446 struct drm_device *dev = crtc->dev;
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
6450 bool visible = base != 0;
6451
6452 if (intel_crtc->cursor_visible != visible) {
6453 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6454 if (base) {
6455 cntl &= ~CURSOR_MODE;
6456 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6457 } else {
6458 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6459 cntl |= CURSOR_MODE_DISABLE;
6460 }
86d3efce
VS		 6461 if (IS_HASWELL(dev))
6462 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6463 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6464
6465 intel_crtc->cursor_visible = visible;
6466 }
6467 /* and commit changes on next vblank */
6468 I915_WRITE(CURBASE_IVB(pipe), base);
6469}
6470
cda4b7d3 6471/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6472static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6473 bool on)
cda4b7d3
CW		 6474{
6475 struct drm_device *dev = crtc->dev;
6476 struct drm_i915_private *dev_priv = dev->dev_private;
6477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6478 int pipe = intel_crtc->pipe;
6479 int x = intel_crtc->cursor_x;
6480 int y = intel_crtc->cursor_y;
560b85bb 6481 u32 base, pos;
cda4b7d3
CW		 6482 bool visible;
6483
6484 pos = 0;
6485
6b383a7f 6486 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6487 base = intel_crtc->cursor_addr;
6488 if (x > (int) crtc->fb->width)
6489 base = 0;
6490
6491 if (y > (int) crtc->fb->height)
6492 base = 0;
6493 } else
6494 base = 0;
6495
6496 if (x < 0) {
6497 if (x + intel_crtc->cursor_width < 0)
6498 base = 0;
6499
6500 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6501 x = -x;
6502 }
6503 pos |= x << CURSOR_X_SHIFT;
6504
6505 if (y < 0) {
6506 if (y + intel_crtc->cursor_height < 0)
6507 base = 0;
6508
6509 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6510 y = -y;
6511 }
6512 pos |= y << CURSOR_Y_SHIFT;
6513
6514 visible = base != 0;
560b85bb 6515 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6516 return;
6517
0cd83aa9 6518 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6519 I915_WRITE(CURPOS_IVB(pipe), pos);
6520 ivb_update_cursor(crtc, base);
6521 } else {
6522 I915_WRITE(CURPOS(pipe), pos);
6523 if (IS_845G(dev) || IS_I865G(dev))
6524 i845_update_cursor(crtc, base);
6525 else
6526 i9xx_update_cursor(crtc, base);
6527 }
cda4b7d3
CW		 6528}
6529
79e53945 6530static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6531 struct drm_file *file,
79e53945
JB		 6532 uint32_t handle,
6533 uint32_t width, uint32_t height)
6534{
6535 struct drm_device *dev = crtc->dev;
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6538 struct drm_i915_gem_object *obj;
cda4b7d3 6539 uint32_t addr;
3f8bc370 6540 int ret;
79e53945 6541
79e53945
JB		 6542 /* if we want to turn off the cursor ignore width and height */
6543 if (!handle) {
28c97730 6544 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6545 addr = 0;
05394f39 6546 obj = NULL;
5004417d 6547 mutex_lock(&dev->struct_mutex);
3f8bc370 6548 goto finish;
79e53945
JB		 6549 }
6550
6551 /* Currently we only support 64x64 cursors */
6552 if (width != 64 || height != 64) {
6553 DRM_ERROR("we currently only support 64x64 cursors\n");
6554 return -EINVAL;
6555 }
6556
05394f39 6557 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6558 if (&obj->base == NULL)
79e53945
JB		 6559 return -ENOENT;
6560
05394f39 6561 if (obj->base.size < width * height * 4) {
79e53945 6562 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6563 ret = -ENOMEM;
6564 goto fail;
79e53945
JB		 6565 }
6566
71acb5eb 6567 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6568 mutex_lock(&dev->struct_mutex);
b295d1b6 6569 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6570 unsigned alignment;
6571
d9e86c0e
CW		 6572 if (obj->tiling_mode) {
6573 DRM_ERROR("cursor cannot be tiled\n");
6574 ret = -EINVAL;
6575 goto fail_locked;
6576 }
6577
693db184
CW		 6578 /* Note that the w/a also requires 2 PTE of padding following
6579 * the bo. We currently fill all unused PTE with the shadow
6580 * page and so we should always have valid PTE following the
6581 * cursor preventing the VT-d warning.
6582 */
6583 alignment = 0;
6584 if (need_vtd_wa(dev))
6585 alignment = 64*1024;
6586
6587 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6588 if (ret) {
6589 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6590 goto fail_locked;
e7b526bb
CW		 6591 }
6592
d9e86c0e
CW		 6593 ret = i915_gem_object_put_fence(obj);
6594 if (ret) {
2da3b9b9 6595 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6596 goto fail_unpin;
6597 }
6598
05394f39 6599 addr = obj->gtt_offset;
71acb5eb 6600 } else {
6eeefaf3 6601 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6602 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6603 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6604 align);
71acb5eb
DA		 6605 if (ret) {
6606 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6607 goto fail_locked;
71acb5eb 6608 }
05394f39 6609 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6610 }
6611
a6c45cf0 6612 if (IS_GEN2(dev))
14b60391
JB		 6613 I915_WRITE(CURSIZE, (height << 12) | width);
6614
3f8bc370 6615 finish:
3f8bc370 6616 if (intel_crtc->cursor_bo) {
b295d1b6 6617 if (dev_priv->info->cursor_needs_physical) {
05394f39 6618 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6619 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6620 } else
6621 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6622 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6623 }
80824003 6624
7f9872e0 6625 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6626
6627 intel_crtc->cursor_addr = addr;
05394f39 6628 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6629 intel_crtc->cursor_width = width;
6630 intel_crtc->cursor_height = height;
6631
40ccc72b 6632 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6633
79e53945 6634 return 0;
e7b526bb 6635fail_unpin:
05394f39 6636 i915_gem_object_unpin(obj);
7f9872e0 6637fail_locked:
34b8686e 6638 mutex_unlock(&dev->struct_mutex);
bc9025bd 6639fail:
05394f39 6640 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6641 return ret;
79e53945
JB		 6642}
6643
6644static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6645{
79e53945 6646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6647
cda4b7d3
CW		 6648 intel_crtc->cursor_x = x;
6649 intel_crtc->cursor_y = y;
652c393a 6650
40ccc72b 6651 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6652
6653 return 0;
6654}
6655
6656/** Sets the color ramps on behalf of RandR */
6657void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6658 u16 blue, int regno)
6659{
6660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6661
6662 intel_crtc->lut_r[regno] = red >> 8;
6663 intel_crtc->lut_g[regno] = green >> 8;
6664 intel_crtc->lut_b[regno] = blue >> 8;
6665}
6666
b8c00ac5
DA		 6667void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6668 u16 *blue, int regno)
6669{
6670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6671
6672 *red = intel_crtc->lut_r[regno] << 8;
6673 *green = intel_crtc->lut_g[regno] << 8;
6674 *blue = intel_crtc->lut_b[regno] << 8;
6675}
6676
79e53945 6677static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6678 u16 *blue, uint32_t start, uint32_t size)
79e53945 6679{
7203425a 6680 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6682
7203425a 6683 for (i = start; i < end; i++) {
79e53945
JB		 6684 intel_crtc->lut_r[i] = red[i] >> 8;
6685 intel_crtc->lut_g[i] = green[i] >> 8;
6686 intel_crtc->lut_b[i] = blue[i] >> 8;
6687 }
6688
6689 intel_crtc_load_lut(crtc);
6690}
6691
79e53945
JB		 6692/* VESA 640x480x72Hz mode to set on the pipe */
6693static struct drm_display_mode load_detect_mode = {
6694 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6695 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6696};
6697
d2dff872
CW		 6698static struct drm_framebuffer *
6699intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6700 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6701 struct drm_i915_gem_object *obj)
6702{
6703 struct intel_framebuffer *intel_fb;
6704 int ret;
6705
6706 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6707 if (!intel_fb) {
6708 drm_gem_object_unreference_unlocked(&obj->base);
6709 return ERR_PTR(-ENOMEM);
6710 }
6711
6712 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6713 if (ret) {
6714 drm_gem_object_unreference_unlocked(&obj->base);
6715 kfree(intel_fb);
6716 return ERR_PTR(ret);
6717 }
6718
6719 return &intel_fb->base;
6720}
6721
6722static u32
6723intel_framebuffer_pitch_for_width(int width, int bpp)
6724{
6725 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6726 return ALIGN(pitch, 64);
6727}
6728
6729static u32
6730intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6731{
6732 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6733 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6734}
6735
6736static struct drm_framebuffer *
6737intel_framebuffer_create_for_mode(struct drm_device *dev,
6738 struct drm_display_mode *mode,
6739 int depth, int bpp)
6740{
6741 struct drm_i915_gem_object *obj;
0fed39bd 6742 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6743
6744 obj = i915_gem_alloc_object(dev,
6745 intel_framebuffer_size_for_mode(mode, bpp));
6746 if (obj == NULL)
6747 return ERR_PTR(-ENOMEM);
6748
6749 mode_cmd.width = mode->hdisplay;
6750 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6751 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6752 bpp);
5ca0c34a 6753 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6754
6755 return intel_framebuffer_create(dev, &mode_cmd, obj);
6756}
6757
6758static struct drm_framebuffer *
6759mode_fits_in_fbdev(struct drm_device *dev,
6760 struct drm_display_mode *mode)
6761{
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 struct drm_i915_gem_object *obj;
6764 struct drm_framebuffer *fb;
6765
6766 if (dev_priv->fbdev == NULL)
6767 return NULL;
6768
6769 obj = dev_priv->fbdev->ifb.obj;
6770 if (obj == NULL)
6771 return NULL;
6772
6773 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6774 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6775 fb->bits_per_pixel))
d2dff872
CW		 6776 return NULL;
6777
01f2c773 6778 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6779 return NULL;
6780
6781 return fb;
6782}
6783
d2434ab7 6784bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6785 struct drm_display_mode *mode,
8261b191 6786 struct intel_load_detect_pipe *old)
79e53945
JB		 6787{
6788 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6789 struct intel_encoder *intel_encoder =
6790 intel_attached_encoder(connector);
79e53945 6791 struct drm_crtc *possible_crtc;
4ef69c7a 6792 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6793 struct drm_crtc *crtc = NULL;
6794 struct drm_device *dev = encoder->dev;
94352cf9 6795 struct drm_framebuffer *fb;
79e53945
JB		 6796 int i = -1;
6797
d2dff872
CW		 6798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6799 connector->base.id, drm_get_connector_name(connector),
6800 encoder->base.id, drm_get_encoder_name(encoder));
6801
79e53945
JB		 6802 /*
6803 * Algorithm gets a little messy:
7a5e4805 6804 *
79e53945
JB		 6805 * - if the connector already has an assigned crtc, use it (but make
6806 * sure it's on first)
7a5e4805 6807 *
79e53945
JB		 6808 * - try to find the first unused crtc that can drive this connector,
6809 * and use that if we find one
79e53945
JB		 6810 */
6811
6812 /* See if we already have a CRTC for this connector */
6813 if (encoder->crtc) {
6814 crtc = encoder->crtc;
8261b191 6815
7b24056b
DV		 6816 mutex_lock(&crtc->mutex);
6817
24218aac 6818 old->dpms_mode = connector->dpms;
8261b191
CW		 6819 old->load_detect_temp = false;
6820
6821 /* Make sure the crtc and connector are running */
24218aac
DV		 6822 if (connector->dpms != DRM_MODE_DPMS_ON)
6823 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6824
7173188d 6825 return true;
79e53945
JB		 6826 }
6827
6828 /* Find an unused one (if possible) */
6829 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6830 i++;
6831 if (!(encoder->possible_crtcs & (1 << i)))
6832 continue;
6833 if (!possible_crtc->enabled) {
6834 crtc = possible_crtc;
6835 break;
6836 }
79e53945
JB		 6837 }
6838
6839 /*
6840 * If we didn't find an unused CRTC, don't use any.
6841 */
6842 if (!crtc) {
7173188d
CW		 6843 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6844 return false;
79e53945
JB		 6845 }
6846
7b24056b 6847 mutex_lock(&crtc->mutex);
fc303101
DV		 6848 intel_encoder->new_crtc = to_intel_crtc(crtc);
6849 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6850
6851 intel_crtc = to_intel_crtc(crtc);
24218aac 6852 old->dpms_mode = connector->dpms;
8261b191 6853 old->load_detect_temp = true;
d2dff872 6854 old->release_fb = NULL;
79e53945 6855
6492711d
CW		 6856 if (!mode)
6857 mode = &load_detect_mode;
79e53945 6858
d2dff872
CW		 6859 /* We need a framebuffer large enough to accommodate all accesses
6860 * that the plane may generate whilst we perform load detection.
6861 * We can not rely on the fbcon either being present (we get called
6862 * during its initialisation to detect all boot displays, or it may
6863 * not even exist) or that it is large enough to satisfy the
6864 * requested mode.
6865 */
94352cf9
DV		 6866 fb = mode_fits_in_fbdev(dev, mode);
6867 if (fb == NULL) {
d2dff872 6868 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6869 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6870 old->release_fb = fb;
d2dff872
CW		 6871 } else
6872 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6873 if (IS_ERR(fb)) {
d2dff872 6874 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6875 mutex_unlock(&crtc->mutex);
0e8b3d3e 6876 return false;
79e53945 6877 }
79e53945 6878
c0c36b94 6879 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6880 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6881 if (old->release_fb)
6882 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6883 mutex_unlock(&crtc->mutex);
0e8b3d3e 6884 return false;
79e53945 6885 }
7173188d 6886
79e53945 6887 /* let the connector get through one full cycle before testing */
9d0498a2 6888 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6889 return true;
79e53945
JB		 6890}
6891
d2434ab7 6892void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6893 struct intel_load_detect_pipe *old)
79e53945 6894{
d2434ab7
DV		 6895 struct intel_encoder *intel_encoder =
6896 intel_attached_encoder(connector);
4ef69c7a 6897 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6898 struct drm_crtc *crtc = encoder->crtc;
79e53945 6899
d2dff872
CW		 6900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6901 connector->base.id, drm_get_connector_name(connector),
6902 encoder->base.id, drm_get_encoder_name(encoder));
6903
8261b191 6904 if (old->load_detect_temp) {
fc303101
DV		 6905 to_intel_connector(connector)->new_encoder = NULL;
6906 intel_encoder->new_crtc = NULL;
6907 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6908
36206361
DV		 6909 if (old->release_fb) {
6910 drm_framebuffer_unregister_private(old->release_fb);
6911 drm_framebuffer_unreference(old->release_fb);
6912 }
d2dff872 6913
67c96400 6914 mutex_unlock(&crtc->mutex);
0622a53c 6915 return;
79e53945
JB		 6916 }
6917
c751ce4f 6918 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6919 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6920 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6921
6922 mutex_unlock(&crtc->mutex);
79e53945
JB		 6923}
6924
6925/* Returns the clock of the currently programmed mode of the given pipe. */
6926static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6927{
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6930 int pipe = intel_crtc->pipe;
548f245b 6931 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6932 u32 fp;
6933 intel_clock_t clock;
6934
6935 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6936 fp = I915_READ(FP0(pipe));
79e53945 6937 else
39adb7a5 6938 fp = I915_READ(FP1(pipe));
79e53945
JB		 6939
6940 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6941 if (IS_PINEVIEW(dev)) {
6942 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6943 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6944 } else {
6945 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6946 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6947 }
6948
a6c45cf0 6949 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6950 if (IS_PINEVIEW(dev))
6951 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6952 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6953 else
6954 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6955 DPLL_FPA01_P1_POST_DIV_SHIFT);
6956
6957 switch (dpll & DPLL_MODE_MASK) {
6958 case DPLLB_MODE_DAC_SERIAL:
6959 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6960 5 : 10;
6961 break;
6962 case DPLLB_MODE_LVDS:
6963 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6964 7 : 14;
6965 break;
6966 default:
28c97730 6967 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6968 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6969 return 0;
6970 }
6971
ac58c3f0
DV		 6972 if (IS_PINEVIEW(dev))
6973 pineview_clock(96000, &clock);
6974 else
6975 i9xx_clock(96000, &clock);
79e53945
JB		 6976 } else {
6977 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6978
6979 if (is_lvds) {
6980 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6981 DPLL_FPA01_P1_POST_DIV_SHIFT);
6982 clock.p2 = 14;
6983
6984 if ((dpll & PLL_REF_INPUT_MASK) ==
6985 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6986 /* XXX: might not be 66MHz */
ac58c3f0 6987 i9xx_clock(66000, &clock);
79e53945 6988 } else
ac58c3f0 6989 i9xx_clock(48000, &clock);
79e53945
JB		 6990 } else {
6991 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6992 clock.p1 = 2;
6993 else {
6994 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6995 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6996 }
6997 if (dpll & PLL_P2_DIVIDE_BY_4)
6998 clock.p2 = 4;
6999 else
7000 clock.p2 = 2;
7001
ac58c3f0 7002 i9xx_clock(48000, &clock);
79e53945
JB		 7003 }
7004 }
7005
7006 /* XXX: It would be nice to validate the clocks, but we can't reuse
7007 * i830PllIsValid() because it relies on the xf86_config connector
7008 * configuration being accurate, which it isn't necessarily.
7009 */
7010
7011 return clock.dot;
7012}
7013
7014/** Returns the currently programmed mode of the given pipe. */
7015struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7016 struct drm_crtc *crtc)
7017{
548f245b 7018 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7020 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7021 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7022 int htot = I915_READ(HTOTAL(cpu_transcoder));
7023 int hsync = I915_READ(HSYNC(cpu_transcoder));
7024 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7025 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7026
7027 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7028 if (!mode)
7029 return NULL;
7030
7031 mode->clock = intel_crtc_clock_get(dev, crtc);
7032 mode->hdisplay = (htot & 0xffff) + 1;
7033 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7034 mode->hsync_start = (hsync & 0xffff) + 1;
7035 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7036 mode->vdisplay = (vtot & 0xffff) + 1;
7037 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7038 mode->vsync_start = (vsync & 0xffff) + 1;
7039 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7040
7041 drm_mode_set_name(mode);
79e53945
JB		 7042
7043 return mode;
7044}
7045
3dec0095 7046static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7047{
7048 struct drm_device *dev = crtc->dev;
7049 drm_i915_private_t *dev_priv = dev->dev_private;
7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7051 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7052 int dpll_reg = DPLL(pipe);
7053 int dpll;
652c393a 7054
bad720ff 7055 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7056 return;
7057
7058 if (!dev_priv->lvds_downclock_avail)
7059 return;
7060
dbdc6479 7061 dpll = I915_READ(dpll_reg);
652c393a 7062 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7063 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7064
8ac5a6d5 7065 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7066
7067 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7068 I915_WRITE(dpll_reg, dpll);
9d0498a2 7069 intel_wait_for_vblank(dev, pipe);
dbdc6479 7070
652c393a
JB		 7071 dpll = I915_READ(dpll_reg);
7072 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7073 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7074 }
652c393a
JB		 7075}
7076
7077static void intel_decrease_pllclock(struct drm_crtc *crtc)
7078{
7079 struct drm_device *dev = crtc->dev;
7080 drm_i915_private_t *dev_priv = dev->dev_private;
7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7082
bad720ff 7083 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7084 return;
7085
7086 if (!dev_priv->lvds_downclock_avail)
7087 return;
7088
7089 /*
7090 * Since this is called by a timer, we should never get here in
7091 * the manual case.
7092 */
7093 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7094 int pipe = intel_crtc->pipe;
7095 int dpll_reg = DPLL(pipe);
7096 int dpll;
f6e5b160 7097
44d98a61 7098 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7099
8ac5a6d5 7100 assert_panel_unlocked(dev_priv, pipe);
652c393a 7101
dc257cf1 7102 dpll = I915_READ(dpll_reg);
652c393a
JB		 7103 dpll |= DISPLAY_RATE_SELECT_FPA1;
7104 I915_WRITE(dpll_reg, dpll);
9d0498a2 7105 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7106 dpll = I915_READ(dpll_reg);
7107 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7108 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7109 }
7110
7111}
7112
f047e395
CW		 7113void intel_mark_busy(struct drm_device *dev)
7114{
f047e395
CW		 7115 i915_update_gfx_val(dev->dev_private);
7116}
7117
7118void intel_mark_idle(struct drm_device *dev)
652c393a 7119{
652c393a 7120 struct drm_crtc *crtc;
652c393a
JB		 7121
7122 if (!i915_powersave)
7123 return;
7124
652c393a 7125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7126 if (!crtc->fb)
7127 continue;
7128
725a5b54 7129 intel_decrease_pllclock(crtc);
652c393a 7130 }
652c393a
JB		 7131}
7132
c65355bb
CW		 7133void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7134 struct intel_ring_buffer *ring)
652c393a 7135{
f047e395
CW		 7136 struct drm_device *dev = obj->base.dev;
7137 struct drm_crtc *crtc;
652c393a 7138
f047e395 7139 if (!i915_powersave)
acb87dfb
CW		 7140 return;
7141
652c393a
JB		 7142 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7143 if (!crtc->fb)
7144 continue;
7145
c65355bb
CW		 7146 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7147 continue;
7148
7149 intel_increase_pllclock(crtc);
7150 if (ring && intel_fbc_enabled(dev))
7151 ring->fbc_dirty = true;
652c393a
JB		 7152 }
7153}
7154
79e53945
JB		 7155static void intel_crtc_destroy(struct drm_crtc *crtc)
7156{
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7158 struct drm_device *dev = crtc->dev;
7159 struct intel_unpin_work *work;
7160 unsigned long flags;
7161
7162 spin_lock_irqsave(&dev->event_lock, flags);
7163 work = intel_crtc->unpin_work;
7164 intel_crtc->unpin_work = NULL;
7165 spin_unlock_irqrestore(&dev->event_lock, flags);
7166
7167 if (work) {
7168 cancel_work_sync(&work->work);
7169 kfree(work);
7170 }
79e53945 7171
40ccc72b
MK		 7172 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7173
79e53945 7174 drm_crtc_cleanup(crtc);
67e77c5a 7175
79e53945
JB		 7176 kfree(intel_crtc);
7177}
7178
6b95a207
KH		 7179static void intel_unpin_work_fn(struct work_struct *__work)
7180{
7181 struct intel_unpin_work *work =
7182 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7183 struct drm_device *dev = work->crtc->dev;
6b95a207 7184
b4a98e57 7185 mutex_lock(&dev->struct_mutex);
1690e1eb 7186 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7187 drm_gem_object_unreference(&work->pending_flip_obj->base);
7188 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7189
b4a98e57
CW		 7190 intel_update_fbc(dev);
7191 mutex_unlock(&dev->struct_mutex);
7192
7193 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7194 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7195
6b95a207
KH		 7196 kfree(work);
7197}
7198
1afe3e9d 7199static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7200 struct drm_crtc *crtc)
6b95a207
KH		 7201{
7202 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7204 struct intel_unpin_work *work;
6b95a207
KH		 7205 unsigned long flags;
7206
7207 /* Ignore early vblank irqs */
7208 if (intel_crtc == NULL)
7209 return;
7210
7211 spin_lock_irqsave(&dev->event_lock, flags);
7212 work = intel_crtc->unpin_work;
e7d841ca
CW		 7213
7214 /* Ensure we don't miss a work->pending update ... */
7215 smp_rmb();
7216
7217 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7218 spin_unlock_irqrestore(&dev->event_lock, flags);
7219 return;
7220 }
7221
e7d841ca
CW		 7222 /* and that the unpin work is consistent wrt ->pending. */
7223 smp_rmb();
7224
6b95a207 7225 intel_crtc->unpin_work = NULL;
6b95a207 7226
45a066eb
RC		 7227 if (work->event)
7228 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7229
0af7e4df
MK		 7230 drm_vblank_put(dev, intel_crtc->pipe);
7231
6b95a207
KH		 7232 spin_unlock_irqrestore(&dev->event_lock, flags);
7233
2c10d571 7234 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7235
7236 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7237
7238 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7239}
7240
1afe3e9d
JB		 7241void intel_finish_page_flip(struct drm_device *dev, int pipe)
7242{
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7245
49b14a5c 7246 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7247}
7248
7249void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7250{
7251 drm_i915_private_t *dev_priv = dev->dev_private;
7252 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7253
49b14a5c 7254 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7255}
7256
6b95a207
KH		 7257void intel_prepare_page_flip(struct drm_device *dev, int plane)
7258{
7259 drm_i915_private_t *dev_priv = dev->dev_private;
7260 struct intel_crtc *intel_crtc =
7261 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7262 unsigned long flags;
7263
e7d841ca
CW		 7264 /* NB: An MMIO update of the plane base pointer will also
7265 * generate a page-flip completion irq, i.e. every modeset
7266 * is also accompanied by a spurious intel_prepare_page_flip().
7267 */
6b95a207 7268 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7269 if (intel_crtc->unpin_work)
7270 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7271 spin_unlock_irqrestore(&dev->event_lock, flags);
7272}
7273
e7d841ca
CW		 7274inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7275{
7276 /* Ensure that the work item is consistent when activating it ... */
7277 smp_wmb();
7278 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7279 /* and that it is marked active as soon as the irq could fire. */
7280 smp_wmb();
7281}
7282
8c9f3aaf
JB		 7283static int intel_gen2_queue_flip(struct drm_device *dev,
7284 struct drm_crtc *crtc,
7285 struct drm_framebuffer *fb,
7286 struct drm_i915_gem_object *obj)
7287{
7288 struct drm_i915_private *dev_priv = dev->dev_private;
7289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7290 u32 flip_mask;
6d90c952 7291 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7292 int ret;
7293
6d90c952 7294 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7295 if (ret)
83d4092b 7296 goto err;
8c9f3aaf 7297
6d90c952 7298 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7299 if (ret)
83d4092b 7300 goto err_unpin;
8c9f3aaf
JB		 7301
7302 /* Can't queue multiple flips, so wait for the previous
7303 * one to finish before executing the next.
7304 */
7305 if (intel_crtc->plane)
7306 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7307 else
7308 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7309 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7310 intel_ring_emit(ring, MI_NOOP);
7311 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7312 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7313 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7314 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7315 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7316
7317 intel_mark_page_flip_active(intel_crtc);
6d90c952 7318 intel_ring_advance(ring);
83d4092b
CW		 7319 return 0;
7320
7321err_unpin:
7322 intel_unpin_fb_obj(obj);
7323err:
8c9f3aaf
JB		 7324 return ret;
7325}
7326
7327static int intel_gen3_queue_flip(struct drm_device *dev,
7328 struct drm_crtc *crtc,
7329 struct drm_framebuffer *fb,
7330 struct drm_i915_gem_object *obj)
7331{
7332 struct drm_i915_private *dev_priv = dev->dev_private;
7333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7334 u32 flip_mask;
6d90c952 7335 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7336 int ret;
7337
6d90c952 7338 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7339 if (ret)
83d4092b 7340 goto err;
8c9f3aaf 7341
6d90c952 7342 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7343 if (ret)
83d4092b 7344 goto err_unpin;
8c9f3aaf
JB		 7345
7346 if (intel_crtc->plane)
7347 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7348 else
7349 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7350 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7351 intel_ring_emit(ring, MI_NOOP);
7352 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7353 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7354 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7355 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7356 intel_ring_emit(ring, MI_NOOP);
7357
e7d841ca 7358 intel_mark_page_flip_active(intel_crtc);
6d90c952 7359 intel_ring_advance(ring);
83d4092b
CW		 7360 return 0;
7361
7362err_unpin:
7363 intel_unpin_fb_obj(obj);
7364err:
8c9f3aaf
JB		 7365 return ret;
7366}
7367
7368static int intel_gen4_queue_flip(struct drm_device *dev,
7369 struct drm_crtc *crtc,
7370 struct drm_framebuffer *fb,
7371 struct drm_i915_gem_object *obj)
7372{
7373 struct drm_i915_private *dev_priv = dev->dev_private;
7374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7375 uint32_t pf, pipesrc;
6d90c952 7376 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7377 int ret;
7378
6d90c952 7379 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7380 if (ret)
83d4092b 7381 goto err;
8c9f3aaf 7382
6d90c952 7383 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7384 if (ret)
83d4092b 7385 goto err_unpin;
8c9f3aaf
JB		 7386
7387 /* i965+ uses the linear or tiled offsets from the
7388 * Display Registers (which do not change across a page-flip)
7389 * so we need only reprogram the base address.
7390 */
6d90c952
DV		 7391 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7392 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7393 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7394 intel_ring_emit(ring,
7395 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7396 obj->tiling_mode);
8c9f3aaf
JB		 7397
7398 /* XXX Enabling the panel-fitter across page-flip is so far
7399 * untested on non-native modes, so ignore it for now.
7400 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7401 */
7402 pf = 0;
7403 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7404 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7405
7406 intel_mark_page_flip_active(intel_crtc);
6d90c952 7407 intel_ring_advance(ring);
83d4092b
CW		 7408 return 0;
7409
7410err_unpin:
7411 intel_unpin_fb_obj(obj);
7412err:
8c9f3aaf
JB		 7413 return ret;
7414}
7415
7416static int intel_gen6_queue_flip(struct drm_device *dev,
7417 struct drm_crtc *crtc,
7418 struct drm_framebuffer *fb,
7419 struct drm_i915_gem_object *obj)
7420{
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7423 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7424 uint32_t pf, pipesrc;
7425 int ret;
7426
6d90c952 7427 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7428 if (ret)
83d4092b 7429 goto err;
8c9f3aaf 7430
6d90c952 7431 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7432 if (ret)
83d4092b 7433 goto err_unpin;
8c9f3aaf 7434
6d90c952
DV		 7435 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7436 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7437 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7438 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7439
dc257cf1
DV		 7440 /* Contrary to the suggestions in the documentation,
7441 * "Enable Panel Fitter" does not seem to be required when page
7442 * flipping with a non-native mode, and worse causes a normal
7443 * modeset to fail.
7444 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7445 */
7446 pf = 0;
8c9f3aaf 7447 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7448 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7449
7450 intel_mark_page_flip_active(intel_crtc);
6d90c952 7451 intel_ring_advance(ring);
83d4092b
CW		 7452 return 0;
7453
7454err_unpin:
7455 intel_unpin_fb_obj(obj);
7456err:
8c9f3aaf
JB		 7457 return ret;
7458}
7459
7c9017e5
JB		 7460/*
7461 * On gen7 we currently use the blit ring because (in early silicon at least)
7462 * the render ring doesn't give us interrpts for page flip completion, which
7463 * means clients will hang after the first flip is queued. Fortunately the
7464 * blit ring generates interrupts properly, so use it instead.
7465 */
7466static int intel_gen7_queue_flip(struct drm_device *dev,
7467 struct drm_crtc *crtc,
7468 struct drm_framebuffer *fb,
7469 struct drm_i915_gem_object *obj)
7470{
7471 struct drm_i915_private *dev_priv = dev->dev_private;
7472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7473 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7474 uint32_t plane_bit = 0;
7c9017e5
JB		 7475 int ret;
7476
7477 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7478 if (ret)
83d4092b 7479 goto err;
7c9017e5 7480
cb05d8de
DV		 7481 switch(intel_crtc->plane) {
7482 case PLANE_A:
7483 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7484 break;
7485 case PLANE_B:
7486 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7487 break;
7488 case PLANE_C:
7489 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7490 break;
7491 default:
7492 WARN_ONCE(1, "unknown plane in flip command\n");
7493 ret = -ENODEV;
ab3951eb 7494 goto err_unpin;
cb05d8de
DV		 7495 }
7496
7c9017e5
JB		 7497 ret = intel_ring_begin(ring, 4);
7498 if (ret)
83d4092b 7499 goto err_unpin;
7c9017e5 7500
cb05d8de 7501 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7502 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7503 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7504 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7505
7506 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7507 intel_ring_advance(ring);
83d4092b
CW		 7508 return 0;
7509
7510err_unpin:
7511 intel_unpin_fb_obj(obj);
7512err:
7c9017e5
JB		 7513 return ret;
7514}
7515
8c9f3aaf
JB		 7516static int intel_default_queue_flip(struct drm_device *dev,
7517 struct drm_crtc *crtc,
7518 struct drm_framebuffer *fb,
7519 struct drm_i915_gem_object *obj)
7520{
7521 return -ENODEV;
7522}
7523
6b95a207
KH		 7524static int intel_crtc_page_flip(struct drm_crtc *crtc,
7525 struct drm_framebuffer *fb,
7526 struct drm_pending_vblank_event *event)
7527{
7528 struct drm_device *dev = crtc->dev;
7529 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7530 struct drm_framebuffer *old_fb = crtc->fb;
7531 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7533 struct intel_unpin_work *work;
8c9f3aaf 7534 unsigned long flags;
52e68630 7535 int ret;
6b95a207 7536
e6a595d2
VS		 7537 /* Can't change pixel format via MI display flips. */
7538 if (fb->pixel_format != crtc->fb->pixel_format)
7539 return -EINVAL;
7540
7541 /*
7542 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7543 * Note that pitch changes could also affect these register.
7544 */
7545 if (INTEL_INFO(dev)->gen > 3 &&
7546 (fb->offsets[0] != crtc->fb->offsets[0] ||
7547 fb->pitches[0] != crtc->fb->pitches[0]))
7548 return -EINVAL;
7549
6b95a207
KH		 7550 work = kzalloc(sizeof *work, GFP_KERNEL);
7551 if (work == NULL)
7552 return -ENOMEM;
7553
6b95a207 7554 work->event = event;
b4a98e57 7555 work->crtc = crtc;
4a35f83b 7556 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7557 INIT_WORK(&work->work, intel_unpin_work_fn);
7558
7317c75e
JB		 7559 ret = drm_vblank_get(dev, intel_crtc->pipe);
7560 if (ret)
7561 goto free_work;
7562
6b95a207
KH		 7563 /* We borrow the event spin lock for protecting unpin_work */
7564 spin_lock_irqsave(&dev->event_lock, flags);
7565 if (intel_crtc->unpin_work) {
7566 spin_unlock_irqrestore(&dev->event_lock, flags);
7567 kfree(work);
7317c75e 7568 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7569
7570 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7571 return -EBUSY;
7572 }
7573 intel_crtc->unpin_work = work;
7574 spin_unlock_irqrestore(&dev->event_lock, flags);
7575
b4a98e57
CW		 7576 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7577 flush_workqueue(dev_priv->wq);
7578
79158103
CW		 7579 ret = i915_mutex_lock_interruptible(dev);
7580 if (ret)
7581 goto cleanup;
6b95a207 7582
75dfca80 7583 /* Reference the objects for the scheduled work. */
05394f39
CW		 7584 drm_gem_object_reference(&work->old_fb_obj->base);
7585 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7586
7587 crtc->fb = fb;
96b099fd 7588
e1f99ce6 7589 work->pending_flip_obj = obj;
e1f99ce6 7590
4e5359cd
SF		 7591 work->enable_stall_check = true;
7592
b4a98e57 7593 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7594 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7595
8c9f3aaf
JB		 7596 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7597 if (ret)
7598 goto cleanup_pending;
6b95a207 7599
7782de3b 7600 intel_disable_fbc(dev);
c65355bb 7601 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7602 mutex_unlock(&dev->struct_mutex);
7603
e5510fac
JB		 7604 trace_i915_flip_request(intel_crtc->plane, obj);
7605
6b95a207 7606 return 0;
96b099fd 7607
8c9f3aaf 7608cleanup_pending:
b4a98e57 7609 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7610 crtc->fb = old_fb;
05394f39
CW		 7611 drm_gem_object_unreference(&work->old_fb_obj->base);
7612 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7613 mutex_unlock(&dev->struct_mutex);
7614
79158103 7615cleanup:
96b099fd
CW		 7616 spin_lock_irqsave(&dev->event_lock, flags);
7617 intel_crtc->unpin_work = NULL;
7618 spin_unlock_irqrestore(&dev->event_lock, flags);
7619
7317c75e
JB		 7620 drm_vblank_put(dev, intel_crtc->pipe);
7621free_work:
96b099fd
CW		 7622 kfree(work);
7623
7624 return ret;
6b95a207
KH		 7625}
7626
f6e5b160 7627static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7628 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7629 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7630};
7631
50f56119
DV		 7632static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7633 struct drm_crtc *crtc)
7634{
7635 struct drm_device *dev;
7636 struct drm_crtc *tmp;
7637 int crtc_mask = 1;
47f1c6c9 7638
50f56119 7639 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7640
50f56119 7641 dev = crtc->dev;
47f1c6c9 7642
50f56119
DV		 7643 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7644 if (tmp == crtc)
7645 break;
7646 crtc_mask <<= 1;
7647 }
47f1c6c9 7648
50f56119
DV		 7649 if (encoder->possible_crtcs & crtc_mask)
7650 return true;
7651 return false;
47f1c6c9 7652}
79e53945 7653
9a935856
DV		 7654/**
7655 * intel_modeset_update_staged_output_state
7656 *
7657 * Updates the staged output configuration state, e.g. after we've read out the
7658 * current hw state.
7659 */
7660static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7661{
9a935856
DV		 7662 struct intel_encoder *encoder;
7663 struct intel_connector *connector;
f6e5b160 7664
9a935856
DV		 7665 list_for_each_entry(connector, &dev->mode_config.connector_list,
7666 base.head) {
7667 connector->new_encoder =
7668 to_intel_encoder(connector->base.encoder);
7669 }
f6e5b160 7670
9a935856
DV		 7671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7672 base.head) {
7673 encoder->new_crtc =
7674 to_intel_crtc(encoder->base.crtc);
7675 }
f6e5b160
CW		 7676}
7677
9a935856
DV		 7678/**
7679 * intel_modeset_commit_output_state
7680 *
7681 * This function copies the stage display pipe configuration to the real one.
7682 */
7683static void intel_modeset_commit_output_state(struct drm_device *dev)
7684{
7685 struct intel_encoder *encoder;
7686 struct intel_connector *connector;
f6e5b160 7687
9a935856
DV		 7688 list_for_each_entry(connector, &dev->mode_config.connector_list,
7689 base.head) {
7690 connector->base.encoder = &connector->new_encoder->base;
7691 }
f6e5b160 7692
9a935856
DV		 7693 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7694 base.head) {
7695 encoder->base.crtc = &encoder->new_crtc->base;
7696 }
7697}
7698
050f7aeb
DV		 7699static void
7700connected_sink_compute_bpp(struct intel_connector * connector,
7701 struct intel_crtc_config *pipe_config)
7702{
7703 int bpp = pipe_config->pipe_bpp;
7704
7705 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7706 connector->base.base.id,
7707 drm_get_connector_name(&connector->base));
7708
7709 /* Don't use an invalid EDID bpc value */
7710 if (connector->base.display_info.bpc &&
7711 connector->base.display_info.bpc * 3 < bpp) {
7712 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7713 bpp, connector->base.display_info.bpc*3);
7714 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7715 }
7716
7717 /* Clamp bpp to 8 on screens without EDID 1.4 */
7718 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7719 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7720 bpp);
7721 pipe_config->pipe_bpp = 24;
7722 }
7723}
7724
4e53c2e0 7725static int
050f7aeb
DV		 7726compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7727 struct drm_framebuffer *fb,
7728 struct intel_crtc_config *pipe_config)
4e53c2e0 7729{
050f7aeb
DV		 7730 struct drm_device *dev = crtc->base.dev;
7731 struct intel_connector *connector;
4e53c2e0
DV		 7732 int bpp;
7733
d42264b1
DV		 7734 switch (fb->pixel_format) {
7735 case DRM_FORMAT_C8:
4e53c2e0
DV		 7736 bpp = 8*3; /* since we go through a colormap */
7737 break;
d42264b1
DV		 7738 case DRM_FORMAT_XRGB1555:
7739 case DRM_FORMAT_ARGB1555:
7740 /* checked in intel_framebuffer_init already */
7741 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7742 return -EINVAL;
7743 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7744 bpp = 6*3; /* min is 18bpp */
7745 break;
d42264b1
DV		 7746 case DRM_FORMAT_XBGR8888:
7747 case DRM_FORMAT_ABGR8888:
7748 /* checked in intel_framebuffer_init already */
7749 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7750 return -EINVAL;
7751 case DRM_FORMAT_XRGB8888:
7752 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7753 bpp = 8*3;
7754 break;
d42264b1
DV		 7755 case DRM_FORMAT_XRGB2101010:
7756 case DRM_FORMAT_ARGB2101010:
7757 case DRM_FORMAT_XBGR2101010:
7758 case DRM_FORMAT_ABGR2101010:
7759 /* checked in intel_framebuffer_init already */
7760 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7761 return -EINVAL;
4e53c2e0
DV		 7762 bpp = 10*3;
7763 break;
baba133a 7764 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7765 default:
7766 DRM_DEBUG_KMS("unsupported depth\n");
7767 return -EINVAL;
7768 }
7769
4e53c2e0
DV		 7770 pipe_config->pipe_bpp = bpp;
7771
7772 /* Clamp display bpp to EDID value */
7773 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7774 base.head) {
1b829e05
DV		 7775 if (!connector->new_encoder ||
7776 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7777 continue;
7778
050f7aeb 7779 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7780 }
7781
7782 return bpp;
7783}
7784
c0b03411
DV		 7785static void intel_dump_pipe_config(struct intel_crtc *crtc,
7786 struct intel_crtc_config *pipe_config,
7787 const char *context)
7788{
7789 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7790 context, pipe_name(crtc->pipe));
7791
7792 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7793 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7794 pipe_config->pipe_bpp, pipe_config->dither);
7795 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7796 pipe_config->has_pch_encoder,
7797 pipe_config->fdi_lanes,
7798 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7799 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7800 pipe_config->fdi_m_n.tu);
7801 DRM_DEBUG_KMS("requested mode:\n");
7802 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7803 DRM_DEBUG_KMS("adjusted mode:\n");
7804 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7805 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7806 pipe_config->gmch_pfit.control,
7807 pipe_config->gmch_pfit.pgm_ratios,
7808 pipe_config->gmch_pfit.lvds_border_bits);
7809 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7810 pipe_config->pch_pfit.pos,
7811 pipe_config->pch_pfit.size);
42db64ef 7812 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7813}
7814
accfc0c5
DV		 7815static bool check_encoder_cloning(struct drm_crtc *crtc)
7816{
7817 int num_encoders = 0;
7818 bool uncloneable_encoders = false;
7819 struct intel_encoder *encoder;
7820
7821 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7822 base.head) {
7823 if (&encoder->new_crtc->base != crtc)
7824 continue;
7825
7826 num_encoders++;
7827 if (!encoder->cloneable)
7828 uncloneable_encoders = true;
7829 }
7830
7831 return !(num_encoders > 1 && uncloneable_encoders);
7832}
7833
b8cecdf5
DV		 7834static struct intel_crtc_config *
7835intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7836 struct drm_framebuffer *fb,
b8cecdf5 7837 struct drm_display_mode *mode)
ee7b9f93 7838{
7758a113 7839 struct drm_device *dev = crtc->dev;
7758a113
DV		 7840 struct drm_encoder_helper_funcs *encoder_funcs;
7841 struct intel_encoder *encoder;
b8cecdf5 7842 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7843 int plane_bpp, ret = -EINVAL;
7844 bool retry = true;
ee7b9f93 7845
accfc0c5
DV		 7846 if (!check_encoder_cloning(crtc)) {
7847 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7848 return ERR_PTR(-EINVAL);
7849 }
7850
b8cecdf5
DV		 7851 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7852 if (!pipe_config)
7758a113
DV		 7853 return ERR_PTR(-ENOMEM);
7854
b8cecdf5
DV		 7855 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7856 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7857 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7858 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7859
050f7aeb
DV		 7860 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7861 * plane pixel format and any sink constraints into account. Returns the
7862 * source plane bpp so that dithering can be selected on mismatches
7863 * after encoders and crtc also have had their say. */
7864 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7865 fb, pipe_config);
4e53c2e0
DV		 7866 if (plane_bpp < 0)
7867 goto fail;
7868
e29c22c0 7869encoder_retry:
ef1b460d 7870 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7871 pipe_config->port_clock = 0;
ef1b460d 7872 pipe_config->pixel_multiplier = 1;
ff9a6750 7873
7758a113
DV		 7874 /* Pass our mode to the connectors and the CRTC to give them a chance to
7875 * adjust it according to limitations or connector properties, and also
7876 * a chance to reject the mode entirely.
47f1c6c9 7877 */
7758a113
DV		 7878 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7879 base.head) {
47f1c6c9 7880
7758a113
DV		 7881 if (&encoder->new_crtc->base != crtc)
7882 continue;
7ae89233
DV		 7883
7884 if (encoder->compute_config) {
7885 if (!(encoder->compute_config(encoder, pipe_config))) {
7886 DRM_DEBUG_KMS("Encoder config failure\n");
7887 goto fail;
7888 }
7889
7890 continue;
7891 }
7892
7758a113 7893 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7894 if (!(encoder_funcs->mode_fixup(&encoder->base,
7895 &pipe_config->requested_mode,
7896 &pipe_config->adjusted_mode))) {
7758a113
DV		 7897 DRM_DEBUG_KMS("Encoder fixup failed\n");
7898 goto fail;
7899 }
ee7b9f93 7900 }
47f1c6c9 7901
ff9a6750
DV		 7902 /* Set default port clock if not overwritten by the encoder. Needs to be
7903 * done afterwards in case the encoder adjusts the mode. */
7904 if (!pipe_config->port_clock)
7905 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7906
a43f6e0f 7907 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7908 if (ret < 0) {
7758a113
DV		 7909 DRM_DEBUG_KMS("CRTC fixup failed\n");
7910 goto fail;
ee7b9f93 7911 }
e29c22c0
DV		 7912
7913 if (ret == RETRY) {
7914 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7915 ret = -EINVAL;
7916 goto fail;
7917 }
7918
7919 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7920 retry = false;
7921 goto encoder_retry;
7922 }
7923
4e53c2e0
DV		 7924 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7925 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7926 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7927
b8cecdf5 7928 return pipe_config;
7758a113 7929fail:
b8cecdf5 7930 kfree(pipe_config);
e29c22c0 7931 return ERR_PTR(ret);
ee7b9f93 7932}
47f1c6c9 7933
e2e1ed41
DV		 7934/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7935 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7936static void
7937intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7938 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7939{
7940 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7941 struct drm_device *dev = crtc->dev;
7942 struct intel_encoder *encoder;
7943 struct intel_connector *connector;
7944 struct drm_crtc *tmp_crtc;
79e53945 7945
e2e1ed41 7946 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7947
e2e1ed41
DV		 7948 /* Check which crtcs have changed outputs connected to them, these need
7949 * to be part of the prepare_pipes mask. We don't (yet) support global
7950 * modeset across multiple crtcs, so modeset_pipes will only have one
7951 * bit set at most. */
7952 list_for_each_entry(connector, &dev->mode_config.connector_list,
7953 base.head) {
7954 if (connector->base.encoder == &connector->new_encoder->base)
7955 continue;
79e53945 7956
e2e1ed41
DV		 7957 if (connector->base.encoder) {
7958 tmp_crtc = connector->base.encoder->crtc;
7959
7960 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7961 }
7962
7963 if (connector->new_encoder)
7964 *prepare_pipes |=
7965 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7966 }
7967
e2e1ed41
DV		 7968 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7969 base.head) {
7970 if (encoder->base.crtc == &encoder->new_crtc->base)
7971 continue;
7972
7973 if (encoder->base.crtc) {
7974 tmp_crtc = encoder->base.crtc;
7975
7976 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7977 }
7978
7979 if (encoder->new_crtc)
7980 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7981 }
7982
e2e1ed41
DV		 7983 /* Check for any pipes that will be fully disabled ... */
7984 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7985 base.head) {
7986 bool used = false;
22fd0fab 7987
e2e1ed41
DV		 7988 /* Don't try to disable disabled crtcs. */
7989 if (!intel_crtc->base.enabled)
7990 continue;
7e7d76c3 7991
e2e1ed41
DV		 7992 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7993 base.head) {
7994 if (encoder->new_crtc == intel_crtc)
7995 used = true;
7996 }
7997
7998 if (!used)
7999 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8000 }
8001
e2e1ed41
DV		 8002
8003 /* set_mode is also used to update properties on life display pipes. */
8004 intel_crtc = to_intel_crtc(crtc);
8005 if (crtc->enabled)
8006 *prepare_pipes |= 1 << intel_crtc->pipe;
8007
b6c5164d
DV		 8008 /*
8009 * For simplicity do a full modeset on any pipe where the output routing
8010 * changed. We could be more clever, but that would require us to be
8011 * more careful with calling the relevant encoder->mode_set functions.
8012 */
e2e1ed41
DV		 8013 if (*prepare_pipes)
8014 *modeset_pipes = *prepare_pipes;
8015
8016 /* ... and mask these out. */
8017 *modeset_pipes &= ~(*disable_pipes);
8018 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8019
8020 /*
8021 * HACK: We don't (yet) fully support global modesets. intel_set_config
8022 * obies this rule, but the modeset restore mode of
8023 * intel_modeset_setup_hw_state does not.
8024 */
8025 *modeset_pipes &= 1 << intel_crtc->pipe;
8026 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8027
8028 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8029 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8030}
79e53945 8031
ea9d758d 8032static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8033{
ea9d758d 8034 struct drm_encoder *encoder;
f6e5b160 8035 struct drm_device *dev = crtc->dev;
f6e5b160 8036
ea9d758d
DV		 8037 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8038 if (encoder->crtc == crtc)
8039 return true;
8040
8041 return false;
8042}
8043
8044static void
8045intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8046{
8047 struct intel_encoder *intel_encoder;
8048 struct intel_crtc *intel_crtc;
8049 struct drm_connector *connector;
8050
8051 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8052 base.head) {
8053 if (!intel_encoder->base.crtc)
8054 continue;
8055
8056 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8057
8058 if (prepare_pipes & (1 << intel_crtc->pipe))
8059 intel_encoder->connectors_active = false;
8060 }
8061
8062 intel_modeset_commit_output_state(dev);
8063
8064 /* Update computed state. */
8065 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8066 base.head) {
8067 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8068 }
8069
8070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8071 if (!connector->encoder || !connector->encoder->crtc)
8072 continue;
8073
8074 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8075
8076 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8077 struct drm_property *dpms_property =
8078 dev->mode_config.dpms_property;
8079
ea9d758d 8080 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8081 drm_object_property_set_value(&connector->base,
68d34720
DV		 8082 dpms_property,
8083 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8084
8085 intel_encoder = to_intel_encoder(connector->encoder);
8086 intel_encoder->connectors_active = true;
8087 }
8088 }
8089
8090}
8091
25c5b266
DV		 8092#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8093 list_for_each_entry((intel_crtc), \
8094 &(dev)->mode_config.crtc_list, \
8095 base.head) \
0973f18f 8096 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8097
0e8ffe1b 8098static bool
2fa2fe9a
DV		 8099intel_pipe_config_compare(struct drm_device *dev,
8100 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8101 struct intel_crtc_config *pipe_config)
8102{
08a24034
DV		 8103#define PIPE_CONF_CHECK_I(name) \
8104 if (current_config->name != pipe_config->name) { \
8105 DRM_ERROR("mismatch in " #name " " \
8106 "(expected %i, found %i)\n", \
8107 current_config->name, \
8108 pipe_config->name); \
8109 return false; \
88adfff1
DV		 8110 }
8111
1bd1bd80
DV		 8112#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8113 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8114 DRM_ERROR("mismatch in " #name " " \
8115 "(expected %i, found %i)\n", \
8116 current_config->name & (mask), \
8117 pipe_config->name & (mask)); \
8118 return false; \
8119 }
8120
bb760063
DV		 8121#define PIPE_CONF_QUIRK(quirk) \
8122 ((current_config->quirks | pipe_config->quirks) & (quirk))
8123
eccb140b
DV		 8124 PIPE_CONF_CHECK_I(cpu_transcoder);
8125
08a24034
DV		 8126 PIPE_CONF_CHECK_I(has_pch_encoder);
8127 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8128 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8129 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8130 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8131 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8132 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8133
1bd1bd80
DV		 8134 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8135 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8136 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8137 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8138 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8139 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8140
8141 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8142 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8143 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8144 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8145 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8146 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8147
6c49f241
DV		 8148 if (!HAS_PCH_SPLIT(dev))
8149 PIPE_CONF_CHECK_I(pixel_multiplier);
8150
1bd1bd80
DV		 8151 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8152 DRM_MODE_FLAG_INTERLACE);
8153
bb760063
DV		 8154 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8155 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8156 DRM_MODE_FLAG_PHSYNC);
8157 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8158 DRM_MODE_FLAG_NHSYNC);
8159 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8160 DRM_MODE_FLAG_PVSYNC);
8161 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8162 DRM_MODE_FLAG_NVSYNC);
8163 }
045ac3b5 8164
1bd1bd80
DV		 8165 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8166 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8167
2fa2fe9a
DV		 8168 PIPE_CONF_CHECK_I(gmch_pfit.control);
8169 /* pfit ratios are autocomputed by the hw on gen4+ */
8170 if (INTEL_INFO(dev)->gen < 4)
8171 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8172 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8173 PIPE_CONF_CHECK_I(pch_pfit.pos);
8174 PIPE_CONF_CHECK_I(pch_pfit.size);
8175
42db64ef
PZ		 8176 PIPE_CONF_CHECK_I(ips_enabled);
8177
c0d43d62
DV		 8178 PIPE_CONF_CHECK_I(shared_dpll);
8179
08a24034 8180#undef PIPE_CONF_CHECK_I
1bd1bd80 8181#undef PIPE_CONF_CHECK_FLAGS
bb760063 8182#undef PIPE_CONF_QUIRK
627eb5a3 8183
0e8ffe1b
DV		 8184 return true;
8185}
8186
b980514c 8187void
8af6cf88
DV		 8188intel_modeset_check_state(struct drm_device *dev)
8189{
0e8ffe1b 8190 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8191 struct intel_crtc *crtc;
8192 struct intel_encoder *encoder;
8193 struct intel_connector *connector;
0e8ffe1b 8194 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8195
8196 list_for_each_entry(connector, &dev->mode_config.connector_list,
8197 base.head) {
8198 /* This also checks the encoder/connector hw state with the
8199 * ->get_hw_state callbacks. */
8200 intel_connector_check_state(connector);
8201
8202 WARN(&connector->new_encoder->base != connector->base.encoder,
8203 "connector's staged encoder doesn't match current encoder\n");
8204 }
8205
8206 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8207 base.head) {
8208 bool enabled = false;
8209 bool active = false;
8210 enum pipe pipe, tracked_pipe;
8211
8212 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8213 encoder->base.base.id,
8214 drm_get_encoder_name(&encoder->base));
8215
8216 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8217 "encoder's stage crtc doesn't match current crtc\n");
8218 WARN(encoder->connectors_active && !encoder->base.crtc,
8219 "encoder's active_connectors set, but no crtc\n");
8220
8221 list_for_each_entry(connector, &dev->mode_config.connector_list,
8222 base.head) {
8223 if (connector->base.encoder != &encoder->base)
8224 continue;
8225 enabled = true;
8226 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8227 active = true;
8228 }
8229 WARN(!!encoder->base.crtc != enabled,
8230 "encoder's enabled state mismatch "
8231 "(expected %i, found %i)\n",
8232 !!encoder->base.crtc, enabled);
8233 WARN(active && !encoder->base.crtc,
8234 "active encoder with no crtc\n");
8235
8236 WARN(encoder->connectors_active != active,
8237 "encoder's computed active state doesn't match tracked active state "
8238 "(expected %i, found %i)\n", active, encoder->connectors_active);
8239
8240 active = encoder->get_hw_state(encoder, &pipe);
8241 WARN(active != encoder->connectors_active,
8242 "encoder's hw state doesn't match sw tracking "
8243 "(expected %i, found %i)\n",
8244 encoder->connectors_active, active);
8245
8246 if (!encoder->base.crtc)
8247 continue;
8248
8249 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8250 WARN(active && pipe != tracked_pipe,
8251 "active encoder's pipe doesn't match"
8252 "(expected %i, found %i)\n",
8253 tracked_pipe, pipe);
8254
8255 }
8256
8257 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8258 base.head) {
8259 bool enabled = false;
8260 bool active = false;
8261
045ac3b5
JB		 8262 memset(&pipe_config, 0, sizeof(pipe_config));
8263
8af6cf88
DV		 8264 DRM_DEBUG_KMS("[CRTC:%d]\n",
8265 crtc->base.base.id);
8266
8267 WARN(crtc->active && !crtc->base.enabled,
8268 "active crtc, but not enabled in sw tracking\n");
8269
8270 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8271 base.head) {
8272 if (encoder->base.crtc != &crtc->base)
8273 continue;
8274 enabled = true;
8275 if (encoder->connectors_active)
8276 active = true;
8277 }
6c49f241 8278
8af6cf88
DV		 8279 WARN(active != crtc->active,
8280 "crtc's computed active state doesn't match tracked active state "
8281 "(expected %i, found %i)\n", active, crtc->active);
8282 WARN(enabled != crtc->base.enabled,
8283 "crtc's computed enabled state doesn't match tracked enabled state "
8284 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8285
0e8ffe1b
DV		 8286 active = dev_priv->display.get_pipe_config(crtc,
8287 &pipe_config);
6c49f241
DV		 8288 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8289 base.head) {
8290 if (encoder->base.crtc != &crtc->base)
8291 continue;
8292 if (encoder->get_config)
8293 encoder->get_config(encoder, &pipe_config);
8294 }
8295
0e8ffe1b
DV		 8296 WARN(crtc->active != active,
8297 "crtc active state doesn't match with hw state "
8298 "(expected %i, found %i)\n", crtc->active, active);
8299
c0b03411
DV		 8300 if (active &&
8301 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8302 WARN(1, "pipe state doesn't match!\n");
8303 intel_dump_pipe_config(crtc, &pipe_config,
8304 "[hw state]");
8305 intel_dump_pipe_config(crtc, &crtc->config,
8306 "[sw state]");
8307 }
8af6cf88
DV		 8308 }
8309}
8310
f30da187
DV		 8311static int __intel_set_mode(struct drm_crtc *crtc,
8312 struct drm_display_mode *mode,
8313 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8314{
8315 struct drm_device *dev = crtc->dev;
dbf2b54e 8316 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8317 struct drm_display_mode *saved_mode, *saved_hwmode;
8318 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8319 struct intel_crtc *intel_crtc;
8320 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8321 int ret = 0;
a6778b3c 8322
3ac18232 8323 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8324 if (!saved_mode)
8325 return -ENOMEM;
3ac18232 8326 saved_hwmode = saved_mode + 1;
a6778b3c 8327
e2e1ed41 8328 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8329 &prepare_pipes, &disable_pipes);
8330
3ac18232
TG		 8331 *saved_hwmode = crtc->hwmode;
8332 *saved_mode = crtc->mode;
a6778b3c 8333
25c5b266
DV		 8334 /* Hack: Because we don't (yet) support global modeset on multiple
8335 * crtcs, we don't keep track of the new mode for more than one crtc.
8336 * Hence simply check whether any bit is set in modeset_pipes in all the
8337 * pieces of code that are not yet converted to deal with mutliple crtcs
8338 * changing their mode at the same time. */
25c5b266 8339 if (modeset_pipes) {
4e53c2e0 8340 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8341 if (IS_ERR(pipe_config)) {
8342 ret = PTR_ERR(pipe_config);
8343 pipe_config = NULL;
8344
3ac18232 8345 goto out;
25c5b266 8346 }
c0b03411
DV		 8347 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8348 "[modeset]");
25c5b266 8349 }
a6778b3c 8350
460da916
DV		 8351 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8352 intel_crtc_disable(&intel_crtc->base);
8353
ea9d758d
DV		 8354 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8355 if (intel_crtc->base.enabled)
8356 dev_priv->display.crtc_disable(&intel_crtc->base);
8357 }
a6778b3c 8358
6c4c86f5
DV		 8359 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8360 * to set it here already despite that we pass it down the callchain.
f6e5b160 8361 */
b8cecdf5 8362 if (modeset_pipes) {
25c5b266 8363 crtc->mode = *mode;
b8cecdf5
DV		 8364 /* mode_set/enable/disable functions rely on a correct pipe
8365 * config. */
8366 to_intel_crtc(crtc)->config = *pipe_config;
8367 }
7758a113 8368
ea9d758d
DV		 8369 /* Only after disabling all output pipelines that will be changed can we
8370 * update the the output configuration. */
8371 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8372
47fab737
DV		 8373 if (dev_priv->display.modeset_global_resources)
8374 dev_priv->display.modeset_global_resources(dev);
8375
a6778b3c
DV		 8376 /* Set up the DPLL and any encoders state that needs to adjust or depend
8377 * on the DPLL.
f6e5b160 8378 */
25c5b266 8379 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8380 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8381 x, y, fb);
8382 if (ret)
8383 goto done;
a6778b3c
DV		 8384 }
8385
8386 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8387 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8388 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8389
25c5b266
DV		 8390 if (modeset_pipes) {
8391 /* Store real post-adjustment hardware mode. */
b8cecdf5 8392 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8393
25c5b266
DV		 8394 /* Calculate and store various constants which
8395 * are later needed by vblank and swap-completion
8396 * timestamping. They are derived from true hwmode.
8397 */
8398 drm_calc_timestamping_constants(crtc);
8399 }
a6778b3c
DV		 8400
8401 /* FIXME: add subpixel order */
8402done:
c0c36b94 8403 if (ret && crtc->enabled) {
3ac18232
TG		 8404 crtc->hwmode = *saved_hwmode;
8405 crtc->mode = *saved_mode;
a6778b3c
DV		 8406 }
8407
3ac18232 8408out:
b8cecdf5 8409 kfree(pipe_config);
3ac18232 8410 kfree(saved_mode);
a6778b3c 8411 return ret;
f6e5b160
CW		 8412}
8413
f30da187
DV		 8414int intel_set_mode(struct drm_crtc *crtc,
8415 struct drm_display_mode *mode,
8416 int x, int y, struct drm_framebuffer *fb)
8417{
8418 int ret;
8419
8420 ret = __intel_set_mode(crtc, mode, x, y, fb);
8421
8422 if (ret == 0)
8423 intel_modeset_check_state(crtc->dev);
8424
8425 return ret;
8426}
8427
c0c36b94
CW		 8428void intel_crtc_restore_mode(struct drm_crtc *crtc)
8429{
8430 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8431}
8432
25c5b266
DV		 8433#undef for_each_intel_crtc_masked
8434
d9e55608
DV		 8435static void intel_set_config_free(struct intel_set_config *config)
8436{
8437 if (!config)
8438 return;
8439
1aa4b628
DV		 8440 kfree(config->save_connector_encoders);
8441 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8442 kfree(config);
8443}
8444
85f9eb71
DV		 8445static int intel_set_config_save_state(struct drm_device *dev,
8446 struct intel_set_config *config)
8447{
85f9eb71
DV		 8448 struct drm_encoder *encoder;
8449 struct drm_connector *connector;
8450 int count;
8451
1aa4b628
DV		 8452 config->save_encoder_crtcs =
8453 kcalloc(dev->mode_config.num_encoder,
8454 sizeof(struct drm_crtc *), GFP_KERNEL);
8455 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8456 return -ENOMEM;
8457
1aa4b628
DV		 8458 config->save_connector_encoders =
8459 kcalloc(dev->mode_config.num_connector,
8460 sizeof(struct drm_encoder *), GFP_KERNEL);
8461 if (!config->save_connector_encoders)
85f9eb71
DV		 8462 return -ENOMEM;
8463
8464 /* Copy data. Note that driver private data is not affected.
8465 * Should anything bad happen only the expected state is
8466 * restored, not the drivers personal bookkeeping.
8467 */
85f9eb71
DV		 8468 count = 0;
8469 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8470 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8471 }
8472
8473 count = 0;
8474 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8475 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8476 }
8477
8478 return 0;
8479}
8480
8481static void intel_set_config_restore_state(struct drm_device *dev,
8482 struct intel_set_config *config)
8483{
9a935856
DV		 8484 struct intel_encoder *encoder;
8485 struct intel_connector *connector;
85f9eb71
DV		 8486 int count;
8487
85f9eb71 8488 count = 0;
9a935856
DV		 8489 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8490 encoder->new_crtc =
8491 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8492 }
8493
8494 count = 0;
9a935856
DV		 8495 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8496 connector->new_encoder =
8497 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8498 }
8499}
8500
5e2b584e
DV		 8501static void
8502intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8503 struct intel_set_config *config)
8504{
8505
8506 /* We should be able to check here if the fb has the same properties
8507 * and then just flip_or_move it */
8508 if (set->crtc->fb != set->fb) {
8509 /* If we have no fb then treat it as a full mode set */
8510 if (set->crtc->fb == NULL) {
8511 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8512 config->mode_changed = true;
8513 } else if (set->fb == NULL) {
8514 config->mode_changed = true;
72f4901e
DV		 8515 } else if (set->fb->pixel_format !=
8516 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8517 config->mode_changed = true;
8518 } else
8519 config->fb_changed = true;
8520 }
8521
835c5873 8522 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8523 config->fb_changed = true;
8524
8525 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8526 DRM_DEBUG_KMS("modes are different, full mode set\n");
8527 drm_mode_debug_printmodeline(&set->crtc->mode);
8528 drm_mode_debug_printmodeline(set->mode);
8529 config->mode_changed = true;
8530 }
8531}
8532
2e431051 8533static int
9a935856
DV		 8534intel_modeset_stage_output_state(struct drm_device *dev,
8535 struct drm_mode_set *set,
8536 struct intel_set_config *config)
50f56119 8537{
85f9eb71 8538 struct drm_crtc *new_crtc;
9a935856
DV		 8539 struct intel_connector *connector;
8540 struct intel_encoder *encoder;
2e431051 8541 int count, ro;
50f56119 8542
9abdda74 8543 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8544 * of connectors. For paranoia, double-check this. */
8545 WARN_ON(!set->fb && (set->num_connectors != 0));
8546 WARN_ON(set->fb && (set->num_connectors == 0));
8547
50f56119 8548 count = 0;
9a935856
DV		 8549 list_for_each_entry(connector, &dev->mode_config.connector_list,
8550 base.head) {
8551 /* Otherwise traverse passed in connector list and get encoders
8552 * for them. */
50f56119 8553 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8554 if (set->connectors[ro] == &connector->base) {
8555 connector->new_encoder = connector->encoder;
50f56119
DV		 8556 break;
8557 }
8558 }
8559
9a935856
DV		 8560 /* If we disable the crtc, disable all its connectors. Also, if
8561 * the connector is on the changing crtc but not on the new
8562 * connector list, disable it. */
8563 if ((!set->fb || ro == set->num_connectors) &&
8564 connector->base.encoder &&
8565 connector->base.encoder->crtc == set->crtc) {
8566 connector->new_encoder = NULL;
8567
8568 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8569 connector->base.base.id,
8570 drm_get_connector_name(&connector->base));
8571 }
8572
8573
8574 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8575 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8576 config->mode_changed = true;
50f56119
DV		 8577 }
8578 }
9a935856 8579 /* connector->new_encoder is now updated for all connectors. */
50f56119 8580
9a935856 8581 /* Update crtc of enabled connectors. */
50f56119 8582 count = 0;
9a935856
DV		 8583 list_for_each_entry(connector, &dev->mode_config.connector_list,
8584 base.head) {
8585 if (!connector->new_encoder)
50f56119
DV		 8586 continue;
8587
9a935856 8588 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8589
8590 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8591 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8592 new_crtc = set->crtc;
8593 }
8594
8595 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8596 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8597 new_crtc)) {
5e2b584e 8598 return -EINVAL;
50f56119 8599 }
9a935856
DV		 8600 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8601
8602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8603 connector->base.base.id,
8604 drm_get_connector_name(&connector->base),
8605 new_crtc->base.id);
8606 }
8607
8608 /* Check for any encoders that needs to be disabled. */
8609 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8610 base.head) {
8611 list_for_each_entry(connector,
8612 &dev->mode_config.connector_list,
8613 base.head) {
8614 if (connector->new_encoder == encoder) {
8615 WARN_ON(!connector->new_encoder->new_crtc);
8616
8617 goto next_encoder;
8618 }
8619 }
8620 encoder->new_crtc = NULL;
8621next_encoder:
8622 /* Only now check for crtc changes so we don't miss encoders
8623 * that will be disabled. */
8624 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8625 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8626 config->mode_changed = true;
50f56119
DV		 8627 }
8628 }
9a935856 8629 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8630
2e431051
DV		 8631 return 0;
8632}
8633
8634static int intel_crtc_set_config(struct drm_mode_set *set)
8635{
8636 struct drm_device *dev;
2e431051
DV		 8637 struct drm_mode_set save_set;
8638 struct intel_set_config *config;
8639 int ret;
2e431051 8640
8d3e375e
DV		 8641 BUG_ON(!set);
8642 BUG_ON(!set->crtc);
8643 BUG_ON(!set->crtc->helper_private);
2e431051 8644
7e53f3a4
DV		 8645 /* Enforce sane interface api - has been abused by the fb helper. */
8646 BUG_ON(!set->mode && set->fb);
8647 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8648
2e431051
DV		 8649 if (set->fb) {
8650 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8651 set->crtc->base.id, set->fb->base.id,
8652 (int)set->num_connectors, set->x, set->y);
8653 } else {
8654 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8655 }
8656
8657 dev = set->crtc->dev;
8658
8659 ret = -ENOMEM;
8660 config = kzalloc(sizeof(*config), GFP_KERNEL);
8661 if (!config)
8662 goto out_config;
8663
8664 ret = intel_set_config_save_state(dev, config);
8665 if (ret)
8666 goto out_config;
8667
8668 save_set.crtc = set->crtc;
8669 save_set.mode = &set->crtc->mode;
8670 save_set.x = set->crtc->x;
8671 save_set.y = set->crtc->y;
8672 save_set.fb = set->crtc->fb;
8673
8674 /* Compute whether we need a full modeset, only an fb base update or no
8675 * change at all. In the future we might also check whether only the
8676 * mode changed, e.g. for LVDS where we only change the panel fitter in
8677 * such cases. */
8678 intel_set_config_compute_mode_changes(set, config);
8679
9a935856 8680 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8681 if (ret)
8682 goto fail;
8683
5e2b584e 8684 if (config->mode_changed) {
c0c36b94
CW		 8685 ret = intel_set_mode(set->crtc, set->mode,
8686 set->x, set->y, set->fb);
8687 if (ret) {
8688 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8689 set->crtc->base.id, ret);
87f1faa6
DV		 8690 goto fail;
8691 }
5e2b584e 8692 } else if (config->fb_changed) {
4878cae2
VS		 8693 intel_crtc_wait_for_pending_flips(set->crtc);
8694
4f660f49 8695 ret = intel_pipe_set_base(set->crtc,
94352cf9 8696 set->x, set->y, set->fb);
50f56119
DV		 8697 }
8698
d9e55608
DV		 8699 intel_set_config_free(config);
8700
50f56119
DV		 8701 return 0;
8702
8703fail:
85f9eb71 8704 intel_set_config_restore_state(dev, config);
50f56119
DV		 8705
8706 /* Try to restore the config */
5e2b584e 8707 if (config->mode_changed &&
c0c36b94
CW		 8708 intel_set_mode(save_set.crtc, save_set.mode,
8709 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8710 DRM_ERROR("failed to restore config after modeset failure\n");
8711
d9e55608
DV		 8712out_config:
8713 intel_set_config_free(config);
50f56119
DV		 8714 return ret;
8715}
f6e5b160
CW		 8716
8717static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8718 .cursor_set = intel_crtc_cursor_set,
8719 .cursor_move = intel_crtc_cursor_move,
8720 .gamma_set = intel_crtc_gamma_set,
50f56119 8721 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8722 .destroy = intel_crtc_destroy,
8723 .page_flip = intel_crtc_page_flip,
8724};
8725
79f689aa
PZ		 8726static void intel_cpu_pll_init(struct drm_device *dev)
8727{
affa9354 8728 if (HAS_DDI(dev))
79f689aa
PZ		 8729 intel_ddi_pll_init(dev);
8730}
8731
46edb027
DV		 8732static char *ibx_pch_dpll_names[] = {
8733 "PCH DPLL A",
8734 "PCH DPLL B",
8735};
8736
7c74ade1 8737static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93
JB		 8738{
8739 drm_i915_private_t *dev_priv = dev->dev_private;
8740 int i;
8741
7c74ade1 8742 dev_priv->num_shared_dpll = 2;
ee7b9f93 8743
e72f9fbf 8744 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8745 dev_priv->shared_dplls[i].id = i;
8746 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
ee7b9f93
JB		 8747 }
8748}
8749
7c74ade1
DV		 8750static void intel_shared_dpll_init(struct drm_device *dev)
8751{
8752 drm_i915_private_t *dev_priv = dev->dev_private;
8753
8754 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8755 ibx_pch_dpll_init(dev);
8756 else
8757 dev_priv->num_shared_dpll = 0;
8758
8759 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8760 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8761 dev_priv->num_shared_dpll);
8762}
8763
b358d0a6 8764static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8765{
22fd0fab 8766 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8767 struct intel_crtc *intel_crtc;
8768 int i;
8769
8770 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8771 if (intel_crtc == NULL)
8772 return;
8773
8774 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8775
8776 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8777 for (i = 0; i < 256; i++) {
8778 intel_crtc->lut_r[i] = i;
8779 intel_crtc->lut_g[i] = i;
8780 intel_crtc->lut_b[i] = i;
8781 }
8782
80824003
JB		 8783 /* Swap pipes & planes for FBC on pre-965 */
8784 intel_crtc->pipe = pipe;
8785 intel_crtc->plane = pipe;
e2e767ab 8786 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8787 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8788 intel_crtc->plane = !pipe;
80824003
JB		 8789 }
8790
22fd0fab
JB		 8791 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8792 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8793 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8794 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8795
79e53945 8796 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8797}
8798
08d7b3d1 8799int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8800 struct drm_file *file)
08d7b3d1 8801{
08d7b3d1 8802 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8803 struct drm_mode_object *drmmode_obj;
8804 struct intel_crtc *crtc;
08d7b3d1 8805
1cff8f6b
DV		 8806 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8807 return -ENODEV;
08d7b3d1 8808
c05422d5
DV		 8809 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8810 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8811
c05422d5 8812 if (!drmmode_obj) {
08d7b3d1
CW		 8813 DRM_ERROR("no such CRTC id\n");
8814 return -EINVAL;
8815 }
8816
c05422d5
DV		 8817 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8818 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8819
c05422d5 8820 return 0;
08d7b3d1
CW		 8821}
8822
66a9278e 8823static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8824{
66a9278e
DV		 8825 struct drm_device *dev = encoder->base.dev;
8826 struct intel_encoder *source_encoder;
79e53945 8827 int index_mask = 0;
79e53945
JB		 8828 int entry = 0;
8829
66a9278e
DV		 8830 list_for_each_entry(source_encoder,
8831 &dev->mode_config.encoder_list, base.head) {
8832
8833 if (encoder == source_encoder)
79e53945 8834 index_mask |= (1 << entry);
66a9278e
DV		 8835
8836 /* Intel hw has only one MUX where enocoders could be cloned. */
8837 if (encoder->cloneable && source_encoder->cloneable)
8838 index_mask |= (1 << entry);
8839
79e53945
JB		 8840 entry++;
8841 }
4ef69c7a 8842
79e53945
JB		 8843 return index_mask;
8844}
8845
4d302442
CW		 8846static bool has_edp_a(struct drm_device *dev)
8847{
8848 struct drm_i915_private *dev_priv = dev->dev_private;
8849
8850 if (!IS_MOBILE(dev))
8851 return false;
8852
8853 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8854 return false;
8855
8856 if (IS_GEN5(dev) &&
8857 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8858 return false;
8859
8860 return true;
8861}
8862
79e53945
JB		 8863static void intel_setup_outputs(struct drm_device *dev)
8864{
725e30ad 8865 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8866 struct intel_encoder *encoder;
cb0953d7 8867 bool dpd_is_edp = false;
f3cfcba6 8868 bool has_lvds;
79e53945 8869
f3cfcba6 8870 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8871 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8872 /* disable the panel fitter on everything but LVDS */
8873 I915_WRITE(PFIT_CONTROL, 0);
8874 }
79e53945 8875
c40c0f5b 8876 if (!IS_ULT(dev))
79935fca 8877 intel_crt_init(dev);
cb0953d7 8878
affa9354 8879 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8880 int found;
8881
8882 /* Haswell uses DDI functions to detect digital outputs */
8883 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8884 /* DDI A only supports eDP */
8885 if (found)
8886 intel_ddi_init(dev, PORT_A);
8887
8888 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8889 * register */
8890 found = I915_READ(SFUSE_STRAP);
8891
8892 if (found & SFUSE_STRAP_DDIB_DETECTED)
8893 intel_ddi_init(dev, PORT_B);
8894 if (found & SFUSE_STRAP_DDIC_DETECTED)
8895 intel_ddi_init(dev, PORT_C);
8896 if (found & SFUSE_STRAP_DDID_DETECTED)
8897 intel_ddi_init(dev, PORT_D);
8898 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8899 int found;
270b3042
DV		 8900 dpd_is_edp = intel_dpd_is_edp(dev);
8901
8902 if (has_edp_a(dev))
8903 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8904
dc0fa718 8905 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8906 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8907 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8908 if (!found)
e2debe91 8909 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8910 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8911 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8912 }
8913
dc0fa718 8914 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8915 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8916
dc0fa718 8917 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8918 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8919
5eb08b69 8920 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8921 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8922
270b3042 8923 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8924 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8925 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8926 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8927 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8928 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8929
dc0fa718 8930 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8931 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8932 PORT_B);
67cfc203
VS		 8933 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8934 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8935 }
103a196f 8936 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8937 bool found = false;
7d57382e 8938
e2debe91 8939 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8940 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8941 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8942 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8943 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8944 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8945 }
27185ae1 8946
e7281eab 8947 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8948 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8949 }
13520b05
KH		 8950
8951 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8952
e2debe91 8953 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8954 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8955 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8956 }
27185ae1 8957
e2debe91 8958 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8959
b01f2c3a
JB		 8960 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8961 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8962 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8963 }
e7281eab 8964 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8965 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8966 }
27185ae1 8967
b01f2c3a 8968 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8969 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8970 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8971 } else if (IS_GEN2(dev))
79e53945
JB		 8972 intel_dvo_init(dev);
8973
103a196f 8974 if (SUPPORTS_TV(dev))
79e53945
JB		 8975 intel_tv_init(dev);
8976
4ef69c7a
CW		 8977 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8978 encoder->base.possible_crtcs = encoder->crtc_mask;
8979 encoder->base.possible_clones =
66a9278e 8980 intel_encoder_clones(encoder);
79e53945 8981 }
47356eb6 8982
dde86e2d 8983 intel_init_pch_refclk(dev);
270b3042
DV		 8984
8985 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8986}
8987
8988static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8989{
8990 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8991
8992 drm_framebuffer_cleanup(fb);
05394f39 8993 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8994
8995 kfree(intel_fb);
8996}
8997
8998static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8999 struct drm_file *file,
79e53945
JB		 9000 unsigned int *handle)
9001{
9002 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9003 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9004
05394f39 9005 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9006}
9007
9008static const struct drm_framebuffer_funcs intel_fb_funcs = {
9009 .destroy = intel_user_framebuffer_destroy,
9010 .create_handle = intel_user_framebuffer_create_handle,
9011};
9012
38651674
DA		 9013int intel_framebuffer_init(struct drm_device *dev,
9014 struct intel_framebuffer *intel_fb,
308e5bcb 9015 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9016 struct drm_i915_gem_object *obj)
79e53945 9017{
79e53945
JB		 9018 int ret;
9019
c16ed4be
CW		 9020 if (obj->tiling_mode == I915_TILING_Y) {
9021 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9022 return -EINVAL;
c16ed4be 9023 }
57cd6508 9024
c16ed4be
CW		 9025 if (mode_cmd->pitches[0] & 63) {
9026 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9027 mode_cmd->pitches[0]);
57cd6508 9028 return -EINVAL;
c16ed4be 9029 }
57cd6508 9030
5d7bd705 9031 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9032 if (mode_cmd->pitches[0] > 32768) {
9033 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9034 mode_cmd->pitches[0]);
5d7bd705 9035 return -EINVAL;
c16ed4be 9036 }
5d7bd705
VS		 9037
9038 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9039 mode_cmd->pitches[0] != obj->stride) {
9040 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9041 mode_cmd->pitches[0], obj->stride);
5d7bd705 9042 return -EINVAL;
c16ed4be 9043 }
5d7bd705 9044
57779d06 9045 /* Reject formats not supported by any plane early. */
308e5bcb 9046 switch (mode_cmd->pixel_format) {
57779d06 9047 case DRM_FORMAT_C8:
04b3924d
VS		 9048 case DRM_FORMAT_RGB565:
9049 case DRM_FORMAT_XRGB8888:
9050 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9051 break;
9052 case DRM_FORMAT_XRGB1555:
9053 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9054 if (INTEL_INFO(dev)->gen > 3) {
9055 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9056 return -EINVAL;
c16ed4be 9057 }
57779d06
VS		 9058 break;
9059 case DRM_FORMAT_XBGR8888:
9060 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9061 case DRM_FORMAT_XRGB2101010:
9062 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9063 case DRM_FORMAT_XBGR2101010:
9064 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9065 if (INTEL_INFO(dev)->gen < 4) {
9066 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9067 return -EINVAL;
c16ed4be 9068 }
b5626747 9069 break;
04b3924d
VS		 9070 case DRM_FORMAT_YUYV:
9071 case DRM_FORMAT_UYVY:
9072 case DRM_FORMAT_YVYU:
9073 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9074 if (INTEL_INFO(dev)->gen < 5) {
9075 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9076 return -EINVAL;
c16ed4be 9077 }
57cd6508
CW		 9078 break;
9079 default:
c16ed4be 9080 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9081 return -EINVAL;
9082 }
9083
90f9a336
VS		 9084 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9085 if (mode_cmd->offsets[0] != 0)
9086 return -EINVAL;
9087
c7d73f6a
DV		 9088 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9089 intel_fb->obj = obj;
9090
79e53945
JB		 9091 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9092 if (ret) {
9093 DRM_ERROR("framebuffer init failed %d\n", ret);
9094 return ret;
9095 }
9096
79e53945
JB		 9097 return 0;
9098}
9099
79e53945
JB		 9100static struct drm_framebuffer *
9101intel_user_framebuffer_create(struct drm_device *dev,
9102 struct drm_file *filp,
308e5bcb 9103 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9104{
05394f39 9105 struct drm_i915_gem_object *obj;
79e53945 9106
308e5bcb
JB		 9107 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9108 mode_cmd->handles[0]));
c8725226 9109 if (&obj->base == NULL)
cce13ff7 9110 return ERR_PTR(-ENOENT);
79e53945 9111
d2dff872 9112 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9113}
9114
79e53945 9115static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9116 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9117 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9118};
9119
e70236a8
JB		 9120/* Set up chip specific display functions */
9121static void intel_init_display(struct drm_device *dev)
9122{
9123 struct drm_i915_private *dev_priv = dev->dev_private;
9124
ee9300bb
DV		 9125 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9126 dev_priv->display.find_dpll = g4x_find_best_dpll;
9127 else if (IS_VALLEYVIEW(dev))
9128 dev_priv->display.find_dpll = vlv_find_best_dpll;
9129 else if (IS_PINEVIEW(dev))
9130 dev_priv->display.find_dpll = pnv_find_best_dpll;
9131 else
9132 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9133
affa9354 9134 if (HAS_DDI(dev)) {
0e8ffe1b 9135 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9136 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9137 dev_priv->display.crtc_enable = haswell_crtc_enable;
9138 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9139 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9140 dev_priv->display.update_plane = ironlake_update_plane;
9141 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9142 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9143 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9144 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9145 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9146 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9147 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9148 } else if (IS_VALLEYVIEW(dev)) {
9149 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9150 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9151 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9152 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9153 dev_priv->display.off = i9xx_crtc_off;
9154 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9155 } else {
0e8ffe1b 9156 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9157 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9158 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9159 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9160 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9161 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9162 }
e70236a8 9163
e70236a8 9164 /* Returns the core display clock speed */
25eb05fc
JB		 9165 if (IS_VALLEYVIEW(dev))
9166 dev_priv->display.get_display_clock_speed =
9167 valleyview_get_display_clock_speed;
9168 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9169 dev_priv->display.get_display_clock_speed =
9170 i945_get_display_clock_speed;
9171 else if (IS_I915G(dev))
9172 dev_priv->display.get_display_clock_speed =
9173 i915_get_display_clock_speed;
f2b115e6 9174 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9175 dev_priv->display.get_display_clock_speed =
9176 i9xx_misc_get_display_clock_speed;
9177 else if (IS_I915GM(dev))
9178 dev_priv->display.get_display_clock_speed =
9179 i915gm_get_display_clock_speed;
9180 else if (IS_I865G(dev))
9181 dev_priv->display.get_display_clock_speed =
9182 i865_get_display_clock_speed;
f0f8a9ce 9183 else if (IS_I85X(dev))
e70236a8
JB		 9184 dev_priv->display.get_display_clock_speed =
9185 i855_get_display_clock_speed;
9186 else /* 852, 830 */
9187 dev_priv->display.get_display_clock_speed =
9188 i830_get_display_clock_speed;
9189
7f8a8569 9190 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9191 if (IS_GEN5(dev)) {
674cf967 9192 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9193 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9194 } else if (IS_GEN6(dev)) {
674cf967 9195 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9196 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9197 } else if (IS_IVYBRIDGE(dev)) {
9198 /* FIXME: detect B0+ stepping and use auto training */
9199 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9200 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9201 dev_priv->display.modeset_global_resources =
9202 ivb_modeset_global_resources;
c82e4d26
ED		 9203 } else if (IS_HASWELL(dev)) {
9204 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9205 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9206 dev_priv->display.modeset_global_resources =
9207 haswell_modeset_global_resources;
a0e63c22 9208 }
6067aaea 9209 } else if (IS_G4X(dev)) {
e0dac65e 9210 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9211 }
8c9f3aaf
JB		 9212
9213 /* Default just returns -ENODEV to indicate unsupported */
9214 dev_priv->display.queue_flip = intel_default_queue_flip;
9215
9216 switch (INTEL_INFO(dev)->gen) {
9217 case 2:
9218 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9219 break;
9220
9221 case 3:
9222 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9223 break;
9224
9225 case 4:
9226 case 5:
9227 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9228 break;
9229
9230 case 6:
9231 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9232 break;
7c9017e5
JB		 9233 case 7:
9234 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9235 break;
8c9f3aaf 9236 }
e70236a8
JB		 9237}
9238
b690e96c
JB		 9239/*
9240 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9241 * resume, or other times. This quirk makes sure that's the case for
9242 * affected systems.
9243 */
0206e353 9244static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9245{
9246 struct drm_i915_private *dev_priv = dev->dev_private;
9247
9248 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9249 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9250}
9251
435793df
KP		 9252/*
9253 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9254 */
9255static void quirk_ssc_force_disable(struct drm_device *dev)
9256{
9257 struct drm_i915_private *dev_priv = dev->dev_private;
9258 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9259 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9260}
9261
4dca20ef 9262/*
5a15ab5b
CE		 9263 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9264 * brightness value
4dca20ef
CE		 9265 */
9266static void quirk_invert_brightness(struct drm_device *dev)
9267{
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9270 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9271}
9272
b690e96c
JB		 9273struct intel_quirk {
9274 int device;
9275 int subsystem_vendor;
9276 int subsystem_device;
9277 void (*hook)(struct drm_device *dev);
9278};
9279
5f85f176
EE		 9280/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9281struct intel_dmi_quirk {
9282 void (*hook)(struct drm_device *dev);
9283 const struct dmi_system_id (*dmi_id_list)[];
9284};
9285
9286static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9287{
9288 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9289 return 1;
9290}
9291
9292static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9293 {
9294 .dmi_id_list = &(const struct dmi_system_id[]) {
9295 {
9296 .callback = intel_dmi_reverse_brightness,
9297 .ident = "NCR Corporation",
9298 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9299 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9300 },
9301 },
9302 { } /* terminating entry */
9303 },
9304 .hook = quirk_invert_brightness,
9305 },
9306};
9307
c43b5634 9308static struct intel_quirk intel_quirks[] = {
b690e96c 9309 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9310 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9311
b690e96c
JB		 9312 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9313 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9314
b690e96c
JB		 9315 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9316 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9317
ccd0d36e 9318 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9319 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9320 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9321
9322 /* Lenovo U160 cannot use SSC on LVDS */
9323 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9324
9325 /* Sony Vaio Y cannot use SSC on LVDS */
9326 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9327
9328 /* Acer Aspire 5734Z must invert backlight brightness */
9329 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9330
9331 /* Acer/eMachines G725 */
9332 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9333
9334 /* Acer/eMachines e725 */
9335 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9336
9337 /* Acer/Packard Bell NCL20 */
9338 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9339
9340 /* Acer Aspire 4736Z */
9341 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9342};
9343
9344static void intel_init_quirks(struct drm_device *dev)
9345{
9346 struct pci_dev *d = dev->pdev;
9347 int i;
9348
9349 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9350 struct intel_quirk *q = &intel_quirks[i];
9351
9352 if (d->device == q->device &&
9353 (d->subsystem_vendor == q->subsystem_vendor ||
9354 q->subsystem_vendor == PCI_ANY_ID) &&
9355 (d->subsystem_device == q->subsystem_device ||
9356 q->subsystem_device == PCI_ANY_ID))
9357 q->hook(dev);
9358 }
5f85f176
EE		 9359 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9360 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9361 intel_dmi_quirks[i].hook(dev);
9362 }
b690e96c
JB		 9363}
9364
9cce37f4
JB		 9365/* Disable the VGA plane that we never use */
9366static void i915_disable_vga(struct drm_device *dev)
9367{
9368 struct drm_i915_private *dev_priv = dev->dev_private;
9369 u8 sr1;
766aa1c4 9370 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9371
9372 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9373 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9374 sr1 = inb(VGA_SR_DATA);
9375 outb(sr1 | 1<<5, VGA_SR_DATA);
9376 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9377 udelay(300);
9378
9379 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9380 POSTING_READ(vga_reg);
9381}
9382
f817586c
DV		 9383void intel_modeset_init_hw(struct drm_device *dev)
9384{
fa42e23c 9385 intel_init_power_well(dev);
0232e927 9386
a8f78b58
ED		 9387 intel_prepare_ddi(dev);
9388
f817586c
DV		 9389 intel_init_clock_gating(dev);
9390
79f5b2c7 9391 mutex_lock(&dev->struct_mutex);
8090c6b9 9392 intel_enable_gt_powersave(dev);
79f5b2c7 9393 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9394}
9395
7d708ee4
ID		 9396void intel_modeset_suspend_hw(struct drm_device *dev)
9397{
9398 intel_suspend_hw(dev);
9399}
9400
79e53945
JB		 9401void intel_modeset_init(struct drm_device *dev)
9402{
652c393a 9403 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9404 int i, j, ret;
79e53945
JB		 9405
9406 drm_mode_config_init(dev);
9407
9408 dev->mode_config.min_width = 0;
9409 dev->mode_config.min_height = 0;
9410
019d96cb
DA		 9411 dev->mode_config.preferred_depth = 24;
9412 dev->mode_config.prefer_shadow = 1;
9413
e6ecefaa 9414 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9415
b690e96c
JB		 9416 intel_init_quirks(dev);
9417
1fa61106
ED		 9418 intel_init_pm(dev);
9419
e3c74757
BW		 9420 if (INTEL_INFO(dev)->num_pipes == 0)
9421 return;
9422
e70236a8
JB		 9423 intel_init_display(dev);
9424
a6c45cf0
CW		 9425 if (IS_GEN2(dev)) {
9426 dev->mode_config.max_width = 2048;
9427 dev->mode_config.max_height = 2048;
9428 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9429 dev->mode_config.max_width = 4096;
9430 dev->mode_config.max_height = 4096;
79e53945 9431 } else {
a6c45cf0
CW		 9432 dev->mode_config.max_width = 8192;
9433 dev->mode_config.max_height = 8192;
79e53945 9434 }
5d4545ae 9435 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9436
28c97730 9437 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9438 INTEL_INFO(dev)->num_pipes,
9439 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9440
7eb552ae 9441 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9442 intel_crtc_init(dev, i);
7f1f3851
JB		 9443 for (j = 0; j < dev_priv->num_plane; j++) {
9444 ret = intel_plane_init(dev, i, j);
9445 if (ret)
06da8da2
VS		 9446 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9447 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9448 }
79e53945
JB		 9449 }
9450
79f689aa 9451 intel_cpu_pll_init(dev);
e72f9fbf 9452 intel_shared_dpll_init(dev);
ee7b9f93 9453
9cce37f4
JB		 9454 /* Just disable it once at startup */
9455 i915_disable_vga(dev);
79e53945 9456 intel_setup_outputs(dev);
11be49eb
CW		 9457
9458 /* Just in case the BIOS is doing something questionable. */
9459 intel_disable_fbc(dev);
2c7111db
CW		 9460}
9461
24929352
DV		 9462static void
9463intel_connector_break_all_links(struct intel_connector *connector)
9464{
9465 connector->base.dpms = DRM_MODE_DPMS_OFF;
9466 connector->base.encoder = NULL;
9467 connector->encoder->connectors_active = false;
9468 connector->encoder->base.crtc = NULL;
9469}
9470
7fad798e
DV		 9471static void intel_enable_pipe_a(struct drm_device *dev)
9472{
9473 struct intel_connector *connector;
9474 struct drm_connector *crt = NULL;
9475 struct intel_load_detect_pipe load_detect_temp;
9476
9477 /* We can't just switch on the pipe A, we need to set things up with a
9478 * proper mode and output configuration. As a gross hack, enable pipe A
9479 * by enabling the load detect pipe once. */
9480 list_for_each_entry(connector,
9481 &dev->mode_config.connector_list,
9482 base.head) {
9483 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9484 crt = &connector->base;
9485 break;
9486 }
9487 }
9488
9489 if (!crt)
9490 return;
9491
9492 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9493 intel_release_load_detect_pipe(crt, &load_detect_temp);
9494
652c393a 9495
7fad798e
DV		 9496}
9497
fa555837
DV		 9498static bool
9499intel_check_plane_mapping(struct intel_crtc *crtc)
9500{
7eb552ae
BW		 9501 struct drm_device *dev = crtc->base.dev;
9502 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9503 u32 reg, val;
9504
7eb552ae 9505 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9506 return true;
9507
9508 reg = DSPCNTR(!crtc->plane);
9509 val = I915_READ(reg);
9510
9511 if ((val & DISPLAY_PLANE_ENABLE) &&
9512 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9513 return false;
9514
9515 return true;
9516}
9517
24929352
DV		 9518static void intel_sanitize_crtc(struct intel_crtc *crtc)
9519{
9520 struct drm_device *dev = crtc->base.dev;
9521 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9522 u32 reg;
24929352 9523
24929352 9524 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9525 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9526 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9527
9528 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9529 * disable the crtc (and hence change the state) if it is wrong. Note
9530 * that gen4+ has a fixed plane -> pipe mapping. */
9531 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9532 struct intel_connector *connector;
9533 bool plane;
9534
24929352
DV		 9535 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9536 crtc->base.base.id);
9537
9538 /* Pipe has the wrong plane attached and the plane is active.
9539 * Temporarily change the plane mapping and disable everything
9540 * ... */
9541 plane = crtc->plane;
9542 crtc->plane = !plane;
9543 dev_priv->display.crtc_disable(&crtc->base);
9544 crtc->plane = plane;
9545
9546 /* ... and break all links. */
9547 list_for_each_entry(connector, &dev->mode_config.connector_list,
9548 base.head) {
9549 if (connector->encoder->base.crtc != &crtc->base)
9550 continue;
9551
9552 intel_connector_break_all_links(connector);
9553 }
9554
9555 WARN_ON(crtc->active);
9556 crtc->base.enabled = false;
9557 }
24929352 9558
7fad798e
DV		 9559 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9560 crtc->pipe == PIPE_A && !crtc->active) {
9561 /* BIOS forgot to enable pipe A, this mostly happens after
9562 * resume. Force-enable the pipe to fix this, the update_dpms
9563 * call below we restore the pipe to the right state, but leave
9564 * the required bits on. */
9565 intel_enable_pipe_a(dev);
9566 }
9567
24929352
DV		 9568 /* Adjust the state of the output pipe according to whether we
9569 * have active connectors/encoders. */
9570 intel_crtc_update_dpms(&crtc->base);
9571
9572 if (crtc->active != crtc->base.enabled) {
9573 struct intel_encoder *encoder;
9574
9575 /* This can happen either due to bugs in the get_hw_state
9576 * functions or because the pipe is force-enabled due to the
9577 * pipe A quirk. */
9578 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9579 crtc->base.base.id,
9580 crtc->base.enabled ? "enabled" : "disabled",
9581 crtc->active ? "enabled" : "disabled");
9582
9583 crtc->base.enabled = crtc->active;
9584
9585 /* Because we only establish the connector -> encoder ->
9586 * crtc links if something is active, this means the
9587 * crtc is now deactivated. Break the links. connector
9588 * -> encoder links are only establish when things are
9589 * actually up, hence no need to break them. */
9590 WARN_ON(crtc->active);
9591
9592 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9593 WARN_ON(encoder->connectors_active);
9594 encoder->base.crtc = NULL;
9595 }
9596 }
9597}
9598
9599static void intel_sanitize_encoder(struct intel_encoder *encoder)
9600{
9601 struct intel_connector *connector;
9602 struct drm_device *dev = encoder->base.dev;
9603
9604 /* We need to check both for a crtc link (meaning that the
9605 * encoder is active and trying to read from a pipe) and the
9606 * pipe itself being active. */
9607 bool has_active_crtc = encoder->base.crtc &&
9608 to_intel_crtc(encoder->base.crtc)->active;
9609
9610 if (encoder->connectors_active && !has_active_crtc) {
9611 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9612 encoder->base.base.id,
9613 drm_get_encoder_name(&encoder->base));
9614
9615 /* Connector is active, but has no active pipe. This is
9616 * fallout from our resume register restoring. Disable
9617 * the encoder manually again. */
9618 if (encoder->base.crtc) {
9619 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9620 encoder->base.base.id,
9621 drm_get_encoder_name(&encoder->base));
9622 encoder->disable(encoder);
9623 }
9624
9625 /* Inconsistent output/port/pipe state happens presumably due to
9626 * a bug in one of the get_hw_state functions. Or someplace else
9627 * in our code, like the register restore mess on resume. Clamp
9628 * things to off as a safer default. */
9629 list_for_each_entry(connector,
9630 &dev->mode_config.connector_list,
9631 base.head) {
9632 if (connector->encoder != encoder)
9633 continue;
9634
9635 intel_connector_break_all_links(connector);
9636 }
9637 }
9638 /* Enabled encoders without active connectors will be fixed in
9639 * the crtc fixup. */
9640}
9641
44cec740 9642void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9643{
9644 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9645 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9646
9647 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9648 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9649 i915_disable_vga(dev);
0fde901f
KM		 9650 }
9651}
9652
24929352
DV		 9653/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9654 * and i915 state tracking structures. */
45e2b5f6
DV		 9655void intel_modeset_setup_hw_state(struct drm_device *dev,
9656 bool force_restore)
24929352
DV		 9657{
9658 struct drm_i915_private *dev_priv = dev->dev_private;
9659 enum pipe pipe;
b5644d05 9660 struct drm_plane *plane;
24929352
DV		 9661 struct intel_crtc *crtc;
9662 struct intel_encoder *encoder;
9663 struct intel_connector *connector;
9664
0e8ffe1b
DV		 9665 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9666 base.head) {
88adfff1 9667 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9668
0e8ffe1b
DV		 9669 crtc->active = dev_priv->display.get_pipe_config(crtc,
9670 &crtc->config);
24929352
DV		 9671
9672 crtc->base.enabled = crtc->active;
9673
9674 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9675 crtc->base.base.id,
9676 crtc->active ? "enabled" : "disabled");
9677 }
9678
affa9354 9679 if (HAS_DDI(dev))
6441ab5f
PZ		 9680 intel_ddi_setup_hw_pll_state(dev);
9681
24929352
DV		 9682 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9683 base.head) {
9684 pipe = 0;
9685
9686 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9687 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9688 encoder->base.crtc = &crtc->base;
9689 if (encoder->get_config)
9690 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9691 } else {
9692 encoder->base.crtc = NULL;
9693 }
9694
9695 encoder->connectors_active = false;
9696 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9697 encoder->base.base.id,
9698 drm_get_encoder_name(&encoder->base),
9699 encoder->base.crtc ? "enabled" : "disabled",
9700 pipe);
9701 }
9702
9703 list_for_each_entry(connector, &dev->mode_config.connector_list,
9704 base.head) {
9705 if (connector->get_hw_state(connector)) {
9706 connector->base.dpms = DRM_MODE_DPMS_ON;
9707 connector->encoder->connectors_active = true;
9708 connector->base.encoder = &connector->encoder->base;
9709 } else {
9710 connector->base.dpms = DRM_MODE_DPMS_OFF;
9711 connector->base.encoder = NULL;
9712 }
9713 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9714 connector->base.base.id,
9715 drm_get_connector_name(&connector->base),
9716 connector->base.encoder ? "enabled" : "disabled");
9717 }
9718
9719 /* HW state is read out, now we need to sanitize this mess. */
9720 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9721 base.head) {
9722 intel_sanitize_encoder(encoder);
9723 }
9724
9725 for_each_pipe(pipe) {
9726 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9727 intel_sanitize_crtc(crtc);
c0b03411 9728 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9729 }
9a935856 9730
45e2b5f6 9731 if (force_restore) {
f30da187
DV		 9732 /*
9733 * We need to use raw interfaces for restoring state to avoid
9734 * checking (bogus) intermediate states.
9735 */
45e2b5f6 9736 for_each_pipe(pipe) {
b5644d05
JB		 9737 struct drm_crtc *crtc =
9738 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9739
9740 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9741 crtc->fb);
45e2b5f6 9742 }
b5644d05
JB		 9743 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9744 intel_plane_restore(plane);
0fde901f
KM		 9745
9746 i915_redisable_vga(dev);
45e2b5f6
DV		 9747 } else {
9748 intel_modeset_update_staged_output_state(dev);
9749 }
8af6cf88
DV		 9750
9751 intel_modeset_check_state(dev);
2e938892
DV		 9752
9753 drm_mode_config_reset(dev);
2c7111db
CW		 9754}
9755
9756void intel_modeset_gem_init(struct drm_device *dev)
9757{
1833b134 9758 intel_modeset_init_hw(dev);
02e792fb
DV		 9759
9760 intel_setup_overlay(dev);
24929352 9761
45e2b5f6 9762 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9763}
9764
9765void intel_modeset_cleanup(struct drm_device *dev)
9766{
652c393a
JB		 9767 struct drm_i915_private *dev_priv = dev->dev_private;
9768 struct drm_crtc *crtc;
9769 struct intel_crtc *intel_crtc;
9770
fd0c0642
DV		 9771 /*
9772 * Interrupts and polling as the first thing to avoid creating havoc.
9773 * Too much stuff here (turning of rps, connectors, ...) would
9774 * experience fancy races otherwise.
9775 */
9776 drm_irq_uninstall(dev);
9777 cancel_work_sync(&dev_priv->hotplug_work);
9778 /*
9779 * Due to the hpd irq storm handling the hotplug work can re-arm the
9780 * poll handlers. Hence disable polling after hpd handling is shut down.
9781 */
f87ea761 9782 drm_kms_helper_poll_fini(dev);
fd0c0642 9783
652c393a
JB		 9784 mutex_lock(&dev->struct_mutex);
9785
723bfd70
JB		 9786 intel_unregister_dsm_handler();
9787
652c393a
JB		 9788 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9789 /* Skip inactive CRTCs */
9790 if (!crtc->fb)
9791 continue;
9792
9793 intel_crtc = to_intel_crtc(crtc);
3dec0095 9794 intel_increase_pllclock(crtc);
652c393a
JB		 9795 }
9796
973d04f9 9797 intel_disable_fbc(dev);
e70236a8 9798
8090c6b9 9799 intel_disable_gt_powersave(dev);
0cdab21f 9800
930ebb46
DV		 9801 ironlake_teardown_rc6(dev);
9802
69341a5e
KH		 9803 mutex_unlock(&dev->struct_mutex);
9804
1630fe75
CW		 9805 /* flush any delayed tasks or pending work */
9806 flush_scheduled_work();
9807
dc652f90
JN		 9808 /* destroy backlight, if any, before the connectors */
9809 intel_panel_destroy_backlight(dev);
9810
79e53945 9811 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9812
9813 intel_cleanup_overlay(dev);
79e53945
JB		 9814}
9815
f1c79df3
ZW		 9816/*
9817 * Return which encoder is currently attached for connector.
9818 */
df0e9248 9819struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9820{
df0e9248
CW		 9821 return &intel_attached_encoder(connector)->base;
9822}
f1c79df3 9823
df0e9248
CW		 9824void intel_connector_attach_encoder(struct intel_connector *connector,
9825 struct intel_encoder *encoder)
9826{
9827 connector->encoder = encoder;
9828 drm_mode_connector_attach_encoder(&connector->base,
9829 &encoder->base);
79e53945 9830}
28d52043
DA		 9831
9832/*
9833 * set vga decode state - true == enable VGA decode
9834 */
9835int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9836{
9837 struct drm_i915_private *dev_priv = dev->dev_private;
9838 u16 gmch_ctrl;
9839
9840 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9841 if (state)
9842 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9843 else
9844 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9845 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9846 return 0;
9847}
c4a1d9e4
CW		 9848
9849#ifdef CONFIG_DEBUG_FS
9850#include <linux/seq_file.h>
9851
9852struct intel_display_error_state {
ff57f1b0
PZ		 9853
9854 u32 power_well_driver;
9855
c4a1d9e4
CW		 9856 struct intel_cursor_error_state {
9857 u32 control;
9858 u32 position;
9859 u32 base;
9860 u32 size;
52331309 9861 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9862
9863 struct intel_pipe_error_state {
ff57f1b0 9864 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9865 u32 conf;
9866 u32 source;
9867
9868 u32 htotal;
9869 u32 hblank;
9870 u32 hsync;
9871 u32 vtotal;
9872 u32 vblank;
9873 u32 vsync;
52331309 9874 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9875
9876 struct intel_plane_error_state {
9877 u32 control;
9878 u32 stride;
9879 u32 size;
9880 u32 pos;
9881 u32 addr;
9882 u32 surface;
9883 u32 tile_offset;
52331309 9884 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9885};
9886
9887struct intel_display_error_state *
9888intel_display_capture_error_state(struct drm_device *dev)
9889{
0206e353 9890 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9891 struct intel_display_error_state *error;
702e7a56 9892 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9893 int i;
9894
9895 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9896 if (error == NULL)
9897 return NULL;
9898
ff57f1b0
PZ		 9899 if (HAS_POWER_WELL(dev))
9900 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9901
52331309 9902 for_each_pipe(i) {
702e7a56 9903 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9904 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9905
a18c4c3d
PZ		 9906 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9907 error->cursor[i].control = I915_READ(CURCNTR(i));
9908 error->cursor[i].position = I915_READ(CURPOS(i));
9909 error->cursor[i].base = I915_READ(CURBASE(i));
9910 } else {
9911 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9912 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9913 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9914 }
c4a1d9e4
CW		 9915
9916 error->plane[i].control = I915_READ(DSPCNTR(i));
9917 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9918 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9919 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9920 error->plane[i].pos = I915_READ(DSPPOS(i));
9921 }
ca291363
PZ		 9922 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9923 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9924 if (INTEL_INFO(dev)->gen >= 4) {
9925 error->plane[i].surface = I915_READ(DSPSURF(i));
9926 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9927 }
9928
702e7a56 9929 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9930 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9931 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9932 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9933 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9934 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9935 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9936 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9937 }
9938
12d217c7
PZ		 9939 /* In the code above we read the registers without checking if the power
9940 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9941 * prevent the next I915_WRITE from detecting it and printing an error
9942 * message. */
9943 if (HAS_POWER_WELL(dev))
9944 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9945
c4a1d9e4
CW		 9946 return error;
9947}
9948
edc3d884
MK		 9949#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9950
c4a1d9e4 9951void
edc3d884 9952intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9953 struct drm_device *dev,
9954 struct intel_display_error_state *error)
9955{
9956 int i;
9957
edc3d884 9958 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9959 if (HAS_POWER_WELL(dev))
edc3d884 9960 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9961 error->power_well_driver);
52331309 9962 for_each_pipe(i) {
edc3d884
MK		 9963 err_printf(m, "Pipe [%d]:\n", i);
9964 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9965 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9966 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9967 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9968 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9969 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9970 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9971 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9972 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9973 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9974
9975 err_printf(m, "Plane [%d]:\n", i);
9976 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9977 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9978 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9979 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9980 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9981 }
4b71a570 9982 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9983 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9984 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9985 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9986 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9987 }
9988
edc3d884
MK		 9989 err_printf(m, "Cursor [%d]:\n", i);
9990 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9991 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9992 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9993 }
9994}
9995#endif
Linux kernel - Deliverables
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