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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
c196e1d6 | 40 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
41 | #include <drm/drm_dp_helper.h> |
42 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
43 | #include <drm/drm_plane_helper.h> |
44 | #include <drm/drm_rect.h> | |
c0f372b3 | 45 | #include <linux/dma_remapping.h> |
79e53945 | 46 | |
465c120c MR |
47 | /* Primary plane formats supported by all gen */ |
48 | #define COMMON_PRIMARY_FORMATS \ | |
49 | DRM_FORMAT_C8, \ | |
50 | DRM_FORMAT_RGB565, \ | |
51 | DRM_FORMAT_XRGB8888, \ | |
52 | DRM_FORMAT_ARGB8888 | |
53 | ||
54 | /* Primary plane formats for gen <= 3 */ | |
55 | static const uint32_t intel_primary_formats_gen2[] = { | |
56 | COMMON_PRIMARY_FORMATS, | |
57 | DRM_FORMAT_XRGB1555, | |
58 | DRM_FORMAT_ARGB1555, | |
59 | }; | |
60 | ||
61 | /* Primary plane formats for gen >= 4 */ | |
62 | static const uint32_t intel_primary_formats_gen4[] = { | |
63 | COMMON_PRIMARY_FORMATS, \ | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_ABGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_ARGB2101010, | |
68 | DRM_FORMAT_XBGR2101010, | |
69 | DRM_FORMAT_ABGR2101010, | |
70 | }; | |
71 | ||
3d7d6510 MR |
72 | /* Cursor formats */ |
73 | static const uint32_t intel_cursor_formats[] = { | |
74 | DRM_FORMAT_ARGB8888, | |
75 | }; | |
76 | ||
6b383a7f | 77 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 78 | |
f1f644dc | 79 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 80 | struct intel_crtc_state *pipe_config); |
18442d08 | 81 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 82 | struct intel_crtc_state *pipe_config); |
f1f644dc | 83 | |
e7457a9a DL |
84 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
85 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
86 | static int intel_framebuffer_init(struct drm_device *dev, |
87 | struct intel_framebuffer *ifb, | |
88 | struct drm_mode_fb_cmd2 *mode_cmd, | |
89 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
90 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
91 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 92 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
93 | struct intel_link_m_n *m_n, |
94 | struct intel_link_m_n *m2_n2); | |
29407aab | 95 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
96 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
97 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 98 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 99 | const struct intel_crtc_state *pipe_config); |
d288f65f | 100 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
102 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
103 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 104 | |
0e32b39c DA |
105 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
106 | { | |
107 | if (!connector->mst_port) | |
108 | return connector->encoder; | |
109 | else | |
110 | return &connector->mst_port->mst_encoders[pipe]->base; | |
111 | } | |
112 | ||
79e53945 | 113 | typedef struct { |
0206e353 | 114 | int min, max; |
79e53945 JB |
115 | } intel_range_t; |
116 | ||
117 | typedef struct { | |
0206e353 AJ |
118 | int dot_limit; |
119 | int p2_slow, p2_fast; | |
79e53945 JB |
120 | } intel_p2_t; |
121 | ||
d4906093 ML |
122 | typedef struct intel_limit intel_limit_t; |
123 | struct intel_limit { | |
0206e353 AJ |
124 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
125 | intel_p2_t p2; | |
d4906093 | 126 | }; |
79e53945 | 127 | |
d2acd215 DV |
128 | int |
129 | intel_pch_rawclk(struct drm_device *dev) | |
130 | { | |
131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132 | ||
133 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
134 | ||
135 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
136 | } | |
137 | ||
021357ac CW |
138 | static inline u32 /* units of 100MHz */ |
139 | intel_fdi_link_freq(struct drm_device *dev) | |
140 | { | |
8b99e68c CW |
141 | if (IS_GEN5(dev)) { |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
144 | } else | |
145 | return 27; | |
021357ac CW |
146 | } |
147 | ||
5d536e28 | 148 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 149 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 150 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 151 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
152 | .m = { .min = 96, .max = 140 }, |
153 | .m1 = { .min = 18, .max = 26 }, | |
154 | .m2 = { .min = 6, .max = 16 }, | |
155 | .p = { .min = 4, .max = 128 }, | |
156 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
157 | .p2 = { .dot_limit = 165000, |
158 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
159 | }; |
160 | ||
5d536e28 DV |
161 | static const intel_limit_t intel_limits_i8xx_dvo = { |
162 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 163 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 164 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
165 | .m = { .min = 96, .max = 140 }, |
166 | .m1 = { .min = 18, .max = 26 }, | |
167 | .m2 = { .min = 6, .max = 16 }, | |
168 | .p = { .min = 4, .max = 128 }, | |
169 | .p1 = { .min = 2, .max = 33 }, | |
170 | .p2 = { .dot_limit = 165000, | |
171 | .p2_slow = 4, .p2_fast = 4 }, | |
172 | }; | |
173 | ||
e4b36699 | 174 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 175 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 176 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 177 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
178 | .m = { .min = 96, .max = 140 }, |
179 | .m1 = { .min = 18, .max = 26 }, | |
180 | .m2 = { .min = 6, .max = 16 }, | |
181 | .p = { .min = 4, .max = 128 }, | |
182 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
183 | .p2 = { .dot_limit = 165000, |
184 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 185 | }; |
273e27ca | 186 | |
e4b36699 | 187 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
188 | .dot = { .min = 20000, .max = 400000 }, |
189 | .vco = { .min = 1400000, .max = 2800000 }, | |
190 | .n = { .min = 1, .max = 6 }, | |
191 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
192 | .m1 = { .min = 8, .max = 18 }, |
193 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
194 | .p = { .min = 5, .max = 80 }, |
195 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
196 | .p2 = { .dot_limit = 200000, |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
201 | .dot = { .min = 20000, .max = 400000 }, |
202 | .vco = { .min = 1400000, .max = 2800000 }, | |
203 | .n = { .min = 1, .max = 6 }, | |
204 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
205 | .m1 = { .min = 8, .max = 18 }, |
206 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
207 | .p = { .min = 7, .max = 98 }, |
208 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
209 | .p2 = { .dot_limit = 112000, |
210 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
211 | }; |
212 | ||
273e27ca | 213 | |
e4b36699 | 214 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
215 | .dot = { .min = 25000, .max = 270000 }, |
216 | .vco = { .min = 1750000, .max = 3500000}, | |
217 | .n = { .min = 1, .max = 4 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 10, .max = 30 }, | |
222 | .p1 = { .min = 1, .max = 3}, | |
223 | .p2 = { .dot_limit = 270000, | |
224 | .p2_slow = 10, | |
225 | .p2_fast = 10 | |
044c7c41 | 226 | }, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
230 | .dot = { .min = 22000, .max = 400000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 4 }, | |
233 | .m = { .min = 104, .max = 138 }, | |
234 | .m1 = { .min = 16, .max = 23 }, | |
235 | .m2 = { .min = 5, .max = 11 }, | |
236 | .p = { .min = 5, .max = 80 }, | |
237 | .p1 = { .min = 1, .max = 8}, | |
238 | .p2 = { .dot_limit = 165000, | |
239 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
240 | }; |
241 | ||
242 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
243 | .dot = { .min = 20000, .max = 115000 }, |
244 | .vco = { .min = 1750000, .max = 3500000 }, | |
245 | .n = { .min = 1, .max = 3 }, | |
246 | .m = { .min = 104, .max = 138 }, | |
247 | .m1 = { .min = 17, .max = 23 }, | |
248 | .m2 = { .min = 5, .max = 11 }, | |
249 | .p = { .min = 28, .max = 112 }, | |
250 | .p1 = { .min = 2, .max = 8 }, | |
251 | .p2 = { .dot_limit = 0, | |
252 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 253 | }, |
e4b36699 KP |
254 | }; |
255 | ||
256 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
257 | .dot = { .min = 80000, .max = 224000 }, |
258 | .vco = { .min = 1750000, .max = 3500000 }, | |
259 | .n = { .min = 1, .max = 3 }, | |
260 | .m = { .min = 104, .max = 138 }, | |
261 | .m1 = { .min = 17, .max = 23 }, | |
262 | .m2 = { .min = 5, .max = 11 }, | |
263 | .p = { .min = 14, .max = 42 }, | |
264 | .p1 = { .min = 2, .max = 6 }, | |
265 | .p2 = { .dot_limit = 0, | |
266 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 267 | }, |
e4b36699 KP |
268 | }; |
269 | ||
f2b115e6 | 270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
271 | .dot = { .min = 20000, .max = 400000}, |
272 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 273 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
274 | .n = { .min = 3, .max = 6 }, |
275 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
277 | .m1 = { .min = 0, .max = 0 }, |
278 | .m2 = { .min = 0, .max = 254 }, | |
279 | .p = { .min = 5, .max = 80 }, | |
280 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
281 | .p2 = { .dot_limit = 200000, |
282 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
283 | }; |
284 | ||
f2b115e6 | 285 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
286 | .dot = { .min = 20000, .max = 400000 }, |
287 | .vco = { .min = 1700000, .max = 3500000 }, | |
288 | .n = { .min = 3, .max = 6 }, | |
289 | .m = { .min = 2, .max = 256 }, | |
290 | .m1 = { .min = 0, .max = 0 }, | |
291 | .m2 = { .min = 0, .max = 254 }, | |
292 | .p = { .min = 7, .max = 112 }, | |
293 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
294 | .p2 = { .dot_limit = 112000, |
295 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
296 | }; |
297 | ||
273e27ca EA |
298 | /* Ironlake / Sandybridge |
299 | * | |
300 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
301 | * the range value for them is (actual_value - 2). | |
302 | */ | |
b91ad0ec | 303 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 350000 }, |
305 | .vco = { .min = 1760000, .max = 3510000 }, | |
306 | .n = { .min = 1, .max = 5 }, | |
307 | .m = { .min = 79, .max = 127 }, | |
308 | .m1 = { .min = 12, .max = 22 }, | |
309 | .m2 = { .min = 5, .max = 9 }, | |
310 | .p = { .min = 5, .max = 80 }, | |
311 | .p1 = { .min = 1, .max = 8 }, | |
312 | .p2 = { .dot_limit = 225000, | |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
b91ad0ec | 316 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
317 | .dot = { .min = 25000, .max = 350000 }, |
318 | .vco = { .min = 1760000, .max = 3510000 }, | |
319 | .n = { .min = 1, .max = 3 }, | |
320 | .m = { .min = 79, .max = 118 }, | |
321 | .m1 = { .min = 12, .max = 22 }, | |
322 | .m2 = { .min = 5, .max = 9 }, | |
323 | .p = { .min = 28, .max = 112 }, | |
324 | .p1 = { .min = 2, .max = 8 }, | |
325 | .p2 = { .dot_limit = 225000, | |
326 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 350000 }, |
331 | .vco = { .min = 1760000, .max = 3510000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 79, .max = 127 }, | |
334 | .m1 = { .min = 12, .max = 22 }, | |
335 | .m2 = { .min = 5, .max = 9 }, | |
336 | .p = { .min = 14, .max = 56 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 225000, | |
339 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
340 | }; |
341 | ||
273e27ca | 342 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 2 }, | |
347 | .m = { .min = 79, .max = 126 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 351 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
352 | .p2 = { .dot_limit = 225000, |
353 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
354 | }; |
355 | ||
356 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 126 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 364 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
365 | .p2 = { .dot_limit = 225000, |
366 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
367 | }; |
368 | ||
dc730512 | 369 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
370 | /* |
371 | * These are the data rate limits (measured in fast clocks) | |
372 | * since those are the strictest limits we have. The fast | |
373 | * clock and actual rate limits are more relaxed, so checking | |
374 | * them would make no difference. | |
375 | */ | |
376 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 377 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 378 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
379 | .m1 = { .min = 2, .max = 3 }, |
380 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 381 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 382 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
383 | }; |
384 | ||
ef9348c8 CML |
385 | static const intel_limit_t intel_limits_chv = { |
386 | /* | |
387 | * These are the data rate limits (measured in fast clocks) | |
388 | * since those are the strictest limits we have. The fast | |
389 | * clock and actual rate limits are more relaxed, so checking | |
390 | * them would make no difference. | |
391 | */ | |
392 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
9505e01a | 393 | .vco = { .min = 4860000, .max = 6480000 }, |
ef9348c8 CML |
394 | .n = { .min = 1, .max = 1 }, |
395 | .m1 = { .min = 2, .max = 2 }, | |
396 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
397 | .p1 = { .min = 2, .max = 4 }, | |
398 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
399 | }; | |
400 | ||
6b4bf1c4 VS |
401 | static void vlv_clock(int refclk, intel_clock_t *clock) |
402 | { | |
403 | clock->m = clock->m1 * clock->m2; | |
404 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
405 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
406 | return; | |
fb03ac01 VS |
407 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
408 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
409 | } |
410 | ||
e0638cdf PZ |
411 | /** |
412 | * Returns whether any output on the specified pipe is of the specified type | |
413 | */ | |
4093561b | 414 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 415 | { |
409ee761 | 416 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
417 | struct intel_encoder *encoder; |
418 | ||
409ee761 | 419 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
420 | if (encoder->type == type) |
421 | return true; | |
422 | ||
423 | return false; | |
424 | } | |
425 | ||
d0737e1d ACO |
426 | /** |
427 | * Returns whether any output on the specified pipe will have the specified | |
428 | * type after a staged modeset is complete, i.e., the same as | |
429 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
430 | * encoder->crtc. | |
431 | */ | |
432 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
433 | { | |
434 | struct drm_device *dev = crtc->base.dev; | |
435 | struct intel_encoder *encoder; | |
436 | ||
437 | for_each_intel_encoder(dev, encoder) | |
438 | if (encoder->new_crtc == crtc && encoder->type == type) | |
439 | return true; | |
440 | ||
441 | return false; | |
442 | } | |
443 | ||
409ee761 | 444 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 445 | int refclk) |
2c07245f | 446 | { |
409ee761 | 447 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 448 | const intel_limit_t *limit; |
b91ad0ec | 449 | |
d0737e1d | 450 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 451 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 452 | if (refclk == 100000) |
b91ad0ec ZW |
453 | limit = &intel_limits_ironlake_dual_lvds_100m; |
454 | else | |
455 | limit = &intel_limits_ironlake_dual_lvds; | |
456 | } else { | |
1b894b59 | 457 | if (refclk == 100000) |
b91ad0ec ZW |
458 | limit = &intel_limits_ironlake_single_lvds_100m; |
459 | else | |
460 | limit = &intel_limits_ironlake_single_lvds; | |
461 | } | |
c6bb3538 | 462 | } else |
b91ad0ec | 463 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
464 | |
465 | return limit; | |
466 | } | |
467 | ||
409ee761 | 468 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 469 | { |
409ee761 | 470 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
471 | const intel_limit_t *limit; |
472 | ||
d0737e1d | 473 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 474 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 475 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 476 | else |
e4b36699 | 477 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
478 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
479 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 480 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 481 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 482 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 483 | } else /* The option is for other outputs */ |
e4b36699 | 484 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
485 | |
486 | return limit; | |
487 | } | |
488 | ||
409ee761 | 489 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 490 | { |
409ee761 | 491 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
492 | const intel_limit_t *limit; |
493 | ||
bad720ff | 494 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 495 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 496 | else if (IS_G4X(dev)) { |
044c7c41 | 497 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 498 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 499 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 500 | limit = &intel_limits_pineview_lvds; |
2177832f | 501 | else |
f2b115e6 | 502 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
503 | } else if (IS_CHERRYVIEW(dev)) { |
504 | limit = &intel_limits_chv; | |
a0c4da24 | 505 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 506 | limit = &intel_limits_vlv; |
a6c45cf0 | 507 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 508 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
509 | limit = &intel_limits_i9xx_lvds; |
510 | else | |
511 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 512 | } else { |
d0737e1d | 513 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 514 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 515 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 516 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
517 | else |
518 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
519 | } |
520 | return limit; | |
521 | } | |
522 | ||
f2b115e6 AJ |
523 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
524 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 525 | { |
2177832f SL |
526 | clock->m = clock->m2 + 2; |
527 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
529 | return; | |
fb03ac01 VS |
530 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
531 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
532 | } |
533 | ||
7429e9d4 DV |
534 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
535 | { | |
536 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
537 | } | |
538 | ||
ac58c3f0 | 539 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 540 | { |
7429e9d4 | 541 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 542 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
543 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
544 | return; | |
fb03ac01 VS |
545 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
546 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
547 | } |
548 | ||
ef9348c8 CML |
549 | static void chv_clock(int refclk, intel_clock_t *clock) |
550 | { | |
551 | clock->m = clock->m1 * clock->m2; | |
552 | clock->p = clock->p1 * clock->p2; | |
553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
554 | return; | |
555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
556 | clock->n << 22); | |
557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
558 | } | |
559 | ||
7c04d1d9 | 560 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
561 | /** |
562 | * Returns whether the given set of divisors are valid for a given refclk with | |
563 | * the given connectors. | |
564 | */ | |
565 | ||
1b894b59 CW |
566 | static bool intel_PLL_is_valid(struct drm_device *dev, |
567 | const intel_limit_t *limit, | |
568 | const intel_clock_t *clock) | |
79e53945 | 569 | { |
f01b7962 VS |
570 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
571 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 572 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 573 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 574 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 575 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 576 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 577 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
578 | |
579 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
580 | if (clock->m1 <= clock->m2) | |
581 | INTELPllInvalid("m1 <= m2\n"); | |
582 | ||
583 | if (!IS_VALLEYVIEW(dev)) { | |
584 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
585 | INTELPllInvalid("p out of range\n"); | |
586 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
587 | INTELPllInvalid("m out of range\n"); | |
588 | } | |
589 | ||
79e53945 | 590 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 591 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
592 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
593 | * connector, etc., rather than just a single range. | |
594 | */ | |
595 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 596 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
597 | |
598 | return true; | |
599 | } | |
600 | ||
d4906093 | 601 | static bool |
a919ff14 | 602 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
603 | int target, int refclk, intel_clock_t *match_clock, |
604 | intel_clock_t *best_clock) | |
79e53945 | 605 | { |
a919ff14 | 606 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 607 | intel_clock_t clock; |
79e53945 JB |
608 | int err = target; |
609 | ||
d0737e1d | 610 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 611 | /* |
a210b028 DV |
612 | * For LVDS just rely on its current settings for dual-channel. |
613 | * We haven't figured out how to reliably set up different | |
614 | * single/dual channel state, if we even can. | |
79e53945 | 615 | */ |
1974cad0 | 616 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
617 | clock.p2 = limit->p2.p2_fast; |
618 | else | |
619 | clock.p2 = limit->p2.p2_slow; | |
620 | } else { | |
621 | if (target < limit->p2.dot_limit) | |
622 | clock.p2 = limit->p2.p2_slow; | |
623 | else | |
624 | clock.p2 = limit->p2.p2_fast; | |
625 | } | |
626 | ||
0206e353 | 627 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 628 | |
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
ac58c3f0 DV |
641 | i9xx_clock(refclk, &clock); |
642 | if (!intel_PLL_is_valid(dev, limit, | |
643 | &clock)) | |
644 | continue; | |
645 | if (match_clock && | |
646 | clock.p != match_clock->p) | |
647 | continue; | |
648 | ||
649 | this_err = abs(clock.dot - target); | |
650 | if (this_err < err) { | |
651 | *best_clock = clock; | |
652 | err = this_err; | |
653 | } | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | ||
659 | return (err != target); | |
660 | } | |
661 | ||
662 | static bool | |
a919ff14 | 663 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
664 | int target, int refclk, intel_clock_t *match_clock, |
665 | intel_clock_t *best_clock) | |
79e53945 | 666 | { |
a919ff14 | 667 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 668 | intel_clock_t clock; |
79e53945 JB |
669 | int err = target; |
670 | ||
d0737e1d | 671 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 672 | /* |
a210b028 DV |
673 | * For LVDS just rely on its current settings for dual-channel. |
674 | * We haven't figured out how to reliably set up different | |
675 | * single/dual channel state, if we even can. | |
79e53945 | 676 | */ |
1974cad0 | 677 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
678 | clock.p2 = limit->p2.p2_fast; |
679 | else | |
680 | clock.p2 = limit->p2.p2_slow; | |
681 | } else { | |
682 | if (target < limit->p2.dot_limit) | |
683 | clock.p2 = limit->p2.p2_slow; | |
684 | else | |
685 | clock.p2 = limit->p2.p2_fast; | |
686 | } | |
687 | ||
0206e353 | 688 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 689 | |
42158660 ZY |
690 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
691 | clock.m1++) { | |
692 | for (clock.m2 = limit->m2.min; | |
693 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
694 | for (clock.n = limit->n.min; |
695 | clock.n <= limit->n.max; clock.n++) { | |
696 | for (clock.p1 = limit->p1.min; | |
697 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
698 | int this_err; |
699 | ||
ac58c3f0 | 700 | pineview_clock(refclk, &clock); |
1b894b59 CW |
701 | if (!intel_PLL_is_valid(dev, limit, |
702 | &clock)) | |
79e53945 | 703 | continue; |
cec2f356 SP |
704 | if (match_clock && |
705 | clock.p != match_clock->p) | |
706 | continue; | |
79e53945 JB |
707 | |
708 | this_err = abs(clock.dot - target); | |
709 | if (this_err < err) { | |
710 | *best_clock = clock; | |
711 | err = this_err; | |
712 | } | |
713 | } | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | return (err != target); | |
719 | } | |
720 | ||
d4906093 | 721 | static bool |
a919ff14 | 722 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
723 | int target, int refclk, intel_clock_t *match_clock, |
724 | intel_clock_t *best_clock) | |
d4906093 | 725 | { |
a919ff14 | 726 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
727 | intel_clock_t clock; |
728 | int max_n; | |
729 | bool found; | |
6ba770dc AJ |
730 | /* approximately equals target * 0.00585 */ |
731 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
732 | found = false; |
733 | ||
d0737e1d | 734 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 735 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
736 | clock.p2 = limit->p2.p2_fast; |
737 | else | |
738 | clock.p2 = limit->p2.p2_slow; | |
739 | } else { | |
740 | if (target < limit->p2.dot_limit) | |
741 | clock.p2 = limit->p2.p2_slow; | |
742 | else | |
743 | clock.p2 = limit->p2.p2_fast; | |
744 | } | |
745 | ||
746 | memset(best_clock, 0, sizeof(*best_clock)); | |
747 | max_n = limit->n.max; | |
f77f13e2 | 748 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 749 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 750 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
751 | for (clock.m1 = limit->m1.max; |
752 | clock.m1 >= limit->m1.min; clock.m1--) { | |
753 | for (clock.m2 = limit->m2.max; | |
754 | clock.m2 >= limit->m2.min; clock.m2--) { | |
755 | for (clock.p1 = limit->p1.max; | |
756 | clock.p1 >= limit->p1.min; clock.p1--) { | |
757 | int this_err; | |
758 | ||
ac58c3f0 | 759 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
760 | if (!intel_PLL_is_valid(dev, limit, |
761 | &clock)) | |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
a0c4da24 | 778 | static bool |
a919ff14 | 779 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
780 | int target, int refclk, intel_clock_t *match_clock, |
781 | intel_clock_t *best_clock) | |
a0c4da24 | 782 | { |
a919ff14 | 783 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 784 | intel_clock_t clock; |
69e4f900 | 785 | unsigned int bestppm = 1000000; |
27e639bf VS |
786 | /* min update 19.2 MHz */ |
787 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 788 | bool found = false; |
a0c4da24 | 789 | |
6b4bf1c4 VS |
790 | target *= 5; /* fast clock */ |
791 | ||
792 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
793 | |
794 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 795 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 796 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 797 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 798 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 799 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 800 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 801 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
802 | unsigned int ppm, diff; |
803 | ||
6b4bf1c4 VS |
804 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
805 | refclk * clock.m1); | |
806 | ||
807 | vlv_clock(refclk, &clock); | |
43b0ac53 | 808 | |
f01b7962 VS |
809 | if (!intel_PLL_is_valid(dev, limit, |
810 | &clock)) | |
43b0ac53 VS |
811 | continue; |
812 | ||
6b4bf1c4 VS |
813 | diff = abs(clock.dot - target); |
814 | ppm = div_u64(1000000ULL * diff, target); | |
815 | ||
816 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 817 | bestppm = 0; |
6b4bf1c4 | 818 | *best_clock = clock; |
49e497ef | 819 | found = true; |
43b0ac53 | 820 | } |
6b4bf1c4 | 821 | |
c686122c | 822 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 823 | bestppm = ppm; |
6b4bf1c4 | 824 | *best_clock = clock; |
49e497ef | 825 | found = true; |
a0c4da24 JB |
826 | } |
827 | } | |
828 | } | |
829 | } | |
830 | } | |
a0c4da24 | 831 | |
49e497ef | 832 | return found; |
a0c4da24 | 833 | } |
a4fc5ed6 | 834 | |
ef9348c8 | 835 | static bool |
a919ff14 | 836 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
837 | int target, int refclk, intel_clock_t *match_clock, |
838 | intel_clock_t *best_clock) | |
839 | { | |
a919ff14 | 840 | struct drm_device *dev = crtc->base.dev; |
ef9348c8 CML |
841 | intel_clock_t clock; |
842 | uint64_t m2; | |
843 | int found = false; | |
844 | ||
845 | memset(best_clock, 0, sizeof(*best_clock)); | |
846 | ||
847 | /* | |
848 | * Based on hardware doc, the n always set to 1, and m1 always | |
849 | * set to 2. If requires to support 200Mhz refclk, we need to | |
850 | * revisit this because n may not 1 anymore. | |
851 | */ | |
852 | clock.n = 1, clock.m1 = 2; | |
853 | target *= 5; /* fast clock */ | |
854 | ||
855 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
856 | for (clock.p2 = limit->p2.p2_fast; | |
857 | clock.p2 >= limit->p2.p2_slow; | |
858 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
859 | ||
860 | clock.p = clock.p1 * clock.p2; | |
861 | ||
862 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
863 | clock.n) << 22, refclk * clock.m1); | |
864 | ||
865 | if (m2 > INT_MAX/clock.m1) | |
866 | continue; | |
867 | ||
868 | clock.m2 = m2; | |
869 | ||
870 | chv_clock(refclk, &clock); | |
871 | ||
872 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
873 | continue; | |
874 | ||
875 | /* based on hardware requirement, prefer bigger p | |
876 | */ | |
877 | if (clock.p > best_clock->p) { | |
878 | *best_clock = clock; | |
879 | found = true; | |
880 | } | |
881 | } | |
882 | } | |
883 | ||
884 | return found; | |
885 | } | |
886 | ||
20ddf665 VS |
887 | bool intel_crtc_active(struct drm_crtc *crtc) |
888 | { | |
889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890 | ||
891 | /* Be paranoid as we can arrive here with only partial | |
892 | * state retrieved from the hardware during setup. | |
893 | * | |
241bfc38 | 894 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
895 | * as Haswell has gained clock readout/fastboot support. |
896 | * | |
66e514c1 | 897 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
898 | * properly reconstruct framebuffers. |
899 | */ | |
f4510a27 | 900 | return intel_crtc->active && crtc->primary->fb && |
6e3c9717 | 901 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
902 | } |
903 | ||
a5c961d1 PZ |
904 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
905 | enum pipe pipe) | |
906 | { | |
907 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
909 | ||
6e3c9717 | 910 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
911 | } |
912 | ||
fbf49ea2 VS |
913 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
914 | { | |
915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
916 | u32 reg = PIPEDSL(pipe); | |
917 | u32 line1, line2; | |
918 | u32 line_mask; | |
919 | ||
920 | if (IS_GEN2(dev)) | |
921 | line_mask = DSL_LINEMASK_GEN2; | |
922 | else | |
923 | line_mask = DSL_LINEMASK_GEN3; | |
924 | ||
925 | line1 = I915_READ(reg) & line_mask; | |
926 | mdelay(5); | |
927 | line2 = I915_READ(reg) & line_mask; | |
928 | ||
929 | return line1 == line2; | |
930 | } | |
931 | ||
ab7ad7f6 KP |
932 | /* |
933 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 934 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
935 | * |
936 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
937 | * spinning on the vblank interrupt status bit, since we won't actually | |
938 | * see an interrupt when the pipe is disabled. | |
939 | * | |
ab7ad7f6 KP |
940 | * On Gen4 and above: |
941 | * wait for the pipe register state bit to turn off | |
942 | * | |
943 | * Otherwise: | |
944 | * wait for the display line value to settle (it usually | |
945 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 946 | * |
9d0498a2 | 947 | */ |
575f7ab7 | 948 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 949 | { |
575f7ab7 | 950 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 951 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 952 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 953 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
954 | |
955 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 956 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
957 | |
958 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
959 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
960 | 100)) | |
284637d9 | 961 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 962 | } else { |
ab7ad7f6 | 963 | /* Wait for the display line to settle */ |
fbf49ea2 | 964 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 965 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 966 | } |
79e53945 JB |
967 | } |
968 | ||
b0ea7d37 DL |
969 | /* |
970 | * ibx_digital_port_connected - is the specified port connected? | |
971 | * @dev_priv: i915 private structure | |
972 | * @port: the port to test | |
973 | * | |
974 | * Returns true if @port is connected, false otherwise. | |
975 | */ | |
976 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
977 | struct intel_digital_port *port) | |
978 | { | |
979 | u32 bit; | |
980 | ||
c36346e3 | 981 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 982 | switch (port->port) { |
c36346e3 DL |
983 | case PORT_B: |
984 | bit = SDE_PORTB_HOTPLUG; | |
985 | break; | |
986 | case PORT_C: | |
987 | bit = SDE_PORTC_HOTPLUG; | |
988 | break; | |
989 | case PORT_D: | |
990 | bit = SDE_PORTD_HOTPLUG; | |
991 | break; | |
992 | default: | |
993 | return true; | |
994 | } | |
995 | } else { | |
eba905b2 | 996 | switch (port->port) { |
c36346e3 DL |
997 | case PORT_B: |
998 | bit = SDE_PORTB_HOTPLUG_CPT; | |
999 | break; | |
1000 | case PORT_C: | |
1001 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1002 | break; | |
1003 | case PORT_D: | |
1004 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1005 | break; | |
1006 | default: | |
1007 | return true; | |
1008 | } | |
b0ea7d37 DL |
1009 | } |
1010 | ||
1011 | return I915_READ(SDEISR) & bit; | |
1012 | } | |
1013 | ||
b24e7179 JB |
1014 | static const char *state_string(bool enabled) |
1015 | { | |
1016 | return enabled ? "on" : "off"; | |
1017 | } | |
1018 | ||
1019 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1020 | void assert_pll(struct drm_i915_private *dev_priv, |
1021 | enum pipe pipe, bool state) | |
b24e7179 JB |
1022 | { |
1023 | int reg; | |
1024 | u32 val; | |
1025 | bool cur_state; | |
1026 | ||
1027 | reg = DPLL(pipe); | |
1028 | val = I915_READ(reg); | |
1029 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1030 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1031 | "PLL state assertion failure (expected %s, current %s)\n", |
1032 | state_string(state), state_string(cur_state)); | |
1033 | } | |
b24e7179 | 1034 | |
23538ef1 JN |
1035 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1036 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1037 | { | |
1038 | u32 val; | |
1039 | bool cur_state; | |
1040 | ||
1041 | mutex_lock(&dev_priv->dpio_lock); | |
1042 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1043 | mutex_unlock(&dev_priv->dpio_lock); | |
1044 | ||
1045 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1046 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1047 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1048 | state_string(state), state_string(cur_state)); | |
1049 | } | |
1050 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1051 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1052 | ||
55607e8a | 1053 | struct intel_shared_dpll * |
e2b78267 DV |
1054 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1055 | { | |
1056 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1057 | ||
6e3c9717 | 1058 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1059 | return NULL; |
1060 | ||
6e3c9717 | 1061 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1062 | } |
1063 | ||
040484af | 1064 | /* For ILK+ */ |
55607e8a DV |
1065 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1066 | struct intel_shared_dpll *pll, | |
1067 | bool state) | |
040484af | 1068 | { |
040484af | 1069 | bool cur_state; |
5358901f | 1070 | struct intel_dpll_hw_state hw_state; |
040484af | 1071 | |
92b27b08 | 1072 | if (WARN (!pll, |
46edb027 | 1073 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1074 | return; |
ee7b9f93 | 1075 | |
5358901f | 1076 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1077 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1078 | "%s assertion failure (expected %s, current %s)\n", |
1079 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1080 | } |
040484af JB |
1081 | |
1082 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1083 | enum pipe pipe, bool state) | |
1084 | { | |
1085 | int reg; | |
1086 | u32 val; | |
1087 | bool cur_state; | |
ad80a810 PZ |
1088 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1089 | pipe); | |
040484af | 1090 | |
affa9354 PZ |
1091 | if (HAS_DDI(dev_priv->dev)) { |
1092 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1093 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1094 | val = I915_READ(reg); |
ad80a810 | 1095 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1096 | } else { |
1097 | reg = FDI_TX_CTL(pipe); | |
1098 | val = I915_READ(reg); | |
1099 | cur_state = !!(val & FDI_TX_ENABLE); | |
1100 | } | |
e2c719b7 | 1101 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1102 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1103 | state_string(state), state_string(cur_state)); | |
1104 | } | |
1105 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1106 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1107 | ||
1108 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1109 | enum pipe pipe, bool state) | |
1110 | { | |
1111 | int reg; | |
1112 | u32 val; | |
1113 | bool cur_state; | |
1114 | ||
d63fa0dc PZ |
1115 | reg = FDI_RX_CTL(pipe); |
1116 | val = I915_READ(reg); | |
1117 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1119 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1120 | state_string(state), state_string(cur_state)); | |
1121 | } | |
1122 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1123 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1124 | ||
1125 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1126 | enum pipe pipe) | |
1127 | { | |
1128 | int reg; | |
1129 | u32 val; | |
1130 | ||
1131 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1132 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1133 | return; |
1134 | ||
bf507ef7 | 1135 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1136 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1137 | return; |
1138 | ||
040484af JB |
1139 | reg = FDI_TX_CTL(pipe); |
1140 | val = I915_READ(reg); | |
e2c719b7 | 1141 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1142 | } |
1143 | ||
55607e8a DV |
1144 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1145 | enum pipe pipe, bool state) | |
040484af JB |
1146 | { |
1147 | int reg; | |
1148 | u32 val; | |
55607e8a | 1149 | bool cur_state; |
040484af JB |
1150 | |
1151 | reg = FDI_RX_CTL(pipe); | |
1152 | val = I915_READ(reg); | |
55607e8a | 1153 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1154 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1155 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1156 | state_string(state), state_string(cur_state)); | |
040484af JB |
1157 | } |
1158 | ||
b680c37a DV |
1159 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1160 | enum pipe pipe) | |
ea0760cf | 1161 | { |
bedd4dba JN |
1162 | struct drm_device *dev = dev_priv->dev; |
1163 | int pp_reg; | |
ea0760cf JB |
1164 | u32 val; |
1165 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1166 | bool locked = true; |
ea0760cf | 1167 | |
bedd4dba JN |
1168 | if (WARN_ON(HAS_DDI(dev))) |
1169 | return; | |
1170 | ||
1171 | if (HAS_PCH_SPLIT(dev)) { | |
1172 | u32 port_sel; | |
1173 | ||
ea0760cf | 1174 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1175 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1176 | ||
1177 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1178 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1179 | panel_pipe = PIPE_B; | |
1180 | /* XXX: else fix for eDP */ | |
1181 | } else if (IS_VALLEYVIEW(dev)) { | |
1182 | /* presumably write lock depends on pipe, not port select */ | |
1183 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1184 | panel_pipe = pipe; | |
ea0760cf JB |
1185 | } else { |
1186 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1187 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1188 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1189 | } |
1190 | ||
1191 | val = I915_READ(pp_reg); | |
1192 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1193 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1194 | locked = false; |
1195 | ||
e2c719b7 | 1196 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1197 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1198 | pipe_name(pipe)); |
ea0760cf JB |
1199 | } |
1200 | ||
93ce0ba6 JN |
1201 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1202 | enum pipe pipe, bool state) | |
1203 | { | |
1204 | struct drm_device *dev = dev_priv->dev; | |
1205 | bool cur_state; | |
1206 | ||
d9d82081 | 1207 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1208 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1209 | else |
5efb3e28 | 1210 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1211 | |
e2c719b7 | 1212 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1213 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1214 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1215 | } | |
1216 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1217 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1218 | ||
b840d907 JB |
1219 | void assert_pipe(struct drm_i915_private *dev_priv, |
1220 | enum pipe pipe, bool state) | |
b24e7179 JB |
1221 | { |
1222 | int reg; | |
1223 | u32 val; | |
63d7bbe9 | 1224 | bool cur_state; |
702e7a56 PZ |
1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1226 | pipe); | |
b24e7179 | 1227 | |
b6b5d049 VS |
1228 | /* if we need the pipe quirk it must be always on */ |
1229 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1230 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1231 | state = true; |
1232 | ||
f458ebbc | 1233 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1234 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1235 | cur_state = false; |
1236 | } else { | |
1237 | reg = PIPECONF(cpu_transcoder); | |
1238 | val = I915_READ(reg); | |
1239 | cur_state = !!(val & PIPECONF_ENABLE); | |
1240 | } | |
1241 | ||
e2c719b7 | 1242 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1243 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1244 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1245 | } |
1246 | ||
931872fc CW |
1247 | static void assert_plane(struct drm_i915_private *dev_priv, |
1248 | enum plane plane, bool state) | |
b24e7179 JB |
1249 | { |
1250 | int reg; | |
1251 | u32 val; | |
931872fc | 1252 | bool cur_state; |
b24e7179 JB |
1253 | |
1254 | reg = DSPCNTR(plane); | |
1255 | val = I915_READ(reg); | |
931872fc | 1256 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1257 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1258 | "plane %c assertion failure (expected %s, current %s)\n", |
1259 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1260 | } |
1261 | ||
931872fc CW |
1262 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1263 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1264 | ||
b24e7179 JB |
1265 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1266 | enum pipe pipe) | |
1267 | { | |
653e1026 | 1268 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1269 | int reg, i; |
1270 | u32 val; | |
1271 | int cur_pipe; | |
1272 | ||
653e1026 VS |
1273 | /* Primary planes are fixed to pipes on gen4+ */ |
1274 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1275 | reg = DSPCNTR(pipe); |
1276 | val = I915_READ(reg); | |
e2c719b7 | 1277 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1278 | "plane %c assertion failure, should be disabled but not\n", |
1279 | plane_name(pipe)); | |
19ec1358 | 1280 | return; |
28c05794 | 1281 | } |
19ec1358 | 1282 | |
b24e7179 | 1283 | /* Need to check both planes against the pipe */ |
055e393f | 1284 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1285 | reg = DSPCNTR(i); |
1286 | val = I915_READ(reg); | |
1287 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1288 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1289 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1290 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1291 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1292 | } |
1293 | } | |
1294 | ||
19332d7a JB |
1295 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1296 | enum pipe pipe) | |
1297 | { | |
20674eef | 1298 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1299 | int reg, sprite; |
19332d7a JB |
1300 | u32 val; |
1301 | ||
7feb8b88 DL |
1302 | if (INTEL_INFO(dev)->gen >= 9) { |
1303 | for_each_sprite(pipe, sprite) { | |
1304 | val = I915_READ(PLANE_CTL(pipe, sprite)); | |
e2c719b7 | 1305 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1306 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1307 | sprite, pipe_name(pipe)); | |
1308 | } | |
1309 | } else if (IS_VALLEYVIEW(dev)) { | |
1fe47785 DL |
1310 | for_each_sprite(pipe, sprite) { |
1311 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1312 | val = I915_READ(reg); |
e2c719b7 | 1313 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1314 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1315 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1316 | } |
1317 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1318 | reg = SPRCTL(pipe); | |
19332d7a | 1319 | val = I915_READ(reg); |
e2c719b7 | 1320 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1321 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1322 | plane_name(pipe), pipe_name(pipe)); |
1323 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1324 | reg = DVSCNTR(pipe); | |
19332d7a | 1325 | val = I915_READ(reg); |
e2c719b7 | 1326 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1327 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1328 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1329 | } |
1330 | } | |
1331 | ||
08c71e5e VS |
1332 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1333 | { | |
e2c719b7 | 1334 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1335 | drm_crtc_vblank_put(crtc); |
1336 | } | |
1337 | ||
89eff4be | 1338 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1339 | { |
1340 | u32 val; | |
1341 | bool enabled; | |
1342 | ||
e2c719b7 | 1343 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1344 | |
92f2584a JB |
1345 | val = I915_READ(PCH_DREF_CONTROL); |
1346 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1347 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1348 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1349 | } |
1350 | ||
ab9412ba DV |
1351 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1352 | enum pipe pipe) | |
92f2584a JB |
1353 | { |
1354 | int reg; | |
1355 | u32 val; | |
1356 | bool enabled; | |
1357 | ||
ab9412ba | 1358 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1359 | val = I915_READ(reg); |
1360 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1361 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1362 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1363 | pipe_name(pipe)); | |
92f2584a JB |
1364 | } |
1365 | ||
4e634389 KP |
1366 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1367 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1368 | { |
1369 | if ((val & DP_PORT_EN) == 0) | |
1370 | return false; | |
1371 | ||
1372 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1373 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1374 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1375 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1376 | return false; | |
44f37d1f CML |
1377 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1378 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1379 | return false; | |
f0575e92 KP |
1380 | } else { |
1381 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1382 | return false; | |
1383 | } | |
1384 | return true; | |
1385 | } | |
1386 | ||
1519b995 KP |
1387 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1388 | enum pipe pipe, u32 val) | |
1389 | { | |
dc0fa718 | 1390 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1391 | return false; |
1392 | ||
1393 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1394 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1395 | return false; |
44f37d1f CML |
1396 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1397 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1398 | return false; | |
1519b995 | 1399 | } else { |
dc0fa718 | 1400 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1401 | return false; |
1402 | } | |
1403 | return true; | |
1404 | } | |
1405 | ||
1406 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1407 | enum pipe pipe, u32 val) | |
1408 | { | |
1409 | if ((val & LVDS_PORT_EN) == 0) | |
1410 | return false; | |
1411 | ||
1412 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1413 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1414 | return false; | |
1415 | } else { | |
1416 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1417 | return false; | |
1418 | } | |
1419 | return true; | |
1420 | } | |
1421 | ||
1422 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1423 | enum pipe pipe, u32 val) | |
1424 | { | |
1425 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1426 | return false; | |
1427 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1428 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1429 | return false; | |
1430 | } else { | |
1431 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1432 | return false; | |
1433 | } | |
1434 | return true; | |
1435 | } | |
1436 | ||
291906f1 | 1437 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1438 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1439 | { |
47a05eca | 1440 | u32 val = I915_READ(reg); |
e2c719b7 | 1441 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1442 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1443 | reg, pipe_name(pipe)); |
de9a35ab | 1444 | |
e2c719b7 | 1445 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1446 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1447 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1448 | } |
1449 | ||
1450 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1451 | enum pipe pipe, int reg) | |
1452 | { | |
47a05eca | 1453 | u32 val = I915_READ(reg); |
e2c719b7 | 1454 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1455 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1456 | reg, pipe_name(pipe)); |
de9a35ab | 1457 | |
e2c719b7 | 1458 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1459 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1460 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1461 | } |
1462 | ||
1463 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1464 | enum pipe pipe) | |
1465 | { | |
1466 | int reg; | |
1467 | u32 val; | |
291906f1 | 1468 | |
f0575e92 KP |
1469 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1470 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1471 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1472 | |
1473 | reg = PCH_ADPA; | |
1474 | val = I915_READ(reg); | |
e2c719b7 | 1475 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1476 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1477 | pipe_name(pipe)); |
291906f1 JB |
1478 | |
1479 | reg = PCH_LVDS; | |
1480 | val = I915_READ(reg); | |
e2c719b7 | 1481 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1482 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1483 | pipe_name(pipe)); |
291906f1 | 1484 | |
e2debe91 PZ |
1485 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1486 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1487 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1488 | } |
1489 | ||
40e9cf64 JB |
1490 | static void intel_init_dpio(struct drm_device *dev) |
1491 | { | |
1492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1493 | ||
1494 | if (!IS_VALLEYVIEW(dev)) | |
1495 | return; | |
1496 | ||
a09caddd CML |
1497 | /* |
1498 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1499 | * CHV x1 PHY (DP/HDMI D) | |
1500 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1501 | */ | |
1502 | if (IS_CHERRYVIEW(dev)) { | |
1503 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1504 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1505 | } else { | |
1506 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1507 | } | |
5382f5f3 JB |
1508 | } |
1509 | ||
d288f65f | 1510 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1511 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1512 | { |
426115cf DV |
1513 | struct drm_device *dev = crtc->base.dev; |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1515 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1516 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1517 | |
426115cf | 1518 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1519 | |
1520 | /* No really, not for ILK+ */ | |
1521 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1522 | ||
1523 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1524 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1525 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1526 | |
426115cf DV |
1527 | I915_WRITE(reg, dpll); |
1528 | POSTING_READ(reg); | |
1529 | udelay(150); | |
1530 | ||
1531 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1532 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1533 | ||
d288f65f | 1534 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1535 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1536 | |
1537 | /* We do this three times for luck */ | |
426115cf | 1538 | I915_WRITE(reg, dpll); |
87442f73 DV |
1539 | POSTING_READ(reg); |
1540 | udelay(150); /* wait for warmup */ | |
426115cf | 1541 | I915_WRITE(reg, dpll); |
87442f73 DV |
1542 | POSTING_READ(reg); |
1543 | udelay(150); /* wait for warmup */ | |
426115cf | 1544 | I915_WRITE(reg, dpll); |
87442f73 DV |
1545 | POSTING_READ(reg); |
1546 | udelay(150); /* wait for warmup */ | |
1547 | } | |
1548 | ||
d288f65f | 1549 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1550 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1551 | { |
1552 | struct drm_device *dev = crtc->base.dev; | |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1554 | int pipe = crtc->pipe; | |
1555 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1556 | u32 tmp; |
1557 | ||
1558 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1559 | ||
1560 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1561 | ||
1562 | mutex_lock(&dev_priv->dpio_lock); | |
1563 | ||
1564 | /* Enable back the 10bit clock to display controller */ | |
1565 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1566 | tmp |= DPIO_DCLKP_EN; | |
1567 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1568 | ||
1569 | /* | |
1570 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1571 | */ | |
1572 | udelay(1); | |
1573 | ||
1574 | /* Enable PLL */ | |
d288f65f | 1575 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1576 | |
1577 | /* Check PLL is locked */ | |
a11b0703 | 1578 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1579 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1580 | ||
a11b0703 | 1581 | /* not sure when this should be written */ |
d288f65f | 1582 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1583 | POSTING_READ(DPLL_MD(pipe)); |
1584 | ||
9d556c99 CML |
1585 | mutex_unlock(&dev_priv->dpio_lock); |
1586 | } | |
1587 | ||
1c4e0274 VS |
1588 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1589 | { | |
1590 | struct intel_crtc *crtc; | |
1591 | int count = 0; | |
1592 | ||
1593 | for_each_intel_crtc(dev, crtc) | |
1594 | count += crtc->active && | |
409ee761 | 1595 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1596 | |
1597 | return count; | |
1598 | } | |
1599 | ||
66e3d5c0 | 1600 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1601 | { |
66e3d5c0 DV |
1602 | struct drm_device *dev = crtc->base.dev; |
1603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1604 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1605 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1606 | |
66e3d5c0 | 1607 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1608 | |
63d7bbe9 | 1609 | /* No really, not for ILK+ */ |
3d13ef2e | 1610 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1611 | |
1612 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1613 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1614 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1615 | |
1c4e0274 VS |
1616 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1617 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1618 | /* | |
1619 | * It appears to be important that we don't enable this | |
1620 | * for the current pipe before otherwise configuring the | |
1621 | * PLL. No idea how this should be handled if multiple | |
1622 | * DVO outputs are enabled simultaneosly. | |
1623 | */ | |
1624 | dpll |= DPLL_DVO_2X_MODE; | |
1625 | I915_WRITE(DPLL(!crtc->pipe), | |
1626 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1627 | } | |
66e3d5c0 DV |
1628 | |
1629 | /* Wait for the clocks to stabilize. */ | |
1630 | POSTING_READ(reg); | |
1631 | udelay(150); | |
1632 | ||
1633 | if (INTEL_INFO(dev)->gen >= 4) { | |
1634 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1635 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1636 | } else { |
1637 | /* The pixel multiplier can only be updated once the | |
1638 | * DPLL is enabled and the clocks are stable. | |
1639 | * | |
1640 | * So write it again. | |
1641 | */ | |
1642 | I915_WRITE(reg, dpll); | |
1643 | } | |
63d7bbe9 JB |
1644 | |
1645 | /* We do this three times for luck */ | |
66e3d5c0 | 1646 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1649 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1650 | POSTING_READ(reg); |
1651 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1652 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1653 | POSTING_READ(reg); |
1654 | udelay(150); /* wait for warmup */ | |
1655 | } | |
1656 | ||
1657 | /** | |
50b44a44 | 1658 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1659 | * @dev_priv: i915 private structure |
1660 | * @pipe: pipe PLL to disable | |
1661 | * | |
1662 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1663 | * | |
1664 | * Note! This is for pre-ILK only. | |
1665 | */ | |
1c4e0274 | 1666 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1667 | { |
1c4e0274 VS |
1668 | struct drm_device *dev = crtc->base.dev; |
1669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1670 | enum pipe pipe = crtc->pipe; | |
1671 | ||
1672 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1673 | if (IS_I830(dev) && | |
409ee761 | 1674 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1675 | intel_num_dvo_pipes(dev) == 1) { |
1676 | I915_WRITE(DPLL(PIPE_B), | |
1677 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1678 | I915_WRITE(DPLL(PIPE_A), | |
1679 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1680 | } | |
1681 | ||
b6b5d049 VS |
1682 | /* Don't disable pipe or pipe PLLs if needed */ |
1683 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1684 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1685 | return; |
1686 | ||
1687 | /* Make sure the pipe isn't still relying on us */ | |
1688 | assert_pipe_disabled(dev_priv, pipe); | |
1689 | ||
50b44a44 DV |
1690 | I915_WRITE(DPLL(pipe), 0); |
1691 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1692 | } |
1693 | ||
f6071166 JB |
1694 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1695 | { | |
1696 | u32 val = 0; | |
1697 | ||
1698 | /* Make sure the pipe isn't still relying on us */ | |
1699 | assert_pipe_disabled(dev_priv, pipe); | |
1700 | ||
e5cbfbfb ID |
1701 | /* |
1702 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1703 | * The latter is needed for VGA hotplug / manual detection. | |
1704 | */ | |
f6071166 | 1705 | if (pipe == PIPE_B) |
e5cbfbfb | 1706 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1707 | I915_WRITE(DPLL(pipe), val); |
1708 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1709 | |
1710 | } | |
1711 | ||
1712 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1713 | { | |
d752048d | 1714 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1715 | u32 val; |
1716 | ||
a11b0703 VS |
1717 | /* Make sure the pipe isn't still relying on us */ |
1718 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1719 | |
a11b0703 | 1720 | /* Set PLL en = 0 */ |
d17ec4ce | 1721 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1722 | if (pipe != PIPE_A) |
1723 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1724 | I915_WRITE(DPLL(pipe), val); | |
1725 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1726 | |
1727 | mutex_lock(&dev_priv->dpio_lock); | |
1728 | ||
1729 | /* Disable 10bit clock to display controller */ | |
1730 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1731 | val &= ~DPIO_DCLKP_EN; | |
1732 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1733 | ||
61407f6d VS |
1734 | /* disable left/right clock distribution */ |
1735 | if (pipe != PIPE_B) { | |
1736 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1737 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1738 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1739 | } else { | |
1740 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1741 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1742 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1743 | } | |
1744 | ||
d752048d | 1745 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1746 | } |
1747 | ||
e4607fcf CML |
1748 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1749 | struct intel_digital_port *dport) | |
89b667f8 JB |
1750 | { |
1751 | u32 port_mask; | |
00fc31b7 | 1752 | int dpll_reg; |
89b667f8 | 1753 | |
e4607fcf CML |
1754 | switch (dport->port) { |
1755 | case PORT_B: | |
89b667f8 | 1756 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1757 | dpll_reg = DPLL(0); |
e4607fcf CML |
1758 | break; |
1759 | case PORT_C: | |
89b667f8 | 1760 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1761 | dpll_reg = DPLL(0); |
1762 | break; | |
1763 | case PORT_D: | |
1764 | port_mask = DPLL_PORTD_READY_MASK; | |
1765 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1766 | break; |
1767 | default: | |
1768 | BUG(); | |
1769 | } | |
89b667f8 | 1770 | |
00fc31b7 | 1771 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1772 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1773 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1774 | } |
1775 | ||
b14b1055 DV |
1776 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1777 | { | |
1778 | struct drm_device *dev = crtc->base.dev; | |
1779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1780 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1781 | ||
be19f0ff CW |
1782 | if (WARN_ON(pll == NULL)) |
1783 | return; | |
1784 | ||
3e369b76 | 1785 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1786 | if (pll->active == 0) { |
1787 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1788 | WARN_ON(pll->on); | |
1789 | assert_shared_dpll_disabled(dev_priv, pll); | |
1790 | ||
1791 | pll->mode_set(dev_priv, pll); | |
1792 | } | |
1793 | } | |
1794 | ||
92f2584a | 1795 | /** |
85b3894f | 1796 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1797 | * @dev_priv: i915 private structure |
1798 | * @pipe: pipe PLL to enable | |
1799 | * | |
1800 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1801 | * drives the transcoder clock. | |
1802 | */ | |
85b3894f | 1803 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1804 | { |
3d13ef2e DL |
1805 | struct drm_device *dev = crtc->base.dev; |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1807 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1808 | |
87a875bb | 1809 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1810 | return; |
1811 | ||
3e369b76 | 1812 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1813 | return; |
ee7b9f93 | 1814 | |
74dd6928 | 1815 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1816 | pll->name, pll->active, pll->on, |
e2b78267 | 1817 | crtc->base.base.id); |
92f2584a | 1818 | |
cdbd2316 DV |
1819 | if (pll->active++) { |
1820 | WARN_ON(!pll->on); | |
e9d6944e | 1821 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1822 | return; |
1823 | } | |
f4a091c7 | 1824 | WARN_ON(pll->on); |
ee7b9f93 | 1825 | |
bd2bb1b9 PZ |
1826 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1827 | ||
46edb027 | 1828 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1829 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1830 | pll->on = true; |
92f2584a JB |
1831 | } |
1832 | ||
f6daaec2 | 1833 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1834 | { |
3d13ef2e DL |
1835 | struct drm_device *dev = crtc->base.dev; |
1836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1837 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1838 | |
92f2584a | 1839 | /* PCH only available on ILK+ */ |
3d13ef2e | 1840 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1841 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1842 | return; |
92f2584a | 1843 | |
3e369b76 | 1844 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1845 | return; |
7a419866 | 1846 | |
46edb027 DV |
1847 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1848 | pll->name, pll->active, pll->on, | |
e2b78267 | 1849 | crtc->base.base.id); |
7a419866 | 1850 | |
48da64a8 | 1851 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1852 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1853 | return; |
1854 | } | |
1855 | ||
e9d6944e | 1856 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1857 | WARN_ON(!pll->on); |
cdbd2316 | 1858 | if (--pll->active) |
7a419866 | 1859 | return; |
ee7b9f93 | 1860 | |
46edb027 | 1861 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1862 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1863 | pll->on = false; |
bd2bb1b9 PZ |
1864 | |
1865 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1866 | } |
1867 | ||
b8a4f404 PZ |
1868 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1869 | enum pipe pipe) | |
040484af | 1870 | { |
23670b32 | 1871 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1872 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1874 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1875 | |
1876 | /* PCH only available on ILK+ */ | |
55522f37 | 1877 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1878 | |
1879 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1880 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1881 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1882 | |
1883 | /* FDI must be feeding us bits for PCH ports */ | |
1884 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1885 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1886 | ||
23670b32 DV |
1887 | if (HAS_PCH_CPT(dev)) { |
1888 | /* Workaround: Set the timing override bit before enabling the | |
1889 | * pch transcoder. */ | |
1890 | reg = TRANS_CHICKEN2(pipe); | |
1891 | val = I915_READ(reg); | |
1892 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1893 | I915_WRITE(reg, val); | |
59c859d6 | 1894 | } |
23670b32 | 1895 | |
ab9412ba | 1896 | reg = PCH_TRANSCONF(pipe); |
040484af | 1897 | val = I915_READ(reg); |
5f7f726d | 1898 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1899 | |
1900 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1901 | /* | |
1902 | * make the BPC in transcoder be consistent with | |
1903 | * that in pipeconf reg. | |
1904 | */ | |
dfd07d72 DV |
1905 | val &= ~PIPECONF_BPC_MASK; |
1906 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1907 | } |
5f7f726d PZ |
1908 | |
1909 | val &= ~TRANS_INTERLACE_MASK; | |
1910 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1911 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1912 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1913 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1914 | else | |
1915 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1916 | else |
1917 | val |= TRANS_PROGRESSIVE; | |
1918 | ||
040484af JB |
1919 | I915_WRITE(reg, val | TRANS_ENABLE); |
1920 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1921 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1922 | } |
1923 | ||
8fb033d7 | 1924 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1925 | enum transcoder cpu_transcoder) |
040484af | 1926 | { |
8fb033d7 | 1927 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1928 | |
1929 | /* PCH only available on ILK+ */ | |
55522f37 | 1930 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1931 | |
8fb033d7 | 1932 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1933 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1934 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1935 | |
223a6fdf PZ |
1936 | /* Workaround: set timing override bit. */ |
1937 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1938 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1939 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1940 | ||
25f3ef11 | 1941 | val = TRANS_ENABLE; |
937bb610 | 1942 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1943 | |
9a76b1c6 PZ |
1944 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1945 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1946 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1947 | else |
1948 | val |= TRANS_PROGRESSIVE; | |
1949 | ||
ab9412ba DV |
1950 | I915_WRITE(LPT_TRANSCONF, val); |
1951 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1952 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1953 | } |
1954 | ||
b8a4f404 PZ |
1955 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1956 | enum pipe pipe) | |
040484af | 1957 | { |
23670b32 DV |
1958 | struct drm_device *dev = dev_priv->dev; |
1959 | uint32_t reg, val; | |
040484af JB |
1960 | |
1961 | /* FDI relies on the transcoder */ | |
1962 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1963 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1964 | ||
291906f1 JB |
1965 | /* Ports must be off as well */ |
1966 | assert_pch_ports_disabled(dev_priv, pipe); | |
1967 | ||
ab9412ba | 1968 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1969 | val = I915_READ(reg); |
1970 | val &= ~TRANS_ENABLE; | |
1971 | I915_WRITE(reg, val); | |
1972 | /* wait for PCH transcoder off, transcoder state */ | |
1973 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1974 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1975 | |
1976 | if (!HAS_PCH_IBX(dev)) { | |
1977 | /* Workaround: Clear the timing override chicken bit again. */ | |
1978 | reg = TRANS_CHICKEN2(pipe); | |
1979 | val = I915_READ(reg); | |
1980 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1981 | I915_WRITE(reg, val); | |
1982 | } | |
040484af JB |
1983 | } |
1984 | ||
ab4d966c | 1985 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1986 | { |
8fb033d7 PZ |
1987 | u32 val; |
1988 | ||
ab9412ba | 1989 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1990 | val &= ~TRANS_ENABLE; |
ab9412ba | 1991 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1992 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1993 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1994 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1995 | |
1996 | /* Workaround: clear timing override bit. */ | |
1997 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1998 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1999 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2000 | } |
2001 | ||
b24e7179 | 2002 | /** |
309cfea8 | 2003 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2004 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2005 | * |
0372264a | 2006 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2007 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2008 | */ |
e1fdc473 | 2009 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2010 | { |
0372264a PZ |
2011 | struct drm_device *dev = crtc->base.dev; |
2012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2013 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2014 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2015 | pipe); | |
1a240d4d | 2016 | enum pipe pch_transcoder; |
b24e7179 JB |
2017 | int reg; |
2018 | u32 val; | |
2019 | ||
58c6eaa2 | 2020 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2021 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2022 | assert_sprites_disabled(dev_priv, pipe); |
2023 | ||
681e5811 | 2024 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2025 | pch_transcoder = TRANSCODER_A; |
2026 | else | |
2027 | pch_transcoder = pipe; | |
2028 | ||
b24e7179 JB |
2029 | /* |
2030 | * A pipe without a PLL won't actually be able to drive bits from | |
2031 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2032 | * need the check. | |
2033 | */ | |
2034 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2035 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2036 | assert_dsi_pll_enabled(dev_priv); |
2037 | else | |
2038 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2039 | else { |
6e3c9717 | 2040 | if (crtc->config->has_pch_encoder) { |
040484af | 2041 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2042 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2043 | assert_fdi_tx_pll_enabled(dev_priv, |
2044 | (enum pipe) cpu_transcoder); | |
040484af JB |
2045 | } |
2046 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2047 | } | |
b24e7179 | 2048 | |
702e7a56 | 2049 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2050 | val = I915_READ(reg); |
7ad25d48 | 2051 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2052 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2053 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2054 | return; |
7ad25d48 | 2055 | } |
00d70b15 CW |
2056 | |
2057 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2058 | POSTING_READ(reg); |
b24e7179 JB |
2059 | } |
2060 | ||
2061 | /** | |
309cfea8 | 2062 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2063 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2064 | * |
575f7ab7 VS |
2065 | * Disable the pipe of @crtc, making sure that various hardware |
2066 | * specific requirements are met, if applicable, e.g. plane | |
2067 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2068 | * |
2069 | * Will wait until the pipe has shut down before returning. | |
2070 | */ | |
575f7ab7 | 2071 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2072 | { |
575f7ab7 | 2073 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2074 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2075 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2076 | int reg; |
2077 | u32 val; | |
2078 | ||
2079 | /* | |
2080 | * Make sure planes won't keep trying to pump pixels to us, | |
2081 | * or we might hang the display. | |
2082 | */ | |
2083 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2084 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2085 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2086 | |
702e7a56 | 2087 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2088 | val = I915_READ(reg); |
00d70b15 CW |
2089 | if ((val & PIPECONF_ENABLE) == 0) |
2090 | return; | |
2091 | ||
67adc644 VS |
2092 | /* |
2093 | * Double wide has implications for planes | |
2094 | * so best keep it disabled when not needed. | |
2095 | */ | |
6e3c9717 | 2096 | if (crtc->config->double_wide) |
67adc644 VS |
2097 | val &= ~PIPECONF_DOUBLE_WIDE; |
2098 | ||
2099 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2100 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2101 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2102 | val &= ~PIPECONF_ENABLE; |
2103 | ||
2104 | I915_WRITE(reg, val); | |
2105 | if ((val & PIPECONF_ENABLE) == 0) | |
2106 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2107 | } |
2108 | ||
d74362c9 KP |
2109 | /* |
2110 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2111 | * trigger in order to latch. The display address reg provides this. | |
2112 | */ | |
1dba99f4 VS |
2113 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2114 | enum plane plane) | |
d74362c9 | 2115 | { |
3d13ef2e DL |
2116 | struct drm_device *dev = dev_priv->dev; |
2117 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2118 | |
2119 | I915_WRITE(reg, I915_READ(reg)); | |
2120 | POSTING_READ(reg); | |
d74362c9 KP |
2121 | } |
2122 | ||
b24e7179 | 2123 | /** |
262ca2b0 | 2124 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2125 | * @plane: plane to be enabled |
2126 | * @crtc: crtc for the plane | |
b24e7179 | 2127 | * |
fdd508a6 | 2128 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2129 | */ |
fdd508a6 VS |
2130 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2131 | struct drm_crtc *crtc) | |
b24e7179 | 2132 | { |
fdd508a6 VS |
2133 | struct drm_device *dev = plane->dev; |
2134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2136 | |
2137 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2138 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2139 | |
98ec7739 VS |
2140 | if (intel_crtc->primary_enabled) |
2141 | return; | |
0037f71c | 2142 | |
4c445e0e | 2143 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2144 | |
fdd508a6 VS |
2145 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2146 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2147 | |
2148 | /* | |
2149 | * BDW signals flip done immediately if the plane | |
2150 | * is disabled, even if the plane enable is already | |
2151 | * armed to occur at the next vblank :( | |
2152 | */ | |
2153 | if (IS_BROADWELL(dev)) | |
2154 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2155 | } |
2156 | ||
b24e7179 | 2157 | /** |
262ca2b0 | 2158 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2159 | * @plane: plane to be disabled |
2160 | * @crtc: crtc for the plane | |
b24e7179 | 2161 | * |
fdd508a6 | 2162 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2163 | */ |
fdd508a6 VS |
2164 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2165 | struct drm_crtc *crtc) | |
b24e7179 | 2166 | { |
fdd508a6 VS |
2167 | struct drm_device *dev = plane->dev; |
2168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2170 | ||
32b7eeec MR |
2171 | if (WARN_ON(!intel_crtc->active)) |
2172 | return; | |
b24e7179 | 2173 | |
98ec7739 VS |
2174 | if (!intel_crtc->primary_enabled) |
2175 | return; | |
0037f71c | 2176 | |
4c445e0e | 2177 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2178 | |
fdd508a6 VS |
2179 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2180 | crtc->x, crtc->y); | |
b24e7179 JB |
2181 | } |
2182 | ||
693db184 CW |
2183 | static bool need_vtd_wa(struct drm_device *dev) |
2184 | { | |
2185 | #ifdef CONFIG_INTEL_IOMMU | |
2186 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2187 | return true; | |
2188 | #endif | |
2189 | return false; | |
2190 | } | |
2191 | ||
ec2c981e | 2192 | int |
091df6cb DV |
2193 | intel_fb_align_height(struct drm_device *dev, int height, |
2194 | uint32_t pixel_format, | |
2195 | uint64_t fb_format_modifier) | |
a57ce0b2 JB |
2196 | { |
2197 | int tile_height; | |
b5d0e9bf | 2198 | uint32_t bits_per_pixel; |
a57ce0b2 | 2199 | |
b5d0e9bf DL |
2200 | switch (fb_format_modifier) { |
2201 | case DRM_FORMAT_MOD_NONE: | |
2202 | tile_height = 1; | |
2203 | break; | |
2204 | case I915_FORMAT_MOD_X_TILED: | |
2205 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2206 | break; | |
2207 | case I915_FORMAT_MOD_Y_TILED: | |
2208 | tile_height = 32; | |
2209 | break; | |
2210 | case I915_FORMAT_MOD_Yf_TILED: | |
2211 | bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2212 | switch (bits_per_pixel) { | |
2213 | default: | |
2214 | case 8: | |
2215 | tile_height = 64; | |
2216 | break; | |
2217 | case 16: | |
2218 | case 32: | |
2219 | tile_height = 32; | |
2220 | break; | |
2221 | case 64: | |
2222 | tile_height = 16; | |
2223 | break; | |
2224 | case 128: | |
2225 | WARN_ONCE(1, | |
2226 | "128-bit pixels are not supported for display!"); | |
2227 | tile_height = 16; | |
2228 | break; | |
2229 | } | |
2230 | break; | |
2231 | default: | |
2232 | MISSING_CASE(fb_format_modifier); | |
2233 | tile_height = 1; | |
2234 | break; | |
2235 | } | |
091df6cb | 2236 | |
a57ce0b2 JB |
2237 | return ALIGN(height, tile_height); |
2238 | } | |
2239 | ||
127bd2ac | 2240 | int |
850c4cdc TU |
2241 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2242 | struct drm_framebuffer *fb, | |
a4872ba6 | 2243 | struct intel_engine_cs *pipelined) |
6b95a207 | 2244 | { |
850c4cdc | 2245 | struct drm_device *dev = fb->dev; |
ce453d81 | 2246 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2247 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 KH |
2248 | u32 alignment; |
2249 | int ret; | |
2250 | ||
ebcdd39e MR |
2251 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2252 | ||
7b911adc TU |
2253 | switch (fb->modifier[0]) { |
2254 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2255 | if (INTEL_INFO(dev)->gen >= 9) |
2256 | alignment = 256 * 1024; | |
2257 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2258 | alignment = 128 * 1024; |
a6c45cf0 | 2259 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2260 | alignment = 4 * 1024; |
2261 | else | |
2262 | alignment = 64 * 1024; | |
6b95a207 | 2263 | break; |
7b911adc | 2264 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2265 | if (INTEL_INFO(dev)->gen >= 9) |
2266 | alignment = 256 * 1024; | |
2267 | else { | |
2268 | /* pin() will align the object as required by fence */ | |
2269 | alignment = 0; | |
2270 | } | |
6b95a207 | 2271 | break; |
7b911adc | 2272 | case I915_FORMAT_MOD_Y_TILED: |
80075d49 | 2273 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2274 | return -EINVAL; |
2275 | default: | |
7b911adc TU |
2276 | MISSING_CASE(fb->modifier[0]); |
2277 | return -EINVAL; | |
6b95a207 KH |
2278 | } |
2279 | ||
693db184 CW |
2280 | /* Note that the w/a also requires 64 PTE of padding following the |
2281 | * bo. We currently fill all unused PTE with the shadow page and so | |
2282 | * we should always have valid PTE following the scanout preventing | |
2283 | * the VT-d warning. | |
2284 | */ | |
2285 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2286 | alignment = 256 * 1024; | |
2287 | ||
d6dd6843 PZ |
2288 | /* |
2289 | * Global gtt pte registers are special registers which actually forward | |
2290 | * writes to a chunk of system memory. Which means that there is no risk | |
2291 | * that the register values disappear as soon as we call | |
2292 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2293 | * pin/unpin/fence and not more. | |
2294 | */ | |
2295 | intel_runtime_pm_get(dev_priv); | |
2296 | ||
ce453d81 | 2297 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2298 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2299 | if (ret) |
ce453d81 | 2300 | goto err_interruptible; |
6b95a207 KH |
2301 | |
2302 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2303 | * fence, whereas 965+ only requires a fence if using | |
2304 | * framebuffer compression. For simplicity, we always install | |
2305 | * a fence as the cost is not that onerous. | |
2306 | */ | |
06d98131 | 2307 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2308 | if (ret) |
2309 | goto err_unpin; | |
1690e1eb | 2310 | |
9a5a53b3 | 2311 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2312 | |
ce453d81 | 2313 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2314 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2315 | return 0; |
48b956c5 CW |
2316 | |
2317 | err_unpin: | |
cc98b413 | 2318 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2319 | err_interruptible: |
2320 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2321 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2322 | return ret; |
6b95a207 KH |
2323 | } |
2324 | ||
f63bdb5f | 2325 | static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1690e1eb | 2326 | { |
ebcdd39e MR |
2327 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2328 | ||
1690e1eb | 2329 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2330 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2331 | } |
2332 | ||
c2c75131 DV |
2333 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2334 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2335 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2336 | unsigned int tiling_mode, | |
2337 | unsigned int cpp, | |
2338 | unsigned int pitch) | |
c2c75131 | 2339 | { |
bc752862 CW |
2340 | if (tiling_mode != I915_TILING_NONE) { |
2341 | unsigned int tile_rows, tiles; | |
c2c75131 | 2342 | |
bc752862 CW |
2343 | tile_rows = *y / 8; |
2344 | *y %= 8; | |
c2c75131 | 2345 | |
bc752862 CW |
2346 | tiles = *x / (512/cpp); |
2347 | *x %= 512/cpp; | |
2348 | ||
2349 | return tile_rows * pitch * 8 + tiles * 4096; | |
2350 | } else { | |
2351 | unsigned int offset; | |
2352 | ||
2353 | offset = *y * pitch + *x * cpp; | |
2354 | *y = 0; | |
2355 | *x = (offset & 4095) / cpp; | |
2356 | return offset & -4096; | |
2357 | } | |
c2c75131 DV |
2358 | } |
2359 | ||
b35d63fa | 2360 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2361 | { |
2362 | switch (format) { | |
2363 | case DISPPLANE_8BPP: | |
2364 | return DRM_FORMAT_C8; | |
2365 | case DISPPLANE_BGRX555: | |
2366 | return DRM_FORMAT_XRGB1555; | |
2367 | case DISPPLANE_BGRX565: | |
2368 | return DRM_FORMAT_RGB565; | |
2369 | default: | |
2370 | case DISPPLANE_BGRX888: | |
2371 | return DRM_FORMAT_XRGB8888; | |
2372 | case DISPPLANE_RGBX888: | |
2373 | return DRM_FORMAT_XBGR8888; | |
2374 | case DISPPLANE_BGRX101010: | |
2375 | return DRM_FORMAT_XRGB2101010; | |
2376 | case DISPPLANE_RGBX101010: | |
2377 | return DRM_FORMAT_XBGR2101010; | |
2378 | } | |
2379 | } | |
2380 | ||
bc8d7dff DL |
2381 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2382 | { | |
2383 | switch (format) { | |
2384 | case PLANE_CTL_FORMAT_RGB_565: | |
2385 | return DRM_FORMAT_RGB565; | |
2386 | default: | |
2387 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2388 | if (rgb_order) { | |
2389 | if (alpha) | |
2390 | return DRM_FORMAT_ABGR8888; | |
2391 | else | |
2392 | return DRM_FORMAT_XBGR8888; | |
2393 | } else { | |
2394 | if (alpha) | |
2395 | return DRM_FORMAT_ARGB8888; | |
2396 | else | |
2397 | return DRM_FORMAT_XRGB8888; | |
2398 | } | |
2399 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2400 | if (rgb_order) | |
2401 | return DRM_FORMAT_XBGR2101010; | |
2402 | else | |
2403 | return DRM_FORMAT_XRGB2101010; | |
2404 | } | |
2405 | } | |
2406 | ||
5724dbd1 DL |
2407 | static bool |
2408 | intel_alloc_plane_obj(struct intel_crtc *crtc, | |
2409 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2410 | { |
2411 | struct drm_device *dev = crtc->base.dev; | |
2412 | struct drm_i915_gem_object *obj = NULL; | |
2413 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2414 | struct drm_framebuffer *fb = &plane_config->fb->base; |
46f297fb JB |
2415 | u32 base = plane_config->base; |
2416 | ||
ff2652ea CW |
2417 | if (plane_config->size == 0) |
2418 | return false; | |
2419 | ||
46f297fb JB |
2420 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2421 | plane_config->size); | |
2422 | if (!obj) | |
484b41dd | 2423 | return false; |
46f297fb | 2424 | |
49af449b DL |
2425 | obj->tiling_mode = plane_config->tiling; |
2426 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2427 | obj->stride = fb->pitches[0]; |
46f297fb | 2428 | |
6bf129df DL |
2429 | mode_cmd.pixel_format = fb->pixel_format; |
2430 | mode_cmd.width = fb->width; | |
2431 | mode_cmd.height = fb->height; | |
2432 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2433 | mode_cmd.modifier[0] = fb->modifier[0]; |
2434 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2435 | |
2436 | mutex_lock(&dev->struct_mutex); | |
2437 | ||
6bf129df | 2438 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2439 | &mode_cmd, obj)) { |
46f297fb JB |
2440 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2441 | goto out_unref_obj; | |
2442 | } | |
2443 | ||
a071fa00 | 2444 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2445 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2446 | |
2447 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2448 | return true; | |
46f297fb JB |
2449 | |
2450 | out_unref_obj: | |
2451 | drm_gem_object_unreference(&obj->base); | |
2452 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2453 | return false; |
2454 | } | |
2455 | ||
afd65eb4 MR |
2456 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2457 | static void | |
2458 | update_state_fb(struct drm_plane *plane) | |
2459 | { | |
2460 | if (plane->fb == plane->state->fb) | |
2461 | return; | |
2462 | ||
2463 | if (plane->state->fb) | |
2464 | drm_framebuffer_unreference(plane->state->fb); | |
2465 | plane->state->fb = plane->fb; | |
2466 | if (plane->state->fb) | |
2467 | drm_framebuffer_reference(plane->state->fb); | |
2468 | } | |
2469 | ||
5724dbd1 DL |
2470 | static void |
2471 | intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2472 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2473 | { |
2474 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2475 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2476 | struct drm_crtc *c; |
2477 | struct intel_crtc *i; | |
2ff8fde1 | 2478 | struct drm_i915_gem_object *obj; |
484b41dd | 2479 | |
2d14030b | 2480 | if (!plane_config->fb) |
484b41dd JB |
2481 | return; |
2482 | ||
f55548b5 | 2483 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) { |
fb9981aa DL |
2484 | struct drm_plane *primary = intel_crtc->base.primary; |
2485 | ||
2486 | primary->fb = &plane_config->fb->base; | |
2487 | primary->state->crtc = &intel_crtc->base; | |
2488 | update_state_fb(primary); | |
2489 | ||
484b41dd | 2490 | return; |
f55548b5 | 2491 | } |
484b41dd | 2492 | |
2d14030b | 2493 | kfree(plane_config->fb); |
484b41dd JB |
2494 | |
2495 | /* | |
2496 | * Failed to alloc the obj, check to see if we should share | |
2497 | * an fb with another CRTC instead | |
2498 | */ | |
70e1e0ec | 2499 | for_each_crtc(dev, c) { |
484b41dd JB |
2500 | i = to_intel_crtc(c); |
2501 | ||
2502 | if (c == &intel_crtc->base) | |
2503 | continue; | |
2504 | ||
2ff8fde1 MR |
2505 | if (!i->active) |
2506 | continue; | |
2507 | ||
2508 | obj = intel_fb_obj(c->primary->fb); | |
2509 | if (obj == NULL) | |
484b41dd JB |
2510 | continue; |
2511 | ||
2ff8fde1 | 2512 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
fb9981aa DL |
2513 | struct drm_plane *primary = intel_crtc->base.primary; |
2514 | ||
d9ceb816 JB |
2515 | if (obj->tiling_mode != I915_TILING_NONE) |
2516 | dev_priv->preserve_bios_swizzle = true; | |
2517 | ||
66e514c1 | 2518 | drm_framebuffer_reference(c->primary->fb); |
fb9981aa DL |
2519 | primary->fb = c->primary->fb; |
2520 | primary->state->crtc = &intel_crtc->base; | |
5ba76c41 | 2521 | update_state_fb(intel_crtc->base.primary); |
2ff8fde1 | 2522 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2523 | break; |
2524 | } | |
2525 | } | |
afd65eb4 | 2526 | |
46f297fb JB |
2527 | } |
2528 | ||
29b9bde6 DV |
2529 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2530 | struct drm_framebuffer *fb, | |
2531 | int x, int y) | |
81255565 JB |
2532 | { |
2533 | struct drm_device *dev = crtc->dev; | |
2534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2535 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2536 | struct drm_i915_gem_object *obj; |
81255565 | 2537 | int plane = intel_crtc->plane; |
e506a0c6 | 2538 | unsigned long linear_offset; |
81255565 | 2539 | u32 dspcntr; |
f45651ba | 2540 | u32 reg = DSPCNTR(plane); |
48404c1e | 2541 | int pixel_size; |
f45651ba | 2542 | |
fdd508a6 VS |
2543 | if (!intel_crtc->primary_enabled) { |
2544 | I915_WRITE(reg, 0); | |
2545 | if (INTEL_INFO(dev)->gen >= 4) | |
2546 | I915_WRITE(DSPSURF(plane), 0); | |
2547 | else | |
2548 | I915_WRITE(DSPADDR(plane), 0); | |
2549 | POSTING_READ(reg); | |
2550 | return; | |
2551 | } | |
2552 | ||
c9ba6fad VS |
2553 | obj = intel_fb_obj(fb); |
2554 | if (WARN_ON(obj == NULL)) | |
2555 | return; | |
2556 | ||
2557 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2558 | ||
f45651ba VS |
2559 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2560 | ||
fdd508a6 | 2561 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2562 | |
2563 | if (INTEL_INFO(dev)->gen < 4) { | |
2564 | if (intel_crtc->pipe == PIPE_B) | |
2565 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2566 | ||
2567 | /* pipesrc and dspsize control the size that is scaled from, | |
2568 | * which should always be the user's requested size. | |
2569 | */ | |
2570 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2571 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2572 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2573 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2574 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2575 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2576 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2577 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2578 | I915_WRITE(PRIMPOS(plane), 0); |
2579 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2580 | } |
81255565 | 2581 | |
57779d06 VS |
2582 | switch (fb->pixel_format) { |
2583 | case DRM_FORMAT_C8: | |
81255565 JB |
2584 | dspcntr |= DISPPLANE_8BPP; |
2585 | break; | |
57779d06 VS |
2586 | case DRM_FORMAT_XRGB1555: |
2587 | case DRM_FORMAT_ARGB1555: | |
2588 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2589 | break; |
57779d06 VS |
2590 | case DRM_FORMAT_RGB565: |
2591 | dspcntr |= DISPPLANE_BGRX565; | |
2592 | break; | |
2593 | case DRM_FORMAT_XRGB8888: | |
2594 | case DRM_FORMAT_ARGB8888: | |
2595 | dspcntr |= DISPPLANE_BGRX888; | |
2596 | break; | |
2597 | case DRM_FORMAT_XBGR8888: | |
2598 | case DRM_FORMAT_ABGR8888: | |
2599 | dspcntr |= DISPPLANE_RGBX888; | |
2600 | break; | |
2601 | case DRM_FORMAT_XRGB2101010: | |
2602 | case DRM_FORMAT_ARGB2101010: | |
2603 | dspcntr |= DISPPLANE_BGRX101010; | |
2604 | break; | |
2605 | case DRM_FORMAT_XBGR2101010: | |
2606 | case DRM_FORMAT_ABGR2101010: | |
2607 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2608 | break; |
2609 | default: | |
baba133a | 2610 | BUG(); |
81255565 | 2611 | } |
57779d06 | 2612 | |
f45651ba VS |
2613 | if (INTEL_INFO(dev)->gen >= 4 && |
2614 | obj->tiling_mode != I915_TILING_NONE) | |
2615 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2616 | |
de1aa629 VS |
2617 | if (IS_G4X(dev)) |
2618 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2619 | ||
b9897127 | 2620 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2621 | |
c2c75131 DV |
2622 | if (INTEL_INFO(dev)->gen >= 4) { |
2623 | intel_crtc->dspaddr_offset = | |
bc752862 | 2624 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2625 | pixel_size, |
bc752862 | 2626 | fb->pitches[0]); |
c2c75131 DV |
2627 | linear_offset -= intel_crtc->dspaddr_offset; |
2628 | } else { | |
e506a0c6 | 2629 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2630 | } |
e506a0c6 | 2631 | |
8e7d688b | 2632 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2633 | dspcntr |= DISPPLANE_ROTATE_180; |
2634 | ||
6e3c9717 ACO |
2635 | x += (intel_crtc->config->pipe_src_w - 1); |
2636 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2637 | |
2638 | /* Finding the last pixel of the last line of the display | |
2639 | data and adding to linear_offset*/ | |
2640 | linear_offset += | |
6e3c9717 ACO |
2641 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2642 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2643 | } |
2644 | ||
2645 | I915_WRITE(reg, dspcntr); | |
2646 | ||
f343c5f6 BW |
2647 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2648 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2649 | fb->pitches[0]); | |
01f2c773 | 2650 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2651 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2652 | I915_WRITE(DSPSURF(plane), |
2653 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2654 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2655 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2656 | } else |
f343c5f6 | 2657 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2658 | POSTING_READ(reg); |
17638cd6 JB |
2659 | } |
2660 | ||
29b9bde6 DV |
2661 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2662 | struct drm_framebuffer *fb, | |
2663 | int x, int y) | |
17638cd6 JB |
2664 | { |
2665 | struct drm_device *dev = crtc->dev; | |
2666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2667 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2668 | struct drm_i915_gem_object *obj; |
17638cd6 | 2669 | int plane = intel_crtc->plane; |
e506a0c6 | 2670 | unsigned long linear_offset; |
17638cd6 | 2671 | u32 dspcntr; |
f45651ba | 2672 | u32 reg = DSPCNTR(plane); |
48404c1e | 2673 | int pixel_size; |
f45651ba | 2674 | |
fdd508a6 VS |
2675 | if (!intel_crtc->primary_enabled) { |
2676 | I915_WRITE(reg, 0); | |
2677 | I915_WRITE(DSPSURF(plane), 0); | |
2678 | POSTING_READ(reg); | |
2679 | return; | |
2680 | } | |
2681 | ||
c9ba6fad VS |
2682 | obj = intel_fb_obj(fb); |
2683 | if (WARN_ON(obj == NULL)) | |
2684 | return; | |
2685 | ||
2686 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2687 | ||
f45651ba VS |
2688 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2689 | ||
fdd508a6 | 2690 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2691 | |
2692 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2693 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2694 | |
57779d06 VS |
2695 | switch (fb->pixel_format) { |
2696 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2697 | dspcntr |= DISPPLANE_8BPP; |
2698 | break; | |
57779d06 VS |
2699 | case DRM_FORMAT_RGB565: |
2700 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2701 | break; |
57779d06 VS |
2702 | case DRM_FORMAT_XRGB8888: |
2703 | case DRM_FORMAT_ARGB8888: | |
2704 | dspcntr |= DISPPLANE_BGRX888; | |
2705 | break; | |
2706 | case DRM_FORMAT_XBGR8888: | |
2707 | case DRM_FORMAT_ABGR8888: | |
2708 | dspcntr |= DISPPLANE_RGBX888; | |
2709 | break; | |
2710 | case DRM_FORMAT_XRGB2101010: | |
2711 | case DRM_FORMAT_ARGB2101010: | |
2712 | dspcntr |= DISPPLANE_BGRX101010; | |
2713 | break; | |
2714 | case DRM_FORMAT_XBGR2101010: | |
2715 | case DRM_FORMAT_ABGR2101010: | |
2716 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2717 | break; |
2718 | default: | |
baba133a | 2719 | BUG(); |
17638cd6 JB |
2720 | } |
2721 | ||
2722 | if (obj->tiling_mode != I915_TILING_NONE) | |
2723 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2724 | |
f45651ba | 2725 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2726 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2727 | |
b9897127 | 2728 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2729 | intel_crtc->dspaddr_offset = |
bc752862 | 2730 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2731 | pixel_size, |
bc752862 | 2732 | fb->pitches[0]); |
c2c75131 | 2733 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2734 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2735 | dspcntr |= DISPPLANE_ROTATE_180; |
2736 | ||
2737 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2738 | x += (intel_crtc->config->pipe_src_w - 1); |
2739 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2740 | |
2741 | /* Finding the last pixel of the last line of the display | |
2742 | data and adding to linear_offset*/ | |
2743 | linear_offset += | |
6e3c9717 ACO |
2744 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2745 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2746 | } |
2747 | } | |
2748 | ||
2749 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2750 | |
f343c5f6 BW |
2751 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2752 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2753 | fb->pitches[0]); | |
01f2c773 | 2754 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2755 | I915_WRITE(DSPSURF(plane), |
2756 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2757 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2758 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2759 | } else { | |
2760 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2761 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2762 | } | |
17638cd6 | 2763 | POSTING_READ(reg); |
17638cd6 JB |
2764 | } |
2765 | ||
b321803d DL |
2766 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2767 | uint32_t pixel_format) | |
2768 | { | |
2769 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2770 | ||
2771 | /* | |
2772 | * The stride is either expressed as a multiple of 64 bytes | |
2773 | * chunks for linear buffers or in number of tiles for tiled | |
2774 | * buffers. | |
2775 | */ | |
2776 | switch (fb_modifier) { | |
2777 | case DRM_FORMAT_MOD_NONE: | |
2778 | return 64; | |
2779 | case I915_FORMAT_MOD_X_TILED: | |
2780 | if (INTEL_INFO(dev)->gen == 2) | |
2781 | return 128; | |
2782 | return 512; | |
2783 | case I915_FORMAT_MOD_Y_TILED: | |
2784 | /* No need to check for old gens and Y tiling since this is | |
2785 | * about the display engine and those will be blocked before | |
2786 | * we get here. | |
2787 | */ | |
2788 | return 128; | |
2789 | case I915_FORMAT_MOD_Yf_TILED: | |
2790 | if (bits_per_pixel == 8) | |
2791 | return 64; | |
2792 | else | |
2793 | return 128; | |
2794 | default: | |
2795 | MISSING_CASE(fb_modifier); | |
2796 | return 64; | |
2797 | } | |
2798 | } | |
2799 | ||
70d21f0e DL |
2800 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2801 | struct drm_framebuffer *fb, | |
2802 | int x, int y) | |
2803 | { | |
2804 | struct drm_device *dev = crtc->dev; | |
2805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2806 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2807 | struct drm_i915_gem_object *obj; |
2808 | int pipe = intel_crtc->pipe; | |
b321803d | 2809 | u32 plane_ctl, stride_div; |
70d21f0e DL |
2810 | |
2811 | if (!intel_crtc->primary_enabled) { | |
2812 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2813 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2814 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2815 | return; | |
2816 | } | |
2817 | ||
2818 | plane_ctl = PLANE_CTL_ENABLE | | |
2819 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2820 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2821 | ||
2822 | switch (fb->pixel_format) { | |
2823 | case DRM_FORMAT_RGB565: | |
2824 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2825 | break; | |
2826 | case DRM_FORMAT_XRGB8888: | |
2827 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2828 | break; | |
2829 | case DRM_FORMAT_XBGR8888: | |
2830 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2831 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2832 | break; | |
2833 | case DRM_FORMAT_XRGB2101010: | |
2834 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2835 | break; | |
2836 | case DRM_FORMAT_XBGR2101010: | |
2837 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2838 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2839 | break; | |
2840 | default: | |
2841 | BUG(); | |
2842 | } | |
2843 | ||
30af77c4 DV |
2844 | switch (fb->modifier[0]) { |
2845 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2846 | break; |
30af77c4 | 2847 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2848 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2849 | break; |
2850 | case I915_FORMAT_MOD_Y_TILED: | |
2851 | plane_ctl |= PLANE_CTL_TILED_Y; | |
2852 | break; | |
2853 | case I915_FORMAT_MOD_Yf_TILED: | |
2854 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
2855 | break; |
2856 | default: | |
b321803d | 2857 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
2858 | } |
2859 | ||
2860 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
8e7d688b | 2861 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) |
1447dde0 | 2862 | plane_ctl |= PLANE_CTL_ROTATE_180; |
70d21f0e | 2863 | |
b321803d DL |
2864 | obj = intel_fb_obj(fb); |
2865 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
2866 | fb->pixel_format); | |
2867 | ||
70d21f0e DL |
2868 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
2869 | ||
2870 | DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n", | |
2871 | i915_gem_obj_ggtt_offset(obj), | |
2872 | x, y, fb->width, fb->height, | |
2873 | fb->pitches[0]); | |
2874 | ||
2875 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
2876 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2877 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
6e3c9717 ACO |
2878 | (intel_crtc->config->pipe_src_h - 1) << 16 | |
2879 | (intel_crtc->config->pipe_src_w - 1)); | |
b321803d | 2880 | I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); |
70d21f0e DL |
2881 | I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); |
2882 | ||
2883 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
2884 | } | |
2885 | ||
17638cd6 JB |
2886 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2887 | static int | |
2888 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2889 | int x, int y, enum mode_set_atomic state) | |
2890 | { | |
2891 | struct drm_device *dev = crtc->dev; | |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2893 | |
6b8e6ed0 CW |
2894 | if (dev_priv->display.disable_fbc) |
2895 | dev_priv->display.disable_fbc(dev); | |
81255565 | 2896 | |
29b9bde6 DV |
2897 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2898 | ||
2899 | return 0; | |
81255565 JB |
2900 | } |
2901 | ||
7514747d | 2902 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 2903 | { |
96a02917 VS |
2904 | struct drm_crtc *crtc; |
2905 | ||
70e1e0ec | 2906 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2907 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2908 | enum plane plane = intel_crtc->plane; | |
2909 | ||
2910 | intel_prepare_page_flip(dev, plane); | |
2911 | intel_finish_page_flip_plane(dev, plane); | |
2912 | } | |
7514747d VS |
2913 | } |
2914 | ||
2915 | static void intel_update_primary_planes(struct drm_device *dev) | |
2916 | { | |
2917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2918 | struct drm_crtc *crtc; | |
96a02917 | 2919 | |
70e1e0ec | 2920 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2921 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2922 | ||
51fd371b | 2923 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2924 | /* |
2925 | * FIXME: Once we have proper support for primary planes (and | |
2926 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2927 | * a NULL crtc->primary->fb. |
947fdaad | 2928 | */ |
f4510a27 | 2929 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2930 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2931 | crtc->primary->fb, |
262ca2b0 MR |
2932 | crtc->x, |
2933 | crtc->y); | |
51fd371b | 2934 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2935 | } |
2936 | } | |
2937 | ||
7514747d VS |
2938 | void intel_prepare_reset(struct drm_device *dev) |
2939 | { | |
f98ce92f VS |
2940 | struct drm_i915_private *dev_priv = to_i915(dev); |
2941 | struct intel_crtc *crtc; | |
2942 | ||
7514747d VS |
2943 | /* no reset support for gen2 */ |
2944 | if (IS_GEN2(dev)) | |
2945 | return; | |
2946 | ||
2947 | /* reset doesn't touch the display */ | |
2948 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
2949 | return; | |
2950 | ||
2951 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
2952 | |
2953 | /* | |
2954 | * Disabling the crtcs gracefully seems nicer. Also the | |
2955 | * g33 docs say we should at least disable all the planes. | |
2956 | */ | |
2957 | for_each_intel_crtc(dev, crtc) { | |
2958 | if (crtc->active) | |
2959 | dev_priv->display.crtc_disable(&crtc->base); | |
2960 | } | |
7514747d VS |
2961 | } |
2962 | ||
2963 | void intel_finish_reset(struct drm_device *dev) | |
2964 | { | |
2965 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2966 | ||
2967 | /* | |
2968 | * Flips in the rings will be nuked by the reset, | |
2969 | * so complete all pending flips so that user space | |
2970 | * will get its events and not get stuck. | |
2971 | */ | |
2972 | intel_complete_page_flips(dev); | |
2973 | ||
2974 | /* no reset support for gen2 */ | |
2975 | if (IS_GEN2(dev)) | |
2976 | return; | |
2977 | ||
2978 | /* reset doesn't touch the display */ | |
2979 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
2980 | /* | |
2981 | * Flips in the rings have been nuked by the reset, | |
2982 | * so update the base address of all primary | |
2983 | * planes to the the last fb to make sure we're | |
2984 | * showing the correct fb after a reset. | |
2985 | */ | |
2986 | intel_update_primary_planes(dev); | |
2987 | return; | |
2988 | } | |
2989 | ||
2990 | /* | |
2991 | * The display has been reset as well, | |
2992 | * so need a full re-initialization. | |
2993 | */ | |
2994 | intel_runtime_pm_disable_interrupts(dev_priv); | |
2995 | intel_runtime_pm_enable_interrupts(dev_priv); | |
2996 | ||
2997 | intel_modeset_init_hw(dev); | |
2998 | ||
2999 | spin_lock_irq(&dev_priv->irq_lock); | |
3000 | if (dev_priv->display.hpd_irq_setup) | |
3001 | dev_priv->display.hpd_irq_setup(dev); | |
3002 | spin_unlock_irq(&dev_priv->irq_lock); | |
3003 | ||
3004 | intel_modeset_setup_hw_state(dev, true); | |
3005 | ||
3006 | intel_hpd_init(dev_priv); | |
3007 | ||
3008 | drm_modeset_unlock_all(dev); | |
3009 | } | |
3010 | ||
14667a4b CW |
3011 | static int |
3012 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3013 | { | |
2ff8fde1 | 3014 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3015 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3016 | bool was_interruptible = dev_priv->mm.interruptible; | |
3017 | int ret; | |
3018 | ||
14667a4b CW |
3019 | /* Big Hammer, we also need to ensure that any pending |
3020 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3021 | * current scanout is retired before unpinning the old | |
3022 | * framebuffer. | |
3023 | * | |
3024 | * This should only fail upon a hung GPU, in which case we | |
3025 | * can safely continue. | |
3026 | */ | |
3027 | dev_priv->mm.interruptible = false; | |
3028 | ret = i915_gem_object_finish_gpu(obj); | |
3029 | dev_priv->mm.interruptible = was_interruptible; | |
3030 | ||
3031 | return ret; | |
3032 | } | |
3033 | ||
7d5e3799 CW |
3034 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3035 | { | |
3036 | struct drm_device *dev = crtc->dev; | |
3037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3039 | bool pending; |
3040 | ||
3041 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3042 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3043 | return false; | |
3044 | ||
5e2d7afc | 3045 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3046 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3047 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3048 | |
3049 | return pending; | |
3050 | } | |
3051 | ||
e30e8f75 GP |
3052 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3053 | { | |
3054 | struct drm_device *dev = crtc->base.dev; | |
3055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3056 | const struct drm_display_mode *adjusted_mode; | |
3057 | ||
3058 | if (!i915.fastboot) | |
3059 | return; | |
3060 | ||
3061 | /* | |
3062 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3063 | * that in compute_mode_changes we check the native mode (not the pfit | |
3064 | * mode) to see if we can flip rather than do a full mode set. In the | |
3065 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3066 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3067 | * sized surface. | |
3068 | * | |
3069 | * To fix this properly, we need to hoist the checks up into | |
3070 | * compute_mode_changes (or above), check the actual pfit state and | |
3071 | * whether the platform allows pfit disable with pipe active, and only | |
3072 | * then update the pipesrc and pfit state, even on the flip path. | |
3073 | */ | |
3074 | ||
6e3c9717 | 3075 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3076 | |
3077 | I915_WRITE(PIPESRC(crtc->pipe), | |
3078 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3079 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3080 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3081 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3082 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3083 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3084 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3085 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3086 | } | |
6e3c9717 ACO |
3087 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3088 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3089 | } |
3090 | ||
5e84e1a4 ZW |
3091 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3092 | { | |
3093 | struct drm_device *dev = crtc->dev; | |
3094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3096 | int pipe = intel_crtc->pipe; | |
3097 | u32 reg, temp; | |
3098 | ||
3099 | /* enable normal train */ | |
3100 | reg = FDI_TX_CTL(pipe); | |
3101 | temp = I915_READ(reg); | |
61e499bf | 3102 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3103 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3104 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3105 | } else { |
3106 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3107 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3108 | } |
5e84e1a4 ZW |
3109 | I915_WRITE(reg, temp); |
3110 | ||
3111 | reg = FDI_RX_CTL(pipe); | |
3112 | temp = I915_READ(reg); | |
3113 | if (HAS_PCH_CPT(dev)) { | |
3114 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3115 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3116 | } else { | |
3117 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3118 | temp |= FDI_LINK_TRAIN_NONE; | |
3119 | } | |
3120 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3121 | ||
3122 | /* wait one idle pattern time */ | |
3123 | POSTING_READ(reg); | |
3124 | udelay(1000); | |
357555c0 JB |
3125 | |
3126 | /* IVB wants error correction enabled */ | |
3127 | if (IS_IVYBRIDGE(dev)) | |
3128 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3129 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3130 | } |
3131 | ||
1fbc0d78 | 3132 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 3133 | { |
83d65738 | 3134 | return crtc->base.state->enable && crtc->active && |
6e3c9717 | 3135 | crtc->config->has_pch_encoder; |
1e833f40 DV |
3136 | } |
3137 | ||
01a415fd DV |
3138 | static void ivb_modeset_global_resources(struct drm_device *dev) |
3139 | { | |
3140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3141 | struct intel_crtc *pipe_B_crtc = | |
3142 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
3143 | struct intel_crtc *pipe_C_crtc = | |
3144 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
3145 | uint32_t temp; | |
3146 | ||
1e833f40 DV |
3147 | /* |
3148 | * When everything is off disable fdi C so that we could enable fdi B | |
3149 | * with all lanes. Note that we don't care about enabled pipes without | |
3150 | * an enabled pch encoder. | |
3151 | */ | |
3152 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
3153 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
3154 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3155 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3156 | ||
3157 | temp = I915_READ(SOUTH_CHICKEN1); | |
3158 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
3159 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
3160 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3161 | } | |
3162 | } | |
3163 | ||
8db9d77b ZW |
3164 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3165 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3166 | { | |
3167 | struct drm_device *dev = crtc->dev; | |
3168 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3170 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3171 | u32 reg, temp, tries; |
8db9d77b | 3172 | |
1c8562f6 | 3173 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3174 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3175 | |
e1a44743 AJ |
3176 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3177 | for train result */ | |
5eddb70b CW |
3178 | reg = FDI_RX_IMR(pipe); |
3179 | temp = I915_READ(reg); | |
e1a44743 AJ |
3180 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3181 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3182 | I915_WRITE(reg, temp); |
3183 | I915_READ(reg); | |
e1a44743 AJ |
3184 | udelay(150); |
3185 | ||
8db9d77b | 3186 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3187 | reg = FDI_TX_CTL(pipe); |
3188 | temp = I915_READ(reg); | |
627eb5a3 | 3189 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3190 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3191 | temp &= ~FDI_LINK_TRAIN_NONE; |
3192 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3193 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3194 | |
5eddb70b CW |
3195 | reg = FDI_RX_CTL(pipe); |
3196 | temp = I915_READ(reg); | |
8db9d77b ZW |
3197 | temp &= ~FDI_LINK_TRAIN_NONE; |
3198 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3199 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3200 | ||
3201 | POSTING_READ(reg); | |
8db9d77b ZW |
3202 | udelay(150); |
3203 | ||
5b2adf89 | 3204 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3205 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3206 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3207 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3208 | |
5eddb70b | 3209 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3210 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3211 | temp = I915_READ(reg); |
8db9d77b ZW |
3212 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3213 | ||
3214 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3215 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3216 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3217 | break; |
3218 | } | |
8db9d77b | 3219 | } |
e1a44743 | 3220 | if (tries == 5) |
5eddb70b | 3221 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3222 | |
3223 | /* Train 2 */ | |
5eddb70b CW |
3224 | reg = FDI_TX_CTL(pipe); |
3225 | temp = I915_READ(reg); | |
8db9d77b ZW |
3226 | temp &= ~FDI_LINK_TRAIN_NONE; |
3227 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3228 | I915_WRITE(reg, temp); |
8db9d77b | 3229 | |
5eddb70b CW |
3230 | reg = FDI_RX_CTL(pipe); |
3231 | temp = I915_READ(reg); | |
8db9d77b ZW |
3232 | temp &= ~FDI_LINK_TRAIN_NONE; |
3233 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3234 | I915_WRITE(reg, temp); |
8db9d77b | 3235 | |
5eddb70b CW |
3236 | POSTING_READ(reg); |
3237 | udelay(150); | |
8db9d77b | 3238 | |
5eddb70b | 3239 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3240 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3241 | temp = I915_READ(reg); |
8db9d77b ZW |
3242 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3243 | ||
3244 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3245 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3246 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3247 | break; | |
3248 | } | |
8db9d77b | 3249 | } |
e1a44743 | 3250 | if (tries == 5) |
5eddb70b | 3251 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3252 | |
3253 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3254 | |
8db9d77b ZW |
3255 | } |
3256 | ||
0206e353 | 3257 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3258 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3259 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3260 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3261 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3262 | }; | |
3263 | ||
3264 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3265 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3266 | { | |
3267 | struct drm_device *dev = crtc->dev; | |
3268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3270 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3271 | u32 reg, temp, i, retry; |
8db9d77b | 3272 | |
e1a44743 AJ |
3273 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3274 | for train result */ | |
5eddb70b CW |
3275 | reg = FDI_RX_IMR(pipe); |
3276 | temp = I915_READ(reg); | |
e1a44743 AJ |
3277 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3278 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3279 | I915_WRITE(reg, temp); |
3280 | ||
3281 | POSTING_READ(reg); | |
e1a44743 AJ |
3282 | udelay(150); |
3283 | ||
8db9d77b | 3284 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3285 | reg = FDI_TX_CTL(pipe); |
3286 | temp = I915_READ(reg); | |
627eb5a3 | 3287 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3288 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3289 | temp &= ~FDI_LINK_TRAIN_NONE; |
3290 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3291 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3292 | /* SNB-B */ | |
3293 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3294 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3295 | |
d74cf324 DV |
3296 | I915_WRITE(FDI_RX_MISC(pipe), |
3297 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3298 | ||
5eddb70b CW |
3299 | reg = FDI_RX_CTL(pipe); |
3300 | temp = I915_READ(reg); | |
8db9d77b ZW |
3301 | if (HAS_PCH_CPT(dev)) { |
3302 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3303 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3304 | } else { | |
3305 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3306 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3307 | } | |
5eddb70b CW |
3308 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3309 | ||
3310 | POSTING_READ(reg); | |
8db9d77b ZW |
3311 | udelay(150); |
3312 | ||
0206e353 | 3313 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3314 | reg = FDI_TX_CTL(pipe); |
3315 | temp = I915_READ(reg); | |
8db9d77b ZW |
3316 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3317 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3318 | I915_WRITE(reg, temp); |
3319 | ||
3320 | POSTING_READ(reg); | |
8db9d77b ZW |
3321 | udelay(500); |
3322 | ||
fa37d39e SP |
3323 | for (retry = 0; retry < 5; retry++) { |
3324 | reg = FDI_RX_IIR(pipe); | |
3325 | temp = I915_READ(reg); | |
3326 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3327 | if (temp & FDI_RX_BIT_LOCK) { | |
3328 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3329 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3330 | break; | |
3331 | } | |
3332 | udelay(50); | |
8db9d77b | 3333 | } |
fa37d39e SP |
3334 | if (retry < 5) |
3335 | break; | |
8db9d77b ZW |
3336 | } |
3337 | if (i == 4) | |
5eddb70b | 3338 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3339 | |
3340 | /* Train 2 */ | |
5eddb70b CW |
3341 | reg = FDI_TX_CTL(pipe); |
3342 | temp = I915_READ(reg); | |
8db9d77b ZW |
3343 | temp &= ~FDI_LINK_TRAIN_NONE; |
3344 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3345 | if (IS_GEN6(dev)) { | |
3346 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3347 | /* SNB-B */ | |
3348 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3349 | } | |
5eddb70b | 3350 | I915_WRITE(reg, temp); |
8db9d77b | 3351 | |
5eddb70b CW |
3352 | reg = FDI_RX_CTL(pipe); |
3353 | temp = I915_READ(reg); | |
8db9d77b ZW |
3354 | if (HAS_PCH_CPT(dev)) { |
3355 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3356 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3357 | } else { | |
3358 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3359 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3360 | } | |
5eddb70b CW |
3361 | I915_WRITE(reg, temp); |
3362 | ||
3363 | POSTING_READ(reg); | |
8db9d77b ZW |
3364 | udelay(150); |
3365 | ||
0206e353 | 3366 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3367 | reg = FDI_TX_CTL(pipe); |
3368 | temp = I915_READ(reg); | |
8db9d77b ZW |
3369 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3370 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3371 | I915_WRITE(reg, temp); |
3372 | ||
3373 | POSTING_READ(reg); | |
8db9d77b ZW |
3374 | udelay(500); |
3375 | ||
fa37d39e SP |
3376 | for (retry = 0; retry < 5; retry++) { |
3377 | reg = FDI_RX_IIR(pipe); | |
3378 | temp = I915_READ(reg); | |
3379 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3380 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3381 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3382 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3383 | break; | |
3384 | } | |
3385 | udelay(50); | |
8db9d77b | 3386 | } |
fa37d39e SP |
3387 | if (retry < 5) |
3388 | break; | |
8db9d77b ZW |
3389 | } |
3390 | if (i == 4) | |
5eddb70b | 3391 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3392 | |
3393 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3394 | } | |
3395 | ||
357555c0 JB |
3396 | /* Manual link training for Ivy Bridge A0 parts */ |
3397 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3398 | { | |
3399 | struct drm_device *dev = crtc->dev; | |
3400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3401 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3402 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3403 | u32 reg, temp, i, j; |
357555c0 JB |
3404 | |
3405 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3406 | for train result */ | |
3407 | reg = FDI_RX_IMR(pipe); | |
3408 | temp = I915_READ(reg); | |
3409 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3410 | temp &= ~FDI_RX_BIT_LOCK; | |
3411 | I915_WRITE(reg, temp); | |
3412 | ||
3413 | POSTING_READ(reg); | |
3414 | udelay(150); | |
3415 | ||
01a415fd DV |
3416 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3417 | I915_READ(FDI_RX_IIR(pipe))); | |
3418 | ||
139ccd3f JB |
3419 | /* Try each vswing and preemphasis setting twice before moving on */ |
3420 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3421 | /* disable first in case we need to retry */ | |
3422 | reg = FDI_TX_CTL(pipe); | |
3423 | temp = I915_READ(reg); | |
3424 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3425 | temp &= ~FDI_TX_ENABLE; | |
3426 | I915_WRITE(reg, temp); | |
357555c0 | 3427 | |
139ccd3f JB |
3428 | reg = FDI_RX_CTL(pipe); |
3429 | temp = I915_READ(reg); | |
3430 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3431 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3432 | temp &= ~FDI_RX_ENABLE; | |
3433 | I915_WRITE(reg, temp); | |
357555c0 | 3434 | |
139ccd3f | 3435 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3436 | reg = FDI_TX_CTL(pipe); |
3437 | temp = I915_READ(reg); | |
139ccd3f | 3438 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3439 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3440 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3441 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3442 | temp |= snb_b_fdi_train_param[j/2]; |
3443 | temp |= FDI_COMPOSITE_SYNC; | |
3444 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3445 | |
139ccd3f JB |
3446 | I915_WRITE(FDI_RX_MISC(pipe), |
3447 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3448 | |
139ccd3f | 3449 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3450 | temp = I915_READ(reg); |
139ccd3f JB |
3451 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3452 | temp |= FDI_COMPOSITE_SYNC; | |
3453 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3454 | |
139ccd3f JB |
3455 | POSTING_READ(reg); |
3456 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3457 | |
139ccd3f JB |
3458 | for (i = 0; i < 4; i++) { |
3459 | reg = FDI_RX_IIR(pipe); | |
3460 | temp = I915_READ(reg); | |
3461 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3462 | |
139ccd3f JB |
3463 | if (temp & FDI_RX_BIT_LOCK || |
3464 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3465 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3466 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3467 | i); | |
3468 | break; | |
3469 | } | |
3470 | udelay(1); /* should be 0.5us */ | |
3471 | } | |
3472 | if (i == 4) { | |
3473 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3474 | continue; | |
3475 | } | |
357555c0 | 3476 | |
139ccd3f | 3477 | /* Train 2 */ |
357555c0 JB |
3478 | reg = FDI_TX_CTL(pipe); |
3479 | temp = I915_READ(reg); | |
139ccd3f JB |
3480 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3481 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3482 | I915_WRITE(reg, temp); | |
3483 | ||
3484 | reg = FDI_RX_CTL(pipe); | |
3485 | temp = I915_READ(reg); | |
3486 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3487 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3488 | I915_WRITE(reg, temp); |
3489 | ||
3490 | POSTING_READ(reg); | |
139ccd3f | 3491 | udelay(2); /* should be 1.5us */ |
357555c0 | 3492 | |
139ccd3f JB |
3493 | for (i = 0; i < 4; i++) { |
3494 | reg = FDI_RX_IIR(pipe); | |
3495 | temp = I915_READ(reg); | |
3496 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3497 | |
139ccd3f JB |
3498 | if (temp & FDI_RX_SYMBOL_LOCK || |
3499 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3500 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3501 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3502 | i); | |
3503 | goto train_done; | |
3504 | } | |
3505 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3506 | } |
139ccd3f JB |
3507 | if (i == 4) |
3508 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3509 | } |
357555c0 | 3510 | |
139ccd3f | 3511 | train_done: |
357555c0 JB |
3512 | DRM_DEBUG_KMS("FDI train done.\n"); |
3513 | } | |
3514 | ||
88cefb6c | 3515 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3516 | { |
88cefb6c | 3517 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3518 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3519 | int pipe = intel_crtc->pipe; |
5eddb70b | 3520 | u32 reg, temp; |
79e53945 | 3521 | |
c64e311e | 3522 | |
c98e9dcf | 3523 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3524 | reg = FDI_RX_CTL(pipe); |
3525 | temp = I915_READ(reg); | |
627eb5a3 | 3526 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3527 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3528 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3529 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3530 | ||
3531 | POSTING_READ(reg); | |
c98e9dcf JB |
3532 | udelay(200); |
3533 | ||
3534 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3535 | temp = I915_READ(reg); |
3536 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3537 | ||
3538 | POSTING_READ(reg); | |
c98e9dcf JB |
3539 | udelay(200); |
3540 | ||
20749730 PZ |
3541 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3542 | reg = FDI_TX_CTL(pipe); | |
3543 | temp = I915_READ(reg); | |
3544 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3545 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3546 | |
20749730 PZ |
3547 | POSTING_READ(reg); |
3548 | udelay(100); | |
6be4a607 | 3549 | } |
0e23b99d JB |
3550 | } |
3551 | ||
88cefb6c DV |
3552 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3553 | { | |
3554 | struct drm_device *dev = intel_crtc->base.dev; | |
3555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3556 | int pipe = intel_crtc->pipe; | |
3557 | u32 reg, temp; | |
3558 | ||
3559 | /* Switch from PCDclk to Rawclk */ | |
3560 | reg = FDI_RX_CTL(pipe); | |
3561 | temp = I915_READ(reg); | |
3562 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3563 | ||
3564 | /* Disable CPU FDI TX PLL */ | |
3565 | reg = FDI_TX_CTL(pipe); | |
3566 | temp = I915_READ(reg); | |
3567 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3568 | ||
3569 | POSTING_READ(reg); | |
3570 | udelay(100); | |
3571 | ||
3572 | reg = FDI_RX_CTL(pipe); | |
3573 | temp = I915_READ(reg); | |
3574 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3575 | ||
3576 | /* Wait for the clocks to turn off. */ | |
3577 | POSTING_READ(reg); | |
3578 | udelay(100); | |
3579 | } | |
3580 | ||
0fc932b8 JB |
3581 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3582 | { | |
3583 | struct drm_device *dev = crtc->dev; | |
3584 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3585 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3586 | int pipe = intel_crtc->pipe; | |
3587 | u32 reg, temp; | |
3588 | ||
3589 | /* disable CPU FDI tx and PCH FDI rx */ | |
3590 | reg = FDI_TX_CTL(pipe); | |
3591 | temp = I915_READ(reg); | |
3592 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3593 | POSTING_READ(reg); | |
3594 | ||
3595 | reg = FDI_RX_CTL(pipe); | |
3596 | temp = I915_READ(reg); | |
3597 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3598 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3599 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3600 | ||
3601 | POSTING_READ(reg); | |
3602 | udelay(100); | |
3603 | ||
3604 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3605 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3606 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3607 | |
3608 | /* still set train pattern 1 */ | |
3609 | reg = FDI_TX_CTL(pipe); | |
3610 | temp = I915_READ(reg); | |
3611 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3612 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3613 | I915_WRITE(reg, temp); | |
3614 | ||
3615 | reg = FDI_RX_CTL(pipe); | |
3616 | temp = I915_READ(reg); | |
3617 | if (HAS_PCH_CPT(dev)) { | |
3618 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3619 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3620 | } else { | |
3621 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3622 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3623 | } | |
3624 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3625 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3626 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3627 | I915_WRITE(reg, temp); |
3628 | ||
3629 | POSTING_READ(reg); | |
3630 | udelay(100); | |
3631 | } | |
3632 | ||
5dce5b93 CW |
3633 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3634 | { | |
3635 | struct intel_crtc *crtc; | |
3636 | ||
3637 | /* Note that we don't need to be called with mode_config.lock here | |
3638 | * as our list of CRTC objects is static for the lifetime of the | |
3639 | * device and so cannot disappear as we iterate. Similarly, we can | |
3640 | * happily treat the predicates as racy, atomic checks as userspace | |
3641 | * cannot claim and pin a new fb without at least acquring the | |
3642 | * struct_mutex and so serialising with us. | |
3643 | */ | |
d3fcc808 | 3644 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3645 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3646 | continue; | |
3647 | ||
3648 | if (crtc->unpin_work) | |
3649 | intel_wait_for_vblank(dev, crtc->pipe); | |
3650 | ||
3651 | return true; | |
3652 | } | |
3653 | ||
3654 | return false; | |
3655 | } | |
3656 | ||
d6bbafa1 CW |
3657 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3658 | { | |
3659 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3660 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3661 | ||
3662 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3663 | smp_rmb(); | |
3664 | intel_crtc->unpin_work = NULL; | |
3665 | ||
3666 | if (work->event) | |
3667 | drm_send_vblank_event(intel_crtc->base.dev, | |
3668 | intel_crtc->pipe, | |
3669 | work->event); | |
3670 | ||
3671 | drm_crtc_vblank_put(&intel_crtc->base); | |
3672 | ||
3673 | wake_up_all(&dev_priv->pending_flip_queue); | |
3674 | queue_work(dev_priv->wq, &work->work); | |
3675 | ||
3676 | trace_i915_flip_complete(intel_crtc->plane, | |
3677 | work->pending_flip_obj); | |
3678 | } | |
3679 | ||
46a55d30 | 3680 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3681 | { |
0f91128d | 3682 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3683 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3684 | |
2c10d571 | 3685 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3686 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3687 | !intel_crtc_has_pending_flip(crtc), | |
3688 | 60*HZ) == 0)) { | |
3689 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3690 | |
5e2d7afc | 3691 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3692 | if (intel_crtc->unpin_work) { |
3693 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3694 | page_flip_completed(intel_crtc); | |
3695 | } | |
5e2d7afc | 3696 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3697 | } |
5bb61643 | 3698 | |
975d568a CW |
3699 | if (crtc->primary->fb) { |
3700 | mutex_lock(&dev->struct_mutex); | |
3701 | intel_finish_fb(crtc->primary->fb); | |
3702 | mutex_unlock(&dev->struct_mutex); | |
3703 | } | |
e6c3a2a6 CW |
3704 | } |
3705 | ||
e615efe4 ED |
3706 | /* Program iCLKIP clock to the desired frequency */ |
3707 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3708 | { | |
3709 | struct drm_device *dev = crtc->dev; | |
3710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3711 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3712 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3713 | u32 temp; | |
3714 | ||
09153000 DV |
3715 | mutex_lock(&dev_priv->dpio_lock); |
3716 | ||
e615efe4 ED |
3717 | /* It is necessary to ungate the pixclk gate prior to programming |
3718 | * the divisors, and gate it back when it is done. | |
3719 | */ | |
3720 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3721 | ||
3722 | /* Disable SSCCTL */ | |
3723 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3724 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3725 | SBI_SSCCTL_DISABLE, | |
3726 | SBI_ICLK); | |
e615efe4 ED |
3727 | |
3728 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3729 | if (clock == 20000) { |
e615efe4 ED |
3730 | auxdiv = 1; |
3731 | divsel = 0x41; | |
3732 | phaseinc = 0x20; | |
3733 | } else { | |
3734 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3735 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3736 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3737 | * convert the virtual clock precision to KHz here for higher |
3738 | * precision. | |
3739 | */ | |
3740 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3741 | u32 iclk_pi_range = 64; | |
3742 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3743 | ||
12d7ceed | 3744 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3745 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3746 | pi_value = desired_divisor % iclk_pi_range; | |
3747 | ||
3748 | auxdiv = 0; | |
3749 | divsel = msb_divisor_value - 2; | |
3750 | phaseinc = pi_value; | |
3751 | } | |
3752 | ||
3753 | /* This should not happen with any sane values */ | |
3754 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3755 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3756 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3757 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3758 | ||
3759 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3760 | clock, |
e615efe4 ED |
3761 | auxdiv, |
3762 | divsel, | |
3763 | phasedir, | |
3764 | phaseinc); | |
3765 | ||
3766 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3767 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3768 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3769 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3770 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3771 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3772 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3773 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3774 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3775 | |
3776 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3777 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3778 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3779 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3780 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3781 | |
3782 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3783 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3784 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3785 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3786 | |
3787 | /* Wait for initialization time */ | |
3788 | udelay(24); | |
3789 | ||
3790 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3791 | |
3792 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3793 | } |
3794 | ||
275f01b2 DV |
3795 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3796 | enum pipe pch_transcoder) | |
3797 | { | |
3798 | struct drm_device *dev = crtc->base.dev; | |
3799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3800 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3801 | |
3802 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3803 | I915_READ(HTOTAL(cpu_transcoder))); | |
3804 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3805 | I915_READ(HBLANK(cpu_transcoder))); | |
3806 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3807 | I915_READ(HSYNC(cpu_transcoder))); | |
3808 | ||
3809 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3810 | I915_READ(VTOTAL(cpu_transcoder))); | |
3811 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3812 | I915_READ(VBLANK(cpu_transcoder))); | |
3813 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3814 | I915_READ(VSYNC(cpu_transcoder))); | |
3815 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3816 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3817 | } | |
3818 | ||
1fbc0d78 DV |
3819 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3820 | { | |
3821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3822 | uint32_t temp; | |
3823 | ||
3824 | temp = I915_READ(SOUTH_CHICKEN1); | |
3825 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3826 | return; | |
3827 | ||
3828 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3829 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3830 | ||
3831 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3832 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3833 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3834 | POSTING_READ(SOUTH_CHICKEN1); | |
3835 | } | |
3836 | ||
3837 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3838 | { | |
3839 | struct drm_device *dev = intel_crtc->base.dev; | |
3840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3841 | ||
3842 | switch (intel_crtc->pipe) { | |
3843 | case PIPE_A: | |
3844 | break; | |
3845 | case PIPE_B: | |
6e3c9717 | 3846 | if (intel_crtc->config->fdi_lanes > 2) |
1fbc0d78 DV |
3847 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
3848 | else | |
3849 | cpt_enable_fdi_bc_bifurcation(dev); | |
3850 | ||
3851 | break; | |
3852 | case PIPE_C: | |
3853 | cpt_enable_fdi_bc_bifurcation(dev); | |
3854 | ||
3855 | break; | |
3856 | default: | |
3857 | BUG(); | |
3858 | } | |
3859 | } | |
3860 | ||
f67a559d JB |
3861 | /* |
3862 | * Enable PCH resources required for PCH ports: | |
3863 | * - PCH PLLs | |
3864 | * - FDI training & RX/TX | |
3865 | * - update transcoder timings | |
3866 | * - DP transcoding bits | |
3867 | * - transcoder | |
3868 | */ | |
3869 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3870 | { |
3871 | struct drm_device *dev = crtc->dev; | |
3872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3874 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3875 | u32 reg, temp; |
2c07245f | 3876 | |
ab9412ba | 3877 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3878 | |
1fbc0d78 DV |
3879 | if (IS_IVYBRIDGE(dev)) |
3880 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3881 | ||
cd986abb DV |
3882 | /* Write the TU size bits before fdi link training, so that error |
3883 | * detection works. */ | |
3884 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3885 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3886 | ||
c98e9dcf | 3887 | /* For PCH output, training FDI link */ |
674cf967 | 3888 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3889 | |
3ad8a208 DV |
3890 | /* We need to program the right clock selection before writing the pixel |
3891 | * mutliplier into the DPLL. */ | |
303b81e0 | 3892 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3893 | u32 sel; |
4b645f14 | 3894 | |
c98e9dcf | 3895 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3896 | temp |= TRANS_DPLL_ENABLE(pipe); |
3897 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 3898 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3899 | temp |= sel; |
3900 | else | |
3901 | temp &= ~sel; | |
c98e9dcf | 3902 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3903 | } |
5eddb70b | 3904 | |
3ad8a208 DV |
3905 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3906 | * transcoder, and we actually should do this to not upset any PCH | |
3907 | * transcoder that already use the clock when we share it. | |
3908 | * | |
3909 | * Note that enable_shared_dpll tries to do the right thing, but | |
3910 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3911 | * the right LVDS enable sequence. */ | |
85b3894f | 3912 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3913 | |
d9b6cb56 JB |
3914 | /* set transcoder timing, panel must allow it */ |
3915 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3916 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3917 | |
303b81e0 | 3918 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3919 | |
c98e9dcf | 3920 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 3921 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 3922 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3923 | reg = TRANS_DP_CTL(pipe); |
3924 | temp = I915_READ(reg); | |
3925 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3926 | TRANS_DP_SYNC_MASK | |
3927 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3928 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3929 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3930 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3931 | |
3932 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3933 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3934 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3935 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3936 | |
3937 | switch (intel_trans_dp_port_sel(crtc)) { | |
3938 | case PCH_DP_B: | |
5eddb70b | 3939 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3940 | break; |
3941 | case PCH_DP_C: | |
5eddb70b | 3942 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3943 | break; |
3944 | case PCH_DP_D: | |
5eddb70b | 3945 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3946 | break; |
3947 | default: | |
e95d41e1 | 3948 | BUG(); |
32f9d658 | 3949 | } |
2c07245f | 3950 | |
5eddb70b | 3951 | I915_WRITE(reg, temp); |
6be4a607 | 3952 | } |
b52eb4dc | 3953 | |
b8a4f404 | 3954 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3955 | } |
3956 | ||
1507e5bd PZ |
3957 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3958 | { | |
3959 | struct drm_device *dev = crtc->dev; | |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 3962 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 3963 | |
ab9412ba | 3964 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3965 | |
8c52b5e8 | 3966 | lpt_program_iclkip(crtc); |
1507e5bd | 3967 | |
0540e488 | 3968 | /* Set transcoder timing. */ |
275f01b2 | 3969 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3970 | |
937bb610 | 3971 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3972 | } |
3973 | ||
716c2e55 | 3974 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3975 | { |
e2b78267 | 3976 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3977 | |
3978 | if (pll == NULL) | |
3979 | return; | |
3980 | ||
3e369b76 | 3981 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 3982 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
3983 | return; |
3984 | } | |
3985 | ||
3e369b76 ACO |
3986 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
3987 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
3988 | WARN_ON(pll->on); |
3989 | WARN_ON(pll->active); | |
3990 | } | |
3991 | ||
6e3c9717 | 3992 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3993 | } |
3994 | ||
190f68c5 ACO |
3995 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
3996 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 3997 | { |
e2b78267 | 3998 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 3999 | struct intel_shared_dpll *pll; |
e2b78267 | 4000 | enum intel_dpll_id i; |
ee7b9f93 | 4001 | |
98b6bd99 DV |
4002 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4003 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4004 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4005 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4006 | |
46edb027 DV |
4007 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4008 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4009 | |
8bd31e67 | 4010 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4011 | |
98b6bd99 DV |
4012 | goto found; |
4013 | } | |
4014 | ||
e72f9fbf DV |
4015 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4016 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4017 | |
4018 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4019 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4020 | continue; |
4021 | ||
190f68c5 | 4022 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4023 | &pll->new_config->hw_state, |
4024 | sizeof(pll->new_config->hw_state)) == 0) { | |
4025 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4026 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4027 | pll->new_config->crtc_mask, |
4028 | pll->active); | |
ee7b9f93 JB |
4029 | goto found; |
4030 | } | |
4031 | } | |
4032 | ||
4033 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4034 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4035 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4036 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4037 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4038 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4039 | goto found; |
4040 | } | |
4041 | } | |
4042 | ||
4043 | return NULL; | |
4044 | ||
4045 | found: | |
8bd31e67 | 4046 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4047 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4048 | |
190f68c5 | 4049 | crtc_state->shared_dpll = i; |
46edb027 DV |
4050 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4051 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4052 | |
8bd31e67 | 4053 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4054 | |
ee7b9f93 JB |
4055 | return pll; |
4056 | } | |
4057 | ||
8bd31e67 ACO |
4058 | /** |
4059 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4060 | * @dev_priv: DRM device | |
4061 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4062 | * | |
4063 | * Starts a new PLL staged config, copying the current config but | |
4064 | * releasing the references of pipes specified in clear_pipes. | |
4065 | */ | |
4066 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4067 | unsigned clear_pipes) | |
4068 | { | |
4069 | struct intel_shared_dpll *pll; | |
4070 | enum intel_dpll_id i; | |
4071 | ||
4072 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4073 | pll = &dev_priv->shared_dplls[i]; | |
4074 | ||
4075 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4076 | GFP_KERNEL); | |
4077 | if (!pll->new_config) | |
4078 | goto cleanup; | |
4079 | ||
4080 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4081 | } | |
4082 | ||
4083 | return 0; | |
4084 | ||
4085 | cleanup: | |
4086 | while (--i >= 0) { | |
4087 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4088 | kfree(pll->new_config); |
8bd31e67 ACO |
4089 | pll->new_config = NULL; |
4090 | } | |
4091 | ||
4092 | return -ENOMEM; | |
4093 | } | |
4094 | ||
4095 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4096 | { | |
4097 | struct intel_shared_dpll *pll; | |
4098 | enum intel_dpll_id i; | |
4099 | ||
4100 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4101 | pll = &dev_priv->shared_dplls[i]; | |
4102 | ||
4103 | WARN_ON(pll->new_config == &pll->config); | |
4104 | ||
4105 | pll->config = *pll->new_config; | |
4106 | kfree(pll->new_config); | |
4107 | pll->new_config = NULL; | |
4108 | } | |
4109 | } | |
4110 | ||
4111 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4112 | { | |
4113 | struct intel_shared_dpll *pll; | |
4114 | enum intel_dpll_id i; | |
4115 | ||
4116 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4117 | pll = &dev_priv->shared_dplls[i]; | |
4118 | ||
4119 | WARN_ON(pll->new_config == &pll->config); | |
4120 | ||
4121 | kfree(pll->new_config); | |
4122 | pll->new_config = NULL; | |
4123 | } | |
4124 | } | |
4125 | ||
a1520318 | 4126 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4127 | { |
4128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4129 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4130 | u32 temp; |
4131 | ||
4132 | temp = I915_READ(dslreg); | |
4133 | udelay(500); | |
4134 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4135 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4136 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4137 | } |
4138 | } | |
4139 | ||
bd2e244f JB |
4140 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4141 | { | |
4142 | struct drm_device *dev = crtc->base.dev; | |
4143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4144 | int pipe = crtc->pipe; | |
4145 | ||
6e3c9717 | 4146 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4147 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4148 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4149 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4150 | } |
4151 | } | |
4152 | ||
b074cec8 JB |
4153 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4154 | { | |
4155 | struct drm_device *dev = crtc->base.dev; | |
4156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4157 | int pipe = crtc->pipe; | |
4158 | ||
6e3c9717 | 4159 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4160 | /* Force use of hard-coded filter coefficients |
4161 | * as some pre-programmed values are broken, | |
4162 | * e.g. x201. | |
4163 | */ | |
4164 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4165 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4166 | PF_PIPE_SEL_IVB(pipe)); | |
4167 | else | |
4168 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4169 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4170 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4171 | } |
4172 | } | |
4173 | ||
4a3b8769 | 4174 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4175 | { |
4176 | struct drm_device *dev = crtc->dev; | |
4177 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4178 | struct drm_plane *plane; |
bb53d4ae VS |
4179 | struct intel_plane *intel_plane; |
4180 | ||
af2b653b MR |
4181 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4182 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4183 | if (intel_plane->pipe == pipe) |
4184 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4185 | } |
bb53d4ae VS |
4186 | } |
4187 | ||
4a3b8769 | 4188 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4189 | { |
4190 | struct drm_device *dev = crtc->dev; | |
4191 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4192 | struct drm_plane *plane; |
bb53d4ae VS |
4193 | struct intel_plane *intel_plane; |
4194 | ||
af2b653b MR |
4195 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4196 | intel_plane = to_intel_plane(plane); | |
bb53d4ae | 4197 | if (intel_plane->pipe == pipe) |
cf4c7c12 | 4198 | plane->funcs->disable_plane(plane); |
af2b653b | 4199 | } |
bb53d4ae VS |
4200 | } |
4201 | ||
20bc8673 | 4202 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4203 | { |
cea165c3 VS |
4204 | struct drm_device *dev = crtc->base.dev; |
4205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4206 | |
6e3c9717 | 4207 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4208 | return; |
4209 | ||
cea165c3 VS |
4210 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4211 | intel_wait_for_vblank(dev, crtc->pipe); | |
4212 | ||
d77e4531 | 4213 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4214 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4215 | mutex_lock(&dev_priv->rps.hw_lock); |
4216 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4217 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4218 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4219 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4220 | * mailbox." Moreover, the mailbox may return a bogus state, |
4221 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4222 | */ |
4223 | } else { | |
4224 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4225 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4226 | * is essentially intel_wait_for_vblank. If we don't have this | |
4227 | * and don't wait for vblanks until the end of crtc_enable, then | |
4228 | * the HW state readout code will complain that the expected | |
4229 | * IPS_CTL value is not the one we read. */ | |
4230 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4231 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4232 | } | |
d77e4531 PZ |
4233 | } |
4234 | ||
20bc8673 | 4235 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4236 | { |
4237 | struct drm_device *dev = crtc->base.dev; | |
4238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4239 | ||
6e3c9717 | 4240 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4241 | return; |
4242 | ||
4243 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4244 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4245 | mutex_lock(&dev_priv->rps.hw_lock); |
4246 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4247 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4248 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4249 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4250 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4251 | } else { |
2a114cc1 | 4252 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4253 | POSTING_READ(IPS_CTL); |
4254 | } | |
d77e4531 PZ |
4255 | |
4256 | /* We need to wait for a vblank before we can disable the plane. */ | |
4257 | intel_wait_for_vblank(dev, crtc->pipe); | |
4258 | } | |
4259 | ||
4260 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4261 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4262 | { | |
4263 | struct drm_device *dev = crtc->dev; | |
4264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4266 | enum pipe pipe = intel_crtc->pipe; | |
4267 | int palreg = PALETTE(pipe); | |
4268 | int i; | |
4269 | bool reenable_ips = false; | |
4270 | ||
4271 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4272 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4273 | return; |
4274 | ||
4275 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4276 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4277 | assert_dsi_pll_enabled(dev_priv); |
4278 | else | |
4279 | assert_pll_enabled(dev_priv, pipe); | |
4280 | } | |
4281 | ||
4282 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4283 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4284 | palreg = LGC_PALETTE(pipe); |
4285 | ||
4286 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4287 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4288 | */ | |
6e3c9717 | 4289 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4290 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4291 | GAMMA_MODE_MODE_SPLIT)) { | |
4292 | hsw_disable_ips(intel_crtc); | |
4293 | reenable_ips = true; | |
4294 | } | |
4295 | ||
4296 | for (i = 0; i < 256; i++) { | |
4297 | I915_WRITE(palreg + 4 * i, | |
4298 | (intel_crtc->lut_r[i] << 16) | | |
4299 | (intel_crtc->lut_g[i] << 8) | | |
4300 | intel_crtc->lut_b[i]); | |
4301 | } | |
4302 | ||
4303 | if (reenable_ips) | |
4304 | hsw_enable_ips(intel_crtc); | |
4305 | } | |
4306 | ||
d3eedb1a VS |
4307 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4308 | { | |
4309 | if (!enable && intel_crtc->overlay) { | |
4310 | struct drm_device *dev = intel_crtc->base.dev; | |
4311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4312 | ||
4313 | mutex_lock(&dev->struct_mutex); | |
4314 | dev_priv->mm.interruptible = false; | |
4315 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4316 | dev_priv->mm.interruptible = true; | |
4317 | mutex_unlock(&dev->struct_mutex); | |
4318 | } | |
4319 | ||
4320 | /* Let userspace switch the overlay on again. In most cases userspace | |
4321 | * has to recompute where to put it anyway. | |
4322 | */ | |
4323 | } | |
4324 | ||
d3eedb1a | 4325 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4326 | { |
4327 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4329 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4330 | |
fdd508a6 | 4331 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4332 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4333 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4334 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4335 | |
4336 | hsw_enable_ips(intel_crtc); | |
4337 | ||
4338 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4339 | intel_fbc_update(dev); |
a5c4d7bc | 4340 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4341 | |
4342 | /* | |
4343 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4344 | * to compute the mask of flip planes precisely. For the time being | |
4345 | * consider this a flip from a NULL plane. | |
4346 | */ | |
4347 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4348 | } |
4349 | ||
d3eedb1a | 4350 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4351 | { |
4352 | struct drm_device *dev = crtc->dev; | |
4353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4354 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4355 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4356 | |
4357 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4358 | |
e35fef21 | 4359 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4360 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4361 | |
4362 | hsw_disable_ips(intel_crtc); | |
4363 | ||
d3eedb1a | 4364 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4365 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4366 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4367 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4368 | |
f99d7069 DV |
4369 | /* |
4370 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4371 | * to compute the mask of flip planes precisely. For the time being | |
4372 | * consider this a flip to a NULL plane. | |
4373 | */ | |
4374 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4375 | } |
4376 | ||
f67a559d JB |
4377 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4378 | { | |
4379 | struct drm_device *dev = crtc->dev; | |
4380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4381 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4382 | struct intel_encoder *encoder; |
f67a559d | 4383 | int pipe = intel_crtc->pipe; |
f67a559d | 4384 | |
83d65738 | 4385 | WARN_ON(!crtc->state->enable); |
08a48469 | 4386 | |
f67a559d JB |
4387 | if (intel_crtc->active) |
4388 | return; | |
4389 | ||
6e3c9717 | 4390 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4391 | intel_prepare_shared_dpll(intel_crtc); |
4392 | ||
6e3c9717 | 4393 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4394 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4395 | |
4396 | intel_set_pipe_timings(intel_crtc); | |
4397 | ||
6e3c9717 | 4398 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4399 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4400 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4401 | } |
4402 | ||
4403 | ironlake_set_pipeconf(crtc); | |
4404 | ||
f67a559d | 4405 | intel_crtc->active = true; |
8664281b | 4406 | |
a72e4c9f DV |
4407 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4408 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4409 | |
f6736a1a | 4410 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4411 | if (encoder->pre_enable) |
4412 | encoder->pre_enable(encoder); | |
f67a559d | 4413 | |
6e3c9717 | 4414 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4415 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4416 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4417 | * enabling. */ | |
88cefb6c | 4418 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4419 | } else { |
4420 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4421 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4422 | } | |
f67a559d | 4423 | |
b074cec8 | 4424 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4425 | |
9c54c0dd JB |
4426 | /* |
4427 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4428 | * clocks enabled | |
4429 | */ | |
4430 | intel_crtc_load_lut(crtc); | |
4431 | ||
f37fcc2a | 4432 | intel_update_watermarks(crtc); |
e1fdc473 | 4433 | intel_enable_pipe(intel_crtc); |
f67a559d | 4434 | |
6e3c9717 | 4435 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4436 | ironlake_pch_enable(crtc); |
c98e9dcf | 4437 | |
f9b61ff6 DV |
4438 | assert_vblank_disabled(crtc); |
4439 | drm_crtc_vblank_on(crtc); | |
4440 | ||
fa5c73b1 DV |
4441 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4442 | encoder->enable(encoder); | |
61b77ddd DV |
4443 | |
4444 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4445 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4446 | |
d3eedb1a | 4447 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4448 | } |
4449 | ||
42db64ef PZ |
4450 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4451 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4452 | { | |
f5adf94e | 4453 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4454 | } |
4455 | ||
e4916946 PZ |
4456 | /* |
4457 | * This implements the workaround described in the "notes" section of the mode | |
4458 | * set sequence documentation. When going from no pipes or single pipe to | |
4459 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4460 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4461 | */ | |
4462 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4463 | { | |
4464 | struct drm_device *dev = crtc->base.dev; | |
4465 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4466 | ||
4467 | /* We want to get the other_active_crtc only if there's only 1 other | |
4468 | * active crtc. */ | |
d3fcc808 | 4469 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4470 | if (!crtc_it->active || crtc_it == crtc) |
4471 | continue; | |
4472 | ||
4473 | if (other_active_crtc) | |
4474 | return; | |
4475 | ||
4476 | other_active_crtc = crtc_it; | |
4477 | } | |
4478 | if (!other_active_crtc) | |
4479 | return; | |
4480 | ||
4481 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4482 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4483 | } | |
4484 | ||
4f771f10 PZ |
4485 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4486 | { | |
4487 | struct drm_device *dev = crtc->dev; | |
4488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4490 | struct intel_encoder *encoder; | |
4491 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4492 | |
83d65738 | 4493 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4494 | |
4495 | if (intel_crtc->active) | |
4496 | return; | |
4497 | ||
df8ad70c DV |
4498 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4499 | intel_enable_shared_dpll(intel_crtc); | |
4500 | ||
6e3c9717 | 4501 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4502 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4503 | |
4504 | intel_set_pipe_timings(intel_crtc); | |
4505 | ||
6e3c9717 ACO |
4506 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4507 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4508 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4509 | } |
4510 | ||
6e3c9717 | 4511 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4512 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4513 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4514 | } |
4515 | ||
4516 | haswell_set_pipeconf(crtc); | |
4517 | ||
4518 | intel_set_pipe_csc(crtc); | |
4519 | ||
4f771f10 | 4520 | intel_crtc->active = true; |
8664281b | 4521 | |
a72e4c9f | 4522 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4523 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4524 | if (encoder->pre_enable) | |
4525 | encoder->pre_enable(encoder); | |
4526 | ||
6e3c9717 | 4527 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4528 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4529 | true); | |
4fe9467d ID |
4530 | dev_priv->display.fdi_link_train(crtc); |
4531 | } | |
4532 | ||
1f544388 | 4533 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4534 | |
bd2e244f JB |
4535 | if (IS_SKYLAKE(dev)) |
4536 | skylake_pfit_enable(intel_crtc); | |
4537 | else | |
4538 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4539 | |
4540 | /* | |
4541 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4542 | * clocks enabled | |
4543 | */ | |
4544 | intel_crtc_load_lut(crtc); | |
4545 | ||
1f544388 | 4546 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4547 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4548 | |
f37fcc2a | 4549 | intel_update_watermarks(crtc); |
e1fdc473 | 4550 | intel_enable_pipe(intel_crtc); |
42db64ef | 4551 | |
6e3c9717 | 4552 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4553 | lpt_pch_enable(crtc); |
4f771f10 | 4554 | |
6e3c9717 | 4555 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4556 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4557 | ||
f9b61ff6 DV |
4558 | assert_vblank_disabled(crtc); |
4559 | drm_crtc_vblank_on(crtc); | |
4560 | ||
8807e55b | 4561 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4562 | encoder->enable(encoder); |
8807e55b JN |
4563 | intel_opregion_notify_encoder(encoder, true); |
4564 | } | |
4f771f10 | 4565 | |
e4916946 PZ |
4566 | /* If we change the relative order between pipe/planes enabling, we need |
4567 | * to change the workaround. */ | |
4568 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4569 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4570 | } |
4571 | ||
bd2e244f JB |
4572 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4573 | { | |
4574 | struct drm_device *dev = crtc->base.dev; | |
4575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4576 | int pipe = crtc->pipe; | |
4577 | ||
4578 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4579 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4580 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4581 | I915_WRITE(PS_CTL(pipe), 0); |
4582 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4583 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4584 | } | |
4585 | } | |
4586 | ||
3f8dce3a DV |
4587 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4588 | { | |
4589 | struct drm_device *dev = crtc->base.dev; | |
4590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4591 | int pipe = crtc->pipe; | |
4592 | ||
4593 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4594 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4595 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4596 | I915_WRITE(PF_CTL(pipe), 0); |
4597 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4598 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4599 | } | |
4600 | } | |
4601 | ||
6be4a607 JB |
4602 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4603 | { | |
4604 | struct drm_device *dev = crtc->dev; | |
4605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4606 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4607 | struct intel_encoder *encoder; |
6be4a607 | 4608 | int pipe = intel_crtc->pipe; |
5eddb70b | 4609 | u32 reg, temp; |
b52eb4dc | 4610 | |
f7abfe8b CW |
4611 | if (!intel_crtc->active) |
4612 | return; | |
4613 | ||
d3eedb1a | 4614 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4615 | |
ea9d758d DV |
4616 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4617 | encoder->disable(encoder); | |
4618 | ||
f9b61ff6 DV |
4619 | drm_crtc_vblank_off(crtc); |
4620 | assert_vblank_disabled(crtc); | |
4621 | ||
6e3c9717 | 4622 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4623 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4624 | |
575f7ab7 | 4625 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4626 | |
3f8dce3a | 4627 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4628 | |
bf49ec8c DV |
4629 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4630 | if (encoder->post_disable) | |
4631 | encoder->post_disable(encoder); | |
2c07245f | 4632 | |
6e3c9717 | 4633 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4634 | ironlake_fdi_disable(crtc); |
913d8d11 | 4635 | |
d925c59a | 4636 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4637 | |
d925c59a DV |
4638 | if (HAS_PCH_CPT(dev)) { |
4639 | /* disable TRANS_DP_CTL */ | |
4640 | reg = TRANS_DP_CTL(pipe); | |
4641 | temp = I915_READ(reg); | |
4642 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4643 | TRANS_DP_PORT_SEL_MASK); | |
4644 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4645 | I915_WRITE(reg, temp); | |
4646 | ||
4647 | /* disable DPLL_SEL */ | |
4648 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4649 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4650 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4651 | } |
e3421a18 | 4652 | |
d925c59a | 4653 | /* disable PCH DPLL */ |
e72f9fbf | 4654 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4655 | |
d925c59a DV |
4656 | ironlake_fdi_pll_disable(intel_crtc); |
4657 | } | |
6b383a7f | 4658 | |
f7abfe8b | 4659 | intel_crtc->active = false; |
46ba614c | 4660 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4661 | |
4662 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4663 | intel_fbc_update(dev); |
d1ebd816 | 4664 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4665 | } |
1b3c7a47 | 4666 | |
4f771f10 | 4667 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4668 | { |
4f771f10 PZ |
4669 | struct drm_device *dev = crtc->dev; |
4670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4672 | struct intel_encoder *encoder; |
6e3c9717 | 4673 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4674 | |
4f771f10 PZ |
4675 | if (!intel_crtc->active) |
4676 | return; | |
4677 | ||
d3eedb1a | 4678 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4679 | |
8807e55b JN |
4680 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4681 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4682 | encoder->disable(encoder); |
8807e55b | 4683 | } |
4f771f10 | 4684 | |
f9b61ff6 DV |
4685 | drm_crtc_vblank_off(crtc); |
4686 | assert_vblank_disabled(crtc); | |
4687 | ||
6e3c9717 | 4688 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4689 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4690 | false); | |
575f7ab7 | 4691 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4692 | |
6e3c9717 | 4693 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4694 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4695 | ||
ad80a810 | 4696 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4697 | |
bd2e244f JB |
4698 | if (IS_SKYLAKE(dev)) |
4699 | skylake_pfit_disable(intel_crtc); | |
4700 | else | |
4701 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4702 | |
1f544388 | 4703 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4704 | |
6e3c9717 | 4705 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4706 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4707 | intel_ddi_fdi_disable(crtc); |
83616634 | 4708 | } |
4f771f10 | 4709 | |
97b040aa ID |
4710 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4711 | if (encoder->post_disable) | |
4712 | encoder->post_disable(encoder); | |
4713 | ||
4f771f10 | 4714 | intel_crtc->active = false; |
46ba614c | 4715 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4716 | |
4717 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4718 | intel_fbc_update(dev); |
4f771f10 | 4719 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4720 | |
4721 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4722 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4723 | } |
4724 | ||
ee7b9f93 JB |
4725 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4726 | { | |
4727 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4728 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4729 | } |
4730 | ||
6441ab5f | 4731 | |
2dd24552 JB |
4732 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4733 | { | |
4734 | struct drm_device *dev = crtc->base.dev; | |
4735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4736 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4737 | |
681a8504 | 4738 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4739 | return; |
4740 | ||
2dd24552 | 4741 | /* |
c0b03411 DV |
4742 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4743 | * according to register description and PRM. | |
2dd24552 | 4744 | */ |
c0b03411 DV |
4745 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4746 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4747 | |
b074cec8 JB |
4748 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4749 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4750 | |
4751 | /* Border color in case we don't scale up to the full screen. Black by | |
4752 | * default, change to something else for debugging. */ | |
4753 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4754 | } |
4755 | ||
d05410f9 DA |
4756 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4757 | { | |
4758 | switch (port) { | |
4759 | case PORT_A: | |
4760 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4761 | case PORT_B: | |
4762 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4763 | case PORT_C: | |
4764 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4765 | case PORT_D: | |
4766 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4767 | default: | |
4768 | WARN_ON_ONCE(1); | |
4769 | return POWER_DOMAIN_PORT_OTHER; | |
4770 | } | |
4771 | } | |
4772 | ||
77d22dca ID |
4773 | #define for_each_power_domain(domain, mask) \ |
4774 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4775 | if ((1 << (domain)) & (mask)) | |
4776 | ||
319be8ae ID |
4777 | enum intel_display_power_domain |
4778 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4779 | { | |
4780 | struct drm_device *dev = intel_encoder->base.dev; | |
4781 | struct intel_digital_port *intel_dig_port; | |
4782 | ||
4783 | switch (intel_encoder->type) { | |
4784 | case INTEL_OUTPUT_UNKNOWN: | |
4785 | /* Only DDI platforms should ever use this output type */ | |
4786 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4787 | case INTEL_OUTPUT_DISPLAYPORT: | |
4788 | case INTEL_OUTPUT_HDMI: | |
4789 | case INTEL_OUTPUT_EDP: | |
4790 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4791 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4792 | case INTEL_OUTPUT_DP_MST: |
4793 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4794 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4795 | case INTEL_OUTPUT_ANALOG: |
4796 | return POWER_DOMAIN_PORT_CRT; | |
4797 | case INTEL_OUTPUT_DSI: | |
4798 | return POWER_DOMAIN_PORT_DSI; | |
4799 | default: | |
4800 | return POWER_DOMAIN_PORT_OTHER; | |
4801 | } | |
4802 | } | |
4803 | ||
4804 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4805 | { |
319be8ae ID |
4806 | struct drm_device *dev = crtc->dev; |
4807 | struct intel_encoder *intel_encoder; | |
4808 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4809 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4810 | unsigned long mask; |
4811 | enum transcoder transcoder; | |
4812 | ||
4813 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4814 | ||
4815 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4816 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4817 | if (intel_crtc->config->pch_pfit.enabled || |
4818 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4819 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4820 | ||
319be8ae ID |
4821 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4822 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4823 | ||
77d22dca ID |
4824 | return mask; |
4825 | } | |
4826 | ||
77d22dca ID |
4827 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4828 | { | |
4829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4830 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4831 | struct intel_crtc *crtc; | |
4832 | ||
4833 | /* | |
4834 | * First get all needed power domains, then put all unneeded, to avoid | |
4835 | * any unnecessary toggling of the power wells. | |
4836 | */ | |
d3fcc808 | 4837 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4838 | enum intel_display_power_domain domain; |
4839 | ||
83d65738 | 4840 | if (!crtc->base.state->enable) |
77d22dca ID |
4841 | continue; |
4842 | ||
319be8ae | 4843 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4844 | |
4845 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4846 | intel_display_power_get(dev_priv, domain); | |
4847 | } | |
4848 | ||
50f6e502 VS |
4849 | if (dev_priv->display.modeset_global_resources) |
4850 | dev_priv->display.modeset_global_resources(dev); | |
4851 | ||
d3fcc808 | 4852 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4853 | enum intel_display_power_domain domain; |
4854 | ||
4855 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4856 | intel_display_power_put(dev_priv, domain); | |
4857 | ||
4858 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4859 | } | |
4860 | ||
4861 | intel_display_set_init_power(dev_priv, false); | |
4862 | } | |
4863 | ||
dfcab17e | 4864 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4865 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4866 | { |
586f49dc | 4867 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4868 | |
586f49dc JB |
4869 | /* Obtain SKU information */ |
4870 | mutex_lock(&dev_priv->dpio_lock); | |
4871 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4872 | CCK_FUSE_HPLL_FREQ_MASK; | |
4873 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4874 | |
dfcab17e | 4875 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4876 | } |
4877 | ||
f8bf63fd VS |
4878 | static void vlv_update_cdclk(struct drm_device *dev) |
4879 | { | |
4880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4881 | ||
4882 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4883 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4884 | dev_priv->vlv_cdclk_freq); |
4885 | ||
4886 | /* | |
4887 | * Program the gmbus_freq based on the cdclk frequency. | |
4888 | * BSpec erroneously claims we should aim for 4MHz, but | |
4889 | * in fact 1MHz is the correct frequency. | |
4890 | */ | |
6be1e3d3 | 4891 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4892 | } |
4893 | ||
30a970c6 JB |
4894 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4895 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4896 | { | |
4897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4898 | u32 val, cmd; | |
4899 | ||
d197b7d3 | 4900 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4901 | |
dfcab17e | 4902 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4903 | cmd = 2; |
dfcab17e | 4904 | else if (cdclk == 266667) |
30a970c6 JB |
4905 | cmd = 1; |
4906 | else | |
4907 | cmd = 0; | |
4908 | ||
4909 | mutex_lock(&dev_priv->rps.hw_lock); | |
4910 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4911 | val &= ~DSPFREQGUAR_MASK; | |
4912 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4913 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4914 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4915 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4916 | 50)) { | |
4917 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4918 | } | |
4919 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4920 | ||
dfcab17e | 4921 | if (cdclk == 400000) { |
6bcda4f0 | 4922 | u32 divider; |
30a970c6 | 4923 | |
6bcda4f0 | 4924 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
4925 | |
4926 | mutex_lock(&dev_priv->dpio_lock); | |
4927 | /* adjust cdclk divider */ | |
4928 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4929 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4930 | val |= divider; |
4931 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4932 | |
4933 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4934 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4935 | 50)) | |
4936 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4937 | mutex_unlock(&dev_priv->dpio_lock); |
4938 | } | |
4939 | ||
4940 | mutex_lock(&dev_priv->dpio_lock); | |
4941 | /* adjust self-refresh exit latency value */ | |
4942 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4943 | val &= ~0x7f; | |
4944 | ||
4945 | /* | |
4946 | * For high bandwidth configs, we set a higher latency in the bunit | |
4947 | * so that the core display fetch happens in time to avoid underruns. | |
4948 | */ | |
dfcab17e | 4949 | if (cdclk == 400000) |
30a970c6 JB |
4950 | val |= 4500 / 250; /* 4.5 usec */ |
4951 | else | |
4952 | val |= 3000 / 250; /* 3.0 usec */ | |
4953 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4954 | mutex_unlock(&dev_priv->dpio_lock); | |
4955 | ||
f8bf63fd | 4956 | vlv_update_cdclk(dev); |
30a970c6 JB |
4957 | } |
4958 | ||
383c5a6a VS |
4959 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4960 | { | |
4961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4962 | u32 val, cmd; | |
4963 | ||
4964 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4965 | ||
4966 | switch (cdclk) { | |
4967 | case 400000: | |
4968 | cmd = 3; | |
4969 | break; | |
4970 | case 333333: | |
4971 | case 320000: | |
4972 | cmd = 2; | |
4973 | break; | |
4974 | case 266667: | |
4975 | cmd = 1; | |
4976 | break; | |
4977 | case 200000: | |
4978 | cmd = 0; | |
4979 | break; | |
4980 | default: | |
5f77eeb0 | 4981 | MISSING_CASE(cdclk); |
383c5a6a VS |
4982 | return; |
4983 | } | |
4984 | ||
4985 | mutex_lock(&dev_priv->rps.hw_lock); | |
4986 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4987 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4988 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4989 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4990 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4991 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4992 | 50)) { | |
4993 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4994 | } | |
4995 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4996 | ||
4997 | vlv_update_cdclk(dev); | |
4998 | } | |
4999 | ||
30a970c6 JB |
5000 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5001 | int max_pixclk) | |
5002 | { | |
6bcda4f0 | 5003 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
29dc7ef3 | 5004 | |
d49a340d VS |
5005 | /* FIXME: Punit isn't quite ready yet */ |
5006 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
5007 | return 400000; | |
5008 | ||
30a970c6 JB |
5009 | /* |
5010 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5011 | * 200MHz | |
5012 | * 267MHz | |
29dc7ef3 | 5013 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
5014 | * 400MHz |
5015 | * So we check to see whether we're above 90% of the lower bin and | |
5016 | * adjust if needed. | |
e37c67a1 VS |
5017 | * |
5018 | * We seem to get an unstable or solid color picture at 200MHz. | |
5019 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5020 | * are off. | |
30a970c6 | 5021 | */ |
29dc7ef3 | 5022 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
5023 | return 400000; |
5024 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 5025 | return freq_320; |
e37c67a1 | 5026 | else if (max_pixclk > 0) |
dfcab17e | 5027 | return 266667; |
e37c67a1 VS |
5028 | else |
5029 | return 200000; | |
30a970c6 JB |
5030 | } |
5031 | ||
2f2d7aa1 VS |
5032 | /* compute the max pixel clock for new configuration */ |
5033 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
5034 | { |
5035 | struct drm_device *dev = dev_priv->dev; | |
5036 | struct intel_crtc *intel_crtc; | |
5037 | int max_pixclk = 0; | |
5038 | ||
d3fcc808 | 5039 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 5040 | if (intel_crtc->new_enabled) |
30a970c6 | 5041 | max_pixclk = max(max_pixclk, |
2d112de7 | 5042 | intel_crtc->new_config->base.adjusted_mode.crtc_clock); |
30a970c6 JB |
5043 | } |
5044 | ||
5045 | return max_pixclk; | |
5046 | } | |
5047 | ||
5048 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 5049 | unsigned *prepare_pipes) |
30a970c6 JB |
5050 | { |
5051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5052 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 5053 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 5054 | |
d60c4473 ID |
5055 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5056 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
5057 | return; |
5058 | ||
2f2d7aa1 | 5059 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 5060 | for_each_intel_crtc(dev, intel_crtc) |
83d65738 | 5061 | if (intel_crtc->base.state->enable) |
30a970c6 JB |
5062 | *prepare_pipes |= (1 << intel_crtc->pipe); |
5063 | } | |
5064 | ||
5065 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
5066 | { | |
5067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 5068 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
5069 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
5070 | ||
383c5a6a | 5071 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5072 | /* |
5073 | * FIXME: We can end up here with all power domains off, yet | |
5074 | * with a CDCLK frequency other than the minimum. To account | |
5075 | * for this take the PIPE-A power domain, which covers the HW | |
5076 | * blocks needed for the following programming. This can be | |
5077 | * removed once it's guaranteed that we get here either with | |
5078 | * the minimum CDCLK set, or the required power domains | |
5079 | * enabled. | |
5080 | */ | |
5081 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5082 | ||
383c5a6a VS |
5083 | if (IS_CHERRYVIEW(dev)) |
5084 | cherryview_set_cdclk(dev, req_cdclk); | |
5085 | else | |
5086 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 ID |
5087 | |
5088 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
383c5a6a | 5089 | } |
30a970c6 JB |
5090 | } |
5091 | ||
89b667f8 JB |
5092 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5093 | { | |
5094 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5095 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5097 | struct intel_encoder *encoder; | |
5098 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5099 | bool is_dsi; |
89b667f8 | 5100 | |
83d65738 | 5101 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5102 | |
5103 | if (intel_crtc->active) | |
5104 | return; | |
5105 | ||
409ee761 | 5106 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5107 | |
1ae0d137 VS |
5108 | if (!is_dsi) { |
5109 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5110 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5111 | else |
6e3c9717 | 5112 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5113 | } |
5b18e57c | 5114 | |
6e3c9717 | 5115 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5116 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5117 | |
5118 | intel_set_pipe_timings(intel_crtc); | |
5119 | ||
c14b0485 VS |
5120 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5122 | ||
5123 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5124 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5125 | } | |
5126 | ||
5b18e57c DV |
5127 | i9xx_set_pipeconf(intel_crtc); |
5128 | ||
89b667f8 | 5129 | intel_crtc->active = true; |
89b667f8 | 5130 | |
a72e4c9f | 5131 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5132 | |
89b667f8 JB |
5133 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5134 | if (encoder->pre_pll_enable) | |
5135 | encoder->pre_pll_enable(encoder); | |
5136 | ||
9d556c99 CML |
5137 | if (!is_dsi) { |
5138 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5139 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5140 | else |
6e3c9717 | 5141 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5142 | } |
89b667f8 JB |
5143 | |
5144 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5145 | if (encoder->pre_enable) | |
5146 | encoder->pre_enable(encoder); | |
5147 | ||
2dd24552 JB |
5148 | i9xx_pfit_enable(intel_crtc); |
5149 | ||
63cbb074 VS |
5150 | intel_crtc_load_lut(crtc); |
5151 | ||
f37fcc2a | 5152 | intel_update_watermarks(crtc); |
e1fdc473 | 5153 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5154 | |
4b3a9526 VS |
5155 | assert_vblank_disabled(crtc); |
5156 | drm_crtc_vblank_on(crtc); | |
5157 | ||
f9b61ff6 DV |
5158 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5159 | encoder->enable(encoder); | |
5160 | ||
9ab0460b | 5161 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5162 | |
56b80e1f | 5163 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5164 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5165 | } |
5166 | ||
f13c2ef3 DV |
5167 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5168 | { | |
5169 | struct drm_device *dev = crtc->base.dev; | |
5170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5171 | ||
6e3c9717 ACO |
5172 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5173 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5174 | } |
5175 | ||
0b8765c6 | 5176 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5177 | { |
5178 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5179 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5181 | struct intel_encoder *encoder; |
79e53945 | 5182 | int pipe = intel_crtc->pipe; |
79e53945 | 5183 | |
83d65738 | 5184 | WARN_ON(!crtc->state->enable); |
08a48469 | 5185 | |
f7abfe8b CW |
5186 | if (intel_crtc->active) |
5187 | return; | |
5188 | ||
f13c2ef3 DV |
5189 | i9xx_set_pll_dividers(intel_crtc); |
5190 | ||
6e3c9717 | 5191 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5192 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5193 | |
5194 | intel_set_pipe_timings(intel_crtc); | |
5195 | ||
5b18e57c DV |
5196 | i9xx_set_pipeconf(intel_crtc); |
5197 | ||
f7abfe8b | 5198 | intel_crtc->active = true; |
6b383a7f | 5199 | |
4a3436e8 | 5200 | if (!IS_GEN2(dev)) |
a72e4c9f | 5201 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5202 | |
9d6d9f19 MK |
5203 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5204 | if (encoder->pre_enable) | |
5205 | encoder->pre_enable(encoder); | |
5206 | ||
f6736a1a DV |
5207 | i9xx_enable_pll(intel_crtc); |
5208 | ||
2dd24552 JB |
5209 | i9xx_pfit_enable(intel_crtc); |
5210 | ||
63cbb074 VS |
5211 | intel_crtc_load_lut(crtc); |
5212 | ||
f37fcc2a | 5213 | intel_update_watermarks(crtc); |
e1fdc473 | 5214 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5215 | |
4b3a9526 VS |
5216 | assert_vblank_disabled(crtc); |
5217 | drm_crtc_vblank_on(crtc); | |
5218 | ||
f9b61ff6 DV |
5219 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5220 | encoder->enable(encoder); | |
5221 | ||
9ab0460b | 5222 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5223 | |
4a3436e8 VS |
5224 | /* |
5225 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5226 | * So don't enable underrun reporting before at least some planes | |
5227 | * are enabled. | |
5228 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5229 | * but leave the pipe running. | |
5230 | */ | |
5231 | if (IS_GEN2(dev)) | |
a72e4c9f | 5232 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5233 | |
56b80e1f | 5234 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5235 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5236 | } |
79e53945 | 5237 | |
87476d63 DV |
5238 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5239 | { | |
5240 | struct drm_device *dev = crtc->base.dev; | |
5241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5242 | |
6e3c9717 | 5243 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5244 | return; |
87476d63 | 5245 | |
328d8e82 | 5246 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5247 | |
328d8e82 DV |
5248 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5249 | I915_READ(PFIT_CONTROL)); | |
5250 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5251 | } |
5252 | ||
0b8765c6 JB |
5253 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5254 | { | |
5255 | struct drm_device *dev = crtc->dev; | |
5256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5258 | struct intel_encoder *encoder; |
0b8765c6 | 5259 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5260 | |
f7abfe8b CW |
5261 | if (!intel_crtc->active) |
5262 | return; | |
5263 | ||
4a3436e8 VS |
5264 | /* |
5265 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5266 | * So diasble underrun reporting before all the planes get disabled. | |
5267 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5268 | * but leave the pipe running. | |
5269 | */ | |
5270 | if (IS_GEN2(dev)) | |
a72e4c9f | 5271 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5272 | |
564ed191 ID |
5273 | /* |
5274 | * Vblank time updates from the shadow to live plane control register | |
5275 | * are blocked if the memory self-refresh mode is active at that | |
5276 | * moment. So to make sure the plane gets truly disabled, disable | |
5277 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5278 | * will be checked/applied by the HW only at the next frame start | |
5279 | * event which is after the vblank start event, so we need to have a | |
5280 | * wait-for-vblank between disabling the plane and the pipe. | |
5281 | */ | |
5282 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5283 | intel_crtc_disable_planes(crtc); |
5284 | ||
6304cd91 VS |
5285 | /* |
5286 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5287 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5288 | * We also need to wait on all gmch platforms because of the |
5289 | * self-refresh mode constraint explained above. | |
6304cd91 | 5290 | */ |
564ed191 | 5291 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5292 | |
4b3a9526 VS |
5293 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5294 | encoder->disable(encoder); | |
5295 | ||
f9b61ff6 DV |
5296 | drm_crtc_vblank_off(crtc); |
5297 | assert_vblank_disabled(crtc); | |
5298 | ||
575f7ab7 | 5299 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5300 | |
87476d63 | 5301 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5302 | |
89b667f8 JB |
5303 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5304 | if (encoder->post_disable) | |
5305 | encoder->post_disable(encoder); | |
5306 | ||
409ee761 | 5307 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5308 | if (IS_CHERRYVIEW(dev)) |
5309 | chv_disable_pll(dev_priv, pipe); | |
5310 | else if (IS_VALLEYVIEW(dev)) | |
5311 | vlv_disable_pll(dev_priv, pipe); | |
5312 | else | |
1c4e0274 | 5313 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5314 | } |
0b8765c6 | 5315 | |
4a3436e8 | 5316 | if (!IS_GEN2(dev)) |
a72e4c9f | 5317 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5318 | |
f7abfe8b | 5319 | intel_crtc->active = false; |
46ba614c | 5320 | intel_update_watermarks(crtc); |
f37fcc2a | 5321 | |
efa9624e | 5322 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5323 | intel_fbc_update(dev); |
efa9624e | 5324 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5325 | } |
5326 | ||
ee7b9f93 JB |
5327 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5328 | { | |
5329 | } | |
5330 | ||
b04c5bd6 BF |
5331 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5332 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5333 | { |
5334 | struct drm_device *dev = crtc->dev; | |
5335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5337 | enum intel_display_power_domain domain; |
5338 | unsigned long domains; | |
976f8a20 | 5339 | |
0e572fe7 DV |
5340 | if (enable) { |
5341 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5342 | domains = get_crtc_power_domains(crtc); |
5343 | for_each_power_domain(domain, domains) | |
5344 | intel_display_power_get(dev_priv, domain); | |
5345 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5346 | |
5347 | dev_priv->display.crtc_enable(crtc); | |
5348 | } | |
5349 | } else { | |
5350 | if (intel_crtc->active) { | |
5351 | dev_priv->display.crtc_disable(crtc); | |
5352 | ||
e1e9fb84 DV |
5353 | domains = intel_crtc->enabled_power_domains; |
5354 | for_each_power_domain(domain, domains) | |
5355 | intel_display_power_put(dev_priv, domain); | |
5356 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5357 | } |
5358 | } | |
b04c5bd6 BF |
5359 | } |
5360 | ||
5361 | /** | |
5362 | * Sets the power management mode of the pipe and plane. | |
5363 | */ | |
5364 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5365 | { | |
5366 | struct drm_device *dev = crtc->dev; | |
5367 | struct intel_encoder *intel_encoder; | |
5368 | bool enable = false; | |
5369 | ||
5370 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5371 | enable |= intel_encoder->connectors_active; | |
5372 | ||
5373 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5374 | } |
5375 | ||
cdd59983 CW |
5376 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5377 | { | |
cdd59983 | 5378 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5379 | struct drm_connector *connector; |
ee7b9f93 | 5380 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5381 | |
976f8a20 | 5382 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5383 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5384 | |
5385 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5386 | dev_priv->display.off(crtc); |
5387 | ||
455a6808 | 5388 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5389 | |
5390 | /* Update computed state. */ | |
5391 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5392 | if (!connector->encoder || !connector->encoder->crtc) | |
5393 | continue; | |
5394 | ||
5395 | if (connector->encoder->crtc != crtc) | |
5396 | continue; | |
5397 | ||
5398 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5399 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5400 | } |
5401 | } | |
5402 | ||
ea5b213a | 5403 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5404 | { |
4ef69c7a | 5405 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5406 | |
ea5b213a CW |
5407 | drm_encoder_cleanup(encoder); |
5408 | kfree(intel_encoder); | |
7e7d76c3 JB |
5409 | } |
5410 | ||
9237329d | 5411 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5412 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5413 | * state of the entire output pipe. */ | |
9237329d | 5414 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5415 | { |
5ab432ef DV |
5416 | if (mode == DRM_MODE_DPMS_ON) { |
5417 | encoder->connectors_active = true; | |
5418 | ||
b2cabb0e | 5419 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5420 | } else { |
5421 | encoder->connectors_active = false; | |
5422 | ||
b2cabb0e | 5423 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5424 | } |
79e53945 JB |
5425 | } |
5426 | ||
0a91ca29 DV |
5427 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5428 | * internal consistency). */ | |
b980514c | 5429 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5430 | { |
0a91ca29 DV |
5431 | if (connector->get_hw_state(connector)) { |
5432 | struct intel_encoder *encoder = connector->encoder; | |
5433 | struct drm_crtc *crtc; | |
5434 | bool encoder_enabled; | |
5435 | enum pipe pipe; | |
5436 | ||
5437 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5438 | connector->base.base.id, | |
c23cc417 | 5439 | connector->base.name); |
0a91ca29 | 5440 | |
0e32b39c DA |
5441 | /* there is no real hw state for MST connectors */ |
5442 | if (connector->mst_port) | |
5443 | return; | |
5444 | ||
e2c719b7 | 5445 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5446 | "wrong connector dpms state\n"); |
e2c719b7 | 5447 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5448 | "active connector not linked to encoder\n"); |
0a91ca29 | 5449 | |
36cd7444 | 5450 | if (encoder) { |
e2c719b7 | 5451 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5452 | "encoder->connectors_active not set\n"); |
5453 | ||
5454 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5455 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5456 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5457 | return; |
0a91ca29 | 5458 | |
36cd7444 | 5459 | crtc = encoder->base.crtc; |
0a91ca29 | 5460 | |
83d65738 MR |
5461 | I915_STATE_WARN(!crtc->state->enable, |
5462 | "crtc not enabled\n"); | |
e2c719b7 RC |
5463 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5464 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5465 | "encoder active on the wrong pipe\n"); |
5466 | } | |
0a91ca29 | 5467 | } |
79e53945 JB |
5468 | } |
5469 | ||
5ab432ef DV |
5470 | /* Even simpler default implementation, if there's really no special case to |
5471 | * consider. */ | |
5472 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5473 | { |
5ab432ef DV |
5474 | /* All the simple cases only support two dpms states. */ |
5475 | if (mode != DRM_MODE_DPMS_ON) | |
5476 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5477 | |
5ab432ef DV |
5478 | if (mode == connector->dpms) |
5479 | return; | |
5480 | ||
5481 | connector->dpms = mode; | |
5482 | ||
5483 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5484 | if (connector->encoder) |
5485 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5486 | |
b980514c | 5487 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5488 | } |
5489 | ||
f0947c37 DV |
5490 | /* Simple connector->get_hw_state implementation for encoders that support only |
5491 | * one connector and no cloning and hence the encoder state determines the state | |
5492 | * of the connector. */ | |
5493 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5494 | { |
24929352 | 5495 | enum pipe pipe = 0; |
f0947c37 | 5496 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5497 | |
f0947c37 | 5498 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5499 | } |
5500 | ||
1857e1da | 5501 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5502 | struct intel_crtc_state *pipe_config) |
1857e1da DV |
5503 | { |
5504 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5505 | struct intel_crtc *pipe_B_crtc = | |
5506 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5507 | ||
5508 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5509 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5510 | if (pipe_config->fdi_lanes > 4) { | |
5511 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5512 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5513 | return false; | |
5514 | } | |
5515 | ||
bafb6553 | 5516 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5517 | if (pipe_config->fdi_lanes > 2) { |
5518 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5519 | pipe_config->fdi_lanes); | |
5520 | return false; | |
5521 | } else { | |
5522 | return true; | |
5523 | } | |
5524 | } | |
5525 | ||
5526 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5527 | return true; | |
5528 | ||
5529 | /* Ivybridge 3 pipe is really complicated */ | |
5530 | switch (pipe) { | |
5531 | case PIPE_A: | |
5532 | return true; | |
5533 | case PIPE_B: | |
5534 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5535 | pipe_config->fdi_lanes > 2) { | |
5536 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5537 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5538 | return false; | |
5539 | } | |
5540 | return true; | |
5541 | case PIPE_C: | |
1e833f40 | 5542 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
6e3c9717 | 5543 | pipe_B_crtc->config->fdi_lanes <= 2) { |
1857e1da DV |
5544 | if (pipe_config->fdi_lanes > 2) { |
5545 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5546 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5547 | return false; | |
5548 | } | |
5549 | } else { | |
5550 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5551 | return false; | |
5552 | } | |
5553 | return true; | |
5554 | default: | |
5555 | BUG(); | |
5556 | } | |
5557 | } | |
5558 | ||
e29c22c0 DV |
5559 | #define RETRY 1 |
5560 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5561 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5562 | { |
1857e1da | 5563 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5564 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
ff9a6750 | 5565 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5566 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5567 | |
e29c22c0 | 5568 | retry: |
877d48d5 DV |
5569 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5570 | * each output octet as 10 bits. The actual frequency | |
5571 | * is stored as a divider into a 100MHz clock, and the | |
5572 | * mode pixel clock is stored in units of 1KHz. | |
5573 | * Hence the bw of each lane in terms of the mode signal | |
5574 | * is: | |
5575 | */ | |
5576 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5577 | ||
241bfc38 | 5578 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5579 | |
2bd89a07 | 5580 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5581 | pipe_config->pipe_bpp); |
5582 | ||
5583 | pipe_config->fdi_lanes = lane; | |
5584 | ||
2bd89a07 | 5585 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5586 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5587 | |
e29c22c0 DV |
5588 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5589 | intel_crtc->pipe, pipe_config); | |
5590 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5591 | pipe_config->pipe_bpp -= 2*3; | |
5592 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5593 | pipe_config->pipe_bpp); | |
5594 | needs_recompute = true; | |
5595 | pipe_config->bw_constrained = true; | |
5596 | ||
5597 | goto retry; | |
5598 | } | |
5599 | ||
5600 | if (needs_recompute) | |
5601 | return RETRY; | |
5602 | ||
5603 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5604 | } |
5605 | ||
42db64ef | 5606 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5607 | struct intel_crtc_state *pipe_config) |
42db64ef | 5608 | { |
d330a953 | 5609 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5610 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5611 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5612 | } |
5613 | ||
a43f6e0f | 5614 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5615 | struct intel_crtc_state *pipe_config) |
79e53945 | 5616 | { |
a43f6e0f | 5617 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5618 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5619 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 5620 | |
ad3a4479 | 5621 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5622 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5623 | int clock_limit = |
5624 | dev_priv->display.get_display_clock_speed(dev); | |
5625 | ||
5626 | /* | |
5627 | * Enable pixel doubling when the dot clock | |
5628 | * is > 90% of the (display) core speed. | |
5629 | * | |
b397c96b VS |
5630 | * GDG double wide on either pipe, |
5631 | * otherwise pipe A only. | |
cf532bb2 | 5632 | */ |
b397c96b | 5633 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5634 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5635 | clock_limit *= 2; |
cf532bb2 | 5636 | pipe_config->double_wide = true; |
ad3a4479 VS |
5637 | } |
5638 | ||
241bfc38 | 5639 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5640 | return -EINVAL; |
2c07245f | 5641 | } |
89749350 | 5642 | |
1d1d0e27 VS |
5643 | /* |
5644 | * Pipe horizontal size must be even in: | |
5645 | * - DVO ganged mode | |
5646 | * - LVDS dual channel mode | |
5647 | * - Double wide pipe | |
5648 | */ | |
b4f2bf4c | 5649 | if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5650 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5651 | pipe_config->pipe_src_w &= ~1; | |
5652 | ||
8693a824 DL |
5653 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5654 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5655 | */ |
5656 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5657 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5658 | return -EINVAL; |
44f46b42 | 5659 | |
bd080ee5 | 5660 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5661 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5662 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5663 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5664 | * for lvds. */ | |
5665 | pipe_config->pipe_bpp = 8*3; | |
5666 | } | |
5667 | ||
f5adf94e | 5668 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5669 | hsw_compute_ips_config(crtc, pipe_config); |
5670 | ||
877d48d5 | 5671 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5672 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5673 | |
e29c22c0 | 5674 | return 0; |
79e53945 JB |
5675 | } |
5676 | ||
25eb05fc JB |
5677 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5678 | { | |
d197b7d3 | 5679 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5680 | u32 val; |
5681 | int divider; | |
5682 | ||
d49a340d VS |
5683 | /* FIXME: Punit isn't quite ready yet */ |
5684 | if (IS_CHERRYVIEW(dev)) | |
5685 | return 400000; | |
5686 | ||
6bcda4f0 VS |
5687 | if (dev_priv->hpll_freq == 0) |
5688 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5689 | ||
d197b7d3 VS |
5690 | mutex_lock(&dev_priv->dpio_lock); |
5691 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5692 | mutex_unlock(&dev_priv->dpio_lock); | |
5693 | ||
5694 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5695 | ||
7d007f40 VS |
5696 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5697 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5698 | "cdclk change in progress\n"); | |
5699 | ||
6bcda4f0 | 5700 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5701 | } |
5702 | ||
e70236a8 JB |
5703 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5704 | { | |
5705 | return 400000; | |
5706 | } | |
79e53945 | 5707 | |
e70236a8 | 5708 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5709 | { |
e70236a8 JB |
5710 | return 333000; |
5711 | } | |
79e53945 | 5712 | |
e70236a8 JB |
5713 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5714 | { | |
5715 | return 200000; | |
5716 | } | |
79e53945 | 5717 | |
257a7ffc DV |
5718 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5719 | { | |
5720 | u16 gcfgc = 0; | |
5721 | ||
5722 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5723 | ||
5724 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5725 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5726 | return 267000; | |
5727 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5728 | return 333000; | |
5729 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5730 | return 444000; | |
5731 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5732 | return 200000; | |
5733 | default: | |
5734 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5735 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5736 | return 133000; | |
5737 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5738 | return 167000; | |
5739 | } | |
5740 | } | |
5741 | ||
e70236a8 JB |
5742 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5743 | { | |
5744 | u16 gcfgc = 0; | |
79e53945 | 5745 | |
e70236a8 JB |
5746 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5747 | ||
5748 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5749 | return 133000; | |
5750 | else { | |
5751 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5752 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5753 | return 333000; | |
5754 | default: | |
5755 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5756 | return 190000; | |
79e53945 | 5757 | } |
e70236a8 JB |
5758 | } |
5759 | } | |
5760 | ||
5761 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5762 | { | |
5763 | return 266000; | |
5764 | } | |
5765 | ||
5766 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5767 | { | |
5768 | u16 hpllcc = 0; | |
5769 | /* Assume that the hardware is in the high speed state. This | |
5770 | * should be the default. | |
5771 | */ | |
5772 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5773 | case GC_CLOCK_133_200: | |
5774 | case GC_CLOCK_100_200: | |
5775 | return 200000; | |
5776 | case GC_CLOCK_166_250: | |
5777 | return 250000; | |
5778 | case GC_CLOCK_100_133: | |
79e53945 | 5779 | return 133000; |
e70236a8 | 5780 | } |
79e53945 | 5781 | |
e70236a8 JB |
5782 | /* Shouldn't happen */ |
5783 | return 0; | |
5784 | } | |
79e53945 | 5785 | |
e70236a8 JB |
5786 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5787 | { | |
5788 | return 133000; | |
79e53945 JB |
5789 | } |
5790 | ||
2c07245f | 5791 | static void |
a65851af | 5792 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5793 | { |
a65851af VS |
5794 | while (*num > DATA_LINK_M_N_MASK || |
5795 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5796 | *num >>= 1; |
5797 | *den >>= 1; | |
5798 | } | |
5799 | } | |
5800 | ||
a65851af VS |
5801 | static void compute_m_n(unsigned int m, unsigned int n, |
5802 | uint32_t *ret_m, uint32_t *ret_n) | |
5803 | { | |
5804 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5805 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5806 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5807 | } | |
5808 | ||
e69d0bc1 DV |
5809 | void |
5810 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5811 | int pixel_clock, int link_clock, | |
5812 | struct intel_link_m_n *m_n) | |
2c07245f | 5813 | { |
e69d0bc1 | 5814 | m_n->tu = 64; |
a65851af VS |
5815 | |
5816 | compute_m_n(bits_per_pixel * pixel_clock, | |
5817 | link_clock * nlanes * 8, | |
5818 | &m_n->gmch_m, &m_n->gmch_n); | |
5819 | ||
5820 | compute_m_n(pixel_clock, link_clock, | |
5821 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5822 | } |
5823 | ||
a7615030 CW |
5824 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5825 | { | |
d330a953 JN |
5826 | if (i915.panel_use_ssc >= 0) |
5827 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5828 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5829 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5830 | } |
5831 | ||
409ee761 | 5832 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5833 | { |
409ee761 | 5834 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5835 | struct drm_i915_private *dev_priv = dev->dev_private; |
5836 | int refclk; | |
5837 | ||
a0c4da24 | 5838 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5839 | refclk = 100000; |
d0737e1d | 5840 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5841 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5842 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5843 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5844 | } else if (!IS_GEN2(dev)) { |
5845 | refclk = 96000; | |
5846 | } else { | |
5847 | refclk = 48000; | |
5848 | } | |
5849 | ||
5850 | return refclk; | |
5851 | } | |
5852 | ||
7429e9d4 | 5853 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5854 | { |
7df00d7a | 5855 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5856 | } |
f47709a9 | 5857 | |
7429e9d4 DV |
5858 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5859 | { | |
5860 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5861 | } |
5862 | ||
f47709a9 | 5863 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 5864 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
5865 | intel_clock_t *reduced_clock) |
5866 | { | |
f47709a9 | 5867 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5868 | u32 fp, fp2 = 0; |
5869 | ||
5870 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 5871 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 5872 | if (reduced_clock) |
7429e9d4 | 5873 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5874 | } else { |
190f68c5 | 5875 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 5876 | if (reduced_clock) |
7429e9d4 | 5877 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5878 | } |
5879 | ||
190f68c5 | 5880 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 5881 | |
f47709a9 | 5882 | crtc->lowfreq_avail = false; |
e1f234bd | 5883 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
d330a953 | 5884 | reduced_clock && i915.powersave) { |
190f68c5 | 5885 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 5886 | crtc->lowfreq_avail = true; |
a7516a05 | 5887 | } else { |
190f68c5 | 5888 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5889 | } |
5890 | } | |
5891 | ||
5e69f97f CML |
5892 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5893 | pipe) | |
89b667f8 JB |
5894 | { |
5895 | u32 reg_val; | |
5896 | ||
5897 | /* | |
5898 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5899 | * and set it to a reasonable value instead. | |
5900 | */ | |
ab3c759a | 5901 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5902 | reg_val &= 0xffffff00; |
5903 | reg_val |= 0x00000030; | |
ab3c759a | 5904 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5905 | |
ab3c759a | 5906 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5907 | reg_val &= 0x8cffffff; |
5908 | reg_val = 0x8c000000; | |
ab3c759a | 5909 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5910 | |
ab3c759a | 5911 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5912 | reg_val &= 0xffffff00; |
ab3c759a | 5913 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5914 | |
ab3c759a | 5915 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5916 | reg_val &= 0x00ffffff; |
5917 | reg_val |= 0xb0000000; | |
ab3c759a | 5918 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5919 | } |
5920 | ||
b551842d DV |
5921 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5922 | struct intel_link_m_n *m_n) | |
5923 | { | |
5924 | struct drm_device *dev = crtc->base.dev; | |
5925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5926 | int pipe = crtc->pipe; | |
5927 | ||
e3b95f1e DV |
5928 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5929 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5930 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5931 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5932 | } |
5933 | ||
5934 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5935 | struct intel_link_m_n *m_n, |
5936 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5937 | { |
5938 | struct drm_device *dev = crtc->base.dev; | |
5939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5940 | int pipe = crtc->pipe; | |
6e3c9717 | 5941 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
5942 | |
5943 | if (INTEL_INFO(dev)->gen >= 5) { | |
5944 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5945 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5946 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5947 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5948 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5949 | * for gen < 8) and if DRRS is supported (to make sure the | |
5950 | * registers are not unnecessarily accessed). | |
5951 | */ | |
44395bfe | 5952 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 5953 | crtc->config->has_drrs) { |
f769cd24 VK |
5954 | I915_WRITE(PIPE_DATA_M2(transcoder), |
5955 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5956 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5957 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5958 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5959 | } | |
b551842d | 5960 | } else { |
e3b95f1e DV |
5961 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5962 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5963 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5964 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5965 | } |
5966 | } | |
5967 | ||
fe3cd48d | 5968 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 5969 | { |
fe3cd48d R |
5970 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
5971 | ||
5972 | if (m_n == M1_N1) { | |
5973 | dp_m_n = &crtc->config->dp_m_n; | |
5974 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
5975 | } else if (m_n == M2_N2) { | |
5976 | ||
5977 | /* | |
5978 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
5979 | * needs to be programmed into M1_N1. | |
5980 | */ | |
5981 | dp_m_n = &crtc->config->dp_m2_n2; | |
5982 | } else { | |
5983 | DRM_ERROR("Unsupported divider value\n"); | |
5984 | return; | |
5985 | } | |
5986 | ||
6e3c9717 ACO |
5987 | if (crtc->config->has_pch_encoder) |
5988 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 5989 | else |
fe3cd48d | 5990 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
5991 | } |
5992 | ||
d288f65f | 5993 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 5994 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
5995 | { |
5996 | u32 dpll, dpll_md; | |
5997 | ||
5998 | /* | |
5999 | * Enable DPIO clock input. We should never disable the reference | |
6000 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6001 | * on it. | |
6002 | */ | |
6003 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6004 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6005 | /* We should never disable this, set it here for state tracking */ | |
6006 | if (crtc->pipe == PIPE_B) | |
6007 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6008 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6009 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6010 | |
d288f65f | 6011 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6012 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6013 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6014 | } |
6015 | ||
d288f65f | 6016 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6017 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6018 | { |
f47709a9 | 6019 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6020 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6021 | int pipe = crtc->pipe; |
bdd4b6a6 | 6022 | u32 mdiv; |
a0c4da24 | 6023 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6024 | u32 coreclk, reg_val; |
a0c4da24 | 6025 | |
09153000 DV |
6026 | mutex_lock(&dev_priv->dpio_lock); |
6027 | ||
d288f65f VS |
6028 | bestn = pipe_config->dpll.n; |
6029 | bestm1 = pipe_config->dpll.m1; | |
6030 | bestm2 = pipe_config->dpll.m2; | |
6031 | bestp1 = pipe_config->dpll.p1; | |
6032 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6033 | |
89b667f8 JB |
6034 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6035 | ||
6036 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6037 | if (pipe == PIPE_B) |
5e69f97f | 6038 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6039 | |
6040 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6041 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6042 | |
6043 | /* Disable target IRef on PLL */ | |
ab3c759a | 6044 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6045 | reg_val &= 0x00ffffff; |
ab3c759a | 6046 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6047 | |
6048 | /* Disable fast lock */ | |
ab3c759a | 6049 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6050 | |
6051 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6052 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6053 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6054 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6055 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6056 | |
6057 | /* | |
6058 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6059 | * but we don't support that). | |
6060 | * Note: don't use the DAC post divider as it seems unstable. | |
6061 | */ | |
6062 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6063 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6064 | |
a0c4da24 | 6065 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6066 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6067 | |
89b667f8 | 6068 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6069 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6070 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6071 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6072 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6073 | 0x009f0003); |
89b667f8 | 6074 | else |
ab3c759a | 6075 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6076 | 0x00d0000f); |
6077 | ||
681a8504 | 6078 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6079 | /* Use SSC source */ |
bdd4b6a6 | 6080 | if (pipe == PIPE_A) |
ab3c759a | 6081 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6082 | 0x0df40000); |
6083 | else | |
ab3c759a | 6084 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6085 | 0x0df70000); |
6086 | } else { /* HDMI or VGA */ | |
6087 | /* Use bend source */ | |
bdd4b6a6 | 6088 | if (pipe == PIPE_A) |
ab3c759a | 6089 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6090 | 0x0df70000); |
6091 | else | |
ab3c759a | 6092 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6093 | 0x0df40000); |
6094 | } | |
a0c4da24 | 6095 | |
ab3c759a | 6096 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6097 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6098 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6099 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6100 | coreclk |= 0x01000000; |
ab3c759a | 6101 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6102 | |
ab3c759a | 6103 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6104 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6105 | } |
6106 | ||
d288f65f | 6107 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6108 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6109 | { |
d288f65f | 6110 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6111 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6112 | DPLL_VCO_ENABLE; | |
6113 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6114 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6115 | |
d288f65f VS |
6116 | pipe_config->dpll_hw_state.dpll_md = |
6117 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6118 | } |
6119 | ||
d288f65f | 6120 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6121 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6122 | { |
6123 | struct drm_device *dev = crtc->base.dev; | |
6124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6125 | int pipe = crtc->pipe; | |
6126 | int dpll_reg = DPLL(crtc->pipe); | |
6127 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 6128 | u32 loopfilter, intcoeff; |
9d556c99 CML |
6129 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
6130 | int refclk; | |
6131 | ||
d288f65f VS |
6132 | bestn = pipe_config->dpll.n; |
6133 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6134 | bestm1 = pipe_config->dpll.m1; | |
6135 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6136 | bestp1 = pipe_config->dpll.p1; | |
6137 | bestp2 = pipe_config->dpll.p2; | |
9d556c99 CML |
6138 | |
6139 | /* | |
6140 | * Enable Refclk and SSC | |
6141 | */ | |
a11b0703 | 6142 | I915_WRITE(dpll_reg, |
d288f65f | 6143 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6144 | |
6145 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6146 | |
9d556c99 CML |
6147 | /* p1 and p2 divider */ |
6148 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6149 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6150 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6151 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6152 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6153 | ||
6154 | /* Feedback post-divider - m2 */ | |
6155 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6156 | ||
6157 | /* Feedback refclk divider - n and m1 */ | |
6158 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6159 | DPIO_CHV_M1_DIV_BY_2 | | |
6160 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6161 | ||
6162 | /* M2 fraction division */ | |
6163 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
6164 | ||
6165 | /* M2 fraction division enable */ | |
6166 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
6167 | DPIO_CHV_FRAC_DIV_EN | | |
6168 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
6169 | ||
6170 | /* Loop filter */ | |
409ee761 | 6171 | refclk = i9xx_get_refclk(crtc, 0); |
9d556c99 CML |
6172 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
6173 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
6174 | if (refclk == 100000) | |
6175 | intcoeff = 11; | |
6176 | else if (refclk == 38400) | |
6177 | intcoeff = 10; | |
6178 | else | |
6179 | intcoeff = 9; | |
6180 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
6181 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
6182 | ||
6183 | /* AFC Recal */ | |
6184 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6185 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6186 | DPIO_AFC_RECAL); | |
6187 | ||
6188 | mutex_unlock(&dev_priv->dpio_lock); | |
6189 | } | |
6190 | ||
d288f65f VS |
6191 | /** |
6192 | * vlv_force_pll_on - forcibly enable just the PLL | |
6193 | * @dev_priv: i915 private structure | |
6194 | * @pipe: pipe PLL to enable | |
6195 | * @dpll: PLL configuration | |
6196 | * | |
6197 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6198 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6199 | * be enabled. | |
6200 | */ | |
6201 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6202 | const struct dpll *dpll) | |
6203 | { | |
6204 | struct intel_crtc *crtc = | |
6205 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6206 | struct intel_crtc_state pipe_config = { |
d288f65f VS |
6207 | .pixel_multiplier = 1, |
6208 | .dpll = *dpll, | |
6209 | }; | |
6210 | ||
6211 | if (IS_CHERRYVIEW(dev)) { | |
6212 | chv_update_pll(crtc, &pipe_config); | |
6213 | chv_prepare_pll(crtc, &pipe_config); | |
6214 | chv_enable_pll(crtc, &pipe_config); | |
6215 | } else { | |
6216 | vlv_update_pll(crtc, &pipe_config); | |
6217 | vlv_prepare_pll(crtc, &pipe_config); | |
6218 | vlv_enable_pll(crtc, &pipe_config); | |
6219 | } | |
6220 | } | |
6221 | ||
6222 | /** | |
6223 | * vlv_force_pll_off - forcibly disable just the PLL | |
6224 | * @dev_priv: i915 private structure | |
6225 | * @pipe: pipe PLL to disable | |
6226 | * | |
6227 | * Disable the PLL for @pipe. To be used in cases where we need | |
6228 | * the PLL enabled even when @pipe is not going to be enabled. | |
6229 | */ | |
6230 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6231 | { | |
6232 | if (IS_CHERRYVIEW(dev)) | |
6233 | chv_disable_pll(to_i915(dev), pipe); | |
6234 | else | |
6235 | vlv_disable_pll(to_i915(dev), pipe); | |
6236 | } | |
6237 | ||
f47709a9 | 6238 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6239 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6240 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6241 | int num_connectors) |
6242 | { | |
f47709a9 | 6243 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6244 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6245 | u32 dpll; |
6246 | bool is_sdvo; | |
190f68c5 | 6247 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6248 | |
190f68c5 | 6249 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6250 | |
d0737e1d ACO |
6251 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6252 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6253 | |
6254 | dpll = DPLL_VGA_MODE_DIS; | |
6255 | ||
d0737e1d | 6256 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6257 | dpll |= DPLLB_MODE_LVDS; |
6258 | else | |
6259 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6260 | |
ef1b460d | 6261 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6262 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6263 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6264 | } |
198a037f DV |
6265 | |
6266 | if (is_sdvo) | |
4a33e48d | 6267 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6268 | |
190f68c5 | 6269 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6270 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6271 | |
6272 | /* compute bitmask from p1 value */ | |
6273 | if (IS_PINEVIEW(dev)) | |
6274 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6275 | else { | |
6276 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6277 | if (IS_G4X(dev) && reduced_clock) | |
6278 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6279 | } | |
6280 | switch (clock->p2) { | |
6281 | case 5: | |
6282 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6283 | break; | |
6284 | case 7: | |
6285 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6286 | break; | |
6287 | case 10: | |
6288 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6289 | break; | |
6290 | case 14: | |
6291 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6292 | break; | |
6293 | } | |
6294 | if (INTEL_INFO(dev)->gen >= 4) | |
6295 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6296 | ||
190f68c5 | 6297 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6298 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6299 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6300 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6301 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6302 | else | |
6303 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6304 | ||
6305 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6306 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6307 | |
eb1cbe48 | 6308 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6309 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6310 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6311 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6312 | } |
6313 | } | |
6314 | ||
f47709a9 | 6315 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6316 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6317 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6318 | int num_connectors) |
6319 | { | |
f47709a9 | 6320 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6321 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6322 | u32 dpll; |
190f68c5 | 6323 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6324 | |
190f68c5 | 6325 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6326 | |
eb1cbe48 DV |
6327 | dpll = DPLL_VGA_MODE_DIS; |
6328 | ||
d0737e1d | 6329 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6330 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6331 | } else { | |
6332 | if (clock->p1 == 2) | |
6333 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6334 | else | |
6335 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6336 | if (clock->p2 == 4) | |
6337 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6338 | } | |
6339 | ||
d0737e1d | 6340 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6341 | dpll |= DPLL_DVO_2X_MODE; |
6342 | ||
d0737e1d | 6343 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6344 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6345 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6346 | else | |
6347 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6348 | ||
6349 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6350 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6351 | } |
6352 | ||
8a654f3b | 6353 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6354 | { |
6355 | struct drm_device *dev = intel_crtc->base.dev; | |
6356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6357 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6358 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6359 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6360 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6361 | uint32_t crtc_vtotal, crtc_vblank_end; |
6362 | int vsyncshift = 0; | |
4d8a62ea DV |
6363 | |
6364 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6365 | * the hw state checker will get angry at the mismatch. */ | |
6366 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6367 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6368 | |
609aeaca | 6369 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6370 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6371 | crtc_vtotal -= 1; |
6372 | crtc_vblank_end -= 1; | |
609aeaca | 6373 | |
409ee761 | 6374 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6375 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6376 | else | |
6377 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6378 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6379 | if (vsyncshift < 0) |
6380 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6381 | } |
6382 | ||
6383 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6384 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6385 | |
fe2b8f9d | 6386 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6387 | (adjusted_mode->crtc_hdisplay - 1) | |
6388 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6389 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6390 | (adjusted_mode->crtc_hblank_start - 1) | |
6391 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6392 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6393 | (adjusted_mode->crtc_hsync_start - 1) | |
6394 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6395 | ||
fe2b8f9d | 6396 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6397 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6398 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6399 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6400 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6401 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6402 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6403 | (adjusted_mode->crtc_vsync_start - 1) | |
6404 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6405 | ||
b5e508d4 PZ |
6406 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6407 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6408 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6409 | * bits. */ | |
6410 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6411 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6412 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6413 | ||
b0e77b9c PZ |
6414 | /* pipesrc controls the size that is scaled from, which should |
6415 | * always be the user's requested size. | |
6416 | */ | |
6417 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6418 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6419 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6420 | } |
6421 | ||
1bd1bd80 | 6422 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6423 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6424 | { |
6425 | struct drm_device *dev = crtc->base.dev; | |
6426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6427 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6428 | uint32_t tmp; | |
6429 | ||
6430 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6431 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6432 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6433 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6434 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6435 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6436 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6437 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6438 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6439 | |
6440 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6441 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6442 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6443 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6444 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6445 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6446 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6447 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6448 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6449 | |
6450 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6451 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6452 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6453 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6454 | } |
6455 | ||
6456 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6457 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6458 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6459 | ||
2d112de7 ACO |
6460 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6461 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6462 | } |
6463 | ||
f6a83288 | 6464 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6465 | struct intel_crtc_state *pipe_config) |
babea61d | 6466 | { |
2d112de7 ACO |
6467 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6468 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6469 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6470 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6471 | |
2d112de7 ACO |
6472 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6473 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6474 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6475 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6476 | |
2d112de7 | 6477 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6478 | |
2d112de7 ACO |
6479 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6480 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6481 | } |
6482 | ||
84b046f3 DV |
6483 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6484 | { | |
6485 | struct drm_device *dev = intel_crtc->base.dev; | |
6486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6487 | uint32_t pipeconf; | |
6488 | ||
9f11a9e4 | 6489 | pipeconf = 0; |
84b046f3 | 6490 | |
b6b5d049 VS |
6491 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6492 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6493 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6494 | |
6e3c9717 | 6495 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6496 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6497 | |
ff9ce46e DV |
6498 | /* only g4x and later have fancy bpc/dither controls */ |
6499 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6500 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6501 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6502 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6503 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6504 | |
6e3c9717 | 6505 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6506 | case 18: |
6507 | pipeconf |= PIPECONF_6BPC; | |
6508 | break; | |
6509 | case 24: | |
6510 | pipeconf |= PIPECONF_8BPC; | |
6511 | break; | |
6512 | case 30: | |
6513 | pipeconf |= PIPECONF_10BPC; | |
6514 | break; | |
6515 | default: | |
6516 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6517 | BUG(); | |
84b046f3 DV |
6518 | } |
6519 | } | |
6520 | ||
6521 | if (HAS_PIPE_CXSR(dev)) { | |
6522 | if (intel_crtc->lowfreq_avail) { | |
6523 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6524 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6525 | } else { | |
6526 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6527 | } |
6528 | } | |
6529 | ||
6e3c9717 | 6530 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6531 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6532 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6533 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6534 | else | |
6535 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6536 | } else | |
84b046f3 DV |
6537 | pipeconf |= PIPECONF_PROGRESSIVE; |
6538 | ||
6e3c9717 | 6539 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6540 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6541 | |
84b046f3 DV |
6542 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6543 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6544 | } | |
6545 | ||
190f68c5 ACO |
6546 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6547 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6548 | { |
c7653199 | 6549 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6550 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6551 | int refclk, num_connectors = 0; |
652c393a | 6552 | intel_clock_t clock, reduced_clock; |
a16af721 | 6553 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6554 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6555 | struct intel_encoder *encoder; |
d4906093 | 6556 | const intel_limit_t *limit; |
79e53945 | 6557 | |
d0737e1d ACO |
6558 | for_each_intel_encoder(dev, encoder) { |
6559 | if (encoder->new_crtc != crtc) | |
6560 | continue; | |
6561 | ||
5eddb70b | 6562 | switch (encoder->type) { |
79e53945 JB |
6563 | case INTEL_OUTPUT_LVDS: |
6564 | is_lvds = true; | |
6565 | break; | |
e9fd1c02 JN |
6566 | case INTEL_OUTPUT_DSI: |
6567 | is_dsi = true; | |
6568 | break; | |
6847d71b PZ |
6569 | default: |
6570 | break; | |
79e53945 | 6571 | } |
43565a06 | 6572 | |
c751ce4f | 6573 | num_connectors++; |
79e53945 JB |
6574 | } |
6575 | ||
f2335330 | 6576 | if (is_dsi) |
5b18e57c | 6577 | return 0; |
f2335330 | 6578 | |
190f68c5 | 6579 | if (!crtc_state->clock_set) { |
409ee761 | 6580 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6581 | |
e9fd1c02 JN |
6582 | /* |
6583 | * Returns a set of divisors for the desired target clock with | |
6584 | * the given refclk, or FALSE. The returned values represent | |
6585 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6586 | * 2) / p1 / p2. | |
6587 | */ | |
409ee761 | 6588 | limit = intel_limit(crtc, refclk); |
c7653199 | 6589 | ok = dev_priv->display.find_dpll(limit, crtc, |
190f68c5 | 6590 | crtc_state->port_clock, |
e9fd1c02 | 6591 | refclk, NULL, &clock); |
f2335330 | 6592 | if (!ok) { |
e9fd1c02 JN |
6593 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6594 | return -EINVAL; | |
6595 | } | |
79e53945 | 6596 | |
f2335330 JN |
6597 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6598 | /* | |
6599 | * Ensure we match the reduced clock's P to the target | |
6600 | * clock. If the clocks don't match, we can't switch | |
6601 | * the display clock by using the FP0/FP1. In such case | |
6602 | * we will disable the LVDS downclock feature. | |
6603 | */ | |
6604 | has_reduced_clock = | |
c7653199 | 6605 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6606 | dev_priv->lvds_downclock, |
6607 | refclk, &clock, | |
6608 | &reduced_clock); | |
6609 | } | |
6610 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
6611 | crtc_state->dpll.n = clock.n; |
6612 | crtc_state->dpll.m1 = clock.m1; | |
6613 | crtc_state->dpll.m2 = clock.m2; | |
6614 | crtc_state->dpll.p1 = clock.p1; | |
6615 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 6616 | } |
7026d4ac | 6617 | |
e9fd1c02 | 6618 | if (IS_GEN2(dev)) { |
190f68c5 | 6619 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
6620 | has_reduced_clock ? &reduced_clock : NULL, |
6621 | num_connectors); | |
9d556c99 | 6622 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 6623 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6624 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 6625 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6626 | } else { |
190f68c5 | 6627 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 6628 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6629 | num_connectors); |
e9fd1c02 | 6630 | } |
79e53945 | 6631 | |
c8f7a0db | 6632 | return 0; |
f564048e EA |
6633 | } |
6634 | ||
2fa2fe9a | 6635 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 6636 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
6637 | { |
6638 | struct drm_device *dev = crtc->base.dev; | |
6639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6640 | uint32_t tmp; | |
6641 | ||
dc9e7dec VS |
6642 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6643 | return; | |
6644 | ||
2fa2fe9a | 6645 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6646 | if (!(tmp & PFIT_ENABLE)) |
6647 | return; | |
2fa2fe9a | 6648 | |
06922821 | 6649 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6650 | if (INTEL_INFO(dev)->gen < 4) { |
6651 | if (crtc->pipe != PIPE_B) | |
6652 | return; | |
2fa2fe9a DV |
6653 | } else { |
6654 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6655 | return; | |
6656 | } | |
6657 | ||
06922821 | 6658 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6659 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6660 | if (INTEL_INFO(dev)->gen < 5) | |
6661 | pipe_config->gmch_pfit.lvds_border_bits = | |
6662 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6663 | } | |
6664 | ||
acbec814 | 6665 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6666 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
6667 | { |
6668 | struct drm_device *dev = crtc->base.dev; | |
6669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6670 | int pipe = pipe_config->cpu_transcoder; | |
6671 | intel_clock_t clock; | |
6672 | u32 mdiv; | |
662c6ecb | 6673 | int refclk = 100000; |
acbec814 | 6674 | |
f573de5a SK |
6675 | /* In case of MIPI DPLL will not even be used */ |
6676 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6677 | return; | |
6678 | ||
acbec814 | 6679 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6680 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6681 | mutex_unlock(&dev_priv->dpio_lock); |
6682 | ||
6683 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6684 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6685 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6686 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6687 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6688 | ||
f646628b | 6689 | vlv_clock(refclk, &clock); |
acbec814 | 6690 | |
f646628b VS |
6691 | /* clock.dot is the fast clock */ |
6692 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6693 | } |
6694 | ||
5724dbd1 DL |
6695 | static void |
6696 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
6697 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
6698 | { |
6699 | struct drm_device *dev = crtc->base.dev; | |
6700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6701 | u32 val, base, offset; | |
6702 | int pipe = crtc->pipe, plane = crtc->plane; | |
6703 | int fourcc, pixel_format; | |
6704 | int aligned_height; | |
b113d5ee | 6705 | struct drm_framebuffer *fb; |
1b842c89 | 6706 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 6707 | |
42a7b088 DL |
6708 | val = I915_READ(DSPCNTR(plane)); |
6709 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
6710 | return; | |
6711 | ||
d9806c9f | 6712 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 6713 | if (!intel_fb) { |
1ad292b5 JB |
6714 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6715 | return; | |
6716 | } | |
6717 | ||
1b842c89 DL |
6718 | fb = &intel_fb->base; |
6719 | ||
18c5247e DV |
6720 | if (INTEL_INFO(dev)->gen >= 4) { |
6721 | if (val & DISPPLANE_TILED) { | |
49af449b | 6722 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
6723 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
6724 | } | |
6725 | } | |
1ad292b5 JB |
6726 | |
6727 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 6728 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
6729 | fb->pixel_format = fourcc; |
6730 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
6731 | |
6732 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 6733 | if (plane_config->tiling) |
1ad292b5 JB |
6734 | offset = I915_READ(DSPTILEOFF(plane)); |
6735 | else | |
6736 | offset = I915_READ(DSPLINOFF(plane)); | |
6737 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6738 | } else { | |
6739 | base = I915_READ(DSPADDR(plane)); | |
6740 | } | |
6741 | plane_config->base = base; | |
6742 | ||
6743 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
6744 | fb->width = ((val >> 16) & 0xfff) + 1; |
6745 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6746 | |
6747 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 6748 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6749 | |
b113d5ee | 6750 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
6751 | fb->pixel_format, |
6752 | fb->modifier[0]); | |
1ad292b5 | 6753 | |
b113d5ee | 6754 | plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); |
1ad292b5 | 6755 | |
2844a921 DL |
6756 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
6757 | pipe_name(pipe), plane, fb->width, fb->height, | |
6758 | fb->bits_per_pixel, base, fb->pitches[0], | |
6759 | plane_config->size); | |
1ad292b5 | 6760 | |
2d14030b | 6761 | plane_config->fb = intel_fb; |
1ad292b5 JB |
6762 | } |
6763 | ||
70b23a98 | 6764 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6765 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
6766 | { |
6767 | struct drm_device *dev = crtc->base.dev; | |
6768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6769 | int pipe = pipe_config->cpu_transcoder; | |
6770 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6771 | intel_clock_t clock; | |
6772 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6773 | int refclk = 100000; | |
6774 | ||
6775 | mutex_lock(&dev_priv->dpio_lock); | |
6776 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6777 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6778 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6779 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6780 | mutex_unlock(&dev_priv->dpio_lock); | |
6781 | ||
6782 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6783 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6784 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6785 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6786 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6787 | ||
6788 | chv_clock(refclk, &clock); | |
6789 | ||
6790 | /* clock.dot is the fast clock */ | |
6791 | pipe_config->port_clock = clock.dot / 5; | |
6792 | } | |
6793 | ||
0e8ffe1b | 6794 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 6795 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
6796 | { |
6797 | struct drm_device *dev = crtc->base.dev; | |
6798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6799 | uint32_t tmp; | |
6800 | ||
f458ebbc DV |
6801 | if (!intel_display_power_is_enabled(dev_priv, |
6802 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6803 | return false; |
6804 | ||
e143a21c | 6805 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6806 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6807 | |
0e8ffe1b DV |
6808 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6809 | if (!(tmp & PIPECONF_ENABLE)) | |
6810 | return false; | |
6811 | ||
42571aef VS |
6812 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6813 | switch (tmp & PIPECONF_BPC_MASK) { | |
6814 | case PIPECONF_6BPC: | |
6815 | pipe_config->pipe_bpp = 18; | |
6816 | break; | |
6817 | case PIPECONF_8BPC: | |
6818 | pipe_config->pipe_bpp = 24; | |
6819 | break; | |
6820 | case PIPECONF_10BPC: | |
6821 | pipe_config->pipe_bpp = 30; | |
6822 | break; | |
6823 | default: | |
6824 | break; | |
6825 | } | |
6826 | } | |
6827 | ||
b5a9fa09 DV |
6828 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6829 | pipe_config->limited_color_range = true; | |
6830 | ||
282740f7 VS |
6831 | if (INTEL_INFO(dev)->gen < 4) |
6832 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6833 | ||
1bd1bd80 DV |
6834 | intel_get_pipe_timings(crtc, pipe_config); |
6835 | ||
2fa2fe9a DV |
6836 | i9xx_get_pfit_config(crtc, pipe_config); |
6837 | ||
6c49f241 DV |
6838 | if (INTEL_INFO(dev)->gen >= 4) { |
6839 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6840 | pipe_config->pixel_multiplier = | |
6841 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6842 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6843 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6844 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6845 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6846 | pipe_config->pixel_multiplier = | |
6847 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6848 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6849 | } else { | |
6850 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6851 | * port and will be fixed up in the encoder->get_config | |
6852 | * function. */ | |
6853 | pipe_config->pixel_multiplier = 1; | |
6854 | } | |
8bcc2795 DV |
6855 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6856 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6857 | /* |
6858 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6859 | * on 830. Filter it out here so that we don't | |
6860 | * report errors due to that. | |
6861 | */ | |
6862 | if (IS_I830(dev)) | |
6863 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6864 | ||
8bcc2795 DV |
6865 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6866 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6867 | } else { |
6868 | /* Mask out read-only status bits. */ | |
6869 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6870 | DPLL_PORTC_READY_MASK | | |
6871 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6872 | } |
6c49f241 | 6873 | |
70b23a98 VS |
6874 | if (IS_CHERRYVIEW(dev)) |
6875 | chv_crtc_clock_get(crtc, pipe_config); | |
6876 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6877 | vlv_crtc_clock_get(crtc, pipe_config); |
6878 | else | |
6879 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6880 | |
0e8ffe1b DV |
6881 | return true; |
6882 | } | |
6883 | ||
dde86e2d | 6884 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6885 | { |
6886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6887 | struct intel_encoder *encoder; |
74cfd7ac | 6888 | u32 val, final; |
13d83a67 | 6889 | bool has_lvds = false; |
199e5d79 | 6890 | bool has_cpu_edp = false; |
199e5d79 | 6891 | bool has_panel = false; |
99eb6a01 KP |
6892 | bool has_ck505 = false; |
6893 | bool can_ssc = false; | |
13d83a67 JB |
6894 | |
6895 | /* We need to take the global config into account */ | |
b2784e15 | 6896 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6897 | switch (encoder->type) { |
6898 | case INTEL_OUTPUT_LVDS: | |
6899 | has_panel = true; | |
6900 | has_lvds = true; | |
6901 | break; | |
6902 | case INTEL_OUTPUT_EDP: | |
6903 | has_panel = true; | |
2de6905f | 6904 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6905 | has_cpu_edp = true; |
6906 | break; | |
6847d71b PZ |
6907 | default: |
6908 | break; | |
13d83a67 JB |
6909 | } |
6910 | } | |
6911 | ||
99eb6a01 | 6912 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6913 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6914 | can_ssc = has_ck505; |
6915 | } else { | |
6916 | has_ck505 = false; | |
6917 | can_ssc = true; | |
6918 | } | |
6919 | ||
2de6905f ID |
6920 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6921 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6922 | |
6923 | /* Ironlake: try to setup display ref clock before DPLL | |
6924 | * enabling. This is only under driver's control after | |
6925 | * PCH B stepping, previous chipset stepping should be | |
6926 | * ignoring this setting. | |
6927 | */ | |
74cfd7ac CW |
6928 | val = I915_READ(PCH_DREF_CONTROL); |
6929 | ||
6930 | /* As we must carefully and slowly disable/enable each source in turn, | |
6931 | * compute the final state we want first and check if we need to | |
6932 | * make any changes at all. | |
6933 | */ | |
6934 | final = val; | |
6935 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6936 | if (has_ck505) | |
6937 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6938 | else | |
6939 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6940 | ||
6941 | final &= ~DREF_SSC_SOURCE_MASK; | |
6942 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6943 | final &= ~DREF_SSC1_ENABLE; | |
6944 | ||
6945 | if (has_panel) { | |
6946 | final |= DREF_SSC_SOURCE_ENABLE; | |
6947 | ||
6948 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6949 | final |= DREF_SSC1_ENABLE; | |
6950 | ||
6951 | if (has_cpu_edp) { | |
6952 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6953 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6954 | else | |
6955 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6956 | } else | |
6957 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6958 | } else { | |
6959 | final |= DREF_SSC_SOURCE_DISABLE; | |
6960 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6961 | } | |
6962 | ||
6963 | if (final == val) | |
6964 | return; | |
6965 | ||
13d83a67 | 6966 | /* Always enable nonspread source */ |
74cfd7ac | 6967 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6968 | |
99eb6a01 | 6969 | if (has_ck505) |
74cfd7ac | 6970 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6971 | else |
74cfd7ac | 6972 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6973 | |
199e5d79 | 6974 | if (has_panel) { |
74cfd7ac CW |
6975 | val &= ~DREF_SSC_SOURCE_MASK; |
6976 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6977 | |
199e5d79 | 6978 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6979 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6980 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6981 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6982 | } else |
74cfd7ac | 6983 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6984 | |
6985 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6986 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6987 | POSTING_READ(PCH_DREF_CONTROL); |
6988 | udelay(200); | |
6989 | ||
74cfd7ac | 6990 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6991 | |
6992 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6993 | if (has_cpu_edp) { |
99eb6a01 | 6994 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6995 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6996 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6997 | } else |
74cfd7ac | 6998 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6999 | } else |
74cfd7ac | 7000 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7001 | |
74cfd7ac | 7002 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7003 | POSTING_READ(PCH_DREF_CONTROL); |
7004 | udelay(200); | |
7005 | } else { | |
7006 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7007 | ||
74cfd7ac | 7008 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7009 | |
7010 | /* Turn off CPU output */ | |
74cfd7ac | 7011 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7012 | |
74cfd7ac | 7013 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7014 | POSTING_READ(PCH_DREF_CONTROL); |
7015 | udelay(200); | |
7016 | ||
7017 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7018 | val &= ~DREF_SSC_SOURCE_MASK; |
7019 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7020 | |
7021 | /* Turn off SSC1 */ | |
74cfd7ac | 7022 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7023 | |
74cfd7ac | 7024 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7025 | POSTING_READ(PCH_DREF_CONTROL); |
7026 | udelay(200); | |
7027 | } | |
74cfd7ac CW |
7028 | |
7029 | BUG_ON(val != final); | |
13d83a67 JB |
7030 | } |
7031 | ||
f31f2d55 | 7032 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7033 | { |
f31f2d55 | 7034 | uint32_t tmp; |
dde86e2d | 7035 | |
0ff066a9 PZ |
7036 | tmp = I915_READ(SOUTH_CHICKEN2); |
7037 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7038 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7039 | |
0ff066a9 PZ |
7040 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7041 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7042 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7043 | |
0ff066a9 PZ |
7044 | tmp = I915_READ(SOUTH_CHICKEN2); |
7045 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7046 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7047 | |
0ff066a9 PZ |
7048 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7049 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7050 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7051 | } |
7052 | ||
7053 | /* WaMPhyProgramming:hsw */ | |
7054 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7055 | { | |
7056 | uint32_t tmp; | |
dde86e2d PZ |
7057 | |
7058 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7059 | tmp &= ~(0xFF << 24); | |
7060 | tmp |= (0x12 << 24); | |
7061 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7062 | ||
dde86e2d PZ |
7063 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7064 | tmp |= (1 << 11); | |
7065 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7066 | ||
7067 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7068 | tmp |= (1 << 11); | |
7069 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7070 | ||
dde86e2d PZ |
7071 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7072 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7073 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7074 | ||
7075 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7076 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7077 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7078 | ||
0ff066a9 PZ |
7079 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7080 | tmp &= ~(7 << 13); | |
7081 | tmp |= (5 << 13); | |
7082 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7083 | |
0ff066a9 PZ |
7084 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7085 | tmp &= ~(7 << 13); | |
7086 | tmp |= (5 << 13); | |
7087 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7088 | |
7089 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7090 | tmp &= ~0xFF; | |
7091 | tmp |= 0x1C; | |
7092 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7093 | ||
7094 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7095 | tmp &= ~0xFF; | |
7096 | tmp |= 0x1C; | |
7097 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7098 | ||
7099 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7100 | tmp &= ~(0xFF << 16); | |
7101 | tmp |= (0x1C << 16); | |
7102 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7103 | ||
7104 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7105 | tmp &= ~(0xFF << 16); | |
7106 | tmp |= (0x1C << 16); | |
7107 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7108 | ||
0ff066a9 PZ |
7109 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7110 | tmp |= (1 << 27); | |
7111 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7112 | |
0ff066a9 PZ |
7113 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7114 | tmp |= (1 << 27); | |
7115 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7116 | |
0ff066a9 PZ |
7117 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7118 | tmp &= ~(0xF << 28); | |
7119 | tmp |= (4 << 28); | |
7120 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7121 | |
0ff066a9 PZ |
7122 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7123 | tmp &= ~(0xF << 28); | |
7124 | tmp |= (4 << 28); | |
7125 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7126 | } |
7127 | ||
2fa86a1f PZ |
7128 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7129 | * Programming" based on the parameters passed: | |
7130 | * - Sequence to enable CLKOUT_DP | |
7131 | * - Sequence to enable CLKOUT_DP without spread | |
7132 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7133 | */ | |
7134 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7135 | bool with_fdi) | |
f31f2d55 PZ |
7136 | { |
7137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7138 | uint32_t reg, tmp; |
7139 | ||
7140 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7141 | with_spread = true; | |
7142 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7143 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7144 | with_fdi = false; | |
f31f2d55 PZ |
7145 | |
7146 | mutex_lock(&dev_priv->dpio_lock); | |
7147 | ||
7148 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7149 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7150 | tmp |= SBI_SSCCTL_PATHALT; | |
7151 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7152 | ||
7153 | udelay(24); | |
7154 | ||
2fa86a1f PZ |
7155 | if (with_spread) { |
7156 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7157 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7158 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7159 | |
2fa86a1f PZ |
7160 | if (with_fdi) { |
7161 | lpt_reset_fdi_mphy(dev_priv); | |
7162 | lpt_program_fdi_mphy(dev_priv); | |
7163 | } | |
7164 | } | |
dde86e2d | 7165 | |
2fa86a1f PZ |
7166 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7167 | SBI_GEN0 : SBI_DBUFF0; | |
7168 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7169 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7170 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7171 | |
7172 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7173 | } |
7174 | ||
47701c3b PZ |
7175 | /* Sequence to disable CLKOUT_DP */ |
7176 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7177 | { | |
7178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7179 | uint32_t reg, tmp; | |
7180 | ||
7181 | mutex_lock(&dev_priv->dpio_lock); | |
7182 | ||
7183 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7184 | SBI_GEN0 : SBI_DBUFF0; | |
7185 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7186 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7187 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7188 | ||
7189 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7190 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7191 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7192 | tmp |= SBI_SSCCTL_PATHALT; | |
7193 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7194 | udelay(32); | |
7195 | } | |
7196 | tmp |= SBI_SSCCTL_DISABLE; | |
7197 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7198 | } | |
7199 | ||
7200 | mutex_unlock(&dev_priv->dpio_lock); | |
7201 | } | |
7202 | ||
bf8fa3d3 PZ |
7203 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7204 | { | |
bf8fa3d3 PZ |
7205 | struct intel_encoder *encoder; |
7206 | bool has_vga = false; | |
7207 | ||
b2784e15 | 7208 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7209 | switch (encoder->type) { |
7210 | case INTEL_OUTPUT_ANALOG: | |
7211 | has_vga = true; | |
7212 | break; | |
6847d71b PZ |
7213 | default: |
7214 | break; | |
bf8fa3d3 PZ |
7215 | } |
7216 | } | |
7217 | ||
47701c3b PZ |
7218 | if (has_vga) |
7219 | lpt_enable_clkout_dp(dev, true, true); | |
7220 | else | |
7221 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7222 | } |
7223 | ||
dde86e2d PZ |
7224 | /* |
7225 | * Initialize reference clocks when the driver loads | |
7226 | */ | |
7227 | void intel_init_pch_refclk(struct drm_device *dev) | |
7228 | { | |
7229 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7230 | ironlake_init_pch_refclk(dev); | |
7231 | else if (HAS_PCH_LPT(dev)) | |
7232 | lpt_init_pch_refclk(dev); | |
7233 | } | |
7234 | ||
d9d444cb JB |
7235 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7236 | { | |
7237 | struct drm_device *dev = crtc->dev; | |
7238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7239 | struct intel_encoder *encoder; | |
d9d444cb JB |
7240 | int num_connectors = 0; |
7241 | bool is_lvds = false; | |
7242 | ||
d0737e1d ACO |
7243 | for_each_intel_encoder(dev, encoder) { |
7244 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7245 | continue; | |
7246 | ||
d9d444cb JB |
7247 | switch (encoder->type) { |
7248 | case INTEL_OUTPUT_LVDS: | |
7249 | is_lvds = true; | |
7250 | break; | |
6847d71b PZ |
7251 | default: |
7252 | break; | |
d9d444cb JB |
7253 | } |
7254 | num_connectors++; | |
7255 | } | |
7256 | ||
7257 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7258 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7259 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7260 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7261 | } |
7262 | ||
7263 | return 120000; | |
7264 | } | |
7265 | ||
6ff93609 | 7266 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7267 | { |
c8203565 | 7268 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7270 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7271 | uint32_t val; |
7272 | ||
78114071 | 7273 | val = 0; |
c8203565 | 7274 | |
6e3c9717 | 7275 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7276 | case 18: |
dfd07d72 | 7277 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7278 | break; |
7279 | case 24: | |
dfd07d72 | 7280 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7281 | break; |
7282 | case 30: | |
dfd07d72 | 7283 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7284 | break; |
7285 | case 36: | |
dfd07d72 | 7286 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7287 | break; |
7288 | default: | |
cc769b62 PZ |
7289 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7290 | BUG(); | |
c8203565 PZ |
7291 | } |
7292 | ||
6e3c9717 | 7293 | if (intel_crtc->config->dither) |
c8203565 PZ |
7294 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7295 | ||
6e3c9717 | 7296 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7297 | val |= PIPECONF_INTERLACED_ILK; |
7298 | else | |
7299 | val |= PIPECONF_PROGRESSIVE; | |
7300 | ||
6e3c9717 | 7301 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7302 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7303 | |
c8203565 PZ |
7304 | I915_WRITE(PIPECONF(pipe), val); |
7305 | POSTING_READ(PIPECONF(pipe)); | |
7306 | } | |
7307 | ||
86d3efce VS |
7308 | /* |
7309 | * Set up the pipe CSC unit. | |
7310 | * | |
7311 | * Currently only full range RGB to limited range RGB conversion | |
7312 | * is supported, but eventually this should handle various | |
7313 | * RGB<->YCbCr scenarios as well. | |
7314 | */ | |
50f3b016 | 7315 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7316 | { |
7317 | struct drm_device *dev = crtc->dev; | |
7318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7319 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7320 | int pipe = intel_crtc->pipe; | |
7321 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7322 | ||
7323 | /* | |
7324 | * TODO: Check what kind of values actually come out of the pipe | |
7325 | * with these coeff/postoff values and adjust to get the best | |
7326 | * accuracy. Perhaps we even need to take the bpc value into | |
7327 | * consideration. | |
7328 | */ | |
7329 | ||
6e3c9717 | 7330 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7331 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7332 | ||
7333 | /* | |
7334 | * GY/GU and RY/RU should be the other way around according | |
7335 | * to BSpec, but reality doesn't agree. Just set them up in | |
7336 | * a way that results in the correct picture. | |
7337 | */ | |
7338 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7339 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7340 | ||
7341 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7342 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7343 | ||
7344 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7345 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7346 | ||
7347 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7348 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7349 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7350 | ||
7351 | if (INTEL_INFO(dev)->gen > 6) { | |
7352 | uint16_t postoff = 0; | |
7353 | ||
6e3c9717 | 7354 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7355 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7356 | |
7357 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7358 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7359 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7360 | ||
7361 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7362 | } else { | |
7363 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7364 | ||
6e3c9717 | 7365 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7366 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7367 | ||
7368 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7369 | } | |
7370 | } | |
7371 | ||
6ff93609 | 7372 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7373 | { |
756f85cf PZ |
7374 | struct drm_device *dev = crtc->dev; |
7375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7377 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7378 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7379 | uint32_t val; |
7380 | ||
3eff4faa | 7381 | val = 0; |
ee2b0b38 | 7382 | |
6e3c9717 | 7383 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7384 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7385 | ||
6e3c9717 | 7386 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7387 | val |= PIPECONF_INTERLACED_ILK; |
7388 | else | |
7389 | val |= PIPECONF_PROGRESSIVE; | |
7390 | ||
702e7a56 PZ |
7391 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7392 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7393 | |
7394 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7395 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7396 | |
3cdf122c | 7397 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7398 | val = 0; |
7399 | ||
6e3c9717 | 7400 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7401 | case 18: |
7402 | val |= PIPEMISC_DITHER_6_BPC; | |
7403 | break; | |
7404 | case 24: | |
7405 | val |= PIPEMISC_DITHER_8_BPC; | |
7406 | break; | |
7407 | case 30: | |
7408 | val |= PIPEMISC_DITHER_10_BPC; | |
7409 | break; | |
7410 | case 36: | |
7411 | val |= PIPEMISC_DITHER_12_BPC; | |
7412 | break; | |
7413 | default: | |
7414 | /* Case prevented by pipe_config_set_bpp. */ | |
7415 | BUG(); | |
7416 | } | |
7417 | ||
6e3c9717 | 7418 | if (intel_crtc->config->dither) |
756f85cf PZ |
7419 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7420 | ||
7421 | I915_WRITE(PIPEMISC(pipe), val); | |
7422 | } | |
ee2b0b38 PZ |
7423 | } |
7424 | ||
6591c6e4 | 7425 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7426 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7427 | intel_clock_t *clock, |
7428 | bool *has_reduced_clock, | |
7429 | intel_clock_t *reduced_clock) | |
7430 | { | |
7431 | struct drm_device *dev = crtc->dev; | |
7432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7434 | int refclk; |
d4906093 | 7435 | const intel_limit_t *limit; |
a16af721 | 7436 | bool ret, is_lvds = false; |
79e53945 | 7437 | |
d0737e1d | 7438 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7439 | |
d9d444cb | 7440 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7441 | |
d4906093 ML |
7442 | /* |
7443 | * Returns a set of divisors for the desired target clock with the given | |
7444 | * refclk, or FALSE. The returned values represent the clock equation: | |
7445 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7446 | */ | |
409ee761 | 7447 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7448 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
190f68c5 | 7449 | crtc_state->port_clock, |
ee9300bb | 7450 | refclk, NULL, clock); |
6591c6e4 PZ |
7451 | if (!ret) |
7452 | return false; | |
cda4b7d3 | 7453 | |
ddc9003c | 7454 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7455 | /* |
7456 | * Ensure we match the reduced clock's P to the target clock. | |
7457 | * If the clocks don't match, we can't switch the display clock | |
7458 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7459 | * downclock feature. | |
7460 | */ | |
ee9300bb | 7461 | *has_reduced_clock = |
a919ff14 | 7462 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7463 | dev_priv->lvds_downclock, |
7464 | refclk, clock, | |
7465 | reduced_clock); | |
652c393a | 7466 | } |
61e9653f | 7467 | |
6591c6e4 PZ |
7468 | return true; |
7469 | } | |
7470 | ||
d4b1931c PZ |
7471 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7472 | { | |
7473 | /* | |
7474 | * Account for spread spectrum to avoid | |
7475 | * oversubscribing the link. Max center spread | |
7476 | * is 2.5%; use 5% for safety's sake. | |
7477 | */ | |
7478 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7479 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7480 | } |
7481 | ||
7429e9d4 | 7482 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7483 | { |
7429e9d4 | 7484 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7485 | } |
7486 | ||
de13a2e3 | 7487 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7488 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7489 | u32 *fp, |
9a7c7890 | 7490 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7491 | { |
de13a2e3 | 7492 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7493 | struct drm_device *dev = crtc->dev; |
7494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7495 | struct intel_encoder *intel_encoder; |
7496 | uint32_t dpll; | |
6cc5f341 | 7497 | int factor, num_connectors = 0; |
09ede541 | 7498 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7499 | |
d0737e1d ACO |
7500 | for_each_intel_encoder(dev, intel_encoder) { |
7501 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7502 | continue; | |
7503 | ||
de13a2e3 | 7504 | switch (intel_encoder->type) { |
79e53945 JB |
7505 | case INTEL_OUTPUT_LVDS: |
7506 | is_lvds = true; | |
7507 | break; | |
7508 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7509 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7510 | is_sdvo = true; |
79e53945 | 7511 | break; |
6847d71b PZ |
7512 | default: |
7513 | break; | |
79e53945 | 7514 | } |
43565a06 | 7515 | |
c751ce4f | 7516 | num_connectors++; |
79e53945 | 7517 | } |
79e53945 | 7518 | |
c1858123 | 7519 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7520 | factor = 21; |
7521 | if (is_lvds) { | |
7522 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7523 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7524 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7525 | factor = 25; |
190f68c5 | 7526 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7527 | factor = 20; |
c1858123 | 7528 | |
190f68c5 | 7529 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7530 | *fp |= FP_CB_TUNE; |
2c07245f | 7531 | |
9a7c7890 DV |
7532 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7533 | *fp2 |= FP_CB_TUNE; | |
7534 | ||
5eddb70b | 7535 | dpll = 0; |
2c07245f | 7536 | |
a07d6787 EA |
7537 | if (is_lvds) |
7538 | dpll |= DPLLB_MODE_LVDS; | |
7539 | else | |
7540 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7541 | |
190f68c5 | 7542 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7543 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7544 | |
7545 | if (is_sdvo) | |
4a33e48d | 7546 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7547 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7548 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7549 | |
a07d6787 | 7550 | /* compute bitmask from p1 value */ |
190f68c5 | 7551 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7552 | /* also FPA1 */ |
190f68c5 | 7553 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7554 | |
190f68c5 | 7555 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7556 | case 5: |
7557 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7558 | break; | |
7559 | case 7: | |
7560 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7561 | break; | |
7562 | case 10: | |
7563 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7564 | break; | |
7565 | case 14: | |
7566 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7567 | break; | |
79e53945 JB |
7568 | } |
7569 | ||
b4c09f3b | 7570 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7571 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7572 | else |
7573 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7574 | ||
959e16d6 | 7575 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7576 | } |
7577 | ||
190f68c5 ACO |
7578 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
7579 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 7580 | { |
c7653199 | 7581 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7582 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7583 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7584 | bool ok, has_reduced_clock = false; |
8b47047b | 7585 | bool is_lvds = false; |
e2b78267 | 7586 | struct intel_shared_dpll *pll; |
de13a2e3 | 7587 | |
409ee761 | 7588 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7589 | |
5dc5298b PZ |
7590 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7591 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7592 | |
190f68c5 | 7593 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 7594 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 7595 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
7596 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7597 | return -EINVAL; | |
79e53945 | 7598 | } |
f47709a9 | 7599 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7600 | if (!crtc_state->clock_set) { |
7601 | crtc_state->dpll.n = clock.n; | |
7602 | crtc_state->dpll.m1 = clock.m1; | |
7603 | crtc_state->dpll.m2 = clock.m2; | |
7604 | crtc_state->dpll.p1 = clock.p1; | |
7605 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7606 | } |
79e53945 | 7607 | |
5dc5298b | 7608 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
7609 | if (crtc_state->has_pch_encoder) { |
7610 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 7611 | if (has_reduced_clock) |
7429e9d4 | 7612 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7613 | |
190f68c5 | 7614 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
7615 | &fp, &reduced_clock, |
7616 | has_reduced_clock ? &fp2 : NULL); | |
7617 | ||
190f68c5 ACO |
7618 | crtc_state->dpll_hw_state.dpll = dpll; |
7619 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7620 | if (has_reduced_clock) |
190f68c5 | 7621 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7622 | else |
190f68c5 | 7623 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 7624 | |
190f68c5 | 7625 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 7626 | if (pll == NULL) { |
84f44ce7 | 7627 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7628 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7629 | return -EINVAL; |
7630 | } | |
3fb37703 | 7631 | } |
79e53945 | 7632 | |
d330a953 | 7633 | if (is_lvds && has_reduced_clock && i915.powersave) |
c7653199 | 7634 | crtc->lowfreq_avail = true; |
bcd644e0 | 7635 | else |
c7653199 | 7636 | crtc->lowfreq_avail = false; |
e2b78267 | 7637 | |
c8f7a0db | 7638 | return 0; |
79e53945 JB |
7639 | } |
7640 | ||
eb14cb74 VS |
7641 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7642 | struct intel_link_m_n *m_n) | |
7643 | { | |
7644 | struct drm_device *dev = crtc->base.dev; | |
7645 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7646 | enum pipe pipe = crtc->pipe; | |
7647 | ||
7648 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7649 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7650 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7651 | & ~TU_SIZE_MASK; | |
7652 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7653 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7654 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7655 | } | |
7656 | ||
7657 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7658 | enum transcoder transcoder, | |
b95af8be VK |
7659 | struct intel_link_m_n *m_n, |
7660 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7661 | { |
7662 | struct drm_device *dev = crtc->base.dev; | |
7663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7664 | enum pipe pipe = crtc->pipe; |
72419203 | 7665 | |
eb14cb74 VS |
7666 | if (INTEL_INFO(dev)->gen >= 5) { |
7667 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7668 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7669 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7670 | & ~TU_SIZE_MASK; | |
7671 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7672 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7673 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7674 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7675 | * gen < 8) and if DRRS is supported (to make sure the | |
7676 | * registers are not unnecessarily read). | |
7677 | */ | |
7678 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 7679 | crtc->config->has_drrs) { |
b95af8be VK |
7680 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
7681 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7682 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7683 | & ~TU_SIZE_MASK; | |
7684 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7685 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7686 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7687 | } | |
eb14cb74 VS |
7688 | } else { |
7689 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7690 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7691 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7692 | & ~TU_SIZE_MASK; | |
7693 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7694 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7695 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7696 | } | |
7697 | } | |
7698 | ||
7699 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 7700 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 7701 | { |
681a8504 | 7702 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
7703 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
7704 | else | |
7705 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7706 | &pipe_config->dp_m_n, |
7707 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7708 | } |
72419203 | 7709 | |
eb14cb74 | 7710 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 7711 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
7712 | { |
7713 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7714 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7715 | } |
7716 | ||
bd2e244f | 7717 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7718 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
7719 | { |
7720 | struct drm_device *dev = crtc->base.dev; | |
7721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7722 | uint32_t tmp; | |
7723 | ||
7724 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7725 | ||
7726 | if (tmp & PS_ENABLE) { | |
7727 | pipe_config->pch_pfit.enabled = true; | |
7728 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7729 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7730 | } | |
7731 | } | |
7732 | ||
5724dbd1 DL |
7733 | static void |
7734 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
7735 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
7736 | { |
7737 | struct drm_device *dev = crtc->base.dev; | |
7738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7739 | u32 val, base, offset, stride_mult; | |
7740 | int pipe = crtc->pipe; | |
7741 | int fourcc, pixel_format; | |
7742 | int aligned_height; | |
7743 | struct drm_framebuffer *fb; | |
1b842c89 | 7744 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 7745 | |
d9806c9f | 7746 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7747 | if (!intel_fb) { |
bc8d7dff DL |
7748 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7749 | return; | |
7750 | } | |
7751 | ||
1b842c89 DL |
7752 | fb = &intel_fb->base; |
7753 | ||
bc8d7dff | 7754 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
7755 | if (!(val & PLANE_CTL_ENABLE)) |
7756 | goto error; | |
7757 | ||
18c5247e | 7758 | if (val & PLANE_CTL_TILED_MASK) { |
bc8d7dff | 7759 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7760 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7761 | } | |
bc8d7dff DL |
7762 | |
7763 | pixel_format = val & PLANE_CTL_FORMAT_MASK; | |
7764 | fourcc = skl_format_to_fourcc(pixel_format, | |
7765 | val & PLANE_CTL_ORDER_RGBX, | |
7766 | val & PLANE_CTL_ALPHA_MASK); | |
7767 | fb->pixel_format = fourcc; | |
7768 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
7769 | ||
7770 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; | |
7771 | plane_config->base = base; | |
7772 | ||
7773 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
7774 | ||
7775 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
7776 | fb->height = ((val >> 16) & 0xfff) + 1; | |
7777 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
7778 | ||
7779 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7780 | switch (plane_config->tiling) { | |
7781 | case I915_TILING_NONE: | |
7782 | stride_mult = 64; | |
7783 | break; | |
7784 | case I915_TILING_X: | |
7785 | stride_mult = 512; | |
7786 | break; | |
7787 | default: | |
7788 | MISSING_CASE(plane_config->tiling); | |
7789 | goto error; | |
7790 | } | |
7791 | fb->pitches[0] = (val & 0x3ff) * stride_mult; | |
7792 | ||
7793 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
7794 | fb->pixel_format, |
7795 | fb->modifier[0]); | |
bc8d7dff DL |
7796 | |
7797 | plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE); | |
7798 | ||
7799 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
7800 | pipe_name(pipe), fb->width, fb->height, | |
7801 | fb->bits_per_pixel, base, fb->pitches[0], | |
7802 | plane_config->size); | |
7803 | ||
2d14030b | 7804 | plane_config->fb = intel_fb; |
bc8d7dff DL |
7805 | return; |
7806 | ||
7807 | error: | |
7808 | kfree(fb); | |
7809 | } | |
7810 | ||
2fa2fe9a | 7811 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7812 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7813 | { |
7814 | struct drm_device *dev = crtc->base.dev; | |
7815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7816 | uint32_t tmp; | |
7817 | ||
7818 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7819 | ||
7820 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7821 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7822 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7823 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7824 | |
7825 | /* We currently do not free assignements of panel fitters on | |
7826 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7827 | * differentiates them) so just WARN about this case for now. */ | |
7828 | if (IS_GEN7(dev)) { | |
7829 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7830 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7831 | } | |
2fa2fe9a | 7832 | } |
79e53945 JB |
7833 | } |
7834 | ||
5724dbd1 DL |
7835 | static void |
7836 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
7837 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
7838 | { |
7839 | struct drm_device *dev = crtc->base.dev; | |
7840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7841 | u32 val, base, offset; | |
aeee5a49 | 7842 | int pipe = crtc->pipe; |
4c6baa59 JB |
7843 | int fourcc, pixel_format; |
7844 | int aligned_height; | |
b113d5ee | 7845 | struct drm_framebuffer *fb; |
1b842c89 | 7846 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 7847 | |
42a7b088 DL |
7848 | val = I915_READ(DSPCNTR(pipe)); |
7849 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7850 | return; | |
7851 | ||
d9806c9f | 7852 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7853 | if (!intel_fb) { |
4c6baa59 JB |
7854 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7855 | return; | |
7856 | } | |
7857 | ||
1b842c89 DL |
7858 | fb = &intel_fb->base; |
7859 | ||
18c5247e DV |
7860 | if (INTEL_INFO(dev)->gen >= 4) { |
7861 | if (val & DISPPLANE_TILED) { | |
49af449b | 7862 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7863 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7864 | } | |
7865 | } | |
4c6baa59 JB |
7866 | |
7867 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7868 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7869 | fb->pixel_format = fourcc; |
7870 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 7871 | |
aeee5a49 | 7872 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 7873 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 7874 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 7875 | } else { |
49af449b | 7876 | if (plane_config->tiling) |
aeee5a49 | 7877 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 7878 | else |
aeee5a49 | 7879 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
7880 | } |
7881 | plane_config->base = base; | |
7882 | ||
7883 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7884 | fb->width = ((val >> 16) & 0xfff) + 1; |
7885 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7886 | |
7887 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7888 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7889 | |
b113d5ee | 7890 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7891 | fb->pixel_format, |
7892 | fb->modifier[0]); | |
4c6baa59 | 7893 | |
b113d5ee | 7894 | plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); |
4c6baa59 | 7895 | |
2844a921 DL |
7896 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7897 | pipe_name(pipe), fb->width, fb->height, | |
7898 | fb->bits_per_pixel, base, fb->pitches[0], | |
7899 | plane_config->size); | |
b113d5ee | 7900 | |
2d14030b | 7901 | plane_config->fb = intel_fb; |
4c6baa59 JB |
7902 | } |
7903 | ||
0e8ffe1b | 7904 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7905 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7906 | { |
7907 | struct drm_device *dev = crtc->base.dev; | |
7908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7909 | uint32_t tmp; | |
7910 | ||
f458ebbc DV |
7911 | if (!intel_display_power_is_enabled(dev_priv, |
7912 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
7913 | return false; |
7914 | ||
e143a21c | 7915 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7916 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7917 | |
0e8ffe1b DV |
7918 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7919 | if (!(tmp & PIPECONF_ENABLE)) | |
7920 | return false; | |
7921 | ||
42571aef VS |
7922 | switch (tmp & PIPECONF_BPC_MASK) { |
7923 | case PIPECONF_6BPC: | |
7924 | pipe_config->pipe_bpp = 18; | |
7925 | break; | |
7926 | case PIPECONF_8BPC: | |
7927 | pipe_config->pipe_bpp = 24; | |
7928 | break; | |
7929 | case PIPECONF_10BPC: | |
7930 | pipe_config->pipe_bpp = 30; | |
7931 | break; | |
7932 | case PIPECONF_12BPC: | |
7933 | pipe_config->pipe_bpp = 36; | |
7934 | break; | |
7935 | default: | |
7936 | break; | |
7937 | } | |
7938 | ||
b5a9fa09 DV |
7939 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7940 | pipe_config->limited_color_range = true; | |
7941 | ||
ab9412ba | 7942 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7943 | struct intel_shared_dpll *pll; |
7944 | ||
88adfff1 DV |
7945 | pipe_config->has_pch_encoder = true; |
7946 | ||
627eb5a3 DV |
7947 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7948 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7949 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7950 | |
7951 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7952 | |
c0d43d62 | 7953 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7954 | pipe_config->shared_dpll = |
7955 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7956 | } else { |
7957 | tmp = I915_READ(PCH_DPLL_SEL); | |
7958 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7959 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7960 | else | |
7961 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7962 | } | |
66e985c0 DV |
7963 | |
7964 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7965 | ||
7966 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7967 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7968 | |
7969 | tmp = pipe_config->dpll_hw_state.dpll; | |
7970 | pipe_config->pixel_multiplier = | |
7971 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7972 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7973 | |
7974 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7975 | } else { |
7976 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7977 | } |
7978 | ||
1bd1bd80 DV |
7979 | intel_get_pipe_timings(crtc, pipe_config); |
7980 | ||
2fa2fe9a DV |
7981 | ironlake_get_pfit_config(crtc, pipe_config); |
7982 | ||
0e8ffe1b DV |
7983 | return true; |
7984 | } | |
7985 | ||
be256dc7 PZ |
7986 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7987 | { | |
7988 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7989 | struct intel_crtc *crtc; |
be256dc7 | 7990 | |
d3fcc808 | 7991 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 7992 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7993 | pipe_name(crtc->pipe)); |
7994 | ||
e2c719b7 RC |
7995 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
7996 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
7997 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7998 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
7999 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8000 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8001 | "CPU PWM1 enabled\n"); |
c5107b87 | 8002 | if (IS_HASWELL(dev)) |
e2c719b7 | 8003 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8004 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8005 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8006 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8007 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8008 | "Utility pin enabled\n"); |
e2c719b7 | 8009 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8010 | |
9926ada1 PZ |
8011 | /* |
8012 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8013 | * interrupts remain enabled. We used to check for that, but since it's | |
8014 | * gen-specific and since we only disable LCPLL after we fully disable | |
8015 | * the interrupts, the check below should be enough. | |
8016 | */ | |
e2c719b7 | 8017 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8018 | } |
8019 | ||
9ccd5aeb PZ |
8020 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8021 | { | |
8022 | struct drm_device *dev = dev_priv->dev; | |
8023 | ||
8024 | if (IS_HASWELL(dev)) | |
8025 | return I915_READ(D_COMP_HSW); | |
8026 | else | |
8027 | return I915_READ(D_COMP_BDW); | |
8028 | } | |
8029 | ||
3c4c9b81 PZ |
8030 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8031 | { | |
8032 | struct drm_device *dev = dev_priv->dev; | |
8033 | ||
8034 | if (IS_HASWELL(dev)) { | |
8035 | mutex_lock(&dev_priv->rps.hw_lock); | |
8036 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8037 | val)) | |
f475dadf | 8038 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8039 | mutex_unlock(&dev_priv->rps.hw_lock); |
8040 | } else { | |
9ccd5aeb PZ |
8041 | I915_WRITE(D_COMP_BDW, val); |
8042 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8043 | } |
be256dc7 PZ |
8044 | } |
8045 | ||
8046 | /* | |
8047 | * This function implements pieces of two sequences from BSpec: | |
8048 | * - Sequence for display software to disable LCPLL | |
8049 | * - Sequence for display software to allow package C8+ | |
8050 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8051 | * register. Callers should take care of disabling all the display engine | |
8052 | * functions, doing the mode unset, fixing interrupts, etc. | |
8053 | */ | |
6ff58d53 PZ |
8054 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8055 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8056 | { |
8057 | uint32_t val; | |
8058 | ||
8059 | assert_can_disable_lcpll(dev_priv); | |
8060 | ||
8061 | val = I915_READ(LCPLL_CTL); | |
8062 | ||
8063 | if (switch_to_fclk) { | |
8064 | val |= LCPLL_CD_SOURCE_FCLK; | |
8065 | I915_WRITE(LCPLL_CTL, val); | |
8066 | ||
8067 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8068 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8069 | DRM_ERROR("Switching to FCLK failed\n"); | |
8070 | ||
8071 | val = I915_READ(LCPLL_CTL); | |
8072 | } | |
8073 | ||
8074 | val |= LCPLL_PLL_DISABLE; | |
8075 | I915_WRITE(LCPLL_CTL, val); | |
8076 | POSTING_READ(LCPLL_CTL); | |
8077 | ||
8078 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8079 | DRM_ERROR("LCPLL still locked\n"); | |
8080 | ||
9ccd5aeb | 8081 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8082 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8083 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8084 | ndelay(100); |
8085 | ||
9ccd5aeb PZ |
8086 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8087 | 1)) | |
be256dc7 PZ |
8088 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8089 | ||
8090 | if (allow_power_down) { | |
8091 | val = I915_READ(LCPLL_CTL); | |
8092 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8093 | I915_WRITE(LCPLL_CTL, val); | |
8094 | POSTING_READ(LCPLL_CTL); | |
8095 | } | |
8096 | } | |
8097 | ||
8098 | /* | |
8099 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8100 | * source. | |
8101 | */ | |
6ff58d53 | 8102 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8103 | { |
8104 | uint32_t val; | |
8105 | ||
8106 | val = I915_READ(LCPLL_CTL); | |
8107 | ||
8108 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8109 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8110 | return; | |
8111 | ||
a8a8bd54 PZ |
8112 | /* |
8113 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8114 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8115 | */ |
59bad947 | 8116 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8117 | |
be256dc7 PZ |
8118 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8119 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8120 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8121 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8122 | } |
8123 | ||
9ccd5aeb | 8124 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8125 | val |= D_COMP_COMP_FORCE; |
8126 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8127 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8128 | |
8129 | val = I915_READ(LCPLL_CTL); | |
8130 | val &= ~LCPLL_PLL_DISABLE; | |
8131 | I915_WRITE(LCPLL_CTL, val); | |
8132 | ||
8133 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8134 | DRM_ERROR("LCPLL not locked yet\n"); | |
8135 | ||
8136 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8137 | val = I915_READ(LCPLL_CTL); | |
8138 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8139 | I915_WRITE(LCPLL_CTL, val); | |
8140 | ||
8141 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8142 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8143 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8144 | } | |
215733fa | 8145 | |
59bad947 | 8146 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8147 | } |
8148 | ||
765dab67 PZ |
8149 | /* |
8150 | * Package states C8 and deeper are really deep PC states that can only be | |
8151 | * reached when all the devices on the system allow it, so even if the graphics | |
8152 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8153 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8154 | * | |
8155 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8156 | * well is disabled and most interrupts are disabled, and these are also | |
8157 | * requirements for runtime PM. When these conditions are met, we manually do | |
8158 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8159 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8160 | * hang the machine. | |
8161 | * | |
8162 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8163 | * the state of some registers, so when we come back from PC8+ we need to | |
8164 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8165 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8166 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8167 | * because of the runtime PM support). | |
8168 | * | |
8169 | * For more, read "Display Sequences for Package C8" on the hardware | |
8170 | * documentation. | |
8171 | */ | |
a14cb6fc | 8172 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8173 | { |
c67a470b PZ |
8174 | struct drm_device *dev = dev_priv->dev; |
8175 | uint32_t val; | |
8176 | ||
c67a470b PZ |
8177 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8178 | ||
c67a470b PZ |
8179 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8180 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8181 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8182 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8183 | } | |
8184 | ||
8185 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8186 | hsw_disable_lcpll(dev_priv, true, true); |
8187 | } | |
8188 | ||
a14cb6fc | 8189 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8190 | { |
8191 | struct drm_device *dev = dev_priv->dev; | |
8192 | uint32_t val; | |
8193 | ||
c67a470b PZ |
8194 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8195 | ||
8196 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8197 | lpt_init_pch_refclk(dev); |
8198 | ||
8199 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8200 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8201 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8202 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8203 | } | |
8204 | ||
8205 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8206 | } |
8207 | ||
190f68c5 ACO |
8208 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8209 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8210 | { |
190f68c5 | 8211 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8212 | return -EINVAL; |
716c2e55 | 8213 | |
c7653199 | 8214 | crtc->lowfreq_avail = false; |
644cef34 | 8215 | |
c8f7a0db | 8216 | return 0; |
79e53945 JB |
8217 | } |
8218 | ||
96b7dfb7 S |
8219 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8220 | enum port port, | |
5cec258b | 8221 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8222 | { |
3148ade7 | 8223 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8224 | |
8225 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8226 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8227 | ||
8228 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8229 | case SKL_DPLL0: |
8230 | /* | |
8231 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8232 | * of the shared DPLL framework and thus needs to be read out | |
8233 | * separately | |
8234 | */ | |
8235 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8236 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8237 | break; | |
96b7dfb7 S |
8238 | case SKL_DPLL1: |
8239 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8240 | break; | |
8241 | case SKL_DPLL2: | |
8242 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8243 | break; | |
8244 | case SKL_DPLL3: | |
8245 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8246 | break; | |
96b7dfb7 S |
8247 | } |
8248 | } | |
8249 | ||
7d2c8175 DL |
8250 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8251 | enum port port, | |
5cec258b | 8252 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8253 | { |
8254 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8255 | ||
8256 | switch (pipe_config->ddi_pll_sel) { | |
8257 | case PORT_CLK_SEL_WRPLL1: | |
8258 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8259 | break; | |
8260 | case PORT_CLK_SEL_WRPLL2: | |
8261 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8262 | break; | |
8263 | } | |
8264 | } | |
8265 | ||
26804afd | 8266 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8267 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8268 | { |
8269 | struct drm_device *dev = crtc->base.dev; | |
8270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8271 | struct intel_shared_dpll *pll; |
26804afd DV |
8272 | enum port port; |
8273 | uint32_t tmp; | |
8274 | ||
8275 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8276 | ||
8277 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8278 | ||
96b7dfb7 S |
8279 | if (IS_SKYLAKE(dev)) |
8280 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8281 | else | |
8282 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8283 | |
d452c5b6 DV |
8284 | if (pipe_config->shared_dpll >= 0) { |
8285 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8286 | ||
8287 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8288 | &pipe_config->dpll_hw_state)); | |
8289 | } | |
8290 | ||
26804afd DV |
8291 | /* |
8292 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8293 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8294 | * the PCH transcoder is on. | |
8295 | */ | |
ca370455 DL |
8296 | if (INTEL_INFO(dev)->gen < 9 && |
8297 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8298 | pipe_config->has_pch_encoder = true; |
8299 | ||
8300 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8301 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8302 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8303 | ||
8304 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8305 | } | |
8306 | } | |
8307 | ||
0e8ffe1b | 8308 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8309 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8310 | { |
8311 | struct drm_device *dev = crtc->base.dev; | |
8312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8313 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8314 | uint32_t tmp; |
8315 | ||
f458ebbc | 8316 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8317 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8318 | return false; | |
8319 | ||
e143a21c | 8320 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8321 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8322 | ||
eccb140b DV |
8323 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8324 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8325 | enum pipe trans_edp_pipe; | |
8326 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8327 | default: | |
8328 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8329 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8330 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8331 | trans_edp_pipe = PIPE_A; | |
8332 | break; | |
8333 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8334 | trans_edp_pipe = PIPE_B; | |
8335 | break; | |
8336 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8337 | trans_edp_pipe = PIPE_C; | |
8338 | break; | |
8339 | } | |
8340 | ||
8341 | if (trans_edp_pipe == crtc->pipe) | |
8342 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8343 | } | |
8344 | ||
f458ebbc | 8345 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8346 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8347 | return false; |
8348 | ||
eccb140b | 8349 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8350 | if (!(tmp & PIPECONF_ENABLE)) |
8351 | return false; | |
8352 | ||
26804afd | 8353 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8354 | |
1bd1bd80 DV |
8355 | intel_get_pipe_timings(crtc, pipe_config); |
8356 | ||
2fa2fe9a | 8357 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8358 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8359 | if (IS_SKYLAKE(dev)) | |
8360 | skylake_get_pfit_config(crtc, pipe_config); | |
8361 | else | |
8362 | ironlake_get_pfit_config(crtc, pipe_config); | |
8363 | } | |
88adfff1 | 8364 | |
e59150dc JB |
8365 | if (IS_HASWELL(dev)) |
8366 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8367 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8368 | |
ebb69c95 CT |
8369 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8370 | pipe_config->pixel_multiplier = | |
8371 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8372 | } else { | |
8373 | pipe_config->pixel_multiplier = 1; | |
8374 | } | |
6c49f241 | 8375 | |
0e8ffe1b DV |
8376 | return true; |
8377 | } | |
8378 | ||
560b85bb CW |
8379 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8380 | { | |
8381 | struct drm_device *dev = crtc->dev; | |
8382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8384 | uint32_t cntl = 0, size = 0; |
560b85bb | 8385 | |
dc41c154 VS |
8386 | if (base) { |
8387 | unsigned int width = intel_crtc->cursor_width; | |
8388 | unsigned int height = intel_crtc->cursor_height; | |
8389 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8390 | ||
8391 | switch (stride) { | |
8392 | default: | |
8393 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8394 | width, stride); | |
8395 | stride = 256; | |
8396 | /* fallthrough */ | |
8397 | case 256: | |
8398 | case 512: | |
8399 | case 1024: | |
8400 | case 2048: | |
8401 | break; | |
4b0e333e CW |
8402 | } |
8403 | ||
dc41c154 VS |
8404 | cntl |= CURSOR_ENABLE | |
8405 | CURSOR_GAMMA_ENABLE | | |
8406 | CURSOR_FORMAT_ARGB | | |
8407 | CURSOR_STRIDE(stride); | |
8408 | ||
8409 | size = (height << 12) | width; | |
4b0e333e | 8410 | } |
560b85bb | 8411 | |
dc41c154 VS |
8412 | if (intel_crtc->cursor_cntl != 0 && |
8413 | (intel_crtc->cursor_base != base || | |
8414 | intel_crtc->cursor_size != size || | |
8415 | intel_crtc->cursor_cntl != cntl)) { | |
8416 | /* On these chipsets we can only modify the base/size/stride | |
8417 | * whilst the cursor is disabled. | |
8418 | */ | |
8419 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8420 | POSTING_READ(_CURACNTR); |
dc41c154 | 8421 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8422 | } |
560b85bb | 8423 | |
99d1f387 | 8424 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8425 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8426 | intel_crtc->cursor_base = base; |
8427 | } | |
4726e0b0 | 8428 | |
dc41c154 VS |
8429 | if (intel_crtc->cursor_size != size) { |
8430 | I915_WRITE(CURSIZE, size); | |
8431 | intel_crtc->cursor_size = size; | |
4b0e333e | 8432 | } |
560b85bb | 8433 | |
4b0e333e | 8434 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8435 | I915_WRITE(_CURACNTR, cntl); |
8436 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8437 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8438 | } |
560b85bb CW |
8439 | } |
8440 | ||
560b85bb | 8441 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8442 | { |
8443 | struct drm_device *dev = crtc->dev; | |
8444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8446 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8447 | uint32_t cntl; |
8448 | ||
8449 | cntl = 0; | |
8450 | if (base) { | |
8451 | cntl = MCURSOR_GAMMA_ENABLE; | |
8452 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8453 | case 64: |
8454 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8455 | break; | |
8456 | case 128: | |
8457 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8458 | break; | |
8459 | case 256: | |
8460 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8461 | break; | |
8462 | default: | |
5f77eeb0 | 8463 | MISSING_CASE(intel_crtc->cursor_width); |
4726e0b0 | 8464 | return; |
65a21cd6 | 8465 | } |
4b0e333e | 8466 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8467 | |
8468 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8469 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8470 | } |
65a21cd6 | 8471 | |
8e7d688b | 8472 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8473 | cntl |= CURSOR_ROTATE_180; |
8474 | ||
4b0e333e CW |
8475 | if (intel_crtc->cursor_cntl != cntl) { |
8476 | I915_WRITE(CURCNTR(pipe), cntl); | |
8477 | POSTING_READ(CURCNTR(pipe)); | |
8478 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8479 | } |
4b0e333e | 8480 | |
65a21cd6 | 8481 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8482 | I915_WRITE(CURBASE(pipe), base); |
8483 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8484 | |
8485 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8486 | } |
8487 | ||
cda4b7d3 | 8488 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8489 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8490 | bool on) | |
cda4b7d3 CW |
8491 | { |
8492 | struct drm_device *dev = crtc->dev; | |
8493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8495 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8496 | int x = crtc->cursor_x; |
8497 | int y = crtc->cursor_y; | |
d6e4db15 | 8498 | u32 base = 0, pos = 0; |
cda4b7d3 | 8499 | |
d6e4db15 | 8500 | if (on) |
cda4b7d3 | 8501 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8502 | |
6e3c9717 | 8503 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8504 | base = 0; |
8505 | ||
6e3c9717 | 8506 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8507 | base = 0; |
8508 | ||
8509 | if (x < 0) { | |
efc9064e | 8510 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8511 | base = 0; |
8512 | ||
8513 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8514 | x = -x; | |
8515 | } | |
8516 | pos |= x << CURSOR_X_SHIFT; | |
8517 | ||
8518 | if (y < 0) { | |
efc9064e | 8519 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8520 | base = 0; |
8521 | ||
8522 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8523 | y = -y; | |
8524 | } | |
8525 | pos |= y << CURSOR_Y_SHIFT; | |
8526 | ||
4b0e333e | 8527 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8528 | return; |
8529 | ||
5efb3e28 VS |
8530 | I915_WRITE(CURPOS(pipe), pos); |
8531 | ||
4398ad45 VS |
8532 | /* ILK+ do this automagically */ |
8533 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8534 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
4398ad45 VS |
8535 | base += (intel_crtc->cursor_height * |
8536 | intel_crtc->cursor_width - 1) * 4; | |
8537 | } | |
8538 | ||
8ac54669 | 8539 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8540 | i845_update_cursor(crtc, base); |
8541 | else | |
8542 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8543 | } |
8544 | ||
dc41c154 VS |
8545 | static bool cursor_size_ok(struct drm_device *dev, |
8546 | uint32_t width, uint32_t height) | |
8547 | { | |
8548 | if (width == 0 || height == 0) | |
8549 | return false; | |
8550 | ||
8551 | /* | |
8552 | * 845g/865g are special in that they are only limited by | |
8553 | * the width of their cursors, the height is arbitrary up to | |
8554 | * the precision of the register. Everything else requires | |
8555 | * square cursors, limited to a few power-of-two sizes. | |
8556 | */ | |
8557 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8558 | if ((width & 63) != 0) | |
8559 | return false; | |
8560 | ||
8561 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8562 | return false; | |
8563 | ||
8564 | if (height > 1023) | |
8565 | return false; | |
8566 | } else { | |
8567 | switch (width | height) { | |
8568 | case 256: | |
8569 | case 128: | |
8570 | if (IS_GEN2(dev)) | |
8571 | return false; | |
8572 | case 64: | |
8573 | break; | |
8574 | default: | |
8575 | return false; | |
8576 | } | |
8577 | } | |
8578 | ||
8579 | return true; | |
8580 | } | |
8581 | ||
79e53945 | 8582 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8583 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8584 | { |
7203425a | 8585 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8586 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8587 | |
7203425a | 8588 | for (i = start; i < end; i++) { |
79e53945 JB |
8589 | intel_crtc->lut_r[i] = red[i] >> 8; |
8590 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8591 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8592 | } | |
8593 | ||
8594 | intel_crtc_load_lut(crtc); | |
8595 | } | |
8596 | ||
79e53945 JB |
8597 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8598 | static struct drm_display_mode load_detect_mode = { | |
8599 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8600 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8601 | }; | |
8602 | ||
a8bb6818 DV |
8603 | struct drm_framebuffer * |
8604 | __intel_framebuffer_create(struct drm_device *dev, | |
8605 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8606 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8607 | { |
8608 | struct intel_framebuffer *intel_fb; | |
8609 | int ret; | |
8610 | ||
8611 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8612 | if (!intel_fb) { | |
6ccb81f2 | 8613 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8614 | return ERR_PTR(-ENOMEM); |
8615 | } | |
8616 | ||
8617 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8618 | if (ret) |
8619 | goto err; | |
d2dff872 CW |
8620 | |
8621 | return &intel_fb->base; | |
dd4916c5 | 8622 | err: |
6ccb81f2 | 8623 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8624 | kfree(intel_fb); |
8625 | ||
8626 | return ERR_PTR(ret); | |
d2dff872 CW |
8627 | } |
8628 | ||
b5ea642a | 8629 | static struct drm_framebuffer * |
a8bb6818 DV |
8630 | intel_framebuffer_create(struct drm_device *dev, |
8631 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8632 | struct drm_i915_gem_object *obj) | |
8633 | { | |
8634 | struct drm_framebuffer *fb; | |
8635 | int ret; | |
8636 | ||
8637 | ret = i915_mutex_lock_interruptible(dev); | |
8638 | if (ret) | |
8639 | return ERR_PTR(ret); | |
8640 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8641 | mutex_unlock(&dev->struct_mutex); | |
8642 | ||
8643 | return fb; | |
8644 | } | |
8645 | ||
d2dff872 CW |
8646 | static u32 |
8647 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8648 | { | |
8649 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8650 | return ALIGN(pitch, 64); | |
8651 | } | |
8652 | ||
8653 | static u32 | |
8654 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8655 | { | |
8656 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8657 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8658 | } |
8659 | ||
8660 | static struct drm_framebuffer * | |
8661 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8662 | struct drm_display_mode *mode, | |
8663 | int depth, int bpp) | |
8664 | { | |
8665 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8666 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8667 | |
8668 | obj = i915_gem_alloc_object(dev, | |
8669 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8670 | if (obj == NULL) | |
8671 | return ERR_PTR(-ENOMEM); | |
8672 | ||
8673 | mode_cmd.width = mode->hdisplay; | |
8674 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8675 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8676 | bpp); | |
5ca0c34a | 8677 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8678 | |
8679 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8680 | } | |
8681 | ||
8682 | static struct drm_framebuffer * | |
8683 | mode_fits_in_fbdev(struct drm_device *dev, | |
8684 | struct drm_display_mode *mode) | |
8685 | { | |
4520f53a | 8686 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8687 | struct drm_i915_private *dev_priv = dev->dev_private; |
8688 | struct drm_i915_gem_object *obj; | |
8689 | struct drm_framebuffer *fb; | |
8690 | ||
4c0e5528 | 8691 | if (!dev_priv->fbdev) |
d2dff872 CW |
8692 | return NULL; |
8693 | ||
4c0e5528 | 8694 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8695 | return NULL; |
8696 | ||
4c0e5528 DV |
8697 | obj = dev_priv->fbdev->fb->obj; |
8698 | BUG_ON(!obj); | |
8699 | ||
8bcd4553 | 8700 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8701 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8702 | fb->bits_per_pixel)) | |
d2dff872 CW |
8703 | return NULL; |
8704 | ||
01f2c773 | 8705 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8706 | return NULL; |
8707 | ||
8708 | return fb; | |
4520f53a DV |
8709 | #else |
8710 | return NULL; | |
8711 | #endif | |
d2dff872 CW |
8712 | } |
8713 | ||
d2434ab7 | 8714 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8715 | struct drm_display_mode *mode, |
51fd371b RC |
8716 | struct intel_load_detect_pipe *old, |
8717 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8718 | { |
8719 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8720 | struct intel_encoder *intel_encoder = |
8721 | intel_attached_encoder(connector); | |
79e53945 | 8722 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8723 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8724 | struct drm_crtc *crtc = NULL; |
8725 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8726 | struct drm_framebuffer *fb; |
51fd371b RC |
8727 | struct drm_mode_config *config = &dev->mode_config; |
8728 | int ret, i = -1; | |
79e53945 | 8729 | |
d2dff872 | 8730 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8731 | connector->base.id, connector->name, |
8e329a03 | 8732 | encoder->base.id, encoder->name); |
d2dff872 | 8733 | |
51fd371b RC |
8734 | retry: |
8735 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8736 | if (ret) | |
8737 | goto fail_unlock; | |
6e9f798d | 8738 | |
79e53945 JB |
8739 | /* |
8740 | * Algorithm gets a little messy: | |
7a5e4805 | 8741 | * |
79e53945 JB |
8742 | * - if the connector already has an assigned crtc, use it (but make |
8743 | * sure it's on first) | |
7a5e4805 | 8744 | * |
79e53945 JB |
8745 | * - try to find the first unused crtc that can drive this connector, |
8746 | * and use that if we find one | |
79e53945 JB |
8747 | */ |
8748 | ||
8749 | /* See if we already have a CRTC for this connector */ | |
8750 | if (encoder->crtc) { | |
8751 | crtc = encoder->crtc; | |
8261b191 | 8752 | |
51fd371b | 8753 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8754 | if (ret) |
8755 | goto fail_unlock; | |
8756 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8757 | if (ret) |
8758 | goto fail_unlock; | |
7b24056b | 8759 | |
24218aac | 8760 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8761 | old->load_detect_temp = false; |
8762 | ||
8763 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8764 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8765 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8766 | |
7173188d | 8767 | return true; |
79e53945 JB |
8768 | } |
8769 | ||
8770 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8771 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8772 | i++; |
8773 | if (!(encoder->possible_crtcs & (1 << i))) | |
8774 | continue; | |
83d65738 | 8775 | if (possible_crtc->state->enable) |
a459249c VS |
8776 | continue; |
8777 | /* This can occur when applying the pipe A quirk on resume. */ | |
8778 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8779 | continue; | |
8780 | ||
8781 | crtc = possible_crtc; | |
8782 | break; | |
79e53945 JB |
8783 | } |
8784 | ||
8785 | /* | |
8786 | * If we didn't find an unused CRTC, don't use any. | |
8787 | */ | |
8788 | if (!crtc) { | |
7173188d | 8789 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8790 | goto fail_unlock; |
79e53945 JB |
8791 | } |
8792 | ||
51fd371b RC |
8793 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8794 | if (ret) | |
4d02e2de DV |
8795 | goto fail_unlock; |
8796 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8797 | if (ret) | |
51fd371b | 8798 | goto fail_unlock; |
fc303101 DV |
8799 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8800 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8801 | |
8802 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 8803 | intel_crtc->new_enabled = true; |
6e3c9717 | 8804 | intel_crtc->new_config = intel_crtc->config; |
24218aac | 8805 | old->dpms_mode = connector->dpms; |
8261b191 | 8806 | old->load_detect_temp = true; |
d2dff872 | 8807 | old->release_fb = NULL; |
79e53945 | 8808 | |
6492711d CW |
8809 | if (!mode) |
8810 | mode = &load_detect_mode; | |
79e53945 | 8811 | |
d2dff872 CW |
8812 | /* We need a framebuffer large enough to accommodate all accesses |
8813 | * that the plane may generate whilst we perform load detection. | |
8814 | * We can not rely on the fbcon either being present (we get called | |
8815 | * during its initialisation to detect all boot displays, or it may | |
8816 | * not even exist) or that it is large enough to satisfy the | |
8817 | * requested mode. | |
8818 | */ | |
94352cf9 DV |
8819 | fb = mode_fits_in_fbdev(dev, mode); |
8820 | if (fb == NULL) { | |
d2dff872 | 8821 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8822 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8823 | old->release_fb = fb; | |
d2dff872 CW |
8824 | } else |
8825 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8826 | if (IS_ERR(fb)) { |
d2dff872 | 8827 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8828 | goto fail; |
79e53945 | 8829 | } |
79e53945 | 8830 | |
c0c36b94 | 8831 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8832 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8833 | if (old->release_fb) |
8834 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8835 | goto fail; |
79e53945 | 8836 | } |
7173188d | 8837 | |
79e53945 | 8838 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8839 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8840 | return true; |
412b61d8 VS |
8841 | |
8842 | fail: | |
83d65738 | 8843 | intel_crtc->new_enabled = crtc->state->enable; |
412b61d8 | 8844 | if (intel_crtc->new_enabled) |
6e3c9717 | 8845 | intel_crtc->new_config = intel_crtc->config; |
412b61d8 VS |
8846 | else |
8847 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8848 | fail_unlock: |
8849 | if (ret == -EDEADLK) { | |
8850 | drm_modeset_backoff(ctx); | |
8851 | goto retry; | |
8852 | } | |
8853 | ||
412b61d8 | 8854 | return false; |
79e53945 JB |
8855 | } |
8856 | ||
d2434ab7 | 8857 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8858 | struct intel_load_detect_pipe *old) |
79e53945 | 8859 | { |
d2434ab7 DV |
8860 | struct intel_encoder *intel_encoder = |
8861 | intel_attached_encoder(connector); | |
4ef69c7a | 8862 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8863 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8864 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8865 | |
d2dff872 | 8866 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8867 | connector->base.id, connector->name, |
8e329a03 | 8868 | encoder->base.id, encoder->name); |
d2dff872 | 8869 | |
8261b191 | 8870 | if (old->load_detect_temp) { |
fc303101 DV |
8871 | to_intel_connector(connector)->new_encoder = NULL; |
8872 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8873 | intel_crtc->new_enabled = false; |
8874 | intel_crtc->new_config = NULL; | |
fc303101 | 8875 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8876 | |
36206361 DV |
8877 | if (old->release_fb) { |
8878 | drm_framebuffer_unregister_private(old->release_fb); | |
8879 | drm_framebuffer_unreference(old->release_fb); | |
8880 | } | |
d2dff872 | 8881 | |
0622a53c | 8882 | return; |
79e53945 JB |
8883 | } |
8884 | ||
c751ce4f | 8885 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8886 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8887 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8888 | } |
8889 | ||
da4a1efa | 8890 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 8891 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
8892 | { |
8893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8894 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8895 | ||
8896 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8897 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8898 | else if (HAS_PCH_SPLIT(dev)) |
8899 | return 120000; | |
8900 | else if (!IS_GEN2(dev)) | |
8901 | return 96000; | |
8902 | else | |
8903 | return 48000; | |
8904 | } | |
8905 | ||
79e53945 | 8906 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 8907 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8908 | struct intel_crtc_state *pipe_config) |
79e53945 | 8909 | { |
f1f644dc | 8910 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8911 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8912 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8913 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8914 | u32 fp; |
8915 | intel_clock_t clock; | |
da4a1efa | 8916 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8917 | |
8918 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8919 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8920 | else |
293623f7 | 8921 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8922 | |
8923 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8924 | if (IS_PINEVIEW(dev)) { |
8925 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8926 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8927 | } else { |
8928 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8929 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8930 | } | |
8931 | ||
a6c45cf0 | 8932 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8933 | if (IS_PINEVIEW(dev)) |
8934 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8935 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8936 | else |
8937 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8938 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8939 | ||
8940 | switch (dpll & DPLL_MODE_MASK) { | |
8941 | case DPLLB_MODE_DAC_SERIAL: | |
8942 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8943 | 5 : 10; | |
8944 | break; | |
8945 | case DPLLB_MODE_LVDS: | |
8946 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8947 | 7 : 14; | |
8948 | break; | |
8949 | default: | |
28c97730 | 8950 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8951 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8952 | return; |
79e53945 JB |
8953 | } |
8954 | ||
ac58c3f0 | 8955 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8956 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8957 | else |
da4a1efa | 8958 | i9xx_clock(refclk, &clock); |
79e53945 | 8959 | } else { |
0fb58223 | 8960 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8961 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8962 | |
8963 | if (is_lvds) { | |
8964 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8965 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8966 | |
8967 | if (lvds & LVDS_CLKB_POWER_UP) | |
8968 | clock.p2 = 7; | |
8969 | else | |
8970 | clock.p2 = 14; | |
79e53945 JB |
8971 | } else { |
8972 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8973 | clock.p1 = 2; | |
8974 | else { | |
8975 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8976 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8977 | } | |
8978 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8979 | clock.p2 = 4; | |
8980 | else | |
8981 | clock.p2 = 2; | |
79e53945 | 8982 | } |
da4a1efa VS |
8983 | |
8984 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8985 | } |
8986 | ||
18442d08 VS |
8987 | /* |
8988 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8989 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8990 | * encoder's get_config() function. |
8991 | */ | |
8992 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8993 | } |
8994 | ||
6878da05 VS |
8995 | int intel_dotclock_calculate(int link_freq, |
8996 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8997 | { |
f1f644dc JB |
8998 | /* |
8999 | * The calculation for the data clock is: | |
1041a02f | 9000 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9001 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9002 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9003 | * |
9004 | * and the link clock is simpler: | |
1041a02f | 9005 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9006 | */ |
9007 | ||
6878da05 VS |
9008 | if (!m_n->link_n) |
9009 | return 0; | |
f1f644dc | 9010 | |
6878da05 VS |
9011 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9012 | } | |
f1f644dc | 9013 | |
18442d08 | 9014 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9015 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9016 | { |
9017 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9018 | |
18442d08 VS |
9019 | /* read out port_clock from the DPLL */ |
9020 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9021 | |
f1f644dc | 9022 | /* |
18442d08 | 9023 | * This value does not include pixel_multiplier. |
241bfc38 | 9024 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9025 | * agree once we know their relationship in the encoder's |
9026 | * get_config() function. | |
79e53945 | 9027 | */ |
2d112de7 | 9028 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9029 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9030 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9031 | } |
9032 | ||
9033 | /** Returns the currently programmed mode of the given pipe. */ | |
9034 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9035 | struct drm_crtc *crtc) | |
9036 | { | |
548f245b | 9037 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9039 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9040 | struct drm_display_mode *mode; |
5cec258b | 9041 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9042 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9043 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9044 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9045 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9046 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9047 | |
9048 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9049 | if (!mode) | |
9050 | return NULL; | |
9051 | ||
f1f644dc JB |
9052 | /* |
9053 | * Construct a pipe_config sufficient for getting the clock info | |
9054 | * back out of crtc_clock_get. | |
9055 | * | |
9056 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9057 | * to use a real value here instead. | |
9058 | */ | |
293623f7 | 9059 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9060 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9061 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9062 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9063 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9064 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9065 | ||
773ae034 | 9066 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9067 | mode->hdisplay = (htot & 0xffff) + 1; |
9068 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9069 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9070 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9071 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9072 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9073 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9074 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9075 | ||
9076 | drm_mode_set_name(mode); | |
79e53945 JB |
9077 | |
9078 | return mode; | |
9079 | } | |
9080 | ||
652c393a JB |
9081 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9082 | { | |
9083 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9084 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9086 | |
baff296c | 9087 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9088 | return; |
9089 | ||
9090 | if (!dev_priv->lvds_downclock_avail) | |
9091 | return; | |
9092 | ||
9093 | /* | |
9094 | * Since this is called by a timer, we should never get here in | |
9095 | * the manual case. | |
9096 | */ | |
9097 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9098 | int pipe = intel_crtc->pipe; |
9099 | int dpll_reg = DPLL(pipe); | |
9100 | int dpll; | |
f6e5b160 | 9101 | |
44d98a61 | 9102 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9103 | |
8ac5a6d5 | 9104 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9105 | |
dc257cf1 | 9106 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9107 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9108 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9109 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9110 | dpll = I915_READ(dpll_reg); |
9111 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9112 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9113 | } |
9114 | ||
9115 | } | |
9116 | ||
f047e395 CW |
9117 | void intel_mark_busy(struct drm_device *dev) |
9118 | { | |
c67a470b PZ |
9119 | struct drm_i915_private *dev_priv = dev->dev_private; |
9120 | ||
f62a0076 CW |
9121 | if (dev_priv->mm.busy) |
9122 | return; | |
9123 | ||
43694d69 | 9124 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9125 | i915_update_gfx_val(dev_priv); |
f62a0076 | 9126 | dev_priv->mm.busy = true; |
f047e395 CW |
9127 | } |
9128 | ||
9129 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9130 | { |
c67a470b | 9131 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9132 | struct drm_crtc *crtc; |
652c393a | 9133 | |
f62a0076 CW |
9134 | if (!dev_priv->mm.busy) |
9135 | return; | |
9136 | ||
9137 | dev_priv->mm.busy = false; | |
9138 | ||
d330a953 | 9139 | if (!i915.powersave) |
bb4cdd53 | 9140 | goto out; |
652c393a | 9141 | |
70e1e0ec | 9142 | for_each_crtc(dev, crtc) { |
f4510a27 | 9143 | if (!crtc->primary->fb) |
652c393a JB |
9144 | continue; |
9145 | ||
725a5b54 | 9146 | intel_decrease_pllclock(crtc); |
652c393a | 9147 | } |
b29c19b6 | 9148 | |
3d13ef2e | 9149 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9150 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
9151 | |
9152 | out: | |
43694d69 | 9153 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9154 | } |
9155 | ||
f5de6e07 ACO |
9156 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9157 | struct intel_crtc_state *crtc_state) | |
9158 | { | |
9159 | kfree(crtc->config); | |
9160 | crtc->config = crtc_state; | |
16f3f658 | 9161 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9162 | } |
9163 | ||
79e53945 JB |
9164 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9165 | { | |
9166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9167 | struct drm_device *dev = crtc->dev; |
9168 | struct intel_unpin_work *work; | |
67e77c5a | 9169 | |
5e2d7afc | 9170 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9171 | work = intel_crtc->unpin_work; |
9172 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9173 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9174 | |
9175 | if (work) { | |
9176 | cancel_work_sync(&work->work); | |
9177 | kfree(work); | |
9178 | } | |
79e53945 | 9179 | |
f5de6e07 | 9180 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9181 | drm_crtc_cleanup(crtc); |
67e77c5a | 9182 | |
79e53945 JB |
9183 | kfree(intel_crtc); |
9184 | } | |
9185 | ||
6b95a207 KH |
9186 | static void intel_unpin_work_fn(struct work_struct *__work) |
9187 | { | |
9188 | struct intel_unpin_work *work = | |
9189 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9190 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9191 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9192 | |
b4a98e57 | 9193 | mutex_lock(&dev->struct_mutex); |
ab8d6675 | 9194 | intel_unpin_fb_obj(intel_fb_obj(work->old_fb)); |
05394f39 | 9195 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
ab8d6675 | 9196 | drm_framebuffer_unreference(work->old_fb); |
d9e86c0e | 9197 | |
7ff0ebcc | 9198 | intel_fbc_update(dev); |
f06cc1b9 JH |
9199 | |
9200 | if (work->flip_queued_req) | |
146d84f0 | 9201 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9202 | mutex_unlock(&dev->struct_mutex); |
9203 | ||
f99d7069 DV |
9204 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9205 | ||
b4a98e57 CW |
9206 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9207 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9208 | ||
6b95a207 KH |
9209 | kfree(work); |
9210 | } | |
9211 | ||
1afe3e9d | 9212 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9213 | struct drm_crtc *crtc) |
6b95a207 | 9214 | { |
6b95a207 KH |
9215 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9216 | struct intel_unpin_work *work; | |
6b95a207 KH |
9217 | unsigned long flags; |
9218 | ||
9219 | /* Ignore early vblank irqs */ | |
9220 | if (intel_crtc == NULL) | |
9221 | return; | |
9222 | ||
f326038a DV |
9223 | /* |
9224 | * This is called both by irq handlers and the reset code (to complete | |
9225 | * lost pageflips) so needs the full irqsave spinlocks. | |
9226 | */ | |
6b95a207 KH |
9227 | spin_lock_irqsave(&dev->event_lock, flags); |
9228 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9229 | |
9230 | /* Ensure we don't miss a work->pending update ... */ | |
9231 | smp_rmb(); | |
9232 | ||
9233 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9234 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9235 | return; | |
9236 | } | |
9237 | ||
d6bbafa1 | 9238 | page_flip_completed(intel_crtc); |
0af7e4df | 9239 | |
6b95a207 | 9240 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9241 | } |
9242 | ||
1afe3e9d JB |
9243 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9244 | { | |
fbee40df | 9245 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9246 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9247 | ||
49b14a5c | 9248 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9249 | } |
9250 | ||
9251 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9252 | { | |
fbee40df | 9253 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9254 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9255 | ||
49b14a5c | 9256 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9257 | } |
9258 | ||
75f7f3ec VS |
9259 | /* Is 'a' after or equal to 'b'? */ |
9260 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9261 | { | |
9262 | return !((a - b) & 0x80000000); | |
9263 | } | |
9264 | ||
9265 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9266 | { | |
9267 | struct drm_device *dev = crtc->base.dev; | |
9268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9269 | ||
bdfa7542 VS |
9270 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9271 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9272 | return true; | |
9273 | ||
75f7f3ec VS |
9274 | /* |
9275 | * The relevant registers doen't exist on pre-ctg. | |
9276 | * As the flip done interrupt doesn't trigger for mmio | |
9277 | * flips on gmch platforms, a flip count check isn't | |
9278 | * really needed there. But since ctg has the registers, | |
9279 | * include it in the check anyway. | |
9280 | */ | |
9281 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9282 | return true; | |
9283 | ||
9284 | /* | |
9285 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9286 | * used the same base address. In that case the mmio flip might | |
9287 | * have completed, but the CS hasn't even executed the flip yet. | |
9288 | * | |
9289 | * A flip count check isn't enough as the CS might have updated | |
9290 | * the base address just after start of vblank, but before we | |
9291 | * managed to process the interrupt. This means we'd complete the | |
9292 | * CS flip too soon. | |
9293 | * | |
9294 | * Combining both checks should get us a good enough result. It may | |
9295 | * still happen that the CS flip has been executed, but has not | |
9296 | * yet actually completed. But in case the base address is the same | |
9297 | * anyway, we don't really care. | |
9298 | */ | |
9299 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9300 | crtc->unpin_work->gtt_offset && | |
9301 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9302 | crtc->unpin_work->flip_count); | |
9303 | } | |
9304 | ||
6b95a207 KH |
9305 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9306 | { | |
fbee40df | 9307 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9308 | struct intel_crtc *intel_crtc = |
9309 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9310 | unsigned long flags; | |
9311 | ||
f326038a DV |
9312 | |
9313 | /* | |
9314 | * This is called both by irq handlers and the reset code (to complete | |
9315 | * lost pageflips) so needs the full irqsave spinlocks. | |
9316 | * | |
9317 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9318 | * generate a page-flip completion irq, i.e. every modeset |
9319 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9320 | */ | |
6b95a207 | 9321 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9322 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9323 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9324 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9325 | } | |
9326 | ||
eba905b2 | 9327 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9328 | { |
9329 | /* Ensure that the work item is consistent when activating it ... */ | |
9330 | smp_wmb(); | |
9331 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9332 | /* and that it is marked active as soon as the irq could fire. */ | |
9333 | smp_wmb(); | |
9334 | } | |
9335 | ||
8c9f3aaf JB |
9336 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9337 | struct drm_crtc *crtc, | |
9338 | struct drm_framebuffer *fb, | |
ed8d1975 | 9339 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9340 | struct intel_engine_cs *ring, |
ed8d1975 | 9341 | uint32_t flags) |
8c9f3aaf | 9342 | { |
8c9f3aaf | 9343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9344 | u32 flip_mask; |
9345 | int ret; | |
9346 | ||
6d90c952 | 9347 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9348 | if (ret) |
4fa62c89 | 9349 | return ret; |
8c9f3aaf JB |
9350 | |
9351 | /* Can't queue multiple flips, so wait for the previous | |
9352 | * one to finish before executing the next. | |
9353 | */ | |
9354 | if (intel_crtc->plane) | |
9355 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9356 | else | |
9357 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9358 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9359 | intel_ring_emit(ring, MI_NOOP); | |
9360 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9361 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9362 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9363 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9364 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9365 | |
9366 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9367 | __intel_ring_advance(ring); |
83d4092b | 9368 | return 0; |
8c9f3aaf JB |
9369 | } |
9370 | ||
9371 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9372 | struct drm_crtc *crtc, | |
9373 | struct drm_framebuffer *fb, | |
ed8d1975 | 9374 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9375 | struct intel_engine_cs *ring, |
ed8d1975 | 9376 | uint32_t flags) |
8c9f3aaf | 9377 | { |
8c9f3aaf | 9378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9379 | u32 flip_mask; |
9380 | int ret; | |
9381 | ||
6d90c952 | 9382 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9383 | if (ret) |
4fa62c89 | 9384 | return ret; |
8c9f3aaf JB |
9385 | |
9386 | if (intel_crtc->plane) | |
9387 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9388 | else | |
9389 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9390 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9391 | intel_ring_emit(ring, MI_NOOP); | |
9392 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9393 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9394 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9395 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9396 | intel_ring_emit(ring, MI_NOOP); |
9397 | ||
e7d841ca | 9398 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9399 | __intel_ring_advance(ring); |
83d4092b | 9400 | return 0; |
8c9f3aaf JB |
9401 | } |
9402 | ||
9403 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9404 | struct drm_crtc *crtc, | |
9405 | struct drm_framebuffer *fb, | |
ed8d1975 | 9406 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9407 | struct intel_engine_cs *ring, |
ed8d1975 | 9408 | uint32_t flags) |
8c9f3aaf JB |
9409 | { |
9410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9411 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9412 | uint32_t pf, pipesrc; | |
9413 | int ret; | |
9414 | ||
6d90c952 | 9415 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9416 | if (ret) |
4fa62c89 | 9417 | return ret; |
8c9f3aaf JB |
9418 | |
9419 | /* i965+ uses the linear or tiled offsets from the | |
9420 | * Display Registers (which do not change across a page-flip) | |
9421 | * so we need only reprogram the base address. | |
9422 | */ | |
6d90c952 DV |
9423 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9424 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9425 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9426 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9427 | obj->tiling_mode); |
8c9f3aaf JB |
9428 | |
9429 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9430 | * untested on non-native modes, so ignore it for now. | |
9431 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9432 | */ | |
9433 | pf = 0; | |
9434 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9435 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9436 | |
9437 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9438 | __intel_ring_advance(ring); |
83d4092b | 9439 | return 0; |
8c9f3aaf JB |
9440 | } |
9441 | ||
9442 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9443 | struct drm_crtc *crtc, | |
9444 | struct drm_framebuffer *fb, | |
ed8d1975 | 9445 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9446 | struct intel_engine_cs *ring, |
ed8d1975 | 9447 | uint32_t flags) |
8c9f3aaf JB |
9448 | { |
9449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9450 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9451 | uint32_t pf, pipesrc; | |
9452 | int ret; | |
9453 | ||
6d90c952 | 9454 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9455 | if (ret) |
4fa62c89 | 9456 | return ret; |
8c9f3aaf | 9457 | |
6d90c952 DV |
9458 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9459 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9460 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9461 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9462 | |
dc257cf1 DV |
9463 | /* Contrary to the suggestions in the documentation, |
9464 | * "Enable Panel Fitter" does not seem to be required when page | |
9465 | * flipping with a non-native mode, and worse causes a normal | |
9466 | * modeset to fail. | |
9467 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9468 | */ | |
9469 | pf = 0; | |
8c9f3aaf | 9470 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9471 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9472 | |
9473 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9474 | __intel_ring_advance(ring); |
83d4092b | 9475 | return 0; |
8c9f3aaf JB |
9476 | } |
9477 | ||
7c9017e5 JB |
9478 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9479 | struct drm_crtc *crtc, | |
9480 | struct drm_framebuffer *fb, | |
ed8d1975 | 9481 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9482 | struct intel_engine_cs *ring, |
ed8d1975 | 9483 | uint32_t flags) |
7c9017e5 | 9484 | { |
7c9017e5 | 9485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9486 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9487 | int len, ret; |
9488 | ||
eba905b2 | 9489 | switch (intel_crtc->plane) { |
cb05d8de DV |
9490 | case PLANE_A: |
9491 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9492 | break; | |
9493 | case PLANE_B: | |
9494 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9495 | break; | |
9496 | case PLANE_C: | |
9497 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9498 | break; | |
9499 | default: | |
9500 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9501 | return -ENODEV; |
cb05d8de DV |
9502 | } |
9503 | ||
ffe74d75 | 9504 | len = 4; |
f476828a | 9505 | if (ring->id == RCS) { |
ffe74d75 | 9506 | len += 6; |
f476828a DL |
9507 | /* |
9508 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9509 | * 48bits addresses, and we need a NOOP for the batch size to | |
9510 | * stay even. | |
9511 | */ | |
9512 | if (IS_GEN8(dev)) | |
9513 | len += 2; | |
9514 | } | |
ffe74d75 | 9515 | |
f66fab8e VS |
9516 | /* |
9517 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9518 | * "The full packet must be contained within the same cache line." | |
9519 | * | |
9520 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9521 | * cacheline, if we ever start emitting more commands before | |
9522 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9523 | * then do the cacheline alignment, and finally emit the | |
9524 | * MI_DISPLAY_FLIP. | |
9525 | */ | |
9526 | ret = intel_ring_cacheline_align(ring); | |
9527 | if (ret) | |
4fa62c89 | 9528 | return ret; |
f66fab8e | 9529 | |
ffe74d75 | 9530 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9531 | if (ret) |
4fa62c89 | 9532 | return ret; |
7c9017e5 | 9533 | |
ffe74d75 CW |
9534 | /* Unmask the flip-done completion message. Note that the bspec says that |
9535 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9536 | * more than one flip event at any time (or ensure that one flip message | |
9537 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9538 | * Experimentation says that BCS works despite DERRMR masking all | |
9539 | * flip-done completion events and that unmasking all planes at once | |
9540 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9541 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9542 | */ | |
9543 | if (ring->id == RCS) { | |
9544 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9545 | intel_ring_emit(ring, DERRMR); | |
9546 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9547 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9548 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9549 | if (IS_GEN8(dev)) |
9550 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9551 | MI_SRM_LRM_GLOBAL_GTT); | |
9552 | else | |
9553 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9554 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9555 | intel_ring_emit(ring, DERRMR); |
9556 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9557 | if (IS_GEN8(dev)) { |
9558 | intel_ring_emit(ring, 0); | |
9559 | intel_ring_emit(ring, MI_NOOP); | |
9560 | } | |
ffe74d75 CW |
9561 | } |
9562 | ||
cb05d8de | 9563 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9564 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9565 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9566 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9567 | |
9568 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9569 | __intel_ring_advance(ring); |
83d4092b | 9570 | return 0; |
7c9017e5 JB |
9571 | } |
9572 | ||
84c33a64 SG |
9573 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9574 | struct drm_i915_gem_object *obj) | |
9575 | { | |
9576 | /* | |
9577 | * This is not being used for older platforms, because | |
9578 | * non-availability of flip done interrupt forces us to use | |
9579 | * CS flips. Older platforms derive flip done using some clever | |
9580 | * tricks involving the flip_pending status bits and vblank irqs. | |
9581 | * So using MMIO flips there would disrupt this mechanism. | |
9582 | */ | |
9583 | ||
8e09bf83 CW |
9584 | if (ring == NULL) |
9585 | return true; | |
9586 | ||
84c33a64 SG |
9587 | if (INTEL_INFO(ring->dev)->gen < 5) |
9588 | return false; | |
9589 | ||
9590 | if (i915.use_mmio_flip < 0) | |
9591 | return false; | |
9592 | else if (i915.use_mmio_flip > 0) | |
9593 | return true; | |
14bf993e OM |
9594 | else if (i915.enable_execlists) |
9595 | return true; | |
84c33a64 | 9596 | else |
41c52415 | 9597 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9598 | } |
9599 | ||
ff944564 DL |
9600 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9601 | { | |
9602 | struct drm_device *dev = intel_crtc->base.dev; | |
9603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9604 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9605 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9606 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9607 | const enum pipe pipe = intel_crtc->pipe; | |
9608 | u32 ctl, stride; | |
9609 | ||
9610 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9611 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9612 | if (obj->tiling_mode == I915_TILING_X) | |
9613 | ctl |= PLANE_CTL_TILED_X; | |
9614 | ||
9615 | /* | |
9616 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9617 | * linear buffers or in number of tiles for tiled buffers. | |
9618 | */ | |
9619 | stride = fb->pitches[0] >> 6; | |
9620 | if (obj->tiling_mode == I915_TILING_X) | |
9621 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9622 | ||
9623 | /* | |
9624 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9625 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9626 | */ | |
9627 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9628 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9629 | ||
9630 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9631 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9632 | } | |
9633 | ||
9634 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9635 | { |
9636 | struct drm_device *dev = intel_crtc->base.dev; | |
9637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9638 | struct intel_framebuffer *intel_fb = | |
9639 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9640 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9641 | u32 dspcntr; | |
9642 | u32 reg; | |
9643 | ||
84c33a64 SG |
9644 | reg = DSPCNTR(intel_crtc->plane); |
9645 | dspcntr = I915_READ(reg); | |
9646 | ||
c5d97472 DL |
9647 | if (obj->tiling_mode != I915_TILING_NONE) |
9648 | dspcntr |= DISPPLANE_TILED; | |
9649 | else | |
9650 | dspcntr &= ~DISPPLANE_TILED; | |
9651 | ||
84c33a64 SG |
9652 | I915_WRITE(reg, dspcntr); |
9653 | ||
9654 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9655 | intel_crtc->unpin_work->gtt_offset); | |
9656 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9657 | |
ff944564 DL |
9658 | } |
9659 | ||
9660 | /* | |
9661 | * XXX: This is the temporary way to update the plane registers until we get | |
9662 | * around to using the usual plane update functions for MMIO flips | |
9663 | */ | |
9664 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9665 | { | |
9666 | struct drm_device *dev = intel_crtc->base.dev; | |
9667 | bool atomic_update; | |
9668 | u32 start_vbl_count; | |
9669 | ||
9670 | intel_mark_page_flip_active(intel_crtc); | |
9671 | ||
9672 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9673 | ||
9674 | if (INTEL_INFO(dev)->gen >= 9) | |
9675 | skl_do_mmio_flip(intel_crtc); | |
9676 | else | |
9677 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9678 | ilk_do_mmio_flip(intel_crtc); | |
9679 | ||
9362c7c5 ACO |
9680 | if (atomic_update) |
9681 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9682 | } |
9683 | ||
9362c7c5 | 9684 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9685 | { |
cc8c4cc2 | 9686 | struct intel_crtc *crtc = |
9362c7c5 | 9687 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9688 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9689 | |
cc8c4cc2 JH |
9690 | mmio_flip = &crtc->mmio_flip; |
9691 | if (mmio_flip->req) | |
9c654818 JH |
9692 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9693 | crtc->reset_counter, | |
9694 | false, NULL, NULL) != 0); | |
84c33a64 | 9695 | |
cc8c4cc2 JH |
9696 | intel_do_mmio_flip(crtc); |
9697 | if (mmio_flip->req) { | |
9698 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 9699 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
9700 | mutex_unlock(&crtc->base.dev->struct_mutex); |
9701 | } | |
84c33a64 SG |
9702 | } |
9703 | ||
9704 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9705 | struct drm_crtc *crtc, | |
9706 | struct drm_framebuffer *fb, | |
9707 | struct drm_i915_gem_object *obj, | |
9708 | struct intel_engine_cs *ring, | |
9709 | uint32_t flags) | |
9710 | { | |
84c33a64 | 9711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9712 | |
cc8c4cc2 JH |
9713 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9714 | obj->last_write_req); | |
536f5b5e ACO |
9715 | |
9716 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9717 | |
84c33a64 SG |
9718 | return 0; |
9719 | } | |
9720 | ||
8c9f3aaf JB |
9721 | static int intel_default_queue_flip(struct drm_device *dev, |
9722 | struct drm_crtc *crtc, | |
9723 | struct drm_framebuffer *fb, | |
ed8d1975 | 9724 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9725 | struct intel_engine_cs *ring, |
ed8d1975 | 9726 | uint32_t flags) |
8c9f3aaf JB |
9727 | { |
9728 | return -ENODEV; | |
9729 | } | |
9730 | ||
d6bbafa1 CW |
9731 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9732 | struct drm_crtc *crtc) | |
9733 | { | |
9734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9735 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9736 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9737 | u32 addr; | |
9738 | ||
9739 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9740 | return true; | |
9741 | ||
9742 | if (!work->enable_stall_check) | |
9743 | return false; | |
9744 | ||
9745 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9746 | if (work->flip_queued_req && |
9747 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
9748 | return false; |
9749 | ||
1e3feefd | 9750 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
9751 | } |
9752 | ||
1e3feefd | 9753 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
9754 | return false; |
9755 | ||
9756 | /* Potential stall - if we see that the flip has happened, | |
9757 | * assume a missed interrupt. */ | |
9758 | if (INTEL_INFO(dev)->gen >= 4) | |
9759 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9760 | else | |
9761 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9762 | ||
9763 | /* There is a potential issue here with a false positive after a flip | |
9764 | * to the same address. We could address this by checking for a | |
9765 | * non-incrementing frame counter. | |
9766 | */ | |
9767 | return addr == work->gtt_offset; | |
9768 | } | |
9769 | ||
9770 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9771 | { | |
9772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9773 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a DV |
9775 | |
9776 | WARN_ON(!in_irq()); | |
d6bbafa1 CW |
9777 | |
9778 | if (crtc == NULL) | |
9779 | return; | |
9780 | ||
f326038a | 9781 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
9782 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
9783 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
1e3feefd DV |
9784 | intel_crtc->unpin_work->flip_queued_vblank, |
9785 | drm_vblank_count(dev, pipe)); | |
d6bbafa1 CW |
9786 | page_flip_completed(intel_crtc); |
9787 | } | |
f326038a | 9788 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
9789 | } |
9790 | ||
6b95a207 KH |
9791 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9792 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9793 | struct drm_pending_vblank_event *event, |
9794 | uint32_t page_flip_flags) | |
6b95a207 KH |
9795 | { |
9796 | struct drm_device *dev = crtc->dev; | |
9797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9798 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9799 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9800 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 9801 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 9802 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9803 | struct intel_unpin_work *work; |
a4872ba6 | 9804 | struct intel_engine_cs *ring; |
52e68630 | 9805 | int ret; |
6b95a207 | 9806 | |
2ff8fde1 MR |
9807 | /* |
9808 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9809 | * check to be safe. In the future we may enable pageflipping from | |
9810 | * a disabled primary plane. | |
9811 | */ | |
9812 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9813 | return -EBUSY; | |
9814 | ||
e6a595d2 | 9815 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9816 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9817 | return -EINVAL; |
9818 | ||
9819 | /* | |
9820 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9821 | * Note that pitch changes could also affect these register. | |
9822 | */ | |
9823 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9824 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9825 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9826 | return -EINVAL; |
9827 | ||
f900db47 CW |
9828 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9829 | goto out_hang; | |
9830 | ||
b14c5679 | 9831 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9832 | if (work == NULL) |
9833 | return -ENOMEM; | |
9834 | ||
6b95a207 | 9835 | work->event = event; |
b4a98e57 | 9836 | work->crtc = crtc; |
ab8d6675 | 9837 | work->old_fb = old_fb; |
6b95a207 KH |
9838 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9839 | ||
87b6b101 | 9840 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9841 | if (ret) |
9842 | goto free_work; | |
9843 | ||
6b95a207 | 9844 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 9845 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 9846 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
9847 | /* Before declaring the flip queue wedged, check if |
9848 | * the hardware completed the operation behind our backs. | |
9849 | */ | |
9850 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9851 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9852 | page_flip_completed(intel_crtc); | |
9853 | } else { | |
9854 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 9855 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 9856 | |
d6bbafa1 CW |
9857 | drm_crtc_vblank_put(crtc); |
9858 | kfree(work); | |
9859 | return -EBUSY; | |
9860 | } | |
6b95a207 KH |
9861 | } |
9862 | intel_crtc->unpin_work = work; | |
5e2d7afc | 9863 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 9864 | |
b4a98e57 CW |
9865 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9866 | flush_workqueue(dev_priv->wq); | |
9867 | ||
79158103 CW |
9868 | ret = i915_mutex_lock_interruptible(dev); |
9869 | if (ret) | |
9870 | goto cleanup; | |
6b95a207 | 9871 | |
75dfca80 | 9872 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 9873 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 9874 | drm_gem_object_reference(&obj->base); |
6b95a207 | 9875 | |
f4510a27 | 9876 | crtc->primary->fb = fb; |
afd65eb4 | 9877 | update_state_fb(crtc->primary); |
1ed1f968 | 9878 | |
e1f99ce6 | 9879 | work->pending_flip_obj = obj; |
e1f99ce6 | 9880 | |
b4a98e57 | 9881 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9882 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9883 | |
75f7f3ec | 9884 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9885 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9886 | |
4fa62c89 VS |
9887 | if (IS_VALLEYVIEW(dev)) { |
9888 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 9889 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
9890 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
9891 | ring = NULL; | |
48bf5b2d | 9892 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 9893 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 9894 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 9895 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
9896 | if (ring == NULL || ring->id != RCS) |
9897 | ring = &dev_priv->ring[BCS]; | |
9898 | } else { | |
9899 | ring = &dev_priv->ring[RCS]; | |
9900 | } | |
9901 | ||
850c4cdc | 9902 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring); |
8c9f3aaf JB |
9903 | if (ret) |
9904 | goto cleanup_pending; | |
6b95a207 | 9905 | |
4fa62c89 VS |
9906 | work->gtt_offset = |
9907 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9908 | ||
d6bbafa1 | 9909 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
9910 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
9911 | page_flip_flags); | |
d6bbafa1 CW |
9912 | if (ret) |
9913 | goto cleanup_unpin; | |
9914 | ||
f06cc1b9 JH |
9915 | i915_gem_request_assign(&work->flip_queued_req, |
9916 | obj->last_write_req); | |
d6bbafa1 | 9917 | } else { |
84c33a64 | 9918 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
9919 | page_flip_flags); |
9920 | if (ret) | |
9921 | goto cleanup_unpin; | |
9922 | ||
f06cc1b9 JH |
9923 | i915_gem_request_assign(&work->flip_queued_req, |
9924 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
9925 | } |
9926 | ||
1e3feefd | 9927 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 9928 | work->enable_stall_check = true; |
4fa62c89 | 9929 | |
ab8d6675 | 9930 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
9931 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9932 | ||
7ff0ebcc | 9933 | intel_fbc_disable(dev); |
f99d7069 | 9934 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9935 | mutex_unlock(&dev->struct_mutex); |
9936 | ||
e5510fac JB |
9937 | trace_i915_flip_request(intel_crtc->plane, obj); |
9938 | ||
6b95a207 | 9939 | return 0; |
96b099fd | 9940 | |
4fa62c89 VS |
9941 | cleanup_unpin: |
9942 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9943 | cleanup_pending: |
b4a98e57 | 9944 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9945 | crtc->primary->fb = old_fb; |
afd65eb4 | 9946 | update_state_fb(crtc->primary); |
ab8d6675 | 9947 | drm_framebuffer_unreference(work->old_fb); |
05394f39 | 9948 | drm_gem_object_unreference(&obj->base); |
96b099fd CW |
9949 | mutex_unlock(&dev->struct_mutex); |
9950 | ||
79158103 | 9951 | cleanup: |
5e2d7afc | 9952 | spin_lock_irq(&dev->event_lock); |
96b099fd | 9953 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 9954 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 9955 | |
87b6b101 | 9956 | drm_crtc_vblank_put(crtc); |
7317c75e | 9957 | free_work: |
96b099fd CW |
9958 | kfree(work); |
9959 | ||
f900db47 CW |
9960 | if (ret == -EIO) { |
9961 | out_hang: | |
53a366b9 | 9962 | ret = intel_plane_restore(primary); |
f0d3dad3 | 9963 | if (ret == 0 && event) { |
5e2d7afc | 9964 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 9965 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 9966 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 9967 | } |
f900db47 | 9968 | } |
96b099fd | 9969 | return ret; |
6b95a207 KH |
9970 | } |
9971 | ||
f6e5b160 | 9972 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9973 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9974 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
9975 | .atomic_begin = intel_begin_crtc_commit, |
9976 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
9977 | }; |
9978 | ||
9a935856 DV |
9979 | /** |
9980 | * intel_modeset_update_staged_output_state | |
9981 | * | |
9982 | * Updates the staged output configuration state, e.g. after we've read out the | |
9983 | * current hw state. | |
9984 | */ | |
9985 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9986 | { |
7668851f | 9987 | struct intel_crtc *crtc; |
9a935856 DV |
9988 | struct intel_encoder *encoder; |
9989 | struct intel_connector *connector; | |
f6e5b160 | 9990 | |
9a935856 DV |
9991 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9992 | base.head) { | |
9993 | connector->new_encoder = | |
9994 | to_intel_encoder(connector->base.encoder); | |
9995 | } | |
f6e5b160 | 9996 | |
b2784e15 | 9997 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9998 | encoder->new_crtc = |
9999 | to_intel_crtc(encoder->base.crtc); | |
10000 | } | |
7668851f | 10001 | |
d3fcc808 | 10002 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10003 | crtc->new_enabled = crtc->base.state->enable; |
7bd0a8e7 VS |
10004 | |
10005 | if (crtc->new_enabled) | |
6e3c9717 | 10006 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
10007 | else |
10008 | crtc->new_config = NULL; | |
7668851f | 10009 | } |
f6e5b160 CW |
10010 | } |
10011 | ||
9a935856 DV |
10012 | /** |
10013 | * intel_modeset_commit_output_state | |
10014 | * | |
10015 | * This function copies the stage display pipe configuration to the real one. | |
10016 | */ | |
10017 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10018 | { | |
7668851f | 10019 | struct intel_crtc *crtc; |
9a935856 DV |
10020 | struct intel_encoder *encoder; |
10021 | struct intel_connector *connector; | |
f6e5b160 | 10022 | |
9a935856 DV |
10023 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10024 | base.head) { | |
10025 | connector->base.encoder = &connector->new_encoder->base; | |
10026 | } | |
f6e5b160 | 10027 | |
b2784e15 | 10028 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10029 | encoder->base.crtc = &encoder->new_crtc->base; |
10030 | } | |
7668851f | 10031 | |
d3fcc808 | 10032 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10033 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10034 | crtc->base.enabled = crtc->new_enabled; |
10035 | } | |
9a935856 DV |
10036 | } |
10037 | ||
050f7aeb | 10038 | static void |
eba905b2 | 10039 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10040 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10041 | { |
10042 | int bpp = pipe_config->pipe_bpp; | |
10043 | ||
10044 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10045 | connector->base.base.id, | |
c23cc417 | 10046 | connector->base.name); |
050f7aeb DV |
10047 | |
10048 | /* Don't use an invalid EDID bpc value */ | |
10049 | if (connector->base.display_info.bpc && | |
10050 | connector->base.display_info.bpc * 3 < bpp) { | |
10051 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10052 | bpp, connector->base.display_info.bpc*3); | |
10053 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10054 | } | |
10055 | ||
10056 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10057 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10058 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10059 | bpp); | |
10060 | pipe_config->pipe_bpp = 24; | |
10061 | } | |
10062 | } | |
10063 | ||
4e53c2e0 | 10064 | static int |
050f7aeb DV |
10065 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10066 | struct drm_framebuffer *fb, | |
5cec258b | 10067 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10068 | { |
050f7aeb DV |
10069 | struct drm_device *dev = crtc->base.dev; |
10070 | struct intel_connector *connector; | |
4e53c2e0 DV |
10071 | int bpp; |
10072 | ||
d42264b1 DV |
10073 | switch (fb->pixel_format) { |
10074 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10075 | bpp = 8*3; /* since we go through a colormap */ |
10076 | break; | |
d42264b1 DV |
10077 | case DRM_FORMAT_XRGB1555: |
10078 | case DRM_FORMAT_ARGB1555: | |
10079 | /* checked in intel_framebuffer_init already */ | |
10080 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10081 | return -EINVAL; | |
10082 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10083 | bpp = 6*3; /* min is 18bpp */ |
10084 | break; | |
d42264b1 DV |
10085 | case DRM_FORMAT_XBGR8888: |
10086 | case DRM_FORMAT_ABGR8888: | |
10087 | /* checked in intel_framebuffer_init already */ | |
10088 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10089 | return -EINVAL; | |
10090 | case DRM_FORMAT_XRGB8888: | |
10091 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10092 | bpp = 8*3; |
10093 | break; | |
d42264b1 DV |
10094 | case DRM_FORMAT_XRGB2101010: |
10095 | case DRM_FORMAT_ARGB2101010: | |
10096 | case DRM_FORMAT_XBGR2101010: | |
10097 | case DRM_FORMAT_ABGR2101010: | |
10098 | /* checked in intel_framebuffer_init already */ | |
10099 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10100 | return -EINVAL; |
4e53c2e0 DV |
10101 | bpp = 10*3; |
10102 | break; | |
baba133a | 10103 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10104 | default: |
10105 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10106 | return -EINVAL; | |
10107 | } | |
10108 | ||
4e53c2e0 DV |
10109 | pipe_config->pipe_bpp = bpp; |
10110 | ||
10111 | /* Clamp display bpp to EDID value */ | |
10112 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 10113 | base.head) { |
1b829e05 DV |
10114 | if (!connector->new_encoder || |
10115 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10116 | continue; |
10117 | ||
050f7aeb | 10118 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10119 | } |
10120 | ||
10121 | return bpp; | |
10122 | } | |
10123 | ||
644db711 DV |
10124 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10125 | { | |
10126 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10127 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10128 | mode->crtc_clock, |
644db711 DV |
10129 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10130 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10131 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10132 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10133 | } | |
10134 | ||
c0b03411 | 10135 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10136 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10137 | const char *context) |
10138 | { | |
10139 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10140 | context, pipe_name(crtc->pipe)); | |
10141 | ||
10142 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10143 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10144 | pipe_config->pipe_bpp, pipe_config->dither); | |
10145 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10146 | pipe_config->has_pch_encoder, | |
10147 | pipe_config->fdi_lanes, | |
10148 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10149 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10150 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10151 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10152 | pipe_config->has_dp_encoder, | |
10153 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10154 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10155 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10156 | |
10157 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10158 | pipe_config->has_dp_encoder, | |
10159 | pipe_config->dp_m2_n2.gmch_m, | |
10160 | pipe_config->dp_m2_n2.gmch_n, | |
10161 | pipe_config->dp_m2_n2.link_m, | |
10162 | pipe_config->dp_m2_n2.link_n, | |
10163 | pipe_config->dp_m2_n2.tu); | |
10164 | ||
55072d19 DV |
10165 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10166 | pipe_config->has_audio, | |
10167 | pipe_config->has_infoframe); | |
10168 | ||
c0b03411 | 10169 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10170 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10171 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10172 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10173 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10174 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10175 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10176 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10177 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10178 | pipe_config->gmch_pfit.control, | |
10179 | pipe_config->gmch_pfit.pgm_ratios, | |
10180 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10181 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10182 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10183 | pipe_config->pch_pfit.size, |
10184 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10185 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10186 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10187 | } |
10188 | ||
bc079e8b VS |
10189 | static bool encoders_cloneable(const struct intel_encoder *a, |
10190 | const struct intel_encoder *b) | |
accfc0c5 | 10191 | { |
bc079e8b VS |
10192 | /* masks could be asymmetric, so check both ways */ |
10193 | return a == b || (a->cloneable & (1 << b->type) && | |
10194 | b->cloneable & (1 << a->type)); | |
10195 | } | |
10196 | ||
10197 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10198 | struct intel_encoder *encoder) | |
10199 | { | |
10200 | struct drm_device *dev = crtc->base.dev; | |
10201 | struct intel_encoder *source_encoder; | |
10202 | ||
b2784e15 | 10203 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10204 | if (source_encoder->new_crtc != crtc) |
10205 | continue; | |
10206 | ||
10207 | if (!encoders_cloneable(encoder, source_encoder)) | |
10208 | return false; | |
10209 | } | |
10210 | ||
10211 | return true; | |
10212 | } | |
10213 | ||
10214 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10215 | { | |
10216 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10217 | struct intel_encoder *encoder; |
10218 | ||
b2784e15 | 10219 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10220 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10221 | continue; |
10222 | ||
bc079e8b VS |
10223 | if (!check_single_encoder_cloning(crtc, encoder)) |
10224 | return false; | |
accfc0c5 DV |
10225 | } |
10226 | ||
bc079e8b | 10227 | return true; |
accfc0c5 DV |
10228 | } |
10229 | ||
00f0b378 VS |
10230 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10231 | { | |
10232 | struct intel_connector *connector; | |
10233 | unsigned int used_ports = 0; | |
10234 | ||
10235 | /* | |
10236 | * Walk the connector list instead of the encoder | |
10237 | * list to detect the problem on ddi platforms | |
10238 | * where there's just one encoder per digital port. | |
10239 | */ | |
10240 | list_for_each_entry(connector, | |
10241 | &dev->mode_config.connector_list, base.head) { | |
10242 | struct intel_encoder *encoder = connector->new_encoder; | |
10243 | ||
10244 | if (!encoder) | |
10245 | continue; | |
10246 | ||
10247 | WARN_ON(!encoder->new_crtc); | |
10248 | ||
10249 | switch (encoder->type) { | |
10250 | unsigned int port_mask; | |
10251 | case INTEL_OUTPUT_UNKNOWN: | |
10252 | if (WARN_ON(!HAS_DDI(dev))) | |
10253 | break; | |
10254 | case INTEL_OUTPUT_DISPLAYPORT: | |
10255 | case INTEL_OUTPUT_HDMI: | |
10256 | case INTEL_OUTPUT_EDP: | |
10257 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10258 | ||
10259 | /* the same port mustn't appear more than once */ | |
10260 | if (used_ports & port_mask) | |
10261 | return false; | |
10262 | ||
10263 | used_ports |= port_mask; | |
10264 | default: | |
10265 | break; | |
10266 | } | |
10267 | } | |
10268 | ||
10269 | return true; | |
10270 | } | |
10271 | ||
5cec258b | 10272 | static struct intel_crtc_state * |
b8cecdf5 | 10273 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10274 | struct drm_framebuffer *fb, |
b8cecdf5 | 10275 | struct drm_display_mode *mode) |
ee7b9f93 | 10276 | { |
7758a113 | 10277 | struct drm_device *dev = crtc->dev; |
7758a113 | 10278 | struct intel_encoder *encoder; |
5cec258b | 10279 | struct intel_crtc_state *pipe_config; |
e29c22c0 DV |
10280 | int plane_bpp, ret = -EINVAL; |
10281 | bool retry = true; | |
ee7b9f93 | 10282 | |
bc079e8b | 10283 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10284 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10285 | return ERR_PTR(-EINVAL); | |
10286 | } | |
10287 | ||
00f0b378 VS |
10288 | if (!check_digital_port_conflicts(dev)) { |
10289 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10290 | return ERR_PTR(-EINVAL); | |
10291 | } | |
10292 | ||
b8cecdf5 DV |
10293 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10294 | if (!pipe_config) | |
7758a113 DV |
10295 | return ERR_PTR(-ENOMEM); |
10296 | ||
07878248 | 10297 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10298 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10299 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10300 | |
e143a21c DV |
10301 | pipe_config->cpu_transcoder = |
10302 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10303 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10304 | |
2960bc9c ID |
10305 | /* |
10306 | * Sanitize sync polarity flags based on requested ones. If neither | |
10307 | * positive or negative polarity is requested, treat this as meaning | |
10308 | * negative polarity. | |
10309 | */ | |
2d112de7 | 10310 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10311 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10312 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10313 | |
2d112de7 | 10314 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10315 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10316 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10317 | |
050f7aeb DV |
10318 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10319 | * plane pixel format and any sink constraints into account. Returns the | |
10320 | * source plane bpp so that dithering can be selected on mismatches | |
10321 | * after encoders and crtc also have had their say. */ | |
10322 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10323 | fb, pipe_config); | |
4e53c2e0 DV |
10324 | if (plane_bpp < 0) |
10325 | goto fail; | |
10326 | ||
e41a56be VS |
10327 | /* |
10328 | * Determine the real pipe dimensions. Note that stereo modes can | |
10329 | * increase the actual pipe size due to the frame doubling and | |
10330 | * insertion of additional space for blanks between the frame. This | |
10331 | * is stored in the crtc timings. We use the requested mode to do this | |
10332 | * computation to clearly distinguish it from the adjusted mode, which | |
10333 | * can be changed by the connectors in the below retry loop. | |
10334 | */ | |
2d112de7 | 10335 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10336 | &pipe_config->pipe_src_w, |
10337 | &pipe_config->pipe_src_h); | |
e41a56be | 10338 | |
e29c22c0 | 10339 | encoder_retry: |
ef1b460d | 10340 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10341 | pipe_config->port_clock = 0; |
ef1b460d | 10342 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10343 | |
135c81b8 | 10344 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10345 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10346 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10347 | |
7758a113 DV |
10348 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10349 | * adjust it according to limitations or connector properties, and also | |
10350 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10351 | */ |
b2784e15 | 10352 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10353 | |
7758a113 DV |
10354 | if (&encoder->new_crtc->base != crtc) |
10355 | continue; | |
7ae89233 | 10356 | |
efea6e8e DV |
10357 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10358 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10359 | goto fail; |
10360 | } | |
ee7b9f93 | 10361 | } |
47f1c6c9 | 10362 | |
ff9a6750 DV |
10363 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10364 | * done afterwards in case the encoder adjusts the mode. */ | |
10365 | if (!pipe_config->port_clock) | |
2d112de7 | 10366 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10367 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10368 | |
a43f6e0f | 10369 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10370 | if (ret < 0) { |
7758a113 DV |
10371 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10372 | goto fail; | |
ee7b9f93 | 10373 | } |
e29c22c0 DV |
10374 | |
10375 | if (ret == RETRY) { | |
10376 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10377 | ret = -EINVAL; | |
10378 | goto fail; | |
10379 | } | |
10380 | ||
10381 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10382 | retry = false; | |
10383 | goto encoder_retry; | |
10384 | } | |
10385 | ||
4e53c2e0 DV |
10386 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10387 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10388 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10389 | ||
b8cecdf5 | 10390 | return pipe_config; |
7758a113 | 10391 | fail: |
b8cecdf5 | 10392 | kfree(pipe_config); |
e29c22c0 | 10393 | return ERR_PTR(ret); |
ee7b9f93 | 10394 | } |
47f1c6c9 | 10395 | |
e2e1ed41 DV |
10396 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10397 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10398 | static void | |
10399 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10400 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10401 | { |
10402 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10403 | struct drm_device *dev = crtc->dev; |
10404 | struct intel_encoder *encoder; | |
10405 | struct intel_connector *connector; | |
10406 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10407 | |
e2e1ed41 | 10408 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10409 | |
e2e1ed41 DV |
10410 | /* Check which crtcs have changed outputs connected to them, these need |
10411 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10412 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10413 | * bit set at most. */ | |
10414 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10415 | base.head) { | |
10416 | if (connector->base.encoder == &connector->new_encoder->base) | |
10417 | continue; | |
79e53945 | 10418 | |
e2e1ed41 DV |
10419 | if (connector->base.encoder) { |
10420 | tmp_crtc = connector->base.encoder->crtc; | |
10421 | ||
10422 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10423 | } | |
10424 | ||
10425 | if (connector->new_encoder) | |
10426 | *prepare_pipes |= | |
10427 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10428 | } |
10429 | ||
b2784e15 | 10430 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10431 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10432 | continue; | |
10433 | ||
10434 | if (encoder->base.crtc) { | |
10435 | tmp_crtc = encoder->base.crtc; | |
10436 | ||
10437 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10438 | } | |
10439 | ||
10440 | if (encoder->new_crtc) | |
10441 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10442 | } |
10443 | ||
7668851f | 10444 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10445 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10446 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 10447 | continue; |
7e7d76c3 | 10448 | |
7668851f | 10449 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10450 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10451 | else |
10452 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10453 | } |
10454 | ||
e2e1ed41 DV |
10455 | |
10456 | /* set_mode is also used to update properties on life display pipes. */ | |
10457 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10458 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10459 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10460 | ||
b6c5164d DV |
10461 | /* |
10462 | * For simplicity do a full modeset on any pipe where the output routing | |
10463 | * changed. We could be more clever, but that would require us to be | |
10464 | * more careful with calling the relevant encoder->mode_set functions. | |
10465 | */ | |
e2e1ed41 DV |
10466 | if (*prepare_pipes) |
10467 | *modeset_pipes = *prepare_pipes; | |
10468 | ||
10469 | /* ... and mask these out. */ | |
10470 | *modeset_pipes &= ~(*disable_pipes); | |
10471 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10472 | |
10473 | /* | |
10474 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10475 | * obies this rule, but the modeset restore mode of | |
10476 | * intel_modeset_setup_hw_state does not. | |
10477 | */ | |
10478 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10479 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10480 | |
10481 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10482 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10483 | } |
79e53945 | 10484 | |
ea9d758d | 10485 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10486 | { |
ea9d758d | 10487 | struct drm_encoder *encoder; |
f6e5b160 | 10488 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10489 | |
ea9d758d DV |
10490 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10491 | if (encoder->crtc == crtc) | |
10492 | return true; | |
10493 | ||
10494 | return false; | |
10495 | } | |
10496 | ||
10497 | static void | |
10498 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10499 | { | |
ba41c0de | 10500 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10501 | struct intel_encoder *intel_encoder; |
10502 | struct intel_crtc *intel_crtc; | |
10503 | struct drm_connector *connector; | |
10504 | ||
ba41c0de DV |
10505 | intel_shared_dpll_commit(dev_priv); |
10506 | ||
b2784e15 | 10507 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10508 | if (!intel_encoder->base.crtc) |
10509 | continue; | |
10510 | ||
10511 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10512 | ||
10513 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10514 | intel_encoder->connectors_active = false; | |
10515 | } | |
10516 | ||
10517 | intel_modeset_commit_output_state(dev); | |
10518 | ||
7668851f | 10519 | /* Double check state. */ |
d3fcc808 | 10520 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10521 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 | 10522 | WARN_ON(intel_crtc->new_config && |
6e3c9717 | 10523 | intel_crtc->new_config != intel_crtc->config); |
83d65738 | 10524 | WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); |
ea9d758d DV |
10525 | } |
10526 | ||
10527 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10528 | if (!connector->encoder || !connector->encoder->crtc) | |
10529 | continue; | |
10530 | ||
10531 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10532 | ||
10533 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10534 | struct drm_property *dpms_property = |
10535 | dev->mode_config.dpms_property; | |
10536 | ||
ea9d758d | 10537 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10538 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10539 | dpms_property, |
10540 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10541 | |
10542 | intel_encoder = to_intel_encoder(connector->encoder); | |
10543 | intel_encoder->connectors_active = true; | |
10544 | } | |
10545 | } | |
10546 | ||
10547 | } | |
10548 | ||
3bd26263 | 10549 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10550 | { |
3bd26263 | 10551 | int diff; |
f1f644dc JB |
10552 | |
10553 | if (clock1 == clock2) | |
10554 | return true; | |
10555 | ||
10556 | if (!clock1 || !clock2) | |
10557 | return false; | |
10558 | ||
10559 | diff = abs(clock1 - clock2); | |
10560 | ||
10561 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10562 | return true; | |
10563 | ||
10564 | return false; | |
10565 | } | |
10566 | ||
25c5b266 DV |
10567 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10568 | list_for_each_entry((intel_crtc), \ | |
10569 | &(dev)->mode_config.crtc_list, \ | |
10570 | base.head) \ | |
0973f18f | 10571 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10572 | |
0e8ffe1b | 10573 | static bool |
2fa2fe9a | 10574 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
10575 | struct intel_crtc_state *current_config, |
10576 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 10577 | { |
66e985c0 DV |
10578 | #define PIPE_CONF_CHECK_X(name) \ |
10579 | if (current_config->name != pipe_config->name) { \ | |
10580 | DRM_ERROR("mismatch in " #name " " \ | |
10581 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10582 | current_config->name, \ | |
10583 | pipe_config->name); \ | |
10584 | return false; \ | |
10585 | } | |
10586 | ||
08a24034 DV |
10587 | #define PIPE_CONF_CHECK_I(name) \ |
10588 | if (current_config->name != pipe_config->name) { \ | |
10589 | DRM_ERROR("mismatch in " #name " " \ | |
10590 | "(expected %i, found %i)\n", \ | |
10591 | current_config->name, \ | |
10592 | pipe_config->name); \ | |
10593 | return false; \ | |
88adfff1 DV |
10594 | } |
10595 | ||
b95af8be VK |
10596 | /* This is required for BDW+ where there is only one set of registers for |
10597 | * switching between high and low RR. | |
10598 | * This macro can be used whenever a comparison has to be made between one | |
10599 | * hw state and multiple sw state variables. | |
10600 | */ | |
10601 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10602 | if ((current_config->name != pipe_config->name) && \ | |
10603 | (current_config->alt_name != pipe_config->name)) { \ | |
10604 | DRM_ERROR("mismatch in " #name " " \ | |
10605 | "(expected %i or %i, found %i)\n", \ | |
10606 | current_config->name, \ | |
10607 | current_config->alt_name, \ | |
10608 | pipe_config->name); \ | |
10609 | return false; \ | |
10610 | } | |
10611 | ||
1bd1bd80 DV |
10612 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10613 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10614 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10615 | "(expected %i, found %i)\n", \ |
10616 | current_config->name & (mask), \ | |
10617 | pipe_config->name & (mask)); \ | |
10618 | return false; \ | |
10619 | } | |
10620 | ||
5e550656 VS |
10621 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10622 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10623 | DRM_ERROR("mismatch in " #name " " \ | |
10624 | "(expected %i, found %i)\n", \ | |
10625 | current_config->name, \ | |
10626 | pipe_config->name); \ | |
10627 | return false; \ | |
10628 | } | |
10629 | ||
bb760063 DV |
10630 | #define PIPE_CONF_QUIRK(quirk) \ |
10631 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10632 | ||
eccb140b DV |
10633 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10634 | ||
08a24034 DV |
10635 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10636 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10637 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10638 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10639 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10640 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10641 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10642 | |
eb14cb74 | 10643 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10644 | |
10645 | if (INTEL_INFO(dev)->gen < 8) { | |
10646 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10647 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10648 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10649 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10650 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10651 | ||
10652 | if (current_config->has_drrs) { | |
10653 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10654 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10655 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10656 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10657 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10658 | } | |
10659 | } else { | |
10660 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10661 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10662 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10663 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10664 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10665 | } | |
eb14cb74 | 10666 | |
2d112de7 ACO |
10667 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
10668 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
10669 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
10670 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
10671 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
10672 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 10673 | |
2d112de7 ACO |
10674 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
10675 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
10676 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
10677 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
10678 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
10679 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 10680 | |
c93f54cf | 10681 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10682 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10683 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10684 | IS_VALLEYVIEW(dev)) | |
10685 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10686 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10687 | |
9ed109a7 DV |
10688 | PIPE_CONF_CHECK_I(has_audio); |
10689 | ||
2d112de7 | 10690 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
10691 | DRM_MODE_FLAG_INTERLACE); |
10692 | ||
bb760063 | 10693 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 10694 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10695 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 10696 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10697 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 10698 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10699 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 10700 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
10701 | DRM_MODE_FLAG_NVSYNC); |
10702 | } | |
045ac3b5 | 10703 | |
37327abd VS |
10704 | PIPE_CONF_CHECK_I(pipe_src_w); |
10705 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10706 | |
9953599b DV |
10707 | /* |
10708 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10709 | * screen. Since we don't yet re-compute the pipe config when moving | |
10710 | * just the lvds port away to another pipe the sw tracking won't match. | |
10711 | * | |
10712 | * Proper atomic modesets with recomputed global state will fix this. | |
10713 | * Until then just don't check gmch state for inherited modes. | |
10714 | */ | |
10715 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10716 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10717 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10718 | if (INTEL_INFO(dev)->gen < 4) | |
10719 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10720 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10721 | } | |
10722 | ||
fd4daa9c CW |
10723 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10724 | if (current_config->pch_pfit.enabled) { | |
10725 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10726 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10727 | } | |
2fa2fe9a | 10728 | |
e59150dc JB |
10729 | /* BDW+ don't expose a synchronous way to read the state */ |
10730 | if (IS_HASWELL(dev)) | |
10731 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10732 | |
282740f7 VS |
10733 | PIPE_CONF_CHECK_I(double_wide); |
10734 | ||
26804afd DV |
10735 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10736 | ||
c0d43d62 | 10737 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10738 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10739 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10740 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10741 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10742 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
10743 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
10744 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
10745 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 10746 | |
42571aef VS |
10747 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10748 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10749 | ||
2d112de7 | 10750 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 10751 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 10752 | |
66e985c0 | 10753 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10754 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10755 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10756 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10757 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10758 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10759 | |
0e8ffe1b DV |
10760 | return true; |
10761 | } | |
10762 | ||
08db6652 DL |
10763 | static void check_wm_state(struct drm_device *dev) |
10764 | { | |
10765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10766 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
10767 | struct intel_crtc *intel_crtc; | |
10768 | int plane; | |
10769 | ||
10770 | if (INTEL_INFO(dev)->gen < 9) | |
10771 | return; | |
10772 | ||
10773 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
10774 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
10775 | ||
10776 | for_each_intel_crtc(dev, intel_crtc) { | |
10777 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
10778 | const enum pipe pipe = intel_crtc->pipe; | |
10779 | ||
10780 | if (!intel_crtc->active) | |
10781 | continue; | |
10782 | ||
10783 | /* planes */ | |
10784 | for_each_plane(pipe, plane) { | |
10785 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
10786 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
10787 | ||
10788 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10789 | continue; | |
10790 | ||
10791 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
10792 | "(expected (%u,%u), found (%u,%u))\n", | |
10793 | pipe_name(pipe), plane + 1, | |
10794 | sw_entry->start, sw_entry->end, | |
10795 | hw_entry->start, hw_entry->end); | |
10796 | } | |
10797 | ||
10798 | /* cursor */ | |
10799 | hw_entry = &hw_ddb.cursor[pipe]; | |
10800 | sw_entry = &sw_ddb->cursor[pipe]; | |
10801 | ||
10802 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10803 | continue; | |
10804 | ||
10805 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
10806 | "(expected (%u,%u), found (%u,%u))\n", | |
10807 | pipe_name(pipe), | |
10808 | sw_entry->start, sw_entry->end, | |
10809 | hw_entry->start, hw_entry->end); | |
10810 | } | |
10811 | } | |
10812 | ||
91d1b4bd DV |
10813 | static void |
10814 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10815 | { |
8af6cf88 DV |
10816 | struct intel_connector *connector; |
10817 | ||
10818 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10819 | base.head) { | |
10820 | /* This also checks the encoder/connector hw state with the | |
10821 | * ->get_hw_state callbacks. */ | |
10822 | intel_connector_check_state(connector); | |
10823 | ||
e2c719b7 | 10824 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
10825 | "connector's staged encoder doesn't match current encoder\n"); |
10826 | } | |
91d1b4bd DV |
10827 | } |
10828 | ||
10829 | static void | |
10830 | check_encoder_state(struct drm_device *dev) | |
10831 | { | |
10832 | struct intel_encoder *encoder; | |
10833 | struct intel_connector *connector; | |
8af6cf88 | 10834 | |
b2784e15 | 10835 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10836 | bool enabled = false; |
10837 | bool active = false; | |
10838 | enum pipe pipe, tracked_pipe; | |
10839 | ||
10840 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10841 | encoder->base.base.id, | |
8e329a03 | 10842 | encoder->base.name); |
8af6cf88 | 10843 | |
e2c719b7 | 10844 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 10845 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 10846 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
10847 | "encoder's active_connectors set, but no crtc\n"); |
10848 | ||
10849 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10850 | base.head) { | |
10851 | if (connector->base.encoder != &encoder->base) | |
10852 | continue; | |
10853 | enabled = true; | |
10854 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10855 | active = true; | |
10856 | } | |
0e32b39c DA |
10857 | /* |
10858 | * for MST connectors if we unplug the connector is gone | |
10859 | * away but the encoder is still connected to a crtc | |
10860 | * until a modeset happens in response to the hotplug. | |
10861 | */ | |
10862 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10863 | continue; | |
10864 | ||
e2c719b7 | 10865 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
10866 | "encoder's enabled state mismatch " |
10867 | "(expected %i, found %i)\n", | |
10868 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 10869 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
10870 | "active encoder with no crtc\n"); |
10871 | ||
e2c719b7 | 10872 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
10873 | "encoder's computed active state doesn't match tracked active state " |
10874 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10875 | ||
10876 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 10877 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
10878 | "encoder's hw state doesn't match sw tracking " |
10879 | "(expected %i, found %i)\n", | |
10880 | encoder->connectors_active, active); | |
10881 | ||
10882 | if (!encoder->base.crtc) | |
10883 | continue; | |
10884 | ||
10885 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 10886 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
10887 | "active encoder's pipe doesn't match" |
10888 | "(expected %i, found %i)\n", | |
10889 | tracked_pipe, pipe); | |
10890 | ||
10891 | } | |
91d1b4bd DV |
10892 | } |
10893 | ||
10894 | static void | |
10895 | check_crtc_state(struct drm_device *dev) | |
10896 | { | |
fbee40df | 10897 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10898 | struct intel_crtc *crtc; |
10899 | struct intel_encoder *encoder; | |
5cec258b | 10900 | struct intel_crtc_state pipe_config; |
8af6cf88 | 10901 | |
d3fcc808 | 10902 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10903 | bool enabled = false; |
10904 | bool active = false; | |
10905 | ||
045ac3b5 JB |
10906 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10907 | ||
8af6cf88 DV |
10908 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10909 | crtc->base.base.id); | |
10910 | ||
83d65738 | 10911 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
10912 | "active crtc, but not enabled in sw tracking\n"); |
10913 | ||
b2784e15 | 10914 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10915 | if (encoder->base.crtc != &crtc->base) |
10916 | continue; | |
10917 | enabled = true; | |
10918 | if (encoder->connectors_active) | |
10919 | active = true; | |
10920 | } | |
6c49f241 | 10921 | |
e2c719b7 | 10922 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
10923 | "crtc's computed active state doesn't match tracked active state " |
10924 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 10925 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 10926 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
10927 | "(expected %i, found %i)\n", enabled, |
10928 | crtc->base.state->enable); | |
8af6cf88 | 10929 | |
0e8ffe1b DV |
10930 | active = dev_priv->display.get_pipe_config(crtc, |
10931 | &pipe_config); | |
d62cf62a | 10932 | |
b6b5d049 VS |
10933 | /* hw state is inconsistent with the pipe quirk */ |
10934 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
10935 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
10936 | active = crtc->active; |
10937 | ||
b2784e15 | 10938 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10939 | enum pipe pipe; |
6c49f241 DV |
10940 | if (encoder->base.crtc != &crtc->base) |
10941 | continue; | |
1d37b689 | 10942 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10943 | encoder->get_config(encoder, &pipe_config); |
10944 | } | |
10945 | ||
e2c719b7 | 10946 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
10947 | "crtc active state doesn't match with hw state " |
10948 | "(expected %i, found %i)\n", crtc->active, active); | |
10949 | ||
c0b03411 | 10950 | if (active && |
6e3c9717 | 10951 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 10952 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
10953 | intel_dump_pipe_config(crtc, &pipe_config, |
10954 | "[hw state]"); | |
6e3c9717 | 10955 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
10956 | "[sw state]"); |
10957 | } | |
8af6cf88 DV |
10958 | } |
10959 | } | |
10960 | ||
91d1b4bd DV |
10961 | static void |
10962 | check_shared_dpll_state(struct drm_device *dev) | |
10963 | { | |
fbee40df | 10964 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10965 | struct intel_crtc *crtc; |
10966 | struct intel_dpll_hw_state dpll_hw_state; | |
10967 | int i; | |
5358901f DV |
10968 | |
10969 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10970 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10971 | int enabled_crtcs = 0, active_crtcs = 0; | |
10972 | bool active; | |
10973 | ||
10974 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10975 | ||
10976 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10977 | ||
10978 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10979 | ||
e2c719b7 | 10980 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 10981 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 10982 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 10983 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 10984 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 10985 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 10986 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 10987 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
10988 | "pll on state mismatch (expected %i, found %i)\n", |
10989 | pll->on, active); | |
10990 | ||
d3fcc808 | 10991 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10992 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
10993 | enabled_crtcs++; |
10994 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10995 | active_crtcs++; | |
10996 | } | |
e2c719b7 | 10997 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
10998 | "pll active crtcs mismatch (expected %i, found %i)\n", |
10999 | pll->active, active_crtcs); | |
e2c719b7 | 11000 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11001 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11002 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11003 | |
e2c719b7 | 11004 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11005 | sizeof(dpll_hw_state)), |
11006 | "pll hw state mismatch\n"); | |
5358901f | 11007 | } |
8af6cf88 DV |
11008 | } |
11009 | ||
91d1b4bd DV |
11010 | void |
11011 | intel_modeset_check_state(struct drm_device *dev) | |
11012 | { | |
08db6652 | 11013 | check_wm_state(dev); |
91d1b4bd DV |
11014 | check_connector_state(dev); |
11015 | check_encoder_state(dev); | |
11016 | check_crtc_state(dev); | |
11017 | check_shared_dpll_state(dev); | |
11018 | } | |
11019 | ||
5cec258b | 11020 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11021 | int dotclock) |
11022 | { | |
11023 | /* | |
11024 | * FDI already provided one idea for the dotclock. | |
11025 | * Yell if the encoder disagrees. | |
11026 | */ | |
2d112de7 | 11027 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11028 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11029 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11030 | } |
11031 | ||
80715b2f VS |
11032 | static void update_scanline_offset(struct intel_crtc *crtc) |
11033 | { | |
11034 | struct drm_device *dev = crtc->base.dev; | |
11035 | ||
11036 | /* | |
11037 | * The scanline counter increments at the leading edge of hsync. | |
11038 | * | |
11039 | * On most platforms it starts counting from vtotal-1 on the | |
11040 | * first active line. That means the scanline counter value is | |
11041 | * always one less than what we would expect. Ie. just after | |
11042 | * start of vblank, which also occurs at start of hsync (on the | |
11043 | * last active line), the scanline counter will read vblank_start-1. | |
11044 | * | |
11045 | * On gen2 the scanline counter starts counting from 1 instead | |
11046 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11047 | * to keep the value positive), instead of adding one. | |
11048 | * | |
11049 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11050 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11051 | * there's an extra 1 line difference. So we need to add two instead of | |
11052 | * one to the value. | |
11053 | */ | |
11054 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11055 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11056 | int vtotal; |
11057 | ||
11058 | vtotal = mode->crtc_vtotal; | |
11059 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11060 | vtotal /= 2; | |
11061 | ||
11062 | crtc->scanline_offset = vtotal - 1; | |
11063 | } else if (HAS_DDI(dev) && | |
409ee761 | 11064 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11065 | crtc->scanline_offset = 2; |
11066 | } else | |
11067 | crtc->scanline_offset = 1; | |
11068 | } | |
11069 | ||
5cec258b | 11070 | static struct intel_crtc_state * |
7f27126e JB |
11071 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11072 | struct drm_display_mode *mode, | |
11073 | struct drm_framebuffer *fb, | |
11074 | unsigned *modeset_pipes, | |
11075 | unsigned *prepare_pipes, | |
11076 | unsigned *disable_pipes) | |
11077 | { | |
5cec258b | 11078 | struct intel_crtc_state *pipe_config = NULL; |
7f27126e JB |
11079 | |
11080 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11081 | prepare_pipes, disable_pipes); | |
11082 | ||
11083 | if ((*modeset_pipes) == 0) | |
11084 | goto out; | |
11085 | ||
11086 | /* | |
11087 | * Note this needs changes when we start tracking multiple modes | |
11088 | * and crtcs. At that point we'll need to compute the whole config | |
11089 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11090 | * for this crtc. | |
11091 | */ | |
11092 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); | |
11093 | if (IS_ERR(pipe_config)) { | |
11094 | goto out; | |
11095 | } | |
11096 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
11097 | "[modeset]"); | |
7f27126e JB |
11098 | |
11099 | out: | |
11100 | return pipe_config; | |
11101 | } | |
11102 | ||
ed6739ef ACO |
11103 | static int __intel_set_mode_setup_plls(struct drm_device *dev, |
11104 | unsigned modeset_pipes, | |
11105 | unsigned disable_pipes) | |
11106 | { | |
11107 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11108 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11109 | struct intel_crtc *intel_crtc; | |
11110 | int ret = 0; | |
11111 | ||
11112 | if (!dev_priv->display.crtc_compute_clock) | |
11113 | return 0; | |
11114 | ||
11115 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11116 | if (ret) | |
11117 | goto done; | |
11118 | ||
11119 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
11120 | struct intel_crtc_state *state = intel_crtc->new_config; | |
11121 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11122 | state); | |
11123 | if (ret) { | |
11124 | intel_shared_dpll_abort_config(dev_priv); | |
11125 | goto done; | |
11126 | } | |
11127 | } | |
11128 | ||
11129 | done: | |
11130 | return ret; | |
11131 | } | |
11132 | ||
f30da187 DV |
11133 | static int __intel_set_mode(struct drm_crtc *crtc, |
11134 | struct drm_display_mode *mode, | |
7f27126e | 11135 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11136 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11137 | unsigned modeset_pipes, |
11138 | unsigned prepare_pipes, | |
11139 | unsigned disable_pipes) | |
a6778b3c DV |
11140 | { |
11141 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11142 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11143 | struct drm_display_mode *saved_mode; |
25c5b266 | 11144 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11145 | int ret = 0; |
a6778b3c | 11146 | |
4b4b9238 | 11147 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11148 | if (!saved_mode) |
11149 | return -ENOMEM; | |
a6778b3c | 11150 | |
3ac18232 | 11151 | *saved_mode = crtc->mode; |
a6778b3c | 11152 | |
b9950a13 VS |
11153 | if (modeset_pipes) |
11154 | to_intel_crtc(crtc)->new_config = pipe_config; | |
11155 | ||
30a970c6 JB |
11156 | /* |
11157 | * See if the config requires any additional preparation, e.g. | |
11158 | * to adjust global state with pipes off. We need to do this | |
11159 | * here so we can get the modeset_pipe updated config for the new | |
11160 | * mode set on this crtc. For other crtcs we need to use the | |
11161 | * adjusted_mode bits in the crtc directly. | |
11162 | */ | |
c164f833 | 11163 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 11164 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 11165 | |
c164f833 VS |
11166 | /* may have added more to prepare_pipes than we should */ |
11167 | prepare_pipes &= ~disable_pipes; | |
11168 | } | |
11169 | ||
ed6739ef ACO |
11170 | ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); |
11171 | if (ret) | |
11172 | goto done; | |
8bd31e67 | 11173 | |
460da916 DV |
11174 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11175 | intel_crtc_disable(&intel_crtc->base); | |
11176 | ||
ea9d758d | 11177 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11178 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11179 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11180 | } | |
a6778b3c | 11181 | |
6c4c86f5 DV |
11182 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11183 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11184 | * |
11185 | * Note we'll need to fix this up when we start tracking multiple | |
11186 | * pipes; here we assume a single modeset_pipe and only track the | |
11187 | * single crtc and mode. | |
f6e5b160 | 11188 | */ |
b8cecdf5 | 11189 | if (modeset_pipes) { |
25c5b266 | 11190 | crtc->mode = *mode; |
b8cecdf5 DV |
11191 | /* mode_set/enable/disable functions rely on a correct pipe |
11192 | * config. */ | |
f5de6e07 | 11193 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11194 | |
11195 | /* | |
11196 | * Calculate and store various constants which | |
11197 | * are later needed by vblank and swap-completion | |
11198 | * timestamping. They are derived from true hwmode. | |
11199 | */ | |
11200 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11201 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11202 | } |
7758a113 | 11203 | |
ea9d758d DV |
11204 | /* Only after disabling all output pipelines that will be changed can we |
11205 | * update the the output configuration. */ | |
11206 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11207 | |
50f6e502 | 11208 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11209 | |
a6778b3c DV |
11210 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11211 | * on the DPLL. | |
f6e5b160 | 11212 | */ |
25c5b266 | 11213 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11214 | struct drm_plane *primary = intel_crtc->base.primary; |
11215 | int vdisplay, hdisplay; | |
4c10794f | 11216 | |
455a6808 GP |
11217 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11218 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11219 | fb, 0, 0, | |
11220 | hdisplay, vdisplay, | |
11221 | x << 16, y << 16, | |
11222 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11223 | } |
11224 | ||
11225 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11226 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11227 | update_scanline_offset(intel_crtc); | |
11228 | ||
25c5b266 | 11229 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11230 | } |
a6778b3c | 11231 | |
a6778b3c DV |
11232 | /* FIXME: add subpixel order */ |
11233 | done: | |
83d65738 | 11234 | if (ret && crtc->state->enable) |
3ac18232 | 11235 | crtc->mode = *saved_mode; |
a6778b3c | 11236 | |
3ac18232 | 11237 | kfree(saved_mode); |
a6778b3c | 11238 | return ret; |
f6e5b160 CW |
11239 | } |
11240 | ||
7f27126e JB |
11241 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11242 | struct drm_display_mode *mode, | |
11243 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11244 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11245 | unsigned modeset_pipes, |
11246 | unsigned prepare_pipes, | |
11247 | unsigned disable_pipes) | |
f30da187 DV |
11248 | { |
11249 | int ret; | |
11250 | ||
7f27126e JB |
11251 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11252 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11253 | |
11254 | if (ret == 0) | |
11255 | intel_modeset_check_state(crtc->dev); | |
11256 | ||
11257 | return ret; | |
11258 | } | |
11259 | ||
7f27126e JB |
11260 | static int intel_set_mode(struct drm_crtc *crtc, |
11261 | struct drm_display_mode *mode, | |
11262 | int x, int y, struct drm_framebuffer *fb) | |
11263 | { | |
5cec258b | 11264 | struct intel_crtc_state *pipe_config; |
7f27126e JB |
11265 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
11266 | ||
11267 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, | |
11268 | &modeset_pipes, | |
11269 | &prepare_pipes, | |
11270 | &disable_pipes); | |
11271 | ||
11272 | if (IS_ERR(pipe_config)) | |
11273 | return PTR_ERR(pipe_config); | |
11274 | ||
11275 | return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11276 | modeset_pipes, prepare_pipes, | |
11277 | disable_pipes); | |
11278 | } | |
11279 | ||
c0c36b94 CW |
11280 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11281 | { | |
f4510a27 | 11282 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11283 | } |
11284 | ||
25c5b266 DV |
11285 | #undef for_each_intel_crtc_masked |
11286 | ||
d9e55608 DV |
11287 | static void intel_set_config_free(struct intel_set_config *config) |
11288 | { | |
11289 | if (!config) | |
11290 | return; | |
11291 | ||
1aa4b628 DV |
11292 | kfree(config->save_connector_encoders); |
11293 | kfree(config->save_encoder_crtcs); | |
7668851f | 11294 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11295 | kfree(config); |
11296 | } | |
11297 | ||
85f9eb71 DV |
11298 | static int intel_set_config_save_state(struct drm_device *dev, |
11299 | struct intel_set_config *config) | |
11300 | { | |
7668851f | 11301 | struct drm_crtc *crtc; |
85f9eb71 DV |
11302 | struct drm_encoder *encoder; |
11303 | struct drm_connector *connector; | |
11304 | int count; | |
11305 | ||
7668851f VS |
11306 | config->save_crtc_enabled = |
11307 | kcalloc(dev->mode_config.num_crtc, | |
11308 | sizeof(bool), GFP_KERNEL); | |
11309 | if (!config->save_crtc_enabled) | |
11310 | return -ENOMEM; | |
11311 | ||
1aa4b628 DV |
11312 | config->save_encoder_crtcs = |
11313 | kcalloc(dev->mode_config.num_encoder, | |
11314 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11315 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11316 | return -ENOMEM; |
11317 | ||
1aa4b628 DV |
11318 | config->save_connector_encoders = |
11319 | kcalloc(dev->mode_config.num_connector, | |
11320 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11321 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11322 | return -ENOMEM; |
11323 | ||
11324 | /* Copy data. Note that driver private data is not affected. | |
11325 | * Should anything bad happen only the expected state is | |
11326 | * restored, not the drivers personal bookkeeping. | |
11327 | */ | |
7668851f | 11328 | count = 0; |
70e1e0ec | 11329 | for_each_crtc(dev, crtc) { |
83d65738 | 11330 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
11331 | } |
11332 | ||
85f9eb71 DV |
11333 | count = 0; |
11334 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11335 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11336 | } |
11337 | ||
11338 | count = 0; | |
11339 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11340 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11341 | } |
11342 | ||
11343 | return 0; | |
11344 | } | |
11345 | ||
11346 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11347 | struct intel_set_config *config) | |
11348 | { | |
7668851f | 11349 | struct intel_crtc *crtc; |
9a935856 DV |
11350 | struct intel_encoder *encoder; |
11351 | struct intel_connector *connector; | |
85f9eb71 DV |
11352 | int count; |
11353 | ||
7668851f | 11354 | count = 0; |
d3fcc808 | 11355 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11356 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11357 | |
11358 | if (crtc->new_enabled) | |
6e3c9717 | 11359 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11360 | else |
11361 | crtc->new_config = NULL; | |
7668851f VS |
11362 | } |
11363 | ||
85f9eb71 | 11364 | count = 0; |
b2784e15 | 11365 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11366 | encoder->new_crtc = |
11367 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11368 | } |
11369 | ||
11370 | count = 0; | |
9a935856 DV |
11371 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11372 | connector->new_encoder = | |
11373 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11374 | } |
11375 | } | |
11376 | ||
e3de42b6 | 11377 | static bool |
2e57f47d | 11378 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11379 | { |
11380 | int i; | |
11381 | ||
2e57f47d CW |
11382 | if (set->num_connectors == 0) |
11383 | return false; | |
11384 | ||
11385 | if (WARN_ON(set->connectors == NULL)) | |
11386 | return false; | |
11387 | ||
11388 | for (i = 0; i < set->num_connectors; i++) | |
11389 | if (set->connectors[i]->encoder && | |
11390 | set->connectors[i]->encoder->crtc == set->crtc && | |
11391 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11392 | return true; |
11393 | ||
11394 | return false; | |
11395 | } | |
11396 | ||
5e2b584e DV |
11397 | static void |
11398 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11399 | struct intel_set_config *config) | |
11400 | { | |
11401 | ||
11402 | /* We should be able to check here if the fb has the same properties | |
11403 | * and then just flip_or_move it */ | |
2e57f47d CW |
11404 | if (is_crtc_connector_off(set)) { |
11405 | config->mode_changed = true; | |
f4510a27 | 11406 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11407 | /* |
11408 | * If we have no fb, we can only flip as long as the crtc is | |
11409 | * active, otherwise we need a full mode set. The crtc may | |
11410 | * be active if we've only disabled the primary plane, or | |
11411 | * in fastboot situations. | |
11412 | */ | |
f4510a27 | 11413 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11414 | struct intel_crtc *intel_crtc = |
11415 | to_intel_crtc(set->crtc); | |
11416 | ||
3b150f08 | 11417 | if (intel_crtc->active) { |
319d9827 JB |
11418 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11419 | config->fb_changed = true; | |
11420 | } else { | |
11421 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11422 | config->mode_changed = true; | |
11423 | } | |
5e2b584e DV |
11424 | } else if (set->fb == NULL) { |
11425 | config->mode_changed = true; | |
72f4901e | 11426 | } else if (set->fb->pixel_format != |
f4510a27 | 11427 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11428 | config->mode_changed = true; |
e3de42b6 | 11429 | } else { |
5e2b584e | 11430 | config->fb_changed = true; |
e3de42b6 | 11431 | } |
5e2b584e DV |
11432 | } |
11433 | ||
835c5873 | 11434 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11435 | config->fb_changed = true; |
11436 | ||
11437 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11438 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11439 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11440 | drm_mode_debug_printmodeline(set->mode); | |
11441 | config->mode_changed = true; | |
11442 | } | |
a1d95703 CW |
11443 | |
11444 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11445 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11446 | } |
11447 | ||
2e431051 | 11448 | static int |
9a935856 DV |
11449 | intel_modeset_stage_output_state(struct drm_device *dev, |
11450 | struct drm_mode_set *set, | |
11451 | struct intel_set_config *config) | |
50f56119 | 11452 | { |
9a935856 DV |
11453 | struct intel_connector *connector; |
11454 | struct intel_encoder *encoder; | |
7668851f | 11455 | struct intel_crtc *crtc; |
f3f08572 | 11456 | int ro; |
50f56119 | 11457 | |
9abdda74 | 11458 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11459 | * of connectors. For paranoia, double-check this. */ |
11460 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11461 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11462 | ||
9a935856 DV |
11463 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11464 | base.head) { | |
11465 | /* Otherwise traverse passed in connector list and get encoders | |
11466 | * for them. */ | |
50f56119 | 11467 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11468 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11469 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11470 | break; |
11471 | } | |
11472 | } | |
11473 | ||
9a935856 DV |
11474 | /* If we disable the crtc, disable all its connectors. Also, if |
11475 | * the connector is on the changing crtc but not on the new | |
11476 | * connector list, disable it. */ | |
11477 | if ((!set->fb || ro == set->num_connectors) && | |
11478 | connector->base.encoder && | |
11479 | connector->base.encoder->crtc == set->crtc) { | |
11480 | connector->new_encoder = NULL; | |
11481 | ||
11482 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11483 | connector->base.base.id, | |
c23cc417 | 11484 | connector->base.name); |
9a935856 DV |
11485 | } |
11486 | ||
11487 | ||
11488 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11489 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11490 | config->mode_changed = true; |
50f56119 DV |
11491 | } |
11492 | } | |
9a935856 | 11493 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11494 | |
9a935856 | 11495 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11496 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11497 | base.head) { | |
7668851f VS |
11498 | struct drm_crtc *new_crtc; |
11499 | ||
9a935856 | 11500 | if (!connector->new_encoder) |
50f56119 DV |
11501 | continue; |
11502 | ||
9a935856 | 11503 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11504 | |
11505 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11506 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11507 | new_crtc = set->crtc; |
11508 | } | |
11509 | ||
11510 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11511 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11512 | new_crtc)) { | |
5e2b584e | 11513 | return -EINVAL; |
50f56119 | 11514 | } |
0e32b39c | 11515 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11516 | |
11517 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11518 | connector->base.base.id, | |
c23cc417 | 11519 | connector->base.name, |
9a935856 DV |
11520 | new_crtc->base.id); |
11521 | } | |
11522 | ||
11523 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11524 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11525 | int num_connectors = 0; |
9a935856 DV |
11526 | list_for_each_entry(connector, |
11527 | &dev->mode_config.connector_list, | |
11528 | base.head) { | |
11529 | if (connector->new_encoder == encoder) { | |
11530 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11531 | num_connectors++; |
9a935856 DV |
11532 | } |
11533 | } | |
5a65f358 PZ |
11534 | |
11535 | if (num_connectors == 0) | |
11536 | encoder->new_crtc = NULL; | |
11537 | else if (num_connectors > 1) | |
11538 | return -EINVAL; | |
11539 | ||
9a935856 DV |
11540 | /* Only now check for crtc changes so we don't miss encoders |
11541 | * that will be disabled. */ | |
11542 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11543 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11544 | config->mode_changed = true; |
50f56119 DV |
11545 | } |
11546 | } | |
9a935856 | 11547 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11548 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11549 | base.head) { | |
11550 | if (connector->new_encoder) | |
11551 | if (connector->new_encoder != connector->encoder) | |
11552 | connector->encoder = connector->new_encoder; | |
11553 | } | |
d3fcc808 | 11554 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11555 | crtc->new_enabled = false; |
11556 | ||
b2784e15 | 11557 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11558 | if (encoder->new_crtc == crtc) { |
11559 | crtc->new_enabled = true; | |
11560 | break; | |
11561 | } | |
11562 | } | |
11563 | ||
83d65738 | 11564 | if (crtc->new_enabled != crtc->base.state->enable) { |
7668851f VS |
11565 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", |
11566 | crtc->new_enabled ? "en" : "dis"); | |
11567 | config->mode_changed = true; | |
11568 | } | |
7bd0a8e7 VS |
11569 | |
11570 | if (crtc->new_enabled) | |
6e3c9717 | 11571 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11572 | else |
11573 | crtc->new_config = NULL; | |
7668851f VS |
11574 | } |
11575 | ||
2e431051 DV |
11576 | return 0; |
11577 | } | |
11578 | ||
7d00a1f5 VS |
11579 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11580 | { | |
11581 | struct drm_device *dev = crtc->base.dev; | |
11582 | struct intel_encoder *encoder; | |
11583 | struct intel_connector *connector; | |
11584 | ||
11585 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11586 | pipe_name(crtc->pipe)); | |
11587 | ||
11588 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11589 | if (connector->new_encoder && | |
11590 | connector->new_encoder->new_crtc == crtc) | |
11591 | connector->new_encoder = NULL; | |
11592 | } | |
11593 | ||
b2784e15 | 11594 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11595 | if (encoder->new_crtc == crtc) |
11596 | encoder->new_crtc = NULL; | |
11597 | } | |
11598 | ||
11599 | crtc->new_enabled = false; | |
7bd0a8e7 | 11600 | crtc->new_config = NULL; |
7d00a1f5 VS |
11601 | } |
11602 | ||
2e431051 DV |
11603 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11604 | { | |
11605 | struct drm_device *dev; | |
2e431051 DV |
11606 | struct drm_mode_set save_set; |
11607 | struct intel_set_config *config; | |
5cec258b | 11608 | struct intel_crtc_state *pipe_config; |
50f52756 | 11609 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 11610 | int ret; |
2e431051 | 11611 | |
8d3e375e DV |
11612 | BUG_ON(!set); |
11613 | BUG_ON(!set->crtc); | |
11614 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11615 | |
7e53f3a4 DV |
11616 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11617 | BUG_ON(!set->mode && set->fb); | |
11618 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11619 | |
2e431051 DV |
11620 | if (set->fb) { |
11621 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11622 | set->crtc->base.id, set->fb->base.id, | |
11623 | (int)set->num_connectors, set->x, set->y); | |
11624 | } else { | |
11625 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11626 | } |
11627 | ||
11628 | dev = set->crtc->dev; | |
11629 | ||
11630 | ret = -ENOMEM; | |
11631 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11632 | if (!config) | |
11633 | goto out_config; | |
11634 | ||
11635 | ret = intel_set_config_save_state(dev, config); | |
11636 | if (ret) | |
11637 | goto out_config; | |
11638 | ||
11639 | save_set.crtc = set->crtc; | |
11640 | save_set.mode = &set->crtc->mode; | |
11641 | save_set.x = set->crtc->x; | |
11642 | save_set.y = set->crtc->y; | |
f4510a27 | 11643 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11644 | |
11645 | /* Compute whether we need a full modeset, only an fb base update or no | |
11646 | * change at all. In the future we might also check whether only the | |
11647 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11648 | * such cases. */ | |
11649 | intel_set_config_compute_mode_changes(set, config); | |
11650 | ||
9a935856 | 11651 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11652 | if (ret) |
11653 | goto fail; | |
11654 | ||
50f52756 JB |
11655 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
11656 | set->fb, | |
11657 | &modeset_pipes, | |
11658 | &prepare_pipes, | |
11659 | &disable_pipes); | |
20664591 | 11660 | if (IS_ERR(pipe_config)) { |
6ac0483b | 11661 | ret = PTR_ERR(pipe_config); |
50f52756 | 11662 | goto fail; |
20664591 | 11663 | } else if (pipe_config) { |
b9950a13 | 11664 | if (pipe_config->has_audio != |
6e3c9717 | 11665 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
11666 | config->mode_changed = true; |
11667 | ||
af15d2ce JB |
11668 | /* |
11669 | * Note we have an issue here with infoframes: current code | |
11670 | * only updates them on the full mode set path per hw | |
11671 | * requirements. So here we should be checking for any | |
11672 | * required changes and forcing a mode set. | |
11673 | */ | |
20664591 | 11674 | } |
50f52756 JB |
11675 | |
11676 | /* set_mode will free it in the mode_changed case */ | |
11677 | if (!config->mode_changed) | |
11678 | kfree(pipe_config); | |
11679 | ||
1f9954d0 JB |
11680 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
11681 | ||
5e2b584e | 11682 | if (config->mode_changed) { |
50f52756 JB |
11683 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
11684 | set->x, set->y, set->fb, pipe_config, | |
11685 | modeset_pipes, prepare_pipes, | |
11686 | disable_pipes); | |
5e2b584e | 11687 | } else if (config->fb_changed) { |
3b150f08 | 11688 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
11689 | struct drm_plane *primary = set->crtc->primary; |
11690 | int vdisplay, hdisplay; | |
3b150f08 | 11691 | |
455a6808 GP |
11692 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
11693 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
11694 | 0, 0, hdisplay, vdisplay, | |
11695 | set->x << 16, set->y << 16, | |
11696 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
11697 | |
11698 | /* | |
11699 | * We need to make sure the primary plane is re-enabled if it | |
11700 | * has previously been turned off. | |
11701 | */ | |
11702 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11703 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11704 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11705 | } |
11706 | ||
7ca51a3a JB |
11707 | /* |
11708 | * In the fastboot case this may be our only check of the | |
11709 | * state after boot. It would be better to only do it on | |
11710 | * the first update, but we don't have a nice way of doing that | |
11711 | * (and really, set_config isn't used much for high freq page | |
11712 | * flipping, so increasing its cost here shouldn't be a big | |
11713 | * deal). | |
11714 | */ | |
d330a953 | 11715 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11716 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11717 | } |
11718 | ||
2d05eae1 | 11719 | if (ret) { |
bf67dfeb DV |
11720 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11721 | set->crtc->base.id, ret); | |
50f56119 | 11722 | fail: |
2d05eae1 | 11723 | intel_set_config_restore_state(dev, config); |
50f56119 | 11724 | |
7d00a1f5 VS |
11725 | /* |
11726 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11727 | * force the pipe off to avoid oopsing in the modeset code | |
11728 | * due to fb==NULL. This should only happen during boot since | |
11729 | * we don't yet reconstruct the FB from the hardware state. | |
11730 | */ | |
11731 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11732 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11733 | ||
2d05eae1 CW |
11734 | /* Try to restore the config */ |
11735 | if (config->mode_changed && | |
11736 | intel_set_mode(save_set.crtc, save_set.mode, | |
11737 | save_set.x, save_set.y, save_set.fb)) | |
11738 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11739 | } | |
50f56119 | 11740 | |
d9e55608 DV |
11741 | out_config: |
11742 | intel_set_config_free(config); | |
50f56119 DV |
11743 | return ret; |
11744 | } | |
f6e5b160 CW |
11745 | |
11746 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11747 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11748 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11749 | .destroy = intel_crtc_destroy, |
11750 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
11751 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
11752 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
11753 | }; |
11754 | ||
5358901f DV |
11755 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11756 | struct intel_shared_dpll *pll, | |
11757 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11758 | { |
5358901f | 11759 | uint32_t val; |
ee7b9f93 | 11760 | |
f458ebbc | 11761 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
11762 | return false; |
11763 | ||
5358901f | 11764 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11765 | hw_state->dpll = val; |
11766 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11767 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11768 | |
11769 | return val & DPLL_VCO_ENABLE; | |
11770 | } | |
11771 | ||
15bdd4cf DV |
11772 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11773 | struct intel_shared_dpll *pll) | |
11774 | { | |
3e369b76 ACO |
11775 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
11776 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
11777 | } |
11778 | ||
e7b903d2 DV |
11779 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11780 | struct intel_shared_dpll *pll) | |
11781 | { | |
e7b903d2 | 11782 | /* PCH refclock must be enabled first */ |
89eff4be | 11783 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11784 | |
3e369b76 | 11785 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
11786 | |
11787 | /* Wait for the clocks to stabilize. */ | |
11788 | POSTING_READ(PCH_DPLL(pll->id)); | |
11789 | udelay(150); | |
11790 | ||
11791 | /* The pixel multiplier can only be updated once the | |
11792 | * DPLL is enabled and the clocks are stable. | |
11793 | * | |
11794 | * So write it again. | |
11795 | */ | |
3e369b76 | 11796 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 11797 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
11798 | udelay(200); |
11799 | } | |
11800 | ||
11801 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11802 | struct intel_shared_dpll *pll) | |
11803 | { | |
11804 | struct drm_device *dev = dev_priv->dev; | |
11805 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11806 | |
11807 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11808 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11809 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11810 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11811 | } |
11812 | ||
15bdd4cf DV |
11813 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11814 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11815 | udelay(200); |
11816 | } | |
11817 | ||
46edb027 DV |
11818 | static char *ibx_pch_dpll_names[] = { |
11819 | "PCH DPLL A", | |
11820 | "PCH DPLL B", | |
11821 | }; | |
11822 | ||
7c74ade1 | 11823 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11824 | { |
e7b903d2 | 11825 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11826 | int i; |
11827 | ||
7c74ade1 | 11828 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11829 | |
e72f9fbf | 11830 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11831 | dev_priv->shared_dplls[i].id = i; |
11832 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11833 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11834 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11835 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11836 | dev_priv->shared_dplls[i].get_hw_state = |
11837 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11838 | } |
11839 | } | |
11840 | ||
7c74ade1 DV |
11841 | static void intel_shared_dpll_init(struct drm_device *dev) |
11842 | { | |
e7b903d2 | 11843 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11844 | |
9cd86933 DV |
11845 | if (HAS_DDI(dev)) |
11846 | intel_ddi_pll_init(dev); | |
11847 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11848 | ibx_pch_dpll_init(dev); |
11849 | else | |
11850 | dev_priv->num_shared_dpll = 0; | |
11851 | ||
11852 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11853 | } |
11854 | ||
6beb8c23 MR |
11855 | /** |
11856 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
11857 | * @plane: drm plane to prepare for | |
11858 | * @fb: framebuffer to prepare for presentation | |
11859 | * | |
11860 | * Prepares a framebuffer for usage on a display plane. Generally this | |
11861 | * involves pinning the underlying object and updating the frontbuffer tracking | |
11862 | * bits. Some older platforms need special physical address handling for | |
11863 | * cursor planes. | |
11864 | * | |
11865 | * Returns 0 on success, negative error code on failure. | |
11866 | */ | |
11867 | int | |
11868 | intel_prepare_plane_fb(struct drm_plane *plane, | |
11869 | struct drm_framebuffer *fb) | |
465c120c MR |
11870 | { |
11871 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
11872 | struct intel_plane *intel_plane = to_intel_plane(plane); |
11873 | enum pipe pipe = intel_plane->pipe; | |
11874 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11875 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
11876 | unsigned frontbuffer_bits = 0; | |
11877 | int ret = 0; | |
465c120c | 11878 | |
ea2c67bb | 11879 | if (!obj) |
465c120c MR |
11880 | return 0; |
11881 | ||
6beb8c23 MR |
11882 | switch (plane->type) { |
11883 | case DRM_PLANE_TYPE_PRIMARY: | |
11884 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
11885 | break; | |
11886 | case DRM_PLANE_TYPE_CURSOR: | |
11887 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
11888 | break; | |
11889 | case DRM_PLANE_TYPE_OVERLAY: | |
11890 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
11891 | break; | |
11892 | } | |
465c120c | 11893 | |
6beb8c23 | 11894 | mutex_lock(&dev->struct_mutex); |
465c120c | 11895 | |
6beb8c23 MR |
11896 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
11897 | INTEL_INFO(dev)->cursor_needs_physical) { | |
11898 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
11899 | ret = i915_gem_object_attach_phys(obj, align); | |
11900 | if (ret) | |
11901 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
11902 | } else { | |
11903 | ret = intel_pin_and_fence_fb_obj(plane, fb, NULL); | |
11904 | } | |
465c120c | 11905 | |
6beb8c23 MR |
11906 | if (ret == 0) |
11907 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 11908 | |
4c34574f | 11909 | mutex_unlock(&dev->struct_mutex); |
465c120c | 11910 | |
6beb8c23 MR |
11911 | return ret; |
11912 | } | |
11913 | ||
38f3ce3a MR |
11914 | /** |
11915 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
11916 | * @plane: drm plane to clean up for | |
11917 | * @fb: old framebuffer that was on plane | |
11918 | * | |
11919 | * Cleans up a framebuffer that has just been removed from a plane. | |
11920 | */ | |
11921 | void | |
11922 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
11923 | struct drm_framebuffer *fb) | |
11924 | { | |
11925 | struct drm_device *dev = plane->dev; | |
11926 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11927 | ||
11928 | if (WARN_ON(!obj)) | |
11929 | return; | |
11930 | ||
11931 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
11932 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
11933 | mutex_lock(&dev->struct_mutex); | |
11934 | intel_unpin_fb_obj(obj); | |
11935 | mutex_unlock(&dev->struct_mutex); | |
11936 | } | |
465c120c MR |
11937 | } |
11938 | ||
11939 | static int | |
3c692a41 GP |
11940 | intel_check_primary_plane(struct drm_plane *plane, |
11941 | struct intel_plane_state *state) | |
11942 | { | |
32b7eeec MR |
11943 | struct drm_device *dev = plane->dev; |
11944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 11945 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 11946 | struct intel_crtc *intel_crtc; |
2b875c22 | 11947 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
11948 | struct drm_rect *dest = &state->dst; |
11949 | struct drm_rect *src = &state->src; | |
11950 | const struct drm_rect *clip = &state->clip; | |
465c120c MR |
11951 | int ret; |
11952 | ||
ea2c67bb MR |
11953 | crtc = crtc ? crtc : plane->crtc; |
11954 | intel_crtc = to_intel_crtc(crtc); | |
11955 | ||
c59cb179 MR |
11956 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
11957 | src, dest, clip, | |
11958 | DRM_PLANE_HELPER_NO_SCALING, | |
11959 | DRM_PLANE_HELPER_NO_SCALING, | |
11960 | false, true, &state->visible); | |
11961 | if (ret) | |
11962 | return ret; | |
465c120c | 11963 | |
32b7eeec MR |
11964 | if (intel_crtc->active) { |
11965 | intel_crtc->atomic.wait_for_flips = true; | |
11966 | ||
11967 | /* | |
11968 | * FBC does not work on some platforms for rotated | |
11969 | * planes, so disable it when rotation is not 0 and | |
11970 | * update it when rotation is set back to 0. | |
11971 | * | |
11972 | * FIXME: This is redundant with the fbc update done in | |
11973 | * the primary plane enable function except that that | |
11974 | * one is done too late. We eventually need to unify | |
11975 | * this. | |
11976 | */ | |
11977 | if (intel_crtc->primary_enabled && | |
11978 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 11979 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 11980 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
11981 | intel_crtc->atomic.disable_fbc = true; |
11982 | } | |
11983 | ||
11984 | if (state->visible) { | |
11985 | /* | |
11986 | * BDW signals flip done immediately if the plane | |
11987 | * is disabled, even if the plane enable is already | |
11988 | * armed to occur at the next vblank :( | |
11989 | */ | |
11990 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
11991 | intel_crtc->atomic.wait_vblank = true; | |
11992 | } | |
11993 | ||
11994 | intel_crtc->atomic.fb_bits |= | |
11995 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
11996 | ||
11997 | intel_crtc->atomic.update_fbc = true; | |
ccc759dc GP |
11998 | } |
11999 | ||
14af293f GP |
12000 | return 0; |
12001 | } | |
12002 | ||
12003 | static void | |
12004 | intel_commit_primary_plane(struct drm_plane *plane, | |
12005 | struct intel_plane_state *state) | |
12006 | { | |
2b875c22 MR |
12007 | struct drm_crtc *crtc = state->base.crtc; |
12008 | struct drm_framebuffer *fb = state->base.fb; | |
12009 | struct drm_device *dev = plane->dev; | |
14af293f | 12010 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12011 | struct intel_crtc *intel_crtc; |
14af293f | 12012 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
14af293f GP |
12013 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12014 | struct drm_rect *src = &state->src; | |
12015 | ||
ea2c67bb MR |
12016 | crtc = crtc ? crtc : plane->crtc; |
12017 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12018 | |
12019 | plane->fb = fb; | |
9dc806fc MR |
12020 | crtc->x = src->x1 >> 16; |
12021 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12022 | |
ccc759dc | 12023 | intel_plane->obj = obj; |
4c34574f | 12024 | |
ccc759dc | 12025 | if (intel_crtc->active) { |
ccc759dc | 12026 | if (state->visible) { |
ccc759dc GP |
12027 | /* FIXME: kill this fastboot hack */ |
12028 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12029 | |
ccc759dc | 12030 | intel_crtc->primary_enabled = true; |
465c120c | 12031 | |
ccc759dc GP |
12032 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12033 | crtc->x, crtc->y); | |
ccc759dc GP |
12034 | } else { |
12035 | /* | |
12036 | * If clipping results in a non-visible primary plane, | |
12037 | * we'll disable the primary plane. Note that this is | |
12038 | * a bit different than what happens if userspace | |
12039 | * explicitly disables the plane by passing fb=0 | |
12040 | * because plane->fb still gets set and pinned. | |
12041 | */ | |
12042 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12043 | } |
ccc759dc | 12044 | } |
465c120c MR |
12045 | } |
12046 | ||
32b7eeec | 12047 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12048 | { |
32b7eeec | 12049 | struct drm_device *dev = crtc->dev; |
140fd38d | 12050 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12052 | struct intel_plane *intel_plane; |
12053 | struct drm_plane *p; | |
12054 | unsigned fb_bits = 0; | |
12055 | ||
12056 | /* Track fb's for any planes being disabled */ | |
12057 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12058 | intel_plane = to_intel_plane(p); | |
12059 | ||
12060 | if (intel_crtc->atomic.disabled_planes & | |
12061 | (1 << drm_plane_index(p))) { | |
12062 | switch (p->type) { | |
12063 | case DRM_PLANE_TYPE_PRIMARY: | |
12064 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12065 | break; | |
12066 | case DRM_PLANE_TYPE_CURSOR: | |
12067 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12068 | break; | |
12069 | case DRM_PLANE_TYPE_OVERLAY: | |
12070 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12071 | break; | |
12072 | } | |
3c692a41 | 12073 | |
ea2c67bb MR |
12074 | mutex_lock(&dev->struct_mutex); |
12075 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12076 | mutex_unlock(&dev->struct_mutex); | |
12077 | } | |
12078 | } | |
3c692a41 | 12079 | |
32b7eeec MR |
12080 | if (intel_crtc->atomic.wait_for_flips) |
12081 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12082 | |
32b7eeec MR |
12083 | if (intel_crtc->atomic.disable_fbc) |
12084 | intel_fbc_disable(dev); | |
3c692a41 | 12085 | |
32b7eeec MR |
12086 | if (intel_crtc->atomic.pre_disable_primary) |
12087 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12088 | |
32b7eeec MR |
12089 | if (intel_crtc->atomic.update_wm) |
12090 | intel_update_watermarks(crtc); | |
3c692a41 | 12091 | |
32b7eeec | 12092 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12093 | |
c34c9ee4 MR |
12094 | /* Perform vblank evasion around commit operation */ |
12095 | if (intel_crtc->active) | |
12096 | intel_crtc->atomic.evade = | |
12097 | intel_pipe_update_start(intel_crtc, | |
12098 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12099 | } |
12100 | ||
12101 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12102 | { | |
12103 | struct drm_device *dev = crtc->dev; | |
12104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12106 | struct drm_plane *p; | |
12107 | ||
c34c9ee4 MR |
12108 | if (intel_crtc->atomic.evade) |
12109 | intel_pipe_update_end(intel_crtc, | |
12110 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12111 | |
140fd38d | 12112 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12113 | |
32b7eeec MR |
12114 | if (intel_crtc->atomic.wait_vblank) |
12115 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12116 | ||
12117 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12118 | ||
12119 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12120 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12121 | intel_fbc_update(dev); |
ccc759dc | 12122 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12123 | } |
3c692a41 | 12124 | |
32b7eeec MR |
12125 | if (intel_crtc->atomic.post_enable_primary) |
12126 | intel_post_enable_primary(crtc); | |
3c692a41 | 12127 | |
32b7eeec MR |
12128 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12129 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12130 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12131 | false, false); | |
12132 | ||
12133 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12134 | } |
12135 | ||
cf4c7c12 | 12136 | /** |
4a3b8769 MR |
12137 | * intel_plane_destroy - destroy a plane |
12138 | * @plane: plane to destroy | |
cf4c7c12 | 12139 | * |
4a3b8769 MR |
12140 | * Common destruction function for all types of planes (primary, cursor, |
12141 | * sprite). | |
cf4c7c12 | 12142 | */ |
4a3b8769 | 12143 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12144 | { |
12145 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12146 | drm_plane_cleanup(plane); | |
12147 | kfree(intel_plane); | |
12148 | } | |
12149 | ||
65a3fea0 | 12150 | const struct drm_plane_funcs intel_plane_funcs = { |
3f678c96 MR |
12151 | .update_plane = drm_atomic_helper_update_plane, |
12152 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12153 | .destroy = intel_plane_destroy, |
c196e1d6 | 12154 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12155 | .atomic_get_property = intel_plane_atomic_get_property, |
12156 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12157 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12158 | .atomic_destroy_state = intel_plane_destroy_state, | |
12159 | ||
465c120c MR |
12160 | }; |
12161 | ||
12162 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12163 | int pipe) | |
12164 | { | |
12165 | struct intel_plane *primary; | |
8e7d688b | 12166 | struct intel_plane_state *state; |
465c120c MR |
12167 | const uint32_t *intel_primary_formats; |
12168 | int num_formats; | |
12169 | ||
12170 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12171 | if (primary == NULL) | |
12172 | return NULL; | |
12173 | ||
8e7d688b MR |
12174 | state = intel_create_plane_state(&primary->base); |
12175 | if (!state) { | |
ea2c67bb MR |
12176 | kfree(primary); |
12177 | return NULL; | |
12178 | } | |
8e7d688b | 12179 | primary->base.state = &state->base; |
ea2c67bb | 12180 | |
465c120c MR |
12181 | primary->can_scale = false; |
12182 | primary->max_downscale = 1; | |
12183 | primary->pipe = pipe; | |
12184 | primary->plane = pipe; | |
c59cb179 MR |
12185 | primary->check_plane = intel_check_primary_plane; |
12186 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
12187 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12188 | primary->plane = !pipe; | |
12189 | ||
12190 | if (INTEL_INFO(dev)->gen <= 3) { | |
12191 | intel_primary_formats = intel_primary_formats_gen2; | |
12192 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12193 | } else { | |
12194 | intel_primary_formats = intel_primary_formats_gen4; | |
12195 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12196 | } | |
12197 | ||
12198 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12199 | &intel_plane_funcs, |
465c120c MR |
12200 | intel_primary_formats, num_formats, |
12201 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
12202 | |
12203 | if (INTEL_INFO(dev)->gen >= 4) { | |
12204 | if (!dev->mode_config.rotation_property) | |
12205 | dev->mode_config.rotation_property = | |
12206 | drm_mode_create_rotation_property(dev, | |
12207 | BIT(DRM_ROTATE_0) | | |
12208 | BIT(DRM_ROTATE_180)); | |
12209 | if (dev->mode_config.rotation_property) | |
12210 | drm_object_attach_property(&primary->base.base, | |
12211 | dev->mode_config.rotation_property, | |
8e7d688b | 12212 | state->base.rotation); |
48404c1e SJ |
12213 | } |
12214 | ||
ea2c67bb MR |
12215 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12216 | ||
465c120c MR |
12217 | return &primary->base; |
12218 | } | |
12219 | ||
3d7d6510 | 12220 | static int |
852e787c GP |
12221 | intel_check_cursor_plane(struct drm_plane *plane, |
12222 | struct intel_plane_state *state) | |
3d7d6510 | 12223 | { |
2b875c22 | 12224 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12225 | struct drm_device *dev = plane->dev; |
2b875c22 | 12226 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12227 | struct drm_rect *dest = &state->dst; |
12228 | struct drm_rect *src = &state->src; | |
12229 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12230 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12231 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12232 | unsigned stride; |
12233 | int ret; | |
3d7d6510 | 12234 | |
ea2c67bb MR |
12235 | crtc = crtc ? crtc : plane->crtc; |
12236 | intel_crtc = to_intel_crtc(crtc); | |
12237 | ||
757f9a3e | 12238 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12239 | src, dest, clip, |
3d7d6510 MR |
12240 | DRM_PLANE_HELPER_NO_SCALING, |
12241 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12242 | true, true, &state->visible); |
757f9a3e GP |
12243 | if (ret) |
12244 | return ret; | |
12245 | ||
12246 | ||
12247 | /* if we want to turn off the cursor ignore width and height */ | |
12248 | if (!obj) | |
32b7eeec | 12249 | goto finish; |
757f9a3e | 12250 | |
757f9a3e | 12251 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12252 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12253 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12254 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12255 | return -EINVAL; |
12256 | } | |
12257 | ||
ea2c67bb MR |
12258 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12259 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12260 | DRM_DEBUG_KMS("buffer is too small\n"); |
12261 | return -ENOMEM; | |
12262 | } | |
12263 | ||
e391ea88 GP |
12264 | if (fb == crtc->cursor->fb) |
12265 | return 0; | |
12266 | ||
6a418fcd | 12267 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
12268 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
12269 | ret = -EINVAL; | |
12270 | } | |
757f9a3e | 12271 | |
32b7eeec MR |
12272 | finish: |
12273 | if (intel_crtc->active) { | |
ea2c67bb | 12274 | if (intel_crtc->cursor_width != state->base.crtc_w) |
32b7eeec MR |
12275 | intel_crtc->atomic.update_wm = true; |
12276 | ||
12277 | intel_crtc->atomic.fb_bits |= | |
12278 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12279 | } | |
12280 | ||
757f9a3e | 12281 | return ret; |
852e787c | 12282 | } |
3d7d6510 | 12283 | |
f4a2cf29 | 12284 | static void |
852e787c GP |
12285 | intel_commit_cursor_plane(struct drm_plane *plane, |
12286 | struct intel_plane_state *state) | |
12287 | { | |
2b875c22 | 12288 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12289 | struct drm_device *dev = plane->dev; |
12290 | struct intel_crtc *intel_crtc; | |
a919db90 | 12291 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 12292 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12293 | uint32_t addr; |
852e787c | 12294 | |
ea2c67bb MR |
12295 | crtc = crtc ? crtc : plane->crtc; |
12296 | intel_crtc = to_intel_crtc(crtc); | |
12297 | ||
2b875c22 | 12298 | plane->fb = state->base.fb; |
ea2c67bb MR |
12299 | crtc->cursor_x = state->base.crtc_x; |
12300 | crtc->cursor_y = state->base.crtc_y; | |
12301 | ||
a919db90 SJ |
12302 | intel_plane->obj = obj; |
12303 | ||
a912f12f GP |
12304 | if (intel_crtc->cursor_bo == obj) |
12305 | goto update; | |
4ed91096 | 12306 | |
f4a2cf29 | 12307 | if (!obj) |
a912f12f | 12308 | addr = 0; |
f4a2cf29 | 12309 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12310 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12311 | else |
a912f12f | 12312 | addr = obj->phys_handle->busaddr; |
852e787c | 12313 | |
a912f12f GP |
12314 | intel_crtc->cursor_addr = addr; |
12315 | intel_crtc->cursor_bo = obj; | |
12316 | update: | |
ea2c67bb MR |
12317 | intel_crtc->cursor_width = state->base.crtc_w; |
12318 | intel_crtc->cursor_height = state->base.crtc_h; | |
852e787c | 12319 | |
32b7eeec | 12320 | if (intel_crtc->active) |
a912f12f | 12321 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
12322 | } |
12323 | ||
3d7d6510 MR |
12324 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
12325 | int pipe) | |
12326 | { | |
12327 | struct intel_plane *cursor; | |
8e7d688b | 12328 | struct intel_plane_state *state; |
3d7d6510 MR |
12329 | |
12330 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12331 | if (cursor == NULL) | |
12332 | return NULL; | |
12333 | ||
8e7d688b MR |
12334 | state = intel_create_plane_state(&cursor->base); |
12335 | if (!state) { | |
ea2c67bb MR |
12336 | kfree(cursor); |
12337 | return NULL; | |
12338 | } | |
8e7d688b | 12339 | cursor->base.state = &state->base; |
ea2c67bb | 12340 | |
3d7d6510 MR |
12341 | cursor->can_scale = false; |
12342 | cursor->max_downscale = 1; | |
12343 | cursor->pipe = pipe; | |
12344 | cursor->plane = pipe; | |
c59cb179 MR |
12345 | cursor->check_plane = intel_check_cursor_plane; |
12346 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12347 | |
12348 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 12349 | &intel_plane_funcs, |
3d7d6510 MR |
12350 | intel_cursor_formats, |
12351 | ARRAY_SIZE(intel_cursor_formats), | |
12352 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12353 | |
12354 | if (INTEL_INFO(dev)->gen >= 4) { | |
12355 | if (!dev->mode_config.rotation_property) | |
12356 | dev->mode_config.rotation_property = | |
12357 | drm_mode_create_rotation_property(dev, | |
12358 | BIT(DRM_ROTATE_0) | | |
12359 | BIT(DRM_ROTATE_180)); | |
12360 | if (dev->mode_config.rotation_property) | |
12361 | drm_object_attach_property(&cursor->base.base, | |
12362 | dev->mode_config.rotation_property, | |
8e7d688b | 12363 | state->base.rotation); |
4398ad45 VS |
12364 | } |
12365 | ||
ea2c67bb MR |
12366 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12367 | ||
3d7d6510 MR |
12368 | return &cursor->base; |
12369 | } | |
12370 | ||
b358d0a6 | 12371 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12372 | { |
fbee40df | 12373 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12374 | struct intel_crtc *intel_crtc; |
f5de6e07 | 12375 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
12376 | struct drm_plane *primary = NULL; |
12377 | struct drm_plane *cursor = NULL; | |
465c120c | 12378 | int i, ret; |
79e53945 | 12379 | |
955382f3 | 12380 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12381 | if (intel_crtc == NULL) |
12382 | return; | |
12383 | ||
f5de6e07 ACO |
12384 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
12385 | if (!crtc_state) | |
12386 | goto fail; | |
12387 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 12388 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 12389 | |
465c120c | 12390 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12391 | if (!primary) |
12392 | goto fail; | |
12393 | ||
12394 | cursor = intel_cursor_plane_create(dev, pipe); | |
12395 | if (!cursor) | |
12396 | goto fail; | |
12397 | ||
465c120c | 12398 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12399 | cursor, &intel_crtc_funcs); |
12400 | if (ret) | |
12401 | goto fail; | |
79e53945 JB |
12402 | |
12403 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12404 | for (i = 0; i < 256; i++) { |
12405 | intel_crtc->lut_r[i] = i; | |
12406 | intel_crtc->lut_g[i] = i; | |
12407 | intel_crtc->lut_b[i] = i; | |
12408 | } | |
12409 | ||
1f1c2e24 VS |
12410 | /* |
12411 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12412 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12413 | */ |
80824003 JB |
12414 | intel_crtc->pipe = pipe; |
12415 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12416 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12417 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12418 | intel_crtc->plane = !pipe; |
80824003 JB |
12419 | } |
12420 | ||
4b0e333e CW |
12421 | intel_crtc->cursor_base = ~0; |
12422 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12423 | intel_crtc->cursor_size = ~0; |
8d7849db | 12424 | |
22fd0fab JB |
12425 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12426 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12427 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12428 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12429 | ||
9362c7c5 ACO |
12430 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12431 | ||
79e53945 | 12432 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12433 | |
12434 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12435 | return; |
12436 | ||
12437 | fail: | |
12438 | if (primary) | |
12439 | drm_plane_cleanup(primary); | |
12440 | if (cursor) | |
12441 | drm_plane_cleanup(cursor); | |
f5de6e07 | 12442 | kfree(crtc_state); |
3d7d6510 | 12443 | kfree(intel_crtc); |
79e53945 JB |
12444 | } |
12445 | ||
752aa88a JB |
12446 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12447 | { | |
12448 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12449 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12450 | |
51fd371b | 12451 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12452 | |
d3babd3f | 12453 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12454 | return INVALID_PIPE; |
12455 | ||
12456 | return to_intel_crtc(encoder->crtc)->pipe; | |
12457 | } | |
12458 | ||
08d7b3d1 | 12459 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12460 | struct drm_file *file) |
08d7b3d1 | 12461 | { |
08d7b3d1 | 12462 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12463 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12464 | struct intel_crtc *crtc; |
08d7b3d1 | 12465 | |
7707e653 | 12466 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12467 | |
7707e653 | 12468 | if (!drmmode_crtc) { |
08d7b3d1 | 12469 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12470 | return -ENOENT; |
08d7b3d1 CW |
12471 | } |
12472 | ||
7707e653 | 12473 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12474 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12475 | |
c05422d5 | 12476 | return 0; |
08d7b3d1 CW |
12477 | } |
12478 | ||
66a9278e | 12479 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12480 | { |
66a9278e DV |
12481 | struct drm_device *dev = encoder->base.dev; |
12482 | struct intel_encoder *source_encoder; | |
79e53945 | 12483 | int index_mask = 0; |
79e53945 JB |
12484 | int entry = 0; |
12485 | ||
b2784e15 | 12486 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12487 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12488 | index_mask |= (1 << entry); |
12489 | ||
79e53945 JB |
12490 | entry++; |
12491 | } | |
4ef69c7a | 12492 | |
79e53945 JB |
12493 | return index_mask; |
12494 | } | |
12495 | ||
4d302442 CW |
12496 | static bool has_edp_a(struct drm_device *dev) |
12497 | { | |
12498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12499 | ||
12500 | if (!IS_MOBILE(dev)) | |
12501 | return false; | |
12502 | ||
12503 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12504 | return false; | |
12505 | ||
e3589908 | 12506 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12507 | return false; |
12508 | ||
12509 | return true; | |
12510 | } | |
12511 | ||
84b4e042 JB |
12512 | static bool intel_crt_present(struct drm_device *dev) |
12513 | { | |
12514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12515 | ||
884497ed DL |
12516 | if (INTEL_INFO(dev)->gen >= 9) |
12517 | return false; | |
12518 | ||
cf404ce4 | 12519 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12520 | return false; |
12521 | ||
12522 | if (IS_CHERRYVIEW(dev)) | |
12523 | return false; | |
12524 | ||
12525 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12526 | return false; | |
12527 | ||
12528 | return true; | |
12529 | } | |
12530 | ||
79e53945 JB |
12531 | static void intel_setup_outputs(struct drm_device *dev) |
12532 | { | |
725e30ad | 12533 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12534 | struct intel_encoder *encoder; |
c6f95f27 | 12535 | struct drm_connector *connector; |
cb0953d7 | 12536 | bool dpd_is_edp = false; |
79e53945 | 12537 | |
c9093354 | 12538 | intel_lvds_init(dev); |
79e53945 | 12539 | |
84b4e042 | 12540 | if (intel_crt_present(dev)) |
79935fca | 12541 | intel_crt_init(dev); |
cb0953d7 | 12542 | |
affa9354 | 12543 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12544 | int found; |
12545 | ||
12546 | /* Haswell uses DDI functions to detect digital outputs */ | |
12547 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12548 | /* DDI A only supports eDP */ | |
12549 | if (found) | |
12550 | intel_ddi_init(dev, PORT_A); | |
12551 | ||
12552 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12553 | * register */ | |
12554 | found = I915_READ(SFUSE_STRAP); | |
12555 | ||
12556 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12557 | intel_ddi_init(dev, PORT_B); | |
12558 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12559 | intel_ddi_init(dev, PORT_C); | |
12560 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12561 | intel_ddi_init(dev, PORT_D); | |
12562 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12563 | int found; |
5d8a7752 | 12564 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12565 | |
12566 | if (has_edp_a(dev)) | |
12567 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12568 | |
dc0fa718 | 12569 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12570 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12571 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12572 | if (!found) |
e2debe91 | 12573 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12574 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12575 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12576 | } |
12577 | ||
dc0fa718 | 12578 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12579 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12580 | |
dc0fa718 | 12581 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12582 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12583 | |
5eb08b69 | 12584 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12585 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12586 | |
270b3042 | 12587 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12588 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12589 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12590 | /* |
12591 | * The DP_DETECTED bit is the latched state of the DDC | |
12592 | * SDA pin at boot. However since eDP doesn't require DDC | |
12593 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12594 | * eDP ports may have been muxed to an alternate function. | |
12595 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12596 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12597 | * detect eDP ports. | |
12598 | */ | |
d2182a66 VS |
12599 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
12600 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
12601 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
12602 | PORT_B); | |
e17ac6db VS |
12603 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
12604 | intel_dp_is_edp(dev, PORT_B)) | |
12605 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 12606 | |
d2182a66 VS |
12607 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
12608 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
12609 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
12610 | PORT_C); | |
e17ac6db VS |
12611 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
12612 | intel_dp_is_edp(dev, PORT_C)) | |
12613 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 12614 | |
9418c1f1 | 12615 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 12616 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
12617 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
12618 | PORT_D); | |
e17ac6db VS |
12619 | /* eDP not supported on port D, so don't check VBT */ |
12620 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12621 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
12622 | } |
12623 | ||
3cfca973 | 12624 | intel_dsi_init(dev); |
103a196f | 12625 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12626 | bool found = false; |
7d57382e | 12627 | |
e2debe91 | 12628 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12629 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12630 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12631 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12632 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12633 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12634 | } |
27185ae1 | 12635 | |
e7281eab | 12636 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12637 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12638 | } |
13520b05 KH |
12639 | |
12640 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12641 | |
e2debe91 | 12642 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12643 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12644 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12645 | } |
27185ae1 | 12646 | |
e2debe91 | 12647 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12648 | |
b01f2c3a JB |
12649 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12650 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12651 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12652 | } |
e7281eab | 12653 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12654 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12655 | } |
27185ae1 | 12656 | |
b01f2c3a | 12657 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12658 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12659 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12660 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12661 | intel_dvo_init(dev); |
12662 | ||
103a196f | 12663 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12664 | intel_tv_init(dev); |
12665 | ||
c6f95f27 MR |
12666 | /* |
12667 | * FIXME: We don't have full atomic support yet, but we want to be | |
12668 | * able to enable/test plane updates via the atomic interface in the | |
12669 | * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core | |
12670 | * will take some atomic codepaths to lookup properties during | |
12671 | * drmModeGetConnector() that unconditionally dereference | |
12672 | * connector->state. | |
12673 | * | |
12674 | * We create a dummy connector state here for each connector to ensure | |
12675 | * the DRM core doesn't try to dereference a NULL connector->state. | |
12676 | * The actual connector properties will never be updated or contain | |
12677 | * useful information, but since we're doing this specifically for | |
12678 | * testing/debug of the plane operations (and only when a specific | |
12679 | * kernel module option is given), that shouldn't really matter. | |
12680 | * | |
12681 | * Once atomic support for crtc's + connectors lands, this loop should | |
12682 | * be removed since we'll be setting up real connector state, which | |
12683 | * will contain Intel-specific properties. | |
12684 | */ | |
12685 | if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { | |
12686 | list_for_each_entry(connector, | |
12687 | &dev->mode_config.connector_list, | |
12688 | head) { | |
12689 | if (!WARN_ON(connector->state)) { | |
12690 | connector->state = | |
12691 | kzalloc(sizeof(*connector->state), | |
12692 | GFP_KERNEL); | |
12693 | } | |
12694 | } | |
12695 | } | |
12696 | ||
0bc12bcb | 12697 | intel_psr_init(dev); |
7c8f8a70 | 12698 | |
b2784e15 | 12699 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12700 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12701 | encoder->base.possible_clones = | |
66a9278e | 12702 | intel_encoder_clones(encoder); |
79e53945 | 12703 | } |
47356eb6 | 12704 | |
dde86e2d | 12705 | intel_init_pch_refclk(dev); |
270b3042 DV |
12706 | |
12707 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12708 | } |
12709 | ||
12710 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12711 | { | |
60a5ca01 | 12712 | struct drm_device *dev = fb->dev; |
79e53945 | 12713 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12714 | |
ef2d633e | 12715 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12716 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12717 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12718 | drm_gem_object_unreference(&intel_fb->obj->base); |
12719 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12720 | kfree(intel_fb); |
12721 | } | |
12722 | ||
12723 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12724 | struct drm_file *file, |
79e53945 JB |
12725 | unsigned int *handle) |
12726 | { | |
12727 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12728 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12729 | |
05394f39 | 12730 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12731 | } |
12732 | ||
12733 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12734 | .destroy = intel_user_framebuffer_destroy, | |
12735 | .create_handle = intel_user_framebuffer_create_handle, | |
12736 | }; | |
12737 | ||
b321803d DL |
12738 | static |
12739 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
12740 | uint32_t pixel_format) | |
12741 | { | |
12742 | u32 gen = INTEL_INFO(dev)->gen; | |
12743 | ||
12744 | if (gen >= 9) { | |
12745 | /* "The stride in bytes must not exceed the of the size of 8K | |
12746 | * pixels and 32K bytes." | |
12747 | */ | |
12748 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
12749 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
12750 | return 32*1024; | |
12751 | } else if (gen >= 4) { | |
12752 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
12753 | return 16*1024; | |
12754 | else | |
12755 | return 32*1024; | |
12756 | } else if (gen >= 3) { | |
12757 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
12758 | return 8*1024; | |
12759 | else | |
12760 | return 16*1024; | |
12761 | } else { | |
12762 | /* XXX DSPC is limited to 4k tiled */ | |
12763 | return 8*1024; | |
12764 | } | |
12765 | } | |
12766 | ||
b5ea642a DV |
12767 | static int intel_framebuffer_init(struct drm_device *dev, |
12768 | struct intel_framebuffer *intel_fb, | |
12769 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12770 | struct drm_i915_gem_object *obj) | |
79e53945 | 12771 | { |
a57ce0b2 | 12772 | int aligned_height; |
79e53945 | 12773 | int ret; |
b321803d | 12774 | u32 pitch_limit, stride_alignment; |
79e53945 | 12775 | |
dd4916c5 DV |
12776 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12777 | ||
2a80eada DV |
12778 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
12779 | /* Enforce that fb modifier and tiling mode match, but only for | |
12780 | * X-tiled. This is needed for FBC. */ | |
12781 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
12782 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
12783 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
12784 | return -EINVAL; | |
12785 | } | |
12786 | } else { | |
12787 | if (obj->tiling_mode == I915_TILING_X) | |
12788 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
12789 | else if (obj->tiling_mode == I915_TILING_Y) { | |
12790 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
12791 | return -EINVAL; | |
12792 | } | |
12793 | } | |
12794 | ||
12795 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) { | |
c16ed4be | 12796 | DRM_DEBUG("hardware does not support tiling Y\n"); |
57cd6508 | 12797 | return -EINVAL; |
c16ed4be | 12798 | } |
57cd6508 | 12799 | |
b321803d DL |
12800 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
12801 | mode_cmd->pixel_format); | |
12802 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
12803 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
12804 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 12805 | return -EINVAL; |
c16ed4be | 12806 | } |
57cd6508 | 12807 | |
b321803d DL |
12808 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
12809 | mode_cmd->pixel_format); | |
a35cdaa0 | 12810 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
12811 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
12812 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 12813 | "tiled" : "linear", |
a35cdaa0 | 12814 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 12815 | return -EINVAL; |
c16ed4be | 12816 | } |
5d7bd705 | 12817 | |
2a80eada | 12818 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
12819 | mode_cmd->pitches[0] != obj->stride) { |
12820 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12821 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12822 | return -EINVAL; |
c16ed4be | 12823 | } |
5d7bd705 | 12824 | |
57779d06 | 12825 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12826 | switch (mode_cmd->pixel_format) { |
57779d06 | 12827 | case DRM_FORMAT_C8: |
04b3924d VS |
12828 | case DRM_FORMAT_RGB565: |
12829 | case DRM_FORMAT_XRGB8888: | |
12830 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12831 | break; |
12832 | case DRM_FORMAT_XRGB1555: | |
12833 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12834 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12835 | DRM_DEBUG("unsupported pixel format: %s\n", |
12836 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12837 | return -EINVAL; |
c16ed4be | 12838 | } |
57779d06 VS |
12839 | break; |
12840 | case DRM_FORMAT_XBGR8888: | |
12841 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12842 | case DRM_FORMAT_XRGB2101010: |
12843 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12844 | case DRM_FORMAT_XBGR2101010: |
12845 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12846 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12847 | DRM_DEBUG("unsupported pixel format: %s\n", |
12848 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12849 | return -EINVAL; |
c16ed4be | 12850 | } |
b5626747 | 12851 | break; |
04b3924d VS |
12852 | case DRM_FORMAT_YUYV: |
12853 | case DRM_FORMAT_UYVY: | |
12854 | case DRM_FORMAT_YVYU: | |
12855 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12856 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12857 | DRM_DEBUG("unsupported pixel format: %s\n", |
12858 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12859 | return -EINVAL; |
c16ed4be | 12860 | } |
57cd6508 CW |
12861 | break; |
12862 | default: | |
4ee62c76 VS |
12863 | DRM_DEBUG("unsupported pixel format: %s\n", |
12864 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12865 | return -EINVAL; |
12866 | } | |
12867 | ||
90f9a336 VS |
12868 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12869 | if (mode_cmd->offsets[0] != 0) | |
12870 | return -EINVAL; | |
12871 | ||
ec2c981e | 12872 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
12873 | mode_cmd->pixel_format, |
12874 | mode_cmd->modifier[0]); | |
53155c0a DV |
12875 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12876 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12877 | return -EINVAL; | |
12878 | ||
c7d73f6a DV |
12879 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12880 | intel_fb->obj = obj; | |
80075d49 | 12881 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12882 | |
79e53945 JB |
12883 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12884 | if (ret) { | |
12885 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12886 | return ret; | |
12887 | } | |
12888 | ||
79e53945 JB |
12889 | return 0; |
12890 | } | |
12891 | ||
79e53945 JB |
12892 | static struct drm_framebuffer * |
12893 | intel_user_framebuffer_create(struct drm_device *dev, | |
12894 | struct drm_file *filp, | |
308e5bcb | 12895 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12896 | { |
05394f39 | 12897 | struct drm_i915_gem_object *obj; |
79e53945 | 12898 | |
308e5bcb JB |
12899 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12900 | mode_cmd->handles[0])); | |
c8725226 | 12901 | if (&obj->base == NULL) |
cce13ff7 | 12902 | return ERR_PTR(-ENOENT); |
79e53945 | 12903 | |
d2dff872 | 12904 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12905 | } |
12906 | ||
4520f53a | 12907 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12908 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12909 | { |
12910 | } | |
12911 | #endif | |
12912 | ||
79e53945 | 12913 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12914 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12915 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
12916 | .atomic_check = intel_atomic_check, |
12917 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
12918 | }; |
12919 | ||
e70236a8 JB |
12920 | /* Set up chip specific display functions */ |
12921 | static void intel_init_display(struct drm_device *dev) | |
12922 | { | |
12923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12924 | ||
ee9300bb DV |
12925 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12926 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12927 | else if (IS_CHERRYVIEW(dev)) |
12928 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12929 | else if (IS_VALLEYVIEW(dev)) |
12930 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12931 | else if (IS_PINEVIEW(dev)) | |
12932 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12933 | else | |
12934 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12935 | ||
bc8d7dff DL |
12936 | if (INTEL_INFO(dev)->gen >= 9) { |
12937 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
12938 | dev_priv->display.get_initial_plane_config = |
12939 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
12940 | dev_priv->display.crtc_compute_clock = |
12941 | haswell_crtc_compute_clock; | |
12942 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
12943 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
12944 | dev_priv->display.off = ironlake_crtc_off; | |
12945 | dev_priv->display.update_primary_plane = | |
12946 | skylake_update_primary_plane; | |
12947 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 12948 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
12949 | dev_priv->display.get_initial_plane_config = |
12950 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
12951 | dev_priv->display.crtc_compute_clock = |
12952 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
12953 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12954 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12955 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
12956 | dev_priv->display.update_primary_plane = |
12957 | ironlake_update_primary_plane; | |
09b4ddf9 | 12958 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12959 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
12960 | dev_priv->display.get_initial_plane_config = |
12961 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
12962 | dev_priv->display.crtc_compute_clock = |
12963 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
12964 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12965 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12966 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12967 | dev_priv->display.update_primary_plane = |
12968 | ironlake_update_primary_plane; | |
89b667f8 JB |
12969 | } else if (IS_VALLEYVIEW(dev)) { |
12970 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
12971 | dev_priv->display.get_initial_plane_config = |
12972 | i9xx_get_initial_plane_config; | |
d6dfee7a | 12973 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
12974 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
12975 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12976 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12977 | dev_priv->display.update_primary_plane = |
12978 | i9xx_update_primary_plane; | |
f564048e | 12979 | } else { |
0e8ffe1b | 12980 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
12981 | dev_priv->display.get_initial_plane_config = |
12982 | i9xx_get_initial_plane_config; | |
d6dfee7a | 12983 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
12984 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12985 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12986 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12987 | dev_priv->display.update_primary_plane = |
12988 | i9xx_update_primary_plane; | |
f564048e | 12989 | } |
e70236a8 | 12990 | |
e70236a8 | 12991 | /* Returns the core display clock speed */ |
25eb05fc JB |
12992 | if (IS_VALLEYVIEW(dev)) |
12993 | dev_priv->display.get_display_clock_speed = | |
12994 | valleyview_get_display_clock_speed; | |
12995 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12996 | dev_priv->display.get_display_clock_speed = |
12997 | i945_get_display_clock_speed; | |
12998 | else if (IS_I915G(dev)) | |
12999 | dev_priv->display.get_display_clock_speed = | |
13000 | i915_get_display_clock_speed; | |
257a7ffc | 13001 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13002 | dev_priv->display.get_display_clock_speed = |
13003 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13004 | else if (IS_PINEVIEW(dev)) |
13005 | dev_priv->display.get_display_clock_speed = | |
13006 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13007 | else if (IS_I915GM(dev)) |
13008 | dev_priv->display.get_display_clock_speed = | |
13009 | i915gm_get_display_clock_speed; | |
13010 | else if (IS_I865G(dev)) | |
13011 | dev_priv->display.get_display_clock_speed = | |
13012 | i865_get_display_clock_speed; | |
f0f8a9ce | 13013 | else if (IS_I85X(dev)) |
e70236a8 JB |
13014 | dev_priv->display.get_display_clock_speed = |
13015 | i855_get_display_clock_speed; | |
13016 | else /* 852, 830 */ | |
13017 | dev_priv->display.get_display_clock_speed = | |
13018 | i830_get_display_clock_speed; | |
13019 | ||
7c10a2b5 | 13020 | if (IS_GEN5(dev)) { |
3bb11b53 | 13021 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13022 | } else if (IS_GEN6(dev)) { |
13023 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13024 | } else if (IS_IVYBRIDGE(dev)) { |
13025 | /* FIXME: detect B0+ stepping and use auto training */ | |
13026 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
3bb11b53 SJ |
13027 | dev_priv->display.modeset_global_resources = |
13028 | ivb_modeset_global_resources; | |
059b2fe9 | 13029 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13030 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13031 | } else if (IS_VALLEYVIEW(dev)) { |
13032 | dev_priv->display.modeset_global_resources = | |
13033 | valleyview_modeset_global_resources; | |
e70236a8 | 13034 | } |
8c9f3aaf | 13035 | |
8c9f3aaf JB |
13036 | switch (INTEL_INFO(dev)->gen) { |
13037 | case 2: | |
13038 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13039 | break; | |
13040 | ||
13041 | case 3: | |
13042 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13043 | break; | |
13044 | ||
13045 | case 4: | |
13046 | case 5: | |
13047 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13048 | break; | |
13049 | ||
13050 | case 6: | |
13051 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13052 | break; | |
7c9017e5 | 13053 | case 7: |
4e0bbc31 | 13054 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13055 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13056 | break; | |
830c81db | 13057 | case 9: |
ba343e02 TU |
13058 | /* Drop through - unsupported since execlist only. */ |
13059 | default: | |
13060 | /* Default just returns -ENODEV to indicate unsupported */ | |
13061 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13062 | } |
7bd688cd JN |
13063 | |
13064 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13065 | |
13066 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13067 | } |
13068 | ||
b690e96c JB |
13069 | /* |
13070 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13071 | * resume, or other times. This quirk makes sure that's the case for | |
13072 | * affected systems. | |
13073 | */ | |
0206e353 | 13074 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13075 | { |
13076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13077 | ||
13078 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13079 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13080 | } |
13081 | ||
b6b5d049 VS |
13082 | static void quirk_pipeb_force(struct drm_device *dev) |
13083 | { | |
13084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13085 | ||
13086 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13087 | DRM_INFO("applying pipe b force quirk\n"); | |
13088 | } | |
13089 | ||
435793df KP |
13090 | /* |
13091 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13092 | */ | |
13093 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13094 | { | |
13095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13096 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13097 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13098 | } |
13099 | ||
4dca20ef | 13100 | /* |
5a15ab5b CE |
13101 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13102 | * brightness value | |
4dca20ef CE |
13103 | */ |
13104 | static void quirk_invert_brightness(struct drm_device *dev) | |
13105 | { | |
13106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13107 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13108 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13109 | } |
13110 | ||
9c72cc6f SD |
13111 | /* Some VBT's incorrectly indicate no backlight is present */ |
13112 | static void quirk_backlight_present(struct drm_device *dev) | |
13113 | { | |
13114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13115 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13116 | DRM_INFO("applying backlight present quirk\n"); | |
13117 | } | |
13118 | ||
b690e96c JB |
13119 | struct intel_quirk { |
13120 | int device; | |
13121 | int subsystem_vendor; | |
13122 | int subsystem_device; | |
13123 | void (*hook)(struct drm_device *dev); | |
13124 | }; | |
13125 | ||
5f85f176 EE |
13126 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13127 | struct intel_dmi_quirk { | |
13128 | void (*hook)(struct drm_device *dev); | |
13129 | const struct dmi_system_id (*dmi_id_list)[]; | |
13130 | }; | |
13131 | ||
13132 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13133 | { | |
13134 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13135 | return 1; | |
13136 | } | |
13137 | ||
13138 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13139 | { | |
13140 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13141 | { | |
13142 | .callback = intel_dmi_reverse_brightness, | |
13143 | .ident = "NCR Corporation", | |
13144 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13145 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13146 | }, | |
13147 | }, | |
13148 | { } /* terminating entry */ | |
13149 | }, | |
13150 | .hook = quirk_invert_brightness, | |
13151 | }, | |
13152 | }; | |
13153 | ||
c43b5634 | 13154 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13155 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13156 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13157 | |
b690e96c JB |
13158 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13159 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13160 | ||
b690e96c JB |
13161 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13162 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13163 | ||
5f080c0f VS |
13164 | /* 830 needs to leave pipe A & dpll A up */ |
13165 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13166 | ||
b6b5d049 VS |
13167 | /* 830 needs to leave pipe B & dpll B up */ |
13168 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13169 | ||
435793df KP |
13170 | /* Lenovo U160 cannot use SSC on LVDS */ |
13171 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13172 | |
13173 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13174 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13175 | |
be505f64 AH |
13176 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13177 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13178 | ||
13179 | /* Acer/eMachines G725 */ | |
13180 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13181 | ||
13182 | /* Acer/eMachines e725 */ | |
13183 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13184 | ||
13185 | /* Acer/Packard Bell NCL20 */ | |
13186 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13187 | ||
13188 | /* Acer Aspire 4736Z */ | |
13189 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13190 | |
13191 | /* Acer Aspire 5336 */ | |
13192 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13193 | |
13194 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13195 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13196 | |
dfb3d47b SD |
13197 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13198 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13199 | ||
b2a9601c | 13200 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13201 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13202 | ||
d4967d8c SD |
13203 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13204 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13205 | |
13206 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13207 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
13208 | }; |
13209 | ||
13210 | static void intel_init_quirks(struct drm_device *dev) | |
13211 | { | |
13212 | struct pci_dev *d = dev->pdev; | |
13213 | int i; | |
13214 | ||
13215 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13216 | struct intel_quirk *q = &intel_quirks[i]; | |
13217 | ||
13218 | if (d->device == q->device && | |
13219 | (d->subsystem_vendor == q->subsystem_vendor || | |
13220 | q->subsystem_vendor == PCI_ANY_ID) && | |
13221 | (d->subsystem_device == q->subsystem_device || | |
13222 | q->subsystem_device == PCI_ANY_ID)) | |
13223 | q->hook(dev); | |
13224 | } | |
5f85f176 EE |
13225 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13226 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13227 | intel_dmi_quirks[i].hook(dev); | |
13228 | } | |
b690e96c JB |
13229 | } |
13230 | ||
9cce37f4 JB |
13231 | /* Disable the VGA plane that we never use */ |
13232 | static void i915_disable_vga(struct drm_device *dev) | |
13233 | { | |
13234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13235 | u8 sr1; | |
766aa1c4 | 13236 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 13237 | |
2b37c616 | 13238 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 13239 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13240 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13241 | sr1 = inb(VGA_SR_DATA); |
13242 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
13243 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
13244 | udelay(300); | |
13245 | ||
01f5a626 | 13246 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13247 | POSTING_READ(vga_reg); |
13248 | } | |
13249 | ||
f817586c DV |
13250 | void intel_modeset_init_hw(struct drm_device *dev) |
13251 | { | |
a8f78b58 ED |
13252 | intel_prepare_ddi(dev); |
13253 | ||
f8bf63fd VS |
13254 | if (IS_VALLEYVIEW(dev)) |
13255 | vlv_update_cdclk(dev); | |
13256 | ||
f817586c DV |
13257 | intel_init_clock_gating(dev); |
13258 | ||
8090c6b9 | 13259 | intel_enable_gt_powersave(dev); |
f817586c DV |
13260 | } |
13261 | ||
79e53945 JB |
13262 | void intel_modeset_init(struct drm_device *dev) |
13263 | { | |
652c393a | 13264 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13265 | int sprite, ret; |
8cc87b75 | 13266 | enum pipe pipe; |
46f297fb | 13267 | struct intel_crtc *crtc; |
79e53945 JB |
13268 | |
13269 | drm_mode_config_init(dev); | |
13270 | ||
13271 | dev->mode_config.min_width = 0; | |
13272 | dev->mode_config.min_height = 0; | |
13273 | ||
019d96cb DA |
13274 | dev->mode_config.preferred_depth = 24; |
13275 | dev->mode_config.prefer_shadow = 1; | |
13276 | ||
25bab385 TU |
13277 | dev->mode_config.allow_fb_modifiers = true; |
13278 | ||
e6ecefaa | 13279 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13280 | |
b690e96c JB |
13281 | intel_init_quirks(dev); |
13282 | ||
1fa61106 ED |
13283 | intel_init_pm(dev); |
13284 | ||
e3c74757 BW |
13285 | if (INTEL_INFO(dev)->num_pipes == 0) |
13286 | return; | |
13287 | ||
e70236a8 | 13288 | intel_init_display(dev); |
7c10a2b5 | 13289 | intel_init_audio(dev); |
e70236a8 | 13290 | |
a6c45cf0 CW |
13291 | if (IS_GEN2(dev)) { |
13292 | dev->mode_config.max_width = 2048; | |
13293 | dev->mode_config.max_height = 2048; | |
13294 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13295 | dev->mode_config.max_width = 4096; |
13296 | dev->mode_config.max_height = 4096; | |
79e53945 | 13297 | } else { |
a6c45cf0 CW |
13298 | dev->mode_config.max_width = 8192; |
13299 | dev->mode_config.max_height = 8192; | |
79e53945 | 13300 | } |
068be561 | 13301 | |
dc41c154 VS |
13302 | if (IS_845G(dev) || IS_I865G(dev)) { |
13303 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13304 | dev->mode_config.cursor_height = 1023; | |
13305 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13306 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13307 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13308 | } else { | |
13309 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13310 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13311 | } | |
13312 | ||
5d4545ae | 13313 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13314 | |
28c97730 | 13315 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13316 | INTEL_INFO(dev)->num_pipes, |
13317 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13318 | |
055e393f | 13319 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13320 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
13321 | for_each_sprite(pipe, sprite) { |
13322 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 13323 | if (ret) |
06da8da2 | 13324 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13325 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13326 | } |
79e53945 JB |
13327 | } |
13328 | ||
f42bb70d JB |
13329 | intel_init_dpio(dev); |
13330 | ||
e72f9fbf | 13331 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13332 | |
9cce37f4 JB |
13333 | /* Just disable it once at startup */ |
13334 | i915_disable_vga(dev); | |
79e53945 | 13335 | intel_setup_outputs(dev); |
11be49eb CW |
13336 | |
13337 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 13338 | intel_fbc_disable(dev); |
fa9fa083 | 13339 | |
6e9f798d | 13340 | drm_modeset_lock_all(dev); |
fa9fa083 | 13341 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13342 | drm_modeset_unlock_all(dev); |
46f297fb | 13343 | |
d3fcc808 | 13344 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13345 | if (!crtc->active) |
13346 | continue; | |
13347 | ||
46f297fb | 13348 | /* |
46f297fb JB |
13349 | * Note that reserving the BIOS fb up front prevents us |
13350 | * from stuffing other stolen allocations like the ring | |
13351 | * on top. This prevents some ugliness at boot time, and | |
13352 | * can even allow for smooth boot transitions if the BIOS | |
13353 | * fb is large enough for the active pipe configuration. | |
13354 | */ | |
5724dbd1 DL |
13355 | if (dev_priv->display.get_initial_plane_config) { |
13356 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
13357 | &crtc->plane_config); |
13358 | /* | |
13359 | * If the fb is shared between multiple heads, we'll | |
13360 | * just get the first one. | |
13361 | */ | |
484b41dd | 13362 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13363 | } |
46f297fb | 13364 | } |
2c7111db CW |
13365 | } |
13366 | ||
7fad798e DV |
13367 | static void intel_enable_pipe_a(struct drm_device *dev) |
13368 | { | |
13369 | struct intel_connector *connector; | |
13370 | struct drm_connector *crt = NULL; | |
13371 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13372 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13373 | |
13374 | /* We can't just switch on the pipe A, we need to set things up with a | |
13375 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13376 | * by enabling the load detect pipe once. */ | |
13377 | list_for_each_entry(connector, | |
13378 | &dev->mode_config.connector_list, | |
13379 | base.head) { | |
13380 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
13381 | crt = &connector->base; | |
13382 | break; | |
13383 | } | |
13384 | } | |
13385 | ||
13386 | if (!crt) | |
13387 | return; | |
13388 | ||
208bf9fd VS |
13389 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13390 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13391 | } |
13392 | ||
fa555837 DV |
13393 | static bool |
13394 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13395 | { | |
7eb552ae BW |
13396 | struct drm_device *dev = crtc->base.dev; |
13397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13398 | u32 reg, val; |
13399 | ||
7eb552ae | 13400 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13401 | return true; |
13402 | ||
13403 | reg = DSPCNTR(!crtc->plane); | |
13404 | val = I915_READ(reg); | |
13405 | ||
13406 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13407 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13408 | return false; | |
13409 | ||
13410 | return true; | |
13411 | } | |
13412 | ||
24929352 DV |
13413 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13414 | { | |
13415 | struct drm_device *dev = crtc->base.dev; | |
13416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13417 | u32 reg; |
24929352 | 13418 | |
24929352 | 13419 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 13420 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
13421 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13422 | ||
d3eaf884 | 13423 | /* restore vblank interrupts to correct state */ |
9625604c | 13424 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
13425 | if (crtc->active) { |
13426 | update_scanline_offset(crtc); | |
9625604c DV |
13427 | drm_crtc_vblank_on(&crtc->base); |
13428 | } | |
d3eaf884 | 13429 | |
24929352 | 13430 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13431 | * disable the crtc (and hence change the state) if it is wrong. Note |
13432 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13433 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13434 | struct intel_connector *connector; |
13435 | bool plane; | |
13436 | ||
24929352 DV |
13437 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13438 | crtc->base.base.id); | |
13439 | ||
13440 | /* Pipe has the wrong plane attached and the plane is active. | |
13441 | * Temporarily change the plane mapping and disable everything | |
13442 | * ... */ | |
13443 | plane = crtc->plane; | |
13444 | crtc->plane = !plane; | |
9c8958bc | 13445 | crtc->primary_enabled = true; |
24929352 DV |
13446 | dev_priv->display.crtc_disable(&crtc->base); |
13447 | crtc->plane = plane; | |
13448 | ||
13449 | /* ... and break all links. */ | |
13450 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13451 | base.head) { | |
13452 | if (connector->encoder->base.crtc != &crtc->base) | |
13453 | continue; | |
13454 | ||
7f1950fb EE |
13455 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13456 | connector->base.encoder = NULL; | |
24929352 | 13457 | } |
7f1950fb EE |
13458 | /* multiple connectors may have the same encoder: |
13459 | * handle them and break crtc link separately */ | |
13460 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13461 | base.head) | |
13462 | if (connector->encoder->base.crtc == &crtc->base) { | |
13463 | connector->encoder->base.crtc = NULL; | |
13464 | connector->encoder->connectors_active = false; | |
13465 | } | |
24929352 DV |
13466 | |
13467 | WARN_ON(crtc->active); | |
83d65738 | 13468 | crtc->base.state->enable = false; |
24929352 DV |
13469 | crtc->base.enabled = false; |
13470 | } | |
24929352 | 13471 | |
7fad798e DV |
13472 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13473 | crtc->pipe == PIPE_A && !crtc->active) { | |
13474 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13475 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13476 | * call below we restore the pipe to the right state, but leave | |
13477 | * the required bits on. */ | |
13478 | intel_enable_pipe_a(dev); | |
13479 | } | |
13480 | ||
24929352 DV |
13481 | /* Adjust the state of the output pipe according to whether we |
13482 | * have active connectors/encoders. */ | |
13483 | intel_crtc_update_dpms(&crtc->base); | |
13484 | ||
83d65738 | 13485 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
13486 | struct intel_encoder *encoder; |
13487 | ||
13488 | /* This can happen either due to bugs in the get_hw_state | |
13489 | * functions or because the pipe is force-enabled due to the | |
13490 | * pipe A quirk. */ | |
13491 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13492 | crtc->base.base.id, | |
83d65738 | 13493 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
13494 | crtc->active ? "enabled" : "disabled"); |
13495 | ||
83d65738 | 13496 | crtc->base.state->enable = crtc->active; |
24929352 DV |
13497 | crtc->base.enabled = crtc->active; |
13498 | ||
13499 | /* Because we only establish the connector -> encoder -> | |
13500 | * crtc links if something is active, this means the | |
13501 | * crtc is now deactivated. Break the links. connector | |
13502 | * -> encoder links are only establish when things are | |
13503 | * actually up, hence no need to break them. */ | |
13504 | WARN_ON(crtc->active); | |
13505 | ||
13506 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13507 | WARN_ON(encoder->connectors_active); | |
13508 | encoder->base.crtc = NULL; | |
13509 | } | |
13510 | } | |
c5ab3bc0 | 13511 | |
a3ed6aad | 13512 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13513 | /* |
13514 | * We start out with underrun reporting disabled to avoid races. | |
13515 | * For correct bookkeeping mark this on active crtcs. | |
13516 | * | |
c5ab3bc0 DV |
13517 | * Also on gmch platforms we dont have any hardware bits to |
13518 | * disable the underrun reporting. Which means we need to start | |
13519 | * out with underrun reporting disabled also on inactive pipes, | |
13520 | * since otherwise we'll complain about the garbage we read when | |
13521 | * e.g. coming up after runtime pm. | |
13522 | * | |
4cc31489 DV |
13523 | * No protection against concurrent access is required - at |
13524 | * worst a fifo underrun happens which also sets this to false. | |
13525 | */ | |
13526 | crtc->cpu_fifo_underrun_disabled = true; | |
13527 | crtc->pch_fifo_underrun_disabled = true; | |
13528 | } | |
24929352 DV |
13529 | } |
13530 | ||
13531 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13532 | { | |
13533 | struct intel_connector *connector; | |
13534 | struct drm_device *dev = encoder->base.dev; | |
13535 | ||
13536 | /* We need to check both for a crtc link (meaning that the | |
13537 | * encoder is active and trying to read from a pipe) and the | |
13538 | * pipe itself being active. */ | |
13539 | bool has_active_crtc = encoder->base.crtc && | |
13540 | to_intel_crtc(encoder->base.crtc)->active; | |
13541 | ||
13542 | if (encoder->connectors_active && !has_active_crtc) { | |
13543 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13544 | encoder->base.base.id, | |
8e329a03 | 13545 | encoder->base.name); |
24929352 DV |
13546 | |
13547 | /* Connector is active, but has no active pipe. This is | |
13548 | * fallout from our resume register restoring. Disable | |
13549 | * the encoder manually again. */ | |
13550 | if (encoder->base.crtc) { | |
13551 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13552 | encoder->base.base.id, | |
8e329a03 | 13553 | encoder->base.name); |
24929352 | 13554 | encoder->disable(encoder); |
a62d1497 VS |
13555 | if (encoder->post_disable) |
13556 | encoder->post_disable(encoder); | |
24929352 | 13557 | } |
7f1950fb EE |
13558 | encoder->base.crtc = NULL; |
13559 | encoder->connectors_active = false; | |
24929352 DV |
13560 | |
13561 | /* Inconsistent output/port/pipe state happens presumably due to | |
13562 | * a bug in one of the get_hw_state functions. Or someplace else | |
13563 | * in our code, like the register restore mess on resume. Clamp | |
13564 | * things to off as a safer default. */ | |
13565 | list_for_each_entry(connector, | |
13566 | &dev->mode_config.connector_list, | |
13567 | base.head) { | |
13568 | if (connector->encoder != encoder) | |
13569 | continue; | |
7f1950fb EE |
13570 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13571 | connector->base.encoder = NULL; | |
24929352 DV |
13572 | } |
13573 | } | |
13574 | /* Enabled encoders without active connectors will be fixed in | |
13575 | * the crtc fixup. */ | |
13576 | } | |
13577 | ||
04098753 | 13578 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13579 | { |
13580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13581 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13582 | |
04098753 ID |
13583 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13584 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13585 | i915_disable_vga(dev); | |
13586 | } | |
13587 | } | |
13588 | ||
13589 | void i915_redisable_vga(struct drm_device *dev) | |
13590 | { | |
13591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13592 | ||
8dc8a27c PZ |
13593 | /* This function can be called both from intel_modeset_setup_hw_state or |
13594 | * at a very early point in our resume sequence, where the power well | |
13595 | * structures are not yet restored. Since this function is at a very | |
13596 | * paranoid "someone might have enabled VGA while we were not looking" | |
13597 | * level, just check if the power well is enabled instead of trying to | |
13598 | * follow the "don't touch the power well if we don't need it" policy | |
13599 | * the rest of the driver uses. */ | |
f458ebbc | 13600 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13601 | return; |
13602 | ||
04098753 | 13603 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13604 | } |
13605 | ||
98ec7739 VS |
13606 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13607 | { | |
13608 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13609 | ||
13610 | if (!crtc->active) | |
13611 | return false; | |
13612 | ||
13613 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13614 | } | |
13615 | ||
30e984df | 13616 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13617 | { |
13618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13619 | enum pipe pipe; | |
24929352 DV |
13620 | struct intel_crtc *crtc; |
13621 | struct intel_encoder *encoder; | |
13622 | struct intel_connector *connector; | |
5358901f | 13623 | int i; |
24929352 | 13624 | |
d3fcc808 | 13625 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 13626 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 13627 | |
6e3c9717 | 13628 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 13629 | |
0e8ffe1b | 13630 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 13631 | crtc->config); |
24929352 | 13632 | |
83d65738 | 13633 | crtc->base.state->enable = crtc->active; |
24929352 | 13634 | crtc->base.enabled = crtc->active; |
98ec7739 | 13635 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13636 | |
13637 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13638 | crtc->base.base.id, | |
13639 | crtc->active ? "enabled" : "disabled"); | |
13640 | } | |
13641 | ||
5358901f DV |
13642 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13643 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13644 | ||
3e369b76 ACO |
13645 | pll->on = pll->get_hw_state(dev_priv, pll, |
13646 | &pll->config.hw_state); | |
5358901f | 13647 | pll->active = 0; |
3e369b76 | 13648 | pll->config.crtc_mask = 0; |
d3fcc808 | 13649 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 13650 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 13651 | pll->active++; |
3e369b76 | 13652 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 13653 | } |
5358901f | 13654 | } |
5358901f | 13655 | |
1e6f2ddc | 13656 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 13657 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 13658 | |
3e369b76 | 13659 | if (pll->config.crtc_mask) |
bd2bb1b9 | 13660 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
13661 | } |
13662 | ||
b2784e15 | 13663 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13664 | pipe = 0; |
13665 | ||
13666 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13667 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13668 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 13669 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
13670 | } else { |
13671 | encoder->base.crtc = NULL; | |
13672 | } | |
13673 | ||
13674 | encoder->connectors_active = false; | |
6f2bcceb | 13675 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13676 | encoder->base.base.id, |
8e329a03 | 13677 | encoder->base.name, |
24929352 | 13678 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13679 | pipe_name(pipe)); |
24929352 DV |
13680 | } |
13681 | ||
13682 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13683 | base.head) { | |
13684 | if (connector->get_hw_state(connector)) { | |
13685 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13686 | connector->encoder->connectors_active = true; | |
13687 | connector->base.encoder = &connector->encoder->base; | |
13688 | } else { | |
13689 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13690 | connector->base.encoder = NULL; | |
13691 | } | |
13692 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13693 | connector->base.base.id, | |
c23cc417 | 13694 | connector->base.name, |
24929352 DV |
13695 | connector->base.encoder ? "enabled" : "disabled"); |
13696 | } | |
30e984df DV |
13697 | } |
13698 | ||
13699 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13700 | * and i915 state tracking structures. */ | |
13701 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13702 | bool force_restore) | |
13703 | { | |
13704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13705 | enum pipe pipe; | |
30e984df DV |
13706 | struct intel_crtc *crtc; |
13707 | struct intel_encoder *encoder; | |
35c95375 | 13708 | int i; |
30e984df DV |
13709 | |
13710 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13711 | |
babea61d JB |
13712 | /* |
13713 | * Now that we have the config, copy it to each CRTC struct | |
13714 | * Note that this could go away if we move to using crtc_config | |
13715 | * checking everywhere. | |
13716 | */ | |
d3fcc808 | 13717 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13718 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
13719 | intel_mode_from_pipe_config(&crtc->base.mode, |
13720 | crtc->config); | |
babea61d JB |
13721 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13722 | crtc->base.base.id); | |
13723 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13724 | } | |
13725 | } | |
13726 | ||
24929352 | 13727 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13728 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13729 | intel_sanitize_encoder(encoder); |
13730 | } | |
13731 | ||
055e393f | 13732 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13733 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13734 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
13735 | intel_dump_pipe_config(crtc, crtc->config, |
13736 | "[setup_hw_state]"); | |
24929352 | 13737 | } |
9a935856 | 13738 | |
35c95375 DV |
13739 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13740 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13741 | ||
13742 | if (!pll->on || pll->active) | |
13743 | continue; | |
13744 | ||
13745 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13746 | ||
13747 | pll->disable(dev_priv, pll); | |
13748 | pll->on = false; | |
13749 | } | |
13750 | ||
3078999f PB |
13751 | if (IS_GEN9(dev)) |
13752 | skl_wm_get_hw_state(dev); | |
13753 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
13754 | ilk_wm_get_hw_state(dev); |
13755 | ||
45e2b5f6 | 13756 | if (force_restore) { |
7d0bc1ea VS |
13757 | i915_redisable_vga(dev); |
13758 | ||
f30da187 DV |
13759 | /* |
13760 | * We need to use raw interfaces for restoring state to avoid | |
13761 | * checking (bogus) intermediate states. | |
13762 | */ | |
055e393f | 13763 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13764 | struct drm_crtc *crtc = |
13765 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 13766 | |
7f27126e JB |
13767 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
13768 | crtc->primary->fb); | |
45e2b5f6 DV |
13769 | } |
13770 | } else { | |
13771 | intel_modeset_update_staged_output_state(dev); | |
13772 | } | |
8af6cf88 DV |
13773 | |
13774 | intel_modeset_check_state(dev); | |
2c7111db CW |
13775 | } |
13776 | ||
13777 | void intel_modeset_gem_init(struct drm_device *dev) | |
13778 | { | |
92122789 | 13779 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 13780 | struct drm_crtc *c; |
2ff8fde1 | 13781 | struct drm_i915_gem_object *obj; |
484b41dd | 13782 | |
ae48434c ID |
13783 | mutex_lock(&dev->struct_mutex); |
13784 | intel_init_gt_powersave(dev); | |
13785 | mutex_unlock(&dev->struct_mutex); | |
13786 | ||
92122789 JB |
13787 | /* |
13788 | * There may be no VBT; and if the BIOS enabled SSC we can | |
13789 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
13790 | * BIOS isn't using it, don't assume it will work even if the VBT | |
13791 | * indicates as much. | |
13792 | */ | |
13793 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
13794 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
13795 | DREF_SSC1_ENABLE); | |
13796 | ||
1833b134 | 13797 | intel_modeset_init_hw(dev); |
02e792fb DV |
13798 | |
13799 | intel_setup_overlay(dev); | |
484b41dd JB |
13800 | |
13801 | /* | |
13802 | * Make sure any fbs we allocated at startup are properly | |
13803 | * pinned & fenced. When we do the allocation it's too early | |
13804 | * for this. | |
13805 | */ | |
13806 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13807 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13808 | obj = intel_fb_obj(c->primary->fb); |
13809 | if (obj == NULL) | |
484b41dd JB |
13810 | continue; |
13811 | ||
850c4cdc TU |
13812 | if (intel_pin_and_fence_fb_obj(c->primary, |
13813 | c->primary->fb, | |
13814 | NULL)) { | |
484b41dd JB |
13815 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13816 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13817 | drm_framebuffer_unreference(c->primary->fb); |
13818 | c->primary->fb = NULL; | |
afd65eb4 | 13819 | update_state_fb(c->primary); |
484b41dd JB |
13820 | } |
13821 | } | |
13822 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
13823 | |
13824 | intel_backlight_register(dev); | |
79e53945 JB |
13825 | } |
13826 | ||
4932e2c3 ID |
13827 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13828 | { | |
13829 | struct drm_connector *connector = &intel_connector->base; | |
13830 | ||
13831 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13832 | drm_connector_unregister(connector); |
4932e2c3 ID |
13833 | } |
13834 | ||
79e53945 JB |
13835 | void intel_modeset_cleanup(struct drm_device *dev) |
13836 | { | |
652c393a | 13837 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13838 | struct drm_connector *connector; |
652c393a | 13839 | |
2eb5252e ID |
13840 | intel_disable_gt_powersave(dev); |
13841 | ||
0962c3c9 VS |
13842 | intel_backlight_unregister(dev); |
13843 | ||
fd0c0642 DV |
13844 | /* |
13845 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 13846 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
13847 | * experience fancy races otherwise. |
13848 | */ | |
2aeb7d3a | 13849 | intel_irq_uninstall(dev_priv); |
eb21b92b | 13850 | |
fd0c0642 DV |
13851 | /* |
13852 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13853 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13854 | */ | |
f87ea761 | 13855 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13856 | |
652c393a JB |
13857 | mutex_lock(&dev->struct_mutex); |
13858 | ||
723bfd70 JB |
13859 | intel_unregister_dsm_handler(); |
13860 | ||
7ff0ebcc | 13861 | intel_fbc_disable(dev); |
e70236a8 | 13862 | |
930ebb46 DV |
13863 | ironlake_teardown_rc6(dev); |
13864 | ||
69341a5e KH |
13865 | mutex_unlock(&dev->struct_mutex); |
13866 | ||
1630fe75 CW |
13867 | /* flush any delayed tasks or pending work */ |
13868 | flush_scheduled_work(); | |
13869 | ||
db31af1d JN |
13870 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13871 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13872 | struct intel_connector *intel_connector; |
13873 | ||
13874 | intel_connector = to_intel_connector(connector); | |
13875 | intel_connector->unregister(intel_connector); | |
db31af1d | 13876 | } |
d9255d57 | 13877 | |
79e53945 | 13878 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13879 | |
13880 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13881 | |
13882 | mutex_lock(&dev->struct_mutex); | |
13883 | intel_cleanup_gt_powersave(dev); | |
13884 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13885 | } |
13886 | ||
f1c79df3 ZW |
13887 | /* |
13888 | * Return which encoder is currently attached for connector. | |
13889 | */ | |
df0e9248 | 13890 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13891 | { |
df0e9248 CW |
13892 | return &intel_attached_encoder(connector)->base; |
13893 | } | |
f1c79df3 | 13894 | |
df0e9248 CW |
13895 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13896 | struct intel_encoder *encoder) | |
13897 | { | |
13898 | connector->encoder = encoder; | |
13899 | drm_mode_connector_attach_encoder(&connector->base, | |
13900 | &encoder->base); | |
79e53945 | 13901 | } |
28d52043 DA |
13902 | |
13903 | /* | |
13904 | * set vga decode state - true == enable VGA decode | |
13905 | */ | |
13906 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13907 | { | |
13908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13909 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13910 | u16 gmch_ctrl; |
13911 | ||
75fa041d CW |
13912 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13913 | DRM_ERROR("failed to read control word\n"); | |
13914 | return -EIO; | |
13915 | } | |
13916 | ||
c0cc8a55 CW |
13917 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13918 | return 0; | |
13919 | ||
28d52043 DA |
13920 | if (state) |
13921 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13922 | else | |
13923 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13924 | |
13925 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13926 | DRM_ERROR("failed to write control word\n"); | |
13927 | return -EIO; | |
13928 | } | |
13929 | ||
28d52043 DA |
13930 | return 0; |
13931 | } | |
c4a1d9e4 | 13932 | |
c4a1d9e4 | 13933 | struct intel_display_error_state { |
ff57f1b0 PZ |
13934 | |
13935 | u32 power_well_driver; | |
13936 | ||
63b66e5b CW |
13937 | int num_transcoders; |
13938 | ||
c4a1d9e4 CW |
13939 | struct intel_cursor_error_state { |
13940 | u32 control; | |
13941 | u32 position; | |
13942 | u32 base; | |
13943 | u32 size; | |
52331309 | 13944 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13945 | |
13946 | struct intel_pipe_error_state { | |
ddf9c536 | 13947 | bool power_domain_on; |
c4a1d9e4 | 13948 | u32 source; |
f301b1e1 | 13949 | u32 stat; |
52331309 | 13950 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13951 | |
13952 | struct intel_plane_error_state { | |
13953 | u32 control; | |
13954 | u32 stride; | |
13955 | u32 size; | |
13956 | u32 pos; | |
13957 | u32 addr; | |
13958 | u32 surface; | |
13959 | u32 tile_offset; | |
52331309 | 13960 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13961 | |
13962 | struct intel_transcoder_error_state { | |
ddf9c536 | 13963 | bool power_domain_on; |
63b66e5b CW |
13964 | enum transcoder cpu_transcoder; |
13965 | ||
13966 | u32 conf; | |
13967 | ||
13968 | u32 htotal; | |
13969 | u32 hblank; | |
13970 | u32 hsync; | |
13971 | u32 vtotal; | |
13972 | u32 vblank; | |
13973 | u32 vsync; | |
13974 | } transcoder[4]; | |
c4a1d9e4 CW |
13975 | }; |
13976 | ||
13977 | struct intel_display_error_state * | |
13978 | intel_display_capture_error_state(struct drm_device *dev) | |
13979 | { | |
fbee40df | 13980 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13981 | struct intel_display_error_state *error; |
63b66e5b CW |
13982 | int transcoders[] = { |
13983 | TRANSCODER_A, | |
13984 | TRANSCODER_B, | |
13985 | TRANSCODER_C, | |
13986 | TRANSCODER_EDP, | |
13987 | }; | |
c4a1d9e4 CW |
13988 | int i; |
13989 | ||
63b66e5b CW |
13990 | if (INTEL_INFO(dev)->num_pipes == 0) |
13991 | return NULL; | |
13992 | ||
9d1cb914 | 13993 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13994 | if (error == NULL) |
13995 | return NULL; | |
13996 | ||
190be112 | 13997 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13998 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13999 | ||
055e393f | 14000 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14001 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14002 | __intel_display_power_is_enabled(dev_priv, |
14003 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14004 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14005 | continue; |
14006 | ||
5efb3e28 VS |
14007 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14008 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14009 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14010 | |
14011 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14012 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14013 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14014 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14015 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14016 | } | |
ca291363 PZ |
14017 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14018 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14019 | if (INTEL_INFO(dev)->gen >= 4) { |
14020 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14021 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14022 | } | |
14023 | ||
c4a1d9e4 | 14024 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14025 | |
3abfce77 | 14026 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14027 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14028 | } |
14029 | ||
14030 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14031 | if (HAS_DDI(dev_priv->dev)) | |
14032 | error->num_transcoders++; /* Account for eDP. */ | |
14033 | ||
14034 | for (i = 0; i < error->num_transcoders; i++) { | |
14035 | enum transcoder cpu_transcoder = transcoders[i]; | |
14036 | ||
ddf9c536 | 14037 | error->transcoder[i].power_domain_on = |
f458ebbc | 14038 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14039 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14040 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14041 | continue; |
14042 | ||
63b66e5b CW |
14043 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14044 | ||
14045 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14046 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14047 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14048 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14049 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14050 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14051 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14052 | } |
14053 | ||
14054 | return error; | |
14055 | } | |
14056 | ||
edc3d884 MK |
14057 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14058 | ||
c4a1d9e4 | 14059 | void |
edc3d884 | 14060 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14061 | struct drm_device *dev, |
14062 | struct intel_display_error_state *error) | |
14063 | { | |
055e393f | 14064 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14065 | int i; |
14066 | ||
63b66e5b CW |
14067 | if (!error) |
14068 | return; | |
14069 | ||
edc3d884 | 14070 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14071 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14072 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14073 | error->power_well_driver); |
055e393f | 14074 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14075 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14076 | err_printf(m, " Power: %s\n", |
14077 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14078 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14079 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14080 | |
14081 | err_printf(m, "Plane [%d]:\n", i); | |
14082 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14083 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14084 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14085 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14086 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14087 | } |
4b71a570 | 14088 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14089 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14090 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14091 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14092 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14093 | } |
14094 | ||
edc3d884 MK |
14095 | err_printf(m, "Cursor [%d]:\n", i); |
14096 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14097 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14098 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14099 | } |
63b66e5b CW |
14100 | |
14101 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14102 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14103 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14104 | err_printf(m, " Power: %s\n", |
14105 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14106 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14107 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14108 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14109 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14110 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14111 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14112 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14113 | } | |
c4a1d9e4 | 14114 | } |
e2fcdaa9 VS |
14115 | |
14116 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14117 | { | |
14118 | struct intel_crtc *crtc; | |
14119 | ||
14120 | for_each_intel_crtc(dev, crtc) { | |
14121 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14122 | |
5e2d7afc | 14123 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14124 | |
14125 | work = crtc->unpin_work; | |
14126 | ||
14127 | if (work && work->event && | |
14128 | work->event->base.file_priv == file) { | |
14129 | kfree(work->event); | |
14130 | work->event = NULL; | |
14131 | } | |
14132 | ||
5e2d7afc | 14133 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14134 | } |
14135 | } |