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drm/i915: Add a for_each_intel_connector macro
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
c196e1d6 40#include <drm/drm_atomic_helper.h>
760285e7
DH		 41#include <drm/drm_dp_helper.h>
42#include <drm/drm_crtc_helper.h>
465c120c
MR		 43#include <drm/drm_plane_helper.h>
44#include <drm/drm_rect.h>
c0f372b3 45#include <linux/dma_remapping.h>
79e53945 46
465c120c
MR		 47/* Primary plane formats supported by all gen */
48#define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54/* Primary plane formats for gen <= 3 */
55static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59};
60
61/* Primary plane formats for gen >= 4 */
62static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70};
71
3d7d6510
MR		 72/* Cursor formats */
73static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75};
76
6b383a7f 77static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 78
f1f644dc 79static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 80 struct intel_crtc_state *pipe_config);
18442d08 81static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 82 struct intel_crtc_state *pipe_config);
f1f644dc 83
e7457a9a
DL		 84static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
eb1bfe80
JB		 86static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
5b18e57c
DV		 90static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 92static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
29407aab 95static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 96static void haswell_set_pipeconf(struct drm_crtc *crtc);
97static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 98static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 99 const struct intel_crtc_state *pipe_config);
d288f65f 100static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 102static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 104
0e32b39c
DA		 105static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106{
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111}
112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
6b4bf1c4
VS		 401static void vlv_clock(int refclk, intel_clock_t *clock)
402{
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
fb03ac01
VS		 407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 409}
410
e0638cdf
PZ		 411/**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
4093561b 414bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 415{
409ee761 416 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 417 struct intel_encoder *encoder;
418
409ee761 419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 420 if (encoder->type == type)
421 return true;
422
423 return false;
424}
425
d0737e1d
ACO		 426/**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433{
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442}
443
409ee761 444static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
1b894b59 445 int refclk)
2c07245f 446{
409ee761 447 struct drm_device *dev = crtc->base.dev;
2c07245f 448 const intel_limit_t *limit;
b91ad0ec 449
d0737e1d 450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev)) {
1b894b59 452 if (refclk == 100000)
b91ad0ec
ZW		 453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
1b894b59 457 if (refclk == 100000)
b91ad0ec
ZW		 458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
c6bb3538 462 } else
b91ad0ec 463 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 464
465 return limit;
466}
467
409ee761 468static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
044c7c41 469{
409ee761 470 struct drm_device *dev = crtc->base.dev;
044c7c41
ML		 471 const intel_limit_t *limit;
472
d0737e1d 473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 474 if (intel_is_dual_link_lvds(dev))
e4b36699 475 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 476 else
e4b36699 477 limit = &intel_limits_g4x_single_channel_lvds;
d0737e1d
ACO		 478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 480 limit = &intel_limits_g4x_hdmi;
d0737e1d 481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 482 limit = &intel_limits_g4x_sdvo;
044c7c41 483 } else /* The option is for other outputs */
e4b36699 484 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 485
486 return limit;
487}
488
409ee761 489static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
79e53945 490{
409ee761 491 struct drm_device *dev = crtc->base.dev;
79e53945
JB		 492 const intel_limit_t *limit;
493
bad720ff 494 if (HAS_PCH_SPLIT(dev))
1b894b59 495 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 496 else if (IS_G4X(dev)) {
044c7c41 497 limit = intel_g4x_limit(crtc);
f2b115e6 498 } else if (IS_PINEVIEW(dev)) {
d0737e1d 499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 500 limit = &intel_limits_pineview_lvds;
2177832f 501 else
f2b115e6 502 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
a0c4da24 505 } else if (IS_VALLEYVIEW(dev)) {
dc730512 506 limit = &intel_limits_vlv;
a6c45cf0 507 } else if (!IS_GEN2(dev)) {
d0737e1d 508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
79e53945 512 } else {
d0737e1d 513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 514 limit = &intel_limits_i8xx_lvds;
d0737e1d 515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 516 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 517 else
518 limit = &intel_limits_i8xx_dac;
79e53945
JB		 519 }
520 return limit;
521}
522
f2b115e6
AJ		 523/* m1 is reserved as 0 in Pineview, n is a ring counter */
524static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 525{
2177832f
SL		 526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
fb03ac01
VS		 530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 532}
533
7429e9d4
DV		 534static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535{
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537}
538
ac58c3f0 539static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 540{
7429e9d4 541 clock->m = i9xx_dpll_compute_m(clock);
79e53945 542 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
fb03ac01
VS		 545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 547}
548
ef9348c8
CML		 549static void chv_clock(int refclk, intel_clock_t *clock)
550{
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558}
559
7c04d1d9 560#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 561/**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
1b894b59
CW		 566static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
79e53945 569{
f01b7962
VS		 570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
79e53945 572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 573 INTELPllInvalid("p1 out of range\n");
79e53945 574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 575 INTELPllInvalid("m2 out of range\n");
79e53945 576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 577 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
79e53945 590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 591 INTELPllInvalid("vco out of range\n");
79e53945
JB		 592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 596 INTELPllInvalid("dot out of range\n");
79e53945
JB		 597
598 return true;
599}
600
d4906093 601static bool
a919ff14 602i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
cec2f356
SP		 603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
79e53945 605{
a919ff14 606 struct drm_device *dev = crtc->base.dev;
79e53945 607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
d0737e1d 610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 611 /*
a210b028
DV		 612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
79e53945 615 */
1974cad0 616 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
0206e353 627 memset(best_clock, 0, sizeof(*best_clock));
79e53945 628
42158660
ZY		 629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 633 if (clock.m2 >= clock.m1)
42158660
ZY		 634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 639 int this_err;
640
ac58c3f0
DV		 641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660}
661
662static bool
a919ff14 663pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
79e53945 666{
a919ff14 667 struct drm_device *dev = crtc->base.dev;
79e53945 668 intel_clock_t clock;
79e53945
JB		 669 int err = target;
670
d0737e1d 671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 672 /*
a210b028
DV		 673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
79e53945 676 */
1974cad0 677 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
0206e353 688 memset(best_clock, 0, sizeof(*best_clock));
79e53945 689
42158660
ZY		 690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 698 int this_err;
699
ac58c3f0 700 pineview_clock(refclk, &clock);
1b894b59
CW		 701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
79e53945 703 continue;
cec2f356
SP		 704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
79e53945
JB		 707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719}
720
d4906093 721static bool
a919ff14 722g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
d4906093 725{
a919ff14 726 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 727 intel_clock_t clock;
728 int max_n;
729 bool found;
6ba770dc
AJ		 730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 732 found = false;
733
d0737e1d 734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 735 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
f77f13e2 748 /* based on hardware requirement, prefer smaller n to precision */
d4906093 749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 750 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
ac58c3f0 759 i9xx_clock(refclk, &clock);
1b894b59
CW		 760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
d4906093 762 continue;
1b894b59
CW		 763
764 this_err = abs(clock.dot - target);
d4906093
ML		 765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
2c07245f
ZW		 775 return found;
776}
777
a0c4da24 778static bool
a919ff14 779vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
a0c4da24 782{
a919ff14 783 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 784 intel_clock_t clock;
69e4f900 785 unsigned int bestppm = 1000000;
27e639bf
VS		 786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 788 bool found = false;
a0c4da24 789
6b4bf1c4
VS		 790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 793
794 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 799 clock.p = clock.p1 * clock.p2;
a0c4da24 800 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 802 unsigned int ppm, diff;
803
6b4bf1c4
VS		 804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
43b0ac53 808
f01b7962
VS		 809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
43b0ac53
VS		 811 continue;
812
6b4bf1c4
VS		 813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 817 bestppm = 0;
6b4bf1c4 818 *best_clock = clock;
49e497ef 819 found = true;
43b0ac53 820 }
6b4bf1c4 821
c686122c 822 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 823 bestppm = ppm;
6b4bf1c4 824 *best_clock = clock;
49e497ef 825 found = true;
a0c4da24
JB		 826 }
827 }
828 }
829 }
830 }
a0c4da24 831
49e497ef 832 return found;
a0c4da24 833}
a4fc5ed6 834
ef9348c8 835static bool
a919ff14 836chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ef9348c8
CML		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839{
a919ff14 840 struct drm_device *dev = crtc->base.dev;
ef9348c8
CML		 841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885}
886
20ddf665
VS		 887bool intel_crtc_active(struct drm_crtc *crtc)
888{
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
241bfc38 894 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 895 * as Haswell has gained clock readout/fastboot support.
896 *
66e514c1 897 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665
VS		 898 * properly reconstruct framebuffers.
899 */
f4510a27 900 return intel_crtc->active && crtc->primary->fb &&
6e3c9717 901 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 902}
903
a5c961d1
PZ		 904enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906{
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
6e3c9717 910 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 911}
912
fbf49ea2
VS		 913static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930}
931
ab7ad7f6
KP		 932/*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 934 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
ab7ad7f6
KP		 940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
58e10eb9 946 *
9d0498a2 947 */
575f7ab7 948static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 949{
575f7ab7 950 struct drm_device *dev = crtc->base.dev;
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 953 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 954
955 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 956 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 957
958 /* Wait for the Pipe State to go off */
58e10eb9
CW		 959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
284637d9 961 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 962 } else {
ab7ad7f6 963 /* Wait for the display line to settle */
fbf49ea2 964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 965 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 966 }
79e53945
JB		 967}
968
b0ea7d37
DL		 969/*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978{
979 u32 bit;
980
c36346e3 981 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 982 switch (port->port) {
c36346e3
DL		 983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
eba905b2 996 switch (port->port) {
c36346e3
DL		 997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
b0ea7d37
DL		 1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012}
1013
b24e7179
JB		 1014static const char *state_string(bool enabled)
1015{
1016 return enabled ? "on" : "off";
1017}
1018
1019/* Only for pre-ILK configs */
55607e8a
DV		 1020void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
b24e7179
JB		 1022{
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1030 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033}
b24e7179 1034
23538ef1
JN		 1035/* XXX: the dsi pll is shared between MIPI DSI ports */
1036static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037{
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1046 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049}
1050#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
55607e8a 1053struct intel_shared_dpll *
e2b78267
DV		 1054intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055{
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
6e3c9717 1058 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1059 return NULL;
1060
6e3c9717 1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1062}
1063
040484af 1064/* For ILK+ */
55607e8a
DV		 1065void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
040484af 1068{
040484af 1069 bool cur_state;
5358901f 1070 struct intel_dpll_hw_state hw_state;
040484af 1071
92b27b08 1072 if (WARN (!pll,
46edb027 1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1074 return;
ee7b9f93 1075
5358901f 1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1077 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
040484af 1080}
040484af
JB		 1081
1082static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084{
1085 int reg;
1086 u32 val;
1087 bool cur_state;
ad80a810
PZ		 1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
040484af 1090
affa9354
PZ		 1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
ad80a810 1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1094 val = I915_READ(reg);
ad80a810 1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
e2c719b7 1101 I915_STATE_WARN(cur_state != state,
040484af
JB		 1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104}
1105#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110{
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
d63fa0dc
PZ		 1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1118 I915_STATE_WARN(cur_state != state,
040484af
JB		 1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121}
1122#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
3d13ef2e 1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1133 return;
1134
bf507ef7 1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1136 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1137 return;
1138
040484af
JB		 1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
e2c719b7 1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1142}
1143
55607e8a
DV		 1144void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
040484af
JB		 1146{
1147 int reg;
1148 u32 val;
55607e8a 1149 bool cur_state;
040484af
JB		 1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
55607e8a 1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1154 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
040484af
JB		 1157}
1158
b680c37a
DV		 1159void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
ea0760cf 1161{
bedd4dba
JN		 1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
ea0760cf
JB		 1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
0de3b485 1166 bool locked = true;
ea0760cf 1167
bedd4dba
JN		 1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
ea0760cf 1174 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
ea0760cf
JB		 1185 } else {
1186 pp_reg = PP_CONTROL;
bedd4dba
JN		 1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
ea0760cf
JB		 1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1194 locked = false;
1195
e2c719b7 1196 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1197 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1198 pipe_name(pipe));
ea0760cf
JB		 1199}
1200
93ce0ba6
JN		 1201static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203{
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
d9d82081 1207 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1209 else
5efb3e28 1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1211
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215}
1216#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
b840d907
JB		 1219void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
b24e7179
JB		 1221{
1222 int reg;
1223 u32 val;
63d7bbe9 1224 bool cur_state;
702e7a56
PZ		 1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
b24e7179 1227
b6b5d049
VS		 1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1231 state = true;
1232
f458ebbc 1233 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
e2c719b7 1242 I915_STATE_WARN(cur_state != state,
63d7bbe9 1243 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1244 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1245}
1246
931872fc
CW		 1247static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
b24e7179
JB		 1249{
1250 int reg;
1251 u32 val;
931872fc 1252 bool cur_state;
b24e7179
JB		 1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
931872fc 1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1257 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1260}
1261
931872fc
CW		 1262#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
b24e7179
JB		 1265static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
653e1026 1268 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
653e1026
VS		 1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
e2c719b7 1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
19ec1358 1280 return;
28c05794 1281 }
19ec1358 1282
b24e7179 1283 /* Need to check both planes against the pipe */
055e393f 1284 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1292 }
1293}
1294
19332d7a
JB		 1295static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297{
20674eef 1298 struct drm_device *dev = dev_priv->dev;
1fe47785 1299 int reg, sprite;
19332d7a
JB		 1300 u32 val;
1301
7feb8b88 1302 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1303 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1304 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1310 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1311 reg = SPCNTR(pipe, sprite);
20674eef 1312 val = I915_READ(reg);
e2c719b7 1313 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1315 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
19332d7a 1319 val = I915_READ(reg);
e2c719b7 1320 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
19332d7a 1325 val = I915_READ(reg);
e2c719b7 1326 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1328 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1329 }
1330}
1331
08c71e5e
VS		 1332static void assert_vblank_disabled(struct drm_crtc *crtc)
1333{
e2c719b7 1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1335 drm_crtc_vblank_put(crtc);
1336}
1337
89eff4be 1338static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1339{
1340 u32 val;
1341 bool enabled;
1342
e2c719b7 1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1344
92f2584a
JB		 1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1349}
1350
ab9412ba
DV		 1351static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
92f2584a
JB		 1353{
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
ab9412ba 1358 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1361 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
92f2584a
JB		 1364}
1365
4e634389
KP		 1366static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1368{
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
44f37d1f
CML		 1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
f0575e92
KP		 1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385}
1386
1519b995
KP		 1387static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389{
dc0fa718 1390 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1395 return false;
44f37d1f
CML		 1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1519b995 1399 } else {
dc0fa718 1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1401 return false;
1402 }
1403 return true;
1404}
1405
1406static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408{
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420}
1421
1422static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424{
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435}
1436
291906f1 1437static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1438 enum pipe pipe, int reg, u32 port_sel)
291906f1 1439{
47a05eca 1440 u32 val = I915_READ(reg);
e2c719b7 1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1443 reg, pipe_name(pipe));
de9a35ab 1444
e2c719b7 1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1446 && (val & DP_PIPEB_SELECT),
de9a35ab 1447 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1448}
1449
1450static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452{
47a05eca 1453 u32 val = I915_READ(reg);
e2c719b7 1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1456 reg, pipe_name(pipe));
de9a35ab 1457
e2c719b7 1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1459 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1460 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1461}
1462
1463static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465{
1466 int reg;
1467 u32 val;
291906f1 1468
f0575e92
KP		 1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
e2c719b7 1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1477 pipe_name(pipe));
291906f1
JB		 1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
e2c719b7 1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1483 pipe_name(pipe));
291906f1 1484
e2debe91
PZ		 1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1488}
1489
40e9cf64
JB		 1490static void intel_init_dpio(struct drm_device *dev)
1491{
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
a09caddd
CML		 1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
5382f5f3
JB		 1508}
1509
d288f65f 1510static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1511 const struct intel_crtc_state *pipe_config)
87442f73 1512{
426115cf
DV		 1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
d288f65f 1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1517
426115cf 1518 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1524 if (IS_MOBILE(dev_priv->dev))
426115cf 1525 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1526
426115cf
DV		 1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
d288f65f 1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1535 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1536
1537 /* We do this three times for luck */
426115cf 1538 I915_WRITE(reg, dpll);
87442f73
DV		 1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
426115cf 1541 I915_WRITE(reg, dpll);
87442f73
DV		 1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
426115cf 1544 I915_WRITE(reg, dpll);
87442f73
DV		 1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547}
1548
d288f65f 1549static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1550 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1551{
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
d288f65f 1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1576
1577 /* Check PLL is locked */
a11b0703 1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
a11b0703 1581 /* not sure when this should be written */
d288f65f 1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1583 POSTING_READ(DPLL_MD(pipe));
1584
9d556c99
CML		 1585 mutex_unlock(&dev_priv->dpio_lock);
1586}
1587
1c4e0274
VS		 1588static int intel_num_dvo_pipes(struct drm_device *dev)
1589{
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
409ee761 1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1596
1597 return count;
1598}
1599
66e3d5c0 1600static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1601{
66e3d5c0
DV		 1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
6e3c9717 1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1606
66e3d5c0 1607 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1608
63d7bbe9 1609 /* No really, not for ILK+ */
3d13ef2e 1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1611
1612 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1615
1c4e0274
VS		 1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
66e3d5c0
DV		 1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1635 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
63d7bbe9
JB		 1644
1645 /* We do this three times for luck */
66e3d5c0 1646 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
66e3d5c0 1649 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
66e3d5c0 1652 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655}
1656
1657/**
50b44a44 1658 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1c4e0274 1666static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1667{
1c4e0274
VS		 1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
409ee761 1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
b6b5d049
VS		 1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
50b44a44
DV		 1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1692}
1693
f6071166
JB		 1694static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695{
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
e5cbfbfb
ID		 1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
f6071166 1705 if (pipe == PIPE_B)
e5cbfbfb 1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1709
1710}
1711
1712static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713{
d752048d 1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1715 u32 val;
1716
a11b0703
VS		 1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1719
a11b0703 1720 /* Set PLL en = 0 */
d17ec4ce 1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
d752048d
VS		 1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
61407f6d
VS		 1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
d752048d 1745 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1746}
1747
e4607fcf
CML		 1748void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
89b667f8
JB		 1750{
1751 u32 port_mask;
00fc31b7 1752 int dpll_reg;
89b667f8 1753
e4607fcf
CML		 1754 switch (dport->port) {
1755 case PORT_B:
89b667f8 1756 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1757 dpll_reg = DPLL(0);
e4607fcf
CML		 1758 break;
1759 case PORT_C:
89b667f8 1760 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1766 break;
1767 default:
1768 BUG();
1769 }
89b667f8 1770
00fc31b7 1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1773 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1774}
1775
b14b1055
DV		 1776static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777{
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
be19f0ff
CW		 1782 if (WARN_ON(pll == NULL))
1783 return;
1784
3e369b76 1785 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793}
1794
92f2584a 1795/**
85b3894f 1796 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
85b3894f 1803static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1804{
3d13ef2e
DL		 1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1808
87a875bb 1809 if (WARN_ON(pll == NULL))
48da64a8
CW		 1810 return;
1811
3e369b76 1812 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1813 return;
ee7b9f93 1814
74dd6928 1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1816 pll->name, pll->active, pll->on,
e2b78267 1817 crtc->base.base.id);
92f2584a 1818
cdbd2316
DV		 1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
e9d6944e 1821 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1822 return;
1823 }
f4a091c7 1824 WARN_ON(pll->on);
ee7b9f93 1825
bd2bb1b9
PZ		 1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
46edb027 1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1829 pll->enable(dev_priv, pll);
ee7b9f93 1830 pll->on = true;
92f2584a
JB		 1831}
1832
f6daaec2 1833static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1834{
3d13ef2e
DL		 1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1838
92f2584a 1839 /* PCH only available on ILK+ */
3d13ef2e 1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1841 if (WARN_ON(pll == NULL))
ee7b9f93 1842 return;
92f2584a 1843
3e369b76 1844 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1845 return;
7a419866 1846
46edb027
DV		 1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
e2b78267 1849 crtc->base.base.id);
7a419866 1850
48da64a8 1851 if (WARN_ON(pll->active == 0)) {
e9d6944e 1852 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1853 return;
1854 }
1855
e9d6944e 1856 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1857 WARN_ON(!pll->on);
cdbd2316 1858 if (--pll->active)
7a419866 1859 return;
ee7b9f93 1860
46edb027 1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1862 pll->disable(dev_priv, pll);
ee7b9f93 1863 pll->on = false;
bd2bb1b9
PZ		 1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1866}
1867
b8a4f404
PZ		 1868static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
040484af 1870{
23670b32 1871 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1874 uint32_t reg, val, pipeconf_val;
040484af
JB		 1875
1876 /* PCH only available on ILK+ */
55522f37 1877 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1878
1879 /* Make sure PCH DPLL is enabled */
e72f9fbf 1880 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1881 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
23670b32
DV		 1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
59c859d6 1894 }
23670b32 1895
ab9412ba 1896 reg = PCH_TRANSCONF(pipe);
040484af 1897 val = I915_READ(reg);
5f7f726d 1898 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
dfd07d72
DV		 1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1907 }
5f7f726d
PZ		 1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1911 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
040484af
JB		 1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1922}
1923
8fb033d7 1924static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1925 enum transcoder cpu_transcoder)
040484af 1926{
8fb033d7 1927 u32 val, pipeconf_val;
8fb033d7
PZ		 1928
1929 /* PCH only available on ILK+ */
55522f37 1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1931
8fb033d7 1932 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1935
223a6fdf
PZ		 1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
25f3ef11 1941 val = TRANS_ENABLE;
937bb610 1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1943
9a76b1c6
PZ		 1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
a35f2679 1946 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
ab9412ba
DV		 1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1952 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1953}
1954
b8a4f404
PZ		 1955static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
040484af 1957{
23670b32
DV		 1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
040484af
JB		 1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
291906f1
JB		 1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
ab9412ba 1968 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
040484af
JB		 1983}
1984
ab4d966c 1985static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1986{
8fb033d7
PZ		 1987 u32 val;
1988
ab9412ba 1989 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1990 val &= ~TRANS_ENABLE;
ab9412ba 1991 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1992 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1994 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1999 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2000}
2001
b24e7179 2002/**
309cfea8 2003 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2004 * @crtc: crtc responsible for the pipe
b24e7179 2005 *
0372264a 2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2008 */
e1fdc473 2009static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2010{
0372264a
PZ		 2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
1a240d4d 2016 enum pipe pch_transcoder;
b24e7179
JB		 2017 int reg;
2018 u32 val;
2019
58c6eaa2 2020 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2021 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2022 assert_sprites_disabled(dev_priv, pipe);
2023
681e5811 2024 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
b24e7179
JB		 2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
040484af 2039 else {
6e3c9717 2040 if (crtc->config->has_pch_encoder) {
040484af 2041 /* if driving the PCH, we need FDI enabled */
cc391bbb 2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
040484af
JB		 2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
b24e7179 2048
702e7a56 2049 reg = PIPECONF(cpu_transcoder);
b24e7179 2050 val = I915_READ(reg);
7ad25d48 2051 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2054 return;
7ad25d48 2055 }
00d70b15
CW		 2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2058 POSTING_READ(reg);
b24e7179
JB		 2059}
2060
2061/**
309cfea8 2062 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2063 * @crtc: crtc whose pipes is to be disabled
b24e7179 2064 *
575f7ab7
VS		 2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
b24e7179
JB		 2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
575f7ab7 2071static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2072{
575f7ab7 2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2075 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2084 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2085 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2086
702e7a56 2087 reg = PIPECONF(cpu_transcoder);
b24e7179 2088 val = I915_READ(reg);
00d70b15
CW		 2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
67adc644
VS		 2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
6e3c9717 2096 if (crtc->config->double_wide)
67adc644
VS		 2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2107}
2108
d74362c9
KP		 2109/*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
1dba99f4
VS		 2113void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
d74362c9 2115{
3d13ef2e
DL		 2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
d74362c9
KP		 2121}
2122
b24e7179 2123/**
262ca2b0 2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
b24e7179 2127 *
fdd508a6 2128 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2129 */
fdd508a6
VS		 2130static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
b24e7179 2132{
fdd508a6
VS		 2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2139
98ec7739
VS		 2140 if (intel_crtc->primary_enabled)
2141 return;
0037f71c 2142
4c445e0e 2143 intel_crtc->primary_enabled = true;
939c2fe8 2144
fdd508a6
VS		 2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
33c3b0d1
VS		 2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2155}
2156
b24e7179 2157/**
262ca2b0 2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
b24e7179 2161 *
fdd508a6 2162 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2163 */
fdd508a6
VS		 2164static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
b24e7179 2166{
fdd508a6
VS		 2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
32b7eeec
MR		 2171 if (WARN_ON(!intel_crtc->active))
2172 return;
b24e7179 2173
98ec7739
VS		 2174 if (!intel_crtc->primary_enabled)
2175 return;
0037f71c 2176
4c445e0e 2177 intel_crtc->primary_enabled = false;
939c2fe8 2178
fdd508a6
VS		 2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
b24e7179
JB		 2181}
2182
693db184
CW		 2183static bool need_vtd_wa(struct drm_device *dev)
2184{
2185#ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188#endif
2189 return false;
2190}
2191
ec2c981e 2192int
091df6cb
DV		 2193intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
a57ce0b2
JB		 2196{
2197 int tile_height;
b5d0e9bf 2198 uint32_t bits_per_pixel;
a57ce0b2 2199
b5d0e9bf
DL		 2200 switch (fb_format_modifier) {
2201 case DRM_FORMAT_MOD_NONE:
2202 tile_height = 1;
2203 break;
2204 case I915_FORMAT_MOD_X_TILED:
2205 tile_height = IS_GEN2(dev) ? 16 : 8;
2206 break;
2207 case I915_FORMAT_MOD_Y_TILED:
2208 tile_height = 32;
2209 break;
2210 case I915_FORMAT_MOD_Yf_TILED:
2211 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212 switch (bits_per_pixel) {
2213 default:
2214 case 8:
2215 tile_height = 64;
2216 break;
2217 case 16:
2218 case 32:
2219 tile_height = 32;
2220 break;
2221 case 64:
2222 tile_height = 16;
2223 break;
2224 case 128:
2225 WARN_ONCE(1,
2226 "128-bit pixels are not supported for display!");
2227 tile_height = 16;
2228 break;
2229 }
2230 break;
2231 default:
2232 MISSING_CASE(fb_format_modifier);
2233 tile_height = 1;
2234 break;
2235 }
091df6cb 2236
a57ce0b2
JB		 2237 return ALIGN(height, tile_height);
2238}
2239
127bd2ac 2240int
850c4cdc
TU		 2241intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242 struct drm_framebuffer *fb,
a4872ba6 2243 struct intel_engine_cs *pipelined)
6b95a207 2244{
850c4cdc 2245 struct drm_device *dev = fb->dev;
ce453d81 2246 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207
KH		 2248 u32 alignment;
2249 int ret;
2250
ebcdd39e
MR		 2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
7b911adc
TU		 2253 switch (fb->modifier[0]) {
2254 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2255 if (INTEL_INFO(dev)->gen >= 9)
2256 alignment = 256 * 1024;
2257 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2258 alignment = 128 * 1024;
a6c45cf0 2259 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2260 alignment = 4 * 1024;
2261 else
2262 alignment = 64 * 1024;
6b95a207 2263 break;
7b911adc 2264 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2265 if (INTEL_INFO(dev)->gen >= 9)
2266 alignment = 256 * 1024;
2267 else {
2268 /* pin() will align the object as required by fence */
2269 alignment = 0;
2270 }
6b95a207 2271 break;
7b911adc 2272 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2273 case I915_FORMAT_MOD_Yf_TILED:
2274 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2276 return -EINVAL;
2277 alignment = 1 * 1024 * 1024;
2278 break;
6b95a207 2279 default:
7b911adc
TU		 2280 MISSING_CASE(fb->modifier[0]);
2281 return -EINVAL;
6b95a207
KH		 2282 }
2283
693db184
CW		 2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2287 * the VT-d warning.
2288 */
2289 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290 alignment = 256 * 1024;
2291
d6dd6843
PZ		 2292 /*
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2298 */
2299 intel_runtime_pm_get(dev_priv);
2300
ce453d81 2301 dev_priv->mm.interruptible = false;
2da3b9b9 2302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2303 if (ret)
ce453d81 2304 goto err_interruptible;
6b95a207
KH		 2305
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2310 */
06d98131 2311 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2312 if (ret)
2313 goto err_unpin;
1690e1eb 2314
9a5a53b3 2315 i915_gem_object_pin_fence(obj);
6b95a207 2316
ce453d81 2317 dev_priv->mm.interruptible = true;
d6dd6843 2318 intel_runtime_pm_put(dev_priv);
6b95a207 2319 return 0;
48b956c5
CW		 2320
2321err_unpin:
cc98b413 2322 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 2323err_interruptible:
2324 dev_priv->mm.interruptible = true;
d6dd6843 2325 intel_runtime_pm_put(dev_priv);
48b956c5 2326 return ret;
6b95a207
KH		 2327}
2328
f63bdb5f 2329static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1690e1eb 2330{
ebcdd39e
MR		 2331 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2332
1690e1eb 2333 i915_gem_object_unpin_fence(obj);
cc98b413 2334 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 2335}
2336
c2c75131
DV		 2337/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
bc752862
CW		 2339unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340 unsigned int tiling_mode,
2341 unsigned int cpp,
2342 unsigned int pitch)
c2c75131 2343{
bc752862
CW		 2344 if (tiling_mode != I915_TILING_NONE) {
2345 unsigned int tile_rows, tiles;
c2c75131 2346
bc752862
CW		 2347 tile_rows = *y / 8;
2348 *y %= 8;
c2c75131 2349
bc752862
CW		 2350 tiles = *x / (512/cpp);
2351 *x %= 512/cpp;
2352
2353 return tile_rows * pitch * 8 + tiles * 4096;
2354 } else {
2355 unsigned int offset;
2356
2357 offset = *y * pitch + *x * cpp;
2358 *y = 0;
2359 *x = (offset & 4095) / cpp;
2360 return offset & -4096;
2361 }
c2c75131
DV		 2362}
2363
b35d63fa 2364static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2365{
2366 switch (format) {
2367 case DISPPLANE_8BPP:
2368 return DRM_FORMAT_C8;
2369 case DISPPLANE_BGRX555:
2370 return DRM_FORMAT_XRGB1555;
2371 case DISPPLANE_BGRX565:
2372 return DRM_FORMAT_RGB565;
2373 default:
2374 case DISPPLANE_BGRX888:
2375 return DRM_FORMAT_XRGB8888;
2376 case DISPPLANE_RGBX888:
2377 return DRM_FORMAT_XBGR8888;
2378 case DISPPLANE_BGRX101010:
2379 return DRM_FORMAT_XRGB2101010;
2380 case DISPPLANE_RGBX101010:
2381 return DRM_FORMAT_XBGR2101010;
2382 }
2383}
2384
bc8d7dff
DL		 2385static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2386{
2387 switch (format) {
2388 case PLANE_CTL_FORMAT_RGB_565:
2389 return DRM_FORMAT_RGB565;
2390 default:
2391 case PLANE_CTL_FORMAT_XRGB_8888:
2392 if (rgb_order) {
2393 if (alpha)
2394 return DRM_FORMAT_ABGR8888;
2395 else
2396 return DRM_FORMAT_XBGR8888;
2397 } else {
2398 if (alpha)
2399 return DRM_FORMAT_ARGB8888;
2400 else
2401 return DRM_FORMAT_XRGB8888;
2402 }
2403 case PLANE_CTL_FORMAT_XRGB_2101010:
2404 if (rgb_order)
2405 return DRM_FORMAT_XBGR2101010;
2406 else
2407 return DRM_FORMAT_XRGB2101010;
2408 }
2409}
2410
5724dbd1
DL		 2411static bool
2412intel_alloc_plane_obj(struct intel_crtc *crtc,
2413 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2414{
2415 struct drm_device *dev = crtc->base.dev;
2416 struct drm_i915_gem_object *obj = NULL;
2417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2418 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2419 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2420 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2421 PAGE_SIZE);
2422
2423 size_aligned -= base_aligned;
46f297fb 2424
ff2652ea
CW		 2425 if (plane_config->size == 0)
2426 return false;
2427
f37b5c2b
DV		 2428 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2429 base_aligned,
2430 base_aligned,
2431 size_aligned);
46f297fb 2432 if (!obj)
484b41dd 2433 return false;
46f297fb 2434
49af449b
DL		 2435 obj->tiling_mode = plane_config->tiling;
2436 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2437 obj->stride = fb->pitches[0];
46f297fb 2438
6bf129df
DL		 2439 mode_cmd.pixel_format = fb->pixel_format;
2440 mode_cmd.width = fb->width;
2441 mode_cmd.height = fb->height;
2442 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2443 mode_cmd.modifier[0] = fb->modifier[0];
2444 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2445
2446 mutex_lock(&dev->struct_mutex);
2447
6bf129df 2448 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2449 &mode_cmd, obj)) {
46f297fb
JB		 2450 DRM_DEBUG_KMS("intel fb init failed\n");
2451 goto out_unref_obj;
2452 }
2453
a071fa00 2454 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
46f297fb 2455 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2456
2457 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2458 return true;
46f297fb
JB		 2459
2460out_unref_obj:
2461 drm_gem_object_unreference(&obj->base);
2462 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2463 return false;
2464}
2465
afd65eb4
MR		 2466/* Update plane->state->fb to match plane->fb after driver-internal updates */
2467static void
2468update_state_fb(struct drm_plane *plane)
2469{
2470 if (plane->fb == plane->state->fb)
2471 return;
2472
2473 if (plane->state->fb)
2474 drm_framebuffer_unreference(plane->state->fb);
2475 plane->state->fb = plane->fb;
2476 if (plane->state->fb)
2477 drm_framebuffer_reference(plane->state->fb);
2478}
2479
5724dbd1
DL		 2480static void
2481intel_find_plane_obj(struct intel_crtc *intel_crtc,
2482 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2483{
2484 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2485 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2486 struct drm_crtc *c;
2487 struct intel_crtc *i;
2ff8fde1 2488 struct drm_i915_gem_object *obj;
484b41dd 2489
2d14030b 2490 if (!plane_config->fb)
484b41dd
JB		 2491 return;
2492
f55548b5 2493 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
fb9981aa
DL		 2494 struct drm_plane *primary = intel_crtc->base.primary;
2495
2496 primary->fb = &plane_config->fb->base;
2497 primary->state->crtc = &intel_crtc->base;
2498 update_state_fb(primary);
2499
484b41dd 2500 return;
f55548b5 2501 }
484b41dd 2502
2d14030b 2503 kfree(plane_config->fb);
484b41dd
JB		 2504
2505 /*
2506 * Failed to alloc the obj, check to see if we should share
2507 * an fb with another CRTC instead
2508 */
70e1e0ec 2509 for_each_crtc(dev, c) {
484b41dd
JB		 2510 i = to_intel_crtc(c);
2511
2512 if (c == &intel_crtc->base)
2513 continue;
2514
2ff8fde1
MR		 2515 if (!i->active)
2516 continue;
2517
2518 obj = intel_fb_obj(c->primary->fb);
2519 if (obj == NULL)
484b41dd
JB		 2520 continue;
2521
2ff8fde1 2522 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
fb9981aa
DL		 2523 struct drm_plane *primary = intel_crtc->base.primary;
2524
d9ceb816
JB		 2525 if (obj->tiling_mode != I915_TILING_NONE)
2526 dev_priv->preserve_bios_swizzle = true;
2527
66e514c1 2528 drm_framebuffer_reference(c->primary->fb);
fb9981aa
DL		 2529 primary->fb = c->primary->fb;
2530 primary->state->crtc = &intel_crtc->base;
5ba76c41 2531 update_state_fb(intel_crtc->base.primary);
2ff8fde1 2532 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
484b41dd
JB		 2533 break;
2534 }
2535 }
afd65eb4 2536
46f297fb
JB		 2537}
2538
29b9bde6
DV		 2539static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2540 struct drm_framebuffer *fb,
2541 int x, int y)
81255565
JB		 2542{
2543 struct drm_device *dev = crtc->dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2546 struct drm_i915_gem_object *obj;
81255565 2547 int plane = intel_crtc->plane;
e506a0c6 2548 unsigned long linear_offset;
81255565 2549 u32 dspcntr;
f45651ba 2550 u32 reg = DSPCNTR(plane);
48404c1e 2551 int pixel_size;
f45651ba 2552
fdd508a6
VS		 2553 if (!intel_crtc->primary_enabled) {
2554 I915_WRITE(reg, 0);
2555 if (INTEL_INFO(dev)->gen >= 4)
2556 I915_WRITE(DSPSURF(plane), 0);
2557 else
2558 I915_WRITE(DSPADDR(plane), 0);
2559 POSTING_READ(reg);
2560 return;
2561 }
2562
c9ba6fad
VS		 2563 obj = intel_fb_obj(fb);
2564 if (WARN_ON(obj == NULL))
2565 return;
2566
2567 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2568
f45651ba
VS		 2569 dspcntr = DISPPLANE_GAMMA_ENABLE;
2570
fdd508a6 2571 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2572
2573 if (INTEL_INFO(dev)->gen < 4) {
2574 if (intel_crtc->pipe == PIPE_B)
2575 dspcntr |= DISPPLANE_SEL_PIPE_B;
2576
2577 /* pipesrc and dspsize control the size that is scaled from,
2578 * which should always be the user's requested size.
2579 */
2580 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2581 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2582 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2583 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2584 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2585 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2586 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2587 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2588 I915_WRITE(PRIMPOS(plane), 0);
2589 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2590 }
81255565 2591
57779d06
VS		 2592 switch (fb->pixel_format) {
2593 case DRM_FORMAT_C8:
81255565
JB		 2594 dspcntr |= DISPPLANE_8BPP;
2595 break;
57779d06
VS		 2596 case DRM_FORMAT_XRGB1555:
2597 case DRM_FORMAT_ARGB1555:
2598 dspcntr |= DISPPLANE_BGRX555;
81255565 2599 break;
57779d06
VS		 2600 case DRM_FORMAT_RGB565:
2601 dspcntr |= DISPPLANE_BGRX565;
2602 break;
2603 case DRM_FORMAT_XRGB8888:
2604 case DRM_FORMAT_ARGB8888:
2605 dspcntr |= DISPPLANE_BGRX888;
2606 break;
2607 case DRM_FORMAT_XBGR8888:
2608 case DRM_FORMAT_ABGR8888:
2609 dspcntr |= DISPPLANE_RGBX888;
2610 break;
2611 case DRM_FORMAT_XRGB2101010:
2612 case DRM_FORMAT_ARGB2101010:
2613 dspcntr |= DISPPLANE_BGRX101010;
2614 break;
2615 case DRM_FORMAT_XBGR2101010:
2616 case DRM_FORMAT_ABGR2101010:
2617 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2618 break;
2619 default:
baba133a 2620 BUG();
81255565 2621 }
57779d06 2622
f45651ba
VS		 2623 if (INTEL_INFO(dev)->gen >= 4 &&
2624 obj->tiling_mode != I915_TILING_NONE)
2625 dspcntr |= DISPPLANE_TILED;
81255565 2626
de1aa629
VS		 2627 if (IS_G4X(dev))
2628 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2629
b9897127 2630 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2631
c2c75131
DV		 2632 if (INTEL_INFO(dev)->gen >= 4) {
2633 intel_crtc->dspaddr_offset =
bc752862 2634 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2635 pixel_size,
bc752862 2636 fb->pitches[0]);
c2c75131
DV		 2637 linear_offset -= intel_crtc->dspaddr_offset;
2638 } else {
e506a0c6 2639 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2640 }
e506a0c6 2641
8e7d688b 2642 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2643 dspcntr |= DISPPLANE_ROTATE_180;
2644
6e3c9717
ACO		 2645 x += (intel_crtc->config->pipe_src_w - 1);
2646 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2647
2648 /* Finding the last pixel of the last line of the display
2649 data and adding to linear_offset*/
2650 linear_offset +=
6e3c9717
ACO		 2651 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2652 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2653 }
2654
2655 I915_WRITE(reg, dspcntr);
2656
f343c5f6
BW		 2657 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2659 fb->pitches[0]);
01f2c773 2660 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2661 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2662 I915_WRITE(DSPSURF(plane),
2663 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2664 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2665 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2666 } else
f343c5f6 2667 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2668 POSTING_READ(reg);
17638cd6
JB		 2669}
2670
29b9bde6
DV		 2671static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2672 struct drm_framebuffer *fb,
2673 int x, int y)
17638cd6
JB		 2674{
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2678 struct drm_i915_gem_object *obj;
17638cd6 2679 int plane = intel_crtc->plane;
e506a0c6 2680 unsigned long linear_offset;
17638cd6 2681 u32 dspcntr;
f45651ba 2682 u32 reg = DSPCNTR(plane);
48404c1e 2683 int pixel_size;
f45651ba 2684
fdd508a6
VS		 2685 if (!intel_crtc->primary_enabled) {
2686 I915_WRITE(reg, 0);
2687 I915_WRITE(DSPSURF(plane), 0);
2688 POSTING_READ(reg);
2689 return;
2690 }
2691
c9ba6fad
VS		 2692 obj = intel_fb_obj(fb);
2693 if (WARN_ON(obj == NULL))
2694 return;
2695
2696 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2697
f45651ba
VS		 2698 dspcntr = DISPPLANE_GAMMA_ENABLE;
2699
fdd508a6 2700 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2701
2702 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2703 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2704
57779d06
VS		 2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
17638cd6
JB		 2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
57779d06
VS		 2709 case DRM_FORMAT_RGB565:
2710 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2711 break;
57779d06
VS		 2712 case DRM_FORMAT_XRGB8888:
2713 case DRM_FORMAT_ARGB8888:
2714 dspcntr |= DISPPLANE_BGRX888;
2715 break;
2716 case DRM_FORMAT_XBGR8888:
2717 case DRM_FORMAT_ABGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
2721 case DRM_FORMAT_ARGB2101010:
2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
2725 case DRM_FORMAT_ABGR2101010:
2726 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2727 break;
2728 default:
baba133a 2729 BUG();
17638cd6
JB		 2730 }
2731
2732 if (obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
17638cd6 2734
f45651ba 2735 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2739 intel_crtc->dspaddr_offset =
bc752862 2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2741 pixel_size,
bc752862 2742 fb->pitches[0]);
c2c75131 2743 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2744 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2745 dspcntr |= DISPPLANE_ROTATE_180;
2746
2747 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2750
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2753 linear_offset +=
6e3c9717
ACO		 2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2756 }
2757 }
2758
2759 I915_WRITE(reg, dspcntr);
17638cd6 2760
f343c5f6
BW		 2761 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2763 fb->pitches[0]);
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2768 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2769 } else {
2770 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2771 I915_WRITE(DSPLINOFF(plane), linear_offset);
2772 }
17638cd6 2773 POSTING_READ(reg);
17638cd6
JB		 2774}
2775
b321803d
DL		 2776u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2777 uint32_t pixel_format)
2778{
2779 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2780
2781 /*
2782 * The stride is either expressed as a multiple of 64 bytes
2783 * chunks for linear buffers or in number of tiles for tiled
2784 * buffers.
2785 */
2786 switch (fb_modifier) {
2787 case DRM_FORMAT_MOD_NONE:
2788 return 64;
2789 case I915_FORMAT_MOD_X_TILED:
2790 if (INTEL_INFO(dev)->gen == 2)
2791 return 128;
2792 return 512;
2793 case I915_FORMAT_MOD_Y_TILED:
2794 /* No need to check for old gens and Y tiling since this is
2795 * about the display engine and those will be blocked before
2796 * we get here.
2797 */
2798 return 128;
2799 case I915_FORMAT_MOD_Yf_TILED:
2800 if (bits_per_pixel == 8)
2801 return 64;
2802 else
2803 return 128;
2804 default:
2805 MISSING_CASE(fb_modifier);
2806 return 64;
2807 }
2808}
2809
70d21f0e
DL		 2810static void skylake_update_primary_plane(struct drm_crtc *crtc,
2811 struct drm_framebuffer *fb,
2812 int x, int y)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2817 struct drm_i915_gem_object *obj;
2818 int pipe = intel_crtc->pipe;
b321803d 2819 u32 plane_ctl, stride_div;
70d21f0e
DL		 2820
2821 if (!intel_crtc->primary_enabled) {
2822 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2823 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2824 POSTING_READ(PLANE_CTL(pipe, 0));
2825 return;
2826 }
2827
2828 plane_ctl = PLANE_CTL_ENABLE |
2829 PLANE_CTL_PIPE_GAMMA_ENABLE |
2830 PLANE_CTL_PIPE_CSC_ENABLE;
2831
2832 switch (fb->pixel_format) {
2833 case DRM_FORMAT_RGB565:
2834 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2835 break;
2836 case DRM_FORMAT_XRGB8888:
2837 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2838 break;
f75fb42a
JN		 2839 case DRM_FORMAT_ARGB8888:
2840 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2841 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2842 break;
70d21f0e
DL		 2843 case DRM_FORMAT_XBGR8888:
2844 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2845 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2846 break;
f75fb42a
JN		 2847 case DRM_FORMAT_ABGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2851 break;
70d21f0e
DL		 2852 case DRM_FORMAT_XRGB2101010:
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2854 break;
2855 case DRM_FORMAT_XBGR2101010:
2856 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858 break;
2859 default:
2860 BUG();
2861 }
2862
30af77c4
DV		 2863 switch (fb->modifier[0]) {
2864 case DRM_FORMAT_MOD_NONE:
70d21f0e 2865 break;
30af77c4 2866 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2867 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2868 break;
2869 case I915_FORMAT_MOD_Y_TILED:
2870 plane_ctl |= PLANE_CTL_TILED_Y;
2871 break;
2872 case I915_FORMAT_MOD_Yf_TILED:
2873 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 2874 break;
2875 default:
b321803d 2876 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 2877 }
2878
2879 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 2881 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 2882
b321803d
DL		 2883 obj = intel_fb_obj(fb);
2884 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2885 fb->pixel_format);
2886
70d21f0e
DL		 2887 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2888
2889 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890 i915_gem_obj_ggtt_offset(obj),
2891 x, y, fb->width, fb->height,
2892 fb->pitches[0]);
2893
2894 I915_WRITE(PLANE_POS(pipe, 0), 0);
2895 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2896 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 2897 (intel_crtc->config->pipe_src_h - 1) << 16 |
2898 (intel_crtc->config->pipe_src_w - 1));
b321803d 2899 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
70d21f0e
DL		 2900 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2901
2902 POSTING_READ(PLANE_SURF(pipe, 0));
2903}
2904
17638cd6
JB		 2905/* Assume fb object is pinned & idle & fenced and just update base pointers */
2906static int
2907intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2908 int x, int y, enum mode_set_atomic state)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2912
6b8e6ed0
CW		 2913 if (dev_priv->display.disable_fbc)
2914 dev_priv->display.disable_fbc(dev);
81255565 2915
29b9bde6
DV		 2916 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2917
2918 return 0;
81255565
JB		 2919}
2920
7514747d 2921static void intel_complete_page_flips(struct drm_device *dev)
96a02917 2922{
96a02917
VS		 2923 struct drm_crtc *crtc;
2924
70e1e0ec 2925 for_each_crtc(dev, crtc) {
96a02917
VS		 2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2927 enum plane plane = intel_crtc->plane;
2928
2929 intel_prepare_page_flip(dev, plane);
2930 intel_finish_page_flip_plane(dev, plane);
2931 }
7514747d
VS		 2932}
2933
2934static void intel_update_primary_planes(struct drm_device *dev)
2935{
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct drm_crtc *crtc;
96a02917 2938
70e1e0ec 2939 for_each_crtc(dev, crtc) {
96a02917
VS		 2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941
51fd371b 2942 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 2943 /*
2944 * FIXME: Once we have proper support for primary planes (and
2945 * disabling them without disabling the entire crtc) allow again
66e514c1 2946 * a NULL crtc->primary->fb.
947fdaad 2947 */
f4510a27 2948 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 2949 dev_priv->display.update_primary_plane(crtc,
66e514c1 2950 crtc->primary->fb,
262ca2b0
MR		 2951 crtc->x,
2952 crtc->y);
51fd371b 2953 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 2954 }
2955}
2956
7514747d
VS		 2957void intel_prepare_reset(struct drm_device *dev)
2958{
f98ce92f
VS		 2959 struct drm_i915_private *dev_priv = to_i915(dev);
2960 struct intel_crtc *crtc;
2961
7514747d
VS		 2962 /* no reset support for gen2 */
2963 if (IS_GEN2(dev))
2964 return;
2965
2966 /* reset doesn't touch the display */
2967 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2968 return;
2969
2970 drm_modeset_lock_all(dev);
f98ce92f
VS		 2971
2972 /*
2973 * Disabling the crtcs gracefully seems nicer. Also the
2974 * g33 docs say we should at least disable all the planes.
2975 */
2976 for_each_intel_crtc(dev, crtc) {
2977 if (crtc->active)
2978 dev_priv->display.crtc_disable(&crtc->base);
2979 }
7514747d
VS		 2980}
2981
2982void intel_finish_reset(struct drm_device *dev)
2983{
2984 struct drm_i915_private *dev_priv = to_i915(dev);
2985
2986 /*
2987 * Flips in the rings will be nuked by the reset,
2988 * so complete all pending flips so that user space
2989 * will get its events and not get stuck.
2990 */
2991 intel_complete_page_flips(dev);
2992
2993 /* no reset support for gen2 */
2994 if (IS_GEN2(dev))
2995 return;
2996
2997 /* reset doesn't touch the display */
2998 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2999 /*
3000 * Flips in the rings have been nuked by the reset,
3001 * so update the base address of all primary
3002 * planes to the the last fb to make sure we're
3003 * showing the correct fb after a reset.
3004 */
3005 intel_update_primary_planes(dev);
3006 return;
3007 }
3008
3009 /*
3010 * The display has been reset as well,
3011 * so need a full re-initialization.
3012 */
3013 intel_runtime_pm_disable_interrupts(dev_priv);
3014 intel_runtime_pm_enable_interrupts(dev_priv);
3015
3016 intel_modeset_init_hw(dev);
3017
3018 spin_lock_irq(&dev_priv->irq_lock);
3019 if (dev_priv->display.hpd_irq_setup)
3020 dev_priv->display.hpd_irq_setup(dev);
3021 spin_unlock_irq(&dev_priv->irq_lock);
3022
3023 intel_modeset_setup_hw_state(dev, true);
3024
3025 intel_hpd_init(dev_priv);
3026
3027 drm_modeset_unlock_all(dev);
3028}
3029
14667a4b
CW		 3030static int
3031intel_finish_fb(struct drm_framebuffer *old_fb)
3032{
2ff8fde1 3033 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3034 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3035 bool was_interruptible = dev_priv->mm.interruptible;
3036 int ret;
3037
14667a4b
CW		 3038 /* Big Hammer, we also need to ensure that any pending
3039 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040 * current scanout is retired before unpinning the old
3041 * framebuffer.
3042 *
3043 * This should only fail upon a hung GPU, in which case we
3044 * can safely continue.
3045 */
3046 dev_priv->mm.interruptible = false;
3047 ret = i915_gem_object_finish_gpu(obj);
3048 dev_priv->mm.interruptible = was_interruptible;
3049
3050 return ret;
3051}
3052
7d5e3799
CW		 3053static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3054{
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3058 bool pending;
3059
3060 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3061 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3062 return false;
3063
5e2d7afc 3064 spin_lock_irq(&dev->event_lock);
7d5e3799 3065 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3066 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3067
3068 return pending;
3069}
3070
e30e8f75
GP		 3071static void intel_update_pipe_size(struct intel_crtc *crtc)
3072{
3073 struct drm_device *dev = crtc->base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 const struct drm_display_mode *adjusted_mode;
3076
3077 if (!i915.fastboot)
3078 return;
3079
3080 /*
3081 * Update pipe size and adjust fitter if needed: the reason for this is
3082 * that in compute_mode_changes we check the native mode (not the pfit
3083 * mode) to see if we can flip rather than do a full mode set. In the
3084 * fastboot case, we'll flip, but if we don't update the pipesrc and
3085 * pfit state, we'll end up with a big fb scanned out into the wrong
3086 * sized surface.
3087 *
3088 * To fix this properly, we need to hoist the checks up into
3089 * compute_mode_changes (or above), check the actual pfit state and
3090 * whether the platform allows pfit disable with pipe active, and only
3091 * then update the pipesrc and pfit state, even on the flip path.
3092 */
3093
6e3c9717 3094 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3095
3096 I915_WRITE(PIPESRC(crtc->pipe),
3097 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3098 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3099 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3100 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3101 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3102 I915_WRITE(PF_CTL(crtc->pipe), 0);
3103 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3104 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3105 }
6e3c9717
ACO		 3106 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3107 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3108}
3109
5e84e1a4
ZW		 3110static void intel_fdi_normal_train(struct drm_crtc *crtc)
3111{
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115 int pipe = intel_crtc->pipe;
3116 u32 reg, temp;
3117
3118 /* enable normal train */
3119 reg = FDI_TX_CTL(pipe);
3120 temp = I915_READ(reg);
61e499bf 3121 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3122 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3123 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3124 } else {
3125 temp &= ~FDI_LINK_TRAIN_NONE;
3126 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3127 }
5e84e1a4
ZW		 3128 I915_WRITE(reg, temp);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 if (HAS_PCH_CPT(dev)) {
3133 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3135 } else {
3136 temp &= ~FDI_LINK_TRAIN_NONE;
3137 temp |= FDI_LINK_TRAIN_NONE;
3138 }
3139 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3140
3141 /* wait one idle pattern time */
3142 POSTING_READ(reg);
3143 udelay(1000);
357555c0
JB		 3144
3145 /* IVB wants error correction enabled */
3146 if (IS_IVYBRIDGE(dev))
3147 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3148 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3149}
3150
1fbc0d78 3151static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
1e833f40 3152{
83d65738 3153 return crtc->base.state->enable && crtc->active &&
6e3c9717 3154 crtc->config->has_pch_encoder;
1e833f40
DV		 3155}
3156
01a415fd
DV		 3157static void ivb_modeset_global_resources(struct drm_device *dev)
3158{
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *pipe_B_crtc =
3161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3162 struct intel_crtc *pipe_C_crtc =
3163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3164 uint32_t temp;
3165
1e833f40
DV		 3166 /*
3167 * When everything is off disable fdi C so that we could enable fdi B
3168 * with all lanes. Note that we don't care about enabled pipes without
3169 * an enabled pch encoder.
3170 */
3171 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3172 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 3173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3175
3176 temp = I915_READ(SOUTH_CHICKEN1);
3177 temp &= ~FDI_BC_BIFURCATION_SELECT;
3178 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179 I915_WRITE(SOUTH_CHICKEN1, temp);
3180 }
3181}
3182
8db9d77b
ZW		 3183/* The FDI link training functions for ILK/Ibexpeak. */
3184static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3185{
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 int pipe = intel_crtc->pipe;
5eddb70b 3190 u32 reg, temp, tries;
8db9d77b 3191
1c8562f6 3192 /* FDI needs bits from pipe first */
0fc932b8 3193 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3194
e1a44743
AJ		 3195 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3196 for train result */
5eddb70b
CW		 3197 reg = FDI_RX_IMR(pipe);
3198 temp = I915_READ(reg);
e1a44743
AJ		 3199 temp &= ~FDI_RX_SYMBOL_LOCK;
3200 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3201 I915_WRITE(reg, temp);
3202 I915_READ(reg);
e1a44743
AJ		 3203 udelay(150);
3204
8db9d77b 3205 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3206 reg = FDI_TX_CTL(pipe);
3207 temp = I915_READ(reg);
627eb5a3 3208 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3209 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3212 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3213
5eddb70b
CW		 3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
8db9d77b
ZW		 3216 temp &= ~FDI_LINK_TRAIN_NONE;
3217 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3218 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3219
3220 POSTING_READ(reg);
8db9d77b
ZW		 3221 udelay(150);
3222
5b2adf89 3223 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3224 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3226 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3227
5eddb70b 3228 reg = FDI_RX_IIR(pipe);
e1a44743 3229 for (tries = 0; tries < 5; tries++) {
5eddb70b 3230 temp = I915_READ(reg);
8db9d77b
ZW		 3231 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3232
3233 if ((temp & FDI_RX_BIT_LOCK)) {
3234 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3235 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3236 break;
3237 }
8db9d77b 3238 }
e1a44743 3239 if (tries == 5)
5eddb70b 3240 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3241
3242 /* Train 2 */
5eddb70b
CW		 3243 reg = FDI_TX_CTL(pipe);
3244 temp = I915_READ(reg);
8db9d77b
ZW		 3245 temp &= ~FDI_LINK_TRAIN_NONE;
3246 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3247 I915_WRITE(reg, temp);
8db9d77b 3248
5eddb70b
CW		 3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
8db9d77b
ZW		 3251 temp &= ~FDI_LINK_TRAIN_NONE;
3252 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3253 I915_WRITE(reg, temp);
8db9d77b 3254
5eddb70b
CW		 3255 POSTING_READ(reg);
3256 udelay(150);
8db9d77b 3257
5eddb70b 3258 reg = FDI_RX_IIR(pipe);
e1a44743 3259 for (tries = 0; tries < 5; tries++) {
5eddb70b 3260 temp = I915_READ(reg);
8db9d77b
ZW		 3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3262
3263 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3264 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3265 DRM_DEBUG_KMS("FDI train 2 done.\n");
3266 break;
3267 }
8db9d77b 3268 }
e1a44743 3269 if (tries == 5)
5eddb70b 3270 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3271
3272 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3273
8db9d77b
ZW		 3274}
3275
0206e353 3276static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3277 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3278 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3279 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3280 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3281};
3282
3283/* The FDI link training functions for SNB/Cougarpoint. */
3284static void gen6_fdi_link_train(struct drm_crtc *crtc)
3285{
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 int pipe = intel_crtc->pipe;
fa37d39e 3290 u32 reg, temp, i, retry;
8db9d77b 3291
e1a44743
AJ		 3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293 for train result */
5eddb70b
CW		 3294 reg = FDI_RX_IMR(pipe);
3295 temp = I915_READ(reg);
e1a44743
AJ		 3296 temp &= ~FDI_RX_SYMBOL_LOCK;
3297 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3298 I915_WRITE(reg, temp);
3299
3300 POSTING_READ(reg);
e1a44743
AJ		 3301 udelay(150);
3302
8db9d77b 3303 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
627eb5a3 3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 /* SNB-B */
3312 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3314
d74cf324
DV		 3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
5eddb70b
CW		 3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
8db9d77b
ZW		 3320 if (HAS_PCH_CPT(dev)) {
3321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3323 } else {
3324 temp &= ~FDI_LINK_TRAIN_NONE;
3325 temp |= FDI_LINK_TRAIN_PATTERN_1;
3326 }
5eddb70b
CW		 3327 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3328
3329 POSTING_READ(reg);
8db9d77b
ZW		 3330 udelay(150);
3331
0206e353 3332 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
8db9d77b
ZW		 3335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3336 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3337 I915_WRITE(reg, temp);
3338
3339 POSTING_READ(reg);
8db9d77b
ZW		 3340 udelay(500);
3341
fa37d39e
SP		 3342 for (retry = 0; retry < 5; retry++) {
3343 reg = FDI_RX_IIR(pipe);
3344 temp = I915_READ(reg);
3345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3346 if (temp & FDI_RX_BIT_LOCK) {
3347 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3348 DRM_DEBUG_KMS("FDI train 1 done.\n");
3349 break;
3350 }
3351 udelay(50);
8db9d77b 3352 }
fa37d39e
SP		 3353 if (retry < 5)
3354 break;
8db9d77b
ZW		 3355 }
3356 if (i == 4)
5eddb70b 3357 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3358
3359 /* Train 2 */
5eddb70b
CW		 3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
8db9d77b
ZW		 3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_PATTERN_2;
3364 if (IS_GEN6(dev)) {
3365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366 /* SNB-B */
3367 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3368 }
5eddb70b 3369 I915_WRITE(reg, temp);
8db9d77b 3370
5eddb70b
CW		 3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
8db9d77b
ZW		 3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 }
5eddb70b
CW		 3380 I915_WRITE(reg, temp);
3381
3382 POSTING_READ(reg);
8db9d77b
ZW		 3383 udelay(150);
3384
0206e353 3385 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
8db9d77b
ZW		 3388 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3389 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3390 I915_WRITE(reg, temp);
3391
3392 POSTING_READ(reg);
8db9d77b
ZW		 3393 udelay(500);
3394
fa37d39e
SP		 3395 for (retry = 0; retry < 5; retry++) {
3396 reg = FDI_RX_IIR(pipe);
3397 temp = I915_READ(reg);
3398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399 if (temp & FDI_RX_SYMBOL_LOCK) {
3400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3402 break;
3403 }
3404 udelay(50);
8db9d77b 3405 }
fa37d39e
SP		 3406 if (retry < 5)
3407 break;
8db9d77b
ZW		 3408 }
3409 if (i == 4)
5eddb70b 3410 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3411
3412 DRM_DEBUG_KMS("FDI train done.\n");
3413}
3414
357555c0
JB		 3415/* Manual link training for Ivy Bridge A0 parts */
3416static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
139ccd3f 3422 u32 reg, temp, i, j;
357555c0
JB		 3423
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425 for train result */
3426 reg = FDI_RX_IMR(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_RX_SYMBOL_LOCK;
3429 temp &= ~FDI_RX_BIT_LOCK;
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
01a415fd
DV		 3435 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436 I915_READ(FDI_RX_IIR(pipe)));
3437
139ccd3f
JB		 3438 /* Try each vswing and preemphasis setting twice before moving on */
3439 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3440 /* disable first in case we need to retry */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3444 temp &= ~FDI_TX_ENABLE;
3445 I915_WRITE(reg, temp);
357555c0 3446
139ccd3f
JB		 3447 reg = FDI_RX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_AUTO;
3450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451 temp &= ~FDI_RX_ENABLE;
3452 I915_WRITE(reg, temp);
357555c0 3453
139ccd3f 3454 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
139ccd3f 3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3459 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3461 temp |= snb_b_fdi_train_param[j/2];
3462 temp |= FDI_COMPOSITE_SYNC;
3463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3464
139ccd3f
JB		 3465 I915_WRITE(FDI_RX_MISC(pipe),
3466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3467
139ccd3f 3468 reg = FDI_RX_CTL(pipe);
357555c0 3469 temp = I915_READ(reg);
139ccd3f
JB		 3470 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3471 temp |= FDI_COMPOSITE_SYNC;
3472 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3473
139ccd3f
JB		 3474 POSTING_READ(reg);
3475 udelay(1); /* should be 0.5us */
357555c0 3476
139ccd3f
JB		 3477 for (i = 0; i < 4; i++) {
3478 reg = FDI_RX_IIR(pipe);
3479 temp = I915_READ(reg);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3481
139ccd3f
JB		 3482 if (temp & FDI_RX_BIT_LOCK ||
3483 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3486 i);
3487 break;
3488 }
3489 udelay(1); /* should be 0.5us */
3490 }
3491 if (i == 4) {
3492 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3493 continue;
3494 }
357555c0 3495
139ccd3f 3496 /* Train 2 */
357555c0
JB		 3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
139ccd3f
JB		 3499 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3501 I915_WRITE(reg, temp);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
139ccd3f 3510 udelay(2); /* should be 1.5us */
357555c0 3511
139ccd3f
JB		 3512 for (i = 0; i < 4; i++) {
3513 reg = FDI_RX_IIR(pipe);
3514 temp = I915_READ(reg);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3516
139ccd3f
JB		 3517 if (temp & FDI_RX_SYMBOL_LOCK ||
3518 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3521 i);
3522 goto train_done;
3523 }
3524 udelay(2); /* should be 1.5us */
357555c0 3525 }
139ccd3f
JB		 3526 if (i == 4)
3527 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3528 }
357555c0 3529
139ccd3f 3530train_done:
357555c0
JB		 3531 DRM_DEBUG_KMS("FDI train done.\n");
3532}
3533
88cefb6c 3534static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3535{
88cefb6c 3536 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3537 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3538 int pipe = intel_crtc->pipe;
5eddb70b 3539 u32 reg, temp;
79e53945 3540
c64e311e 3541
c98e9dcf 3542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3543 reg = FDI_RX_CTL(pipe);
3544 temp = I915_READ(reg);
627eb5a3 3545 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3547 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3548 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3549
3550 POSTING_READ(reg);
c98e9dcf
JB		 3551 udelay(200);
3552
3553 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3554 temp = I915_READ(reg);
3555 I915_WRITE(reg, temp | FDI_PCDCLK);
3556
3557 POSTING_READ(reg);
c98e9dcf
JB		 3558 udelay(200);
3559
20749730
PZ		 3560 /* Enable CPU FDI TX PLL, always on for Ironlake */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3564 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3565
20749730
PZ		 3566 POSTING_READ(reg);
3567 udelay(100);
6be4a607 3568 }
0e23b99d
JB		 3569}
3570
88cefb6c
DV		 3571static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3572{
3573 struct drm_device *dev = intel_crtc->base.dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 int pipe = intel_crtc->pipe;
3576 u32 reg, temp;
3577
3578 /* Switch from PCDclk to Rawclk */
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3582
3583 /* Disable CPU FDI TX PLL */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3587
3588 POSTING_READ(reg);
3589 udelay(100);
3590
3591 reg = FDI_RX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3594
3595 /* Wait for the clocks to turn off. */
3596 POSTING_READ(reg);
3597 udelay(100);
3598}
3599
0fc932b8
JB		 3600static void ironlake_fdi_disable(struct drm_crtc *crtc)
3601{
3602 struct drm_device *dev = crtc->dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605 int pipe = intel_crtc->pipe;
3606 u32 reg, temp;
3607
3608 /* disable CPU FDI tx and PCH FDI rx */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3612 POSTING_READ(reg);
3613
3614 reg = FDI_RX_CTL(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~(0x7 << 16);
dfd07d72 3617 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3618 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3619
3620 POSTING_READ(reg);
3621 udelay(100);
3622
3623 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3624 if (HAS_PCH_IBX(dev))
6f06ce18 3625 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3626
3627 /* still set train pattern 1 */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_LINK_TRAIN_NONE;
3631 temp |= FDI_LINK_TRAIN_PATTERN_1;
3632 I915_WRITE(reg, temp);
3633
3634 reg = FDI_RX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 if (HAS_PCH_CPT(dev)) {
3637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 } else {
3640 temp &= ~FDI_LINK_TRAIN_NONE;
3641 temp |= FDI_LINK_TRAIN_PATTERN_1;
3642 }
3643 /* BPC in FDI rx is consistent with that in PIPECONF */
3644 temp &= ~(0x07 << 16);
dfd07d72 3645 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3646 I915_WRITE(reg, temp);
3647
3648 POSTING_READ(reg);
3649 udelay(100);
3650}
3651
5dce5b93
CW		 3652bool intel_has_pending_fb_unpin(struct drm_device *dev)
3653{
3654 struct intel_crtc *crtc;
3655
3656 /* Note that we don't need to be called with mode_config.lock here
3657 * as our list of CRTC objects is static for the lifetime of the
3658 * device and so cannot disappear as we iterate. Similarly, we can
3659 * happily treat the predicates as racy, atomic checks as userspace
3660 * cannot claim and pin a new fb without at least acquring the
3661 * struct_mutex and so serialising with us.
3662 */
d3fcc808 3663 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3664 if (atomic_read(&crtc->unpin_work_count) == 0)
3665 continue;
3666
3667 if (crtc->unpin_work)
3668 intel_wait_for_vblank(dev, crtc->pipe);
3669
3670 return true;
3671 }
3672
3673 return false;
3674}
3675
d6bbafa1
CW		 3676static void page_flip_completed(struct intel_crtc *intel_crtc)
3677{
3678 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3679 struct intel_unpin_work *work = intel_crtc->unpin_work;
3680
3681 /* ensure that the unpin work is consistent wrt ->pending. */
3682 smp_rmb();
3683 intel_crtc->unpin_work = NULL;
3684
3685 if (work->event)
3686 drm_send_vblank_event(intel_crtc->base.dev,
3687 intel_crtc->pipe,
3688 work->event);
3689
3690 drm_crtc_vblank_put(&intel_crtc->base);
3691
3692 wake_up_all(&dev_priv->pending_flip_queue);
3693 queue_work(dev_priv->wq, &work->work);
3694
3695 trace_i915_flip_complete(intel_crtc->plane,
3696 work->pending_flip_obj);
3697}
3698
46a55d30 3699void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3700{
0f91128d 3701 struct drm_device *dev = crtc->dev;
5bb61643 3702 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3703
2c10d571 3704 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3705 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3706 !intel_crtc_has_pending_flip(crtc),
3707 60*HZ) == 0)) {
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3709
5e2d7afc 3710 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3711 if (intel_crtc->unpin_work) {
3712 WARN_ONCE(1, "Removing stuck page flip\n");
3713 page_flip_completed(intel_crtc);
3714 }
5e2d7afc 3715 spin_unlock_irq(&dev->event_lock);
9c787942 3716 }
5bb61643 3717
975d568a
CW		 3718 if (crtc->primary->fb) {
3719 mutex_lock(&dev->struct_mutex);
3720 intel_finish_fb(crtc->primary->fb);
3721 mutex_unlock(&dev->struct_mutex);
3722 }
e6c3a2a6
CW		 3723}
3724
e615efe4
ED		 3725/* Program iCLKIP clock to the desired frequency */
3726static void lpt_program_iclkip(struct drm_crtc *crtc)
3727{
3728 struct drm_device *dev = crtc->dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3730 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3731 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3732 u32 temp;
3733
09153000
DV		 3734 mutex_lock(&dev_priv->dpio_lock);
3735
e615efe4
ED		 3736 /* It is necessary to ungate the pixclk gate prior to programming
3737 * the divisors, and gate it back when it is done.
3738 */
3739 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3740
3741 /* Disable SSCCTL */
3742 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3743 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3744 SBI_SSCCTL_DISABLE,
3745 SBI_ICLK);
e615efe4
ED		 3746
3747 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3748 if (clock == 20000) {
e615efe4
ED		 3749 auxdiv = 1;
3750 divsel = 0x41;
3751 phaseinc = 0x20;
3752 } else {
3753 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3754 * but the adjusted_mode->crtc_clock in in KHz. To get the
3755 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3756 * convert the virtual clock precision to KHz here for higher
3757 * precision.
3758 */
3759 u32 iclk_virtual_root_freq = 172800 * 1000;
3760 u32 iclk_pi_range = 64;
3761 u32 desired_divisor, msb_divisor_value, pi_value;
3762
12d7ceed 3763 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3764 msb_divisor_value = desired_divisor / iclk_pi_range;
3765 pi_value = desired_divisor % iclk_pi_range;
3766
3767 auxdiv = 0;
3768 divsel = msb_divisor_value - 2;
3769 phaseinc = pi_value;
3770 }
3771
3772 /* This should not happen with any sane values */
3773 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3774 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3775 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3776 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3777
3778 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3779 clock,
e615efe4
ED		 3780 auxdiv,
3781 divsel,
3782 phasedir,
3783 phaseinc);
3784
3785 /* Program SSCDIVINTPHASE6 */
988d6ee8 3786 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3787 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3788 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3789 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3790 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3791 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3792 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3793 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3794
3795 /* Program SSCAUXDIV */
988d6ee8 3796 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3797 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3799 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3800
3801 /* Enable modulator and associated divider */
988d6ee8 3802 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3803 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3804 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3805
3806 /* Wait for initialization time */
3807 udelay(24);
3808
3809 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3810
3811 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3812}
3813
275f01b2
DV		 3814static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3815 enum pipe pch_transcoder)
3816{
3817 struct drm_device *dev = crtc->base.dev;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3819 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3820
3821 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3822 I915_READ(HTOTAL(cpu_transcoder)));
3823 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3824 I915_READ(HBLANK(cpu_transcoder)));
3825 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3826 I915_READ(HSYNC(cpu_transcoder)));
3827
3828 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3829 I915_READ(VTOTAL(cpu_transcoder)));
3830 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3831 I915_READ(VBLANK(cpu_transcoder)));
3832 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3833 I915_READ(VSYNC(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3835 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3836}
3837
1fbc0d78
DV		 3838static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t temp;
3842
3843 temp = I915_READ(SOUTH_CHICKEN1);
3844 if (temp & FDI_BC_BIFURCATION_SELECT)
3845 return;
3846
3847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3849
3850 temp |= FDI_BC_BIFURCATION_SELECT;
3851 DRM_DEBUG_KMS("enabling fdi C rx\n");
3852 I915_WRITE(SOUTH_CHICKEN1, temp);
3853 POSTING_READ(SOUTH_CHICKEN1);
3854}
3855
3856static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3857{
3858 struct drm_device *dev = intel_crtc->base.dev;
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 switch (intel_crtc->pipe) {
3862 case PIPE_A:
3863 break;
3864 case PIPE_B:
6e3c9717 3865 if (intel_crtc->config->fdi_lanes > 2)
1fbc0d78
DV		 3866 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3867 else
3868 cpt_enable_fdi_bc_bifurcation(dev);
3869
3870 break;
3871 case PIPE_C:
3872 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874 break;
3875 default:
3876 BUG();
3877 }
3878}
3879
f67a559d
JB		 3880/*
3881 * Enable PCH resources required for PCH ports:
3882 * - PCH PLLs
3883 * - FDI training & RX/TX
3884 * - update transcoder timings
3885 * - DP transcoding bits
3886 * - transcoder
3887 */
3888static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3889{
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 int pipe = intel_crtc->pipe;
ee7b9f93 3894 u32 reg, temp;
2c07245f 3895
ab9412ba 3896 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3897
1fbc0d78
DV		 3898 if (IS_IVYBRIDGE(dev))
3899 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3900
cd986abb
DV		 3901 /* Write the TU size bits before fdi link training, so that error
3902 * detection works. */
3903 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3904 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3905
c98e9dcf 3906 /* For PCH output, training FDI link */
674cf967 3907 dev_priv->display.fdi_link_train(crtc);
2c07245f 3908
3ad8a208
DV		 3909 /* We need to program the right clock selection before writing the pixel
3910 * mutliplier into the DPLL. */
303b81e0 3911 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3912 u32 sel;
4b645f14 3913
c98e9dcf 3914 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3915 temp |= TRANS_DPLL_ENABLE(pipe);
3916 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 3917 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3918 temp |= sel;
3919 else
3920 temp &= ~sel;
c98e9dcf 3921 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3922 }
5eddb70b 3923
3ad8a208
DV		 3924 /* XXX: pch pll's can be enabled any time before we enable the PCH
3925 * transcoder, and we actually should do this to not upset any PCH
3926 * transcoder that already use the clock when we share it.
3927 *
3928 * Note that enable_shared_dpll tries to do the right thing, but
3929 * get_shared_dpll unconditionally resets the pll - we need that to have
3930 * the right LVDS enable sequence. */
85b3894f 3931 intel_enable_shared_dpll(intel_crtc);
3ad8a208 3932
d9b6cb56
JB		 3933 /* set transcoder timing, panel must allow it */
3934 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3935 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3936
303b81e0 3937 intel_fdi_normal_train(crtc);
5e84e1a4 3938
c98e9dcf 3939 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 3940 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 3941 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3942 reg = TRANS_DP_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3945 TRANS_DP_SYNC_MASK |
3946 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3947 temp |= (TRANS_DP_OUTPUT_ENABLE |
3948 TRANS_DP_ENH_FRAMING);
9325c9f0 3949 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3950
3951 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3952 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3953 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3954 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3955
3956 switch (intel_trans_dp_port_sel(crtc)) {
3957 case PCH_DP_B:
5eddb70b 3958 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3959 break;
3960 case PCH_DP_C:
5eddb70b 3961 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3962 break;
3963 case PCH_DP_D:
5eddb70b 3964 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3965 break;
3966 default:
e95d41e1 3967 BUG();
32f9d658 3968 }
2c07245f 3969
5eddb70b 3970 I915_WRITE(reg, temp);
6be4a607 3971 }
b52eb4dc 3972
b8a4f404 3973 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3974}
3975
1507e5bd
PZ		 3976static void lpt_pch_enable(struct drm_crtc *crtc)
3977{
3978 struct drm_device *dev = crtc->dev;
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 3981 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 3982
ab9412ba 3983 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3984
8c52b5e8 3985 lpt_program_iclkip(crtc);
1507e5bd 3986
0540e488 3987 /* Set transcoder timing. */
275f01b2 3988 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3989
937bb610 3990 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3991}
3992
716c2e55 3993void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3994{
e2b78267 3995 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3996
3997 if (pll == NULL)
3998 return;
3999
3e369b76 4000 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4001 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4002 return;
4003 }
4004
3e369b76
ACO		 4005 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4006 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4007 WARN_ON(pll->on);
4008 WARN_ON(pll->active);
4009 }
4010
6e3c9717 4011 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4012}
4013
190f68c5
ACO		 4014struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4015 struct intel_crtc_state *crtc_state)
ee7b9f93 4016{
e2b78267 4017 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4018 struct intel_shared_dpll *pll;
e2b78267 4019 enum intel_dpll_id i;
ee7b9f93 4020
98b6bd99
DV		 4021 if (HAS_PCH_IBX(dev_priv->dev)) {
4022 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4023 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4024 pll = &dev_priv->shared_dplls[i];
98b6bd99 4025
46edb027
DV		 4026 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027 crtc->base.base.id, pll->name);
98b6bd99 4028
8bd31e67 4029 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4030
98b6bd99
DV		 4031 goto found;
4032 }
4033
e72f9fbf
DV		 4034 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4035 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4036
4037 /* Only want to check enabled timings first */
8bd31e67 4038 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4039 continue;
4040
190f68c5 4041 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4042 &pll->new_config->hw_state,
4043 sizeof(pll->new_config->hw_state)) == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4045 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4046 pll->new_config->crtc_mask,
4047 pll->active);
ee7b9f93
JB		 4048 goto found;
4049 }
4050 }
4051
4052 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4053 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4054 pll = &dev_priv->shared_dplls[i];
8bd31e67 4055 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4056 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4058 goto found;
4059 }
4060 }
4061
4062 return NULL;
4063
4064found:
8bd31e67 4065 if (pll->new_config->crtc_mask == 0)
190f68c5 4066 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4067
190f68c5 4068 crtc_state->shared_dpll = i;
46edb027
DV		 4069 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4070 pipe_name(crtc->pipe));
ee7b9f93 4071
8bd31e67 4072 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4073
ee7b9f93
JB		 4074 return pll;
4075}
4076
8bd31e67
ACO		 4077/**
4078 * intel_shared_dpll_start_config - start a new PLL staged config
4079 * @dev_priv: DRM device
4080 * @clear_pipes: mask of pipes that will have their PLLs freed
4081 *
4082 * Starts a new PLL staged config, copying the current config but
4083 * releasing the references of pipes specified in clear_pipes.
4084 */
4085static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4086 unsigned clear_pipes)
4087{
4088 struct intel_shared_dpll *pll;
4089 enum intel_dpll_id i;
4090
4091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4092 pll = &dev_priv->shared_dplls[i];
4093
4094 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4095 GFP_KERNEL);
4096 if (!pll->new_config)
4097 goto cleanup;
4098
4099 pll->new_config->crtc_mask &= ~clear_pipes;
4100 }
4101
4102 return 0;
4103
4104cleanup:
4105 while (--i >= 0) {
4106 pll = &dev_priv->shared_dplls[i];
f354d733 4107 kfree(pll->new_config);
8bd31e67
ACO		 4108 pll->new_config = NULL;
4109 }
4110
4111 return -ENOMEM;
4112}
4113
4114static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4115{
4116 struct intel_shared_dpll *pll;
4117 enum intel_dpll_id i;
4118
4119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4120 pll = &dev_priv->shared_dplls[i];
4121
4122 WARN_ON(pll->new_config == &pll->config);
4123
4124 pll->config = *pll->new_config;
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4127 }
4128}
4129
4130static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4131{
4132 struct intel_shared_dpll *pll;
4133 enum intel_dpll_id i;
4134
4135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4136 pll = &dev_priv->shared_dplls[i];
4137
4138 WARN_ON(pll->new_config == &pll->config);
4139
4140 kfree(pll->new_config);
4141 pll->new_config = NULL;
4142 }
4143}
4144
a1520318 4145static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4146{
4147 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4148 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4149 u32 temp;
4150
4151 temp = I915_READ(dslreg);
4152 udelay(500);
4153 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4154 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4155 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4156 }
4157}
4158
bd2e244f
JB		 4159static void skylake_pfit_enable(struct intel_crtc *crtc)
4160{
4161 struct drm_device *dev = crtc->base.dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 int pipe = crtc->pipe;
4164
6e3c9717 4165 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4166 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4167 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4168 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4169 }
4170}
4171
b074cec8
JB		 4172static void ironlake_pfit_enable(struct intel_crtc *crtc)
4173{
4174 struct drm_device *dev = crtc->base.dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int pipe = crtc->pipe;
4177
6e3c9717 4178 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4179 /* Force use of hard-coded filter coefficients
4180 * as some pre-programmed values are broken,
4181 * e.g. x201.
4182 */
4183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4185 PF_PIPE_SEL_IVB(pipe));
4186 else
4187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4188 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4190 }
4191}
4192
4a3b8769 4193static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4194{
4195 struct drm_device *dev = crtc->dev;
4196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4197 struct drm_plane *plane;
bb53d4ae
VS		 4198 struct intel_plane *intel_plane;
4199
af2b653b
MR		 4200 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4201 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4202 if (intel_plane->pipe == pipe)
4203 intel_plane_restore(&intel_plane->base);
af2b653b 4204 }
bb53d4ae
VS		 4205}
4206
4a3b8769 4207static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4208{
4209 struct drm_device *dev = crtc->dev;
4210 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4211 struct drm_plane *plane;
bb53d4ae
VS		 4212 struct intel_plane *intel_plane;
4213
af2b653b
MR		 4214 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4215 intel_plane = to_intel_plane(plane);
bb53d4ae 4216 if (intel_plane->pipe == pipe)
cf4c7c12 4217 plane->funcs->disable_plane(plane);
af2b653b 4218 }
bb53d4ae
VS		 4219}
4220
20bc8673 4221void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4222{
cea165c3
VS		 4223 struct drm_device *dev = crtc->base.dev;
4224 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4225
6e3c9717 4226 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4227 return;
4228
cea165c3
VS		 4229 /* We can only enable IPS after we enable a plane and wait for a vblank */
4230 intel_wait_for_vblank(dev, crtc->pipe);
4231
d77e4531 4232 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4233 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4234 mutex_lock(&dev_priv->rps.hw_lock);
4235 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4236 mutex_unlock(&dev_priv->rps.hw_lock);
4237 /* Quoting Art Runyan: "its not safe to expect any particular
4238 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4239 * mailbox." Moreover, the mailbox may return a bogus state,
4240 * so we need to just enable it and continue on.
2a114cc1
BW		 4241 */
4242 } else {
4243 I915_WRITE(IPS_CTL, IPS_ENABLE);
4244 /* The bit only becomes 1 in the next vblank, so this wait here
4245 * is essentially intel_wait_for_vblank. If we don't have this
4246 * and don't wait for vblanks until the end of crtc_enable, then
4247 * the HW state readout code will complain that the expected
4248 * IPS_CTL value is not the one we read. */
4249 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4250 DRM_ERROR("Timed out waiting for IPS enable\n");
4251 }
d77e4531
PZ		 4252}
4253
20bc8673 4254void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4255{
4256 struct drm_device *dev = crtc->base.dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258
6e3c9717 4259 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4260 return;
4261
4262 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4263 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4264 mutex_lock(&dev_priv->rps.hw_lock);
4265 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4266 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4267 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4268 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4269 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4270 } else {
2a114cc1 4271 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4272 POSTING_READ(IPS_CTL);
4273 }
d77e4531
PZ		 4274
4275 /* We need to wait for a vblank before we can disable the plane. */
4276 intel_wait_for_vblank(dev, crtc->pipe);
4277}
4278
4279/** Loads the palette/gamma unit for the CRTC with the prepared values */
4280static void intel_crtc_load_lut(struct drm_crtc *crtc)
4281{
4282 struct drm_device *dev = crtc->dev;
4283 struct drm_i915_private *dev_priv = dev->dev_private;
4284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4285 enum pipe pipe = intel_crtc->pipe;
4286 int palreg = PALETTE(pipe);
4287 int i;
4288 bool reenable_ips = false;
4289
4290 /* The clocks have to be on to load the palette. */
83d65738 4291 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4292 return;
4293
4294 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4295 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4296 assert_dsi_pll_enabled(dev_priv);
4297 else
4298 assert_pll_enabled(dev_priv, pipe);
4299 }
4300
4301 /* use legacy palette for Ironlake */
7a1db49a 4302 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4303 palreg = LGC_PALETTE(pipe);
4304
4305 /* Workaround : Do not read or write the pipe palette/gamma data while
4306 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4307 */
6e3c9717 4308 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4309 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4310 GAMMA_MODE_MODE_SPLIT)) {
4311 hsw_disable_ips(intel_crtc);
4312 reenable_ips = true;
4313 }
4314
4315 for (i = 0; i < 256; i++) {
4316 I915_WRITE(palreg + 4 * i,
4317 (intel_crtc->lut_r[i] << 16) |
4318 (intel_crtc->lut_g[i] << 8) |
4319 intel_crtc->lut_b[i]);
4320 }
4321
4322 if (reenable_ips)
4323 hsw_enable_ips(intel_crtc);
4324}
4325
d3eedb1a
VS		 4326static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4327{
4328 if (!enable && intel_crtc->overlay) {
4329 struct drm_device *dev = intel_crtc->base.dev;
4330 struct drm_i915_private *dev_priv = dev->dev_private;
4331
4332 mutex_lock(&dev->struct_mutex);
4333 dev_priv->mm.interruptible = false;
4334 (void) intel_overlay_switch_off(intel_crtc->overlay);
4335 dev_priv->mm.interruptible = true;
4336 mutex_unlock(&dev->struct_mutex);
4337 }
4338
4339 /* Let userspace switch the overlay on again. In most cases userspace
4340 * has to recompute where to put it anyway.
4341 */
4342}
4343
d3eedb1a 4344static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4345{
4346 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 int pipe = intel_crtc->pipe;
a5c4d7bc 4349
fdd508a6 4350 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4351 intel_enable_sprite_planes(crtc);
a5c4d7bc 4352 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4353 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4354
4355 hsw_enable_ips(intel_crtc);
4356
4357 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4358 intel_fbc_update(dev);
a5c4d7bc 4359 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4360
4361 /*
4362 * FIXME: Once we grow proper nuclear flip support out of this we need
4363 * to compute the mask of flip planes precisely. For the time being
4364 * consider this a flip from a NULL plane.
4365 */
4366 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4367}
4368
d3eedb1a 4369static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4370{
4371 struct drm_device *dev = crtc->dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4375
4376 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4377
e35fef21 4378 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4379 intel_fbc_disable(dev);
a5c4d7bc
VS		 4380
4381 hsw_disable_ips(intel_crtc);
4382
d3eedb1a 4383 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4384 intel_crtc_update_cursor(crtc, false);
4a3b8769 4385 intel_disable_sprite_planes(crtc);
fdd508a6 4386 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4387
f99d7069
DV		 4388 /*
4389 * FIXME: Once we grow proper nuclear flip support out of this we need
4390 * to compute the mask of flip planes precisely. For the time being
4391 * consider this a flip to a NULL plane.
4392 */
4393 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4394}
4395
f67a559d
JB		 4396static void ironlake_crtc_enable(struct drm_crtc *crtc)
4397{
4398 struct drm_device *dev = crtc->dev;
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4401 struct intel_encoder *encoder;
f67a559d 4402 int pipe = intel_crtc->pipe;
f67a559d 4403
83d65738 4404 WARN_ON(!crtc->state->enable);
08a48469 4405
f67a559d
JB		 4406 if (intel_crtc->active)
4407 return;
4408
6e3c9717 4409 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4410 intel_prepare_shared_dpll(intel_crtc);
4411
6e3c9717 4412 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4413 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4414
4415 intel_set_pipe_timings(intel_crtc);
4416
6e3c9717 4417 if (intel_crtc->config->has_pch_encoder) {
29407aab 4418 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4419 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4420 }
4421
4422 ironlake_set_pipeconf(crtc);
4423
f67a559d 4424 intel_crtc->active = true;
8664281b 4425
a72e4c9f
DV		 4426 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4427 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4428
f6736a1a 4429 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4430 if (encoder->pre_enable)
4431 encoder->pre_enable(encoder);
f67a559d 4432
6e3c9717 4433 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4434 /* Note: FDI PLL enabling _must_ be done before we enable the
4435 * cpu pipes, hence this is separate from all the other fdi/pch
4436 * enabling. */
88cefb6c 4437 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4438 } else {
4439 assert_fdi_tx_disabled(dev_priv, pipe);
4440 assert_fdi_rx_disabled(dev_priv, pipe);
4441 }
f67a559d 4442
b074cec8 4443 ironlake_pfit_enable(intel_crtc);
f67a559d 4444
9c54c0dd
JB		 4445 /*
4446 * On ILK+ LUT must be loaded before the pipe is running but with
4447 * clocks enabled
4448 */
4449 intel_crtc_load_lut(crtc);
4450
f37fcc2a 4451 intel_update_watermarks(crtc);
e1fdc473 4452 intel_enable_pipe(intel_crtc);
f67a559d 4453
6e3c9717 4454 if (intel_crtc->config->has_pch_encoder)
f67a559d 4455 ironlake_pch_enable(crtc);
c98e9dcf 4456
f9b61ff6
DV		 4457 assert_vblank_disabled(crtc);
4458 drm_crtc_vblank_on(crtc);
4459
fa5c73b1
DV		 4460 for_each_encoder_on_crtc(dev, crtc, encoder)
4461 encoder->enable(encoder);
61b77ddd
DV		 4462
4463 if (HAS_PCH_CPT(dev))
a1520318 4464 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4465
d3eedb1a 4466 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4467}
4468
42db64ef
PZ		 4469/* IPS only exists on ULT machines and is tied to pipe A. */
4470static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4471{
f5adf94e 4472 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4473}
4474
e4916946
PZ		 4475/*
4476 * This implements the workaround described in the "notes" section of the mode
4477 * set sequence documentation. When going from no pipes or single pipe to
4478 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4479 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4480 */
4481static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4482{
4483 struct drm_device *dev = crtc->base.dev;
4484 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4485
4486 /* We want to get the other_active_crtc only if there's only 1 other
4487 * active crtc. */
d3fcc808 4488 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4489 if (!crtc_it->active || crtc_it == crtc)
4490 continue;
4491
4492 if (other_active_crtc)
4493 return;
4494
4495 other_active_crtc = crtc_it;
4496 }
4497 if (!other_active_crtc)
4498 return;
4499
4500 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4501 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4502}
4503
4f771f10
PZ		 4504static void haswell_crtc_enable(struct drm_crtc *crtc)
4505{
4506 struct drm_device *dev = crtc->dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4509 struct intel_encoder *encoder;
4510 int pipe = intel_crtc->pipe;
4f771f10 4511
83d65738 4512 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4513
4514 if (intel_crtc->active)
4515 return;
4516
df8ad70c
DV		 4517 if (intel_crtc_to_shared_dpll(intel_crtc))
4518 intel_enable_shared_dpll(intel_crtc);
4519
6e3c9717 4520 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4521 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4522
4523 intel_set_pipe_timings(intel_crtc);
4524
6e3c9717
ACO		 4525 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4526 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4527 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4528 }
4529
6e3c9717 4530 if (intel_crtc->config->has_pch_encoder) {
229fca97 4531 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4532 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4533 }
4534
4535 haswell_set_pipeconf(crtc);
4536
4537 intel_set_pipe_csc(crtc);
4538
4f771f10 4539 intel_crtc->active = true;
8664281b 4540
a72e4c9f 4541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4542 for_each_encoder_on_crtc(dev, crtc, encoder)
4543 if (encoder->pre_enable)
4544 encoder->pre_enable(encoder);
4545
6e3c9717 4546 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4547 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4548 true);
4fe9467d
ID		 4549 dev_priv->display.fdi_link_train(crtc);
4550 }
4551
1f544388 4552 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4553
bd2e244f
JB		 4554 if (IS_SKYLAKE(dev))
4555 skylake_pfit_enable(intel_crtc);
4556 else
4557 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4558
4559 /*
4560 * On ILK+ LUT must be loaded before the pipe is running but with
4561 * clocks enabled
4562 */
4563 intel_crtc_load_lut(crtc);
4564
1f544388 4565 intel_ddi_set_pipe_settings(crtc);
8228c251 4566 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4567
f37fcc2a 4568 intel_update_watermarks(crtc);
e1fdc473 4569 intel_enable_pipe(intel_crtc);
42db64ef 4570
6e3c9717 4571 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4572 lpt_pch_enable(crtc);
4f771f10 4573
6e3c9717 4574 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4575 intel_ddi_set_vc_payload_alloc(crtc, true);
4576
f9b61ff6
DV		 4577 assert_vblank_disabled(crtc);
4578 drm_crtc_vblank_on(crtc);
4579
8807e55b 4580 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4581 encoder->enable(encoder);
8807e55b
JN		 4582 intel_opregion_notify_encoder(encoder, true);
4583 }
4f771f10 4584
e4916946
PZ		 4585 /* If we change the relative order between pipe/planes enabling, we need
4586 * to change the workaround. */
4587 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4588 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4589}
4590
bd2e244f
JB		 4591static void skylake_pfit_disable(struct intel_crtc *crtc)
4592{
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 int pipe = crtc->pipe;
4596
4597 /* To avoid upsetting the power well on haswell only disable the pfit if
4598 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4599 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4600 I915_WRITE(PS_CTL(pipe), 0);
4601 I915_WRITE(PS_WIN_POS(pipe), 0);
4602 I915_WRITE(PS_WIN_SZ(pipe), 0);
4603 }
4604}
4605
3f8dce3a
DV		 4606static void ironlake_pfit_disable(struct intel_crtc *crtc)
4607{
4608 struct drm_device *dev = crtc->base.dev;
4609 struct drm_i915_private *dev_priv = dev->dev_private;
4610 int pipe = crtc->pipe;
4611
4612 /* To avoid upsetting the power well on haswell only disable the pfit if
4613 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4614 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4615 I915_WRITE(PF_CTL(pipe), 0);
4616 I915_WRITE(PF_WIN_POS(pipe), 0);
4617 I915_WRITE(PF_WIN_SZ(pipe), 0);
4618 }
4619}
4620
6be4a607
JB		 4621static void ironlake_crtc_disable(struct drm_crtc *crtc)
4622{
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4626 struct intel_encoder *encoder;
6be4a607 4627 int pipe = intel_crtc->pipe;
5eddb70b 4628 u32 reg, temp;
b52eb4dc 4629
f7abfe8b
CW		 4630 if (!intel_crtc->active)
4631 return;
4632
d3eedb1a 4633 intel_crtc_disable_planes(crtc);
a5c4d7bc 4634
ea9d758d
DV		 4635 for_each_encoder_on_crtc(dev, crtc, encoder)
4636 encoder->disable(encoder);
4637
f9b61ff6
DV		 4638 drm_crtc_vblank_off(crtc);
4639 assert_vblank_disabled(crtc);
4640
6e3c9717 4641 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4642 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4643
575f7ab7 4644 intel_disable_pipe(intel_crtc);
32f9d658 4645
3f8dce3a 4646 ironlake_pfit_disable(intel_crtc);
2c07245f 4647
bf49ec8c
DV		 4648 for_each_encoder_on_crtc(dev, crtc, encoder)
4649 if (encoder->post_disable)
4650 encoder->post_disable(encoder);
2c07245f 4651
6e3c9717 4652 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4653 ironlake_fdi_disable(crtc);
913d8d11 4654
d925c59a 4655 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4656
d925c59a
DV		 4657 if (HAS_PCH_CPT(dev)) {
4658 /* disable TRANS_DP_CTL */
4659 reg = TRANS_DP_CTL(pipe);
4660 temp = I915_READ(reg);
4661 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4662 TRANS_DP_PORT_SEL_MASK);
4663 temp |= TRANS_DP_PORT_SEL_NONE;
4664 I915_WRITE(reg, temp);
4665
4666 /* disable DPLL_SEL */
4667 temp = I915_READ(PCH_DPLL_SEL);
11887397 4668 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4669 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4670 }
e3421a18 4671
d925c59a 4672 /* disable PCH DPLL */
e72f9fbf 4673 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4674
d925c59a
DV		 4675 ironlake_fdi_pll_disable(intel_crtc);
4676 }
6b383a7f 4677
f7abfe8b 4678 intel_crtc->active = false;
46ba614c 4679 intel_update_watermarks(crtc);
d1ebd816
BW		 4680
4681 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4682 intel_fbc_update(dev);
d1ebd816 4683 mutex_unlock(&dev->struct_mutex);
6be4a607 4684}
1b3c7a47 4685
4f771f10 4686static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4687{
4f771f10
PZ		 4688 struct drm_device *dev = crtc->dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4691 struct intel_encoder *encoder;
6e3c9717 4692 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4693
4f771f10
PZ		 4694 if (!intel_crtc->active)
4695 return;
4696
d3eedb1a 4697 intel_crtc_disable_planes(crtc);
dda9a66a 4698
8807e55b
JN		 4699 for_each_encoder_on_crtc(dev, crtc, encoder) {
4700 intel_opregion_notify_encoder(encoder, false);
4f771f10 4701 encoder->disable(encoder);
8807e55b 4702 }
4f771f10 4703
f9b61ff6
DV		 4704 drm_crtc_vblank_off(crtc);
4705 assert_vblank_disabled(crtc);
4706
6e3c9717 4707 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4708 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4709 false);
575f7ab7 4710 intel_disable_pipe(intel_crtc);
4f771f10 4711
6e3c9717 4712 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4713 intel_ddi_set_vc_payload_alloc(crtc, false);
4714
ad80a810 4715 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4716
bd2e244f
JB		 4717 if (IS_SKYLAKE(dev))
4718 skylake_pfit_disable(intel_crtc);
4719 else
4720 ironlake_pfit_disable(intel_crtc);
4f771f10 4721
1f544388 4722 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4723
6e3c9717 4724 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4725 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4726 intel_ddi_fdi_disable(crtc);
83616634 4727 }
4f771f10 4728
97b040aa
ID		 4729 for_each_encoder_on_crtc(dev, crtc, encoder)
4730 if (encoder->post_disable)
4731 encoder->post_disable(encoder);
4732
4f771f10 4733 intel_crtc->active = false;
46ba614c 4734 intel_update_watermarks(crtc);
4f771f10
PZ		 4735
4736 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4737 intel_fbc_update(dev);
4f771f10 4738 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4739
4740 if (intel_crtc_to_shared_dpll(intel_crtc))
4741 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4742}
4743
ee7b9f93
JB		 4744static void ironlake_crtc_off(struct drm_crtc *crtc)
4745{
4746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4747 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4748}
4749
6441ab5f 4750
2dd24552
JB		 4751static void i9xx_pfit_enable(struct intel_crtc *crtc)
4752{
4753 struct drm_device *dev = crtc->base.dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4755 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4756
681a8504 4757 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4758 return;
4759
2dd24552 4760 /*
c0b03411
DV		 4761 * The panel fitter should only be adjusted whilst the pipe is disabled,
4762 * according to register description and PRM.
2dd24552 4763 */
c0b03411
DV		 4764 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4765 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4766
b074cec8
JB		 4767 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4768 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4769
4770 /* Border color in case we don't scale up to the full screen. Black by
4771 * default, change to something else for debugging. */
4772 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4773}
4774
d05410f9
DA		 4775static enum intel_display_power_domain port_to_power_domain(enum port port)
4776{
4777 switch (port) {
4778 case PORT_A:
4779 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4780 case PORT_B:
4781 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4782 case PORT_C:
4783 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4784 case PORT_D:
4785 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4786 default:
4787 WARN_ON_ONCE(1);
4788 return POWER_DOMAIN_PORT_OTHER;
4789 }
4790}
4791
77d22dca
ID		 4792#define for_each_power_domain(domain, mask) \
4793 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4794 if ((1 << (domain)) & (mask))
4795
319be8ae
ID		 4796enum intel_display_power_domain
4797intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4798{
4799 struct drm_device *dev = intel_encoder->base.dev;
4800 struct intel_digital_port *intel_dig_port;
4801
4802 switch (intel_encoder->type) {
4803 case INTEL_OUTPUT_UNKNOWN:
4804 /* Only DDI platforms should ever use this output type */
4805 WARN_ON_ONCE(!HAS_DDI(dev));
4806 case INTEL_OUTPUT_DISPLAYPORT:
4807 case INTEL_OUTPUT_HDMI:
4808 case INTEL_OUTPUT_EDP:
4809 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4810 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4811 case INTEL_OUTPUT_DP_MST:
4812 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4813 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4814 case INTEL_OUTPUT_ANALOG:
4815 return POWER_DOMAIN_PORT_CRT;
4816 case INTEL_OUTPUT_DSI:
4817 return POWER_DOMAIN_PORT_DSI;
4818 default:
4819 return POWER_DOMAIN_PORT_OTHER;
4820 }
4821}
4822
4823static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4824{
319be8ae
ID		 4825 struct drm_device *dev = crtc->dev;
4826 struct intel_encoder *intel_encoder;
4827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4828 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4829 unsigned long mask;
4830 enum transcoder transcoder;
4831
4832 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4833
4834 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4835 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4836 if (intel_crtc->config->pch_pfit.enabled ||
4837 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4838 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4839
319be8ae
ID		 4840 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4841 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4842
77d22dca
ID		 4843 return mask;
4844}
4845
77d22dca
ID		 4846static void modeset_update_crtc_power_domains(struct drm_device *dev)
4847{
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4850 struct intel_crtc *crtc;
4851
4852 /*
4853 * First get all needed power domains, then put all unneeded, to avoid
4854 * any unnecessary toggling of the power wells.
4855 */
d3fcc808 4856 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4857 enum intel_display_power_domain domain;
4858
83d65738 4859 if (!crtc->base.state->enable)
77d22dca
ID		 4860 continue;
4861
319be8ae 4862 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4863
4864 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4865 intel_display_power_get(dev_priv, domain);
4866 }
4867
50f6e502
VS		 4868 if (dev_priv->display.modeset_global_resources)
4869 dev_priv->display.modeset_global_resources(dev);
4870
d3fcc808 4871 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4872 enum intel_display_power_domain domain;
4873
4874 for_each_power_domain(domain, crtc->enabled_power_domains)
4875 intel_display_power_put(dev_priv, domain);
4876
4877 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4878 }
4879
4880 intel_display_set_init_power(dev_priv, false);
4881}
4882
dfcab17e 4883/* returns HPLL frequency in kHz */
f8bf63fd 4884static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 4885{
586f49dc 4886 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 4887
586f49dc
JB		 4888 /* Obtain SKU information */
4889 mutex_lock(&dev_priv->dpio_lock);
4890 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4891 CCK_FUSE_HPLL_FREQ_MASK;
4892 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 4893
dfcab17e 4894 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 4895}
4896
f8bf63fd
VS		 4897static void vlv_update_cdclk(struct drm_device *dev)
4898{
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900
4901 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 4902 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 4903 dev_priv->vlv_cdclk_freq);
4904
4905 /*
4906 * Program the gmbus_freq based on the cdclk frequency.
4907 * BSpec erroneously claims we should aim for 4MHz, but
4908 * in fact 1MHz is the correct frequency.
4909 */
6be1e3d3 4910 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 4911}
4912
30a970c6
JB		 4913/* Adjust CDclk dividers to allow high res or save power if possible */
4914static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4915{
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917 u32 val, cmd;
4918
d197b7d3 4919 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 4920
dfcab17e 4921 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 4922 cmd = 2;
dfcab17e 4923 else if (cdclk == 266667)
30a970c6
JB		 4924 cmd = 1;
4925 else
4926 cmd = 0;
4927
4928 mutex_lock(&dev_priv->rps.hw_lock);
4929 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4930 val &= ~DSPFREQGUAR_MASK;
4931 val |= (cmd << DSPFREQGUAR_SHIFT);
4932 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4933 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4934 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4935 50)) {
4936 DRM_ERROR("timed out waiting for CDclk change\n");
4937 }
4938 mutex_unlock(&dev_priv->rps.hw_lock);
4939
dfcab17e 4940 if (cdclk == 400000) {
6bcda4f0 4941 u32 divider;
30a970c6 4942
6bcda4f0 4943 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 4944
4945 mutex_lock(&dev_priv->dpio_lock);
4946 /* adjust cdclk divider */
4947 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 4948 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 4949 val |= divider;
4950 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 4951
4952 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4953 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4954 50))
4955 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 4956 mutex_unlock(&dev_priv->dpio_lock);
4957 }
4958
4959 mutex_lock(&dev_priv->dpio_lock);
4960 /* adjust self-refresh exit latency value */
4961 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4962 val &= ~0x7f;
4963
4964 /*
4965 * For high bandwidth configs, we set a higher latency in the bunit
4966 * so that the core display fetch happens in time to avoid underruns.
4967 */
dfcab17e 4968 if (cdclk == 400000)
30a970c6
JB		 4969 val |= 4500 / 250; /* 4.5 usec */
4970 else
4971 val |= 3000 / 250; /* 3.0 usec */
4972 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4973 mutex_unlock(&dev_priv->dpio_lock);
4974
f8bf63fd 4975 vlv_update_cdclk(dev);
30a970c6
JB		 4976}
4977
383c5a6a
VS		 4978static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4979{
4980 struct drm_i915_private *dev_priv = dev->dev_private;
4981 u32 val, cmd;
4982
4983 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4984
4985 switch (cdclk) {
4986 case 400000:
4987 cmd = 3;
4988 break;
4989 case 333333:
4990 case 320000:
4991 cmd = 2;
4992 break;
4993 case 266667:
4994 cmd = 1;
4995 break;
4996 case 200000:
4997 cmd = 0;
4998 break;
4999 default:
5f77eeb0 5000 MISSING_CASE(cdclk);
383c5a6a
VS		 5001 return;
5002 }
5003
5004 mutex_lock(&dev_priv->rps.hw_lock);
5005 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5006 val &= ~DSPFREQGUAR_MASK_CHV;
5007 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5008 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5009 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5010 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5011 50)) {
5012 DRM_ERROR("timed out waiting for CDclk change\n");
5013 }
5014 mutex_unlock(&dev_priv->rps.hw_lock);
5015
5016 vlv_update_cdclk(dev);
5017}
5018
30a970c6
JB		 5019static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5020 int max_pixclk)
5021{
6bcda4f0 5022 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
29dc7ef3 5023
d49a340d
VS		 5024 /* FIXME: Punit isn't quite ready yet */
5025 if (IS_CHERRYVIEW(dev_priv->dev))
5026 return 400000;
5027
30a970c6
JB		 5028 /*
5029 * Really only a few cases to deal with, as only 4 CDclks are supported:
5030 * 200MHz
5031 * 267MHz
29dc7ef3 5032 * 320/333MHz (depends on HPLL freq)
30a970c6
JB		 5033 * 400MHz
5034 * So we check to see whether we're above 90% of the lower bin and
5035 * adjust if needed.
e37c67a1
VS		 5036 *
5037 * We seem to get an unstable or solid color picture at 200MHz.
5038 * Not sure what's wrong. For now use 200MHz only when all pipes
5039 * are off.
30a970c6 5040 */
29dc7ef3 5041 if (max_pixclk > freq_320*9/10)
dfcab17e
VS		 5042 return 400000;
5043 else if (max_pixclk > 266667*9/10)
29dc7ef3 5044 return freq_320;
e37c67a1 5045 else if (max_pixclk > 0)
dfcab17e 5046 return 266667;
e37c67a1
VS		 5047 else
5048 return 200000;
30a970c6
JB		 5049}
5050
2f2d7aa1
VS		 5051/* compute the max pixel clock for new configuration */
5052static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
30a970c6
JB		 5053{
5054 struct drm_device *dev = dev_priv->dev;
5055 struct intel_crtc *intel_crtc;
5056 int max_pixclk = 0;
5057
d3fcc808 5058 for_each_intel_crtc(dev, intel_crtc) {
2f2d7aa1 5059 if (intel_crtc->new_enabled)
30a970c6 5060 max_pixclk = max(max_pixclk,
2d112de7 5061 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5062 }
5063
5064 return max_pixclk;
5065}
5066
5067static void valleyview_modeset_global_pipes(struct drm_device *dev,
2f2d7aa1 5068 unsigned *prepare_pipes)
30a970c6
JB		 5069{
5070 struct drm_i915_private *dev_priv = dev->dev_private;
5071 struct intel_crtc *intel_crtc;
2f2d7aa1 5072 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6 5073
d60c4473
ID		 5074 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5075 dev_priv->vlv_cdclk_freq)
30a970c6
JB		 5076 return;
5077
2f2d7aa1 5078 /* disable/enable all currently active pipes while we change cdclk */
d3fcc808 5079 for_each_intel_crtc(dev, intel_crtc)
83d65738 5080 if (intel_crtc->base.state->enable)
30a970c6
JB		 5081 *prepare_pipes |= (1 << intel_crtc->pipe);
5082}
5083
5084static void valleyview_modeset_global_resources(struct drm_device *dev)
5085{
5086 struct drm_i915_private *dev_priv = dev->dev_private;
2f2d7aa1 5087 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6
JB		 5088 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5089
383c5a6a 5090 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5091 /*
5092 * FIXME: We can end up here with all power domains off, yet
5093 * with a CDCLK frequency other than the minimum. To account
5094 * for this take the PIPE-A power domain, which covers the HW
5095 * blocks needed for the following programming. This can be
5096 * removed once it's guaranteed that we get here either with
5097 * the minimum CDCLK set, or the required power domains
5098 * enabled.
5099 */
5100 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5101
383c5a6a
VS		 5102 if (IS_CHERRYVIEW(dev))
5103 cherryview_set_cdclk(dev, req_cdclk);
5104 else
5105 valleyview_set_cdclk(dev, req_cdclk);
738c05c0
ID		 5106
5107 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5108 }
30a970c6
JB		 5109}
5110
89b667f8
JB		 5111static void valleyview_crtc_enable(struct drm_crtc *crtc)
5112{
5113 struct drm_device *dev = crtc->dev;
a72e4c9f 5114 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5116 struct intel_encoder *encoder;
5117 int pipe = intel_crtc->pipe;
23538ef1 5118 bool is_dsi;
89b667f8 5119
83d65738 5120 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5121
5122 if (intel_crtc->active)
5123 return;
5124
409ee761 5125 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5126
1ae0d137
VS		 5127 if (!is_dsi) {
5128 if (IS_CHERRYVIEW(dev))
6e3c9717 5129 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5130 else
6e3c9717 5131 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5132 }
5b18e57c 5133
6e3c9717 5134 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5135 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5136
5137 intel_set_pipe_timings(intel_crtc);
5138
c14b0485
VS		 5139 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141
5142 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5143 I915_WRITE(CHV_CANVAS(pipe), 0);
5144 }
5145
5b18e57c
DV		 5146 i9xx_set_pipeconf(intel_crtc);
5147
89b667f8 5148 intel_crtc->active = true;
89b667f8 5149
a72e4c9f 5150 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5151
89b667f8
JB		 5152 for_each_encoder_on_crtc(dev, crtc, encoder)
5153 if (encoder->pre_pll_enable)
5154 encoder->pre_pll_enable(encoder);
5155
9d556c99
CML		 5156 if (!is_dsi) {
5157 if (IS_CHERRYVIEW(dev))
6e3c9717 5158 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5159 else
6e3c9717 5160 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5161 }
89b667f8
JB		 5162
5163 for_each_encoder_on_crtc(dev, crtc, encoder)
5164 if (encoder->pre_enable)
5165 encoder->pre_enable(encoder);
5166
2dd24552
JB		 5167 i9xx_pfit_enable(intel_crtc);
5168
63cbb074
VS		 5169 intel_crtc_load_lut(crtc);
5170
f37fcc2a 5171 intel_update_watermarks(crtc);
e1fdc473 5172 intel_enable_pipe(intel_crtc);
be6a6f8e 5173
4b3a9526
VS		 5174 assert_vblank_disabled(crtc);
5175 drm_crtc_vblank_on(crtc);
5176
f9b61ff6
DV		 5177 for_each_encoder_on_crtc(dev, crtc, encoder)
5178 encoder->enable(encoder);
5179
9ab0460b 5180 intel_crtc_enable_planes(crtc);
d40d9187 5181
56b80e1f 5182 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5183 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5184}
5185
f13c2ef3
DV		 5186static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5187{
5188 struct drm_device *dev = crtc->base.dev;
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190
6e3c9717
ACO		 5191 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5192 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5193}
5194
0b8765c6 5195static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5196{
5197 struct drm_device *dev = crtc->dev;
a72e4c9f 5198 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5200 struct intel_encoder *encoder;
79e53945 5201 int pipe = intel_crtc->pipe;
79e53945 5202
83d65738 5203 WARN_ON(!crtc->state->enable);
08a48469 5204
f7abfe8b
CW		 5205 if (intel_crtc->active)
5206 return;
5207
f13c2ef3
DV		 5208 i9xx_set_pll_dividers(intel_crtc);
5209
6e3c9717 5210 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5211 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5212
5213 intel_set_pipe_timings(intel_crtc);
5214
5b18e57c
DV		 5215 i9xx_set_pipeconf(intel_crtc);
5216
f7abfe8b 5217 intel_crtc->active = true;
6b383a7f 5218
4a3436e8 5219 if (!IS_GEN2(dev))
a72e4c9f 5220 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5221
9d6d9f19
MK		 5222 for_each_encoder_on_crtc(dev, crtc, encoder)
5223 if (encoder->pre_enable)
5224 encoder->pre_enable(encoder);
5225
f6736a1a
DV		 5226 i9xx_enable_pll(intel_crtc);
5227
2dd24552
JB		 5228 i9xx_pfit_enable(intel_crtc);
5229
63cbb074
VS		 5230 intel_crtc_load_lut(crtc);
5231
f37fcc2a 5232 intel_update_watermarks(crtc);
e1fdc473 5233 intel_enable_pipe(intel_crtc);
be6a6f8e 5234
4b3a9526
VS		 5235 assert_vblank_disabled(crtc);
5236 drm_crtc_vblank_on(crtc);
5237
f9b61ff6
DV		 5238 for_each_encoder_on_crtc(dev, crtc, encoder)
5239 encoder->enable(encoder);
5240
9ab0460b 5241 intel_crtc_enable_planes(crtc);
d40d9187 5242
4a3436e8
VS		 5243 /*
5244 * Gen2 reports pipe underruns whenever all planes are disabled.
5245 * So don't enable underrun reporting before at least some planes
5246 * are enabled.
5247 * FIXME: Need to fix the logic to work when we turn off all planes
5248 * but leave the pipe running.
5249 */
5250 if (IS_GEN2(dev))
a72e4c9f 5251 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5252
56b80e1f 5253 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5254 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5255}
79e53945 5256
87476d63
DV		 5257static void i9xx_pfit_disable(struct intel_crtc *crtc)
5258{
5259 struct drm_device *dev = crtc->base.dev;
5260 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5261
6e3c9717 5262 if (!crtc->config->gmch_pfit.control)
328d8e82 5263 return;
87476d63 5264
328d8e82 5265 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5266
328d8e82
DV		 5267 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5268 I915_READ(PFIT_CONTROL));
5269 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5270}
5271
0b8765c6
JB		 5272static void i9xx_crtc_disable(struct drm_crtc *crtc)
5273{
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5277 struct intel_encoder *encoder;
0b8765c6 5278 int pipe = intel_crtc->pipe;
ef9c3aee 5279
f7abfe8b
CW		 5280 if (!intel_crtc->active)
5281 return;
5282
4a3436e8
VS		 5283 /*
5284 * Gen2 reports pipe underruns whenever all planes are disabled.
5285 * So diasble underrun reporting before all the planes get disabled.
5286 * FIXME: Need to fix the logic to work when we turn off all planes
5287 * but leave the pipe running.
5288 */
5289 if (IS_GEN2(dev))
a72e4c9f 5290 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5291
564ed191
ID		 5292 /*
5293 * Vblank time updates from the shadow to live plane control register
5294 * are blocked if the memory self-refresh mode is active at that
5295 * moment. So to make sure the plane gets truly disabled, disable
5296 * first the self-refresh mode. The self-refresh enable bit in turn
5297 * will be checked/applied by the HW only at the next frame start
5298 * event which is after the vblank start event, so we need to have a
5299 * wait-for-vblank between disabling the plane and the pipe.
5300 */
5301 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5302 intel_crtc_disable_planes(crtc);
5303
6304cd91
VS		 5304 /*
5305 * On gen2 planes are double buffered but the pipe isn't, so we must
5306 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5307 * We also need to wait on all gmch platforms because of the
5308 * self-refresh mode constraint explained above.
6304cd91 5309 */
564ed191 5310 intel_wait_for_vblank(dev, pipe);
6304cd91 5311
4b3a9526
VS		 5312 for_each_encoder_on_crtc(dev, crtc, encoder)
5313 encoder->disable(encoder);
5314
f9b61ff6
DV		 5315 drm_crtc_vblank_off(crtc);
5316 assert_vblank_disabled(crtc);
5317
575f7ab7 5318 intel_disable_pipe(intel_crtc);
24a1f16d 5319
87476d63 5320 i9xx_pfit_disable(intel_crtc);
24a1f16d 5321
89b667f8
JB		 5322 for_each_encoder_on_crtc(dev, crtc, encoder)
5323 if (encoder->post_disable)
5324 encoder->post_disable(encoder);
5325
409ee761 5326 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5327 if (IS_CHERRYVIEW(dev))
5328 chv_disable_pll(dev_priv, pipe);
5329 else if (IS_VALLEYVIEW(dev))
5330 vlv_disable_pll(dev_priv, pipe);
5331 else
1c4e0274 5332 i9xx_disable_pll(intel_crtc);
076ed3b2 5333 }
0b8765c6 5334
4a3436e8 5335 if (!IS_GEN2(dev))
a72e4c9f 5336 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5337
f7abfe8b 5338 intel_crtc->active = false;
46ba614c 5339 intel_update_watermarks(crtc);
f37fcc2a 5340
efa9624e 5341 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5342 intel_fbc_update(dev);
efa9624e 5343 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5344}
5345
ee7b9f93
JB		 5346static void i9xx_crtc_off(struct drm_crtc *crtc)
5347{
5348}
5349
b04c5bd6
BF		 5350/* Master function to enable/disable CRTC and corresponding power wells */
5351void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5352{
5353 struct drm_device *dev = crtc->dev;
5354 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5356 enum intel_display_power_domain domain;
5357 unsigned long domains;
976f8a20 5358
0e572fe7
DV		 5359 if (enable) {
5360 if (!intel_crtc->active) {
e1e9fb84
DV		 5361 domains = get_crtc_power_domains(crtc);
5362 for_each_power_domain(domain, domains)
5363 intel_display_power_get(dev_priv, domain);
5364 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5365
5366 dev_priv->display.crtc_enable(crtc);
5367 }
5368 } else {
5369 if (intel_crtc->active) {
5370 dev_priv->display.crtc_disable(crtc);
5371
e1e9fb84
DV		 5372 domains = intel_crtc->enabled_power_domains;
5373 for_each_power_domain(domain, domains)
5374 intel_display_power_put(dev_priv, domain);
5375 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5376 }
5377 }
b04c5bd6
BF		 5378}
5379
5380/**
5381 * Sets the power management mode of the pipe and plane.
5382 */
5383void intel_crtc_update_dpms(struct drm_crtc *crtc)
5384{
5385 struct drm_device *dev = crtc->dev;
5386 struct intel_encoder *intel_encoder;
5387 bool enable = false;
5388
5389 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5390 enable |= intel_encoder->connectors_active;
5391
5392 intel_crtc_control(crtc, enable);
976f8a20
DV		 5393}
5394
cdd59983
CW		 5395static void intel_crtc_disable(struct drm_crtc *crtc)
5396{
cdd59983 5397 struct drm_device *dev = crtc->dev;
976f8a20 5398 struct drm_connector *connector;
ee7b9f93 5399 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5400
976f8a20 5401 /* crtc should still be enabled when we disable it. */
83d65738 5402 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5403
5404 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5405 dev_priv->display.off(crtc);
5406
455a6808 5407 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5408
5409 /* Update computed state. */
5410 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5411 if (!connector->encoder || !connector->encoder->crtc)
5412 continue;
5413
5414 if (connector->encoder->crtc != crtc)
5415 continue;
5416
5417 connector->dpms = DRM_MODE_DPMS_OFF;
5418 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5419 }
5420}
5421
ea5b213a 5422void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5423{
4ef69c7a 5424 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5425
ea5b213a
CW		 5426 drm_encoder_cleanup(encoder);
5427 kfree(intel_encoder);
7e7d76c3
JB		 5428}
5429
9237329d 5430/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5431 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5432 * state of the entire output pipe. */
9237329d 5433static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5434{
5ab432ef
DV		 5435 if (mode == DRM_MODE_DPMS_ON) {
5436 encoder->connectors_active = true;
5437
b2cabb0e 5438 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5439 } else {
5440 encoder->connectors_active = false;
5441
b2cabb0e 5442 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5443 }
79e53945
JB		 5444}
5445
0a91ca29
DV		 5446/* Cross check the actual hw state with our own modeset state tracking (and it's
5447 * internal consistency). */
b980514c 5448static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5449{
0a91ca29
DV		 5450 if (connector->get_hw_state(connector)) {
5451 struct intel_encoder *encoder = connector->encoder;
5452 struct drm_crtc *crtc;
5453 bool encoder_enabled;
5454 enum pipe pipe;
5455
5456 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5457 connector->base.base.id,
c23cc417 5458 connector->base.name);
0a91ca29 5459
0e32b39c
DA		 5460 /* there is no real hw state for MST connectors */
5461 if (connector->mst_port)
5462 return;
5463
e2c719b7 5464 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5465 "wrong connector dpms state\n");
e2c719b7 5466 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5467 "active connector not linked to encoder\n");
0a91ca29 5468
36cd7444 5469 if (encoder) {
e2c719b7 5470 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5471 "encoder->connectors_active not set\n");
5472
5473 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5474 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5475 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5476 return;
0a91ca29 5477
36cd7444 5478 crtc = encoder->base.crtc;
0a91ca29 5479
83d65738
MR		 5480 I915_STATE_WARN(!crtc->state->enable,
5481 "crtc not enabled\n");
e2c719b7
RC		 5482 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5483 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5484 "encoder active on the wrong pipe\n");
5485 }
0a91ca29 5486 }
79e53945
JB		 5487}
5488
5ab432ef
DV		 5489/* Even simpler default implementation, if there's really no special case to
5490 * consider. */
5491void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5492{
5ab432ef
DV		 5493 /* All the simple cases only support two dpms states. */
5494 if (mode != DRM_MODE_DPMS_ON)
5495 mode = DRM_MODE_DPMS_OFF;
d4270e57 5496
5ab432ef
DV		 5497 if (mode == connector->dpms)
5498 return;
5499
5500 connector->dpms = mode;
5501
5502 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5503 if (connector->encoder)
5504 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5505
b980514c 5506 intel_modeset_check_state(connector->dev);
79e53945
JB		 5507}
5508
f0947c37
DV		 5509/* Simple connector->get_hw_state implementation for encoders that support only
5510 * one connector and no cloning and hence the encoder state determines the state
5511 * of the connector. */
5512bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5513{
24929352 5514 enum pipe pipe = 0;
f0947c37 5515 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5516
f0947c37 5517 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5518}
5519
1857e1da 5520static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5521 struct intel_crtc_state *pipe_config)
1857e1da
DV		 5522{
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524 struct intel_crtc *pipe_B_crtc =
5525 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5526
5527 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5528 pipe_name(pipe), pipe_config->fdi_lanes);
5529 if (pipe_config->fdi_lanes > 4) {
5530 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5531 pipe_name(pipe), pipe_config->fdi_lanes);
5532 return false;
5533 }
5534
bafb6553 5535 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5536 if (pipe_config->fdi_lanes > 2) {
5537 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5538 pipe_config->fdi_lanes);
5539 return false;
5540 } else {
5541 return true;
5542 }
5543 }
5544
5545 if (INTEL_INFO(dev)->num_pipes == 2)
5546 return true;
5547
5548 /* Ivybridge 3 pipe is really complicated */
5549 switch (pipe) {
5550 case PIPE_A:
5551 return true;
5552 case PIPE_B:
5553 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5554 pipe_config->fdi_lanes > 2) {
5555 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5556 pipe_name(pipe), pipe_config->fdi_lanes);
5557 return false;
5558 }
5559 return true;
5560 case PIPE_C:
1e833f40 5561 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
6e3c9717 5562 pipe_B_crtc->config->fdi_lanes <= 2) {
1857e1da
DV		 5563 if (pipe_config->fdi_lanes > 2) {
5564 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5565 pipe_name(pipe), pipe_config->fdi_lanes);
5566 return false;
5567 }
5568 } else {
5569 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5570 return false;
5571 }
5572 return true;
5573 default:
5574 BUG();
5575 }
5576}
5577
e29c22c0
DV		 5578#define RETRY 1
5579static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5580 struct intel_crtc_state *pipe_config)
877d48d5 5581{
1857e1da 5582 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5583 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
ff9a6750 5584 int lane, link_bw, fdi_dotclock;
e29c22c0 5585 bool setup_ok, needs_recompute = false;
877d48d5 5586
e29c22c0 5587retry:
877d48d5
DV		 5588 /* FDI is a binary signal running at ~2.7GHz, encoding
5589 * each output octet as 10 bits. The actual frequency
5590 * is stored as a divider into a 100MHz clock, and the
5591 * mode pixel clock is stored in units of 1KHz.
5592 * Hence the bw of each lane in terms of the mode signal
5593 * is:
5594 */
5595 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5596
241bfc38 5597 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5598
2bd89a07 5599 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5600 pipe_config->pipe_bpp);
5601
5602 pipe_config->fdi_lanes = lane;
5603
2bd89a07 5604 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5605 link_bw, &pipe_config->fdi_m_n);
1857e1da 5606
e29c22c0
DV		 5607 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5608 intel_crtc->pipe, pipe_config);
5609 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5610 pipe_config->pipe_bpp -= 2*3;
5611 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5612 pipe_config->pipe_bpp);
5613 needs_recompute = true;
5614 pipe_config->bw_constrained = true;
5615
5616 goto retry;
5617 }
5618
5619 if (needs_recompute)
5620 return RETRY;
5621
5622 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 5623}
5624
42db64ef 5625static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5626 struct intel_crtc_state *pipe_config)
42db64ef 5627{
d330a953 5628 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5629 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5630 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5631}
5632
a43f6e0f 5633static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5634 struct intel_crtc_state *pipe_config)
79e53945 5635{
a43f6e0f 5636 struct drm_device *dev = crtc->base.dev;
8bd31e67 5637 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5638 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5639
ad3a4479 5640 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5641 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5642 int clock_limit =
5643 dev_priv->display.get_display_clock_speed(dev);
5644
5645 /*
5646 * Enable pixel doubling when the dot clock
5647 * is > 90% of the (display) core speed.
5648 *
b397c96b
VS		 5649 * GDG double wide on either pipe,
5650 * otherwise pipe A only.
cf532bb2 5651 */
b397c96b 5652 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5653 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5654 clock_limit *= 2;
cf532bb2 5655 pipe_config->double_wide = true;
ad3a4479
VS		 5656 }
5657
241bfc38 5658 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5659 return -EINVAL;
2c07245f 5660 }
89749350 5661
1d1d0e27
VS		 5662 /*
5663 * Pipe horizontal size must be even in:
5664 * - DVO ganged mode
5665 * - LVDS dual channel mode
5666 * - Double wide pipe
5667 */
b4f2bf4c 5668 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5669 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5670 pipe_config->pipe_src_w &= ~1;
5671
8693a824
DL		 5672 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5673 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5674 */
5675 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5676 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5677 return -EINVAL;
44f46b42 5678
bd080ee5 5679 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5680 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5681 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5682 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5683 * for lvds. */
5684 pipe_config->pipe_bpp = 8*3;
5685 }
5686
f5adf94e 5687 if (HAS_IPS(dev))
a43f6e0f
DV		 5688 hsw_compute_ips_config(crtc, pipe_config);
5689
877d48d5 5690 if (pipe_config->has_pch_encoder)
a43f6e0f 5691 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5692
e29c22c0 5693 return 0;
79e53945
JB		 5694}
5695
25eb05fc
JB		 5696static int valleyview_get_display_clock_speed(struct drm_device *dev)
5697{
d197b7d3 5698 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5699 u32 val;
5700 int divider;
5701
d49a340d
VS		 5702 /* FIXME: Punit isn't quite ready yet */
5703 if (IS_CHERRYVIEW(dev))
5704 return 400000;
5705
6bcda4f0
VS		 5706 if (dev_priv->hpll_freq == 0)
5707 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5708
d197b7d3
VS		 5709 mutex_lock(&dev_priv->dpio_lock);
5710 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5711 mutex_unlock(&dev_priv->dpio_lock);
5712
5713 divider = val & DISPLAY_FREQUENCY_VALUES;
5714
7d007f40
VS		 5715 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5716 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5717 "cdclk change in progress\n");
5718
6bcda4f0 5719 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5720}
5721
e70236a8
JB		 5722static int i945_get_display_clock_speed(struct drm_device *dev)
5723{
5724 return 400000;
5725}
79e53945 5726
e70236a8 5727static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 5728{
e70236a8
JB		 5729 return 333000;
5730}
79e53945 5731
e70236a8
JB		 5732static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5733{
5734 return 200000;
5735}
79e53945 5736
257a7ffc
DV		 5737static int pnv_get_display_clock_speed(struct drm_device *dev)
5738{
5739 u16 gcfgc = 0;
5740
5741 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5742
5743 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5744 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5745 return 267000;
5746 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5747 return 333000;
5748 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5749 return 444000;
5750 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5751 return 200000;
5752 default:
5753 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5754 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5755 return 133000;
5756 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5757 return 167000;
5758 }
5759}
5760
e70236a8
JB		 5761static int i915gm_get_display_clock_speed(struct drm_device *dev)
5762{
5763 u16 gcfgc = 0;
79e53945 5764
e70236a8
JB		 5765 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5766
5767 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5768 return 133000;
5769 else {
5770 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5771 case GC_DISPLAY_CLOCK_333_MHZ:
5772 return 333000;
5773 default:
5774 case GC_DISPLAY_CLOCK_190_200_MHZ:
5775 return 190000;
79e53945 5776 }
e70236a8
JB		 5777 }
5778}
5779
5780static int i865_get_display_clock_speed(struct drm_device *dev)
5781{
5782 return 266000;
5783}
5784
5785static int i855_get_display_clock_speed(struct drm_device *dev)
5786{
5787 u16 hpllcc = 0;
5788 /* Assume that the hardware is in the high speed state. This
5789 * should be the default.
5790 */
5791 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5792 case GC_CLOCK_133_200:
5793 case GC_CLOCK_100_200:
5794 return 200000;
5795 case GC_CLOCK_166_250:
5796 return 250000;
5797 case GC_CLOCK_100_133:
79e53945 5798 return 133000;
e70236a8 5799 }
79e53945 5800
e70236a8
JB		 5801 /* Shouldn't happen */
5802 return 0;
5803}
79e53945 5804
e70236a8
JB		 5805static int i830_get_display_clock_speed(struct drm_device *dev)
5806{
5807 return 133000;
79e53945
JB		 5808}
5809
2c07245f 5810static void
a65851af 5811intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 5812{
a65851af
VS		 5813 while (*num > DATA_LINK_M_N_MASK ||
5814 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 5815 *num >>= 1;
5816 *den >>= 1;
5817 }
5818}
5819
a65851af
VS		 5820static void compute_m_n(unsigned int m, unsigned int n,
5821 uint32_t *ret_m, uint32_t *ret_n)
5822{
5823 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5824 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5825 intel_reduce_m_n_ratio(ret_m, ret_n);
5826}
5827
e69d0bc1
DV		 5828void
5829intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5830 int pixel_clock, int link_clock,
5831 struct intel_link_m_n *m_n)
2c07245f 5832{
e69d0bc1 5833 m_n->tu = 64;
a65851af
VS		 5834
5835 compute_m_n(bits_per_pixel * pixel_clock,
5836 link_clock * nlanes * 8,
5837 &m_n->gmch_m, &m_n->gmch_n);
5838
5839 compute_m_n(pixel_clock, link_clock,
5840 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 5841}
5842
a7615030
CW		 5843static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5844{
d330a953
JN		 5845 if (i915.panel_use_ssc >= 0)
5846 return i915.panel_use_ssc != 0;
41aa3448 5847 return dev_priv->vbt.lvds_use_ssc
435793df 5848 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 5849}
5850
409ee761 5851static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
c65d77d8 5852{
409ee761 5853 struct drm_device *dev = crtc->base.dev;
c65d77d8
JB		 5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 int refclk;
5856
a0c4da24 5857 if (IS_VALLEYVIEW(dev)) {
9a0ea498 5858 refclk = 100000;
d0737e1d 5859 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 5860 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 5861 refclk = dev_priv->vbt.lvds_ssc_freq;
5862 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 5863 } else if (!IS_GEN2(dev)) {
5864 refclk = 96000;
5865 } else {
5866 refclk = 48000;
5867 }
5868
5869 return refclk;
5870}
5871
7429e9d4 5872static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 5873{
7df00d7a 5874 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 5875}
f47709a9 5876
7429e9d4
DV		 5877static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5878{
5879 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 5880}
5881
f47709a9 5882static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 5883 struct intel_crtc_state *crtc_state,
a7516a05
JB		 5884 intel_clock_t *reduced_clock)
5885{
f47709a9 5886 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 5887 u32 fp, fp2 = 0;
5888
5889 if (IS_PINEVIEW(dev)) {
190f68c5 5890 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 5891 if (reduced_clock)
7429e9d4 5892 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 5893 } else {
190f68c5 5894 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 5895 if (reduced_clock)
7429e9d4 5896 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 5897 }
5898
190f68c5 5899 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 5900
f47709a9 5901 crtc->lowfreq_avail = false;
e1f234bd 5902 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
d330a953 5903 reduced_clock && i915.powersave) {
190f68c5 5904 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 5905 crtc->lowfreq_avail = true;
a7516a05 5906 } else {
190f68c5 5907 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 5908 }
5909}
5910
5e69f97f
CML		 5911static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5912 pipe)
89b667f8
JB		 5913{
5914 u32 reg_val;
5915
5916 /*
5917 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5918 * and set it to a reasonable value instead.
5919 */
ab3c759a 5920 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 5921 reg_val &= 0xffffff00;
5922 reg_val |= 0x00000030;
ab3c759a 5923 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 5924
ab3c759a 5925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 5926 reg_val &= 0x8cffffff;
5927 reg_val = 0x8c000000;
ab3c759a 5928 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 5929
ab3c759a 5930 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 5931 reg_val &= 0xffffff00;
ab3c759a 5932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 5933
ab3c759a 5934 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 5935 reg_val &= 0x00ffffff;
5936 reg_val |= 0xb0000000;
ab3c759a 5937 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 5938}
5939
b551842d
DV		 5940static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5941 struct intel_link_m_n *m_n)
5942{
5943 struct drm_device *dev = crtc->base.dev;
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945 int pipe = crtc->pipe;
5946
e3b95f1e
DV		 5947 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5948 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5949 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5950 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 5951}
5952
5953static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 5954 struct intel_link_m_n *m_n,
5955 struct intel_link_m_n *m2_n2)
b551842d
DV		 5956{
5957 struct drm_device *dev = crtc->base.dev;
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 int pipe = crtc->pipe;
6e3c9717 5960 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 5961
5962 if (INTEL_INFO(dev)->gen >= 5) {
5963 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5964 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5965 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5966 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 5967 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5968 * for gen < 8) and if DRRS is supported (to make sure the
5969 * registers are not unnecessarily accessed).
5970 */
44395bfe 5971 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 5972 crtc->config->has_drrs) {
f769cd24
VK		 5973 I915_WRITE(PIPE_DATA_M2(transcoder),
5974 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5975 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5976 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5977 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5978 }
b551842d 5979 } else {
e3b95f1e
DV		 5980 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5981 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5982 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5983 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 5984 }
5985}
5986
fe3cd48d 5987void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 5988{
fe3cd48d
R		 5989 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5990
5991 if (m_n == M1_N1) {
5992 dp_m_n = &crtc->config->dp_m_n;
5993 dp_m2_n2 = &crtc->config->dp_m2_n2;
5994 } else if (m_n == M2_N2) {
5995
5996 /*
5997 * M2_N2 registers are not supported. Hence m2_n2 divider value
5998 * needs to be programmed into M1_N1.
5999 */
6000 dp_m_n = &crtc->config->dp_m2_n2;
6001 } else {
6002 DRM_ERROR("Unsupported divider value\n");
6003 return;
6004 }
6005
6e3c9717
ACO		 6006 if (crtc->config->has_pch_encoder)
6007 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6008 else
fe3cd48d 6009 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6010}
6011
d288f65f 6012static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6013 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6014{
6015 u32 dpll, dpll_md;
6016
6017 /*
6018 * Enable DPIO clock input. We should never disable the reference
6019 * clock for pipe B, since VGA hotplug / manual detection depends
6020 * on it.
6021 */
6022 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6023 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6024 /* We should never disable this, set it here for state tracking */
6025 if (crtc->pipe == PIPE_B)
6026 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6027 dpll |= DPLL_VCO_ENABLE;
d288f65f 6028 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6029
d288f65f 6030 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6031 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6032 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6033}
6034
d288f65f 6035static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6036 const struct intel_crtc_state *pipe_config)
a0c4da24 6037{
f47709a9 6038 struct drm_device *dev = crtc->base.dev;
a0c4da24 6039 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6040 int pipe = crtc->pipe;
bdd4b6a6 6041 u32 mdiv;
a0c4da24 6042 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6043 u32 coreclk, reg_val;
a0c4da24 6044
09153000
DV		 6045 mutex_lock(&dev_priv->dpio_lock);
6046
d288f65f
VS		 6047 bestn = pipe_config->dpll.n;
6048 bestm1 = pipe_config->dpll.m1;
6049 bestm2 = pipe_config->dpll.m2;
6050 bestp1 = pipe_config->dpll.p1;
6051 bestp2 = pipe_config->dpll.p2;
a0c4da24 6052
89b667f8
JB		 6053 /* See eDP HDMI DPIO driver vbios notes doc */
6054
6055 /* PLL B needs special handling */
bdd4b6a6 6056 if (pipe == PIPE_B)
5e69f97f 6057 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6058
6059 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6060 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6061
6062 /* Disable target IRef on PLL */
ab3c759a 6063 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6064 reg_val &= 0x00ffffff;
ab3c759a 6065 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6066
6067 /* Disable fast lock */
ab3c759a 6068 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6069
6070 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6071 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6072 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6073 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6074 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6075
6076 /*
6077 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6078 * but we don't support that).
6079 * Note: don't use the DAC post divider as it seems unstable.
6080 */
6081 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6082 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6083
a0c4da24 6084 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6085 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6086
89b667f8 6087 /* Set HBR and RBR LPF coefficients */
d288f65f 6088 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6089 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6090 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6091 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6092 0x009f0003);
89b667f8 6093 else
ab3c759a 6094 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6095 0x00d0000f);
6096
681a8504 6097 if (pipe_config->has_dp_encoder) {
89b667f8 6098 /* Use SSC source */
bdd4b6a6 6099 if (pipe == PIPE_A)
ab3c759a 6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6101 0x0df40000);
6102 else
ab3c759a 6103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6104 0x0df70000);
6105 } else { /* HDMI or VGA */
6106 /* Use bend source */
bdd4b6a6 6107 if (pipe == PIPE_A)
ab3c759a 6108 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6109 0x0df70000);
6110 else
ab3c759a 6111 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6112 0x0df40000);
6113 }
a0c4da24 6114
ab3c759a 6115 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6116 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6117 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6118 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6119 coreclk |= 0x01000000;
ab3c759a 6120 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6121
ab3c759a 6122 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6123 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6124}
6125
d288f65f 6126static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6127 struct intel_crtc_state *pipe_config)
1ae0d137 6128{
d288f65f 6129 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6130 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6131 DPLL_VCO_ENABLE;
6132 if (crtc->pipe != PIPE_A)
d288f65f 6133 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6134
d288f65f
VS		 6135 pipe_config->dpll_hw_state.dpll_md =
6136 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6137}
6138
d288f65f 6139static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6140 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6141{
6142 struct drm_device *dev = crtc->base.dev;
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 int pipe = crtc->pipe;
6145 int dpll_reg = DPLL(crtc->pipe);
6146 enum dpio_channel port = vlv_pipe_to_channel(pipe);
580d3811 6147 u32 loopfilter, intcoeff;
9d556c99
CML		 6148 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6149 int refclk;
6150
d288f65f
VS		 6151 bestn = pipe_config->dpll.n;
6152 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6153 bestm1 = pipe_config->dpll.m1;
6154 bestm2 = pipe_config->dpll.m2 >> 22;
6155 bestp1 = pipe_config->dpll.p1;
6156 bestp2 = pipe_config->dpll.p2;
9d556c99
CML		 6157
6158 /*
6159 * Enable Refclk and SSC
6160 */
a11b0703 6161 I915_WRITE(dpll_reg,
d288f65f 6162 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6163
6164 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6165
9d556c99
CML		 6166 /* p1 and p2 divider */
6167 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6168 5 << DPIO_CHV_S1_DIV_SHIFT |
6169 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6170 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6171 1 << DPIO_CHV_K_DIV_SHIFT);
6172
6173 /* Feedback post-divider - m2 */
6174 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6175
6176 /* Feedback refclk divider - n and m1 */
6177 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6178 DPIO_CHV_M1_DIV_BY_2 |
6179 1 << DPIO_CHV_N_DIV_SHIFT);
6180
6181 /* M2 fraction division */
6182 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6183
6184 /* M2 fraction division enable */
6185 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6186 DPIO_CHV_FRAC_DIV_EN |
6187 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6188
6189 /* Loop filter */
409ee761 6190 refclk = i9xx_get_refclk(crtc, 0);
9d556c99
CML		 6191 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6192 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6193 if (refclk == 100000)
6194 intcoeff = 11;
6195 else if (refclk == 38400)
6196 intcoeff = 10;
6197 else
6198 intcoeff = 9;
6199 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6200 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6201
6202 /* AFC Recal */
6203 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6204 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6205 DPIO_AFC_RECAL);
6206
6207 mutex_unlock(&dev_priv->dpio_lock);
6208}
6209
d288f65f
VS		 6210/**
6211 * vlv_force_pll_on - forcibly enable just the PLL
6212 * @dev_priv: i915 private structure
6213 * @pipe: pipe PLL to enable
6214 * @dpll: PLL configuration
6215 *
6216 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6217 * in cases where we need the PLL enabled even when @pipe is not going to
6218 * be enabled.
6219 */
6220void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6221 const struct dpll *dpll)
6222{
6223 struct intel_crtc *crtc =
6224 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6225 struct intel_crtc_state pipe_config = {
d288f65f
VS		 6226 .pixel_multiplier = 1,
6227 .dpll = *dpll,
6228 };
6229
6230 if (IS_CHERRYVIEW(dev)) {
6231 chv_update_pll(crtc, &pipe_config);
6232 chv_prepare_pll(crtc, &pipe_config);
6233 chv_enable_pll(crtc, &pipe_config);
6234 } else {
6235 vlv_update_pll(crtc, &pipe_config);
6236 vlv_prepare_pll(crtc, &pipe_config);
6237 vlv_enable_pll(crtc, &pipe_config);
6238 }
6239}
6240
6241/**
6242 * vlv_force_pll_off - forcibly disable just the PLL
6243 * @dev_priv: i915 private structure
6244 * @pipe: pipe PLL to disable
6245 *
6246 * Disable the PLL for @pipe. To be used in cases where we need
6247 * the PLL enabled even when @pipe is not going to be enabled.
6248 */
6249void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6250{
6251 if (IS_CHERRYVIEW(dev))
6252 chv_disable_pll(to_i915(dev), pipe);
6253 else
6254 vlv_disable_pll(to_i915(dev), pipe);
6255}
6256
f47709a9 6257static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6258 struct intel_crtc_state *crtc_state,
f47709a9 6259 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6260 int num_connectors)
6261{
f47709a9 6262 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6263 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6264 u32 dpll;
6265 bool is_sdvo;
190f68c5 6266 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6267
190f68c5 6268 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6269
d0737e1d
ACO		 6270 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6271 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6272
6273 dpll = DPLL_VGA_MODE_DIS;
6274
d0737e1d 6275 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6276 dpll |= DPLLB_MODE_LVDS;
6277 else
6278 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6279
ef1b460d 6280 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6281 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6282 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6283 }
198a037f
DV		 6284
6285 if (is_sdvo)
4a33e48d 6286 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6287
190f68c5 6288 if (crtc_state->has_dp_encoder)
4a33e48d 6289 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6290
6291 /* compute bitmask from p1 value */
6292 if (IS_PINEVIEW(dev))
6293 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6294 else {
6295 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6296 if (IS_G4X(dev) && reduced_clock)
6297 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6298 }
6299 switch (clock->p2) {
6300 case 5:
6301 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6302 break;
6303 case 7:
6304 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6305 break;
6306 case 10:
6307 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6308 break;
6309 case 14:
6310 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6311 break;
6312 }
6313 if (INTEL_INFO(dev)->gen >= 4)
6314 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6315
190f68c5 6316 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6317 dpll |= PLL_REF_INPUT_TVCLKINBC;
d0737e1d 6318 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6319 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6320 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6321 else
6322 dpll |= PLL_REF_INPUT_DREFCLK;
6323
6324 dpll |= DPLL_VCO_ENABLE;
190f68c5 6325 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6326
eb1cbe48 6327 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6328 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6329 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6330 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6331 }
6332}
6333
f47709a9 6334static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6335 struct intel_crtc_state *crtc_state,
f47709a9 6336 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6337 int num_connectors)
6338{
f47709a9 6339 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6340 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6341 u32 dpll;
190f68c5 6342 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6343
190f68c5 6344 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6345
eb1cbe48
DV		 6346 dpll = DPLL_VGA_MODE_DIS;
6347
d0737e1d 6348 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6349 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6350 } else {
6351 if (clock->p1 == 2)
6352 dpll |= PLL_P1_DIVIDE_BY_TWO;
6353 else
6354 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6355 if (clock->p2 == 4)
6356 dpll |= PLL_P2_DIVIDE_BY_4;
6357 }
6358
d0737e1d 6359 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6360 dpll |= DPLL_DVO_2X_MODE;
6361
d0737e1d 6362 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6363 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6364 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6365 else
6366 dpll |= PLL_REF_INPUT_DREFCLK;
6367
6368 dpll |= DPLL_VCO_ENABLE;
190f68c5 6369 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6370}
6371
8a654f3b 6372static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6373{
6374 struct drm_device *dev = intel_crtc->base.dev;
6375 struct drm_i915_private *dev_priv = dev->dev_private;
6376 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6377 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6378 struct drm_display_mode *adjusted_mode =
6e3c9717 6379 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6380 uint32_t crtc_vtotal, crtc_vblank_end;
6381 int vsyncshift = 0;
4d8a62ea
DV		 6382
6383 /* We need to be careful not to changed the adjusted mode, for otherwise
6384 * the hw state checker will get angry at the mismatch. */
6385 crtc_vtotal = adjusted_mode->crtc_vtotal;
6386 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6387
609aeaca 6388 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6389 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6390 crtc_vtotal -= 1;
6391 crtc_vblank_end -= 1;
609aeaca 6392
409ee761 6393 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6394 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6395 else
6396 vsyncshift = adjusted_mode->crtc_hsync_start -
6397 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6398 if (vsyncshift < 0)
6399 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6400 }
6401
6402 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6403 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6404
fe2b8f9d 6405 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6406 (adjusted_mode->crtc_hdisplay - 1) |
6407 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6408 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6409 (adjusted_mode->crtc_hblank_start - 1) |
6410 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6411 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6412 (adjusted_mode->crtc_hsync_start - 1) |
6413 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6414
fe2b8f9d 6415 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6416 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6417 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6418 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6419 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6420 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6421 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6422 (adjusted_mode->crtc_vsync_start - 1) |
6423 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6424
b5e508d4
PZ		 6425 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6426 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6427 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6428 * bits. */
6429 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6430 (pipe == PIPE_B || pipe == PIPE_C))
6431 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6432
b0e77b9c
PZ		 6433 /* pipesrc controls the size that is scaled from, which should
6434 * always be the user's requested size.
6435 */
6436 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6437 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6438 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6439}
6440
1bd1bd80 6441static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6442 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6443{
6444 struct drm_device *dev = crtc->base.dev;
6445 struct drm_i915_private *dev_priv = dev->dev_private;
6446 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6447 uint32_t tmp;
6448
6449 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6450 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6451 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6452 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6453 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6454 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6455 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6456 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6457 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6458
6459 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6460 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6461 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6462 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6463 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6464 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6465 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6466 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6467 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6468
6469 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6470 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6471 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6472 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6473 }
6474
6475 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6476 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6477 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6478
2d112de7
ACO		 6479 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6480 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6481}
6482
f6a83288 6483void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6484 struct intel_crtc_state *pipe_config)
babea61d 6485{
2d112de7
ACO		 6486 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6487 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6488 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6489 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6490
2d112de7
ACO		 6491 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6492 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6493 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6494 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6495
2d112de7 6496 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6497
2d112de7
ACO		 6498 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6499 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6500}
6501
84b046f3
DV		 6502static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6503{
6504 struct drm_device *dev = intel_crtc->base.dev;
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506 uint32_t pipeconf;
6507
9f11a9e4 6508 pipeconf = 0;
84b046f3 6509
b6b5d049
VS		 6510 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6511 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6512 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6513
6e3c9717 6514 if (intel_crtc->config->double_wide)
cf532bb2 6515 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6516
ff9ce46e
DV		 6517 /* only g4x and later have fancy bpc/dither controls */
6518 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6519 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6520 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6521 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6522 PIPECONF_DITHER_TYPE_SP;
84b046f3 6523
6e3c9717 6524 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6525 case 18:
6526 pipeconf |= PIPECONF_6BPC;
6527 break;
6528 case 24:
6529 pipeconf |= PIPECONF_8BPC;
6530 break;
6531 case 30:
6532 pipeconf |= PIPECONF_10BPC;
6533 break;
6534 default:
6535 /* Case prevented by intel_choose_pipe_bpp_dither. */
6536 BUG();
84b046f3
DV		 6537 }
6538 }
6539
6540 if (HAS_PIPE_CXSR(dev)) {
6541 if (intel_crtc->lowfreq_avail) {
6542 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6543 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6544 } else {
6545 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6546 }
6547 }
6548
6e3c9717 6549 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6550 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6551 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6552 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6553 else
6554 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6555 } else
84b046f3
DV		 6556 pipeconf |= PIPECONF_PROGRESSIVE;
6557
6e3c9717 6558 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6559 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6560
84b046f3
DV		 6561 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6562 POSTING_READ(PIPECONF(intel_crtc->pipe));
6563}
6564
190f68c5
ACO		 6565static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6566 struct intel_crtc_state *crtc_state)
79e53945 6567{
c7653199 6568 struct drm_device *dev = crtc->base.dev;
79e53945 6569 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6570 int refclk, num_connectors = 0;
652c393a 6571 intel_clock_t clock, reduced_clock;
a16af721 6572 bool ok, has_reduced_clock = false;
e9fd1c02 6573 bool is_lvds = false, is_dsi = false;
5eddb70b 6574 struct intel_encoder *encoder;
d4906093 6575 const intel_limit_t *limit;
79e53945 6576
d0737e1d
ACO		 6577 for_each_intel_encoder(dev, encoder) {
6578 if (encoder->new_crtc != crtc)
6579 continue;
6580
5eddb70b 6581 switch (encoder->type) {
79e53945
JB		 6582 case INTEL_OUTPUT_LVDS:
6583 is_lvds = true;
6584 break;
e9fd1c02
JN		 6585 case INTEL_OUTPUT_DSI:
6586 is_dsi = true;
6587 break;
6847d71b
PZ		 6588 default:
6589 break;
79e53945 6590 }
43565a06 6591
c751ce4f 6592 num_connectors++;
79e53945
JB		 6593 }
6594
f2335330 6595 if (is_dsi)
5b18e57c 6596 return 0;
f2335330 6597
190f68c5 6598 if (!crtc_state->clock_set) {
409ee761 6599 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 6600
e9fd1c02
JN		 6601 /*
6602 * Returns a set of divisors for the desired target clock with
6603 * the given refclk, or FALSE. The returned values represent
6604 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6605 * 2) / p1 / p2.
6606 */
409ee761 6607 limit = intel_limit(crtc, refclk);
c7653199 6608 ok = dev_priv->display.find_dpll(limit, crtc,
190f68c5 6609 crtc_state->port_clock,
e9fd1c02 6610 refclk, NULL, &clock);
f2335330 6611 if (!ok) {
e9fd1c02
JN		 6612 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6613 return -EINVAL;
6614 }
79e53945 6615
f2335330
JN		 6616 if (is_lvds && dev_priv->lvds_downclock_avail) {
6617 /*
6618 * Ensure we match the reduced clock's P to the target
6619 * clock. If the clocks don't match, we can't switch
6620 * the display clock by using the FP0/FP1. In such case
6621 * we will disable the LVDS downclock feature.
6622 */
6623 has_reduced_clock =
c7653199 6624 dev_priv->display.find_dpll(limit, crtc,
f2335330
JN		 6625 dev_priv->lvds_downclock,
6626 refclk, &clock,
6627 &reduced_clock);
6628 }
6629 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6630 crtc_state->dpll.n = clock.n;
6631 crtc_state->dpll.m1 = clock.m1;
6632 crtc_state->dpll.m2 = clock.m2;
6633 crtc_state->dpll.p1 = clock.p1;
6634 crtc_state->dpll.p2 = clock.p2;
f47709a9 6635 }
7026d4ac 6636
e9fd1c02 6637 if (IS_GEN2(dev)) {
190f68c5 6638 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6639 has_reduced_clock ? &reduced_clock : NULL,
6640 num_connectors);
9d556c99 6641 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6642 chv_update_pll(crtc, crtc_state);
e9fd1c02 6643 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6644 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6645 } else {
190f68c5 6646 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6647 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6648 num_connectors);
e9fd1c02 6649 }
79e53945 6650
c8f7a0db 6651 return 0;
f564048e
EA		 6652}
6653
2fa2fe9a 6654static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6655 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6656{
6657 struct drm_device *dev = crtc->base.dev;
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659 uint32_t tmp;
6660
dc9e7dec
VS		 6661 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6662 return;
6663
2fa2fe9a 6664 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6665 if (!(tmp & PFIT_ENABLE))
6666 return;
2fa2fe9a 6667
06922821 6668 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6669 if (INTEL_INFO(dev)->gen < 4) {
6670 if (crtc->pipe != PIPE_B)
6671 return;
2fa2fe9a
DV		 6672 } else {
6673 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6674 return;
6675 }
6676
06922821 6677 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 6678 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6679 if (INTEL_INFO(dev)->gen < 5)
6680 pipe_config->gmch_pfit.lvds_border_bits =
6681 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6682}
6683
acbec814 6684static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6685 struct intel_crtc_state *pipe_config)
acbec814
JB		 6686{
6687 struct drm_device *dev = crtc->base.dev;
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689 int pipe = pipe_config->cpu_transcoder;
6690 intel_clock_t clock;
6691 u32 mdiv;
662c6ecb 6692 int refclk = 100000;
acbec814 6693
f573de5a
SK		 6694 /* In case of MIPI DPLL will not even be used */
6695 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6696 return;
6697
acbec814 6698 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 6699 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 6700 mutex_unlock(&dev_priv->dpio_lock);
6701
6702 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6703 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6704 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6705 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6706 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6707
f646628b 6708 vlv_clock(refclk, &clock);
acbec814 6709
f646628b
VS		 6710 /* clock.dot is the fast clock */
6711 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 6712}
6713
5724dbd1
DL		 6714static void
6715i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6716 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 6717{
6718 struct drm_device *dev = crtc->base.dev;
6719 struct drm_i915_private *dev_priv = dev->dev_private;
6720 u32 val, base, offset;
6721 int pipe = crtc->pipe, plane = crtc->plane;
6722 int fourcc, pixel_format;
6723 int aligned_height;
b113d5ee 6724 struct drm_framebuffer *fb;
1b842c89 6725 struct intel_framebuffer *intel_fb;
1ad292b5 6726
42a7b088
DL		 6727 val = I915_READ(DSPCNTR(plane));
6728 if (!(val & DISPLAY_PLANE_ENABLE))
6729 return;
6730
d9806c9f 6731 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 6732 if (!intel_fb) {
1ad292b5
JB		 6733 DRM_DEBUG_KMS("failed to alloc fb\n");
6734 return;
6735 }
6736
1b842c89
DL		 6737 fb = &intel_fb->base;
6738
18c5247e
DV		 6739 if (INTEL_INFO(dev)->gen >= 4) {
6740 if (val & DISPPLANE_TILED) {
49af449b 6741 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 6742 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6743 }
6744 }
1ad292b5
JB		 6745
6746 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 6747 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 6748 fb->pixel_format = fourcc;
6749 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 6750
6751 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 6752 if (plane_config->tiling)
1ad292b5
JB		 6753 offset = I915_READ(DSPTILEOFF(plane));
6754 else
6755 offset = I915_READ(DSPLINOFF(plane));
6756 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6757 } else {
6758 base = I915_READ(DSPADDR(plane));
6759 }
6760 plane_config->base = base;
6761
6762 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 6763 fb->width = ((val >> 16) & 0xfff) + 1;
6764 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 6765
6766 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 6767 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 6768
b113d5ee 6769 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 6770 fb->pixel_format,
6771 fb->modifier[0]);
1ad292b5 6772
f37b5c2b 6773 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 6774
2844a921
DL		 6775 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6776 pipe_name(pipe), plane, fb->width, fb->height,
6777 fb->bits_per_pixel, base, fb->pitches[0],
6778 plane_config->size);
1ad292b5 6779
2d14030b 6780 plane_config->fb = intel_fb;
1ad292b5
JB		 6781}
6782
70b23a98 6783static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6784 struct intel_crtc_state *pipe_config)
70b23a98
VS		 6785{
6786 struct drm_device *dev = crtc->base.dev;
6787 struct drm_i915_private *dev_priv = dev->dev_private;
6788 int pipe = pipe_config->cpu_transcoder;
6789 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6790 intel_clock_t clock;
6791 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6792 int refclk = 100000;
6793
6794 mutex_lock(&dev_priv->dpio_lock);
6795 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6796 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6797 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6798 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6799 mutex_unlock(&dev_priv->dpio_lock);
6800
6801 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6802 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6803 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6804 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6805 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6806
6807 chv_clock(refclk, &clock);
6808
6809 /* clock.dot is the fast clock */
6810 pipe_config->port_clock = clock.dot / 5;
6811}
6812
0e8ffe1b 6813static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 6814 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 6815{
6816 struct drm_device *dev = crtc->base.dev;
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 uint32_t tmp;
6819
f458ebbc
DV		 6820 if (!intel_display_power_is_enabled(dev_priv,
6821 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 6822 return false;
6823
e143a21c 6824 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6825 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6826
0e8ffe1b
DV		 6827 tmp = I915_READ(PIPECONF(crtc->pipe));
6828 if (!(tmp & PIPECONF_ENABLE))
6829 return false;
6830
42571aef
VS		 6831 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6832 switch (tmp & PIPECONF_BPC_MASK) {
6833 case PIPECONF_6BPC:
6834 pipe_config->pipe_bpp = 18;
6835 break;
6836 case PIPECONF_8BPC:
6837 pipe_config->pipe_bpp = 24;
6838 break;
6839 case PIPECONF_10BPC:
6840 pipe_config->pipe_bpp = 30;
6841 break;
6842 default:
6843 break;
6844 }
6845 }
6846
b5a9fa09
DV		 6847 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6848 pipe_config->limited_color_range = true;
6849
282740f7
VS		 6850 if (INTEL_INFO(dev)->gen < 4)
6851 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6852
1bd1bd80
DV		 6853 intel_get_pipe_timings(crtc, pipe_config);
6854
2fa2fe9a
DV		 6855 i9xx_get_pfit_config(crtc, pipe_config);
6856
6c49f241
DV		 6857 if (INTEL_INFO(dev)->gen >= 4) {
6858 tmp = I915_READ(DPLL_MD(crtc->pipe));
6859 pipe_config->pixel_multiplier =
6860 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6861 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 6862 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 6863 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6864 tmp = I915_READ(DPLL(crtc->pipe));
6865 pipe_config->pixel_multiplier =
6866 ((tmp & SDVO_MULTIPLIER_MASK)
6867 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6868 } else {
6869 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6870 * port and will be fixed up in the encoder->get_config
6871 * function. */
6872 pipe_config->pixel_multiplier = 1;
6873 }
8bcc2795
DV		 6874 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6875 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 6876 /*
6877 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6878 * on 830. Filter it out here so that we don't
6879 * report errors due to that.
6880 */
6881 if (IS_I830(dev))
6882 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6883
8bcc2795
DV		 6884 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6885 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 6886 } else {
6887 /* Mask out read-only status bits. */
6888 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6889 DPLL_PORTC_READY_MASK |
6890 DPLL_PORTB_READY_MASK);
8bcc2795 6891 }
6c49f241 6892
70b23a98
VS		 6893 if (IS_CHERRYVIEW(dev))
6894 chv_crtc_clock_get(crtc, pipe_config);
6895 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 6896 vlv_crtc_clock_get(crtc, pipe_config);
6897 else
6898 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 6899
0e8ffe1b
DV		 6900 return true;
6901}
6902
dde86e2d 6903static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 6904{
6905 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 6906 struct intel_encoder *encoder;
74cfd7ac 6907 u32 val, final;
13d83a67 6908 bool has_lvds = false;
199e5d79 6909 bool has_cpu_edp = false;
199e5d79 6910 bool has_panel = false;
99eb6a01
KP		 6911 bool has_ck505 = false;
6912 bool can_ssc = false;
13d83a67
JB		 6913
6914 /* We need to take the global config into account */
b2784e15 6915 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 6916 switch (encoder->type) {
6917 case INTEL_OUTPUT_LVDS:
6918 has_panel = true;
6919 has_lvds = true;
6920 break;
6921 case INTEL_OUTPUT_EDP:
6922 has_panel = true;
2de6905f 6923 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 6924 has_cpu_edp = true;
6925 break;
6847d71b
PZ		 6926 default:
6927 break;
13d83a67
JB		 6928 }
6929 }
6930
99eb6a01 6931 if (HAS_PCH_IBX(dev)) {
41aa3448 6932 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 6933 can_ssc = has_ck505;
6934 } else {
6935 has_ck505 = false;
6936 can_ssc = true;
6937 }
6938
2de6905f
ID		 6939 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6940 has_panel, has_lvds, has_ck505);
13d83a67
JB		 6941
6942 /* Ironlake: try to setup display ref clock before DPLL
6943 * enabling. This is only under driver's control after
6944 * PCH B stepping, previous chipset stepping should be
6945 * ignoring this setting.
6946 */
74cfd7ac
CW		 6947 val = I915_READ(PCH_DREF_CONTROL);
6948
6949 /* As we must carefully and slowly disable/enable each source in turn,
6950 * compute the final state we want first and check if we need to
6951 * make any changes at all.
6952 */
6953 final = val;
6954 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6955 if (has_ck505)
6956 final |= DREF_NONSPREAD_CK505_ENABLE;
6957 else
6958 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6959
6960 final &= ~DREF_SSC_SOURCE_MASK;
6961 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6962 final &= ~DREF_SSC1_ENABLE;
6963
6964 if (has_panel) {
6965 final |= DREF_SSC_SOURCE_ENABLE;
6966
6967 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6968 final |= DREF_SSC1_ENABLE;
6969
6970 if (has_cpu_edp) {
6971 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6972 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6973 else
6974 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6975 } else
6976 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6977 } else {
6978 final |= DREF_SSC_SOURCE_DISABLE;
6979 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6980 }
6981
6982 if (final == val)
6983 return;
6984
13d83a67 6985 /* Always enable nonspread source */
74cfd7ac 6986 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 6987
99eb6a01 6988 if (has_ck505)
74cfd7ac 6989 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 6990 else
74cfd7ac 6991 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 6992
199e5d79 6993 if (has_panel) {
74cfd7ac
CW		 6994 val &= ~DREF_SSC_SOURCE_MASK;
6995 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 6996
199e5d79 6997 /* SSC must be turned on before enabling the CPU output */
99eb6a01 6998 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 6999 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7000 val |= DREF_SSC1_ENABLE;
e77166b5 7001 } else
74cfd7ac 7002 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7003
7004 /* Get SSC going before enabling the outputs */
74cfd7ac 7005 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7006 POSTING_READ(PCH_DREF_CONTROL);
7007 udelay(200);
7008
74cfd7ac 7009 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7010
7011 /* Enable CPU source on CPU attached eDP */
199e5d79 7012 if (has_cpu_edp) {
99eb6a01 7013 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7014 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7015 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7016 } else
74cfd7ac 7017 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7018 } else
74cfd7ac 7019 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7020
74cfd7ac 7021 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7022 POSTING_READ(PCH_DREF_CONTROL);
7023 udelay(200);
7024 } else {
7025 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7026
74cfd7ac 7027 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7028
7029 /* Turn off CPU output */
74cfd7ac 7030 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7031
74cfd7ac 7032 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7033 POSTING_READ(PCH_DREF_CONTROL);
7034 udelay(200);
7035
7036 /* Turn off the SSC source */
74cfd7ac
CW		 7037 val &= ~DREF_SSC_SOURCE_MASK;
7038 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7039
7040 /* Turn off SSC1 */
74cfd7ac 7041 val &= ~DREF_SSC1_ENABLE;
199e5d79 7042
74cfd7ac 7043 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7044 POSTING_READ(PCH_DREF_CONTROL);
7045 udelay(200);
7046 }
74cfd7ac
CW		 7047
7048 BUG_ON(val != final);
13d83a67
JB		 7049}
7050
f31f2d55 7051static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7052{
f31f2d55 7053 uint32_t tmp;
dde86e2d 7054
0ff066a9
PZ		 7055 tmp = I915_READ(SOUTH_CHICKEN2);
7056 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7057 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7058
0ff066a9
PZ		 7059 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7060 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7061 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7062
0ff066a9
PZ		 7063 tmp = I915_READ(SOUTH_CHICKEN2);
7064 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7065 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7066
0ff066a9
PZ		 7067 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7068 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7069 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7070}
7071
7072/* WaMPhyProgramming:hsw */
7073static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7074{
7075 uint32_t tmp;
dde86e2d
PZ		 7076
7077 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7078 tmp &= ~(0xFF << 24);
7079 tmp |= (0x12 << 24);
7080 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7081
dde86e2d
PZ		 7082 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7083 tmp |= (1 << 11);
7084 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7085
7086 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7087 tmp |= (1 << 11);
7088 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7089
dde86e2d
PZ		 7090 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7091 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7092 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7093
7094 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7095 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7096 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7097
0ff066a9
PZ		 7098 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7099 tmp &= ~(7 << 13);
7100 tmp |= (5 << 13);
7101 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7102
0ff066a9
PZ		 7103 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7104 tmp &= ~(7 << 13);
7105 tmp |= (5 << 13);
7106 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7107
7108 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7109 tmp &= ~0xFF;
7110 tmp |= 0x1C;
7111 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7112
7113 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7114 tmp &= ~0xFF;
7115 tmp |= 0x1C;
7116 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7117
7118 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7119 tmp &= ~(0xFF << 16);
7120 tmp |= (0x1C << 16);
7121 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7122
7123 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7124 tmp &= ~(0xFF << 16);
7125 tmp |= (0x1C << 16);
7126 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7127
0ff066a9
PZ		 7128 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7129 tmp |= (1 << 27);
7130 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7131
0ff066a9
PZ		 7132 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7133 tmp |= (1 << 27);
7134 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7135
0ff066a9
PZ		 7136 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7137 tmp &= ~(0xF << 28);
7138 tmp |= (4 << 28);
7139 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7140
0ff066a9
PZ		 7141 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7142 tmp &= ~(0xF << 28);
7143 tmp |= (4 << 28);
7144 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7145}
7146
2fa86a1f
PZ		 7147/* Implements 3 different sequences from BSpec chapter "Display iCLK
7148 * Programming" based on the parameters passed:
7149 * - Sequence to enable CLKOUT_DP
7150 * - Sequence to enable CLKOUT_DP without spread
7151 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7152 */
7153static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7154 bool with_fdi)
f31f2d55
PZ		 7155{
7156 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7157 uint32_t reg, tmp;
7158
7159 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7160 with_spread = true;
7161 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7162 with_fdi, "LP PCH doesn't have FDI\n"))
7163 with_fdi = false;
f31f2d55
PZ		 7164
7165 mutex_lock(&dev_priv->dpio_lock);
7166
7167 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7168 tmp &= ~SBI_SSCCTL_DISABLE;
7169 tmp |= SBI_SSCCTL_PATHALT;
7170 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7171
7172 udelay(24);
7173
2fa86a1f
PZ		 7174 if (with_spread) {
7175 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7176 tmp &= ~SBI_SSCCTL_PATHALT;
7177 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7178
2fa86a1f
PZ		 7179 if (with_fdi) {
7180 lpt_reset_fdi_mphy(dev_priv);
7181 lpt_program_fdi_mphy(dev_priv);
7182 }
7183 }
dde86e2d 7184
2fa86a1f
PZ		 7185 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7186 SBI_GEN0 : SBI_DBUFF0;
7187 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7188 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7189 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7190
7191 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7192}
7193
47701c3b
PZ		 7194/* Sequence to disable CLKOUT_DP */
7195static void lpt_disable_clkout_dp(struct drm_device *dev)
7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 uint32_t reg, tmp;
7199
7200 mutex_lock(&dev_priv->dpio_lock);
7201
7202 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7203 SBI_GEN0 : SBI_DBUFF0;
7204 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7205 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7206 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7207
7208 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7209 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7210 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7211 tmp |= SBI_SSCCTL_PATHALT;
7212 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7213 udelay(32);
7214 }
7215 tmp |= SBI_SSCCTL_DISABLE;
7216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7217 }
7218
7219 mutex_unlock(&dev_priv->dpio_lock);
7220}
7221
bf8fa3d3
PZ		 7222static void lpt_init_pch_refclk(struct drm_device *dev)
7223{
bf8fa3d3
PZ		 7224 struct intel_encoder *encoder;
7225 bool has_vga = false;
7226
b2784e15 7227 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7228 switch (encoder->type) {
7229 case INTEL_OUTPUT_ANALOG:
7230 has_vga = true;
7231 break;
6847d71b
PZ		 7232 default:
7233 break;
bf8fa3d3
PZ		 7234 }
7235 }
7236
47701c3b
PZ		 7237 if (has_vga)
7238 lpt_enable_clkout_dp(dev, true, true);
7239 else
7240 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7241}
7242
dde86e2d
PZ		 7243/*
7244 * Initialize reference clocks when the driver loads
7245 */
7246void intel_init_pch_refclk(struct drm_device *dev)
7247{
7248 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7249 ironlake_init_pch_refclk(dev);
7250 else if (HAS_PCH_LPT(dev))
7251 lpt_init_pch_refclk(dev);
7252}
7253
d9d444cb
JB		 7254static int ironlake_get_refclk(struct drm_crtc *crtc)
7255{
7256 struct drm_device *dev = crtc->dev;
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 struct intel_encoder *encoder;
d9d444cb
JB		 7259 int num_connectors = 0;
7260 bool is_lvds = false;
7261
d0737e1d
ACO		 7262 for_each_intel_encoder(dev, encoder) {
7263 if (encoder->new_crtc != to_intel_crtc(crtc))
7264 continue;
7265
d9d444cb
JB		 7266 switch (encoder->type) {
7267 case INTEL_OUTPUT_LVDS:
7268 is_lvds = true;
7269 break;
6847d71b
PZ		 7270 default:
7271 break;
d9d444cb
JB		 7272 }
7273 num_connectors++;
7274 }
7275
7276 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7277 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7278 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7279 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7280 }
7281
7282 return 120000;
7283}
7284
6ff93609 7285static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7286{
c8203565 7287 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7289 int pipe = intel_crtc->pipe;
c8203565
PZ		 7290 uint32_t val;
7291
78114071 7292 val = 0;
c8203565 7293
6e3c9717 7294 switch (intel_crtc->config->pipe_bpp) {
c8203565 7295 case 18:
dfd07d72 7296 val |= PIPECONF_6BPC;
c8203565
PZ		 7297 break;
7298 case 24:
dfd07d72 7299 val |= PIPECONF_8BPC;
c8203565
PZ		 7300 break;
7301 case 30:
dfd07d72 7302 val |= PIPECONF_10BPC;
c8203565
PZ		 7303 break;
7304 case 36:
dfd07d72 7305 val |= PIPECONF_12BPC;
c8203565
PZ		 7306 break;
7307 default:
cc769b62
PZ		 7308 /* Case prevented by intel_choose_pipe_bpp_dither. */
7309 BUG();
c8203565
PZ		 7310 }
7311
6e3c9717 7312 if (intel_crtc->config->dither)
c8203565
PZ		 7313 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7314
6e3c9717 7315 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7316 val |= PIPECONF_INTERLACED_ILK;
7317 else
7318 val |= PIPECONF_PROGRESSIVE;
7319
6e3c9717 7320 if (intel_crtc->config->limited_color_range)
3685a8f3 7321 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7322
c8203565
PZ		 7323 I915_WRITE(PIPECONF(pipe), val);
7324 POSTING_READ(PIPECONF(pipe));
7325}
7326
86d3efce
VS		 7327/*
7328 * Set up the pipe CSC unit.
7329 *
7330 * Currently only full range RGB to limited range RGB conversion
7331 * is supported, but eventually this should handle various
7332 * RGB<->YCbCr scenarios as well.
7333 */
50f3b016 7334static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7335{
7336 struct drm_device *dev = crtc->dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7339 int pipe = intel_crtc->pipe;
7340 uint16_t coeff = 0x7800; /* 1.0 */
7341
7342 /*
7343 * TODO: Check what kind of values actually come out of the pipe
7344 * with these coeff/postoff values and adjust to get the best
7345 * accuracy. Perhaps we even need to take the bpc value into
7346 * consideration.
7347 */
7348
6e3c9717 7349 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7350 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7351
7352 /*
7353 * GY/GU and RY/RU should be the other way around according
7354 * to BSpec, but reality doesn't agree. Just set them up in
7355 * a way that results in the correct picture.
7356 */
7357 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7358 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7359
7360 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7361 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7362
7363 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7364 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7365
7366 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7367 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7368 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7369
7370 if (INTEL_INFO(dev)->gen > 6) {
7371 uint16_t postoff = 0;
7372
6e3c9717 7373 if (intel_crtc->config->limited_color_range)
32cf0cb0 7374 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7375
7376 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7377 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7378 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7379
7380 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7381 } else {
7382 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7383
6e3c9717 7384 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7385 mode |= CSC_BLACK_SCREEN_OFFSET;
7386
7387 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7388 }
7389}
7390
6ff93609 7391static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7392{
756f85cf
PZ		 7393 struct drm_device *dev = crtc->dev;
7394 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7396 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7397 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7398 uint32_t val;
7399
3eff4faa 7400 val = 0;
ee2b0b38 7401
6e3c9717 7402 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7403 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7404
6e3c9717 7405 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7406 val |= PIPECONF_INTERLACED_ILK;
7407 else
7408 val |= PIPECONF_PROGRESSIVE;
7409
702e7a56
PZ		 7410 I915_WRITE(PIPECONF(cpu_transcoder), val);
7411 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7412
7413 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7414 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7415
3cdf122c 7416 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7417 val = 0;
7418
6e3c9717 7419 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7420 case 18:
7421 val |= PIPEMISC_DITHER_6_BPC;
7422 break;
7423 case 24:
7424 val |= PIPEMISC_DITHER_8_BPC;
7425 break;
7426 case 30:
7427 val |= PIPEMISC_DITHER_10_BPC;
7428 break;
7429 case 36:
7430 val |= PIPEMISC_DITHER_12_BPC;
7431 break;
7432 default:
7433 /* Case prevented by pipe_config_set_bpp. */
7434 BUG();
7435 }
7436
6e3c9717 7437 if (intel_crtc->config->dither)
756f85cf
PZ		 7438 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7439
7440 I915_WRITE(PIPEMISC(pipe), val);
7441 }
ee2b0b38
PZ		 7442}
7443
6591c6e4 7444static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7445 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7446 intel_clock_t *clock,
7447 bool *has_reduced_clock,
7448 intel_clock_t *reduced_clock)
7449{
7450 struct drm_device *dev = crtc->dev;
7451 struct drm_i915_private *dev_priv = dev->dev_private;
a919ff14 7452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591c6e4 7453 int refclk;
d4906093 7454 const intel_limit_t *limit;
a16af721 7455 bool ret, is_lvds = false;
79e53945 7456
d0737e1d 7457 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
79e53945 7458
d9d444cb 7459 refclk = ironlake_get_refclk(crtc);
79e53945 7460
d4906093
ML		 7461 /*
7462 * Returns a set of divisors for the desired target clock with the given
7463 * refclk, or FALSE. The returned values represent the clock equation:
7464 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7465 */
409ee761 7466 limit = intel_limit(intel_crtc, refclk);
a919ff14 7467 ret = dev_priv->display.find_dpll(limit, intel_crtc,
190f68c5 7468 crtc_state->port_clock,
ee9300bb 7469 refclk, NULL, clock);
6591c6e4
PZ		 7470 if (!ret)
7471 return false;
cda4b7d3 7472
ddc9003c 7473 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7474 /*
7475 * Ensure we match the reduced clock's P to the target clock.
7476 * If the clocks don't match, we can't switch the display clock
7477 * by using the FP0/FP1. In such case we will disable the LVDS
7478 * downclock feature.
7479 */
ee9300bb 7480 *has_reduced_clock =
a919ff14 7481 dev_priv->display.find_dpll(limit, intel_crtc,
ee9300bb
DV		 7482 dev_priv->lvds_downclock,
7483 refclk, clock,
7484 reduced_clock);
652c393a 7485 }
61e9653f 7486
6591c6e4
PZ		 7487 return true;
7488}
7489
d4b1931c
PZ		 7490int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7491{
7492 /*
7493 * Account for spread spectrum to avoid
7494 * oversubscribing the link. Max center spread
7495 * is 2.5%; use 5% for safety's sake.
7496 */
7497 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7498 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7499}
7500
7429e9d4 7501static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7502{
7429e9d4 7503 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7504}
7505
de13a2e3 7506static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7507 struct intel_crtc_state *crtc_state,
7429e9d4 7508 u32 *fp,
9a7c7890 7509 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7510{
de13a2e3 7511 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7512 struct drm_device *dev = crtc->dev;
7513 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 7514 struct intel_encoder *intel_encoder;
7515 uint32_t dpll;
6cc5f341 7516 int factor, num_connectors = 0;
09ede541 7517 bool is_lvds = false, is_sdvo = false;
79e53945 7518
d0737e1d
ACO		 7519 for_each_intel_encoder(dev, intel_encoder) {
7520 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7521 continue;
7522
de13a2e3 7523 switch (intel_encoder->type) {
79e53945
JB		 7524 case INTEL_OUTPUT_LVDS:
7525 is_lvds = true;
7526 break;
7527 case INTEL_OUTPUT_SDVO:
7d57382e 7528 case INTEL_OUTPUT_HDMI:
79e53945 7529 is_sdvo = true;
79e53945 7530 break;
6847d71b
PZ		 7531 default:
7532 break;
79e53945 7533 }
43565a06 7534
c751ce4f 7535 num_connectors++;
79e53945 7536 }
79e53945 7537
c1858123 7538 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7539 factor = 21;
7540 if (is_lvds) {
7541 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7542 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7543 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7544 factor = 25;
190f68c5 7545 } else if (crtc_state->sdvo_tv_clock)
8febb297 7546 factor = 20;
c1858123 7547
190f68c5 7548 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7549 *fp |= FP_CB_TUNE;
2c07245f 7550
9a7c7890
DV		 7551 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7552 *fp2 |= FP_CB_TUNE;
7553
5eddb70b 7554 dpll = 0;
2c07245f 7555
a07d6787
EA		 7556 if (is_lvds)
7557 dpll |= DPLLB_MODE_LVDS;
7558 else
7559 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7560
190f68c5 7561 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7562 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7563
7564 if (is_sdvo)
4a33e48d 7565 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7566 if (crtc_state->has_dp_encoder)
4a33e48d 7567 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7568
a07d6787 7569 /* compute bitmask from p1 value */
190f68c5 7570 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7571 /* also FPA1 */
190f68c5 7572 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7573
190f68c5 7574 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7575 case 5:
7576 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7577 break;
7578 case 7:
7579 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7580 break;
7581 case 10:
7582 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7583 break;
7584 case 14:
7585 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7586 break;
79e53945
JB		 7587 }
7588
b4c09f3b 7589 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7591 else
7592 dpll |= PLL_REF_INPUT_DREFCLK;
7593
959e16d6 7594 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7595}
7596
190f68c5
ACO		 7597static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7598 struct intel_crtc_state *crtc_state)
de13a2e3 7599{
c7653199 7600 struct drm_device *dev = crtc->base.dev;
de13a2e3 7601 intel_clock_t clock, reduced_clock;
cbbab5bd 7602 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7603 bool ok, has_reduced_clock = false;
8b47047b 7604 bool is_lvds = false;
e2b78267 7605 struct intel_shared_dpll *pll;
de13a2e3 7606
409ee761 7607 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7608
5dc5298b
PZ		 7609 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7610 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7611
190f68c5 7612 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7613 &has_reduced_clock, &reduced_clock);
190f68c5 7614 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7615 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7616 return -EINVAL;
79e53945 7617 }
f47709a9 7618 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7619 if (!crtc_state->clock_set) {
7620 crtc_state->dpll.n = clock.n;
7621 crtc_state->dpll.m1 = clock.m1;
7622 crtc_state->dpll.m2 = clock.m2;
7623 crtc_state->dpll.p1 = clock.p1;
7624 crtc_state->dpll.p2 = clock.p2;
f47709a9 7625 }
79e53945 7626
5dc5298b 7627 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7628 if (crtc_state->has_pch_encoder) {
7629 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7630 if (has_reduced_clock)
7429e9d4 7631 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7632
190f68c5 7633 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7634 &fp, &reduced_clock,
7635 has_reduced_clock ? &fp2 : NULL);
7636
190f68c5
ACO		 7637 crtc_state->dpll_hw_state.dpll = dpll;
7638 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7639 if (has_reduced_clock)
190f68c5 7640 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7641 else
190f68c5 7642 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7643
190f68c5 7644 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7645 if (pll == NULL) {
84f44ce7 7646 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7647 pipe_name(crtc->pipe));
4b645f14
JB		 7648 return -EINVAL;
7649 }
3fb37703 7650 }
79e53945 7651
d330a953 7652 if (is_lvds && has_reduced_clock && i915.powersave)
c7653199 7653 crtc->lowfreq_avail = true;
bcd644e0 7654 else
c7653199 7655 crtc->lowfreq_avail = false;
e2b78267 7656
c8f7a0db 7657 return 0;
79e53945
JB		 7658}
7659
eb14cb74
VS		 7660static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7661 struct intel_link_m_n *m_n)
7662{
7663 struct drm_device *dev = crtc->base.dev;
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665 enum pipe pipe = crtc->pipe;
7666
7667 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7668 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7669 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7670 & ~TU_SIZE_MASK;
7671 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7672 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7673 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7674}
7675
7676static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7677 enum transcoder transcoder,
b95af8be
VK		 7678 struct intel_link_m_n *m_n,
7679 struct intel_link_m_n *m2_n2)
72419203
DV		 7680{
7681 struct drm_device *dev = crtc->base.dev;
7682 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 7683 enum pipe pipe = crtc->pipe;
72419203 7684
eb14cb74
VS		 7685 if (INTEL_INFO(dev)->gen >= 5) {
7686 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7687 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7688 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7689 & ~TU_SIZE_MASK;
7690 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7691 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7692 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 7693 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7694 * gen < 8) and if DRRS is supported (to make sure the
7695 * registers are not unnecessarily read).
7696 */
7697 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 7698 crtc->config->has_drrs) {
b95af8be
VK		 7699 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7700 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7701 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7702 & ~TU_SIZE_MASK;
7703 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7704 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7705 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7706 }
eb14cb74
VS		 7707 } else {
7708 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7709 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7710 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7711 & ~TU_SIZE_MASK;
7712 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7713 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7714 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7715 }
7716}
7717
7718void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 7719 struct intel_crtc_state *pipe_config)
eb14cb74 7720{
681a8504 7721 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 7722 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7723 else
7724 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 7725 &pipe_config->dp_m_n,
7726 &pipe_config->dp_m2_n2);
eb14cb74 7727}
72419203 7728
eb14cb74 7729static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 7730 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 7731{
7732 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 7733 &pipe_config->fdi_m_n, NULL);
72419203
DV		 7734}
7735
bd2e244f 7736static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7737 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 7738{
7739 struct drm_device *dev = crtc->base.dev;
7740 struct drm_i915_private *dev_priv = dev->dev_private;
7741 uint32_t tmp;
7742
7743 tmp = I915_READ(PS_CTL(crtc->pipe));
7744
7745 if (tmp & PS_ENABLE) {
7746 pipe_config->pch_pfit.enabled = true;
7747 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7748 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7749 }
7750}
7751
5724dbd1
DL		 7752static void
7753skylake_get_initial_plane_config(struct intel_crtc *crtc,
7754 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 7755{
7756 struct drm_device *dev = crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 7758 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 7759 int pipe = crtc->pipe;
7760 int fourcc, pixel_format;
7761 int aligned_height;
7762 struct drm_framebuffer *fb;
1b842c89 7763 struct intel_framebuffer *intel_fb;
bc8d7dff 7764
d9806c9f 7765 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7766 if (!intel_fb) {
bc8d7dff
DL		 7767 DRM_DEBUG_KMS("failed to alloc fb\n");
7768 return;
7769 }
7770
1b842c89
DL		 7771 fb = &intel_fb->base;
7772
bc8d7dff 7773 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 7774 if (!(val & PLANE_CTL_ENABLE))
7775 goto error;
7776
bc8d7dff
DL		 7777 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7778 fourcc = skl_format_to_fourcc(pixel_format,
7779 val & PLANE_CTL_ORDER_RGBX,
7780 val & PLANE_CTL_ALPHA_MASK);
7781 fb->pixel_format = fourcc;
7782 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7783
40f46283
DL		 7784 tiling = val & PLANE_CTL_TILED_MASK;
7785 switch (tiling) {
7786 case PLANE_CTL_TILED_LINEAR:
7787 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7788 break;
7789 case PLANE_CTL_TILED_X:
7790 plane_config->tiling = I915_TILING_X;
7791 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7792 break;
7793 case PLANE_CTL_TILED_Y:
7794 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7795 break;
7796 case PLANE_CTL_TILED_YF:
7797 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7798 break;
7799 default:
7800 MISSING_CASE(tiling);
7801 goto error;
7802 }
7803
bc8d7dff
DL		 7804 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7805 plane_config->base = base;
7806
7807 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7808
7809 val = I915_READ(PLANE_SIZE(pipe, 0));
7810 fb->height = ((val >> 16) & 0xfff) + 1;
7811 fb->width = ((val >> 0) & 0x1fff) + 1;
7812
7813 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 7814 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7815 fb->pixel_format);
bc8d7dff
DL		 7816 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7817
7818 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7819 fb->pixel_format,
7820 fb->modifier[0]);
bc8d7dff 7821
f37b5c2b 7822 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 7823
7824 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7825 pipe_name(pipe), fb->width, fb->height,
7826 fb->bits_per_pixel, base, fb->pitches[0],
7827 plane_config->size);
7828
2d14030b 7829 plane_config->fb = intel_fb;
bc8d7dff
DL		 7830 return;
7831
7832error:
7833 kfree(fb);
7834}
7835
2fa2fe9a 7836static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7837 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7838{
7839 struct drm_device *dev = crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 uint32_t tmp;
7842
7843 tmp = I915_READ(PF_CTL(crtc->pipe));
7844
7845 if (tmp & PF_ENABLE) {
fd4daa9c 7846 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 7847 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7848 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 7849
7850 /* We currently do not free assignements of panel fitters on
7851 * ivb/hsw (since we don't use the higher upscaling modes which
7852 * differentiates them) so just WARN about this case for now. */
7853 if (IS_GEN7(dev)) {
7854 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7855 PF_PIPE_SEL_IVB(crtc->pipe));
7856 }
2fa2fe9a 7857 }
79e53945
JB		 7858}
7859
5724dbd1
DL		 7860static void
7861ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7862 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 7863{
7864 struct drm_device *dev = crtc->base.dev;
7865 struct drm_i915_private *dev_priv = dev->dev_private;
7866 u32 val, base, offset;
aeee5a49 7867 int pipe = crtc->pipe;
4c6baa59
JB		 7868 int fourcc, pixel_format;
7869 int aligned_height;
b113d5ee 7870 struct drm_framebuffer *fb;
1b842c89 7871 struct intel_framebuffer *intel_fb;
4c6baa59 7872
42a7b088
DL		 7873 val = I915_READ(DSPCNTR(pipe));
7874 if (!(val & DISPLAY_PLANE_ENABLE))
7875 return;
7876
d9806c9f 7877 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7878 if (!intel_fb) {
4c6baa59
JB		 7879 DRM_DEBUG_KMS("failed to alloc fb\n");
7880 return;
7881 }
7882
1b842c89
DL		 7883 fb = &intel_fb->base;
7884
18c5247e
DV		 7885 if (INTEL_INFO(dev)->gen >= 4) {
7886 if (val & DISPPLANE_TILED) {
49af449b 7887 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7888 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7889 }
7890 }
4c6baa59
JB		 7891
7892 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7893 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7894 fb->pixel_format = fourcc;
7895 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 7896
aeee5a49 7897 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 7898 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 7899 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 7900 } else {
49af449b 7901 if (plane_config->tiling)
aeee5a49 7902 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 7903 else
aeee5a49 7904 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 7905 }
7906 plane_config->base = base;
7907
7908 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7909 fb->width = ((val >> 16) & 0xfff) + 1;
7910 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 7911
7912 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7913 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 7914
b113d5ee 7915 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7916 fb->pixel_format,
7917 fb->modifier[0]);
4c6baa59 7918
f37b5c2b 7919 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 7920
2844a921
DL		 7921 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7922 pipe_name(pipe), fb->width, fb->height,
7923 fb->bits_per_pixel, base, fb->pitches[0],
7924 plane_config->size);
b113d5ee 7925
2d14030b 7926 plane_config->fb = intel_fb;
4c6baa59
JB		 7927}
7928
0e8ffe1b 7929static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7930 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7931{
7932 struct drm_device *dev = crtc->base.dev;
7933 struct drm_i915_private *dev_priv = dev->dev_private;
7934 uint32_t tmp;
7935
f458ebbc
DV		 7936 if (!intel_display_power_is_enabled(dev_priv,
7937 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 7938 return false;
7939
e143a21c 7940 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7941 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7942
0e8ffe1b
DV		 7943 tmp = I915_READ(PIPECONF(crtc->pipe));
7944 if (!(tmp & PIPECONF_ENABLE))
7945 return false;
7946
42571aef
VS		 7947 switch (tmp & PIPECONF_BPC_MASK) {
7948 case PIPECONF_6BPC:
7949 pipe_config->pipe_bpp = 18;
7950 break;
7951 case PIPECONF_8BPC:
7952 pipe_config->pipe_bpp = 24;
7953 break;
7954 case PIPECONF_10BPC:
7955 pipe_config->pipe_bpp = 30;
7956 break;
7957 case PIPECONF_12BPC:
7958 pipe_config->pipe_bpp = 36;
7959 break;
7960 default:
7961 break;
7962 }
7963
b5a9fa09
DV		 7964 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7965 pipe_config->limited_color_range = true;
7966
ab9412ba 7967 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 7968 struct intel_shared_dpll *pll;
7969
88adfff1
DV		 7970 pipe_config->has_pch_encoder = true;
7971
627eb5a3
DV		 7972 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7973 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7974 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 7975
7976 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 7977
c0d43d62 7978 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 7979 pipe_config->shared_dpll =
7980 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 7981 } else {
7982 tmp = I915_READ(PCH_DPLL_SEL);
7983 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7984 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7985 else
7986 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7987 }
66e985c0
DV		 7988
7989 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7990
7991 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7992 &pipe_config->dpll_hw_state));
c93f54cf
DV		 7993
7994 tmp = pipe_config->dpll_hw_state.dpll;
7995 pipe_config->pixel_multiplier =
7996 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7997 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 7998
7999 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8000 } else {
8001 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8002 }
8003
1bd1bd80
DV		 8004 intel_get_pipe_timings(crtc, pipe_config);
8005
2fa2fe9a
DV		 8006 ironlake_get_pfit_config(crtc, pipe_config);
8007
0e8ffe1b
DV		 8008 return true;
8009}
8010
be256dc7
PZ		 8011static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8012{
8013 struct drm_device *dev = dev_priv->dev;
be256dc7 8014 struct intel_crtc *crtc;
be256dc7 8015
d3fcc808 8016 for_each_intel_crtc(dev, crtc)
e2c719b7 8017 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8018 pipe_name(crtc->pipe));
8019
e2c719b7
RC		 8020 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8021 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8022 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8023 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8024 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8025 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8026 "CPU PWM1 enabled\n");
c5107b87 8027 if (IS_HASWELL(dev))
e2c719b7 8028 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8029 "CPU PWM2 enabled\n");
e2c719b7 8030 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8031 "PCH PWM1 enabled\n");
e2c719b7 8032 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8033 "Utility pin enabled\n");
e2c719b7 8034 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8035
9926ada1
PZ		 8036 /*
8037 * In theory we can still leave IRQs enabled, as long as only the HPD
8038 * interrupts remain enabled. We used to check for that, but since it's
8039 * gen-specific and since we only disable LCPLL after we fully disable
8040 * the interrupts, the check below should be enough.
8041 */
e2c719b7 8042 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8043}
8044
9ccd5aeb
PZ		 8045static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8046{
8047 struct drm_device *dev = dev_priv->dev;
8048
8049 if (IS_HASWELL(dev))
8050 return I915_READ(D_COMP_HSW);
8051 else
8052 return I915_READ(D_COMP_BDW);
8053}
8054
3c4c9b81
PZ		 8055static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8056{
8057 struct drm_device *dev = dev_priv->dev;
8058
8059 if (IS_HASWELL(dev)) {
8060 mutex_lock(&dev_priv->rps.hw_lock);
8061 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8062 val))
f475dadf 8063 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8064 mutex_unlock(&dev_priv->rps.hw_lock);
8065 } else {
9ccd5aeb
PZ		 8066 I915_WRITE(D_COMP_BDW, val);
8067 POSTING_READ(D_COMP_BDW);
3c4c9b81 8068 }
be256dc7
PZ		 8069}
8070
8071/*
8072 * This function implements pieces of two sequences from BSpec:
8073 * - Sequence for display software to disable LCPLL
8074 * - Sequence for display software to allow package C8+
8075 * The steps implemented here are just the steps that actually touch the LCPLL
8076 * register. Callers should take care of disabling all the display engine
8077 * functions, doing the mode unset, fixing interrupts, etc.
8078 */
6ff58d53
PZ		 8079static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8080 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8081{
8082 uint32_t val;
8083
8084 assert_can_disable_lcpll(dev_priv);
8085
8086 val = I915_READ(LCPLL_CTL);
8087
8088 if (switch_to_fclk) {
8089 val |= LCPLL_CD_SOURCE_FCLK;
8090 I915_WRITE(LCPLL_CTL, val);
8091
8092 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8093 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8094 DRM_ERROR("Switching to FCLK failed\n");
8095
8096 val = I915_READ(LCPLL_CTL);
8097 }
8098
8099 val |= LCPLL_PLL_DISABLE;
8100 I915_WRITE(LCPLL_CTL, val);
8101 POSTING_READ(LCPLL_CTL);
8102
8103 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8104 DRM_ERROR("LCPLL still locked\n");
8105
9ccd5aeb 8106 val = hsw_read_dcomp(dev_priv);
be256dc7 8107 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8108 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8109 ndelay(100);
8110
9ccd5aeb
PZ		 8111 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8112 1))
be256dc7
PZ		 8113 DRM_ERROR("D_COMP RCOMP still in progress\n");
8114
8115 if (allow_power_down) {
8116 val = I915_READ(LCPLL_CTL);
8117 val |= LCPLL_POWER_DOWN_ALLOW;
8118 I915_WRITE(LCPLL_CTL, val);
8119 POSTING_READ(LCPLL_CTL);
8120 }
8121}
8122
8123/*
8124 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8125 * source.
8126 */
6ff58d53 8127static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8128{
8129 uint32_t val;
8130
8131 val = I915_READ(LCPLL_CTL);
8132
8133 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8134 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8135 return;
8136
a8a8bd54
PZ		 8137 /*
8138 * Make sure we're not on PC8 state before disabling PC8, otherwise
8139 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8140 */
59bad947 8141 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8142
be256dc7
PZ		 8143 if (val & LCPLL_POWER_DOWN_ALLOW) {
8144 val &= ~LCPLL_POWER_DOWN_ALLOW;
8145 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8146 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8147 }
8148
9ccd5aeb 8149 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8150 val |= D_COMP_COMP_FORCE;
8151 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8152 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8153
8154 val = I915_READ(LCPLL_CTL);
8155 val &= ~LCPLL_PLL_DISABLE;
8156 I915_WRITE(LCPLL_CTL, val);
8157
8158 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8159 DRM_ERROR("LCPLL not locked yet\n");
8160
8161 if (val & LCPLL_CD_SOURCE_FCLK) {
8162 val = I915_READ(LCPLL_CTL);
8163 val &= ~LCPLL_CD_SOURCE_FCLK;
8164 I915_WRITE(LCPLL_CTL, val);
8165
8166 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8167 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8168 DRM_ERROR("Switching back to LCPLL failed\n");
8169 }
215733fa 8170
59bad947 8171 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8172}
8173
765dab67
PZ		 8174/*
8175 * Package states C8 and deeper are really deep PC states that can only be
8176 * reached when all the devices on the system allow it, so even if the graphics
8177 * device allows PC8+, it doesn't mean the system will actually get to these
8178 * states. Our driver only allows PC8+ when going into runtime PM.
8179 *
8180 * The requirements for PC8+ are that all the outputs are disabled, the power
8181 * well is disabled and most interrupts are disabled, and these are also
8182 * requirements for runtime PM. When these conditions are met, we manually do
8183 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8184 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8185 * hang the machine.
8186 *
8187 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8188 * the state of some registers, so when we come back from PC8+ we need to
8189 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8190 * need to take care of the registers kept by RC6. Notice that this happens even
8191 * if we don't put the device in PCI D3 state (which is what currently happens
8192 * because of the runtime PM support).
8193 *
8194 * For more, read "Display Sequences for Package C8" on the hardware
8195 * documentation.
8196 */
a14cb6fc 8197void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8198{
c67a470b
PZ		 8199 struct drm_device *dev = dev_priv->dev;
8200 uint32_t val;
8201
c67a470b
PZ		 8202 DRM_DEBUG_KMS("Enabling package C8+\n");
8203
c67a470b
PZ		 8204 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8205 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8206 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8207 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8208 }
8209
8210 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8211 hsw_disable_lcpll(dev_priv, true, true);
8212}
8213
a14cb6fc 8214void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8215{
8216 struct drm_device *dev = dev_priv->dev;
8217 uint32_t val;
8218
c67a470b
PZ		 8219 DRM_DEBUG_KMS("Disabling package C8+\n");
8220
8221 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8222 lpt_init_pch_refclk(dev);
8223
8224 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8225 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8226 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8227 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8228 }
8229
8230 intel_prepare_ddi(dev);
c67a470b
PZ		 8231}
8232
190f68c5
ACO		 8233static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8234 struct intel_crtc_state *crtc_state)
09b4ddf9 8235{
190f68c5 8236 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8237 return -EINVAL;
716c2e55 8238
c7653199 8239 crtc->lowfreq_avail = false;
644cef34 8240
c8f7a0db 8241 return 0;
79e53945
JB		 8242}
8243
96b7dfb7
S		 8244static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8245 enum port port,
5cec258b 8246 struct intel_crtc_state *pipe_config)
96b7dfb7 8247{
3148ade7 8248 u32 temp, dpll_ctl1;
96b7dfb7
S		 8249
8250 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8251 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8252
8253 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8254 case SKL_DPLL0:
8255 /*
8256 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8257 * of the shared DPLL framework and thus needs to be read out
8258 * separately
8259 */
8260 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8261 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8262 break;
96b7dfb7
S		 8263 case SKL_DPLL1:
8264 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8265 break;
8266 case SKL_DPLL2:
8267 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8268 break;
8269 case SKL_DPLL3:
8270 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8271 break;
96b7dfb7
S		 8272 }
8273}
8274
7d2c8175
DL		 8275static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8276 enum port port,
5cec258b 8277 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8278{
8279 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8280
8281 switch (pipe_config->ddi_pll_sel) {
8282 case PORT_CLK_SEL_WRPLL1:
8283 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8284 break;
8285 case PORT_CLK_SEL_WRPLL2:
8286 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8287 break;
8288 }
8289}
8290
26804afd 8291static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8292 struct intel_crtc_state *pipe_config)
26804afd
DV		 8293{
8294 struct drm_device *dev = crtc->base.dev;
8295 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8296 struct intel_shared_dpll *pll;
26804afd
DV		 8297 enum port port;
8298 uint32_t tmp;
8299
8300 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8301
8302 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8303
96b7dfb7
S		 8304 if (IS_SKYLAKE(dev))
8305 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8306 else
8307 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8308
d452c5b6
DV		 8309 if (pipe_config->shared_dpll >= 0) {
8310 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8311
8312 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8313 &pipe_config->dpll_hw_state));
8314 }
8315
26804afd
DV		 8316 /*
8317 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8318 * DDI E. So just check whether this pipe is wired to DDI E and whether
8319 * the PCH transcoder is on.
8320 */
ca370455
DL		 8321 if (INTEL_INFO(dev)->gen < 9 &&
8322 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8323 pipe_config->has_pch_encoder = true;
8324
8325 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8326 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8327 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8328
8329 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8330 }
8331}
8332
0e8ffe1b 8333static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8334 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8335{
8336 struct drm_device *dev = crtc->base.dev;
8337 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8338 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8339 uint32_t tmp;
8340
f458ebbc 8341 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8342 POWER_DOMAIN_PIPE(crtc->pipe)))
8343 return false;
8344
e143a21c 8345 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8346 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8347
eccb140b
DV		 8348 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8349 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8350 enum pipe trans_edp_pipe;
8351 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8352 default:
8353 WARN(1, "unknown pipe linked to edp transcoder\n");
8354 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8355 case TRANS_DDI_EDP_INPUT_A_ON:
8356 trans_edp_pipe = PIPE_A;
8357 break;
8358 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8359 trans_edp_pipe = PIPE_B;
8360 break;
8361 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8362 trans_edp_pipe = PIPE_C;
8363 break;
8364 }
8365
8366 if (trans_edp_pipe == crtc->pipe)
8367 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8368 }
8369
f458ebbc 8370 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8371 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8372 return false;
8373
eccb140b 8374 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8375 if (!(tmp & PIPECONF_ENABLE))
8376 return false;
8377
26804afd 8378 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8379
1bd1bd80
DV		 8380 intel_get_pipe_timings(crtc, pipe_config);
8381
2fa2fe9a 8382 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8383 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8384 if (IS_SKYLAKE(dev))
8385 skylake_get_pfit_config(crtc, pipe_config);
8386 else
8387 ironlake_get_pfit_config(crtc, pipe_config);
8388 }
88adfff1 8389
e59150dc
JB		 8390 if (IS_HASWELL(dev))
8391 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8392 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8393
ebb69c95
CT		 8394 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8395 pipe_config->pixel_multiplier =
8396 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8397 } else {
8398 pipe_config->pixel_multiplier = 1;
8399 }
6c49f241 8400
0e8ffe1b
DV		 8401 return true;
8402}
8403
560b85bb
CW		 8404static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8405{
8406 struct drm_device *dev = crtc->dev;
8407 struct drm_i915_private *dev_priv = dev->dev_private;
8408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8409 uint32_t cntl = 0, size = 0;
560b85bb 8410
dc41c154 8411 if (base) {
3dd512fb
MR		 8412 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8413 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8414 unsigned int stride = roundup_pow_of_two(width) * 4;
8415
8416 switch (stride) {
8417 default:
8418 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8419 width, stride);
8420 stride = 256;
8421 /* fallthrough */
8422 case 256:
8423 case 512:
8424 case 1024:
8425 case 2048:
8426 break;
4b0e333e
CW		 8427 }
8428
dc41c154
VS		 8429 cntl |= CURSOR_ENABLE |
8430 CURSOR_GAMMA_ENABLE |
8431 CURSOR_FORMAT_ARGB |
8432 CURSOR_STRIDE(stride);
8433
8434 size = (height << 12) | width;
4b0e333e 8435 }
560b85bb 8436
dc41c154
VS		 8437 if (intel_crtc->cursor_cntl != 0 &&
8438 (intel_crtc->cursor_base != base ||
8439 intel_crtc->cursor_size != size ||
8440 intel_crtc->cursor_cntl != cntl)) {
8441 /* On these chipsets we can only modify the base/size/stride
8442 * whilst the cursor is disabled.
8443 */
8444 I915_WRITE(_CURACNTR, 0);
4b0e333e 8445 POSTING_READ(_CURACNTR);
dc41c154 8446 intel_crtc->cursor_cntl = 0;
4b0e333e 8447 }
560b85bb 8448
99d1f387 8449 if (intel_crtc->cursor_base != base) {
9db4a9c7 8450 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8451 intel_crtc->cursor_base = base;
8452 }
4726e0b0 8453
dc41c154
VS		 8454 if (intel_crtc->cursor_size != size) {
8455 I915_WRITE(CURSIZE, size);
8456 intel_crtc->cursor_size = size;
4b0e333e 8457 }
560b85bb 8458
4b0e333e 8459 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8460 I915_WRITE(_CURACNTR, cntl);
8461 POSTING_READ(_CURACNTR);
4b0e333e 8462 intel_crtc->cursor_cntl = cntl;
560b85bb 8463 }
560b85bb
CW		 8464}
8465
560b85bb 8466static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8467{
8468 struct drm_device *dev = crtc->dev;
8469 struct drm_i915_private *dev_priv = dev->dev_private;
8470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8471 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8472 uint32_t cntl;
8473
8474 cntl = 0;
8475 if (base) {
8476 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8477 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8478 case 64:
8479 cntl |= CURSOR_MODE_64_ARGB_AX;
8480 break;
8481 case 128:
8482 cntl |= CURSOR_MODE_128_ARGB_AX;
8483 break;
8484 case 256:
8485 cntl |= CURSOR_MODE_256_ARGB_AX;
8486 break;
8487 default:
3dd512fb 8488 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8489 return;
65a21cd6 8490 }
4b0e333e 8491 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8492
8493 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8494 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8495 }
65a21cd6 8496
8e7d688b 8497 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8498 cntl |= CURSOR_ROTATE_180;
8499
4b0e333e
CW		 8500 if (intel_crtc->cursor_cntl != cntl) {
8501 I915_WRITE(CURCNTR(pipe), cntl);
8502 POSTING_READ(CURCNTR(pipe));
8503 intel_crtc->cursor_cntl = cntl;
65a21cd6 8504 }
4b0e333e 8505
65a21cd6 8506 /* and commit changes on next vblank */
5efb3e28
VS		 8507 I915_WRITE(CURBASE(pipe), base);
8508 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8509
8510 intel_crtc->cursor_base = base;
65a21cd6
JB		 8511}
8512
cda4b7d3 8513/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8514static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8515 bool on)
cda4b7d3
CW		 8516{
8517 struct drm_device *dev = crtc->dev;
8518 struct drm_i915_private *dev_priv = dev->dev_private;
8519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8520 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8521 int x = crtc->cursor_x;
8522 int y = crtc->cursor_y;
d6e4db15 8523 u32 base = 0, pos = 0;
cda4b7d3 8524
d6e4db15 8525 if (on)
cda4b7d3 8526 base = intel_crtc->cursor_addr;
cda4b7d3 8527
6e3c9717 8528 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8529 base = 0;
8530
6e3c9717 8531 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8532 base = 0;
8533
8534 if (x < 0) {
3dd512fb 8535 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8536 base = 0;
8537
8538 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8539 x = -x;
8540 }
8541 pos |= x << CURSOR_X_SHIFT;
8542
8543 if (y < 0) {
3dd512fb 8544 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8545 base = 0;
8546
8547 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8548 y = -y;
8549 }
8550 pos |= y << CURSOR_Y_SHIFT;
8551
4b0e333e 8552 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8553 return;
8554
5efb3e28
VS		 8555 I915_WRITE(CURPOS(pipe), pos);
8556
4398ad45
VS		 8557 /* ILK+ do this automagically */
8558 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8559 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8560 base += (intel_crtc->base.cursor->state->crtc_h *
8561 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8562 }
8563
8ac54669 8564 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8565 i845_update_cursor(crtc, base);
8566 else
8567 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8568}
8569
dc41c154
VS		 8570static bool cursor_size_ok(struct drm_device *dev,
8571 uint32_t width, uint32_t height)
8572{
8573 if (width == 0 || height == 0)
8574 return false;
8575
8576 /*
8577 * 845g/865g are special in that they are only limited by
8578 * the width of their cursors, the height is arbitrary up to
8579 * the precision of the register. Everything else requires
8580 * square cursors, limited to a few power-of-two sizes.
8581 */
8582 if (IS_845G(dev) || IS_I865G(dev)) {
8583 if ((width & 63) != 0)
8584 return false;
8585
8586 if (width > (IS_845G(dev) ? 64 : 512))
8587 return false;
8588
8589 if (height > 1023)
8590 return false;
8591 } else {
8592 switch (width | height) {
8593 case 256:
8594 case 128:
8595 if (IS_GEN2(dev))
8596 return false;
8597 case 64:
8598 break;
8599 default:
8600 return false;
8601 }
8602 }
8603
8604 return true;
8605}
8606
79e53945 8607static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8608 u16 *blue, uint32_t start, uint32_t size)
79e53945 8609{
7203425a 8610 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8612
7203425a 8613 for (i = start; i < end; i++) {
79e53945
JB		 8614 intel_crtc->lut_r[i] = red[i] >> 8;
8615 intel_crtc->lut_g[i] = green[i] >> 8;
8616 intel_crtc->lut_b[i] = blue[i] >> 8;
8617 }
8618
8619 intel_crtc_load_lut(crtc);
8620}
8621
79e53945
JB		 8622/* VESA 640x480x72Hz mode to set on the pipe */
8623static struct drm_display_mode load_detect_mode = {
8624 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8625 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8626};
8627
a8bb6818
DV		 8628struct drm_framebuffer *
8629__intel_framebuffer_create(struct drm_device *dev,
8630 struct drm_mode_fb_cmd2 *mode_cmd,
8631 struct drm_i915_gem_object *obj)
d2dff872
CW		 8632{
8633 struct intel_framebuffer *intel_fb;
8634 int ret;
8635
8636 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8637 if (!intel_fb) {
6ccb81f2 8638 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8639 return ERR_PTR(-ENOMEM);
8640 }
8641
8642 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8643 if (ret)
8644 goto err;
d2dff872
CW		 8645
8646 return &intel_fb->base;
dd4916c5 8647err:
6ccb81f2 8648 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8649 kfree(intel_fb);
8650
8651 return ERR_PTR(ret);
d2dff872
CW		 8652}
8653
b5ea642a 8654static struct drm_framebuffer *
a8bb6818
DV		 8655intel_framebuffer_create(struct drm_device *dev,
8656 struct drm_mode_fb_cmd2 *mode_cmd,
8657 struct drm_i915_gem_object *obj)
8658{
8659 struct drm_framebuffer *fb;
8660 int ret;
8661
8662 ret = i915_mutex_lock_interruptible(dev);
8663 if (ret)
8664 return ERR_PTR(ret);
8665 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8666 mutex_unlock(&dev->struct_mutex);
8667
8668 return fb;
8669}
8670
d2dff872
CW		 8671static u32
8672intel_framebuffer_pitch_for_width(int width, int bpp)
8673{
8674 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8675 return ALIGN(pitch, 64);
8676}
8677
8678static u32
8679intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8680{
8681 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 8682 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 8683}
8684
8685static struct drm_framebuffer *
8686intel_framebuffer_create_for_mode(struct drm_device *dev,
8687 struct drm_display_mode *mode,
8688 int depth, int bpp)
8689{
8690 struct drm_i915_gem_object *obj;
0fed39bd 8691 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 8692
8693 obj = i915_gem_alloc_object(dev,
8694 intel_framebuffer_size_for_mode(mode, bpp));
8695 if (obj == NULL)
8696 return ERR_PTR(-ENOMEM);
8697
8698 mode_cmd.width = mode->hdisplay;
8699 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 8700 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8701 bpp);
5ca0c34a 8702 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 8703
8704 return intel_framebuffer_create(dev, &mode_cmd, obj);
8705}
8706
8707static struct drm_framebuffer *
8708mode_fits_in_fbdev(struct drm_device *dev,
8709 struct drm_display_mode *mode)
8710{
4520f53a 8711#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 8712 struct drm_i915_private *dev_priv = dev->dev_private;
8713 struct drm_i915_gem_object *obj;
8714 struct drm_framebuffer *fb;
8715
4c0e5528 8716 if (!dev_priv->fbdev)
d2dff872
CW		 8717 return NULL;
8718
4c0e5528 8719 if (!dev_priv->fbdev->fb)
d2dff872
CW		 8720 return NULL;
8721
4c0e5528
DV		 8722 obj = dev_priv->fbdev->fb->obj;
8723 BUG_ON(!obj);
8724
8bcd4553 8725 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 8726 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8727 fb->bits_per_pixel))
d2dff872
CW		 8728 return NULL;
8729
01f2c773 8730 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 8731 return NULL;
8732
8733 return fb;
4520f53a
DV		 8734#else
8735 return NULL;
8736#endif
d2dff872
CW		 8737}
8738
d2434ab7 8739bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 8740 struct drm_display_mode *mode,
51fd371b
RC		 8741 struct intel_load_detect_pipe *old,
8742 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 8743{
8744 struct intel_crtc *intel_crtc;
d2434ab7
DV		 8745 struct intel_encoder *intel_encoder =
8746 intel_attached_encoder(connector);
79e53945 8747 struct drm_crtc *possible_crtc;
4ef69c7a 8748 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 8749 struct drm_crtc *crtc = NULL;
8750 struct drm_device *dev = encoder->dev;
94352cf9 8751 struct drm_framebuffer *fb;
51fd371b
RC		 8752 struct drm_mode_config *config = &dev->mode_config;
8753 int ret, i = -1;
79e53945 8754
d2dff872 8755 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 8756 connector->base.id, connector->name,
8e329a03 8757 encoder->base.id, encoder->name);
d2dff872 8758
51fd371b
RC		 8759retry:
8760 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8761 if (ret)
8762 goto fail_unlock;
6e9f798d 8763
79e53945
JB		 8764 /*
8765 * Algorithm gets a little messy:
7a5e4805 8766 *
79e53945
JB		 8767 * - if the connector already has an assigned crtc, use it (but make
8768 * sure it's on first)
7a5e4805 8769 *
79e53945
JB		 8770 * - try to find the first unused crtc that can drive this connector,
8771 * and use that if we find one
79e53945
JB		 8772 */
8773
8774 /* See if we already have a CRTC for this connector */
8775 if (encoder->crtc) {
8776 crtc = encoder->crtc;
8261b191 8777
51fd371b 8778 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 8779 if (ret)
8780 goto fail_unlock;
8781 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 8782 if (ret)
8783 goto fail_unlock;
7b24056b 8784
24218aac 8785 old->dpms_mode = connector->dpms;
8261b191
CW		 8786 old->load_detect_temp = false;
8787
8788 /* Make sure the crtc and connector are running */
24218aac
DV		 8789 if (connector->dpms != DRM_MODE_DPMS_ON)
8790 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 8791
7173188d 8792 return true;
79e53945
JB		 8793 }
8794
8795 /* Find an unused one (if possible) */
70e1e0ec 8796 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 8797 i++;
8798 if (!(encoder->possible_crtcs & (1 << i)))
8799 continue;
83d65738 8800 if (possible_crtc->state->enable)
a459249c
VS		 8801 continue;
8802 /* This can occur when applying the pipe A quirk on resume. */
8803 if (to_intel_crtc(possible_crtc)->new_enabled)
8804 continue;
8805
8806 crtc = possible_crtc;
8807 break;
79e53945
JB		 8808 }
8809
8810 /*
8811 * If we didn't find an unused CRTC, don't use any.
8812 */
8813 if (!crtc) {
7173188d 8814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 8815 goto fail_unlock;
79e53945
JB		 8816 }
8817
51fd371b
RC		 8818 ret = drm_modeset_lock(&crtc->mutex, ctx);
8819 if (ret)
4d02e2de
DV		 8820 goto fail_unlock;
8821 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8822 if (ret)
51fd371b 8823 goto fail_unlock;
fc303101
DV		 8824 intel_encoder->new_crtc = to_intel_crtc(crtc);
8825 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 8826
8827 intel_crtc = to_intel_crtc(crtc);
412b61d8 8828 intel_crtc->new_enabled = true;
6e3c9717 8829 intel_crtc->new_config = intel_crtc->config;
24218aac 8830 old->dpms_mode = connector->dpms;
8261b191 8831 old->load_detect_temp = true;
d2dff872 8832 old->release_fb = NULL;
79e53945 8833
6492711d
CW		 8834 if (!mode)
8835 mode = &load_detect_mode;
79e53945 8836
d2dff872
CW		 8837 /* We need a framebuffer large enough to accommodate all accesses
8838 * that the plane may generate whilst we perform load detection.
8839 * We can not rely on the fbcon either being present (we get called
8840 * during its initialisation to detect all boot displays, or it may
8841 * not even exist) or that it is large enough to satisfy the
8842 * requested mode.
8843 */
94352cf9
DV		 8844 fb = mode_fits_in_fbdev(dev, mode);
8845 if (fb == NULL) {
d2dff872 8846 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 8847 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8848 old->release_fb = fb;
d2dff872
CW		 8849 } else
8850 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 8851 if (IS_ERR(fb)) {
d2dff872 8852 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 8853 goto fail;
79e53945 8854 }
79e53945 8855
c0c36b94 8856 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 8857 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 8858 if (old->release_fb)
8859 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 8860 goto fail;
79e53945 8861 }
9128b040 8862 crtc->primary->crtc = crtc;
7173188d 8863
79e53945 8864 /* let the connector get through one full cycle before testing */
9d0498a2 8865 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 8866 return true;
412b61d8
VS		 8867
8868 fail:
83d65738 8869 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 8870 if (intel_crtc->new_enabled)
6e3c9717 8871 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 8872 else
8873 intel_crtc->new_config = NULL;
51fd371b
RC		 8874fail_unlock:
8875 if (ret == -EDEADLK) {
8876 drm_modeset_backoff(ctx);
8877 goto retry;
8878 }
8879
412b61d8 8880 return false;
79e53945
JB		 8881}
8882
d2434ab7 8883void intel_release_load_detect_pipe(struct drm_connector *connector,
208bf9fd 8884 struct intel_load_detect_pipe *old)
79e53945 8885{
d2434ab7
DV		 8886 struct intel_encoder *intel_encoder =
8887 intel_attached_encoder(connector);
4ef69c7a 8888 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 8889 struct drm_crtc *crtc = encoder->crtc;
412b61d8 8890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8891
d2dff872 8892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 8893 connector->base.id, connector->name,
8e329a03 8894 encoder->base.id, encoder->name);
d2dff872 8895
8261b191 8896 if (old->load_detect_temp) {
fc303101
DV		 8897 to_intel_connector(connector)->new_encoder = NULL;
8898 intel_encoder->new_crtc = NULL;
412b61d8
VS		 8899 intel_crtc->new_enabled = false;
8900 intel_crtc->new_config = NULL;
fc303101 8901 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 8902
36206361
DV		 8903 if (old->release_fb) {
8904 drm_framebuffer_unregister_private(old->release_fb);
8905 drm_framebuffer_unreference(old->release_fb);
8906 }
d2dff872 8907
0622a53c 8908 return;
79e53945
JB		 8909 }
8910
c751ce4f 8911 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 8912 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8913 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 8914}
8915
da4a1efa 8916static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 8917 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 8918{
8919 struct drm_i915_private *dev_priv = dev->dev_private;
8920 u32 dpll = pipe_config->dpll_hw_state.dpll;
8921
8922 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 8923 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 8924 else if (HAS_PCH_SPLIT(dev))
8925 return 120000;
8926 else if (!IS_GEN2(dev))
8927 return 96000;
8928 else
8929 return 48000;
8930}
8931
79e53945 8932/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 8933static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8934 struct intel_crtc_state *pipe_config)
79e53945 8935{
f1f644dc 8936 struct drm_device *dev = crtc->base.dev;
79e53945 8937 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 8938 int pipe = pipe_config->cpu_transcoder;
293623f7 8939 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 8940 u32 fp;
8941 intel_clock_t clock;
da4a1efa 8942 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 8943
8944 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 8945 fp = pipe_config->dpll_hw_state.fp0;
79e53945 8946 else
293623f7 8947 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 8948
8949 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 8950 if (IS_PINEVIEW(dev)) {
8951 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8952 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 8953 } else {
8954 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8955 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8956 }
8957
a6c45cf0 8958 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 8959 if (IS_PINEVIEW(dev))
8960 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8961 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 8962 else
8963 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 8964 DPLL_FPA01_P1_POST_DIV_SHIFT);
8965
8966 switch (dpll & DPLL_MODE_MASK) {
8967 case DPLLB_MODE_DAC_SERIAL:
8968 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8969 5 : 10;
8970 break;
8971 case DPLLB_MODE_LVDS:
8972 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8973 7 : 14;
8974 break;
8975 default:
28c97730 8976 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 8977 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 8978 return;
79e53945
JB		 8979 }
8980
ac58c3f0 8981 if (IS_PINEVIEW(dev))
da4a1efa 8982 pineview_clock(refclk, &clock);
ac58c3f0 8983 else
da4a1efa 8984 i9xx_clock(refclk, &clock);
79e53945 8985 } else {
0fb58223 8986 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 8987 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 8988
8989 if (is_lvds) {
8990 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8991 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 8992
8993 if (lvds & LVDS_CLKB_POWER_UP)
8994 clock.p2 = 7;
8995 else
8996 clock.p2 = 14;
79e53945
JB		 8997 } else {
8998 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8999 clock.p1 = 2;
9000 else {
9001 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9002 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9003 }
9004 if (dpll & PLL_P2_DIVIDE_BY_4)
9005 clock.p2 = 4;
9006 else
9007 clock.p2 = 2;
79e53945 9008 }
da4a1efa
VS		 9009
9010 i9xx_clock(refclk, &clock);
79e53945
JB		 9011 }
9012
18442d08
VS		 9013 /*
9014 * This value includes pixel_multiplier. We will use
241bfc38 9015 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9016 * encoder's get_config() function.
9017 */
9018 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9019}
9020
6878da05
VS		 9021int intel_dotclock_calculate(int link_freq,
9022 const struct intel_link_m_n *m_n)
f1f644dc 9023{
f1f644dc
JB		 9024 /*
9025 * The calculation for the data clock is:
1041a02f 9026 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9027 * But we want to avoid losing precison if possible, so:
1041a02f 9028 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9029 *
9030 * and the link clock is simpler:
1041a02f 9031 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9032 */
9033
6878da05
VS		 9034 if (!m_n->link_n)
9035 return 0;
f1f644dc 9036
6878da05
VS		 9037 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9038}
f1f644dc 9039
18442d08 9040static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9041 struct intel_crtc_state *pipe_config)
6878da05
VS		 9042{
9043 struct drm_device *dev = crtc->base.dev;
79e53945 9044
18442d08
VS		 9045 /* read out port_clock from the DPLL */
9046 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9047
f1f644dc 9048 /*
18442d08 9049 * This value does not include pixel_multiplier.
241bfc38 9050 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9051 * agree once we know their relationship in the encoder's
9052 * get_config() function.
79e53945 9053 */
2d112de7 9054 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9055 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9056 &pipe_config->fdi_m_n);
79e53945
JB		 9057}
9058
9059/** Returns the currently programmed mode of the given pipe. */
9060struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9061 struct drm_crtc *crtc)
9062{
548f245b 9063 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9065 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9066 struct drm_display_mode *mode;
5cec258b 9067 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9068 int htot = I915_READ(HTOTAL(cpu_transcoder));
9069 int hsync = I915_READ(HSYNC(cpu_transcoder));
9070 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9071 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9072 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9073
9074 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9075 if (!mode)
9076 return NULL;
9077
f1f644dc
JB		 9078 /*
9079 * Construct a pipe_config sufficient for getting the clock info
9080 * back out of crtc_clock_get.
9081 *
9082 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9083 * to use a real value here instead.
9084 */
293623f7 9085 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9086 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9087 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9088 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9089 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9090 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9091
773ae034 9092 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9093 mode->hdisplay = (htot & 0xffff) + 1;
9094 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9095 mode->hsync_start = (hsync & 0xffff) + 1;
9096 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9097 mode->vdisplay = (vtot & 0xffff) + 1;
9098 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9099 mode->vsync_start = (vsync & 0xffff) + 1;
9100 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9101
9102 drm_mode_set_name(mode);
79e53945
JB		 9103
9104 return mode;
9105}
9106
652c393a
JB		 9107static void intel_decrease_pllclock(struct drm_crtc *crtc)
9108{
9109 struct drm_device *dev = crtc->dev;
fbee40df 9110 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9112
baff296c 9113 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9114 return;
9115
9116 if (!dev_priv->lvds_downclock_avail)
9117 return;
9118
9119 /*
9120 * Since this is called by a timer, we should never get here in
9121 * the manual case.
9122 */
9123 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9124 int pipe = intel_crtc->pipe;
9125 int dpll_reg = DPLL(pipe);
9126 int dpll;
f6e5b160 9127
44d98a61 9128 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9129
8ac5a6d5 9130 assert_panel_unlocked(dev_priv, pipe);
652c393a 9131
dc257cf1 9132 dpll = I915_READ(dpll_reg);
652c393a
JB		 9133 dpll |= DISPLAY_RATE_SELECT_FPA1;
9134 I915_WRITE(dpll_reg, dpll);
9d0498a2 9135 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9136 dpll = I915_READ(dpll_reg);
9137 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9138 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9139 }
9140
9141}
9142
f047e395
CW		 9143void intel_mark_busy(struct drm_device *dev)
9144{
c67a470b
PZ		 9145 struct drm_i915_private *dev_priv = dev->dev_private;
9146
f62a0076
CW		 9147 if (dev_priv->mm.busy)
9148 return;
9149
43694d69 9150 intel_runtime_pm_get(dev_priv);
c67a470b 9151 i915_update_gfx_val(dev_priv);
f62a0076 9152 dev_priv->mm.busy = true;
f047e395
CW		 9153}
9154
9155void intel_mark_idle(struct drm_device *dev)
652c393a 9156{
c67a470b 9157 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9158 struct drm_crtc *crtc;
652c393a 9159
f62a0076
CW		 9160 if (!dev_priv->mm.busy)
9161 return;
9162
9163 dev_priv->mm.busy = false;
9164
d330a953 9165 if (!i915.powersave)
bb4cdd53 9166 goto out;
652c393a 9167
70e1e0ec 9168 for_each_crtc(dev, crtc) {
f4510a27 9169 if (!crtc->primary->fb)
652c393a
JB		 9170 continue;
9171
725a5b54 9172 intel_decrease_pllclock(crtc);
652c393a 9173 }
b29c19b6 9174
3d13ef2e 9175 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9176 gen6_rps_idle(dev->dev_private);
bb4cdd53
PZ		 9177
9178out:
43694d69 9179 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9180}
9181
f5de6e07
ACO		 9182static void intel_crtc_set_state(struct intel_crtc *crtc,
9183 struct intel_crtc_state *crtc_state)
9184{
9185 kfree(crtc->config);
9186 crtc->config = crtc_state;
16f3f658 9187 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9188}
9189
79e53945
JB		 9190static void intel_crtc_destroy(struct drm_crtc *crtc)
9191{
9192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9193 struct drm_device *dev = crtc->dev;
9194 struct intel_unpin_work *work;
67e77c5a 9195
5e2d7afc 9196 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9197 work = intel_crtc->unpin_work;
9198 intel_crtc->unpin_work = NULL;
5e2d7afc 9199 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9200
9201 if (work) {
9202 cancel_work_sync(&work->work);
9203 kfree(work);
9204 }
79e53945 9205
f5de6e07 9206 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9207 drm_crtc_cleanup(crtc);
67e77c5a 9208
79e53945
JB		 9209 kfree(intel_crtc);
9210}
9211
6b95a207
KH		 9212static void intel_unpin_work_fn(struct work_struct *__work)
9213{
9214 struct intel_unpin_work *work =
9215 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9216 struct drm_device *dev = work->crtc->dev;
f99d7069 9217 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9218
b4a98e57 9219 mutex_lock(&dev->struct_mutex);
ab8d6675 9220 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
05394f39 9221 drm_gem_object_unreference(&work->pending_flip_obj->base);
ab8d6675 9222 drm_framebuffer_unreference(work->old_fb);
d9e86c0e 9223
7ff0ebcc 9224 intel_fbc_update(dev);
f06cc1b9
JH		 9225
9226 if (work->flip_queued_req)
146d84f0 9227 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9228 mutex_unlock(&dev->struct_mutex);
9229
f99d7069
DV		 9230 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9231
b4a98e57
CW		 9232 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9233 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9234
6b95a207
KH		 9235 kfree(work);
9236}
9237
1afe3e9d 9238static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9239 struct drm_crtc *crtc)
6b95a207 9240{
6b95a207
KH		 9241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9242 struct intel_unpin_work *work;
6b95a207
KH		 9243 unsigned long flags;
9244
9245 /* Ignore early vblank irqs */
9246 if (intel_crtc == NULL)
9247 return;
9248
f326038a
DV		 9249 /*
9250 * This is called both by irq handlers and the reset code (to complete
9251 * lost pageflips) so needs the full irqsave spinlocks.
9252 */
6b95a207
KH		 9253 spin_lock_irqsave(&dev->event_lock, flags);
9254 work = intel_crtc->unpin_work;
e7d841ca
CW		 9255
9256 /* Ensure we don't miss a work->pending update ... */
9257 smp_rmb();
9258
9259 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9260 spin_unlock_irqrestore(&dev->event_lock, flags);
9261 return;
9262 }
9263
d6bbafa1 9264 page_flip_completed(intel_crtc);
0af7e4df 9265
6b95a207 9266 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9267}
9268
1afe3e9d
JB		 9269void intel_finish_page_flip(struct drm_device *dev, int pipe)
9270{
fbee40df 9271 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9272 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9273
49b14a5c 9274 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9275}
9276
9277void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9278{
fbee40df 9279 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9280 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9281
49b14a5c 9282 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9283}
9284
75f7f3ec
VS		 9285/* Is 'a' after or equal to 'b'? */
9286static bool g4x_flip_count_after_eq(u32 a, u32 b)
9287{
9288 return !((a - b) & 0x80000000);
9289}
9290
9291static bool page_flip_finished(struct intel_crtc *crtc)
9292{
9293 struct drm_device *dev = crtc->base.dev;
9294 struct drm_i915_private *dev_priv = dev->dev_private;
9295
bdfa7542
VS		 9296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9297 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9298 return true;
9299
75f7f3ec
VS		 9300 /*
9301 * The relevant registers doen't exist on pre-ctg.
9302 * As the flip done interrupt doesn't trigger for mmio
9303 * flips on gmch platforms, a flip count check isn't
9304 * really needed there. But since ctg has the registers,
9305 * include it in the check anyway.
9306 */
9307 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9308 return true;
9309
9310 /*
9311 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9312 * used the same base address. In that case the mmio flip might
9313 * have completed, but the CS hasn't even executed the flip yet.
9314 *
9315 * A flip count check isn't enough as the CS might have updated
9316 * the base address just after start of vblank, but before we
9317 * managed to process the interrupt. This means we'd complete the
9318 * CS flip too soon.
9319 *
9320 * Combining both checks should get us a good enough result. It may
9321 * still happen that the CS flip has been executed, but has not
9322 * yet actually completed. But in case the base address is the same
9323 * anyway, we don't really care.
9324 */
9325 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9326 crtc->unpin_work->gtt_offset &&
9327 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9328 crtc->unpin_work->flip_count);
9329}
9330
6b95a207
KH		 9331void intel_prepare_page_flip(struct drm_device *dev, int plane)
9332{
fbee40df 9333 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9334 struct intel_crtc *intel_crtc =
9335 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9336 unsigned long flags;
9337
f326038a
DV		 9338
9339 /*
9340 * This is called both by irq handlers and the reset code (to complete
9341 * lost pageflips) so needs the full irqsave spinlocks.
9342 *
9343 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9344 * generate a page-flip completion irq, i.e. every modeset
9345 * is also accompanied by a spurious intel_prepare_page_flip().
9346 */
6b95a207 9347 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9348 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9349 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9350 spin_unlock_irqrestore(&dev->event_lock, flags);
9351}
9352
eba905b2 9353static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9354{
9355 /* Ensure that the work item is consistent when activating it ... */
9356 smp_wmb();
9357 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9358 /* and that it is marked active as soon as the irq could fire. */
9359 smp_wmb();
9360}
9361
8c9f3aaf
JB		 9362static int intel_gen2_queue_flip(struct drm_device *dev,
9363 struct drm_crtc *crtc,
9364 struct drm_framebuffer *fb,
ed8d1975 9365 struct drm_i915_gem_object *obj,
a4872ba6 9366 struct intel_engine_cs *ring,
ed8d1975 9367 uint32_t flags)
8c9f3aaf 9368{
8c9f3aaf 9369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9370 u32 flip_mask;
9371 int ret;
9372
6d90c952 9373 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9374 if (ret)
4fa62c89 9375 return ret;
8c9f3aaf
JB		 9376
9377 /* Can't queue multiple flips, so wait for the previous
9378 * one to finish before executing the next.
9379 */
9380 if (intel_crtc->plane)
9381 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9382 else
9383 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9384 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9385 intel_ring_emit(ring, MI_NOOP);
9386 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9387 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9388 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9389 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9390 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9391
9392 intel_mark_page_flip_active(intel_crtc);
09246732 9393 __intel_ring_advance(ring);
83d4092b 9394 return 0;
8c9f3aaf
JB		 9395}
9396
9397static int intel_gen3_queue_flip(struct drm_device *dev,
9398 struct drm_crtc *crtc,
9399 struct drm_framebuffer *fb,
ed8d1975 9400 struct drm_i915_gem_object *obj,
a4872ba6 9401 struct intel_engine_cs *ring,
ed8d1975 9402 uint32_t flags)
8c9f3aaf 9403{
8c9f3aaf 9404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9405 u32 flip_mask;
9406 int ret;
9407
6d90c952 9408 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9409 if (ret)
4fa62c89 9410 return ret;
8c9f3aaf
JB		 9411
9412 if (intel_crtc->plane)
9413 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9414 else
9415 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9416 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9417 intel_ring_emit(ring, MI_NOOP);
9418 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9419 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9420 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9421 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9422 intel_ring_emit(ring, MI_NOOP);
9423
e7d841ca 9424 intel_mark_page_flip_active(intel_crtc);
09246732 9425 __intel_ring_advance(ring);
83d4092b 9426 return 0;
8c9f3aaf
JB		 9427}
9428
9429static int intel_gen4_queue_flip(struct drm_device *dev,
9430 struct drm_crtc *crtc,
9431 struct drm_framebuffer *fb,
ed8d1975 9432 struct drm_i915_gem_object *obj,
a4872ba6 9433 struct intel_engine_cs *ring,
ed8d1975 9434 uint32_t flags)
8c9f3aaf
JB		 9435{
9436 struct drm_i915_private *dev_priv = dev->dev_private;
9437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9438 uint32_t pf, pipesrc;
9439 int ret;
9440
6d90c952 9441 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9442 if (ret)
4fa62c89 9443 return ret;
8c9f3aaf
JB		 9444
9445 /* i965+ uses the linear or tiled offsets from the
9446 * Display Registers (which do not change across a page-flip)
9447 * so we need only reprogram the base address.
9448 */
6d90c952
DV		 9449 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9450 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9451 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9453 obj->tiling_mode);
8c9f3aaf
JB		 9454
9455 /* XXX Enabling the panel-fitter across page-flip is so far
9456 * untested on non-native modes, so ignore it for now.
9457 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9458 */
9459 pf = 0;
9460 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9461 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9462
9463 intel_mark_page_flip_active(intel_crtc);
09246732 9464 __intel_ring_advance(ring);
83d4092b 9465 return 0;
8c9f3aaf
JB		 9466}
9467
9468static int intel_gen6_queue_flip(struct drm_device *dev,
9469 struct drm_crtc *crtc,
9470 struct drm_framebuffer *fb,
ed8d1975 9471 struct drm_i915_gem_object *obj,
a4872ba6 9472 struct intel_engine_cs *ring,
ed8d1975 9473 uint32_t flags)
8c9f3aaf
JB		 9474{
9475 struct drm_i915_private *dev_priv = dev->dev_private;
9476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9477 uint32_t pf, pipesrc;
9478 int ret;
9479
6d90c952 9480 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9481 if (ret)
4fa62c89 9482 return ret;
8c9f3aaf 9483
6d90c952
DV		 9484 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9485 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9486 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9487 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9488
dc257cf1
DV		 9489 /* Contrary to the suggestions in the documentation,
9490 * "Enable Panel Fitter" does not seem to be required when page
9491 * flipping with a non-native mode, and worse causes a normal
9492 * modeset to fail.
9493 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9494 */
9495 pf = 0;
8c9f3aaf 9496 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9497 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9498
9499 intel_mark_page_flip_active(intel_crtc);
09246732 9500 __intel_ring_advance(ring);
83d4092b 9501 return 0;
8c9f3aaf
JB		 9502}
9503
7c9017e5
JB		 9504static int intel_gen7_queue_flip(struct drm_device *dev,
9505 struct drm_crtc *crtc,
9506 struct drm_framebuffer *fb,
ed8d1975 9507 struct drm_i915_gem_object *obj,
a4872ba6 9508 struct intel_engine_cs *ring,
ed8d1975 9509 uint32_t flags)
7c9017e5 9510{
7c9017e5 9511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9512 uint32_t plane_bit = 0;
ffe74d75
CW		 9513 int len, ret;
9514
eba905b2 9515 switch (intel_crtc->plane) {
cb05d8de
DV		 9516 case PLANE_A:
9517 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9518 break;
9519 case PLANE_B:
9520 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9521 break;
9522 case PLANE_C:
9523 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9524 break;
9525 default:
9526 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9527 return -ENODEV;
cb05d8de
DV		 9528 }
9529
ffe74d75 9530 len = 4;
f476828a 9531 if (ring->id == RCS) {
ffe74d75 9532 len += 6;
f476828a
DL		 9533 /*
9534 * On Gen 8, SRM is now taking an extra dword to accommodate
9535 * 48bits addresses, and we need a NOOP for the batch size to
9536 * stay even.
9537 */
9538 if (IS_GEN8(dev))
9539 len += 2;
9540 }
ffe74d75 9541
f66fab8e
VS		 9542 /*
9543 * BSpec MI_DISPLAY_FLIP for IVB:
9544 * "The full packet must be contained within the same cache line."
9545 *
9546 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9547 * cacheline, if we ever start emitting more commands before
9548 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9549 * then do the cacheline alignment, and finally emit the
9550 * MI_DISPLAY_FLIP.
9551 */
9552 ret = intel_ring_cacheline_align(ring);
9553 if (ret)
4fa62c89 9554 return ret;
f66fab8e 9555
ffe74d75 9556 ret = intel_ring_begin(ring, len);
7c9017e5 9557 if (ret)
4fa62c89 9558 return ret;
7c9017e5 9559
ffe74d75
CW		 9560 /* Unmask the flip-done completion message. Note that the bspec says that
9561 * we should do this for both the BCS and RCS, and that we must not unmask
9562 * more than one flip event at any time (or ensure that one flip message
9563 * can be sent by waiting for flip-done prior to queueing new flips).
9564 * Experimentation says that BCS works despite DERRMR masking all
9565 * flip-done completion events and that unmasking all planes at once
9566 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9567 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9568 */
9569 if (ring->id == RCS) {
9570 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9571 intel_ring_emit(ring, DERRMR);
9572 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9573 DERRMR_PIPEB_PRI_FLIP_DONE |
9574 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9575 if (IS_GEN8(dev))
9576 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9577 MI_SRM_LRM_GLOBAL_GTT);
9578 else
9579 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9580 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9581 intel_ring_emit(ring, DERRMR);
9582 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9583 if (IS_GEN8(dev)) {
9584 intel_ring_emit(ring, 0);
9585 intel_ring_emit(ring, MI_NOOP);
9586 }
ffe74d75
CW		 9587 }
9588
cb05d8de 9589 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9590 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9591 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9592 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9593
9594 intel_mark_page_flip_active(intel_crtc);
09246732 9595 __intel_ring_advance(ring);
83d4092b 9596 return 0;
7c9017e5
JB		 9597}
9598
84c33a64
SG		 9599static bool use_mmio_flip(struct intel_engine_cs *ring,
9600 struct drm_i915_gem_object *obj)
9601{
9602 /*
9603 * This is not being used for older platforms, because
9604 * non-availability of flip done interrupt forces us to use
9605 * CS flips. Older platforms derive flip done using some clever
9606 * tricks involving the flip_pending status bits and vblank irqs.
9607 * So using MMIO flips there would disrupt this mechanism.
9608 */
9609
8e09bf83
CW		 9610 if (ring == NULL)
9611 return true;
9612
84c33a64
SG		 9613 if (INTEL_INFO(ring->dev)->gen < 5)
9614 return false;
9615
9616 if (i915.use_mmio_flip < 0)
9617 return false;
9618 else if (i915.use_mmio_flip > 0)
9619 return true;
14bf993e
OM		 9620 else if (i915.enable_execlists)
9621 return true;
84c33a64 9622 else
41c52415 9623 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 9624}
9625
ff944564
DL		 9626static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9627{
9628 struct drm_device *dev = intel_crtc->base.dev;
9629 struct drm_i915_private *dev_priv = dev->dev_private;
9630 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9631 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9632 struct drm_i915_gem_object *obj = intel_fb->obj;
9633 const enum pipe pipe = intel_crtc->pipe;
9634 u32 ctl, stride;
9635
9636 ctl = I915_READ(PLANE_CTL(pipe, 0));
9637 ctl &= ~PLANE_CTL_TILED_MASK;
9638 if (obj->tiling_mode == I915_TILING_X)
9639 ctl |= PLANE_CTL_TILED_X;
9640
9641 /*
9642 * The stride is either expressed as a multiple of 64 bytes chunks for
9643 * linear buffers or in number of tiles for tiled buffers.
9644 */
9645 stride = fb->pitches[0] >> 6;
9646 if (obj->tiling_mode == I915_TILING_X)
9647 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9648
9649 /*
9650 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9651 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9652 */
9653 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9654 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9655
9656 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9657 POSTING_READ(PLANE_SURF(pipe, 0));
9658}
9659
9660static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 9661{
9662 struct drm_device *dev = intel_crtc->base.dev;
9663 struct drm_i915_private *dev_priv = dev->dev_private;
9664 struct intel_framebuffer *intel_fb =
9665 to_intel_framebuffer(intel_crtc->base.primary->fb);
9666 struct drm_i915_gem_object *obj = intel_fb->obj;
9667 u32 dspcntr;
9668 u32 reg;
9669
84c33a64
SG		 9670 reg = DSPCNTR(intel_crtc->plane);
9671 dspcntr = I915_READ(reg);
9672
c5d97472
DL		 9673 if (obj->tiling_mode != I915_TILING_NONE)
9674 dspcntr |= DISPPLANE_TILED;
9675 else
9676 dspcntr &= ~DISPPLANE_TILED;
9677
84c33a64
SG		 9678 I915_WRITE(reg, dspcntr);
9679
9680 I915_WRITE(DSPSURF(intel_crtc->plane),
9681 intel_crtc->unpin_work->gtt_offset);
9682 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 9683
ff944564
DL		 9684}
9685
9686/*
9687 * XXX: This is the temporary way to update the plane registers until we get
9688 * around to using the usual plane update functions for MMIO flips
9689 */
9690static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9691{
9692 struct drm_device *dev = intel_crtc->base.dev;
9693 bool atomic_update;
9694 u32 start_vbl_count;
9695
9696 intel_mark_page_flip_active(intel_crtc);
9697
9698 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9699
9700 if (INTEL_INFO(dev)->gen >= 9)
9701 skl_do_mmio_flip(intel_crtc);
9702 else
9703 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9704 ilk_do_mmio_flip(intel_crtc);
9705
9362c7c5
ACO		 9706 if (atomic_update)
9707 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 9708}
9709
9362c7c5 9710static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 9711{
cc8c4cc2 9712 struct intel_crtc *crtc =
9362c7c5 9713 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 9714 struct intel_mmio_flip *mmio_flip;
84c33a64 9715
cc8c4cc2
JH		 9716 mmio_flip = &crtc->mmio_flip;
9717 if (mmio_flip->req)
9c654818
JH		 9718 WARN_ON(__i915_wait_request(mmio_flip->req,
9719 crtc->reset_counter,
9720 false, NULL, NULL) != 0);
84c33a64 9721
cc8c4cc2
JH		 9722 intel_do_mmio_flip(crtc);
9723 if (mmio_flip->req) {
9724 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 9725 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 9726 mutex_unlock(&crtc->base.dev->struct_mutex);
9727 }
84c33a64
SG		 9728}
9729
9730static int intel_queue_mmio_flip(struct drm_device *dev,
9731 struct drm_crtc *crtc,
9732 struct drm_framebuffer *fb,
9733 struct drm_i915_gem_object *obj,
9734 struct intel_engine_cs *ring,
9735 uint32_t flags)
9736{
84c33a64 9737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 9738
cc8c4cc2
JH		 9739 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9740 obj->last_write_req);
536f5b5e
ACO		 9741
9742 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 9743
84c33a64
SG		 9744 return 0;
9745}
9746
8c9f3aaf
JB		 9747static int intel_default_queue_flip(struct drm_device *dev,
9748 struct drm_crtc *crtc,
9749 struct drm_framebuffer *fb,
ed8d1975 9750 struct drm_i915_gem_object *obj,
a4872ba6 9751 struct intel_engine_cs *ring,
ed8d1975 9752 uint32_t flags)
8c9f3aaf
JB		 9753{
9754 return -ENODEV;
9755}
9756
d6bbafa1
CW		 9757static bool __intel_pageflip_stall_check(struct drm_device *dev,
9758 struct drm_crtc *crtc)
9759{
9760 struct drm_i915_private *dev_priv = dev->dev_private;
9761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9762 struct intel_unpin_work *work = intel_crtc->unpin_work;
9763 u32 addr;
9764
9765 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9766 return true;
9767
9768 if (!work->enable_stall_check)
9769 return false;
9770
9771 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 9772 if (work->flip_queued_req &&
9773 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 9774 return false;
9775
1e3feefd 9776 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 9777 }
9778
1e3feefd 9779 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 9780 return false;
9781
9782 /* Potential stall - if we see that the flip has happened,
9783 * assume a missed interrupt. */
9784 if (INTEL_INFO(dev)->gen >= 4)
9785 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9786 else
9787 addr = I915_READ(DSPADDR(intel_crtc->plane));
9788
9789 /* There is a potential issue here with a false positive after a flip
9790 * to the same address. We could address this by checking for a
9791 * non-incrementing frame counter.
9792 */
9793 return addr == work->gtt_offset;
9794}
9795
9796void intel_check_page_flip(struct drm_device *dev, int pipe)
9797{
9798 struct drm_i915_private *dev_priv = dev->dev_private;
9799 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a
DV		 9801
9802 WARN_ON(!in_irq());
d6bbafa1
CW		 9803
9804 if (crtc == NULL)
9805 return;
9806
f326038a 9807 spin_lock(&dev->event_lock);
d6bbafa1
CW		 9808 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9809 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 9810 intel_crtc->unpin_work->flip_queued_vblank,
9811 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 9812 page_flip_completed(intel_crtc);
9813 }
f326038a 9814 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 9815}
9816
6b95a207
KH		 9817static int intel_crtc_page_flip(struct drm_crtc *crtc,
9818 struct drm_framebuffer *fb,
ed8d1975
KP		 9819 struct drm_pending_vblank_event *event,
9820 uint32_t page_flip_flags)
6b95a207
KH		 9821{
9822 struct drm_device *dev = crtc->dev;
9823 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 9824 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 9825 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 9826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 9827 struct drm_plane *primary = crtc->primary;
a071fa00 9828 enum pipe pipe = intel_crtc->pipe;
6b95a207 9829 struct intel_unpin_work *work;
a4872ba6 9830 struct intel_engine_cs *ring;
52e68630 9831 int ret;
6b95a207 9832
2ff8fde1
MR		 9833 /*
9834 * drm_mode_page_flip_ioctl() should already catch this, but double
9835 * check to be safe. In the future we may enable pageflipping from
9836 * a disabled primary plane.
9837 */
9838 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9839 return -EBUSY;
9840
e6a595d2 9841 /* Can't change pixel format via MI display flips. */
f4510a27 9842 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 9843 return -EINVAL;
9844
9845 /*
9846 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9847 * Note that pitch changes could also affect these register.
9848 */
9849 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 9850 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9851 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 9852 return -EINVAL;
9853
f900db47
CW		 9854 if (i915_terminally_wedged(&dev_priv->gpu_error))
9855 goto out_hang;
9856
b14c5679 9857 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 9858 if (work == NULL)
9859 return -ENOMEM;
9860
6b95a207 9861 work->event = event;
b4a98e57 9862 work->crtc = crtc;
ab8d6675 9863 work->old_fb = old_fb;
6b95a207
KH		 9864 INIT_WORK(&work->work, intel_unpin_work_fn);
9865
87b6b101 9866 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 9867 if (ret)
9868 goto free_work;
9869
6b95a207 9870 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 9871 spin_lock_irq(&dev->event_lock);
6b95a207 9872 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 9873 /* Before declaring the flip queue wedged, check if
9874 * the hardware completed the operation behind our backs.
9875 */
9876 if (__intel_pageflip_stall_check(dev, crtc)) {
9877 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9878 page_flip_completed(intel_crtc);
9879 } else {
9880 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 9881 spin_unlock_irq(&dev->event_lock);
468f0b44 9882
d6bbafa1
CW		 9883 drm_crtc_vblank_put(crtc);
9884 kfree(work);
9885 return -EBUSY;
9886 }
6b95a207
KH		 9887 }
9888 intel_crtc->unpin_work = work;
5e2d7afc 9889 spin_unlock_irq(&dev->event_lock);
6b95a207 9890
b4a98e57
CW		 9891 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9892 flush_workqueue(dev_priv->wq);
9893
79158103
CW		 9894 ret = i915_mutex_lock_interruptible(dev);
9895 if (ret)
9896 goto cleanup;
6b95a207 9897
75dfca80 9898 /* Reference the objects for the scheduled work. */
ab8d6675 9899 drm_framebuffer_reference(work->old_fb);
05394f39 9900 drm_gem_object_reference(&obj->base);
6b95a207 9901
f4510a27 9902 crtc->primary->fb = fb;
afd65eb4 9903 update_state_fb(crtc->primary);
1ed1f968 9904
e1f99ce6 9905 work->pending_flip_obj = obj;
e1f99ce6 9906
b4a98e57 9907 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 9908 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 9909
75f7f3ec 9910 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 9911 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 9912
4fa62c89
VS		 9913 if (IS_VALLEYVIEW(dev)) {
9914 ring = &dev_priv->ring[BCS];
ab8d6675 9915 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 9916 /* vlv: DISPLAY_FLIP fails to change tiling */
9917 ring = NULL;
48bf5b2d 9918 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 9919 ring = &dev_priv->ring[BCS];
4fa62c89 9920 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 9921 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 9922 if (ring == NULL || ring->id != RCS)
9923 ring = &dev_priv->ring[BCS];
9924 } else {
9925 ring = &dev_priv->ring[RCS];
9926 }
9927
850c4cdc 9928 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
8c9f3aaf
JB		 9929 if (ret)
9930 goto cleanup_pending;
6b95a207 9931
4fa62c89
VS		 9932 work->gtt_offset =
9933 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9934
d6bbafa1 9935 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 9936 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9937 page_flip_flags);
d6bbafa1
CW		 9938 if (ret)
9939 goto cleanup_unpin;
9940
f06cc1b9
JH		 9941 i915_gem_request_assign(&work->flip_queued_req,
9942 obj->last_write_req);
d6bbafa1 9943 } else {
84c33a64 9944 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 9945 page_flip_flags);
9946 if (ret)
9947 goto cleanup_unpin;
9948
f06cc1b9
JH		 9949 i915_gem_request_assign(&work->flip_queued_req,
9950 intel_ring_get_request(ring));
d6bbafa1
CW		 9951 }
9952
1e3feefd 9953 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 9954 work->enable_stall_check = true;
4fa62c89 9955
ab8d6675 9956 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 9957 INTEL_FRONTBUFFER_PRIMARY(pipe));
9958
7ff0ebcc 9959 intel_fbc_disable(dev);
f99d7069 9960 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 9961 mutex_unlock(&dev->struct_mutex);
9962
e5510fac
JB		 9963 trace_i915_flip_request(intel_crtc->plane, obj);
9964
6b95a207 9965 return 0;
96b099fd 9966
4fa62c89
VS		 9967cleanup_unpin:
9968 intel_unpin_fb_obj(obj);
8c9f3aaf 9969cleanup_pending:
b4a98e57 9970 atomic_dec(&intel_crtc->unpin_work_count);
f4510a27 9971 crtc->primary->fb = old_fb;
afd65eb4 9972 update_state_fb(crtc->primary);
ab8d6675 9973 drm_framebuffer_unreference(work->old_fb);
05394f39 9974 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 9975 mutex_unlock(&dev->struct_mutex);
9976
79158103 9977cleanup:
5e2d7afc 9978 spin_lock_irq(&dev->event_lock);
96b099fd 9979 intel_crtc->unpin_work = NULL;
5e2d7afc 9980 spin_unlock_irq(&dev->event_lock);
96b099fd 9981
87b6b101 9982 drm_crtc_vblank_put(crtc);
7317c75e 9983free_work:
96b099fd
CW		 9984 kfree(work);
9985
f900db47
CW		 9986 if (ret == -EIO) {
9987out_hang:
53a366b9 9988 ret = intel_plane_restore(primary);
f0d3dad3 9989 if (ret == 0 && event) {
5e2d7afc 9990 spin_lock_irq(&dev->event_lock);
a071fa00 9991 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 9992 spin_unlock_irq(&dev->event_lock);
f0d3dad3 9993 }
f900db47 9994 }
96b099fd 9995 return ret;
6b95a207
KH		 9996}
9997
f6e5b160 9998static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 9999 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10000 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10001 .atomic_begin = intel_begin_crtc_commit,
10002 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10003};
10004
9a935856
DV		 10005/**
10006 * intel_modeset_update_staged_output_state
10007 *
10008 * Updates the staged output configuration state, e.g. after we've read out the
10009 * current hw state.
10010 */
10011static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10012{
7668851f 10013 struct intel_crtc *crtc;
9a935856
DV		 10014 struct intel_encoder *encoder;
10015 struct intel_connector *connector;
f6e5b160 10016
3a3371ff 10017 for_each_intel_connector(dev, connector) {
9a935856
DV		 10018 connector->new_encoder =
10019 to_intel_encoder(connector->base.encoder);
10020 }
f6e5b160 10021
b2784e15 10022 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10023 encoder->new_crtc =
10024 to_intel_crtc(encoder->base.crtc);
10025 }
7668851f 10026
d3fcc808 10027 for_each_intel_crtc(dev, crtc) {
83d65738 10028 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10029
10030 if (crtc->new_enabled)
6e3c9717 10031 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10032 else
10033 crtc->new_config = NULL;
7668851f 10034 }
f6e5b160
CW		 10035}
10036
9a935856
DV		 10037/**
10038 * intel_modeset_commit_output_state
10039 *
10040 * This function copies the stage display pipe configuration to the real one.
10041 */
10042static void intel_modeset_commit_output_state(struct drm_device *dev)
10043{
7668851f 10044 struct intel_crtc *crtc;
9a935856
DV		 10045 struct intel_encoder *encoder;
10046 struct intel_connector *connector;
f6e5b160 10047
3a3371ff 10048 for_each_intel_connector(dev, connector) {
9a935856
DV		 10049 connector->base.encoder = &connector->new_encoder->base;
10050 }
f6e5b160 10051
b2784e15 10052 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10053 encoder->base.crtc = &encoder->new_crtc->base;
10054 }
7668851f 10055
d3fcc808 10056 for_each_intel_crtc(dev, crtc) {
83d65738 10057 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10058 crtc->base.enabled = crtc->new_enabled;
10059 }
9a935856
DV		 10060}
10061
050f7aeb 10062static void
eba905b2 10063connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10064 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10065{
10066 int bpp = pipe_config->pipe_bpp;
10067
10068 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10069 connector->base.base.id,
c23cc417 10070 connector->base.name);
050f7aeb
DV		 10071
10072 /* Don't use an invalid EDID bpc value */
10073 if (connector->base.display_info.bpc &&
10074 connector->base.display_info.bpc * 3 < bpp) {
10075 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10076 bpp, connector->base.display_info.bpc*3);
10077 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10078 }
10079
10080 /* Clamp bpp to 8 on screens without EDID 1.4 */
10081 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10082 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10083 bpp);
10084 pipe_config->pipe_bpp = 24;
10085 }
10086}
10087
4e53c2e0 10088static int
050f7aeb
DV		 10089compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10090 struct drm_framebuffer *fb,
5cec258b 10091 struct intel_crtc_state *pipe_config)
4e53c2e0 10092{
050f7aeb
DV		 10093 struct drm_device *dev = crtc->base.dev;
10094 struct intel_connector *connector;
4e53c2e0
DV		 10095 int bpp;
10096
d42264b1
DV		 10097 switch (fb->pixel_format) {
10098 case DRM_FORMAT_C8:
4e53c2e0
DV		 10099 bpp = 8*3; /* since we go through a colormap */
10100 break;
d42264b1
DV		 10101 case DRM_FORMAT_XRGB1555:
10102 case DRM_FORMAT_ARGB1555:
10103 /* checked in intel_framebuffer_init already */
10104 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10105 return -EINVAL;
10106 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10107 bpp = 6*3; /* min is 18bpp */
10108 break;
d42264b1
DV		 10109 case DRM_FORMAT_XBGR8888:
10110 case DRM_FORMAT_ABGR8888:
10111 /* checked in intel_framebuffer_init already */
10112 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10113 return -EINVAL;
10114 case DRM_FORMAT_XRGB8888:
10115 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10116 bpp = 8*3;
10117 break;
d42264b1
DV		 10118 case DRM_FORMAT_XRGB2101010:
10119 case DRM_FORMAT_ARGB2101010:
10120 case DRM_FORMAT_XBGR2101010:
10121 case DRM_FORMAT_ABGR2101010:
10122 /* checked in intel_framebuffer_init already */
10123 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10124 return -EINVAL;
4e53c2e0
DV		 10125 bpp = 10*3;
10126 break;
baba133a 10127 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10128 default:
10129 DRM_DEBUG_KMS("unsupported depth\n");
10130 return -EINVAL;
10131 }
10132
4e53c2e0
DV		 10133 pipe_config->pipe_bpp = bpp;
10134
10135 /* Clamp display bpp to EDID value */
3a3371ff 10136 for_each_intel_connector(dev, connector) {
1b829e05
DV		 10137 if (!connector->new_encoder ||
10138 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 10139 continue;
10140
050f7aeb 10141 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10142 }
10143
10144 return bpp;
10145}
10146
644db711
DV		 10147static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10148{
10149 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10150 "type: 0x%x flags: 0x%x\n",
1342830c 10151 mode->crtc_clock,
644db711
DV		 10152 mode->crtc_hdisplay, mode->crtc_hsync_start,
10153 mode->crtc_hsync_end, mode->crtc_htotal,
10154 mode->crtc_vdisplay, mode->crtc_vsync_start,
10155 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10156}
10157
c0b03411 10158static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10159 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10160 const char *context)
10161{
10162 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10163 context, pipe_name(crtc->pipe));
10164
10165 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10166 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10167 pipe_config->pipe_bpp, pipe_config->dither);
10168 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10169 pipe_config->has_pch_encoder,
10170 pipe_config->fdi_lanes,
10171 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10172 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10173 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10174 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10175 pipe_config->has_dp_encoder,
10176 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10177 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10178 pipe_config->dp_m_n.tu);
b95af8be
VK		 10179
10180 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10181 pipe_config->has_dp_encoder,
10182 pipe_config->dp_m2_n2.gmch_m,
10183 pipe_config->dp_m2_n2.gmch_n,
10184 pipe_config->dp_m2_n2.link_m,
10185 pipe_config->dp_m2_n2.link_n,
10186 pipe_config->dp_m2_n2.tu);
10187
55072d19
DV		 10188 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10189 pipe_config->has_audio,
10190 pipe_config->has_infoframe);
10191
c0b03411 10192 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10193 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10194 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10195 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10196 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10197 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10198 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10199 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10200 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10201 pipe_config->gmch_pfit.control,
10202 pipe_config->gmch_pfit.pgm_ratios,
10203 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10204 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10205 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10206 pipe_config->pch_pfit.size,
10207 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10208 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10209 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10210}
10211
bc079e8b
VS		 10212static bool encoders_cloneable(const struct intel_encoder *a,
10213 const struct intel_encoder *b)
accfc0c5 10214{
bc079e8b
VS		 10215 /* masks could be asymmetric, so check both ways */
10216 return a == b || (a->cloneable & (1 << b->type) &&
10217 b->cloneable & (1 << a->type));
10218}
10219
10220static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10221 struct intel_encoder *encoder)
10222{
10223 struct drm_device *dev = crtc->base.dev;
10224 struct intel_encoder *source_encoder;
10225
b2784e15 10226 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10227 if (source_encoder->new_crtc != crtc)
10228 continue;
10229
10230 if (!encoders_cloneable(encoder, source_encoder))
10231 return false;
10232 }
10233
10234 return true;
10235}
10236
10237static bool check_encoder_cloning(struct intel_crtc *crtc)
10238{
10239 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10240 struct intel_encoder *encoder;
10241
b2784e15 10242 for_each_intel_encoder(dev, encoder) {
bc079e8b 10243 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10244 continue;
10245
bc079e8b
VS		 10246 if (!check_single_encoder_cloning(crtc, encoder))
10247 return false;
accfc0c5
DV		 10248 }
10249
bc079e8b 10250 return true;
accfc0c5
DV		 10251}
10252
00f0b378
VS		 10253static bool check_digital_port_conflicts(struct drm_device *dev)
10254{
10255 struct intel_connector *connector;
10256 unsigned int used_ports = 0;
10257
10258 /*
10259 * Walk the connector list instead of the encoder
10260 * list to detect the problem on ddi platforms
10261 * where there's just one encoder per digital port.
10262 */
3a3371ff 10263 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10264 struct intel_encoder *encoder = connector->new_encoder;
10265
10266 if (!encoder)
10267 continue;
10268
10269 WARN_ON(!encoder->new_crtc);
10270
10271 switch (encoder->type) {
10272 unsigned int port_mask;
10273 case INTEL_OUTPUT_UNKNOWN:
10274 if (WARN_ON(!HAS_DDI(dev)))
10275 break;
10276 case INTEL_OUTPUT_DISPLAYPORT:
10277 case INTEL_OUTPUT_HDMI:
10278 case INTEL_OUTPUT_EDP:
10279 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10280
10281 /* the same port mustn't appear more than once */
10282 if (used_ports & port_mask)
10283 return false;
10284
10285 used_ports |= port_mask;
10286 default:
10287 break;
10288 }
10289 }
10290
10291 return true;
10292}
10293
5cec258b 10294static struct intel_crtc_state *
b8cecdf5 10295intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10296 struct drm_framebuffer *fb,
b8cecdf5 10297 struct drm_display_mode *mode)
ee7b9f93 10298{
7758a113 10299 struct drm_device *dev = crtc->dev;
7758a113 10300 struct intel_encoder *encoder;
5cec258b 10301 struct intel_crtc_state *pipe_config;
e29c22c0
DV		 10302 int plane_bpp, ret = -EINVAL;
10303 bool retry = true;
ee7b9f93 10304
bc079e8b 10305 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10306 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10307 return ERR_PTR(-EINVAL);
10308 }
10309
00f0b378
VS		 10310 if (!check_digital_port_conflicts(dev)) {
10311 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10312 return ERR_PTR(-EINVAL);
10313 }
10314
b8cecdf5
DV		 10315 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10316 if (!pipe_config)
7758a113
DV		 10317 return ERR_PTR(-ENOMEM);
10318
07878248 10319 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10320 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10321 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10322
e143a21c
DV		 10323 pipe_config->cpu_transcoder =
10324 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10325 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10326
2960bc9c
ID		 10327 /*
10328 * Sanitize sync polarity flags based on requested ones. If neither
10329 * positive or negative polarity is requested, treat this as meaning
10330 * negative polarity.
10331 */
2d112de7 10332 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10333 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10334 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10335
2d112de7 10336 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10337 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10338 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10339
050f7aeb
DV		 10340 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10341 * plane pixel format and any sink constraints into account. Returns the
10342 * source plane bpp so that dithering can be selected on mismatches
10343 * after encoders and crtc also have had their say. */
10344 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10345 fb, pipe_config);
4e53c2e0
DV		 10346 if (plane_bpp < 0)
10347 goto fail;
10348
e41a56be
VS		 10349 /*
10350 * Determine the real pipe dimensions. Note that stereo modes can
10351 * increase the actual pipe size due to the frame doubling and
10352 * insertion of additional space for blanks between the frame. This
10353 * is stored in the crtc timings. We use the requested mode to do this
10354 * computation to clearly distinguish it from the adjusted mode, which
10355 * can be changed by the connectors in the below retry loop.
10356 */
2d112de7 10357 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10358 &pipe_config->pipe_src_w,
10359 &pipe_config->pipe_src_h);
e41a56be 10360
e29c22c0 10361encoder_retry:
ef1b460d 10362 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10363 pipe_config->port_clock = 0;
ef1b460d 10364 pipe_config->pixel_multiplier = 1;
ff9a6750 10365
135c81b8 10366 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10367 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10368 CRTC_STEREO_DOUBLE);
135c81b8 10369
7758a113
DV		 10370 /* Pass our mode to the connectors and the CRTC to give them a chance to
10371 * adjust it according to limitations or connector properties, and also
10372 * a chance to reject the mode entirely.
47f1c6c9 10373 */
b2784e15 10374 for_each_intel_encoder(dev, encoder) {
47f1c6c9 10375
7758a113
DV		 10376 if (&encoder->new_crtc->base != crtc)
10377 continue;
7ae89233 10378
efea6e8e
DV		 10379 if (!(encoder->compute_config(encoder, pipe_config))) {
10380 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10381 goto fail;
10382 }
ee7b9f93 10383 }
47f1c6c9 10384
ff9a6750
DV		 10385 /* Set default port clock if not overwritten by the encoder. Needs to be
10386 * done afterwards in case the encoder adjusts the mode. */
10387 if (!pipe_config->port_clock)
2d112de7 10388 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10389 * pipe_config->pixel_multiplier;
ff9a6750 10390
a43f6e0f 10391 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10392 if (ret < 0) {
7758a113
DV		 10393 DRM_DEBUG_KMS("CRTC fixup failed\n");
10394 goto fail;
ee7b9f93 10395 }
e29c22c0
DV		 10396
10397 if (ret == RETRY) {
10398 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10399 ret = -EINVAL;
10400 goto fail;
10401 }
10402
10403 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10404 retry = false;
10405 goto encoder_retry;
10406 }
10407
4e53c2e0
DV		 10408 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10409 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10410 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10411
b8cecdf5 10412 return pipe_config;
7758a113 10413fail:
b8cecdf5 10414 kfree(pipe_config);
e29c22c0 10415 return ERR_PTR(ret);
ee7b9f93 10416}
47f1c6c9 10417
e2e1ed41
DV		 10418/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10419 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10420static void
10421intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10422 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10423{
10424 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10425 struct drm_device *dev = crtc->dev;
10426 struct intel_encoder *encoder;
10427 struct intel_connector *connector;
10428 struct drm_crtc *tmp_crtc;
79e53945 10429
e2e1ed41 10430 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10431
e2e1ed41
DV		 10432 /* Check which crtcs have changed outputs connected to them, these need
10433 * to be part of the prepare_pipes mask. We don't (yet) support global
10434 * modeset across multiple crtcs, so modeset_pipes will only have one
10435 * bit set at most. */
3a3371ff 10436 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10437 if (connector->base.encoder == &connector->new_encoder->base)
10438 continue;
79e53945 10439
e2e1ed41
DV		 10440 if (connector->base.encoder) {
10441 tmp_crtc = connector->base.encoder->crtc;
10442
10443 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10444 }
10445
10446 if (connector->new_encoder)
10447 *prepare_pipes |=
10448 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10449 }
10450
b2784e15 10451 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10452 if (encoder->base.crtc == &encoder->new_crtc->base)
10453 continue;
10454
10455 if (encoder->base.crtc) {
10456 tmp_crtc = encoder->base.crtc;
10457
10458 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10459 }
10460
10461 if (encoder->new_crtc)
10462 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10463 }
10464
7668851f 10465 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10466 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10467 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10468 continue;
7e7d76c3 10469
7668851f 10470 if (!intel_crtc->new_enabled)
e2e1ed41 10471 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10472 else
10473 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10474 }
10475
e2e1ed41
DV		 10476
10477 /* set_mode is also used to update properties on life display pipes. */
10478 intel_crtc = to_intel_crtc(crtc);
7668851f 10479 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10480 *prepare_pipes |= 1 << intel_crtc->pipe;
10481
b6c5164d
DV		 10482 /*
10483 * For simplicity do a full modeset on any pipe where the output routing
10484 * changed. We could be more clever, but that would require us to be
10485 * more careful with calling the relevant encoder->mode_set functions.
10486 */
e2e1ed41
DV		 10487 if (*prepare_pipes)
10488 *modeset_pipes = *prepare_pipes;
10489
10490 /* ... and mask these out. */
10491 *modeset_pipes &= ~(*disable_pipes);
10492 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10493
10494 /*
10495 * HACK: We don't (yet) fully support global modesets. intel_set_config
10496 * obies this rule, but the modeset restore mode of
10497 * intel_modeset_setup_hw_state does not.
10498 */
10499 *modeset_pipes &= 1 << intel_crtc->pipe;
10500 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10501
10502 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10503 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10504}
79e53945 10505
ea9d758d 10506static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10507{
ea9d758d 10508 struct drm_encoder *encoder;
f6e5b160 10509 struct drm_device *dev = crtc->dev;
f6e5b160 10510
ea9d758d
DV		 10511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10512 if (encoder->crtc == crtc)
10513 return true;
10514
10515 return false;
10516}
10517
10518static void
10519intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10520{
ba41c0de 10521 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10522 struct intel_encoder *intel_encoder;
10523 struct intel_crtc *intel_crtc;
10524 struct drm_connector *connector;
10525
ba41c0de
DV		 10526 intel_shared_dpll_commit(dev_priv);
10527
b2784e15 10528 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10529 if (!intel_encoder->base.crtc)
10530 continue;
10531
10532 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10533
10534 if (prepare_pipes & (1 << intel_crtc->pipe))
10535 intel_encoder->connectors_active = false;
10536 }
10537
10538 intel_modeset_commit_output_state(dev);
10539
7668851f 10540 /* Double check state. */
d3fcc808 10541 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10542 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10543 WARN_ON(intel_crtc->new_config &&
6e3c9717 10544 intel_crtc->new_config != intel_crtc->config);
83d65738 10545 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10546 }
10547
10548 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10549 if (!connector->encoder || !connector->encoder->crtc)
10550 continue;
10551
10552 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10553
10554 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10555 struct drm_property *dpms_property =
10556 dev->mode_config.dpms_property;
10557
ea9d758d 10558 connector->dpms = DRM_MODE_DPMS_ON;
662595df 10559 drm_object_property_set_value(&connector->base,
68d34720
DV		 10560 dpms_property,
10561 DRM_MODE_DPMS_ON);
ea9d758d
DV		 10562
10563 intel_encoder = to_intel_encoder(connector->encoder);
10564 intel_encoder->connectors_active = true;
10565 }
10566 }
10567
10568}
10569
3bd26263 10570static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 10571{
3bd26263 10572 int diff;
f1f644dc
JB		 10573
10574 if (clock1 == clock2)
10575 return true;
10576
10577 if (!clock1 || !clock2)
10578 return false;
10579
10580 diff = abs(clock1 - clock2);
10581
10582 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10583 return true;
10584
10585 return false;
10586}
10587
25c5b266
DV		 10588#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10589 list_for_each_entry((intel_crtc), \
10590 &(dev)->mode_config.crtc_list, \
10591 base.head) \
0973f18f 10592 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 10593
0e8ffe1b 10594static bool
2fa2fe9a 10595intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 10596 struct intel_crtc_state *current_config,
10597 struct intel_crtc_state *pipe_config)
0e8ffe1b 10598{
66e985c0
DV		 10599#define PIPE_CONF_CHECK_X(name) \
10600 if (current_config->name != pipe_config->name) { \
10601 DRM_ERROR("mismatch in " #name " " \
10602 "(expected 0x%08x, found 0x%08x)\n", \
10603 current_config->name, \
10604 pipe_config->name); \
10605 return false; \
10606 }
10607
08a24034
DV		 10608#define PIPE_CONF_CHECK_I(name) \
10609 if (current_config->name != pipe_config->name) { \
10610 DRM_ERROR("mismatch in " #name " " \
10611 "(expected %i, found %i)\n", \
10612 current_config->name, \
10613 pipe_config->name); \
10614 return false; \
88adfff1
DV		 10615 }
10616
b95af8be
VK		 10617/* This is required for BDW+ where there is only one set of registers for
10618 * switching between high and low RR.
10619 * This macro can be used whenever a comparison has to be made between one
10620 * hw state and multiple sw state variables.
10621 */
10622#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10623 if ((current_config->name != pipe_config->name) && \
10624 (current_config->alt_name != pipe_config->name)) { \
10625 DRM_ERROR("mismatch in " #name " " \
10626 "(expected %i or %i, found %i)\n", \
10627 current_config->name, \
10628 current_config->alt_name, \
10629 pipe_config->name); \
10630 return false; \
10631 }
10632
1bd1bd80
DV		 10633#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10634 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 10635 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 10636 "(expected %i, found %i)\n", \
10637 current_config->name & (mask), \
10638 pipe_config->name & (mask)); \
10639 return false; \
10640 }
10641
5e550656
VS		 10642#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10643 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10644 DRM_ERROR("mismatch in " #name " " \
10645 "(expected %i, found %i)\n", \
10646 current_config->name, \
10647 pipe_config->name); \
10648 return false; \
10649 }
10650
bb760063
DV		 10651#define PIPE_CONF_QUIRK(quirk) \
10652 ((current_config->quirks | pipe_config->quirks) & (quirk))
10653
eccb140b
DV		 10654 PIPE_CONF_CHECK_I(cpu_transcoder);
10655
08a24034
DV		 10656 PIPE_CONF_CHECK_I(has_pch_encoder);
10657 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 10658 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10659 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10660 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10661 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10662 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 10663
eb14cb74 10664 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 10665
10666 if (INTEL_INFO(dev)->gen < 8) {
10667 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10668 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10669 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10670 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10671 PIPE_CONF_CHECK_I(dp_m_n.tu);
10672
10673 if (current_config->has_drrs) {
10674 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10675 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10676 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10677 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10678 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10679 }
10680 } else {
10681 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10682 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10683 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10684 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10685 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10686 }
eb14cb74 10687
2d112de7
ACO		 10688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10693 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 10694
2d112de7
ACO		 10695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10698 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10699 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10700 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 10701
c93f54cf 10702 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 10703 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 10704 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10705 IS_VALLEYVIEW(dev))
10706 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 10707 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 10708
9ed109a7
DV		 10709 PIPE_CONF_CHECK_I(has_audio);
10710
2d112de7 10711 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 10712 DRM_MODE_FLAG_INTERLACE);
10713
bb760063 10714 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 10715 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10716 DRM_MODE_FLAG_PHSYNC);
2d112de7 10717 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10718 DRM_MODE_FLAG_NHSYNC);
2d112de7 10719 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10720 DRM_MODE_FLAG_PVSYNC);
2d112de7 10721 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 10722 DRM_MODE_FLAG_NVSYNC);
10723 }
045ac3b5 10724
37327abd
VS		 10725 PIPE_CONF_CHECK_I(pipe_src_w);
10726 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 10727
9953599b
DV		 10728 /*
10729 * FIXME: BIOS likes to set up a cloned config with lvds+external
10730 * screen. Since we don't yet re-compute the pipe config when moving
10731 * just the lvds port away to another pipe the sw tracking won't match.
10732 *
10733 * Proper atomic modesets with recomputed global state will fix this.
10734 * Until then just don't check gmch state for inherited modes.
10735 */
10736 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10737 PIPE_CONF_CHECK_I(gmch_pfit.control);
10738 /* pfit ratios are autocomputed by the hw on gen4+ */
10739 if (INTEL_INFO(dev)->gen < 4)
10740 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10741 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10742 }
10743
fd4daa9c
CW		 10744 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10745 if (current_config->pch_pfit.enabled) {
10746 PIPE_CONF_CHECK_I(pch_pfit.pos);
10747 PIPE_CONF_CHECK_I(pch_pfit.size);
10748 }
2fa2fe9a 10749
e59150dc
JB		 10750 /* BDW+ don't expose a synchronous way to read the state */
10751 if (IS_HASWELL(dev))
10752 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 10753
282740f7
VS		 10754 PIPE_CONF_CHECK_I(double_wide);
10755
26804afd
DV		 10756 PIPE_CONF_CHECK_X(ddi_pll_sel);
10757
c0d43d62 10758 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 10759 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 10760 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 10761 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10762 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 10763 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 10764 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10765 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10766 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 10767
42571aef
VS		 10768 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10769 PIPE_CONF_CHECK_I(pipe_bpp);
10770
2d112de7 10771 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 10772 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 10773
66e985c0 10774#undef PIPE_CONF_CHECK_X
08a24034 10775#undef PIPE_CONF_CHECK_I
b95af8be 10776#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 10777#undef PIPE_CONF_CHECK_FLAGS
5e550656 10778#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 10779#undef PIPE_CONF_QUIRK
88adfff1 10780
0e8ffe1b
DV		 10781 return true;
10782}
10783
08db6652
DL		 10784static void check_wm_state(struct drm_device *dev)
10785{
10786 struct drm_i915_private *dev_priv = dev->dev_private;
10787 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10788 struct intel_crtc *intel_crtc;
10789 int plane;
10790
10791 if (INTEL_INFO(dev)->gen < 9)
10792 return;
10793
10794 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10795 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10796
10797 for_each_intel_crtc(dev, intel_crtc) {
10798 struct skl_ddb_entry *hw_entry, *sw_entry;
10799 const enum pipe pipe = intel_crtc->pipe;
10800
10801 if (!intel_crtc->active)
10802 continue;
10803
10804 /* planes */
dd740780 10805 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 10806 hw_entry = &hw_ddb.plane[pipe][plane];
10807 sw_entry = &sw_ddb->plane[pipe][plane];
10808
10809 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10810 continue;
10811
10812 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10813 "(expected (%u,%u), found (%u,%u))\n",
10814 pipe_name(pipe), plane + 1,
10815 sw_entry->start, sw_entry->end,
10816 hw_entry->start, hw_entry->end);
10817 }
10818
10819 /* cursor */
10820 hw_entry = &hw_ddb.cursor[pipe];
10821 sw_entry = &sw_ddb->cursor[pipe];
10822
10823 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10824 continue;
10825
10826 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10827 "(expected (%u,%u), found (%u,%u))\n",
10828 pipe_name(pipe),
10829 sw_entry->start, sw_entry->end,
10830 hw_entry->start, hw_entry->end);
10831 }
10832}
10833
91d1b4bd
DV		 10834static void
10835check_connector_state(struct drm_device *dev)
8af6cf88 10836{
8af6cf88
DV		 10837 struct intel_connector *connector;
10838
3a3371ff 10839 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 10840 /* This also checks the encoder/connector hw state with the
10841 * ->get_hw_state callbacks. */
10842 intel_connector_check_state(connector);
10843
e2c719b7 10844 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 10845 "connector's staged encoder doesn't match current encoder\n");
10846 }
91d1b4bd
DV		 10847}
10848
10849static void
10850check_encoder_state(struct drm_device *dev)
10851{
10852 struct intel_encoder *encoder;
10853 struct intel_connector *connector;
8af6cf88 10854
b2784e15 10855 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 10856 bool enabled = false;
10857 bool active = false;
10858 enum pipe pipe, tracked_pipe;
10859
10860 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10861 encoder->base.base.id,
8e329a03 10862 encoder->base.name);
8af6cf88 10863
e2c719b7 10864 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 10865 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 10866 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 10867 "encoder's active_connectors set, but no crtc\n");
10868
3a3371ff 10869 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 10870 if (connector->base.encoder != &encoder->base)
10871 continue;
10872 enabled = true;
10873 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10874 active = true;
10875 }
0e32b39c
DA		 10876 /*
10877 * for MST connectors if we unplug the connector is gone
10878 * away but the encoder is still connected to a crtc
10879 * until a modeset happens in response to the hotplug.
10880 */
10881 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10882 continue;
10883
e2c719b7 10884 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 10885 "encoder's enabled state mismatch "
10886 "(expected %i, found %i)\n",
10887 !!encoder->base.crtc, enabled);
e2c719b7 10888 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 10889 "active encoder with no crtc\n");
10890
e2c719b7 10891 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 10892 "encoder's computed active state doesn't match tracked active state "
10893 "(expected %i, found %i)\n", active, encoder->connectors_active);
10894
10895 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 10896 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 10897 "encoder's hw state doesn't match sw tracking "
10898 "(expected %i, found %i)\n",
10899 encoder->connectors_active, active);
10900
10901 if (!encoder->base.crtc)
10902 continue;
10903
10904 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 10905 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 10906 "active encoder's pipe doesn't match"
10907 "(expected %i, found %i)\n",
10908 tracked_pipe, pipe);
10909
10910 }
91d1b4bd
DV		 10911}
10912
10913static void
10914check_crtc_state(struct drm_device *dev)
10915{
fbee40df 10916 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 10917 struct intel_crtc *crtc;
10918 struct intel_encoder *encoder;
5cec258b 10919 struct intel_crtc_state pipe_config;
8af6cf88 10920
d3fcc808 10921 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 10922 bool enabled = false;
10923 bool active = false;
10924
045ac3b5
JB		 10925 memset(&pipe_config, 0, sizeof(pipe_config));
10926
8af6cf88
DV		 10927 DRM_DEBUG_KMS("[CRTC:%d]\n",
10928 crtc->base.base.id);
10929
83d65738 10930 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 10931 "active crtc, but not enabled in sw tracking\n");
10932
b2784e15 10933 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 10934 if (encoder->base.crtc != &crtc->base)
10935 continue;
10936 enabled = true;
10937 if (encoder->connectors_active)
10938 active = true;
10939 }
6c49f241 10940
e2c719b7 10941 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 10942 "crtc's computed active state doesn't match tracked active state "
10943 "(expected %i, found %i)\n", active, crtc->active);
83d65738 10944 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 10945 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 10946 "(expected %i, found %i)\n", enabled,
10947 crtc->base.state->enable);
8af6cf88 10948
0e8ffe1b
DV		 10949 active = dev_priv->display.get_pipe_config(crtc,
10950 &pipe_config);
d62cf62a 10951
b6b5d049
VS		 10952 /* hw state is inconsistent with the pipe quirk */
10953 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10954 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 10955 active = crtc->active;
10956
b2784e15 10957 for_each_intel_encoder(dev, encoder) {
3eaba51c 10958 enum pipe pipe;
6c49f241
DV		 10959 if (encoder->base.crtc != &crtc->base)
10960 continue;
1d37b689 10961 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 10962 encoder->get_config(encoder, &pipe_config);
10963 }
10964
e2c719b7 10965 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 10966 "crtc active state doesn't match with hw state "
10967 "(expected %i, found %i)\n", crtc->active, active);
10968
c0b03411 10969 if (active &&
6e3c9717 10970 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 10971 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 10972 intel_dump_pipe_config(crtc, &pipe_config,
10973 "[hw state]");
6e3c9717 10974 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 10975 "[sw state]");
10976 }
8af6cf88
DV		 10977 }
10978}
10979
91d1b4bd
DV		 10980static void
10981check_shared_dpll_state(struct drm_device *dev)
10982{
fbee40df 10983 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 10984 struct intel_crtc *crtc;
10985 struct intel_dpll_hw_state dpll_hw_state;
10986 int i;
5358901f
DV		 10987
10988 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10989 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10990 int enabled_crtcs = 0, active_crtcs = 0;
10991 bool active;
10992
10993 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10994
10995 DRM_DEBUG_KMS("%s\n", pll->name);
10996
10997 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10998
e2c719b7 10999 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11000 "more active pll users than references: %i vs %i\n",
3e369b76 11001 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11002 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11003 "pll in active use but not on in sw tracking\n");
e2c719b7 11004 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11005 "pll in on but not on in use in sw tracking\n");
e2c719b7 11006 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11007 "pll on state mismatch (expected %i, found %i)\n",
11008 pll->on, active);
11009
d3fcc808 11010 for_each_intel_crtc(dev, crtc) {
83d65738 11011 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11012 enabled_crtcs++;
11013 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11014 active_crtcs++;
11015 }
e2c719b7 11016 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11017 "pll active crtcs mismatch (expected %i, found %i)\n",
11018 pll->active, active_crtcs);
e2c719b7 11019 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11020 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11021 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11022
e2c719b7 11023 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11024 sizeof(dpll_hw_state)),
11025 "pll hw state mismatch\n");
5358901f 11026 }
8af6cf88
DV		 11027}
11028
91d1b4bd
DV		 11029void
11030intel_modeset_check_state(struct drm_device *dev)
11031{
08db6652 11032 check_wm_state(dev);
91d1b4bd
DV		 11033 check_connector_state(dev);
11034 check_encoder_state(dev);
11035 check_crtc_state(dev);
11036 check_shared_dpll_state(dev);
11037}
11038
5cec258b 11039void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11040 int dotclock)
11041{
11042 /*
11043 * FDI already provided one idea for the dotclock.
11044 * Yell if the encoder disagrees.
11045 */
2d112de7 11046 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11047 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11048 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11049}
11050
80715b2f
VS		 11051static void update_scanline_offset(struct intel_crtc *crtc)
11052{
11053 struct drm_device *dev = crtc->base.dev;
11054
11055 /*
11056 * The scanline counter increments at the leading edge of hsync.
11057 *
11058 * On most platforms it starts counting from vtotal-1 on the
11059 * first active line. That means the scanline counter value is
11060 * always one less than what we would expect. Ie. just after
11061 * start of vblank, which also occurs at start of hsync (on the
11062 * last active line), the scanline counter will read vblank_start-1.
11063 *
11064 * On gen2 the scanline counter starts counting from 1 instead
11065 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11066 * to keep the value positive), instead of adding one.
11067 *
11068 * On HSW+ the behaviour of the scanline counter depends on the output
11069 * type. For DP ports it behaves like most other platforms, but on HDMI
11070 * there's an extra 1 line difference. So we need to add two instead of
11071 * one to the value.
11072 */
11073 if (IS_GEN2(dev)) {
6e3c9717 11074 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11075 int vtotal;
11076
11077 vtotal = mode->crtc_vtotal;
11078 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11079 vtotal /= 2;
11080
11081 crtc->scanline_offset = vtotal - 1;
11082 } else if (HAS_DDI(dev) &&
409ee761 11083 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11084 crtc->scanline_offset = 2;
11085 } else
11086 crtc->scanline_offset = 1;
11087}
11088
5cec258b 11089static struct intel_crtc_state *
7f27126e
JB		 11090intel_modeset_compute_config(struct drm_crtc *crtc,
11091 struct drm_display_mode *mode,
11092 struct drm_framebuffer *fb,
11093 unsigned *modeset_pipes,
11094 unsigned *prepare_pipes,
11095 unsigned *disable_pipes)
11096{
5cec258b 11097 struct intel_crtc_state *pipe_config = NULL;
7f27126e
JB		 11098
11099 intel_modeset_affected_pipes(crtc, modeset_pipes,
11100 prepare_pipes, disable_pipes);
11101
11102 if ((*modeset_pipes) == 0)
11103 goto out;
11104
11105 /*
11106 * Note this needs changes when we start tracking multiple modes
11107 * and crtcs. At that point we'll need to compute the whole config
11108 * (i.e. one pipe_config for each crtc) rather than just the one
11109 * for this crtc.
11110 */
11111 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11112 if (IS_ERR(pipe_config)) {
11113 goto out;
11114 }
11115 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11116 "[modeset]");
7f27126e
JB		 11117
11118out:
11119 return pipe_config;
11120}
11121
ed6739ef
ACO		 11122static int __intel_set_mode_setup_plls(struct drm_device *dev,
11123 unsigned modeset_pipes,
11124 unsigned disable_pipes)
11125{
11126 struct drm_i915_private *dev_priv = to_i915(dev);
11127 unsigned clear_pipes = modeset_pipes | disable_pipes;
11128 struct intel_crtc *intel_crtc;
11129 int ret = 0;
11130
11131 if (!dev_priv->display.crtc_compute_clock)
11132 return 0;
11133
11134 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11135 if (ret)
11136 goto done;
11137
11138 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11139 struct intel_crtc_state *state = intel_crtc->new_config;
11140 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11141 state);
11142 if (ret) {
11143 intel_shared_dpll_abort_config(dev_priv);
11144 goto done;
11145 }
11146 }
11147
11148done:
11149 return ret;
11150}
11151
f30da187
DV		 11152static int __intel_set_mode(struct drm_crtc *crtc,
11153 struct drm_display_mode *mode,
7f27126e 11154 int x, int y, struct drm_framebuffer *fb,
5cec258b 11155 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11156 unsigned modeset_pipes,
11157 unsigned prepare_pipes,
11158 unsigned disable_pipes)
a6778b3c
DV		 11159{
11160 struct drm_device *dev = crtc->dev;
fbee40df 11161 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11162 struct drm_display_mode *saved_mode;
25c5b266 11163 struct intel_crtc *intel_crtc;
c0c36b94 11164 int ret = 0;
a6778b3c 11165
4b4b9238 11166 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11167 if (!saved_mode)
11168 return -ENOMEM;
a6778b3c 11169
3ac18232 11170 *saved_mode = crtc->mode;
a6778b3c 11171
b9950a13
VS		 11172 if (modeset_pipes)
11173 to_intel_crtc(crtc)->new_config = pipe_config;
11174
30a970c6
JB		 11175 /*
11176 * See if the config requires any additional preparation, e.g.
11177 * to adjust global state with pipes off. We need to do this
11178 * here so we can get the modeset_pipe updated config for the new
11179 * mode set on this crtc. For other crtcs we need to use the
11180 * adjusted_mode bits in the crtc directly.
11181 */
c164f833 11182 if (IS_VALLEYVIEW(dev)) {
2f2d7aa1 11183 valleyview_modeset_global_pipes(dev, &prepare_pipes);
30a970c6 11184
c164f833
VS		 11185 /* may have added more to prepare_pipes than we should */
11186 prepare_pipes &= ~disable_pipes;
11187 }
11188
ed6739ef
ACO		 11189 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11190 if (ret)
11191 goto done;
8bd31e67 11192
460da916
DV		 11193 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11194 intel_crtc_disable(&intel_crtc->base);
11195
ea9d758d 11196 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11197 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11198 dev_priv->display.crtc_disable(&intel_crtc->base);
11199 }
a6778b3c 11200
6c4c86f5
DV		 11201 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11202 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11203 *
11204 * Note we'll need to fix this up when we start tracking multiple
11205 * pipes; here we assume a single modeset_pipe and only track the
11206 * single crtc and mode.
f6e5b160 11207 */
b8cecdf5 11208 if (modeset_pipes) {
25c5b266 11209 crtc->mode = *mode;
b8cecdf5
DV		 11210 /* mode_set/enable/disable functions rely on a correct pipe
11211 * config. */
f5de6e07 11212 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11213
11214 /*
11215 * Calculate and store various constants which
11216 * are later needed by vblank and swap-completion
11217 * timestamping. They are derived from true hwmode.
11218 */
11219 drm_calc_timestamping_constants(crtc,
2d112de7 11220 &pipe_config->base.adjusted_mode);
b8cecdf5 11221 }
7758a113 11222
ea9d758d
DV		 11223 /* Only after disabling all output pipelines that will be changed can we
11224 * update the the output configuration. */
11225 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11226
50f6e502 11227 modeset_update_crtc_power_domains(dev);
47fab737 11228
a6778b3c
DV		 11229 /* Set up the DPLL and any encoders state that needs to adjust or depend
11230 * on the DPLL.
f6e5b160 11231 */
25c5b266 11232 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11233 struct drm_plane *primary = intel_crtc->base.primary;
11234 int vdisplay, hdisplay;
4c10794f 11235
455a6808
GP		 11236 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11237 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11238 fb, 0, 0,
11239 hdisplay, vdisplay,
11240 x << 16, y << 16,
11241 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11242 }
11243
11244 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11245 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11246 update_scanline_offset(intel_crtc);
11247
25c5b266 11248 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11249 }
a6778b3c 11250
a6778b3c
DV		 11251 /* FIXME: add subpixel order */
11252done:
83d65738 11253 if (ret && crtc->state->enable)
3ac18232 11254 crtc->mode = *saved_mode;
a6778b3c 11255
3ac18232 11256 kfree(saved_mode);
a6778b3c 11257 return ret;
f6e5b160
CW		 11258}
11259
7f27126e
JB		 11260static int intel_set_mode_pipes(struct drm_crtc *crtc,
11261 struct drm_display_mode *mode,
11262 int x, int y, struct drm_framebuffer *fb,
5cec258b 11263 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11264 unsigned modeset_pipes,
11265 unsigned prepare_pipes,
11266 unsigned disable_pipes)
f30da187
DV		 11267{
11268 int ret;
11269
7f27126e
JB		 11270 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11271 prepare_pipes, disable_pipes);
f30da187
DV		 11272
11273 if (ret == 0)
11274 intel_modeset_check_state(crtc->dev);
11275
11276 return ret;
11277}
11278
7f27126e
JB		 11279static int intel_set_mode(struct drm_crtc *crtc,
11280 struct drm_display_mode *mode,
11281 int x, int y, struct drm_framebuffer *fb)
11282{
5cec258b 11283 struct intel_crtc_state *pipe_config;
7f27126e
JB		 11284 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11285
11286 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11287 &modeset_pipes,
11288 &prepare_pipes,
11289 &disable_pipes);
11290
11291 if (IS_ERR(pipe_config))
11292 return PTR_ERR(pipe_config);
11293
11294 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11295 modeset_pipes, prepare_pipes,
11296 disable_pipes);
11297}
11298
c0c36b94
CW		 11299void intel_crtc_restore_mode(struct drm_crtc *crtc)
11300{
f4510a27 11301 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
c0c36b94
CW		 11302}
11303
25c5b266
DV		 11304#undef for_each_intel_crtc_masked
11305
d9e55608
DV		 11306static void intel_set_config_free(struct intel_set_config *config)
11307{
11308 if (!config)
11309 return;
11310
1aa4b628
DV		 11311 kfree(config->save_connector_encoders);
11312 kfree(config->save_encoder_crtcs);
7668851f 11313 kfree(config->save_crtc_enabled);
d9e55608
DV		 11314 kfree(config);
11315}
11316
85f9eb71
DV		 11317static int intel_set_config_save_state(struct drm_device *dev,
11318 struct intel_set_config *config)
11319{
7668851f 11320 struct drm_crtc *crtc;
85f9eb71
DV		 11321 struct drm_encoder *encoder;
11322 struct drm_connector *connector;
11323 int count;
11324
7668851f
VS		 11325 config->save_crtc_enabled =
11326 kcalloc(dev->mode_config.num_crtc,
11327 sizeof(bool), GFP_KERNEL);
11328 if (!config->save_crtc_enabled)
11329 return -ENOMEM;
11330
1aa4b628
DV		 11331 config->save_encoder_crtcs =
11332 kcalloc(dev->mode_config.num_encoder,
11333 sizeof(struct drm_crtc *), GFP_KERNEL);
11334 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11335 return -ENOMEM;
11336
1aa4b628
DV		 11337 config->save_connector_encoders =
11338 kcalloc(dev->mode_config.num_connector,
11339 sizeof(struct drm_encoder *), GFP_KERNEL);
11340 if (!config->save_connector_encoders)
85f9eb71
DV		 11341 return -ENOMEM;
11342
11343 /* Copy data. Note that driver private data is not affected.
11344 * Should anything bad happen only the expected state is
11345 * restored, not the drivers personal bookkeeping.
11346 */
7668851f 11347 count = 0;
70e1e0ec 11348 for_each_crtc(dev, crtc) {
83d65738 11349 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11350 }
11351
85f9eb71
DV		 11352 count = 0;
11353 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11354 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11355 }
11356
11357 count = 0;
11358 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11359 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11360 }
11361
11362 return 0;
11363}
11364
11365static void intel_set_config_restore_state(struct drm_device *dev,
11366 struct intel_set_config *config)
11367{
7668851f 11368 struct intel_crtc *crtc;
9a935856
DV		 11369 struct intel_encoder *encoder;
11370 struct intel_connector *connector;
85f9eb71
DV		 11371 int count;
11372
7668851f 11373 count = 0;
d3fcc808 11374 for_each_intel_crtc(dev, crtc) {
7668851f 11375 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11376
11377 if (crtc->new_enabled)
6e3c9717 11378 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11379 else
11380 crtc->new_config = NULL;
7668851f
VS		 11381 }
11382
85f9eb71 11383 count = 0;
b2784e15 11384 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11385 encoder->new_crtc =
11386 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11387 }
11388
11389 count = 0;
3a3371ff 11390 for_each_intel_connector(dev, connector) {
9a935856
DV		 11391 connector->new_encoder =
11392 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11393 }
11394}
11395
e3de42b6 11396static bool
2e57f47d 11397is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11398{
11399 int i;
11400
2e57f47d
CW		 11401 if (set->num_connectors == 0)
11402 return false;
11403
11404 if (WARN_ON(set->connectors == NULL))
11405 return false;
11406
11407 for (i = 0; i < set->num_connectors; i++)
11408 if (set->connectors[i]->encoder &&
11409 set->connectors[i]->encoder->crtc == set->crtc &&
11410 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11411 return true;
11412
11413 return false;
11414}
11415
5e2b584e
DV		 11416static void
11417intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11418 struct intel_set_config *config)
11419{
11420
11421 /* We should be able to check here if the fb has the same properties
11422 * and then just flip_or_move it */
2e57f47d
CW		 11423 if (is_crtc_connector_off(set)) {
11424 config->mode_changed = true;
f4510a27 11425 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11426 /*
11427 * If we have no fb, we can only flip as long as the crtc is
11428 * active, otherwise we need a full mode set. The crtc may
11429 * be active if we've only disabled the primary plane, or
11430 * in fastboot situations.
11431 */
f4510a27 11432 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11433 struct intel_crtc *intel_crtc =
11434 to_intel_crtc(set->crtc);
11435
3b150f08 11436 if (intel_crtc->active) {
319d9827
JB		 11437 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11438 config->fb_changed = true;
11439 } else {
11440 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11441 config->mode_changed = true;
11442 }
5e2b584e
DV		 11443 } else if (set->fb == NULL) {
11444 config->mode_changed = true;
72f4901e 11445 } else if (set->fb->pixel_format !=
f4510a27 11446 set->crtc->primary->fb->pixel_format) {
5e2b584e 11447 config->mode_changed = true;
e3de42b6 11448 } else {
5e2b584e 11449 config->fb_changed = true;
e3de42b6 11450 }
5e2b584e
DV		 11451 }
11452
835c5873 11453 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11454 config->fb_changed = true;
11455
11456 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11457 DRM_DEBUG_KMS("modes are different, full mode set\n");
11458 drm_mode_debug_printmodeline(&set->crtc->mode);
11459 drm_mode_debug_printmodeline(set->mode);
11460 config->mode_changed = true;
11461 }
a1d95703
CW		 11462
11463 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11464 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 11465}
11466
2e431051 11467static int
9a935856
DV		 11468intel_modeset_stage_output_state(struct drm_device *dev,
11469 struct drm_mode_set *set,
11470 struct intel_set_config *config)
50f56119 11471{
9a935856
DV		 11472 struct intel_connector *connector;
11473 struct intel_encoder *encoder;
7668851f 11474 struct intel_crtc *crtc;
f3f08572 11475 int ro;
50f56119 11476
9abdda74 11477 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 11478 * of connectors. For paranoia, double-check this. */
11479 WARN_ON(!set->fb && (set->num_connectors != 0));
11480 WARN_ON(set->fb && (set->num_connectors == 0));
11481
3a3371ff 11482 for_each_intel_connector(dev, connector) {
9a935856
DV		 11483 /* Otherwise traverse passed in connector list and get encoders
11484 * for them. */
50f56119 11485 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11486 if (set->connectors[ro] == &connector->base) {
0e32b39c 11487 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 11488 break;
11489 }
11490 }
11491
9a935856
DV		 11492 /* If we disable the crtc, disable all its connectors. Also, if
11493 * the connector is on the changing crtc but not on the new
11494 * connector list, disable it. */
11495 if ((!set->fb || ro == set->num_connectors) &&
11496 connector->base.encoder &&
11497 connector->base.encoder->crtc == set->crtc) {
11498 connector->new_encoder = NULL;
11499
11500 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11501 connector->base.base.id,
c23cc417 11502 connector->base.name);
9a935856
DV		 11503 }
11504
11505
11506 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 11507 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 11508 config->mode_changed = true;
50f56119
DV		 11509 }
11510 }
9a935856 11511 /* connector->new_encoder is now updated for all connectors. */
50f56119 11512
9a935856 11513 /* Update crtc of enabled connectors. */
3a3371ff 11514 for_each_intel_connector(dev, connector) {
7668851f
VS		 11515 struct drm_crtc *new_crtc;
11516
9a935856 11517 if (!connector->new_encoder)
50f56119
DV		 11518 continue;
11519
9a935856 11520 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 11521
11522 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11523 if (set->connectors[ro] == &connector->base)
50f56119
DV		 11524 new_crtc = set->crtc;
11525 }
11526
11527 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 11528 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11529 new_crtc)) {
5e2b584e 11530 return -EINVAL;
50f56119 11531 }
0e32b39c 11532 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856
DV		 11533
11534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11535 connector->base.base.id,
c23cc417 11536 connector->base.name,
9a935856
DV		 11537 new_crtc->base.id);
11538 }
11539
11540 /* Check for any encoders that needs to be disabled. */
b2784e15 11541 for_each_intel_encoder(dev, encoder) {
5a65f358 11542 int num_connectors = 0;
3a3371ff 11543 for_each_intel_connector(dev, connector) {
9a935856
DV		 11544 if (connector->new_encoder == encoder) {
11545 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 11546 num_connectors++;
9a935856
DV		 11547 }
11548 }
5a65f358
PZ		 11549
11550 if (num_connectors == 0)
11551 encoder->new_crtc = NULL;
11552 else if (num_connectors > 1)
11553 return -EINVAL;
11554
9a935856
DV		 11555 /* Only now check for crtc changes so we don't miss encoders
11556 * that will be disabled. */
11557 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 11558 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 11559 config->mode_changed = true;
50f56119
DV		 11560 }
11561 }
9a935856 11562 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 11563 for_each_intel_connector(dev, connector) {
0e32b39c
DA		 11564 if (connector->new_encoder)
11565 if (connector->new_encoder != connector->encoder)
11566 connector->encoder = connector->new_encoder;
11567 }
d3fcc808 11568 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 11569 crtc->new_enabled = false;
11570
b2784e15 11571 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 11572 if (encoder->new_crtc == crtc) {
11573 crtc->new_enabled = true;
11574 break;
11575 }
11576 }
11577
83d65738 11578 if (crtc->new_enabled != crtc->base.state->enable) {
7668851f
VS		 11579 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11580 crtc->new_enabled ? "en" : "dis");
11581 config->mode_changed = true;
11582 }
7bd0a8e7
VS		 11583
11584 if (crtc->new_enabled)
6e3c9717 11585 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11586 else
11587 crtc->new_config = NULL;
7668851f
VS		 11588 }
11589
2e431051
DV		 11590 return 0;
11591}
11592
7d00a1f5
VS		 11593static void disable_crtc_nofb(struct intel_crtc *crtc)
11594{
11595 struct drm_device *dev = crtc->base.dev;
11596 struct intel_encoder *encoder;
11597 struct intel_connector *connector;
11598
11599 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11600 pipe_name(crtc->pipe));
11601
3a3371ff 11602 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 11603 if (connector->new_encoder &&
11604 connector->new_encoder->new_crtc == crtc)
11605 connector->new_encoder = NULL;
11606 }
11607
b2784e15 11608 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 11609 if (encoder->new_crtc == crtc)
11610 encoder->new_crtc = NULL;
11611 }
11612
11613 crtc->new_enabled = false;
7bd0a8e7 11614 crtc->new_config = NULL;
7d00a1f5
VS		 11615}
11616
2e431051
DV		 11617static int intel_crtc_set_config(struct drm_mode_set *set)
11618{
11619 struct drm_device *dev;
2e431051
DV		 11620 struct drm_mode_set save_set;
11621 struct intel_set_config *config;
5cec258b 11622 struct intel_crtc_state *pipe_config;
50f52756 11623 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 11624 int ret;
2e431051 11625
8d3e375e
DV		 11626 BUG_ON(!set);
11627 BUG_ON(!set->crtc);
11628 BUG_ON(!set->crtc->helper_private);
2e431051 11629
7e53f3a4
DV		 11630 /* Enforce sane interface api - has been abused by the fb helper. */
11631 BUG_ON(!set->mode && set->fb);
11632 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 11633
2e431051
DV		 11634 if (set->fb) {
11635 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11636 set->crtc->base.id, set->fb->base.id,
11637 (int)set->num_connectors, set->x, set->y);
11638 } else {
11639 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 11640 }
11641
11642 dev = set->crtc->dev;
11643
11644 ret = -ENOMEM;
11645 config = kzalloc(sizeof(*config), GFP_KERNEL);
11646 if (!config)
11647 goto out_config;
11648
11649 ret = intel_set_config_save_state(dev, config);
11650 if (ret)
11651 goto out_config;
11652
11653 save_set.crtc = set->crtc;
11654 save_set.mode = &set->crtc->mode;
11655 save_set.x = set->crtc->x;
11656 save_set.y = set->crtc->y;
f4510a27 11657 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 11658
11659 /* Compute whether we need a full modeset, only an fb base update or no
11660 * change at all. In the future we might also check whether only the
11661 * mode changed, e.g. for LVDS where we only change the panel fitter in
11662 * such cases. */
11663 intel_set_config_compute_mode_changes(set, config);
11664
9a935856 11665 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 11666 if (ret)
11667 goto fail;
11668
50f52756
JB		 11669 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11670 set->fb,
11671 &modeset_pipes,
11672 &prepare_pipes,
11673 &disable_pipes);
20664591 11674 if (IS_ERR(pipe_config)) {
6ac0483b 11675 ret = PTR_ERR(pipe_config);
50f52756 11676 goto fail;
20664591 11677 } else if (pipe_config) {
b9950a13 11678 if (pipe_config->has_audio !=
6e3c9717 11679 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 11680 config->mode_changed = true;
11681
af15d2ce
JB		 11682 /*
11683 * Note we have an issue here with infoframes: current code
11684 * only updates them on the full mode set path per hw
11685 * requirements. So here we should be checking for any
11686 * required changes and forcing a mode set.
11687 */
20664591 11688 }
50f52756
JB		 11689
11690 /* set_mode will free it in the mode_changed case */
11691 if (!config->mode_changed)
11692 kfree(pipe_config);
11693
1f9954d0
JB		 11694 intel_update_pipe_size(to_intel_crtc(set->crtc));
11695
5e2b584e 11696 if (config->mode_changed) {
50f52756
JB		 11697 ret = intel_set_mode_pipes(set->crtc, set->mode,
11698 set->x, set->y, set->fb, pipe_config,
11699 modeset_pipes, prepare_pipes,
11700 disable_pipes);
5e2b584e 11701 } else if (config->fb_changed) {
3b150f08 11702 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 11703 struct drm_plane *primary = set->crtc->primary;
11704 int vdisplay, hdisplay;
3b150f08 11705
455a6808
GP		 11706 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11707 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11708 0, 0, hdisplay, vdisplay,
11709 set->x << 16, set->y << 16,
11710 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 11711
11712 /*
11713 * We need to make sure the primary plane is re-enabled if it
11714 * has previously been turned off.
11715 */
11716 if (!intel_crtc->primary_enabled && ret == 0) {
11717 WARN_ON(!intel_crtc->active);
fdd508a6 11718 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 11719 }
11720
7ca51a3a
JB		 11721 /*
11722 * In the fastboot case this may be our only check of the
11723 * state after boot. It would be better to only do it on
11724 * the first update, but we don't have a nice way of doing that
11725 * (and really, set_config isn't used much for high freq page
11726 * flipping, so increasing its cost here shouldn't be a big
11727 * deal).
11728 */
d330a953 11729 if (i915.fastboot && ret == 0)
7ca51a3a 11730 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 11731 }
11732
2d05eae1 11733 if (ret) {
bf67dfeb
DV		 11734 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11735 set->crtc->base.id, ret);
50f56119 11736fail:
2d05eae1 11737 intel_set_config_restore_state(dev, config);
50f56119 11738
7d00a1f5
VS		 11739 /*
11740 * HACK: if the pipe was on, but we didn't have a framebuffer,
11741 * force the pipe off to avoid oopsing in the modeset code
11742 * due to fb==NULL. This should only happen during boot since
11743 * we don't yet reconstruct the FB from the hardware state.
11744 */
11745 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11746 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11747
2d05eae1
CW		 11748 /* Try to restore the config */
11749 if (config->mode_changed &&
11750 intel_set_mode(save_set.crtc, save_set.mode,
11751 save_set.x, save_set.y, save_set.fb))
11752 DRM_ERROR("failed to restore config after modeset failure\n");
11753 }
50f56119 11754
d9e55608
DV		 11755out_config:
11756 intel_set_config_free(config);
50f56119
DV		 11757 return ret;
11758}
f6e5b160
CW		 11759
11760static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 11761 .gamma_set = intel_crtc_gamma_set,
50f56119 11762 .set_config = intel_crtc_set_config,
f6e5b160
CW		 11763 .destroy = intel_crtc_destroy,
11764 .page_flip = intel_crtc_page_flip,
1356837e
MR		 11765 .atomic_duplicate_state = intel_crtc_duplicate_state,
11766 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 11767};
11768
5358901f
DV		 11769static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11770 struct intel_shared_dpll *pll,
11771 struct intel_dpll_hw_state *hw_state)
ee7b9f93 11772{
5358901f 11773 uint32_t val;
ee7b9f93 11774
f458ebbc 11775 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 11776 return false;
11777
5358901f 11778 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 11779 hw_state->dpll = val;
11780 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11781 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 11782
11783 return val & DPLL_VCO_ENABLE;
11784}
11785
15bdd4cf
DV		 11786static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11787 struct intel_shared_dpll *pll)
11788{
3e369b76
ACO		 11789 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11790 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 11791}
11792
e7b903d2
DV		 11793static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11794 struct intel_shared_dpll *pll)
11795{
e7b903d2 11796 /* PCH refclock must be enabled first */
89eff4be 11797 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 11798
3e369b76 11799 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 11800
11801 /* Wait for the clocks to stabilize. */
11802 POSTING_READ(PCH_DPLL(pll->id));
11803 udelay(150);
11804
11805 /* The pixel multiplier can only be updated once the
11806 * DPLL is enabled and the clocks are stable.
11807 *
11808 * So write it again.
11809 */
3e369b76 11810 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 11811 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11812 udelay(200);
11813}
11814
11815static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11816 struct intel_shared_dpll *pll)
11817{
11818 struct drm_device *dev = dev_priv->dev;
11819 struct intel_crtc *crtc;
e7b903d2
DV		 11820
11821 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 11822 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 11823 if (intel_crtc_to_shared_dpll(crtc) == pll)
11824 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 11825 }
11826
15bdd4cf
DV		 11827 I915_WRITE(PCH_DPLL(pll->id), 0);
11828 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11829 udelay(200);
11830}
11831
46edb027
DV		 11832static char *ibx_pch_dpll_names[] = {
11833 "PCH DPLL A",
11834 "PCH DPLL B",
11835};
11836
7c74ade1 11837static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 11838{
e7b903d2 11839 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 11840 int i;
11841
7c74ade1 11842 dev_priv->num_shared_dpll = 2;
ee7b9f93 11843
e72f9fbf 11844 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 11845 dev_priv->shared_dplls[i].id = i;
11846 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 11847 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 11848 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11849 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 11850 dev_priv->shared_dplls[i].get_hw_state =
11851 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 11852 }
11853}
11854
7c74ade1
DV		 11855static void intel_shared_dpll_init(struct drm_device *dev)
11856{
e7b903d2 11857 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 11858
9cd86933
DV		 11859 if (HAS_DDI(dev))
11860 intel_ddi_pll_init(dev);
11861 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 11862 ibx_pch_dpll_init(dev);
11863 else
11864 dev_priv->num_shared_dpll = 0;
11865
11866 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 11867}
11868
6beb8c23
MR		 11869/**
11870 * intel_prepare_plane_fb - Prepare fb for usage on plane
11871 * @plane: drm plane to prepare for
11872 * @fb: framebuffer to prepare for presentation
11873 *
11874 * Prepares a framebuffer for usage on a display plane. Generally this
11875 * involves pinning the underlying object and updating the frontbuffer tracking
11876 * bits. Some older platforms need special physical address handling for
11877 * cursor planes.
11878 *
11879 * Returns 0 on success, negative error code on failure.
11880 */
11881int
11882intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 11883 struct drm_framebuffer *fb,
11884 const struct drm_plane_state *new_state)
465c120c
MR		 11885{
11886 struct drm_device *dev = plane->dev;
6beb8c23
MR		 11887 struct intel_plane *intel_plane = to_intel_plane(plane);
11888 enum pipe pipe = intel_plane->pipe;
11889 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11890 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11891 unsigned frontbuffer_bits = 0;
11892 int ret = 0;
465c120c 11893
ea2c67bb 11894 if (!obj)
465c120c
MR		 11895 return 0;
11896
6beb8c23
MR		 11897 switch (plane->type) {
11898 case DRM_PLANE_TYPE_PRIMARY:
11899 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11900 break;
11901 case DRM_PLANE_TYPE_CURSOR:
11902 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11903 break;
11904 case DRM_PLANE_TYPE_OVERLAY:
11905 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11906 break;
11907 }
465c120c 11908
6beb8c23 11909 mutex_lock(&dev->struct_mutex);
465c120c 11910
6beb8c23
MR		 11911 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11912 INTEL_INFO(dev)->cursor_needs_physical) {
11913 int align = IS_I830(dev) ? 16 * 1024 : 256;
11914 ret = i915_gem_object_attach_phys(obj, align);
11915 if (ret)
11916 DRM_DEBUG_KMS("failed to attach phys object\n");
11917 } else {
11918 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11919 }
465c120c 11920
6beb8c23
MR		 11921 if (ret == 0)
11922 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 11923
4c34574f 11924 mutex_unlock(&dev->struct_mutex);
465c120c 11925
6beb8c23
MR		 11926 return ret;
11927}
11928
38f3ce3a
MR		 11929/**
11930 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11931 * @plane: drm plane to clean up for
11932 * @fb: old framebuffer that was on plane
11933 *
11934 * Cleans up a framebuffer that has just been removed from a plane.
11935 */
11936void
11937intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 11938 struct drm_framebuffer *fb,
11939 const struct drm_plane_state *old_state)
38f3ce3a
MR		 11940{
11941 struct drm_device *dev = plane->dev;
11942 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11943
11944 if (WARN_ON(!obj))
11945 return;
11946
11947 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11948 !INTEL_INFO(dev)->cursor_needs_physical) {
11949 mutex_lock(&dev->struct_mutex);
11950 intel_unpin_fb_obj(obj);
11951 mutex_unlock(&dev->struct_mutex);
11952 }
465c120c
MR		 11953}
11954
11955static int
3c692a41
GP		 11956intel_check_primary_plane(struct drm_plane *plane,
11957 struct intel_plane_state *state)
11958{
32b7eeec
MR		 11959 struct drm_device *dev = plane->dev;
11960 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 11961 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 11962 struct intel_crtc *intel_crtc;
2b875c22 11963 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 11964 struct drm_rect *dest = &state->dst;
11965 struct drm_rect *src = &state->src;
11966 const struct drm_rect *clip = &state->clip;
465c120c
MR		 11967 int ret;
11968
ea2c67bb
MR		 11969 crtc = crtc ? crtc : plane->crtc;
11970 intel_crtc = to_intel_crtc(crtc);
11971
c59cb179
MR		 11972 ret = drm_plane_helper_check_update(plane, crtc, fb,
11973 src, dest, clip,
11974 DRM_PLANE_HELPER_NO_SCALING,
11975 DRM_PLANE_HELPER_NO_SCALING,
11976 false, true, &state->visible);
11977 if (ret)
11978 return ret;
465c120c 11979
32b7eeec
MR		 11980 if (intel_crtc->active) {
11981 intel_crtc->atomic.wait_for_flips = true;
11982
11983 /*
11984 * FBC does not work on some platforms for rotated
11985 * planes, so disable it when rotation is not 0 and
11986 * update it when rotation is set back to 0.
11987 *
11988 * FIXME: This is redundant with the fbc update done in
11989 * the primary plane enable function except that that
11990 * one is done too late. We eventually need to unify
11991 * this.
11992 */
11993 if (intel_crtc->primary_enabled &&
11994 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 11995 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 11996 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 11997 intel_crtc->atomic.disable_fbc = true;
11998 }
11999
12000 if (state->visible) {
12001 /*
12002 * BDW signals flip done immediately if the plane
12003 * is disabled, even if the plane enable is already
12004 * armed to occur at the next vblank :(
12005 */
12006 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12007 intel_crtc->atomic.wait_vblank = true;
12008 }
12009
12010 intel_crtc->atomic.fb_bits |=
12011 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12012
12013 intel_crtc->atomic.update_fbc = true;
0fda6568
TU		 12014
12015 /* Update watermarks on tiling changes. */
12016 if (!plane->state->fb || !state->base.fb ||
12017 plane->state->fb->modifier[0] !=
12018 state->base.fb->modifier[0])
12019 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12020 }
12021
14af293f
GP		 12022 return 0;
12023}
12024
12025static void
12026intel_commit_primary_plane(struct drm_plane *plane,
12027 struct intel_plane_state *state)
12028{
2b875c22
MR		 12029 struct drm_crtc *crtc = state->base.crtc;
12030 struct drm_framebuffer *fb = state->base.fb;
12031 struct drm_device *dev = plane->dev;
14af293f 12032 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12033 struct intel_crtc *intel_crtc;
14af293f 12034 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14af293f
GP		 12035 struct intel_plane *intel_plane = to_intel_plane(plane);
12036 struct drm_rect *src = &state->src;
12037
ea2c67bb
MR		 12038 crtc = crtc ? crtc : plane->crtc;
12039 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12040
12041 plane->fb = fb;
9dc806fc
MR		 12042 crtc->x = src->x1 >> 16;
12043 crtc->y = src->y1 >> 16;
ccc759dc 12044
ccc759dc 12045 intel_plane->obj = obj;
4c34574f 12046
ccc759dc 12047 if (intel_crtc->active) {
ccc759dc 12048 if (state->visible) {
ccc759dc
GP		 12049 /* FIXME: kill this fastboot hack */
12050 intel_update_pipe_size(intel_crtc);
465c120c 12051
ccc759dc 12052 intel_crtc->primary_enabled = true;
465c120c 12053
ccc759dc
GP		 12054 dev_priv->display.update_primary_plane(crtc, plane->fb,
12055 crtc->x, crtc->y);
ccc759dc
GP		 12056 } else {
12057 /*
12058 * If clipping results in a non-visible primary plane,
12059 * we'll disable the primary plane. Note that this is
12060 * a bit different than what happens if userspace
12061 * explicitly disables the plane by passing fb=0
12062 * because plane->fb still gets set and pinned.
12063 */
12064 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12065 }
ccc759dc 12066 }
465c120c
MR		 12067}
12068
32b7eeec 12069static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12070{
32b7eeec 12071 struct drm_device *dev = crtc->dev;
140fd38d 12072 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12074 struct intel_plane *intel_plane;
12075 struct drm_plane *p;
12076 unsigned fb_bits = 0;
12077
12078 /* Track fb's for any planes being disabled */
12079 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12080 intel_plane = to_intel_plane(p);
12081
12082 if (intel_crtc->atomic.disabled_planes &
12083 (1 << drm_plane_index(p))) {
12084 switch (p->type) {
12085 case DRM_PLANE_TYPE_PRIMARY:
12086 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12087 break;
12088 case DRM_PLANE_TYPE_CURSOR:
12089 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12090 break;
12091 case DRM_PLANE_TYPE_OVERLAY:
12092 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12093 break;
12094 }
3c692a41 12095
ea2c67bb
MR		 12096 mutex_lock(&dev->struct_mutex);
12097 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12098 mutex_unlock(&dev->struct_mutex);
12099 }
12100 }
3c692a41 12101
32b7eeec
MR		 12102 if (intel_crtc->atomic.wait_for_flips)
12103 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12104
32b7eeec
MR		 12105 if (intel_crtc->atomic.disable_fbc)
12106 intel_fbc_disable(dev);
3c692a41 12107
32b7eeec
MR		 12108 if (intel_crtc->atomic.pre_disable_primary)
12109 intel_pre_disable_primary(crtc);
3c692a41 12110
32b7eeec
MR		 12111 if (intel_crtc->atomic.update_wm)
12112 intel_update_watermarks(crtc);
3c692a41 12113
32b7eeec 12114 intel_runtime_pm_get(dev_priv);
3c692a41 12115
c34c9ee4
MR		 12116 /* Perform vblank evasion around commit operation */
12117 if (intel_crtc->active)
12118 intel_crtc->atomic.evade =
12119 intel_pipe_update_start(intel_crtc,
12120 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12121}
12122
12123static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12124{
12125 struct drm_device *dev = crtc->dev;
12126 struct drm_i915_private *dev_priv = dev->dev_private;
12127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12128 struct drm_plane *p;
12129
c34c9ee4
MR		 12130 if (intel_crtc->atomic.evade)
12131 intel_pipe_update_end(intel_crtc,
12132 intel_crtc->atomic.start_vbl_count);
3c692a41 12133
140fd38d 12134 intel_runtime_pm_put(dev_priv);
3c692a41 12135
32b7eeec
MR		 12136 if (intel_crtc->atomic.wait_vblank)
12137 intel_wait_for_vblank(dev, intel_crtc->pipe);
12138
12139 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12140
12141 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12142 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12143 intel_fbc_update(dev);
ccc759dc 12144 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12145 }
3c692a41 12146
32b7eeec
MR		 12147 if (intel_crtc->atomic.post_enable_primary)
12148 intel_post_enable_primary(crtc);
3c692a41 12149
32b7eeec
MR		 12150 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12151 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12152 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12153 false, false);
12154
12155 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12156}
12157
cf4c7c12 12158/**
4a3b8769
MR		 12159 * intel_plane_destroy - destroy a plane
12160 * @plane: plane to destroy
cf4c7c12 12161 *
4a3b8769
MR		 12162 * Common destruction function for all types of planes (primary, cursor,
12163 * sprite).
cf4c7c12 12164 */
4a3b8769 12165void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12166{
12167 struct intel_plane *intel_plane = to_intel_plane(plane);
12168 drm_plane_cleanup(plane);
12169 kfree(intel_plane);
12170}
12171
65a3fea0 12172const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12173 .update_plane = drm_plane_helper_update,
12174 .disable_plane = drm_plane_helper_disable,
3d7d6510 12175 .destroy = intel_plane_destroy,
c196e1d6 12176 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12177 .atomic_get_property = intel_plane_atomic_get_property,
12178 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12179 .atomic_duplicate_state = intel_plane_duplicate_state,
12180 .atomic_destroy_state = intel_plane_destroy_state,
12181
465c120c
MR		 12182};
12183
12184static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12185 int pipe)
12186{
12187 struct intel_plane *primary;
8e7d688b 12188 struct intel_plane_state *state;
465c120c
MR		 12189 const uint32_t *intel_primary_formats;
12190 int num_formats;
12191
12192 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12193 if (primary == NULL)
12194 return NULL;
12195
8e7d688b
MR		 12196 state = intel_create_plane_state(&primary->base);
12197 if (!state) {
ea2c67bb
MR		 12198 kfree(primary);
12199 return NULL;
12200 }
8e7d688b 12201 primary->base.state = &state->base;
ea2c67bb 12202
465c120c
MR		 12203 primary->can_scale = false;
12204 primary->max_downscale = 1;
12205 primary->pipe = pipe;
12206 primary->plane = pipe;
c59cb179
MR		 12207 primary->check_plane = intel_check_primary_plane;
12208 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12209 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12210 primary->plane = !pipe;
12211
12212 if (INTEL_INFO(dev)->gen <= 3) {
12213 intel_primary_formats = intel_primary_formats_gen2;
12214 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12215 } else {
12216 intel_primary_formats = intel_primary_formats_gen4;
12217 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12218 }
12219
12220 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12221 &intel_plane_funcs,
465c120c
MR		 12222 intel_primary_formats, num_formats,
12223 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12224
12225 if (INTEL_INFO(dev)->gen >= 4) {
12226 if (!dev->mode_config.rotation_property)
12227 dev->mode_config.rotation_property =
12228 drm_mode_create_rotation_property(dev,
12229 BIT(DRM_ROTATE_0) |
12230 BIT(DRM_ROTATE_180));
12231 if (dev->mode_config.rotation_property)
12232 drm_object_attach_property(&primary->base.base,
12233 dev->mode_config.rotation_property,
8e7d688b 12234 state->base.rotation);
48404c1e
SJ		 12235 }
12236
ea2c67bb
MR		 12237 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12238
465c120c
MR		 12239 return &primary->base;
12240}
12241
3d7d6510 12242static int
852e787c
GP		 12243intel_check_cursor_plane(struct drm_plane *plane,
12244 struct intel_plane_state *state)
3d7d6510 12245{
2b875c22 12246 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12247 struct drm_device *dev = plane->dev;
2b875c22 12248 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12249 struct drm_rect *dest = &state->dst;
12250 struct drm_rect *src = &state->src;
12251 const struct drm_rect *clip = &state->clip;
757f9a3e 12252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12253 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12254 unsigned stride;
12255 int ret;
3d7d6510 12256
ea2c67bb
MR		 12257 crtc = crtc ? crtc : plane->crtc;
12258 intel_crtc = to_intel_crtc(crtc);
12259
757f9a3e 12260 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12261 src, dest, clip,
3d7d6510
MR		 12262 DRM_PLANE_HELPER_NO_SCALING,
12263 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12264 true, true, &state->visible);
757f9a3e
GP		 12265 if (ret)
12266 return ret;
12267
12268
12269 /* if we want to turn off the cursor ignore width and height */
12270 if (!obj)
32b7eeec 12271 goto finish;
757f9a3e 12272
757f9a3e 12273 /* Check for which cursor types we support */
ea2c67bb
MR		 12274 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12275 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12276 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12277 return -EINVAL;
12278 }
12279
ea2c67bb
MR		 12280 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12281 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12282 DRM_DEBUG_KMS("buffer is too small\n");
12283 return -ENOMEM;
12284 }
12285
3a656b54 12286 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12287 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12288 ret = -EINVAL;
12289 }
757f9a3e 12290
32b7eeec
MR		 12291finish:
12292 if (intel_crtc->active) {
3dd512fb 12293 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12294 intel_crtc->atomic.update_wm = true;
12295
12296 intel_crtc->atomic.fb_bits |=
12297 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12298 }
12299
757f9a3e 12300 return ret;
852e787c 12301}
3d7d6510 12302
f4a2cf29 12303static void
852e787c
GP		 12304intel_commit_cursor_plane(struct drm_plane *plane,
12305 struct intel_plane_state *state)
12306{
2b875c22 12307 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12308 struct drm_device *dev = plane->dev;
12309 struct intel_crtc *intel_crtc;
a919db90 12310 struct intel_plane *intel_plane = to_intel_plane(plane);
2b875c22 12311 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12312 uint32_t addr;
852e787c 12313
ea2c67bb
MR		 12314 crtc = crtc ? crtc : plane->crtc;
12315 intel_crtc = to_intel_crtc(crtc);
12316
2b875c22 12317 plane->fb = state->base.fb;
ea2c67bb
MR		 12318 crtc->cursor_x = state->base.crtc_x;
12319 crtc->cursor_y = state->base.crtc_y;
12320
a919db90
SJ		 12321 intel_plane->obj = obj;
12322
a912f12f
GP		 12323 if (intel_crtc->cursor_bo == obj)
12324 goto update;
4ed91096 12325
f4a2cf29 12326 if (!obj)
a912f12f 12327 addr = 0;
f4a2cf29 12328 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12329 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12330 else
a912f12f 12331 addr = obj->phys_handle->busaddr;
852e787c 12332
a912f12f
GP		 12333 intel_crtc->cursor_addr = addr;
12334 intel_crtc->cursor_bo = obj;
12335update:
852e787c 12336
32b7eeec 12337 if (intel_crtc->active)
a912f12f 12338 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12339}
12340
3d7d6510
MR		 12341static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12342 int pipe)
12343{
12344 struct intel_plane *cursor;
8e7d688b 12345 struct intel_plane_state *state;
3d7d6510
MR		 12346
12347 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12348 if (cursor == NULL)
12349 return NULL;
12350
8e7d688b
MR		 12351 state = intel_create_plane_state(&cursor->base);
12352 if (!state) {
ea2c67bb
MR		 12353 kfree(cursor);
12354 return NULL;
12355 }
8e7d688b 12356 cursor->base.state = &state->base;
ea2c67bb 12357
3d7d6510
MR		 12358 cursor->can_scale = false;
12359 cursor->max_downscale = 1;
12360 cursor->pipe = pipe;
12361 cursor->plane = pipe;
c59cb179
MR		 12362 cursor->check_plane = intel_check_cursor_plane;
12363 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12364
12365 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12366 &intel_plane_funcs,
3d7d6510
MR		 12367 intel_cursor_formats,
12368 ARRAY_SIZE(intel_cursor_formats),
12369 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12370
12371 if (INTEL_INFO(dev)->gen >= 4) {
12372 if (!dev->mode_config.rotation_property)
12373 dev->mode_config.rotation_property =
12374 drm_mode_create_rotation_property(dev,
12375 BIT(DRM_ROTATE_0) |
12376 BIT(DRM_ROTATE_180));
12377 if (dev->mode_config.rotation_property)
12378 drm_object_attach_property(&cursor->base.base,
12379 dev->mode_config.rotation_property,
8e7d688b 12380 state->base.rotation);
4398ad45
VS		 12381 }
12382
ea2c67bb
MR		 12383 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12384
3d7d6510
MR		 12385 return &cursor->base;
12386}
12387
b358d0a6 12388static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12389{
fbee40df 12390 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12391 struct intel_crtc *intel_crtc;
f5de6e07 12392 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12393 struct drm_plane *primary = NULL;
12394 struct drm_plane *cursor = NULL;
465c120c 12395 int i, ret;
79e53945 12396
955382f3 12397 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12398 if (intel_crtc == NULL)
12399 return;
12400
f5de6e07
ACO		 12401 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12402 if (!crtc_state)
12403 goto fail;
12404 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12405 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12406
465c120c 12407 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12408 if (!primary)
12409 goto fail;
12410
12411 cursor = intel_cursor_plane_create(dev, pipe);
12412 if (!cursor)
12413 goto fail;
12414
465c120c 12415 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 12416 cursor, &intel_crtc_funcs);
12417 if (ret)
12418 goto fail;
79e53945
JB		 12419
12420 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 12421 for (i = 0; i < 256; i++) {
12422 intel_crtc->lut_r[i] = i;
12423 intel_crtc->lut_g[i] = i;
12424 intel_crtc->lut_b[i] = i;
12425 }
12426
1f1c2e24
VS		 12427 /*
12428 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 12429 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 12430 */
80824003
JB		 12431 intel_crtc->pipe = pipe;
12432 intel_crtc->plane = pipe;
3a77c4c4 12433 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 12434 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 12435 intel_crtc->plane = !pipe;
80824003
JB		 12436 }
12437
4b0e333e
CW		 12438 intel_crtc->cursor_base = ~0;
12439 intel_crtc->cursor_cntl = ~0;
dc41c154 12440 intel_crtc->cursor_size = ~0;
8d7849db 12441
22fd0fab
JB		 12442 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12443 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12444 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12445 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12446
9362c7c5
ACO		 12447 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12448
79e53945 12449 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 12450
12451 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 12452 return;
12453
12454fail:
12455 if (primary)
12456 drm_plane_cleanup(primary);
12457 if (cursor)
12458 drm_plane_cleanup(cursor);
f5de6e07 12459 kfree(crtc_state);
3d7d6510 12460 kfree(intel_crtc);
79e53945
JB		 12461}
12462
752aa88a
JB		 12463enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12464{
12465 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 12466 struct drm_device *dev = connector->base.dev;
752aa88a 12467
51fd371b 12468 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 12469
d3babd3f 12470 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 12471 return INVALID_PIPE;
12472
12473 return to_intel_crtc(encoder->crtc)->pipe;
12474}
12475
08d7b3d1 12476int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 12477 struct drm_file *file)
08d7b3d1 12478{
08d7b3d1 12479 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 12480 struct drm_crtc *drmmode_crtc;
c05422d5 12481 struct intel_crtc *crtc;
08d7b3d1 12482
7707e653 12483 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 12484
7707e653 12485 if (!drmmode_crtc) {
08d7b3d1 12486 DRM_ERROR("no such CRTC id\n");
3f2c2057 12487 return -ENOENT;
08d7b3d1
CW		 12488 }
12489
7707e653 12490 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 12491 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 12492
c05422d5 12493 return 0;
08d7b3d1
CW		 12494}
12495
66a9278e 12496static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 12497{
66a9278e
DV		 12498 struct drm_device *dev = encoder->base.dev;
12499 struct intel_encoder *source_encoder;
79e53945 12500 int index_mask = 0;
79e53945
JB		 12501 int entry = 0;
12502
b2784e15 12503 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 12504 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 12505 index_mask |= (1 << entry);
12506
79e53945
JB		 12507 entry++;
12508 }
4ef69c7a 12509
79e53945
JB		 12510 return index_mask;
12511}
12512
4d302442
CW		 12513static bool has_edp_a(struct drm_device *dev)
12514{
12515 struct drm_i915_private *dev_priv = dev->dev_private;
12516
12517 if (!IS_MOBILE(dev))
12518 return false;
12519
12520 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12521 return false;
12522
e3589908 12523 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 12524 return false;
12525
12526 return true;
12527}
12528
84b4e042
JB		 12529static bool intel_crt_present(struct drm_device *dev)
12530{
12531 struct drm_i915_private *dev_priv = dev->dev_private;
12532
884497ed
DL		 12533 if (INTEL_INFO(dev)->gen >= 9)
12534 return false;
12535
cf404ce4 12536 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 12537 return false;
12538
12539 if (IS_CHERRYVIEW(dev))
12540 return false;
12541
12542 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12543 return false;
12544
12545 return true;
12546}
12547
79e53945
JB		 12548static void intel_setup_outputs(struct drm_device *dev)
12549{
725e30ad 12550 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 12551 struct intel_encoder *encoder;
c6f95f27 12552 struct drm_connector *connector;
cb0953d7 12553 bool dpd_is_edp = false;
79e53945 12554
c9093354 12555 intel_lvds_init(dev);
79e53945 12556
84b4e042 12557 if (intel_crt_present(dev))
79935fca 12558 intel_crt_init(dev);
cb0953d7 12559
affa9354 12560 if (HAS_DDI(dev)) {
0e72a5b5
ED		 12561 int found;
12562
12563 /* Haswell uses DDI functions to detect digital outputs */
12564 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12565 /* DDI A only supports eDP */
12566 if (found)
12567 intel_ddi_init(dev, PORT_A);
12568
12569 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12570 * register */
12571 found = I915_READ(SFUSE_STRAP);
12572
12573 if (found & SFUSE_STRAP_DDIB_DETECTED)
12574 intel_ddi_init(dev, PORT_B);
12575 if (found & SFUSE_STRAP_DDIC_DETECTED)
12576 intel_ddi_init(dev, PORT_C);
12577 if (found & SFUSE_STRAP_DDID_DETECTED)
12578 intel_ddi_init(dev, PORT_D);
12579 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 12580 int found;
5d8a7752 12581 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 12582
12583 if (has_edp_a(dev))
12584 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 12585
dc0fa718 12586 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 12587 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 12588 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 12589 if (!found)
e2debe91 12590 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 12591 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 12592 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 12593 }
12594
dc0fa718 12595 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 12596 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 12597
dc0fa718 12598 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 12599 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 12600
5eb08b69 12601 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 12602 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 12603
270b3042 12604 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 12605 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 12606 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 12607 /*
12608 * The DP_DETECTED bit is the latched state of the DDC
12609 * SDA pin at boot. However since eDP doesn't require DDC
12610 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12611 * eDP ports may have been muxed to an alternate function.
12612 * Thus we can't rely on the DP_DETECTED bit alone to detect
12613 * eDP ports. Consult the VBT as well as DP_DETECTED to
12614 * detect eDP ports.
12615 */
d2182a66
VS		 12616 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12617 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 12618 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12619 PORT_B);
e17ac6db
VS		 12620 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12621 intel_dp_is_edp(dev, PORT_B))
12622 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 12623
d2182a66
VS		 12624 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12625 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 12626 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12627 PORT_C);
e17ac6db
VS		 12628 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12629 intel_dp_is_edp(dev, PORT_C))
12630 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 12631
9418c1f1 12632 if (IS_CHERRYVIEW(dev)) {
e17ac6db 12633 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 12634 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12635 PORT_D);
e17ac6db
VS		 12636 /* eDP not supported on port D, so don't check VBT */
12637 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12638 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 12639 }
12640
3cfca973 12641 intel_dsi_init(dev);
103a196f 12642 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 12643 bool found = false;
7d57382e 12644
e2debe91 12645 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12646 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 12647 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 12648 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12649 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 12650 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 12651 }
27185ae1 12652
e7281eab 12653 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12654 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 12655 }
13520b05
KH		 12656
12657 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 12658
e2debe91 12659 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12660 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 12661 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 12662 }
27185ae1 12663
e2debe91 12664 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 12665
b01f2c3a
JB		 12666 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12667 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 12668 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 12669 }
e7281eab 12670 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12671 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 12672 }
27185ae1 12673
b01f2c3a 12674 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 12675 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 12676 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 12677 } else if (IS_GEN2(dev))
79e53945
JB		 12678 intel_dvo_init(dev);
12679
103a196f 12680 if (SUPPORTS_TV(dev))
79e53945
JB		 12681 intel_tv_init(dev);
12682
c6f95f27
MR		 12683 /*
12684 * FIXME: We don't have full atomic support yet, but we want to be
12685 * able to enable/test plane updates via the atomic interface in the
12686 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12687 * will take some atomic codepaths to lookup properties during
12688 * drmModeGetConnector() that unconditionally dereference
12689 * connector->state.
12690 *
12691 * We create a dummy connector state here for each connector to ensure
12692 * the DRM core doesn't try to dereference a NULL connector->state.
12693 * The actual connector properties will never be updated or contain
12694 * useful information, but since we're doing this specifically for
12695 * testing/debug of the plane operations (and only when a specific
12696 * kernel module option is given), that shouldn't really matter.
12697 *
12698 * Once atomic support for crtc's + connectors lands, this loop should
12699 * be removed since we'll be setting up real connector state, which
12700 * will contain Intel-specific properties.
12701 */
12702 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12703 list_for_each_entry(connector,
12704 &dev->mode_config.connector_list,
12705 head) {
12706 if (!WARN_ON(connector->state)) {
12707 connector->state =
12708 kzalloc(sizeof(*connector->state),
12709 GFP_KERNEL);
12710 }
12711 }
12712 }
12713
0bc12bcb 12714 intel_psr_init(dev);
7c8f8a70 12715
b2784e15 12716 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 12717 encoder->base.possible_crtcs = encoder->crtc_mask;
12718 encoder->base.possible_clones =
66a9278e 12719 intel_encoder_clones(encoder);
79e53945 12720 }
47356eb6 12721
dde86e2d 12722 intel_init_pch_refclk(dev);
270b3042
DV		 12723
12724 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 12725}
12726
12727static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12728{
60a5ca01 12729 struct drm_device *dev = fb->dev;
79e53945 12730 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 12731
ef2d633e 12732 drm_framebuffer_cleanup(fb);
60a5ca01 12733 mutex_lock(&dev->struct_mutex);
ef2d633e 12734 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 12735 drm_gem_object_unreference(&intel_fb->obj->base);
12736 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 12737 kfree(intel_fb);
12738}
12739
12740static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 12741 struct drm_file *file,
79e53945
JB		 12742 unsigned int *handle)
12743{
12744 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 12745 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 12746
05394f39 12747 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 12748}
12749
12750static const struct drm_framebuffer_funcs intel_fb_funcs = {
12751 .destroy = intel_user_framebuffer_destroy,
12752 .create_handle = intel_user_framebuffer_create_handle,
12753};
12754
b321803d
DL		 12755static
12756u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12757 uint32_t pixel_format)
12758{
12759 u32 gen = INTEL_INFO(dev)->gen;
12760
12761 if (gen >= 9) {
12762 /* "The stride in bytes must not exceed the of the size of 8K
12763 * pixels and 32K bytes."
12764 */
12765 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12766 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12767 return 32*1024;
12768 } else if (gen >= 4) {
12769 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12770 return 16*1024;
12771 else
12772 return 32*1024;
12773 } else if (gen >= 3) {
12774 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12775 return 8*1024;
12776 else
12777 return 16*1024;
12778 } else {
12779 /* XXX DSPC is limited to 4k tiled */
12780 return 8*1024;
12781 }
12782}
12783
b5ea642a
DV		 12784static int intel_framebuffer_init(struct drm_device *dev,
12785 struct intel_framebuffer *intel_fb,
12786 struct drm_mode_fb_cmd2 *mode_cmd,
12787 struct drm_i915_gem_object *obj)
79e53945 12788{
a57ce0b2 12789 int aligned_height;
79e53945 12790 int ret;
b321803d 12791 u32 pitch_limit, stride_alignment;
79e53945 12792
dd4916c5
DV		 12793 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12794
2a80eada
DV		 12795 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12796 /* Enforce that fb modifier and tiling mode match, but only for
12797 * X-tiled. This is needed for FBC. */
12798 if (!!(obj->tiling_mode == I915_TILING_X) !=
12799 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12800 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12801 return -EINVAL;
12802 }
12803 } else {
12804 if (obj->tiling_mode == I915_TILING_X)
12805 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12806 else if (obj->tiling_mode == I915_TILING_Y) {
12807 DRM_DEBUG("No Y tiling for legacy addfb\n");
12808 return -EINVAL;
12809 }
12810 }
12811
9a8f0a12
TU		 12812 /* Passed in modifier sanity checking. */
12813 switch (mode_cmd->modifier[0]) {
12814 case I915_FORMAT_MOD_Y_TILED:
12815 case I915_FORMAT_MOD_Yf_TILED:
12816 if (INTEL_INFO(dev)->gen < 9) {
12817 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12818 mode_cmd->modifier[0]);
12819 return -EINVAL;
12820 }
12821 case DRM_FORMAT_MOD_NONE:
12822 case I915_FORMAT_MOD_X_TILED:
12823 break;
12824 default:
12825 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12826 mode_cmd->modifier[0]);
57cd6508 12827 return -EINVAL;
c16ed4be 12828 }
57cd6508 12829
b321803d
DL		 12830 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12831 mode_cmd->pixel_format);
12832 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12833 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12834 mode_cmd->pitches[0], stride_alignment);
57cd6508 12835 return -EINVAL;
c16ed4be 12836 }
57cd6508 12837
b321803d
DL		 12838 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12839 mode_cmd->pixel_format);
a35cdaa0 12840 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 12841 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12842 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 12843 "tiled" : "linear",
a35cdaa0 12844 mode_cmd->pitches[0], pitch_limit);
5d7bd705 12845 return -EINVAL;
c16ed4be 12846 }
5d7bd705 12847
2a80eada 12848 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 12849 mode_cmd->pitches[0] != obj->stride) {
12850 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12851 mode_cmd->pitches[0], obj->stride);
5d7bd705 12852 return -EINVAL;
c16ed4be 12853 }
5d7bd705 12854
57779d06 12855 /* Reject formats not supported by any plane early. */
308e5bcb 12856 switch (mode_cmd->pixel_format) {
57779d06 12857 case DRM_FORMAT_C8:
04b3924d
VS		 12858 case DRM_FORMAT_RGB565:
12859 case DRM_FORMAT_XRGB8888:
12860 case DRM_FORMAT_ARGB8888:
57779d06
VS		 12861 break;
12862 case DRM_FORMAT_XRGB1555:
12863 case DRM_FORMAT_ARGB1555:
c16ed4be 12864 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 12865 DRM_DEBUG("unsupported pixel format: %s\n",
12866 drm_get_format_name(mode_cmd->pixel_format));
57779d06 12867 return -EINVAL;
c16ed4be 12868 }
57779d06
VS		 12869 break;
12870 case DRM_FORMAT_XBGR8888:
12871 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 12872 case DRM_FORMAT_XRGB2101010:
12873 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 12874 case DRM_FORMAT_XBGR2101010:
12875 case DRM_FORMAT_ABGR2101010:
c16ed4be 12876 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 12877 DRM_DEBUG("unsupported pixel format: %s\n",
12878 drm_get_format_name(mode_cmd->pixel_format));
57779d06 12879 return -EINVAL;
c16ed4be 12880 }
b5626747 12881 break;
04b3924d
VS		 12882 case DRM_FORMAT_YUYV:
12883 case DRM_FORMAT_UYVY:
12884 case DRM_FORMAT_YVYU:
12885 case DRM_FORMAT_VYUY:
c16ed4be 12886 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 12887 DRM_DEBUG("unsupported pixel format: %s\n",
12888 drm_get_format_name(mode_cmd->pixel_format));
57779d06 12889 return -EINVAL;
c16ed4be 12890 }
57cd6508
CW		 12891 break;
12892 default:
4ee62c76
VS		 12893 DRM_DEBUG("unsupported pixel format: %s\n",
12894 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 12895 return -EINVAL;
12896 }
12897
90f9a336
VS		 12898 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12899 if (mode_cmd->offsets[0] != 0)
12900 return -EINVAL;
12901
ec2c981e 12902 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 12903 mode_cmd->pixel_format,
12904 mode_cmd->modifier[0]);
53155c0a
DV		 12905 /* FIXME drm helper for size checks (especially planar formats)? */
12906 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12907 return -EINVAL;
12908
c7d73f6a
DV		 12909 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12910 intel_fb->obj = obj;
80075d49 12911 intel_fb->obj->framebuffer_references++;
c7d73f6a 12912
79e53945
JB		 12913 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12914 if (ret) {
12915 DRM_ERROR("framebuffer init failed %d\n", ret);
12916 return ret;
12917 }
12918
79e53945
JB		 12919 return 0;
12920}
12921
79e53945
JB		 12922static struct drm_framebuffer *
12923intel_user_framebuffer_create(struct drm_device *dev,
12924 struct drm_file *filp,
308e5bcb 12925 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 12926{
05394f39 12927 struct drm_i915_gem_object *obj;
79e53945 12928
308e5bcb
JB		 12929 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12930 mode_cmd->handles[0]));
c8725226 12931 if (&obj->base == NULL)
cce13ff7 12932 return ERR_PTR(-ENOENT);
79e53945 12933
d2dff872 12934 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 12935}
12936
4520f53a 12937#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 12938static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 12939{
12940}
12941#endif
12942
79e53945 12943static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 12944 .fb_create = intel_user_framebuffer_create,
0632fef6 12945 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 12946 .atomic_check = intel_atomic_check,
12947 .atomic_commit = intel_atomic_commit,
79e53945
JB		 12948};
12949
e70236a8
JB		 12950/* Set up chip specific display functions */
12951static void intel_init_display(struct drm_device *dev)
12952{
12953 struct drm_i915_private *dev_priv = dev->dev_private;
12954
ee9300bb
DV		 12955 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12956 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 12957 else if (IS_CHERRYVIEW(dev))
12958 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 12959 else if (IS_VALLEYVIEW(dev))
12960 dev_priv->display.find_dpll = vlv_find_best_dpll;
12961 else if (IS_PINEVIEW(dev))
12962 dev_priv->display.find_dpll = pnv_find_best_dpll;
12963 else
12964 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12965
bc8d7dff
DL		 12966 if (INTEL_INFO(dev)->gen >= 9) {
12967 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 12968 dev_priv->display.get_initial_plane_config =
12969 skylake_get_initial_plane_config;
bc8d7dff
DL		 12970 dev_priv->display.crtc_compute_clock =
12971 haswell_crtc_compute_clock;
12972 dev_priv->display.crtc_enable = haswell_crtc_enable;
12973 dev_priv->display.crtc_disable = haswell_crtc_disable;
12974 dev_priv->display.off = ironlake_crtc_off;
12975 dev_priv->display.update_primary_plane =
12976 skylake_update_primary_plane;
12977 } else if (HAS_DDI(dev)) {
0e8ffe1b 12978 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 12979 dev_priv->display.get_initial_plane_config =
12980 ironlake_get_initial_plane_config;
797d0259
ACO		 12981 dev_priv->display.crtc_compute_clock =
12982 haswell_crtc_compute_clock;
4f771f10
PZ		 12983 dev_priv->display.crtc_enable = haswell_crtc_enable;
12984 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 12985 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 12986 dev_priv->display.update_primary_plane =
12987 ironlake_update_primary_plane;
09b4ddf9 12988 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 12989 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 12990 dev_priv->display.get_initial_plane_config =
12991 ironlake_get_initial_plane_config;
3fb37703
ACO		 12992 dev_priv->display.crtc_compute_clock =
12993 ironlake_crtc_compute_clock;
76e5a89c
DV		 12994 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12995 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 12996 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 12997 dev_priv->display.update_primary_plane =
12998 ironlake_update_primary_plane;
89b667f8
JB		 12999 } else if (IS_VALLEYVIEW(dev)) {
13000 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13001 dev_priv->display.get_initial_plane_config =
13002 i9xx_get_initial_plane_config;
d6dfee7a 13003 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13004 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13005 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13006 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13007 dev_priv->display.update_primary_plane =
13008 i9xx_update_primary_plane;
f564048e 13009 } else {
0e8ffe1b 13010 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13011 dev_priv->display.get_initial_plane_config =
13012 i9xx_get_initial_plane_config;
d6dfee7a 13013 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13014 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13015 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13016 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13017 dev_priv->display.update_primary_plane =
13018 i9xx_update_primary_plane;
f564048e 13019 }
e70236a8 13020
e70236a8 13021 /* Returns the core display clock speed */
25eb05fc
JB		 13022 if (IS_VALLEYVIEW(dev))
13023 dev_priv->display.get_display_clock_speed =
13024 valleyview_get_display_clock_speed;
13025 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13026 dev_priv->display.get_display_clock_speed =
13027 i945_get_display_clock_speed;
13028 else if (IS_I915G(dev))
13029 dev_priv->display.get_display_clock_speed =
13030 i915_get_display_clock_speed;
257a7ffc 13031 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13032 dev_priv->display.get_display_clock_speed =
13033 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13034 else if (IS_PINEVIEW(dev))
13035 dev_priv->display.get_display_clock_speed =
13036 pnv_get_display_clock_speed;
e70236a8
JB		 13037 else if (IS_I915GM(dev))
13038 dev_priv->display.get_display_clock_speed =
13039 i915gm_get_display_clock_speed;
13040 else if (IS_I865G(dev))
13041 dev_priv->display.get_display_clock_speed =
13042 i865_get_display_clock_speed;
f0f8a9ce 13043 else if (IS_I85X(dev))
e70236a8
JB		 13044 dev_priv->display.get_display_clock_speed =
13045 i855_get_display_clock_speed;
13046 else /* 852, 830 */
13047 dev_priv->display.get_display_clock_speed =
13048 i830_get_display_clock_speed;
13049
7c10a2b5 13050 if (IS_GEN5(dev)) {
3bb11b53 13051 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13052 } else if (IS_GEN6(dev)) {
13053 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13054 } else if (IS_IVYBRIDGE(dev)) {
13055 /* FIXME: detect B0+ stepping and use auto training */
13056 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
3bb11b53
SJ		 13057 dev_priv->display.modeset_global_resources =
13058 ivb_modeset_global_resources;
059b2fe9 13059 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13060 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13061 } else if (IS_VALLEYVIEW(dev)) {
13062 dev_priv->display.modeset_global_resources =
13063 valleyview_modeset_global_resources;
e70236a8 13064 }
8c9f3aaf 13065
8c9f3aaf
JB		 13066 switch (INTEL_INFO(dev)->gen) {
13067 case 2:
13068 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13069 break;
13070
13071 case 3:
13072 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13073 break;
13074
13075 case 4:
13076 case 5:
13077 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13078 break;
13079
13080 case 6:
13081 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13082 break;
7c9017e5 13083 case 7:
4e0bbc31 13084 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13085 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13086 break;
830c81db 13087 case 9:
ba343e02
TU		 13088 /* Drop through - unsupported since execlist only. */
13089 default:
13090 /* Default just returns -ENODEV to indicate unsupported */
13091 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13092 }
7bd688cd
JN		 13093
13094 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13095
13096 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13097}
13098
b690e96c
JB		 13099/*
13100 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13101 * resume, or other times. This quirk makes sure that's the case for
13102 * affected systems.
13103 */
0206e353 13104static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13105{
13106 struct drm_i915_private *dev_priv = dev->dev_private;
13107
13108 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13109 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13110}
13111
b6b5d049
VS		 13112static void quirk_pipeb_force(struct drm_device *dev)
13113{
13114 struct drm_i915_private *dev_priv = dev->dev_private;
13115
13116 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13117 DRM_INFO("applying pipe b force quirk\n");
13118}
13119
435793df
KP		 13120/*
13121 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13122 */
13123static void quirk_ssc_force_disable(struct drm_device *dev)
13124{
13125 struct drm_i915_private *dev_priv = dev->dev_private;
13126 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13127 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13128}
13129
4dca20ef 13130/*
5a15ab5b
CE		 13131 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13132 * brightness value
4dca20ef
CE		 13133 */
13134static void quirk_invert_brightness(struct drm_device *dev)
13135{
13136 struct drm_i915_private *dev_priv = dev->dev_private;
13137 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13138 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13139}
13140
9c72cc6f
SD		 13141/* Some VBT's incorrectly indicate no backlight is present */
13142static void quirk_backlight_present(struct drm_device *dev)
13143{
13144 struct drm_i915_private *dev_priv = dev->dev_private;
13145 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13146 DRM_INFO("applying backlight present quirk\n");
13147}
13148
b690e96c
JB		 13149struct intel_quirk {
13150 int device;
13151 int subsystem_vendor;
13152 int subsystem_device;
13153 void (*hook)(struct drm_device *dev);
13154};
13155
5f85f176
EE		 13156/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13157struct intel_dmi_quirk {
13158 void (*hook)(struct drm_device *dev);
13159 const struct dmi_system_id (*dmi_id_list)[];
13160};
13161
13162static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13163{
13164 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13165 return 1;
13166}
13167
13168static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13169 {
13170 .dmi_id_list = &(const struct dmi_system_id[]) {
13171 {
13172 .callback = intel_dmi_reverse_brightness,
13173 .ident = "NCR Corporation",
13174 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13175 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13176 },
13177 },
13178 { } /* terminating entry */
13179 },
13180 .hook = quirk_invert_brightness,
13181 },
13182};
13183
c43b5634 13184static struct intel_quirk intel_quirks[] = {
b690e96c 13185 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13186 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13187
b690e96c
JB		 13188 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13189 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13190
b690e96c
JB		 13191 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13192 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13193
5f080c0f
VS		 13194 /* 830 needs to leave pipe A & dpll A up */
13195 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13196
b6b5d049
VS		 13197 /* 830 needs to leave pipe B & dpll B up */
13198 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13199
435793df
KP		 13200 /* Lenovo U160 cannot use SSC on LVDS */
13201 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13202
13203 /* Sony Vaio Y cannot use SSC on LVDS */
13204 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13205
be505f64
AH		 13206 /* Acer Aspire 5734Z must invert backlight brightness */
13207 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13208
13209 /* Acer/eMachines G725 */
13210 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13211
13212 /* Acer/eMachines e725 */
13213 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13214
13215 /* Acer/Packard Bell NCL20 */
13216 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13217
13218 /* Acer Aspire 4736Z */
13219 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13220
13221 /* Acer Aspire 5336 */
13222 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13223
13224 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13225 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13226
dfb3d47b
SD		 13227 /* Acer C720 Chromebook (Core i3 4005U) */
13228 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13229
b2a9601c 13230 /* Apple Macbook 2,1 (Core 2 T7400) */
13231 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13232
d4967d8c
SD		 13233 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13234 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13235
13236 /* HP Chromebook 14 (Celeron 2955U) */
13237 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13238
13239 /* Dell Chromebook 11 */
13240 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13241};
13242
13243static void intel_init_quirks(struct drm_device *dev)
13244{
13245 struct pci_dev *d = dev->pdev;
13246 int i;
13247
13248 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13249 struct intel_quirk *q = &intel_quirks[i];
13250
13251 if (d->device == q->device &&
13252 (d->subsystem_vendor == q->subsystem_vendor ||
13253 q->subsystem_vendor == PCI_ANY_ID) &&
13254 (d->subsystem_device == q->subsystem_device ||
13255 q->subsystem_device == PCI_ANY_ID))
13256 q->hook(dev);
13257 }
5f85f176
EE		 13258 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13259 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13260 intel_dmi_quirks[i].hook(dev);
13261 }
b690e96c
JB		 13262}
13263
9cce37f4
JB		 13264/* Disable the VGA plane that we never use */
13265static void i915_disable_vga(struct drm_device *dev)
13266{
13267 struct drm_i915_private *dev_priv = dev->dev_private;
13268 u8 sr1;
766aa1c4 13269 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13270
2b37c616 13271 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13272 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13273 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13274 sr1 = inb(VGA_SR_DATA);
13275 outb(sr1 | 1<<5, VGA_SR_DATA);
13276 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13277 udelay(300);
13278
01f5a626 13279 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13280 POSTING_READ(vga_reg);
13281}
13282
f817586c
DV		 13283void intel_modeset_init_hw(struct drm_device *dev)
13284{
a8f78b58
ED		 13285 intel_prepare_ddi(dev);
13286
f8bf63fd
VS		 13287 if (IS_VALLEYVIEW(dev))
13288 vlv_update_cdclk(dev);
13289
f817586c
DV		 13290 intel_init_clock_gating(dev);
13291
8090c6b9 13292 intel_enable_gt_powersave(dev);
f817586c
DV		 13293}
13294
79e53945
JB		 13295void intel_modeset_init(struct drm_device *dev)
13296{
652c393a 13297 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13298 int sprite, ret;
8cc87b75 13299 enum pipe pipe;
46f297fb 13300 struct intel_crtc *crtc;
79e53945
JB		 13301
13302 drm_mode_config_init(dev);
13303
13304 dev->mode_config.min_width = 0;
13305 dev->mode_config.min_height = 0;
13306
019d96cb
DA		 13307 dev->mode_config.preferred_depth = 24;
13308 dev->mode_config.prefer_shadow = 1;
13309
25bab385
TU		 13310 dev->mode_config.allow_fb_modifiers = true;
13311
e6ecefaa 13312 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13313
b690e96c
JB		 13314 intel_init_quirks(dev);
13315
1fa61106
ED		 13316 intel_init_pm(dev);
13317
e3c74757
BW		 13318 if (INTEL_INFO(dev)->num_pipes == 0)
13319 return;
13320
e70236a8 13321 intel_init_display(dev);
7c10a2b5 13322 intel_init_audio(dev);
e70236a8 13323
a6c45cf0
CW		 13324 if (IS_GEN2(dev)) {
13325 dev->mode_config.max_width = 2048;
13326 dev->mode_config.max_height = 2048;
13327 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13328 dev->mode_config.max_width = 4096;
13329 dev->mode_config.max_height = 4096;
79e53945 13330 } else {
a6c45cf0
CW		 13331 dev->mode_config.max_width = 8192;
13332 dev->mode_config.max_height = 8192;
79e53945 13333 }
068be561 13334
dc41c154
VS		 13335 if (IS_845G(dev) || IS_I865G(dev)) {
13336 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13337 dev->mode_config.cursor_height = 1023;
13338 } else if (IS_GEN2(dev)) {
068be561
DL		 13339 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13340 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13341 } else {
13342 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13343 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13344 }
13345
5d4545ae 13346 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13347
28c97730 13348 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13349 INTEL_INFO(dev)->num_pipes,
13350 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13351
055e393f 13352 for_each_pipe(dev_priv, pipe) {
8cc87b75 13353 intel_crtc_init(dev, pipe);
3bdcfc0c 13354 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13355 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13356 if (ret)
06da8da2 13357 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13358 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13359 }
79e53945
JB		 13360 }
13361
f42bb70d
JB		 13362 intel_init_dpio(dev);
13363
e72f9fbf 13364 intel_shared_dpll_init(dev);
ee7b9f93 13365
9cce37f4
JB		 13366 /* Just disable it once at startup */
13367 i915_disable_vga(dev);
79e53945 13368 intel_setup_outputs(dev);
11be49eb
CW		 13369
13370 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13371 intel_fbc_disable(dev);
fa9fa083 13372
6e9f798d 13373 drm_modeset_lock_all(dev);
fa9fa083 13374 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13375 drm_modeset_unlock_all(dev);
46f297fb 13376
d3fcc808 13377 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13378 if (!crtc->active)
13379 continue;
13380
46f297fb 13381 /*
46f297fb
JB		 13382 * Note that reserving the BIOS fb up front prevents us
13383 * from stuffing other stolen allocations like the ring
13384 * on top. This prevents some ugliness at boot time, and
13385 * can even allow for smooth boot transitions if the BIOS
13386 * fb is large enough for the active pipe configuration.
13387 */
5724dbd1
DL		 13388 if (dev_priv->display.get_initial_plane_config) {
13389 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13390 &crtc->plane_config);
13391 /*
13392 * If the fb is shared between multiple heads, we'll
13393 * just get the first one.
13394 */
484b41dd 13395 intel_find_plane_obj(crtc, &crtc->plane_config);
46f297fb 13396 }
46f297fb 13397 }
2c7111db
CW		 13398}
13399
7fad798e
DV		 13400static void intel_enable_pipe_a(struct drm_device *dev)
13401{
13402 struct intel_connector *connector;
13403 struct drm_connector *crt = NULL;
13404 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 13405 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 13406
13407 /* We can't just switch on the pipe A, we need to set things up with a
13408 * proper mode and output configuration. As a gross hack, enable pipe A
13409 * by enabling the load detect pipe once. */
3a3371ff 13410 for_each_intel_connector(dev, connector) {
7fad798e
DV		 13411 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13412 crt = &connector->base;
13413 break;
13414 }
13415 }
13416
13417 if (!crt)
13418 return;
13419
208bf9fd
VS		 13420 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13421 intel_release_load_detect_pipe(crt, &load_detect_temp);
7fad798e
DV		 13422}
13423
fa555837
DV		 13424static bool
13425intel_check_plane_mapping(struct intel_crtc *crtc)
13426{
7eb552ae
BW		 13427 struct drm_device *dev = crtc->base.dev;
13428 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 13429 u32 reg, val;
13430
7eb552ae 13431 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 13432 return true;
13433
13434 reg = DSPCNTR(!crtc->plane);
13435 val = I915_READ(reg);
13436
13437 if ((val & DISPLAY_PLANE_ENABLE) &&
13438 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13439 return false;
13440
13441 return true;
13442}
13443
24929352
DV		 13444static void intel_sanitize_crtc(struct intel_crtc *crtc)
13445{
13446 struct drm_device *dev = crtc->base.dev;
13447 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 13448 u32 reg;
24929352 13449
24929352 13450 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 13451 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 13452 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13453
d3eaf884 13454 /* restore vblank interrupts to correct state */
9625604c 13455 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 13456 if (crtc->active) {
13457 update_scanline_offset(crtc);
9625604c
DV		 13458 drm_crtc_vblank_on(&crtc->base);
13459 }
d3eaf884 13460
24929352 13461 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 13462 * disable the crtc (and hence change the state) if it is wrong. Note
13463 * that gen4+ has a fixed plane -> pipe mapping. */
13464 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 13465 struct intel_connector *connector;
13466 bool plane;
13467
24929352
DV		 13468 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13469 crtc->base.base.id);
13470
13471 /* Pipe has the wrong plane attached and the plane is active.
13472 * Temporarily change the plane mapping and disable everything
13473 * ... */
13474 plane = crtc->plane;
13475 crtc->plane = !plane;
9c8958bc 13476 crtc->primary_enabled = true;
24929352
DV		 13477 dev_priv->display.crtc_disable(&crtc->base);
13478 crtc->plane = plane;
13479
13480 /* ... and break all links. */
3a3371ff 13481 for_each_intel_connector(dev, connector) {
24929352
DV		 13482 if (connector->encoder->base.crtc != &crtc->base)
13483 continue;
13484
7f1950fb
EE		 13485 connector->base.dpms = DRM_MODE_DPMS_OFF;
13486 connector->base.encoder = NULL;
24929352 13487 }
7f1950fb
EE		 13488 /* multiple connectors may have the same encoder:
13489 * handle them and break crtc link separately */
3a3371ff 13490 for_each_intel_connector(dev, connector)
7f1950fb
EE		 13491 if (connector->encoder->base.crtc == &crtc->base) {
13492 connector->encoder->base.crtc = NULL;
13493 connector->encoder->connectors_active = false;
13494 }
24929352
DV		 13495
13496 WARN_ON(crtc->active);
83d65738 13497 crtc->base.state->enable = false;
24929352
DV		 13498 crtc->base.enabled = false;
13499 }
24929352 13500
7fad798e
DV		 13501 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13502 crtc->pipe == PIPE_A && !crtc->active) {
13503 /* BIOS forgot to enable pipe A, this mostly happens after
13504 * resume. Force-enable the pipe to fix this, the update_dpms
13505 * call below we restore the pipe to the right state, but leave
13506 * the required bits on. */
13507 intel_enable_pipe_a(dev);
13508 }
13509
24929352
DV		 13510 /* Adjust the state of the output pipe according to whether we
13511 * have active connectors/encoders. */
13512 intel_crtc_update_dpms(&crtc->base);
13513
83d65738 13514 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 13515 struct intel_encoder *encoder;
13516
13517 /* This can happen either due to bugs in the get_hw_state
13518 * functions or because the pipe is force-enabled due to the
13519 * pipe A quirk. */
13520 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13521 crtc->base.base.id,
83d65738 13522 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 13523 crtc->active ? "enabled" : "disabled");
13524
83d65738 13525 crtc->base.state->enable = crtc->active;
24929352
DV		 13526 crtc->base.enabled = crtc->active;
13527
13528 /* Because we only establish the connector -> encoder ->
13529 * crtc links if something is active, this means the
13530 * crtc is now deactivated. Break the links. connector
13531 * -> encoder links are only establish when things are
13532 * actually up, hence no need to break them. */
13533 WARN_ON(crtc->active);
13534
13535 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13536 WARN_ON(encoder->connectors_active);
13537 encoder->base.crtc = NULL;
13538 }
13539 }
c5ab3bc0 13540
a3ed6aad 13541 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 13542 /*
13543 * We start out with underrun reporting disabled to avoid races.
13544 * For correct bookkeeping mark this on active crtcs.
13545 *
c5ab3bc0
DV		 13546 * Also on gmch platforms we dont have any hardware bits to
13547 * disable the underrun reporting. Which means we need to start
13548 * out with underrun reporting disabled also on inactive pipes,
13549 * since otherwise we'll complain about the garbage we read when
13550 * e.g. coming up after runtime pm.
13551 *
4cc31489
DV		 13552 * No protection against concurrent access is required - at
13553 * worst a fifo underrun happens which also sets this to false.
13554 */
13555 crtc->cpu_fifo_underrun_disabled = true;
13556 crtc->pch_fifo_underrun_disabled = true;
13557 }
24929352
DV		 13558}
13559
13560static void intel_sanitize_encoder(struct intel_encoder *encoder)
13561{
13562 struct intel_connector *connector;
13563 struct drm_device *dev = encoder->base.dev;
13564
13565 /* We need to check both for a crtc link (meaning that the
13566 * encoder is active and trying to read from a pipe) and the
13567 * pipe itself being active. */
13568 bool has_active_crtc = encoder->base.crtc &&
13569 to_intel_crtc(encoder->base.crtc)->active;
13570
13571 if (encoder->connectors_active && !has_active_crtc) {
13572 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13573 encoder->base.base.id,
8e329a03 13574 encoder->base.name);
24929352
DV		 13575
13576 /* Connector is active, but has no active pipe. This is
13577 * fallout from our resume register restoring. Disable
13578 * the encoder manually again. */
13579 if (encoder->base.crtc) {
13580 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13581 encoder->base.base.id,
8e329a03 13582 encoder->base.name);
24929352 13583 encoder->disable(encoder);
a62d1497
VS		 13584 if (encoder->post_disable)
13585 encoder->post_disable(encoder);
24929352 13586 }
7f1950fb
EE		 13587 encoder->base.crtc = NULL;
13588 encoder->connectors_active = false;
24929352
DV		 13589
13590 /* Inconsistent output/port/pipe state happens presumably due to
13591 * a bug in one of the get_hw_state functions. Or someplace else
13592 * in our code, like the register restore mess on resume. Clamp
13593 * things to off as a safer default. */
3a3371ff 13594 for_each_intel_connector(dev, connector) {
24929352
DV		 13595 if (connector->encoder != encoder)
13596 continue;
7f1950fb
EE		 13597 connector->base.dpms = DRM_MODE_DPMS_OFF;
13598 connector->base.encoder = NULL;
24929352
DV		 13599 }
13600 }
13601 /* Enabled encoders without active connectors will be fixed in
13602 * the crtc fixup. */
13603}
13604
04098753 13605void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 13606{
13607 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 13608 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 13609
04098753
ID		 13610 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13611 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13612 i915_disable_vga(dev);
13613 }
13614}
13615
13616void i915_redisable_vga(struct drm_device *dev)
13617{
13618 struct drm_i915_private *dev_priv = dev->dev_private;
13619
8dc8a27c
PZ		 13620 /* This function can be called both from intel_modeset_setup_hw_state or
13621 * at a very early point in our resume sequence, where the power well
13622 * structures are not yet restored. Since this function is at a very
13623 * paranoid "someone might have enabled VGA while we were not looking"
13624 * level, just check if the power well is enabled instead of trying to
13625 * follow the "don't touch the power well if we don't need it" policy
13626 * the rest of the driver uses. */
f458ebbc 13627 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 13628 return;
13629
04098753 13630 i915_redisable_vga_power_on(dev);
0fde901f
KM		 13631}
13632
98ec7739
VS		 13633static bool primary_get_hw_state(struct intel_crtc *crtc)
13634{
13635 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13636
13637 if (!crtc->active)
13638 return false;
13639
13640 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13641}
13642
30e984df 13643static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 13644{
13645 struct drm_i915_private *dev_priv = dev->dev_private;
13646 enum pipe pipe;
24929352
DV		 13647 struct intel_crtc *crtc;
13648 struct intel_encoder *encoder;
13649 struct intel_connector *connector;
5358901f 13650 int i;
24929352 13651
d3fcc808 13652 for_each_intel_crtc(dev, crtc) {
6e3c9717 13653 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 13654
6e3c9717 13655 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 13656
0e8ffe1b 13657 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 13658 crtc->config);
24929352 13659
83d65738 13660 crtc->base.state->enable = crtc->active;
24929352 13661 crtc->base.enabled = crtc->active;
98ec7739 13662 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 13663
13664 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13665 crtc->base.base.id,
13666 crtc->active ? "enabled" : "disabled");
13667 }
13668
5358901f
DV		 13669 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13670 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13671
3e369b76
ACO		 13672 pll->on = pll->get_hw_state(dev_priv, pll,
13673 &pll->config.hw_state);
5358901f 13674 pll->active = 0;
3e369b76 13675 pll->config.crtc_mask = 0;
d3fcc808 13676 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 13677 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 13678 pll->active++;
3e369b76 13679 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 13680 }
5358901f 13681 }
5358901f 13682
1e6f2ddc 13683 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 13684 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 13685
3e369b76 13686 if (pll->config.crtc_mask)
bd2bb1b9 13687 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 13688 }
13689
b2784e15 13690 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13691 pipe = 0;
13692
13693 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 13694 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13695 encoder->base.crtc = &crtc->base;
6e3c9717 13696 encoder->get_config(encoder, crtc->config);
24929352
DV		 13697 } else {
13698 encoder->base.crtc = NULL;
13699 }
13700
13701 encoder->connectors_active = false;
6f2bcceb 13702 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 13703 encoder->base.base.id,
8e329a03 13704 encoder->base.name,
24929352 13705 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 13706 pipe_name(pipe));
24929352
DV		 13707 }
13708
3a3371ff 13709 for_each_intel_connector(dev, connector) {
24929352
DV		 13710 if (connector->get_hw_state(connector)) {
13711 connector->base.dpms = DRM_MODE_DPMS_ON;
13712 connector->encoder->connectors_active = true;
13713 connector->base.encoder = &connector->encoder->base;
13714 } else {
13715 connector->base.dpms = DRM_MODE_DPMS_OFF;
13716 connector->base.encoder = NULL;
13717 }
13718 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13719 connector->base.base.id,
c23cc417 13720 connector->base.name,
24929352
DV		 13721 connector->base.encoder ? "enabled" : "disabled");
13722 }
30e984df
DV		 13723}
13724
13725/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13726 * and i915 state tracking structures. */
13727void intel_modeset_setup_hw_state(struct drm_device *dev,
13728 bool force_restore)
13729{
13730 struct drm_i915_private *dev_priv = dev->dev_private;
13731 enum pipe pipe;
30e984df
DV		 13732 struct intel_crtc *crtc;
13733 struct intel_encoder *encoder;
35c95375 13734 int i;
30e984df
DV		 13735
13736 intel_modeset_readout_hw_state(dev);
24929352 13737
babea61d
JB		 13738 /*
13739 * Now that we have the config, copy it to each CRTC struct
13740 * Note that this could go away if we move to using crtc_config
13741 * checking everywhere.
13742 */
d3fcc808 13743 for_each_intel_crtc(dev, crtc) {
d330a953 13744 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 13745 intel_mode_from_pipe_config(&crtc->base.mode,
13746 crtc->config);
babea61d
JB		 13747 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13748 crtc->base.base.id);
13749 drm_mode_debug_printmodeline(&crtc->base.mode);
13750 }
13751 }
13752
24929352 13753 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 13754 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13755 intel_sanitize_encoder(encoder);
13756 }
13757
055e393f 13758 for_each_pipe(dev_priv, pipe) {
24929352
DV		 13759 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13760 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 13761 intel_dump_pipe_config(crtc, crtc->config,
13762 "[setup_hw_state]");
24929352 13763 }
9a935856 13764
35c95375
DV		 13765 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13766 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13767
13768 if (!pll->on || pll->active)
13769 continue;
13770
13771 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13772
13773 pll->disable(dev_priv, pll);
13774 pll->on = false;
13775 }
13776
3078999f
PB		 13777 if (IS_GEN9(dev))
13778 skl_wm_get_hw_state(dev);
13779 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 13780 ilk_wm_get_hw_state(dev);
13781
45e2b5f6 13782 if (force_restore) {
7d0bc1ea
VS		 13783 i915_redisable_vga(dev);
13784
f30da187
DV		 13785 /*
13786 * We need to use raw interfaces for restoring state to avoid
13787 * checking (bogus) intermediate states.
13788 */
055e393f 13789 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 13790 struct drm_crtc *crtc =
13791 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 13792
7f27126e
JB		 13793 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13794 crtc->primary->fb);
45e2b5f6
DV		 13795 }
13796 } else {
13797 intel_modeset_update_staged_output_state(dev);
13798 }
8af6cf88
DV		 13799
13800 intel_modeset_check_state(dev);
2c7111db
CW		 13801}
13802
13803void intel_modeset_gem_init(struct drm_device *dev)
13804{
92122789 13805 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 13806 struct drm_crtc *c;
2ff8fde1 13807 struct drm_i915_gem_object *obj;
484b41dd 13808
ae48434c
ID		 13809 mutex_lock(&dev->struct_mutex);
13810 intel_init_gt_powersave(dev);
13811 mutex_unlock(&dev->struct_mutex);
13812
92122789
JB		 13813 /*
13814 * There may be no VBT; and if the BIOS enabled SSC we can
13815 * just keep using it to avoid unnecessary flicker. Whereas if the
13816 * BIOS isn't using it, don't assume it will work even if the VBT
13817 * indicates as much.
13818 */
13819 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13820 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13821 DREF_SSC1_ENABLE);
13822
1833b134 13823 intel_modeset_init_hw(dev);
02e792fb
DV		 13824
13825 intel_setup_overlay(dev);
484b41dd
JB		 13826
13827 /*
13828 * Make sure any fbs we allocated at startup are properly
13829 * pinned & fenced. When we do the allocation it's too early
13830 * for this.
13831 */
13832 mutex_lock(&dev->struct_mutex);
70e1e0ec 13833 for_each_crtc(dev, c) {
2ff8fde1
MR		 13834 obj = intel_fb_obj(c->primary->fb);
13835 if (obj == NULL)
484b41dd
JB		 13836 continue;
13837
850c4cdc
TU		 13838 if (intel_pin_and_fence_fb_obj(c->primary,
13839 c->primary->fb,
13840 NULL)) {
484b41dd
JB		 13841 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13842 to_intel_crtc(c)->pipe);
66e514c1
DA		 13843 drm_framebuffer_unreference(c->primary->fb);
13844 c->primary->fb = NULL;
afd65eb4 13845 update_state_fb(c->primary);
484b41dd
JB		 13846 }
13847 }
13848 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 13849
13850 intel_backlight_register(dev);
79e53945
JB		 13851}
13852
4932e2c3
ID		 13853void intel_connector_unregister(struct intel_connector *intel_connector)
13854{
13855 struct drm_connector *connector = &intel_connector->base;
13856
13857 intel_panel_destroy_backlight(connector);
34ea3d38 13858 drm_connector_unregister(connector);
4932e2c3
ID		 13859}
13860
79e53945
JB		 13861void intel_modeset_cleanup(struct drm_device *dev)
13862{
652c393a 13863 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 13864 struct drm_connector *connector;
652c393a 13865
2eb5252e
ID		 13866 intel_disable_gt_powersave(dev);
13867
0962c3c9
VS		 13868 intel_backlight_unregister(dev);
13869
fd0c0642
DV		 13870 /*
13871 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 13872 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 13873 * experience fancy races otherwise.
13874 */
2aeb7d3a 13875 intel_irq_uninstall(dev_priv);
eb21b92b 13876
fd0c0642
DV		 13877 /*
13878 * Due to the hpd irq storm handling the hotplug work can re-arm the
13879 * poll handlers. Hence disable polling after hpd handling is shut down.
13880 */
f87ea761 13881 drm_kms_helper_poll_fini(dev);
fd0c0642 13882
652c393a
JB		 13883 mutex_lock(&dev->struct_mutex);
13884
723bfd70
JB		 13885 intel_unregister_dsm_handler();
13886
7ff0ebcc 13887 intel_fbc_disable(dev);
e70236a8 13888
930ebb46
DV		 13889 ironlake_teardown_rc6(dev);
13890
69341a5e
KH		 13891 mutex_unlock(&dev->struct_mutex);
13892
1630fe75
CW		 13893 /* flush any delayed tasks or pending work */
13894 flush_scheduled_work();
13895
db31af1d
JN		 13896 /* destroy the backlight and sysfs files before encoders/connectors */
13897 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 13898 struct intel_connector *intel_connector;
13899
13900 intel_connector = to_intel_connector(connector);
13901 intel_connector->unregister(intel_connector);
db31af1d 13902 }
d9255d57 13903
79e53945 13904 drm_mode_config_cleanup(dev);
4d7bb011
DV		 13905
13906 intel_cleanup_overlay(dev);
ae48434c
ID		 13907
13908 mutex_lock(&dev->struct_mutex);
13909 intel_cleanup_gt_powersave(dev);
13910 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13911}
13912
f1c79df3
ZW		 13913/*
13914 * Return which encoder is currently attached for connector.
13915 */
df0e9248 13916struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 13917{
df0e9248
CW		 13918 return &intel_attached_encoder(connector)->base;
13919}
f1c79df3 13920
df0e9248
CW		 13921void intel_connector_attach_encoder(struct intel_connector *connector,
13922 struct intel_encoder *encoder)
13923{
13924 connector->encoder = encoder;
13925 drm_mode_connector_attach_encoder(&connector->base,
13926 &encoder->base);
79e53945 13927}
28d52043
DA		 13928
13929/*
13930 * set vga decode state - true == enable VGA decode
13931 */
13932int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13933{
13934 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 13935 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 13936 u16 gmch_ctrl;
13937
75fa041d
CW		 13938 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13939 DRM_ERROR("failed to read control word\n");
13940 return -EIO;
13941 }
13942
c0cc8a55
CW		 13943 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13944 return 0;
13945
28d52043
DA		 13946 if (state)
13947 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13948 else
13949 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 13950
13951 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13952 DRM_ERROR("failed to write control word\n");
13953 return -EIO;
13954 }
13955
28d52043
DA		 13956 return 0;
13957}
c4a1d9e4 13958
c4a1d9e4 13959struct intel_display_error_state {
ff57f1b0
PZ		 13960
13961 u32 power_well_driver;
13962
63b66e5b
CW		 13963 int num_transcoders;
13964
c4a1d9e4
CW		 13965 struct intel_cursor_error_state {
13966 u32 control;
13967 u32 position;
13968 u32 base;
13969 u32 size;
52331309 13970 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 13971
13972 struct intel_pipe_error_state {
ddf9c536 13973 bool power_domain_on;
c4a1d9e4 13974 u32 source;
f301b1e1 13975 u32 stat;
52331309 13976 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 13977
13978 struct intel_plane_error_state {
13979 u32 control;
13980 u32 stride;
13981 u32 size;
13982 u32 pos;
13983 u32 addr;
13984 u32 surface;
13985 u32 tile_offset;
52331309 13986 } plane[I915_MAX_PIPES];
63b66e5b
CW		 13987
13988 struct intel_transcoder_error_state {
ddf9c536 13989 bool power_domain_on;
63b66e5b
CW		 13990 enum transcoder cpu_transcoder;
13991
13992 u32 conf;
13993
13994 u32 htotal;
13995 u32 hblank;
13996 u32 hsync;
13997 u32 vtotal;
13998 u32 vblank;
13999 u32 vsync;
14000 } transcoder[4];
c4a1d9e4
CW		 14001};
14002
14003struct intel_display_error_state *
14004intel_display_capture_error_state(struct drm_device *dev)
14005{
fbee40df 14006 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14007 struct intel_display_error_state *error;
63b66e5b
CW		 14008 int transcoders[] = {
14009 TRANSCODER_A,
14010 TRANSCODER_B,
14011 TRANSCODER_C,
14012 TRANSCODER_EDP,
14013 };
c4a1d9e4
CW		 14014 int i;
14015
63b66e5b
CW		 14016 if (INTEL_INFO(dev)->num_pipes == 0)
14017 return NULL;
14018
9d1cb914 14019 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14020 if (error == NULL)
14021 return NULL;
14022
190be112 14023 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14024 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14025
055e393f 14026 for_each_pipe(dev_priv, i) {
ddf9c536 14027 error->pipe[i].power_domain_on =
f458ebbc
DV		 14028 __intel_display_power_is_enabled(dev_priv,
14029 POWER_DOMAIN_PIPE(i));
ddf9c536 14030 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14031 continue;
14032
5efb3e28
VS		 14033 error->cursor[i].control = I915_READ(CURCNTR(i));
14034 error->cursor[i].position = I915_READ(CURPOS(i));
14035 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14036
14037 error->plane[i].control = I915_READ(DSPCNTR(i));
14038 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14039 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14040 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14041 error->plane[i].pos = I915_READ(DSPPOS(i));
14042 }
ca291363
PZ		 14043 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14044 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14045 if (INTEL_INFO(dev)->gen >= 4) {
14046 error->plane[i].surface = I915_READ(DSPSURF(i));
14047 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14048 }
14049
c4a1d9e4 14050 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14051
3abfce77 14052 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14053 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14054 }
14055
14056 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14057 if (HAS_DDI(dev_priv->dev))
14058 error->num_transcoders++; /* Account for eDP. */
14059
14060 for (i = 0; i < error->num_transcoders; i++) {
14061 enum transcoder cpu_transcoder = transcoders[i];
14062
ddf9c536 14063 error->transcoder[i].power_domain_on =
f458ebbc 14064 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14065 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14066 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14067 continue;
14068
63b66e5b
CW		 14069 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14070
14071 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14072 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14073 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14074 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14075 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14076 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14077 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14078 }
14079
14080 return error;
14081}
14082
edc3d884
MK		 14083#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14084
c4a1d9e4 14085void
edc3d884 14086intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14087 struct drm_device *dev,
14088 struct intel_display_error_state *error)
14089{
055e393f 14090 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14091 int i;
14092
63b66e5b
CW		 14093 if (!error)
14094 return;
14095
edc3d884 14096 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14097 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14098 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14099 error->power_well_driver);
055e393f 14100 for_each_pipe(dev_priv, i) {
edc3d884 14101 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14102 err_printf(m, " Power: %s\n",
14103 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14104 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14105 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14106
14107 err_printf(m, "Plane [%d]:\n", i);
14108 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14109 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14110 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14111 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14112 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14113 }
4b71a570 14114 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14115 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14116 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14117 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14118 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14119 }
14120
edc3d884
MK		 14121 err_printf(m, "Cursor [%d]:\n", i);
14122 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14123 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14124 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14125 }
63b66e5b
CW		 14126
14127 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14128 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14129 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14130 err_printf(m, " Power: %s\n",
14131 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14132 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14133 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14134 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14135 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14136 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14137 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14138 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14139 }
c4a1d9e4 14140}
e2fcdaa9
VS		 14141
14142void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14143{
14144 struct intel_crtc *crtc;
14145
14146 for_each_intel_crtc(dev, crtc) {
14147 struct intel_unpin_work *work;
e2fcdaa9 14148
5e2d7afc 14149 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14150
14151 work = crtc->unpin_work;
14152
14153 if (work && work->event &&
14154 work->event->base.file_priv == file) {
14155 kfree(work->event);
14156 work->event = NULL;
14157 }
14158
5e2d7afc 14159 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14160 }
14161}
Linux kernel - Deliverables
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