Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
e7457a9a | 106 | |
0e32b39c DA |
107 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
108 | { | |
109 | if (!connector->mst_port) | |
110 | return connector->encoder; | |
111 | else | |
112 | return &connector->mst_port->mst_encoders[pipe]->base; | |
113 | } | |
114 | ||
79e53945 | 115 | typedef struct { |
0206e353 | 116 | int min, max; |
79e53945 JB |
117 | } intel_range_t; |
118 | ||
119 | typedef struct { | |
0206e353 AJ |
120 | int dot_limit; |
121 | int p2_slow, p2_fast; | |
79e53945 JB |
122 | } intel_p2_t; |
123 | ||
d4906093 ML |
124 | typedef struct intel_limit intel_limit_t; |
125 | struct intel_limit { | |
0206e353 AJ |
126 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
127 | intel_p2_t p2; | |
d4906093 | 128 | }; |
79e53945 | 129 | |
d2acd215 DV |
130 | int |
131 | intel_pch_rawclk(struct drm_device *dev) | |
132 | { | |
133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
134 | ||
135 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
136 | ||
137 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
138 | } | |
139 | ||
021357ac CW |
140 | static inline u32 /* units of 100MHz */ |
141 | intel_fdi_link_freq(struct drm_device *dev) | |
142 | { | |
8b99e68c CW |
143 | if (IS_GEN5(dev)) { |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
146 | } else | |
147 | return 27; | |
021357ac CW |
148 | } |
149 | ||
5d536e28 | 150 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 151 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 152 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 153 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
154 | .m = { .min = 96, .max = 140 }, |
155 | .m1 = { .min = 18, .max = 26 }, | |
156 | .m2 = { .min = 6, .max = 16 }, | |
157 | .p = { .min = 4, .max = 128 }, | |
158 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
159 | .p2 = { .dot_limit = 165000, |
160 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
161 | }; |
162 | ||
5d536e28 DV |
163 | static const intel_limit_t intel_limits_i8xx_dvo = { |
164 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 165 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 166 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
167 | .m = { .min = 96, .max = 140 }, |
168 | .m1 = { .min = 18, .max = 26 }, | |
169 | .m2 = { .min = 6, .max = 16 }, | |
170 | .p = { .min = 4, .max = 128 }, | |
171 | .p1 = { .min = 2, .max = 33 }, | |
172 | .p2 = { .dot_limit = 165000, | |
173 | .p2_slow = 4, .p2_fast = 4 }, | |
174 | }; | |
175 | ||
e4b36699 | 176 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 177 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 178 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 179 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
180 | .m = { .min = 96, .max = 140 }, |
181 | .m1 = { .min = 18, .max = 26 }, | |
182 | .m2 = { .min = 6, .max = 16 }, | |
183 | .p = { .min = 4, .max = 128 }, | |
184 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
185 | .p2 = { .dot_limit = 165000, |
186 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 187 | }; |
273e27ca | 188 | |
e4b36699 | 189 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
190 | .dot = { .min = 20000, .max = 400000 }, |
191 | .vco = { .min = 1400000, .max = 2800000 }, | |
192 | .n = { .min = 1, .max = 6 }, | |
193 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
194 | .m1 = { .min = 8, .max = 18 }, |
195 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
196 | .p = { .min = 5, .max = 80 }, |
197 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
198 | .p2 = { .dot_limit = 200000, |
199 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
200 | }; |
201 | ||
202 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
203 | .dot = { .min = 20000, .max = 400000 }, |
204 | .vco = { .min = 1400000, .max = 2800000 }, | |
205 | .n = { .min = 1, .max = 6 }, | |
206 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
207 | .m1 = { .min = 8, .max = 18 }, |
208 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
209 | .p = { .min = 7, .max = 98 }, |
210 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
211 | .p2 = { .dot_limit = 112000, |
212 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
213 | }; |
214 | ||
273e27ca | 215 | |
e4b36699 | 216 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
217 | .dot = { .min = 25000, .max = 270000 }, |
218 | .vco = { .min = 1750000, .max = 3500000}, | |
219 | .n = { .min = 1, .max = 4 }, | |
220 | .m = { .min = 104, .max = 138 }, | |
221 | .m1 = { .min = 17, .max = 23 }, | |
222 | .m2 = { .min = 5, .max = 11 }, | |
223 | .p = { .min = 10, .max = 30 }, | |
224 | .p1 = { .min = 1, .max = 3}, | |
225 | .p2 = { .dot_limit = 270000, | |
226 | .p2_slow = 10, | |
227 | .p2_fast = 10 | |
044c7c41 | 228 | }, |
e4b36699 KP |
229 | }; |
230 | ||
231 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
232 | .dot = { .min = 22000, .max = 400000 }, |
233 | .vco = { .min = 1750000, .max = 3500000}, | |
234 | .n = { .min = 1, .max = 4 }, | |
235 | .m = { .min = 104, .max = 138 }, | |
236 | .m1 = { .min = 16, .max = 23 }, | |
237 | .m2 = { .min = 5, .max = 11 }, | |
238 | .p = { .min = 5, .max = 80 }, | |
239 | .p1 = { .min = 1, .max = 8}, | |
240 | .p2 = { .dot_limit = 165000, | |
241 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
242 | }; |
243 | ||
244 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
245 | .dot = { .min = 20000, .max = 115000 }, |
246 | .vco = { .min = 1750000, .max = 3500000 }, | |
247 | .n = { .min = 1, .max = 3 }, | |
248 | .m = { .min = 104, .max = 138 }, | |
249 | .m1 = { .min = 17, .max = 23 }, | |
250 | .m2 = { .min = 5, .max = 11 }, | |
251 | .p = { .min = 28, .max = 112 }, | |
252 | .p1 = { .min = 2, .max = 8 }, | |
253 | .p2 = { .dot_limit = 0, | |
254 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 255 | }, |
e4b36699 KP |
256 | }; |
257 | ||
258 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
259 | .dot = { .min = 80000, .max = 224000 }, |
260 | .vco = { .min = 1750000, .max = 3500000 }, | |
261 | .n = { .min = 1, .max = 3 }, | |
262 | .m = { .min = 104, .max = 138 }, | |
263 | .m1 = { .min = 17, .max = 23 }, | |
264 | .m2 = { .min = 5, .max = 11 }, | |
265 | .p = { .min = 14, .max = 42 }, | |
266 | .p1 = { .min = 2, .max = 6 }, | |
267 | .p2 = { .dot_limit = 0, | |
268 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 269 | }, |
e4b36699 KP |
270 | }; |
271 | ||
f2b115e6 | 272 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
273 | .dot = { .min = 20000, .max = 400000}, |
274 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 275 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
276 | .n = { .min = 3, .max = 6 }, |
277 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 278 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
279 | .m1 = { .min = 0, .max = 0 }, |
280 | .m2 = { .min = 0, .max = 254 }, | |
281 | .p = { .min = 5, .max = 80 }, | |
282 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
283 | .p2 = { .dot_limit = 200000, |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
285 | }; |
286 | ||
f2b115e6 | 287 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1700000, .max = 3500000 }, | |
290 | .n = { .min = 3, .max = 6 }, | |
291 | .m = { .min = 2, .max = 256 }, | |
292 | .m1 = { .min = 0, .max = 0 }, | |
293 | .m2 = { .min = 0, .max = 254 }, | |
294 | .p = { .min = 7, .max = 112 }, | |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
298 | }; |
299 | ||
273e27ca EA |
300 | /* Ironlake / Sandybridge |
301 | * | |
302 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
303 | * the range value for them is (actual_value - 2). | |
304 | */ | |
b91ad0ec | 305 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, | |
308 | .n = { .min = 1, .max = 5 }, | |
309 | .m = { .min = 79, .max = 127 }, | |
310 | .m1 = { .min = 12, .max = 22 }, | |
311 | .m2 = { .min = 5, .max = 9 }, | |
312 | .p = { .min = 5, .max = 80 }, | |
313 | .p1 = { .min = 1, .max = 8 }, | |
314 | .p2 = { .dot_limit = 225000, | |
315 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
316 | }; |
317 | ||
b91ad0ec | 318 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 118 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 28, .max = 112 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
329 | }; |
330 | ||
331 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
332 | .dot = { .min = 25000, .max = 350000 }, |
333 | .vco = { .min = 1760000, .max = 3510000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 79, .max = 127 }, | |
336 | .m1 = { .min = 12, .max = 22 }, | |
337 | .m2 = { .min = 5, .max = 9 }, | |
338 | .p = { .min = 14, .max = 56 }, | |
339 | .p1 = { .min = 2, .max = 8 }, | |
340 | .p2 = { .dot_limit = 225000, | |
341 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
342 | }; |
343 | ||
273e27ca | 344 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 345 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
346 | .dot = { .min = 25000, .max = 350000 }, |
347 | .vco = { .min = 1760000, .max = 3510000 }, | |
348 | .n = { .min = 1, .max = 2 }, | |
349 | .m = { .min = 79, .max = 126 }, | |
350 | .m1 = { .min = 12, .max = 22 }, | |
351 | .m2 = { .min = 5, .max = 9 }, | |
352 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 353 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
354 | .p2 = { .dot_limit = 225000, |
355 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
356 | }; |
357 | ||
358 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 3 }, | |
362 | .m = { .min = 79, .max = 126 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 366 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
367 | .p2 = { .dot_limit = 225000, |
368 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
369 | }; |
370 | ||
dc730512 | 371 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
372 | /* |
373 | * These are the data rate limits (measured in fast clocks) | |
374 | * since those are the strictest limits we have. The fast | |
375 | * clock and actual rate limits are more relaxed, so checking | |
376 | * them would make no difference. | |
377 | */ | |
378 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 379 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 380 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
381 | .m1 = { .min = 2, .max = 3 }, |
382 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 383 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 384 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
385 | }; |
386 | ||
ef9348c8 CML |
387 | static const intel_limit_t intel_limits_chv = { |
388 | /* | |
389 | * These are the data rate limits (measured in fast clocks) | |
390 | * since those are the strictest limits we have. The fast | |
391 | * clock and actual rate limits are more relaxed, so checking | |
392 | * them would make no difference. | |
393 | */ | |
394 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 395 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
396 | .n = { .min = 1, .max = 1 }, |
397 | .m1 = { .min = 2, .max = 2 }, | |
398 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
399 | .p1 = { .min = 2, .max = 4 }, | |
400 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
401 | }; | |
402 | ||
6b4bf1c4 VS |
403 | static void vlv_clock(int refclk, intel_clock_t *clock) |
404 | { | |
405 | clock->m = clock->m1 * clock->m2; | |
406 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
407 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
408 | return; | |
fb03ac01 VS |
409 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
410 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
411 | } |
412 | ||
e0638cdf PZ |
413 | /** |
414 | * Returns whether any output on the specified pipe is of the specified type | |
415 | */ | |
4093561b | 416 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 417 | { |
409ee761 | 418 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
419 | struct intel_encoder *encoder; |
420 | ||
409ee761 | 421 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
422 | if (encoder->type == type) |
423 | return true; | |
424 | ||
425 | return false; | |
426 | } | |
427 | ||
d0737e1d ACO |
428 | /** |
429 | * Returns whether any output on the specified pipe will have the specified | |
430 | * type after a staged modeset is complete, i.e., the same as | |
431 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
432 | * encoder->crtc. | |
433 | */ | |
434 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
435 | { | |
436 | struct drm_device *dev = crtc->base.dev; | |
437 | struct intel_encoder *encoder; | |
438 | ||
439 | for_each_intel_encoder(dev, encoder) | |
440 | if (encoder->new_crtc == crtc && encoder->type == type) | |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
445 | ||
409ee761 | 446 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 447 | int refclk) |
2c07245f | 448 | { |
409ee761 | 449 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 450 | const intel_limit_t *limit; |
b91ad0ec | 451 | |
d0737e1d | 452 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 453 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 454 | if (refclk == 100000) |
b91ad0ec ZW |
455 | limit = &intel_limits_ironlake_dual_lvds_100m; |
456 | else | |
457 | limit = &intel_limits_ironlake_dual_lvds; | |
458 | } else { | |
1b894b59 | 459 | if (refclk == 100000) |
b91ad0ec ZW |
460 | limit = &intel_limits_ironlake_single_lvds_100m; |
461 | else | |
462 | limit = &intel_limits_ironlake_single_lvds; | |
463 | } | |
c6bb3538 | 464 | } else |
b91ad0ec | 465 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
466 | |
467 | return limit; | |
468 | } | |
469 | ||
409ee761 | 470 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 471 | { |
409ee761 | 472 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
473 | const intel_limit_t *limit; |
474 | ||
d0737e1d | 475 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 476 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 477 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 478 | else |
e4b36699 | 479 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
480 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
481 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 482 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 483 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 484 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 485 | } else /* The option is for other outputs */ |
e4b36699 | 486 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
487 | |
488 | return limit; | |
489 | } | |
490 | ||
409ee761 | 491 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 492 | { |
409ee761 | 493 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
494 | const intel_limit_t *limit; |
495 | ||
bad720ff | 496 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 497 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 498 | else if (IS_G4X(dev)) { |
044c7c41 | 499 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 500 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 501 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 502 | limit = &intel_limits_pineview_lvds; |
2177832f | 503 | else |
f2b115e6 | 504 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
505 | } else if (IS_CHERRYVIEW(dev)) { |
506 | limit = &intel_limits_chv; | |
a0c4da24 | 507 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 508 | limit = &intel_limits_vlv; |
a6c45cf0 | 509 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 510 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
511 | limit = &intel_limits_i9xx_lvds; |
512 | else | |
513 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 514 | } else { |
d0737e1d | 515 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 516 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 517 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 518 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
519 | else |
520 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
521 | } |
522 | return limit; | |
523 | } | |
524 | ||
f2b115e6 AJ |
525 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
526 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 527 | { |
2177832f SL |
528 | clock->m = clock->m2 + 2; |
529 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
530 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
531 | return; | |
fb03ac01 VS |
532 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
533 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
534 | } |
535 | ||
7429e9d4 DV |
536 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
537 | { | |
538 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
539 | } | |
540 | ||
ac58c3f0 | 541 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 542 | { |
7429e9d4 | 543 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 544 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
545 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
546 | return; | |
fb03ac01 VS |
547 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
548 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
549 | } |
550 | ||
ef9348c8 CML |
551 | static void chv_clock(int refclk, intel_clock_t *clock) |
552 | { | |
553 | clock->m = clock->m1 * clock->m2; | |
554 | clock->p = clock->p1 * clock->p2; | |
555 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
556 | return; | |
557 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
558 | clock->n << 22); | |
559 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
560 | } | |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
1b894b59 CW |
568 | static bool intel_PLL_is_valid(struct drm_device *dev, |
569 | const intel_limit_t *limit, | |
570 | const intel_clock_t *clock) | |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
580 | |
581 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
582 | if (clock->m1 <= clock->m2) | |
583 | INTELPllInvalid("m1 <= m2\n"); | |
584 | ||
585 | if (!IS_VALLEYVIEW(dev)) { | |
586 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
587 | INTELPllInvalid("p out of range\n"); | |
588 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
589 | INTELPllInvalid("m out of range\n"); | |
590 | } | |
591 | ||
79e53945 | 592 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 593 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
594 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
595 | * connector, etc., rather than just a single range. | |
596 | */ | |
597 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 598 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
599 | |
600 | return true; | |
601 | } | |
602 | ||
d4906093 | 603 | static bool |
a919ff14 | 604 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
605 | int target, int refclk, intel_clock_t *match_clock, |
606 | intel_clock_t *best_clock) | |
79e53945 | 607 | { |
a919ff14 | 608 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 609 | intel_clock_t clock; |
79e53945 JB |
610 | int err = target; |
611 | ||
d0737e1d | 612 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
619 | clock.p2 = limit->p2.p2_fast; |
620 | else | |
621 | clock.p2 = limit->p2.p2_slow; | |
622 | } else { | |
623 | if (target < limit->p2.dot_limit) | |
624 | clock.p2 = limit->p2.p2_slow; | |
625 | else | |
626 | clock.p2 = limit->p2.p2_fast; | |
627 | } | |
628 | ||
0206e353 | 629 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 630 | |
42158660 ZY |
631 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
632 | clock.m1++) { | |
633 | for (clock.m2 = limit->m2.min; | |
634 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 635 | if (clock.m2 >= clock.m1) |
42158660 ZY |
636 | break; |
637 | for (clock.n = limit->n.min; | |
638 | clock.n <= limit->n.max; clock.n++) { | |
639 | for (clock.p1 = limit->p1.min; | |
640 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
641 | int this_err; |
642 | ||
ac58c3f0 DV |
643 | i9xx_clock(refclk, &clock); |
644 | if (!intel_PLL_is_valid(dev, limit, | |
645 | &clock)) | |
646 | continue; | |
647 | if (match_clock && | |
648 | clock.p != match_clock->p) | |
649 | continue; | |
650 | ||
651 | this_err = abs(clock.dot - target); | |
652 | if (this_err < err) { | |
653 | *best_clock = clock; | |
654 | err = this_err; | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | } | |
660 | ||
661 | return (err != target); | |
662 | } | |
663 | ||
664 | static bool | |
a919ff14 | 665 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
666 | int target, int refclk, intel_clock_t *match_clock, |
667 | intel_clock_t *best_clock) | |
79e53945 | 668 | { |
a919ff14 | 669 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 670 | intel_clock_t clock; |
79e53945 JB |
671 | int err = target; |
672 | ||
d0737e1d | 673 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 674 | /* |
a210b028 DV |
675 | * For LVDS just rely on its current settings for dual-channel. |
676 | * We haven't figured out how to reliably set up different | |
677 | * single/dual channel state, if we even can. | |
79e53945 | 678 | */ |
1974cad0 | 679 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
680 | clock.p2 = limit->p2.p2_fast; |
681 | else | |
682 | clock.p2 = limit->p2.p2_slow; | |
683 | } else { | |
684 | if (target < limit->p2.dot_limit) | |
685 | clock.p2 = limit->p2.p2_slow; | |
686 | else | |
687 | clock.p2 = limit->p2.p2_fast; | |
688 | } | |
689 | ||
0206e353 | 690 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 691 | |
42158660 ZY |
692 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
693 | clock.m1++) { | |
694 | for (clock.m2 = limit->m2.min; | |
695 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
696 | for (clock.n = limit->n.min; |
697 | clock.n <= limit->n.max; clock.n++) { | |
698 | for (clock.p1 = limit->p1.min; | |
699 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
700 | int this_err; |
701 | ||
ac58c3f0 | 702 | pineview_clock(refclk, &clock); |
1b894b59 CW |
703 | if (!intel_PLL_is_valid(dev, limit, |
704 | &clock)) | |
79e53945 | 705 | continue; |
cec2f356 SP |
706 | if (match_clock && |
707 | clock.p != match_clock->p) | |
708 | continue; | |
79e53945 JB |
709 | |
710 | this_err = abs(clock.dot - target); | |
711 | if (this_err < err) { | |
712 | *best_clock = clock; | |
713 | err = this_err; | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
720 | return (err != target); | |
721 | } | |
722 | ||
d4906093 | 723 | static bool |
a919ff14 | 724 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
725 | int target, int refclk, intel_clock_t *match_clock, |
726 | intel_clock_t *best_clock) | |
d4906093 | 727 | { |
a919ff14 | 728 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
729 | intel_clock_t clock; |
730 | int max_n; | |
731 | bool found; | |
6ba770dc AJ |
732 | /* approximately equals target * 0.00585 */ |
733 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
734 | found = false; |
735 | ||
d0737e1d | 736 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 737 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
738 | clock.p2 = limit->p2.p2_fast; |
739 | else | |
740 | clock.p2 = limit->p2.p2_slow; | |
741 | } else { | |
742 | if (target < limit->p2.dot_limit) | |
743 | clock.p2 = limit->p2.p2_slow; | |
744 | else | |
745 | clock.p2 = limit->p2.p2_fast; | |
746 | } | |
747 | ||
748 | memset(best_clock, 0, sizeof(*best_clock)); | |
749 | max_n = limit->n.max; | |
f77f13e2 | 750 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 751 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 752 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
753 | for (clock.m1 = limit->m1.max; |
754 | clock.m1 >= limit->m1.min; clock.m1--) { | |
755 | for (clock.m2 = limit->m2.max; | |
756 | clock.m2 >= limit->m2.min; clock.m2--) { | |
757 | for (clock.p1 = limit->p1.max; | |
758 | clock.p1 >= limit->p1.min; clock.p1--) { | |
759 | int this_err; | |
760 | ||
ac58c3f0 | 761 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
762 | if (!intel_PLL_is_valid(dev, limit, |
763 | &clock)) | |
d4906093 | 764 | continue; |
1b894b59 CW |
765 | |
766 | this_err = abs(clock.dot - target); | |
d4906093 ML |
767 | if (this_err < err_most) { |
768 | *best_clock = clock; | |
769 | err_most = this_err; | |
770 | max_n = clock.n; | |
771 | found = true; | |
772 | } | |
773 | } | |
774 | } | |
775 | } | |
776 | } | |
2c07245f ZW |
777 | return found; |
778 | } | |
779 | ||
d5dd62bd ID |
780 | /* |
781 | * Check if the calculated PLL configuration is more optimal compared to the | |
782 | * best configuration and error found so far. Return the calculated error. | |
783 | */ | |
784 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
785 | const intel_clock_t *calculated_clock, | |
786 | const intel_clock_t *best_clock, | |
787 | unsigned int best_error_ppm, | |
788 | unsigned int *error_ppm) | |
789 | { | |
9ca3ba01 ID |
790 | /* |
791 | * For CHV ignore the error and consider only the P value. | |
792 | * Prefer a bigger P value based on HW requirements. | |
793 | */ | |
794 | if (IS_CHERRYVIEW(dev)) { | |
795 | *error_ppm = 0; | |
796 | ||
797 | return calculated_clock->p > best_clock->p; | |
798 | } | |
799 | ||
24be4e46 ID |
800 | if (WARN_ON_ONCE(!target_freq)) |
801 | return false; | |
802 | ||
d5dd62bd ID |
803 | *error_ppm = div_u64(1000000ULL * |
804 | abs(target_freq - calculated_clock->dot), | |
805 | target_freq); | |
806 | /* | |
807 | * Prefer a better P value over a better (smaller) error if the error | |
808 | * is small. Ensure this preference for future configurations too by | |
809 | * setting the error to 0. | |
810 | */ | |
811 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
812 | *error_ppm = 0; | |
813 | ||
814 | return true; | |
815 | } | |
816 | ||
817 | return *error_ppm + 10 < best_error_ppm; | |
818 | } | |
819 | ||
a0c4da24 | 820 | static bool |
a919ff14 | 821 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
822 | int target, int refclk, intel_clock_t *match_clock, |
823 | intel_clock_t *best_clock) | |
a0c4da24 | 824 | { |
a919ff14 | 825 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 826 | intel_clock_t clock; |
69e4f900 | 827 | unsigned int bestppm = 1000000; |
27e639bf VS |
828 | /* min update 19.2 MHz */ |
829 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 830 | bool found = false; |
a0c4da24 | 831 | |
6b4bf1c4 VS |
832 | target *= 5; /* fast clock */ |
833 | ||
834 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
835 | |
836 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 837 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 838 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 839 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 841 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 842 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 843 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 844 | unsigned int ppm; |
69e4f900 | 845 | |
6b4bf1c4 VS |
846 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
847 | refclk * clock.m1); | |
848 | ||
849 | vlv_clock(refclk, &clock); | |
43b0ac53 | 850 | |
f01b7962 VS |
851 | if (!intel_PLL_is_valid(dev, limit, |
852 | &clock)) | |
43b0ac53 VS |
853 | continue; |
854 | ||
d5dd62bd ID |
855 | if (!vlv_PLL_is_optimal(dev, target, |
856 | &clock, | |
857 | best_clock, | |
858 | bestppm, &ppm)) | |
859 | continue; | |
6b4bf1c4 | 860 | |
d5dd62bd ID |
861 | *best_clock = clock; |
862 | bestppm = ppm; | |
863 | found = true; | |
a0c4da24 JB |
864 | } |
865 | } | |
866 | } | |
867 | } | |
a0c4da24 | 868 | |
49e497ef | 869 | return found; |
a0c4da24 | 870 | } |
a4fc5ed6 | 871 | |
ef9348c8 | 872 | static bool |
a919ff14 | 873 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
874 | int target, int refclk, intel_clock_t *match_clock, |
875 | intel_clock_t *best_clock) | |
876 | { | |
a919ff14 | 877 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 878 | unsigned int best_error_ppm; |
ef9348c8 CML |
879 | intel_clock_t clock; |
880 | uint64_t m2; | |
881 | int found = false; | |
882 | ||
883 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 884 | best_error_ppm = 1000000; |
ef9348c8 CML |
885 | |
886 | /* | |
887 | * Based on hardware doc, the n always set to 1, and m1 always | |
888 | * set to 2. If requires to support 200Mhz refclk, we need to | |
889 | * revisit this because n may not 1 anymore. | |
890 | */ | |
891 | clock.n = 1, clock.m1 = 2; | |
892 | target *= 5; /* fast clock */ | |
893 | ||
894 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
895 | for (clock.p2 = limit->p2.p2_fast; | |
896 | clock.p2 >= limit->p2.p2_slow; | |
897 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 898 | unsigned int error_ppm; |
ef9348c8 CML |
899 | |
900 | clock.p = clock.p1 * clock.p2; | |
901 | ||
902 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
903 | clock.n) << 22, refclk * clock.m1); | |
904 | ||
905 | if (m2 > INT_MAX/clock.m1) | |
906 | continue; | |
907 | ||
908 | clock.m2 = m2; | |
909 | ||
910 | chv_clock(refclk, &clock); | |
911 | ||
912 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
913 | continue; | |
914 | ||
9ca3ba01 ID |
915 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
916 | best_error_ppm, &error_ppm)) | |
917 | continue; | |
918 | ||
919 | *best_clock = clock; | |
920 | best_error_ppm = error_ppm; | |
921 | found = true; | |
ef9348c8 CML |
922 | } |
923 | } | |
924 | ||
925 | return found; | |
926 | } | |
927 | ||
20ddf665 VS |
928 | bool intel_crtc_active(struct drm_crtc *crtc) |
929 | { | |
930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
931 | ||
932 | /* Be paranoid as we can arrive here with only partial | |
933 | * state retrieved from the hardware during setup. | |
934 | * | |
241bfc38 | 935 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
936 | * as Haswell has gained clock readout/fastboot support. |
937 | * | |
66e514c1 | 938 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 939 | * properly reconstruct framebuffers. |
c3d1f436 MR |
940 | * |
941 | * FIXME: The intel_crtc->active here should be switched to | |
942 | * crtc->state->active once we have proper CRTC states wired up | |
943 | * for atomic. | |
20ddf665 | 944 | */ |
c3d1f436 | 945 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 946 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
947 | } |
948 | ||
a5c961d1 PZ |
949 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
950 | enum pipe pipe) | |
951 | { | |
952 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
954 | ||
6e3c9717 | 955 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
956 | } |
957 | ||
fbf49ea2 VS |
958 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
959 | { | |
960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
961 | u32 reg = PIPEDSL(pipe); | |
962 | u32 line1, line2; | |
963 | u32 line_mask; | |
964 | ||
965 | if (IS_GEN2(dev)) | |
966 | line_mask = DSL_LINEMASK_GEN2; | |
967 | else | |
968 | line_mask = DSL_LINEMASK_GEN3; | |
969 | ||
970 | line1 = I915_READ(reg) & line_mask; | |
971 | mdelay(5); | |
972 | line2 = I915_READ(reg) & line_mask; | |
973 | ||
974 | return line1 == line2; | |
975 | } | |
976 | ||
ab7ad7f6 KP |
977 | /* |
978 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 979 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
980 | * |
981 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
982 | * spinning on the vblank interrupt status bit, since we won't actually | |
983 | * see an interrupt when the pipe is disabled. | |
984 | * | |
ab7ad7f6 KP |
985 | * On Gen4 and above: |
986 | * wait for the pipe register state bit to turn off | |
987 | * | |
988 | * Otherwise: | |
989 | * wait for the display line value to settle (it usually | |
990 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 991 | * |
9d0498a2 | 992 | */ |
575f7ab7 | 993 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 994 | { |
575f7ab7 | 995 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 996 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 997 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 998 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
999 | |
1000 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1001 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1002 | |
1003 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1004 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1005 | 100)) | |
284637d9 | 1006 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1007 | } else { |
ab7ad7f6 | 1008 | /* Wait for the display line to settle */ |
fbf49ea2 | 1009 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1010 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1011 | } |
79e53945 JB |
1012 | } |
1013 | ||
b0ea7d37 DL |
1014 | /* |
1015 | * ibx_digital_port_connected - is the specified port connected? | |
1016 | * @dev_priv: i915 private structure | |
1017 | * @port: the port to test | |
1018 | * | |
1019 | * Returns true if @port is connected, false otherwise. | |
1020 | */ | |
1021 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1022 | struct intel_digital_port *port) | |
1023 | { | |
1024 | u32 bit; | |
1025 | ||
c36346e3 | 1026 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1027 | switch (port->port) { |
c36346e3 DL |
1028 | case PORT_B: |
1029 | bit = SDE_PORTB_HOTPLUG; | |
1030 | break; | |
1031 | case PORT_C: | |
1032 | bit = SDE_PORTC_HOTPLUG; | |
1033 | break; | |
1034 | case PORT_D: | |
1035 | bit = SDE_PORTD_HOTPLUG; | |
1036 | break; | |
1037 | default: | |
1038 | return true; | |
1039 | } | |
1040 | } else { | |
eba905b2 | 1041 | switch (port->port) { |
c36346e3 DL |
1042 | case PORT_B: |
1043 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1044 | break; | |
1045 | case PORT_C: | |
1046 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1047 | break; | |
1048 | case PORT_D: | |
1049 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1050 | break; | |
1051 | default: | |
1052 | return true; | |
1053 | } | |
b0ea7d37 DL |
1054 | } |
1055 | ||
1056 | return I915_READ(SDEISR) & bit; | |
1057 | } | |
1058 | ||
b24e7179 JB |
1059 | static const char *state_string(bool enabled) |
1060 | { | |
1061 | return enabled ? "on" : "off"; | |
1062 | } | |
1063 | ||
1064 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1065 | void assert_pll(struct drm_i915_private *dev_priv, |
1066 | enum pipe pipe, bool state) | |
b24e7179 JB |
1067 | { |
1068 | int reg; | |
1069 | u32 val; | |
1070 | bool cur_state; | |
1071 | ||
1072 | reg = DPLL(pipe); | |
1073 | val = I915_READ(reg); | |
1074 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1075 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1076 | "PLL state assertion failure (expected %s, current %s)\n", |
1077 | state_string(state), state_string(cur_state)); | |
1078 | } | |
b24e7179 | 1079 | |
23538ef1 JN |
1080 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1081 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1082 | { | |
1083 | u32 val; | |
1084 | bool cur_state; | |
1085 | ||
1086 | mutex_lock(&dev_priv->dpio_lock); | |
1087 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1088 | mutex_unlock(&dev_priv->dpio_lock); | |
1089 | ||
1090 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1091 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1092 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1093 | state_string(state), state_string(cur_state)); | |
1094 | } | |
1095 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1096 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1097 | ||
55607e8a | 1098 | struct intel_shared_dpll * |
e2b78267 DV |
1099 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1102 | ||
6e3c9717 | 1103 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1104 | return NULL; |
1105 | ||
6e3c9717 | 1106 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1107 | } |
1108 | ||
040484af | 1109 | /* For ILK+ */ |
55607e8a DV |
1110 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1111 | struct intel_shared_dpll *pll, | |
1112 | bool state) | |
040484af | 1113 | { |
040484af | 1114 | bool cur_state; |
5358901f | 1115 | struct intel_dpll_hw_state hw_state; |
040484af | 1116 | |
92b27b08 | 1117 | if (WARN (!pll, |
46edb027 | 1118 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1119 | return; |
ee7b9f93 | 1120 | |
5358901f | 1121 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1122 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1123 | "%s assertion failure (expected %s, current %s)\n", |
1124 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1125 | } |
040484af JB |
1126 | |
1127 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1128 | enum pipe pipe, bool state) | |
1129 | { | |
1130 | int reg; | |
1131 | u32 val; | |
1132 | bool cur_state; | |
ad80a810 PZ |
1133 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1134 | pipe); | |
040484af | 1135 | |
affa9354 PZ |
1136 | if (HAS_DDI(dev_priv->dev)) { |
1137 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1138 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1139 | val = I915_READ(reg); |
ad80a810 | 1140 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1141 | } else { |
1142 | reg = FDI_TX_CTL(pipe); | |
1143 | val = I915_READ(reg); | |
1144 | cur_state = !!(val & FDI_TX_ENABLE); | |
1145 | } | |
e2c719b7 | 1146 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1147 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1148 | state_string(state), state_string(cur_state)); | |
1149 | } | |
1150 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1151 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1152 | ||
1153 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1154 | enum pipe pipe, bool state) | |
1155 | { | |
1156 | int reg; | |
1157 | u32 val; | |
1158 | bool cur_state; | |
1159 | ||
d63fa0dc PZ |
1160 | reg = FDI_RX_CTL(pipe); |
1161 | val = I915_READ(reg); | |
1162 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1163 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1164 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1165 | state_string(state), state_string(cur_state)); | |
1166 | } | |
1167 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1168 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1169 | ||
1170 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1171 | enum pipe pipe) | |
1172 | { | |
1173 | int reg; | |
1174 | u32 val; | |
1175 | ||
1176 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1177 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1178 | return; |
1179 | ||
bf507ef7 | 1180 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1181 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1182 | return; |
1183 | ||
040484af JB |
1184 | reg = FDI_TX_CTL(pipe); |
1185 | val = I915_READ(reg); | |
e2c719b7 | 1186 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1187 | } |
1188 | ||
55607e8a DV |
1189 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1190 | enum pipe pipe, bool state) | |
040484af JB |
1191 | { |
1192 | int reg; | |
1193 | u32 val; | |
55607e8a | 1194 | bool cur_state; |
040484af JB |
1195 | |
1196 | reg = FDI_RX_CTL(pipe); | |
1197 | val = I915_READ(reg); | |
55607e8a | 1198 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1199 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1200 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1201 | state_string(state), state_string(cur_state)); | |
040484af JB |
1202 | } |
1203 | ||
b680c37a DV |
1204 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1205 | enum pipe pipe) | |
ea0760cf | 1206 | { |
bedd4dba JN |
1207 | struct drm_device *dev = dev_priv->dev; |
1208 | int pp_reg; | |
ea0760cf JB |
1209 | u32 val; |
1210 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1211 | bool locked = true; |
ea0760cf | 1212 | |
bedd4dba JN |
1213 | if (WARN_ON(HAS_DDI(dev))) |
1214 | return; | |
1215 | ||
1216 | if (HAS_PCH_SPLIT(dev)) { | |
1217 | u32 port_sel; | |
1218 | ||
ea0760cf | 1219 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1220 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1221 | ||
1222 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1223 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1224 | panel_pipe = PIPE_B; | |
1225 | /* XXX: else fix for eDP */ | |
1226 | } else if (IS_VALLEYVIEW(dev)) { | |
1227 | /* presumably write lock depends on pipe, not port select */ | |
1228 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1229 | panel_pipe = pipe; | |
ea0760cf JB |
1230 | } else { |
1231 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1232 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1233 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1234 | } |
1235 | ||
1236 | val = I915_READ(pp_reg); | |
1237 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1238 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1239 | locked = false; |
1240 | ||
e2c719b7 | 1241 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1242 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1243 | pipe_name(pipe)); |
ea0760cf JB |
1244 | } |
1245 | ||
93ce0ba6 JN |
1246 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1247 | enum pipe pipe, bool state) | |
1248 | { | |
1249 | struct drm_device *dev = dev_priv->dev; | |
1250 | bool cur_state; | |
1251 | ||
d9d82081 | 1252 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1253 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1254 | else |
5efb3e28 | 1255 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1256 | |
e2c719b7 | 1257 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1258 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1259 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1260 | } | |
1261 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1262 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1263 | ||
b840d907 JB |
1264 | void assert_pipe(struct drm_i915_private *dev_priv, |
1265 | enum pipe pipe, bool state) | |
b24e7179 JB |
1266 | { |
1267 | int reg; | |
1268 | u32 val; | |
63d7bbe9 | 1269 | bool cur_state; |
702e7a56 PZ |
1270 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1271 | pipe); | |
b24e7179 | 1272 | |
b6b5d049 VS |
1273 | /* if we need the pipe quirk it must be always on */ |
1274 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1275 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1276 | state = true; |
1277 | ||
f458ebbc | 1278 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1279 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1280 | cur_state = false; |
1281 | } else { | |
1282 | reg = PIPECONF(cpu_transcoder); | |
1283 | val = I915_READ(reg); | |
1284 | cur_state = !!(val & PIPECONF_ENABLE); | |
1285 | } | |
1286 | ||
e2c719b7 | 1287 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1288 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1289 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1290 | } |
1291 | ||
931872fc CW |
1292 | static void assert_plane(struct drm_i915_private *dev_priv, |
1293 | enum plane plane, bool state) | |
b24e7179 JB |
1294 | { |
1295 | int reg; | |
1296 | u32 val; | |
931872fc | 1297 | bool cur_state; |
b24e7179 JB |
1298 | |
1299 | reg = DSPCNTR(plane); | |
1300 | val = I915_READ(reg); | |
931872fc | 1301 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1303 | "plane %c assertion failure (expected %s, current %s)\n", |
1304 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1305 | } |
1306 | ||
931872fc CW |
1307 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1308 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1309 | ||
b24e7179 JB |
1310 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1311 | enum pipe pipe) | |
1312 | { | |
653e1026 | 1313 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1314 | int reg, i; |
1315 | u32 val; | |
1316 | int cur_pipe; | |
1317 | ||
653e1026 VS |
1318 | /* Primary planes are fixed to pipes on gen4+ */ |
1319 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1320 | reg = DSPCNTR(pipe); |
1321 | val = I915_READ(reg); | |
e2c719b7 | 1322 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1323 | "plane %c assertion failure, should be disabled but not\n", |
1324 | plane_name(pipe)); | |
19ec1358 | 1325 | return; |
28c05794 | 1326 | } |
19ec1358 | 1327 | |
b24e7179 | 1328 | /* Need to check both planes against the pipe */ |
055e393f | 1329 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1330 | reg = DSPCNTR(i); |
1331 | val = I915_READ(reg); | |
1332 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1333 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1334 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1335 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1336 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1337 | } |
1338 | } | |
1339 | ||
19332d7a JB |
1340 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe) | |
1342 | { | |
20674eef | 1343 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1344 | int reg, sprite; |
19332d7a JB |
1345 | u32 val; |
1346 | ||
7feb8b88 | 1347 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1348 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1349 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1350 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1351 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1352 | sprite, pipe_name(pipe)); | |
1353 | } | |
1354 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1355 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1356 | reg = SPCNTR(pipe, sprite); |
20674eef | 1357 | val = I915_READ(reg); |
e2c719b7 | 1358 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1359 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1360 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1361 | } |
1362 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1363 | reg = SPRCTL(pipe); | |
19332d7a | 1364 | val = I915_READ(reg); |
e2c719b7 | 1365 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1366 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1367 | plane_name(pipe), pipe_name(pipe)); |
1368 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1369 | reg = DVSCNTR(pipe); | |
19332d7a | 1370 | val = I915_READ(reg); |
e2c719b7 | 1371 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1372 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1373 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1374 | } |
1375 | } | |
1376 | ||
08c71e5e VS |
1377 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1378 | { | |
e2c719b7 | 1379 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1380 | drm_crtc_vblank_put(crtc); |
1381 | } | |
1382 | ||
89eff4be | 1383 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1384 | { |
1385 | u32 val; | |
1386 | bool enabled; | |
1387 | ||
e2c719b7 | 1388 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1389 | |
92f2584a JB |
1390 | val = I915_READ(PCH_DREF_CONTROL); |
1391 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1392 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1393 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1394 | } |
1395 | ||
ab9412ba DV |
1396 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1397 | enum pipe pipe) | |
92f2584a JB |
1398 | { |
1399 | int reg; | |
1400 | u32 val; | |
1401 | bool enabled; | |
1402 | ||
ab9412ba | 1403 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1404 | val = I915_READ(reg); |
1405 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1406 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1407 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1408 | pipe_name(pipe)); | |
92f2584a JB |
1409 | } |
1410 | ||
4e634389 KP |
1411 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1412 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1413 | { |
1414 | if ((val & DP_PORT_EN) == 0) | |
1415 | return false; | |
1416 | ||
1417 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1418 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1419 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1420 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1421 | return false; | |
44f37d1f CML |
1422 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1423 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1424 | return false; | |
f0575e92 KP |
1425 | } else { |
1426 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1427 | return false; | |
1428 | } | |
1429 | return true; | |
1430 | } | |
1431 | ||
1519b995 KP |
1432 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1433 | enum pipe pipe, u32 val) | |
1434 | { | |
dc0fa718 | 1435 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1436 | return false; |
1437 | ||
1438 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1439 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1440 | return false; |
44f37d1f CML |
1441 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1442 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1443 | return false; | |
1519b995 | 1444 | } else { |
dc0fa718 | 1445 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1446 | return false; |
1447 | } | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1452 | enum pipe pipe, u32 val) | |
1453 | { | |
1454 | if ((val & LVDS_PORT_EN) == 0) | |
1455 | return false; | |
1456 | ||
1457 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1458 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1459 | return false; | |
1460 | } else { | |
1461 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1462 | return false; | |
1463 | } | |
1464 | return true; | |
1465 | } | |
1466 | ||
1467 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1468 | enum pipe pipe, u32 val) | |
1469 | { | |
1470 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1471 | return false; | |
1472 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1473 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1474 | return false; | |
1475 | } else { | |
1476 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1477 | return false; | |
1478 | } | |
1479 | return true; | |
1480 | } | |
1481 | ||
291906f1 | 1482 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1483 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1484 | { |
47a05eca | 1485 | u32 val = I915_READ(reg); |
e2c719b7 | 1486 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1487 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1488 | reg, pipe_name(pipe)); |
de9a35ab | 1489 | |
e2c719b7 | 1490 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1491 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1492 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1493 | } |
1494 | ||
1495 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1496 | enum pipe pipe, int reg) | |
1497 | { | |
47a05eca | 1498 | u32 val = I915_READ(reg); |
e2c719b7 | 1499 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1500 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1501 | reg, pipe_name(pipe)); |
de9a35ab | 1502 | |
e2c719b7 | 1503 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1504 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1505 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1506 | } |
1507 | ||
1508 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1509 | enum pipe pipe) | |
1510 | { | |
1511 | int reg; | |
1512 | u32 val; | |
291906f1 | 1513 | |
f0575e92 KP |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1515 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1516 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1517 | |
1518 | reg = PCH_ADPA; | |
1519 | val = I915_READ(reg); | |
e2c719b7 | 1520 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1521 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1522 | pipe_name(pipe)); |
291906f1 JB |
1523 | |
1524 | reg = PCH_LVDS; | |
1525 | val = I915_READ(reg); | |
e2c719b7 | 1526 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1527 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1528 | pipe_name(pipe)); |
291906f1 | 1529 | |
e2debe91 PZ |
1530 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1531 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1532 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1533 | } |
1534 | ||
40e9cf64 JB |
1535 | static void intel_init_dpio(struct drm_device *dev) |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1538 | ||
1539 | if (!IS_VALLEYVIEW(dev)) | |
1540 | return; | |
1541 | ||
a09caddd CML |
1542 | /* |
1543 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1544 | * CHV x1 PHY (DP/HDMI D) | |
1545 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1546 | */ | |
1547 | if (IS_CHERRYVIEW(dev)) { | |
1548 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1549 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1550 | } else { | |
1551 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1552 | } | |
5382f5f3 JB |
1553 | } |
1554 | ||
d288f65f | 1555 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1556 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1557 | { |
426115cf DV |
1558 | struct drm_device *dev = crtc->base.dev; |
1559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1560 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1561 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1562 | |
426115cf | 1563 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1564 | |
1565 | /* No really, not for ILK+ */ | |
1566 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1567 | ||
1568 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1569 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1570 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1571 | |
426115cf DV |
1572 | I915_WRITE(reg, dpll); |
1573 | POSTING_READ(reg); | |
1574 | udelay(150); | |
1575 | ||
1576 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1577 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1578 | ||
d288f65f | 1579 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1580 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1581 | |
1582 | /* We do this three times for luck */ | |
426115cf | 1583 | I915_WRITE(reg, dpll); |
87442f73 DV |
1584 | POSTING_READ(reg); |
1585 | udelay(150); /* wait for warmup */ | |
426115cf | 1586 | I915_WRITE(reg, dpll); |
87442f73 DV |
1587 | POSTING_READ(reg); |
1588 | udelay(150); /* wait for warmup */ | |
426115cf | 1589 | I915_WRITE(reg, dpll); |
87442f73 DV |
1590 | POSTING_READ(reg); |
1591 | udelay(150); /* wait for warmup */ | |
1592 | } | |
1593 | ||
d288f65f | 1594 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1595 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1596 | { |
1597 | struct drm_device *dev = crtc->base.dev; | |
1598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1599 | int pipe = crtc->pipe; | |
1600 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1601 | u32 tmp; |
1602 | ||
1603 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1604 | ||
1605 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1606 | ||
1607 | mutex_lock(&dev_priv->dpio_lock); | |
1608 | ||
1609 | /* Enable back the 10bit clock to display controller */ | |
1610 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1611 | tmp |= DPIO_DCLKP_EN; | |
1612 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1613 | ||
1614 | /* | |
1615 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1616 | */ | |
1617 | udelay(1); | |
1618 | ||
1619 | /* Enable PLL */ | |
d288f65f | 1620 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1621 | |
1622 | /* Check PLL is locked */ | |
a11b0703 | 1623 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1624 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1625 | ||
a11b0703 | 1626 | /* not sure when this should be written */ |
d288f65f | 1627 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1628 | POSTING_READ(DPLL_MD(pipe)); |
1629 | ||
9d556c99 CML |
1630 | mutex_unlock(&dev_priv->dpio_lock); |
1631 | } | |
1632 | ||
1c4e0274 VS |
1633 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1634 | { | |
1635 | struct intel_crtc *crtc; | |
1636 | int count = 0; | |
1637 | ||
1638 | for_each_intel_crtc(dev, crtc) | |
1639 | count += crtc->active && | |
409ee761 | 1640 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1641 | |
1642 | return count; | |
1643 | } | |
1644 | ||
66e3d5c0 | 1645 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1646 | { |
66e3d5c0 DV |
1647 | struct drm_device *dev = crtc->base.dev; |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1649 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1650 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1651 | |
66e3d5c0 | 1652 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1653 | |
63d7bbe9 | 1654 | /* No really, not for ILK+ */ |
3d13ef2e | 1655 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1656 | |
1657 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1658 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1659 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1660 | |
1c4e0274 VS |
1661 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1662 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1663 | /* | |
1664 | * It appears to be important that we don't enable this | |
1665 | * for the current pipe before otherwise configuring the | |
1666 | * PLL. No idea how this should be handled if multiple | |
1667 | * DVO outputs are enabled simultaneosly. | |
1668 | */ | |
1669 | dpll |= DPLL_DVO_2X_MODE; | |
1670 | I915_WRITE(DPLL(!crtc->pipe), | |
1671 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1672 | } | |
66e3d5c0 DV |
1673 | |
1674 | /* Wait for the clocks to stabilize. */ | |
1675 | POSTING_READ(reg); | |
1676 | udelay(150); | |
1677 | ||
1678 | if (INTEL_INFO(dev)->gen >= 4) { | |
1679 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1680 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1681 | } else { |
1682 | /* The pixel multiplier can only be updated once the | |
1683 | * DPLL is enabled and the clocks are stable. | |
1684 | * | |
1685 | * So write it again. | |
1686 | */ | |
1687 | I915_WRITE(reg, dpll); | |
1688 | } | |
63d7bbe9 JB |
1689 | |
1690 | /* We do this three times for luck */ | |
66e3d5c0 | 1691 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1692 | POSTING_READ(reg); |
1693 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1694 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1695 | POSTING_READ(reg); |
1696 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1697 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1698 | POSTING_READ(reg); |
1699 | udelay(150); /* wait for warmup */ | |
1700 | } | |
1701 | ||
1702 | /** | |
50b44a44 | 1703 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1704 | * @dev_priv: i915 private structure |
1705 | * @pipe: pipe PLL to disable | |
1706 | * | |
1707 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1708 | * | |
1709 | * Note! This is for pre-ILK only. | |
1710 | */ | |
1c4e0274 | 1711 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1712 | { |
1c4e0274 VS |
1713 | struct drm_device *dev = crtc->base.dev; |
1714 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1715 | enum pipe pipe = crtc->pipe; | |
1716 | ||
1717 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1718 | if (IS_I830(dev) && | |
409ee761 | 1719 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1720 | intel_num_dvo_pipes(dev) == 1) { |
1721 | I915_WRITE(DPLL(PIPE_B), | |
1722 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1723 | I915_WRITE(DPLL(PIPE_A), | |
1724 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1725 | } | |
1726 | ||
b6b5d049 VS |
1727 | /* Don't disable pipe or pipe PLLs if needed */ |
1728 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1729 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1730 | return; |
1731 | ||
1732 | /* Make sure the pipe isn't still relying on us */ | |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
1734 | ||
50b44a44 DV |
1735 | I915_WRITE(DPLL(pipe), 0); |
1736 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1737 | } |
1738 | ||
f6071166 JB |
1739 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1740 | { | |
1741 | u32 val = 0; | |
1742 | ||
1743 | /* Make sure the pipe isn't still relying on us */ | |
1744 | assert_pipe_disabled(dev_priv, pipe); | |
1745 | ||
e5cbfbfb ID |
1746 | /* |
1747 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1748 | * The latter is needed for VGA hotplug / manual detection. | |
1749 | */ | |
f6071166 | 1750 | if (pipe == PIPE_B) |
e5cbfbfb | 1751 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1752 | I915_WRITE(DPLL(pipe), val); |
1753 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1754 | |
1755 | } | |
1756 | ||
1757 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1758 | { | |
d752048d | 1759 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1760 | u32 val; |
1761 | ||
a11b0703 VS |
1762 | /* Make sure the pipe isn't still relying on us */ |
1763 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1764 | |
a11b0703 | 1765 | /* Set PLL en = 0 */ |
d17ec4ce | 1766 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1767 | if (pipe != PIPE_A) |
1768 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1769 | I915_WRITE(DPLL(pipe), val); | |
1770 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1771 | |
1772 | mutex_lock(&dev_priv->dpio_lock); | |
1773 | ||
1774 | /* Disable 10bit clock to display controller */ | |
1775 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1776 | val &= ~DPIO_DCLKP_EN; | |
1777 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1778 | ||
61407f6d VS |
1779 | /* disable left/right clock distribution */ |
1780 | if (pipe != PIPE_B) { | |
1781 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1782 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1783 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1784 | } else { | |
1785 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1786 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1787 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1788 | } | |
1789 | ||
d752048d | 1790 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1791 | } |
1792 | ||
e4607fcf CML |
1793 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1794 | struct intel_digital_port *dport) | |
89b667f8 JB |
1795 | { |
1796 | u32 port_mask; | |
00fc31b7 | 1797 | int dpll_reg; |
89b667f8 | 1798 | |
e4607fcf CML |
1799 | switch (dport->port) { |
1800 | case PORT_B: | |
89b667f8 | 1801 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1802 | dpll_reg = DPLL(0); |
e4607fcf CML |
1803 | break; |
1804 | case PORT_C: | |
89b667f8 | 1805 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1806 | dpll_reg = DPLL(0); |
1807 | break; | |
1808 | case PORT_D: | |
1809 | port_mask = DPLL_PORTD_READY_MASK; | |
1810 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1811 | break; |
1812 | default: | |
1813 | BUG(); | |
1814 | } | |
89b667f8 | 1815 | |
00fc31b7 | 1816 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1817 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1818 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1819 | } |
1820 | ||
b14b1055 DV |
1821 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1822 | { | |
1823 | struct drm_device *dev = crtc->base.dev; | |
1824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1825 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1826 | ||
be19f0ff CW |
1827 | if (WARN_ON(pll == NULL)) |
1828 | return; | |
1829 | ||
3e369b76 | 1830 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1831 | if (pll->active == 0) { |
1832 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1833 | WARN_ON(pll->on); | |
1834 | assert_shared_dpll_disabled(dev_priv, pll); | |
1835 | ||
1836 | pll->mode_set(dev_priv, pll); | |
1837 | } | |
1838 | } | |
1839 | ||
92f2584a | 1840 | /** |
85b3894f | 1841 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1842 | * @dev_priv: i915 private structure |
1843 | * @pipe: pipe PLL to enable | |
1844 | * | |
1845 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1846 | * drives the transcoder clock. | |
1847 | */ | |
85b3894f | 1848 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1849 | { |
3d13ef2e DL |
1850 | struct drm_device *dev = crtc->base.dev; |
1851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1852 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1853 | |
87a875bb | 1854 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1855 | return; |
1856 | ||
3e369b76 | 1857 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1858 | return; |
ee7b9f93 | 1859 | |
74dd6928 | 1860 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1861 | pll->name, pll->active, pll->on, |
e2b78267 | 1862 | crtc->base.base.id); |
92f2584a | 1863 | |
cdbd2316 DV |
1864 | if (pll->active++) { |
1865 | WARN_ON(!pll->on); | |
e9d6944e | 1866 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1867 | return; |
1868 | } | |
f4a091c7 | 1869 | WARN_ON(pll->on); |
ee7b9f93 | 1870 | |
bd2bb1b9 PZ |
1871 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1872 | ||
46edb027 | 1873 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1874 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1875 | pll->on = true; |
92f2584a JB |
1876 | } |
1877 | ||
f6daaec2 | 1878 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1879 | { |
3d13ef2e DL |
1880 | struct drm_device *dev = crtc->base.dev; |
1881 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1882 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1883 | |
92f2584a | 1884 | /* PCH only available on ILK+ */ |
3d13ef2e | 1885 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1886 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1887 | return; |
92f2584a | 1888 | |
3e369b76 | 1889 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1890 | return; |
7a419866 | 1891 | |
46edb027 DV |
1892 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1893 | pll->name, pll->active, pll->on, | |
e2b78267 | 1894 | crtc->base.base.id); |
7a419866 | 1895 | |
48da64a8 | 1896 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1897 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1898 | return; |
1899 | } | |
1900 | ||
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1902 | WARN_ON(!pll->on); |
cdbd2316 | 1903 | if (--pll->active) |
7a419866 | 1904 | return; |
ee7b9f93 | 1905 | |
46edb027 | 1906 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1907 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1908 | pll->on = false; |
bd2bb1b9 PZ |
1909 | |
1910 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1911 | } |
1912 | ||
b8a4f404 PZ |
1913 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1914 | enum pipe pipe) | |
040484af | 1915 | { |
23670b32 | 1916 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1917 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1918 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1919 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1920 | |
1921 | /* PCH only available on ILK+ */ | |
55522f37 | 1922 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1923 | |
1924 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1925 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1926 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1927 | |
1928 | /* FDI must be feeding us bits for PCH ports */ | |
1929 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1930 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1931 | ||
23670b32 DV |
1932 | if (HAS_PCH_CPT(dev)) { |
1933 | /* Workaround: Set the timing override bit before enabling the | |
1934 | * pch transcoder. */ | |
1935 | reg = TRANS_CHICKEN2(pipe); | |
1936 | val = I915_READ(reg); | |
1937 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1938 | I915_WRITE(reg, val); | |
59c859d6 | 1939 | } |
23670b32 | 1940 | |
ab9412ba | 1941 | reg = PCH_TRANSCONF(pipe); |
040484af | 1942 | val = I915_READ(reg); |
5f7f726d | 1943 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1944 | |
1945 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1946 | /* | |
1947 | * make the BPC in transcoder be consistent with | |
1948 | * that in pipeconf reg. | |
1949 | */ | |
dfd07d72 DV |
1950 | val &= ~PIPECONF_BPC_MASK; |
1951 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1952 | } |
5f7f726d PZ |
1953 | |
1954 | val &= ~TRANS_INTERLACE_MASK; | |
1955 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1956 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1957 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1958 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1959 | else | |
1960 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1961 | else |
1962 | val |= TRANS_PROGRESSIVE; | |
1963 | ||
040484af JB |
1964 | I915_WRITE(reg, val | TRANS_ENABLE); |
1965 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1966 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1967 | } |
1968 | ||
8fb033d7 | 1969 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1970 | enum transcoder cpu_transcoder) |
040484af | 1971 | { |
8fb033d7 | 1972 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1973 | |
1974 | /* PCH only available on ILK+ */ | |
55522f37 | 1975 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1976 | |
8fb033d7 | 1977 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1978 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1979 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1980 | |
223a6fdf PZ |
1981 | /* Workaround: set timing override bit. */ |
1982 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1984 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1985 | ||
25f3ef11 | 1986 | val = TRANS_ENABLE; |
937bb610 | 1987 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1988 | |
9a76b1c6 PZ |
1989 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1990 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1991 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1992 | else |
1993 | val |= TRANS_PROGRESSIVE; | |
1994 | ||
ab9412ba DV |
1995 | I915_WRITE(LPT_TRANSCONF, val); |
1996 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1997 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1998 | } |
1999 | ||
b8a4f404 PZ |
2000 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2001 | enum pipe pipe) | |
040484af | 2002 | { |
23670b32 DV |
2003 | struct drm_device *dev = dev_priv->dev; |
2004 | uint32_t reg, val; | |
040484af JB |
2005 | |
2006 | /* FDI relies on the transcoder */ | |
2007 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2008 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2009 | ||
291906f1 JB |
2010 | /* Ports must be off as well */ |
2011 | assert_pch_ports_disabled(dev_priv, pipe); | |
2012 | ||
ab9412ba | 2013 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2014 | val = I915_READ(reg); |
2015 | val &= ~TRANS_ENABLE; | |
2016 | I915_WRITE(reg, val); | |
2017 | /* wait for PCH transcoder off, transcoder state */ | |
2018 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2019 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2020 | |
2021 | if (!HAS_PCH_IBX(dev)) { | |
2022 | /* Workaround: Clear the timing override chicken bit again. */ | |
2023 | reg = TRANS_CHICKEN2(pipe); | |
2024 | val = I915_READ(reg); | |
2025 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2026 | I915_WRITE(reg, val); | |
2027 | } | |
040484af JB |
2028 | } |
2029 | ||
ab4d966c | 2030 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2031 | { |
8fb033d7 PZ |
2032 | u32 val; |
2033 | ||
ab9412ba | 2034 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2035 | val &= ~TRANS_ENABLE; |
ab9412ba | 2036 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2037 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2038 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2039 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2040 | |
2041 | /* Workaround: clear timing override bit. */ | |
2042 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2043 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2044 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2045 | } |
2046 | ||
b24e7179 | 2047 | /** |
309cfea8 | 2048 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2049 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2050 | * |
0372264a | 2051 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2052 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2053 | */ |
e1fdc473 | 2054 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2055 | { |
0372264a PZ |
2056 | struct drm_device *dev = crtc->base.dev; |
2057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2058 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2059 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2060 | pipe); | |
1a240d4d | 2061 | enum pipe pch_transcoder; |
b24e7179 JB |
2062 | int reg; |
2063 | u32 val; | |
2064 | ||
58c6eaa2 | 2065 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2066 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2067 | assert_sprites_disabled(dev_priv, pipe); |
2068 | ||
681e5811 | 2069 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2070 | pch_transcoder = TRANSCODER_A; |
2071 | else | |
2072 | pch_transcoder = pipe; | |
2073 | ||
b24e7179 JB |
2074 | /* |
2075 | * A pipe without a PLL won't actually be able to drive bits from | |
2076 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2077 | * need the check. | |
2078 | */ | |
2079 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2080 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2081 | assert_dsi_pll_enabled(dev_priv); |
2082 | else | |
2083 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2084 | else { |
6e3c9717 | 2085 | if (crtc->config->has_pch_encoder) { |
040484af | 2086 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2087 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2088 | assert_fdi_tx_pll_enabled(dev_priv, |
2089 | (enum pipe) cpu_transcoder); | |
040484af JB |
2090 | } |
2091 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2092 | } | |
b24e7179 | 2093 | |
702e7a56 | 2094 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2095 | val = I915_READ(reg); |
7ad25d48 | 2096 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2097 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2098 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2099 | return; |
7ad25d48 | 2100 | } |
00d70b15 CW |
2101 | |
2102 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2103 | POSTING_READ(reg); |
b24e7179 JB |
2104 | } |
2105 | ||
2106 | /** | |
309cfea8 | 2107 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2108 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2109 | * |
575f7ab7 VS |
2110 | * Disable the pipe of @crtc, making sure that various hardware |
2111 | * specific requirements are met, if applicable, e.g. plane | |
2112 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2113 | * |
2114 | * Will wait until the pipe has shut down before returning. | |
2115 | */ | |
575f7ab7 | 2116 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2117 | { |
575f7ab7 | 2118 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2119 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2120 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2121 | int reg; |
2122 | u32 val; | |
2123 | ||
2124 | /* | |
2125 | * Make sure planes won't keep trying to pump pixels to us, | |
2126 | * or we might hang the display. | |
2127 | */ | |
2128 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2129 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2130 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2131 | |
702e7a56 | 2132 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2133 | val = I915_READ(reg); |
00d70b15 CW |
2134 | if ((val & PIPECONF_ENABLE) == 0) |
2135 | return; | |
2136 | ||
67adc644 VS |
2137 | /* |
2138 | * Double wide has implications for planes | |
2139 | * so best keep it disabled when not needed. | |
2140 | */ | |
6e3c9717 | 2141 | if (crtc->config->double_wide) |
67adc644 VS |
2142 | val &= ~PIPECONF_DOUBLE_WIDE; |
2143 | ||
2144 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2145 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2146 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2147 | val &= ~PIPECONF_ENABLE; |
2148 | ||
2149 | I915_WRITE(reg, val); | |
2150 | if ((val & PIPECONF_ENABLE) == 0) | |
2151 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2152 | } |
2153 | ||
d74362c9 KP |
2154 | /* |
2155 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2156 | * trigger in order to latch. The display address reg provides this. | |
2157 | */ | |
1dba99f4 VS |
2158 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2159 | enum plane plane) | |
d74362c9 | 2160 | { |
3d13ef2e DL |
2161 | struct drm_device *dev = dev_priv->dev; |
2162 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2163 | |
2164 | I915_WRITE(reg, I915_READ(reg)); | |
2165 | POSTING_READ(reg); | |
d74362c9 KP |
2166 | } |
2167 | ||
b24e7179 | 2168 | /** |
262ca2b0 | 2169 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2170 | * @plane: plane to be enabled |
2171 | * @crtc: crtc for the plane | |
b24e7179 | 2172 | * |
fdd508a6 | 2173 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2174 | */ |
fdd508a6 VS |
2175 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2176 | struct drm_crtc *crtc) | |
b24e7179 | 2177 | { |
fdd508a6 VS |
2178 | struct drm_device *dev = plane->dev; |
2179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2181 | |
2182 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2183 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2184 | |
98ec7739 VS |
2185 | if (intel_crtc->primary_enabled) |
2186 | return; | |
0037f71c | 2187 | |
4c445e0e | 2188 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2189 | |
fdd508a6 VS |
2190 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2191 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2192 | |
2193 | /* | |
2194 | * BDW signals flip done immediately if the plane | |
2195 | * is disabled, even if the plane enable is already | |
2196 | * armed to occur at the next vblank :( | |
2197 | */ | |
2198 | if (IS_BROADWELL(dev)) | |
2199 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2200 | } |
2201 | ||
b24e7179 | 2202 | /** |
262ca2b0 | 2203 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2204 | * @plane: plane to be disabled |
2205 | * @crtc: crtc for the plane | |
b24e7179 | 2206 | * |
fdd508a6 | 2207 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2208 | */ |
fdd508a6 VS |
2209 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2210 | struct drm_crtc *crtc) | |
b24e7179 | 2211 | { |
fdd508a6 VS |
2212 | struct drm_device *dev = plane->dev; |
2213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2215 | ||
32b7eeec MR |
2216 | if (WARN_ON(!intel_crtc->active)) |
2217 | return; | |
b24e7179 | 2218 | |
98ec7739 VS |
2219 | if (!intel_crtc->primary_enabled) |
2220 | return; | |
0037f71c | 2221 | |
4c445e0e | 2222 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2223 | |
fdd508a6 VS |
2224 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2225 | crtc->x, crtc->y); | |
b24e7179 JB |
2226 | } |
2227 | ||
693db184 CW |
2228 | static bool need_vtd_wa(struct drm_device *dev) |
2229 | { | |
2230 | #ifdef CONFIG_INTEL_IOMMU | |
2231 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2232 | return true; | |
2233 | #endif | |
2234 | return false; | |
2235 | } | |
2236 | ||
50470bb0 | 2237 | unsigned int |
6761dd31 TU |
2238 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2239 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2240 | { |
6761dd31 TU |
2241 | unsigned int tile_height; |
2242 | uint32_t pixel_bytes; | |
a57ce0b2 | 2243 | |
b5d0e9bf DL |
2244 | switch (fb_format_modifier) { |
2245 | case DRM_FORMAT_MOD_NONE: | |
2246 | tile_height = 1; | |
2247 | break; | |
2248 | case I915_FORMAT_MOD_X_TILED: | |
2249 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2250 | break; | |
2251 | case I915_FORMAT_MOD_Y_TILED: | |
2252 | tile_height = 32; | |
2253 | break; | |
2254 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2255 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2256 | switch (pixel_bytes) { | |
b5d0e9bf | 2257 | default: |
6761dd31 | 2258 | case 1: |
b5d0e9bf DL |
2259 | tile_height = 64; |
2260 | break; | |
6761dd31 TU |
2261 | case 2: |
2262 | case 4: | |
b5d0e9bf DL |
2263 | tile_height = 32; |
2264 | break; | |
6761dd31 | 2265 | case 8: |
b5d0e9bf DL |
2266 | tile_height = 16; |
2267 | break; | |
6761dd31 | 2268 | case 16: |
b5d0e9bf DL |
2269 | WARN_ONCE(1, |
2270 | "128-bit pixels are not supported for display!"); | |
2271 | tile_height = 16; | |
2272 | break; | |
2273 | } | |
2274 | break; | |
2275 | default: | |
2276 | MISSING_CASE(fb_format_modifier); | |
2277 | tile_height = 1; | |
2278 | break; | |
2279 | } | |
091df6cb | 2280 | |
6761dd31 TU |
2281 | return tile_height; |
2282 | } | |
2283 | ||
2284 | unsigned int | |
2285 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2286 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2287 | { | |
2288 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2289 | fb_format_modifier)); | |
a57ce0b2 JB |
2290 | } |
2291 | ||
f64b98cd TU |
2292 | static int |
2293 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2294 | const struct drm_plane_state *plane_state) | |
2295 | { | |
50470bb0 TU |
2296 | struct intel_rotation_info *info = &view->rotation_info; |
2297 | static const struct i915_ggtt_view rotated_view = | |
2298 | { .type = I915_GGTT_VIEW_ROTATED }; | |
2299 | ||
f64b98cd TU |
2300 | *view = i915_ggtt_view_normal; |
2301 | ||
50470bb0 TU |
2302 | if (!plane_state) |
2303 | return 0; | |
2304 | ||
121920fa | 2305 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2306 | return 0; |
2307 | ||
2308 | *view = rotated_view; | |
2309 | ||
2310 | info->height = fb->height; | |
2311 | info->pixel_format = fb->pixel_format; | |
2312 | info->pitch = fb->pitches[0]; | |
2313 | info->fb_modifier = fb->modifier[0]; | |
2314 | ||
2315 | if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED || | |
2316 | info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) { | |
2317 | DRM_DEBUG_KMS( | |
2318 | "Y or Yf tiling is needed for 90/270 rotation!\n"); | |
2319 | return -EINVAL; | |
2320 | } | |
2321 | ||
f64b98cd TU |
2322 | return 0; |
2323 | } | |
2324 | ||
127bd2ac | 2325 | int |
850c4cdc TU |
2326 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2327 | struct drm_framebuffer *fb, | |
82bc3b2d | 2328 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2329 | struct intel_engine_cs *pipelined) |
6b95a207 | 2330 | { |
850c4cdc | 2331 | struct drm_device *dev = fb->dev; |
ce453d81 | 2332 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2333 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2334 | struct i915_ggtt_view view; |
6b95a207 KH |
2335 | u32 alignment; |
2336 | int ret; | |
2337 | ||
ebcdd39e MR |
2338 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2339 | ||
7b911adc TU |
2340 | switch (fb->modifier[0]) { |
2341 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2342 | if (INTEL_INFO(dev)->gen >= 9) |
2343 | alignment = 256 * 1024; | |
2344 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2345 | alignment = 128 * 1024; |
a6c45cf0 | 2346 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2347 | alignment = 4 * 1024; |
2348 | else | |
2349 | alignment = 64 * 1024; | |
6b95a207 | 2350 | break; |
7b911adc | 2351 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2352 | if (INTEL_INFO(dev)->gen >= 9) |
2353 | alignment = 256 * 1024; | |
2354 | else { | |
2355 | /* pin() will align the object as required by fence */ | |
2356 | alignment = 0; | |
2357 | } | |
6b95a207 | 2358 | break; |
7b911adc | 2359 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2360 | case I915_FORMAT_MOD_Yf_TILED: |
2361 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2362 | "Y tiling bo slipped through, driver bug!\n")) | |
2363 | return -EINVAL; | |
2364 | alignment = 1 * 1024 * 1024; | |
2365 | break; | |
6b95a207 | 2366 | default: |
7b911adc TU |
2367 | MISSING_CASE(fb->modifier[0]); |
2368 | return -EINVAL; | |
6b95a207 KH |
2369 | } |
2370 | ||
f64b98cd TU |
2371 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2372 | if (ret) | |
2373 | return ret; | |
2374 | ||
693db184 CW |
2375 | /* Note that the w/a also requires 64 PTE of padding following the |
2376 | * bo. We currently fill all unused PTE with the shadow page and so | |
2377 | * we should always have valid PTE following the scanout preventing | |
2378 | * the VT-d warning. | |
2379 | */ | |
2380 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2381 | alignment = 256 * 1024; | |
2382 | ||
d6dd6843 PZ |
2383 | /* |
2384 | * Global gtt pte registers are special registers which actually forward | |
2385 | * writes to a chunk of system memory. Which means that there is no risk | |
2386 | * that the register values disappear as soon as we call | |
2387 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2388 | * pin/unpin/fence and not more. | |
2389 | */ | |
2390 | intel_runtime_pm_get(dev_priv); | |
2391 | ||
ce453d81 | 2392 | dev_priv->mm.interruptible = false; |
e6617330 | 2393 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2394 | &view); |
48b956c5 | 2395 | if (ret) |
ce453d81 | 2396 | goto err_interruptible; |
6b95a207 KH |
2397 | |
2398 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2399 | * fence, whereas 965+ only requires a fence if using | |
2400 | * framebuffer compression. For simplicity, we always install | |
2401 | * a fence as the cost is not that onerous. | |
2402 | */ | |
06d98131 | 2403 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2404 | if (ret) |
2405 | goto err_unpin; | |
1690e1eb | 2406 | |
9a5a53b3 | 2407 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2408 | |
ce453d81 | 2409 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2410 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2411 | return 0; |
48b956c5 CW |
2412 | |
2413 | err_unpin: | |
f64b98cd | 2414 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2415 | err_interruptible: |
2416 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2417 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2418 | return ret; |
6b95a207 KH |
2419 | } |
2420 | ||
82bc3b2d TU |
2421 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2422 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2423 | { |
82bc3b2d | 2424 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2425 | struct i915_ggtt_view view; |
2426 | int ret; | |
82bc3b2d | 2427 | |
ebcdd39e MR |
2428 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2429 | ||
f64b98cd TU |
2430 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2431 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2432 | ||
1690e1eb | 2433 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2434 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2435 | } |
2436 | ||
c2c75131 DV |
2437 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2438 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2439 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2440 | unsigned int tiling_mode, | |
2441 | unsigned int cpp, | |
2442 | unsigned int pitch) | |
c2c75131 | 2443 | { |
bc752862 CW |
2444 | if (tiling_mode != I915_TILING_NONE) { |
2445 | unsigned int tile_rows, tiles; | |
c2c75131 | 2446 | |
bc752862 CW |
2447 | tile_rows = *y / 8; |
2448 | *y %= 8; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tiles = *x / (512/cpp); |
2451 | *x %= 512/cpp; | |
2452 | ||
2453 | return tile_rows * pitch * 8 + tiles * 4096; | |
2454 | } else { | |
2455 | unsigned int offset; | |
2456 | ||
2457 | offset = *y * pitch + *x * cpp; | |
2458 | *y = 0; | |
2459 | *x = (offset & 4095) / cpp; | |
2460 | return offset & -4096; | |
2461 | } | |
c2c75131 DV |
2462 | } |
2463 | ||
b35d63fa | 2464 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2465 | { |
2466 | switch (format) { | |
2467 | case DISPPLANE_8BPP: | |
2468 | return DRM_FORMAT_C8; | |
2469 | case DISPPLANE_BGRX555: | |
2470 | return DRM_FORMAT_XRGB1555; | |
2471 | case DISPPLANE_BGRX565: | |
2472 | return DRM_FORMAT_RGB565; | |
2473 | default: | |
2474 | case DISPPLANE_BGRX888: | |
2475 | return DRM_FORMAT_XRGB8888; | |
2476 | case DISPPLANE_RGBX888: | |
2477 | return DRM_FORMAT_XBGR8888; | |
2478 | case DISPPLANE_BGRX101010: | |
2479 | return DRM_FORMAT_XRGB2101010; | |
2480 | case DISPPLANE_RGBX101010: | |
2481 | return DRM_FORMAT_XBGR2101010; | |
2482 | } | |
2483 | } | |
2484 | ||
bc8d7dff DL |
2485 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2486 | { | |
2487 | switch (format) { | |
2488 | case PLANE_CTL_FORMAT_RGB_565: | |
2489 | return DRM_FORMAT_RGB565; | |
2490 | default: | |
2491 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2492 | if (rgb_order) { | |
2493 | if (alpha) | |
2494 | return DRM_FORMAT_ABGR8888; | |
2495 | else | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | } else { | |
2498 | if (alpha) | |
2499 | return DRM_FORMAT_ARGB8888; | |
2500 | else | |
2501 | return DRM_FORMAT_XRGB8888; | |
2502 | } | |
2503 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2504 | if (rgb_order) | |
2505 | return DRM_FORMAT_XBGR2101010; | |
2506 | else | |
2507 | return DRM_FORMAT_XRGB2101010; | |
2508 | } | |
2509 | } | |
2510 | ||
5724dbd1 | 2511 | static bool |
f6936e29 DV |
2512 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2513 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2514 | { |
2515 | struct drm_device *dev = crtc->base.dev; | |
2516 | struct drm_i915_gem_object *obj = NULL; | |
2517 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2518 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2519 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2520 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2521 | PAGE_SIZE); | |
2522 | ||
2523 | size_aligned -= base_aligned; | |
46f297fb | 2524 | |
ff2652ea CW |
2525 | if (plane_config->size == 0) |
2526 | return false; | |
2527 | ||
f37b5c2b DV |
2528 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2529 | base_aligned, | |
2530 | base_aligned, | |
2531 | size_aligned); | |
46f297fb | 2532 | if (!obj) |
484b41dd | 2533 | return false; |
46f297fb | 2534 | |
49af449b DL |
2535 | obj->tiling_mode = plane_config->tiling; |
2536 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2537 | obj->stride = fb->pitches[0]; |
46f297fb | 2538 | |
6bf129df DL |
2539 | mode_cmd.pixel_format = fb->pixel_format; |
2540 | mode_cmd.width = fb->width; | |
2541 | mode_cmd.height = fb->height; | |
2542 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2543 | mode_cmd.modifier[0] = fb->modifier[0]; |
2544 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2545 | |
2546 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2547 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2548 | &mode_cmd, obj)) { |
46f297fb JB |
2549 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2550 | goto out_unref_obj; | |
2551 | } | |
46f297fb | 2552 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2553 | |
f6936e29 | 2554 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2555 | return true; |
46f297fb JB |
2556 | |
2557 | out_unref_obj: | |
2558 | drm_gem_object_unreference(&obj->base); | |
2559 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2560 | return false; |
2561 | } | |
2562 | ||
afd65eb4 MR |
2563 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2564 | static void | |
2565 | update_state_fb(struct drm_plane *plane) | |
2566 | { | |
2567 | if (plane->fb == plane->state->fb) | |
2568 | return; | |
2569 | ||
2570 | if (plane->state->fb) | |
2571 | drm_framebuffer_unreference(plane->state->fb); | |
2572 | plane->state->fb = plane->fb; | |
2573 | if (plane->state->fb) | |
2574 | drm_framebuffer_reference(plane->state->fb); | |
2575 | } | |
2576 | ||
5724dbd1 | 2577 | static void |
f6936e29 DV |
2578 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2579 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2580 | { |
2581 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2582 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2583 | struct drm_crtc *c; |
2584 | struct intel_crtc *i; | |
2ff8fde1 | 2585 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2586 | struct drm_plane *primary = intel_crtc->base.primary; |
2587 | struct drm_framebuffer *fb; | |
484b41dd | 2588 | |
2d14030b | 2589 | if (!plane_config->fb) |
484b41dd JB |
2590 | return; |
2591 | ||
f6936e29 | 2592 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2593 | fb = &plane_config->fb->base; |
2594 | goto valid_fb; | |
f55548b5 | 2595 | } |
484b41dd | 2596 | |
2d14030b | 2597 | kfree(plane_config->fb); |
484b41dd JB |
2598 | |
2599 | /* | |
2600 | * Failed to alloc the obj, check to see if we should share | |
2601 | * an fb with another CRTC instead | |
2602 | */ | |
70e1e0ec | 2603 | for_each_crtc(dev, c) { |
484b41dd JB |
2604 | i = to_intel_crtc(c); |
2605 | ||
2606 | if (c == &intel_crtc->base) | |
2607 | continue; | |
2608 | ||
2ff8fde1 MR |
2609 | if (!i->active) |
2610 | continue; | |
2611 | ||
88595ac9 DV |
2612 | fb = c->primary->fb; |
2613 | if (!fb) | |
484b41dd JB |
2614 | continue; |
2615 | ||
88595ac9 | 2616 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2617 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2618 | drm_framebuffer_reference(fb); |
2619 | goto valid_fb; | |
484b41dd JB |
2620 | } |
2621 | } | |
88595ac9 DV |
2622 | |
2623 | return; | |
2624 | ||
2625 | valid_fb: | |
2626 | obj = intel_fb_obj(fb); | |
2627 | if (obj->tiling_mode != I915_TILING_NONE) | |
2628 | dev_priv->preserve_bios_swizzle = true; | |
2629 | ||
2630 | primary->fb = fb; | |
2631 | primary->state->crtc = &intel_crtc->base; | |
2632 | primary->crtc = &intel_crtc->base; | |
2633 | update_state_fb(primary); | |
2634 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2635 | } |
2636 | ||
29b9bde6 DV |
2637 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2638 | struct drm_framebuffer *fb, | |
2639 | int x, int y) | |
81255565 JB |
2640 | { |
2641 | struct drm_device *dev = crtc->dev; | |
2642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2644 | struct drm_i915_gem_object *obj; |
81255565 | 2645 | int plane = intel_crtc->plane; |
e506a0c6 | 2646 | unsigned long linear_offset; |
81255565 | 2647 | u32 dspcntr; |
f45651ba | 2648 | u32 reg = DSPCNTR(plane); |
48404c1e | 2649 | int pixel_size; |
f45651ba | 2650 | |
fdd508a6 VS |
2651 | if (!intel_crtc->primary_enabled) { |
2652 | I915_WRITE(reg, 0); | |
2653 | if (INTEL_INFO(dev)->gen >= 4) | |
2654 | I915_WRITE(DSPSURF(plane), 0); | |
2655 | else | |
2656 | I915_WRITE(DSPADDR(plane), 0); | |
2657 | POSTING_READ(reg); | |
2658 | return; | |
2659 | } | |
2660 | ||
c9ba6fad VS |
2661 | obj = intel_fb_obj(fb); |
2662 | if (WARN_ON(obj == NULL)) | |
2663 | return; | |
2664 | ||
2665 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2666 | ||
f45651ba VS |
2667 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2668 | ||
fdd508a6 | 2669 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2670 | |
2671 | if (INTEL_INFO(dev)->gen < 4) { | |
2672 | if (intel_crtc->pipe == PIPE_B) | |
2673 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2674 | ||
2675 | /* pipesrc and dspsize control the size that is scaled from, | |
2676 | * which should always be the user's requested size. | |
2677 | */ | |
2678 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2679 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2680 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2681 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2682 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2683 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2684 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2685 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2686 | I915_WRITE(PRIMPOS(plane), 0); |
2687 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2688 | } |
81255565 | 2689 | |
57779d06 VS |
2690 | switch (fb->pixel_format) { |
2691 | case DRM_FORMAT_C8: | |
81255565 JB |
2692 | dspcntr |= DISPPLANE_8BPP; |
2693 | break; | |
57779d06 VS |
2694 | case DRM_FORMAT_XRGB1555: |
2695 | case DRM_FORMAT_ARGB1555: | |
2696 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2697 | break; |
57779d06 VS |
2698 | case DRM_FORMAT_RGB565: |
2699 | dspcntr |= DISPPLANE_BGRX565; | |
2700 | break; | |
2701 | case DRM_FORMAT_XRGB8888: | |
2702 | case DRM_FORMAT_ARGB8888: | |
2703 | dspcntr |= DISPPLANE_BGRX888; | |
2704 | break; | |
2705 | case DRM_FORMAT_XBGR8888: | |
2706 | case DRM_FORMAT_ABGR8888: | |
2707 | dspcntr |= DISPPLANE_RGBX888; | |
2708 | break; | |
2709 | case DRM_FORMAT_XRGB2101010: | |
2710 | case DRM_FORMAT_ARGB2101010: | |
2711 | dspcntr |= DISPPLANE_BGRX101010; | |
2712 | break; | |
2713 | case DRM_FORMAT_XBGR2101010: | |
2714 | case DRM_FORMAT_ABGR2101010: | |
2715 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2716 | break; |
2717 | default: | |
baba133a | 2718 | BUG(); |
81255565 | 2719 | } |
57779d06 | 2720 | |
f45651ba VS |
2721 | if (INTEL_INFO(dev)->gen >= 4 && |
2722 | obj->tiling_mode != I915_TILING_NONE) | |
2723 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2724 | |
de1aa629 VS |
2725 | if (IS_G4X(dev)) |
2726 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2727 | ||
b9897127 | 2728 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2729 | |
c2c75131 DV |
2730 | if (INTEL_INFO(dev)->gen >= 4) { |
2731 | intel_crtc->dspaddr_offset = | |
bc752862 | 2732 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2733 | pixel_size, |
bc752862 | 2734 | fb->pitches[0]); |
c2c75131 DV |
2735 | linear_offset -= intel_crtc->dspaddr_offset; |
2736 | } else { | |
e506a0c6 | 2737 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2738 | } |
e506a0c6 | 2739 | |
8e7d688b | 2740 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2741 | dspcntr |= DISPPLANE_ROTATE_180; |
2742 | ||
6e3c9717 ACO |
2743 | x += (intel_crtc->config->pipe_src_w - 1); |
2744 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2745 | |
2746 | /* Finding the last pixel of the last line of the display | |
2747 | data and adding to linear_offset*/ | |
2748 | linear_offset += | |
6e3c9717 ACO |
2749 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2750 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2751 | } |
2752 | ||
2753 | I915_WRITE(reg, dspcntr); | |
2754 | ||
01f2c773 | 2755 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2756 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2757 | I915_WRITE(DSPSURF(plane), |
2758 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2759 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2760 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2761 | } else |
f343c5f6 | 2762 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2763 | POSTING_READ(reg); |
17638cd6 JB |
2764 | } |
2765 | ||
29b9bde6 DV |
2766 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2767 | struct drm_framebuffer *fb, | |
2768 | int x, int y) | |
17638cd6 JB |
2769 | { |
2770 | struct drm_device *dev = crtc->dev; | |
2771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2773 | struct drm_i915_gem_object *obj; |
17638cd6 | 2774 | int plane = intel_crtc->plane; |
e506a0c6 | 2775 | unsigned long linear_offset; |
17638cd6 | 2776 | u32 dspcntr; |
f45651ba | 2777 | u32 reg = DSPCNTR(plane); |
48404c1e | 2778 | int pixel_size; |
f45651ba | 2779 | |
fdd508a6 VS |
2780 | if (!intel_crtc->primary_enabled) { |
2781 | I915_WRITE(reg, 0); | |
2782 | I915_WRITE(DSPSURF(plane), 0); | |
2783 | POSTING_READ(reg); | |
2784 | return; | |
2785 | } | |
2786 | ||
c9ba6fad VS |
2787 | obj = intel_fb_obj(fb); |
2788 | if (WARN_ON(obj == NULL)) | |
2789 | return; | |
2790 | ||
2791 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2792 | ||
f45651ba VS |
2793 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2794 | ||
fdd508a6 | 2795 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2796 | |
2797 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2798 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2799 | |
57779d06 VS |
2800 | switch (fb->pixel_format) { |
2801 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2802 | dspcntr |= DISPPLANE_8BPP; |
2803 | break; | |
57779d06 VS |
2804 | case DRM_FORMAT_RGB565: |
2805 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2806 | break; |
57779d06 VS |
2807 | case DRM_FORMAT_XRGB8888: |
2808 | case DRM_FORMAT_ARGB8888: | |
2809 | dspcntr |= DISPPLANE_BGRX888; | |
2810 | break; | |
2811 | case DRM_FORMAT_XBGR8888: | |
2812 | case DRM_FORMAT_ABGR8888: | |
2813 | dspcntr |= DISPPLANE_RGBX888; | |
2814 | break; | |
2815 | case DRM_FORMAT_XRGB2101010: | |
2816 | case DRM_FORMAT_ARGB2101010: | |
2817 | dspcntr |= DISPPLANE_BGRX101010; | |
2818 | break; | |
2819 | case DRM_FORMAT_XBGR2101010: | |
2820 | case DRM_FORMAT_ABGR2101010: | |
2821 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2822 | break; |
2823 | default: | |
baba133a | 2824 | BUG(); |
17638cd6 JB |
2825 | } |
2826 | ||
2827 | if (obj->tiling_mode != I915_TILING_NONE) | |
2828 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2829 | |
f45651ba | 2830 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2831 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2832 | |
b9897127 | 2833 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2834 | intel_crtc->dspaddr_offset = |
bc752862 | 2835 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2836 | pixel_size, |
bc752862 | 2837 | fb->pitches[0]); |
c2c75131 | 2838 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2839 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2840 | dspcntr |= DISPPLANE_ROTATE_180; |
2841 | ||
2842 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2843 | x += (intel_crtc->config->pipe_src_w - 1); |
2844 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2845 | |
2846 | /* Finding the last pixel of the last line of the display | |
2847 | data and adding to linear_offset*/ | |
2848 | linear_offset += | |
6e3c9717 ACO |
2849 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2850 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2851 | } |
2852 | } | |
2853 | ||
2854 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2855 | |
01f2c773 | 2856 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2857 | I915_WRITE(DSPSURF(plane), |
2858 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2859 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2860 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2861 | } else { | |
2862 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2863 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2864 | } | |
17638cd6 | 2865 | POSTING_READ(reg); |
17638cd6 JB |
2866 | } |
2867 | ||
b321803d DL |
2868 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2869 | uint32_t pixel_format) | |
2870 | { | |
2871 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2872 | ||
2873 | /* | |
2874 | * The stride is either expressed as a multiple of 64 bytes | |
2875 | * chunks for linear buffers or in number of tiles for tiled | |
2876 | * buffers. | |
2877 | */ | |
2878 | switch (fb_modifier) { | |
2879 | case DRM_FORMAT_MOD_NONE: | |
2880 | return 64; | |
2881 | case I915_FORMAT_MOD_X_TILED: | |
2882 | if (INTEL_INFO(dev)->gen == 2) | |
2883 | return 128; | |
2884 | return 512; | |
2885 | case I915_FORMAT_MOD_Y_TILED: | |
2886 | /* No need to check for old gens and Y tiling since this is | |
2887 | * about the display engine and those will be blocked before | |
2888 | * we get here. | |
2889 | */ | |
2890 | return 128; | |
2891 | case I915_FORMAT_MOD_Yf_TILED: | |
2892 | if (bits_per_pixel == 8) | |
2893 | return 64; | |
2894 | else | |
2895 | return 128; | |
2896 | default: | |
2897 | MISSING_CASE(fb_modifier); | |
2898 | return 64; | |
2899 | } | |
2900 | } | |
2901 | ||
121920fa TU |
2902 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2903 | struct drm_i915_gem_object *obj) | |
2904 | { | |
2905 | enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL; | |
2906 | ||
2907 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
2908 | view = I915_GGTT_VIEW_ROTATED; | |
2909 | ||
2910 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2911 | } | |
2912 | ||
70d21f0e DL |
2913 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2914 | struct drm_framebuffer *fb, | |
2915 | int x, int y) | |
2916 | { | |
2917 | struct drm_device *dev = crtc->dev; | |
2918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2919 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
70d21f0e DL |
2920 | struct drm_i915_gem_object *obj; |
2921 | int pipe = intel_crtc->pipe; | |
b321803d | 2922 | u32 plane_ctl, stride_div; |
121920fa | 2923 | unsigned long surf_addr; |
70d21f0e DL |
2924 | |
2925 | if (!intel_crtc->primary_enabled) { | |
2926 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2927 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2928 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2929 | return; | |
2930 | } | |
2931 | ||
2932 | plane_ctl = PLANE_CTL_ENABLE | | |
2933 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2934 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2935 | ||
2936 | switch (fb->pixel_format) { | |
2937 | case DRM_FORMAT_RGB565: | |
2938 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2939 | break; | |
2940 | case DRM_FORMAT_XRGB8888: | |
2941 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2942 | break; | |
f75fb42a JN |
2943 | case DRM_FORMAT_ARGB8888: |
2944 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2945 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2946 | break; | |
70d21f0e DL |
2947 | case DRM_FORMAT_XBGR8888: |
2948 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2949 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2950 | break; | |
f75fb42a JN |
2951 | case DRM_FORMAT_ABGR8888: |
2952 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2953 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2954 | plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2955 | break; | |
70d21f0e DL |
2956 | case DRM_FORMAT_XRGB2101010: |
2957 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2958 | break; | |
2959 | case DRM_FORMAT_XBGR2101010: | |
2960 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2961 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2962 | break; | |
2963 | default: | |
2964 | BUG(); | |
2965 | } | |
2966 | ||
30af77c4 DV |
2967 | switch (fb->modifier[0]) { |
2968 | case DRM_FORMAT_MOD_NONE: | |
70d21f0e | 2969 | break; |
30af77c4 | 2970 | case I915_FORMAT_MOD_X_TILED: |
70d21f0e | 2971 | plane_ctl |= PLANE_CTL_TILED_X; |
b321803d DL |
2972 | break; |
2973 | case I915_FORMAT_MOD_Y_TILED: | |
2974 | plane_ctl |= PLANE_CTL_TILED_Y; | |
2975 | break; | |
2976 | case I915_FORMAT_MOD_Yf_TILED: | |
2977 | plane_ctl |= PLANE_CTL_TILED_YF; | |
70d21f0e DL |
2978 | break; |
2979 | default: | |
b321803d | 2980 | MISSING_CASE(fb->modifier[0]); |
70d21f0e DL |
2981 | } |
2982 | ||
2983 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
8e7d688b | 2984 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) |
1447dde0 | 2985 | plane_ctl |= PLANE_CTL_ROTATE_180; |
70d21f0e | 2986 | |
b321803d DL |
2987 | obj = intel_fb_obj(fb); |
2988 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
2989 | fb->pixel_format); | |
121920fa | 2990 | surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj); |
b321803d | 2991 | |
70d21f0e | 2992 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
70d21f0e DL |
2993 | I915_WRITE(PLANE_POS(pipe, 0), 0); |
2994 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2995 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
6e3c9717 ACO |
2996 | (intel_crtc->config->pipe_src_h - 1) << 16 | |
2997 | (intel_crtc->config->pipe_src_w - 1)); | |
b321803d | 2998 | I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); |
121920fa | 2999 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3000 | |
3001 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3002 | } | |
3003 | ||
17638cd6 JB |
3004 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3005 | static int | |
3006 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3007 | int x, int y, enum mode_set_atomic state) | |
3008 | { | |
3009 | struct drm_device *dev = crtc->dev; | |
3010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3011 | |
6b8e6ed0 CW |
3012 | if (dev_priv->display.disable_fbc) |
3013 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3014 | |
29b9bde6 DV |
3015 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3016 | ||
3017 | return 0; | |
81255565 JB |
3018 | } |
3019 | ||
7514747d | 3020 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3021 | { |
96a02917 VS |
3022 | struct drm_crtc *crtc; |
3023 | ||
70e1e0ec | 3024 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3026 | enum plane plane = intel_crtc->plane; | |
3027 | ||
3028 | intel_prepare_page_flip(dev, plane); | |
3029 | intel_finish_page_flip_plane(dev, plane); | |
3030 | } | |
7514747d VS |
3031 | } |
3032 | ||
3033 | static void intel_update_primary_planes(struct drm_device *dev) | |
3034 | { | |
3035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3036 | struct drm_crtc *crtc; | |
96a02917 | 3037 | |
70e1e0ec | 3038 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3040 | ||
51fd371b | 3041 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3042 | /* |
3043 | * FIXME: Once we have proper support for primary planes (and | |
3044 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3045 | * a NULL crtc->primary->fb. |
947fdaad | 3046 | */ |
f4510a27 | 3047 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3048 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3049 | crtc->primary->fb, |
262ca2b0 MR |
3050 | crtc->x, |
3051 | crtc->y); | |
51fd371b | 3052 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3053 | } |
3054 | } | |
3055 | ||
7514747d VS |
3056 | void intel_prepare_reset(struct drm_device *dev) |
3057 | { | |
f98ce92f VS |
3058 | struct drm_i915_private *dev_priv = to_i915(dev); |
3059 | struct intel_crtc *crtc; | |
3060 | ||
7514747d VS |
3061 | /* no reset support for gen2 */ |
3062 | if (IS_GEN2(dev)) | |
3063 | return; | |
3064 | ||
3065 | /* reset doesn't touch the display */ | |
3066 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3067 | return; | |
3068 | ||
3069 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3070 | |
3071 | /* | |
3072 | * Disabling the crtcs gracefully seems nicer. Also the | |
3073 | * g33 docs say we should at least disable all the planes. | |
3074 | */ | |
3075 | for_each_intel_crtc(dev, crtc) { | |
3076 | if (crtc->active) | |
3077 | dev_priv->display.crtc_disable(&crtc->base); | |
3078 | } | |
7514747d VS |
3079 | } |
3080 | ||
3081 | void intel_finish_reset(struct drm_device *dev) | |
3082 | { | |
3083 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3084 | ||
3085 | /* | |
3086 | * Flips in the rings will be nuked by the reset, | |
3087 | * so complete all pending flips so that user space | |
3088 | * will get its events and not get stuck. | |
3089 | */ | |
3090 | intel_complete_page_flips(dev); | |
3091 | ||
3092 | /* no reset support for gen2 */ | |
3093 | if (IS_GEN2(dev)) | |
3094 | return; | |
3095 | ||
3096 | /* reset doesn't touch the display */ | |
3097 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3098 | /* | |
3099 | * Flips in the rings have been nuked by the reset, | |
3100 | * so update the base address of all primary | |
3101 | * planes to the the last fb to make sure we're | |
3102 | * showing the correct fb after a reset. | |
3103 | */ | |
3104 | intel_update_primary_planes(dev); | |
3105 | return; | |
3106 | } | |
3107 | ||
3108 | /* | |
3109 | * The display has been reset as well, | |
3110 | * so need a full re-initialization. | |
3111 | */ | |
3112 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3113 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3114 | ||
3115 | intel_modeset_init_hw(dev); | |
3116 | ||
3117 | spin_lock_irq(&dev_priv->irq_lock); | |
3118 | if (dev_priv->display.hpd_irq_setup) | |
3119 | dev_priv->display.hpd_irq_setup(dev); | |
3120 | spin_unlock_irq(&dev_priv->irq_lock); | |
3121 | ||
3122 | intel_modeset_setup_hw_state(dev, true); | |
3123 | ||
3124 | intel_hpd_init(dev_priv); | |
3125 | ||
3126 | drm_modeset_unlock_all(dev); | |
3127 | } | |
3128 | ||
14667a4b CW |
3129 | static int |
3130 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3131 | { | |
2ff8fde1 | 3132 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3133 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3134 | bool was_interruptible = dev_priv->mm.interruptible; | |
3135 | int ret; | |
3136 | ||
14667a4b CW |
3137 | /* Big Hammer, we also need to ensure that any pending |
3138 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3139 | * current scanout is retired before unpinning the old | |
3140 | * framebuffer. | |
3141 | * | |
3142 | * This should only fail upon a hung GPU, in which case we | |
3143 | * can safely continue. | |
3144 | */ | |
3145 | dev_priv->mm.interruptible = false; | |
3146 | ret = i915_gem_object_finish_gpu(obj); | |
3147 | dev_priv->mm.interruptible = was_interruptible; | |
3148 | ||
3149 | return ret; | |
3150 | } | |
3151 | ||
7d5e3799 CW |
3152 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3153 | { | |
3154 | struct drm_device *dev = crtc->dev; | |
3155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3157 | bool pending; |
3158 | ||
3159 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3160 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3161 | return false; | |
3162 | ||
5e2d7afc | 3163 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3164 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3165 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3166 | |
3167 | return pending; | |
3168 | } | |
3169 | ||
e30e8f75 GP |
3170 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3171 | { | |
3172 | struct drm_device *dev = crtc->base.dev; | |
3173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3174 | const struct drm_display_mode *adjusted_mode; | |
3175 | ||
3176 | if (!i915.fastboot) | |
3177 | return; | |
3178 | ||
3179 | /* | |
3180 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3181 | * that in compute_mode_changes we check the native mode (not the pfit | |
3182 | * mode) to see if we can flip rather than do a full mode set. In the | |
3183 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3184 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3185 | * sized surface. | |
3186 | * | |
3187 | * To fix this properly, we need to hoist the checks up into | |
3188 | * compute_mode_changes (or above), check the actual pfit state and | |
3189 | * whether the platform allows pfit disable with pipe active, and only | |
3190 | * then update the pipesrc and pfit state, even on the flip path. | |
3191 | */ | |
3192 | ||
6e3c9717 | 3193 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3194 | |
3195 | I915_WRITE(PIPESRC(crtc->pipe), | |
3196 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3197 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3198 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3199 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3200 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3201 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3202 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3203 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3204 | } | |
6e3c9717 ACO |
3205 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3206 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3207 | } |
3208 | ||
5e84e1a4 ZW |
3209 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3210 | { | |
3211 | struct drm_device *dev = crtc->dev; | |
3212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3214 | int pipe = intel_crtc->pipe; | |
3215 | u32 reg, temp; | |
3216 | ||
3217 | /* enable normal train */ | |
3218 | reg = FDI_TX_CTL(pipe); | |
3219 | temp = I915_READ(reg); | |
61e499bf | 3220 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3221 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3222 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3223 | } else { |
3224 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3225 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3226 | } |
5e84e1a4 ZW |
3227 | I915_WRITE(reg, temp); |
3228 | ||
3229 | reg = FDI_RX_CTL(pipe); | |
3230 | temp = I915_READ(reg); | |
3231 | if (HAS_PCH_CPT(dev)) { | |
3232 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3233 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3234 | } else { | |
3235 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3236 | temp |= FDI_LINK_TRAIN_NONE; | |
3237 | } | |
3238 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3239 | ||
3240 | /* wait one idle pattern time */ | |
3241 | POSTING_READ(reg); | |
3242 | udelay(1000); | |
357555c0 JB |
3243 | |
3244 | /* IVB wants error correction enabled */ | |
3245 | if (IS_IVYBRIDGE(dev)) | |
3246 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3247 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3248 | } |
3249 | ||
8db9d77b ZW |
3250 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3251 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3252 | { | |
3253 | struct drm_device *dev = crtc->dev; | |
3254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3255 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3256 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3257 | u32 reg, temp, tries; |
8db9d77b | 3258 | |
1c8562f6 | 3259 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3260 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3261 | |
e1a44743 AJ |
3262 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3263 | for train result */ | |
5eddb70b CW |
3264 | reg = FDI_RX_IMR(pipe); |
3265 | temp = I915_READ(reg); | |
e1a44743 AJ |
3266 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3267 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3268 | I915_WRITE(reg, temp); |
3269 | I915_READ(reg); | |
e1a44743 AJ |
3270 | udelay(150); |
3271 | ||
8db9d77b | 3272 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3273 | reg = FDI_TX_CTL(pipe); |
3274 | temp = I915_READ(reg); | |
627eb5a3 | 3275 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3276 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3277 | temp &= ~FDI_LINK_TRAIN_NONE; |
3278 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3279 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3280 | |
5eddb70b CW |
3281 | reg = FDI_RX_CTL(pipe); |
3282 | temp = I915_READ(reg); | |
8db9d77b ZW |
3283 | temp &= ~FDI_LINK_TRAIN_NONE; |
3284 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3285 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3286 | ||
3287 | POSTING_READ(reg); | |
8db9d77b ZW |
3288 | udelay(150); |
3289 | ||
5b2adf89 | 3290 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3291 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3292 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3293 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3294 | |
5eddb70b | 3295 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3296 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3297 | temp = I915_READ(reg); |
8db9d77b ZW |
3298 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3299 | ||
3300 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3301 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3302 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3303 | break; |
3304 | } | |
8db9d77b | 3305 | } |
e1a44743 | 3306 | if (tries == 5) |
5eddb70b | 3307 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3308 | |
3309 | /* Train 2 */ | |
5eddb70b CW |
3310 | reg = FDI_TX_CTL(pipe); |
3311 | temp = I915_READ(reg); | |
8db9d77b ZW |
3312 | temp &= ~FDI_LINK_TRAIN_NONE; |
3313 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3314 | I915_WRITE(reg, temp); |
8db9d77b | 3315 | |
5eddb70b CW |
3316 | reg = FDI_RX_CTL(pipe); |
3317 | temp = I915_READ(reg); | |
8db9d77b ZW |
3318 | temp &= ~FDI_LINK_TRAIN_NONE; |
3319 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3320 | I915_WRITE(reg, temp); |
8db9d77b | 3321 | |
5eddb70b CW |
3322 | POSTING_READ(reg); |
3323 | udelay(150); | |
8db9d77b | 3324 | |
5eddb70b | 3325 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3326 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3327 | temp = I915_READ(reg); |
8db9d77b ZW |
3328 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3329 | ||
3330 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3331 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3332 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3333 | break; | |
3334 | } | |
8db9d77b | 3335 | } |
e1a44743 | 3336 | if (tries == 5) |
5eddb70b | 3337 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3338 | |
3339 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3340 | |
8db9d77b ZW |
3341 | } |
3342 | ||
0206e353 | 3343 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3344 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3345 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3346 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3347 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3348 | }; | |
3349 | ||
3350 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3351 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3352 | { | |
3353 | struct drm_device *dev = crtc->dev; | |
3354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3356 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3357 | u32 reg, temp, i, retry; |
8db9d77b | 3358 | |
e1a44743 AJ |
3359 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3360 | for train result */ | |
5eddb70b CW |
3361 | reg = FDI_RX_IMR(pipe); |
3362 | temp = I915_READ(reg); | |
e1a44743 AJ |
3363 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3364 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3365 | I915_WRITE(reg, temp); |
3366 | ||
3367 | POSTING_READ(reg); | |
e1a44743 AJ |
3368 | udelay(150); |
3369 | ||
8db9d77b | 3370 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3371 | reg = FDI_TX_CTL(pipe); |
3372 | temp = I915_READ(reg); | |
627eb5a3 | 3373 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3374 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3375 | temp &= ~FDI_LINK_TRAIN_NONE; |
3376 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3377 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3378 | /* SNB-B */ | |
3379 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3380 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3381 | |
d74cf324 DV |
3382 | I915_WRITE(FDI_RX_MISC(pipe), |
3383 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3384 | ||
5eddb70b CW |
3385 | reg = FDI_RX_CTL(pipe); |
3386 | temp = I915_READ(reg); | |
8db9d77b ZW |
3387 | if (HAS_PCH_CPT(dev)) { |
3388 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3389 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3390 | } else { | |
3391 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3392 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3393 | } | |
5eddb70b CW |
3394 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3395 | ||
3396 | POSTING_READ(reg); | |
8db9d77b ZW |
3397 | udelay(150); |
3398 | ||
0206e353 | 3399 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3400 | reg = FDI_TX_CTL(pipe); |
3401 | temp = I915_READ(reg); | |
8db9d77b ZW |
3402 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3403 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3404 | I915_WRITE(reg, temp); |
3405 | ||
3406 | POSTING_READ(reg); | |
8db9d77b ZW |
3407 | udelay(500); |
3408 | ||
fa37d39e SP |
3409 | for (retry = 0; retry < 5; retry++) { |
3410 | reg = FDI_RX_IIR(pipe); | |
3411 | temp = I915_READ(reg); | |
3412 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3413 | if (temp & FDI_RX_BIT_LOCK) { | |
3414 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3415 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3416 | break; | |
3417 | } | |
3418 | udelay(50); | |
8db9d77b | 3419 | } |
fa37d39e SP |
3420 | if (retry < 5) |
3421 | break; | |
8db9d77b ZW |
3422 | } |
3423 | if (i == 4) | |
5eddb70b | 3424 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3425 | |
3426 | /* Train 2 */ | |
5eddb70b CW |
3427 | reg = FDI_TX_CTL(pipe); |
3428 | temp = I915_READ(reg); | |
8db9d77b ZW |
3429 | temp &= ~FDI_LINK_TRAIN_NONE; |
3430 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3431 | if (IS_GEN6(dev)) { | |
3432 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3433 | /* SNB-B */ | |
3434 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3435 | } | |
5eddb70b | 3436 | I915_WRITE(reg, temp); |
8db9d77b | 3437 | |
5eddb70b CW |
3438 | reg = FDI_RX_CTL(pipe); |
3439 | temp = I915_READ(reg); | |
8db9d77b ZW |
3440 | if (HAS_PCH_CPT(dev)) { |
3441 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3442 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3443 | } else { | |
3444 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3445 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3446 | } | |
5eddb70b CW |
3447 | I915_WRITE(reg, temp); |
3448 | ||
3449 | POSTING_READ(reg); | |
8db9d77b ZW |
3450 | udelay(150); |
3451 | ||
0206e353 | 3452 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3453 | reg = FDI_TX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3456 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3457 | I915_WRITE(reg, temp); |
3458 | ||
3459 | POSTING_READ(reg); | |
8db9d77b ZW |
3460 | udelay(500); |
3461 | ||
fa37d39e SP |
3462 | for (retry = 0; retry < 5; retry++) { |
3463 | reg = FDI_RX_IIR(pipe); | |
3464 | temp = I915_READ(reg); | |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3466 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3467 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3468 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3469 | break; | |
3470 | } | |
3471 | udelay(50); | |
8db9d77b | 3472 | } |
fa37d39e SP |
3473 | if (retry < 5) |
3474 | break; | |
8db9d77b ZW |
3475 | } |
3476 | if (i == 4) | |
5eddb70b | 3477 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3480 | } | |
3481 | ||
357555c0 JB |
3482 | /* Manual link training for Ivy Bridge A0 parts */ |
3483 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3484 | { | |
3485 | struct drm_device *dev = crtc->dev; | |
3486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3488 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3489 | u32 reg, temp, i, j; |
357555c0 JB |
3490 | |
3491 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3492 | for train result */ | |
3493 | reg = FDI_RX_IMR(pipe); | |
3494 | temp = I915_READ(reg); | |
3495 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3496 | temp &= ~FDI_RX_BIT_LOCK; | |
3497 | I915_WRITE(reg, temp); | |
3498 | ||
3499 | POSTING_READ(reg); | |
3500 | udelay(150); | |
3501 | ||
01a415fd DV |
3502 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3503 | I915_READ(FDI_RX_IIR(pipe))); | |
3504 | ||
139ccd3f JB |
3505 | /* Try each vswing and preemphasis setting twice before moving on */ |
3506 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3507 | /* disable first in case we need to retry */ | |
3508 | reg = FDI_TX_CTL(pipe); | |
3509 | temp = I915_READ(reg); | |
3510 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3511 | temp &= ~FDI_TX_ENABLE; | |
3512 | I915_WRITE(reg, temp); | |
357555c0 | 3513 | |
139ccd3f JB |
3514 | reg = FDI_RX_CTL(pipe); |
3515 | temp = I915_READ(reg); | |
3516 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3517 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3518 | temp &= ~FDI_RX_ENABLE; | |
3519 | I915_WRITE(reg, temp); | |
357555c0 | 3520 | |
139ccd3f | 3521 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3522 | reg = FDI_TX_CTL(pipe); |
3523 | temp = I915_READ(reg); | |
139ccd3f | 3524 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3525 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3526 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3527 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3528 | temp |= snb_b_fdi_train_param[j/2]; |
3529 | temp |= FDI_COMPOSITE_SYNC; | |
3530 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3531 | |
139ccd3f JB |
3532 | I915_WRITE(FDI_RX_MISC(pipe), |
3533 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3534 | |
139ccd3f | 3535 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3536 | temp = I915_READ(reg); |
139ccd3f JB |
3537 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3538 | temp |= FDI_COMPOSITE_SYNC; | |
3539 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3540 | |
139ccd3f JB |
3541 | POSTING_READ(reg); |
3542 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3543 | |
139ccd3f JB |
3544 | for (i = 0; i < 4; i++) { |
3545 | reg = FDI_RX_IIR(pipe); | |
3546 | temp = I915_READ(reg); | |
3547 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3548 | |
139ccd3f JB |
3549 | if (temp & FDI_RX_BIT_LOCK || |
3550 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3551 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3552 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3553 | i); | |
3554 | break; | |
3555 | } | |
3556 | udelay(1); /* should be 0.5us */ | |
3557 | } | |
3558 | if (i == 4) { | |
3559 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3560 | continue; | |
3561 | } | |
357555c0 | 3562 | |
139ccd3f | 3563 | /* Train 2 */ |
357555c0 JB |
3564 | reg = FDI_TX_CTL(pipe); |
3565 | temp = I915_READ(reg); | |
139ccd3f JB |
3566 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3567 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3568 | I915_WRITE(reg, temp); | |
3569 | ||
3570 | reg = FDI_RX_CTL(pipe); | |
3571 | temp = I915_READ(reg); | |
3572 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3573 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3574 | I915_WRITE(reg, temp); |
3575 | ||
3576 | POSTING_READ(reg); | |
139ccd3f | 3577 | udelay(2); /* should be 1.5us */ |
357555c0 | 3578 | |
139ccd3f JB |
3579 | for (i = 0; i < 4; i++) { |
3580 | reg = FDI_RX_IIR(pipe); | |
3581 | temp = I915_READ(reg); | |
3582 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3583 | |
139ccd3f JB |
3584 | if (temp & FDI_RX_SYMBOL_LOCK || |
3585 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3586 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3587 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3588 | i); | |
3589 | goto train_done; | |
3590 | } | |
3591 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3592 | } |
139ccd3f JB |
3593 | if (i == 4) |
3594 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3595 | } |
357555c0 | 3596 | |
139ccd3f | 3597 | train_done: |
357555c0 JB |
3598 | DRM_DEBUG_KMS("FDI train done.\n"); |
3599 | } | |
3600 | ||
88cefb6c | 3601 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3602 | { |
88cefb6c | 3603 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3604 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3605 | int pipe = intel_crtc->pipe; |
5eddb70b | 3606 | u32 reg, temp; |
79e53945 | 3607 | |
c64e311e | 3608 | |
c98e9dcf | 3609 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3610 | reg = FDI_RX_CTL(pipe); |
3611 | temp = I915_READ(reg); | |
627eb5a3 | 3612 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3613 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3614 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3615 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3616 | ||
3617 | POSTING_READ(reg); | |
c98e9dcf JB |
3618 | udelay(200); |
3619 | ||
3620 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3621 | temp = I915_READ(reg); |
3622 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3623 | ||
3624 | POSTING_READ(reg); | |
c98e9dcf JB |
3625 | udelay(200); |
3626 | ||
20749730 PZ |
3627 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3628 | reg = FDI_TX_CTL(pipe); | |
3629 | temp = I915_READ(reg); | |
3630 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3631 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3632 | |
20749730 PZ |
3633 | POSTING_READ(reg); |
3634 | udelay(100); | |
6be4a607 | 3635 | } |
0e23b99d JB |
3636 | } |
3637 | ||
88cefb6c DV |
3638 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3639 | { | |
3640 | struct drm_device *dev = intel_crtc->base.dev; | |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3642 | int pipe = intel_crtc->pipe; | |
3643 | u32 reg, temp; | |
3644 | ||
3645 | /* Switch from PCDclk to Rawclk */ | |
3646 | reg = FDI_RX_CTL(pipe); | |
3647 | temp = I915_READ(reg); | |
3648 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3649 | ||
3650 | /* Disable CPU FDI TX PLL */ | |
3651 | reg = FDI_TX_CTL(pipe); | |
3652 | temp = I915_READ(reg); | |
3653 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3654 | ||
3655 | POSTING_READ(reg); | |
3656 | udelay(100); | |
3657 | ||
3658 | reg = FDI_RX_CTL(pipe); | |
3659 | temp = I915_READ(reg); | |
3660 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3661 | ||
3662 | /* Wait for the clocks to turn off. */ | |
3663 | POSTING_READ(reg); | |
3664 | udelay(100); | |
3665 | } | |
3666 | ||
0fc932b8 JB |
3667 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3668 | { | |
3669 | struct drm_device *dev = crtc->dev; | |
3670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3671 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3672 | int pipe = intel_crtc->pipe; | |
3673 | u32 reg, temp; | |
3674 | ||
3675 | /* disable CPU FDI tx and PCH FDI rx */ | |
3676 | reg = FDI_TX_CTL(pipe); | |
3677 | temp = I915_READ(reg); | |
3678 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3679 | POSTING_READ(reg); | |
3680 | ||
3681 | reg = FDI_RX_CTL(pipe); | |
3682 | temp = I915_READ(reg); | |
3683 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3684 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3685 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3686 | ||
3687 | POSTING_READ(reg); | |
3688 | udelay(100); | |
3689 | ||
3690 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3691 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3692 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3693 | |
3694 | /* still set train pattern 1 */ | |
3695 | reg = FDI_TX_CTL(pipe); | |
3696 | temp = I915_READ(reg); | |
3697 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3698 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3699 | I915_WRITE(reg, temp); | |
3700 | ||
3701 | reg = FDI_RX_CTL(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | if (HAS_PCH_CPT(dev)) { | |
3704 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3705 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3706 | } else { | |
3707 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3708 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3709 | } | |
3710 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3711 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3712 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3713 | I915_WRITE(reg, temp); |
3714 | ||
3715 | POSTING_READ(reg); | |
3716 | udelay(100); | |
3717 | } | |
3718 | ||
5dce5b93 CW |
3719 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3720 | { | |
3721 | struct intel_crtc *crtc; | |
3722 | ||
3723 | /* Note that we don't need to be called with mode_config.lock here | |
3724 | * as our list of CRTC objects is static for the lifetime of the | |
3725 | * device and so cannot disappear as we iterate. Similarly, we can | |
3726 | * happily treat the predicates as racy, atomic checks as userspace | |
3727 | * cannot claim and pin a new fb without at least acquring the | |
3728 | * struct_mutex and so serialising with us. | |
3729 | */ | |
d3fcc808 | 3730 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3731 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3732 | continue; | |
3733 | ||
3734 | if (crtc->unpin_work) | |
3735 | intel_wait_for_vblank(dev, crtc->pipe); | |
3736 | ||
3737 | return true; | |
3738 | } | |
3739 | ||
3740 | return false; | |
3741 | } | |
3742 | ||
d6bbafa1 CW |
3743 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3744 | { | |
3745 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3746 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3747 | ||
3748 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3749 | smp_rmb(); | |
3750 | intel_crtc->unpin_work = NULL; | |
3751 | ||
3752 | if (work->event) | |
3753 | drm_send_vblank_event(intel_crtc->base.dev, | |
3754 | intel_crtc->pipe, | |
3755 | work->event); | |
3756 | ||
3757 | drm_crtc_vblank_put(&intel_crtc->base); | |
3758 | ||
3759 | wake_up_all(&dev_priv->pending_flip_queue); | |
3760 | queue_work(dev_priv->wq, &work->work); | |
3761 | ||
3762 | trace_i915_flip_complete(intel_crtc->plane, | |
3763 | work->pending_flip_obj); | |
3764 | } | |
3765 | ||
46a55d30 | 3766 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3767 | { |
0f91128d | 3768 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3769 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3770 | |
2c10d571 | 3771 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3772 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3773 | !intel_crtc_has_pending_flip(crtc), | |
3774 | 60*HZ) == 0)) { | |
3775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3776 | |
5e2d7afc | 3777 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3778 | if (intel_crtc->unpin_work) { |
3779 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3780 | page_flip_completed(intel_crtc); | |
3781 | } | |
5e2d7afc | 3782 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3783 | } |
5bb61643 | 3784 | |
975d568a CW |
3785 | if (crtc->primary->fb) { |
3786 | mutex_lock(&dev->struct_mutex); | |
3787 | intel_finish_fb(crtc->primary->fb); | |
3788 | mutex_unlock(&dev->struct_mutex); | |
3789 | } | |
e6c3a2a6 CW |
3790 | } |
3791 | ||
e615efe4 ED |
3792 | /* Program iCLKIP clock to the desired frequency */ |
3793 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3794 | { | |
3795 | struct drm_device *dev = crtc->dev; | |
3796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3797 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3798 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3799 | u32 temp; | |
3800 | ||
09153000 DV |
3801 | mutex_lock(&dev_priv->dpio_lock); |
3802 | ||
e615efe4 ED |
3803 | /* It is necessary to ungate the pixclk gate prior to programming |
3804 | * the divisors, and gate it back when it is done. | |
3805 | */ | |
3806 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3807 | ||
3808 | /* Disable SSCCTL */ | |
3809 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3810 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3811 | SBI_SSCCTL_DISABLE, | |
3812 | SBI_ICLK); | |
e615efe4 ED |
3813 | |
3814 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3815 | if (clock == 20000) { |
e615efe4 ED |
3816 | auxdiv = 1; |
3817 | divsel = 0x41; | |
3818 | phaseinc = 0x20; | |
3819 | } else { | |
3820 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3821 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3822 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3823 | * convert the virtual clock precision to KHz here for higher |
3824 | * precision. | |
3825 | */ | |
3826 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3827 | u32 iclk_pi_range = 64; | |
3828 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3829 | ||
12d7ceed | 3830 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3831 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3832 | pi_value = desired_divisor % iclk_pi_range; | |
3833 | ||
3834 | auxdiv = 0; | |
3835 | divsel = msb_divisor_value - 2; | |
3836 | phaseinc = pi_value; | |
3837 | } | |
3838 | ||
3839 | /* This should not happen with any sane values */ | |
3840 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3841 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3842 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3843 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3844 | ||
3845 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3846 | clock, |
e615efe4 ED |
3847 | auxdiv, |
3848 | divsel, | |
3849 | phasedir, | |
3850 | phaseinc); | |
3851 | ||
3852 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3853 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3854 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3855 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3856 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3857 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3858 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3859 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3860 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3861 | |
3862 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3863 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3864 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3865 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3866 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3867 | |
3868 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3869 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3870 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3871 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3872 | |
3873 | /* Wait for initialization time */ | |
3874 | udelay(24); | |
3875 | ||
3876 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3877 | |
3878 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3879 | } |
3880 | ||
275f01b2 DV |
3881 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3882 | enum pipe pch_transcoder) | |
3883 | { | |
3884 | struct drm_device *dev = crtc->base.dev; | |
3885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3886 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3887 | |
3888 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3889 | I915_READ(HTOTAL(cpu_transcoder))); | |
3890 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3891 | I915_READ(HBLANK(cpu_transcoder))); | |
3892 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3893 | I915_READ(HSYNC(cpu_transcoder))); | |
3894 | ||
3895 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3896 | I915_READ(VTOTAL(cpu_transcoder))); | |
3897 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3898 | I915_READ(VBLANK(cpu_transcoder))); | |
3899 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3900 | I915_READ(VSYNC(cpu_transcoder))); | |
3901 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3902 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3903 | } | |
3904 | ||
003632d9 | 3905 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
3906 | { |
3907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3908 | uint32_t temp; | |
3909 | ||
3910 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 3911 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
3912 | return; |
3913 | ||
3914 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3915 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3916 | ||
003632d9 ACO |
3917 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
3918 | if (enable) | |
3919 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3920 | ||
3921 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
3922 | I915_WRITE(SOUTH_CHICKEN1, temp); |
3923 | POSTING_READ(SOUTH_CHICKEN1); | |
3924 | } | |
3925 | ||
3926 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3927 | { | |
3928 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
3929 | |
3930 | switch (intel_crtc->pipe) { | |
3931 | case PIPE_A: | |
3932 | break; | |
3933 | case PIPE_B: | |
6e3c9717 | 3934 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 3935 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 3936 | else |
003632d9 | 3937 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3938 | |
3939 | break; | |
3940 | case PIPE_C: | |
003632d9 | 3941 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
3942 | |
3943 | break; | |
3944 | default: | |
3945 | BUG(); | |
3946 | } | |
3947 | } | |
3948 | ||
f67a559d JB |
3949 | /* |
3950 | * Enable PCH resources required for PCH ports: | |
3951 | * - PCH PLLs | |
3952 | * - FDI training & RX/TX | |
3953 | * - update transcoder timings | |
3954 | * - DP transcoding bits | |
3955 | * - transcoder | |
3956 | */ | |
3957 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3958 | { |
3959 | struct drm_device *dev = crtc->dev; | |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3962 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3963 | u32 reg, temp; |
2c07245f | 3964 | |
ab9412ba | 3965 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3966 | |
1fbc0d78 DV |
3967 | if (IS_IVYBRIDGE(dev)) |
3968 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3969 | ||
cd986abb DV |
3970 | /* Write the TU size bits before fdi link training, so that error |
3971 | * detection works. */ | |
3972 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3973 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3974 | ||
c98e9dcf | 3975 | /* For PCH output, training FDI link */ |
674cf967 | 3976 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3977 | |
3ad8a208 DV |
3978 | /* We need to program the right clock selection before writing the pixel |
3979 | * mutliplier into the DPLL. */ | |
303b81e0 | 3980 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3981 | u32 sel; |
4b645f14 | 3982 | |
c98e9dcf | 3983 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3984 | temp |= TRANS_DPLL_ENABLE(pipe); |
3985 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 3986 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3987 | temp |= sel; |
3988 | else | |
3989 | temp &= ~sel; | |
c98e9dcf | 3990 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3991 | } |
5eddb70b | 3992 | |
3ad8a208 DV |
3993 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3994 | * transcoder, and we actually should do this to not upset any PCH | |
3995 | * transcoder that already use the clock when we share it. | |
3996 | * | |
3997 | * Note that enable_shared_dpll tries to do the right thing, but | |
3998 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3999 | * the right LVDS enable sequence. */ | |
85b3894f | 4000 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4001 | |
d9b6cb56 JB |
4002 | /* set transcoder timing, panel must allow it */ |
4003 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4004 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4005 | |
303b81e0 | 4006 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4007 | |
c98e9dcf | 4008 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4009 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4010 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4011 | reg = TRANS_DP_CTL(pipe); |
4012 | temp = I915_READ(reg); | |
4013 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4014 | TRANS_DP_SYNC_MASK | |
4015 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4016 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4017 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4018 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4019 | |
4020 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4021 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4022 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4023 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4024 | |
4025 | switch (intel_trans_dp_port_sel(crtc)) { | |
4026 | case PCH_DP_B: | |
5eddb70b | 4027 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4028 | break; |
4029 | case PCH_DP_C: | |
5eddb70b | 4030 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4031 | break; |
4032 | case PCH_DP_D: | |
5eddb70b | 4033 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4034 | break; |
4035 | default: | |
e95d41e1 | 4036 | BUG(); |
32f9d658 | 4037 | } |
2c07245f | 4038 | |
5eddb70b | 4039 | I915_WRITE(reg, temp); |
6be4a607 | 4040 | } |
b52eb4dc | 4041 | |
b8a4f404 | 4042 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4043 | } |
4044 | ||
1507e5bd PZ |
4045 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4046 | { | |
4047 | struct drm_device *dev = crtc->dev; | |
4048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4050 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4051 | |
ab9412ba | 4052 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4053 | |
8c52b5e8 | 4054 | lpt_program_iclkip(crtc); |
1507e5bd | 4055 | |
0540e488 | 4056 | /* Set transcoder timing. */ |
275f01b2 | 4057 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4058 | |
937bb610 | 4059 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4060 | } |
4061 | ||
716c2e55 | 4062 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4063 | { |
e2b78267 | 4064 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4065 | |
4066 | if (pll == NULL) | |
4067 | return; | |
4068 | ||
3e369b76 | 4069 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4070 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4071 | return; |
4072 | } | |
4073 | ||
3e369b76 ACO |
4074 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4075 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4076 | WARN_ON(pll->on); |
4077 | WARN_ON(pll->active); | |
4078 | } | |
4079 | ||
6e3c9717 | 4080 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4081 | } |
4082 | ||
190f68c5 ACO |
4083 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4084 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4085 | { |
e2b78267 | 4086 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4087 | struct intel_shared_dpll *pll; |
e2b78267 | 4088 | enum intel_dpll_id i; |
ee7b9f93 | 4089 | |
98b6bd99 DV |
4090 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4091 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4092 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4093 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4094 | |
46edb027 DV |
4095 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4096 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4097 | |
8bd31e67 | 4098 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4099 | |
98b6bd99 DV |
4100 | goto found; |
4101 | } | |
4102 | ||
e72f9fbf DV |
4103 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4104 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4105 | |
4106 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4107 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4108 | continue; |
4109 | ||
190f68c5 | 4110 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4111 | &pll->new_config->hw_state, |
4112 | sizeof(pll->new_config->hw_state)) == 0) { | |
4113 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4114 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4115 | pll->new_config->crtc_mask, |
4116 | pll->active); | |
ee7b9f93 JB |
4117 | goto found; |
4118 | } | |
4119 | } | |
4120 | ||
4121 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4122 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4123 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4124 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4125 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4126 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4127 | goto found; |
4128 | } | |
4129 | } | |
4130 | ||
4131 | return NULL; | |
4132 | ||
4133 | found: | |
8bd31e67 | 4134 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4135 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4136 | |
190f68c5 | 4137 | crtc_state->shared_dpll = i; |
46edb027 DV |
4138 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4139 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4140 | |
8bd31e67 | 4141 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4142 | |
ee7b9f93 JB |
4143 | return pll; |
4144 | } | |
4145 | ||
8bd31e67 ACO |
4146 | /** |
4147 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4148 | * @dev_priv: DRM device | |
4149 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4150 | * | |
4151 | * Starts a new PLL staged config, copying the current config but | |
4152 | * releasing the references of pipes specified in clear_pipes. | |
4153 | */ | |
4154 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4155 | unsigned clear_pipes) | |
4156 | { | |
4157 | struct intel_shared_dpll *pll; | |
4158 | enum intel_dpll_id i; | |
4159 | ||
4160 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4161 | pll = &dev_priv->shared_dplls[i]; | |
4162 | ||
4163 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4164 | GFP_KERNEL); | |
4165 | if (!pll->new_config) | |
4166 | goto cleanup; | |
4167 | ||
4168 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4169 | } | |
4170 | ||
4171 | return 0; | |
4172 | ||
4173 | cleanup: | |
4174 | while (--i >= 0) { | |
4175 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4176 | kfree(pll->new_config); |
8bd31e67 ACO |
4177 | pll->new_config = NULL; |
4178 | } | |
4179 | ||
4180 | return -ENOMEM; | |
4181 | } | |
4182 | ||
4183 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4184 | { | |
4185 | struct intel_shared_dpll *pll; | |
4186 | enum intel_dpll_id i; | |
4187 | ||
4188 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4189 | pll = &dev_priv->shared_dplls[i]; | |
4190 | ||
4191 | WARN_ON(pll->new_config == &pll->config); | |
4192 | ||
4193 | pll->config = *pll->new_config; | |
4194 | kfree(pll->new_config); | |
4195 | pll->new_config = NULL; | |
4196 | } | |
4197 | } | |
4198 | ||
4199 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4200 | { | |
4201 | struct intel_shared_dpll *pll; | |
4202 | enum intel_dpll_id i; | |
4203 | ||
4204 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4205 | pll = &dev_priv->shared_dplls[i]; | |
4206 | ||
4207 | WARN_ON(pll->new_config == &pll->config); | |
4208 | ||
4209 | kfree(pll->new_config); | |
4210 | pll->new_config = NULL; | |
4211 | } | |
4212 | } | |
4213 | ||
a1520318 | 4214 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4215 | { |
4216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4217 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4218 | u32 temp; |
4219 | ||
4220 | temp = I915_READ(dslreg); | |
4221 | udelay(500); | |
4222 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4223 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4224 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4225 | } |
4226 | } | |
4227 | ||
bd2e244f JB |
4228 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4229 | { | |
4230 | struct drm_device *dev = crtc->base.dev; | |
4231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4232 | int pipe = crtc->pipe; | |
4233 | ||
6e3c9717 | 4234 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f | 4235 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); |
6e3c9717 ACO |
4236 | I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4237 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4238 | } |
4239 | } | |
4240 | ||
b074cec8 JB |
4241 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4242 | { | |
4243 | struct drm_device *dev = crtc->base.dev; | |
4244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4245 | int pipe = crtc->pipe; | |
4246 | ||
6e3c9717 | 4247 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4248 | /* Force use of hard-coded filter coefficients |
4249 | * as some pre-programmed values are broken, | |
4250 | * e.g. x201. | |
4251 | */ | |
4252 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4253 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4254 | PF_PIPE_SEL_IVB(pipe)); | |
4255 | else | |
4256 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4257 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4258 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4259 | } |
4260 | } | |
4261 | ||
4a3b8769 | 4262 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4263 | { |
4264 | struct drm_device *dev = crtc->dev; | |
4265 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4266 | struct drm_plane *plane; |
bb53d4ae VS |
4267 | struct intel_plane *intel_plane; |
4268 | ||
af2b653b MR |
4269 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4270 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4271 | if (intel_plane->pipe == pipe) |
4272 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4273 | } |
bb53d4ae VS |
4274 | } |
4275 | ||
0d703d4e MR |
4276 | /* |
4277 | * Disable a plane internally without actually modifying the plane's state. | |
4278 | * This will allow us to easily restore the plane later by just reprogramming | |
4279 | * its state. | |
4280 | */ | |
4281 | static void disable_plane_internal(struct drm_plane *plane) | |
4282 | { | |
4283 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4284 | struct drm_plane_state *state = | |
4285 | plane->funcs->atomic_duplicate_state(plane); | |
4286 | struct intel_plane_state *intel_state = to_intel_plane_state(state); | |
4287 | ||
4288 | intel_state->visible = false; | |
4289 | intel_plane->commit_plane(plane, intel_state); | |
4290 | ||
4291 | intel_plane_destroy_state(plane, state); | |
4292 | } | |
4293 | ||
4a3b8769 | 4294 | static void intel_disable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4295 | { |
4296 | struct drm_device *dev = crtc->dev; | |
4297 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4298 | struct drm_plane *plane; |
bb53d4ae VS |
4299 | struct intel_plane *intel_plane; |
4300 | ||
af2b653b MR |
4301 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4302 | intel_plane = to_intel_plane(plane); | |
0d703d4e MR |
4303 | if (plane->fb && intel_plane->pipe == pipe) |
4304 | disable_plane_internal(plane); | |
af2b653b | 4305 | } |
bb53d4ae VS |
4306 | } |
4307 | ||
20bc8673 | 4308 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4309 | { |
cea165c3 VS |
4310 | struct drm_device *dev = crtc->base.dev; |
4311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4312 | |
6e3c9717 | 4313 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4314 | return; |
4315 | ||
cea165c3 VS |
4316 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4317 | intel_wait_for_vblank(dev, crtc->pipe); | |
4318 | ||
d77e4531 | 4319 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4320 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4321 | mutex_lock(&dev_priv->rps.hw_lock); |
4322 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4323 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4324 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4325 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4326 | * mailbox." Moreover, the mailbox may return a bogus state, |
4327 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4328 | */ |
4329 | } else { | |
4330 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4331 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4332 | * is essentially intel_wait_for_vblank. If we don't have this | |
4333 | * and don't wait for vblanks until the end of crtc_enable, then | |
4334 | * the HW state readout code will complain that the expected | |
4335 | * IPS_CTL value is not the one we read. */ | |
4336 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4337 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4338 | } | |
d77e4531 PZ |
4339 | } |
4340 | ||
20bc8673 | 4341 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4342 | { |
4343 | struct drm_device *dev = crtc->base.dev; | |
4344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4345 | ||
6e3c9717 | 4346 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4347 | return; |
4348 | ||
4349 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4350 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4351 | mutex_lock(&dev_priv->rps.hw_lock); |
4352 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4353 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4354 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4355 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4356 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4357 | } else { |
2a114cc1 | 4358 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4359 | POSTING_READ(IPS_CTL); |
4360 | } | |
d77e4531 PZ |
4361 | |
4362 | /* We need to wait for a vblank before we can disable the plane. */ | |
4363 | intel_wait_for_vblank(dev, crtc->pipe); | |
4364 | } | |
4365 | ||
4366 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4367 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4368 | { | |
4369 | struct drm_device *dev = crtc->dev; | |
4370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4372 | enum pipe pipe = intel_crtc->pipe; | |
4373 | int palreg = PALETTE(pipe); | |
4374 | int i; | |
4375 | bool reenable_ips = false; | |
4376 | ||
4377 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4378 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4379 | return; |
4380 | ||
4381 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4382 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4383 | assert_dsi_pll_enabled(dev_priv); |
4384 | else | |
4385 | assert_pll_enabled(dev_priv, pipe); | |
4386 | } | |
4387 | ||
4388 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4389 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4390 | palreg = LGC_PALETTE(pipe); |
4391 | ||
4392 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4393 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4394 | */ | |
6e3c9717 | 4395 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4396 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4397 | GAMMA_MODE_MODE_SPLIT)) { | |
4398 | hsw_disable_ips(intel_crtc); | |
4399 | reenable_ips = true; | |
4400 | } | |
4401 | ||
4402 | for (i = 0; i < 256; i++) { | |
4403 | I915_WRITE(palreg + 4 * i, | |
4404 | (intel_crtc->lut_r[i] << 16) | | |
4405 | (intel_crtc->lut_g[i] << 8) | | |
4406 | intel_crtc->lut_b[i]); | |
4407 | } | |
4408 | ||
4409 | if (reenable_ips) | |
4410 | hsw_enable_ips(intel_crtc); | |
4411 | } | |
4412 | ||
d3eedb1a VS |
4413 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4414 | { | |
4415 | if (!enable && intel_crtc->overlay) { | |
4416 | struct drm_device *dev = intel_crtc->base.dev; | |
4417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4418 | ||
4419 | mutex_lock(&dev->struct_mutex); | |
4420 | dev_priv->mm.interruptible = false; | |
4421 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4422 | dev_priv->mm.interruptible = true; | |
4423 | mutex_unlock(&dev->struct_mutex); | |
4424 | } | |
4425 | ||
4426 | /* Let userspace switch the overlay on again. In most cases userspace | |
4427 | * has to recompute where to put it anyway. | |
4428 | */ | |
4429 | } | |
4430 | ||
d3eedb1a | 4431 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4432 | { |
4433 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4435 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4436 | |
fdd508a6 | 4437 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4a3b8769 | 4438 | intel_enable_sprite_planes(crtc); |
a5c4d7bc | 4439 | intel_crtc_update_cursor(crtc, true); |
d3eedb1a | 4440 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4441 | |
4442 | hsw_enable_ips(intel_crtc); | |
4443 | ||
4444 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4445 | intel_fbc_update(dev); |
a5c4d7bc | 4446 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4447 | |
4448 | /* | |
4449 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4450 | * to compute the mask of flip planes precisely. For the time being | |
4451 | * consider this a flip from a NULL plane. | |
4452 | */ | |
4453 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4454 | } |
4455 | ||
d3eedb1a | 4456 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4457 | { |
4458 | struct drm_device *dev = crtc->dev; | |
4459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4461 | int pipe = intel_crtc->pipe; | |
a5c4d7bc VS |
4462 | |
4463 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc | 4464 | |
e35fef21 | 4465 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4466 | intel_fbc_disable(dev); |
a5c4d7bc VS |
4467 | |
4468 | hsw_disable_ips(intel_crtc); | |
4469 | ||
d3eedb1a | 4470 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc | 4471 | intel_crtc_update_cursor(crtc, false); |
4a3b8769 | 4472 | intel_disable_sprite_planes(crtc); |
fdd508a6 | 4473 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4474 | |
f99d7069 DV |
4475 | /* |
4476 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4477 | * to compute the mask of flip planes precisely. For the time being | |
4478 | * consider this a flip to a NULL plane. | |
4479 | */ | |
4480 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4481 | } |
4482 | ||
f67a559d JB |
4483 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4484 | { | |
4485 | struct drm_device *dev = crtc->dev; | |
4486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4488 | struct intel_encoder *encoder; |
f67a559d | 4489 | int pipe = intel_crtc->pipe; |
f67a559d | 4490 | |
83d65738 | 4491 | WARN_ON(!crtc->state->enable); |
08a48469 | 4492 | |
f67a559d JB |
4493 | if (intel_crtc->active) |
4494 | return; | |
4495 | ||
6e3c9717 | 4496 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4497 | intel_prepare_shared_dpll(intel_crtc); |
4498 | ||
6e3c9717 | 4499 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4500 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4501 | |
4502 | intel_set_pipe_timings(intel_crtc); | |
4503 | ||
6e3c9717 | 4504 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4505 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4506 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4507 | } |
4508 | ||
4509 | ironlake_set_pipeconf(crtc); | |
4510 | ||
f67a559d | 4511 | intel_crtc->active = true; |
8664281b | 4512 | |
a72e4c9f DV |
4513 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4514 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4515 | |
f6736a1a | 4516 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4517 | if (encoder->pre_enable) |
4518 | encoder->pre_enable(encoder); | |
f67a559d | 4519 | |
6e3c9717 | 4520 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4521 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4522 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4523 | * enabling. */ | |
88cefb6c | 4524 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4525 | } else { |
4526 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4527 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4528 | } | |
f67a559d | 4529 | |
b074cec8 | 4530 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4531 | |
9c54c0dd JB |
4532 | /* |
4533 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4534 | * clocks enabled | |
4535 | */ | |
4536 | intel_crtc_load_lut(crtc); | |
4537 | ||
f37fcc2a | 4538 | intel_update_watermarks(crtc); |
e1fdc473 | 4539 | intel_enable_pipe(intel_crtc); |
f67a559d | 4540 | |
6e3c9717 | 4541 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4542 | ironlake_pch_enable(crtc); |
c98e9dcf | 4543 | |
f9b61ff6 DV |
4544 | assert_vblank_disabled(crtc); |
4545 | drm_crtc_vblank_on(crtc); | |
4546 | ||
fa5c73b1 DV |
4547 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4548 | encoder->enable(encoder); | |
61b77ddd DV |
4549 | |
4550 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4551 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4552 | |
d3eedb1a | 4553 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4554 | } |
4555 | ||
42db64ef PZ |
4556 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4557 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4558 | { | |
f5adf94e | 4559 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4560 | } |
4561 | ||
e4916946 PZ |
4562 | /* |
4563 | * This implements the workaround described in the "notes" section of the mode | |
4564 | * set sequence documentation. When going from no pipes or single pipe to | |
4565 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4566 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4567 | */ | |
4568 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4569 | { | |
4570 | struct drm_device *dev = crtc->base.dev; | |
4571 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4572 | ||
4573 | /* We want to get the other_active_crtc only if there's only 1 other | |
4574 | * active crtc. */ | |
d3fcc808 | 4575 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4576 | if (!crtc_it->active || crtc_it == crtc) |
4577 | continue; | |
4578 | ||
4579 | if (other_active_crtc) | |
4580 | return; | |
4581 | ||
4582 | other_active_crtc = crtc_it; | |
4583 | } | |
4584 | if (!other_active_crtc) | |
4585 | return; | |
4586 | ||
4587 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4588 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4589 | } | |
4590 | ||
4f771f10 PZ |
4591 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4592 | { | |
4593 | struct drm_device *dev = crtc->dev; | |
4594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4596 | struct intel_encoder *encoder; | |
4597 | int pipe = intel_crtc->pipe; | |
4f771f10 | 4598 | |
83d65738 | 4599 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
4600 | |
4601 | if (intel_crtc->active) | |
4602 | return; | |
4603 | ||
df8ad70c DV |
4604 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4605 | intel_enable_shared_dpll(intel_crtc); | |
4606 | ||
6e3c9717 | 4607 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4608 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4609 | |
4610 | intel_set_pipe_timings(intel_crtc); | |
4611 | ||
6e3c9717 ACO |
4612 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4613 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4614 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4615 | } |
4616 | ||
6e3c9717 | 4617 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4618 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4619 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4620 | } |
4621 | ||
4622 | haswell_set_pipeconf(crtc); | |
4623 | ||
4624 | intel_set_pipe_csc(crtc); | |
4625 | ||
4f771f10 | 4626 | intel_crtc->active = true; |
8664281b | 4627 | |
a72e4c9f | 4628 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4629 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4630 | if (encoder->pre_enable) | |
4631 | encoder->pre_enable(encoder); | |
4632 | ||
6e3c9717 | 4633 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
4634 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4635 | true); | |
4fe9467d ID |
4636 | dev_priv->display.fdi_link_train(crtc); |
4637 | } | |
4638 | ||
1f544388 | 4639 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4640 | |
bd2e244f JB |
4641 | if (IS_SKYLAKE(dev)) |
4642 | skylake_pfit_enable(intel_crtc); | |
4643 | else | |
4644 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4645 | |
4646 | /* | |
4647 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4648 | * clocks enabled | |
4649 | */ | |
4650 | intel_crtc_load_lut(crtc); | |
4651 | ||
1f544388 | 4652 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4653 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4654 | |
f37fcc2a | 4655 | intel_update_watermarks(crtc); |
e1fdc473 | 4656 | intel_enable_pipe(intel_crtc); |
42db64ef | 4657 | |
6e3c9717 | 4658 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4659 | lpt_pch_enable(crtc); |
4f771f10 | 4660 | |
6e3c9717 | 4661 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4662 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4663 | ||
f9b61ff6 DV |
4664 | assert_vblank_disabled(crtc); |
4665 | drm_crtc_vblank_on(crtc); | |
4666 | ||
8807e55b | 4667 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4668 | encoder->enable(encoder); |
8807e55b JN |
4669 | intel_opregion_notify_encoder(encoder, true); |
4670 | } | |
4f771f10 | 4671 | |
e4916946 PZ |
4672 | /* If we change the relative order between pipe/planes enabling, we need |
4673 | * to change the workaround. */ | |
4674 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4675 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4676 | } |
4677 | ||
bd2e244f JB |
4678 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4679 | { | |
4680 | struct drm_device *dev = crtc->base.dev; | |
4681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4682 | int pipe = crtc->pipe; | |
4683 | ||
4684 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4685 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4686 | if (crtc->config->pch_pfit.enabled) { |
bd2e244f JB |
4687 | I915_WRITE(PS_CTL(pipe), 0); |
4688 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4689 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4690 | } | |
4691 | } | |
4692 | ||
3f8dce3a DV |
4693 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4694 | { | |
4695 | struct drm_device *dev = crtc->base.dev; | |
4696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4697 | int pipe = crtc->pipe; | |
4698 | ||
4699 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4700 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 4701 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4702 | I915_WRITE(PF_CTL(pipe), 0); |
4703 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4704 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4705 | } | |
4706 | } | |
4707 | ||
6be4a607 JB |
4708 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4709 | { | |
4710 | struct drm_device *dev = crtc->dev; | |
4711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4713 | struct intel_encoder *encoder; |
6be4a607 | 4714 | int pipe = intel_crtc->pipe; |
5eddb70b | 4715 | u32 reg, temp; |
b52eb4dc | 4716 | |
f7abfe8b CW |
4717 | if (!intel_crtc->active) |
4718 | return; | |
4719 | ||
d3eedb1a | 4720 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4721 | |
ea9d758d DV |
4722 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4723 | encoder->disable(encoder); | |
4724 | ||
f9b61ff6 DV |
4725 | drm_crtc_vblank_off(crtc); |
4726 | assert_vblank_disabled(crtc); | |
4727 | ||
6e3c9717 | 4728 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 4729 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4730 | |
575f7ab7 | 4731 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4732 | |
3f8dce3a | 4733 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4734 | |
bf49ec8c DV |
4735 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4736 | if (encoder->post_disable) | |
4737 | encoder->post_disable(encoder); | |
2c07245f | 4738 | |
6e3c9717 | 4739 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4740 | ironlake_fdi_disable(crtc); |
913d8d11 | 4741 | |
d925c59a | 4742 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4743 | |
d925c59a DV |
4744 | if (HAS_PCH_CPT(dev)) { |
4745 | /* disable TRANS_DP_CTL */ | |
4746 | reg = TRANS_DP_CTL(pipe); | |
4747 | temp = I915_READ(reg); | |
4748 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4749 | TRANS_DP_PORT_SEL_MASK); | |
4750 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4751 | I915_WRITE(reg, temp); | |
4752 | ||
4753 | /* disable DPLL_SEL */ | |
4754 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4755 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4756 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4757 | } |
e3421a18 | 4758 | |
d925c59a | 4759 | /* disable PCH DPLL */ |
e72f9fbf | 4760 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4761 | |
d925c59a DV |
4762 | ironlake_fdi_pll_disable(intel_crtc); |
4763 | } | |
6b383a7f | 4764 | |
f7abfe8b | 4765 | intel_crtc->active = false; |
46ba614c | 4766 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4767 | |
4768 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4769 | intel_fbc_update(dev); |
d1ebd816 | 4770 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4771 | } |
1b3c7a47 | 4772 | |
4f771f10 | 4773 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4774 | { |
4f771f10 PZ |
4775 | struct drm_device *dev = crtc->dev; |
4776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4778 | struct intel_encoder *encoder; |
6e3c9717 | 4779 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 4780 | |
4f771f10 PZ |
4781 | if (!intel_crtc->active) |
4782 | return; | |
4783 | ||
d3eedb1a | 4784 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4785 | |
8807e55b JN |
4786 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4787 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4788 | encoder->disable(encoder); |
8807e55b | 4789 | } |
4f771f10 | 4790 | |
f9b61ff6 DV |
4791 | drm_crtc_vblank_off(crtc); |
4792 | assert_vblank_disabled(crtc); | |
4793 | ||
6e3c9717 | 4794 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
4795 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4796 | false); | |
575f7ab7 | 4797 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4798 | |
6e3c9717 | 4799 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
4800 | intel_ddi_set_vc_payload_alloc(crtc, false); |
4801 | ||
ad80a810 | 4802 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4803 | |
bd2e244f JB |
4804 | if (IS_SKYLAKE(dev)) |
4805 | skylake_pfit_disable(intel_crtc); | |
4806 | else | |
4807 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4808 | |
1f544388 | 4809 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4810 | |
6e3c9717 | 4811 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 4812 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 4813 | intel_ddi_fdi_disable(crtc); |
83616634 | 4814 | } |
4f771f10 | 4815 | |
97b040aa ID |
4816 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4817 | if (encoder->post_disable) | |
4818 | encoder->post_disable(encoder); | |
4819 | ||
4f771f10 | 4820 | intel_crtc->active = false; |
46ba614c | 4821 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4822 | |
4823 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4824 | intel_fbc_update(dev); |
4f771f10 | 4825 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
4826 | |
4827 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4828 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4829 | } |
4830 | ||
ee7b9f93 JB |
4831 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4832 | { | |
4833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4834 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4835 | } |
4836 | ||
6441ab5f | 4837 | |
2dd24552 JB |
4838 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4839 | { | |
4840 | struct drm_device *dev = crtc->base.dev; | |
4841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4842 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 4843 | |
681a8504 | 4844 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
4845 | return; |
4846 | ||
2dd24552 | 4847 | /* |
c0b03411 DV |
4848 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4849 | * according to register description and PRM. | |
2dd24552 | 4850 | */ |
c0b03411 DV |
4851 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4852 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4853 | |
b074cec8 JB |
4854 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4855 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4856 | |
4857 | /* Border color in case we don't scale up to the full screen. Black by | |
4858 | * default, change to something else for debugging. */ | |
4859 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4860 | } |
4861 | ||
d05410f9 DA |
4862 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4863 | { | |
4864 | switch (port) { | |
4865 | case PORT_A: | |
4866 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4867 | case PORT_B: | |
4868 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4869 | case PORT_C: | |
4870 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4871 | case PORT_D: | |
4872 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4873 | default: | |
4874 | WARN_ON_ONCE(1); | |
4875 | return POWER_DOMAIN_PORT_OTHER; | |
4876 | } | |
4877 | } | |
4878 | ||
77d22dca ID |
4879 | #define for_each_power_domain(domain, mask) \ |
4880 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4881 | if ((1 << (domain)) & (mask)) | |
4882 | ||
319be8ae ID |
4883 | enum intel_display_power_domain |
4884 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4885 | { | |
4886 | struct drm_device *dev = intel_encoder->base.dev; | |
4887 | struct intel_digital_port *intel_dig_port; | |
4888 | ||
4889 | switch (intel_encoder->type) { | |
4890 | case INTEL_OUTPUT_UNKNOWN: | |
4891 | /* Only DDI platforms should ever use this output type */ | |
4892 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4893 | case INTEL_OUTPUT_DISPLAYPORT: | |
4894 | case INTEL_OUTPUT_HDMI: | |
4895 | case INTEL_OUTPUT_EDP: | |
4896 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4897 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4898 | case INTEL_OUTPUT_DP_MST: |
4899 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4900 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4901 | case INTEL_OUTPUT_ANALOG: |
4902 | return POWER_DOMAIN_PORT_CRT; | |
4903 | case INTEL_OUTPUT_DSI: | |
4904 | return POWER_DOMAIN_PORT_DSI; | |
4905 | default: | |
4906 | return POWER_DOMAIN_PORT_OTHER; | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4911 | { |
319be8ae ID |
4912 | struct drm_device *dev = crtc->dev; |
4913 | struct intel_encoder *intel_encoder; | |
4914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4915 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4916 | unsigned long mask; |
4917 | enum transcoder transcoder; | |
4918 | ||
4919 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4920 | ||
4921 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4922 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
4923 | if (intel_crtc->config->pch_pfit.enabled || |
4924 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
4925 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4926 | ||
319be8ae ID |
4927 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4928 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4929 | ||
77d22dca ID |
4930 | return mask; |
4931 | } | |
4932 | ||
679dacd4 | 4933 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 4934 | { |
679dacd4 | 4935 | struct drm_device *dev = state->dev; |
77d22dca ID |
4936 | struct drm_i915_private *dev_priv = dev->dev_private; |
4937 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4938 | struct intel_crtc *crtc; | |
4939 | ||
4940 | /* | |
4941 | * First get all needed power domains, then put all unneeded, to avoid | |
4942 | * any unnecessary toggling of the power wells. | |
4943 | */ | |
d3fcc808 | 4944 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4945 | enum intel_display_power_domain domain; |
4946 | ||
83d65738 | 4947 | if (!crtc->base.state->enable) |
77d22dca ID |
4948 | continue; |
4949 | ||
319be8ae | 4950 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4951 | |
4952 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4953 | intel_display_power_get(dev_priv, domain); | |
4954 | } | |
4955 | ||
50f6e502 | 4956 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 4957 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 4958 | |
d3fcc808 | 4959 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4960 | enum intel_display_power_domain domain; |
4961 | ||
4962 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4963 | intel_display_power_put(dev_priv, domain); | |
4964 | ||
4965 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4966 | } | |
4967 | ||
4968 | intel_display_set_init_power(dev_priv, false); | |
4969 | } | |
4970 | ||
dfcab17e | 4971 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4972 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4973 | { |
586f49dc | 4974 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4975 | |
586f49dc JB |
4976 | /* Obtain SKU information */ |
4977 | mutex_lock(&dev_priv->dpio_lock); | |
4978 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4979 | CCK_FUSE_HPLL_FREQ_MASK; | |
4980 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4981 | |
dfcab17e | 4982 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4983 | } |
4984 | ||
f8bf63fd VS |
4985 | static void vlv_update_cdclk(struct drm_device *dev) |
4986 | { | |
4987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4988 | ||
4989 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4990 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4991 | dev_priv->vlv_cdclk_freq); |
4992 | ||
4993 | /* | |
4994 | * Program the gmbus_freq based on the cdclk frequency. | |
4995 | * BSpec erroneously claims we should aim for 4MHz, but | |
4996 | * in fact 1MHz is the correct frequency. | |
4997 | */ | |
6be1e3d3 | 4998 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4999 | } |
5000 | ||
30a970c6 JB |
5001 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5002 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5003 | { | |
5004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5005 | u32 val, cmd; | |
5006 | ||
d197b7d3 | 5007 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 5008 | |
dfcab17e | 5009 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5010 | cmd = 2; |
dfcab17e | 5011 | else if (cdclk == 266667) |
30a970c6 JB |
5012 | cmd = 1; |
5013 | else | |
5014 | cmd = 0; | |
5015 | ||
5016 | mutex_lock(&dev_priv->rps.hw_lock); | |
5017 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5018 | val &= ~DSPFREQGUAR_MASK; | |
5019 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5020 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5021 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5022 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5023 | 50)) { | |
5024 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5025 | } | |
5026 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5027 | ||
dfcab17e | 5028 | if (cdclk == 400000) { |
6bcda4f0 | 5029 | u32 divider; |
30a970c6 | 5030 | |
6bcda4f0 | 5031 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5032 | |
5033 | mutex_lock(&dev_priv->dpio_lock); | |
5034 | /* adjust cdclk divider */ | |
5035 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5036 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5037 | val |= divider; |
5038 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5039 | |
5040 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5041 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5042 | 50)) | |
5043 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5044 | mutex_unlock(&dev_priv->dpio_lock); |
5045 | } | |
5046 | ||
5047 | mutex_lock(&dev_priv->dpio_lock); | |
5048 | /* adjust self-refresh exit latency value */ | |
5049 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5050 | val &= ~0x7f; | |
5051 | ||
5052 | /* | |
5053 | * For high bandwidth configs, we set a higher latency in the bunit | |
5054 | * so that the core display fetch happens in time to avoid underruns. | |
5055 | */ | |
dfcab17e | 5056 | if (cdclk == 400000) |
30a970c6 JB |
5057 | val |= 4500 / 250; /* 4.5 usec */ |
5058 | else | |
5059 | val |= 3000 / 250; /* 3.0 usec */ | |
5060 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5061 | mutex_unlock(&dev_priv->dpio_lock); | |
5062 | ||
f8bf63fd | 5063 | vlv_update_cdclk(dev); |
30a970c6 JB |
5064 | } |
5065 | ||
383c5a6a VS |
5066 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5067 | { | |
5068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5069 | u32 val, cmd; | |
5070 | ||
5071 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
5072 | ||
5073 | switch (cdclk) { | |
383c5a6a VS |
5074 | case 333333: |
5075 | case 320000: | |
383c5a6a | 5076 | case 266667: |
383c5a6a | 5077 | case 200000: |
383c5a6a VS |
5078 | break; |
5079 | default: | |
5f77eeb0 | 5080 | MISSING_CASE(cdclk); |
383c5a6a VS |
5081 | return; |
5082 | } | |
5083 | ||
9d0d3fda VS |
5084 | /* |
5085 | * Specs are full of misinformation, but testing on actual | |
5086 | * hardware has shown that we just need to write the desired | |
5087 | * CCK divider into the Punit register. | |
5088 | */ | |
5089 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5090 | ||
383c5a6a VS |
5091 | mutex_lock(&dev_priv->rps.hw_lock); |
5092 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5093 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5094 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5095 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5096 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5097 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5098 | 50)) { | |
5099 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5100 | } | |
5101 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5102 | ||
5103 | vlv_update_cdclk(dev); | |
5104 | } | |
5105 | ||
30a970c6 JB |
5106 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5107 | int max_pixclk) | |
5108 | { | |
6bcda4f0 | 5109 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5110 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5111 | |
30a970c6 JB |
5112 | /* |
5113 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5114 | * 200MHz | |
5115 | * 267MHz | |
29dc7ef3 | 5116 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5117 | * 400MHz (VLV only) |
5118 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5119 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5120 | * |
5121 | * We seem to get an unstable or solid color picture at 200MHz. | |
5122 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5123 | * are off. | |
30a970c6 | 5124 | */ |
6cca3195 VS |
5125 | if (!IS_CHERRYVIEW(dev_priv) && |
5126 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5127 | return 400000; |
6cca3195 | 5128 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5129 | return freq_320; |
e37c67a1 | 5130 | else if (max_pixclk > 0) |
dfcab17e | 5131 | return 266667; |
e37c67a1 VS |
5132 | else |
5133 | return 200000; | |
30a970c6 JB |
5134 | } |
5135 | ||
2f2d7aa1 VS |
5136 | /* compute the max pixel clock for new configuration */ |
5137 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
5138 | { |
5139 | struct drm_device *dev = dev_priv->dev; | |
5140 | struct intel_crtc *intel_crtc; | |
5141 | int max_pixclk = 0; | |
5142 | ||
d3fcc808 | 5143 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 5144 | if (intel_crtc->new_enabled) |
30a970c6 | 5145 | max_pixclk = max(max_pixclk, |
2d112de7 | 5146 | intel_crtc->new_config->base.adjusted_mode.crtc_clock); |
30a970c6 JB |
5147 | } |
5148 | ||
5149 | return max_pixclk; | |
5150 | } | |
5151 | ||
5152 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 5153 | unsigned *prepare_pipes) |
30a970c6 JB |
5154 | { |
5155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5156 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 5157 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 5158 | |
d60c4473 ID |
5159 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
5160 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
5161 | return; |
5162 | ||
2f2d7aa1 | 5163 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 5164 | for_each_intel_crtc(dev, intel_crtc) |
83d65738 | 5165 | if (intel_crtc->base.state->enable) |
30a970c6 JB |
5166 | *prepare_pipes |= (1 << intel_crtc->pipe); |
5167 | } | |
5168 | ||
1e69cd74 VS |
5169 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5170 | { | |
5171 | unsigned int credits, default_credits; | |
5172 | ||
5173 | if (IS_CHERRYVIEW(dev_priv)) | |
5174 | default_credits = PFI_CREDIT(12); | |
5175 | else | |
5176 | default_credits = PFI_CREDIT(8); | |
5177 | ||
5178 | if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { | |
5179 | /* CHV suggested value is 31 or 63 */ | |
5180 | if (IS_CHERRYVIEW(dev_priv)) | |
5181 | credits = PFI_CREDIT_31; | |
5182 | else | |
5183 | credits = PFI_CREDIT(15); | |
5184 | } else { | |
5185 | credits = default_credits; | |
5186 | } | |
5187 | ||
5188 | /* | |
5189 | * WA - write default credits before re-programming | |
5190 | * FIXME: should we also set the resend bit here? | |
5191 | */ | |
5192 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5193 | default_credits); | |
5194 | ||
5195 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5196 | credits | PFI_CREDIT_RESEND); | |
5197 | ||
5198 | /* | |
5199 | * FIXME is this guaranteed to clear | |
5200 | * immediately or should we poll for it? | |
5201 | */ | |
5202 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5203 | } | |
5204 | ||
679dacd4 | 5205 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5206 | { |
679dacd4 | 5207 | struct drm_device *dev = state->dev; |
30a970c6 | 5208 | struct drm_i915_private *dev_priv = dev->dev_private; |
2f2d7aa1 | 5209 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
5210 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
5211 | ||
383c5a6a | 5212 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
5213 | /* |
5214 | * FIXME: We can end up here with all power domains off, yet | |
5215 | * with a CDCLK frequency other than the minimum. To account | |
5216 | * for this take the PIPE-A power domain, which covers the HW | |
5217 | * blocks needed for the following programming. This can be | |
5218 | * removed once it's guaranteed that we get here either with | |
5219 | * the minimum CDCLK set, or the required power domains | |
5220 | * enabled. | |
5221 | */ | |
5222 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5223 | ||
383c5a6a VS |
5224 | if (IS_CHERRYVIEW(dev)) |
5225 | cherryview_set_cdclk(dev, req_cdclk); | |
5226 | else | |
5227 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5228 | |
1e69cd74 VS |
5229 | vlv_program_pfi_credits(dev_priv); |
5230 | ||
738c05c0 | 5231 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5232 | } |
30a970c6 JB |
5233 | } |
5234 | ||
89b667f8 JB |
5235 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5236 | { | |
5237 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5238 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5240 | struct intel_encoder *encoder; | |
5241 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5242 | bool is_dsi; |
89b667f8 | 5243 | |
83d65738 | 5244 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5245 | |
5246 | if (intel_crtc->active) | |
5247 | return; | |
5248 | ||
409ee761 | 5249 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5250 | |
1ae0d137 VS |
5251 | if (!is_dsi) { |
5252 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5253 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5254 | else |
6e3c9717 | 5255 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5256 | } |
5b18e57c | 5257 | |
6e3c9717 | 5258 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5259 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5260 | |
5261 | intel_set_pipe_timings(intel_crtc); | |
5262 | ||
c14b0485 VS |
5263 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5265 | ||
5266 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5267 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5268 | } | |
5269 | ||
5b18e57c DV |
5270 | i9xx_set_pipeconf(intel_crtc); |
5271 | ||
89b667f8 | 5272 | intel_crtc->active = true; |
89b667f8 | 5273 | |
a72e4c9f | 5274 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5275 | |
89b667f8 JB |
5276 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5277 | if (encoder->pre_pll_enable) | |
5278 | encoder->pre_pll_enable(encoder); | |
5279 | ||
9d556c99 CML |
5280 | if (!is_dsi) { |
5281 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5282 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5283 | else |
6e3c9717 | 5284 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5285 | } |
89b667f8 JB |
5286 | |
5287 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5288 | if (encoder->pre_enable) | |
5289 | encoder->pre_enable(encoder); | |
5290 | ||
2dd24552 JB |
5291 | i9xx_pfit_enable(intel_crtc); |
5292 | ||
63cbb074 VS |
5293 | intel_crtc_load_lut(crtc); |
5294 | ||
f37fcc2a | 5295 | intel_update_watermarks(crtc); |
e1fdc473 | 5296 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5297 | |
4b3a9526 VS |
5298 | assert_vblank_disabled(crtc); |
5299 | drm_crtc_vblank_on(crtc); | |
5300 | ||
f9b61ff6 DV |
5301 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5302 | encoder->enable(encoder); | |
5303 | ||
9ab0460b | 5304 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5305 | |
56b80e1f | 5306 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5307 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5308 | } |
5309 | ||
f13c2ef3 DV |
5310 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5311 | { | |
5312 | struct drm_device *dev = crtc->base.dev; | |
5313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5314 | ||
6e3c9717 ACO |
5315 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5316 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5317 | } |
5318 | ||
0b8765c6 | 5319 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5320 | { |
5321 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5322 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5324 | struct intel_encoder *encoder; |
79e53945 | 5325 | int pipe = intel_crtc->pipe; |
79e53945 | 5326 | |
83d65738 | 5327 | WARN_ON(!crtc->state->enable); |
08a48469 | 5328 | |
f7abfe8b CW |
5329 | if (intel_crtc->active) |
5330 | return; | |
5331 | ||
f13c2ef3 DV |
5332 | i9xx_set_pll_dividers(intel_crtc); |
5333 | ||
6e3c9717 | 5334 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5335 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5336 | |
5337 | intel_set_pipe_timings(intel_crtc); | |
5338 | ||
5b18e57c DV |
5339 | i9xx_set_pipeconf(intel_crtc); |
5340 | ||
f7abfe8b | 5341 | intel_crtc->active = true; |
6b383a7f | 5342 | |
4a3436e8 | 5343 | if (!IS_GEN2(dev)) |
a72e4c9f | 5344 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5345 | |
9d6d9f19 MK |
5346 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5347 | if (encoder->pre_enable) | |
5348 | encoder->pre_enable(encoder); | |
5349 | ||
f6736a1a DV |
5350 | i9xx_enable_pll(intel_crtc); |
5351 | ||
2dd24552 JB |
5352 | i9xx_pfit_enable(intel_crtc); |
5353 | ||
63cbb074 VS |
5354 | intel_crtc_load_lut(crtc); |
5355 | ||
f37fcc2a | 5356 | intel_update_watermarks(crtc); |
e1fdc473 | 5357 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5358 | |
4b3a9526 VS |
5359 | assert_vblank_disabled(crtc); |
5360 | drm_crtc_vblank_on(crtc); | |
5361 | ||
f9b61ff6 DV |
5362 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5363 | encoder->enable(encoder); | |
5364 | ||
9ab0460b | 5365 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5366 | |
4a3436e8 VS |
5367 | /* |
5368 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5369 | * So don't enable underrun reporting before at least some planes | |
5370 | * are enabled. | |
5371 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5372 | * but leave the pipe running. | |
5373 | */ | |
5374 | if (IS_GEN2(dev)) | |
a72e4c9f | 5375 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5376 | |
56b80e1f | 5377 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5378 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5379 | } |
79e53945 | 5380 | |
87476d63 DV |
5381 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5382 | { | |
5383 | struct drm_device *dev = crtc->base.dev; | |
5384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5385 | |
6e3c9717 | 5386 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5387 | return; |
87476d63 | 5388 | |
328d8e82 | 5389 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5390 | |
328d8e82 DV |
5391 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5392 | I915_READ(PFIT_CONTROL)); | |
5393 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5394 | } |
5395 | ||
0b8765c6 JB |
5396 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5397 | { | |
5398 | struct drm_device *dev = crtc->dev; | |
5399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5401 | struct intel_encoder *encoder; |
0b8765c6 | 5402 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5403 | |
f7abfe8b CW |
5404 | if (!intel_crtc->active) |
5405 | return; | |
5406 | ||
4a3436e8 VS |
5407 | /* |
5408 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5409 | * So diasble underrun reporting before all the planes get disabled. | |
5410 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5411 | * but leave the pipe running. | |
5412 | */ | |
5413 | if (IS_GEN2(dev)) | |
a72e4c9f | 5414 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5415 | |
564ed191 ID |
5416 | /* |
5417 | * Vblank time updates from the shadow to live plane control register | |
5418 | * are blocked if the memory self-refresh mode is active at that | |
5419 | * moment. So to make sure the plane gets truly disabled, disable | |
5420 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5421 | * will be checked/applied by the HW only at the next frame start | |
5422 | * event which is after the vblank start event, so we need to have a | |
5423 | * wait-for-vblank between disabling the plane and the pipe. | |
5424 | */ | |
5425 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5426 | intel_crtc_disable_planes(crtc); |
5427 | ||
6304cd91 VS |
5428 | /* |
5429 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5430 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5431 | * We also need to wait on all gmch platforms because of the |
5432 | * self-refresh mode constraint explained above. | |
6304cd91 | 5433 | */ |
564ed191 | 5434 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5435 | |
4b3a9526 VS |
5436 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5437 | encoder->disable(encoder); | |
5438 | ||
f9b61ff6 DV |
5439 | drm_crtc_vblank_off(crtc); |
5440 | assert_vblank_disabled(crtc); | |
5441 | ||
575f7ab7 | 5442 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5443 | |
87476d63 | 5444 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5445 | |
89b667f8 JB |
5446 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5447 | if (encoder->post_disable) | |
5448 | encoder->post_disable(encoder); | |
5449 | ||
409ee761 | 5450 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5451 | if (IS_CHERRYVIEW(dev)) |
5452 | chv_disable_pll(dev_priv, pipe); | |
5453 | else if (IS_VALLEYVIEW(dev)) | |
5454 | vlv_disable_pll(dev_priv, pipe); | |
5455 | else | |
1c4e0274 | 5456 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5457 | } |
0b8765c6 | 5458 | |
4a3436e8 | 5459 | if (!IS_GEN2(dev)) |
a72e4c9f | 5460 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5461 | |
f7abfe8b | 5462 | intel_crtc->active = false; |
46ba614c | 5463 | intel_update_watermarks(crtc); |
f37fcc2a | 5464 | |
efa9624e | 5465 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 5466 | intel_fbc_update(dev); |
efa9624e | 5467 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5468 | } |
5469 | ||
ee7b9f93 JB |
5470 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5471 | { | |
5472 | } | |
5473 | ||
b04c5bd6 BF |
5474 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5475 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5476 | { |
5477 | struct drm_device *dev = crtc->dev; | |
5478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5480 | enum intel_display_power_domain domain; |
5481 | unsigned long domains; | |
976f8a20 | 5482 | |
0e572fe7 DV |
5483 | if (enable) { |
5484 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5485 | domains = get_crtc_power_domains(crtc); |
5486 | for_each_power_domain(domain, domains) | |
5487 | intel_display_power_get(dev_priv, domain); | |
5488 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5489 | |
5490 | dev_priv->display.crtc_enable(crtc); | |
5491 | } | |
5492 | } else { | |
5493 | if (intel_crtc->active) { | |
5494 | dev_priv->display.crtc_disable(crtc); | |
5495 | ||
e1e9fb84 DV |
5496 | domains = intel_crtc->enabled_power_domains; |
5497 | for_each_power_domain(domain, domains) | |
5498 | intel_display_power_put(dev_priv, domain); | |
5499 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5500 | } |
5501 | } | |
b04c5bd6 BF |
5502 | } |
5503 | ||
5504 | /** | |
5505 | * Sets the power management mode of the pipe and plane. | |
5506 | */ | |
5507 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5508 | { | |
5509 | struct drm_device *dev = crtc->dev; | |
5510 | struct intel_encoder *intel_encoder; | |
5511 | bool enable = false; | |
5512 | ||
5513 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5514 | enable |= intel_encoder->connectors_active; | |
5515 | ||
5516 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5517 | } |
5518 | ||
cdd59983 CW |
5519 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5520 | { | |
cdd59983 | 5521 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5522 | struct drm_connector *connector; |
ee7b9f93 | 5523 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5524 | |
976f8a20 | 5525 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 5526 | WARN_ON(!crtc->state->enable); |
976f8a20 DV |
5527 | |
5528 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5529 | dev_priv->display.off(crtc); |
5530 | ||
455a6808 | 5531 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5532 | |
5533 | /* Update computed state. */ | |
5534 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5535 | if (!connector->encoder || !connector->encoder->crtc) | |
5536 | continue; | |
5537 | ||
5538 | if (connector->encoder->crtc != crtc) | |
5539 | continue; | |
5540 | ||
5541 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5542 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5543 | } |
5544 | } | |
5545 | ||
ea5b213a | 5546 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5547 | { |
4ef69c7a | 5548 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5549 | |
ea5b213a CW |
5550 | drm_encoder_cleanup(encoder); |
5551 | kfree(intel_encoder); | |
7e7d76c3 JB |
5552 | } |
5553 | ||
9237329d | 5554 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5555 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5556 | * state of the entire output pipe. */ | |
9237329d | 5557 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5558 | { |
5ab432ef DV |
5559 | if (mode == DRM_MODE_DPMS_ON) { |
5560 | encoder->connectors_active = true; | |
5561 | ||
b2cabb0e | 5562 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5563 | } else { |
5564 | encoder->connectors_active = false; | |
5565 | ||
b2cabb0e | 5566 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5567 | } |
79e53945 JB |
5568 | } |
5569 | ||
0a91ca29 DV |
5570 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5571 | * internal consistency). */ | |
b980514c | 5572 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5573 | { |
0a91ca29 DV |
5574 | if (connector->get_hw_state(connector)) { |
5575 | struct intel_encoder *encoder = connector->encoder; | |
5576 | struct drm_crtc *crtc; | |
5577 | bool encoder_enabled; | |
5578 | enum pipe pipe; | |
5579 | ||
5580 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5581 | connector->base.base.id, | |
c23cc417 | 5582 | connector->base.name); |
0a91ca29 | 5583 | |
0e32b39c DA |
5584 | /* there is no real hw state for MST connectors */ |
5585 | if (connector->mst_port) | |
5586 | return; | |
5587 | ||
e2c719b7 | 5588 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 5589 | "wrong connector dpms state\n"); |
e2c719b7 | 5590 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 5591 | "active connector not linked to encoder\n"); |
0a91ca29 | 5592 | |
36cd7444 | 5593 | if (encoder) { |
e2c719b7 | 5594 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
5595 | "encoder->connectors_active not set\n"); |
5596 | ||
5597 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
5598 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
5599 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 5600 | return; |
0a91ca29 | 5601 | |
36cd7444 | 5602 | crtc = encoder->base.crtc; |
0a91ca29 | 5603 | |
83d65738 MR |
5604 | I915_STATE_WARN(!crtc->state->enable, |
5605 | "crtc not enabled\n"); | |
e2c719b7 RC |
5606 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
5607 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
5608 | "encoder active on the wrong pipe\n"); |
5609 | } | |
0a91ca29 | 5610 | } |
79e53945 JB |
5611 | } |
5612 | ||
5ab432ef DV |
5613 | /* Even simpler default implementation, if there's really no special case to |
5614 | * consider. */ | |
5615 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5616 | { |
5ab432ef DV |
5617 | /* All the simple cases only support two dpms states. */ |
5618 | if (mode != DRM_MODE_DPMS_ON) | |
5619 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5620 | |
5ab432ef DV |
5621 | if (mode == connector->dpms) |
5622 | return; | |
5623 | ||
5624 | connector->dpms = mode; | |
5625 | ||
5626 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5627 | if (connector->encoder) |
5628 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5629 | |
b980514c | 5630 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5631 | } |
5632 | ||
f0947c37 DV |
5633 | /* Simple connector->get_hw_state implementation for encoders that support only |
5634 | * one connector and no cloning and hence the encoder state determines the state | |
5635 | * of the connector. */ | |
5636 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5637 | { |
24929352 | 5638 | enum pipe pipe = 0; |
f0947c37 | 5639 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5640 | |
f0947c37 | 5641 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5642 | } |
5643 | ||
d272ddfa VS |
5644 | static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe) |
5645 | { | |
5646 | struct intel_crtc *crtc = | |
5647 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5648 | ||
5649 | if (crtc->base.state->enable && | |
5650 | crtc->config->has_pch_encoder) | |
5651 | return crtc->config->fdi_lanes; | |
5652 | ||
5653 | return 0; | |
5654 | } | |
5655 | ||
1857e1da | 5656 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5657 | struct intel_crtc_state *pipe_config) |
1857e1da | 5658 | { |
1857e1da DV |
5659 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
5660 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5661 | if (pipe_config->fdi_lanes > 4) { | |
5662 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5663 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5664 | return false; | |
5665 | } | |
5666 | ||
bafb6553 | 5667 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5668 | if (pipe_config->fdi_lanes > 2) { |
5669 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5670 | pipe_config->fdi_lanes); | |
5671 | return false; | |
5672 | } else { | |
5673 | return true; | |
5674 | } | |
5675 | } | |
5676 | ||
5677 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5678 | return true; | |
5679 | ||
5680 | /* Ivybridge 3 pipe is really complicated */ | |
5681 | switch (pipe) { | |
5682 | case PIPE_A: | |
5683 | return true; | |
5684 | case PIPE_B: | |
d272ddfa VS |
5685 | if (pipe_config->fdi_lanes > 2 && |
5686 | pipe_required_fdi_lanes(dev, PIPE_C) > 0) { | |
1857e1da DV |
5687 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
5688 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5689 | return false; | |
5690 | } | |
5691 | return true; | |
5692 | case PIPE_C: | |
251cc67c VS |
5693 | if (pipe_config->fdi_lanes > 2) { |
5694 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
5695 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5696 | return false; | |
5697 | } | |
d272ddfa | 5698 | if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) { |
1857e1da DV |
5699 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
5700 | return false; | |
5701 | } | |
5702 | return true; | |
5703 | default: | |
5704 | BUG(); | |
5705 | } | |
5706 | } | |
5707 | ||
e29c22c0 DV |
5708 | #define RETRY 1 |
5709 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 5710 | struct intel_crtc_state *pipe_config) |
877d48d5 | 5711 | { |
1857e1da | 5712 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 5713 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
ff9a6750 | 5714 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5715 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5716 | |
e29c22c0 | 5717 | retry: |
877d48d5 DV |
5718 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5719 | * each output octet as 10 bits. The actual frequency | |
5720 | * is stored as a divider into a 100MHz clock, and the | |
5721 | * mode pixel clock is stored in units of 1KHz. | |
5722 | * Hence the bw of each lane in terms of the mode signal | |
5723 | * is: | |
5724 | */ | |
5725 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5726 | ||
241bfc38 | 5727 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5728 | |
2bd89a07 | 5729 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5730 | pipe_config->pipe_bpp); |
5731 | ||
5732 | pipe_config->fdi_lanes = lane; | |
5733 | ||
2bd89a07 | 5734 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5735 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5736 | |
e29c22c0 DV |
5737 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5738 | intel_crtc->pipe, pipe_config); | |
5739 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5740 | pipe_config->pipe_bpp -= 2*3; | |
5741 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5742 | pipe_config->pipe_bpp); | |
5743 | needs_recompute = true; | |
5744 | pipe_config->bw_constrained = true; | |
5745 | ||
5746 | goto retry; | |
5747 | } | |
5748 | ||
5749 | if (needs_recompute) | |
5750 | return RETRY; | |
5751 | ||
5752 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5753 | } |
5754 | ||
42db64ef | 5755 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 5756 | struct intel_crtc_state *pipe_config) |
42db64ef | 5757 | { |
d330a953 | 5758 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5759 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5760 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5761 | } |
5762 | ||
a43f6e0f | 5763 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 5764 | struct intel_crtc_state *pipe_config) |
79e53945 | 5765 | { |
a43f6e0f | 5766 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5767 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 5768 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 5769 | |
ad3a4479 | 5770 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5771 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5772 | int clock_limit = |
5773 | dev_priv->display.get_display_clock_speed(dev); | |
5774 | ||
5775 | /* | |
5776 | * Enable pixel doubling when the dot clock | |
5777 | * is > 90% of the (display) core speed. | |
5778 | * | |
b397c96b VS |
5779 | * GDG double wide on either pipe, |
5780 | * otherwise pipe A only. | |
cf532bb2 | 5781 | */ |
b397c96b | 5782 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5783 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5784 | clock_limit *= 2; |
cf532bb2 | 5785 | pipe_config->double_wide = true; |
ad3a4479 VS |
5786 | } |
5787 | ||
241bfc38 | 5788 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5789 | return -EINVAL; |
2c07245f | 5790 | } |
89749350 | 5791 | |
1d1d0e27 VS |
5792 | /* |
5793 | * Pipe horizontal size must be even in: | |
5794 | * - DVO ganged mode | |
5795 | * - LVDS dual channel mode | |
5796 | * - Double wide pipe | |
5797 | */ | |
b4f2bf4c | 5798 | if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5799 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5800 | pipe_config->pipe_src_w &= ~1; | |
5801 | ||
8693a824 DL |
5802 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5803 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5804 | */ |
5805 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5806 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5807 | return -EINVAL; |
44f46b42 | 5808 | |
bd080ee5 | 5809 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5810 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5811 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5812 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5813 | * for lvds. */ | |
5814 | pipe_config->pipe_bpp = 8*3; | |
5815 | } | |
5816 | ||
f5adf94e | 5817 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5818 | hsw_compute_ips_config(crtc, pipe_config); |
5819 | ||
877d48d5 | 5820 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5821 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5822 | |
e29c22c0 | 5823 | return 0; |
79e53945 JB |
5824 | } |
5825 | ||
25eb05fc JB |
5826 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5827 | { | |
d197b7d3 | 5828 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5829 | u32 val; |
5830 | int divider; | |
5831 | ||
6bcda4f0 VS |
5832 | if (dev_priv->hpll_freq == 0) |
5833 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5834 | ||
d197b7d3 VS |
5835 | mutex_lock(&dev_priv->dpio_lock); |
5836 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5837 | mutex_unlock(&dev_priv->dpio_lock); | |
5838 | ||
5839 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5840 | ||
7d007f40 VS |
5841 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5842 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5843 | "cdclk change in progress\n"); | |
5844 | ||
6bcda4f0 | 5845 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5846 | } |
5847 | ||
e70236a8 JB |
5848 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5849 | { | |
5850 | return 400000; | |
5851 | } | |
79e53945 | 5852 | |
e70236a8 | 5853 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5854 | { |
e70236a8 JB |
5855 | return 333000; |
5856 | } | |
79e53945 | 5857 | |
e70236a8 JB |
5858 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5859 | { | |
5860 | return 200000; | |
5861 | } | |
79e53945 | 5862 | |
257a7ffc DV |
5863 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5864 | { | |
5865 | u16 gcfgc = 0; | |
5866 | ||
5867 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5868 | ||
5869 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5870 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5871 | return 267000; | |
5872 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5873 | return 333000; | |
5874 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5875 | return 444000; | |
5876 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5877 | return 200000; | |
5878 | default: | |
5879 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5880 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5881 | return 133000; | |
5882 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5883 | return 167000; | |
5884 | } | |
5885 | } | |
5886 | ||
e70236a8 JB |
5887 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5888 | { | |
5889 | u16 gcfgc = 0; | |
79e53945 | 5890 | |
e70236a8 JB |
5891 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5892 | ||
5893 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5894 | return 133000; | |
5895 | else { | |
5896 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5897 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5898 | return 333000; | |
5899 | default: | |
5900 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5901 | return 190000; | |
79e53945 | 5902 | } |
e70236a8 JB |
5903 | } |
5904 | } | |
5905 | ||
5906 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5907 | { | |
5908 | return 266000; | |
5909 | } | |
5910 | ||
5911 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5912 | { | |
5913 | u16 hpllcc = 0; | |
5914 | /* Assume that the hardware is in the high speed state. This | |
5915 | * should be the default. | |
5916 | */ | |
5917 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5918 | case GC_CLOCK_133_200: | |
5919 | case GC_CLOCK_100_200: | |
5920 | return 200000; | |
5921 | case GC_CLOCK_166_250: | |
5922 | return 250000; | |
5923 | case GC_CLOCK_100_133: | |
79e53945 | 5924 | return 133000; |
e70236a8 | 5925 | } |
79e53945 | 5926 | |
e70236a8 JB |
5927 | /* Shouldn't happen */ |
5928 | return 0; | |
5929 | } | |
79e53945 | 5930 | |
e70236a8 JB |
5931 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5932 | { | |
5933 | return 133000; | |
79e53945 JB |
5934 | } |
5935 | ||
2c07245f | 5936 | static void |
a65851af | 5937 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5938 | { |
a65851af VS |
5939 | while (*num > DATA_LINK_M_N_MASK || |
5940 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5941 | *num >>= 1; |
5942 | *den >>= 1; | |
5943 | } | |
5944 | } | |
5945 | ||
a65851af VS |
5946 | static void compute_m_n(unsigned int m, unsigned int n, |
5947 | uint32_t *ret_m, uint32_t *ret_n) | |
5948 | { | |
5949 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5950 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5951 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5952 | } | |
5953 | ||
e69d0bc1 DV |
5954 | void |
5955 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5956 | int pixel_clock, int link_clock, | |
5957 | struct intel_link_m_n *m_n) | |
2c07245f | 5958 | { |
e69d0bc1 | 5959 | m_n->tu = 64; |
a65851af VS |
5960 | |
5961 | compute_m_n(bits_per_pixel * pixel_clock, | |
5962 | link_clock * nlanes * 8, | |
5963 | &m_n->gmch_m, &m_n->gmch_n); | |
5964 | ||
5965 | compute_m_n(pixel_clock, link_clock, | |
5966 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5967 | } |
5968 | ||
a7615030 CW |
5969 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5970 | { | |
d330a953 JN |
5971 | if (i915.panel_use_ssc >= 0) |
5972 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5973 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5974 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5975 | } |
5976 | ||
409ee761 | 5977 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5978 | { |
409ee761 | 5979 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5980 | struct drm_i915_private *dev_priv = dev->dev_private; |
5981 | int refclk; | |
5982 | ||
a0c4da24 | 5983 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5984 | refclk = 100000; |
d0737e1d | 5985 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5986 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5987 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5988 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5989 | } else if (!IS_GEN2(dev)) { |
5990 | refclk = 96000; | |
5991 | } else { | |
5992 | refclk = 48000; | |
5993 | } | |
5994 | ||
5995 | return refclk; | |
5996 | } | |
5997 | ||
7429e9d4 | 5998 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5999 | { |
7df00d7a | 6000 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6001 | } |
f47709a9 | 6002 | |
7429e9d4 DV |
6003 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6004 | { | |
6005 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6006 | } |
6007 | ||
f47709a9 | 6008 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6009 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6010 | intel_clock_t *reduced_clock) |
6011 | { | |
f47709a9 | 6012 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6013 | u32 fp, fp2 = 0; |
6014 | ||
6015 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6016 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6017 | if (reduced_clock) |
7429e9d4 | 6018 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6019 | } else { |
190f68c5 | 6020 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6021 | if (reduced_clock) |
7429e9d4 | 6022 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6023 | } |
6024 | ||
190f68c5 | 6025 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6026 | |
f47709a9 | 6027 | crtc->lowfreq_avail = false; |
e1f234bd | 6028 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
ab585dea | 6029 | reduced_clock) { |
190f68c5 | 6030 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6031 | crtc->lowfreq_avail = true; |
a7516a05 | 6032 | } else { |
190f68c5 | 6033 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6034 | } |
6035 | } | |
6036 | ||
5e69f97f CML |
6037 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6038 | pipe) | |
89b667f8 JB |
6039 | { |
6040 | u32 reg_val; | |
6041 | ||
6042 | /* | |
6043 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6044 | * and set it to a reasonable value instead. | |
6045 | */ | |
ab3c759a | 6046 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6047 | reg_val &= 0xffffff00; |
6048 | reg_val |= 0x00000030; | |
ab3c759a | 6049 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6050 | |
ab3c759a | 6051 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6052 | reg_val &= 0x8cffffff; |
6053 | reg_val = 0x8c000000; | |
ab3c759a | 6054 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6055 | |
ab3c759a | 6056 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6057 | reg_val &= 0xffffff00; |
ab3c759a | 6058 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6059 | |
ab3c759a | 6060 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6061 | reg_val &= 0x00ffffff; |
6062 | reg_val |= 0xb0000000; | |
ab3c759a | 6063 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6064 | } |
6065 | ||
b551842d DV |
6066 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6067 | struct intel_link_m_n *m_n) | |
6068 | { | |
6069 | struct drm_device *dev = crtc->base.dev; | |
6070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6071 | int pipe = crtc->pipe; | |
6072 | ||
e3b95f1e DV |
6073 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6074 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6075 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6076 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6077 | } |
6078 | ||
6079 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6080 | struct intel_link_m_n *m_n, |
6081 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6082 | { |
6083 | struct drm_device *dev = crtc->base.dev; | |
6084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6085 | int pipe = crtc->pipe; | |
6e3c9717 | 6086 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6087 | |
6088 | if (INTEL_INFO(dev)->gen >= 5) { | |
6089 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6090 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6091 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6092 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6093 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6094 | * for gen < 8) and if DRRS is supported (to make sure the | |
6095 | * registers are not unnecessarily accessed). | |
6096 | */ | |
44395bfe | 6097 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6098 | crtc->config->has_drrs) { |
f769cd24 VK |
6099 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6100 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6101 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6102 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6103 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6104 | } | |
b551842d | 6105 | } else { |
e3b95f1e DV |
6106 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6107 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6108 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6109 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6110 | } |
6111 | } | |
6112 | ||
fe3cd48d | 6113 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6114 | { |
fe3cd48d R |
6115 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6116 | ||
6117 | if (m_n == M1_N1) { | |
6118 | dp_m_n = &crtc->config->dp_m_n; | |
6119 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6120 | } else if (m_n == M2_N2) { | |
6121 | ||
6122 | /* | |
6123 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6124 | * needs to be programmed into M1_N1. | |
6125 | */ | |
6126 | dp_m_n = &crtc->config->dp_m2_n2; | |
6127 | } else { | |
6128 | DRM_ERROR("Unsupported divider value\n"); | |
6129 | return; | |
6130 | } | |
6131 | ||
6e3c9717 ACO |
6132 | if (crtc->config->has_pch_encoder) |
6133 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6134 | else |
fe3cd48d | 6135 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6136 | } |
6137 | ||
d288f65f | 6138 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6139 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6140 | { |
6141 | u32 dpll, dpll_md; | |
6142 | ||
6143 | /* | |
6144 | * Enable DPIO clock input. We should never disable the reference | |
6145 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6146 | * on it. | |
6147 | */ | |
6148 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6149 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6150 | /* We should never disable this, set it here for state tracking */ | |
6151 | if (crtc->pipe == PIPE_B) | |
6152 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6153 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6154 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6155 | |
d288f65f | 6156 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6157 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6158 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6159 | } |
6160 | ||
d288f65f | 6161 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6162 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6163 | { |
f47709a9 | 6164 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6165 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6166 | int pipe = crtc->pipe; |
bdd4b6a6 | 6167 | u32 mdiv; |
a0c4da24 | 6168 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6169 | u32 coreclk, reg_val; |
a0c4da24 | 6170 | |
09153000 DV |
6171 | mutex_lock(&dev_priv->dpio_lock); |
6172 | ||
d288f65f VS |
6173 | bestn = pipe_config->dpll.n; |
6174 | bestm1 = pipe_config->dpll.m1; | |
6175 | bestm2 = pipe_config->dpll.m2; | |
6176 | bestp1 = pipe_config->dpll.p1; | |
6177 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6178 | |
89b667f8 JB |
6179 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6180 | ||
6181 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6182 | if (pipe == PIPE_B) |
5e69f97f | 6183 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6184 | |
6185 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6186 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6187 | |
6188 | /* Disable target IRef on PLL */ | |
ab3c759a | 6189 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6190 | reg_val &= 0x00ffffff; |
ab3c759a | 6191 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6192 | |
6193 | /* Disable fast lock */ | |
ab3c759a | 6194 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6195 | |
6196 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6197 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6198 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6199 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6200 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6201 | |
6202 | /* | |
6203 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6204 | * but we don't support that). | |
6205 | * Note: don't use the DAC post divider as it seems unstable. | |
6206 | */ | |
6207 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6208 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6209 | |
a0c4da24 | 6210 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6211 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6212 | |
89b667f8 | 6213 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6214 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6215 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6216 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6217 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6218 | 0x009f0003); |
89b667f8 | 6219 | else |
ab3c759a | 6220 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6221 | 0x00d0000f); |
6222 | ||
681a8504 | 6223 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6224 | /* Use SSC source */ |
bdd4b6a6 | 6225 | if (pipe == PIPE_A) |
ab3c759a | 6226 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6227 | 0x0df40000); |
6228 | else | |
ab3c759a | 6229 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6230 | 0x0df70000); |
6231 | } else { /* HDMI or VGA */ | |
6232 | /* Use bend source */ | |
bdd4b6a6 | 6233 | if (pipe == PIPE_A) |
ab3c759a | 6234 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6235 | 0x0df70000); |
6236 | else | |
ab3c759a | 6237 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6238 | 0x0df40000); |
6239 | } | |
a0c4da24 | 6240 | |
ab3c759a | 6241 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6242 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6243 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6244 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6245 | coreclk |= 0x01000000; |
ab3c759a | 6246 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6247 | |
ab3c759a | 6248 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6249 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6250 | } |
6251 | ||
d288f65f | 6252 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6253 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6254 | { |
d288f65f | 6255 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6256 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6257 | DPLL_VCO_ENABLE; | |
6258 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6259 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6260 | |
d288f65f VS |
6261 | pipe_config->dpll_hw_state.dpll_md = |
6262 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6263 | } |
6264 | ||
d288f65f | 6265 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6266 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6267 | { |
6268 | struct drm_device *dev = crtc->base.dev; | |
6269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6270 | int pipe = crtc->pipe; | |
6271 | int dpll_reg = DPLL(crtc->pipe); | |
6272 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6273 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6274 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6275 | u32 dpio_val; |
9cbe40c1 | 6276 | int vco; |
9d556c99 | 6277 | |
d288f65f VS |
6278 | bestn = pipe_config->dpll.n; |
6279 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6280 | bestm1 = pipe_config->dpll.m1; | |
6281 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6282 | bestp1 = pipe_config->dpll.p1; | |
6283 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6284 | vco = pipe_config->dpll.vco; |
a945ce7e | 6285 | dpio_val = 0; |
9cbe40c1 | 6286 | loopfilter = 0; |
9d556c99 CML |
6287 | |
6288 | /* | |
6289 | * Enable Refclk and SSC | |
6290 | */ | |
a11b0703 | 6291 | I915_WRITE(dpll_reg, |
d288f65f | 6292 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
6293 | |
6294 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 6295 | |
9d556c99 CML |
6296 | /* p1 and p2 divider */ |
6297 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6298 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6299 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6300 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6301 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6302 | ||
6303 | /* Feedback post-divider - m2 */ | |
6304 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6305 | ||
6306 | /* Feedback refclk divider - n and m1 */ | |
6307 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6308 | DPIO_CHV_M1_DIV_BY_2 | | |
6309 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6310 | ||
6311 | /* M2 fraction division */ | |
a945ce7e VP |
6312 | if (bestm2_frac) |
6313 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
6314 | |
6315 | /* M2 fraction division enable */ | |
a945ce7e VP |
6316 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6317 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6318 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6319 | if (bestm2_frac) | |
6320 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6321 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6322 | |
de3a0fde VP |
6323 | /* Program digital lock detect threshold */ |
6324 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6325 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6326 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6327 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6328 | if (!bestm2_frac) | |
6329 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6330 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6331 | ||
9d556c99 | 6332 | /* Loop filter */ |
9cbe40c1 VP |
6333 | if (vco == 5400000) { |
6334 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6335 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6336 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6337 | tribuf_calcntr = 0x9; | |
6338 | } else if (vco <= 6200000) { | |
6339 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6340 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6341 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6342 | tribuf_calcntr = 0x9; | |
6343 | } else if (vco <= 6480000) { | |
6344 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6345 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6346 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6347 | tribuf_calcntr = 0x8; | |
6348 | } else { | |
6349 | /* Not supported. Apply the same limits as in the max case */ | |
6350 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6351 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6352 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6353 | tribuf_calcntr = 0; | |
6354 | } | |
9d556c99 CML |
6355 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6356 | ||
968040b2 | 6357 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6358 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6359 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6360 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6361 | ||
9d556c99 CML |
6362 | /* AFC Recal */ |
6363 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6364 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6365 | DPIO_AFC_RECAL); | |
6366 | ||
6367 | mutex_unlock(&dev_priv->dpio_lock); | |
6368 | } | |
6369 | ||
d288f65f VS |
6370 | /** |
6371 | * vlv_force_pll_on - forcibly enable just the PLL | |
6372 | * @dev_priv: i915 private structure | |
6373 | * @pipe: pipe PLL to enable | |
6374 | * @dpll: PLL configuration | |
6375 | * | |
6376 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6377 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6378 | * be enabled. | |
6379 | */ | |
6380 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6381 | const struct dpll *dpll) | |
6382 | { | |
6383 | struct intel_crtc *crtc = | |
6384 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 6385 | struct intel_crtc_state pipe_config = { |
d288f65f VS |
6386 | .pixel_multiplier = 1, |
6387 | .dpll = *dpll, | |
6388 | }; | |
6389 | ||
6390 | if (IS_CHERRYVIEW(dev)) { | |
6391 | chv_update_pll(crtc, &pipe_config); | |
6392 | chv_prepare_pll(crtc, &pipe_config); | |
6393 | chv_enable_pll(crtc, &pipe_config); | |
6394 | } else { | |
6395 | vlv_update_pll(crtc, &pipe_config); | |
6396 | vlv_prepare_pll(crtc, &pipe_config); | |
6397 | vlv_enable_pll(crtc, &pipe_config); | |
6398 | } | |
6399 | } | |
6400 | ||
6401 | /** | |
6402 | * vlv_force_pll_off - forcibly disable just the PLL | |
6403 | * @dev_priv: i915 private structure | |
6404 | * @pipe: pipe PLL to disable | |
6405 | * | |
6406 | * Disable the PLL for @pipe. To be used in cases where we need | |
6407 | * the PLL enabled even when @pipe is not going to be enabled. | |
6408 | */ | |
6409 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6410 | { | |
6411 | if (IS_CHERRYVIEW(dev)) | |
6412 | chv_disable_pll(to_i915(dev), pipe); | |
6413 | else | |
6414 | vlv_disable_pll(to_i915(dev), pipe); | |
6415 | } | |
6416 | ||
f47709a9 | 6417 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6418 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6419 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6420 | int num_connectors) |
6421 | { | |
f47709a9 | 6422 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6423 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6424 | u32 dpll; |
6425 | bool is_sdvo; | |
190f68c5 | 6426 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6427 | |
190f68c5 | 6428 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6429 | |
d0737e1d ACO |
6430 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6431 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6432 | |
6433 | dpll = DPLL_VGA_MODE_DIS; | |
6434 | ||
d0737e1d | 6435 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6436 | dpll |= DPLLB_MODE_LVDS; |
6437 | else | |
6438 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6439 | |
ef1b460d | 6440 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 6441 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6442 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6443 | } |
198a037f DV |
6444 | |
6445 | if (is_sdvo) | |
4a33e48d | 6446 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6447 | |
190f68c5 | 6448 | if (crtc_state->has_dp_encoder) |
4a33e48d | 6449 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6450 | |
6451 | /* compute bitmask from p1 value */ | |
6452 | if (IS_PINEVIEW(dev)) | |
6453 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6454 | else { | |
6455 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6456 | if (IS_G4X(dev) && reduced_clock) | |
6457 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6458 | } | |
6459 | switch (clock->p2) { | |
6460 | case 5: | |
6461 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6462 | break; | |
6463 | case 7: | |
6464 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6465 | break; | |
6466 | case 10: | |
6467 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6468 | break; | |
6469 | case 14: | |
6470 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6471 | break; | |
6472 | } | |
6473 | if (INTEL_INFO(dev)->gen >= 4) | |
6474 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6475 | ||
190f68c5 | 6476 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6477 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6478 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6479 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6480 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6481 | else | |
6482 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6483 | ||
6484 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6485 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6486 | |
eb1cbe48 | 6487 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 6488 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6489 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6490 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6491 | } |
6492 | } | |
6493 | ||
f47709a9 | 6494 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 6495 | struct intel_crtc_state *crtc_state, |
f47709a9 | 6496 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6497 | int num_connectors) |
6498 | { | |
f47709a9 | 6499 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6500 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6501 | u32 dpll; |
190f68c5 | 6502 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6503 | |
190f68c5 | 6504 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6505 | |
eb1cbe48 DV |
6506 | dpll = DPLL_VGA_MODE_DIS; |
6507 | ||
d0737e1d | 6508 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6509 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6510 | } else { | |
6511 | if (clock->p1 == 2) | |
6512 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6513 | else | |
6514 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6515 | if (clock->p2 == 4) | |
6516 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6517 | } | |
6518 | ||
d0737e1d | 6519 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6520 | dpll |= DPLL_DVO_2X_MODE; |
6521 | ||
d0737e1d | 6522 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6523 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6524 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6525 | else | |
6526 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6527 | ||
6528 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6529 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6530 | } |
6531 | ||
8a654f3b | 6532 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6533 | { |
6534 | struct drm_device *dev = intel_crtc->base.dev; | |
6535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6536 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 6537 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 6538 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 6539 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6540 | uint32_t crtc_vtotal, crtc_vblank_end; |
6541 | int vsyncshift = 0; | |
4d8a62ea DV |
6542 | |
6543 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6544 | * the hw state checker will get angry at the mismatch. */ | |
6545 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6546 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6547 | |
609aeaca | 6548 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6549 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6550 | crtc_vtotal -= 1; |
6551 | crtc_vblank_end -= 1; | |
609aeaca | 6552 | |
409ee761 | 6553 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6554 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6555 | else | |
6556 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6557 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6558 | if (vsyncshift < 0) |
6559 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6560 | } |
6561 | ||
6562 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6563 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6564 | |
fe2b8f9d | 6565 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6566 | (adjusted_mode->crtc_hdisplay - 1) | |
6567 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6568 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6569 | (adjusted_mode->crtc_hblank_start - 1) | |
6570 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6571 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6572 | (adjusted_mode->crtc_hsync_start - 1) | |
6573 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6574 | ||
fe2b8f9d | 6575 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6576 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6577 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6578 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6579 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6580 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6581 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6582 | (adjusted_mode->crtc_vsync_start - 1) | |
6583 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6584 | ||
b5e508d4 PZ |
6585 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6586 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6587 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6588 | * bits. */ | |
6589 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6590 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6591 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6592 | ||
b0e77b9c PZ |
6593 | /* pipesrc controls the size that is scaled from, which should |
6594 | * always be the user's requested size. | |
6595 | */ | |
6596 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6597 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6598 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6599 | } |
6600 | ||
1bd1bd80 | 6601 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6602 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6603 | { |
6604 | struct drm_device *dev = crtc->base.dev; | |
6605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6606 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6607 | uint32_t tmp; | |
6608 | ||
6609 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6610 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6611 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6612 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6613 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6614 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6615 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6616 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6617 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6618 | |
6619 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6620 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6621 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6622 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6623 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6624 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6625 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6626 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6627 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6628 | |
6629 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6630 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6631 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6632 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
6633 | } |
6634 | ||
6635 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6636 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6637 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6638 | ||
2d112de7 ACO |
6639 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6640 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6641 | } |
6642 | ||
f6a83288 | 6643 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6644 | struct intel_crtc_state *pipe_config) |
babea61d | 6645 | { |
2d112de7 ACO |
6646 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6647 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6648 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6649 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6650 | |
2d112de7 ACO |
6651 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6652 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6653 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6654 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6655 | |
2d112de7 | 6656 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 6657 | |
2d112de7 ACO |
6658 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
6659 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
6660 | } |
6661 | ||
84b046f3 DV |
6662 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6663 | { | |
6664 | struct drm_device *dev = intel_crtc->base.dev; | |
6665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6666 | uint32_t pipeconf; | |
6667 | ||
9f11a9e4 | 6668 | pipeconf = 0; |
84b046f3 | 6669 | |
b6b5d049 VS |
6670 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6671 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6672 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6673 | |
6e3c9717 | 6674 | if (intel_crtc->config->double_wide) |
cf532bb2 | 6675 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 6676 | |
ff9ce46e DV |
6677 | /* only g4x and later have fancy bpc/dither controls */ |
6678 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 6679 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 6680 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 6681 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 6682 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6683 | |
6e3c9717 | 6684 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
6685 | case 18: |
6686 | pipeconf |= PIPECONF_6BPC; | |
6687 | break; | |
6688 | case 24: | |
6689 | pipeconf |= PIPECONF_8BPC; | |
6690 | break; | |
6691 | case 30: | |
6692 | pipeconf |= PIPECONF_10BPC; | |
6693 | break; | |
6694 | default: | |
6695 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6696 | BUG(); | |
84b046f3 DV |
6697 | } |
6698 | } | |
6699 | ||
6700 | if (HAS_PIPE_CXSR(dev)) { | |
6701 | if (intel_crtc->lowfreq_avail) { | |
6702 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6703 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6704 | } else { | |
6705 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6706 | } |
6707 | } | |
6708 | ||
6e3c9717 | 6709 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 6710 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 6711 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6712 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6713 | else | |
6714 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6715 | } else | |
84b046f3 DV |
6716 | pipeconf |= PIPECONF_PROGRESSIVE; |
6717 | ||
6e3c9717 | 6718 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 6719 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 6720 | |
84b046f3 DV |
6721 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6722 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6723 | } | |
6724 | ||
190f68c5 ACO |
6725 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
6726 | struct intel_crtc_state *crtc_state) | |
79e53945 | 6727 | { |
c7653199 | 6728 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6729 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6730 | int refclk, num_connectors = 0; |
652c393a | 6731 | intel_clock_t clock, reduced_clock; |
a16af721 | 6732 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6733 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6734 | struct intel_encoder *encoder; |
d4906093 | 6735 | const intel_limit_t *limit; |
79e53945 | 6736 | |
d0737e1d ACO |
6737 | for_each_intel_encoder(dev, encoder) { |
6738 | if (encoder->new_crtc != crtc) | |
6739 | continue; | |
6740 | ||
5eddb70b | 6741 | switch (encoder->type) { |
79e53945 JB |
6742 | case INTEL_OUTPUT_LVDS: |
6743 | is_lvds = true; | |
6744 | break; | |
e9fd1c02 JN |
6745 | case INTEL_OUTPUT_DSI: |
6746 | is_dsi = true; | |
6747 | break; | |
6847d71b PZ |
6748 | default: |
6749 | break; | |
79e53945 | 6750 | } |
43565a06 | 6751 | |
c751ce4f | 6752 | num_connectors++; |
79e53945 JB |
6753 | } |
6754 | ||
f2335330 | 6755 | if (is_dsi) |
5b18e57c | 6756 | return 0; |
f2335330 | 6757 | |
190f68c5 | 6758 | if (!crtc_state->clock_set) { |
409ee761 | 6759 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6760 | |
e9fd1c02 JN |
6761 | /* |
6762 | * Returns a set of divisors for the desired target clock with | |
6763 | * the given refclk, or FALSE. The returned values represent | |
6764 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6765 | * 2) / p1 / p2. | |
6766 | */ | |
409ee761 | 6767 | limit = intel_limit(crtc, refclk); |
c7653199 | 6768 | ok = dev_priv->display.find_dpll(limit, crtc, |
190f68c5 | 6769 | crtc_state->port_clock, |
e9fd1c02 | 6770 | refclk, NULL, &clock); |
f2335330 | 6771 | if (!ok) { |
e9fd1c02 JN |
6772 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6773 | return -EINVAL; | |
6774 | } | |
79e53945 | 6775 | |
f2335330 JN |
6776 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6777 | /* | |
6778 | * Ensure we match the reduced clock's P to the target | |
6779 | * clock. If the clocks don't match, we can't switch | |
6780 | * the display clock by using the FP0/FP1. In such case | |
6781 | * we will disable the LVDS downclock feature. | |
6782 | */ | |
6783 | has_reduced_clock = | |
c7653199 | 6784 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6785 | dev_priv->lvds_downclock, |
6786 | refclk, &clock, | |
6787 | &reduced_clock); | |
6788 | } | |
6789 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
6790 | crtc_state->dpll.n = clock.n; |
6791 | crtc_state->dpll.m1 = clock.m1; | |
6792 | crtc_state->dpll.m2 = clock.m2; | |
6793 | crtc_state->dpll.p1 = clock.p1; | |
6794 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 6795 | } |
7026d4ac | 6796 | |
e9fd1c02 | 6797 | if (IS_GEN2(dev)) { |
190f68c5 | 6798 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
6799 | has_reduced_clock ? &reduced_clock : NULL, |
6800 | num_connectors); | |
9d556c99 | 6801 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 6802 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6803 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 6804 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 6805 | } else { |
190f68c5 | 6806 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 6807 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6808 | num_connectors); |
e9fd1c02 | 6809 | } |
79e53945 | 6810 | |
c8f7a0db | 6811 | return 0; |
f564048e EA |
6812 | } |
6813 | ||
2fa2fe9a | 6814 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 6815 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
6816 | { |
6817 | struct drm_device *dev = crtc->base.dev; | |
6818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6819 | uint32_t tmp; | |
6820 | ||
dc9e7dec VS |
6821 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6822 | return; | |
6823 | ||
2fa2fe9a | 6824 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6825 | if (!(tmp & PFIT_ENABLE)) |
6826 | return; | |
2fa2fe9a | 6827 | |
06922821 | 6828 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6829 | if (INTEL_INFO(dev)->gen < 4) { |
6830 | if (crtc->pipe != PIPE_B) | |
6831 | return; | |
2fa2fe9a DV |
6832 | } else { |
6833 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6834 | return; | |
6835 | } | |
6836 | ||
06922821 | 6837 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6838 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6839 | if (INTEL_INFO(dev)->gen < 5) | |
6840 | pipe_config->gmch_pfit.lvds_border_bits = | |
6841 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6842 | } | |
6843 | ||
acbec814 | 6844 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6845 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
6846 | { |
6847 | struct drm_device *dev = crtc->base.dev; | |
6848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6849 | int pipe = pipe_config->cpu_transcoder; | |
6850 | intel_clock_t clock; | |
6851 | u32 mdiv; | |
662c6ecb | 6852 | int refclk = 100000; |
acbec814 | 6853 | |
f573de5a SK |
6854 | /* In case of MIPI DPLL will not even be used */ |
6855 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6856 | return; | |
6857 | ||
acbec814 | 6858 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6859 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6860 | mutex_unlock(&dev_priv->dpio_lock); |
6861 | ||
6862 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6863 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6864 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6865 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6866 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6867 | ||
f646628b | 6868 | vlv_clock(refclk, &clock); |
acbec814 | 6869 | |
f646628b VS |
6870 | /* clock.dot is the fast clock */ |
6871 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6872 | } |
6873 | ||
5724dbd1 DL |
6874 | static void |
6875 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
6876 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
6877 | { |
6878 | struct drm_device *dev = crtc->base.dev; | |
6879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6880 | u32 val, base, offset; | |
6881 | int pipe = crtc->pipe, plane = crtc->plane; | |
6882 | int fourcc, pixel_format; | |
6761dd31 | 6883 | unsigned int aligned_height; |
b113d5ee | 6884 | struct drm_framebuffer *fb; |
1b842c89 | 6885 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 6886 | |
42a7b088 DL |
6887 | val = I915_READ(DSPCNTR(plane)); |
6888 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
6889 | return; | |
6890 | ||
d9806c9f | 6891 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 6892 | if (!intel_fb) { |
1ad292b5 JB |
6893 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6894 | return; | |
6895 | } | |
6896 | ||
1b842c89 DL |
6897 | fb = &intel_fb->base; |
6898 | ||
18c5247e DV |
6899 | if (INTEL_INFO(dev)->gen >= 4) { |
6900 | if (val & DISPPLANE_TILED) { | |
49af449b | 6901 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
6902 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
6903 | } | |
6904 | } | |
1ad292b5 JB |
6905 | |
6906 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 6907 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
6908 | fb->pixel_format = fourcc; |
6909 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
6910 | |
6911 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 6912 | if (plane_config->tiling) |
1ad292b5 JB |
6913 | offset = I915_READ(DSPTILEOFF(plane)); |
6914 | else | |
6915 | offset = I915_READ(DSPLINOFF(plane)); | |
6916 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6917 | } else { | |
6918 | base = I915_READ(DSPADDR(plane)); | |
6919 | } | |
6920 | plane_config->base = base; | |
6921 | ||
6922 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
6923 | fb->width = ((val >> 16) & 0xfff) + 1; |
6924 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6925 | |
6926 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 6927 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6928 | |
b113d5ee | 6929 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
6930 | fb->pixel_format, |
6931 | fb->modifier[0]); | |
1ad292b5 | 6932 | |
f37b5c2b | 6933 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 6934 | |
2844a921 DL |
6935 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
6936 | pipe_name(pipe), plane, fb->width, fb->height, | |
6937 | fb->bits_per_pixel, base, fb->pitches[0], | |
6938 | plane_config->size); | |
1ad292b5 | 6939 | |
2d14030b | 6940 | plane_config->fb = intel_fb; |
1ad292b5 JB |
6941 | } |
6942 | ||
70b23a98 | 6943 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 6944 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
6945 | { |
6946 | struct drm_device *dev = crtc->base.dev; | |
6947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6948 | int pipe = pipe_config->cpu_transcoder; | |
6949 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6950 | intel_clock_t clock; | |
6951 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6952 | int refclk = 100000; | |
6953 | ||
6954 | mutex_lock(&dev_priv->dpio_lock); | |
6955 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6956 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6957 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6958 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6959 | mutex_unlock(&dev_priv->dpio_lock); | |
6960 | ||
6961 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6962 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6963 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6964 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6965 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6966 | ||
6967 | chv_clock(refclk, &clock); | |
6968 | ||
6969 | /* clock.dot is the fast clock */ | |
6970 | pipe_config->port_clock = clock.dot / 5; | |
6971 | } | |
6972 | ||
0e8ffe1b | 6973 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 6974 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
6975 | { |
6976 | struct drm_device *dev = crtc->base.dev; | |
6977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6978 | uint32_t tmp; | |
6979 | ||
f458ebbc DV |
6980 | if (!intel_display_power_is_enabled(dev_priv, |
6981 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6982 | return false; |
6983 | ||
e143a21c | 6984 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6985 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6986 | |
0e8ffe1b DV |
6987 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6988 | if (!(tmp & PIPECONF_ENABLE)) | |
6989 | return false; | |
6990 | ||
42571aef VS |
6991 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6992 | switch (tmp & PIPECONF_BPC_MASK) { | |
6993 | case PIPECONF_6BPC: | |
6994 | pipe_config->pipe_bpp = 18; | |
6995 | break; | |
6996 | case PIPECONF_8BPC: | |
6997 | pipe_config->pipe_bpp = 24; | |
6998 | break; | |
6999 | case PIPECONF_10BPC: | |
7000 | pipe_config->pipe_bpp = 30; | |
7001 | break; | |
7002 | default: | |
7003 | break; | |
7004 | } | |
7005 | } | |
7006 | ||
b5a9fa09 DV |
7007 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7008 | pipe_config->limited_color_range = true; | |
7009 | ||
282740f7 VS |
7010 | if (INTEL_INFO(dev)->gen < 4) |
7011 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7012 | ||
1bd1bd80 DV |
7013 | intel_get_pipe_timings(crtc, pipe_config); |
7014 | ||
2fa2fe9a DV |
7015 | i9xx_get_pfit_config(crtc, pipe_config); |
7016 | ||
6c49f241 DV |
7017 | if (INTEL_INFO(dev)->gen >= 4) { |
7018 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7019 | pipe_config->pixel_multiplier = | |
7020 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7021 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7022 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7023 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7024 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7025 | pipe_config->pixel_multiplier = | |
7026 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7027 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7028 | } else { | |
7029 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7030 | * port and will be fixed up in the encoder->get_config | |
7031 | * function. */ | |
7032 | pipe_config->pixel_multiplier = 1; | |
7033 | } | |
8bcc2795 DV |
7034 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7035 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7036 | /* |
7037 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7038 | * on 830. Filter it out here so that we don't | |
7039 | * report errors due to that. | |
7040 | */ | |
7041 | if (IS_I830(dev)) | |
7042 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7043 | ||
8bcc2795 DV |
7044 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7045 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7046 | } else { |
7047 | /* Mask out read-only status bits. */ | |
7048 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7049 | DPLL_PORTC_READY_MASK | | |
7050 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7051 | } |
6c49f241 | 7052 | |
70b23a98 VS |
7053 | if (IS_CHERRYVIEW(dev)) |
7054 | chv_crtc_clock_get(crtc, pipe_config); | |
7055 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7056 | vlv_crtc_clock_get(crtc, pipe_config); |
7057 | else | |
7058 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7059 | |
0e8ffe1b DV |
7060 | return true; |
7061 | } | |
7062 | ||
dde86e2d | 7063 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7064 | { |
7065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7066 | struct intel_encoder *encoder; |
74cfd7ac | 7067 | u32 val, final; |
13d83a67 | 7068 | bool has_lvds = false; |
199e5d79 | 7069 | bool has_cpu_edp = false; |
199e5d79 | 7070 | bool has_panel = false; |
99eb6a01 KP |
7071 | bool has_ck505 = false; |
7072 | bool can_ssc = false; | |
13d83a67 JB |
7073 | |
7074 | /* We need to take the global config into account */ | |
b2784e15 | 7075 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7076 | switch (encoder->type) { |
7077 | case INTEL_OUTPUT_LVDS: | |
7078 | has_panel = true; | |
7079 | has_lvds = true; | |
7080 | break; | |
7081 | case INTEL_OUTPUT_EDP: | |
7082 | has_panel = true; | |
2de6905f | 7083 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7084 | has_cpu_edp = true; |
7085 | break; | |
6847d71b PZ |
7086 | default: |
7087 | break; | |
13d83a67 JB |
7088 | } |
7089 | } | |
7090 | ||
99eb6a01 | 7091 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7092 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7093 | can_ssc = has_ck505; |
7094 | } else { | |
7095 | has_ck505 = false; | |
7096 | can_ssc = true; | |
7097 | } | |
7098 | ||
2de6905f ID |
7099 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7100 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7101 | |
7102 | /* Ironlake: try to setup display ref clock before DPLL | |
7103 | * enabling. This is only under driver's control after | |
7104 | * PCH B stepping, previous chipset stepping should be | |
7105 | * ignoring this setting. | |
7106 | */ | |
74cfd7ac CW |
7107 | val = I915_READ(PCH_DREF_CONTROL); |
7108 | ||
7109 | /* As we must carefully and slowly disable/enable each source in turn, | |
7110 | * compute the final state we want first and check if we need to | |
7111 | * make any changes at all. | |
7112 | */ | |
7113 | final = val; | |
7114 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7115 | if (has_ck505) | |
7116 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7117 | else | |
7118 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7119 | ||
7120 | final &= ~DREF_SSC_SOURCE_MASK; | |
7121 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7122 | final &= ~DREF_SSC1_ENABLE; | |
7123 | ||
7124 | if (has_panel) { | |
7125 | final |= DREF_SSC_SOURCE_ENABLE; | |
7126 | ||
7127 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7128 | final |= DREF_SSC1_ENABLE; | |
7129 | ||
7130 | if (has_cpu_edp) { | |
7131 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7132 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7133 | else | |
7134 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7135 | } else | |
7136 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7137 | } else { | |
7138 | final |= DREF_SSC_SOURCE_DISABLE; | |
7139 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7140 | } | |
7141 | ||
7142 | if (final == val) | |
7143 | return; | |
7144 | ||
13d83a67 | 7145 | /* Always enable nonspread source */ |
74cfd7ac | 7146 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7147 | |
99eb6a01 | 7148 | if (has_ck505) |
74cfd7ac | 7149 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7150 | else |
74cfd7ac | 7151 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7152 | |
199e5d79 | 7153 | if (has_panel) { |
74cfd7ac CW |
7154 | val &= ~DREF_SSC_SOURCE_MASK; |
7155 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7156 | |
199e5d79 | 7157 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7158 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7159 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7160 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7161 | } else |
74cfd7ac | 7162 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7163 | |
7164 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7165 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7166 | POSTING_READ(PCH_DREF_CONTROL); |
7167 | udelay(200); | |
7168 | ||
74cfd7ac | 7169 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7170 | |
7171 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7172 | if (has_cpu_edp) { |
99eb6a01 | 7173 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7174 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7175 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7176 | } else |
74cfd7ac | 7177 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7178 | } else |
74cfd7ac | 7179 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7180 | |
74cfd7ac | 7181 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7182 | POSTING_READ(PCH_DREF_CONTROL); |
7183 | udelay(200); | |
7184 | } else { | |
7185 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7186 | ||
74cfd7ac | 7187 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7188 | |
7189 | /* Turn off CPU output */ | |
74cfd7ac | 7190 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7191 | |
74cfd7ac | 7192 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7193 | POSTING_READ(PCH_DREF_CONTROL); |
7194 | udelay(200); | |
7195 | ||
7196 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7197 | val &= ~DREF_SSC_SOURCE_MASK; |
7198 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7199 | |
7200 | /* Turn off SSC1 */ | |
74cfd7ac | 7201 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7202 | |
74cfd7ac | 7203 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7204 | POSTING_READ(PCH_DREF_CONTROL); |
7205 | udelay(200); | |
7206 | } | |
74cfd7ac CW |
7207 | |
7208 | BUG_ON(val != final); | |
13d83a67 JB |
7209 | } |
7210 | ||
f31f2d55 | 7211 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7212 | { |
f31f2d55 | 7213 | uint32_t tmp; |
dde86e2d | 7214 | |
0ff066a9 PZ |
7215 | tmp = I915_READ(SOUTH_CHICKEN2); |
7216 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7217 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7218 | |
0ff066a9 PZ |
7219 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7220 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7221 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7222 | |
0ff066a9 PZ |
7223 | tmp = I915_READ(SOUTH_CHICKEN2); |
7224 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7225 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7226 | |
0ff066a9 PZ |
7227 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7228 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7229 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7230 | } |
7231 | ||
7232 | /* WaMPhyProgramming:hsw */ | |
7233 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7234 | { | |
7235 | uint32_t tmp; | |
dde86e2d PZ |
7236 | |
7237 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7238 | tmp &= ~(0xFF << 24); | |
7239 | tmp |= (0x12 << 24); | |
7240 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7241 | ||
dde86e2d PZ |
7242 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7243 | tmp |= (1 << 11); | |
7244 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7245 | ||
7246 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7247 | tmp |= (1 << 11); | |
7248 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7249 | ||
dde86e2d PZ |
7250 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7251 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7252 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7253 | ||
7254 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7255 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7256 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7257 | ||
0ff066a9 PZ |
7258 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7259 | tmp &= ~(7 << 13); | |
7260 | tmp |= (5 << 13); | |
7261 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7262 | |
0ff066a9 PZ |
7263 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7264 | tmp &= ~(7 << 13); | |
7265 | tmp |= (5 << 13); | |
7266 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7267 | |
7268 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7269 | tmp &= ~0xFF; | |
7270 | tmp |= 0x1C; | |
7271 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7272 | ||
7273 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7274 | tmp &= ~0xFF; | |
7275 | tmp |= 0x1C; | |
7276 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7277 | ||
7278 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7279 | tmp &= ~(0xFF << 16); | |
7280 | tmp |= (0x1C << 16); | |
7281 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7282 | ||
7283 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7284 | tmp &= ~(0xFF << 16); | |
7285 | tmp |= (0x1C << 16); | |
7286 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7287 | ||
0ff066a9 PZ |
7288 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7289 | tmp |= (1 << 27); | |
7290 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7291 | |
0ff066a9 PZ |
7292 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7293 | tmp |= (1 << 27); | |
7294 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7295 | |
0ff066a9 PZ |
7296 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7297 | tmp &= ~(0xF << 28); | |
7298 | tmp |= (4 << 28); | |
7299 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7300 | |
0ff066a9 PZ |
7301 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7302 | tmp &= ~(0xF << 28); | |
7303 | tmp |= (4 << 28); | |
7304 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7305 | } |
7306 | ||
2fa86a1f PZ |
7307 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7308 | * Programming" based on the parameters passed: | |
7309 | * - Sequence to enable CLKOUT_DP | |
7310 | * - Sequence to enable CLKOUT_DP without spread | |
7311 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7312 | */ | |
7313 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
7314 | bool with_fdi) | |
f31f2d55 PZ |
7315 | { |
7316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
7317 | uint32_t reg, tmp; |
7318 | ||
7319 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7320 | with_spread = true; | |
7321 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
7322 | with_fdi, "LP PCH doesn't have FDI\n")) | |
7323 | with_fdi = false; | |
f31f2d55 PZ |
7324 | |
7325 | mutex_lock(&dev_priv->dpio_lock); | |
7326 | ||
7327 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7328 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7329 | tmp |= SBI_SSCCTL_PATHALT; | |
7330 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7331 | ||
7332 | udelay(24); | |
7333 | ||
2fa86a1f PZ |
7334 | if (with_spread) { |
7335 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7336 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7337 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7338 | |
2fa86a1f PZ |
7339 | if (with_fdi) { |
7340 | lpt_reset_fdi_mphy(dev_priv); | |
7341 | lpt_program_fdi_mphy(dev_priv); | |
7342 | } | |
7343 | } | |
dde86e2d | 7344 | |
2fa86a1f PZ |
7345 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7346 | SBI_GEN0 : SBI_DBUFF0; | |
7347 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7348 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7349 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7350 | |
7351 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7352 | } |
7353 | ||
47701c3b PZ |
7354 | /* Sequence to disable CLKOUT_DP */ |
7355 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7356 | { | |
7357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7358 | uint32_t reg, tmp; | |
7359 | ||
7360 | mutex_lock(&dev_priv->dpio_lock); | |
7361 | ||
7362 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7363 | SBI_GEN0 : SBI_DBUFF0; | |
7364 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7365 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7366 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7367 | ||
7368 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7369 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7370 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7371 | tmp |= SBI_SSCCTL_PATHALT; | |
7372 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7373 | udelay(32); | |
7374 | } | |
7375 | tmp |= SBI_SSCCTL_DISABLE; | |
7376 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7377 | } | |
7378 | ||
7379 | mutex_unlock(&dev_priv->dpio_lock); | |
7380 | } | |
7381 | ||
bf8fa3d3 PZ |
7382 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7383 | { | |
bf8fa3d3 PZ |
7384 | struct intel_encoder *encoder; |
7385 | bool has_vga = false; | |
7386 | ||
b2784e15 | 7387 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7388 | switch (encoder->type) { |
7389 | case INTEL_OUTPUT_ANALOG: | |
7390 | has_vga = true; | |
7391 | break; | |
6847d71b PZ |
7392 | default: |
7393 | break; | |
bf8fa3d3 PZ |
7394 | } |
7395 | } | |
7396 | ||
47701c3b PZ |
7397 | if (has_vga) |
7398 | lpt_enable_clkout_dp(dev, true, true); | |
7399 | else | |
7400 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7401 | } |
7402 | ||
dde86e2d PZ |
7403 | /* |
7404 | * Initialize reference clocks when the driver loads | |
7405 | */ | |
7406 | void intel_init_pch_refclk(struct drm_device *dev) | |
7407 | { | |
7408 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7409 | ironlake_init_pch_refclk(dev); | |
7410 | else if (HAS_PCH_LPT(dev)) | |
7411 | lpt_init_pch_refclk(dev); | |
7412 | } | |
7413 | ||
d9d444cb JB |
7414 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7415 | { | |
7416 | struct drm_device *dev = crtc->dev; | |
7417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7418 | struct intel_encoder *encoder; | |
d9d444cb JB |
7419 | int num_connectors = 0; |
7420 | bool is_lvds = false; | |
7421 | ||
d0737e1d ACO |
7422 | for_each_intel_encoder(dev, encoder) { |
7423 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7424 | continue; | |
7425 | ||
d9d444cb JB |
7426 | switch (encoder->type) { |
7427 | case INTEL_OUTPUT_LVDS: | |
7428 | is_lvds = true; | |
7429 | break; | |
6847d71b PZ |
7430 | default: |
7431 | break; | |
d9d444cb JB |
7432 | } |
7433 | num_connectors++; | |
7434 | } | |
7435 | ||
7436 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7437 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7438 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7439 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7440 | } |
7441 | ||
7442 | return 120000; | |
7443 | } | |
7444 | ||
6ff93609 | 7445 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7446 | { |
c8203565 | 7447 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7448 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7449 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7450 | uint32_t val; |
7451 | ||
78114071 | 7452 | val = 0; |
c8203565 | 7453 | |
6e3c9717 | 7454 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7455 | case 18: |
dfd07d72 | 7456 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7457 | break; |
7458 | case 24: | |
dfd07d72 | 7459 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7460 | break; |
7461 | case 30: | |
dfd07d72 | 7462 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7463 | break; |
7464 | case 36: | |
dfd07d72 | 7465 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7466 | break; |
7467 | default: | |
cc769b62 PZ |
7468 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7469 | BUG(); | |
c8203565 PZ |
7470 | } |
7471 | ||
6e3c9717 | 7472 | if (intel_crtc->config->dither) |
c8203565 PZ |
7473 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7474 | ||
6e3c9717 | 7475 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7476 | val |= PIPECONF_INTERLACED_ILK; |
7477 | else | |
7478 | val |= PIPECONF_PROGRESSIVE; | |
7479 | ||
6e3c9717 | 7480 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7481 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7482 | |
c8203565 PZ |
7483 | I915_WRITE(PIPECONF(pipe), val); |
7484 | POSTING_READ(PIPECONF(pipe)); | |
7485 | } | |
7486 | ||
86d3efce VS |
7487 | /* |
7488 | * Set up the pipe CSC unit. | |
7489 | * | |
7490 | * Currently only full range RGB to limited range RGB conversion | |
7491 | * is supported, but eventually this should handle various | |
7492 | * RGB<->YCbCr scenarios as well. | |
7493 | */ | |
50f3b016 | 7494 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7495 | { |
7496 | struct drm_device *dev = crtc->dev; | |
7497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7498 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7499 | int pipe = intel_crtc->pipe; | |
7500 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7501 | ||
7502 | /* | |
7503 | * TODO: Check what kind of values actually come out of the pipe | |
7504 | * with these coeff/postoff values and adjust to get the best | |
7505 | * accuracy. Perhaps we even need to take the bpc value into | |
7506 | * consideration. | |
7507 | */ | |
7508 | ||
6e3c9717 | 7509 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7510 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7511 | ||
7512 | /* | |
7513 | * GY/GU and RY/RU should be the other way around according | |
7514 | * to BSpec, but reality doesn't agree. Just set them up in | |
7515 | * a way that results in the correct picture. | |
7516 | */ | |
7517 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7518 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7519 | ||
7520 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7521 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7522 | ||
7523 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7524 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7525 | ||
7526 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7527 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7528 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7529 | ||
7530 | if (INTEL_INFO(dev)->gen > 6) { | |
7531 | uint16_t postoff = 0; | |
7532 | ||
6e3c9717 | 7533 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 7534 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7535 | |
7536 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7537 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7538 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7539 | ||
7540 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7541 | } else { | |
7542 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7543 | ||
6e3c9717 | 7544 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
7545 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7546 | ||
7547 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7548 | } | |
7549 | } | |
7550 | ||
6ff93609 | 7551 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7552 | { |
756f85cf PZ |
7553 | struct drm_device *dev = crtc->dev; |
7554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7556 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7557 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
7558 | uint32_t val; |
7559 | ||
3eff4faa | 7560 | val = 0; |
ee2b0b38 | 7561 | |
6e3c9717 | 7562 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7563 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7564 | ||
6e3c9717 | 7565 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7566 | val |= PIPECONF_INTERLACED_ILK; |
7567 | else | |
7568 | val |= PIPECONF_PROGRESSIVE; | |
7569 | ||
702e7a56 PZ |
7570 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7571 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7572 | |
7573 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7574 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7575 | |
3cdf122c | 7576 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7577 | val = 0; |
7578 | ||
6e3c9717 | 7579 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
7580 | case 18: |
7581 | val |= PIPEMISC_DITHER_6_BPC; | |
7582 | break; | |
7583 | case 24: | |
7584 | val |= PIPEMISC_DITHER_8_BPC; | |
7585 | break; | |
7586 | case 30: | |
7587 | val |= PIPEMISC_DITHER_10_BPC; | |
7588 | break; | |
7589 | case 36: | |
7590 | val |= PIPEMISC_DITHER_12_BPC; | |
7591 | break; | |
7592 | default: | |
7593 | /* Case prevented by pipe_config_set_bpp. */ | |
7594 | BUG(); | |
7595 | } | |
7596 | ||
6e3c9717 | 7597 | if (intel_crtc->config->dither) |
756f85cf PZ |
7598 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
7599 | ||
7600 | I915_WRITE(PIPEMISC(pipe), val); | |
7601 | } | |
ee2b0b38 PZ |
7602 | } |
7603 | ||
6591c6e4 | 7604 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 7605 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
7606 | intel_clock_t *clock, |
7607 | bool *has_reduced_clock, | |
7608 | intel_clock_t *reduced_clock) | |
7609 | { | |
7610 | struct drm_device *dev = crtc->dev; | |
7611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7612 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7613 | int refclk; |
d4906093 | 7614 | const intel_limit_t *limit; |
a16af721 | 7615 | bool ret, is_lvds = false; |
79e53945 | 7616 | |
d0737e1d | 7617 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7618 | |
d9d444cb | 7619 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7620 | |
d4906093 ML |
7621 | /* |
7622 | * Returns a set of divisors for the desired target clock with the given | |
7623 | * refclk, or FALSE. The returned values represent the clock equation: | |
7624 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7625 | */ | |
409ee761 | 7626 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7627 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
190f68c5 | 7628 | crtc_state->port_clock, |
ee9300bb | 7629 | refclk, NULL, clock); |
6591c6e4 PZ |
7630 | if (!ret) |
7631 | return false; | |
cda4b7d3 | 7632 | |
ddc9003c | 7633 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7634 | /* |
7635 | * Ensure we match the reduced clock's P to the target clock. | |
7636 | * If the clocks don't match, we can't switch the display clock | |
7637 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7638 | * downclock feature. | |
7639 | */ | |
ee9300bb | 7640 | *has_reduced_clock = |
a919ff14 | 7641 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7642 | dev_priv->lvds_downclock, |
7643 | refclk, clock, | |
7644 | reduced_clock); | |
652c393a | 7645 | } |
61e9653f | 7646 | |
6591c6e4 PZ |
7647 | return true; |
7648 | } | |
7649 | ||
d4b1931c PZ |
7650 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7651 | { | |
7652 | /* | |
7653 | * Account for spread spectrum to avoid | |
7654 | * oversubscribing the link. Max center spread | |
7655 | * is 2.5%; use 5% for safety's sake. | |
7656 | */ | |
7657 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7658 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7659 | } |
7660 | ||
7429e9d4 | 7661 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7662 | { |
7429e9d4 | 7663 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7664 | } |
7665 | ||
de13a2e3 | 7666 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 7667 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 7668 | u32 *fp, |
9a7c7890 | 7669 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7670 | { |
de13a2e3 | 7671 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7672 | struct drm_device *dev = crtc->dev; |
7673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7674 | struct intel_encoder *intel_encoder; |
7675 | uint32_t dpll; | |
6cc5f341 | 7676 | int factor, num_connectors = 0; |
09ede541 | 7677 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7678 | |
d0737e1d ACO |
7679 | for_each_intel_encoder(dev, intel_encoder) { |
7680 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7681 | continue; | |
7682 | ||
de13a2e3 | 7683 | switch (intel_encoder->type) { |
79e53945 JB |
7684 | case INTEL_OUTPUT_LVDS: |
7685 | is_lvds = true; | |
7686 | break; | |
7687 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7688 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7689 | is_sdvo = true; |
79e53945 | 7690 | break; |
6847d71b PZ |
7691 | default: |
7692 | break; | |
79e53945 | 7693 | } |
43565a06 | 7694 | |
c751ce4f | 7695 | num_connectors++; |
79e53945 | 7696 | } |
79e53945 | 7697 | |
c1858123 | 7698 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7699 | factor = 21; |
7700 | if (is_lvds) { | |
7701 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7702 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7703 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7704 | factor = 25; |
190f68c5 | 7705 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 7706 | factor = 20; |
c1858123 | 7707 | |
190f68c5 | 7708 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 7709 | *fp |= FP_CB_TUNE; |
2c07245f | 7710 | |
9a7c7890 DV |
7711 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7712 | *fp2 |= FP_CB_TUNE; | |
7713 | ||
5eddb70b | 7714 | dpll = 0; |
2c07245f | 7715 | |
a07d6787 EA |
7716 | if (is_lvds) |
7717 | dpll |= DPLLB_MODE_LVDS; | |
7718 | else | |
7719 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7720 | |
190f68c5 | 7721 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7722 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7723 | |
7724 | if (is_sdvo) | |
4a33e48d | 7725 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 7726 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7727 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7728 | |
a07d6787 | 7729 | /* compute bitmask from p1 value */ |
190f68c5 | 7730 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7731 | /* also FPA1 */ |
190f68c5 | 7732 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7733 | |
190f68c5 | 7734 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
7735 | case 5: |
7736 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7737 | break; | |
7738 | case 7: | |
7739 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7740 | break; | |
7741 | case 10: | |
7742 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7743 | break; | |
7744 | case 14: | |
7745 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7746 | break; | |
79e53945 JB |
7747 | } |
7748 | ||
b4c09f3b | 7749 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7750 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7751 | else |
7752 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7753 | ||
959e16d6 | 7754 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7755 | } |
7756 | ||
190f68c5 ACO |
7757 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
7758 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 7759 | { |
c7653199 | 7760 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7761 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7762 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7763 | bool ok, has_reduced_clock = false; |
8b47047b | 7764 | bool is_lvds = false; |
e2b78267 | 7765 | struct intel_shared_dpll *pll; |
de13a2e3 | 7766 | |
409ee761 | 7767 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7768 | |
5dc5298b PZ |
7769 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7770 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7771 | |
190f68c5 | 7772 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 7773 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 7774 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
7775 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7776 | return -EINVAL; | |
79e53945 | 7777 | } |
f47709a9 | 7778 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7779 | if (!crtc_state->clock_set) { |
7780 | crtc_state->dpll.n = clock.n; | |
7781 | crtc_state->dpll.m1 = clock.m1; | |
7782 | crtc_state->dpll.m2 = clock.m2; | |
7783 | crtc_state->dpll.p1 = clock.p1; | |
7784 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7785 | } |
79e53945 | 7786 | |
5dc5298b | 7787 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
7788 | if (crtc_state->has_pch_encoder) { |
7789 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 7790 | if (has_reduced_clock) |
7429e9d4 | 7791 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7792 | |
190f68c5 | 7793 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
7794 | &fp, &reduced_clock, |
7795 | has_reduced_clock ? &fp2 : NULL); | |
7796 | ||
190f68c5 ACO |
7797 | crtc_state->dpll_hw_state.dpll = dpll; |
7798 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7799 | if (has_reduced_clock) |
190f68c5 | 7800 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7801 | else |
190f68c5 | 7802 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 7803 | |
190f68c5 | 7804 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 7805 | if (pll == NULL) { |
84f44ce7 | 7806 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7807 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7808 | return -EINVAL; |
7809 | } | |
3fb37703 | 7810 | } |
79e53945 | 7811 | |
ab585dea | 7812 | if (is_lvds && has_reduced_clock) |
c7653199 | 7813 | crtc->lowfreq_avail = true; |
bcd644e0 | 7814 | else |
c7653199 | 7815 | crtc->lowfreq_avail = false; |
e2b78267 | 7816 | |
c8f7a0db | 7817 | return 0; |
79e53945 JB |
7818 | } |
7819 | ||
eb14cb74 VS |
7820 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7821 | struct intel_link_m_n *m_n) | |
7822 | { | |
7823 | struct drm_device *dev = crtc->base.dev; | |
7824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7825 | enum pipe pipe = crtc->pipe; | |
7826 | ||
7827 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7828 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7829 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7830 | & ~TU_SIZE_MASK; | |
7831 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7832 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7833 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7834 | } | |
7835 | ||
7836 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7837 | enum transcoder transcoder, | |
b95af8be VK |
7838 | struct intel_link_m_n *m_n, |
7839 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7840 | { |
7841 | struct drm_device *dev = crtc->base.dev; | |
7842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7843 | enum pipe pipe = crtc->pipe; |
72419203 | 7844 | |
eb14cb74 VS |
7845 | if (INTEL_INFO(dev)->gen >= 5) { |
7846 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7847 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7848 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7849 | & ~TU_SIZE_MASK; | |
7850 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7851 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7852 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7853 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7854 | * gen < 8) and if DRRS is supported (to make sure the | |
7855 | * registers are not unnecessarily read). | |
7856 | */ | |
7857 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 7858 | crtc->config->has_drrs) { |
b95af8be VK |
7859 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
7860 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7861 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7862 | & ~TU_SIZE_MASK; | |
7863 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7864 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7865 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7866 | } | |
eb14cb74 VS |
7867 | } else { |
7868 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7869 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7870 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7871 | & ~TU_SIZE_MASK; | |
7872 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7873 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7874 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7875 | } | |
7876 | } | |
7877 | ||
7878 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 7879 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 7880 | { |
681a8504 | 7881 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
7882 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
7883 | else | |
7884 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7885 | &pipe_config->dp_m_n, |
7886 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7887 | } |
72419203 | 7888 | |
eb14cb74 | 7889 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 7890 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
7891 | { |
7892 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7893 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7894 | } |
7895 | ||
bd2e244f | 7896 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7897 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
7898 | { |
7899 | struct drm_device *dev = crtc->base.dev; | |
7900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7901 | uint32_t tmp; | |
7902 | ||
7903 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7904 | ||
7905 | if (tmp & PS_ENABLE) { | |
7906 | pipe_config->pch_pfit.enabled = true; | |
7907 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7908 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7909 | } | |
7910 | } | |
7911 | ||
5724dbd1 DL |
7912 | static void |
7913 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
7914 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
7915 | { |
7916 | struct drm_device *dev = crtc->base.dev; | |
7917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 7918 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
7919 | int pipe = crtc->pipe; |
7920 | int fourcc, pixel_format; | |
6761dd31 | 7921 | unsigned int aligned_height; |
bc8d7dff | 7922 | struct drm_framebuffer *fb; |
1b842c89 | 7923 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 7924 | |
d9806c9f | 7925 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7926 | if (!intel_fb) { |
bc8d7dff DL |
7927 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7928 | return; | |
7929 | } | |
7930 | ||
1b842c89 DL |
7931 | fb = &intel_fb->base; |
7932 | ||
bc8d7dff | 7933 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
7934 | if (!(val & PLANE_CTL_ENABLE)) |
7935 | goto error; | |
7936 | ||
bc8d7dff DL |
7937 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
7938 | fourcc = skl_format_to_fourcc(pixel_format, | |
7939 | val & PLANE_CTL_ORDER_RGBX, | |
7940 | val & PLANE_CTL_ALPHA_MASK); | |
7941 | fb->pixel_format = fourcc; | |
7942 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
7943 | ||
40f46283 DL |
7944 | tiling = val & PLANE_CTL_TILED_MASK; |
7945 | switch (tiling) { | |
7946 | case PLANE_CTL_TILED_LINEAR: | |
7947 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
7948 | break; | |
7949 | case PLANE_CTL_TILED_X: | |
7950 | plane_config->tiling = I915_TILING_X; | |
7951 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
7952 | break; | |
7953 | case PLANE_CTL_TILED_Y: | |
7954 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
7955 | break; | |
7956 | case PLANE_CTL_TILED_YF: | |
7957 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
7958 | break; | |
7959 | default: | |
7960 | MISSING_CASE(tiling); | |
7961 | goto error; | |
7962 | } | |
7963 | ||
bc8d7dff DL |
7964 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
7965 | plane_config->base = base; | |
7966 | ||
7967 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
7968 | ||
7969 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
7970 | fb->height = ((val >> 16) & 0xfff) + 1; | |
7971 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
7972 | ||
7973 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
7974 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
7975 | fb->pixel_format); | |
bc8d7dff DL |
7976 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
7977 | ||
7978 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
7979 | fb->pixel_format, |
7980 | fb->modifier[0]); | |
bc8d7dff | 7981 | |
f37b5c2b | 7982 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
7983 | |
7984 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
7985 | pipe_name(pipe), fb->width, fb->height, | |
7986 | fb->bits_per_pixel, base, fb->pitches[0], | |
7987 | plane_config->size); | |
7988 | ||
2d14030b | 7989 | plane_config->fb = intel_fb; |
bc8d7dff DL |
7990 | return; |
7991 | ||
7992 | error: | |
7993 | kfree(fb); | |
7994 | } | |
7995 | ||
2fa2fe9a | 7996 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7997 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7998 | { |
7999 | struct drm_device *dev = crtc->base.dev; | |
8000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8001 | uint32_t tmp; | |
8002 | ||
8003 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8004 | ||
8005 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8006 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8007 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8008 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8009 | |
8010 | /* We currently do not free assignements of panel fitters on | |
8011 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8012 | * differentiates them) so just WARN about this case for now. */ | |
8013 | if (IS_GEN7(dev)) { | |
8014 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8015 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8016 | } | |
2fa2fe9a | 8017 | } |
79e53945 JB |
8018 | } |
8019 | ||
5724dbd1 DL |
8020 | static void |
8021 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8022 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8023 | { |
8024 | struct drm_device *dev = crtc->base.dev; | |
8025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8026 | u32 val, base, offset; | |
aeee5a49 | 8027 | int pipe = crtc->pipe; |
4c6baa59 | 8028 | int fourcc, pixel_format; |
6761dd31 | 8029 | unsigned int aligned_height; |
b113d5ee | 8030 | struct drm_framebuffer *fb; |
1b842c89 | 8031 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8032 | |
42a7b088 DL |
8033 | val = I915_READ(DSPCNTR(pipe)); |
8034 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8035 | return; | |
8036 | ||
d9806c9f | 8037 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8038 | if (!intel_fb) { |
4c6baa59 JB |
8039 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8040 | return; | |
8041 | } | |
8042 | ||
1b842c89 DL |
8043 | fb = &intel_fb->base; |
8044 | ||
18c5247e DV |
8045 | if (INTEL_INFO(dev)->gen >= 4) { |
8046 | if (val & DISPPLANE_TILED) { | |
49af449b | 8047 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8048 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8049 | } | |
8050 | } | |
4c6baa59 JB |
8051 | |
8052 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8053 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8054 | fb->pixel_format = fourcc; |
8055 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8056 | |
aeee5a49 | 8057 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8058 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8059 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8060 | } else { |
49af449b | 8061 | if (plane_config->tiling) |
aeee5a49 | 8062 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8063 | else |
aeee5a49 | 8064 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8065 | } |
8066 | plane_config->base = base; | |
8067 | ||
8068 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8069 | fb->width = ((val >> 16) & 0xfff) + 1; |
8070 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8071 | |
8072 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8073 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8074 | |
b113d5ee | 8075 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8076 | fb->pixel_format, |
8077 | fb->modifier[0]); | |
4c6baa59 | 8078 | |
f37b5c2b | 8079 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8080 | |
2844a921 DL |
8081 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8082 | pipe_name(pipe), fb->width, fb->height, | |
8083 | fb->bits_per_pixel, base, fb->pitches[0], | |
8084 | plane_config->size); | |
b113d5ee | 8085 | |
2d14030b | 8086 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8087 | } |
8088 | ||
0e8ffe1b | 8089 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8090 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8091 | { |
8092 | struct drm_device *dev = crtc->base.dev; | |
8093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8094 | uint32_t tmp; | |
8095 | ||
f458ebbc DV |
8096 | if (!intel_display_power_is_enabled(dev_priv, |
8097 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8098 | return false; |
8099 | ||
e143a21c | 8100 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8101 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8102 | |
0e8ffe1b DV |
8103 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8104 | if (!(tmp & PIPECONF_ENABLE)) | |
8105 | return false; | |
8106 | ||
42571aef VS |
8107 | switch (tmp & PIPECONF_BPC_MASK) { |
8108 | case PIPECONF_6BPC: | |
8109 | pipe_config->pipe_bpp = 18; | |
8110 | break; | |
8111 | case PIPECONF_8BPC: | |
8112 | pipe_config->pipe_bpp = 24; | |
8113 | break; | |
8114 | case PIPECONF_10BPC: | |
8115 | pipe_config->pipe_bpp = 30; | |
8116 | break; | |
8117 | case PIPECONF_12BPC: | |
8118 | pipe_config->pipe_bpp = 36; | |
8119 | break; | |
8120 | default: | |
8121 | break; | |
8122 | } | |
8123 | ||
b5a9fa09 DV |
8124 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8125 | pipe_config->limited_color_range = true; | |
8126 | ||
ab9412ba | 8127 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8128 | struct intel_shared_dpll *pll; |
8129 | ||
88adfff1 DV |
8130 | pipe_config->has_pch_encoder = true; |
8131 | ||
627eb5a3 DV |
8132 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8133 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8134 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8135 | |
8136 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8137 | |
c0d43d62 | 8138 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8139 | pipe_config->shared_dpll = |
8140 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8141 | } else { |
8142 | tmp = I915_READ(PCH_DPLL_SEL); | |
8143 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8144 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8145 | else | |
8146 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8147 | } | |
66e985c0 DV |
8148 | |
8149 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8150 | ||
8151 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8152 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8153 | |
8154 | tmp = pipe_config->dpll_hw_state.dpll; | |
8155 | pipe_config->pixel_multiplier = | |
8156 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8157 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8158 | |
8159 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8160 | } else { |
8161 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8162 | } |
8163 | ||
1bd1bd80 DV |
8164 | intel_get_pipe_timings(crtc, pipe_config); |
8165 | ||
2fa2fe9a DV |
8166 | ironlake_get_pfit_config(crtc, pipe_config); |
8167 | ||
0e8ffe1b DV |
8168 | return true; |
8169 | } | |
8170 | ||
be256dc7 PZ |
8171 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8172 | { | |
8173 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8174 | struct intel_crtc *crtc; |
be256dc7 | 8175 | |
d3fcc808 | 8176 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8177 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8178 | pipe_name(crtc->pipe)); |
8179 | ||
e2c719b7 RC |
8180 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8181 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8182 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8183 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8184 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8185 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8186 | "CPU PWM1 enabled\n"); |
c5107b87 | 8187 | if (IS_HASWELL(dev)) |
e2c719b7 | 8188 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8189 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8190 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8191 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8192 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8193 | "Utility pin enabled\n"); |
e2c719b7 | 8194 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8195 | |
9926ada1 PZ |
8196 | /* |
8197 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8198 | * interrupts remain enabled. We used to check for that, but since it's | |
8199 | * gen-specific and since we only disable LCPLL after we fully disable | |
8200 | * the interrupts, the check below should be enough. | |
8201 | */ | |
e2c719b7 | 8202 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8203 | } |
8204 | ||
9ccd5aeb PZ |
8205 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8206 | { | |
8207 | struct drm_device *dev = dev_priv->dev; | |
8208 | ||
8209 | if (IS_HASWELL(dev)) | |
8210 | return I915_READ(D_COMP_HSW); | |
8211 | else | |
8212 | return I915_READ(D_COMP_BDW); | |
8213 | } | |
8214 | ||
3c4c9b81 PZ |
8215 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8216 | { | |
8217 | struct drm_device *dev = dev_priv->dev; | |
8218 | ||
8219 | if (IS_HASWELL(dev)) { | |
8220 | mutex_lock(&dev_priv->rps.hw_lock); | |
8221 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8222 | val)) | |
f475dadf | 8223 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8224 | mutex_unlock(&dev_priv->rps.hw_lock); |
8225 | } else { | |
9ccd5aeb PZ |
8226 | I915_WRITE(D_COMP_BDW, val); |
8227 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8228 | } |
be256dc7 PZ |
8229 | } |
8230 | ||
8231 | /* | |
8232 | * This function implements pieces of two sequences from BSpec: | |
8233 | * - Sequence for display software to disable LCPLL | |
8234 | * - Sequence for display software to allow package C8+ | |
8235 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8236 | * register. Callers should take care of disabling all the display engine | |
8237 | * functions, doing the mode unset, fixing interrupts, etc. | |
8238 | */ | |
6ff58d53 PZ |
8239 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8240 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8241 | { |
8242 | uint32_t val; | |
8243 | ||
8244 | assert_can_disable_lcpll(dev_priv); | |
8245 | ||
8246 | val = I915_READ(LCPLL_CTL); | |
8247 | ||
8248 | if (switch_to_fclk) { | |
8249 | val |= LCPLL_CD_SOURCE_FCLK; | |
8250 | I915_WRITE(LCPLL_CTL, val); | |
8251 | ||
8252 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
8253 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
8254 | DRM_ERROR("Switching to FCLK failed\n"); | |
8255 | ||
8256 | val = I915_READ(LCPLL_CTL); | |
8257 | } | |
8258 | ||
8259 | val |= LCPLL_PLL_DISABLE; | |
8260 | I915_WRITE(LCPLL_CTL, val); | |
8261 | POSTING_READ(LCPLL_CTL); | |
8262 | ||
8263 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
8264 | DRM_ERROR("LCPLL still locked\n"); | |
8265 | ||
9ccd5aeb | 8266 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8267 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8268 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8269 | ndelay(100); |
8270 | ||
9ccd5aeb PZ |
8271 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8272 | 1)) | |
be256dc7 PZ |
8273 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8274 | ||
8275 | if (allow_power_down) { | |
8276 | val = I915_READ(LCPLL_CTL); | |
8277 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8278 | I915_WRITE(LCPLL_CTL, val); | |
8279 | POSTING_READ(LCPLL_CTL); | |
8280 | } | |
8281 | } | |
8282 | ||
8283 | /* | |
8284 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8285 | * source. | |
8286 | */ | |
6ff58d53 | 8287 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8288 | { |
8289 | uint32_t val; | |
8290 | ||
8291 | val = I915_READ(LCPLL_CTL); | |
8292 | ||
8293 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8294 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8295 | return; | |
8296 | ||
a8a8bd54 PZ |
8297 | /* |
8298 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8299 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8300 | */ |
59bad947 | 8301 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8302 | |
be256dc7 PZ |
8303 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8304 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8305 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8306 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8307 | } |
8308 | ||
9ccd5aeb | 8309 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8310 | val |= D_COMP_COMP_FORCE; |
8311 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8312 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8313 | |
8314 | val = I915_READ(LCPLL_CTL); | |
8315 | val &= ~LCPLL_PLL_DISABLE; | |
8316 | I915_WRITE(LCPLL_CTL, val); | |
8317 | ||
8318 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
8319 | DRM_ERROR("LCPLL not locked yet\n"); | |
8320 | ||
8321 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8322 | val = I915_READ(LCPLL_CTL); | |
8323 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8324 | I915_WRITE(LCPLL_CTL, val); | |
8325 | ||
8326 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
8327 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
8328 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
8329 | } | |
215733fa | 8330 | |
59bad947 | 8331 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
8332 | } |
8333 | ||
765dab67 PZ |
8334 | /* |
8335 | * Package states C8 and deeper are really deep PC states that can only be | |
8336 | * reached when all the devices on the system allow it, so even if the graphics | |
8337 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8338 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8339 | * | |
8340 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8341 | * well is disabled and most interrupts are disabled, and these are also | |
8342 | * requirements for runtime PM. When these conditions are met, we manually do | |
8343 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8344 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8345 | * hang the machine. | |
8346 | * | |
8347 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8348 | * the state of some registers, so when we come back from PC8+ we need to | |
8349 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8350 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8351 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8352 | * because of the runtime PM support). | |
8353 | * | |
8354 | * For more, read "Display Sequences for Package C8" on the hardware | |
8355 | * documentation. | |
8356 | */ | |
a14cb6fc | 8357 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8358 | { |
c67a470b PZ |
8359 | struct drm_device *dev = dev_priv->dev; |
8360 | uint32_t val; | |
8361 | ||
c67a470b PZ |
8362 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8363 | ||
c67a470b PZ |
8364 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
8365 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8366 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8367 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8368 | } | |
8369 | ||
8370 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
8371 | hsw_disable_lcpll(dev_priv, true, true); |
8372 | } | |
8373 | ||
a14cb6fc | 8374 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
8375 | { |
8376 | struct drm_device *dev = dev_priv->dev; | |
8377 | uint32_t val; | |
8378 | ||
c67a470b PZ |
8379 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8380 | ||
8381 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
8382 | lpt_init_pch_refclk(dev); |
8383 | ||
8384 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
8385 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
8386 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8387 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8388 | } | |
8389 | ||
8390 | intel_prepare_ddi(dev); | |
c67a470b PZ |
8391 | } |
8392 | ||
190f68c5 ACO |
8393 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8394 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8395 | { |
190f68c5 | 8396 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 8397 | return -EINVAL; |
716c2e55 | 8398 | |
c7653199 | 8399 | crtc->lowfreq_avail = false; |
644cef34 | 8400 | |
c8f7a0db | 8401 | return 0; |
79e53945 JB |
8402 | } |
8403 | ||
96b7dfb7 S |
8404 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8405 | enum port port, | |
5cec258b | 8406 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8407 | { |
3148ade7 | 8408 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
8409 | |
8410 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
8411 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
8412 | ||
8413 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
8414 | case SKL_DPLL0: |
8415 | /* | |
8416 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
8417 | * of the shared DPLL framework and thus needs to be read out | |
8418 | * separately | |
8419 | */ | |
8420 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8421 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8422 | break; | |
96b7dfb7 S |
8423 | case SKL_DPLL1: |
8424 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8425 | break; | |
8426 | case SKL_DPLL2: | |
8427 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8428 | break; | |
8429 | case SKL_DPLL3: | |
8430 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8431 | break; | |
96b7dfb7 S |
8432 | } |
8433 | } | |
8434 | ||
7d2c8175 DL |
8435 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8436 | enum port port, | |
5cec258b | 8437 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
8438 | { |
8439 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8440 | ||
8441 | switch (pipe_config->ddi_pll_sel) { | |
8442 | case PORT_CLK_SEL_WRPLL1: | |
8443 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8444 | break; | |
8445 | case PORT_CLK_SEL_WRPLL2: | |
8446 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8447 | break; | |
8448 | } | |
8449 | } | |
8450 | ||
26804afd | 8451 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 8452 | struct intel_crtc_state *pipe_config) |
26804afd DV |
8453 | { |
8454 | struct drm_device *dev = crtc->base.dev; | |
8455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8456 | struct intel_shared_dpll *pll; |
26804afd DV |
8457 | enum port port; |
8458 | uint32_t tmp; | |
8459 | ||
8460 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8461 | ||
8462 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8463 | ||
96b7dfb7 S |
8464 | if (IS_SKYLAKE(dev)) |
8465 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8466 | else | |
8467 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8468 | |
d452c5b6 DV |
8469 | if (pipe_config->shared_dpll >= 0) { |
8470 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8471 | ||
8472 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8473 | &pipe_config->dpll_hw_state)); | |
8474 | } | |
8475 | ||
26804afd DV |
8476 | /* |
8477 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8478 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8479 | * the PCH transcoder is on. | |
8480 | */ | |
ca370455 DL |
8481 | if (INTEL_INFO(dev)->gen < 9 && |
8482 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8483 | pipe_config->has_pch_encoder = true; |
8484 | ||
8485 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8486 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8487 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8488 | ||
8489 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8490 | } | |
8491 | } | |
8492 | ||
0e8ffe1b | 8493 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8494 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8495 | { |
8496 | struct drm_device *dev = crtc->base.dev; | |
8497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8498 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8499 | uint32_t tmp; |
8500 | ||
f458ebbc | 8501 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8502 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8503 | return false; | |
8504 | ||
e143a21c | 8505 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8506 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8507 | ||
eccb140b DV |
8508 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8509 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8510 | enum pipe trans_edp_pipe; | |
8511 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8512 | default: | |
8513 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8514 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8515 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8516 | trans_edp_pipe = PIPE_A; | |
8517 | break; | |
8518 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8519 | trans_edp_pipe = PIPE_B; | |
8520 | break; | |
8521 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8522 | trans_edp_pipe = PIPE_C; | |
8523 | break; | |
8524 | } | |
8525 | ||
8526 | if (trans_edp_pipe == crtc->pipe) | |
8527 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8528 | } | |
8529 | ||
f458ebbc | 8530 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8531 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8532 | return false; |
8533 | ||
eccb140b | 8534 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8535 | if (!(tmp & PIPECONF_ENABLE)) |
8536 | return false; | |
8537 | ||
26804afd | 8538 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8539 | |
1bd1bd80 DV |
8540 | intel_get_pipe_timings(crtc, pipe_config); |
8541 | ||
2fa2fe9a | 8542 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8543 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8544 | if (IS_SKYLAKE(dev)) | |
8545 | skylake_get_pfit_config(crtc, pipe_config); | |
8546 | else | |
8547 | ironlake_get_pfit_config(crtc, pipe_config); | |
8548 | } | |
88adfff1 | 8549 | |
e59150dc JB |
8550 | if (IS_HASWELL(dev)) |
8551 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8552 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8553 | |
ebb69c95 CT |
8554 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8555 | pipe_config->pixel_multiplier = | |
8556 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8557 | } else { | |
8558 | pipe_config->pixel_multiplier = 1; | |
8559 | } | |
6c49f241 | 8560 | |
0e8ffe1b DV |
8561 | return true; |
8562 | } | |
8563 | ||
560b85bb CW |
8564 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8565 | { | |
8566 | struct drm_device *dev = crtc->dev; | |
8567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8569 | uint32_t cntl = 0, size = 0; |
560b85bb | 8570 | |
dc41c154 | 8571 | if (base) { |
3dd512fb MR |
8572 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
8573 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
8574 | unsigned int stride = roundup_pow_of_two(width) * 4; |
8575 | ||
8576 | switch (stride) { | |
8577 | default: | |
8578 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8579 | width, stride); | |
8580 | stride = 256; | |
8581 | /* fallthrough */ | |
8582 | case 256: | |
8583 | case 512: | |
8584 | case 1024: | |
8585 | case 2048: | |
8586 | break; | |
4b0e333e CW |
8587 | } |
8588 | ||
dc41c154 VS |
8589 | cntl |= CURSOR_ENABLE | |
8590 | CURSOR_GAMMA_ENABLE | | |
8591 | CURSOR_FORMAT_ARGB | | |
8592 | CURSOR_STRIDE(stride); | |
8593 | ||
8594 | size = (height << 12) | width; | |
4b0e333e | 8595 | } |
560b85bb | 8596 | |
dc41c154 VS |
8597 | if (intel_crtc->cursor_cntl != 0 && |
8598 | (intel_crtc->cursor_base != base || | |
8599 | intel_crtc->cursor_size != size || | |
8600 | intel_crtc->cursor_cntl != cntl)) { | |
8601 | /* On these chipsets we can only modify the base/size/stride | |
8602 | * whilst the cursor is disabled. | |
8603 | */ | |
8604 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8605 | POSTING_READ(_CURACNTR); |
dc41c154 | 8606 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8607 | } |
560b85bb | 8608 | |
99d1f387 | 8609 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8610 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8611 | intel_crtc->cursor_base = base; |
8612 | } | |
4726e0b0 | 8613 | |
dc41c154 VS |
8614 | if (intel_crtc->cursor_size != size) { |
8615 | I915_WRITE(CURSIZE, size); | |
8616 | intel_crtc->cursor_size = size; | |
4b0e333e | 8617 | } |
560b85bb | 8618 | |
4b0e333e | 8619 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8620 | I915_WRITE(_CURACNTR, cntl); |
8621 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8622 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8623 | } |
560b85bb CW |
8624 | } |
8625 | ||
560b85bb | 8626 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8627 | { |
8628 | struct drm_device *dev = crtc->dev; | |
8629 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8631 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8632 | uint32_t cntl; |
8633 | ||
8634 | cntl = 0; | |
8635 | if (base) { | |
8636 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 8637 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
8638 | case 64: |
8639 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8640 | break; | |
8641 | case 128: | |
8642 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8643 | break; | |
8644 | case 256: | |
8645 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8646 | break; | |
8647 | default: | |
3dd512fb | 8648 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 8649 | return; |
65a21cd6 | 8650 | } |
4b0e333e | 8651 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8652 | |
8653 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8654 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8655 | } |
65a21cd6 | 8656 | |
8e7d688b | 8657 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
8658 | cntl |= CURSOR_ROTATE_180; |
8659 | ||
4b0e333e CW |
8660 | if (intel_crtc->cursor_cntl != cntl) { |
8661 | I915_WRITE(CURCNTR(pipe), cntl); | |
8662 | POSTING_READ(CURCNTR(pipe)); | |
8663 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8664 | } |
4b0e333e | 8665 | |
65a21cd6 | 8666 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8667 | I915_WRITE(CURBASE(pipe), base); |
8668 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8669 | |
8670 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8671 | } |
8672 | ||
cda4b7d3 | 8673 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8674 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8675 | bool on) | |
cda4b7d3 CW |
8676 | { |
8677 | struct drm_device *dev = crtc->dev; | |
8678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8680 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8681 | int x = crtc->cursor_x; |
8682 | int y = crtc->cursor_y; | |
d6e4db15 | 8683 | u32 base = 0, pos = 0; |
cda4b7d3 | 8684 | |
d6e4db15 | 8685 | if (on) |
cda4b7d3 | 8686 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8687 | |
6e3c9717 | 8688 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
8689 | base = 0; |
8690 | ||
6e3c9717 | 8691 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
8692 | base = 0; |
8693 | ||
8694 | if (x < 0) { | |
3dd512fb | 8695 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
8696 | base = 0; |
8697 | ||
8698 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8699 | x = -x; | |
8700 | } | |
8701 | pos |= x << CURSOR_X_SHIFT; | |
8702 | ||
8703 | if (y < 0) { | |
3dd512fb | 8704 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
8705 | base = 0; |
8706 | ||
8707 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8708 | y = -y; | |
8709 | } | |
8710 | pos |= y << CURSOR_Y_SHIFT; | |
8711 | ||
4b0e333e | 8712 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8713 | return; |
8714 | ||
5efb3e28 VS |
8715 | I915_WRITE(CURPOS(pipe), pos); |
8716 | ||
4398ad45 VS |
8717 | /* ILK+ do this automagically */ |
8718 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 8719 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
8720 | base += (intel_crtc->base.cursor->state->crtc_h * |
8721 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
8722 | } |
8723 | ||
8ac54669 | 8724 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8725 | i845_update_cursor(crtc, base); |
8726 | else | |
8727 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8728 | } |
8729 | ||
dc41c154 VS |
8730 | static bool cursor_size_ok(struct drm_device *dev, |
8731 | uint32_t width, uint32_t height) | |
8732 | { | |
8733 | if (width == 0 || height == 0) | |
8734 | return false; | |
8735 | ||
8736 | /* | |
8737 | * 845g/865g are special in that they are only limited by | |
8738 | * the width of their cursors, the height is arbitrary up to | |
8739 | * the precision of the register. Everything else requires | |
8740 | * square cursors, limited to a few power-of-two sizes. | |
8741 | */ | |
8742 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8743 | if ((width & 63) != 0) | |
8744 | return false; | |
8745 | ||
8746 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8747 | return false; | |
8748 | ||
8749 | if (height > 1023) | |
8750 | return false; | |
8751 | } else { | |
8752 | switch (width | height) { | |
8753 | case 256: | |
8754 | case 128: | |
8755 | if (IS_GEN2(dev)) | |
8756 | return false; | |
8757 | case 64: | |
8758 | break; | |
8759 | default: | |
8760 | return false; | |
8761 | } | |
8762 | } | |
8763 | ||
8764 | return true; | |
8765 | } | |
8766 | ||
79e53945 | 8767 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8768 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8769 | { |
7203425a | 8770 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8772 | |
7203425a | 8773 | for (i = start; i < end; i++) { |
79e53945 JB |
8774 | intel_crtc->lut_r[i] = red[i] >> 8; |
8775 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8776 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8777 | } | |
8778 | ||
8779 | intel_crtc_load_lut(crtc); | |
8780 | } | |
8781 | ||
79e53945 JB |
8782 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8783 | static struct drm_display_mode load_detect_mode = { | |
8784 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8785 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8786 | }; | |
8787 | ||
a8bb6818 DV |
8788 | struct drm_framebuffer * |
8789 | __intel_framebuffer_create(struct drm_device *dev, | |
8790 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8791 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8792 | { |
8793 | struct intel_framebuffer *intel_fb; | |
8794 | int ret; | |
8795 | ||
8796 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8797 | if (!intel_fb) { | |
6ccb81f2 | 8798 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8799 | return ERR_PTR(-ENOMEM); |
8800 | } | |
8801 | ||
8802 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8803 | if (ret) |
8804 | goto err; | |
d2dff872 CW |
8805 | |
8806 | return &intel_fb->base; | |
dd4916c5 | 8807 | err: |
6ccb81f2 | 8808 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8809 | kfree(intel_fb); |
8810 | ||
8811 | return ERR_PTR(ret); | |
d2dff872 CW |
8812 | } |
8813 | ||
b5ea642a | 8814 | static struct drm_framebuffer * |
a8bb6818 DV |
8815 | intel_framebuffer_create(struct drm_device *dev, |
8816 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8817 | struct drm_i915_gem_object *obj) | |
8818 | { | |
8819 | struct drm_framebuffer *fb; | |
8820 | int ret; | |
8821 | ||
8822 | ret = i915_mutex_lock_interruptible(dev); | |
8823 | if (ret) | |
8824 | return ERR_PTR(ret); | |
8825 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8826 | mutex_unlock(&dev->struct_mutex); | |
8827 | ||
8828 | return fb; | |
8829 | } | |
8830 | ||
d2dff872 CW |
8831 | static u32 |
8832 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8833 | { | |
8834 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8835 | return ALIGN(pitch, 64); | |
8836 | } | |
8837 | ||
8838 | static u32 | |
8839 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8840 | { | |
8841 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8842 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8843 | } |
8844 | ||
8845 | static struct drm_framebuffer * | |
8846 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8847 | struct drm_display_mode *mode, | |
8848 | int depth, int bpp) | |
8849 | { | |
8850 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8851 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8852 | |
8853 | obj = i915_gem_alloc_object(dev, | |
8854 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8855 | if (obj == NULL) | |
8856 | return ERR_PTR(-ENOMEM); | |
8857 | ||
8858 | mode_cmd.width = mode->hdisplay; | |
8859 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8860 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8861 | bpp); | |
5ca0c34a | 8862 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8863 | |
8864 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8865 | } | |
8866 | ||
8867 | static struct drm_framebuffer * | |
8868 | mode_fits_in_fbdev(struct drm_device *dev, | |
8869 | struct drm_display_mode *mode) | |
8870 | { | |
4520f53a | 8871 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8872 | struct drm_i915_private *dev_priv = dev->dev_private; |
8873 | struct drm_i915_gem_object *obj; | |
8874 | struct drm_framebuffer *fb; | |
8875 | ||
4c0e5528 | 8876 | if (!dev_priv->fbdev) |
d2dff872 CW |
8877 | return NULL; |
8878 | ||
4c0e5528 | 8879 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8880 | return NULL; |
8881 | ||
4c0e5528 DV |
8882 | obj = dev_priv->fbdev->fb->obj; |
8883 | BUG_ON(!obj); | |
8884 | ||
8bcd4553 | 8885 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8886 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8887 | fb->bits_per_pixel)) | |
d2dff872 CW |
8888 | return NULL; |
8889 | ||
01f2c773 | 8890 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8891 | return NULL; |
8892 | ||
8893 | return fb; | |
4520f53a DV |
8894 | #else |
8895 | return NULL; | |
8896 | #endif | |
d2dff872 CW |
8897 | } |
8898 | ||
d2434ab7 | 8899 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8900 | struct drm_display_mode *mode, |
51fd371b RC |
8901 | struct intel_load_detect_pipe *old, |
8902 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8903 | { |
8904 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8905 | struct intel_encoder *intel_encoder = |
8906 | intel_attached_encoder(connector); | |
79e53945 | 8907 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8908 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8909 | struct drm_crtc *crtc = NULL; |
8910 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8911 | struct drm_framebuffer *fb; |
51fd371b | 8912 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 8913 | struct drm_atomic_state *state = NULL; |
944b0c76 | 8914 | struct drm_connector_state *connector_state; |
51fd371b | 8915 | int ret, i = -1; |
79e53945 | 8916 | |
d2dff872 | 8917 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8918 | connector->base.id, connector->name, |
8e329a03 | 8919 | encoder->base.id, encoder->name); |
d2dff872 | 8920 | |
51fd371b RC |
8921 | retry: |
8922 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8923 | if (ret) | |
8924 | goto fail_unlock; | |
6e9f798d | 8925 | |
79e53945 JB |
8926 | /* |
8927 | * Algorithm gets a little messy: | |
7a5e4805 | 8928 | * |
79e53945 JB |
8929 | * - if the connector already has an assigned crtc, use it (but make |
8930 | * sure it's on first) | |
7a5e4805 | 8931 | * |
79e53945 JB |
8932 | * - try to find the first unused crtc that can drive this connector, |
8933 | * and use that if we find one | |
79e53945 JB |
8934 | */ |
8935 | ||
8936 | /* See if we already have a CRTC for this connector */ | |
8937 | if (encoder->crtc) { | |
8938 | crtc = encoder->crtc; | |
8261b191 | 8939 | |
51fd371b | 8940 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8941 | if (ret) |
8942 | goto fail_unlock; | |
8943 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8944 | if (ret) |
8945 | goto fail_unlock; | |
7b24056b | 8946 | |
24218aac | 8947 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8948 | old->load_detect_temp = false; |
8949 | ||
8950 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8951 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8952 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8953 | |
7173188d | 8954 | return true; |
79e53945 JB |
8955 | } |
8956 | ||
8957 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8958 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8959 | i++; |
8960 | if (!(encoder->possible_crtcs & (1 << i))) | |
8961 | continue; | |
83d65738 | 8962 | if (possible_crtc->state->enable) |
a459249c VS |
8963 | continue; |
8964 | /* This can occur when applying the pipe A quirk on resume. */ | |
8965 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8966 | continue; | |
8967 | ||
8968 | crtc = possible_crtc; | |
8969 | break; | |
79e53945 JB |
8970 | } |
8971 | ||
8972 | /* | |
8973 | * If we didn't find an unused CRTC, don't use any. | |
8974 | */ | |
8975 | if (!crtc) { | |
7173188d | 8976 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8977 | goto fail_unlock; |
79e53945 JB |
8978 | } |
8979 | ||
51fd371b RC |
8980 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8981 | if (ret) | |
4d02e2de DV |
8982 | goto fail_unlock; |
8983 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8984 | if (ret) | |
51fd371b | 8985 | goto fail_unlock; |
fc303101 DV |
8986 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8987 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8988 | |
8989 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 8990 | intel_crtc->new_enabled = true; |
6e3c9717 | 8991 | intel_crtc->new_config = intel_crtc->config; |
24218aac | 8992 | old->dpms_mode = connector->dpms; |
8261b191 | 8993 | old->load_detect_temp = true; |
d2dff872 | 8994 | old->release_fb = NULL; |
79e53945 | 8995 | |
83a57153 ACO |
8996 | state = drm_atomic_state_alloc(dev); |
8997 | if (!state) | |
8998 | return false; | |
8999 | ||
9000 | state->acquire_ctx = ctx; | |
9001 | ||
944b0c76 ACO |
9002 | connector_state = drm_atomic_get_connector_state(state, connector); |
9003 | if (IS_ERR(connector_state)) { | |
9004 | ret = PTR_ERR(connector_state); | |
9005 | goto fail; | |
9006 | } | |
9007 | ||
9008 | connector_state->crtc = crtc; | |
9009 | connector_state->best_encoder = &intel_encoder->base; | |
9010 | ||
6492711d CW |
9011 | if (!mode) |
9012 | mode = &load_detect_mode; | |
79e53945 | 9013 | |
d2dff872 CW |
9014 | /* We need a framebuffer large enough to accommodate all accesses |
9015 | * that the plane may generate whilst we perform load detection. | |
9016 | * We can not rely on the fbcon either being present (we get called | |
9017 | * during its initialisation to detect all boot displays, or it may | |
9018 | * not even exist) or that it is large enough to satisfy the | |
9019 | * requested mode. | |
9020 | */ | |
94352cf9 DV |
9021 | fb = mode_fits_in_fbdev(dev, mode); |
9022 | if (fb == NULL) { | |
d2dff872 | 9023 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9024 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9025 | old->release_fb = fb; | |
d2dff872 CW |
9026 | } else |
9027 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9028 | if (IS_ERR(fb)) { |
d2dff872 | 9029 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9030 | goto fail; |
79e53945 | 9031 | } |
79e53945 | 9032 | |
83a57153 | 9033 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9034 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9035 | if (old->release_fb) |
9036 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9037 | goto fail; |
79e53945 | 9038 | } |
9128b040 | 9039 | crtc->primary->crtc = crtc; |
7173188d | 9040 | |
79e53945 | 9041 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9042 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9043 | return true; |
412b61d8 VS |
9044 | |
9045 | fail: | |
83d65738 | 9046 | intel_crtc->new_enabled = crtc->state->enable; |
412b61d8 | 9047 | if (intel_crtc->new_enabled) |
6e3c9717 | 9048 | intel_crtc->new_config = intel_crtc->config; |
412b61d8 VS |
9049 | else |
9050 | intel_crtc->new_config = NULL; | |
51fd371b | 9051 | fail_unlock: |
83a57153 ACO |
9052 | if (state) { |
9053 | drm_atomic_state_free(state); | |
9054 | state = NULL; | |
9055 | } | |
9056 | ||
51fd371b RC |
9057 | if (ret == -EDEADLK) { |
9058 | drm_modeset_backoff(ctx); | |
9059 | goto retry; | |
9060 | } | |
9061 | ||
412b61d8 | 9062 | return false; |
79e53945 JB |
9063 | } |
9064 | ||
d2434ab7 | 9065 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9066 | struct intel_load_detect_pipe *old, |
9067 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9068 | { |
83a57153 | 9069 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9070 | struct intel_encoder *intel_encoder = |
9071 | intel_attached_encoder(connector); | |
4ef69c7a | 9072 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9073 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9075 | struct drm_atomic_state *state; |
944b0c76 | 9076 | struct drm_connector_state *connector_state; |
79e53945 | 9077 | |
d2dff872 | 9078 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9079 | connector->base.id, connector->name, |
8e329a03 | 9080 | encoder->base.id, encoder->name); |
d2dff872 | 9081 | |
8261b191 | 9082 | if (old->load_detect_temp) { |
83a57153 | 9083 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9084 | if (!state) |
9085 | goto fail; | |
83a57153 ACO |
9086 | |
9087 | state->acquire_ctx = ctx; | |
9088 | ||
944b0c76 ACO |
9089 | connector_state = drm_atomic_get_connector_state(state, connector); |
9090 | if (IS_ERR(connector_state)) | |
9091 | goto fail; | |
9092 | ||
fc303101 DV |
9093 | to_intel_connector(connector)->new_encoder = NULL; |
9094 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
9095 | intel_crtc->new_enabled = false; |
9096 | intel_crtc->new_config = NULL; | |
944b0c76 ACO |
9097 | |
9098 | connector_state->best_encoder = NULL; | |
9099 | connector_state->crtc = NULL; | |
9100 | ||
83a57153 ACO |
9101 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9102 | ||
9103 | drm_atomic_state_free(state); | |
d2dff872 | 9104 | |
36206361 DV |
9105 | if (old->release_fb) { |
9106 | drm_framebuffer_unregister_private(old->release_fb); | |
9107 | drm_framebuffer_unreference(old->release_fb); | |
9108 | } | |
d2dff872 | 9109 | |
0622a53c | 9110 | return; |
79e53945 JB |
9111 | } |
9112 | ||
c751ce4f | 9113 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9114 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9115 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9116 | |
9117 | return; | |
9118 | fail: | |
9119 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9120 | drm_atomic_state_free(state); | |
79e53945 JB |
9121 | } |
9122 | ||
da4a1efa | 9123 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9124 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9125 | { |
9126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9127 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9128 | ||
9129 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9130 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9131 | else if (HAS_PCH_SPLIT(dev)) |
9132 | return 120000; | |
9133 | else if (!IS_GEN2(dev)) | |
9134 | return 96000; | |
9135 | else | |
9136 | return 48000; | |
9137 | } | |
9138 | ||
79e53945 | 9139 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9140 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9141 | struct intel_crtc_state *pipe_config) |
79e53945 | 9142 | { |
f1f644dc | 9143 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9144 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9145 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9146 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9147 | u32 fp; |
9148 | intel_clock_t clock; | |
da4a1efa | 9149 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9150 | |
9151 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9152 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9153 | else |
293623f7 | 9154 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9155 | |
9156 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9157 | if (IS_PINEVIEW(dev)) { |
9158 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9159 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9160 | } else { |
9161 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9162 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9163 | } | |
9164 | ||
a6c45cf0 | 9165 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9166 | if (IS_PINEVIEW(dev)) |
9167 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9168 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9169 | else |
9170 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9171 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9172 | ||
9173 | switch (dpll & DPLL_MODE_MASK) { | |
9174 | case DPLLB_MODE_DAC_SERIAL: | |
9175 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9176 | 5 : 10; | |
9177 | break; | |
9178 | case DPLLB_MODE_LVDS: | |
9179 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9180 | 7 : 14; | |
9181 | break; | |
9182 | default: | |
28c97730 | 9183 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9184 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9185 | return; |
79e53945 JB |
9186 | } |
9187 | ||
ac58c3f0 | 9188 | if (IS_PINEVIEW(dev)) |
da4a1efa | 9189 | pineview_clock(refclk, &clock); |
ac58c3f0 | 9190 | else |
da4a1efa | 9191 | i9xx_clock(refclk, &clock); |
79e53945 | 9192 | } else { |
0fb58223 | 9193 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9194 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9195 | |
9196 | if (is_lvds) { | |
9197 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9198 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9199 | |
9200 | if (lvds & LVDS_CLKB_POWER_UP) | |
9201 | clock.p2 = 7; | |
9202 | else | |
9203 | clock.p2 = 14; | |
79e53945 JB |
9204 | } else { |
9205 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9206 | clock.p1 = 2; | |
9207 | else { | |
9208 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9209 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9210 | } | |
9211 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9212 | clock.p2 = 4; | |
9213 | else | |
9214 | clock.p2 = 2; | |
79e53945 | 9215 | } |
da4a1efa VS |
9216 | |
9217 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
9218 | } |
9219 | ||
18442d08 VS |
9220 | /* |
9221 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9222 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9223 | * encoder's get_config() function. |
9224 | */ | |
9225 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
9226 | } |
9227 | ||
6878da05 VS |
9228 | int intel_dotclock_calculate(int link_freq, |
9229 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9230 | { |
f1f644dc JB |
9231 | /* |
9232 | * The calculation for the data clock is: | |
1041a02f | 9233 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9234 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9235 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9236 | * |
9237 | * and the link clock is simpler: | |
1041a02f | 9238 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9239 | */ |
9240 | ||
6878da05 VS |
9241 | if (!m_n->link_n) |
9242 | return 0; | |
f1f644dc | 9243 | |
6878da05 VS |
9244 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9245 | } | |
f1f644dc | 9246 | |
18442d08 | 9247 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9248 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
9249 | { |
9250 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 9251 | |
18442d08 VS |
9252 | /* read out port_clock from the DPLL */ |
9253 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9254 | |
f1f644dc | 9255 | /* |
18442d08 | 9256 | * This value does not include pixel_multiplier. |
241bfc38 | 9257 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
9258 | * agree once we know their relationship in the encoder's |
9259 | * get_config() function. | |
79e53945 | 9260 | */ |
2d112de7 | 9261 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
9262 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
9263 | &pipe_config->fdi_m_n); | |
79e53945 JB |
9264 | } |
9265 | ||
9266 | /** Returns the currently programmed mode of the given pipe. */ | |
9267 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9268 | struct drm_crtc *crtc) | |
9269 | { | |
548f245b | 9270 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 9271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9272 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9273 | struct drm_display_mode *mode; |
5cec258b | 9274 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
9275 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9276 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9277 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9278 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9279 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9280 | |
9281 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9282 | if (!mode) | |
9283 | return NULL; | |
9284 | ||
f1f644dc JB |
9285 | /* |
9286 | * Construct a pipe_config sufficient for getting the clock info | |
9287 | * back out of crtc_clock_get. | |
9288 | * | |
9289 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9290 | * to use a real value here instead. | |
9291 | */ | |
293623f7 | 9292 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9293 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9294 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9295 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9296 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9297 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9298 | ||
773ae034 | 9299 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9300 | mode->hdisplay = (htot & 0xffff) + 1; |
9301 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9302 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9303 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9304 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9305 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9306 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9307 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9308 | ||
9309 | drm_mode_set_name(mode); | |
79e53945 JB |
9310 | |
9311 | return mode; | |
9312 | } | |
9313 | ||
652c393a JB |
9314 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
9315 | { | |
9316 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9317 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9319 | |
baff296c | 9320 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9321 | return; |
9322 | ||
9323 | if (!dev_priv->lvds_downclock_avail) | |
9324 | return; | |
9325 | ||
9326 | /* | |
9327 | * Since this is called by a timer, we should never get here in | |
9328 | * the manual case. | |
9329 | */ | |
9330 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9331 | int pipe = intel_crtc->pipe; |
9332 | int dpll_reg = DPLL(pipe); | |
9333 | int dpll; | |
f6e5b160 | 9334 | |
44d98a61 | 9335 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9336 | |
8ac5a6d5 | 9337 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9338 | |
dc257cf1 | 9339 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9340 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9341 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9342 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9343 | dpll = I915_READ(dpll_reg); |
9344 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9345 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9346 | } |
9347 | ||
9348 | } | |
9349 | ||
f047e395 CW |
9350 | void intel_mark_busy(struct drm_device *dev) |
9351 | { | |
c67a470b PZ |
9352 | struct drm_i915_private *dev_priv = dev->dev_private; |
9353 | ||
f62a0076 CW |
9354 | if (dev_priv->mm.busy) |
9355 | return; | |
9356 | ||
43694d69 | 9357 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9358 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
9359 | if (INTEL_INFO(dev)->gen >= 6) |
9360 | gen6_rps_busy(dev_priv); | |
f62a0076 | 9361 | dev_priv->mm.busy = true; |
f047e395 CW |
9362 | } |
9363 | ||
9364 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9365 | { |
c67a470b | 9366 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9367 | struct drm_crtc *crtc; |
652c393a | 9368 | |
f62a0076 CW |
9369 | if (!dev_priv->mm.busy) |
9370 | return; | |
9371 | ||
9372 | dev_priv->mm.busy = false; | |
9373 | ||
70e1e0ec | 9374 | for_each_crtc(dev, crtc) { |
f4510a27 | 9375 | if (!crtc->primary->fb) |
652c393a JB |
9376 | continue; |
9377 | ||
725a5b54 | 9378 | intel_decrease_pllclock(crtc); |
652c393a | 9379 | } |
b29c19b6 | 9380 | |
3d13ef2e | 9381 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9382 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 9383 | |
43694d69 | 9384 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9385 | } |
9386 | ||
f5de6e07 ACO |
9387 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
9388 | struct intel_crtc_state *crtc_state) | |
9389 | { | |
9390 | kfree(crtc->config); | |
9391 | crtc->config = crtc_state; | |
16f3f658 | 9392 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
9393 | } |
9394 | ||
79e53945 JB |
9395 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9396 | { | |
9397 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9398 | struct drm_device *dev = crtc->dev; |
9399 | struct intel_unpin_work *work; | |
67e77c5a | 9400 | |
5e2d7afc | 9401 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
9402 | work = intel_crtc->unpin_work; |
9403 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 9404 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
9405 | |
9406 | if (work) { | |
9407 | cancel_work_sync(&work->work); | |
9408 | kfree(work); | |
9409 | } | |
79e53945 | 9410 | |
f5de6e07 | 9411 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 9412 | drm_crtc_cleanup(crtc); |
67e77c5a | 9413 | |
79e53945 JB |
9414 | kfree(intel_crtc); |
9415 | } | |
9416 | ||
6b95a207 KH |
9417 | static void intel_unpin_work_fn(struct work_struct *__work) |
9418 | { | |
9419 | struct intel_unpin_work *work = | |
9420 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9421 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9422 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9423 | |
b4a98e57 | 9424 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 9425 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 9426 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 9427 | |
7ff0ebcc | 9428 | intel_fbc_update(dev); |
f06cc1b9 JH |
9429 | |
9430 | if (work->flip_queued_req) | |
146d84f0 | 9431 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
9432 | mutex_unlock(&dev->struct_mutex); |
9433 | ||
f99d7069 | 9434 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 9435 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 9436 | |
b4a98e57 CW |
9437 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9438 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9439 | ||
6b95a207 KH |
9440 | kfree(work); |
9441 | } | |
9442 | ||
1afe3e9d | 9443 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9444 | struct drm_crtc *crtc) |
6b95a207 | 9445 | { |
6b95a207 KH |
9446 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9447 | struct intel_unpin_work *work; | |
6b95a207 KH |
9448 | unsigned long flags; |
9449 | ||
9450 | /* Ignore early vblank irqs */ | |
9451 | if (intel_crtc == NULL) | |
9452 | return; | |
9453 | ||
f326038a DV |
9454 | /* |
9455 | * This is called both by irq handlers and the reset code (to complete | |
9456 | * lost pageflips) so needs the full irqsave spinlocks. | |
9457 | */ | |
6b95a207 KH |
9458 | spin_lock_irqsave(&dev->event_lock, flags); |
9459 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9460 | |
9461 | /* Ensure we don't miss a work->pending update ... */ | |
9462 | smp_rmb(); | |
9463 | ||
9464 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9465 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9466 | return; | |
9467 | } | |
9468 | ||
d6bbafa1 | 9469 | page_flip_completed(intel_crtc); |
0af7e4df | 9470 | |
6b95a207 | 9471 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9472 | } |
9473 | ||
1afe3e9d JB |
9474 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9475 | { | |
fbee40df | 9476 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9477 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9478 | ||
49b14a5c | 9479 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9480 | } |
9481 | ||
9482 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9483 | { | |
fbee40df | 9484 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9485 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9486 | ||
49b14a5c | 9487 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9488 | } |
9489 | ||
75f7f3ec VS |
9490 | /* Is 'a' after or equal to 'b'? */ |
9491 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9492 | { | |
9493 | return !((a - b) & 0x80000000); | |
9494 | } | |
9495 | ||
9496 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9497 | { | |
9498 | struct drm_device *dev = crtc->base.dev; | |
9499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9500 | ||
bdfa7542 VS |
9501 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9502 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9503 | return true; | |
9504 | ||
75f7f3ec VS |
9505 | /* |
9506 | * The relevant registers doen't exist on pre-ctg. | |
9507 | * As the flip done interrupt doesn't trigger for mmio | |
9508 | * flips on gmch platforms, a flip count check isn't | |
9509 | * really needed there. But since ctg has the registers, | |
9510 | * include it in the check anyway. | |
9511 | */ | |
9512 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9513 | return true; | |
9514 | ||
9515 | /* | |
9516 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9517 | * used the same base address. In that case the mmio flip might | |
9518 | * have completed, but the CS hasn't even executed the flip yet. | |
9519 | * | |
9520 | * A flip count check isn't enough as the CS might have updated | |
9521 | * the base address just after start of vblank, but before we | |
9522 | * managed to process the interrupt. This means we'd complete the | |
9523 | * CS flip too soon. | |
9524 | * | |
9525 | * Combining both checks should get us a good enough result. It may | |
9526 | * still happen that the CS flip has been executed, but has not | |
9527 | * yet actually completed. But in case the base address is the same | |
9528 | * anyway, we don't really care. | |
9529 | */ | |
9530 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9531 | crtc->unpin_work->gtt_offset && | |
9532 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9533 | crtc->unpin_work->flip_count); | |
9534 | } | |
9535 | ||
6b95a207 KH |
9536 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9537 | { | |
fbee40df | 9538 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9539 | struct intel_crtc *intel_crtc = |
9540 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9541 | unsigned long flags; | |
9542 | ||
f326038a DV |
9543 | |
9544 | /* | |
9545 | * This is called both by irq handlers and the reset code (to complete | |
9546 | * lost pageflips) so needs the full irqsave spinlocks. | |
9547 | * | |
9548 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9549 | * generate a page-flip completion irq, i.e. every modeset |
9550 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9551 | */ | |
6b95a207 | 9552 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9553 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9554 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9555 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9556 | } | |
9557 | ||
eba905b2 | 9558 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9559 | { |
9560 | /* Ensure that the work item is consistent when activating it ... */ | |
9561 | smp_wmb(); | |
9562 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9563 | /* and that it is marked active as soon as the irq could fire. */ | |
9564 | smp_wmb(); | |
9565 | } | |
9566 | ||
8c9f3aaf JB |
9567 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9568 | struct drm_crtc *crtc, | |
9569 | struct drm_framebuffer *fb, | |
ed8d1975 | 9570 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9571 | struct intel_engine_cs *ring, |
ed8d1975 | 9572 | uint32_t flags) |
8c9f3aaf | 9573 | { |
8c9f3aaf | 9574 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9575 | u32 flip_mask; |
9576 | int ret; | |
9577 | ||
6d90c952 | 9578 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9579 | if (ret) |
4fa62c89 | 9580 | return ret; |
8c9f3aaf JB |
9581 | |
9582 | /* Can't queue multiple flips, so wait for the previous | |
9583 | * one to finish before executing the next. | |
9584 | */ | |
9585 | if (intel_crtc->plane) | |
9586 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9587 | else | |
9588 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9589 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9590 | intel_ring_emit(ring, MI_NOOP); | |
9591 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9592 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9593 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9594 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9595 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9596 | |
9597 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9598 | __intel_ring_advance(ring); |
83d4092b | 9599 | return 0; |
8c9f3aaf JB |
9600 | } |
9601 | ||
9602 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9603 | struct drm_crtc *crtc, | |
9604 | struct drm_framebuffer *fb, | |
ed8d1975 | 9605 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9606 | struct intel_engine_cs *ring, |
ed8d1975 | 9607 | uint32_t flags) |
8c9f3aaf | 9608 | { |
8c9f3aaf | 9609 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9610 | u32 flip_mask; |
9611 | int ret; | |
9612 | ||
6d90c952 | 9613 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9614 | if (ret) |
4fa62c89 | 9615 | return ret; |
8c9f3aaf JB |
9616 | |
9617 | if (intel_crtc->plane) | |
9618 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9619 | else | |
9620 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9621 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9622 | intel_ring_emit(ring, MI_NOOP); | |
9623 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9624 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9625 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9626 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9627 | intel_ring_emit(ring, MI_NOOP); |
9628 | ||
e7d841ca | 9629 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9630 | __intel_ring_advance(ring); |
83d4092b | 9631 | return 0; |
8c9f3aaf JB |
9632 | } |
9633 | ||
9634 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9635 | struct drm_crtc *crtc, | |
9636 | struct drm_framebuffer *fb, | |
ed8d1975 | 9637 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9638 | struct intel_engine_cs *ring, |
ed8d1975 | 9639 | uint32_t flags) |
8c9f3aaf JB |
9640 | { |
9641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9643 | uint32_t pf, pipesrc; | |
9644 | int ret; | |
9645 | ||
6d90c952 | 9646 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9647 | if (ret) |
4fa62c89 | 9648 | return ret; |
8c9f3aaf JB |
9649 | |
9650 | /* i965+ uses the linear or tiled offsets from the | |
9651 | * Display Registers (which do not change across a page-flip) | |
9652 | * so we need only reprogram the base address. | |
9653 | */ | |
6d90c952 DV |
9654 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9655 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9656 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9657 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9658 | obj->tiling_mode); |
8c9f3aaf JB |
9659 | |
9660 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9661 | * untested on non-native modes, so ignore it for now. | |
9662 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9663 | */ | |
9664 | pf = 0; | |
9665 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9666 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9667 | |
9668 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9669 | __intel_ring_advance(ring); |
83d4092b | 9670 | return 0; |
8c9f3aaf JB |
9671 | } |
9672 | ||
9673 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9674 | struct drm_crtc *crtc, | |
9675 | struct drm_framebuffer *fb, | |
ed8d1975 | 9676 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9677 | struct intel_engine_cs *ring, |
ed8d1975 | 9678 | uint32_t flags) |
8c9f3aaf JB |
9679 | { |
9680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9682 | uint32_t pf, pipesrc; | |
9683 | int ret; | |
9684 | ||
6d90c952 | 9685 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9686 | if (ret) |
4fa62c89 | 9687 | return ret; |
8c9f3aaf | 9688 | |
6d90c952 DV |
9689 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9690 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9691 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9692 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9693 | |
dc257cf1 DV |
9694 | /* Contrary to the suggestions in the documentation, |
9695 | * "Enable Panel Fitter" does not seem to be required when page | |
9696 | * flipping with a non-native mode, and worse causes a normal | |
9697 | * modeset to fail. | |
9698 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9699 | */ | |
9700 | pf = 0; | |
8c9f3aaf | 9701 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9702 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9703 | |
9704 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9705 | __intel_ring_advance(ring); |
83d4092b | 9706 | return 0; |
8c9f3aaf JB |
9707 | } |
9708 | ||
7c9017e5 JB |
9709 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9710 | struct drm_crtc *crtc, | |
9711 | struct drm_framebuffer *fb, | |
ed8d1975 | 9712 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9713 | struct intel_engine_cs *ring, |
ed8d1975 | 9714 | uint32_t flags) |
7c9017e5 | 9715 | { |
7c9017e5 | 9716 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9717 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9718 | int len, ret; |
9719 | ||
eba905b2 | 9720 | switch (intel_crtc->plane) { |
cb05d8de DV |
9721 | case PLANE_A: |
9722 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9723 | break; | |
9724 | case PLANE_B: | |
9725 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9726 | break; | |
9727 | case PLANE_C: | |
9728 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9729 | break; | |
9730 | default: | |
9731 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9732 | return -ENODEV; |
cb05d8de DV |
9733 | } |
9734 | ||
ffe74d75 | 9735 | len = 4; |
f476828a | 9736 | if (ring->id == RCS) { |
ffe74d75 | 9737 | len += 6; |
f476828a DL |
9738 | /* |
9739 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9740 | * 48bits addresses, and we need a NOOP for the batch size to | |
9741 | * stay even. | |
9742 | */ | |
9743 | if (IS_GEN8(dev)) | |
9744 | len += 2; | |
9745 | } | |
ffe74d75 | 9746 | |
f66fab8e VS |
9747 | /* |
9748 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9749 | * "The full packet must be contained within the same cache line." | |
9750 | * | |
9751 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9752 | * cacheline, if we ever start emitting more commands before | |
9753 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9754 | * then do the cacheline alignment, and finally emit the | |
9755 | * MI_DISPLAY_FLIP. | |
9756 | */ | |
9757 | ret = intel_ring_cacheline_align(ring); | |
9758 | if (ret) | |
4fa62c89 | 9759 | return ret; |
f66fab8e | 9760 | |
ffe74d75 | 9761 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9762 | if (ret) |
4fa62c89 | 9763 | return ret; |
7c9017e5 | 9764 | |
ffe74d75 CW |
9765 | /* Unmask the flip-done completion message. Note that the bspec says that |
9766 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9767 | * more than one flip event at any time (or ensure that one flip message | |
9768 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9769 | * Experimentation says that BCS works despite DERRMR masking all | |
9770 | * flip-done completion events and that unmasking all planes at once | |
9771 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9772 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9773 | */ | |
9774 | if (ring->id == RCS) { | |
9775 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9776 | intel_ring_emit(ring, DERRMR); | |
9777 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9778 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9779 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9780 | if (IS_GEN8(dev)) |
9781 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9782 | MI_SRM_LRM_GLOBAL_GTT); | |
9783 | else | |
9784 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9785 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9786 | intel_ring_emit(ring, DERRMR); |
9787 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9788 | if (IS_GEN8(dev)) { |
9789 | intel_ring_emit(ring, 0); | |
9790 | intel_ring_emit(ring, MI_NOOP); | |
9791 | } | |
ffe74d75 CW |
9792 | } |
9793 | ||
cb05d8de | 9794 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9795 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9796 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9797 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9798 | |
9799 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9800 | __intel_ring_advance(ring); |
83d4092b | 9801 | return 0; |
7c9017e5 JB |
9802 | } |
9803 | ||
84c33a64 SG |
9804 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9805 | struct drm_i915_gem_object *obj) | |
9806 | { | |
9807 | /* | |
9808 | * This is not being used for older platforms, because | |
9809 | * non-availability of flip done interrupt forces us to use | |
9810 | * CS flips. Older platforms derive flip done using some clever | |
9811 | * tricks involving the flip_pending status bits and vblank irqs. | |
9812 | * So using MMIO flips there would disrupt this mechanism. | |
9813 | */ | |
9814 | ||
8e09bf83 CW |
9815 | if (ring == NULL) |
9816 | return true; | |
9817 | ||
84c33a64 SG |
9818 | if (INTEL_INFO(ring->dev)->gen < 5) |
9819 | return false; | |
9820 | ||
9821 | if (i915.use_mmio_flip < 0) | |
9822 | return false; | |
9823 | else if (i915.use_mmio_flip > 0) | |
9824 | return true; | |
14bf993e OM |
9825 | else if (i915.enable_execlists) |
9826 | return true; | |
84c33a64 | 9827 | else |
41c52415 | 9828 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9829 | } |
9830 | ||
ff944564 DL |
9831 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9832 | { | |
9833 | struct drm_device *dev = intel_crtc->base.dev; | |
9834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9835 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9836 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9837 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9838 | const enum pipe pipe = intel_crtc->pipe; | |
9839 | u32 ctl, stride; | |
9840 | ||
9841 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9842 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9843 | if (obj->tiling_mode == I915_TILING_X) | |
9844 | ctl |= PLANE_CTL_TILED_X; | |
9845 | ||
9846 | /* | |
9847 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9848 | * linear buffers or in number of tiles for tiled buffers. | |
9849 | */ | |
9850 | stride = fb->pitches[0] >> 6; | |
9851 | if (obj->tiling_mode == I915_TILING_X) | |
9852 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9853 | ||
9854 | /* | |
9855 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9856 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9857 | */ | |
9858 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9859 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9860 | ||
9861 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9862 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9863 | } | |
9864 | ||
9865 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9866 | { |
9867 | struct drm_device *dev = intel_crtc->base.dev; | |
9868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9869 | struct intel_framebuffer *intel_fb = | |
9870 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9871 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9872 | u32 dspcntr; | |
9873 | u32 reg; | |
9874 | ||
84c33a64 SG |
9875 | reg = DSPCNTR(intel_crtc->plane); |
9876 | dspcntr = I915_READ(reg); | |
9877 | ||
c5d97472 DL |
9878 | if (obj->tiling_mode != I915_TILING_NONE) |
9879 | dspcntr |= DISPPLANE_TILED; | |
9880 | else | |
9881 | dspcntr &= ~DISPPLANE_TILED; | |
9882 | ||
84c33a64 SG |
9883 | I915_WRITE(reg, dspcntr); |
9884 | ||
9885 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9886 | intel_crtc->unpin_work->gtt_offset); | |
9887 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9888 | |
ff944564 DL |
9889 | } |
9890 | ||
9891 | /* | |
9892 | * XXX: This is the temporary way to update the plane registers until we get | |
9893 | * around to using the usual plane update functions for MMIO flips | |
9894 | */ | |
9895 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9896 | { | |
9897 | struct drm_device *dev = intel_crtc->base.dev; | |
9898 | bool atomic_update; | |
9899 | u32 start_vbl_count; | |
9900 | ||
9901 | intel_mark_page_flip_active(intel_crtc); | |
9902 | ||
9903 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9904 | ||
9905 | if (INTEL_INFO(dev)->gen >= 9) | |
9906 | skl_do_mmio_flip(intel_crtc); | |
9907 | else | |
9908 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9909 | ilk_do_mmio_flip(intel_crtc); | |
9910 | ||
9362c7c5 ACO |
9911 | if (atomic_update) |
9912 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9913 | } |
9914 | ||
9362c7c5 | 9915 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9916 | { |
cc8c4cc2 | 9917 | struct intel_crtc *crtc = |
9362c7c5 | 9918 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9919 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9920 | |
cc8c4cc2 JH |
9921 | mmio_flip = &crtc->mmio_flip; |
9922 | if (mmio_flip->req) | |
9c654818 JH |
9923 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9924 | crtc->reset_counter, | |
9925 | false, NULL, NULL) != 0); | |
84c33a64 | 9926 | |
cc8c4cc2 JH |
9927 | intel_do_mmio_flip(crtc); |
9928 | if (mmio_flip->req) { | |
9929 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 9930 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
9931 | mutex_unlock(&crtc->base.dev->struct_mutex); |
9932 | } | |
84c33a64 SG |
9933 | } |
9934 | ||
9935 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9936 | struct drm_crtc *crtc, | |
9937 | struct drm_framebuffer *fb, | |
9938 | struct drm_i915_gem_object *obj, | |
9939 | struct intel_engine_cs *ring, | |
9940 | uint32_t flags) | |
9941 | { | |
84c33a64 | 9942 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9943 | |
cc8c4cc2 JH |
9944 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9945 | obj->last_write_req); | |
536f5b5e ACO |
9946 | |
9947 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9948 | |
84c33a64 SG |
9949 | return 0; |
9950 | } | |
9951 | ||
8c9f3aaf JB |
9952 | static int intel_default_queue_flip(struct drm_device *dev, |
9953 | struct drm_crtc *crtc, | |
9954 | struct drm_framebuffer *fb, | |
ed8d1975 | 9955 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9956 | struct intel_engine_cs *ring, |
ed8d1975 | 9957 | uint32_t flags) |
8c9f3aaf JB |
9958 | { |
9959 | return -ENODEV; | |
9960 | } | |
9961 | ||
d6bbafa1 CW |
9962 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9963 | struct drm_crtc *crtc) | |
9964 | { | |
9965 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9966 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9967 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9968 | u32 addr; | |
9969 | ||
9970 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9971 | return true; | |
9972 | ||
9973 | if (!work->enable_stall_check) | |
9974 | return false; | |
9975 | ||
9976 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9977 | if (work->flip_queued_req && |
9978 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
9979 | return false; |
9980 | ||
1e3feefd | 9981 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
9982 | } |
9983 | ||
1e3feefd | 9984 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
9985 | return false; |
9986 | ||
9987 | /* Potential stall - if we see that the flip has happened, | |
9988 | * assume a missed interrupt. */ | |
9989 | if (INTEL_INFO(dev)->gen >= 4) | |
9990 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9991 | else | |
9992 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9993 | ||
9994 | /* There is a potential issue here with a false positive after a flip | |
9995 | * to the same address. We could address this by checking for a | |
9996 | * non-incrementing frame counter. | |
9997 | */ | |
9998 | return addr == work->gtt_offset; | |
9999 | } | |
10000 | ||
10001 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10002 | { | |
10003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10004 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a | 10006 | |
6c51d46f | 10007 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10008 | |
10009 | if (crtc == NULL) | |
10010 | return; | |
10011 | ||
f326038a | 10012 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
10013 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
10014 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
1e3feefd DV |
10015 | intel_crtc->unpin_work->flip_queued_vblank, |
10016 | drm_vblank_count(dev, pipe)); | |
d6bbafa1 CW |
10017 | page_flip_completed(intel_crtc); |
10018 | } | |
f326038a | 10019 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10020 | } |
10021 | ||
6b95a207 KH |
10022 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10023 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10024 | struct drm_pending_vblank_event *event, |
10025 | uint32_t page_flip_flags) | |
6b95a207 KH |
10026 | { |
10027 | struct drm_device *dev = crtc->dev; | |
10028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10029 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10030 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10032 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10033 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10034 | struct intel_unpin_work *work; |
a4872ba6 | 10035 | struct intel_engine_cs *ring; |
52e68630 | 10036 | int ret; |
6b95a207 | 10037 | |
2ff8fde1 MR |
10038 | /* |
10039 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10040 | * check to be safe. In the future we may enable pageflipping from | |
10041 | * a disabled primary plane. | |
10042 | */ | |
10043 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10044 | return -EBUSY; | |
10045 | ||
e6a595d2 | 10046 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10047 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10048 | return -EINVAL; |
10049 | ||
10050 | /* | |
10051 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10052 | * Note that pitch changes could also affect these register. | |
10053 | */ | |
10054 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10055 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10056 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10057 | return -EINVAL; |
10058 | ||
f900db47 CW |
10059 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10060 | goto out_hang; | |
10061 | ||
b14c5679 | 10062 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10063 | if (work == NULL) |
10064 | return -ENOMEM; | |
10065 | ||
6b95a207 | 10066 | work->event = event; |
b4a98e57 | 10067 | work->crtc = crtc; |
ab8d6675 | 10068 | work->old_fb = old_fb; |
6b95a207 KH |
10069 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10070 | ||
87b6b101 | 10071 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10072 | if (ret) |
10073 | goto free_work; | |
10074 | ||
6b95a207 | 10075 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10076 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10077 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10078 | /* Before declaring the flip queue wedged, check if |
10079 | * the hardware completed the operation behind our backs. | |
10080 | */ | |
10081 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10082 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10083 | page_flip_completed(intel_crtc); | |
10084 | } else { | |
10085 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10086 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10087 | |
d6bbafa1 CW |
10088 | drm_crtc_vblank_put(crtc); |
10089 | kfree(work); | |
10090 | return -EBUSY; | |
10091 | } | |
6b95a207 KH |
10092 | } |
10093 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10094 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10095 | |
b4a98e57 CW |
10096 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10097 | flush_workqueue(dev_priv->wq); | |
10098 | ||
75dfca80 | 10099 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10100 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10101 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10102 | |
f4510a27 | 10103 | crtc->primary->fb = fb; |
afd65eb4 | 10104 | update_state_fb(crtc->primary); |
1ed1f968 | 10105 | |
e1f99ce6 | 10106 | work->pending_flip_obj = obj; |
e1f99ce6 | 10107 | |
89ed88ba CW |
10108 | ret = i915_mutex_lock_interruptible(dev); |
10109 | if (ret) | |
10110 | goto cleanup; | |
10111 | ||
b4a98e57 | 10112 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10113 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10114 | |
75f7f3ec | 10115 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10116 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10117 | |
4fa62c89 VS |
10118 | if (IS_VALLEYVIEW(dev)) { |
10119 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10120 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10121 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10122 | ring = NULL; | |
48bf5b2d | 10123 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10124 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10125 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10126 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10127 | if (ring == NULL || ring->id != RCS) |
10128 | ring = &dev_priv->ring[BCS]; | |
10129 | } else { | |
10130 | ring = &dev_priv->ring[RCS]; | |
10131 | } | |
10132 | ||
82bc3b2d TU |
10133 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
10134 | crtc->primary->state, ring); | |
8c9f3aaf JB |
10135 | if (ret) |
10136 | goto cleanup_pending; | |
6b95a207 | 10137 | |
121920fa TU |
10138 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10139 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10140 | |
d6bbafa1 | 10141 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
10142 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10143 | page_flip_flags); | |
d6bbafa1 CW |
10144 | if (ret) |
10145 | goto cleanup_unpin; | |
10146 | ||
f06cc1b9 JH |
10147 | i915_gem_request_assign(&work->flip_queued_req, |
10148 | obj->last_write_req); | |
d6bbafa1 | 10149 | } else { |
84c33a64 | 10150 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10151 | page_flip_flags); |
10152 | if (ret) | |
10153 | goto cleanup_unpin; | |
10154 | ||
f06cc1b9 JH |
10155 | i915_gem_request_assign(&work->flip_queued_req, |
10156 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10157 | } |
10158 | ||
1e3feefd | 10159 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10160 | work->enable_stall_check = true; |
4fa62c89 | 10161 | |
ab8d6675 | 10162 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
10163 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
10164 | ||
7ff0ebcc | 10165 | intel_fbc_disable(dev); |
f99d7069 | 10166 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10167 | mutex_unlock(&dev->struct_mutex); |
10168 | ||
e5510fac JB |
10169 | trace_i915_flip_request(intel_crtc->plane, obj); |
10170 | ||
6b95a207 | 10171 | return 0; |
96b099fd | 10172 | |
4fa62c89 | 10173 | cleanup_unpin: |
82bc3b2d | 10174 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 10175 | cleanup_pending: |
b4a98e57 | 10176 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
10177 | mutex_unlock(&dev->struct_mutex); |
10178 | cleanup: | |
f4510a27 | 10179 | crtc->primary->fb = old_fb; |
afd65eb4 | 10180 | update_state_fb(crtc->primary); |
89ed88ba CW |
10181 | |
10182 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 10183 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 10184 | |
5e2d7afc | 10185 | spin_lock_irq(&dev->event_lock); |
96b099fd | 10186 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 10187 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 10188 | |
87b6b101 | 10189 | drm_crtc_vblank_put(crtc); |
7317c75e | 10190 | free_work: |
96b099fd CW |
10191 | kfree(work); |
10192 | ||
f900db47 CW |
10193 | if (ret == -EIO) { |
10194 | out_hang: | |
53a366b9 | 10195 | ret = intel_plane_restore(primary); |
f0d3dad3 | 10196 | if (ret == 0 && event) { |
5e2d7afc | 10197 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 10198 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 10199 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 10200 | } |
f900db47 | 10201 | } |
96b099fd | 10202 | return ret; |
6b95a207 KH |
10203 | } |
10204 | ||
f6e5b160 | 10205 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10206 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10207 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
10208 | .atomic_begin = intel_begin_crtc_commit, |
10209 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
10210 | }; |
10211 | ||
9a935856 DV |
10212 | /** |
10213 | * intel_modeset_update_staged_output_state | |
10214 | * | |
10215 | * Updates the staged output configuration state, e.g. after we've read out the | |
10216 | * current hw state. | |
10217 | */ | |
10218 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10219 | { |
7668851f | 10220 | struct intel_crtc *crtc; |
9a935856 DV |
10221 | struct intel_encoder *encoder; |
10222 | struct intel_connector *connector; | |
f6e5b160 | 10223 | |
3a3371ff | 10224 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10225 | connector->new_encoder = |
10226 | to_intel_encoder(connector->base.encoder); | |
10227 | } | |
f6e5b160 | 10228 | |
b2784e15 | 10229 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10230 | encoder->new_crtc = |
10231 | to_intel_crtc(encoder->base.crtc); | |
10232 | } | |
7668851f | 10233 | |
d3fcc808 | 10234 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10235 | crtc->new_enabled = crtc->base.state->enable; |
7bd0a8e7 VS |
10236 | |
10237 | if (crtc->new_enabled) | |
6e3c9717 | 10238 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
10239 | else |
10240 | crtc->new_config = NULL; | |
7668851f | 10241 | } |
f6e5b160 CW |
10242 | } |
10243 | ||
d29b2f9d ACO |
10244 | /* Transitional helper to copy current connector/encoder state to |
10245 | * connector->state. This is needed so that code that is partially | |
10246 | * converted to atomic does the right thing. | |
10247 | */ | |
10248 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
10249 | { | |
10250 | struct intel_connector *connector; | |
10251 | ||
10252 | for_each_intel_connector(dev, connector) { | |
10253 | if (connector->base.encoder) { | |
10254 | connector->base.state->best_encoder = | |
10255 | connector->base.encoder; | |
10256 | connector->base.state->crtc = | |
10257 | connector->base.encoder->crtc; | |
10258 | } else { | |
10259 | connector->base.state->best_encoder = NULL; | |
10260 | connector->base.state->crtc = NULL; | |
10261 | } | |
10262 | } | |
10263 | } | |
10264 | ||
9a935856 DV |
10265 | /** |
10266 | * intel_modeset_commit_output_state | |
10267 | * | |
10268 | * This function copies the stage display pipe configuration to the real one. | |
10269 | */ | |
10270 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10271 | { | |
7668851f | 10272 | struct intel_crtc *crtc; |
9a935856 DV |
10273 | struct intel_encoder *encoder; |
10274 | struct intel_connector *connector; | |
f6e5b160 | 10275 | |
3a3371ff | 10276 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
10277 | connector->base.encoder = &connector->new_encoder->base; |
10278 | } | |
f6e5b160 | 10279 | |
b2784e15 | 10280 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10281 | encoder->base.crtc = &encoder->new_crtc->base; |
10282 | } | |
7668851f | 10283 | |
d3fcc808 | 10284 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 10285 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
10286 | crtc->base.enabled = crtc->new_enabled; |
10287 | } | |
d29b2f9d ACO |
10288 | |
10289 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
10290 | } |
10291 | ||
050f7aeb | 10292 | static void |
eba905b2 | 10293 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10294 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
10295 | { |
10296 | int bpp = pipe_config->pipe_bpp; | |
10297 | ||
10298 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10299 | connector->base.base.id, | |
c23cc417 | 10300 | connector->base.name); |
050f7aeb DV |
10301 | |
10302 | /* Don't use an invalid EDID bpc value */ | |
10303 | if (connector->base.display_info.bpc && | |
10304 | connector->base.display_info.bpc * 3 < bpp) { | |
10305 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10306 | bpp, connector->base.display_info.bpc*3); | |
10307 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10308 | } | |
10309 | ||
10310 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10311 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10312 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10313 | bpp); | |
10314 | pipe_config->pipe_bpp = 24; | |
10315 | } | |
10316 | } | |
10317 | ||
4e53c2e0 | 10318 | static int |
050f7aeb DV |
10319 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10320 | struct drm_framebuffer *fb, | |
5cec258b | 10321 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10322 | { |
050f7aeb | 10323 | struct drm_device *dev = crtc->base.dev; |
1486017f | 10324 | struct drm_atomic_state *state; |
050f7aeb | 10325 | struct intel_connector *connector; |
1486017f | 10326 | int bpp, i; |
4e53c2e0 | 10327 | |
d42264b1 DV |
10328 | switch (fb->pixel_format) { |
10329 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10330 | bpp = 8*3; /* since we go through a colormap */ |
10331 | break; | |
d42264b1 DV |
10332 | case DRM_FORMAT_XRGB1555: |
10333 | case DRM_FORMAT_ARGB1555: | |
10334 | /* checked in intel_framebuffer_init already */ | |
10335 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10336 | return -EINVAL; | |
10337 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10338 | bpp = 6*3; /* min is 18bpp */ |
10339 | break; | |
d42264b1 DV |
10340 | case DRM_FORMAT_XBGR8888: |
10341 | case DRM_FORMAT_ABGR8888: | |
10342 | /* checked in intel_framebuffer_init already */ | |
10343 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10344 | return -EINVAL; | |
10345 | case DRM_FORMAT_XRGB8888: | |
10346 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10347 | bpp = 8*3; |
10348 | break; | |
d42264b1 DV |
10349 | case DRM_FORMAT_XRGB2101010: |
10350 | case DRM_FORMAT_ARGB2101010: | |
10351 | case DRM_FORMAT_XBGR2101010: | |
10352 | case DRM_FORMAT_ABGR2101010: | |
10353 | /* checked in intel_framebuffer_init already */ | |
10354 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10355 | return -EINVAL; |
4e53c2e0 DV |
10356 | bpp = 10*3; |
10357 | break; | |
baba133a | 10358 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10359 | default: |
10360 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10361 | return -EINVAL; | |
10362 | } | |
10363 | ||
4e53c2e0 DV |
10364 | pipe_config->pipe_bpp = bpp; |
10365 | ||
1486017f ACO |
10366 | state = pipe_config->base.state; |
10367 | ||
4e53c2e0 | 10368 | /* Clamp display bpp to EDID value */ |
1486017f ACO |
10369 | for (i = 0; i < state->num_connector; i++) { |
10370 | if (!state->connectors[i]) | |
10371 | continue; | |
10372 | ||
10373 | connector = to_intel_connector(state->connectors[i]); | |
10374 | if (state->connector_states[i]->crtc != &crtc->base) | |
4e53c2e0 DV |
10375 | continue; |
10376 | ||
050f7aeb | 10377 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10378 | } |
10379 | ||
10380 | return bpp; | |
10381 | } | |
10382 | ||
644db711 DV |
10383 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10384 | { | |
10385 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10386 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10387 | mode->crtc_clock, |
644db711 DV |
10388 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10389 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10390 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10391 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10392 | } | |
10393 | ||
c0b03411 | 10394 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10395 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10396 | const char *context) |
10397 | { | |
10398 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10399 | context, pipe_name(crtc->pipe)); | |
10400 | ||
10401 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10402 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10403 | pipe_config->pipe_bpp, pipe_config->dither); | |
10404 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10405 | pipe_config->has_pch_encoder, | |
10406 | pipe_config->fdi_lanes, | |
10407 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10408 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10409 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10410 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10411 | pipe_config->has_dp_encoder, | |
10412 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10413 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10414 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10415 | |
10416 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10417 | pipe_config->has_dp_encoder, | |
10418 | pipe_config->dp_m2_n2.gmch_m, | |
10419 | pipe_config->dp_m2_n2.gmch_n, | |
10420 | pipe_config->dp_m2_n2.link_m, | |
10421 | pipe_config->dp_m2_n2.link_n, | |
10422 | pipe_config->dp_m2_n2.tu); | |
10423 | ||
55072d19 DV |
10424 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
10425 | pipe_config->has_audio, | |
10426 | pipe_config->has_infoframe); | |
10427 | ||
c0b03411 | 10428 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10429 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10430 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10431 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10432 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 10433 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10434 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10435 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10436 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10437 | pipe_config->gmch_pfit.control, | |
10438 | pipe_config->gmch_pfit.pgm_ratios, | |
10439 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10440 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10441 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10442 | pipe_config->pch_pfit.size, |
10443 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10444 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10445 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10446 | } |
10447 | ||
bc079e8b VS |
10448 | static bool encoders_cloneable(const struct intel_encoder *a, |
10449 | const struct intel_encoder *b) | |
accfc0c5 | 10450 | { |
bc079e8b VS |
10451 | /* masks could be asymmetric, so check both ways */ |
10452 | return a == b || (a->cloneable & (1 << b->type) && | |
10453 | b->cloneable & (1 << a->type)); | |
10454 | } | |
10455 | ||
10456 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10457 | struct intel_encoder *encoder) | |
10458 | { | |
10459 | struct drm_device *dev = crtc->base.dev; | |
10460 | struct intel_encoder *source_encoder; | |
10461 | ||
b2784e15 | 10462 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10463 | if (source_encoder->new_crtc != crtc) |
10464 | continue; | |
10465 | ||
10466 | if (!encoders_cloneable(encoder, source_encoder)) | |
10467 | return false; | |
10468 | } | |
10469 | ||
10470 | return true; | |
10471 | } | |
10472 | ||
10473 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10474 | { | |
10475 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10476 | struct intel_encoder *encoder; |
10477 | ||
b2784e15 | 10478 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10479 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10480 | continue; |
10481 | ||
bc079e8b VS |
10482 | if (!check_single_encoder_cloning(crtc, encoder)) |
10483 | return false; | |
accfc0c5 DV |
10484 | } |
10485 | ||
bc079e8b | 10486 | return true; |
accfc0c5 DV |
10487 | } |
10488 | ||
00f0b378 VS |
10489 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10490 | { | |
10491 | struct intel_connector *connector; | |
10492 | unsigned int used_ports = 0; | |
10493 | ||
10494 | /* | |
10495 | * Walk the connector list instead of the encoder | |
10496 | * list to detect the problem on ddi platforms | |
10497 | * where there's just one encoder per digital port. | |
10498 | */ | |
3a3371ff | 10499 | for_each_intel_connector(dev, connector) { |
00f0b378 VS |
10500 | struct intel_encoder *encoder = connector->new_encoder; |
10501 | ||
10502 | if (!encoder) | |
10503 | continue; | |
10504 | ||
10505 | WARN_ON(!encoder->new_crtc); | |
10506 | ||
10507 | switch (encoder->type) { | |
10508 | unsigned int port_mask; | |
10509 | case INTEL_OUTPUT_UNKNOWN: | |
10510 | if (WARN_ON(!HAS_DDI(dev))) | |
10511 | break; | |
10512 | case INTEL_OUTPUT_DISPLAYPORT: | |
10513 | case INTEL_OUTPUT_HDMI: | |
10514 | case INTEL_OUTPUT_EDP: | |
10515 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10516 | ||
10517 | /* the same port mustn't appear more than once */ | |
10518 | if (used_ports & port_mask) | |
10519 | return false; | |
10520 | ||
10521 | used_ports |= port_mask; | |
10522 | default: | |
10523 | break; | |
10524 | } | |
10525 | } | |
10526 | ||
10527 | return true; | |
10528 | } | |
10529 | ||
83a57153 ACO |
10530 | static void |
10531 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10532 | { | |
10533 | struct drm_crtc_state tmp_state; | |
10534 | ||
10535 | /* Clear only the intel specific part of the crtc state */ | |
10536 | tmp_state = crtc_state->base; | |
10537 | memset(crtc_state, 0, sizeof *crtc_state); | |
10538 | crtc_state->base = tmp_state; | |
10539 | } | |
10540 | ||
5cec258b | 10541 | static struct intel_crtc_state * |
b8cecdf5 | 10542 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
4e53c2e0 | 10543 | struct drm_framebuffer *fb, |
83a57153 ACO |
10544 | struct drm_display_mode *mode, |
10545 | struct drm_atomic_state *state) | |
ee7b9f93 | 10546 | { |
7758a113 | 10547 | struct drm_device *dev = crtc->dev; |
7758a113 | 10548 | struct intel_encoder *encoder; |
0b901879 ACO |
10549 | struct intel_connector *connector; |
10550 | struct drm_connector_state *connector_state; | |
5cec258b | 10551 | struct intel_crtc_state *pipe_config; |
e29c22c0 | 10552 | int plane_bpp, ret = -EINVAL; |
0b901879 | 10553 | int i; |
e29c22c0 | 10554 | bool retry = true; |
ee7b9f93 | 10555 | |
bc079e8b | 10556 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10557 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10558 | return ERR_PTR(-EINVAL); | |
10559 | } | |
10560 | ||
00f0b378 VS |
10561 | if (!check_digital_port_conflicts(dev)) { |
10562 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10563 | return ERR_PTR(-EINVAL); | |
10564 | } | |
10565 | ||
83a57153 ACO |
10566 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
10567 | if (IS_ERR(pipe_config)) | |
10568 | return pipe_config; | |
10569 | ||
10570 | clear_intel_crtc_state(pipe_config); | |
7758a113 | 10571 | |
07878248 | 10572 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
10573 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
10574 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 10575 | |
e143a21c DV |
10576 | pipe_config->cpu_transcoder = |
10577 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10578 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10579 | |
2960bc9c ID |
10580 | /* |
10581 | * Sanitize sync polarity flags based on requested ones. If neither | |
10582 | * positive or negative polarity is requested, treat this as meaning | |
10583 | * negative polarity. | |
10584 | */ | |
2d112de7 | 10585 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10586 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10587 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10588 | |
2d112de7 | 10589 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10590 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10591 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10592 | |
050f7aeb DV |
10593 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10594 | * plane pixel format and any sink constraints into account. Returns the | |
10595 | * source plane bpp so that dithering can be selected on mismatches | |
10596 | * after encoders and crtc also have had their say. */ | |
10597 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10598 | fb, pipe_config); | |
4e53c2e0 DV |
10599 | if (plane_bpp < 0) |
10600 | goto fail; | |
10601 | ||
e41a56be VS |
10602 | /* |
10603 | * Determine the real pipe dimensions. Note that stereo modes can | |
10604 | * increase the actual pipe size due to the frame doubling and | |
10605 | * insertion of additional space for blanks between the frame. This | |
10606 | * is stored in the crtc timings. We use the requested mode to do this | |
10607 | * computation to clearly distinguish it from the adjusted mode, which | |
10608 | * can be changed by the connectors in the below retry loop. | |
10609 | */ | |
2d112de7 | 10610 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10611 | &pipe_config->pipe_src_w, |
10612 | &pipe_config->pipe_src_h); | |
e41a56be | 10613 | |
e29c22c0 | 10614 | encoder_retry: |
ef1b460d | 10615 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10616 | pipe_config->port_clock = 0; |
ef1b460d | 10617 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10618 | |
135c81b8 | 10619 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10620 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10621 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10622 | |
7758a113 DV |
10623 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10624 | * adjust it according to limitations or connector properties, and also | |
10625 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10626 | */ |
0b901879 ACO |
10627 | for (i = 0; i < state->num_connector; i++) { |
10628 | connector = to_intel_connector(state->connectors[i]); | |
10629 | if (!connector) | |
10630 | continue; | |
47f1c6c9 | 10631 | |
0b901879 ACO |
10632 | connector_state = state->connector_states[i]; |
10633 | if (connector_state->crtc != crtc) | |
7758a113 | 10634 | continue; |
7ae89233 | 10635 | |
0b901879 ACO |
10636 | encoder = to_intel_encoder(connector_state->best_encoder); |
10637 | ||
efea6e8e DV |
10638 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10639 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10640 | goto fail; |
10641 | } | |
ee7b9f93 | 10642 | } |
47f1c6c9 | 10643 | |
ff9a6750 DV |
10644 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10645 | * done afterwards in case the encoder adjusts the mode. */ | |
10646 | if (!pipe_config->port_clock) | |
2d112de7 | 10647 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10648 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10649 | |
a43f6e0f | 10650 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10651 | if (ret < 0) { |
7758a113 DV |
10652 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10653 | goto fail; | |
ee7b9f93 | 10654 | } |
e29c22c0 DV |
10655 | |
10656 | if (ret == RETRY) { | |
10657 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10658 | ret = -EINVAL; | |
10659 | goto fail; | |
10660 | } | |
10661 | ||
10662 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10663 | retry = false; | |
10664 | goto encoder_retry; | |
10665 | } | |
10666 | ||
4e53c2e0 DV |
10667 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10668 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10669 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10670 | ||
b8cecdf5 | 10671 | return pipe_config; |
7758a113 | 10672 | fail: |
e29c22c0 | 10673 | return ERR_PTR(ret); |
ee7b9f93 | 10674 | } |
47f1c6c9 | 10675 | |
e2e1ed41 DV |
10676 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10677 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10678 | static void | |
10679 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10680 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10681 | { |
10682 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10683 | struct drm_device *dev = crtc->dev; |
10684 | struct intel_encoder *encoder; | |
10685 | struct intel_connector *connector; | |
10686 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10687 | |
e2e1ed41 | 10688 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10689 | |
e2e1ed41 DV |
10690 | /* Check which crtcs have changed outputs connected to them, these need |
10691 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10692 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10693 | * bit set at most. */ | |
3a3371ff | 10694 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
10695 | if (connector->base.encoder == &connector->new_encoder->base) |
10696 | continue; | |
79e53945 | 10697 | |
e2e1ed41 DV |
10698 | if (connector->base.encoder) { |
10699 | tmp_crtc = connector->base.encoder->crtc; | |
10700 | ||
10701 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10702 | } | |
10703 | ||
10704 | if (connector->new_encoder) | |
10705 | *prepare_pipes |= | |
10706 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10707 | } |
10708 | ||
b2784e15 | 10709 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10710 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10711 | continue; | |
10712 | ||
10713 | if (encoder->base.crtc) { | |
10714 | tmp_crtc = encoder->base.crtc; | |
10715 | ||
10716 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10717 | } | |
10718 | ||
10719 | if (encoder->new_crtc) | |
10720 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10721 | } |
10722 | ||
7668851f | 10723 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10724 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10725 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 10726 | continue; |
7e7d76c3 | 10727 | |
7668851f | 10728 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10729 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10730 | else |
10731 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10732 | } |
10733 | ||
e2e1ed41 DV |
10734 | |
10735 | /* set_mode is also used to update properties on life display pipes. */ | |
10736 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10737 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10738 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10739 | ||
b6c5164d DV |
10740 | /* |
10741 | * For simplicity do a full modeset on any pipe where the output routing | |
10742 | * changed. We could be more clever, but that would require us to be | |
10743 | * more careful with calling the relevant encoder->mode_set functions. | |
10744 | */ | |
e2e1ed41 DV |
10745 | if (*prepare_pipes) |
10746 | *modeset_pipes = *prepare_pipes; | |
10747 | ||
10748 | /* ... and mask these out. */ | |
10749 | *modeset_pipes &= ~(*disable_pipes); | |
10750 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10751 | |
10752 | /* | |
10753 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10754 | * obies this rule, but the modeset restore mode of | |
10755 | * intel_modeset_setup_hw_state does not. | |
10756 | */ | |
10757 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10758 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10759 | |
10760 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10761 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10762 | } |
79e53945 | 10763 | |
ea9d758d | 10764 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10765 | { |
ea9d758d | 10766 | struct drm_encoder *encoder; |
f6e5b160 | 10767 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10768 | |
ea9d758d DV |
10769 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10770 | if (encoder->crtc == crtc) | |
10771 | return true; | |
10772 | ||
10773 | return false; | |
10774 | } | |
10775 | ||
10776 | static void | |
10777 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10778 | { | |
ba41c0de | 10779 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10780 | struct intel_encoder *intel_encoder; |
10781 | struct intel_crtc *intel_crtc; | |
10782 | struct drm_connector *connector; | |
10783 | ||
ba41c0de DV |
10784 | intel_shared_dpll_commit(dev_priv); |
10785 | ||
b2784e15 | 10786 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10787 | if (!intel_encoder->base.crtc) |
10788 | continue; | |
10789 | ||
10790 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10791 | ||
10792 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10793 | intel_encoder->connectors_active = false; | |
10794 | } | |
10795 | ||
10796 | intel_modeset_commit_output_state(dev); | |
10797 | ||
7668851f | 10798 | /* Double check state. */ |
d3fcc808 | 10799 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 10800 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 | 10801 | WARN_ON(intel_crtc->new_config && |
6e3c9717 | 10802 | intel_crtc->new_config != intel_crtc->config); |
83d65738 | 10803 | WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); |
ea9d758d DV |
10804 | } |
10805 | ||
10806 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10807 | if (!connector->encoder || !connector->encoder->crtc) | |
10808 | continue; | |
10809 | ||
10810 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10811 | ||
10812 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10813 | struct drm_property *dpms_property = |
10814 | dev->mode_config.dpms_property; | |
10815 | ||
ea9d758d | 10816 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10817 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10818 | dpms_property, |
10819 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10820 | |
10821 | intel_encoder = to_intel_encoder(connector->encoder); | |
10822 | intel_encoder->connectors_active = true; | |
10823 | } | |
10824 | } | |
10825 | ||
10826 | } | |
10827 | ||
3bd26263 | 10828 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10829 | { |
3bd26263 | 10830 | int diff; |
f1f644dc JB |
10831 | |
10832 | if (clock1 == clock2) | |
10833 | return true; | |
10834 | ||
10835 | if (!clock1 || !clock2) | |
10836 | return false; | |
10837 | ||
10838 | diff = abs(clock1 - clock2); | |
10839 | ||
10840 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10841 | return true; | |
10842 | ||
10843 | return false; | |
10844 | } | |
10845 | ||
25c5b266 DV |
10846 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10847 | list_for_each_entry((intel_crtc), \ | |
10848 | &(dev)->mode_config.crtc_list, \ | |
10849 | base.head) \ | |
0973f18f | 10850 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10851 | |
0e8ffe1b | 10852 | static bool |
2fa2fe9a | 10853 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
10854 | struct intel_crtc_state *current_config, |
10855 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 10856 | { |
66e985c0 DV |
10857 | #define PIPE_CONF_CHECK_X(name) \ |
10858 | if (current_config->name != pipe_config->name) { \ | |
10859 | DRM_ERROR("mismatch in " #name " " \ | |
10860 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10861 | current_config->name, \ | |
10862 | pipe_config->name); \ | |
10863 | return false; \ | |
10864 | } | |
10865 | ||
08a24034 DV |
10866 | #define PIPE_CONF_CHECK_I(name) \ |
10867 | if (current_config->name != pipe_config->name) { \ | |
10868 | DRM_ERROR("mismatch in " #name " " \ | |
10869 | "(expected %i, found %i)\n", \ | |
10870 | current_config->name, \ | |
10871 | pipe_config->name); \ | |
10872 | return false; \ | |
88adfff1 DV |
10873 | } |
10874 | ||
b95af8be VK |
10875 | /* This is required for BDW+ where there is only one set of registers for |
10876 | * switching between high and low RR. | |
10877 | * This macro can be used whenever a comparison has to be made between one | |
10878 | * hw state and multiple sw state variables. | |
10879 | */ | |
10880 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10881 | if ((current_config->name != pipe_config->name) && \ | |
10882 | (current_config->alt_name != pipe_config->name)) { \ | |
10883 | DRM_ERROR("mismatch in " #name " " \ | |
10884 | "(expected %i or %i, found %i)\n", \ | |
10885 | current_config->name, \ | |
10886 | current_config->alt_name, \ | |
10887 | pipe_config->name); \ | |
10888 | return false; \ | |
10889 | } | |
10890 | ||
1bd1bd80 DV |
10891 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10892 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10893 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10894 | "(expected %i, found %i)\n", \ |
10895 | current_config->name & (mask), \ | |
10896 | pipe_config->name & (mask)); \ | |
10897 | return false; \ | |
10898 | } | |
10899 | ||
5e550656 VS |
10900 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10901 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10902 | DRM_ERROR("mismatch in " #name " " \ | |
10903 | "(expected %i, found %i)\n", \ | |
10904 | current_config->name, \ | |
10905 | pipe_config->name); \ | |
10906 | return false; \ | |
10907 | } | |
10908 | ||
bb760063 DV |
10909 | #define PIPE_CONF_QUIRK(quirk) \ |
10910 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10911 | ||
eccb140b DV |
10912 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10913 | ||
08a24034 DV |
10914 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10915 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10916 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10917 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10918 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10919 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10920 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10921 | |
eb14cb74 | 10922 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10923 | |
10924 | if (INTEL_INFO(dev)->gen < 8) { | |
10925 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10926 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10927 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10928 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10929 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10930 | ||
10931 | if (current_config->has_drrs) { | |
10932 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10933 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10934 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10935 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10936 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10937 | } | |
10938 | } else { | |
10939 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10940 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10941 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10942 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10943 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10944 | } | |
eb14cb74 | 10945 | |
2d112de7 ACO |
10946 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
10947 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
10948 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
10949 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
10950 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
10951 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 10952 | |
2d112de7 ACO |
10953 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
10954 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
10955 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
10956 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
10957 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
10958 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 10959 | |
c93f54cf | 10960 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10961 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10962 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10963 | IS_VALLEYVIEW(dev)) | |
10964 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10965 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10966 | |
9ed109a7 DV |
10967 | PIPE_CONF_CHECK_I(has_audio); |
10968 | ||
2d112de7 | 10969 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
10970 | DRM_MODE_FLAG_INTERLACE); |
10971 | ||
bb760063 | 10972 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 10973 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10974 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 10975 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10976 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 10977 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 10978 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 10979 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
10980 | DRM_MODE_FLAG_NVSYNC); |
10981 | } | |
045ac3b5 | 10982 | |
37327abd VS |
10983 | PIPE_CONF_CHECK_I(pipe_src_w); |
10984 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10985 | |
9953599b DV |
10986 | /* |
10987 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10988 | * screen. Since we don't yet re-compute the pipe config when moving | |
10989 | * just the lvds port away to another pipe the sw tracking won't match. | |
10990 | * | |
10991 | * Proper atomic modesets with recomputed global state will fix this. | |
10992 | * Until then just don't check gmch state for inherited modes. | |
10993 | */ | |
10994 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10995 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10996 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10997 | if (INTEL_INFO(dev)->gen < 4) | |
10998 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10999 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11000 | } | |
11001 | ||
fd4daa9c CW |
11002 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11003 | if (current_config->pch_pfit.enabled) { | |
11004 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11005 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11006 | } | |
2fa2fe9a | 11007 | |
e59150dc JB |
11008 | /* BDW+ don't expose a synchronous way to read the state */ |
11009 | if (IS_HASWELL(dev)) | |
11010 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11011 | |
282740f7 VS |
11012 | PIPE_CONF_CHECK_I(double_wide); |
11013 | ||
26804afd DV |
11014 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11015 | ||
c0d43d62 | 11016 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11017 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11018 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11019 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11020 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11021 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11022 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11023 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11024 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11025 | |
42571aef VS |
11026 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11027 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11028 | ||
2d112de7 | 11029 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11030 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11031 | |
66e985c0 | 11032 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11033 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11034 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11035 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11036 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11037 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11038 | |
0e8ffe1b DV |
11039 | return true; |
11040 | } | |
11041 | ||
08db6652 DL |
11042 | static void check_wm_state(struct drm_device *dev) |
11043 | { | |
11044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11045 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11046 | struct intel_crtc *intel_crtc; | |
11047 | int plane; | |
11048 | ||
11049 | if (INTEL_INFO(dev)->gen < 9) | |
11050 | return; | |
11051 | ||
11052 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11053 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11054 | ||
11055 | for_each_intel_crtc(dev, intel_crtc) { | |
11056 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11057 | const enum pipe pipe = intel_crtc->pipe; | |
11058 | ||
11059 | if (!intel_crtc->active) | |
11060 | continue; | |
11061 | ||
11062 | /* planes */ | |
dd740780 | 11063 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11064 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11065 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11066 | ||
11067 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11068 | continue; | |
11069 | ||
11070 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11071 | "(expected (%u,%u), found (%u,%u))\n", | |
11072 | pipe_name(pipe), plane + 1, | |
11073 | sw_entry->start, sw_entry->end, | |
11074 | hw_entry->start, hw_entry->end); | |
11075 | } | |
11076 | ||
11077 | /* cursor */ | |
11078 | hw_entry = &hw_ddb.cursor[pipe]; | |
11079 | sw_entry = &sw_ddb->cursor[pipe]; | |
11080 | ||
11081 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11082 | continue; | |
11083 | ||
11084 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11085 | "(expected (%u,%u), found (%u,%u))\n", | |
11086 | pipe_name(pipe), | |
11087 | sw_entry->start, sw_entry->end, | |
11088 | hw_entry->start, hw_entry->end); | |
11089 | } | |
11090 | } | |
11091 | ||
91d1b4bd DV |
11092 | static void |
11093 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11094 | { |
8af6cf88 DV |
11095 | struct intel_connector *connector; |
11096 | ||
3a3371ff | 11097 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11098 | /* This also checks the encoder/connector hw state with the |
11099 | * ->get_hw_state callbacks. */ | |
11100 | intel_connector_check_state(connector); | |
11101 | ||
e2c719b7 | 11102 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11103 | "connector's staged encoder doesn't match current encoder\n"); |
11104 | } | |
91d1b4bd DV |
11105 | } |
11106 | ||
11107 | static void | |
11108 | check_encoder_state(struct drm_device *dev) | |
11109 | { | |
11110 | struct intel_encoder *encoder; | |
11111 | struct intel_connector *connector; | |
8af6cf88 | 11112 | |
b2784e15 | 11113 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11114 | bool enabled = false; |
11115 | bool active = false; | |
11116 | enum pipe pipe, tracked_pipe; | |
11117 | ||
11118 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11119 | encoder->base.base.id, | |
8e329a03 | 11120 | encoder->base.name); |
8af6cf88 | 11121 | |
e2c719b7 | 11122 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11123 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11124 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11125 | "encoder's active_connectors set, but no crtc\n"); |
11126 | ||
3a3371ff | 11127 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11128 | if (connector->base.encoder != &encoder->base) |
11129 | continue; | |
11130 | enabled = true; | |
11131 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11132 | active = true; | |
11133 | } | |
0e32b39c DA |
11134 | /* |
11135 | * for MST connectors if we unplug the connector is gone | |
11136 | * away but the encoder is still connected to a crtc | |
11137 | * until a modeset happens in response to the hotplug. | |
11138 | */ | |
11139 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11140 | continue; | |
11141 | ||
e2c719b7 | 11142 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11143 | "encoder's enabled state mismatch " |
11144 | "(expected %i, found %i)\n", | |
11145 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11146 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11147 | "active encoder with no crtc\n"); |
11148 | ||
e2c719b7 | 11149 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11150 | "encoder's computed active state doesn't match tracked active state " |
11151 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
11152 | ||
11153 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 11154 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
11155 | "encoder's hw state doesn't match sw tracking " |
11156 | "(expected %i, found %i)\n", | |
11157 | encoder->connectors_active, active); | |
11158 | ||
11159 | if (!encoder->base.crtc) | |
11160 | continue; | |
11161 | ||
11162 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 11163 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
11164 | "active encoder's pipe doesn't match" |
11165 | "(expected %i, found %i)\n", | |
11166 | tracked_pipe, pipe); | |
11167 | ||
11168 | } | |
91d1b4bd DV |
11169 | } |
11170 | ||
11171 | static void | |
11172 | check_crtc_state(struct drm_device *dev) | |
11173 | { | |
fbee40df | 11174 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11175 | struct intel_crtc *crtc; |
11176 | struct intel_encoder *encoder; | |
5cec258b | 11177 | struct intel_crtc_state pipe_config; |
8af6cf88 | 11178 | |
d3fcc808 | 11179 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
11180 | bool enabled = false; |
11181 | bool active = false; | |
11182 | ||
045ac3b5 JB |
11183 | memset(&pipe_config, 0, sizeof(pipe_config)); |
11184 | ||
8af6cf88 DV |
11185 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
11186 | crtc->base.base.id); | |
11187 | ||
83d65738 | 11188 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
11189 | "active crtc, but not enabled in sw tracking\n"); |
11190 | ||
b2784e15 | 11191 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11192 | if (encoder->base.crtc != &crtc->base) |
11193 | continue; | |
11194 | enabled = true; | |
11195 | if (encoder->connectors_active) | |
11196 | active = true; | |
11197 | } | |
6c49f241 | 11198 | |
e2c719b7 | 11199 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
11200 | "crtc's computed active state doesn't match tracked active state " |
11201 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 11202 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 11203 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
11204 | "(expected %i, found %i)\n", enabled, |
11205 | crtc->base.state->enable); | |
8af6cf88 | 11206 | |
0e8ffe1b DV |
11207 | active = dev_priv->display.get_pipe_config(crtc, |
11208 | &pipe_config); | |
d62cf62a | 11209 | |
b6b5d049 VS |
11210 | /* hw state is inconsistent with the pipe quirk */ |
11211 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11212 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
11213 | active = crtc->active; |
11214 | ||
b2784e15 | 11215 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 11216 | enum pipe pipe; |
6c49f241 DV |
11217 | if (encoder->base.crtc != &crtc->base) |
11218 | continue; | |
1d37b689 | 11219 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
11220 | encoder->get_config(encoder, &pipe_config); |
11221 | } | |
11222 | ||
e2c719b7 | 11223 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
11224 | "crtc active state doesn't match with hw state " |
11225 | "(expected %i, found %i)\n", crtc->active, active); | |
11226 | ||
c0b03411 | 11227 | if (active && |
6e3c9717 | 11228 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 11229 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
11230 | intel_dump_pipe_config(crtc, &pipe_config, |
11231 | "[hw state]"); | |
6e3c9717 | 11232 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
11233 | "[sw state]"); |
11234 | } | |
8af6cf88 DV |
11235 | } |
11236 | } | |
11237 | ||
91d1b4bd DV |
11238 | static void |
11239 | check_shared_dpll_state(struct drm_device *dev) | |
11240 | { | |
fbee40df | 11241 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
11242 | struct intel_crtc *crtc; |
11243 | struct intel_dpll_hw_state dpll_hw_state; | |
11244 | int i; | |
5358901f DV |
11245 | |
11246 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
11247 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11248 | int enabled_crtcs = 0, active_crtcs = 0; | |
11249 | bool active; | |
11250 | ||
11251 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
11252 | ||
11253 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11254 | ||
11255 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11256 | ||
e2c719b7 | 11257 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 11258 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 11259 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 11260 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 11261 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 11262 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 11263 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 11264 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
11265 | "pll on state mismatch (expected %i, found %i)\n", |
11266 | pll->on, active); | |
11267 | ||
d3fcc808 | 11268 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11269 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
11270 | enabled_crtcs++; |
11271 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11272 | active_crtcs++; | |
11273 | } | |
e2c719b7 | 11274 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
11275 | "pll active crtcs mismatch (expected %i, found %i)\n", |
11276 | pll->active, active_crtcs); | |
e2c719b7 | 11277 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 11278 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 11279 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 11280 | |
e2c719b7 | 11281 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
11282 | sizeof(dpll_hw_state)), |
11283 | "pll hw state mismatch\n"); | |
5358901f | 11284 | } |
8af6cf88 DV |
11285 | } |
11286 | ||
91d1b4bd DV |
11287 | void |
11288 | intel_modeset_check_state(struct drm_device *dev) | |
11289 | { | |
08db6652 | 11290 | check_wm_state(dev); |
91d1b4bd DV |
11291 | check_connector_state(dev); |
11292 | check_encoder_state(dev); | |
11293 | check_crtc_state(dev); | |
11294 | check_shared_dpll_state(dev); | |
11295 | } | |
11296 | ||
5cec258b | 11297 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
11298 | int dotclock) |
11299 | { | |
11300 | /* | |
11301 | * FDI already provided one idea for the dotclock. | |
11302 | * Yell if the encoder disagrees. | |
11303 | */ | |
2d112de7 | 11304 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11305 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 11306 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11307 | } |
11308 | ||
80715b2f VS |
11309 | static void update_scanline_offset(struct intel_crtc *crtc) |
11310 | { | |
11311 | struct drm_device *dev = crtc->base.dev; | |
11312 | ||
11313 | /* | |
11314 | * The scanline counter increments at the leading edge of hsync. | |
11315 | * | |
11316 | * On most platforms it starts counting from vtotal-1 on the | |
11317 | * first active line. That means the scanline counter value is | |
11318 | * always one less than what we would expect. Ie. just after | |
11319 | * start of vblank, which also occurs at start of hsync (on the | |
11320 | * last active line), the scanline counter will read vblank_start-1. | |
11321 | * | |
11322 | * On gen2 the scanline counter starts counting from 1 instead | |
11323 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11324 | * to keep the value positive), instead of adding one. | |
11325 | * | |
11326 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11327 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11328 | * there's an extra 1 line difference. So we need to add two instead of | |
11329 | * one to the value. | |
11330 | */ | |
11331 | if (IS_GEN2(dev)) { | |
6e3c9717 | 11332 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11333 | int vtotal; |
11334 | ||
11335 | vtotal = mode->crtc_vtotal; | |
11336 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11337 | vtotal /= 2; | |
11338 | ||
11339 | crtc->scanline_offset = vtotal - 1; | |
11340 | } else if (HAS_DDI(dev) && | |
409ee761 | 11341 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11342 | crtc->scanline_offset = 2; |
11343 | } else | |
11344 | crtc->scanline_offset = 1; | |
11345 | } | |
11346 | ||
5cec258b | 11347 | static struct intel_crtc_state * |
7f27126e JB |
11348 | intel_modeset_compute_config(struct drm_crtc *crtc, |
11349 | struct drm_display_mode *mode, | |
11350 | struct drm_framebuffer *fb, | |
83a57153 | 11351 | struct drm_atomic_state *state, |
7f27126e JB |
11352 | unsigned *modeset_pipes, |
11353 | unsigned *prepare_pipes, | |
11354 | unsigned *disable_pipes) | |
11355 | { | |
db7542dd | 11356 | struct drm_device *dev = crtc->dev; |
5cec258b | 11357 | struct intel_crtc_state *pipe_config = NULL; |
db7542dd | 11358 | struct intel_crtc *intel_crtc; |
0b901879 ACO |
11359 | int ret = 0; |
11360 | ||
11361 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11362 | if (ret) | |
11363 | return ERR_PTR(ret); | |
7f27126e JB |
11364 | |
11365 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
11366 | prepare_pipes, disable_pipes); | |
11367 | ||
db7542dd ACO |
11368 | for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { |
11369 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11370 | if (IS_ERR(pipe_config)) | |
11371 | return pipe_config; | |
11372 | ||
11373 | pipe_config->base.enable = false; | |
11374 | } | |
7f27126e JB |
11375 | |
11376 | /* | |
11377 | * Note this needs changes when we start tracking multiple modes | |
11378 | * and crtcs. At that point we'll need to compute the whole config | |
11379 | * (i.e. one pipe_config for each crtc) rather than just the one | |
11380 | * for this crtc. | |
11381 | */ | |
db7542dd ACO |
11382 | for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { |
11383 | /* FIXME: For now we still expect modeset_pipes has at most | |
11384 | * one bit set. */ | |
11385 | if (WARN_ON(&intel_crtc->base != crtc)) | |
11386 | continue; | |
83a57153 | 11387 | |
db7542dd ACO |
11388 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state); |
11389 | if (IS_ERR(pipe_config)) | |
11390 | return pipe_config; | |
7f27126e | 11391 | |
db7542dd ACO |
11392 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11393 | "[modeset]"); | |
11394 | } | |
11395 | ||
11396 | return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));; | |
7f27126e JB |
11397 | } |
11398 | ||
ed6739ef ACO |
11399 | static int __intel_set_mode_setup_plls(struct drm_device *dev, |
11400 | unsigned modeset_pipes, | |
11401 | unsigned disable_pipes) | |
11402 | { | |
11403 | struct drm_i915_private *dev_priv = to_i915(dev); | |
11404 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
11405 | struct intel_crtc *intel_crtc; | |
11406 | int ret = 0; | |
11407 | ||
11408 | if (!dev_priv->display.crtc_compute_clock) | |
11409 | return 0; | |
11410 | ||
11411 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
11412 | if (ret) | |
11413 | goto done; | |
11414 | ||
11415 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
11416 | struct intel_crtc_state *state = intel_crtc->new_config; | |
11417 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11418 | state); | |
11419 | if (ret) { | |
11420 | intel_shared_dpll_abort_config(dev_priv); | |
11421 | goto done; | |
11422 | } | |
11423 | } | |
11424 | ||
11425 | done: | |
11426 | return ret; | |
11427 | } | |
11428 | ||
f30da187 DV |
11429 | static int __intel_set_mode(struct drm_crtc *crtc, |
11430 | struct drm_display_mode *mode, | |
7f27126e | 11431 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 11432 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11433 | unsigned modeset_pipes, |
11434 | unsigned prepare_pipes, | |
11435 | unsigned disable_pipes) | |
a6778b3c DV |
11436 | { |
11437 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11438 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11439 | struct drm_display_mode *saved_mode; |
83a57153 | 11440 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 11441 | struct intel_crtc *intel_crtc; |
c0c36b94 | 11442 | int ret = 0; |
a6778b3c | 11443 | |
4b4b9238 | 11444 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11445 | if (!saved_mode) |
11446 | return -ENOMEM; | |
a6778b3c | 11447 | |
83a57153 ACO |
11448 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
11449 | if (!crtc_state_copy) { | |
11450 | ret = -ENOMEM; | |
11451 | goto done; | |
11452 | } | |
11453 | ||
3ac18232 | 11454 | *saved_mode = crtc->mode; |
a6778b3c | 11455 | |
b9950a13 VS |
11456 | if (modeset_pipes) |
11457 | to_intel_crtc(crtc)->new_config = pipe_config; | |
11458 | ||
30a970c6 JB |
11459 | /* |
11460 | * See if the config requires any additional preparation, e.g. | |
11461 | * to adjust global state with pipes off. We need to do this | |
11462 | * here so we can get the modeset_pipe updated config for the new | |
11463 | * mode set on this crtc. For other crtcs we need to use the | |
11464 | * adjusted_mode bits in the crtc directly. | |
11465 | */ | |
c164f833 | 11466 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 11467 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 11468 | |
c164f833 VS |
11469 | /* may have added more to prepare_pipes than we should */ |
11470 | prepare_pipes &= ~disable_pipes; | |
11471 | } | |
11472 | ||
ed6739ef ACO |
11473 | ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes); |
11474 | if (ret) | |
11475 | goto done; | |
8bd31e67 | 11476 | |
460da916 DV |
11477 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11478 | intel_crtc_disable(&intel_crtc->base); | |
11479 | ||
ea9d758d | 11480 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
83d65738 | 11481 | if (intel_crtc->base.state->enable) |
ea9d758d DV |
11482 | dev_priv->display.crtc_disable(&intel_crtc->base); |
11483 | } | |
a6778b3c | 11484 | |
6c4c86f5 DV |
11485 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11486 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
11487 | * |
11488 | * Note we'll need to fix this up when we start tracking multiple | |
11489 | * pipes; here we assume a single modeset_pipe and only track the | |
11490 | * single crtc and mode. | |
f6e5b160 | 11491 | */ |
b8cecdf5 | 11492 | if (modeset_pipes) { |
25c5b266 | 11493 | crtc->mode = *mode; |
b8cecdf5 DV |
11494 | /* mode_set/enable/disable functions rely on a correct pipe |
11495 | * config. */ | |
f5de6e07 | 11496 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
11497 | |
11498 | /* | |
11499 | * Calculate and store various constants which | |
11500 | * are later needed by vblank and swap-completion | |
11501 | * timestamping. They are derived from true hwmode. | |
11502 | */ | |
11503 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 11504 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 11505 | } |
7758a113 | 11506 | |
ea9d758d DV |
11507 | /* Only after disabling all output pipelines that will be changed can we |
11508 | * update the the output configuration. */ | |
11509 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11510 | |
679dacd4 | 11511 | modeset_update_crtc_power_domains(pipe_config->base.state); |
47fab737 | 11512 | |
a6778b3c DV |
11513 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11514 | * on the DPLL. | |
f6e5b160 | 11515 | */ |
25c5b266 | 11516 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11517 | struct drm_plane *primary = intel_crtc->base.primary; |
11518 | int vdisplay, hdisplay; | |
4c10794f | 11519 | |
455a6808 GP |
11520 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11521 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11522 | fb, 0, 0, | |
11523 | hdisplay, vdisplay, | |
11524 | x << 16, y << 16, | |
11525 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11526 | } |
11527 | ||
11528 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11529 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11530 | update_scanline_offset(intel_crtc); | |
11531 | ||
25c5b266 | 11532 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11533 | } |
a6778b3c | 11534 | |
a6778b3c DV |
11535 | /* FIXME: add subpixel order */ |
11536 | done: | |
83d65738 | 11537 | if (ret && crtc->state->enable) |
3ac18232 | 11538 | crtc->mode = *saved_mode; |
a6778b3c | 11539 | |
83a57153 ACO |
11540 | if (ret == 0 && pipe_config) { |
11541 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11542 | ||
11543 | /* The pipe_config will be freed with the atomic state, so | |
11544 | * make a copy. */ | |
11545 | memcpy(crtc_state_copy, intel_crtc->config, | |
11546 | sizeof *crtc_state_copy); | |
11547 | intel_crtc->config = crtc_state_copy; | |
11548 | intel_crtc->base.state = &crtc_state_copy->base; | |
11549 | ||
11550 | if (modeset_pipes) | |
11551 | intel_crtc->new_config = intel_crtc->config; | |
11552 | } else { | |
11553 | kfree(crtc_state_copy); | |
11554 | } | |
11555 | ||
3ac18232 | 11556 | kfree(saved_mode); |
a6778b3c | 11557 | return ret; |
f6e5b160 CW |
11558 | } |
11559 | ||
7f27126e JB |
11560 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11561 | struct drm_display_mode *mode, | |
11562 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 11563 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
11564 | unsigned modeset_pipes, |
11565 | unsigned prepare_pipes, | |
11566 | unsigned disable_pipes) | |
f30da187 DV |
11567 | { |
11568 | int ret; | |
11569 | ||
7f27126e JB |
11570 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11571 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11572 | |
11573 | if (ret == 0) | |
11574 | intel_modeset_check_state(crtc->dev); | |
11575 | ||
11576 | return ret; | |
11577 | } | |
11578 | ||
7f27126e JB |
11579 | static int intel_set_mode(struct drm_crtc *crtc, |
11580 | struct drm_display_mode *mode, | |
83a57153 ACO |
11581 | int x, int y, struct drm_framebuffer *fb, |
11582 | struct drm_atomic_state *state) | |
7f27126e | 11583 | { |
5cec258b | 11584 | struct intel_crtc_state *pipe_config; |
7f27126e | 11585 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 11586 | int ret = 0; |
7f27126e | 11587 | |
83a57153 | 11588 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, state, |
7f27126e JB |
11589 | &modeset_pipes, |
11590 | &prepare_pipes, | |
11591 | &disable_pipes); | |
11592 | ||
83a57153 ACO |
11593 | if (IS_ERR(pipe_config)) { |
11594 | ret = PTR_ERR(pipe_config); | |
11595 | goto out; | |
11596 | } | |
11597 | ||
11598 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11599 | modeset_pipes, prepare_pipes, | |
11600 | disable_pipes); | |
11601 | if (ret) | |
11602 | goto out; | |
7f27126e | 11603 | |
83a57153 ACO |
11604 | out: |
11605 | return ret; | |
7f27126e JB |
11606 | } |
11607 | ||
c0c36b94 CW |
11608 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11609 | { | |
83a57153 ACO |
11610 | struct drm_device *dev = crtc->dev; |
11611 | struct drm_atomic_state *state; | |
11612 | struct intel_encoder *encoder; | |
11613 | struct intel_connector *connector; | |
11614 | struct drm_connector_state *connector_state; | |
11615 | ||
11616 | state = drm_atomic_state_alloc(dev); | |
11617 | if (!state) { | |
11618 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
11619 | crtc->base.id); | |
11620 | return; | |
11621 | } | |
11622 | ||
11623 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
11624 | ||
11625 | /* The force restore path in the HW readout code relies on the staged | |
11626 | * config still keeping the user requested config while the actual | |
11627 | * state has been overwritten by the configuration read from HW. We | |
11628 | * need to copy the staged config to the atomic state, otherwise the | |
11629 | * mode set will just reapply the state the HW is already in. */ | |
11630 | for_each_intel_encoder(dev, encoder) { | |
11631 | if (&encoder->new_crtc->base != crtc) | |
11632 | continue; | |
11633 | ||
11634 | for_each_intel_connector(dev, connector) { | |
11635 | if (connector->new_encoder != encoder) | |
11636 | continue; | |
11637 | ||
11638 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
11639 | if (IS_ERR(connector_state)) { | |
11640 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
11641 | connector->base.base.id, | |
11642 | connector->base.name, | |
11643 | PTR_ERR(connector_state)); | |
11644 | continue; | |
11645 | } | |
11646 | ||
11647 | connector_state->crtc = crtc; | |
11648 | connector_state->best_encoder = &encoder->base; | |
11649 | } | |
11650 | } | |
11651 | ||
11652 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, | |
11653 | state); | |
11654 | ||
11655 | drm_atomic_state_free(state); | |
c0c36b94 CW |
11656 | } |
11657 | ||
25c5b266 DV |
11658 | #undef for_each_intel_crtc_masked |
11659 | ||
d9e55608 DV |
11660 | static void intel_set_config_free(struct intel_set_config *config) |
11661 | { | |
11662 | if (!config) | |
11663 | return; | |
11664 | ||
1aa4b628 DV |
11665 | kfree(config->save_connector_encoders); |
11666 | kfree(config->save_encoder_crtcs); | |
7668851f | 11667 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11668 | kfree(config); |
11669 | } | |
11670 | ||
85f9eb71 DV |
11671 | static int intel_set_config_save_state(struct drm_device *dev, |
11672 | struct intel_set_config *config) | |
11673 | { | |
7668851f | 11674 | struct drm_crtc *crtc; |
85f9eb71 DV |
11675 | struct drm_encoder *encoder; |
11676 | struct drm_connector *connector; | |
11677 | int count; | |
11678 | ||
7668851f VS |
11679 | config->save_crtc_enabled = |
11680 | kcalloc(dev->mode_config.num_crtc, | |
11681 | sizeof(bool), GFP_KERNEL); | |
11682 | if (!config->save_crtc_enabled) | |
11683 | return -ENOMEM; | |
11684 | ||
1aa4b628 DV |
11685 | config->save_encoder_crtcs = |
11686 | kcalloc(dev->mode_config.num_encoder, | |
11687 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11688 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11689 | return -ENOMEM; |
11690 | ||
1aa4b628 DV |
11691 | config->save_connector_encoders = |
11692 | kcalloc(dev->mode_config.num_connector, | |
11693 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11694 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11695 | return -ENOMEM; |
11696 | ||
11697 | /* Copy data. Note that driver private data is not affected. | |
11698 | * Should anything bad happen only the expected state is | |
11699 | * restored, not the drivers personal bookkeeping. | |
11700 | */ | |
7668851f | 11701 | count = 0; |
70e1e0ec | 11702 | for_each_crtc(dev, crtc) { |
83d65738 | 11703 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
11704 | } |
11705 | ||
85f9eb71 DV |
11706 | count = 0; |
11707 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11708 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11709 | } |
11710 | ||
11711 | count = 0; | |
11712 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11713 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11714 | } |
11715 | ||
11716 | return 0; | |
11717 | } | |
11718 | ||
11719 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11720 | struct intel_set_config *config) | |
11721 | { | |
7668851f | 11722 | struct intel_crtc *crtc; |
9a935856 DV |
11723 | struct intel_encoder *encoder; |
11724 | struct intel_connector *connector; | |
85f9eb71 DV |
11725 | int count; |
11726 | ||
7668851f | 11727 | count = 0; |
d3fcc808 | 11728 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11729 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11730 | |
11731 | if (crtc->new_enabled) | |
6e3c9717 | 11732 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11733 | else |
11734 | crtc->new_config = NULL; | |
7668851f VS |
11735 | } |
11736 | ||
85f9eb71 | 11737 | count = 0; |
b2784e15 | 11738 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11739 | encoder->new_crtc = |
11740 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11741 | } |
11742 | ||
11743 | count = 0; | |
3a3371ff | 11744 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11745 | connector->new_encoder = |
11746 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11747 | } |
11748 | } | |
11749 | ||
e3de42b6 | 11750 | static bool |
2e57f47d | 11751 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11752 | { |
11753 | int i; | |
11754 | ||
2e57f47d CW |
11755 | if (set->num_connectors == 0) |
11756 | return false; | |
11757 | ||
11758 | if (WARN_ON(set->connectors == NULL)) | |
11759 | return false; | |
11760 | ||
11761 | for (i = 0; i < set->num_connectors; i++) | |
11762 | if (set->connectors[i]->encoder && | |
11763 | set->connectors[i]->encoder->crtc == set->crtc && | |
11764 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11765 | return true; |
11766 | ||
11767 | return false; | |
11768 | } | |
11769 | ||
5e2b584e DV |
11770 | static void |
11771 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11772 | struct intel_set_config *config) | |
11773 | { | |
11774 | ||
11775 | /* We should be able to check here if the fb has the same properties | |
11776 | * and then just flip_or_move it */ | |
2e57f47d CW |
11777 | if (is_crtc_connector_off(set)) { |
11778 | config->mode_changed = true; | |
f4510a27 | 11779 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11780 | /* |
11781 | * If we have no fb, we can only flip as long as the crtc is | |
11782 | * active, otherwise we need a full mode set. The crtc may | |
11783 | * be active if we've only disabled the primary plane, or | |
11784 | * in fastboot situations. | |
11785 | */ | |
f4510a27 | 11786 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11787 | struct intel_crtc *intel_crtc = |
11788 | to_intel_crtc(set->crtc); | |
11789 | ||
3b150f08 | 11790 | if (intel_crtc->active) { |
319d9827 JB |
11791 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11792 | config->fb_changed = true; | |
11793 | } else { | |
11794 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11795 | config->mode_changed = true; | |
11796 | } | |
5e2b584e DV |
11797 | } else if (set->fb == NULL) { |
11798 | config->mode_changed = true; | |
72f4901e | 11799 | } else if (set->fb->pixel_format != |
f4510a27 | 11800 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11801 | config->mode_changed = true; |
e3de42b6 | 11802 | } else { |
5e2b584e | 11803 | config->fb_changed = true; |
e3de42b6 | 11804 | } |
5e2b584e DV |
11805 | } |
11806 | ||
835c5873 | 11807 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11808 | config->fb_changed = true; |
11809 | ||
11810 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11811 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11812 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11813 | drm_mode_debug_printmodeline(set->mode); | |
11814 | config->mode_changed = true; | |
11815 | } | |
a1d95703 CW |
11816 | |
11817 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11818 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11819 | } |
11820 | ||
2e431051 | 11821 | static int |
9a935856 DV |
11822 | intel_modeset_stage_output_state(struct drm_device *dev, |
11823 | struct drm_mode_set *set, | |
944b0c76 ACO |
11824 | struct intel_set_config *config, |
11825 | struct drm_atomic_state *state) | |
50f56119 | 11826 | { |
9a935856 | 11827 | struct intel_connector *connector; |
944b0c76 | 11828 | struct drm_connector_state *connector_state; |
9a935856 | 11829 | struct intel_encoder *encoder; |
7668851f | 11830 | struct intel_crtc *crtc; |
f3f08572 | 11831 | int ro; |
50f56119 | 11832 | |
9abdda74 | 11833 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11834 | * of connectors. For paranoia, double-check this. */ |
11835 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11836 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11837 | ||
3a3371ff | 11838 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11839 | /* Otherwise traverse passed in connector list and get encoders |
11840 | * for them. */ | |
50f56119 | 11841 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11842 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11843 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11844 | break; |
11845 | } | |
11846 | } | |
11847 | ||
9a935856 DV |
11848 | /* If we disable the crtc, disable all its connectors. Also, if |
11849 | * the connector is on the changing crtc but not on the new | |
11850 | * connector list, disable it. */ | |
11851 | if ((!set->fb || ro == set->num_connectors) && | |
11852 | connector->base.encoder && | |
11853 | connector->base.encoder->crtc == set->crtc) { | |
11854 | connector->new_encoder = NULL; | |
11855 | ||
11856 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11857 | connector->base.base.id, | |
c23cc417 | 11858 | connector->base.name); |
9a935856 DV |
11859 | } |
11860 | ||
11861 | ||
11862 | if (&connector->new_encoder->base != connector->base.encoder) { | |
10634189 ACO |
11863 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", |
11864 | connector->base.base.id, | |
11865 | connector->base.name); | |
5e2b584e | 11866 | config->mode_changed = true; |
50f56119 DV |
11867 | } |
11868 | } | |
9a935856 | 11869 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11870 | |
9a935856 | 11871 | /* Update crtc of enabled connectors. */ |
3a3371ff | 11872 | for_each_intel_connector(dev, connector) { |
7668851f VS |
11873 | struct drm_crtc *new_crtc; |
11874 | ||
9a935856 | 11875 | if (!connector->new_encoder) |
50f56119 DV |
11876 | continue; |
11877 | ||
9a935856 | 11878 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11879 | |
11880 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11881 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11882 | new_crtc = set->crtc; |
11883 | } | |
11884 | ||
11885 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11886 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11887 | new_crtc)) { | |
5e2b584e | 11888 | return -EINVAL; |
50f56119 | 11889 | } |
0e32b39c | 11890 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 11891 | |
944b0c76 ACO |
11892 | connector_state = |
11893 | drm_atomic_get_connector_state(state, &connector->base); | |
11894 | if (IS_ERR(connector_state)) | |
11895 | return PTR_ERR(connector_state); | |
11896 | ||
11897 | connector_state->crtc = new_crtc; | |
11898 | connector_state->best_encoder = &connector->new_encoder->base; | |
11899 | ||
9a935856 DV |
11900 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
11901 | connector->base.base.id, | |
c23cc417 | 11902 | connector->base.name, |
9a935856 DV |
11903 | new_crtc->base.id); |
11904 | } | |
11905 | ||
11906 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11907 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11908 | int num_connectors = 0; |
3a3371ff | 11909 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11910 | if (connector->new_encoder == encoder) { |
11911 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11912 | num_connectors++; |
9a935856 DV |
11913 | } |
11914 | } | |
5a65f358 PZ |
11915 | |
11916 | if (num_connectors == 0) | |
11917 | encoder->new_crtc = NULL; | |
11918 | else if (num_connectors > 1) | |
11919 | return -EINVAL; | |
11920 | ||
9a935856 DV |
11921 | /* Only now check for crtc changes so we don't miss encoders |
11922 | * that will be disabled. */ | |
11923 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
10634189 ACO |
11924 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", |
11925 | encoder->base.base.id, | |
11926 | encoder->base.name); | |
5e2b584e | 11927 | config->mode_changed = true; |
50f56119 DV |
11928 | } |
11929 | } | |
9a935856 | 11930 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 11931 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
11932 | connector_state = |
11933 | drm_atomic_get_connector_state(state, &connector->base); | |
11934 | ||
11935 | if (connector->new_encoder) { | |
0e32b39c DA |
11936 | if (connector->new_encoder != connector->encoder) |
11937 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
11938 | } else { |
11939 | connector_state->crtc = NULL; | |
11940 | } | |
0e32b39c | 11941 | } |
d3fcc808 | 11942 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11943 | crtc->new_enabled = false; |
11944 | ||
b2784e15 | 11945 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11946 | if (encoder->new_crtc == crtc) { |
11947 | crtc->new_enabled = true; | |
11948 | break; | |
11949 | } | |
11950 | } | |
11951 | ||
83d65738 | 11952 | if (crtc->new_enabled != crtc->base.state->enable) { |
10634189 ACO |
11953 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", |
11954 | crtc->base.base.id, | |
7668851f VS |
11955 | crtc->new_enabled ? "en" : "dis"); |
11956 | config->mode_changed = true; | |
11957 | } | |
7bd0a8e7 VS |
11958 | |
11959 | if (crtc->new_enabled) | |
6e3c9717 | 11960 | crtc->new_config = crtc->config; |
7bd0a8e7 VS |
11961 | else |
11962 | crtc->new_config = NULL; | |
7668851f VS |
11963 | } |
11964 | ||
2e431051 DV |
11965 | return 0; |
11966 | } | |
11967 | ||
7d00a1f5 VS |
11968 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11969 | { | |
11970 | struct drm_device *dev = crtc->base.dev; | |
11971 | struct intel_encoder *encoder; | |
11972 | struct intel_connector *connector; | |
11973 | ||
11974 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11975 | pipe_name(crtc->pipe)); | |
11976 | ||
3a3371ff | 11977 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
11978 | if (connector->new_encoder && |
11979 | connector->new_encoder->new_crtc == crtc) | |
11980 | connector->new_encoder = NULL; | |
11981 | } | |
11982 | ||
b2784e15 | 11983 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11984 | if (encoder->new_crtc == crtc) |
11985 | encoder->new_crtc = NULL; | |
11986 | } | |
11987 | ||
11988 | crtc->new_enabled = false; | |
7bd0a8e7 | 11989 | crtc->new_config = NULL; |
7d00a1f5 VS |
11990 | } |
11991 | ||
2e431051 DV |
11992 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11993 | { | |
11994 | struct drm_device *dev; | |
2e431051 | 11995 | struct drm_mode_set save_set; |
83a57153 | 11996 | struct drm_atomic_state *state = NULL; |
2e431051 | 11997 | struct intel_set_config *config; |
5cec258b | 11998 | struct intel_crtc_state *pipe_config; |
50f52756 | 11999 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12000 | int ret; |
2e431051 | 12001 | |
8d3e375e DV |
12002 | BUG_ON(!set); |
12003 | BUG_ON(!set->crtc); | |
12004 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12005 | |
7e53f3a4 DV |
12006 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12007 | BUG_ON(!set->mode && set->fb); | |
12008 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12009 | |
2e431051 DV |
12010 | if (set->fb) { |
12011 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12012 | set->crtc->base.id, set->fb->base.id, | |
12013 | (int)set->num_connectors, set->x, set->y); | |
12014 | } else { | |
12015 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12016 | } |
12017 | ||
12018 | dev = set->crtc->dev; | |
12019 | ||
12020 | ret = -ENOMEM; | |
12021 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12022 | if (!config) | |
12023 | goto out_config; | |
12024 | ||
12025 | ret = intel_set_config_save_state(dev, config); | |
12026 | if (ret) | |
12027 | goto out_config; | |
12028 | ||
12029 | save_set.crtc = set->crtc; | |
12030 | save_set.mode = &set->crtc->mode; | |
12031 | save_set.x = set->crtc->x; | |
12032 | save_set.y = set->crtc->y; | |
f4510a27 | 12033 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
12034 | |
12035 | /* Compute whether we need a full modeset, only an fb base update or no | |
12036 | * change at all. In the future we might also check whether only the | |
12037 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12038 | * such cases. */ | |
12039 | intel_set_config_compute_mode_changes(set, config); | |
12040 | ||
83a57153 ACO |
12041 | state = drm_atomic_state_alloc(dev); |
12042 | if (!state) { | |
12043 | ret = -ENOMEM; | |
12044 | goto out_config; | |
12045 | } | |
12046 | ||
12047 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12048 | ||
944b0c76 | 12049 | ret = intel_modeset_stage_output_state(dev, set, config, state); |
2e431051 DV |
12050 | if (ret) |
12051 | goto fail; | |
12052 | ||
50f52756 | 12053 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
83a57153 | 12054 | set->fb, state, |
50f52756 JB |
12055 | &modeset_pipes, |
12056 | &prepare_pipes, | |
12057 | &disable_pipes); | |
20664591 | 12058 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12059 | ret = PTR_ERR(pipe_config); |
50f52756 | 12060 | goto fail; |
20664591 | 12061 | } else if (pipe_config) { |
b9950a13 | 12062 | if (pipe_config->has_audio != |
6e3c9717 | 12063 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12064 | config->mode_changed = true; |
12065 | ||
af15d2ce JB |
12066 | /* |
12067 | * Note we have an issue here with infoframes: current code | |
12068 | * only updates them on the full mode set path per hw | |
12069 | * requirements. So here we should be checking for any | |
12070 | * required changes and forcing a mode set. | |
12071 | */ | |
20664591 | 12072 | } |
50f52756 | 12073 | |
1f9954d0 JB |
12074 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12075 | ||
5e2b584e | 12076 | if (config->mode_changed) { |
50f52756 JB |
12077 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12078 | set->x, set->y, set->fb, pipe_config, | |
12079 | modeset_pipes, prepare_pipes, | |
12080 | disable_pipes); | |
5e2b584e | 12081 | } else if (config->fb_changed) { |
3b150f08 | 12082 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
12083 | struct drm_plane *primary = set->crtc->primary; |
12084 | int vdisplay, hdisplay; | |
3b150f08 | 12085 | |
455a6808 GP |
12086 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
12087 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
12088 | 0, 0, hdisplay, vdisplay, | |
12089 | set->x << 16, set->y << 16, | |
12090 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12091 | |
12092 | /* | |
12093 | * We need to make sure the primary plane is re-enabled if it | |
12094 | * has previously been turned off. | |
12095 | */ | |
12096 | if (!intel_crtc->primary_enabled && ret == 0) { | |
12097 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 12098 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
12099 | } |
12100 | ||
7ca51a3a JB |
12101 | /* |
12102 | * In the fastboot case this may be our only check of the | |
12103 | * state after boot. It would be better to only do it on | |
12104 | * the first update, but we don't have a nice way of doing that | |
12105 | * (and really, set_config isn't used much for high freq page | |
12106 | * flipping, so increasing its cost here shouldn't be a big | |
12107 | * deal). | |
12108 | */ | |
d330a953 | 12109 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12110 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12111 | } |
12112 | ||
2d05eae1 | 12113 | if (ret) { |
bf67dfeb DV |
12114 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12115 | set->crtc->base.id, ret); | |
50f56119 | 12116 | fail: |
2d05eae1 | 12117 | intel_set_config_restore_state(dev, config); |
50f56119 | 12118 | |
83a57153 ACO |
12119 | drm_atomic_state_clear(state); |
12120 | ||
7d00a1f5 VS |
12121 | /* |
12122 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12123 | * force the pipe off to avoid oopsing in the modeset code | |
12124 | * due to fb==NULL. This should only happen during boot since | |
12125 | * we don't yet reconstruct the FB from the hardware state. | |
12126 | */ | |
12127 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12128 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
12129 | ||
2d05eae1 CW |
12130 | /* Try to restore the config */ |
12131 | if (config->mode_changed && | |
12132 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
12133 | save_set.x, save_set.y, save_set.fb, |
12134 | state)) | |
2d05eae1 CW |
12135 | DRM_ERROR("failed to restore config after modeset failure\n"); |
12136 | } | |
50f56119 | 12137 | |
d9e55608 | 12138 | out_config: |
83a57153 ACO |
12139 | if (state) |
12140 | drm_atomic_state_free(state); | |
12141 | ||
d9e55608 | 12142 | intel_set_config_free(config); |
50f56119 DV |
12143 | return ret; |
12144 | } | |
f6e5b160 CW |
12145 | |
12146 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 12147 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 12148 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
12149 | .destroy = intel_crtc_destroy, |
12150 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
12151 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12152 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
12153 | }; |
12154 | ||
5358901f DV |
12155 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
12156 | struct intel_shared_dpll *pll, | |
12157 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 12158 | { |
5358901f | 12159 | uint32_t val; |
ee7b9f93 | 12160 | |
f458ebbc | 12161 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
12162 | return false; |
12163 | ||
5358901f | 12164 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
12165 | hw_state->dpll = val; |
12166 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
12167 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
12168 | |
12169 | return val & DPLL_VCO_ENABLE; | |
12170 | } | |
12171 | ||
15bdd4cf DV |
12172 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
12173 | struct intel_shared_dpll *pll) | |
12174 | { | |
3e369b76 ACO |
12175 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
12176 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
12177 | } |
12178 | ||
e7b903d2 DV |
12179 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
12180 | struct intel_shared_dpll *pll) | |
12181 | { | |
e7b903d2 | 12182 | /* PCH refclock must be enabled first */ |
89eff4be | 12183 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 12184 | |
3e369b76 | 12185 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
12186 | |
12187 | /* Wait for the clocks to stabilize. */ | |
12188 | POSTING_READ(PCH_DPLL(pll->id)); | |
12189 | udelay(150); | |
12190 | ||
12191 | /* The pixel multiplier can only be updated once the | |
12192 | * DPLL is enabled and the clocks are stable. | |
12193 | * | |
12194 | * So write it again. | |
12195 | */ | |
3e369b76 | 12196 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 12197 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
12198 | udelay(200); |
12199 | } | |
12200 | ||
12201 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
12202 | struct intel_shared_dpll *pll) | |
12203 | { | |
12204 | struct drm_device *dev = dev_priv->dev; | |
12205 | struct intel_crtc *crtc; | |
e7b903d2 DV |
12206 | |
12207 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 12208 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
12209 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
12210 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
12211 | } |
12212 | ||
15bdd4cf DV |
12213 | I915_WRITE(PCH_DPLL(pll->id), 0); |
12214 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
12215 | udelay(200); |
12216 | } | |
12217 | ||
46edb027 DV |
12218 | static char *ibx_pch_dpll_names[] = { |
12219 | "PCH DPLL A", | |
12220 | "PCH DPLL B", | |
12221 | }; | |
12222 | ||
7c74ade1 | 12223 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 12224 | { |
e7b903d2 | 12225 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
12226 | int i; |
12227 | ||
7c74ade1 | 12228 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 12229 | |
e72f9fbf | 12230 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
12231 | dev_priv->shared_dplls[i].id = i; |
12232 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 12233 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
12234 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
12235 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
12236 | dev_priv->shared_dplls[i].get_hw_state = |
12237 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
12238 | } |
12239 | } | |
12240 | ||
7c74ade1 DV |
12241 | static void intel_shared_dpll_init(struct drm_device *dev) |
12242 | { | |
e7b903d2 | 12243 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 12244 | |
9cd86933 DV |
12245 | if (HAS_DDI(dev)) |
12246 | intel_ddi_pll_init(dev); | |
12247 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
12248 | ibx_pch_dpll_init(dev); |
12249 | else | |
12250 | dev_priv->num_shared_dpll = 0; | |
12251 | ||
12252 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
12253 | } |
12254 | ||
1fc0a8f7 TU |
12255 | /** |
12256 | * intel_wm_need_update - Check whether watermarks need updating | |
12257 | * @plane: drm plane | |
12258 | * @state: new plane state | |
12259 | * | |
12260 | * Check current plane state versus the new one to determine whether | |
12261 | * watermarks need to be recalculated. | |
12262 | * | |
12263 | * Returns true or false. | |
12264 | */ | |
12265 | bool intel_wm_need_update(struct drm_plane *plane, | |
12266 | struct drm_plane_state *state) | |
12267 | { | |
12268 | /* Update watermarks on tiling changes. */ | |
12269 | if (!plane->state->fb || !state->fb || | |
12270 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
12271 | plane->state->rotation != state->rotation) | |
12272 | return true; | |
12273 | ||
12274 | return false; | |
12275 | } | |
12276 | ||
6beb8c23 MR |
12277 | /** |
12278 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12279 | * @plane: drm plane to prepare for | |
12280 | * @fb: framebuffer to prepare for presentation | |
12281 | * | |
12282 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12283 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12284 | * bits. Some older platforms need special physical address handling for | |
12285 | * cursor planes. | |
12286 | * | |
12287 | * Returns 0 on success, negative error code on failure. | |
12288 | */ | |
12289 | int | |
12290 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12291 | struct drm_framebuffer *fb, |
12292 | const struct drm_plane_state *new_state) | |
465c120c MR |
12293 | { |
12294 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
12295 | struct intel_plane *intel_plane = to_intel_plane(plane); |
12296 | enum pipe pipe = intel_plane->pipe; | |
12297 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12298 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
12299 | unsigned frontbuffer_bits = 0; | |
12300 | int ret = 0; | |
465c120c | 12301 | |
ea2c67bb | 12302 | if (!obj) |
465c120c MR |
12303 | return 0; |
12304 | ||
6beb8c23 MR |
12305 | switch (plane->type) { |
12306 | case DRM_PLANE_TYPE_PRIMARY: | |
12307 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
12308 | break; | |
12309 | case DRM_PLANE_TYPE_CURSOR: | |
12310 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
12311 | break; | |
12312 | case DRM_PLANE_TYPE_OVERLAY: | |
12313 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
12314 | break; | |
12315 | } | |
465c120c | 12316 | |
6beb8c23 | 12317 | mutex_lock(&dev->struct_mutex); |
465c120c | 12318 | |
6beb8c23 MR |
12319 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12320 | INTEL_INFO(dev)->cursor_needs_physical) { | |
12321 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
12322 | ret = i915_gem_object_attach_phys(obj, align); | |
12323 | if (ret) | |
12324 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12325 | } else { | |
82bc3b2d | 12326 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 12327 | } |
465c120c | 12328 | |
6beb8c23 MR |
12329 | if (ret == 0) |
12330 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 12331 | |
4c34574f | 12332 | mutex_unlock(&dev->struct_mutex); |
465c120c | 12333 | |
6beb8c23 MR |
12334 | return ret; |
12335 | } | |
12336 | ||
38f3ce3a MR |
12337 | /** |
12338 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12339 | * @plane: drm plane to clean up for | |
12340 | * @fb: old framebuffer that was on plane | |
12341 | * | |
12342 | * Cleans up a framebuffer that has just been removed from a plane. | |
12343 | */ | |
12344 | void | |
12345 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
12346 | struct drm_framebuffer *fb, |
12347 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
12348 | { |
12349 | struct drm_device *dev = plane->dev; | |
12350 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12351 | ||
12352 | if (WARN_ON(!obj)) | |
12353 | return; | |
12354 | ||
12355 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
12356 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
12357 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 12358 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
12359 | mutex_unlock(&dev->struct_mutex); |
12360 | } | |
465c120c MR |
12361 | } |
12362 | ||
12363 | static int | |
3c692a41 GP |
12364 | intel_check_primary_plane(struct drm_plane *plane, |
12365 | struct intel_plane_state *state) | |
12366 | { | |
32b7eeec MR |
12367 | struct drm_device *dev = plane->dev; |
12368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 12369 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12370 | struct intel_crtc *intel_crtc; |
2b875c22 | 12371 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
12372 | struct drm_rect *dest = &state->dst; |
12373 | struct drm_rect *src = &state->src; | |
12374 | const struct drm_rect *clip = &state->clip; | |
465c120c MR |
12375 | int ret; |
12376 | ||
ea2c67bb MR |
12377 | crtc = crtc ? crtc : plane->crtc; |
12378 | intel_crtc = to_intel_crtc(crtc); | |
12379 | ||
c59cb179 MR |
12380 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
12381 | src, dest, clip, | |
12382 | DRM_PLANE_HELPER_NO_SCALING, | |
12383 | DRM_PLANE_HELPER_NO_SCALING, | |
12384 | false, true, &state->visible); | |
12385 | if (ret) | |
12386 | return ret; | |
465c120c | 12387 | |
32b7eeec MR |
12388 | if (intel_crtc->active) { |
12389 | intel_crtc->atomic.wait_for_flips = true; | |
12390 | ||
12391 | /* | |
12392 | * FBC does not work on some platforms for rotated | |
12393 | * planes, so disable it when rotation is not 0 and | |
12394 | * update it when rotation is set back to 0. | |
12395 | * | |
12396 | * FIXME: This is redundant with the fbc update done in | |
12397 | * the primary plane enable function except that that | |
12398 | * one is done too late. We eventually need to unify | |
12399 | * this. | |
12400 | */ | |
12401 | if (intel_crtc->primary_enabled && | |
12402 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
e35fef21 | 12403 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 12404 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
12405 | intel_crtc->atomic.disable_fbc = true; |
12406 | } | |
12407 | ||
12408 | if (state->visible) { | |
12409 | /* | |
12410 | * BDW signals flip done immediately if the plane | |
12411 | * is disabled, even if the plane enable is already | |
12412 | * armed to occur at the next vblank :( | |
12413 | */ | |
12414 | if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) | |
12415 | intel_crtc->atomic.wait_vblank = true; | |
12416 | } | |
12417 | ||
12418 | intel_crtc->atomic.fb_bits |= | |
12419 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
12420 | ||
12421 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 12422 | |
1fc0a8f7 | 12423 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 12424 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
12425 | } |
12426 | ||
14af293f GP |
12427 | return 0; |
12428 | } | |
12429 | ||
12430 | static void | |
12431 | intel_commit_primary_plane(struct drm_plane *plane, | |
12432 | struct intel_plane_state *state) | |
12433 | { | |
2b875c22 MR |
12434 | struct drm_crtc *crtc = state->base.crtc; |
12435 | struct drm_framebuffer *fb = state->base.fb; | |
12436 | struct drm_device *dev = plane->dev; | |
14af293f | 12437 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 12438 | struct intel_crtc *intel_crtc; |
14af293f GP |
12439 | struct drm_rect *src = &state->src; |
12440 | ||
ea2c67bb MR |
12441 | crtc = crtc ? crtc : plane->crtc; |
12442 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
12443 | |
12444 | plane->fb = fb; | |
9dc806fc MR |
12445 | crtc->x = src->x1 >> 16; |
12446 | crtc->y = src->y1 >> 16; | |
ccc759dc | 12447 | |
ccc759dc | 12448 | if (intel_crtc->active) { |
ccc759dc | 12449 | if (state->visible) { |
ccc759dc GP |
12450 | /* FIXME: kill this fastboot hack */ |
12451 | intel_update_pipe_size(intel_crtc); | |
465c120c | 12452 | |
ccc759dc | 12453 | intel_crtc->primary_enabled = true; |
465c120c | 12454 | |
ccc759dc GP |
12455 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
12456 | crtc->x, crtc->y); | |
ccc759dc GP |
12457 | } else { |
12458 | /* | |
12459 | * If clipping results in a non-visible primary plane, | |
12460 | * we'll disable the primary plane. Note that this is | |
12461 | * a bit different than what happens if userspace | |
12462 | * explicitly disables the plane by passing fb=0 | |
12463 | * because plane->fb still gets set and pinned. | |
12464 | */ | |
12465 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 12466 | } |
ccc759dc | 12467 | } |
465c120c MR |
12468 | } |
12469 | ||
32b7eeec | 12470 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 12471 | { |
32b7eeec | 12472 | struct drm_device *dev = crtc->dev; |
140fd38d | 12473 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 12474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
12475 | struct intel_plane *intel_plane; |
12476 | struct drm_plane *p; | |
12477 | unsigned fb_bits = 0; | |
12478 | ||
12479 | /* Track fb's for any planes being disabled */ | |
12480 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
12481 | intel_plane = to_intel_plane(p); | |
12482 | ||
12483 | if (intel_crtc->atomic.disabled_planes & | |
12484 | (1 << drm_plane_index(p))) { | |
12485 | switch (p->type) { | |
12486 | case DRM_PLANE_TYPE_PRIMARY: | |
12487 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
12488 | break; | |
12489 | case DRM_PLANE_TYPE_CURSOR: | |
12490 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
12491 | break; | |
12492 | case DRM_PLANE_TYPE_OVERLAY: | |
12493 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
12494 | break; | |
12495 | } | |
3c692a41 | 12496 | |
ea2c67bb MR |
12497 | mutex_lock(&dev->struct_mutex); |
12498 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
12499 | mutex_unlock(&dev->struct_mutex); | |
12500 | } | |
12501 | } | |
3c692a41 | 12502 | |
32b7eeec MR |
12503 | if (intel_crtc->atomic.wait_for_flips) |
12504 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 12505 | |
32b7eeec MR |
12506 | if (intel_crtc->atomic.disable_fbc) |
12507 | intel_fbc_disable(dev); | |
3c692a41 | 12508 | |
32b7eeec MR |
12509 | if (intel_crtc->atomic.pre_disable_primary) |
12510 | intel_pre_disable_primary(crtc); | |
3c692a41 | 12511 | |
32b7eeec MR |
12512 | if (intel_crtc->atomic.update_wm) |
12513 | intel_update_watermarks(crtc); | |
3c692a41 | 12514 | |
32b7eeec | 12515 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 12516 | |
c34c9ee4 MR |
12517 | /* Perform vblank evasion around commit operation */ |
12518 | if (intel_crtc->active) | |
12519 | intel_crtc->atomic.evade = | |
12520 | intel_pipe_update_start(intel_crtc, | |
12521 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
12522 | } |
12523 | ||
12524 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
12525 | { | |
12526 | struct drm_device *dev = crtc->dev; | |
12527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12528 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12529 | struct drm_plane *p; | |
12530 | ||
c34c9ee4 MR |
12531 | if (intel_crtc->atomic.evade) |
12532 | intel_pipe_update_end(intel_crtc, | |
12533 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 12534 | |
140fd38d | 12535 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 12536 | |
32b7eeec MR |
12537 | if (intel_crtc->atomic.wait_vblank) |
12538 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
12539 | ||
12540 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
12541 | ||
12542 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 12543 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 12544 | intel_fbc_update(dev); |
ccc759dc | 12545 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 12546 | } |
3c692a41 | 12547 | |
32b7eeec MR |
12548 | if (intel_crtc->atomic.post_enable_primary) |
12549 | intel_post_enable_primary(crtc); | |
3c692a41 | 12550 | |
32b7eeec MR |
12551 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
12552 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
12553 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
12554 | false, false); | |
12555 | ||
12556 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
12557 | } |
12558 | ||
cf4c7c12 | 12559 | /** |
4a3b8769 MR |
12560 | * intel_plane_destroy - destroy a plane |
12561 | * @plane: plane to destroy | |
cf4c7c12 | 12562 | * |
4a3b8769 MR |
12563 | * Common destruction function for all types of planes (primary, cursor, |
12564 | * sprite). | |
cf4c7c12 | 12565 | */ |
4a3b8769 | 12566 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
12567 | { |
12568 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12569 | drm_plane_cleanup(plane); | |
12570 | kfree(intel_plane); | |
12571 | } | |
12572 | ||
65a3fea0 | 12573 | const struct drm_plane_funcs intel_plane_funcs = { |
ff42e093 DV |
12574 | .update_plane = drm_plane_helper_update, |
12575 | .disable_plane = drm_plane_helper_disable, | |
3d7d6510 | 12576 | .destroy = intel_plane_destroy, |
c196e1d6 | 12577 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
12578 | .atomic_get_property = intel_plane_atomic_get_property, |
12579 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12580 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12581 | .atomic_destroy_state = intel_plane_destroy_state, | |
12582 | ||
465c120c MR |
12583 | }; |
12584 | ||
12585 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
12586 | int pipe) | |
12587 | { | |
12588 | struct intel_plane *primary; | |
8e7d688b | 12589 | struct intel_plane_state *state; |
465c120c MR |
12590 | const uint32_t *intel_primary_formats; |
12591 | int num_formats; | |
12592 | ||
12593 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
12594 | if (primary == NULL) | |
12595 | return NULL; | |
12596 | ||
8e7d688b MR |
12597 | state = intel_create_plane_state(&primary->base); |
12598 | if (!state) { | |
ea2c67bb MR |
12599 | kfree(primary); |
12600 | return NULL; | |
12601 | } | |
8e7d688b | 12602 | primary->base.state = &state->base; |
ea2c67bb | 12603 | |
465c120c MR |
12604 | primary->can_scale = false; |
12605 | primary->max_downscale = 1; | |
12606 | primary->pipe = pipe; | |
12607 | primary->plane = pipe; | |
c59cb179 MR |
12608 | primary->check_plane = intel_check_primary_plane; |
12609 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
12610 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12611 | primary->plane = !pipe; | |
12612 | ||
12613 | if (INTEL_INFO(dev)->gen <= 3) { | |
12614 | intel_primary_formats = intel_primary_formats_gen2; | |
12615 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12616 | } else { | |
12617 | intel_primary_formats = intel_primary_formats_gen4; | |
12618 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12619 | } | |
12620 | ||
12621 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 12622 | &intel_plane_funcs, |
465c120c MR |
12623 | intel_primary_formats, num_formats, |
12624 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
12625 | |
12626 | if (INTEL_INFO(dev)->gen >= 4) { | |
12627 | if (!dev->mode_config.rotation_property) | |
12628 | dev->mode_config.rotation_property = | |
12629 | drm_mode_create_rotation_property(dev, | |
12630 | BIT(DRM_ROTATE_0) | | |
12631 | BIT(DRM_ROTATE_180)); | |
12632 | if (dev->mode_config.rotation_property) | |
12633 | drm_object_attach_property(&primary->base.base, | |
12634 | dev->mode_config.rotation_property, | |
8e7d688b | 12635 | state->base.rotation); |
48404c1e SJ |
12636 | } |
12637 | ||
ea2c67bb MR |
12638 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
12639 | ||
465c120c MR |
12640 | return &primary->base; |
12641 | } | |
12642 | ||
3d7d6510 | 12643 | static int |
852e787c GP |
12644 | intel_check_cursor_plane(struct drm_plane *plane, |
12645 | struct intel_plane_state *state) | |
3d7d6510 | 12646 | { |
2b875c22 | 12647 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 12648 | struct drm_device *dev = plane->dev; |
2b875c22 | 12649 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12650 | struct drm_rect *dest = &state->dst; |
12651 | struct drm_rect *src = &state->src; | |
12652 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 12653 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 12654 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
12655 | unsigned stride; |
12656 | int ret; | |
3d7d6510 | 12657 | |
ea2c67bb MR |
12658 | crtc = crtc ? crtc : plane->crtc; |
12659 | intel_crtc = to_intel_crtc(crtc); | |
12660 | ||
757f9a3e | 12661 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12662 | src, dest, clip, |
3d7d6510 MR |
12663 | DRM_PLANE_HELPER_NO_SCALING, |
12664 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12665 | true, true, &state->visible); |
757f9a3e GP |
12666 | if (ret) |
12667 | return ret; | |
12668 | ||
12669 | ||
12670 | /* if we want to turn off the cursor ignore width and height */ | |
12671 | if (!obj) | |
32b7eeec | 12672 | goto finish; |
757f9a3e | 12673 | |
757f9a3e | 12674 | /* Check for which cursor types we support */ |
ea2c67bb MR |
12675 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
12676 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
12677 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
12678 | return -EINVAL; |
12679 | } | |
12680 | ||
ea2c67bb MR |
12681 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
12682 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
12683 | DRM_DEBUG_KMS("buffer is too small\n"); |
12684 | return -ENOMEM; | |
12685 | } | |
12686 | ||
3a656b54 | 12687 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
12688 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
12689 | ret = -EINVAL; | |
12690 | } | |
757f9a3e | 12691 | |
32b7eeec MR |
12692 | finish: |
12693 | if (intel_crtc->active) { | |
3749f463 | 12694 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
12695 | intel_crtc->atomic.update_wm = true; |
12696 | ||
12697 | intel_crtc->atomic.fb_bits |= | |
12698 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
12699 | } | |
12700 | ||
757f9a3e | 12701 | return ret; |
852e787c | 12702 | } |
3d7d6510 | 12703 | |
f4a2cf29 | 12704 | static void |
852e787c GP |
12705 | intel_commit_cursor_plane(struct drm_plane *plane, |
12706 | struct intel_plane_state *state) | |
12707 | { | |
2b875c22 | 12708 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
12709 | struct drm_device *dev = plane->dev; |
12710 | struct intel_crtc *intel_crtc; | |
2b875c22 | 12711 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 12712 | uint32_t addr; |
852e787c | 12713 | |
ea2c67bb MR |
12714 | crtc = crtc ? crtc : plane->crtc; |
12715 | intel_crtc = to_intel_crtc(crtc); | |
12716 | ||
2b875c22 | 12717 | plane->fb = state->base.fb; |
ea2c67bb MR |
12718 | crtc->cursor_x = state->base.crtc_x; |
12719 | crtc->cursor_y = state->base.crtc_y; | |
12720 | ||
a912f12f GP |
12721 | if (intel_crtc->cursor_bo == obj) |
12722 | goto update; | |
4ed91096 | 12723 | |
f4a2cf29 | 12724 | if (!obj) |
a912f12f | 12725 | addr = 0; |
f4a2cf29 | 12726 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12727 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12728 | else |
a912f12f | 12729 | addr = obj->phys_handle->busaddr; |
852e787c | 12730 | |
a912f12f GP |
12731 | intel_crtc->cursor_addr = addr; |
12732 | intel_crtc->cursor_bo = obj; | |
12733 | update: | |
852e787c | 12734 | |
32b7eeec | 12735 | if (intel_crtc->active) |
a912f12f | 12736 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
12737 | } |
12738 | ||
3d7d6510 MR |
12739 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
12740 | int pipe) | |
12741 | { | |
12742 | struct intel_plane *cursor; | |
8e7d688b | 12743 | struct intel_plane_state *state; |
3d7d6510 MR |
12744 | |
12745 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12746 | if (cursor == NULL) | |
12747 | return NULL; | |
12748 | ||
8e7d688b MR |
12749 | state = intel_create_plane_state(&cursor->base); |
12750 | if (!state) { | |
ea2c67bb MR |
12751 | kfree(cursor); |
12752 | return NULL; | |
12753 | } | |
8e7d688b | 12754 | cursor->base.state = &state->base; |
ea2c67bb | 12755 | |
3d7d6510 MR |
12756 | cursor->can_scale = false; |
12757 | cursor->max_downscale = 1; | |
12758 | cursor->pipe = pipe; | |
12759 | cursor->plane = pipe; | |
c59cb179 MR |
12760 | cursor->check_plane = intel_check_cursor_plane; |
12761 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12762 | |
12763 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 12764 | &intel_plane_funcs, |
3d7d6510 MR |
12765 | intel_cursor_formats, |
12766 | ARRAY_SIZE(intel_cursor_formats), | |
12767 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12768 | |
12769 | if (INTEL_INFO(dev)->gen >= 4) { | |
12770 | if (!dev->mode_config.rotation_property) | |
12771 | dev->mode_config.rotation_property = | |
12772 | drm_mode_create_rotation_property(dev, | |
12773 | BIT(DRM_ROTATE_0) | | |
12774 | BIT(DRM_ROTATE_180)); | |
12775 | if (dev->mode_config.rotation_property) | |
12776 | drm_object_attach_property(&cursor->base.base, | |
12777 | dev->mode_config.rotation_property, | |
8e7d688b | 12778 | state->base.rotation); |
4398ad45 VS |
12779 | } |
12780 | ||
ea2c67bb MR |
12781 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
12782 | ||
3d7d6510 MR |
12783 | return &cursor->base; |
12784 | } | |
12785 | ||
b358d0a6 | 12786 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12787 | { |
fbee40df | 12788 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12789 | struct intel_crtc *intel_crtc; |
f5de6e07 | 12790 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
12791 | struct drm_plane *primary = NULL; |
12792 | struct drm_plane *cursor = NULL; | |
465c120c | 12793 | int i, ret; |
79e53945 | 12794 | |
955382f3 | 12795 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12796 | if (intel_crtc == NULL) |
12797 | return; | |
12798 | ||
f5de6e07 ACO |
12799 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
12800 | if (!crtc_state) | |
12801 | goto fail; | |
12802 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 12803 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 12804 | |
465c120c | 12805 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12806 | if (!primary) |
12807 | goto fail; | |
12808 | ||
12809 | cursor = intel_cursor_plane_create(dev, pipe); | |
12810 | if (!cursor) | |
12811 | goto fail; | |
12812 | ||
465c120c | 12813 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12814 | cursor, &intel_crtc_funcs); |
12815 | if (ret) | |
12816 | goto fail; | |
79e53945 JB |
12817 | |
12818 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12819 | for (i = 0; i < 256; i++) { |
12820 | intel_crtc->lut_r[i] = i; | |
12821 | intel_crtc->lut_g[i] = i; | |
12822 | intel_crtc->lut_b[i] = i; | |
12823 | } | |
12824 | ||
1f1c2e24 VS |
12825 | /* |
12826 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12827 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12828 | */ |
80824003 JB |
12829 | intel_crtc->pipe = pipe; |
12830 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12831 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12832 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12833 | intel_crtc->plane = !pipe; |
80824003 JB |
12834 | } |
12835 | ||
4b0e333e CW |
12836 | intel_crtc->cursor_base = ~0; |
12837 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12838 | intel_crtc->cursor_size = ~0; |
8d7849db | 12839 | |
22fd0fab JB |
12840 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12841 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12842 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12843 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12844 | ||
9362c7c5 ACO |
12845 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12846 | ||
79e53945 | 12847 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12848 | |
12849 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12850 | return; |
12851 | ||
12852 | fail: | |
12853 | if (primary) | |
12854 | drm_plane_cleanup(primary); | |
12855 | if (cursor) | |
12856 | drm_plane_cleanup(cursor); | |
f5de6e07 | 12857 | kfree(crtc_state); |
3d7d6510 | 12858 | kfree(intel_crtc); |
79e53945 JB |
12859 | } |
12860 | ||
752aa88a JB |
12861 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12862 | { | |
12863 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12864 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12865 | |
51fd371b | 12866 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12867 | |
d3babd3f | 12868 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12869 | return INVALID_PIPE; |
12870 | ||
12871 | return to_intel_crtc(encoder->crtc)->pipe; | |
12872 | } | |
12873 | ||
08d7b3d1 | 12874 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12875 | struct drm_file *file) |
08d7b3d1 | 12876 | { |
08d7b3d1 | 12877 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12878 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12879 | struct intel_crtc *crtc; |
08d7b3d1 | 12880 | |
7707e653 | 12881 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12882 | |
7707e653 | 12883 | if (!drmmode_crtc) { |
08d7b3d1 | 12884 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12885 | return -ENOENT; |
08d7b3d1 CW |
12886 | } |
12887 | ||
7707e653 | 12888 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12889 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12890 | |
c05422d5 | 12891 | return 0; |
08d7b3d1 CW |
12892 | } |
12893 | ||
66a9278e | 12894 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12895 | { |
66a9278e DV |
12896 | struct drm_device *dev = encoder->base.dev; |
12897 | struct intel_encoder *source_encoder; | |
79e53945 | 12898 | int index_mask = 0; |
79e53945 JB |
12899 | int entry = 0; |
12900 | ||
b2784e15 | 12901 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12902 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12903 | index_mask |= (1 << entry); |
12904 | ||
79e53945 JB |
12905 | entry++; |
12906 | } | |
4ef69c7a | 12907 | |
79e53945 JB |
12908 | return index_mask; |
12909 | } | |
12910 | ||
4d302442 CW |
12911 | static bool has_edp_a(struct drm_device *dev) |
12912 | { | |
12913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12914 | ||
12915 | if (!IS_MOBILE(dev)) | |
12916 | return false; | |
12917 | ||
12918 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12919 | return false; | |
12920 | ||
e3589908 | 12921 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12922 | return false; |
12923 | ||
12924 | return true; | |
12925 | } | |
12926 | ||
84b4e042 JB |
12927 | static bool intel_crt_present(struct drm_device *dev) |
12928 | { | |
12929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12930 | ||
884497ed DL |
12931 | if (INTEL_INFO(dev)->gen >= 9) |
12932 | return false; | |
12933 | ||
cf404ce4 | 12934 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12935 | return false; |
12936 | ||
12937 | if (IS_CHERRYVIEW(dev)) | |
12938 | return false; | |
12939 | ||
12940 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12941 | return false; | |
12942 | ||
12943 | return true; | |
12944 | } | |
12945 | ||
79e53945 JB |
12946 | static void intel_setup_outputs(struct drm_device *dev) |
12947 | { | |
725e30ad | 12948 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12949 | struct intel_encoder *encoder; |
c6f95f27 | 12950 | struct drm_connector *connector; |
cb0953d7 | 12951 | bool dpd_is_edp = false; |
79e53945 | 12952 | |
c9093354 | 12953 | intel_lvds_init(dev); |
79e53945 | 12954 | |
84b4e042 | 12955 | if (intel_crt_present(dev)) |
79935fca | 12956 | intel_crt_init(dev); |
cb0953d7 | 12957 | |
affa9354 | 12958 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12959 | int found; |
12960 | ||
de31facd JB |
12961 | /* |
12962 | * Haswell uses DDI functions to detect digital outputs. | |
12963 | * On SKL pre-D0 the strap isn't connected, so we assume | |
12964 | * it's there. | |
12965 | */ | |
0e72a5b5 | 12966 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
12967 | /* WaIgnoreDDIAStrap: skl */ |
12968 | if (found || | |
12969 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
12970 | intel_ddi_init(dev, PORT_A); |
12971 | ||
12972 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12973 | * register */ | |
12974 | found = I915_READ(SFUSE_STRAP); | |
12975 | ||
12976 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12977 | intel_ddi_init(dev, PORT_B); | |
12978 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12979 | intel_ddi_init(dev, PORT_C); | |
12980 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12981 | intel_ddi_init(dev, PORT_D); | |
12982 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12983 | int found; |
5d8a7752 | 12984 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12985 | |
12986 | if (has_edp_a(dev)) | |
12987 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12988 | |
dc0fa718 | 12989 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12990 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12991 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12992 | if (!found) |
e2debe91 | 12993 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12994 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12995 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12996 | } |
12997 | ||
dc0fa718 | 12998 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12999 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13000 | |
dc0fa718 | 13001 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13002 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13003 | |
5eb08b69 | 13004 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13005 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13006 | |
270b3042 | 13007 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13008 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 13009 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
13010 | /* |
13011 | * The DP_DETECTED bit is the latched state of the DDC | |
13012 | * SDA pin at boot. However since eDP doesn't require DDC | |
13013 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13014 | * eDP ports may have been muxed to an alternate function. | |
13015 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13016 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13017 | * detect eDP ports. | |
13018 | */ | |
d2182a66 VS |
13019 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
13020 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
13021 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
13022 | PORT_B); | |
e17ac6db VS |
13023 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
13024 | intel_dp_is_edp(dev, PORT_B)) | |
13025 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 13026 | |
d2182a66 VS |
13027 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
13028 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
13029 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
13030 | PORT_C); | |
e17ac6db VS |
13031 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
13032 | intel_dp_is_edp(dev, PORT_C)) | |
13033 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 13034 | |
9418c1f1 | 13035 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 13036 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
13037 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
13038 | PORT_D); | |
e17ac6db VS |
13039 | /* eDP not supported on port D, so don't check VBT */ |
13040 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
13041 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
13042 | } |
13043 | ||
3cfca973 | 13044 | intel_dsi_init(dev); |
103a196f | 13045 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 13046 | bool found = false; |
7d57382e | 13047 | |
e2debe91 | 13048 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13049 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 13050 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
13051 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
13052 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 13053 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13054 | } |
27185ae1 | 13055 | |
e7281eab | 13056 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13057 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 13058 | } |
13520b05 KH |
13059 | |
13060 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13061 | |
e2debe91 | 13062 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13063 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 13064 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 13065 | } |
27185ae1 | 13066 | |
e2debe91 | 13067 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13068 | |
b01f2c3a JB |
13069 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
13070 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 13071 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13072 | } |
e7281eab | 13073 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 13074 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 13075 | } |
27185ae1 | 13076 | |
b01f2c3a | 13077 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 13078 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 13079 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 13080 | } else if (IS_GEN2(dev)) |
79e53945 JB |
13081 | intel_dvo_init(dev); |
13082 | ||
103a196f | 13083 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
13084 | intel_tv_init(dev); |
13085 | ||
c6f95f27 MR |
13086 | /* |
13087 | * FIXME: We don't have full atomic support yet, but we want to be | |
13088 | * able to enable/test plane updates via the atomic interface in the | |
13089 | * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core | |
13090 | * will take some atomic codepaths to lookup properties during | |
13091 | * drmModeGetConnector() that unconditionally dereference | |
13092 | * connector->state. | |
13093 | * | |
13094 | * We create a dummy connector state here for each connector to ensure | |
13095 | * the DRM core doesn't try to dereference a NULL connector->state. | |
13096 | * The actual connector properties will never be updated or contain | |
13097 | * useful information, but since we're doing this specifically for | |
13098 | * testing/debug of the plane operations (and only when a specific | |
13099 | * kernel module option is given), that shouldn't really matter. | |
13100 | * | |
d29b2f9d ACO |
13101 | * We are also relying on these states to convert the legacy mode set |
13102 | * to use a drm_atomic_state struct. The states are kept consistent | |
13103 | * with actual state, so that it is safe to rely on that instead of | |
13104 | * the staged config. | |
13105 | * | |
c6f95f27 MR |
13106 | * Once atomic support for crtc's + connectors lands, this loop should |
13107 | * be removed since we'll be setting up real connector state, which | |
13108 | * will contain Intel-specific properties. | |
13109 | */ | |
d29b2f9d ACO |
13110 | list_for_each_entry(connector, |
13111 | &dev->mode_config.connector_list, | |
13112 | head) { | |
13113 | if (!WARN_ON(connector->state)) { | |
13114 | connector->state = kzalloc(sizeof(*connector->state), | |
13115 | GFP_KERNEL); | |
c6f95f27 MR |
13116 | } |
13117 | } | |
13118 | ||
0bc12bcb | 13119 | intel_psr_init(dev); |
7c8f8a70 | 13120 | |
b2784e15 | 13121 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
13122 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13123 | encoder->base.possible_clones = | |
66a9278e | 13124 | intel_encoder_clones(encoder); |
79e53945 | 13125 | } |
47356eb6 | 13126 | |
dde86e2d | 13127 | intel_init_pch_refclk(dev); |
270b3042 DV |
13128 | |
13129 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
13130 | } |
13131 | ||
13132 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13133 | { | |
60a5ca01 | 13134 | struct drm_device *dev = fb->dev; |
79e53945 | 13135 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 13136 | |
ef2d633e | 13137 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 13138 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 13139 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
13140 | drm_gem_object_unreference(&intel_fb->obj->base); |
13141 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13142 | kfree(intel_fb); |
13143 | } | |
13144 | ||
13145 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13146 | struct drm_file *file, |
79e53945 JB |
13147 | unsigned int *handle) |
13148 | { | |
13149 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13150 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13151 | |
05394f39 | 13152 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13153 | } |
13154 | ||
13155 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
13156 | .destroy = intel_user_framebuffer_destroy, | |
13157 | .create_handle = intel_user_framebuffer_create_handle, | |
13158 | }; | |
13159 | ||
b321803d DL |
13160 | static |
13161 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
13162 | uint32_t pixel_format) | |
13163 | { | |
13164 | u32 gen = INTEL_INFO(dev)->gen; | |
13165 | ||
13166 | if (gen >= 9) { | |
13167 | /* "The stride in bytes must not exceed the of the size of 8K | |
13168 | * pixels and 32K bytes." | |
13169 | */ | |
13170 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
13171 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
13172 | return 32*1024; | |
13173 | } else if (gen >= 4) { | |
13174 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13175 | return 16*1024; | |
13176 | else | |
13177 | return 32*1024; | |
13178 | } else if (gen >= 3) { | |
13179 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13180 | return 8*1024; | |
13181 | else | |
13182 | return 16*1024; | |
13183 | } else { | |
13184 | /* XXX DSPC is limited to 4k tiled */ | |
13185 | return 8*1024; | |
13186 | } | |
13187 | } | |
13188 | ||
b5ea642a DV |
13189 | static int intel_framebuffer_init(struct drm_device *dev, |
13190 | struct intel_framebuffer *intel_fb, | |
13191 | struct drm_mode_fb_cmd2 *mode_cmd, | |
13192 | struct drm_i915_gem_object *obj) | |
79e53945 | 13193 | { |
6761dd31 | 13194 | unsigned int aligned_height; |
79e53945 | 13195 | int ret; |
b321803d | 13196 | u32 pitch_limit, stride_alignment; |
79e53945 | 13197 | |
dd4916c5 DV |
13198 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
13199 | ||
2a80eada DV |
13200 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
13201 | /* Enforce that fb modifier and tiling mode match, but only for | |
13202 | * X-tiled. This is needed for FBC. */ | |
13203 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
13204 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
13205 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
13206 | return -EINVAL; | |
13207 | } | |
13208 | } else { | |
13209 | if (obj->tiling_mode == I915_TILING_X) | |
13210 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
13211 | else if (obj->tiling_mode == I915_TILING_Y) { | |
13212 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
13213 | return -EINVAL; | |
13214 | } | |
13215 | } | |
13216 | ||
9a8f0a12 TU |
13217 | /* Passed in modifier sanity checking. */ |
13218 | switch (mode_cmd->modifier[0]) { | |
13219 | case I915_FORMAT_MOD_Y_TILED: | |
13220 | case I915_FORMAT_MOD_Yf_TILED: | |
13221 | if (INTEL_INFO(dev)->gen < 9) { | |
13222 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
13223 | mode_cmd->modifier[0]); | |
13224 | return -EINVAL; | |
13225 | } | |
13226 | case DRM_FORMAT_MOD_NONE: | |
13227 | case I915_FORMAT_MOD_X_TILED: | |
13228 | break; | |
13229 | default: | |
c0f40428 JB |
13230 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
13231 | mode_cmd->modifier[0]); | |
57cd6508 | 13232 | return -EINVAL; |
c16ed4be | 13233 | } |
57cd6508 | 13234 | |
b321803d DL |
13235 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
13236 | mode_cmd->pixel_format); | |
13237 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
13238 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
13239 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 13240 | return -EINVAL; |
c16ed4be | 13241 | } |
57cd6508 | 13242 | |
b321803d DL |
13243 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
13244 | mode_cmd->pixel_format); | |
a35cdaa0 | 13245 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
13246 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
13247 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 13248 | "tiled" : "linear", |
a35cdaa0 | 13249 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 13250 | return -EINVAL; |
c16ed4be | 13251 | } |
5d7bd705 | 13252 | |
2a80eada | 13253 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
13254 | mode_cmd->pitches[0] != obj->stride) { |
13255 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
13256 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 13257 | return -EINVAL; |
c16ed4be | 13258 | } |
5d7bd705 | 13259 | |
57779d06 | 13260 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13261 | switch (mode_cmd->pixel_format) { |
57779d06 | 13262 | case DRM_FORMAT_C8: |
04b3924d VS |
13263 | case DRM_FORMAT_RGB565: |
13264 | case DRM_FORMAT_XRGB8888: | |
13265 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13266 | break; |
13267 | case DRM_FORMAT_XRGB1555: | |
13268 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 13269 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
13270 | DRM_DEBUG("unsupported pixel format: %s\n", |
13271 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13272 | return -EINVAL; |
c16ed4be | 13273 | } |
57779d06 VS |
13274 | break; |
13275 | case DRM_FORMAT_XBGR8888: | |
13276 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
13277 | case DRM_FORMAT_XRGB2101010: |
13278 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
13279 | case DRM_FORMAT_XBGR2101010: |
13280 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 13281 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
13282 | DRM_DEBUG("unsupported pixel format: %s\n", |
13283 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13284 | return -EINVAL; |
c16ed4be | 13285 | } |
b5626747 | 13286 | break; |
04b3924d VS |
13287 | case DRM_FORMAT_YUYV: |
13288 | case DRM_FORMAT_UYVY: | |
13289 | case DRM_FORMAT_YVYU: | |
13290 | case DRM_FORMAT_VYUY: | |
c16ed4be | 13291 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
13292 | DRM_DEBUG("unsupported pixel format: %s\n", |
13293 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 13294 | return -EINVAL; |
c16ed4be | 13295 | } |
57cd6508 CW |
13296 | break; |
13297 | default: | |
4ee62c76 VS |
13298 | DRM_DEBUG("unsupported pixel format: %s\n", |
13299 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
13300 | return -EINVAL; |
13301 | } | |
13302 | ||
90f9a336 VS |
13303 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13304 | if (mode_cmd->offsets[0] != 0) | |
13305 | return -EINVAL; | |
13306 | ||
ec2c981e | 13307 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
13308 | mode_cmd->pixel_format, |
13309 | mode_cmd->modifier[0]); | |
53155c0a DV |
13310 | /* FIXME drm helper for size checks (especially planar formats)? */ |
13311 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
13312 | return -EINVAL; | |
13313 | ||
c7d73f6a DV |
13314 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
13315 | intel_fb->obj = obj; | |
80075d49 | 13316 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 13317 | |
79e53945 JB |
13318 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
13319 | if (ret) { | |
13320 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
13321 | return ret; | |
13322 | } | |
13323 | ||
79e53945 JB |
13324 | return 0; |
13325 | } | |
13326 | ||
79e53945 JB |
13327 | static struct drm_framebuffer * |
13328 | intel_user_framebuffer_create(struct drm_device *dev, | |
13329 | struct drm_file *filp, | |
308e5bcb | 13330 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 13331 | { |
05394f39 | 13332 | struct drm_i915_gem_object *obj; |
79e53945 | 13333 | |
308e5bcb JB |
13334 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
13335 | mode_cmd->handles[0])); | |
c8725226 | 13336 | if (&obj->base == NULL) |
cce13ff7 | 13337 | return ERR_PTR(-ENOENT); |
79e53945 | 13338 | |
d2dff872 | 13339 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
13340 | } |
13341 | ||
4520f53a | 13342 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 13343 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
13344 | { |
13345 | } | |
13346 | #endif | |
13347 | ||
79e53945 | 13348 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13349 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 13350 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13351 | .atomic_check = intel_atomic_check, |
13352 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
13353 | }; |
13354 | ||
e70236a8 JB |
13355 | /* Set up chip specific display functions */ |
13356 | static void intel_init_display(struct drm_device *dev) | |
13357 | { | |
13358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13359 | ||
ee9300bb DV |
13360 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
13361 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
13362 | else if (IS_CHERRYVIEW(dev)) |
13363 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
13364 | else if (IS_VALLEYVIEW(dev)) |
13365 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
13366 | else if (IS_PINEVIEW(dev)) | |
13367 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
13368 | else | |
13369 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
13370 | ||
bc8d7dff DL |
13371 | if (INTEL_INFO(dev)->gen >= 9) { |
13372 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
13373 | dev_priv->display.get_initial_plane_config = |
13374 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13375 | dev_priv->display.crtc_compute_clock = |
13376 | haswell_crtc_compute_clock; | |
13377 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13378 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
13379 | dev_priv->display.off = ironlake_crtc_off; | |
13380 | dev_priv->display.update_primary_plane = | |
13381 | skylake_update_primary_plane; | |
13382 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 13383 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13384 | dev_priv->display.get_initial_plane_config = |
13385 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13386 | dev_priv->display.crtc_compute_clock = |
13387 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13388 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13389 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 13390 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
13391 | dev_priv->display.update_primary_plane = |
13392 | ironlake_update_primary_plane; | |
09b4ddf9 | 13393 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 13394 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13395 | dev_priv->display.get_initial_plane_config = |
13396 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13397 | dev_priv->display.crtc_compute_clock = |
13398 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13399 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13400 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 13401 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
13402 | dev_priv->display.update_primary_plane = |
13403 | ironlake_update_primary_plane; | |
89b667f8 JB |
13404 | } else if (IS_VALLEYVIEW(dev)) { |
13405 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
13406 | dev_priv->display.get_initial_plane_config = |
13407 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13408 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
13409 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13410 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13411 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
13412 | dev_priv->display.update_primary_plane = |
13413 | i9xx_update_primary_plane; | |
f564048e | 13414 | } else { |
0e8ffe1b | 13415 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13416 | dev_priv->display.get_initial_plane_config = |
13417 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13418 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13419 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13420 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 13421 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
13422 | dev_priv->display.update_primary_plane = |
13423 | i9xx_update_primary_plane; | |
f564048e | 13424 | } |
e70236a8 | 13425 | |
e70236a8 | 13426 | /* Returns the core display clock speed */ |
25eb05fc JB |
13427 | if (IS_VALLEYVIEW(dev)) |
13428 | dev_priv->display.get_display_clock_speed = | |
13429 | valleyview_get_display_clock_speed; | |
13430 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
13431 | dev_priv->display.get_display_clock_speed = |
13432 | i945_get_display_clock_speed; | |
13433 | else if (IS_I915G(dev)) | |
13434 | dev_priv->display.get_display_clock_speed = | |
13435 | i915_get_display_clock_speed; | |
257a7ffc | 13436 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
13437 | dev_priv->display.get_display_clock_speed = |
13438 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
13439 | else if (IS_PINEVIEW(dev)) |
13440 | dev_priv->display.get_display_clock_speed = | |
13441 | pnv_get_display_clock_speed; | |
e70236a8 JB |
13442 | else if (IS_I915GM(dev)) |
13443 | dev_priv->display.get_display_clock_speed = | |
13444 | i915gm_get_display_clock_speed; | |
13445 | else if (IS_I865G(dev)) | |
13446 | dev_priv->display.get_display_clock_speed = | |
13447 | i865_get_display_clock_speed; | |
f0f8a9ce | 13448 | else if (IS_I85X(dev)) |
e70236a8 JB |
13449 | dev_priv->display.get_display_clock_speed = |
13450 | i855_get_display_clock_speed; | |
13451 | else /* 852, 830 */ | |
13452 | dev_priv->display.get_display_clock_speed = | |
13453 | i830_get_display_clock_speed; | |
13454 | ||
7c10a2b5 | 13455 | if (IS_GEN5(dev)) { |
3bb11b53 | 13456 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
13457 | } else if (IS_GEN6(dev)) { |
13458 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
13459 | } else if (IS_IVYBRIDGE(dev)) { |
13460 | /* FIXME: detect B0+ stepping and use auto training */ | |
13461 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 13462 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 13463 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
13464 | } else if (IS_VALLEYVIEW(dev)) { |
13465 | dev_priv->display.modeset_global_resources = | |
13466 | valleyview_modeset_global_resources; | |
e70236a8 | 13467 | } |
8c9f3aaf | 13468 | |
8c9f3aaf JB |
13469 | switch (INTEL_INFO(dev)->gen) { |
13470 | case 2: | |
13471 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
13472 | break; | |
13473 | ||
13474 | case 3: | |
13475 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
13476 | break; | |
13477 | ||
13478 | case 4: | |
13479 | case 5: | |
13480 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
13481 | break; | |
13482 | ||
13483 | case 6: | |
13484 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
13485 | break; | |
7c9017e5 | 13486 | case 7: |
4e0bbc31 | 13487 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
13488 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
13489 | break; | |
830c81db | 13490 | case 9: |
ba343e02 TU |
13491 | /* Drop through - unsupported since execlist only. */ |
13492 | default: | |
13493 | /* Default just returns -ENODEV to indicate unsupported */ | |
13494 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 13495 | } |
7bd688cd JN |
13496 | |
13497 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
13498 | |
13499 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
13500 | } |
13501 | ||
b690e96c JB |
13502 | /* |
13503 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
13504 | * resume, or other times. This quirk makes sure that's the case for | |
13505 | * affected systems. | |
13506 | */ | |
0206e353 | 13507 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
13508 | { |
13509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13510 | ||
13511 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 13512 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
13513 | } |
13514 | ||
b6b5d049 VS |
13515 | static void quirk_pipeb_force(struct drm_device *dev) |
13516 | { | |
13517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13518 | ||
13519 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
13520 | DRM_INFO("applying pipe b force quirk\n"); | |
13521 | } | |
13522 | ||
435793df KP |
13523 | /* |
13524 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
13525 | */ | |
13526 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
13527 | { | |
13528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13529 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 13530 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
13531 | } |
13532 | ||
4dca20ef | 13533 | /* |
5a15ab5b CE |
13534 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
13535 | * brightness value | |
4dca20ef CE |
13536 | */ |
13537 | static void quirk_invert_brightness(struct drm_device *dev) | |
13538 | { | |
13539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13540 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 13541 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
13542 | } |
13543 | ||
9c72cc6f SD |
13544 | /* Some VBT's incorrectly indicate no backlight is present */ |
13545 | static void quirk_backlight_present(struct drm_device *dev) | |
13546 | { | |
13547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13548 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
13549 | DRM_INFO("applying backlight present quirk\n"); | |
13550 | } | |
13551 | ||
b690e96c JB |
13552 | struct intel_quirk { |
13553 | int device; | |
13554 | int subsystem_vendor; | |
13555 | int subsystem_device; | |
13556 | void (*hook)(struct drm_device *dev); | |
13557 | }; | |
13558 | ||
5f85f176 EE |
13559 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
13560 | struct intel_dmi_quirk { | |
13561 | void (*hook)(struct drm_device *dev); | |
13562 | const struct dmi_system_id (*dmi_id_list)[]; | |
13563 | }; | |
13564 | ||
13565 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
13566 | { | |
13567 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
13568 | return 1; | |
13569 | } | |
13570 | ||
13571 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
13572 | { | |
13573 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
13574 | { | |
13575 | .callback = intel_dmi_reverse_brightness, | |
13576 | .ident = "NCR Corporation", | |
13577 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
13578 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
13579 | }, | |
13580 | }, | |
13581 | { } /* terminating entry */ | |
13582 | }, | |
13583 | .hook = quirk_invert_brightness, | |
13584 | }, | |
13585 | }; | |
13586 | ||
c43b5634 | 13587 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 13588 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 13589 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 13590 | |
b690e96c JB |
13591 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
13592 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
13593 | ||
b690e96c JB |
13594 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
13595 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
13596 | ||
5f080c0f VS |
13597 | /* 830 needs to leave pipe A & dpll A up */ |
13598 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
13599 | ||
b6b5d049 VS |
13600 | /* 830 needs to leave pipe B & dpll B up */ |
13601 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
13602 | ||
435793df KP |
13603 | /* Lenovo U160 cannot use SSC on LVDS */ |
13604 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
13605 | |
13606 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
13607 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 13608 | |
be505f64 AH |
13609 | /* Acer Aspire 5734Z must invert backlight brightness */ |
13610 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
13611 | ||
13612 | /* Acer/eMachines G725 */ | |
13613 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
13614 | ||
13615 | /* Acer/eMachines e725 */ | |
13616 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
13617 | ||
13618 | /* Acer/Packard Bell NCL20 */ | |
13619 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
13620 | ||
13621 | /* Acer Aspire 4736Z */ | |
13622 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
13623 | |
13624 | /* Acer Aspire 5336 */ | |
13625 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
13626 | |
13627 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
13628 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 13629 | |
dfb3d47b SD |
13630 | /* Acer C720 Chromebook (Core i3 4005U) */ |
13631 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
13632 | ||
b2a9601c | 13633 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
13634 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
13635 | ||
d4967d8c SD |
13636 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
13637 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
13638 | |
13639 | /* HP Chromebook 14 (Celeron 2955U) */ | |
13640 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
13641 | |
13642 | /* Dell Chromebook 11 */ | |
13643 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
13644 | }; |
13645 | ||
13646 | static void intel_init_quirks(struct drm_device *dev) | |
13647 | { | |
13648 | struct pci_dev *d = dev->pdev; | |
13649 | int i; | |
13650 | ||
13651 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
13652 | struct intel_quirk *q = &intel_quirks[i]; | |
13653 | ||
13654 | if (d->device == q->device && | |
13655 | (d->subsystem_vendor == q->subsystem_vendor || | |
13656 | q->subsystem_vendor == PCI_ANY_ID) && | |
13657 | (d->subsystem_device == q->subsystem_device || | |
13658 | q->subsystem_device == PCI_ANY_ID)) | |
13659 | q->hook(dev); | |
13660 | } | |
5f85f176 EE |
13661 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
13662 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
13663 | intel_dmi_quirks[i].hook(dev); | |
13664 | } | |
b690e96c JB |
13665 | } |
13666 | ||
9cce37f4 JB |
13667 | /* Disable the VGA plane that we never use */ |
13668 | static void i915_disable_vga(struct drm_device *dev) | |
13669 | { | |
13670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13671 | u8 sr1; | |
766aa1c4 | 13672 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 13673 | |
2b37c616 | 13674 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 13675 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 13676 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
13677 | sr1 = inb(VGA_SR_DATA); |
13678 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
13679 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
13680 | udelay(300); | |
13681 | ||
01f5a626 | 13682 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
13683 | POSTING_READ(vga_reg); |
13684 | } | |
13685 | ||
f817586c DV |
13686 | void intel_modeset_init_hw(struct drm_device *dev) |
13687 | { | |
a8f78b58 ED |
13688 | intel_prepare_ddi(dev); |
13689 | ||
f8bf63fd VS |
13690 | if (IS_VALLEYVIEW(dev)) |
13691 | vlv_update_cdclk(dev); | |
13692 | ||
f817586c DV |
13693 | intel_init_clock_gating(dev); |
13694 | ||
8090c6b9 | 13695 | intel_enable_gt_powersave(dev); |
f817586c DV |
13696 | } |
13697 | ||
79e53945 JB |
13698 | void intel_modeset_init(struct drm_device *dev) |
13699 | { | |
652c393a | 13700 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13701 | int sprite, ret; |
8cc87b75 | 13702 | enum pipe pipe; |
46f297fb | 13703 | struct intel_crtc *crtc; |
79e53945 JB |
13704 | |
13705 | drm_mode_config_init(dev); | |
13706 | ||
13707 | dev->mode_config.min_width = 0; | |
13708 | dev->mode_config.min_height = 0; | |
13709 | ||
019d96cb DA |
13710 | dev->mode_config.preferred_depth = 24; |
13711 | dev->mode_config.prefer_shadow = 1; | |
13712 | ||
25bab385 TU |
13713 | dev->mode_config.allow_fb_modifiers = true; |
13714 | ||
e6ecefaa | 13715 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13716 | |
b690e96c JB |
13717 | intel_init_quirks(dev); |
13718 | ||
1fa61106 ED |
13719 | intel_init_pm(dev); |
13720 | ||
e3c74757 BW |
13721 | if (INTEL_INFO(dev)->num_pipes == 0) |
13722 | return; | |
13723 | ||
e70236a8 | 13724 | intel_init_display(dev); |
7c10a2b5 | 13725 | intel_init_audio(dev); |
e70236a8 | 13726 | |
a6c45cf0 CW |
13727 | if (IS_GEN2(dev)) { |
13728 | dev->mode_config.max_width = 2048; | |
13729 | dev->mode_config.max_height = 2048; | |
13730 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13731 | dev->mode_config.max_width = 4096; |
13732 | dev->mode_config.max_height = 4096; | |
79e53945 | 13733 | } else { |
a6c45cf0 CW |
13734 | dev->mode_config.max_width = 8192; |
13735 | dev->mode_config.max_height = 8192; | |
79e53945 | 13736 | } |
068be561 | 13737 | |
dc41c154 VS |
13738 | if (IS_845G(dev) || IS_I865G(dev)) { |
13739 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13740 | dev->mode_config.cursor_height = 1023; | |
13741 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13742 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13743 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13744 | } else { | |
13745 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13746 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13747 | } | |
13748 | ||
5d4545ae | 13749 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13750 | |
28c97730 | 13751 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13752 | INTEL_INFO(dev)->num_pipes, |
13753 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13754 | |
055e393f | 13755 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13756 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 13757 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 13758 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 13759 | if (ret) |
06da8da2 | 13760 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13761 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13762 | } |
79e53945 JB |
13763 | } |
13764 | ||
f42bb70d JB |
13765 | intel_init_dpio(dev); |
13766 | ||
e72f9fbf | 13767 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13768 | |
9cce37f4 JB |
13769 | /* Just disable it once at startup */ |
13770 | i915_disable_vga(dev); | |
79e53945 | 13771 | intel_setup_outputs(dev); |
11be49eb CW |
13772 | |
13773 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 13774 | intel_fbc_disable(dev); |
fa9fa083 | 13775 | |
6e9f798d | 13776 | drm_modeset_lock_all(dev); |
fa9fa083 | 13777 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13778 | drm_modeset_unlock_all(dev); |
46f297fb | 13779 | |
d3fcc808 | 13780 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13781 | if (!crtc->active) |
13782 | continue; | |
13783 | ||
46f297fb | 13784 | /* |
46f297fb JB |
13785 | * Note that reserving the BIOS fb up front prevents us |
13786 | * from stuffing other stolen allocations like the ring | |
13787 | * on top. This prevents some ugliness at boot time, and | |
13788 | * can even allow for smooth boot transitions if the BIOS | |
13789 | * fb is large enough for the active pipe configuration. | |
13790 | */ | |
5724dbd1 DL |
13791 | if (dev_priv->display.get_initial_plane_config) { |
13792 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
13793 | &crtc->plane_config); |
13794 | /* | |
13795 | * If the fb is shared between multiple heads, we'll | |
13796 | * just get the first one. | |
13797 | */ | |
f6936e29 | 13798 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13799 | } |
46f297fb | 13800 | } |
2c7111db CW |
13801 | } |
13802 | ||
7fad798e DV |
13803 | static void intel_enable_pipe_a(struct drm_device *dev) |
13804 | { | |
13805 | struct intel_connector *connector; | |
13806 | struct drm_connector *crt = NULL; | |
13807 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13808 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13809 | |
13810 | /* We can't just switch on the pipe A, we need to set things up with a | |
13811 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13812 | * by enabling the load detect pipe once. */ | |
3a3371ff | 13813 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
13814 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
13815 | crt = &connector->base; | |
13816 | break; | |
13817 | } | |
13818 | } | |
13819 | ||
13820 | if (!crt) | |
13821 | return; | |
13822 | ||
208bf9fd | 13823 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 13824 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
13825 | } |
13826 | ||
fa555837 DV |
13827 | static bool |
13828 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13829 | { | |
7eb552ae BW |
13830 | struct drm_device *dev = crtc->base.dev; |
13831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13832 | u32 reg, val; |
13833 | ||
7eb552ae | 13834 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13835 | return true; |
13836 | ||
13837 | reg = DSPCNTR(!crtc->plane); | |
13838 | val = I915_READ(reg); | |
13839 | ||
13840 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13841 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13842 | return false; | |
13843 | ||
13844 | return true; | |
13845 | } | |
13846 | ||
24929352 DV |
13847 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13848 | { | |
13849 | struct drm_device *dev = crtc->base.dev; | |
13850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13851 | u32 reg; |
24929352 | 13852 | |
24929352 | 13853 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 13854 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
13855 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13856 | ||
d3eaf884 | 13857 | /* restore vblank interrupts to correct state */ |
9625604c | 13858 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
13859 | if (crtc->active) { |
13860 | update_scanline_offset(crtc); | |
9625604c DV |
13861 | drm_crtc_vblank_on(&crtc->base); |
13862 | } | |
d3eaf884 | 13863 | |
24929352 | 13864 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13865 | * disable the crtc (and hence change the state) if it is wrong. Note |
13866 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13867 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13868 | struct intel_connector *connector; |
13869 | bool plane; | |
13870 | ||
24929352 DV |
13871 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13872 | crtc->base.base.id); | |
13873 | ||
13874 | /* Pipe has the wrong plane attached and the plane is active. | |
13875 | * Temporarily change the plane mapping and disable everything | |
13876 | * ... */ | |
13877 | plane = crtc->plane; | |
13878 | crtc->plane = !plane; | |
9c8958bc | 13879 | crtc->primary_enabled = true; |
24929352 DV |
13880 | dev_priv->display.crtc_disable(&crtc->base); |
13881 | crtc->plane = plane; | |
13882 | ||
13883 | /* ... and break all links. */ | |
3a3371ff | 13884 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13885 | if (connector->encoder->base.crtc != &crtc->base) |
13886 | continue; | |
13887 | ||
7f1950fb EE |
13888 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13889 | connector->base.encoder = NULL; | |
24929352 | 13890 | } |
7f1950fb EE |
13891 | /* multiple connectors may have the same encoder: |
13892 | * handle them and break crtc link separately */ | |
3a3371ff | 13893 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
13894 | if (connector->encoder->base.crtc == &crtc->base) { |
13895 | connector->encoder->base.crtc = NULL; | |
13896 | connector->encoder->connectors_active = false; | |
13897 | } | |
24929352 DV |
13898 | |
13899 | WARN_ON(crtc->active); | |
83d65738 | 13900 | crtc->base.state->enable = false; |
24929352 DV |
13901 | crtc->base.enabled = false; |
13902 | } | |
24929352 | 13903 | |
7fad798e DV |
13904 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13905 | crtc->pipe == PIPE_A && !crtc->active) { | |
13906 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13907 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13908 | * call below we restore the pipe to the right state, but leave | |
13909 | * the required bits on. */ | |
13910 | intel_enable_pipe_a(dev); | |
13911 | } | |
13912 | ||
24929352 DV |
13913 | /* Adjust the state of the output pipe according to whether we |
13914 | * have active connectors/encoders. */ | |
13915 | intel_crtc_update_dpms(&crtc->base); | |
13916 | ||
83d65738 | 13917 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
13918 | struct intel_encoder *encoder; |
13919 | ||
13920 | /* This can happen either due to bugs in the get_hw_state | |
13921 | * functions or because the pipe is force-enabled due to the | |
13922 | * pipe A quirk. */ | |
13923 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13924 | crtc->base.base.id, | |
83d65738 | 13925 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
13926 | crtc->active ? "enabled" : "disabled"); |
13927 | ||
83d65738 | 13928 | crtc->base.state->enable = crtc->active; |
24929352 DV |
13929 | crtc->base.enabled = crtc->active; |
13930 | ||
13931 | /* Because we only establish the connector -> encoder -> | |
13932 | * crtc links if something is active, this means the | |
13933 | * crtc is now deactivated. Break the links. connector | |
13934 | * -> encoder links are only establish when things are | |
13935 | * actually up, hence no need to break them. */ | |
13936 | WARN_ON(crtc->active); | |
13937 | ||
13938 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13939 | WARN_ON(encoder->connectors_active); | |
13940 | encoder->base.crtc = NULL; | |
13941 | } | |
13942 | } | |
c5ab3bc0 | 13943 | |
a3ed6aad | 13944 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13945 | /* |
13946 | * We start out with underrun reporting disabled to avoid races. | |
13947 | * For correct bookkeeping mark this on active crtcs. | |
13948 | * | |
c5ab3bc0 DV |
13949 | * Also on gmch platforms we dont have any hardware bits to |
13950 | * disable the underrun reporting. Which means we need to start | |
13951 | * out with underrun reporting disabled also on inactive pipes, | |
13952 | * since otherwise we'll complain about the garbage we read when | |
13953 | * e.g. coming up after runtime pm. | |
13954 | * | |
4cc31489 DV |
13955 | * No protection against concurrent access is required - at |
13956 | * worst a fifo underrun happens which also sets this to false. | |
13957 | */ | |
13958 | crtc->cpu_fifo_underrun_disabled = true; | |
13959 | crtc->pch_fifo_underrun_disabled = true; | |
13960 | } | |
24929352 DV |
13961 | } |
13962 | ||
13963 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13964 | { | |
13965 | struct intel_connector *connector; | |
13966 | struct drm_device *dev = encoder->base.dev; | |
13967 | ||
13968 | /* We need to check both for a crtc link (meaning that the | |
13969 | * encoder is active and trying to read from a pipe) and the | |
13970 | * pipe itself being active. */ | |
13971 | bool has_active_crtc = encoder->base.crtc && | |
13972 | to_intel_crtc(encoder->base.crtc)->active; | |
13973 | ||
13974 | if (encoder->connectors_active && !has_active_crtc) { | |
13975 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13976 | encoder->base.base.id, | |
8e329a03 | 13977 | encoder->base.name); |
24929352 DV |
13978 | |
13979 | /* Connector is active, but has no active pipe. This is | |
13980 | * fallout from our resume register restoring. Disable | |
13981 | * the encoder manually again. */ | |
13982 | if (encoder->base.crtc) { | |
13983 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13984 | encoder->base.base.id, | |
8e329a03 | 13985 | encoder->base.name); |
24929352 | 13986 | encoder->disable(encoder); |
a62d1497 VS |
13987 | if (encoder->post_disable) |
13988 | encoder->post_disable(encoder); | |
24929352 | 13989 | } |
7f1950fb EE |
13990 | encoder->base.crtc = NULL; |
13991 | encoder->connectors_active = false; | |
24929352 DV |
13992 | |
13993 | /* Inconsistent output/port/pipe state happens presumably due to | |
13994 | * a bug in one of the get_hw_state functions. Or someplace else | |
13995 | * in our code, like the register restore mess on resume. Clamp | |
13996 | * things to off as a safer default. */ | |
3a3371ff | 13997 | for_each_intel_connector(dev, connector) { |
24929352 DV |
13998 | if (connector->encoder != encoder) |
13999 | continue; | |
7f1950fb EE |
14000 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14001 | connector->base.encoder = NULL; | |
24929352 DV |
14002 | } |
14003 | } | |
14004 | /* Enabled encoders without active connectors will be fixed in | |
14005 | * the crtc fixup. */ | |
14006 | } | |
14007 | ||
04098753 | 14008 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14009 | { |
14010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14011 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14012 | |
04098753 ID |
14013 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14014 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14015 | i915_disable_vga(dev); | |
14016 | } | |
14017 | } | |
14018 | ||
14019 | void i915_redisable_vga(struct drm_device *dev) | |
14020 | { | |
14021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14022 | ||
8dc8a27c PZ |
14023 | /* This function can be called both from intel_modeset_setup_hw_state or |
14024 | * at a very early point in our resume sequence, where the power well | |
14025 | * structures are not yet restored. Since this function is at a very | |
14026 | * paranoid "someone might have enabled VGA while we were not looking" | |
14027 | * level, just check if the power well is enabled instead of trying to | |
14028 | * follow the "don't touch the power well if we don't need it" policy | |
14029 | * the rest of the driver uses. */ | |
f458ebbc | 14030 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14031 | return; |
14032 | ||
04098753 | 14033 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
14034 | } |
14035 | ||
98ec7739 VS |
14036 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
14037 | { | |
14038 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
14039 | ||
14040 | if (!crtc->active) | |
14041 | return false; | |
14042 | ||
14043 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
14044 | } | |
14045 | ||
30e984df | 14046 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
14047 | { |
14048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14049 | enum pipe pipe; | |
24929352 DV |
14050 | struct intel_crtc *crtc; |
14051 | struct intel_encoder *encoder; | |
14052 | struct intel_connector *connector; | |
5358901f | 14053 | int i; |
24929352 | 14054 | |
d3fcc808 | 14055 | for_each_intel_crtc(dev, crtc) { |
6e3c9717 | 14056 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 14057 | |
6e3c9717 | 14058 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 14059 | |
0e8ffe1b | 14060 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 14061 | crtc->config); |
24929352 | 14062 | |
83d65738 | 14063 | crtc->base.state->enable = crtc->active; |
24929352 | 14064 | crtc->base.enabled = crtc->active; |
98ec7739 | 14065 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
14066 | |
14067 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
14068 | crtc->base.base.id, | |
14069 | crtc->active ? "enabled" : "disabled"); | |
14070 | } | |
14071 | ||
5358901f DV |
14072 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14073 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14074 | ||
3e369b76 ACO |
14075 | pll->on = pll->get_hw_state(dev_priv, pll, |
14076 | &pll->config.hw_state); | |
5358901f | 14077 | pll->active = 0; |
3e369b76 | 14078 | pll->config.crtc_mask = 0; |
d3fcc808 | 14079 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 14080 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 14081 | pll->active++; |
3e369b76 | 14082 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 14083 | } |
5358901f | 14084 | } |
5358901f | 14085 | |
1e6f2ddc | 14086 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 14087 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 14088 | |
3e369b76 | 14089 | if (pll->config.crtc_mask) |
bd2bb1b9 | 14090 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
14091 | } |
14092 | ||
b2784e15 | 14093 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14094 | pipe = 0; |
14095 | ||
14096 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
14097 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14098 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 14099 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
14100 | } else { |
14101 | encoder->base.crtc = NULL; | |
14102 | } | |
14103 | ||
14104 | encoder->connectors_active = false; | |
6f2bcceb | 14105 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 14106 | encoder->base.base.id, |
8e329a03 | 14107 | encoder->base.name, |
24929352 | 14108 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 14109 | pipe_name(pipe)); |
24929352 DV |
14110 | } |
14111 | ||
3a3371ff | 14112 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14113 | if (connector->get_hw_state(connector)) { |
14114 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
14115 | connector->encoder->connectors_active = true; | |
14116 | connector->base.encoder = &connector->encoder->base; | |
14117 | } else { | |
14118 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14119 | connector->base.encoder = NULL; | |
14120 | } | |
14121 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
14122 | connector->base.base.id, | |
c23cc417 | 14123 | connector->base.name, |
24929352 DV |
14124 | connector->base.encoder ? "enabled" : "disabled"); |
14125 | } | |
30e984df DV |
14126 | } |
14127 | ||
14128 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
14129 | * and i915 state tracking structures. */ | |
14130 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
14131 | bool force_restore) | |
14132 | { | |
14133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14134 | enum pipe pipe; | |
30e984df DV |
14135 | struct intel_crtc *crtc; |
14136 | struct intel_encoder *encoder; | |
35c95375 | 14137 | int i; |
30e984df DV |
14138 | |
14139 | intel_modeset_readout_hw_state(dev); | |
24929352 | 14140 | |
babea61d JB |
14141 | /* |
14142 | * Now that we have the config, copy it to each CRTC struct | |
14143 | * Note that this could go away if we move to using crtc_config | |
14144 | * checking everywhere. | |
14145 | */ | |
d3fcc808 | 14146 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 14147 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
14148 | intel_mode_from_pipe_config(&crtc->base.mode, |
14149 | crtc->config); | |
babea61d JB |
14150 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
14151 | crtc->base.base.id); | |
14152 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
14153 | } | |
14154 | } | |
14155 | ||
24929352 | 14156 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 14157 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14158 | intel_sanitize_encoder(encoder); |
14159 | } | |
14160 | ||
055e393f | 14161 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
14162 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
14163 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
14164 | intel_dump_pipe_config(crtc, crtc->config, |
14165 | "[setup_hw_state]"); | |
24929352 | 14166 | } |
9a935856 | 14167 | |
d29b2f9d ACO |
14168 | intel_modeset_update_connector_atomic_state(dev); |
14169 | ||
35c95375 DV |
14170 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14171 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14172 | ||
14173 | if (!pll->on || pll->active) | |
14174 | continue; | |
14175 | ||
14176 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14177 | ||
14178 | pll->disable(dev_priv, pll); | |
14179 | pll->on = false; | |
14180 | } | |
14181 | ||
3078999f PB |
14182 | if (IS_GEN9(dev)) |
14183 | skl_wm_get_hw_state(dev); | |
14184 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
14185 | ilk_wm_get_hw_state(dev); |
14186 | ||
45e2b5f6 | 14187 | if (force_restore) { |
7d0bc1ea VS |
14188 | i915_redisable_vga(dev); |
14189 | ||
f30da187 DV |
14190 | /* |
14191 | * We need to use raw interfaces for restoring state to avoid | |
14192 | * checking (bogus) intermediate states. | |
14193 | */ | |
055e393f | 14194 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
14195 | struct drm_crtc *crtc = |
14196 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 14197 | |
83a57153 | 14198 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
14199 | } |
14200 | } else { | |
14201 | intel_modeset_update_staged_output_state(dev); | |
14202 | } | |
8af6cf88 DV |
14203 | |
14204 | intel_modeset_check_state(dev); | |
2c7111db CW |
14205 | } |
14206 | ||
14207 | void intel_modeset_gem_init(struct drm_device *dev) | |
14208 | { | |
92122789 | 14209 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 14210 | struct drm_crtc *c; |
2ff8fde1 | 14211 | struct drm_i915_gem_object *obj; |
484b41dd | 14212 | |
ae48434c ID |
14213 | mutex_lock(&dev->struct_mutex); |
14214 | intel_init_gt_powersave(dev); | |
14215 | mutex_unlock(&dev->struct_mutex); | |
14216 | ||
92122789 JB |
14217 | /* |
14218 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14219 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14220 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14221 | * indicates as much. | |
14222 | */ | |
14223 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
14224 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14225 | DREF_SSC1_ENABLE); | |
14226 | ||
1833b134 | 14227 | intel_modeset_init_hw(dev); |
02e792fb DV |
14228 | |
14229 | intel_setup_overlay(dev); | |
484b41dd JB |
14230 | |
14231 | /* | |
14232 | * Make sure any fbs we allocated at startup are properly | |
14233 | * pinned & fenced. When we do the allocation it's too early | |
14234 | * for this. | |
14235 | */ | |
14236 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 14237 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
14238 | obj = intel_fb_obj(c->primary->fb); |
14239 | if (obj == NULL) | |
484b41dd JB |
14240 | continue; |
14241 | ||
850c4cdc TU |
14242 | if (intel_pin_and_fence_fb_obj(c->primary, |
14243 | c->primary->fb, | |
82bc3b2d | 14244 | c->primary->state, |
850c4cdc | 14245 | NULL)) { |
484b41dd JB |
14246 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
14247 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
14248 | drm_framebuffer_unreference(c->primary->fb); |
14249 | c->primary->fb = NULL; | |
afd65eb4 | 14250 | update_state_fb(c->primary); |
484b41dd JB |
14251 | } |
14252 | } | |
14253 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
14254 | |
14255 | intel_backlight_register(dev); | |
79e53945 JB |
14256 | } |
14257 | ||
4932e2c3 ID |
14258 | void intel_connector_unregister(struct intel_connector *intel_connector) |
14259 | { | |
14260 | struct drm_connector *connector = &intel_connector->base; | |
14261 | ||
14262 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 14263 | drm_connector_unregister(connector); |
4932e2c3 ID |
14264 | } |
14265 | ||
79e53945 JB |
14266 | void intel_modeset_cleanup(struct drm_device *dev) |
14267 | { | |
652c393a | 14268 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 14269 | struct drm_connector *connector; |
652c393a | 14270 | |
2eb5252e ID |
14271 | intel_disable_gt_powersave(dev); |
14272 | ||
0962c3c9 VS |
14273 | intel_backlight_unregister(dev); |
14274 | ||
fd0c0642 DV |
14275 | /* |
14276 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 14277 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
14278 | * experience fancy races otherwise. |
14279 | */ | |
2aeb7d3a | 14280 | intel_irq_uninstall(dev_priv); |
eb21b92b | 14281 | |
fd0c0642 DV |
14282 | /* |
14283 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
14284 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
14285 | */ | |
f87ea761 | 14286 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 14287 | |
652c393a JB |
14288 | mutex_lock(&dev->struct_mutex); |
14289 | ||
723bfd70 JB |
14290 | intel_unregister_dsm_handler(); |
14291 | ||
7ff0ebcc | 14292 | intel_fbc_disable(dev); |
e70236a8 | 14293 | |
69341a5e KH |
14294 | mutex_unlock(&dev->struct_mutex); |
14295 | ||
1630fe75 CW |
14296 | /* flush any delayed tasks or pending work */ |
14297 | flush_scheduled_work(); | |
14298 | ||
db31af1d JN |
14299 | /* destroy the backlight and sysfs files before encoders/connectors */ |
14300 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
14301 | struct intel_connector *intel_connector; |
14302 | ||
14303 | intel_connector = to_intel_connector(connector); | |
14304 | intel_connector->unregister(intel_connector); | |
db31af1d | 14305 | } |
d9255d57 | 14306 | |
79e53945 | 14307 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
14308 | |
14309 | intel_cleanup_overlay(dev); | |
ae48434c ID |
14310 | |
14311 | mutex_lock(&dev->struct_mutex); | |
14312 | intel_cleanup_gt_powersave(dev); | |
14313 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14314 | } |
14315 | ||
f1c79df3 ZW |
14316 | /* |
14317 | * Return which encoder is currently attached for connector. | |
14318 | */ | |
df0e9248 | 14319 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 14320 | { |
df0e9248 CW |
14321 | return &intel_attached_encoder(connector)->base; |
14322 | } | |
f1c79df3 | 14323 | |
df0e9248 CW |
14324 | void intel_connector_attach_encoder(struct intel_connector *connector, |
14325 | struct intel_encoder *encoder) | |
14326 | { | |
14327 | connector->encoder = encoder; | |
14328 | drm_mode_connector_attach_encoder(&connector->base, | |
14329 | &encoder->base); | |
79e53945 | 14330 | } |
28d52043 DA |
14331 | |
14332 | /* | |
14333 | * set vga decode state - true == enable VGA decode | |
14334 | */ | |
14335 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
14336 | { | |
14337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 14338 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
14339 | u16 gmch_ctrl; |
14340 | ||
75fa041d CW |
14341 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
14342 | DRM_ERROR("failed to read control word\n"); | |
14343 | return -EIO; | |
14344 | } | |
14345 | ||
c0cc8a55 CW |
14346 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
14347 | return 0; | |
14348 | ||
28d52043 DA |
14349 | if (state) |
14350 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
14351 | else | |
14352 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
14353 | |
14354 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
14355 | DRM_ERROR("failed to write control word\n"); | |
14356 | return -EIO; | |
14357 | } | |
14358 | ||
28d52043 DA |
14359 | return 0; |
14360 | } | |
c4a1d9e4 | 14361 | |
c4a1d9e4 | 14362 | struct intel_display_error_state { |
ff57f1b0 PZ |
14363 | |
14364 | u32 power_well_driver; | |
14365 | ||
63b66e5b CW |
14366 | int num_transcoders; |
14367 | ||
c4a1d9e4 CW |
14368 | struct intel_cursor_error_state { |
14369 | u32 control; | |
14370 | u32 position; | |
14371 | u32 base; | |
14372 | u32 size; | |
52331309 | 14373 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14374 | |
14375 | struct intel_pipe_error_state { | |
ddf9c536 | 14376 | bool power_domain_on; |
c4a1d9e4 | 14377 | u32 source; |
f301b1e1 | 14378 | u32 stat; |
52331309 | 14379 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
14380 | |
14381 | struct intel_plane_error_state { | |
14382 | u32 control; | |
14383 | u32 stride; | |
14384 | u32 size; | |
14385 | u32 pos; | |
14386 | u32 addr; | |
14387 | u32 surface; | |
14388 | u32 tile_offset; | |
52331309 | 14389 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
14390 | |
14391 | struct intel_transcoder_error_state { | |
ddf9c536 | 14392 | bool power_domain_on; |
63b66e5b CW |
14393 | enum transcoder cpu_transcoder; |
14394 | ||
14395 | u32 conf; | |
14396 | ||
14397 | u32 htotal; | |
14398 | u32 hblank; | |
14399 | u32 hsync; | |
14400 | u32 vtotal; | |
14401 | u32 vblank; | |
14402 | u32 vsync; | |
14403 | } transcoder[4]; | |
c4a1d9e4 CW |
14404 | }; |
14405 | ||
14406 | struct intel_display_error_state * | |
14407 | intel_display_capture_error_state(struct drm_device *dev) | |
14408 | { | |
fbee40df | 14409 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 14410 | struct intel_display_error_state *error; |
63b66e5b CW |
14411 | int transcoders[] = { |
14412 | TRANSCODER_A, | |
14413 | TRANSCODER_B, | |
14414 | TRANSCODER_C, | |
14415 | TRANSCODER_EDP, | |
14416 | }; | |
c4a1d9e4 CW |
14417 | int i; |
14418 | ||
63b66e5b CW |
14419 | if (INTEL_INFO(dev)->num_pipes == 0) |
14420 | return NULL; | |
14421 | ||
9d1cb914 | 14422 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
14423 | if (error == NULL) |
14424 | return NULL; | |
14425 | ||
190be112 | 14426 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
14427 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
14428 | ||
055e393f | 14429 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 14430 | error->pipe[i].power_domain_on = |
f458ebbc DV |
14431 | __intel_display_power_is_enabled(dev_priv, |
14432 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 14433 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
14434 | continue; |
14435 | ||
5efb3e28 VS |
14436 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
14437 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
14438 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
14439 | |
14440 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
14441 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 14442 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 14443 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
14444 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
14445 | } | |
ca291363 PZ |
14446 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
14447 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
14448 | if (INTEL_INFO(dev)->gen >= 4) { |
14449 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
14450 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
14451 | } | |
14452 | ||
c4a1d9e4 | 14453 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 14454 | |
3abfce77 | 14455 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 14456 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
14457 | } |
14458 | ||
14459 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
14460 | if (HAS_DDI(dev_priv->dev)) | |
14461 | error->num_transcoders++; /* Account for eDP. */ | |
14462 | ||
14463 | for (i = 0; i < error->num_transcoders; i++) { | |
14464 | enum transcoder cpu_transcoder = transcoders[i]; | |
14465 | ||
ddf9c536 | 14466 | error->transcoder[i].power_domain_on = |
f458ebbc | 14467 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 14468 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 14469 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
14470 | continue; |
14471 | ||
63b66e5b CW |
14472 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
14473 | ||
14474 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
14475 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
14476 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
14477 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
14478 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
14479 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
14480 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
14481 | } |
14482 | ||
14483 | return error; | |
14484 | } | |
14485 | ||
edc3d884 MK |
14486 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
14487 | ||
c4a1d9e4 | 14488 | void |
edc3d884 | 14489 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
14490 | struct drm_device *dev, |
14491 | struct intel_display_error_state *error) | |
14492 | { | |
055e393f | 14493 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
14494 | int i; |
14495 | ||
63b66e5b CW |
14496 | if (!error) |
14497 | return; | |
14498 | ||
edc3d884 | 14499 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 14500 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 14501 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 14502 | error->power_well_driver); |
055e393f | 14503 | for_each_pipe(dev_priv, i) { |
edc3d884 | 14504 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
14505 | err_printf(m, " Power: %s\n", |
14506 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 14507 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 14508 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
14509 | |
14510 | err_printf(m, "Plane [%d]:\n", i); | |
14511 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
14512 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 14513 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
14514 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
14515 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 14516 | } |
4b71a570 | 14517 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 14518 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 14519 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
14520 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
14521 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
14522 | } |
14523 | ||
edc3d884 MK |
14524 | err_printf(m, "Cursor [%d]:\n", i); |
14525 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
14526 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
14527 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 14528 | } |
63b66e5b CW |
14529 | |
14530 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 14531 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 14532 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
14533 | err_printf(m, " Power: %s\n", |
14534 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
14535 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
14536 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
14537 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
14538 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
14539 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
14540 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
14541 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
14542 | } | |
c4a1d9e4 | 14543 | } |
e2fcdaa9 VS |
14544 | |
14545 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
14546 | { | |
14547 | struct intel_crtc *crtc; | |
14548 | ||
14549 | for_each_intel_crtc(dev, crtc) { | |
14550 | struct intel_unpin_work *work; | |
e2fcdaa9 | 14551 | |
5e2d7afc | 14552 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14553 | |
14554 | work = crtc->unpin_work; | |
14555 | ||
14556 | if (work && work->event && | |
14557 | work->event->base.file_priv == file) { | |
14558 | kfree(work->event); | |
14559 | work->event = NULL; | |
14560 | } | |
14561 | ||
5e2d7afc | 14562 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
14563 | } |
14564 | } |