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drm/i915: Rename vlv_cdclk_freq to cdclk_freq
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
e7457a9a 108
0e32b39c
DA		 109static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
110{
111 if (!connector->mst_port)
112 return connector->encoder;
113 else
114 return &connector->mst_port->mst_encoders[pipe]->base;
115}
116
79e53945 117typedef struct {
0206e353 118 int min, max;
79e53945
JB		 119} intel_range_t;
120
121typedef struct {
0206e353
AJ		 122 int dot_limit;
123 int p2_slow, p2_fast;
79e53945
JB		 124} intel_p2_t;
125
d4906093
ML		 126typedef struct intel_limit intel_limit_t;
127struct intel_limit {
0206e353
AJ		 128 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_p2_t p2;
d4906093 130};
79e53945 131
d2acd215
DV		 132int
133intel_pch_rawclk(struct drm_device *dev)
134{
135 struct drm_i915_private *dev_priv = dev->dev_private;
136
137 WARN_ON(!HAS_PCH_SPLIT(dev));
138
139 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
140}
141
021357ac
CW		 142static inline u32 /* units of 100MHz */
143intel_fdi_link_freq(struct drm_device *dev)
144{
8b99e68c
CW		 145 if (IS_GEN5(dev)) {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 } else
149 return 27;
021357ac
CW		 150}
151
5d536e28 152static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 153 .dot = { .min = 25000, .max = 350000 },
9c333719 154 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 155 .n = { .min = 2, .max = 16 },
0206e353
AJ		 156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 163};
164
5d536e28
DV		 165static const intel_limit_t intel_limits_i8xx_dvo = {
166 .dot = { .min = 25000, .max = 350000 },
9c333719 167 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 168 .n = { .min = 2, .max = 16 },
5d536e28
DV		 169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 2, .max = 33 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 4, .p2_fast = 4 },
176};
177
e4b36699 178static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 179 .dot = { .min = 25000, .max = 350000 },
9c333719 180 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 181 .n = { .min = 2, .max = 16 },
0206e353
AJ		 182 .m = { .min = 96, .max = 140 },
183 .m1 = { .min = 18, .max = 26 },
184 .m2 = { .min = 6, .max = 16 },
185 .p = { .min = 4, .max = 128 },
186 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 187 .p2 = { .dot_limit = 165000,
188 .p2_slow = 14, .p2_fast = 7 },
e4b36699 189};
273e27ca 190
e4b36699 191static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 198 .p = { .min = 5, .max = 80 },
199 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 200 .p2 = { .dot_limit = 200000,
201 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 202};
203
204static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 205 .dot = { .min = 20000, .max = 400000 },
206 .vco = { .min = 1400000, .max = 2800000 },
207 .n = { .min = 1, .max = 6 },
208 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 209 .m1 = { .min = 8, .max = 18 },
210 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 211 .p = { .min = 7, .max = 98 },
212 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 213 .p2 = { .dot_limit = 112000,
214 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 215};
216
273e27ca 217
e4b36699 218static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 219 .dot = { .min = 25000, .max = 270000 },
220 .vco = { .min = 1750000, .max = 3500000},
221 .n = { .min = 1, .max = 4 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 10, .max = 30 },
226 .p1 = { .min = 1, .max = 3},
227 .p2 = { .dot_limit = 270000,
228 .p2_slow = 10,
229 .p2_fast = 10
044c7c41 230 },
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 234 .dot = { .min = 22000, .max = 400000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 4 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 16, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 5, .max = 80 },
241 .p1 = { .min = 1, .max = 8},
242 .p2 = { .dot_limit = 165000,
243 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 244};
245
246static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 247 .dot = { .min = 20000, .max = 115000 },
248 .vco = { .min = 1750000, .max = 3500000 },
249 .n = { .min = 1, .max = 3 },
250 .m = { .min = 104, .max = 138 },
251 .m1 = { .min = 17, .max = 23 },
252 .m2 = { .min = 5, .max = 11 },
253 .p = { .min = 28, .max = 112 },
254 .p1 = { .min = 2, .max = 8 },
255 .p2 = { .dot_limit = 0,
256 .p2_slow = 14, .p2_fast = 14
044c7c41 257 },
e4b36699
KP		 258};
259
260static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 261 .dot = { .min = 80000, .max = 224000 },
262 .vco = { .min = 1750000, .max = 3500000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 104, .max = 138 },
265 .m1 = { .min = 17, .max = 23 },
266 .m2 = { .min = 5, .max = 11 },
267 .p = { .min = 14, .max = 42 },
268 .p1 = { .min = 2, .max = 6 },
269 .p2 = { .dot_limit = 0,
270 .p2_slow = 7, .p2_fast = 7
044c7c41 271 },
e4b36699
KP		 272};
273
f2b115e6 274static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000},
276 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 277 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
273e27ca 280 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 5, .max = 80 },
284 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 285 .p2 = { .dot_limit = 200000,
286 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 287};
288
f2b115e6 289static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 290 .dot = { .min = 20000, .max = 400000 },
291 .vco = { .min = 1700000, .max = 3500000 },
292 .n = { .min = 3, .max = 6 },
293 .m = { .min = 2, .max = 256 },
294 .m1 = { .min = 0, .max = 0 },
295 .m2 = { .min = 0, .max = 254 },
296 .p = { .min = 7, .max = 112 },
297 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 298 .p2 = { .dot_limit = 112000,
299 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 300};
301
273e27ca
EA		 302/* Ironlake / Sandybridge
303 *
304 * We calculate clock using (register_value + 2) for N/M1/M2, so here
305 * the range value for them is (actual_value - 2).
306 */
b91ad0ec 307static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 5 },
311 .m = { .min = 79, .max = 127 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331};
332
333static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 3 },
337 .m = { .min = 79, .max = 127 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 14, .max = 56 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 344};
345
273e27ca 346/* LVDS 100mhz refclk limits. */
b91ad0ec 347static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 2 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 28, .max = 112 },
0206e353 355 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 358};
359
360static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 361 .dot = { .min = 25000, .max = 350000 },
362 .vco = { .min = 1760000, .max = 3510000 },
363 .n = { .min = 1, .max = 3 },
364 .m = { .min = 79, .max = 126 },
365 .m1 = { .min = 12, .max = 22 },
366 .m2 = { .min = 5, .max = 9 },
367 .p = { .min = 14, .max = 42 },
0206e353 368 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 369 .p2 = { .dot_limit = 225000,
370 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 371};
372
dc730512 373static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 374 /*
375 * These are the data rate limits (measured in fast clocks)
376 * since those are the strictest limits we have. The fast
377 * clock and actual rate limits are more relaxed, so checking
378 * them would make no difference.
379 */
380 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 381 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 382 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 383 .m1 = { .min = 2, .max = 3 },
384 .m2 = { .min = 11, .max = 156 },
b99ab663 385 .p1 = { .min = 2, .max = 3 },
5fdc9c49 386 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 387};
388
ef9348c8
CML		 389static const intel_limit_t intel_limits_chv = {
390 /*
391 * These are the data rate limits (measured in fast clocks)
392 * since those are the strictest limits we have. The fast
393 * clock and actual rate limits are more relaxed, so checking
394 * them would make no difference.
395 */
396 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 397 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 398 .n = { .min = 1, .max = 1 },
399 .m1 = { .min = 2, .max = 2 },
400 .m2 = { .min = 24 << 22, .max = 175 << 22 },
401 .p1 = { .min = 2, .max = 4 },
402 .p2 = { .p2_slow = 1, .p2_fast = 14 },
403};
404
6b4bf1c4
VS		 405static void vlv_clock(int refclk, intel_clock_t *clock)
406{
407 clock->m = clock->m1 * clock->m2;
408 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 409 if (WARN_ON(clock->n == 0 || clock->p == 0))
410 return;
fb03ac01
VS		 411 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
412 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 413}
414
e0638cdf
PZ		 415/**
416 * Returns whether any output on the specified pipe is of the specified type
417 */
4093561b 418bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 419{
409ee761 420 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 421 struct intel_encoder *encoder;
422
409ee761 423 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 424 if (encoder->type == type)
425 return true;
426
427 return false;
428}
429
d0737e1d
ACO		 430/**
431 * Returns whether any output on the specified pipe will have the specified
432 * type after a staged modeset is complete, i.e., the same as
433 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
434 * encoder->crtc.
435 */
a93e255f
ACO		 436static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
437 int type)
d0737e1d 438{
a93e255f
ACO		 439 struct drm_atomic_state *state = crtc_state->base.state;
440 struct drm_connector_state *connector_state;
d0737e1d 441 struct intel_encoder *encoder;
a93e255f
ACO		 442 int i, num_connectors = 0;
443
444 for (i = 0; i < state->num_connector; i++) {
445 if (!state->connectors[i])
446 continue;
447
448 connector_state = state->connector_states[i];
449 if (connector_state->crtc != crtc_state->base.crtc)
450 continue;
451
452 num_connectors++;
d0737e1d 453
a93e255f
ACO		 454 encoder = to_intel_encoder(connector_state->best_encoder);
455 if (encoder->type == type)
d0737e1d 456 return true;
a93e255f
ACO		 457 }
458
459 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 460
461 return false;
462}
463
a93e255f
ACO		 464static const intel_limit_t *
465intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 466{
a93e255f 467 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 468 const intel_limit_t *limit;
b91ad0ec 469
a93e255f 470 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 471 if (intel_is_dual_link_lvds(dev)) {
1b894b59 472 if (refclk == 100000)
b91ad0ec
ZW		 473 limit = &intel_limits_ironlake_dual_lvds_100m;
474 else
475 limit = &intel_limits_ironlake_dual_lvds;
476 } else {
1b894b59 477 if (refclk == 100000)
b91ad0ec
ZW		 478 limit = &intel_limits_ironlake_single_lvds_100m;
479 else
480 limit = &intel_limits_ironlake_single_lvds;
481 }
c6bb3538 482 } else
b91ad0ec 483 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 484
485 return limit;
486}
487
a93e255f
ACO		 488static const intel_limit_t *
489intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 490{
a93e255f 491 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 492 const intel_limit_t *limit;
493
a93e255f 494 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 495 if (intel_is_dual_link_lvds(dev))
e4b36699 496 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 497 else
e4b36699 498 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 499 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
500 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 501 limit = &intel_limits_g4x_hdmi;
a93e255f 502 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 503 limit = &intel_limits_g4x_sdvo;
044c7c41 504 } else /* The option is for other outputs */
e4b36699 505 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 506
507 return limit;
508}
509
a93e255f
ACO		 510static const intel_limit_t *
511intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 512{
a93e255f 513 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 514 const intel_limit_t *limit;
515
bad720ff 516 if (HAS_PCH_SPLIT(dev))
a93e255f 517 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 518 else if (IS_G4X(dev)) {
a93e255f 519 limit = intel_g4x_limit(crtc_state);
f2b115e6 520 } else if (IS_PINEVIEW(dev)) {
a93e255f 521 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 522 limit = &intel_limits_pineview_lvds;
2177832f 523 else
f2b115e6 524 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 525 } else if (IS_CHERRYVIEW(dev)) {
526 limit = &intel_limits_chv;
a0c4da24 527 } else if (IS_VALLEYVIEW(dev)) {
dc730512 528 limit = &intel_limits_vlv;
a6c45cf0 529 } else if (!IS_GEN2(dev)) {
a93e255f 530 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 531 limit = &intel_limits_i9xx_lvds;
532 else
533 limit = &intel_limits_i9xx_sdvo;
79e53945 534 } else {
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 536 limit = &intel_limits_i8xx_lvds;
a93e255f 537 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 538 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 539 else
540 limit = &intel_limits_i8xx_dac;
79e53945
JB		 541 }
542 return limit;
543}
544
f2b115e6
AJ		 545/* m1 is reserved as 0 in Pineview, n is a ring counter */
546static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 547{
2177832f
SL		 548 clock->m = clock->m2 + 2;
549 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
fb03ac01
VS		 552 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
553 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 554}
555
7429e9d4
DV		 556static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
557{
558 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
559}
560
ac58c3f0 561static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 562{
7429e9d4 563 clock->m = i9xx_dpll_compute_m(clock);
79e53945 564 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 565 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
566 return;
fb03ac01
VS		 567 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
568 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 569}
570
ef9348c8
CML		 571static void chv_clock(int refclk, intel_clock_t *clock)
572{
573 clock->m = clock->m1 * clock->m2;
574 clock->p = clock->p1 * clock->p2;
575 if (WARN_ON(clock->n == 0 || clock->p == 0))
576 return;
577 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
578 clock->n << 22);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580}
581
7c04d1d9 582#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 583/**
584 * Returns whether the given set of divisors are valid for a given refclk with
585 * the given connectors.
586 */
587
1b894b59
CW		 588static bool intel_PLL_is_valid(struct drm_device *dev,
589 const intel_limit_t *limit,
590 const intel_clock_t *clock)
79e53945 591{
f01b7962
VS		 592 if (clock->n < limit->n.min || limit->n.max < clock->n)
593 INTELPllInvalid("n out of range\n");
79e53945 594 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 595 INTELPllInvalid("p1 out of range\n");
79e53945 596 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 597 INTELPllInvalid("m2 out of range\n");
79e53945 598 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 599 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 600
601 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
602 if (clock->m1 <= clock->m2)
603 INTELPllInvalid("m1 <= m2\n");
604
605 if (!IS_VALLEYVIEW(dev)) {
606 if (clock->p < limit->p.min || limit->p.max < clock->p)
607 INTELPllInvalid("p out of range\n");
608 if (clock->m < limit->m.min || limit->m.max < clock->m)
609 INTELPllInvalid("m out of range\n");
610 }
611
79e53945 612 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 613 INTELPllInvalid("vco out of range\n");
79e53945
JB		 614 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
615 * connector, etc., rather than just a single range.
616 */
617 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 618 INTELPllInvalid("dot out of range\n");
79e53945
JB		 619
620 return true;
621}
622
d4906093 623static bool
a93e255f
ACO		 624i9xx_find_best_dpll(const intel_limit_t *limit,
625 struct intel_crtc_state *crtc_state,
cec2f356
SP		 626 int target, int refclk, intel_clock_t *match_clock,
627 intel_clock_t *best_clock)
79e53945 628{
a93e255f 629 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 630 struct drm_device *dev = crtc->base.dev;
79e53945 631 intel_clock_t clock;
79e53945
JB		 632 int err = target;
633
a93e255f 634 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 635 /*
a210b028
DV		 636 * For LVDS just rely on its current settings for dual-channel.
637 * We haven't figured out how to reliably set up different
638 * single/dual channel state, if we even can.
79e53945 639 */
1974cad0 640 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
0206e353 651 memset(best_clock, 0, sizeof(*best_clock));
79e53945 652
42158660
ZY		 653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 657 if (clock.m2 >= clock.m1)
42158660
ZY		 658 break;
659 for (clock.n = limit->n.min;
660 clock.n <= limit->n.max; clock.n++) {
661 for (clock.p1 = limit->p1.min;
662 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 663 int this_err;
664
ac58c3f0
DV		 665 i9xx_clock(refclk, &clock);
666 if (!intel_PLL_is_valid(dev, limit,
667 &clock))
668 continue;
669 if (match_clock &&
670 clock.p != match_clock->p)
671 continue;
672
673 this_err = abs(clock.dot - target);
674 if (this_err < err) {
675 *best_clock = clock;
676 err = this_err;
677 }
678 }
679 }
680 }
681 }
682
683 return (err != target);
684}
685
686static bool
a93e255f
ACO		 687pnv_find_best_dpll(const intel_limit_t *limit,
688 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
79e53945 691{
a93e255f 692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 693 struct drm_device *dev = crtc->base.dev;
79e53945 694 intel_clock_t clock;
79e53945
JB		 695 int err = target;
696
a93e255f 697 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 698 /*
a210b028
DV		 699 * For LVDS just rely on its current settings for dual-channel.
700 * We haven't figured out how to reliably set up different
701 * single/dual channel state, if we even can.
79e53945 702 */
1974cad0 703 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 720 for (clock.n = limit->n.min;
721 clock.n <= limit->n.max; clock.n++) {
722 for (clock.p1 = limit->p1.min;
723 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 724 int this_err;
725
ac58c3f0 726 pineview_clock(refclk, &clock);
1b894b59
CW		 727 if (!intel_PLL_is_valid(dev, limit,
728 &clock))
79e53945 729 continue;
cec2f356
SP		 730 if (match_clock &&
731 clock.p != match_clock->p)
732 continue;
79e53945
JB		 733
734 this_err = abs(clock.dot - target);
735 if (this_err < err) {
736 *best_clock = clock;
737 err = this_err;
738 }
739 }
740 }
741 }
742 }
743
744 return (err != target);
745}
746
d4906093 747static bool
a93e255f
ACO		 748g4x_find_best_dpll(const intel_limit_t *limit,
749 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093 752{
a93e255f 753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 754 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
a93e255f 762 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 763 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 764 clock.p2 = limit->p2.p2_fast;
765 else
766 clock.p2 = limit->p2.p2_slow;
767 } else {
768 if (target < limit->p2.dot_limit)
769 clock.p2 = limit->p2.p2_slow;
770 else
771 clock.p2 = limit->p2.p2_fast;
772 }
773
774 memset(best_clock, 0, sizeof(*best_clock));
775 max_n = limit->n.max;
f77f13e2 776 /* based on hardware requirement, prefer smaller n to precision */
d4906093 777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 778 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 779 for (clock.m1 = limit->m1.max;
780 clock.m1 >= limit->m1.min; clock.m1--) {
781 for (clock.m2 = limit->m2.max;
782 clock.m2 >= limit->m2.min; clock.m2--) {
783 for (clock.p1 = limit->p1.max;
784 clock.p1 >= limit->p1.min; clock.p1--) {
785 int this_err;
786
ac58c3f0 787 i9xx_clock(refclk, &clock);
1b894b59
CW		 788 if (!intel_PLL_is_valid(dev, limit,
789 &clock))
d4906093 790 continue;
1b894b59
CW		 791
792 this_err = abs(clock.dot - target);
d4906093
ML		 793 if (this_err < err_most) {
794 *best_clock = clock;
795 err_most = this_err;
796 max_n = clock.n;
797 found = true;
798 }
799 }
800 }
801 }
802 }
2c07245f
ZW		 803 return found;
804}
805
d5dd62bd
ID		 806/*
807 * Check if the calculated PLL configuration is more optimal compared to the
808 * best configuration and error found so far. Return the calculated error.
809 */
810static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
811 const intel_clock_t *calculated_clock,
812 const intel_clock_t *best_clock,
813 unsigned int best_error_ppm,
814 unsigned int *error_ppm)
815{
9ca3ba01
ID		 816 /*
817 * For CHV ignore the error and consider only the P value.
818 * Prefer a bigger P value based on HW requirements.
819 */
820 if (IS_CHERRYVIEW(dev)) {
821 *error_ppm = 0;
822
823 return calculated_clock->p > best_clock->p;
824 }
825
24be4e46
ID		 826 if (WARN_ON_ONCE(!target_freq))
827 return false;
828
d5dd62bd
ID		 829 *error_ppm = div_u64(1000000ULL *
830 abs(target_freq - calculated_clock->dot),
831 target_freq);
832 /*
833 * Prefer a better P value over a better (smaller) error if the error
834 * is small. Ensure this preference for future configurations too by
835 * setting the error to 0.
836 */
837 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
838 *error_ppm = 0;
839
840 return true;
841 }
842
843 return *error_ppm + 10 < best_error_ppm;
844}
845
a0c4da24 846static bool
a93e255f
ACO		 847vlv_find_best_dpll(const intel_limit_t *limit,
848 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 849 int target, int refclk, intel_clock_t *match_clock,
850 intel_clock_t *best_clock)
a0c4da24 851{
a93e255f 852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 853 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 854 intel_clock_t clock;
69e4f900 855 unsigned int bestppm = 1000000;
27e639bf
VS		 856 /* min update 19.2 MHz */
857 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 858 bool found = false;
a0c4da24 859
6b4bf1c4
VS		 860 target *= 5; /* fast clock */
861
862 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 863
864 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 865 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 866 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 867 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 868 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 869 clock.p = clock.p1 * clock.p2;
a0c4da24 870 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 871 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 872 unsigned int ppm;
69e4f900 873
6b4bf1c4
VS		 874 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
875 refclk * clock.m1);
876
877 vlv_clock(refclk, &clock);
43b0ac53 878
f01b7962
VS		 879 if (!intel_PLL_is_valid(dev, limit,
880 &clock))
43b0ac53
VS		 881 continue;
882
d5dd62bd
ID		 883 if (!vlv_PLL_is_optimal(dev, target,
884 &clock,
885 best_clock,
886 bestppm, &ppm))
887 continue;
6b4bf1c4 888
d5dd62bd
ID		 889 *best_clock = clock;
890 bestppm = ppm;
891 found = true;
a0c4da24
JB		 892 }
893 }
894 }
895 }
a0c4da24 896
49e497ef 897 return found;
a0c4da24 898}
a4fc5ed6 899
ef9348c8 900static bool
a93e255f
ACO		 901chv_find_best_dpll(const intel_limit_t *limit,
902 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 903 int target, int refclk, intel_clock_t *match_clock,
904 intel_clock_t *best_clock)
905{
a93e255f 906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 907 struct drm_device *dev = crtc->base.dev;
9ca3ba01 908 unsigned int best_error_ppm;
ef9348c8
CML		 909 intel_clock_t clock;
910 uint64_t m2;
911 int found = false;
912
913 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 914 best_error_ppm = 1000000;
ef9348c8
CML		 915
916 /*
917 * Based on hardware doc, the n always set to 1, and m1 always
918 * set to 2. If requires to support 200Mhz refclk, we need to
919 * revisit this because n may not 1 anymore.
920 */
921 clock.n = 1, clock.m1 = 2;
922 target *= 5; /* fast clock */
923
924 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
925 for (clock.p2 = limit->p2.p2_fast;
926 clock.p2 >= limit->p2.p2_slow;
927 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 928 unsigned int error_ppm;
ef9348c8
CML		 929
930 clock.p = clock.p1 * clock.p2;
931
932 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
933 clock.n) << 22, refclk * clock.m1);
934
935 if (m2 > INT_MAX/clock.m1)
936 continue;
937
938 clock.m2 = m2;
939
940 chv_clock(refclk, &clock);
941
942 if (!intel_PLL_is_valid(dev, limit, &clock))
943 continue;
944
9ca3ba01
ID		 945 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
946 best_error_ppm, &error_ppm))
947 continue;
948
949 *best_clock = clock;
950 best_error_ppm = error_ppm;
951 found = true;
ef9348c8
CML		 952 }
953 }
954
955 return found;
956}
957
20ddf665
VS		 958bool intel_crtc_active(struct drm_crtc *crtc)
959{
960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
961
962 /* Be paranoid as we can arrive here with only partial
963 * state retrieved from the hardware during setup.
964 *
241bfc38 965 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 966 * as Haswell has gained clock readout/fastboot support.
967 *
66e514c1 968 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 969 * properly reconstruct framebuffers.
c3d1f436
MR		 970 *
971 * FIXME: The intel_crtc->active here should be switched to
972 * crtc->state->active once we have proper CRTC states wired up
973 * for atomic.
20ddf665 974 */
c3d1f436 975 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 976 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 977}
978
a5c961d1
PZ		 979enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
980 enum pipe pipe)
981{
982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
6e3c9717 985 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 986}
987
fbf49ea2
VS		 988static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
989{
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 reg = PIPEDSL(pipe);
992 u32 line1, line2;
993 u32 line_mask;
994
995 if (IS_GEN2(dev))
996 line_mask = DSL_LINEMASK_GEN2;
997 else
998 line_mask = DSL_LINEMASK_GEN3;
999
1000 line1 = I915_READ(reg) & line_mask;
1001 mdelay(5);
1002 line2 = I915_READ(reg) & line_mask;
1003
1004 return line1 == line2;
1005}
1006
ab7ad7f6
KP		 1007/*
1008 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1009 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1010 *
1011 * After disabling a pipe, we can't wait for vblank in the usual way,
1012 * spinning on the vblank interrupt status bit, since we won't actually
1013 * see an interrupt when the pipe is disabled.
1014 *
ab7ad7f6
KP		 1015 * On Gen4 and above:
1016 * wait for the pipe register state bit to turn off
1017 *
1018 * Otherwise:
1019 * wait for the display line value to settle (it usually
1020 * ends up stopping at the start of the next frame).
58e10eb9 1021 *
9d0498a2 1022 */
575f7ab7 1023static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1024{
575f7ab7 1025 struct drm_device *dev = crtc->base.dev;
9d0498a2 1026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1028 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1029
1030 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1031 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1032
1033 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1034 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1035 100))
284637d9 1036 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1037 } else {
ab7ad7f6 1038 /* Wait for the display line to settle */
fbf49ea2 1039 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1040 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1041 }
79e53945
JB		 1042}
1043
b0ea7d37
DL		 1044/*
1045 * ibx_digital_port_connected - is the specified port connected?
1046 * @dev_priv: i915 private structure
1047 * @port: the port to test
1048 *
1049 * Returns true if @port is connected, false otherwise.
1050 */
1051bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1052 struct intel_digital_port *port)
1053{
1054 u32 bit;
1055
c36346e3 1056 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1057 switch (port->port) {
c36346e3
DL		 1058 case PORT_B:
1059 bit = SDE_PORTB_HOTPLUG;
1060 break;
1061 case PORT_C:
1062 bit = SDE_PORTC_HOTPLUG;
1063 break;
1064 case PORT_D:
1065 bit = SDE_PORTD_HOTPLUG;
1066 break;
1067 default:
1068 return true;
1069 }
1070 } else {
eba905b2 1071 switch (port->port) {
c36346e3
DL		 1072 case PORT_B:
1073 bit = SDE_PORTB_HOTPLUG_CPT;
1074 break;
1075 case PORT_C:
1076 bit = SDE_PORTC_HOTPLUG_CPT;
1077 break;
1078 case PORT_D:
1079 bit = SDE_PORTD_HOTPLUG_CPT;
1080 break;
1081 default:
1082 return true;
1083 }
b0ea7d37
DL		 1084 }
1085
1086 return I915_READ(SDEISR) & bit;
1087}
1088
b24e7179
JB		 1089static const char *state_string(bool enabled)
1090{
1091 return enabled ? "on" : "off";
1092}
1093
1094/* Only for pre-ILK configs */
55607e8a
DV		 1095void assert_pll(struct drm_i915_private *dev_priv,
1096 enum pipe pipe, bool state)
b24e7179
JB		 1097{
1098 int reg;
1099 u32 val;
1100 bool cur_state;
1101
1102 reg = DPLL(pipe);
1103 val = I915_READ(reg);
1104 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1105 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1106 "PLL state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108}
b24e7179 1109
23538ef1
JN		 1110/* XXX: the dsi pll is shared between MIPI DSI ports */
1111static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1112{
1113 u32 val;
1114 bool cur_state;
1115
1116 mutex_lock(&dev_priv->dpio_lock);
1117 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1118 mutex_unlock(&dev_priv->dpio_lock);
1119
1120 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1121 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1122 "DSI PLL state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1126#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1127
55607e8a 1128struct intel_shared_dpll *
e2b78267
DV		 1129intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1130{
1131 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1132
6e3c9717 1133 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1134 return NULL;
1135
6e3c9717 1136 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1137}
1138
040484af 1139/* For ILK+ */
55607e8a
DV		 1140void assert_shared_dpll(struct drm_i915_private *dev_priv,
1141 struct intel_shared_dpll *pll,
1142 bool state)
040484af 1143{
040484af 1144 bool cur_state;
5358901f 1145 struct intel_dpll_hw_state hw_state;
040484af 1146
92b27b08 1147 if (WARN (!pll,
46edb027 1148 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1149 return;
ee7b9f93 1150
5358901f 1151 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1152 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1153 "%s assertion failure (expected %s, current %s)\n",
1154 pll->name, state_string(state), state_string(cur_state));
040484af 1155}
040484af
JB		 1156
1157static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159{
1160 int reg;
1161 u32 val;
1162 bool cur_state;
ad80a810
PZ		 1163 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1164 pipe);
040484af 1165
affa9354
PZ		 1166 if (HAS_DDI(dev_priv->dev)) {
1167 /* DDI does not have a specific FDI_TX register */
ad80a810 1168 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1169 val = I915_READ(reg);
ad80a810 1170 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1171 } else {
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 cur_state = !!(val & FDI_TX_ENABLE);
1175 }
e2c719b7 1176 I915_STATE_WARN(cur_state != state,
040484af
JB		 1177 "FDI TX state assertion failure (expected %s, current %s)\n",
1178 state_string(state), state_string(cur_state));
1179}
1180#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1181#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1182
1183static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185{
1186 int reg;
1187 u32 val;
1188 bool cur_state;
1189
d63fa0dc
PZ		 1190 reg = FDI_RX_CTL(pipe);
1191 val = I915_READ(reg);
1192 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1193 I915_STATE_WARN(cur_state != state,
040484af
JB		 1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 state_string(state), state_string(cur_state));
1196}
1197#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202{
1203 int reg;
1204 u32 val;
1205
1206 /* ILK FDI PLL is always enabled */
3d13ef2e 1207 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1208 return;
1209
bf507ef7 1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1211 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1212 return;
1213
040484af
JB		 1214 reg = FDI_TX_CTL(pipe);
1215 val = I915_READ(reg);
e2c719b7 1216 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1217}
1218
55607e8a
DV		 1219void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
040484af
JB		 1221{
1222 int reg;
1223 u32 val;
55607e8a 1224 bool cur_state;
040484af
JB		 1225
1226 reg = FDI_RX_CTL(pipe);
1227 val = I915_READ(reg);
55607e8a 1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1229 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 state_string(state), state_string(cur_state));
040484af
JB		 1232}
1233
b680c37a
DV		 1234void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
ea0760cf 1236{
bedd4dba
JN		 1237 struct drm_device *dev = dev_priv->dev;
1238 int pp_reg;
ea0760cf
JB		 1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
0de3b485 1241 bool locked = true;
ea0760cf 1242
bedd4dba
JN		 1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
ea0760cf 1249 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
ea0760cf
JB		 1260 } else {
1261 pp_reg = PP_CONTROL;
bedd4dba
JN		 1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
ea0760cf
JB		 1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1269 locked = false;
1270
e2c719b7 1271 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1272 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1273 pipe_name(pipe));
ea0760cf
JB		 1274}
1275
93ce0ba6
JN		 1276static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278{
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
d9d82081 1282 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1283 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1284 else
5efb3e28 1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1286
e2c719b7 1287 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), state_string(state), state_string(cur_state));
1290}
1291#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
b840d907
JB		 1294void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
b24e7179
JB		 1296{
1297 int reg;
1298 u32 val;
63d7bbe9 1299 bool cur_state;
702e7a56
PZ		 1300 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1301 pipe);
b24e7179 1302
b6b5d049
VS		 1303 /* if we need the pipe quirk it must be always on */
1304 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1306 state = true;
1307
f458ebbc 1308 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1309 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1310 cur_state = false;
1311 } else {
1312 reg = PIPECONF(cpu_transcoder);
1313 val = I915_READ(reg);
1314 cur_state = !!(val & PIPECONF_ENABLE);
1315 }
1316
e2c719b7 1317 I915_STATE_WARN(cur_state != state,
63d7bbe9 1318 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1319 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1320}
1321
931872fc
CW		 1322static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
931872fc 1327 bool cur_state;
b24e7179
JB		 1328
1329 reg = DSPCNTR(plane);
1330 val = I915_READ(reg);
931872fc 1331 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1332 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1333 "plane %c assertion failure (expected %s, current %s)\n",
1334 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1335}
1336
931872fc
CW		 1337#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1338#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1339
b24e7179
JB		 1340static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe)
1342{
653e1026 1343 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1344 int reg, i;
1345 u32 val;
1346 int cur_pipe;
1347
653e1026
VS		 1348 /* Primary planes are fixed to pipes on gen4+ */
1349 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1350 reg = DSPCNTR(pipe);
1351 val = I915_READ(reg);
e2c719b7 1352 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1353 "plane %c assertion failure, should be disabled but not\n",
1354 plane_name(pipe));
19ec1358 1355 return;
28c05794 1356 }
19ec1358 1357
b24e7179 1358 /* Need to check both planes against the pipe */
055e393f 1359 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1360 reg = DSPCNTR(i);
1361 val = I915_READ(reg);
1362 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1363 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1364 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1365 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1367 }
1368}
1369
19332d7a
JB		 1370static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe)
1372{
20674eef 1373 struct drm_device *dev = dev_priv->dev;
1fe47785 1374 int reg, sprite;
19332d7a
JB		 1375 u32 val;
1376
7feb8b88 1377 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1378 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1379 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1380 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1381 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1382 sprite, pipe_name(pipe));
1383 }
1384 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1385 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1386 reg = SPCNTR(pipe, sprite);
20674eef 1387 val = I915_READ(reg);
e2c719b7 1388 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1390 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1391 }
1392 } else if (INTEL_INFO(dev)->gen >= 7) {
1393 reg = SPRCTL(pipe);
19332d7a 1394 val = I915_READ(reg);
e2c719b7 1395 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1396 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1397 plane_name(pipe), pipe_name(pipe));
1398 } else if (INTEL_INFO(dev)->gen >= 5) {
1399 reg = DVSCNTR(pipe);
19332d7a 1400 val = I915_READ(reg);
e2c719b7 1401 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1402 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1403 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1404 }
1405}
1406
08c71e5e
VS		 1407static void assert_vblank_disabled(struct drm_crtc *crtc)
1408{
e2c719b7 1409 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1410 drm_crtc_vblank_put(crtc);
1411}
1412
89eff4be 1413static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1414{
1415 u32 val;
1416 bool enabled;
1417
e2c719b7 1418 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1419
92f2584a
JB		 1420 val = I915_READ(PCH_DREF_CONTROL);
1421 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1422 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1423 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1424}
1425
ab9412ba
DV		 1426static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe)
92f2584a
JB		 1428{
1429 int reg;
1430 u32 val;
1431 bool enabled;
1432
ab9412ba 1433 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1434 val = I915_READ(reg);
1435 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1436 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1437 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1438 pipe_name(pipe));
92f2584a
JB		 1439}
1440
4e634389
KP		 1441static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1443{
1444 if ((val & DP_PORT_EN) == 0)
1445 return false;
1446
1447 if (HAS_PCH_CPT(dev_priv->dev)) {
1448 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1449 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1450 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1451 return false;
44f37d1f
CML		 1452 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1453 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1454 return false;
f0575e92
KP		 1455 } else {
1456 if ((val & DP_PIPE_MASK) != (pipe << 30))
1457 return false;
1458 }
1459 return true;
1460}
1461
1519b995
KP		 1462static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe, u32 val)
1464{
dc0fa718 1465 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1466 return false;
1467
1468 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1469 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1470 return false;
44f37d1f
CML		 1471 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1472 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1473 return false;
1519b995 1474 } else {
dc0fa718 1475 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1476 return false;
1477 }
1478 return true;
1479}
1480
1481static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, u32 val)
1483{
1484 if ((val & LVDS_PORT_EN) == 0)
1485 return false;
1486
1487 if (HAS_PCH_CPT(dev_priv->dev)) {
1488 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1489 return false;
1490 } else {
1491 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1492 return false;
1493 }
1494 return true;
1495}
1496
1497static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
1500 if ((val & ADPA_DAC_ENABLE) == 0)
1501 return false;
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504 return false;
1505 } else {
1506 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1507 return false;
1508 }
1509 return true;
1510}
1511
291906f1 1512static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1513 enum pipe pipe, int reg, u32 port_sel)
291906f1 1514{
47a05eca 1515 u32 val = I915_READ(reg);
e2c719b7 1516 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1517 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1518 reg, pipe_name(pipe));
de9a35ab 1519
e2c719b7 1520 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1521 && (val & DP_PIPEB_SELECT),
de9a35ab 1522 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1523}
1524
1525static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, int reg)
1527{
47a05eca 1528 u32 val = I915_READ(reg);
e2c719b7 1529 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1530 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1531 reg, pipe_name(pipe));
de9a35ab 1532
e2c719b7 1533 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1534 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1535 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1536}
1537
1538static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1539 enum pipe pipe)
1540{
1541 int reg;
1542 u32 val;
291906f1 1543
f0575e92
KP		 1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1545 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1546 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1547
1548 reg = PCH_ADPA;
1549 val = I915_READ(reg);
e2c719b7 1550 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1551 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1552 pipe_name(pipe));
291906f1
JB		 1553
1554 reg = PCH_LVDS;
1555 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1557 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 pipe_name(pipe));
291906f1 1559
e2debe91
PZ		 1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1561 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1562 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1563}
1564
40e9cf64
JB		 1565static void intel_init_dpio(struct drm_device *dev)
1566{
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568
1569 if (!IS_VALLEYVIEW(dev))
1570 return;
1571
a09caddd
CML		 1572 /*
1573 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1574 * CHV x1 PHY (DP/HDMI D)
1575 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1576 */
1577 if (IS_CHERRYVIEW(dev)) {
1578 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1580 } else {
1581 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1582 }
5382f5f3
JB		 1583}
1584
d288f65f 1585static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1586 const struct intel_crtc_state *pipe_config)
87442f73 1587{
426115cf
DV		 1588 struct drm_device *dev = crtc->base.dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 int reg = DPLL(crtc->pipe);
d288f65f 1591 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1592
426115cf 1593 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1594
1595 /* No really, not for ILK+ */
1596 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1597
1598 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1599 if (IS_MOBILE(dev_priv->dev))
426115cf 1600 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1601
426115cf
DV		 1602 I915_WRITE(reg, dpll);
1603 POSTING_READ(reg);
1604 udelay(150);
1605
1606 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1607 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1608
d288f65f 1609 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1610 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1611
1612 /* We do this three times for luck */
426115cf 1613 I915_WRITE(reg, dpll);
87442f73
DV		 1614 POSTING_READ(reg);
1615 udelay(150); /* wait for warmup */
426115cf 1616 I915_WRITE(reg, dpll);
87442f73
DV		 1617 POSTING_READ(reg);
1618 udelay(150); /* wait for warmup */
426115cf 1619 I915_WRITE(reg, dpll);
87442f73
DV		 1620 POSTING_READ(reg);
1621 udelay(150); /* wait for warmup */
1622}
1623
d288f65f 1624static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1625 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1626{
1627 struct drm_device *dev = crtc->base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 int pipe = crtc->pipe;
1630 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1631 u32 tmp;
1632
1633 assert_pipe_disabled(dev_priv, crtc->pipe);
1634
1635 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1636
1637 mutex_lock(&dev_priv->dpio_lock);
1638
1639 /* Enable back the 10bit clock to display controller */
1640 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1641 tmp |= DPIO_DCLKP_EN;
1642 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1643
1644 /*
1645 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1646 */
1647 udelay(1);
1648
1649 /* Enable PLL */
d288f65f 1650 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1651
1652 /* Check PLL is locked */
a11b0703 1653 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1654 DRM_ERROR("PLL %d failed to lock\n", pipe);
1655
a11b0703 1656 /* not sure when this should be written */
d288f65f 1657 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1658 POSTING_READ(DPLL_MD(pipe));
1659
9d556c99
CML		 1660 mutex_unlock(&dev_priv->dpio_lock);
1661}
1662
1c4e0274
VS		 1663static int intel_num_dvo_pipes(struct drm_device *dev)
1664{
1665 struct intel_crtc *crtc;
1666 int count = 0;
1667
1668 for_each_intel_crtc(dev, crtc)
1669 count += crtc->active &&
409ee761 1670 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1671
1672 return count;
1673}
1674
66e3d5c0 1675static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1676{
66e3d5c0
DV		 1677 struct drm_device *dev = crtc->base.dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 int reg = DPLL(crtc->pipe);
6e3c9717 1680 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1681
66e3d5c0 1682 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1683
63d7bbe9 1684 /* No really, not for ILK+ */
3d13ef2e 1685 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1686
1687 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1688 if (IS_MOBILE(dev) && !IS_I830(dev))
1689 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1690
1c4e0274
VS		 1691 /* Enable DVO 2x clock on both PLLs if necessary */
1692 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1693 /*
1694 * It appears to be important that we don't enable this
1695 * for the current pipe before otherwise configuring the
1696 * PLL. No idea how this should be handled if multiple
1697 * DVO outputs are enabled simultaneosly.
1698 */
1699 dpll |= DPLL_DVO_2X_MODE;
1700 I915_WRITE(DPLL(!crtc->pipe),
1701 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1702 }
66e3d5c0
DV		 1703
1704 /* Wait for the clocks to stabilize. */
1705 POSTING_READ(reg);
1706 udelay(150);
1707
1708 if (INTEL_INFO(dev)->gen >= 4) {
1709 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1710 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1711 } else {
1712 /* The pixel multiplier can only be updated once the
1713 * DPLL is enabled and the clocks are stable.
1714 *
1715 * So write it again.
1716 */
1717 I915_WRITE(reg, dpll);
1718 }
63d7bbe9
JB		 1719
1720 /* We do this three times for luck */
66e3d5c0 1721 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1722 POSTING_READ(reg);
1723 udelay(150); /* wait for warmup */
66e3d5c0 1724 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1725 POSTING_READ(reg);
1726 udelay(150); /* wait for warmup */
66e3d5c0 1727 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1728 POSTING_READ(reg);
1729 udelay(150); /* wait for warmup */
1730}
1731
1732/**
50b44a44 1733 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1734 * @dev_priv: i915 private structure
1735 * @pipe: pipe PLL to disable
1736 *
1737 * Disable the PLL for @pipe, making sure the pipe is off first.
1738 *
1739 * Note! This is for pre-ILK only.
1740 */
1c4e0274 1741static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1742{
1c4e0274
VS		 1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 enum pipe pipe = crtc->pipe;
1746
1747 /* Disable DVO 2x clock on both PLLs if necessary */
1748 if (IS_I830(dev) &&
409ee761 1749 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1750 intel_num_dvo_pipes(dev) == 1) {
1751 I915_WRITE(DPLL(PIPE_B),
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1753 I915_WRITE(DPLL(PIPE_A),
1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1755 }
1756
b6b5d049
VS		 1757 /* Don't disable pipe or pipe PLLs if needed */
1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1760 return;
1761
1762 /* Make sure the pipe isn't still relying on us */
1763 assert_pipe_disabled(dev_priv, pipe);
1764
50b44a44
DV		 1765 I915_WRITE(DPLL(pipe), 0);
1766 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1767}
1768
f6071166
JB		 1769static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1770{
1771 u32 val = 0;
1772
1773 /* Make sure the pipe isn't still relying on us */
1774 assert_pipe_disabled(dev_priv, pipe);
1775
e5cbfbfb
ID		 1776 /*
1777 * Leave integrated clock source and reference clock enabled for pipe B.
1778 * The latter is needed for VGA hotplug / manual detection.
1779 */
f6071166 1780 if (pipe == PIPE_B)
e5cbfbfb 1781 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1782 I915_WRITE(DPLL(pipe), val);
1783 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1784
1785}
1786
1787static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788{
d752048d 1789 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1790 u32 val;
1791
a11b0703
VS		 1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1794
a11b0703 1795 /* Set PLL en = 0 */
d17ec4ce 1796 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1797 if (pipe != PIPE_A)
1798 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1799 I915_WRITE(DPLL(pipe), val);
1800 POSTING_READ(DPLL(pipe));
d752048d
VS		 1801
1802 mutex_lock(&dev_priv->dpio_lock);
1803
1804 /* Disable 10bit clock to display controller */
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1806 val &= ~DPIO_DCLKP_EN;
1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1808
61407f6d
VS		 1809 /* disable left/right clock distribution */
1810 if (pipe != PIPE_B) {
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1812 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1814 } else {
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1816 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1818 }
1819
d752048d 1820 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1821}
1822
e4607fcf
CML		 1823void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1824 struct intel_digital_port *dport)
89b667f8
JB		 1825{
1826 u32 port_mask;
00fc31b7 1827 int dpll_reg;
89b667f8 1828
e4607fcf
CML		 1829 switch (dport->port) {
1830 case PORT_B:
89b667f8 1831 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1832 dpll_reg = DPLL(0);
e4607fcf
CML		 1833 break;
1834 case PORT_C:
89b667f8 1835 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_D:
1839 port_mask = DPLL_PORTD_READY_MASK;
1840 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1841 break;
1842 default:
1843 BUG();
1844 }
89b667f8 1845
00fc31b7 1846 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1847 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1848 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1849}
1850
b14b1055
DV		 1851static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1852{
1853 struct drm_device *dev = crtc->base.dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1856
be19f0ff
CW		 1857 if (WARN_ON(pll == NULL))
1858 return;
1859
3e369b76 1860 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1861 if (pll->active == 0) {
1862 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1863 WARN_ON(pll->on);
1864 assert_shared_dpll_disabled(dev_priv, pll);
1865
1866 pll->mode_set(dev_priv, pll);
1867 }
1868}
1869
92f2584a 1870/**
85b3894f 1871 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1872 * @dev_priv: i915 private structure
1873 * @pipe: pipe PLL to enable
1874 *
1875 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1876 * drives the transcoder clock.
1877 */
85b3894f 1878static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1879{
3d13ef2e
DL		 1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1883
87a875bb 1884 if (WARN_ON(pll == NULL))
48da64a8
CW		 1885 return;
1886
3e369b76 1887 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1888 return;
ee7b9f93 1889
74dd6928 1890 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1891 pll->name, pll->active, pll->on,
e2b78267 1892 crtc->base.base.id);
92f2584a 1893
cdbd2316
DV		 1894 if (pll->active++) {
1895 WARN_ON(!pll->on);
e9d6944e 1896 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1897 return;
1898 }
f4a091c7 1899 WARN_ON(pll->on);
ee7b9f93 1900
bd2bb1b9
PZ		 1901 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1902
46edb027 1903 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1904 pll->enable(dev_priv, pll);
ee7b9f93 1905 pll->on = true;
92f2584a
JB		 1906}
1907
f6daaec2 1908static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1909{
3d13ef2e
DL		 1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1913
92f2584a 1914 /* PCH only available on ILK+ */
3d13ef2e 1915 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1916 if (WARN_ON(pll == NULL))
ee7b9f93 1917 return;
92f2584a 1918
3e369b76 1919 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1920 return;
7a419866 1921
46edb027
DV		 1922 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1923 pll->name, pll->active, pll->on,
e2b78267 1924 crtc->base.base.id);
7a419866 1925
48da64a8 1926 if (WARN_ON(pll->active == 0)) {
e9d6944e 1927 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1928 return;
1929 }
1930
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1932 WARN_ON(!pll->on);
cdbd2316 1933 if (--pll->active)
7a419866 1934 return;
ee7b9f93 1935
46edb027 1936 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1937 pll->disable(dev_priv, pll);
ee7b9f93 1938 pll->on = false;
bd2bb1b9
PZ		 1939
1940 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1941}
1942
b8a4f404
PZ		 1943static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1944 enum pipe pipe)
040484af 1945{
23670b32 1946 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1949 uint32_t reg, val, pipeconf_val;
040484af
JB		 1950
1951 /* PCH only available on ILK+ */
55522f37 1952 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1953
1954 /* Make sure PCH DPLL is enabled */
e72f9fbf 1955 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1956 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1957
1958 /* FDI must be feeding us bits for PCH ports */
1959 assert_fdi_tx_enabled(dev_priv, pipe);
1960 assert_fdi_rx_enabled(dev_priv, pipe);
1961
23670b32
DV		 1962 if (HAS_PCH_CPT(dev)) {
1963 /* Workaround: Set the timing override bit before enabling the
1964 * pch transcoder. */
1965 reg = TRANS_CHICKEN2(pipe);
1966 val = I915_READ(reg);
1967 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(reg, val);
59c859d6 1969 }
23670b32 1970
ab9412ba 1971 reg = PCH_TRANSCONF(pipe);
040484af 1972 val = I915_READ(reg);
5f7f726d 1973 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1974
1975 if (HAS_PCH_IBX(dev_priv->dev)) {
1976 /*
1977 * make the BPC in transcoder be consistent with
1978 * that in pipeconf reg.
1979 */
dfd07d72
DV		 1980 val &= ~PIPECONF_BPC_MASK;
1981 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1982 }
5f7f726d
PZ		 1983
1984 val &= ~TRANS_INTERLACE_MASK;
1985 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1986 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1987 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1988 val |= TRANS_LEGACY_INTERLACED_ILK;
1989 else
1990 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
040484af
JB		 1994 I915_WRITE(reg, val | TRANS_ENABLE);
1995 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1996 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1997}
1998
8fb033d7 1999static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2000 enum transcoder cpu_transcoder)
040484af 2001{
8fb033d7 2002 u32 val, pipeconf_val;
8fb033d7
PZ		 2003
2004 /* PCH only available on ILK+ */
55522f37 2005 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2006
8fb033d7 2007 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2008 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2009 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2010
223a6fdf
PZ		 2011 /* Workaround: set timing override bit. */
2012 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2013 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2014 I915_WRITE(_TRANSA_CHICKEN2, val);
2015
25f3ef11 2016 val = TRANS_ENABLE;
937bb610 2017 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2018
9a76b1c6
PZ		 2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2020 PIPECONF_INTERLACED_ILK)
a35f2679 2021 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2022 else
2023 val |= TRANS_PROGRESSIVE;
2024
ab9412ba
DV		 2025 I915_WRITE(LPT_TRANSCONF, val);
2026 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2027 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2028}
2029
b8a4f404
PZ		 2030static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2031 enum pipe pipe)
040484af 2032{
23670b32
DV		 2033 struct drm_device *dev = dev_priv->dev;
2034 uint32_t reg, val;
040484af
JB		 2035
2036 /* FDI relies on the transcoder */
2037 assert_fdi_tx_disabled(dev_priv, pipe);
2038 assert_fdi_rx_disabled(dev_priv, pipe);
2039
291906f1
JB		 2040 /* Ports must be off as well */
2041 assert_pch_ports_disabled(dev_priv, pipe);
2042
ab9412ba 2043 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2044 val = I915_READ(reg);
2045 val &= ~TRANS_ENABLE;
2046 I915_WRITE(reg, val);
2047 /* wait for PCH transcoder off, transcoder state */
2048 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2049 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2050
2051 if (!HAS_PCH_IBX(dev)) {
2052 /* Workaround: Clear the timing override chicken bit again. */
2053 reg = TRANS_CHICKEN2(pipe);
2054 val = I915_READ(reg);
2055 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2056 I915_WRITE(reg, val);
2057 }
040484af
JB		 2058}
2059
ab4d966c 2060static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2061{
8fb033d7
PZ		 2062 u32 val;
2063
ab9412ba 2064 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2065 val &= ~TRANS_ENABLE;
ab9412ba 2066 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2067 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2068 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2069 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2070
2071 /* Workaround: clear timing override bit. */
2072 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2074 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2075}
2076
b24e7179 2077/**
309cfea8 2078 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2079 * @crtc: crtc responsible for the pipe
b24e7179 2080 *
0372264a 2081 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2082 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2083 */
e1fdc473 2084static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2085{
0372264a
PZ		 2086 struct drm_device *dev = crtc->base.dev;
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2090 pipe);
1a240d4d 2091 enum pipe pch_transcoder;
b24e7179
JB		 2092 int reg;
2093 u32 val;
2094
58c6eaa2 2095 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2096 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2097 assert_sprites_disabled(dev_priv, pipe);
2098
681e5811 2099 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2100 pch_transcoder = TRANSCODER_A;
2101 else
2102 pch_transcoder = pipe;
2103
b24e7179
JB		 2104 /*
2105 * A pipe without a PLL won't actually be able to drive bits from
2106 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2107 * need the check.
2108 */
2109 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2111 assert_dsi_pll_enabled(dev_priv);
2112 else
2113 assert_pll_enabled(dev_priv, pipe);
040484af 2114 else {
6e3c9717 2115 if (crtc->config->has_pch_encoder) {
040484af 2116 /* if driving the PCH, we need FDI enabled */
cc391bbb 2117 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2118 assert_fdi_tx_pll_enabled(dev_priv,
2119 (enum pipe) cpu_transcoder);
040484af
JB		 2120 }
2121 /* FIXME: assert CPU port conditions for SNB+ */
2122 }
b24e7179 2123
702e7a56 2124 reg = PIPECONF(cpu_transcoder);
b24e7179 2125 val = I915_READ(reg);
7ad25d48 2126 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2129 return;
7ad25d48 2130 }
00d70b15
CW		 2131
2132 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2133 POSTING_READ(reg);
b24e7179
JB		 2134}
2135
2136/**
309cfea8 2137 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2138 * @crtc: crtc whose pipes is to be disabled
b24e7179 2139 *
575f7ab7
VS		 2140 * Disable the pipe of @crtc, making sure that various hardware
2141 * specific requirements are met, if applicable, e.g. plane
2142 * disabled, panel fitter off, etc.
b24e7179
JB		 2143 *
2144 * Will wait until the pipe has shut down before returning.
2145 */
575f7ab7 2146static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2147{
575f7ab7 2148 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2149 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2150 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2151 int reg;
2152 u32 val;
2153
2154 /*
2155 * Make sure planes won't keep trying to pump pixels to us,
2156 * or we might hang the display.
2157 */
2158 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2159 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2160 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
00d70b15
CW		 2164 if ((val & PIPECONF_ENABLE) == 0)
2165 return;
2166
67adc644
VS		 2167 /*
2168 * Double wide has implications for planes
2169 * so best keep it disabled when not needed.
2170 */
6e3c9717 2171 if (crtc->config->double_wide)
67adc644
VS		 2172 val &= ~PIPECONF_DOUBLE_WIDE;
2173
2174 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2177 val &= ~PIPECONF_ENABLE;
2178
2179 I915_WRITE(reg, val);
2180 if ((val & PIPECONF_ENABLE) == 0)
2181 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2182}
2183
d74362c9
KP		 2184/*
2185 * Plane regs are double buffered, going from enabled->disabled needs a
2186 * trigger in order to latch. The display address reg provides this.
2187 */
1dba99f4
VS		 2188void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2189 enum plane plane)
d74362c9 2190{
3d13ef2e
DL		 2191 struct drm_device *dev = dev_priv->dev;
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2193
2194 I915_WRITE(reg, I915_READ(reg));
2195 POSTING_READ(reg);
d74362c9
KP		 2196}
2197
b24e7179 2198/**
262ca2b0 2199 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2200 * @plane: plane to be enabled
2201 * @crtc: crtc for the plane
b24e7179 2202 *
fdd508a6 2203 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2204 */
fdd508a6
VS		 2205static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2206 struct drm_crtc *crtc)
b24e7179 2207{
fdd508a6
VS		 2208 struct drm_device *dev = plane->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2211
2212 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2214
98ec7739
VS		 2215 if (intel_crtc->primary_enabled)
2216 return;
0037f71c 2217
4c445e0e 2218 intel_crtc->primary_enabled = true;
939c2fe8 2219
fdd508a6
VS		 2220 dev_priv->display.update_primary_plane(crtc, plane->fb,
2221 crtc->x, crtc->y);
33c3b0d1
VS		 2222
2223 /*
2224 * BDW signals flip done immediately if the plane
2225 * is disabled, even if the plane enable is already
2226 * armed to occur at the next vblank :(
2227 */
2228 if (IS_BROADWELL(dev))
2229 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2230}
2231
b24e7179 2232/**
262ca2b0 2233 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2234 * @plane: plane to be disabled
2235 * @crtc: crtc for the plane
b24e7179 2236 *
fdd508a6 2237 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2238 */
fdd508a6
VS		 2239static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2240 struct drm_crtc *crtc)
b24e7179 2241{
fdd508a6
VS		 2242 struct drm_device *dev = plane->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2245
32b7eeec
MR		 2246 if (WARN_ON(!intel_crtc->active))
2247 return;
b24e7179 2248
98ec7739
VS		 2249 if (!intel_crtc->primary_enabled)
2250 return;
0037f71c 2251
4c445e0e 2252 intel_crtc->primary_enabled = false;
939c2fe8 2253
fdd508a6
VS		 2254 dev_priv->display.update_primary_plane(crtc, plane->fb,
2255 crtc->x, crtc->y);
b24e7179
JB		 2256}
2257
693db184
CW		 2258static bool need_vtd_wa(struct drm_device *dev)
2259{
2260#ifdef CONFIG_INTEL_IOMMU
2261 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2262 return true;
2263#endif
2264 return false;
2265}
2266
50470bb0 2267unsigned int
6761dd31
TU		 2268intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2269 uint64_t fb_format_modifier)
a57ce0b2 2270{
6761dd31
TU		 2271 unsigned int tile_height;
2272 uint32_t pixel_bytes;
a57ce0b2 2273
b5d0e9bf
DL		 2274 switch (fb_format_modifier) {
2275 case DRM_FORMAT_MOD_NONE:
2276 tile_height = 1;
2277 break;
2278 case I915_FORMAT_MOD_X_TILED:
2279 tile_height = IS_GEN2(dev) ? 16 : 8;
2280 break;
2281 case I915_FORMAT_MOD_Y_TILED:
2282 tile_height = 32;
2283 break;
2284 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2285 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2286 switch (pixel_bytes) {
b5d0e9bf 2287 default:
6761dd31 2288 case 1:
b5d0e9bf
DL		 2289 tile_height = 64;
2290 break;
6761dd31
TU		 2291 case 2:
2292 case 4:
b5d0e9bf
DL		 2293 tile_height = 32;
2294 break;
6761dd31 2295 case 8:
b5d0e9bf
DL		 2296 tile_height = 16;
2297 break;
6761dd31 2298 case 16:
b5d0e9bf
DL		 2299 WARN_ONCE(1,
2300 "128-bit pixels are not supported for display!");
2301 tile_height = 16;
2302 break;
2303 }
2304 break;
2305 default:
2306 MISSING_CASE(fb_format_modifier);
2307 tile_height = 1;
2308 break;
2309 }
091df6cb 2310
6761dd31
TU		 2311 return tile_height;
2312}
2313
2314unsigned int
2315intel_fb_align_height(struct drm_device *dev, unsigned int height,
2316 uint32_t pixel_format, uint64_t fb_format_modifier)
2317{
2318 return ALIGN(height, intel_tile_height(dev, pixel_format,
2319 fb_format_modifier));
a57ce0b2
JB		 2320}
2321
f64b98cd
TU		 2322static int
2323intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2324 const struct drm_plane_state *plane_state)
2325{
50470bb0 2326 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2327
f64b98cd
TU		 2328 *view = i915_ggtt_view_normal;
2329
50470bb0
TU		 2330 if (!plane_state)
2331 return 0;
2332
121920fa 2333 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2334 return 0;
2335
9abc4648 2336 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2337
2338 info->height = fb->height;
2339 info->pixel_format = fb->pixel_format;
2340 info->pitch = fb->pitches[0];
2341 info->fb_modifier = fb->modifier[0];
2342
f64b98cd
TU		 2343 return 0;
2344}
2345
127bd2ac 2346int
850c4cdc
TU		 2347intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2348 struct drm_framebuffer *fb,
82bc3b2d 2349 const struct drm_plane_state *plane_state,
a4872ba6 2350 struct intel_engine_cs *pipelined)
6b95a207 2351{
850c4cdc 2352 struct drm_device *dev = fb->dev;
ce453d81 2353 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2354 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2355 struct i915_ggtt_view view;
6b95a207
KH		 2356 u32 alignment;
2357 int ret;
2358
ebcdd39e
MR		 2359 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2360
7b911adc
TU		 2361 switch (fb->modifier[0]) {
2362 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2363 if (INTEL_INFO(dev)->gen >= 9)
2364 alignment = 256 * 1024;
2365 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2366 alignment = 128 * 1024;
a6c45cf0 2367 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2368 alignment = 4 * 1024;
2369 else
2370 alignment = 64 * 1024;
6b95a207 2371 break;
7b911adc 2372 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2373 if (INTEL_INFO(dev)->gen >= 9)
2374 alignment = 256 * 1024;
2375 else {
2376 /* pin() will align the object as required by fence */
2377 alignment = 0;
2378 }
6b95a207 2379 break;
7b911adc 2380 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2381 case I915_FORMAT_MOD_Yf_TILED:
2382 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2383 "Y tiling bo slipped through, driver bug!\n"))
2384 return -EINVAL;
2385 alignment = 1 * 1024 * 1024;
2386 break;
6b95a207 2387 default:
7b911adc
TU		 2388 MISSING_CASE(fb->modifier[0]);
2389 return -EINVAL;
6b95a207
KH		 2390 }
2391
f64b98cd
TU		 2392 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2393 if (ret)
2394 return ret;
2395
693db184
CW		 2396 /* Note that the w/a also requires 64 PTE of padding following the
2397 * bo. We currently fill all unused PTE with the shadow page and so
2398 * we should always have valid PTE following the scanout preventing
2399 * the VT-d warning.
2400 */
2401 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2402 alignment = 256 * 1024;
2403
d6dd6843
PZ		 2404 /*
2405 * Global gtt pte registers are special registers which actually forward
2406 * writes to a chunk of system memory. Which means that there is no risk
2407 * that the register values disappear as soon as we call
2408 * intel_runtime_pm_put(), so it is correct to wrap only the
2409 * pin/unpin/fence and not more.
2410 */
2411 intel_runtime_pm_get(dev_priv);
2412
ce453d81 2413 dev_priv->mm.interruptible = false;
e6617330 2414 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2415 &view);
48b956c5 2416 if (ret)
ce453d81 2417 goto err_interruptible;
6b95a207
KH		 2418
2419 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2420 * fence, whereas 965+ only requires a fence if using
2421 * framebuffer compression. For simplicity, we always install
2422 * a fence as the cost is not that onerous.
2423 */
06d98131 2424 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2425 if (ret)
2426 goto err_unpin;
1690e1eb 2427
9a5a53b3 2428 i915_gem_object_pin_fence(obj);
6b95a207 2429
ce453d81 2430 dev_priv->mm.interruptible = true;
d6dd6843 2431 intel_runtime_pm_put(dev_priv);
6b95a207 2432 return 0;
48b956c5
CW		 2433
2434err_unpin:
f64b98cd 2435 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2436err_interruptible:
2437 dev_priv->mm.interruptible = true;
d6dd6843 2438 intel_runtime_pm_put(dev_priv);
48b956c5 2439 return ret;
6b95a207
KH		 2440}
2441
82bc3b2d
TU		 2442static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2443 const struct drm_plane_state *plane_state)
1690e1eb 2444{
82bc3b2d 2445 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2446 struct i915_ggtt_view view;
2447 int ret;
82bc3b2d 2448
ebcdd39e
MR		 2449 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2450
f64b98cd
TU		 2451 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2452 WARN_ONCE(ret, "Couldn't get view from plane state!");
2453
1690e1eb 2454 i915_gem_object_unpin_fence(obj);
f64b98cd 2455 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2456}
2457
c2c75131
DV		 2458/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2459 * is assumed to be a power-of-two. */
bc752862
CW		 2460unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2461 unsigned int tiling_mode,
2462 unsigned int cpp,
2463 unsigned int pitch)
c2c75131 2464{
bc752862
CW		 2465 if (tiling_mode != I915_TILING_NONE) {
2466 unsigned int tile_rows, tiles;
c2c75131 2467
bc752862
CW		 2468 tile_rows = *y / 8;
2469 *y %= 8;
c2c75131 2470
bc752862
CW		 2471 tiles = *x / (512/cpp);
2472 *x %= 512/cpp;
2473
2474 return tile_rows * pitch * 8 + tiles * 4096;
2475 } else {
2476 unsigned int offset;
2477
2478 offset = *y * pitch + *x * cpp;
2479 *y = 0;
2480 *x = (offset & 4095) / cpp;
2481 return offset & -4096;
2482 }
c2c75131
DV		 2483}
2484
b35d63fa 2485static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2486{
2487 switch (format) {
2488 case DISPPLANE_8BPP:
2489 return DRM_FORMAT_C8;
2490 case DISPPLANE_BGRX555:
2491 return DRM_FORMAT_XRGB1555;
2492 case DISPPLANE_BGRX565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case DISPPLANE_BGRX888:
2496 return DRM_FORMAT_XRGB8888;
2497 case DISPPLANE_RGBX888:
2498 return DRM_FORMAT_XBGR8888;
2499 case DISPPLANE_BGRX101010:
2500 return DRM_FORMAT_XRGB2101010;
2501 case DISPPLANE_RGBX101010:
2502 return DRM_FORMAT_XBGR2101010;
2503 }
2504}
2505
bc8d7dff
DL		 2506static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2507{
2508 switch (format) {
2509 case PLANE_CTL_FORMAT_RGB_565:
2510 return DRM_FORMAT_RGB565;
2511 default:
2512 case PLANE_CTL_FORMAT_XRGB_8888:
2513 if (rgb_order) {
2514 if (alpha)
2515 return DRM_FORMAT_ABGR8888;
2516 else
2517 return DRM_FORMAT_XBGR8888;
2518 } else {
2519 if (alpha)
2520 return DRM_FORMAT_ARGB8888;
2521 else
2522 return DRM_FORMAT_XRGB8888;
2523 }
2524 case PLANE_CTL_FORMAT_XRGB_2101010:
2525 if (rgb_order)
2526 return DRM_FORMAT_XBGR2101010;
2527 else
2528 return DRM_FORMAT_XRGB2101010;
2529 }
2530}
2531
5724dbd1 2532static bool
f6936e29
DV		 2533intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2534 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2535{
2536 struct drm_device *dev = crtc->base.dev;
2537 struct drm_i915_gem_object *obj = NULL;
2538 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2539 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2540 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2541 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2542 PAGE_SIZE);
2543
2544 size_aligned -= base_aligned;
46f297fb 2545
ff2652ea
CW		 2546 if (plane_config->size == 0)
2547 return false;
2548
f37b5c2b
DV		 2549 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2550 base_aligned,
2551 base_aligned,
2552 size_aligned);
46f297fb 2553 if (!obj)
484b41dd 2554 return false;
46f297fb 2555
49af449b
DL		 2556 obj->tiling_mode = plane_config->tiling;
2557 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2558 obj->stride = fb->pitches[0];
46f297fb 2559
6bf129df
DL		 2560 mode_cmd.pixel_format = fb->pixel_format;
2561 mode_cmd.width = fb->width;
2562 mode_cmd.height = fb->height;
2563 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2564 mode_cmd.modifier[0] = fb->modifier[0];
2565 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2566
2567 mutex_lock(&dev->struct_mutex);
6bf129df 2568 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2569 &mode_cmd, obj)) {
46f297fb
JB		 2570 DRM_DEBUG_KMS("intel fb init failed\n");
2571 goto out_unref_obj;
2572 }
46f297fb 2573 mutex_unlock(&dev->struct_mutex);
484b41dd 2574
f6936e29 2575 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2576 return true;
46f297fb
JB		 2577
2578out_unref_obj:
2579 drm_gem_object_unreference(&obj->base);
2580 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2581 return false;
2582}
2583
afd65eb4
MR		 2584/* Update plane->state->fb to match plane->fb after driver-internal updates */
2585static void
2586update_state_fb(struct drm_plane *plane)
2587{
2588 if (plane->fb == plane->state->fb)
2589 return;
2590
2591 if (plane->state->fb)
2592 drm_framebuffer_unreference(plane->state->fb);
2593 plane->state->fb = plane->fb;
2594 if (plane->state->fb)
2595 drm_framebuffer_reference(plane->state->fb);
2596}
2597
5724dbd1 2598static void
f6936e29
DV		 2599intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2600 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2601{
2602 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2603 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2604 struct drm_crtc *c;
2605 struct intel_crtc *i;
2ff8fde1 2606 struct drm_i915_gem_object *obj;
88595ac9
DV		 2607 struct drm_plane *primary = intel_crtc->base.primary;
2608 struct drm_framebuffer *fb;
484b41dd 2609
2d14030b 2610 if (!plane_config->fb)
484b41dd
JB		 2611 return;
2612
f6936e29 2613 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2614 fb = &plane_config->fb->base;
2615 goto valid_fb;
f55548b5 2616 }
484b41dd 2617
2d14030b 2618 kfree(plane_config->fb);
484b41dd
JB		 2619
2620 /*
2621 * Failed to alloc the obj, check to see if we should share
2622 * an fb with another CRTC instead
2623 */
70e1e0ec 2624 for_each_crtc(dev, c) {
484b41dd
JB		 2625 i = to_intel_crtc(c);
2626
2627 if (c == &intel_crtc->base)
2628 continue;
2629
2ff8fde1
MR		 2630 if (!i->active)
2631 continue;
2632
88595ac9
DV		 2633 fb = c->primary->fb;
2634 if (!fb)
484b41dd
JB		 2635 continue;
2636
88595ac9 2637 obj = intel_fb_obj(fb);
2ff8fde1 2638 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2639 drm_framebuffer_reference(fb);
2640 goto valid_fb;
484b41dd
JB		 2641 }
2642 }
88595ac9
DV		 2643
2644 return;
2645
2646valid_fb:
2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2650
2651 primary->fb = fb;
2652 primary->state->crtc = &intel_crtc->base;
2653 primary->crtc = &intel_crtc->base;
2654 update_state_fb(primary);
2655 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2656}
2657
29b9bde6
DV		 2658static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2660 int x, int y)
81255565
JB		 2661{
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2665 struct drm_i915_gem_object *obj;
81255565 2666 int plane = intel_crtc->plane;
e506a0c6 2667 unsigned long linear_offset;
81255565 2668 u32 dspcntr;
f45651ba 2669 u32 reg = DSPCNTR(plane);
48404c1e 2670 int pixel_size;
f45651ba 2671
fdd508a6
VS		 2672 if (!intel_crtc->primary_enabled) {
2673 I915_WRITE(reg, 0);
2674 if (INTEL_INFO(dev)->gen >= 4)
2675 I915_WRITE(DSPSURF(plane), 0);
2676 else
2677 I915_WRITE(DSPADDR(plane), 0);
2678 POSTING_READ(reg);
2679 return;
2680 }
2681
c9ba6fad
VS		 2682 obj = intel_fb_obj(fb);
2683 if (WARN_ON(obj == NULL))
2684 return;
2685
2686 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2687
f45651ba
VS		 2688 dspcntr = DISPPLANE_GAMMA_ENABLE;
2689
fdd508a6 2690 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2691
2692 if (INTEL_INFO(dev)->gen < 4) {
2693 if (intel_crtc->pipe == PIPE_B)
2694 dspcntr |= DISPPLANE_SEL_PIPE_B;
2695
2696 /* pipesrc and dspsize control the size that is scaled from,
2697 * which should always be the user's requested size.
2698 */
2699 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2700 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2701 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2702 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2703 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2704 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2707 I915_WRITE(PRIMPOS(plane), 0);
2708 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2709 }
81255565 2710
57779d06
VS		 2711 switch (fb->pixel_format) {
2712 case DRM_FORMAT_C8:
81255565
JB		 2713 dspcntr |= DISPPLANE_8BPP;
2714 break;
57779d06
VS		 2715 case DRM_FORMAT_XRGB1555:
2716 case DRM_FORMAT_ARGB1555:
2717 dspcntr |= DISPPLANE_BGRX555;
81255565 2718 break;
57779d06
VS		 2719 case DRM_FORMAT_RGB565:
2720 dspcntr |= DISPPLANE_BGRX565;
2721 break;
2722 case DRM_FORMAT_XRGB8888:
2723 case DRM_FORMAT_ARGB8888:
2724 dspcntr |= DISPPLANE_BGRX888;
2725 break;
2726 case DRM_FORMAT_XBGR8888:
2727 case DRM_FORMAT_ABGR8888:
2728 dspcntr |= DISPPLANE_RGBX888;
2729 break;
2730 case DRM_FORMAT_XRGB2101010:
2731 case DRM_FORMAT_ARGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 case DRM_FORMAT_ABGR2101010:
2736 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2737 break;
2738 default:
baba133a 2739 BUG();
81255565 2740 }
57779d06 2741
f45651ba
VS		 2742 if (INTEL_INFO(dev)->gen >= 4 &&
2743 obj->tiling_mode != I915_TILING_NONE)
2744 dspcntr |= DISPPLANE_TILED;
81255565 2745
de1aa629
VS		 2746 if (IS_G4X(dev))
2747 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2748
b9897127 2749 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2750
c2c75131
DV		 2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 intel_crtc->dspaddr_offset =
bc752862 2753 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2754 pixel_size,
bc752862 2755 fb->pitches[0]);
c2c75131
DV		 2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
e506a0c6 2758 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2759 }
e506a0c6 2760
8e7d688b 2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
6e3c9717
ACO		 2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
6e3c9717
ACO		 2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2772 }
2773
2774 I915_WRITE(reg, dspcntr);
2775
01f2c773 2776 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2777 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2778 I915_WRITE(DSPSURF(plane),
2779 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2780 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2781 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2782 } else
f343c5f6 2783 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2784 POSTING_READ(reg);
17638cd6
JB		 2785}
2786
29b9bde6
DV		 2787static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2788 struct drm_framebuffer *fb,
2789 int x, int y)
17638cd6
JB		 2790{
2791 struct drm_device *dev = crtc->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2794 struct drm_i915_gem_object *obj;
17638cd6 2795 int plane = intel_crtc->plane;
e506a0c6 2796 unsigned long linear_offset;
17638cd6 2797 u32 dspcntr;
f45651ba 2798 u32 reg = DSPCNTR(plane);
48404c1e 2799 int pixel_size;
f45651ba 2800
fdd508a6
VS		 2801 if (!intel_crtc->primary_enabled) {
2802 I915_WRITE(reg, 0);
2803 I915_WRITE(DSPSURF(plane), 0);
2804 POSTING_READ(reg);
2805 return;
2806 }
2807
c9ba6fad
VS		 2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2810 return;
2811
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
f45651ba
VS		 2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
fdd508a6 2816 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2817
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2820
57779d06
VS		 2821 switch (fb->pixel_format) {
2822 case DRM_FORMAT_C8:
17638cd6
JB		 2823 dspcntr |= DISPPLANE_8BPP;
2824 break;
57779d06
VS		 2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2827 break;
57779d06
VS		 2828 case DRM_FORMAT_XRGB8888:
2829 case DRM_FORMAT_ARGB8888:
2830 dspcntr |= DISPPLANE_BGRX888;
2831 break;
2832 case DRM_FORMAT_XBGR8888:
2833 case DRM_FORMAT_ABGR8888:
2834 dspcntr |= DISPPLANE_RGBX888;
2835 break;
2836 case DRM_FORMAT_XRGB2101010:
2837 case DRM_FORMAT_ARGB2101010:
2838 dspcntr |= DISPPLANE_BGRX101010;
2839 break;
2840 case DRM_FORMAT_XBGR2101010:
2841 case DRM_FORMAT_ABGR2101010:
2842 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2843 break;
2844 default:
baba133a 2845 BUG();
17638cd6
JB		 2846 }
2847
2848 if (obj->tiling_mode != I915_TILING_NONE)
2849 dspcntr |= DISPPLANE_TILED;
17638cd6 2850
f45651ba 2851 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2852 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2853
b9897127 2854 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2855 intel_crtc->dspaddr_offset =
bc752862 2856 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2857 pixel_size,
bc752862 2858 fb->pitches[0]);
c2c75131 2859 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2860 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2861 dspcntr |= DISPPLANE_ROTATE_180;
2862
2863 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2864 x += (intel_crtc->config->pipe_src_w - 1);
2865 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2866
2867 /* Finding the last pixel of the last line of the display
2868 data and adding to linear_offset*/
2869 linear_offset +=
6e3c9717
ACO		 2870 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2871 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2872 }
2873 }
2874
2875 I915_WRITE(reg, dspcntr);
17638cd6 2876
01f2c773 2877 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2878 I915_WRITE(DSPSURF(plane),
2879 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2881 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2882 } else {
2883 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2884 I915_WRITE(DSPLINOFF(plane), linear_offset);
2885 }
17638cd6 2886 POSTING_READ(reg);
17638cd6
JB		 2887}
2888
b321803d
DL		 2889u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2890 uint32_t pixel_format)
2891{
2892 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2893
2894 /*
2895 * The stride is either expressed as a multiple of 64 bytes
2896 * chunks for linear buffers or in number of tiles for tiled
2897 * buffers.
2898 */
2899 switch (fb_modifier) {
2900 case DRM_FORMAT_MOD_NONE:
2901 return 64;
2902 case I915_FORMAT_MOD_X_TILED:
2903 if (INTEL_INFO(dev)->gen == 2)
2904 return 128;
2905 return 512;
2906 case I915_FORMAT_MOD_Y_TILED:
2907 /* No need to check for old gens and Y tiling since this is
2908 * about the display engine and those will be blocked before
2909 * we get here.
2910 */
2911 return 128;
2912 case I915_FORMAT_MOD_Yf_TILED:
2913 if (bits_per_pixel == 8)
2914 return 64;
2915 else
2916 return 128;
2917 default:
2918 MISSING_CASE(fb_modifier);
2919 return 64;
2920 }
2921}
2922
121920fa
TU		 2923unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2924 struct drm_i915_gem_object *obj)
2925{
9abc4648 2926 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2927
2928 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2929 view = &i915_ggtt_view_rotated;
121920fa
TU		 2930
2931 return i915_gem_obj_ggtt_offset_view(obj, view);
2932}
2933
a1b2278e
CK		 2934/*
2935 * This function detaches (aka. unbinds) unused scalers in hardware
2936 */
2937void skl_detach_scalers(struct intel_crtc *intel_crtc)
2938{
2939 struct drm_device *dev;
2940 struct drm_i915_private *dev_priv;
2941 struct intel_crtc_scaler_state *scaler_state;
2942 int i;
2943
2944 if (!intel_crtc || !intel_crtc->config)
2945 return;
2946
2947 dev = intel_crtc->base.dev;
2948 dev_priv = dev->dev_private;
2949 scaler_state = &intel_crtc->config->scaler_state;
2950
2951 /* loop through and disable scalers that aren't in use */
2952 for (i = 0; i < intel_crtc->num_scalers; i++) {
2953 if (!scaler_state->scalers[i].in_use) {
2954 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2955 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2956 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2957 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2958 intel_crtc->base.base.id, intel_crtc->pipe, i);
2959 }
2960 }
2961}
2962
70d21f0e
DL		 2963static void skylake_update_primary_plane(struct drm_crtc *crtc,
2964 struct drm_framebuffer *fb,
2965 int x, int y)
2966{
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2970 struct drm_i915_gem_object *obj;
2971 int pipe = intel_crtc->pipe;
3b7a5119
SJ		 2972 u32 plane_ctl, stride_div, stride;
2973 u32 tile_height, plane_offset, plane_size;
2974 unsigned int rotation;
2975 int x_offset, y_offset;
121920fa 2976 unsigned long surf_addr;
3b7a5119 2977 struct drm_plane *plane;
70d21f0e
DL		 2978
2979 if (!intel_crtc->primary_enabled) {
2980 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2981 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2982 POSTING_READ(PLANE_CTL(pipe, 0));
2983 return;
2984 }
2985
2986 plane_ctl = PLANE_CTL_ENABLE |
2987 PLANE_CTL_PIPE_GAMMA_ENABLE |
2988 PLANE_CTL_PIPE_CSC_ENABLE;
2989
2990 switch (fb->pixel_format) {
2991 case DRM_FORMAT_RGB565:
2992 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2993 break;
2994 case DRM_FORMAT_XRGB8888:
2995 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2996 break;
f75fb42a
JN		 2997 case DRM_FORMAT_ARGB8888:
2998 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2999 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3000 break;
70d21f0e
DL		 3001 case DRM_FORMAT_XBGR8888:
3002 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3003 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3004 break;
f75fb42a
JN		 3005 case DRM_FORMAT_ABGR8888:
3006 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3007 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3008 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3009 break;
70d21f0e
DL		 3010 case DRM_FORMAT_XRGB2101010:
3011 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3012 break;
3013 case DRM_FORMAT_XBGR2101010:
3014 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3015 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3016 break;
3017 default:
3018 BUG();
3019 }
3020
30af77c4
DV		 3021 switch (fb->modifier[0]) {
3022 case DRM_FORMAT_MOD_NONE:
70d21f0e 3023 break;
30af77c4 3024 case I915_FORMAT_MOD_X_TILED:
70d21f0e 3025 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 3026 break;
3027 case I915_FORMAT_MOD_Y_TILED:
3028 plane_ctl |= PLANE_CTL_TILED_Y;
3029 break;
3030 case I915_FORMAT_MOD_Yf_TILED:
3031 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3032 break;
3033 default:
b321803d 3034 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3035 }
3036
3037 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3b7a5119
SJ		 3038
3039 plane = crtc->primary;
3040 rotation = plane->state->rotation;
3041 switch (rotation) {
3042 case BIT(DRM_ROTATE_90):
3043 plane_ctl |= PLANE_CTL_ROTATE_90;
3044 break;
3045
3046 case BIT(DRM_ROTATE_180):
1447dde0 3047 plane_ctl |= PLANE_CTL_ROTATE_180;
3b7a5119
SJ		 3048 break;
3049
3050 case BIT(DRM_ROTATE_270):
3051 plane_ctl |= PLANE_CTL_ROTATE_270;
3052 break;
3053 }
70d21f0e 3054
b321803d
DL		 3055 obj = intel_fb_obj(fb);
3056 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3057 fb->pixel_format);
3b7a5119
SJ		 3058 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3059
3060 if (intel_rotation_90_or_270(rotation)) {
3061 /* stride = Surface height in tiles */
3062 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3063 fb->modifier[0]);
3064 stride = DIV_ROUND_UP(fb->height, tile_height);
3065 x_offset = stride * tile_height - y - (plane->state->src_h >> 16);
3066 y_offset = x;
3067 plane_size = ((plane->state->src_w >> 16) - 1) << 16 |
3068 ((plane->state->src_h >> 16) - 1);
3069 } else {
3070 stride = fb->pitches[0] / stride_div;
3071 x_offset = x;
3072 y_offset = y;
3073 plane_size = ((plane->state->src_h >> 16) - 1) << 16 |
3074 ((plane->state->src_w >> 16) - 1);
3075 }
3076 plane_offset = y_offset << 16 | x_offset;
b321803d 3077
70d21f0e 3078 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e 3079 I915_WRITE(PLANE_POS(pipe, 0), 0);
3b7a5119
SJ		 3080 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3081 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3082 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
121920fa 3083 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3084
3085 POSTING_READ(PLANE_SURF(pipe, 0));
3086}
3087
17638cd6
JB		 3088/* Assume fb object is pinned & idle & fenced and just update base pointers */
3089static int
3090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3091 int x, int y, enum mode_set_atomic state)
3092{
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3095
6b8e6ed0
CW		 3096 if (dev_priv->display.disable_fbc)
3097 dev_priv->display.disable_fbc(dev);
81255565 3098
29b9bde6
DV		 3099 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3100
3101 return 0;
81255565
JB		 3102}
3103
7514747d 3104static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3105{
96a02917
VS		 3106 struct drm_crtc *crtc;
3107
70e1e0ec 3108 for_each_crtc(dev, crtc) {
96a02917
VS		 3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110 enum plane plane = intel_crtc->plane;
3111
3112 intel_prepare_page_flip(dev, plane);
3113 intel_finish_page_flip_plane(dev, plane);
3114 }
7514747d
VS		 3115}
3116
3117static void intel_update_primary_planes(struct drm_device *dev)
3118{
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120 struct drm_crtc *crtc;
96a02917 3121
70e1e0ec 3122 for_each_crtc(dev, crtc) {
96a02917
VS		 3123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3124
51fd371b 3125 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3126 /*
3127 * FIXME: Once we have proper support for primary planes (and
3128 * disabling them without disabling the entire crtc) allow again
66e514c1 3129 * a NULL crtc->primary->fb.
947fdaad 3130 */
f4510a27 3131 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3132 dev_priv->display.update_primary_plane(crtc,
66e514c1 3133 crtc->primary->fb,
262ca2b0
MR		 3134 crtc->x,
3135 crtc->y);
51fd371b 3136 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3137 }
3138}
3139
7514747d
VS		 3140void intel_prepare_reset(struct drm_device *dev)
3141{
f98ce92f
VS		 3142 struct drm_i915_private *dev_priv = to_i915(dev);
3143 struct intel_crtc *crtc;
3144
7514747d
VS		 3145 /* no reset support for gen2 */
3146 if (IS_GEN2(dev))
3147 return;
3148
3149 /* reset doesn't touch the display */
3150 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3151 return;
3152
3153 drm_modeset_lock_all(dev);
f98ce92f
VS		 3154
3155 /*
3156 * Disabling the crtcs gracefully seems nicer. Also the
3157 * g33 docs say we should at least disable all the planes.
3158 */
3159 for_each_intel_crtc(dev, crtc) {
3160 if (crtc->active)
3161 dev_priv->display.crtc_disable(&crtc->base);
3162 }
7514747d
VS		 3163}
3164
3165void intel_finish_reset(struct drm_device *dev)
3166{
3167 struct drm_i915_private *dev_priv = to_i915(dev);
3168
3169 /*
3170 * Flips in the rings will be nuked by the reset,
3171 * so complete all pending flips so that user space
3172 * will get its events and not get stuck.
3173 */
3174 intel_complete_page_flips(dev);
3175
3176 /* no reset support for gen2 */
3177 if (IS_GEN2(dev))
3178 return;
3179
3180 /* reset doesn't touch the display */
3181 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3182 /*
3183 * Flips in the rings have been nuked by the reset,
3184 * so update the base address of all primary
3185 * planes to the the last fb to make sure we're
3186 * showing the correct fb after a reset.
3187 */
3188 intel_update_primary_planes(dev);
3189 return;
3190 }
3191
3192 /*
3193 * The display has been reset as well,
3194 * so need a full re-initialization.
3195 */
3196 intel_runtime_pm_disable_interrupts(dev_priv);
3197 intel_runtime_pm_enable_interrupts(dev_priv);
3198
3199 intel_modeset_init_hw(dev);
3200
3201 spin_lock_irq(&dev_priv->irq_lock);
3202 if (dev_priv->display.hpd_irq_setup)
3203 dev_priv->display.hpd_irq_setup(dev);
3204 spin_unlock_irq(&dev_priv->irq_lock);
3205
3206 intel_modeset_setup_hw_state(dev, true);
3207
3208 intel_hpd_init(dev_priv);
3209
3210 drm_modeset_unlock_all(dev);
3211}
3212
14667a4b
CW		 3213static int
3214intel_finish_fb(struct drm_framebuffer *old_fb)
3215{
2ff8fde1 3216 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3217 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3218 bool was_interruptible = dev_priv->mm.interruptible;
3219 int ret;
3220
14667a4b
CW		 3221 /* Big Hammer, we also need to ensure that any pending
3222 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3223 * current scanout is retired before unpinning the old
3224 * framebuffer.
3225 *
3226 * This should only fail upon a hung GPU, in which case we
3227 * can safely continue.
3228 */
3229 dev_priv->mm.interruptible = false;
3230 ret = i915_gem_object_finish_gpu(obj);
3231 dev_priv->mm.interruptible = was_interruptible;
3232
3233 return ret;
3234}
3235
7d5e3799
CW		 3236static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3241 bool pending;
3242
3243 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245 return false;
3246
5e2d7afc 3247 spin_lock_irq(&dev->event_lock);
7d5e3799 3248 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3249 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3250
3251 return pending;
3252}
3253
e30e8f75
GP		 3254static void intel_update_pipe_size(struct intel_crtc *crtc)
3255{
3256 struct drm_device *dev = crtc->base.dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 const struct drm_display_mode *adjusted_mode;
3259
3260 if (!i915.fastboot)
3261 return;
3262
3263 /*
3264 * Update pipe size and adjust fitter if needed: the reason for this is
3265 * that in compute_mode_changes we check the native mode (not the pfit
3266 * mode) to see if we can flip rather than do a full mode set. In the
3267 * fastboot case, we'll flip, but if we don't update the pipesrc and
3268 * pfit state, we'll end up with a big fb scanned out into the wrong
3269 * sized surface.
3270 *
3271 * To fix this properly, we need to hoist the checks up into
3272 * compute_mode_changes (or above), check the actual pfit state and
3273 * whether the platform allows pfit disable with pipe active, and only
3274 * then update the pipesrc and pfit state, even on the flip path.
3275 */
3276
6e3c9717 3277 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3278
3279 I915_WRITE(PIPESRC(crtc->pipe),
3280 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3281 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3282 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3283 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3284 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3285 I915_WRITE(PF_CTL(crtc->pipe), 0);
3286 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3287 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3288 }
6e3c9717
ACO		 3289 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3290 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3291}
3292
5e84e1a4
ZW		 3293static void intel_fdi_normal_train(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298 int pipe = intel_crtc->pipe;
3299 u32 reg, temp;
3300
3301 /* enable normal train */
3302 reg = FDI_TX_CTL(pipe);
3303 temp = I915_READ(reg);
61e499bf 3304 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3307 } else {
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3310 }
5e84e1a4
ZW		 3311 I915_WRITE(reg, temp);
3312
3313 reg = FDI_RX_CTL(pipe);
3314 temp = I915_READ(reg);
3315 if (HAS_PCH_CPT(dev)) {
3316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3318 } else {
3319 temp &= ~FDI_LINK_TRAIN_NONE;
3320 temp |= FDI_LINK_TRAIN_NONE;
3321 }
3322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3323
3324 /* wait one idle pattern time */
3325 POSTING_READ(reg);
3326 udelay(1000);
357555c0
JB		 3327
3328 /* IVB wants error correction enabled */
3329 if (IS_IVYBRIDGE(dev))
3330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3331 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3332}
3333
8db9d77b
ZW		 3334/* The FDI link training functions for ILK/Ibexpeak. */
3335static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3336{
3337 struct drm_device *dev = crtc->dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int pipe = intel_crtc->pipe;
5eddb70b 3341 u32 reg, temp, tries;
8db9d77b 3342
1c8562f6 3343 /* FDI needs bits from pipe first */
0fc932b8 3344 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3345
e1a44743
AJ		 3346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3347 for train result */
5eddb70b
CW		 3348 reg = FDI_RX_IMR(pipe);
3349 temp = I915_READ(reg);
e1a44743
AJ		 3350 temp &= ~FDI_RX_SYMBOL_LOCK;
3351 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3352 I915_WRITE(reg, temp);
3353 I915_READ(reg);
e1a44743
AJ		 3354 udelay(150);
3355
8db9d77b 3356 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3357 reg = FDI_TX_CTL(pipe);
3358 temp = I915_READ(reg);
627eb5a3 3359 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3360 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3363 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3364
5eddb70b
CW		 3365 reg = FDI_RX_CTL(pipe);
3366 temp = I915_READ(reg);
8db9d77b
ZW		 3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3369 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3370
3371 POSTING_READ(reg);
8db9d77b
ZW		 3372 udelay(150);
3373
5b2adf89 3374 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3375 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3376 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3377 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3378
5eddb70b 3379 reg = FDI_RX_IIR(pipe);
e1a44743 3380 for (tries = 0; tries < 5; tries++) {
5eddb70b 3381 temp = I915_READ(reg);
8db9d77b
ZW		 3382 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3383
3384 if ((temp & FDI_RX_BIT_LOCK)) {
3385 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3386 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3387 break;
3388 }
8db9d77b 3389 }
e1a44743 3390 if (tries == 5)
5eddb70b 3391 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3392
3393 /* Train 2 */
5eddb70b
CW		 3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
8db9d77b
ZW		 3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3398 I915_WRITE(reg, temp);
8db9d77b 3399
5eddb70b
CW		 3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
8db9d77b
ZW		 3402 temp &= ~FDI_LINK_TRAIN_NONE;
3403 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3404 I915_WRITE(reg, temp);
8db9d77b 3405
5eddb70b
CW		 3406 POSTING_READ(reg);
3407 udelay(150);
8db9d77b 3408
5eddb70b 3409 reg = FDI_RX_IIR(pipe);
e1a44743 3410 for (tries = 0; tries < 5; tries++) {
5eddb70b 3411 temp = I915_READ(reg);
8db9d77b
ZW		 3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413
3414 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3415 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3416 DRM_DEBUG_KMS("FDI train 2 done.\n");
3417 break;
3418 }
8db9d77b 3419 }
e1a44743 3420 if (tries == 5)
5eddb70b 3421 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3422
3423 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3424
8db9d77b
ZW		 3425}
3426
0206e353 3427static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3428 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3429 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3430 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3431 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3432};
3433
3434/* The FDI link training functions for SNB/Cougarpoint. */
3435static void gen6_fdi_link_train(struct drm_crtc *crtc)
3436{
3437 struct drm_device *dev = crtc->dev;
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3440 int pipe = intel_crtc->pipe;
fa37d39e 3441 u32 reg, temp, i, retry;
8db9d77b 3442
e1a44743
AJ		 3443 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3444 for train result */
5eddb70b
CW		 3445 reg = FDI_RX_IMR(pipe);
3446 temp = I915_READ(reg);
e1a44743
AJ		 3447 temp &= ~FDI_RX_SYMBOL_LOCK;
3448 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3449 I915_WRITE(reg, temp);
3450
3451 POSTING_READ(reg);
e1a44743
AJ		 3452 udelay(150);
3453
8db9d77b 3454 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
627eb5a3 3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_1;
3461 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3462 /* SNB-B */
3463 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3464 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3465
d74cf324
DV		 3466 I915_WRITE(FDI_RX_MISC(pipe),
3467 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3468
5eddb70b
CW		 3469 reg = FDI_RX_CTL(pipe);
3470 temp = I915_READ(reg);
8db9d77b
ZW		 3471 if (HAS_PCH_CPT(dev)) {
3472 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3473 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3474 } else {
3475 temp &= ~FDI_LINK_TRAIN_NONE;
3476 temp |= FDI_LINK_TRAIN_PATTERN_1;
3477 }
5eddb70b
CW		 3478 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3479
3480 POSTING_READ(reg);
8db9d77b
ZW		 3481 udelay(150);
3482
0206e353 3483 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3484 reg = FDI_TX_CTL(pipe);
3485 temp = I915_READ(reg);
8db9d77b
ZW		 3486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
8db9d77b
ZW		 3491 udelay(500);
3492
fa37d39e
SP		 3493 for (retry = 0; retry < 5; retry++) {
3494 reg = FDI_RX_IIR(pipe);
3495 temp = I915_READ(reg);
3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497 if (temp & FDI_RX_BIT_LOCK) {
3498 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3499 DRM_DEBUG_KMS("FDI train 1 done.\n");
3500 break;
3501 }
3502 udelay(50);
8db9d77b 3503 }
fa37d39e
SP		 3504 if (retry < 5)
3505 break;
8db9d77b
ZW		 3506 }
3507 if (i == 4)
5eddb70b 3508 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3509
3510 /* Train 2 */
5eddb70b
CW		 3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
8db9d77b
ZW		 3513 temp &= ~FDI_LINK_TRAIN_NONE;
3514 temp |= FDI_LINK_TRAIN_PATTERN_2;
3515 if (IS_GEN6(dev)) {
3516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3517 /* SNB-B */
3518 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3519 }
5eddb70b 3520 I915_WRITE(reg, temp);
8db9d77b 3521
5eddb70b
CW		 3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
8db9d77b
ZW		 3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3527 } else {
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_2;
3530 }
5eddb70b
CW		 3531 I915_WRITE(reg, temp);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(150);
3535
0206e353 3536 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
8db9d77b
ZW		 3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3541 I915_WRITE(reg, temp);
3542
3543 POSTING_READ(reg);
8db9d77b
ZW		 3544 udelay(500);
3545
fa37d39e
SP		 3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_SYMBOL_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3552 DRM_DEBUG_KMS("FDI train 2 done.\n");
3553 break;
3554 }
3555 udelay(50);
8db9d77b 3556 }
fa37d39e
SP		 3557 if (retry < 5)
3558 break;
8db9d77b
ZW		 3559 }
3560 if (i == 4)
5eddb70b 3561 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3562
3563 DRM_DEBUG_KMS("FDI train done.\n");
3564}
3565
357555c0
JB		 3566/* Manual link training for Ivy Bridge A0 parts */
3567static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3568{
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
139ccd3f 3573 u32 reg, temp, i, j;
357555c0
JB		 3574
3575 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3576 for train result */
3577 reg = FDI_RX_IMR(pipe);
3578 temp = I915_READ(reg);
3579 temp &= ~FDI_RX_SYMBOL_LOCK;
3580 temp &= ~FDI_RX_BIT_LOCK;
3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
3584 udelay(150);
3585
01a415fd
DV		 3586 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3587 I915_READ(FDI_RX_IIR(pipe)));
3588
139ccd3f
JB		 3589 /* Try each vswing and preemphasis setting twice before moving on */
3590 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3591 /* disable first in case we need to retry */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3595 temp &= ~FDI_TX_ENABLE;
3596 I915_WRITE(reg, temp);
357555c0 3597
139ccd3f
JB		 3598 reg = FDI_RX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_AUTO;
3601 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3602 temp &= ~FDI_RX_ENABLE;
3603 I915_WRITE(reg, temp);
357555c0 3604
139ccd3f 3605 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3606 reg = FDI_TX_CTL(pipe);
3607 temp = I915_READ(reg);
139ccd3f 3608 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3609 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3610 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3612 temp |= snb_b_fdi_train_param[j/2];
3613 temp |= FDI_COMPOSITE_SYNC;
3614 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3615
139ccd3f
JB		 3616 I915_WRITE(FDI_RX_MISC(pipe),
3617 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3618
139ccd3f 3619 reg = FDI_RX_CTL(pipe);
357555c0 3620 temp = I915_READ(reg);
139ccd3f
JB		 3621 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3622 temp |= FDI_COMPOSITE_SYNC;
3623 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3624
139ccd3f
JB		 3625 POSTING_READ(reg);
3626 udelay(1); /* should be 0.5us */
357555c0 3627
139ccd3f
JB		 3628 for (i = 0; i < 4; i++) {
3629 reg = FDI_RX_IIR(pipe);
3630 temp = I915_READ(reg);
3631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3632
139ccd3f
JB		 3633 if (temp & FDI_RX_BIT_LOCK ||
3634 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3635 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3636 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3637 i);
3638 break;
3639 }
3640 udelay(1); /* should be 0.5us */
3641 }
3642 if (i == 4) {
3643 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3644 continue;
3645 }
357555c0 3646
139ccd3f 3647 /* Train 2 */
357555c0
JB		 3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
139ccd3f
JB		 3650 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3651 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3652 I915_WRITE(reg, temp);
3653
3654 reg = FDI_RX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3657 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3658 I915_WRITE(reg, temp);
3659
3660 POSTING_READ(reg);
139ccd3f 3661 udelay(2); /* should be 1.5us */
357555c0 3662
139ccd3f
JB		 3663 for (i = 0; i < 4; i++) {
3664 reg = FDI_RX_IIR(pipe);
3665 temp = I915_READ(reg);
3666 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3667
139ccd3f
JB		 3668 if (temp & FDI_RX_SYMBOL_LOCK ||
3669 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3670 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3671 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3672 i);
3673 goto train_done;
3674 }
3675 udelay(2); /* should be 1.5us */
357555c0 3676 }
139ccd3f
JB		 3677 if (i == 4)
3678 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3679 }
357555c0 3680
139ccd3f 3681train_done:
357555c0
JB		 3682 DRM_DEBUG_KMS("FDI train done.\n");
3683}
3684
88cefb6c 3685static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3686{
88cefb6c 3687 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3688 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3689 int pipe = intel_crtc->pipe;
5eddb70b 3690 u32 reg, temp;
79e53945 3691
c64e311e 3692
c98e9dcf 3693 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
627eb5a3 3696 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3698 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3699 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3700
3701 POSTING_READ(reg);
c98e9dcf
JB		 3702 udelay(200);
3703
3704 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3705 temp = I915_READ(reg);
3706 I915_WRITE(reg, temp | FDI_PCDCLK);
3707
3708 POSTING_READ(reg);
c98e9dcf
JB		 3709 udelay(200);
3710
20749730
PZ		 3711 /* Enable CPU FDI TX PLL, always on for Ironlake */
3712 reg = FDI_TX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3715 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3716
20749730
PZ		 3717 POSTING_READ(reg);
3718 udelay(100);
6be4a607 3719 }
0e23b99d
JB		 3720}
3721
88cefb6c
DV		 3722static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3723{
3724 struct drm_device *dev = intel_crtc->base.dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 int pipe = intel_crtc->pipe;
3727 u32 reg, temp;
3728
3729 /* Switch from PCDclk to Rawclk */
3730 reg = FDI_RX_CTL(pipe);
3731 temp = I915_READ(reg);
3732 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3733
3734 /* Disable CPU FDI TX PLL */
3735 reg = FDI_TX_CTL(pipe);
3736 temp = I915_READ(reg);
3737 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3738
3739 POSTING_READ(reg);
3740 udelay(100);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3745
3746 /* Wait for the clocks to turn off. */
3747 POSTING_READ(reg);
3748 udelay(100);
3749}
3750
0fc932b8
JB		 3751static void ironlake_fdi_disable(struct drm_crtc *crtc)
3752{
3753 struct drm_device *dev = crtc->dev;
3754 struct drm_i915_private *dev_priv = dev->dev_private;
3755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756 int pipe = intel_crtc->pipe;
3757 u32 reg, temp;
3758
3759 /* disable CPU FDI tx and PCH FDI rx */
3760 reg = FDI_TX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3763 POSTING_READ(reg);
3764
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(0x7 << 16);
dfd07d72 3768 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3770
3771 POSTING_READ(reg);
3772 udelay(100);
3773
3774 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3775 if (HAS_PCH_IBX(dev))
6f06ce18 3776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3777
3778 /* still set train pattern 1 */
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_LINK_TRAIN_NONE;
3782 temp |= FDI_LINK_TRAIN_PATTERN_1;
3783 I915_WRITE(reg, temp);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 if (HAS_PCH_CPT(dev)) {
3788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3789 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3790 } else {
3791 temp &= ~FDI_LINK_TRAIN_NONE;
3792 temp |= FDI_LINK_TRAIN_PATTERN_1;
3793 }
3794 /* BPC in FDI rx is consistent with that in PIPECONF */
3795 temp &= ~(0x07 << 16);
dfd07d72 3796 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3797 I915_WRITE(reg, temp);
3798
3799 POSTING_READ(reg);
3800 udelay(100);
3801}
3802
5dce5b93
CW		 3803bool intel_has_pending_fb_unpin(struct drm_device *dev)
3804{
3805 struct intel_crtc *crtc;
3806
3807 /* Note that we don't need to be called with mode_config.lock here
3808 * as our list of CRTC objects is static for the lifetime of the
3809 * device and so cannot disappear as we iterate. Similarly, we can
3810 * happily treat the predicates as racy, atomic checks as userspace
3811 * cannot claim and pin a new fb without at least acquring the
3812 * struct_mutex and so serialising with us.
3813 */
d3fcc808 3814 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3815 if (atomic_read(&crtc->unpin_work_count) == 0)
3816 continue;
3817
3818 if (crtc->unpin_work)
3819 intel_wait_for_vblank(dev, crtc->pipe);
3820
3821 return true;
3822 }
3823
3824 return false;
3825}
3826
d6bbafa1
CW		 3827static void page_flip_completed(struct intel_crtc *intel_crtc)
3828{
3829 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3830 struct intel_unpin_work *work = intel_crtc->unpin_work;
3831
3832 /* ensure that the unpin work is consistent wrt ->pending. */
3833 smp_rmb();
3834 intel_crtc->unpin_work = NULL;
3835
3836 if (work->event)
3837 drm_send_vblank_event(intel_crtc->base.dev,
3838 intel_crtc->pipe,
3839 work->event);
3840
3841 drm_crtc_vblank_put(&intel_crtc->base);
3842
3843 wake_up_all(&dev_priv->pending_flip_queue);
3844 queue_work(dev_priv->wq, &work->work);
3845
3846 trace_i915_flip_complete(intel_crtc->plane,
3847 work->pending_flip_obj);
3848}
3849
46a55d30 3850void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3851{
0f91128d 3852 struct drm_device *dev = crtc->dev;
5bb61643 3853 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3854
2c10d571 3855 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3856 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3857 !intel_crtc_has_pending_flip(crtc),
3858 60*HZ) == 0)) {
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3860
5e2d7afc 3861 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3862 if (intel_crtc->unpin_work) {
3863 WARN_ONCE(1, "Removing stuck page flip\n");
3864 page_flip_completed(intel_crtc);
3865 }
5e2d7afc 3866 spin_unlock_irq(&dev->event_lock);
9c787942 3867 }
5bb61643 3868
975d568a
CW		 3869 if (crtc->primary->fb) {
3870 mutex_lock(&dev->struct_mutex);
3871 intel_finish_fb(crtc->primary->fb);
3872 mutex_unlock(&dev->struct_mutex);
3873 }
e6c3a2a6
CW		 3874}
3875
e615efe4
ED		 3876/* Program iCLKIP clock to the desired frequency */
3877static void lpt_program_iclkip(struct drm_crtc *crtc)
3878{
3879 struct drm_device *dev = crtc->dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3881 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3882 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3883 u32 temp;
3884
09153000
DV		 3885 mutex_lock(&dev_priv->dpio_lock);
3886
e615efe4
ED		 3887 /* It is necessary to ungate the pixclk gate prior to programming
3888 * the divisors, and gate it back when it is done.
3889 */
3890 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3891
3892 /* Disable SSCCTL */
3893 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3894 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3895 SBI_SSCCTL_DISABLE,
3896 SBI_ICLK);
e615efe4
ED		 3897
3898 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3899 if (clock == 20000) {
e615efe4
ED		 3900 auxdiv = 1;
3901 divsel = 0x41;
3902 phaseinc = 0x20;
3903 } else {
3904 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3905 * but the adjusted_mode->crtc_clock in in KHz. To get the
3906 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3907 * convert the virtual clock precision to KHz here for higher
3908 * precision.
3909 */
3910 u32 iclk_virtual_root_freq = 172800 * 1000;
3911 u32 iclk_pi_range = 64;
3912 u32 desired_divisor, msb_divisor_value, pi_value;
3913
12d7ceed 3914 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3915 msb_divisor_value = desired_divisor / iclk_pi_range;
3916 pi_value = desired_divisor % iclk_pi_range;
3917
3918 auxdiv = 0;
3919 divsel = msb_divisor_value - 2;
3920 phaseinc = pi_value;
3921 }
3922
3923 /* This should not happen with any sane values */
3924 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3925 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3926 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3927 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3928
3929 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3930 clock,
e615efe4
ED		 3931 auxdiv,
3932 divsel,
3933 phasedir,
3934 phaseinc);
3935
3936 /* Program SSCDIVINTPHASE6 */
988d6ee8 3937 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3938 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3939 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3940 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3941 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3942 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3943 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3944 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3945
3946 /* Program SSCAUXDIV */
988d6ee8 3947 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3948 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3949 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3950 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3951
3952 /* Enable modulator and associated divider */
988d6ee8 3953 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3954 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3955 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3956
3957 /* Wait for initialization time */
3958 udelay(24);
3959
3960 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3961
3962 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3963}
3964
275f01b2
DV		 3965static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3966 enum pipe pch_transcoder)
3967{
3968 struct drm_device *dev = crtc->base.dev;
3969 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3970 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3971
3972 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3973 I915_READ(HTOTAL(cpu_transcoder)));
3974 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3975 I915_READ(HBLANK(cpu_transcoder)));
3976 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3977 I915_READ(HSYNC(cpu_transcoder)));
3978
3979 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3980 I915_READ(VTOTAL(cpu_transcoder)));
3981 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3982 I915_READ(VBLANK(cpu_transcoder)));
3983 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3984 I915_READ(VSYNC(cpu_transcoder)));
3985 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3986 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3987}
3988
003632d9 3989static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3990{
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 uint32_t temp;
3993
3994 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3995 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3996 return;
3997
3998 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3999 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4000
003632d9
ACO		 4001 temp &= ~FDI_BC_BIFURCATION_SELECT;
4002 if (enable)
4003 temp |= FDI_BC_BIFURCATION_SELECT;
4004
4005 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4006 I915_WRITE(SOUTH_CHICKEN1, temp);
4007 POSTING_READ(SOUTH_CHICKEN1);
4008}
4009
4010static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4011{
4012 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4013
4014 switch (intel_crtc->pipe) {
4015 case PIPE_A:
4016 break;
4017 case PIPE_B:
6e3c9717 4018 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4019 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4020 else
003632d9 4021 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4022
4023 break;
4024 case PIPE_C:
003632d9 4025 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4026
4027 break;
4028 default:
4029 BUG();
4030 }
4031}
4032
f67a559d
JB		 4033/*
4034 * Enable PCH resources required for PCH ports:
4035 * - PCH PLLs
4036 * - FDI training & RX/TX
4037 * - update transcoder timings
4038 * - DP transcoding bits
4039 * - transcoder
4040 */
4041static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 int pipe = intel_crtc->pipe;
ee7b9f93 4047 u32 reg, temp;
2c07245f 4048
ab9412ba 4049 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4050
1fbc0d78
DV		 4051 if (IS_IVYBRIDGE(dev))
4052 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4053
cd986abb
DV		 4054 /* Write the TU size bits before fdi link training, so that error
4055 * detection works. */
4056 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4057 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4058
c98e9dcf 4059 /* For PCH output, training FDI link */
674cf967 4060 dev_priv->display.fdi_link_train(crtc);
2c07245f 4061
3ad8a208
DV		 4062 /* We need to program the right clock selection before writing the pixel
4063 * mutliplier into the DPLL. */
303b81e0 4064 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4065 u32 sel;
4b645f14 4066
c98e9dcf 4067 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4068 temp |= TRANS_DPLL_ENABLE(pipe);
4069 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4070 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4071 temp |= sel;
4072 else
4073 temp &= ~sel;
c98e9dcf 4074 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4075 }
5eddb70b 4076
3ad8a208
DV		 4077 /* XXX: pch pll's can be enabled any time before we enable the PCH
4078 * transcoder, and we actually should do this to not upset any PCH
4079 * transcoder that already use the clock when we share it.
4080 *
4081 * Note that enable_shared_dpll tries to do the right thing, but
4082 * get_shared_dpll unconditionally resets the pll - we need that to have
4083 * the right LVDS enable sequence. */
85b3894f 4084 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4085
d9b6cb56
JB		 4086 /* set transcoder timing, panel must allow it */
4087 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4088 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4089
303b81e0 4090 intel_fdi_normal_train(crtc);
5e84e1a4 4091
c98e9dcf 4092 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4093 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4094 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4095 reg = TRANS_DP_CTL(pipe);
4096 temp = I915_READ(reg);
4097 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4098 TRANS_DP_SYNC_MASK |
4099 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4100 temp |= (TRANS_DP_OUTPUT_ENABLE |
4101 TRANS_DP_ENH_FRAMING);
9325c9f0 4102 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4103
4104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4105 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4106 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4107 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4108
4109 switch (intel_trans_dp_port_sel(crtc)) {
4110 case PCH_DP_B:
5eddb70b 4111 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4112 break;
4113 case PCH_DP_C:
5eddb70b 4114 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4115 break;
4116 case PCH_DP_D:
5eddb70b 4117 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4118 break;
4119 default:
e95d41e1 4120 BUG();
32f9d658 4121 }
2c07245f 4122
5eddb70b 4123 I915_WRITE(reg, temp);
6be4a607 4124 }
b52eb4dc 4125
b8a4f404 4126 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4127}
4128
1507e5bd
PZ		 4129static void lpt_pch_enable(struct drm_crtc *crtc)
4130{
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4135
ab9412ba 4136 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4137
8c52b5e8 4138 lpt_program_iclkip(crtc);
1507e5bd 4139
0540e488 4140 /* Set transcoder timing. */
275f01b2 4141 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4142
937bb610 4143 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4144}
4145
716c2e55 4146void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4147{
e2b78267 4148 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4149
4150 if (pll == NULL)
4151 return;
4152
3e369b76 4153 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4154 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4155 return;
4156 }
4157
3e369b76
ACO		 4158 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4159 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4160 WARN_ON(pll->on);
4161 WARN_ON(pll->active);
4162 }
4163
6e3c9717 4164 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4165}
4166
190f68c5
ACO		 4167struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4168 struct intel_crtc_state *crtc_state)
ee7b9f93 4169{
e2b78267 4170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4171 struct intel_shared_dpll *pll;
e2b78267 4172 enum intel_dpll_id i;
ee7b9f93 4173
98b6bd99
DV		 4174 if (HAS_PCH_IBX(dev_priv->dev)) {
4175 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4176 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4177 pll = &dev_priv->shared_dplls[i];
98b6bd99 4178
46edb027
DV		 4179 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4180 crtc->base.base.id, pll->name);
98b6bd99 4181
8bd31e67 4182 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4183
98b6bd99
DV		 4184 goto found;
4185 }
4186
e72f9fbf
DV		 4187 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4188 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4189
4190 /* Only want to check enabled timings first */
8bd31e67 4191 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4192 continue;
4193
190f68c5 4194 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4195 &pll->new_config->hw_state,
4196 sizeof(pll->new_config->hw_state)) == 0) {
4197 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4198 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4199 pll->new_config->crtc_mask,
4200 pll->active);
ee7b9f93
JB		 4201 goto found;
4202 }
4203 }
4204
4205 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4206 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4207 pll = &dev_priv->shared_dplls[i];
8bd31e67 4208 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4209 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4210 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4211 goto found;
4212 }
4213 }
4214
4215 return NULL;
4216
4217found:
8bd31e67 4218 if (pll->new_config->crtc_mask == 0)
190f68c5 4219 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4220
190f68c5 4221 crtc_state->shared_dpll = i;
46edb027
DV		 4222 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4223 pipe_name(crtc->pipe));
ee7b9f93 4224
8bd31e67 4225 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4226
ee7b9f93
JB		 4227 return pll;
4228}
4229
8bd31e67
ACO		 4230/**
4231 * intel_shared_dpll_start_config - start a new PLL staged config
4232 * @dev_priv: DRM device
4233 * @clear_pipes: mask of pipes that will have their PLLs freed
4234 *
4235 * Starts a new PLL staged config, copying the current config but
4236 * releasing the references of pipes specified in clear_pipes.
4237 */
4238static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4239 unsigned clear_pipes)
4240{
4241 struct intel_shared_dpll *pll;
4242 enum intel_dpll_id i;
4243
4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
4246
4247 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4248 GFP_KERNEL);
4249 if (!pll->new_config)
4250 goto cleanup;
4251
4252 pll->new_config->crtc_mask &= ~clear_pipes;
4253 }
4254
4255 return 0;
4256
4257cleanup:
4258 while (--i >= 0) {
4259 pll = &dev_priv->shared_dplls[i];
f354d733 4260 kfree(pll->new_config);
8bd31e67
ACO		 4261 pll->new_config = NULL;
4262 }
4263
4264 return -ENOMEM;
4265}
4266
4267static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4268{
4269 struct intel_shared_dpll *pll;
4270 enum intel_dpll_id i;
4271
4272 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4273 pll = &dev_priv->shared_dplls[i];
4274
4275 WARN_ON(pll->new_config == &pll->config);
4276
4277 pll->config = *pll->new_config;
4278 kfree(pll->new_config);
4279 pll->new_config = NULL;
4280 }
4281}
4282
4283static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4284{
4285 struct intel_shared_dpll *pll;
4286 enum intel_dpll_id i;
4287
4288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4289 pll = &dev_priv->shared_dplls[i];
4290
4291 WARN_ON(pll->new_config == &pll->config);
4292
4293 kfree(pll->new_config);
4294 pll->new_config = NULL;
4295 }
4296}
4297
a1520318 4298static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4299{
4300 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4301 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4302 u32 temp;
4303
4304 temp = I915_READ(dslreg);
4305 udelay(500);
4306 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4307 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4308 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4309 }
4310}
4311
a1b2278e
CK		 4312/**
4313 * skl_update_scaler_users - Stages update to crtc's scaler state
4314 * @intel_crtc: crtc
4315 * @crtc_state: crtc_state
4316 * @plane: plane (NULL indicates crtc is requesting update)
4317 * @plane_state: plane's state
4318 * @force_detach: request unconditional detachment of scaler
4319 *
4320 * This function updates scaler state for requested plane or crtc.
4321 * To request scaler usage update for a plane, caller shall pass plane pointer.
4322 * To request scaler usage update for crtc, caller shall pass plane pointer
4323 * as NULL.
4324 *
4325 * Return
4326 * 0 - scaler_usage updated successfully
4327 * error - requested scaling cannot be supported or other error condition
4328 */
4329int
4330skl_update_scaler_users(
4331 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4332 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4333 int force_detach)
4334{
4335 int need_scaling;
4336 int idx;
4337 int src_w, src_h, dst_w, dst_h;
4338 int *scaler_id;
4339 struct drm_framebuffer *fb;
4340 struct intel_crtc_scaler_state *scaler_state;
4341
4342 if (!intel_crtc || !crtc_state)
4343 return 0;
4344
4345 scaler_state = &crtc_state->scaler_state;
4346
4347 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4348 fb = intel_plane ? plane_state->base.fb : NULL;
4349
4350 if (intel_plane) {
4351 src_w = drm_rect_width(&plane_state->src) >> 16;
4352 src_h = drm_rect_height(&plane_state->src) >> 16;
4353 dst_w = drm_rect_width(&plane_state->dst);
4354 dst_h = drm_rect_height(&plane_state->dst);
4355 scaler_id = &plane_state->scaler_id;
4356 } else {
4357 struct drm_display_mode *adjusted_mode =
4358 &crtc_state->base.adjusted_mode;
4359 src_w = crtc_state->pipe_src_w;
4360 src_h = crtc_state->pipe_src_h;
4361 dst_w = adjusted_mode->hdisplay;
4362 dst_h = adjusted_mode->vdisplay;
4363 scaler_id = &scaler_state->scaler_id;
4364 }
4365 need_scaling = (src_w != dst_w || src_h != dst_h);
4366
4367 /*
4368 * if plane is being disabled or scaler is no more required or force detach
4369 * - free scaler binded to this plane/crtc
4370 * - in order to do this, update crtc->scaler_usage
4371 *
4372 * Here scaler state in crtc_state is set free so that
4373 * scaler can be assigned to other user. Actual register
4374 * update to free the scaler is done in plane/panel-fit programming.
4375 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4376 */
4377 if (force_detach || !need_scaling || (intel_plane &&
4378 (!fb || !plane_state->visible))) {
4379 if (*scaler_id >= 0) {
4380 scaler_state->scaler_users &= ~(1 << idx);
4381 scaler_state->scalers[*scaler_id].in_use = 0;
4382
4383 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4384 "crtc_state = %p scaler_users = 0x%x\n",
4385 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4386 intel_plane ? intel_plane->base.base.id :
4387 intel_crtc->base.base.id, crtc_state,
4388 scaler_state->scaler_users);
4389 *scaler_id = -1;
4390 }
4391 return 0;
4392 }
4393
4394 /* range checks */
4395 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4396 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4397
4398 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4399 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4400 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4401 "size is out of scaler range\n",
4402 intel_plane ? "PLANE" : "CRTC",
4403 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4404 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4405 return -EINVAL;
4406 }
4407
4408 /* check colorkey */
4409 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4410 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4411 intel_plane->base.base.id);
4412 return -EINVAL;
4413 }
4414
4415 /* Check src format */
4416 if (intel_plane) {
4417 switch (fb->pixel_format) {
4418 case DRM_FORMAT_RGB565:
4419 case DRM_FORMAT_XBGR8888:
4420 case DRM_FORMAT_XRGB8888:
4421 case DRM_FORMAT_ABGR8888:
4422 case DRM_FORMAT_ARGB8888:
4423 case DRM_FORMAT_XRGB2101010:
4424 case DRM_FORMAT_ARGB2101010:
4425 case DRM_FORMAT_XBGR2101010:
4426 case DRM_FORMAT_ABGR2101010:
4427 case DRM_FORMAT_YUYV:
4428 case DRM_FORMAT_YVYU:
4429 case DRM_FORMAT_UYVY:
4430 case DRM_FORMAT_VYUY:
4431 break;
4432 default:
4433 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4434 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4435 return -EINVAL;
4436 }
4437 }
4438
4439 /* mark this plane as a scaler user in crtc_state */
4440 scaler_state->scaler_users |= (1 << idx);
4441 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4442 "crtc_state = %p scaler_users = 0x%x\n",
4443 intel_plane ? "PLANE" : "CRTC",
4444 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4445 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4446 return 0;
4447}
4448
4449static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4450{
4451 struct drm_device *dev = crtc->base.dev;
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 int pipe = crtc->pipe;
a1b2278e
CK		 4454 struct intel_crtc_scaler_state *scaler_state =
4455 &crtc->config->scaler_state;
4456
4457 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4458
4459 /* To update pfit, first update scaler state */
4460 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4461 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4462 skl_detach_scalers(crtc);
4463 if (!enable)
4464 return;
bd2e244f 4465
6e3c9717 4466 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4467 int id;
4468
4469 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4470 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4471 return;
4472 }
4473
4474 id = scaler_state->scaler_id;
4475 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4476 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4477 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4478 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4479
4480 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4481 }
4482}
4483
b074cec8
JB		 4484static void ironlake_pfit_enable(struct intel_crtc *crtc)
4485{
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 int pipe = crtc->pipe;
4489
6e3c9717 4490 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4491 /* Force use of hard-coded filter coefficients
4492 * as some pre-programmed values are broken,
4493 * e.g. x201.
4494 */
4495 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4496 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4497 PF_PIPE_SEL_IVB(pipe));
4498 else
4499 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4500 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4501 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4502 }
4503}
4504
4a3b8769 4505static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4506{
4507 struct drm_device *dev = crtc->dev;
4508 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4509 struct drm_plane *plane;
bb53d4ae
VS		 4510 struct intel_plane *intel_plane;
4511
af2b653b
MR		 4512 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4513 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4514 if (intel_plane->pipe == pipe)
4515 intel_plane_restore(&intel_plane->base);
af2b653b 4516 }
bb53d4ae
VS		 4517}
4518
0d703d4e
MR		 4519/*
4520 * Disable a plane internally without actually modifying the plane's state.
4521 * This will allow us to easily restore the plane later by just reprogramming
4522 * its state.
4523 */
4524static void disable_plane_internal(struct drm_plane *plane)
4525{
4526 struct intel_plane *intel_plane = to_intel_plane(plane);
4527 struct drm_plane_state *state =
4528 plane->funcs->atomic_duplicate_state(plane);
4529 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4530
4531 intel_state->visible = false;
4532 intel_plane->commit_plane(plane, intel_state);
4533
4534 intel_plane_destroy_state(plane, state);
4535}
4536
4a3b8769 4537static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4538{
4539 struct drm_device *dev = crtc->dev;
4540 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4541 struct drm_plane *plane;
bb53d4ae
VS		 4542 struct intel_plane *intel_plane;
4543
af2b653b
MR		 4544 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4545 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4546 if (plane->fb && intel_plane->pipe == pipe)
4547 disable_plane_internal(plane);
af2b653b 4548 }
bb53d4ae
VS		 4549}
4550
20bc8673 4551void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4552{
cea165c3
VS		 4553 struct drm_device *dev = crtc->base.dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4555
6e3c9717 4556 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4557 return;
4558
cea165c3
VS		 4559 /* We can only enable IPS after we enable a plane and wait for a vblank */
4560 intel_wait_for_vblank(dev, crtc->pipe);
4561
d77e4531 4562 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4563 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4564 mutex_lock(&dev_priv->rps.hw_lock);
4565 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4566 mutex_unlock(&dev_priv->rps.hw_lock);
4567 /* Quoting Art Runyan: "its not safe to expect any particular
4568 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4569 * mailbox." Moreover, the mailbox may return a bogus state,
4570 * so we need to just enable it and continue on.
2a114cc1
BW		 4571 */
4572 } else {
4573 I915_WRITE(IPS_CTL, IPS_ENABLE);
4574 /* The bit only becomes 1 in the next vblank, so this wait here
4575 * is essentially intel_wait_for_vblank. If we don't have this
4576 * and don't wait for vblanks until the end of crtc_enable, then
4577 * the HW state readout code will complain that the expected
4578 * IPS_CTL value is not the one we read. */
4579 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4580 DRM_ERROR("Timed out waiting for IPS enable\n");
4581 }
d77e4531
PZ		 4582}
4583
20bc8673 4584void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4585{
4586 struct drm_device *dev = crtc->base.dev;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588
6e3c9717 4589 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4590 return;
4591
4592 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4593 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4594 mutex_lock(&dev_priv->rps.hw_lock);
4595 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4596 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4597 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4598 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4599 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4600 } else {
2a114cc1 4601 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4602 POSTING_READ(IPS_CTL);
4603 }
d77e4531
PZ		 4604
4605 /* We need to wait for a vblank before we can disable the plane. */
4606 intel_wait_for_vblank(dev, crtc->pipe);
4607}
4608
4609/** Loads the palette/gamma unit for the CRTC with the prepared values */
4610static void intel_crtc_load_lut(struct drm_crtc *crtc)
4611{
4612 struct drm_device *dev = crtc->dev;
4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4615 enum pipe pipe = intel_crtc->pipe;
4616 int palreg = PALETTE(pipe);
4617 int i;
4618 bool reenable_ips = false;
4619
4620 /* The clocks have to be on to load the palette. */
83d65738 4621 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4622 return;
4623
4624 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4625 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4626 assert_dsi_pll_enabled(dev_priv);
4627 else
4628 assert_pll_enabled(dev_priv, pipe);
4629 }
4630
4631 /* use legacy palette for Ironlake */
7a1db49a 4632 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4633 palreg = LGC_PALETTE(pipe);
4634
4635 /* Workaround : Do not read or write the pipe palette/gamma data while
4636 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4637 */
6e3c9717 4638 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4639 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4640 GAMMA_MODE_MODE_SPLIT)) {
4641 hsw_disable_ips(intel_crtc);
4642 reenable_ips = true;
4643 }
4644
4645 for (i = 0; i < 256; i++) {
4646 I915_WRITE(palreg + 4 * i,
4647 (intel_crtc->lut_r[i] << 16) |
4648 (intel_crtc->lut_g[i] << 8) |
4649 intel_crtc->lut_b[i]);
4650 }
4651
4652 if (reenable_ips)
4653 hsw_enable_ips(intel_crtc);
4654}
4655
d3eedb1a
VS		 4656static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4657{
4658 if (!enable && intel_crtc->overlay) {
4659 struct drm_device *dev = intel_crtc->base.dev;
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661
4662 mutex_lock(&dev->struct_mutex);
4663 dev_priv->mm.interruptible = false;
4664 (void) intel_overlay_switch_off(intel_crtc->overlay);
4665 dev_priv->mm.interruptible = true;
4666 mutex_unlock(&dev->struct_mutex);
4667 }
4668
4669 /* Let userspace switch the overlay on again. In most cases userspace
4670 * has to recompute where to put it anyway.
4671 */
4672}
4673
d3eedb1a 4674static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4675{
4676 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 int pipe = intel_crtc->pipe;
a5c4d7bc 4679
fdd508a6 4680 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4681 intel_enable_sprite_planes(crtc);
a5c4d7bc 4682 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4683 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4684
4685 hsw_enable_ips(intel_crtc);
4686
4687 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4688 intel_fbc_update(dev);
a5c4d7bc 4689 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4690
4691 /*
4692 * FIXME: Once we grow proper nuclear flip support out of this we need
4693 * to compute the mask of flip planes precisely. For the time being
4694 * consider this a flip from a NULL plane.
4695 */
4696 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4697}
4698
d3eedb1a 4699static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4700{
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4705
4706 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4707
e35fef21 4708 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4709 intel_fbc_disable(dev);
a5c4d7bc
VS		 4710
4711 hsw_disable_ips(intel_crtc);
4712
d3eedb1a 4713 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4714 intel_crtc_update_cursor(crtc, false);
4a3b8769 4715 intel_disable_sprite_planes(crtc);
fdd508a6 4716 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4717
f99d7069
DV		 4718 /*
4719 * FIXME: Once we grow proper nuclear flip support out of this we need
4720 * to compute the mask of flip planes precisely. For the time being
4721 * consider this a flip to a NULL plane.
4722 */
4723 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4724}
4725
f67a559d
JB		 4726static void ironlake_crtc_enable(struct drm_crtc *crtc)
4727{
4728 struct drm_device *dev = crtc->dev;
4729 struct drm_i915_private *dev_priv = dev->dev_private;
4730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4731 struct intel_encoder *encoder;
f67a559d 4732 int pipe = intel_crtc->pipe;
f67a559d 4733
83d65738 4734 WARN_ON(!crtc->state->enable);
08a48469 4735
f67a559d
JB		 4736 if (intel_crtc->active)
4737 return;
4738
6e3c9717 4739 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4740 intel_prepare_shared_dpll(intel_crtc);
4741
6e3c9717 4742 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4743 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4744
4745 intel_set_pipe_timings(intel_crtc);
4746
6e3c9717 4747 if (intel_crtc->config->has_pch_encoder) {
29407aab 4748 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4749 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4750 }
4751
4752 ironlake_set_pipeconf(crtc);
4753
f67a559d 4754 intel_crtc->active = true;
8664281b 4755
a72e4c9f
DV		 4756 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4758
f6736a1a 4759 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4760 if (encoder->pre_enable)
4761 encoder->pre_enable(encoder);
f67a559d 4762
6e3c9717 4763 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4764 /* Note: FDI PLL enabling _must_ be done before we enable the
4765 * cpu pipes, hence this is separate from all the other fdi/pch
4766 * enabling. */
88cefb6c 4767 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4768 } else {
4769 assert_fdi_tx_disabled(dev_priv, pipe);
4770 assert_fdi_rx_disabled(dev_priv, pipe);
4771 }
f67a559d 4772
b074cec8 4773 ironlake_pfit_enable(intel_crtc);
f67a559d 4774
9c54c0dd
JB		 4775 /*
4776 * On ILK+ LUT must be loaded before the pipe is running but with
4777 * clocks enabled
4778 */
4779 intel_crtc_load_lut(crtc);
4780
f37fcc2a 4781 intel_update_watermarks(crtc);
e1fdc473 4782 intel_enable_pipe(intel_crtc);
f67a559d 4783
6e3c9717 4784 if (intel_crtc->config->has_pch_encoder)
f67a559d 4785 ironlake_pch_enable(crtc);
c98e9dcf 4786
f9b61ff6
DV		 4787 assert_vblank_disabled(crtc);
4788 drm_crtc_vblank_on(crtc);
4789
fa5c73b1
DV		 4790 for_each_encoder_on_crtc(dev, crtc, encoder)
4791 encoder->enable(encoder);
61b77ddd
DV		 4792
4793 if (HAS_PCH_CPT(dev))
a1520318 4794 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4795
d3eedb1a 4796 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4797}
4798
42db64ef
PZ		 4799/* IPS only exists on ULT machines and is tied to pipe A. */
4800static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4801{
f5adf94e 4802 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4803}
4804
e4916946
PZ		 4805/*
4806 * This implements the workaround described in the "notes" section of the mode
4807 * set sequence documentation. When going from no pipes or single pipe to
4808 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4809 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4810 */
4811static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->base.dev;
4814 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4815
4816 /* We want to get the other_active_crtc only if there's only 1 other
4817 * active crtc. */
d3fcc808 4818 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4819 if (!crtc_it->active || crtc_it == crtc)
4820 continue;
4821
4822 if (other_active_crtc)
4823 return;
4824
4825 other_active_crtc = crtc_it;
4826 }
4827 if (!other_active_crtc)
4828 return;
4829
4830 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4831 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4832}
4833
4f771f10
PZ		 4834static void haswell_crtc_enable(struct drm_crtc *crtc)
4835{
4836 struct drm_device *dev = crtc->dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839 struct intel_encoder *encoder;
4840 int pipe = intel_crtc->pipe;
4f771f10 4841
83d65738 4842 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4843
4844 if (intel_crtc->active)
4845 return;
4846
df8ad70c
DV		 4847 if (intel_crtc_to_shared_dpll(intel_crtc))
4848 intel_enable_shared_dpll(intel_crtc);
4849
6e3c9717 4850 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4851 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4852
4853 intel_set_pipe_timings(intel_crtc);
4854
6e3c9717
ACO		 4855 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4856 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4857 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4858 }
4859
6e3c9717 4860 if (intel_crtc->config->has_pch_encoder) {
229fca97 4861 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4862 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4863 }
4864
4865 haswell_set_pipeconf(crtc);
4866
4867 intel_set_pipe_csc(crtc);
4868
4f771f10 4869 intel_crtc->active = true;
8664281b 4870
a72e4c9f 4871 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
4875
6e3c9717 4876 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4877 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4878 true);
4fe9467d
ID		 4879 dev_priv->display.fdi_link_train(crtc);
4880 }
4881
1f544388 4882 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4883
bd2e244f 4884 if (IS_SKYLAKE(dev))
a1b2278e 4885 skylake_pfit_update(intel_crtc, 1);
bd2e244f
JB		 4886 else
4887 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4888
4889 /*
4890 * On ILK+ LUT must be loaded before the pipe is running but with
4891 * clocks enabled
4892 */
4893 intel_crtc_load_lut(crtc);
4894
1f544388 4895 intel_ddi_set_pipe_settings(crtc);
8228c251 4896 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4897
f37fcc2a 4898 intel_update_watermarks(crtc);
e1fdc473 4899 intel_enable_pipe(intel_crtc);
42db64ef 4900
6e3c9717 4901 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4902 lpt_pch_enable(crtc);
4f771f10 4903
6e3c9717 4904 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4905 intel_ddi_set_vc_payload_alloc(crtc, true);
4906
f9b61ff6
DV		 4907 assert_vblank_disabled(crtc);
4908 drm_crtc_vblank_on(crtc);
4909
8807e55b 4910 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4911 encoder->enable(encoder);
8807e55b
JN		 4912 intel_opregion_notify_encoder(encoder, true);
4913 }
4f771f10 4914
e4916946
PZ		 4915 /* If we change the relative order between pipe/planes enabling, we need
4916 * to change the workaround. */
4917 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4918 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4919}
4920
3f8dce3a
DV		 4921static void ironlake_pfit_disable(struct intel_crtc *crtc)
4922{
4923 struct drm_device *dev = crtc->base.dev;
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 int pipe = crtc->pipe;
4926
4927 /* To avoid upsetting the power well on haswell only disable the pfit if
4928 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4929 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4930 I915_WRITE(PF_CTL(pipe), 0);
4931 I915_WRITE(PF_WIN_POS(pipe), 0);
4932 I915_WRITE(PF_WIN_SZ(pipe), 0);
4933 }
4934}
4935
6be4a607
JB		 4936static void ironlake_crtc_disable(struct drm_crtc *crtc)
4937{
4938 struct drm_device *dev = crtc->dev;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4941 struct intel_encoder *encoder;
6be4a607 4942 int pipe = intel_crtc->pipe;
5eddb70b 4943 u32 reg, temp;
b52eb4dc 4944
f7abfe8b
CW		 4945 if (!intel_crtc->active)
4946 return;
4947
d3eedb1a 4948 intel_crtc_disable_planes(crtc);
a5c4d7bc 4949
ea9d758d
DV		 4950 for_each_encoder_on_crtc(dev, crtc, encoder)
4951 encoder->disable(encoder);
4952
f9b61ff6
DV		 4953 drm_crtc_vblank_off(crtc);
4954 assert_vblank_disabled(crtc);
4955
6e3c9717 4956 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4957 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4958
575f7ab7 4959 intel_disable_pipe(intel_crtc);
32f9d658 4960
3f8dce3a 4961 ironlake_pfit_disable(intel_crtc);
2c07245f 4962
bf49ec8c
DV		 4963 for_each_encoder_on_crtc(dev, crtc, encoder)
4964 if (encoder->post_disable)
4965 encoder->post_disable(encoder);
2c07245f 4966
6e3c9717 4967 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4968 ironlake_fdi_disable(crtc);
913d8d11 4969
d925c59a 4970 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4971
d925c59a
DV		 4972 if (HAS_PCH_CPT(dev)) {
4973 /* disable TRANS_DP_CTL */
4974 reg = TRANS_DP_CTL(pipe);
4975 temp = I915_READ(reg);
4976 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4977 TRANS_DP_PORT_SEL_MASK);
4978 temp |= TRANS_DP_PORT_SEL_NONE;
4979 I915_WRITE(reg, temp);
4980
4981 /* disable DPLL_SEL */
4982 temp = I915_READ(PCH_DPLL_SEL);
11887397 4983 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4984 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4985 }
e3421a18 4986
d925c59a 4987 /* disable PCH DPLL */
e72f9fbf 4988 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4989
d925c59a
DV		 4990 ironlake_fdi_pll_disable(intel_crtc);
4991 }
6b383a7f 4992
f7abfe8b 4993 intel_crtc->active = false;
46ba614c 4994 intel_update_watermarks(crtc);
d1ebd816
BW		 4995
4996 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4997 intel_fbc_update(dev);
d1ebd816 4998 mutex_unlock(&dev->struct_mutex);
6be4a607 4999}
1b3c7a47 5000
4f771f10 5001static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5002{
4f771f10
PZ		 5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5006 struct intel_encoder *encoder;
6e3c9717 5007 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5008
4f771f10
PZ		 5009 if (!intel_crtc->active)
5010 return;
5011
d3eedb1a 5012 intel_crtc_disable_planes(crtc);
dda9a66a 5013
8807e55b
JN		 5014 for_each_encoder_on_crtc(dev, crtc, encoder) {
5015 intel_opregion_notify_encoder(encoder, false);
4f771f10 5016 encoder->disable(encoder);
8807e55b 5017 }
4f771f10 5018
f9b61ff6
DV		 5019 drm_crtc_vblank_off(crtc);
5020 assert_vblank_disabled(crtc);
5021
6e3c9717 5022 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5023 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5024 false);
575f7ab7 5025 intel_disable_pipe(intel_crtc);
4f771f10 5026
6e3c9717 5027 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5028 intel_ddi_set_vc_payload_alloc(crtc, false);
5029
ad80a810 5030 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5031
bd2e244f 5032 if (IS_SKYLAKE(dev))
a1b2278e 5033 skylake_pfit_update(intel_crtc, 0);
bd2e244f
JB		 5034 else
5035 ironlake_pfit_disable(intel_crtc);
4f771f10 5036
1f544388 5037 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5038
6e3c9717 5039 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5040 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5041 intel_ddi_fdi_disable(crtc);
83616634 5042 }
4f771f10 5043
97b040aa
ID		 5044 for_each_encoder_on_crtc(dev, crtc, encoder)
5045 if (encoder->post_disable)
5046 encoder->post_disable(encoder);
5047
4f771f10 5048 intel_crtc->active = false;
46ba614c 5049 intel_update_watermarks(crtc);
4f771f10
PZ		 5050
5051 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5052 intel_fbc_update(dev);
4f771f10 5053 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5054
5055 if (intel_crtc_to_shared_dpll(intel_crtc))
5056 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5057}
5058
ee7b9f93
JB		 5059static void ironlake_crtc_off(struct drm_crtc *crtc)
5060{
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5062 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5063}
5064
6441ab5f 5065
2dd24552
JB		 5066static void i9xx_pfit_enable(struct intel_crtc *crtc)
5067{
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5070 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5071
681a8504 5072 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5073 return;
5074
2dd24552 5075 /*
c0b03411
DV		 5076 * The panel fitter should only be adjusted whilst the pipe is disabled,
5077 * according to register description and PRM.
2dd24552 5078 */
c0b03411
DV		 5079 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5080 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5081
b074cec8
JB		 5082 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5083 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5084
5085 /* Border color in case we don't scale up to the full screen. Black by
5086 * default, change to something else for debugging. */
5087 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5088}
5089
d05410f9
DA		 5090static enum intel_display_power_domain port_to_power_domain(enum port port)
5091{
5092 switch (port) {
5093 case PORT_A:
5094 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5095 case PORT_B:
5096 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5097 case PORT_C:
5098 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5099 case PORT_D:
5100 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5101 default:
5102 WARN_ON_ONCE(1);
5103 return POWER_DOMAIN_PORT_OTHER;
5104 }
5105}
5106
77d22dca
ID		 5107#define for_each_power_domain(domain, mask) \
5108 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5109 if ((1 << (domain)) & (mask))
5110
319be8ae
ID		 5111enum intel_display_power_domain
5112intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5113{
5114 struct drm_device *dev = intel_encoder->base.dev;
5115 struct intel_digital_port *intel_dig_port;
5116
5117 switch (intel_encoder->type) {
5118 case INTEL_OUTPUT_UNKNOWN:
5119 /* Only DDI platforms should ever use this output type */
5120 WARN_ON_ONCE(!HAS_DDI(dev));
5121 case INTEL_OUTPUT_DISPLAYPORT:
5122 case INTEL_OUTPUT_HDMI:
5123 case INTEL_OUTPUT_EDP:
5124 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5125 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5126 case INTEL_OUTPUT_DP_MST:
5127 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5128 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5129 case INTEL_OUTPUT_ANALOG:
5130 return POWER_DOMAIN_PORT_CRT;
5131 case INTEL_OUTPUT_DSI:
5132 return POWER_DOMAIN_PORT_DSI;
5133 default:
5134 return POWER_DOMAIN_PORT_OTHER;
5135 }
5136}
5137
5138static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5139{
319be8ae
ID		 5140 struct drm_device *dev = crtc->dev;
5141 struct intel_encoder *intel_encoder;
5142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5144 unsigned long mask;
5145 enum transcoder transcoder;
5146
5147 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5148
5149 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5150 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5151 if (intel_crtc->config->pch_pfit.enabled ||
5152 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5153 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5154
319be8ae
ID		 5155 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5156 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5157
77d22dca
ID		 5158 return mask;
5159}
5160
679dacd4 5161static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5162{
679dacd4 5163 struct drm_device *dev = state->dev;
77d22dca
ID		 5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5166 struct intel_crtc *crtc;
5167
5168 /*
5169 * First get all needed power domains, then put all unneeded, to avoid
5170 * any unnecessary toggling of the power wells.
5171 */
d3fcc808 5172 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5173 enum intel_display_power_domain domain;
5174
83d65738 5175 if (!crtc->base.state->enable)
77d22dca
ID		 5176 continue;
5177
319be8ae 5178 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5179
5180 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5181 intel_display_power_get(dev_priv, domain);
5182 }
5183
50f6e502 5184 if (dev_priv->display.modeset_global_resources)
679dacd4 5185 dev_priv->display.modeset_global_resources(state);
50f6e502 5186
d3fcc808 5187 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5188 enum intel_display_power_domain domain;
5189
5190 for_each_power_domain(domain, crtc->enabled_power_domains)
5191 intel_display_power_put(dev_priv, domain);
5192
5193 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5194 }
5195
5196 intel_display_set_init_power(dev_priv, false);
5197}
5198
dfcab17e 5199/* returns HPLL frequency in kHz */
f8bf63fd 5200static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5201{
586f49dc 5202 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5203
586f49dc
JB		 5204 /* Obtain SKU information */
5205 mutex_lock(&dev_priv->dpio_lock);
5206 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5207 CCK_FUSE_HPLL_FREQ_MASK;
5208 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5209
dfcab17e 5210 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5211}
5212
f8bf63fd
VS		 5213static void vlv_update_cdclk(struct drm_device *dev)
5214{
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216
164dfd28 5217 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5218 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5219 dev_priv->cdclk_freq);
f8bf63fd
VS		 5220
5221 /*
5222 * Program the gmbus_freq based on the cdclk frequency.
5223 * BSpec erroneously claims we should aim for 4MHz, but
5224 * in fact 1MHz is the correct frequency.
5225 */
164dfd28 5226 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5227}
5228
30a970c6
JB		 5229/* Adjust CDclk dividers to allow high res or save power if possible */
5230static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5231{
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 u32 val, cmd;
5234
164dfd28
VK		 5235 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5236 != dev_priv->cdclk_freq);
d60c4473 5237
dfcab17e 5238 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5239 cmd = 2;
dfcab17e 5240 else if (cdclk == 266667)
30a970c6
JB		 5241 cmd = 1;
5242 else
5243 cmd = 0;
5244
5245 mutex_lock(&dev_priv->rps.hw_lock);
5246 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5247 val &= ~DSPFREQGUAR_MASK;
5248 val |= (cmd << DSPFREQGUAR_SHIFT);
5249 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5250 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5251 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5252 50)) {
5253 DRM_ERROR("timed out waiting for CDclk change\n");
5254 }
5255 mutex_unlock(&dev_priv->rps.hw_lock);
5256
dfcab17e 5257 if (cdclk == 400000) {
6bcda4f0 5258 u32 divider;
30a970c6 5259
6bcda4f0 5260 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5261
5262 mutex_lock(&dev_priv->dpio_lock);
5263 /* adjust cdclk divider */
5264 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5265 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5266 val |= divider;
5267 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5268
5269 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5270 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5271 50))
5272 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5273 mutex_unlock(&dev_priv->dpio_lock);
5274 }
5275
5276 mutex_lock(&dev_priv->dpio_lock);
5277 /* adjust self-refresh exit latency value */
5278 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5279 val &= ~0x7f;
5280
5281 /*
5282 * For high bandwidth configs, we set a higher latency in the bunit
5283 * so that the core display fetch happens in time to avoid underruns.
5284 */
dfcab17e 5285 if (cdclk == 400000)
30a970c6
JB		 5286 val |= 4500 / 250; /* 4.5 usec */
5287 else
5288 val |= 3000 / 250; /* 3.0 usec */
5289 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5290 mutex_unlock(&dev_priv->dpio_lock);
5291
f8bf63fd 5292 vlv_update_cdclk(dev);
30a970c6
JB		 5293}
5294
383c5a6a
VS		 5295static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5296{
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298 u32 val, cmd;
5299
164dfd28
VK		 5300 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5301 != dev_priv->cdclk_freq);
383c5a6a
VS		 5302
5303 switch (cdclk) {
383c5a6a
VS		 5304 case 333333:
5305 case 320000:
383c5a6a 5306 case 266667:
383c5a6a 5307 case 200000:
383c5a6a
VS		 5308 break;
5309 default:
5f77eeb0 5310 MISSING_CASE(cdclk);
383c5a6a
VS		 5311 return;
5312 }
5313
9d0d3fda
VS		 5314 /*
5315 * Specs are full of misinformation, but testing on actual
5316 * hardware has shown that we just need to write the desired
5317 * CCK divider into the Punit register.
5318 */
5319 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5320
383c5a6a
VS		 5321 mutex_lock(&dev_priv->rps.hw_lock);
5322 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5323 val &= ~DSPFREQGUAR_MASK_CHV;
5324 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5325 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5326 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5327 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5328 50)) {
5329 DRM_ERROR("timed out waiting for CDclk change\n");
5330 }
5331 mutex_unlock(&dev_priv->rps.hw_lock);
5332
5333 vlv_update_cdclk(dev);
5334}
5335
30a970c6
JB		 5336static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5337 int max_pixclk)
5338{
6bcda4f0 5339 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5340 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5341
30a970c6
JB		 5342 /*
5343 * Really only a few cases to deal with, as only 4 CDclks are supported:
5344 * 200MHz
5345 * 267MHz
29dc7ef3 5346 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5347 * 400MHz (VLV only)
5348 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5349 * of the lower bin and adjust if needed.
e37c67a1
VS		 5350 *
5351 * We seem to get an unstable or solid color picture at 200MHz.
5352 * Not sure what's wrong. For now use 200MHz only when all pipes
5353 * are off.
30a970c6 5354 */
6cca3195
VS		 5355 if (!IS_CHERRYVIEW(dev_priv) &&
5356 max_pixclk > freq_320*limit/100)
dfcab17e 5357 return 400000;
6cca3195 5358 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5359 return freq_320;
e37c67a1 5360 else if (max_pixclk > 0)
dfcab17e 5361 return 266667;
e37c67a1
VS		 5362 else
5363 return 200000;
30a970c6
JB		 5364}
5365
2f2d7aa1 5366/* compute the max pixel clock for new configuration */
304603f4 5367static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5368{
304603f4 5369 struct drm_device *dev = state->dev;
30a970c6 5370 struct intel_crtc *intel_crtc;
304603f4 5371 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5372 int max_pixclk = 0;
5373
d3fcc808 5374 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5375 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5376 if (IS_ERR(crtc_state))
5377 return PTR_ERR(crtc_state);
5378
5379 if (!crtc_state->base.enable)
5380 continue;
5381
5382 max_pixclk = max(max_pixclk,
5383 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5384 }
5385
5386 return max_pixclk;
5387}
5388
304603f4 5389static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5390 unsigned *prepare_pipes)
30a970c6 5391{
304603f4 5392 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5393 struct intel_crtc *intel_crtc;
304603f4
ACO		 5394 int max_pixclk = intel_mode_max_pixclk(state);
5395
5396 if (max_pixclk < 0)
5397 return max_pixclk;
30a970c6 5398
d60c4473 5399 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
164dfd28 5400 dev_priv->cdclk_freq)
304603f4 5401 return 0;
30a970c6 5402
2f2d7aa1 5403 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5404 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5405 if (intel_crtc->base.state->enable)
30a970c6 5406 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5407
5408 return 0;
30a970c6
JB		 5409}
5410
1e69cd74
VS		 5411static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5412{
5413 unsigned int credits, default_credits;
5414
5415 if (IS_CHERRYVIEW(dev_priv))
5416 default_credits = PFI_CREDIT(12);
5417 else
5418 default_credits = PFI_CREDIT(8);
5419
164dfd28 5420 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5421 /* CHV suggested value is 31 or 63 */
5422 if (IS_CHERRYVIEW(dev_priv))
5423 credits = PFI_CREDIT_31;
5424 else
5425 credits = PFI_CREDIT(15);
5426 } else {
5427 credits = default_credits;
5428 }
5429
5430 /*
5431 * WA - write default credits before re-programming
5432 * FIXME: should we also set the resend bit here?
5433 */
5434 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5435 default_credits);
5436
5437 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5438 credits | PFI_CREDIT_RESEND);
5439
5440 /*
5441 * FIXME is this guaranteed to clear
5442 * immediately or should we poll for it?
5443 */
5444 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5445}
5446
679dacd4 5447static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5448{
679dacd4 5449 struct drm_device *dev = state->dev;
30a970c6 5450 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5451 int max_pixclk = intel_mode_max_pixclk(state);
5452 int req_cdclk;
5453
5454 /* The only reason this can fail is if we fail to add the crtc_state
5455 * to the atomic state. But that can't happen since the call to
5456 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5457 * can't have failed otherwise the mode set would be aborted) added all
5458 * the states already. */
5459 if (WARN_ON(max_pixclk < 0))
5460 return;
5461
5462 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5463
164dfd28 5464 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5465 /*
5466 * FIXME: We can end up here with all power domains off, yet
5467 * with a CDCLK frequency other than the minimum. To account
5468 * for this take the PIPE-A power domain, which covers the HW
5469 * blocks needed for the following programming. This can be
5470 * removed once it's guaranteed that we get here either with
5471 * the minimum CDCLK set, or the required power domains
5472 * enabled.
5473 */
5474 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5475
383c5a6a
VS		 5476 if (IS_CHERRYVIEW(dev))
5477 cherryview_set_cdclk(dev, req_cdclk);
5478 else
5479 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5480
1e69cd74
VS		 5481 vlv_program_pfi_credits(dev_priv);
5482
738c05c0 5483 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5484 }
30a970c6
JB		 5485}
5486
89b667f8
JB		 5487static void valleyview_crtc_enable(struct drm_crtc *crtc)
5488{
5489 struct drm_device *dev = crtc->dev;
a72e4c9f 5490 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5492 struct intel_encoder *encoder;
5493 int pipe = intel_crtc->pipe;
23538ef1 5494 bool is_dsi;
89b667f8 5495
83d65738 5496 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5497
5498 if (intel_crtc->active)
5499 return;
5500
409ee761 5501 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5502
1ae0d137
VS		 5503 if (!is_dsi) {
5504 if (IS_CHERRYVIEW(dev))
6e3c9717 5505 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5506 else
6e3c9717 5507 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5508 }
5b18e57c 5509
6e3c9717 5510 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5511 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5512
5513 intel_set_pipe_timings(intel_crtc);
5514
c14b0485
VS		 5515 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5516 struct drm_i915_private *dev_priv = dev->dev_private;
5517
5518 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5519 I915_WRITE(CHV_CANVAS(pipe), 0);
5520 }
5521
5b18e57c
DV		 5522 i9xx_set_pipeconf(intel_crtc);
5523
89b667f8 5524 intel_crtc->active = true;
89b667f8 5525
a72e4c9f 5526 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5527
89b667f8
JB		 5528 for_each_encoder_on_crtc(dev, crtc, encoder)
5529 if (encoder->pre_pll_enable)
5530 encoder->pre_pll_enable(encoder);
5531
9d556c99
CML		 5532 if (!is_dsi) {
5533 if (IS_CHERRYVIEW(dev))
6e3c9717 5534 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5535 else
6e3c9717 5536 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5537 }
89b667f8
JB		 5538
5539 for_each_encoder_on_crtc(dev, crtc, encoder)
5540 if (encoder->pre_enable)
5541 encoder->pre_enable(encoder);
5542
2dd24552
JB		 5543 i9xx_pfit_enable(intel_crtc);
5544
63cbb074
VS		 5545 intel_crtc_load_lut(crtc);
5546
f37fcc2a 5547 intel_update_watermarks(crtc);
e1fdc473 5548 intel_enable_pipe(intel_crtc);
be6a6f8e 5549
4b3a9526
VS		 5550 assert_vblank_disabled(crtc);
5551 drm_crtc_vblank_on(crtc);
5552
f9b61ff6
DV		 5553 for_each_encoder_on_crtc(dev, crtc, encoder)
5554 encoder->enable(encoder);
5555
9ab0460b 5556 intel_crtc_enable_planes(crtc);
d40d9187 5557
56b80e1f 5558 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5559 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5560}
5561
f13c2ef3
DV		 5562static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5563{
5564 struct drm_device *dev = crtc->base.dev;
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566
6e3c9717
ACO		 5567 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5568 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5569}
5570
0b8765c6 5571static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5572{
5573 struct drm_device *dev = crtc->dev;
a72e4c9f 5574 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5576 struct intel_encoder *encoder;
79e53945 5577 int pipe = intel_crtc->pipe;
79e53945 5578
83d65738 5579 WARN_ON(!crtc->state->enable);
08a48469 5580
f7abfe8b
CW		 5581 if (intel_crtc->active)
5582 return;
5583
f13c2ef3
DV		 5584 i9xx_set_pll_dividers(intel_crtc);
5585
6e3c9717 5586 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5587 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5588
5589 intel_set_pipe_timings(intel_crtc);
5590
5b18e57c
DV		 5591 i9xx_set_pipeconf(intel_crtc);
5592
f7abfe8b 5593 intel_crtc->active = true;
6b383a7f 5594
4a3436e8 5595 if (!IS_GEN2(dev))
a72e4c9f 5596 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5597
9d6d9f19
MK		 5598 for_each_encoder_on_crtc(dev, crtc, encoder)
5599 if (encoder->pre_enable)
5600 encoder->pre_enable(encoder);
5601
f6736a1a
DV		 5602 i9xx_enable_pll(intel_crtc);
5603
2dd24552
JB		 5604 i9xx_pfit_enable(intel_crtc);
5605
63cbb074
VS		 5606 intel_crtc_load_lut(crtc);
5607
f37fcc2a 5608 intel_update_watermarks(crtc);
e1fdc473 5609 intel_enable_pipe(intel_crtc);
be6a6f8e 5610
4b3a9526
VS		 5611 assert_vblank_disabled(crtc);
5612 drm_crtc_vblank_on(crtc);
5613
f9b61ff6
DV		 5614 for_each_encoder_on_crtc(dev, crtc, encoder)
5615 encoder->enable(encoder);
5616
9ab0460b 5617 intel_crtc_enable_planes(crtc);
d40d9187 5618
4a3436e8
VS		 5619 /*
5620 * Gen2 reports pipe underruns whenever all planes are disabled.
5621 * So don't enable underrun reporting before at least some planes
5622 * are enabled.
5623 * FIXME: Need to fix the logic to work when we turn off all planes
5624 * but leave the pipe running.
5625 */
5626 if (IS_GEN2(dev))
a72e4c9f 5627 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5628
56b80e1f 5629 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5630 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5631}
79e53945 5632
87476d63
DV		 5633static void i9xx_pfit_disable(struct intel_crtc *crtc)
5634{
5635 struct drm_device *dev = crtc->base.dev;
5636 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5637
6e3c9717 5638 if (!crtc->config->gmch_pfit.control)
328d8e82 5639 return;
87476d63 5640
328d8e82 5641 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5642
328d8e82
DV		 5643 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5644 I915_READ(PFIT_CONTROL));
5645 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5646}
5647
0b8765c6
JB		 5648static void i9xx_crtc_disable(struct drm_crtc *crtc)
5649{
5650 struct drm_device *dev = crtc->dev;
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5653 struct intel_encoder *encoder;
0b8765c6 5654 int pipe = intel_crtc->pipe;
ef9c3aee 5655
f7abfe8b
CW		 5656 if (!intel_crtc->active)
5657 return;
5658
4a3436e8
VS		 5659 /*
5660 * Gen2 reports pipe underruns whenever all planes are disabled.
5661 * So diasble underrun reporting before all the planes get disabled.
5662 * FIXME: Need to fix the logic to work when we turn off all planes
5663 * but leave the pipe running.
5664 */
5665 if (IS_GEN2(dev))
a72e4c9f 5666 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5667
564ed191
ID		 5668 /*
5669 * Vblank time updates from the shadow to live plane control register
5670 * are blocked if the memory self-refresh mode is active at that
5671 * moment. So to make sure the plane gets truly disabled, disable
5672 * first the self-refresh mode. The self-refresh enable bit in turn
5673 * will be checked/applied by the HW only at the next frame start
5674 * event which is after the vblank start event, so we need to have a
5675 * wait-for-vblank between disabling the plane and the pipe.
5676 */
5677 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5678 intel_crtc_disable_planes(crtc);
5679
6304cd91
VS		 5680 /*
5681 * On gen2 planes are double buffered but the pipe isn't, so we must
5682 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5683 * We also need to wait on all gmch platforms because of the
5684 * self-refresh mode constraint explained above.
6304cd91 5685 */
564ed191 5686 intel_wait_for_vblank(dev, pipe);
6304cd91 5687
4b3a9526
VS		 5688 for_each_encoder_on_crtc(dev, crtc, encoder)
5689 encoder->disable(encoder);
5690
f9b61ff6
DV		 5691 drm_crtc_vblank_off(crtc);
5692 assert_vblank_disabled(crtc);
5693
575f7ab7 5694 intel_disable_pipe(intel_crtc);
24a1f16d 5695
87476d63 5696 i9xx_pfit_disable(intel_crtc);
24a1f16d 5697
89b667f8
JB		 5698 for_each_encoder_on_crtc(dev, crtc, encoder)
5699 if (encoder->post_disable)
5700 encoder->post_disable(encoder);
5701
409ee761 5702 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5703 if (IS_CHERRYVIEW(dev))
5704 chv_disable_pll(dev_priv, pipe);
5705 else if (IS_VALLEYVIEW(dev))
5706 vlv_disable_pll(dev_priv, pipe);
5707 else
1c4e0274 5708 i9xx_disable_pll(intel_crtc);
076ed3b2 5709 }
0b8765c6 5710
4a3436e8 5711 if (!IS_GEN2(dev))
a72e4c9f 5712 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5713
f7abfe8b 5714 intel_crtc->active = false;
46ba614c 5715 intel_update_watermarks(crtc);
f37fcc2a 5716
efa9624e 5717 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5718 intel_fbc_update(dev);
efa9624e 5719 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5720}
5721
ee7b9f93
JB		 5722static void i9xx_crtc_off(struct drm_crtc *crtc)
5723{
5724}
5725
b04c5bd6
BF		 5726/* Master function to enable/disable CRTC and corresponding power wells */
5727void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5728{
5729 struct drm_device *dev = crtc->dev;
5730 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5732 enum intel_display_power_domain domain;
5733 unsigned long domains;
976f8a20 5734
0e572fe7
DV		 5735 if (enable) {
5736 if (!intel_crtc->active) {
e1e9fb84
DV		 5737 domains = get_crtc_power_domains(crtc);
5738 for_each_power_domain(domain, domains)
5739 intel_display_power_get(dev_priv, domain);
5740 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5741
5742 dev_priv->display.crtc_enable(crtc);
5743 }
5744 } else {
5745 if (intel_crtc->active) {
5746 dev_priv->display.crtc_disable(crtc);
5747
e1e9fb84
DV		 5748 domains = intel_crtc->enabled_power_domains;
5749 for_each_power_domain(domain, domains)
5750 intel_display_power_put(dev_priv, domain);
5751 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5752 }
5753 }
b04c5bd6
BF		 5754}
5755
5756/**
5757 * Sets the power management mode of the pipe and plane.
5758 */
5759void intel_crtc_update_dpms(struct drm_crtc *crtc)
5760{
5761 struct drm_device *dev = crtc->dev;
5762 struct intel_encoder *intel_encoder;
5763 bool enable = false;
5764
5765 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5766 enable |= intel_encoder->connectors_active;
5767
5768 intel_crtc_control(crtc, enable);
976f8a20
DV		 5769}
5770
cdd59983
CW		 5771static void intel_crtc_disable(struct drm_crtc *crtc)
5772{
cdd59983 5773 struct drm_device *dev = crtc->dev;
976f8a20 5774 struct drm_connector *connector;
ee7b9f93 5775 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5776
976f8a20 5777 /* crtc should still be enabled when we disable it. */
83d65738 5778 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5779
5780 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5781 dev_priv->display.off(crtc);
5782
70a101f8 5783 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 5784
5785 /* Update computed state. */
5786 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5787 if (!connector->encoder || !connector->encoder->crtc)
5788 continue;
5789
5790 if (connector->encoder->crtc != crtc)
5791 continue;
5792
5793 connector->dpms = DRM_MODE_DPMS_OFF;
5794 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5795 }
5796}
5797
ea5b213a 5798void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5799{
4ef69c7a 5800 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5801
ea5b213a
CW		 5802 drm_encoder_cleanup(encoder);
5803 kfree(intel_encoder);
7e7d76c3
JB		 5804}
5805
9237329d 5806/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5807 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5808 * state of the entire output pipe. */
9237329d 5809static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5810{
5ab432ef
DV		 5811 if (mode == DRM_MODE_DPMS_ON) {
5812 encoder->connectors_active = true;
5813
b2cabb0e 5814 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5815 } else {
5816 encoder->connectors_active = false;
5817
b2cabb0e 5818 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5819 }
79e53945
JB		 5820}
5821
0a91ca29
DV		 5822/* Cross check the actual hw state with our own modeset state tracking (and it's
5823 * internal consistency). */
b980514c 5824static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5825{
0a91ca29
DV		 5826 if (connector->get_hw_state(connector)) {
5827 struct intel_encoder *encoder = connector->encoder;
5828 struct drm_crtc *crtc;
5829 bool encoder_enabled;
5830 enum pipe pipe;
5831
5832 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5833 connector->base.base.id,
c23cc417 5834 connector->base.name);
0a91ca29 5835
0e32b39c
DA		 5836 /* there is no real hw state for MST connectors */
5837 if (connector->mst_port)
5838 return;
5839
e2c719b7 5840 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5841 "wrong connector dpms state\n");
e2c719b7 5842 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5843 "active connector not linked to encoder\n");
0a91ca29 5844
36cd7444 5845 if (encoder) {
e2c719b7 5846 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5847 "encoder->connectors_active not set\n");
5848
5849 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5850 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5851 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5852 return;
0a91ca29 5853
36cd7444 5854 crtc = encoder->base.crtc;
0a91ca29 5855
83d65738
MR		 5856 I915_STATE_WARN(!crtc->state->enable,
5857 "crtc not enabled\n");
e2c719b7
RC		 5858 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5859 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5860 "encoder active on the wrong pipe\n");
5861 }
0a91ca29 5862 }
79e53945
JB		 5863}
5864
9bdbd0b9
ACO		 5865int intel_connector_init(struct intel_connector *connector)
5866{
5867 struct drm_connector_state *connector_state;
5868
5869 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
5870 if (!connector_state)
5871 return -ENOMEM;
5872
5873 connector->base.state = connector_state;
5874 return 0;
5875}
5876
5877struct intel_connector *intel_connector_alloc(void)
5878{
5879 struct intel_connector *connector;
5880
5881 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5882 if (!connector)
5883 return NULL;
5884
5885 if (intel_connector_init(connector) < 0) {
5886 kfree(connector);
5887 return NULL;
5888 }
5889
5890 return connector;
5891}
5892
5ab432ef
DV		 5893/* Even simpler default implementation, if there's really no special case to
5894 * consider. */
5895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5896{
5ab432ef
DV		 5897 /* All the simple cases only support two dpms states. */
5898 if (mode != DRM_MODE_DPMS_ON)
5899 mode = DRM_MODE_DPMS_OFF;
d4270e57 5900
5ab432ef
DV		 5901 if (mode == connector->dpms)
5902 return;
5903
5904 connector->dpms = mode;
5905
5906 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5907 if (connector->encoder)
5908 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5909
b980514c 5910 intel_modeset_check_state(connector->dev);
79e53945
JB		 5911}
5912
f0947c37
DV		 5913/* Simple connector->get_hw_state implementation for encoders that support only
5914 * one connector and no cloning and hence the encoder state determines the state
5915 * of the connector. */
5916bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5917{
24929352 5918 enum pipe pipe = 0;
f0947c37 5919 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5920
f0947c37 5921 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5922}
5923
6d293983 5924static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 5925{
6d293983
ACO		 5926 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5927 return crtc_state->fdi_lanes;
d272ddfa
VS		 5928
5929 return 0;
5930}
5931
6d293983 5932static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5933 struct intel_crtc_state *pipe_config)
1857e1da 5934{
6d293983
ACO		 5935 struct drm_atomic_state *state = pipe_config->base.state;
5936 struct intel_crtc *other_crtc;
5937 struct intel_crtc_state *other_crtc_state;
5938
1857e1da
DV		 5939 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5940 pipe_name(pipe), pipe_config->fdi_lanes);
5941 if (pipe_config->fdi_lanes > 4) {
5942 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5943 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5944 return -EINVAL;
1857e1da
DV		 5945 }
5946
bafb6553 5947 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5948 if (pipe_config->fdi_lanes > 2) {
5949 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5950 pipe_config->fdi_lanes);
6d293983 5951 return -EINVAL;
1857e1da 5952 } else {
6d293983 5953 return 0;
1857e1da
DV		 5954 }
5955 }
5956
5957 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 5958 return 0;
1857e1da
DV		 5959
5960 /* Ivybridge 3 pipe is really complicated */
5961 switch (pipe) {
5962 case PIPE_A:
6d293983 5963 return 0;
1857e1da 5964 case PIPE_B:
6d293983
ACO		 5965 if (pipe_config->fdi_lanes <= 2)
5966 return 0;
5967
5968 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5969 other_crtc_state =
5970 intel_atomic_get_crtc_state(state, other_crtc);
5971 if (IS_ERR(other_crtc_state))
5972 return PTR_ERR(other_crtc_state);
5973
5974 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 5975 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5976 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5977 return -EINVAL;
1857e1da 5978 }
6d293983 5979 return 0;
1857e1da 5980 case PIPE_C:
251cc67c
VS		 5981 if (pipe_config->fdi_lanes > 2) {
5982 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5983 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5984 return -EINVAL;
251cc67c 5985 }
6d293983
ACO		 5986
5987 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5988 other_crtc_state =
5989 intel_atomic_get_crtc_state(state, other_crtc);
5990 if (IS_ERR(other_crtc_state))
5991 return PTR_ERR(other_crtc_state);
5992
5993 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 5994 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 5995 return -EINVAL;
1857e1da 5996 }
6d293983 5997 return 0;
1857e1da
DV		 5998 default:
5999 BUG();
6000 }
6001}
6002
e29c22c0
DV		 6003#define RETRY 1
6004static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6005 struct intel_crtc_state *pipe_config)
877d48d5 6006{
1857e1da 6007 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6008 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6009 int lane, link_bw, fdi_dotclock, ret;
6010 bool needs_recompute = false;
877d48d5 6011
e29c22c0 6012retry:
877d48d5
DV		 6013 /* FDI is a binary signal running at ~2.7GHz, encoding
6014 * each output octet as 10 bits. The actual frequency
6015 * is stored as a divider into a 100MHz clock, and the
6016 * mode pixel clock is stored in units of 1KHz.
6017 * Hence the bw of each lane in terms of the mode signal
6018 * is:
6019 */
6020 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6021
241bfc38 6022 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6023
2bd89a07 6024 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6025 pipe_config->pipe_bpp);
6026
6027 pipe_config->fdi_lanes = lane;
6028
2bd89a07 6029 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6030 link_bw, &pipe_config->fdi_m_n);
1857e1da 6031
6d293983
ACO		 6032 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6033 intel_crtc->pipe, pipe_config);
6034 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6035 pipe_config->pipe_bpp -= 2*3;
6036 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6037 pipe_config->pipe_bpp);
6038 needs_recompute = true;
6039 pipe_config->bw_constrained = true;
6040
6041 goto retry;
6042 }
6043
6044 if (needs_recompute)
6045 return RETRY;
6046
6d293983 6047 return ret;
877d48d5
DV		 6048}
6049
42db64ef 6050static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6051 struct intel_crtc_state *pipe_config)
42db64ef 6052{
d330a953 6053 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6054 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6055 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6056}
6057
a43f6e0f 6058static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6059 struct intel_crtc_state *pipe_config)
79e53945 6060{
a43f6e0f 6061 struct drm_device *dev = crtc->base.dev;
8bd31e67 6062 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6063 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6064 int ret;
89749350 6065
ad3a4479 6066 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6067 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6068 int clock_limit =
6069 dev_priv->display.get_display_clock_speed(dev);
6070
6071 /*
6072 * Enable pixel doubling when the dot clock
6073 * is > 90% of the (display) core speed.
6074 *
b397c96b
VS		 6075 * GDG double wide on either pipe,
6076 * otherwise pipe A only.
cf532bb2 6077 */
b397c96b 6078 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6079 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6080 clock_limit *= 2;
cf532bb2 6081 pipe_config->double_wide = true;
ad3a4479
VS		 6082 }
6083
241bfc38 6084 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6085 return -EINVAL;
2c07245f 6086 }
89749350 6087
1d1d0e27
VS		 6088 /*
6089 * Pipe horizontal size must be even in:
6090 * - DVO ganged mode
6091 * - LVDS dual channel mode
6092 * - Double wide pipe
6093 */
a93e255f 6094 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6095 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6096 pipe_config->pipe_src_w &= ~1;
6097
8693a824
DL		 6098 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6099 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6100 */
6101 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6102 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6103 return -EINVAL;
44f46b42 6104
bd080ee5 6105 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 6106 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 6107 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 6108 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
6109 * for lvds. */
6110 pipe_config->pipe_bpp = 8*3;
6111 }
6112
f5adf94e 6113 if (HAS_IPS(dev))
a43f6e0f
DV		 6114 hsw_compute_ips_config(crtc, pipe_config);
6115
877d48d5 6116 if (pipe_config->has_pch_encoder)
a43f6e0f 6117 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6118
d03c93d4
CK		 6119 /* FIXME: remove below call once atomic mode set is place and all crtc
6120 * related checks called from atomic_crtc_check function */
6121 ret = 0;
6122 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6123 crtc, pipe_config->base.state);
6124 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6125
6126 return ret;
79e53945
JB		 6127}
6128
1652d19e
VS		 6129static int skylake_get_display_clock_speed(struct drm_device *dev)
6130{
6131 struct drm_i915_private *dev_priv = to_i915(dev);
6132 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6133 uint32_t cdctl = I915_READ(CDCLK_CTL);
6134 uint32_t linkrate;
6135
6136 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6137 WARN(1, "LCPLL1 not enabled\n");
6138 return 24000; /* 24MHz is the cd freq with NSSC ref */
6139 }
6140
6141 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6142 return 540000;
6143
6144 linkrate = (I915_READ(DPLL_CTRL1) &
6145 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6146
6147 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
6148 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
6149 /* vco 8640 */
6150 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6151 case CDCLK_FREQ_450_432:
6152 return 432000;
6153 case CDCLK_FREQ_337_308:
6154 return 308570;
6155 case CDCLK_FREQ_675_617:
6156 return 617140;
6157 default:
6158 WARN(1, "Unknown cd freq selection\n");
6159 }
6160 } else {
6161 /* vco 8100 */
6162 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6163 case CDCLK_FREQ_450_432:
6164 return 450000;
6165 case CDCLK_FREQ_337_308:
6166 return 337500;
6167 case CDCLK_FREQ_675_617:
6168 return 675000;
6169 default:
6170 WARN(1, "Unknown cd freq selection\n");
6171 }
6172 }
6173
6174 /* error case, do as if DPLL0 isn't enabled */
6175 return 24000;
6176}
6177
6178static int broadwell_get_display_clock_speed(struct drm_device *dev)
6179{
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181 uint32_t lcpll = I915_READ(LCPLL_CTL);
6182 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6183
6184 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6185 return 800000;
6186 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6187 return 450000;
6188 else if (freq == LCPLL_CLK_FREQ_450)
6189 return 450000;
6190 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6191 return 540000;
6192 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6193 return 337500;
6194 else
6195 return 675000;
6196}
6197
6198static int haswell_get_display_clock_speed(struct drm_device *dev)
6199{
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 uint32_t lcpll = I915_READ(LCPLL_CTL);
6202 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6203
6204 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6205 return 800000;
6206 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6207 return 450000;
6208 else if (freq == LCPLL_CLK_FREQ_450)
6209 return 450000;
6210 else if (IS_HSW_ULT(dev))
6211 return 337500;
6212 else
6213 return 540000;
6214}
6215
25eb05fc
JB		 6216static int valleyview_get_display_clock_speed(struct drm_device *dev)
6217{
d197b7d3 6218 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6219 u32 val;
6220 int divider;
6221
6bcda4f0
VS		 6222 if (dev_priv->hpll_freq == 0)
6223 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6224
d197b7d3
VS		 6225 mutex_lock(&dev_priv->dpio_lock);
6226 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6227 mutex_unlock(&dev_priv->dpio_lock);
6228
6229 divider = val & DISPLAY_FREQUENCY_VALUES;
6230
7d007f40
VS		 6231 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6232 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6233 "cdclk change in progress\n");
6234
6bcda4f0 6235 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6236}
6237
b37a6434
VS		 6238static int ilk_get_display_clock_speed(struct drm_device *dev)
6239{
6240 return 450000;
6241}
6242
e70236a8
JB		 6243static int i945_get_display_clock_speed(struct drm_device *dev)
6244{
6245 return 400000;
6246}
79e53945 6247
e70236a8 6248static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6249{
e907f170 6250 return 333333;
e70236a8 6251}
79e53945 6252
e70236a8
JB		 6253static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6254{
6255 return 200000;
6256}
79e53945 6257
257a7ffc
DV		 6258static int pnv_get_display_clock_speed(struct drm_device *dev)
6259{
6260 u16 gcfgc = 0;
6261
6262 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6263
6264 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6265 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6266 return 266667;
257a7ffc 6267 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6268 return 333333;
257a7ffc 6269 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6270 return 444444;
257a7ffc
DV		 6271 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6272 return 200000;
6273 default:
6274 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6275 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6276 return 133333;
257a7ffc 6277 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6278 return 166667;
257a7ffc
DV		 6279 }
6280}
6281
e70236a8
JB		 6282static int i915gm_get_display_clock_speed(struct drm_device *dev)
6283{
6284 u16 gcfgc = 0;
79e53945 6285
e70236a8
JB		 6286 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6287
6288 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6289 return 133333;
e70236a8
JB		 6290 else {
6291 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6292 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6293 return 333333;
e70236a8
JB		 6294 default:
6295 case GC_DISPLAY_CLOCK_190_200_MHZ:
6296 return 190000;
79e53945 6297 }
e70236a8
JB		 6298 }
6299}
6300
6301static int i865_get_display_clock_speed(struct drm_device *dev)
6302{
e907f170 6303 return 266667;
e70236a8
JB		 6304}
6305
6306static int i855_get_display_clock_speed(struct drm_device *dev)
6307{
6308 u16 hpllcc = 0;
6309 /* Assume that the hardware is in the high speed state. This
6310 * should be the default.
6311 */
6312 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6313 case GC_CLOCK_133_200:
6314 case GC_CLOCK_100_200:
6315 return 200000;
6316 case GC_CLOCK_166_250:
6317 return 250000;
6318 case GC_CLOCK_100_133:
e907f170 6319 return 133333;
e70236a8 6320 }
79e53945 6321
e70236a8
JB		 6322 /* Shouldn't happen */
6323 return 0;
6324}
79e53945 6325
e70236a8
JB		 6326static int i830_get_display_clock_speed(struct drm_device *dev)
6327{
e907f170 6328 return 133333;
79e53945
JB		 6329}
6330
2c07245f 6331static void
a65851af 6332intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6333{
a65851af
VS		 6334 while (*num > DATA_LINK_M_N_MASK ||
6335 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6336 *num >>= 1;
6337 *den >>= 1;
6338 }
6339}
6340
a65851af
VS		 6341static void compute_m_n(unsigned int m, unsigned int n,
6342 uint32_t *ret_m, uint32_t *ret_n)
6343{
6344 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6345 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6346 intel_reduce_m_n_ratio(ret_m, ret_n);
6347}
6348
e69d0bc1
DV		 6349void
6350intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6351 int pixel_clock, int link_clock,
6352 struct intel_link_m_n *m_n)
2c07245f 6353{
e69d0bc1 6354 m_n->tu = 64;
a65851af
VS		 6355
6356 compute_m_n(bits_per_pixel * pixel_clock,
6357 link_clock * nlanes * 8,
6358 &m_n->gmch_m, &m_n->gmch_n);
6359
6360 compute_m_n(pixel_clock, link_clock,
6361 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6362}
6363
a7615030
CW		 6364static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6365{
d330a953
JN		 6366 if (i915.panel_use_ssc >= 0)
6367 return i915.panel_use_ssc != 0;
41aa3448 6368 return dev_priv->vbt.lvds_use_ssc
435793df 6369 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6370}
6371
a93e255f
ACO		 6372static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6373 int num_connectors)
c65d77d8 6374{
a93e255f 6375 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 int refclk;
6378
a93e255f
ACO		 6379 WARN_ON(!crtc_state->base.state);
6380
a0c4da24 6381 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6382 refclk = 100000;
a93e255f 6383 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6384 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6385 refclk = dev_priv->vbt.lvds_ssc_freq;
6386 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6387 } else if (!IS_GEN2(dev)) {
6388 refclk = 96000;
6389 } else {
6390 refclk = 48000;
6391 }
6392
6393 return refclk;
6394}
6395
7429e9d4 6396static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6397{
7df00d7a 6398 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6399}
f47709a9 6400
7429e9d4
DV		 6401static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6402{
6403 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6404}
6405
f47709a9 6406static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6407 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6408 intel_clock_t *reduced_clock)
6409{
f47709a9 6410 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6411 u32 fp, fp2 = 0;
6412
6413 if (IS_PINEVIEW(dev)) {
190f68c5 6414 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6415 if (reduced_clock)
7429e9d4 6416 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6417 } else {
190f68c5 6418 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6419 if (reduced_clock)
7429e9d4 6420 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6421 }
6422
190f68c5 6423 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6424
f47709a9 6425 crtc->lowfreq_avail = false;
a93e255f 6426 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6427 reduced_clock) {
190f68c5 6428 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6429 crtc->lowfreq_avail = true;
a7516a05 6430 } else {
190f68c5 6431 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6432 }
6433}
6434
5e69f97f
CML		 6435static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6436 pipe)
89b667f8
JB		 6437{
6438 u32 reg_val;
6439
6440 /*
6441 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6442 * and set it to a reasonable value instead.
6443 */
ab3c759a 6444 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6445 reg_val &= 0xffffff00;
6446 reg_val |= 0x00000030;
ab3c759a 6447 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6448
ab3c759a 6449 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6450 reg_val &= 0x8cffffff;
6451 reg_val = 0x8c000000;
ab3c759a 6452 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6453
ab3c759a 6454 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6455 reg_val &= 0xffffff00;
ab3c759a 6456 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6457
ab3c759a 6458 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6459 reg_val &= 0x00ffffff;
6460 reg_val |= 0xb0000000;
ab3c759a 6461 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6462}
6463
b551842d
DV		 6464static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6465 struct intel_link_m_n *m_n)
6466{
6467 struct drm_device *dev = crtc->base.dev;
6468 struct drm_i915_private *dev_priv = dev->dev_private;
6469 int pipe = crtc->pipe;
6470
e3b95f1e
DV		 6471 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6472 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6473 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6474 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6475}
6476
6477static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6478 struct intel_link_m_n *m_n,
6479 struct intel_link_m_n *m2_n2)
b551842d
DV		 6480{
6481 struct drm_device *dev = crtc->base.dev;
6482 struct drm_i915_private *dev_priv = dev->dev_private;
6483 int pipe = crtc->pipe;
6e3c9717 6484 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6485
6486 if (INTEL_INFO(dev)->gen >= 5) {
6487 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6488 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6489 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6490 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6491 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6492 * for gen < 8) and if DRRS is supported (to make sure the
6493 * registers are not unnecessarily accessed).
6494 */
44395bfe 6495 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6496 crtc->config->has_drrs) {
f769cd24
VK		 6497 I915_WRITE(PIPE_DATA_M2(transcoder),
6498 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6499 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6500 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6501 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6502 }
b551842d 6503 } else {
e3b95f1e
DV		 6504 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6505 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6506 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6507 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6508 }
6509}
6510
fe3cd48d 6511void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6512{
fe3cd48d
R		 6513 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6514
6515 if (m_n == M1_N1) {
6516 dp_m_n = &crtc->config->dp_m_n;
6517 dp_m2_n2 = &crtc->config->dp_m2_n2;
6518 } else if (m_n == M2_N2) {
6519
6520 /*
6521 * M2_N2 registers are not supported. Hence m2_n2 divider value
6522 * needs to be programmed into M1_N1.
6523 */
6524 dp_m_n = &crtc->config->dp_m2_n2;
6525 } else {
6526 DRM_ERROR("Unsupported divider value\n");
6527 return;
6528 }
6529
6e3c9717
ACO		 6530 if (crtc->config->has_pch_encoder)
6531 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6532 else
fe3cd48d 6533 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6534}
6535
d288f65f 6536static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6537 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6538{
6539 u32 dpll, dpll_md;
6540
6541 /*
6542 * Enable DPIO clock input. We should never disable the reference
6543 * clock for pipe B, since VGA hotplug / manual detection depends
6544 * on it.
6545 */
6546 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6547 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6548 /* We should never disable this, set it here for state tracking */
6549 if (crtc->pipe == PIPE_B)
6550 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6551 dpll |= DPLL_VCO_ENABLE;
d288f65f 6552 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6553
d288f65f 6554 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6555 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6556 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6557}
6558
d288f65f 6559static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6560 const struct intel_crtc_state *pipe_config)
a0c4da24 6561{
f47709a9 6562 struct drm_device *dev = crtc->base.dev;
a0c4da24 6563 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6564 int pipe = crtc->pipe;
bdd4b6a6 6565 u32 mdiv;
a0c4da24 6566 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6567 u32 coreclk, reg_val;
a0c4da24 6568
09153000
DV		 6569 mutex_lock(&dev_priv->dpio_lock);
6570
d288f65f
VS		 6571 bestn = pipe_config->dpll.n;
6572 bestm1 = pipe_config->dpll.m1;
6573 bestm2 = pipe_config->dpll.m2;
6574 bestp1 = pipe_config->dpll.p1;
6575 bestp2 = pipe_config->dpll.p2;
a0c4da24 6576
89b667f8
JB		 6577 /* See eDP HDMI DPIO driver vbios notes doc */
6578
6579 /* PLL B needs special handling */
bdd4b6a6 6580 if (pipe == PIPE_B)
5e69f97f 6581 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6582
6583 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6585
6586 /* Disable target IRef on PLL */
ab3c759a 6587 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6588 reg_val &= 0x00ffffff;
ab3c759a 6589 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6590
6591 /* Disable fast lock */
ab3c759a 6592 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6593
6594 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6595 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6596 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6597 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6598 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6599
6600 /*
6601 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6602 * but we don't support that).
6603 * Note: don't use the DAC post divider as it seems unstable.
6604 */
6605 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6606 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6607
a0c4da24 6608 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6610
89b667f8 6611 /* Set HBR and RBR LPF coefficients */
d288f65f 6612 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6613 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6614 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6615 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6616 0x009f0003);
89b667f8 6617 else
ab3c759a 6618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6619 0x00d0000f);
6620
681a8504 6621 if (pipe_config->has_dp_encoder) {
89b667f8 6622 /* Use SSC source */
bdd4b6a6 6623 if (pipe == PIPE_A)
ab3c759a 6624 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6625 0x0df40000);
6626 else
ab3c759a 6627 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6628 0x0df70000);
6629 } else { /* HDMI or VGA */
6630 /* Use bend source */
bdd4b6a6 6631 if (pipe == PIPE_A)
ab3c759a 6632 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6633 0x0df70000);
6634 else
ab3c759a 6635 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6636 0x0df40000);
6637 }
a0c4da24 6638
ab3c759a 6639 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6640 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6642 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6643 coreclk |= 0x01000000;
ab3c759a 6644 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6645
ab3c759a 6646 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6647 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6648}
6649
d288f65f 6650static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6651 struct intel_crtc_state *pipe_config)
1ae0d137 6652{
d288f65f 6653 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6654 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6655 DPLL_VCO_ENABLE;
6656 if (crtc->pipe != PIPE_A)
d288f65f 6657 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6658
d288f65f
VS		 6659 pipe_config->dpll_hw_state.dpll_md =
6660 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6661}
6662
d288f65f 6663static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6664 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6665{
6666 struct drm_device *dev = crtc->base.dev;
6667 struct drm_i915_private *dev_priv = dev->dev_private;
6668 int pipe = crtc->pipe;
6669 int dpll_reg = DPLL(crtc->pipe);
6670 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6671 u32 loopfilter, tribuf_calcntr;
9d556c99 6672 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6673 u32 dpio_val;
9cbe40c1 6674 int vco;
9d556c99 6675
d288f65f
VS		 6676 bestn = pipe_config->dpll.n;
6677 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6678 bestm1 = pipe_config->dpll.m1;
6679 bestm2 = pipe_config->dpll.m2 >> 22;
6680 bestp1 = pipe_config->dpll.p1;
6681 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6682 vco = pipe_config->dpll.vco;
a945ce7e 6683 dpio_val = 0;
9cbe40c1 6684 loopfilter = 0;
9d556c99
CML		 6685
6686 /*
6687 * Enable Refclk and SSC
6688 */
a11b0703 6689 I915_WRITE(dpll_reg,
d288f65f 6690 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6691
6692 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6693
9d556c99
CML		 6694 /* p1 and p2 divider */
6695 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6696 5 << DPIO_CHV_S1_DIV_SHIFT |
6697 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6698 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6699 1 << DPIO_CHV_K_DIV_SHIFT);
6700
6701 /* Feedback post-divider - m2 */
6702 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6703
6704 /* Feedback refclk divider - n and m1 */
6705 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6706 DPIO_CHV_M1_DIV_BY_2 |
6707 1 << DPIO_CHV_N_DIV_SHIFT);
6708
6709 /* M2 fraction division */
a945ce7e
VP		 6710 if (bestm2_frac)
6711 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6712
6713 /* M2 fraction division enable */
a945ce7e
VP		 6714 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6715 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6716 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6717 if (bestm2_frac)
6718 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6719 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6720
de3a0fde
VP		 6721 /* Program digital lock detect threshold */
6722 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6723 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6724 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6725 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6726 if (!bestm2_frac)
6727 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6728 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6729
9d556c99 6730 /* Loop filter */
9cbe40c1
VP		 6731 if (vco == 5400000) {
6732 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6733 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6734 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6735 tribuf_calcntr = 0x9;
6736 } else if (vco <= 6200000) {
6737 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6738 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6739 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6740 tribuf_calcntr = 0x9;
6741 } else if (vco <= 6480000) {
6742 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6743 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6744 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6745 tribuf_calcntr = 0x8;
6746 } else {
6747 /* Not supported. Apply the same limits as in the max case */
6748 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6749 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6750 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6751 tribuf_calcntr = 0;
6752 }
9d556c99
CML		 6753 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6754
968040b2 6755 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6756 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6757 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6758 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6759
9d556c99
CML		 6760 /* AFC Recal */
6761 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6762 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6763 DPIO_AFC_RECAL);
6764
6765 mutex_unlock(&dev_priv->dpio_lock);
6766}
6767
d288f65f
VS		 6768/**
6769 * vlv_force_pll_on - forcibly enable just the PLL
6770 * @dev_priv: i915 private structure
6771 * @pipe: pipe PLL to enable
6772 * @dpll: PLL configuration
6773 *
6774 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6775 * in cases where we need the PLL enabled even when @pipe is not going to
6776 * be enabled.
6777 */
6778void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6779 const struct dpll *dpll)
6780{
6781 struct intel_crtc *crtc =
6782 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6783 struct intel_crtc_state pipe_config = {
a93e255f 6784 .base.crtc = &crtc->base,
d288f65f
VS		 6785 .pixel_multiplier = 1,
6786 .dpll = *dpll,
6787 };
6788
6789 if (IS_CHERRYVIEW(dev)) {
6790 chv_update_pll(crtc, &pipe_config);
6791 chv_prepare_pll(crtc, &pipe_config);
6792 chv_enable_pll(crtc, &pipe_config);
6793 } else {
6794 vlv_update_pll(crtc, &pipe_config);
6795 vlv_prepare_pll(crtc, &pipe_config);
6796 vlv_enable_pll(crtc, &pipe_config);
6797 }
6798}
6799
6800/**
6801 * vlv_force_pll_off - forcibly disable just the PLL
6802 * @dev_priv: i915 private structure
6803 * @pipe: pipe PLL to disable
6804 *
6805 * Disable the PLL for @pipe. To be used in cases where we need
6806 * the PLL enabled even when @pipe is not going to be enabled.
6807 */
6808void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6809{
6810 if (IS_CHERRYVIEW(dev))
6811 chv_disable_pll(to_i915(dev), pipe);
6812 else
6813 vlv_disable_pll(to_i915(dev), pipe);
6814}
6815
f47709a9 6816static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6817 struct intel_crtc_state *crtc_state,
f47709a9 6818 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6819 int num_connectors)
6820{
f47709a9 6821 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6822 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6823 u32 dpll;
6824 bool is_sdvo;
190f68c5 6825 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6826
190f68c5 6827 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6828
a93e255f
ACO		 6829 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6830 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6831
6832 dpll = DPLL_VGA_MODE_DIS;
6833
a93e255f 6834 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6835 dpll |= DPLLB_MODE_LVDS;
6836 else
6837 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6838
ef1b460d 6839 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6840 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6841 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6842 }
198a037f
DV		 6843
6844 if (is_sdvo)
4a33e48d 6845 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6846
190f68c5 6847 if (crtc_state->has_dp_encoder)
4a33e48d 6848 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6849
6850 /* compute bitmask from p1 value */
6851 if (IS_PINEVIEW(dev))
6852 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6853 else {
6854 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6855 if (IS_G4X(dev) && reduced_clock)
6856 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6857 }
6858 switch (clock->p2) {
6859 case 5:
6860 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6861 break;
6862 case 7:
6863 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6864 break;
6865 case 10:
6866 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6867 break;
6868 case 14:
6869 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6870 break;
6871 }
6872 if (INTEL_INFO(dev)->gen >= 4)
6873 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6874
190f68c5 6875 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6876 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 6877 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6878 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6879 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6880 else
6881 dpll |= PLL_REF_INPUT_DREFCLK;
6882
6883 dpll |= DPLL_VCO_ENABLE;
190f68c5 6884 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6885
eb1cbe48 6886 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6887 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6888 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6889 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6890 }
6891}
6892
f47709a9 6893static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6894 struct intel_crtc_state *crtc_state,
f47709a9 6895 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6896 int num_connectors)
6897{
f47709a9 6898 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6899 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6900 u32 dpll;
190f68c5 6901 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6902
190f68c5 6903 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6904
eb1cbe48
DV		 6905 dpll = DPLL_VGA_MODE_DIS;
6906
a93e255f 6907 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6908 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6909 } else {
6910 if (clock->p1 == 2)
6911 dpll |= PLL_P1_DIVIDE_BY_TWO;
6912 else
6913 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6914 if (clock->p2 == 4)
6915 dpll |= PLL_P2_DIVIDE_BY_4;
6916 }
6917
a93e255f 6918 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6919 dpll |= DPLL_DVO_2X_MODE;
6920
a93e255f 6921 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6922 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6923 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6924 else
6925 dpll |= PLL_REF_INPUT_DREFCLK;
6926
6927 dpll |= DPLL_VCO_ENABLE;
190f68c5 6928 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6929}
6930
8a654f3b 6931static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6932{
6933 struct drm_device *dev = intel_crtc->base.dev;
6934 struct drm_i915_private *dev_priv = dev->dev_private;
6935 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6936 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6937 struct drm_display_mode *adjusted_mode =
6e3c9717 6938 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6939 uint32_t crtc_vtotal, crtc_vblank_end;
6940 int vsyncshift = 0;
4d8a62ea
DV		 6941
6942 /* We need to be careful not to changed the adjusted mode, for otherwise
6943 * the hw state checker will get angry at the mismatch. */
6944 crtc_vtotal = adjusted_mode->crtc_vtotal;
6945 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6946
609aeaca 6947 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6948 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6949 crtc_vtotal -= 1;
6950 crtc_vblank_end -= 1;
609aeaca 6951
409ee761 6952 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6953 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6954 else
6955 vsyncshift = adjusted_mode->crtc_hsync_start -
6956 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6957 if (vsyncshift < 0)
6958 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6959 }
6960
6961 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6962 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6963
fe2b8f9d 6964 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6965 (adjusted_mode->crtc_hdisplay - 1) |
6966 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6967 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6968 (adjusted_mode->crtc_hblank_start - 1) |
6969 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6970 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6971 (adjusted_mode->crtc_hsync_start - 1) |
6972 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6973
fe2b8f9d 6974 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6975 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6976 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6977 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6978 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6979 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6980 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6981 (adjusted_mode->crtc_vsync_start - 1) |
6982 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6983
b5e508d4
PZ		 6984 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6985 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6986 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6987 * bits. */
6988 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6989 (pipe == PIPE_B || pipe == PIPE_C))
6990 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6991
b0e77b9c
PZ		 6992 /* pipesrc controls the size that is scaled from, which should
6993 * always be the user's requested size.
6994 */
6995 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6996 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6997 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6998}
6999
1bd1bd80 7000static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7001 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7002{
7003 struct drm_device *dev = crtc->base.dev;
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7006 uint32_t tmp;
7007
7008 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7009 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7010 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7011 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7012 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7013 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7014 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7015 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7016 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7017
7018 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7019 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7020 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7021 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7022 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7023 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7024 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7025 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7026 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7027
7028 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7029 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7030 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7031 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7032 }
7033
7034 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7035 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7036 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7037
2d112de7
ACO		 7038 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7039 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7040}
7041
f6a83288 7042void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7043 struct intel_crtc_state *pipe_config)
babea61d 7044{
2d112de7
ACO		 7045 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7046 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7047 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7048 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7049
2d112de7
ACO		 7050 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7051 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7052 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7053 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7054
2d112de7 7055 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7056
2d112de7
ACO		 7057 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7058 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7059}
7060
84b046f3
DV		 7061static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7062{
7063 struct drm_device *dev = intel_crtc->base.dev;
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065 uint32_t pipeconf;
7066
9f11a9e4 7067 pipeconf = 0;
84b046f3 7068
b6b5d049
VS		 7069 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7070 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7071 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7072
6e3c9717 7073 if (intel_crtc->config->double_wide)
cf532bb2 7074 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7075
ff9ce46e
DV		 7076 /* only g4x and later have fancy bpc/dither controls */
7077 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7078 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7079 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7080 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7081 PIPECONF_DITHER_TYPE_SP;
84b046f3 7082
6e3c9717 7083 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7084 case 18:
7085 pipeconf |= PIPECONF_6BPC;
7086 break;
7087 case 24:
7088 pipeconf |= PIPECONF_8BPC;
7089 break;
7090 case 30:
7091 pipeconf |= PIPECONF_10BPC;
7092 break;
7093 default:
7094 /* Case prevented by intel_choose_pipe_bpp_dither. */
7095 BUG();
84b046f3
DV		 7096 }
7097 }
7098
7099 if (HAS_PIPE_CXSR(dev)) {
7100 if (intel_crtc->lowfreq_avail) {
7101 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7102 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7103 } else {
7104 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7105 }
7106 }
7107
6e3c9717 7108 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7109 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7110 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7111 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7112 else
7113 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7114 } else
84b046f3
DV		 7115 pipeconf |= PIPECONF_PROGRESSIVE;
7116
6e3c9717 7117 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7118 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7119
84b046f3
DV		 7120 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7121 POSTING_READ(PIPECONF(intel_crtc->pipe));
7122}
7123
190f68c5
ACO		 7124static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7125 struct intel_crtc_state *crtc_state)
79e53945 7126{
c7653199 7127 struct drm_device *dev = crtc->base.dev;
79e53945 7128 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7129 int refclk, num_connectors = 0;
652c393a 7130 intel_clock_t clock, reduced_clock;
a16af721 7131 bool ok, has_reduced_clock = false;
e9fd1c02 7132 bool is_lvds = false, is_dsi = false;
5eddb70b 7133 struct intel_encoder *encoder;
d4906093 7134 const intel_limit_t *limit;
55bb9992
ACO		 7135 struct drm_atomic_state *state = crtc_state->base.state;
7136 struct drm_connector_state *connector_state;
7137 int i;
79e53945 7138
55bb9992
ACO		 7139 for (i = 0; i < state->num_connector; i++) {
7140 if (!state->connectors[i])
d0737e1d
ACO		 7141 continue;
7142
55bb9992
ACO		 7143 connector_state = state->connector_states[i];
7144 if (connector_state->crtc != &crtc->base)
7145 continue;
7146
7147 encoder = to_intel_encoder(connector_state->best_encoder);
7148
5eddb70b 7149 switch (encoder->type) {
79e53945
JB		 7150 case INTEL_OUTPUT_LVDS:
7151 is_lvds = true;
7152 break;
e9fd1c02
JN		 7153 case INTEL_OUTPUT_DSI:
7154 is_dsi = true;
7155 break;
6847d71b
PZ		 7156 default:
7157 break;
79e53945 7158 }
43565a06 7159
c751ce4f 7160 num_connectors++;
79e53945
JB		 7161 }
7162
f2335330 7163 if (is_dsi)
5b18e57c 7164 return 0;
f2335330 7165
190f68c5 7166 if (!crtc_state->clock_set) {
a93e255f 7167 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7168
e9fd1c02
JN		 7169 /*
7170 * Returns a set of divisors for the desired target clock with
7171 * the given refclk, or FALSE. The returned values represent
7172 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7173 * 2) / p1 / p2.
7174 */
a93e255f
ACO		 7175 limit = intel_limit(crtc_state, refclk);
7176 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7177 crtc_state->port_clock,
e9fd1c02 7178 refclk, NULL, &clock);
f2335330 7179 if (!ok) {
e9fd1c02
JN		 7180 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7181 return -EINVAL;
7182 }
79e53945 7183
f2335330
JN		 7184 if (is_lvds && dev_priv->lvds_downclock_avail) {
7185 /*
7186 * Ensure we match the reduced clock's P to the target
7187 * clock. If the clocks don't match, we can't switch
7188 * the display clock by using the FP0/FP1. In such case
7189 * we will disable the LVDS downclock feature.
7190 */
7191 has_reduced_clock =
a93e255f 7192 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7193 dev_priv->lvds_downclock,
7194 refclk, &clock,
7195 &reduced_clock);
7196 }
7197 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7198 crtc_state->dpll.n = clock.n;
7199 crtc_state->dpll.m1 = clock.m1;
7200 crtc_state->dpll.m2 = clock.m2;
7201 crtc_state->dpll.p1 = clock.p1;
7202 crtc_state->dpll.p2 = clock.p2;
f47709a9 7203 }
7026d4ac 7204
e9fd1c02 7205 if (IS_GEN2(dev)) {
190f68c5 7206 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7207 has_reduced_clock ? &reduced_clock : NULL,
7208 num_connectors);
9d556c99 7209 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7210 chv_update_pll(crtc, crtc_state);
e9fd1c02 7211 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7212 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7213 } else {
190f68c5 7214 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7215 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7216 num_connectors);
e9fd1c02 7217 }
79e53945 7218
c8f7a0db 7219 return 0;
f564048e
EA		 7220}
7221
2fa2fe9a 7222static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7223 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7224{
7225 struct drm_device *dev = crtc->base.dev;
7226 struct drm_i915_private *dev_priv = dev->dev_private;
7227 uint32_t tmp;
7228
dc9e7dec
VS		 7229 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7230 return;
7231
2fa2fe9a 7232 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7233 if (!(tmp & PFIT_ENABLE))
7234 return;
2fa2fe9a 7235
06922821 7236 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7237 if (INTEL_INFO(dev)->gen < 4) {
7238 if (crtc->pipe != PIPE_B)
7239 return;
2fa2fe9a
DV		 7240 } else {
7241 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7242 return;
7243 }
7244
06922821 7245 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7246 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7247 if (INTEL_INFO(dev)->gen < 5)
7248 pipe_config->gmch_pfit.lvds_border_bits =
7249 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7250}
7251
acbec814 7252static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7253 struct intel_crtc_state *pipe_config)
acbec814
JB		 7254{
7255 struct drm_device *dev = crtc->base.dev;
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257 int pipe = pipe_config->cpu_transcoder;
7258 intel_clock_t clock;
7259 u32 mdiv;
662c6ecb 7260 int refclk = 100000;
acbec814 7261
f573de5a
SK		 7262 /* In case of MIPI DPLL will not even be used */
7263 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7264 return;
7265
acbec814 7266 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7267 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7268 mutex_unlock(&dev_priv->dpio_lock);
7269
7270 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7271 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7272 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7273 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7274 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7275
f646628b 7276 vlv_clock(refclk, &clock);
acbec814 7277
f646628b
VS		 7278 /* clock.dot is the fast clock */
7279 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7280}
7281
5724dbd1
DL		 7282static void
7283i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7284 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7285{
7286 struct drm_device *dev = crtc->base.dev;
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 u32 val, base, offset;
7289 int pipe = crtc->pipe, plane = crtc->plane;
7290 int fourcc, pixel_format;
6761dd31 7291 unsigned int aligned_height;
b113d5ee 7292 struct drm_framebuffer *fb;
1b842c89 7293 struct intel_framebuffer *intel_fb;
1ad292b5 7294
42a7b088
DL		 7295 val = I915_READ(DSPCNTR(plane));
7296 if (!(val & DISPLAY_PLANE_ENABLE))
7297 return;
7298
d9806c9f 7299 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7300 if (!intel_fb) {
1ad292b5
JB		 7301 DRM_DEBUG_KMS("failed to alloc fb\n");
7302 return;
7303 }
7304
1b842c89
DL		 7305 fb = &intel_fb->base;
7306
18c5247e
DV		 7307 if (INTEL_INFO(dev)->gen >= 4) {
7308 if (val & DISPPLANE_TILED) {
49af449b 7309 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7310 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7311 }
7312 }
1ad292b5
JB		 7313
7314 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7315 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7316 fb->pixel_format = fourcc;
7317 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7318
7319 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7320 if (plane_config->tiling)
1ad292b5
JB		 7321 offset = I915_READ(DSPTILEOFF(plane));
7322 else
7323 offset = I915_READ(DSPLINOFF(plane));
7324 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7325 } else {
7326 base = I915_READ(DSPADDR(plane));
7327 }
7328 plane_config->base = base;
7329
7330 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7331 fb->width = ((val >> 16) & 0xfff) + 1;
7332 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7333
7334 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7335 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7336
b113d5ee 7337 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7338 fb->pixel_format,
7339 fb->modifier[0]);
1ad292b5 7340
f37b5c2b 7341 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7342
2844a921
DL		 7343 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7344 pipe_name(pipe), plane, fb->width, fb->height,
7345 fb->bits_per_pixel, base, fb->pitches[0],
7346 plane_config->size);
1ad292b5 7347
2d14030b 7348 plane_config->fb = intel_fb;
1ad292b5
JB		 7349}
7350
70b23a98 7351static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7352 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7353{
7354 struct drm_device *dev = crtc->base.dev;
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 int pipe = pipe_config->cpu_transcoder;
7357 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7358 intel_clock_t clock;
7359 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7360 int refclk = 100000;
7361
7362 mutex_lock(&dev_priv->dpio_lock);
7363 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7364 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7365 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7366 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7367 mutex_unlock(&dev_priv->dpio_lock);
7368
7369 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7370 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7371 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7372 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7373 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7374
7375 chv_clock(refclk, &clock);
7376
7377 /* clock.dot is the fast clock */
7378 pipe_config->port_clock = clock.dot / 5;
7379}
7380
0e8ffe1b 7381static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7382 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7383{
7384 struct drm_device *dev = crtc->base.dev;
7385 struct drm_i915_private *dev_priv = dev->dev_private;
7386 uint32_t tmp;
7387
f458ebbc
DV		 7388 if (!intel_display_power_is_enabled(dev_priv,
7389 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7390 return false;
7391
e143a21c 7392 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7393 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7394
0e8ffe1b
DV		 7395 tmp = I915_READ(PIPECONF(crtc->pipe));
7396 if (!(tmp & PIPECONF_ENABLE))
7397 return false;
7398
42571aef
VS		 7399 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7400 switch (tmp & PIPECONF_BPC_MASK) {
7401 case PIPECONF_6BPC:
7402 pipe_config->pipe_bpp = 18;
7403 break;
7404 case PIPECONF_8BPC:
7405 pipe_config->pipe_bpp = 24;
7406 break;
7407 case PIPECONF_10BPC:
7408 pipe_config->pipe_bpp = 30;
7409 break;
7410 default:
7411 break;
7412 }
7413 }
7414
b5a9fa09
DV		 7415 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7416 pipe_config->limited_color_range = true;
7417
282740f7
VS		 7418 if (INTEL_INFO(dev)->gen < 4)
7419 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7420
1bd1bd80
DV		 7421 intel_get_pipe_timings(crtc, pipe_config);
7422
2fa2fe9a
DV		 7423 i9xx_get_pfit_config(crtc, pipe_config);
7424
6c49f241
DV		 7425 if (INTEL_INFO(dev)->gen >= 4) {
7426 tmp = I915_READ(DPLL_MD(crtc->pipe));
7427 pipe_config->pixel_multiplier =
7428 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7429 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7430 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7431 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7432 tmp = I915_READ(DPLL(crtc->pipe));
7433 pipe_config->pixel_multiplier =
7434 ((tmp & SDVO_MULTIPLIER_MASK)
7435 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7436 } else {
7437 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7438 * port and will be fixed up in the encoder->get_config
7439 * function. */
7440 pipe_config->pixel_multiplier = 1;
7441 }
8bcc2795
DV		 7442 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7443 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7444 /*
7445 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7446 * on 830. Filter it out here so that we don't
7447 * report errors due to that.
7448 */
7449 if (IS_I830(dev))
7450 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7451
8bcc2795
DV		 7452 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7453 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7454 } else {
7455 /* Mask out read-only status bits. */
7456 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7457 DPLL_PORTC_READY_MASK |
7458 DPLL_PORTB_READY_MASK);
8bcc2795 7459 }
6c49f241 7460
70b23a98
VS		 7461 if (IS_CHERRYVIEW(dev))
7462 chv_crtc_clock_get(crtc, pipe_config);
7463 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7464 vlv_crtc_clock_get(crtc, pipe_config);
7465 else
7466 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7467
0e8ffe1b
DV		 7468 return true;
7469}
7470
dde86e2d 7471static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7472{
7473 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7474 struct intel_encoder *encoder;
74cfd7ac 7475 u32 val, final;
13d83a67 7476 bool has_lvds = false;
199e5d79 7477 bool has_cpu_edp = false;
199e5d79 7478 bool has_panel = false;
99eb6a01
KP		 7479 bool has_ck505 = false;
7480 bool can_ssc = false;
13d83a67
JB		 7481
7482 /* We need to take the global config into account */
b2784e15 7483 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7484 switch (encoder->type) {
7485 case INTEL_OUTPUT_LVDS:
7486 has_panel = true;
7487 has_lvds = true;
7488 break;
7489 case INTEL_OUTPUT_EDP:
7490 has_panel = true;
2de6905f 7491 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7492 has_cpu_edp = true;
7493 break;
6847d71b
PZ		 7494 default:
7495 break;
13d83a67
JB		 7496 }
7497 }
7498
99eb6a01 7499 if (HAS_PCH_IBX(dev)) {
41aa3448 7500 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7501 can_ssc = has_ck505;
7502 } else {
7503 has_ck505 = false;
7504 can_ssc = true;
7505 }
7506
2de6905f
ID		 7507 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7508 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7509
7510 /* Ironlake: try to setup display ref clock before DPLL
7511 * enabling. This is only under driver's control after
7512 * PCH B stepping, previous chipset stepping should be
7513 * ignoring this setting.
7514 */
74cfd7ac
CW		 7515 val = I915_READ(PCH_DREF_CONTROL);
7516
7517 /* As we must carefully and slowly disable/enable each source in turn,
7518 * compute the final state we want first and check if we need to
7519 * make any changes at all.
7520 */
7521 final = val;
7522 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7523 if (has_ck505)
7524 final |= DREF_NONSPREAD_CK505_ENABLE;
7525 else
7526 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7527
7528 final &= ~DREF_SSC_SOURCE_MASK;
7529 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7530 final &= ~DREF_SSC1_ENABLE;
7531
7532 if (has_panel) {
7533 final |= DREF_SSC_SOURCE_ENABLE;
7534
7535 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7536 final |= DREF_SSC1_ENABLE;
7537
7538 if (has_cpu_edp) {
7539 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7540 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7541 else
7542 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7543 } else
7544 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7545 } else {
7546 final |= DREF_SSC_SOURCE_DISABLE;
7547 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7548 }
7549
7550 if (final == val)
7551 return;
7552
13d83a67 7553 /* Always enable nonspread source */
74cfd7ac 7554 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7555
99eb6a01 7556 if (has_ck505)
74cfd7ac 7557 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7558 else
74cfd7ac 7559 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7560
199e5d79 7561 if (has_panel) {
74cfd7ac
CW		 7562 val &= ~DREF_SSC_SOURCE_MASK;
7563 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7564
199e5d79 7565 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7566 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7567 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7568 val |= DREF_SSC1_ENABLE;
e77166b5 7569 } else
74cfd7ac 7570 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7571
7572 /* Get SSC going before enabling the outputs */
74cfd7ac 7573 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7574 POSTING_READ(PCH_DREF_CONTROL);
7575 udelay(200);
7576
74cfd7ac 7577 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7578
7579 /* Enable CPU source on CPU attached eDP */
199e5d79 7580 if (has_cpu_edp) {
99eb6a01 7581 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7582 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7583 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7584 } else
74cfd7ac 7585 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7586 } else
74cfd7ac 7587 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7588
74cfd7ac 7589 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7590 POSTING_READ(PCH_DREF_CONTROL);
7591 udelay(200);
7592 } else {
7593 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7594
74cfd7ac 7595 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7596
7597 /* Turn off CPU output */
74cfd7ac 7598 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7599
74cfd7ac 7600 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7601 POSTING_READ(PCH_DREF_CONTROL);
7602 udelay(200);
7603
7604 /* Turn off the SSC source */
74cfd7ac
CW		 7605 val &= ~DREF_SSC_SOURCE_MASK;
7606 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7607
7608 /* Turn off SSC1 */
74cfd7ac 7609 val &= ~DREF_SSC1_ENABLE;
199e5d79 7610
74cfd7ac 7611 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7612 POSTING_READ(PCH_DREF_CONTROL);
7613 udelay(200);
7614 }
74cfd7ac
CW		 7615
7616 BUG_ON(val != final);
13d83a67
JB		 7617}
7618
f31f2d55 7619static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7620{
f31f2d55 7621 uint32_t tmp;
dde86e2d 7622
0ff066a9
PZ		 7623 tmp = I915_READ(SOUTH_CHICKEN2);
7624 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7625 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7626
0ff066a9
PZ		 7627 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7628 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7629 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7630
0ff066a9
PZ		 7631 tmp = I915_READ(SOUTH_CHICKEN2);
7632 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7633 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7634
0ff066a9
PZ		 7635 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7636 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7637 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7638}
7639
7640/* WaMPhyProgramming:hsw */
7641static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7642{
7643 uint32_t tmp;
dde86e2d
PZ		 7644
7645 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7646 tmp &= ~(0xFF << 24);
7647 tmp |= (0x12 << 24);
7648 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7649
dde86e2d
PZ		 7650 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7651 tmp |= (1 << 11);
7652 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7653
7654 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7655 tmp |= (1 << 11);
7656 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7657
dde86e2d
PZ		 7658 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7659 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7660 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7661
7662 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7663 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7664 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7665
0ff066a9
PZ		 7666 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7667 tmp &= ~(7 << 13);
7668 tmp |= (5 << 13);
7669 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7670
0ff066a9
PZ		 7671 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7672 tmp &= ~(7 << 13);
7673 tmp |= (5 << 13);
7674 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7675
7676 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7677 tmp &= ~0xFF;
7678 tmp |= 0x1C;
7679 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7680
7681 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7682 tmp &= ~0xFF;
7683 tmp |= 0x1C;
7684 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7685
7686 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7687 tmp &= ~(0xFF << 16);
7688 tmp |= (0x1C << 16);
7689 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7690
7691 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7692 tmp &= ~(0xFF << 16);
7693 tmp |= (0x1C << 16);
7694 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7695
0ff066a9
PZ		 7696 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7697 tmp |= (1 << 27);
7698 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7699
0ff066a9
PZ		 7700 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7701 tmp |= (1 << 27);
7702 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7703
0ff066a9
PZ		 7704 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7705 tmp &= ~(0xF << 28);
7706 tmp |= (4 << 28);
7707 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7708
0ff066a9
PZ		 7709 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7710 tmp &= ~(0xF << 28);
7711 tmp |= (4 << 28);
7712 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7713}
7714
2fa86a1f
PZ		 7715/* Implements 3 different sequences from BSpec chapter "Display iCLK
7716 * Programming" based on the parameters passed:
7717 * - Sequence to enable CLKOUT_DP
7718 * - Sequence to enable CLKOUT_DP without spread
7719 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7720 */
7721static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7722 bool with_fdi)
f31f2d55
PZ		 7723{
7724 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7725 uint32_t reg, tmp;
7726
7727 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7728 with_spread = true;
7729 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7730 with_fdi, "LP PCH doesn't have FDI\n"))
7731 with_fdi = false;
f31f2d55
PZ		 7732
7733 mutex_lock(&dev_priv->dpio_lock);
7734
7735 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7736 tmp &= ~SBI_SSCCTL_DISABLE;
7737 tmp |= SBI_SSCCTL_PATHALT;
7738 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7739
7740 udelay(24);
7741
2fa86a1f
PZ		 7742 if (with_spread) {
7743 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7744 tmp &= ~SBI_SSCCTL_PATHALT;
7745 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7746
2fa86a1f
PZ		 7747 if (with_fdi) {
7748 lpt_reset_fdi_mphy(dev_priv);
7749 lpt_program_fdi_mphy(dev_priv);
7750 }
7751 }
dde86e2d 7752
2fa86a1f
PZ		 7753 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7754 SBI_GEN0 : SBI_DBUFF0;
7755 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7756 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7757 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7758
7759 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7760}
7761
47701c3b
PZ		 7762/* Sequence to disable CLKOUT_DP */
7763static void lpt_disable_clkout_dp(struct drm_device *dev)
7764{
7765 struct drm_i915_private *dev_priv = dev->dev_private;
7766 uint32_t reg, tmp;
7767
7768 mutex_lock(&dev_priv->dpio_lock);
7769
7770 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7771 SBI_GEN0 : SBI_DBUFF0;
7772 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7773 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7774 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7775
7776 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7777 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7778 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7779 tmp |= SBI_SSCCTL_PATHALT;
7780 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7781 udelay(32);
7782 }
7783 tmp |= SBI_SSCCTL_DISABLE;
7784 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7785 }
7786
7787 mutex_unlock(&dev_priv->dpio_lock);
7788}
7789
bf8fa3d3
PZ		 7790static void lpt_init_pch_refclk(struct drm_device *dev)
7791{
bf8fa3d3
PZ		 7792 struct intel_encoder *encoder;
7793 bool has_vga = false;
7794
b2784e15 7795 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7796 switch (encoder->type) {
7797 case INTEL_OUTPUT_ANALOG:
7798 has_vga = true;
7799 break;
6847d71b
PZ		 7800 default:
7801 break;
bf8fa3d3
PZ		 7802 }
7803 }
7804
47701c3b
PZ		 7805 if (has_vga)
7806 lpt_enable_clkout_dp(dev, true, true);
7807 else
7808 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7809}
7810
dde86e2d
PZ		 7811/*
7812 * Initialize reference clocks when the driver loads
7813 */
7814void intel_init_pch_refclk(struct drm_device *dev)
7815{
7816 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7817 ironlake_init_pch_refclk(dev);
7818 else if (HAS_PCH_LPT(dev))
7819 lpt_init_pch_refclk(dev);
7820}
7821
55bb9992 7822static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 7823{
55bb9992 7824 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 7825 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7826 struct drm_atomic_state *state = crtc_state->base.state;
7827 struct drm_connector_state *connector_state;
d9d444cb 7828 struct intel_encoder *encoder;
55bb9992 7829 int num_connectors = 0, i;
d9d444cb
JB		 7830 bool is_lvds = false;
7831
55bb9992
ACO		 7832 for (i = 0; i < state->num_connector; i++) {
7833 if (!state->connectors[i])
d0737e1d
ACO		 7834 continue;
7835
55bb9992
ACO		 7836 connector_state = state->connector_states[i];
7837 if (connector_state->crtc != crtc_state->base.crtc)
7838 continue;
7839
7840 encoder = to_intel_encoder(connector_state->best_encoder);
7841
d9d444cb
JB		 7842 switch (encoder->type) {
7843 case INTEL_OUTPUT_LVDS:
7844 is_lvds = true;
7845 break;
6847d71b
PZ		 7846 default:
7847 break;
d9d444cb
JB		 7848 }
7849 num_connectors++;
7850 }
7851
7852 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7853 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7854 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7855 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7856 }
7857
7858 return 120000;
7859}
7860
6ff93609 7861static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7862{
c8203565 7863 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7865 int pipe = intel_crtc->pipe;
c8203565
PZ		 7866 uint32_t val;
7867
78114071 7868 val = 0;
c8203565 7869
6e3c9717 7870 switch (intel_crtc->config->pipe_bpp) {
c8203565 7871 case 18:
dfd07d72 7872 val |= PIPECONF_6BPC;
c8203565
PZ		 7873 break;
7874 case 24:
dfd07d72 7875 val |= PIPECONF_8BPC;
c8203565
PZ		 7876 break;
7877 case 30:
dfd07d72 7878 val |= PIPECONF_10BPC;
c8203565
PZ		 7879 break;
7880 case 36:
dfd07d72 7881 val |= PIPECONF_12BPC;
c8203565
PZ		 7882 break;
7883 default:
cc769b62
PZ		 7884 /* Case prevented by intel_choose_pipe_bpp_dither. */
7885 BUG();
c8203565
PZ		 7886 }
7887
6e3c9717 7888 if (intel_crtc->config->dither)
c8203565
PZ		 7889 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7890
6e3c9717 7891 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7892 val |= PIPECONF_INTERLACED_ILK;
7893 else
7894 val |= PIPECONF_PROGRESSIVE;
7895
6e3c9717 7896 if (intel_crtc->config->limited_color_range)
3685a8f3 7897 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7898
c8203565
PZ		 7899 I915_WRITE(PIPECONF(pipe), val);
7900 POSTING_READ(PIPECONF(pipe));
7901}
7902
86d3efce
VS		 7903/*
7904 * Set up the pipe CSC unit.
7905 *
7906 * Currently only full range RGB to limited range RGB conversion
7907 * is supported, but eventually this should handle various
7908 * RGB<->YCbCr scenarios as well.
7909 */
50f3b016 7910static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7911{
7912 struct drm_device *dev = crtc->dev;
7913 struct drm_i915_private *dev_priv = dev->dev_private;
7914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7915 int pipe = intel_crtc->pipe;
7916 uint16_t coeff = 0x7800; /* 1.0 */
7917
7918 /*
7919 * TODO: Check what kind of values actually come out of the pipe
7920 * with these coeff/postoff values and adjust to get the best
7921 * accuracy. Perhaps we even need to take the bpc value into
7922 * consideration.
7923 */
7924
6e3c9717 7925 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7926 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7927
7928 /*
7929 * GY/GU and RY/RU should be the other way around according
7930 * to BSpec, but reality doesn't agree. Just set them up in
7931 * a way that results in the correct picture.
7932 */
7933 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7934 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7935
7936 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7937 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7938
7939 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7940 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7941
7942 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7943 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7944 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7945
7946 if (INTEL_INFO(dev)->gen > 6) {
7947 uint16_t postoff = 0;
7948
6e3c9717 7949 if (intel_crtc->config->limited_color_range)
32cf0cb0 7950 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7951
7952 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7953 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7954 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7955
7956 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7957 } else {
7958 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7959
6e3c9717 7960 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7961 mode |= CSC_BLACK_SCREEN_OFFSET;
7962
7963 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7964 }
7965}
7966
6ff93609 7967static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7968{
756f85cf
PZ		 7969 struct drm_device *dev = crtc->dev;
7970 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7972 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7973 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7974 uint32_t val;
7975
3eff4faa 7976 val = 0;
ee2b0b38 7977
6e3c9717 7978 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7979 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7980
6e3c9717 7981 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7982 val |= PIPECONF_INTERLACED_ILK;
7983 else
7984 val |= PIPECONF_PROGRESSIVE;
7985
702e7a56
PZ		 7986 I915_WRITE(PIPECONF(cpu_transcoder), val);
7987 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7988
7989 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7990 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7991
3cdf122c 7992 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7993 val = 0;
7994
6e3c9717 7995 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7996 case 18:
7997 val |= PIPEMISC_DITHER_6_BPC;
7998 break;
7999 case 24:
8000 val |= PIPEMISC_DITHER_8_BPC;
8001 break;
8002 case 30:
8003 val |= PIPEMISC_DITHER_10_BPC;
8004 break;
8005 case 36:
8006 val |= PIPEMISC_DITHER_12_BPC;
8007 break;
8008 default:
8009 /* Case prevented by pipe_config_set_bpp. */
8010 BUG();
8011 }
8012
6e3c9717 8013 if (intel_crtc->config->dither)
756f85cf
PZ		 8014 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8015
8016 I915_WRITE(PIPEMISC(pipe), val);
8017 }
ee2b0b38
PZ		 8018}
8019
6591c6e4 8020static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8021 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8022 intel_clock_t *clock,
8023 bool *has_reduced_clock,
8024 intel_clock_t *reduced_clock)
8025{
8026 struct drm_device *dev = crtc->dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8028 int refclk;
d4906093 8029 const intel_limit_t *limit;
a16af721 8030 bool ret, is_lvds = false;
79e53945 8031
a93e255f 8032 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8033
55bb9992 8034 refclk = ironlake_get_refclk(crtc_state);
79e53945 8035
d4906093
ML		 8036 /*
8037 * Returns a set of divisors for the desired target clock with the given
8038 * refclk, or FALSE. The returned values represent the clock equation:
8039 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8040 */
a93e255f
ACO		 8041 limit = intel_limit(crtc_state, refclk);
8042 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8043 crtc_state->port_clock,
ee9300bb 8044 refclk, NULL, clock);
6591c6e4
PZ		 8045 if (!ret)
8046 return false;
cda4b7d3 8047
ddc9003c 8048 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8049 /*
8050 * Ensure we match the reduced clock's P to the target clock.
8051 * If the clocks don't match, we can't switch the display clock
8052 * by using the FP0/FP1. In such case we will disable the LVDS
8053 * downclock feature.
8054 */
ee9300bb 8055 *has_reduced_clock =
a93e255f 8056 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8057 dev_priv->lvds_downclock,
8058 refclk, clock,
8059 reduced_clock);
652c393a 8060 }
61e9653f 8061
6591c6e4
PZ		 8062 return true;
8063}
8064
d4b1931c
PZ		 8065int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8066{
8067 /*
8068 * Account for spread spectrum to avoid
8069 * oversubscribing the link. Max center spread
8070 * is 2.5%; use 5% for safety's sake.
8071 */
8072 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8073 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8074}
8075
7429e9d4 8076static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8077{
7429e9d4 8078 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8079}
8080
de13a2e3 8081static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8082 struct intel_crtc_state *crtc_state,
7429e9d4 8083 u32 *fp,
9a7c7890 8084 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8085{
de13a2e3 8086 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8087 struct drm_device *dev = crtc->dev;
8088 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8089 struct drm_atomic_state *state = crtc_state->base.state;
8090 struct drm_connector_state *connector_state;
8091 struct intel_encoder *encoder;
de13a2e3 8092 uint32_t dpll;
55bb9992 8093 int factor, num_connectors = 0, i;
09ede541 8094 bool is_lvds = false, is_sdvo = false;
79e53945 8095
55bb9992
ACO		 8096 for (i = 0; i < state->num_connector; i++) {
8097 if (!state->connectors[i])
d0737e1d
ACO		 8098 continue;
8099
55bb9992
ACO		 8100 connector_state = state->connector_states[i];
8101 if (connector_state->crtc != crtc_state->base.crtc)
8102 continue;
8103
8104 encoder = to_intel_encoder(connector_state->best_encoder);
8105
8106 switch (encoder->type) {
79e53945
JB		 8107 case INTEL_OUTPUT_LVDS:
8108 is_lvds = true;
8109 break;
8110 case INTEL_OUTPUT_SDVO:
7d57382e 8111 case INTEL_OUTPUT_HDMI:
79e53945 8112 is_sdvo = true;
79e53945 8113 break;
6847d71b
PZ		 8114 default:
8115 break;
79e53945 8116 }
43565a06 8117
c751ce4f 8118 num_connectors++;
79e53945 8119 }
79e53945 8120
c1858123 8121 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8122 factor = 21;
8123 if (is_lvds) {
8124 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8125 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8126 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8127 factor = 25;
190f68c5 8128 } else if (crtc_state->sdvo_tv_clock)
8febb297 8129 factor = 20;
c1858123 8130
190f68c5 8131 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8132 *fp |= FP_CB_TUNE;
2c07245f 8133
9a7c7890
DV		 8134 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8135 *fp2 |= FP_CB_TUNE;
8136
5eddb70b 8137 dpll = 0;
2c07245f 8138
a07d6787
EA		 8139 if (is_lvds)
8140 dpll |= DPLLB_MODE_LVDS;
8141 else
8142 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8143
190f68c5 8144 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8145 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8146
8147 if (is_sdvo)
4a33e48d 8148 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8149 if (crtc_state->has_dp_encoder)
4a33e48d 8150 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8151
a07d6787 8152 /* compute bitmask from p1 value */
190f68c5 8153 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8154 /* also FPA1 */
190f68c5 8155 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8156
190f68c5 8157 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8158 case 5:
8159 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8160 break;
8161 case 7:
8162 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8163 break;
8164 case 10:
8165 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8166 break;
8167 case 14:
8168 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8169 break;
79e53945
JB		 8170 }
8171
b4c09f3b 8172 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8173 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8174 else
8175 dpll |= PLL_REF_INPUT_DREFCLK;
8176
959e16d6 8177 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8178}
8179
190f68c5
ACO		 8180static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8181 struct intel_crtc_state *crtc_state)
de13a2e3 8182{
c7653199 8183 struct drm_device *dev = crtc->base.dev;
de13a2e3 8184 intel_clock_t clock, reduced_clock;
cbbab5bd 8185 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8186 bool ok, has_reduced_clock = false;
8b47047b 8187 bool is_lvds = false;
e2b78267 8188 struct intel_shared_dpll *pll;
de13a2e3 8189
409ee761 8190 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8191
5dc5298b
PZ		 8192 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8193 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8194
190f68c5 8195 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8196 &has_reduced_clock, &reduced_clock);
190f68c5 8197 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8198 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8199 return -EINVAL;
79e53945 8200 }
f47709a9 8201 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8202 if (!crtc_state->clock_set) {
8203 crtc_state->dpll.n = clock.n;
8204 crtc_state->dpll.m1 = clock.m1;
8205 crtc_state->dpll.m2 = clock.m2;
8206 crtc_state->dpll.p1 = clock.p1;
8207 crtc_state->dpll.p2 = clock.p2;
f47709a9 8208 }
79e53945 8209
5dc5298b 8210 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8211 if (crtc_state->has_pch_encoder) {
8212 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8213 if (has_reduced_clock)
7429e9d4 8214 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8215
190f68c5 8216 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8217 &fp, &reduced_clock,
8218 has_reduced_clock ? &fp2 : NULL);
8219
190f68c5
ACO		 8220 crtc_state->dpll_hw_state.dpll = dpll;
8221 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8222 if (has_reduced_clock)
190f68c5 8223 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8224 else
190f68c5 8225 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8226
190f68c5 8227 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8228 if (pll == NULL) {
84f44ce7 8229 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8230 pipe_name(crtc->pipe));
4b645f14
JB		 8231 return -EINVAL;
8232 }
3fb37703 8233 }
79e53945 8234
ab585dea 8235 if (is_lvds && has_reduced_clock)
c7653199 8236 crtc->lowfreq_avail = true;
bcd644e0 8237 else
c7653199 8238 crtc->lowfreq_avail = false;
e2b78267 8239
c8f7a0db 8240 return 0;
79e53945
JB		 8241}
8242
eb14cb74
VS		 8243static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8244 struct intel_link_m_n *m_n)
8245{
8246 struct drm_device *dev = crtc->base.dev;
8247 struct drm_i915_private *dev_priv = dev->dev_private;
8248 enum pipe pipe = crtc->pipe;
8249
8250 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8251 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8252 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8253 & ~TU_SIZE_MASK;
8254 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8255 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8256 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8257}
8258
8259static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8260 enum transcoder transcoder,
b95af8be
VK		 8261 struct intel_link_m_n *m_n,
8262 struct intel_link_m_n *m2_n2)
72419203
DV		 8263{
8264 struct drm_device *dev = crtc->base.dev;
8265 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8266 enum pipe pipe = crtc->pipe;
72419203 8267
eb14cb74
VS		 8268 if (INTEL_INFO(dev)->gen >= 5) {
8269 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8270 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8271 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8272 & ~TU_SIZE_MASK;
8273 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8274 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8275 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8276 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8277 * gen < 8) and if DRRS is supported (to make sure the
8278 * registers are not unnecessarily read).
8279 */
8280 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8281 crtc->config->has_drrs) {
b95af8be
VK		 8282 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8283 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8284 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8285 & ~TU_SIZE_MASK;
8286 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8287 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8288 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8289 }
eb14cb74
VS		 8290 } else {
8291 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8292 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8293 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8294 & ~TU_SIZE_MASK;
8295 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8296 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8297 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8298 }
8299}
8300
8301void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8302 struct intel_crtc_state *pipe_config)
eb14cb74 8303{
681a8504 8304 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8305 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8306 else
8307 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8308 &pipe_config->dp_m_n,
8309 &pipe_config->dp_m2_n2);
eb14cb74 8310}
72419203 8311
eb14cb74 8312static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8313 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8314{
8315 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8316 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8317}
8318
bd2e244f 8319static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8320 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8321{
8322 struct drm_device *dev = crtc->base.dev;
8323 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8324 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8325 uint32_t ps_ctrl = 0;
8326 int id = -1;
8327 int i;
bd2e244f 8328
a1b2278e
CK		 8329 /* find scaler attached to this pipe */
8330 for (i = 0; i < crtc->num_scalers; i++) {
8331 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8332 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8333 id = i;
8334 pipe_config->pch_pfit.enabled = true;
8335 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8336 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8337 break;
8338 }
8339 }
bd2e244f 8340
a1b2278e
CK		 8341 scaler_state->scaler_id = id;
8342 if (id >= 0) {
8343 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8344 } else {
8345 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8346 }
8347}
8348
5724dbd1
DL		 8349static void
8350skylake_get_initial_plane_config(struct intel_crtc *crtc,
8351 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8352{
8353 struct drm_device *dev = crtc->base.dev;
8354 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8355 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8356 int pipe = crtc->pipe;
8357 int fourcc, pixel_format;
6761dd31 8358 unsigned int aligned_height;
bc8d7dff 8359 struct drm_framebuffer *fb;
1b842c89 8360 struct intel_framebuffer *intel_fb;
bc8d7dff 8361
d9806c9f 8362 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8363 if (!intel_fb) {
bc8d7dff
DL		 8364 DRM_DEBUG_KMS("failed to alloc fb\n");
8365 return;
8366 }
8367
1b842c89
DL		 8368 fb = &intel_fb->base;
8369
bc8d7dff 8370 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8371 if (!(val & PLANE_CTL_ENABLE))
8372 goto error;
8373
bc8d7dff
DL		 8374 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8375 fourcc = skl_format_to_fourcc(pixel_format,
8376 val & PLANE_CTL_ORDER_RGBX,
8377 val & PLANE_CTL_ALPHA_MASK);
8378 fb->pixel_format = fourcc;
8379 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8380
40f46283
DL		 8381 tiling = val & PLANE_CTL_TILED_MASK;
8382 switch (tiling) {
8383 case PLANE_CTL_TILED_LINEAR:
8384 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8385 break;
8386 case PLANE_CTL_TILED_X:
8387 plane_config->tiling = I915_TILING_X;
8388 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8389 break;
8390 case PLANE_CTL_TILED_Y:
8391 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8392 break;
8393 case PLANE_CTL_TILED_YF:
8394 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8395 break;
8396 default:
8397 MISSING_CASE(tiling);
8398 goto error;
8399 }
8400
bc8d7dff
DL		 8401 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8402 plane_config->base = base;
8403
8404 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8405
8406 val = I915_READ(PLANE_SIZE(pipe, 0));
8407 fb->height = ((val >> 16) & 0xfff) + 1;
8408 fb->width = ((val >> 0) & 0x1fff) + 1;
8409
8410 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8411 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8412 fb->pixel_format);
bc8d7dff
DL		 8413 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8414
8415 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8416 fb->pixel_format,
8417 fb->modifier[0]);
bc8d7dff 8418
f37b5c2b 8419 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8420
8421 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8422 pipe_name(pipe), fb->width, fb->height,
8423 fb->bits_per_pixel, base, fb->pitches[0],
8424 plane_config->size);
8425
2d14030b 8426 plane_config->fb = intel_fb;
bc8d7dff
DL		 8427 return;
8428
8429error:
8430 kfree(fb);
8431}
8432
2fa2fe9a 8433static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8434 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8435{
8436 struct drm_device *dev = crtc->base.dev;
8437 struct drm_i915_private *dev_priv = dev->dev_private;
8438 uint32_t tmp;
8439
8440 tmp = I915_READ(PF_CTL(crtc->pipe));
8441
8442 if (tmp & PF_ENABLE) {
fd4daa9c 8443 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8444 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8445 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8446
8447 /* We currently do not free assignements of panel fitters on
8448 * ivb/hsw (since we don't use the higher upscaling modes which
8449 * differentiates them) so just WARN about this case for now. */
8450 if (IS_GEN7(dev)) {
8451 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8452 PF_PIPE_SEL_IVB(crtc->pipe));
8453 }
2fa2fe9a 8454 }
79e53945
JB		 8455}
8456
5724dbd1
DL		 8457static void
8458ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8459 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8460{
8461 struct drm_device *dev = crtc->base.dev;
8462 struct drm_i915_private *dev_priv = dev->dev_private;
8463 u32 val, base, offset;
aeee5a49 8464 int pipe = crtc->pipe;
4c6baa59 8465 int fourcc, pixel_format;
6761dd31 8466 unsigned int aligned_height;
b113d5ee 8467 struct drm_framebuffer *fb;
1b842c89 8468 struct intel_framebuffer *intel_fb;
4c6baa59 8469
42a7b088
DL		 8470 val = I915_READ(DSPCNTR(pipe));
8471 if (!(val & DISPLAY_PLANE_ENABLE))
8472 return;
8473
d9806c9f 8474 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8475 if (!intel_fb) {
4c6baa59
JB		 8476 DRM_DEBUG_KMS("failed to alloc fb\n");
8477 return;
8478 }
8479
1b842c89
DL		 8480 fb = &intel_fb->base;
8481
18c5247e
DV		 8482 if (INTEL_INFO(dev)->gen >= 4) {
8483 if (val & DISPPLANE_TILED) {
49af449b 8484 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8485 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8486 }
8487 }
4c6baa59
JB		 8488
8489 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8490 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8491 fb->pixel_format = fourcc;
8492 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8493
aeee5a49 8494 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8495 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8496 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8497 } else {
49af449b 8498 if (plane_config->tiling)
aeee5a49 8499 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8500 else
aeee5a49 8501 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8502 }
8503 plane_config->base = base;
8504
8505 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8506 fb->width = ((val >> 16) & 0xfff) + 1;
8507 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8508
8509 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8510 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8511
b113d5ee 8512 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8513 fb->pixel_format,
8514 fb->modifier[0]);
4c6baa59 8515
f37b5c2b 8516 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8517
2844a921
DL		 8518 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8519 pipe_name(pipe), fb->width, fb->height,
8520 fb->bits_per_pixel, base, fb->pitches[0],
8521 plane_config->size);
b113d5ee 8522
2d14030b 8523 plane_config->fb = intel_fb;
4c6baa59
JB		 8524}
8525
0e8ffe1b 8526static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8527 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8528{
8529 struct drm_device *dev = crtc->base.dev;
8530 struct drm_i915_private *dev_priv = dev->dev_private;
8531 uint32_t tmp;
8532
f458ebbc
DV		 8533 if (!intel_display_power_is_enabled(dev_priv,
8534 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8535 return false;
8536
e143a21c 8537 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8538 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8539
0e8ffe1b
DV		 8540 tmp = I915_READ(PIPECONF(crtc->pipe));
8541 if (!(tmp & PIPECONF_ENABLE))
8542 return false;
8543
42571aef
VS		 8544 switch (tmp & PIPECONF_BPC_MASK) {
8545 case PIPECONF_6BPC:
8546 pipe_config->pipe_bpp = 18;
8547 break;
8548 case PIPECONF_8BPC:
8549 pipe_config->pipe_bpp = 24;
8550 break;
8551 case PIPECONF_10BPC:
8552 pipe_config->pipe_bpp = 30;
8553 break;
8554 case PIPECONF_12BPC:
8555 pipe_config->pipe_bpp = 36;
8556 break;
8557 default:
8558 break;
8559 }
8560
b5a9fa09
DV		 8561 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8562 pipe_config->limited_color_range = true;
8563
ab9412ba 8564 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8565 struct intel_shared_dpll *pll;
8566
88adfff1
DV		 8567 pipe_config->has_pch_encoder = true;
8568
627eb5a3
DV		 8569 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8570 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8571 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8572
8573 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8574
c0d43d62 8575 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8576 pipe_config->shared_dpll =
8577 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8578 } else {
8579 tmp = I915_READ(PCH_DPLL_SEL);
8580 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8581 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8582 else
8583 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8584 }
66e985c0
DV		 8585
8586 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8587
8588 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8589 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8590
8591 tmp = pipe_config->dpll_hw_state.dpll;
8592 pipe_config->pixel_multiplier =
8593 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8594 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8595
8596 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8597 } else {
8598 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8599 }
8600
1bd1bd80
DV		 8601 intel_get_pipe_timings(crtc, pipe_config);
8602
2fa2fe9a
DV		 8603 ironlake_get_pfit_config(crtc, pipe_config);
8604
0e8ffe1b
DV		 8605 return true;
8606}
8607
be256dc7
PZ		 8608static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8609{
8610 struct drm_device *dev = dev_priv->dev;
be256dc7 8611 struct intel_crtc *crtc;
be256dc7 8612
d3fcc808 8613 for_each_intel_crtc(dev, crtc)
e2c719b7 8614 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8615 pipe_name(crtc->pipe));
8616
e2c719b7
RC		 8617 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8618 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8619 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8620 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8621 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8622 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8623 "CPU PWM1 enabled\n");
c5107b87 8624 if (IS_HASWELL(dev))
e2c719b7 8625 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8626 "CPU PWM2 enabled\n");
e2c719b7 8627 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8628 "PCH PWM1 enabled\n");
e2c719b7 8629 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8630 "Utility pin enabled\n");
e2c719b7 8631 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8632
9926ada1
PZ		 8633 /*
8634 * In theory we can still leave IRQs enabled, as long as only the HPD
8635 * interrupts remain enabled. We used to check for that, but since it's
8636 * gen-specific and since we only disable LCPLL after we fully disable
8637 * the interrupts, the check below should be enough.
8638 */
e2c719b7 8639 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8640}
8641
9ccd5aeb
PZ		 8642static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8643{
8644 struct drm_device *dev = dev_priv->dev;
8645
8646 if (IS_HASWELL(dev))
8647 return I915_READ(D_COMP_HSW);
8648 else
8649 return I915_READ(D_COMP_BDW);
8650}
8651
3c4c9b81
PZ		 8652static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8653{
8654 struct drm_device *dev = dev_priv->dev;
8655
8656 if (IS_HASWELL(dev)) {
8657 mutex_lock(&dev_priv->rps.hw_lock);
8658 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8659 val))
f475dadf 8660 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8661 mutex_unlock(&dev_priv->rps.hw_lock);
8662 } else {
9ccd5aeb
PZ		 8663 I915_WRITE(D_COMP_BDW, val);
8664 POSTING_READ(D_COMP_BDW);
3c4c9b81 8665 }
be256dc7
PZ		 8666}
8667
8668/*
8669 * This function implements pieces of two sequences from BSpec:
8670 * - Sequence for display software to disable LCPLL
8671 * - Sequence for display software to allow package C8+
8672 * The steps implemented here are just the steps that actually touch the LCPLL
8673 * register. Callers should take care of disabling all the display engine
8674 * functions, doing the mode unset, fixing interrupts, etc.
8675 */
6ff58d53
PZ		 8676static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8677 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8678{
8679 uint32_t val;
8680
8681 assert_can_disable_lcpll(dev_priv);
8682
8683 val = I915_READ(LCPLL_CTL);
8684
8685 if (switch_to_fclk) {
8686 val |= LCPLL_CD_SOURCE_FCLK;
8687 I915_WRITE(LCPLL_CTL, val);
8688
8689 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8690 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8691 DRM_ERROR("Switching to FCLK failed\n");
8692
8693 val = I915_READ(LCPLL_CTL);
8694 }
8695
8696 val |= LCPLL_PLL_DISABLE;
8697 I915_WRITE(LCPLL_CTL, val);
8698 POSTING_READ(LCPLL_CTL);
8699
8700 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8701 DRM_ERROR("LCPLL still locked\n");
8702
9ccd5aeb 8703 val = hsw_read_dcomp(dev_priv);
be256dc7 8704 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8705 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8706 ndelay(100);
8707
9ccd5aeb
PZ		 8708 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8709 1))
be256dc7
PZ		 8710 DRM_ERROR("D_COMP RCOMP still in progress\n");
8711
8712 if (allow_power_down) {
8713 val = I915_READ(LCPLL_CTL);
8714 val |= LCPLL_POWER_DOWN_ALLOW;
8715 I915_WRITE(LCPLL_CTL, val);
8716 POSTING_READ(LCPLL_CTL);
8717 }
8718}
8719
8720/*
8721 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8722 * source.
8723 */
6ff58d53 8724static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8725{
8726 uint32_t val;
8727
8728 val = I915_READ(LCPLL_CTL);
8729
8730 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8731 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8732 return;
8733
a8a8bd54
PZ		 8734 /*
8735 * Make sure we're not on PC8 state before disabling PC8, otherwise
8736 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8737 */
59bad947 8738 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8739
be256dc7
PZ		 8740 if (val & LCPLL_POWER_DOWN_ALLOW) {
8741 val &= ~LCPLL_POWER_DOWN_ALLOW;
8742 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8743 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8744 }
8745
9ccd5aeb 8746 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8747 val |= D_COMP_COMP_FORCE;
8748 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8749 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8750
8751 val = I915_READ(LCPLL_CTL);
8752 val &= ~LCPLL_PLL_DISABLE;
8753 I915_WRITE(LCPLL_CTL, val);
8754
8755 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8756 DRM_ERROR("LCPLL not locked yet\n");
8757
8758 if (val & LCPLL_CD_SOURCE_FCLK) {
8759 val = I915_READ(LCPLL_CTL);
8760 val &= ~LCPLL_CD_SOURCE_FCLK;
8761 I915_WRITE(LCPLL_CTL, val);
8762
8763 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8764 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8765 DRM_ERROR("Switching back to LCPLL failed\n");
8766 }
215733fa 8767
59bad947 8768 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8769}
8770
765dab67
PZ		 8771/*
8772 * Package states C8 and deeper are really deep PC states that can only be
8773 * reached when all the devices on the system allow it, so even if the graphics
8774 * device allows PC8+, it doesn't mean the system will actually get to these
8775 * states. Our driver only allows PC8+ when going into runtime PM.
8776 *
8777 * The requirements for PC8+ are that all the outputs are disabled, the power
8778 * well is disabled and most interrupts are disabled, and these are also
8779 * requirements for runtime PM. When these conditions are met, we manually do
8780 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8781 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8782 * hang the machine.
8783 *
8784 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8785 * the state of some registers, so when we come back from PC8+ we need to
8786 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8787 * need to take care of the registers kept by RC6. Notice that this happens even
8788 * if we don't put the device in PCI D3 state (which is what currently happens
8789 * because of the runtime PM support).
8790 *
8791 * For more, read "Display Sequences for Package C8" on the hardware
8792 * documentation.
8793 */
a14cb6fc 8794void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8795{
c67a470b
PZ		 8796 struct drm_device *dev = dev_priv->dev;
8797 uint32_t val;
8798
c67a470b
PZ		 8799 DRM_DEBUG_KMS("Enabling package C8+\n");
8800
c67a470b
PZ		 8801 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8802 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8803 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8804 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8805 }
8806
8807 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8808 hsw_disable_lcpll(dev_priv, true, true);
8809}
8810
a14cb6fc 8811void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8812{
8813 struct drm_device *dev = dev_priv->dev;
8814 uint32_t val;
8815
c67a470b
PZ		 8816 DRM_DEBUG_KMS("Disabling package C8+\n");
8817
8818 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8819 lpt_init_pch_refclk(dev);
8820
8821 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8822 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8823 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8824 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8825 }
8826
8827 intel_prepare_ddi(dev);
c67a470b
PZ		 8828}
8829
190f68c5
ACO		 8830static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8831 struct intel_crtc_state *crtc_state)
09b4ddf9 8832{
190f68c5 8833 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8834 return -EINVAL;
716c2e55 8835
c7653199 8836 crtc->lowfreq_avail = false;
644cef34 8837
c8f7a0db 8838 return 0;
79e53945
JB		 8839}
8840
96b7dfb7
S		 8841static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8842 enum port port,
5cec258b 8843 struct intel_crtc_state *pipe_config)
96b7dfb7 8844{
3148ade7 8845 u32 temp, dpll_ctl1;
96b7dfb7
S		 8846
8847 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8848 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8849
8850 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8851 case SKL_DPLL0:
8852 /*
8853 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8854 * of the shared DPLL framework and thus needs to be read out
8855 * separately
8856 */
8857 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8858 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8859 break;
96b7dfb7
S		 8860 case SKL_DPLL1:
8861 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8862 break;
8863 case SKL_DPLL2:
8864 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8865 break;
8866 case SKL_DPLL3:
8867 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8868 break;
96b7dfb7
S		 8869 }
8870}
8871
7d2c8175
DL		 8872static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8873 enum port port,
5cec258b 8874 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8875{
8876 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8877
8878 switch (pipe_config->ddi_pll_sel) {
8879 case PORT_CLK_SEL_WRPLL1:
8880 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8881 break;
8882 case PORT_CLK_SEL_WRPLL2:
8883 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8884 break;
8885 }
8886}
8887
26804afd 8888static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8889 struct intel_crtc_state *pipe_config)
26804afd
DV		 8890{
8891 struct drm_device *dev = crtc->base.dev;
8892 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8893 struct intel_shared_dpll *pll;
26804afd
DV		 8894 enum port port;
8895 uint32_t tmp;
8896
8897 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8898
8899 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8900
96b7dfb7
S		 8901 if (IS_SKYLAKE(dev))
8902 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8903 else
8904 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8905
d452c5b6
DV		 8906 if (pipe_config->shared_dpll >= 0) {
8907 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8908
8909 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8910 &pipe_config->dpll_hw_state));
8911 }
8912
26804afd
DV		 8913 /*
8914 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8915 * DDI E. So just check whether this pipe is wired to DDI E and whether
8916 * the PCH transcoder is on.
8917 */
ca370455
DL		 8918 if (INTEL_INFO(dev)->gen < 9 &&
8919 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8920 pipe_config->has_pch_encoder = true;
8921
8922 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8924 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8925
8926 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8927 }
8928}
8929
0e8ffe1b 8930static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8931 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8932{
8933 struct drm_device *dev = crtc->base.dev;
8934 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8935 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8936 uint32_t tmp;
8937
f458ebbc 8938 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8939 POWER_DOMAIN_PIPE(crtc->pipe)))
8940 return false;
8941
e143a21c 8942 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8943 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8944
eccb140b
DV		 8945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8946 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8947 enum pipe trans_edp_pipe;
8948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8949 default:
8950 WARN(1, "unknown pipe linked to edp transcoder\n");
8951 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8952 case TRANS_DDI_EDP_INPUT_A_ON:
8953 trans_edp_pipe = PIPE_A;
8954 break;
8955 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8956 trans_edp_pipe = PIPE_B;
8957 break;
8958 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8959 trans_edp_pipe = PIPE_C;
8960 break;
8961 }
8962
8963 if (trans_edp_pipe == crtc->pipe)
8964 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8965 }
8966
f458ebbc 8967 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8968 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8969 return false;
8970
eccb140b 8971 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8972 if (!(tmp & PIPECONF_ENABLE))
8973 return false;
8974
26804afd 8975 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8976
1bd1bd80
DV		 8977 intel_get_pipe_timings(crtc, pipe_config);
8978
a1b2278e
CK		 8979 if (INTEL_INFO(dev)->gen >= 9) {
8980 skl_init_scalers(dev, crtc, pipe_config);
8981 }
8982
2fa2fe9a 8983 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8984 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8985 if (IS_SKYLAKE(dev))
8986 skylake_get_pfit_config(crtc, pipe_config);
8987 else
8988 ironlake_get_pfit_config(crtc, pipe_config);
a1b2278e
CK		 8989 } else {
8990 pipe_config->scaler_state.scaler_id = -1;
8991 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 8992 }
88adfff1 8993
e59150dc
JB		 8994 if (IS_HASWELL(dev))
8995 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8996 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8997
ebb69c95
CT		 8998 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8999 pipe_config->pixel_multiplier =
9000 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9001 } else {
9002 pipe_config->pixel_multiplier = 1;
9003 }
6c49f241 9004
0e8ffe1b
DV		 9005 return true;
9006}
9007
560b85bb
CW		 9008static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9009{
9010 struct drm_device *dev = crtc->dev;
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9013 uint32_t cntl = 0, size = 0;
560b85bb 9014
dc41c154 9015 if (base) {
3dd512fb
MR		 9016 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9017 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9018 unsigned int stride = roundup_pow_of_two(width) * 4;
9019
9020 switch (stride) {
9021 default:
9022 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9023 width, stride);
9024 stride = 256;
9025 /* fallthrough */
9026 case 256:
9027 case 512:
9028 case 1024:
9029 case 2048:
9030 break;
4b0e333e
CW		 9031 }
9032
dc41c154
VS		 9033 cntl |= CURSOR_ENABLE |
9034 CURSOR_GAMMA_ENABLE |
9035 CURSOR_FORMAT_ARGB |
9036 CURSOR_STRIDE(stride);
9037
9038 size = (height << 12) | width;
4b0e333e 9039 }
560b85bb 9040
dc41c154
VS		 9041 if (intel_crtc->cursor_cntl != 0 &&
9042 (intel_crtc->cursor_base != base ||
9043 intel_crtc->cursor_size != size ||
9044 intel_crtc->cursor_cntl != cntl)) {
9045 /* On these chipsets we can only modify the base/size/stride
9046 * whilst the cursor is disabled.
9047 */
9048 I915_WRITE(_CURACNTR, 0);
4b0e333e 9049 POSTING_READ(_CURACNTR);
dc41c154 9050 intel_crtc->cursor_cntl = 0;
4b0e333e 9051 }
560b85bb 9052
99d1f387 9053 if (intel_crtc->cursor_base != base) {
9db4a9c7 9054 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9055 intel_crtc->cursor_base = base;
9056 }
4726e0b0 9057
dc41c154
VS		 9058 if (intel_crtc->cursor_size != size) {
9059 I915_WRITE(CURSIZE, size);
9060 intel_crtc->cursor_size = size;
4b0e333e 9061 }
560b85bb 9062
4b0e333e 9063 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9064 I915_WRITE(_CURACNTR, cntl);
9065 POSTING_READ(_CURACNTR);
4b0e333e 9066 intel_crtc->cursor_cntl = cntl;
560b85bb 9067 }
560b85bb
CW		 9068}
9069
560b85bb 9070static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9071{
9072 struct drm_device *dev = crtc->dev;
9073 struct drm_i915_private *dev_priv = dev->dev_private;
9074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9075 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9076 uint32_t cntl;
9077
9078 cntl = 0;
9079 if (base) {
9080 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9081 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9082 case 64:
9083 cntl |= CURSOR_MODE_64_ARGB_AX;
9084 break;
9085 case 128:
9086 cntl |= CURSOR_MODE_128_ARGB_AX;
9087 break;
9088 case 256:
9089 cntl |= CURSOR_MODE_256_ARGB_AX;
9090 break;
9091 default:
3dd512fb 9092 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9093 return;
65a21cd6 9094 }
4b0e333e 9095 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9096
9097 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9098 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9099 }
65a21cd6 9100
8e7d688b 9101 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9102 cntl |= CURSOR_ROTATE_180;
9103
4b0e333e
CW		 9104 if (intel_crtc->cursor_cntl != cntl) {
9105 I915_WRITE(CURCNTR(pipe), cntl);
9106 POSTING_READ(CURCNTR(pipe));
9107 intel_crtc->cursor_cntl = cntl;
65a21cd6 9108 }
4b0e333e 9109
65a21cd6 9110 /* and commit changes on next vblank */
5efb3e28
VS		 9111 I915_WRITE(CURBASE(pipe), base);
9112 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9113
9114 intel_crtc->cursor_base = base;
65a21cd6
JB		 9115}
9116
cda4b7d3 9117/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9118static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9119 bool on)
cda4b7d3
CW		 9120{
9121 struct drm_device *dev = crtc->dev;
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9124 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9125 int x = crtc->cursor_x;
9126 int y = crtc->cursor_y;
d6e4db15 9127 u32 base = 0, pos = 0;
cda4b7d3 9128
d6e4db15 9129 if (on)
cda4b7d3 9130 base = intel_crtc->cursor_addr;
cda4b7d3 9131
6e3c9717 9132 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9133 base = 0;
9134
6e3c9717 9135 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9136 base = 0;
9137
9138 if (x < 0) {
3dd512fb 9139 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9140 base = 0;
9141
9142 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9143 x = -x;
9144 }
9145 pos |= x << CURSOR_X_SHIFT;
9146
9147 if (y < 0) {
3dd512fb 9148 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9149 base = 0;
9150
9151 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9152 y = -y;
9153 }
9154 pos |= y << CURSOR_Y_SHIFT;
9155
4b0e333e 9156 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9157 return;
9158
5efb3e28
VS		 9159 I915_WRITE(CURPOS(pipe), pos);
9160
4398ad45
VS		 9161 /* ILK+ do this automagically */
9162 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9163 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9164 base += (intel_crtc->base.cursor->state->crtc_h *
9165 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9166 }
9167
8ac54669 9168 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9169 i845_update_cursor(crtc, base);
9170 else
9171 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9172}
9173
dc41c154
VS		 9174static bool cursor_size_ok(struct drm_device *dev,
9175 uint32_t width, uint32_t height)
9176{
9177 if (width == 0 || height == 0)
9178 return false;
9179
9180 /*
9181 * 845g/865g are special in that they are only limited by
9182 * the width of their cursors, the height is arbitrary up to
9183 * the precision of the register. Everything else requires
9184 * square cursors, limited to a few power-of-two sizes.
9185 */
9186 if (IS_845G(dev) || IS_I865G(dev)) {
9187 if ((width & 63) != 0)
9188 return false;
9189
9190 if (width > (IS_845G(dev) ? 64 : 512))
9191 return false;
9192
9193 if (height > 1023)
9194 return false;
9195 } else {
9196 switch (width | height) {
9197 case 256:
9198 case 128:
9199 if (IS_GEN2(dev))
9200 return false;
9201 case 64:
9202 break;
9203 default:
9204 return false;
9205 }
9206 }
9207
9208 return true;
9209}
9210
79e53945 9211static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9212 u16 *blue, uint32_t start, uint32_t size)
79e53945 9213{
7203425a 9214 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9216
7203425a 9217 for (i = start; i < end; i++) {
79e53945
JB		 9218 intel_crtc->lut_r[i] = red[i] >> 8;
9219 intel_crtc->lut_g[i] = green[i] >> 8;
9220 intel_crtc->lut_b[i] = blue[i] >> 8;
9221 }
9222
9223 intel_crtc_load_lut(crtc);
9224}
9225
79e53945
JB		 9226/* VESA 640x480x72Hz mode to set on the pipe */
9227static struct drm_display_mode load_detect_mode = {
9228 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9229 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9230};
9231
a8bb6818
DV		 9232struct drm_framebuffer *
9233__intel_framebuffer_create(struct drm_device *dev,
9234 struct drm_mode_fb_cmd2 *mode_cmd,
9235 struct drm_i915_gem_object *obj)
d2dff872
CW		 9236{
9237 struct intel_framebuffer *intel_fb;
9238 int ret;
9239
9240 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9241 if (!intel_fb) {
6ccb81f2 9242 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9243 return ERR_PTR(-ENOMEM);
9244 }
9245
9246 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9247 if (ret)
9248 goto err;
d2dff872
CW		 9249
9250 return &intel_fb->base;
dd4916c5 9251err:
6ccb81f2 9252 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9253 kfree(intel_fb);
9254
9255 return ERR_PTR(ret);
d2dff872
CW		 9256}
9257
b5ea642a 9258static struct drm_framebuffer *
a8bb6818
DV		 9259intel_framebuffer_create(struct drm_device *dev,
9260 struct drm_mode_fb_cmd2 *mode_cmd,
9261 struct drm_i915_gem_object *obj)
9262{
9263 struct drm_framebuffer *fb;
9264 int ret;
9265
9266 ret = i915_mutex_lock_interruptible(dev);
9267 if (ret)
9268 return ERR_PTR(ret);
9269 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9270 mutex_unlock(&dev->struct_mutex);
9271
9272 return fb;
9273}
9274
d2dff872
CW		 9275static u32
9276intel_framebuffer_pitch_for_width(int width, int bpp)
9277{
9278 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9279 return ALIGN(pitch, 64);
9280}
9281
9282static u32
9283intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9284{
9285 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9286 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9287}
9288
9289static struct drm_framebuffer *
9290intel_framebuffer_create_for_mode(struct drm_device *dev,
9291 struct drm_display_mode *mode,
9292 int depth, int bpp)
9293{
9294 struct drm_i915_gem_object *obj;
0fed39bd 9295 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9296
9297 obj = i915_gem_alloc_object(dev,
9298 intel_framebuffer_size_for_mode(mode, bpp));
9299 if (obj == NULL)
9300 return ERR_PTR(-ENOMEM);
9301
9302 mode_cmd.width = mode->hdisplay;
9303 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9304 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9305 bpp);
5ca0c34a 9306 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9307
9308 return intel_framebuffer_create(dev, &mode_cmd, obj);
9309}
9310
9311static struct drm_framebuffer *
9312mode_fits_in_fbdev(struct drm_device *dev,
9313 struct drm_display_mode *mode)
9314{
4520f53a 9315#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9316 struct drm_i915_private *dev_priv = dev->dev_private;
9317 struct drm_i915_gem_object *obj;
9318 struct drm_framebuffer *fb;
9319
4c0e5528 9320 if (!dev_priv->fbdev)
d2dff872
CW		 9321 return NULL;
9322
4c0e5528 9323 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9324 return NULL;
9325
4c0e5528
DV		 9326 obj = dev_priv->fbdev->fb->obj;
9327 BUG_ON(!obj);
9328
8bcd4553 9329 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9330 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9331 fb->bits_per_pixel))
d2dff872
CW		 9332 return NULL;
9333
01f2c773 9334 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9335 return NULL;
9336
9337 return fb;
4520f53a
DV		 9338#else
9339 return NULL;
9340#endif
d2dff872
CW		 9341}
9342
d2434ab7 9343bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9344 struct drm_display_mode *mode,
51fd371b
RC		 9345 struct intel_load_detect_pipe *old,
9346 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9347{
9348 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9349 struct intel_encoder *intel_encoder =
9350 intel_attached_encoder(connector);
79e53945 9351 struct drm_crtc *possible_crtc;
4ef69c7a 9352 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9353 struct drm_crtc *crtc = NULL;
9354 struct drm_device *dev = encoder->dev;
94352cf9 9355 struct drm_framebuffer *fb;
51fd371b 9356 struct drm_mode_config *config = &dev->mode_config;
83a57153 9357 struct drm_atomic_state *state = NULL;
944b0c76 9358 struct drm_connector_state *connector_state;
51fd371b 9359 int ret, i = -1;
79e53945 9360
d2dff872 9361 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9362 connector->base.id, connector->name,
8e329a03 9363 encoder->base.id, encoder->name);
d2dff872 9364
51fd371b
RC		 9365retry:
9366 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9367 if (ret)
9368 goto fail_unlock;
6e9f798d 9369
79e53945
JB		 9370 /*
9371 * Algorithm gets a little messy:
7a5e4805 9372 *
79e53945
JB		 9373 * - if the connector already has an assigned crtc, use it (but make
9374 * sure it's on first)
7a5e4805 9375 *
79e53945
JB		 9376 * - try to find the first unused crtc that can drive this connector,
9377 * and use that if we find one
79e53945
JB		 9378 */
9379
9380 /* See if we already have a CRTC for this connector */
9381 if (encoder->crtc) {
9382 crtc = encoder->crtc;
8261b191 9383
51fd371b 9384 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9385 if (ret)
9386 goto fail_unlock;
9387 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9388 if (ret)
9389 goto fail_unlock;
7b24056b 9390
24218aac 9391 old->dpms_mode = connector->dpms;
8261b191
CW		 9392 old->load_detect_temp = false;
9393
9394 /* Make sure the crtc and connector are running */
24218aac
DV		 9395 if (connector->dpms != DRM_MODE_DPMS_ON)
9396 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9397
7173188d 9398 return true;
79e53945
JB		 9399 }
9400
9401 /* Find an unused one (if possible) */
70e1e0ec 9402 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9403 i++;
9404 if (!(encoder->possible_crtcs & (1 << i)))
9405 continue;
83d65738 9406 if (possible_crtc->state->enable)
a459249c
VS		 9407 continue;
9408 /* This can occur when applying the pipe A quirk on resume. */
9409 if (to_intel_crtc(possible_crtc)->new_enabled)
9410 continue;
9411
9412 crtc = possible_crtc;
9413 break;
79e53945
JB		 9414 }
9415
9416 /*
9417 * If we didn't find an unused CRTC, don't use any.
9418 */
9419 if (!crtc) {
7173188d 9420 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9421 goto fail_unlock;
79e53945
JB		 9422 }
9423
51fd371b
RC		 9424 ret = drm_modeset_lock(&crtc->mutex, ctx);
9425 if (ret)
4d02e2de
DV		 9426 goto fail_unlock;
9427 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9428 if (ret)
51fd371b 9429 goto fail_unlock;
fc303101
DV		 9430 intel_encoder->new_crtc = to_intel_crtc(crtc);
9431 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9432
9433 intel_crtc = to_intel_crtc(crtc);
412b61d8 9434 intel_crtc->new_enabled = true;
24218aac 9435 old->dpms_mode = connector->dpms;
8261b191 9436 old->load_detect_temp = true;
d2dff872 9437 old->release_fb = NULL;
79e53945 9438
83a57153
ACO		 9439 state = drm_atomic_state_alloc(dev);
9440 if (!state)
9441 return false;
9442
9443 state->acquire_ctx = ctx;
9444
944b0c76
ACO		 9445 connector_state = drm_atomic_get_connector_state(state, connector);
9446 if (IS_ERR(connector_state)) {
9447 ret = PTR_ERR(connector_state);
9448 goto fail;
9449 }
9450
9451 connector_state->crtc = crtc;
9452 connector_state->best_encoder = &intel_encoder->base;
9453
6492711d
CW		 9454 if (!mode)
9455 mode = &load_detect_mode;
79e53945 9456
d2dff872
CW		 9457 /* We need a framebuffer large enough to accommodate all accesses
9458 * that the plane may generate whilst we perform load detection.
9459 * We can not rely on the fbcon either being present (we get called
9460 * during its initialisation to detect all boot displays, or it may
9461 * not even exist) or that it is large enough to satisfy the
9462 * requested mode.
9463 */
94352cf9
DV		 9464 fb = mode_fits_in_fbdev(dev, mode);
9465 if (fb == NULL) {
d2dff872 9466 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9467 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9468 old->release_fb = fb;
d2dff872
CW		 9469 } else
9470 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9471 if (IS_ERR(fb)) {
d2dff872 9472 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9473 goto fail;
79e53945 9474 }
79e53945 9475
83a57153 9476 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9477 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9478 if (old->release_fb)
9479 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9480 goto fail;
79e53945 9481 }
9128b040 9482 crtc->primary->crtc = crtc;
7173188d 9483
79e53945 9484 /* let the connector get through one full cycle before testing */
9d0498a2 9485 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9486 return true;
412b61d8
VS		 9487
9488 fail:
83d65738 9489 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9490fail_unlock:
83a57153
ACO		 9491 if (state) {
9492 drm_atomic_state_free(state);
9493 state = NULL;
9494 }
9495
51fd371b
RC		 9496 if (ret == -EDEADLK) {
9497 drm_modeset_backoff(ctx);
9498 goto retry;
9499 }
9500
412b61d8 9501 return false;
79e53945
JB		 9502}
9503
d2434ab7 9504void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9505 struct intel_load_detect_pipe *old,
9506 struct drm_modeset_acquire_ctx *ctx)
79e53945 9507{
83a57153 9508 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9509 struct intel_encoder *intel_encoder =
9510 intel_attached_encoder(connector);
4ef69c7a 9511 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9512 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9514 struct drm_atomic_state *state;
944b0c76 9515 struct drm_connector_state *connector_state;
79e53945 9516
d2dff872 9517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9518 connector->base.id, connector->name,
8e329a03 9519 encoder->base.id, encoder->name);
d2dff872 9520
8261b191 9521 if (old->load_detect_temp) {
83a57153 9522 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9523 if (!state)
9524 goto fail;
83a57153
ACO		 9525
9526 state->acquire_ctx = ctx;
9527
944b0c76
ACO		 9528 connector_state = drm_atomic_get_connector_state(state, connector);
9529 if (IS_ERR(connector_state))
9530 goto fail;
9531
fc303101
DV		 9532 to_intel_connector(connector)->new_encoder = NULL;
9533 intel_encoder->new_crtc = NULL;
412b61d8 9534 intel_crtc->new_enabled = false;
944b0c76
ACO		 9535
9536 connector_state->best_encoder = NULL;
9537 connector_state->crtc = NULL;
9538
83a57153
ACO		 9539 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9540
9541 drm_atomic_state_free(state);
d2dff872 9542
36206361
DV		 9543 if (old->release_fb) {
9544 drm_framebuffer_unregister_private(old->release_fb);
9545 drm_framebuffer_unreference(old->release_fb);
9546 }
d2dff872 9547
0622a53c 9548 return;
79e53945
JB		 9549 }
9550
c751ce4f 9551 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9552 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9553 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9554
9555 return;
9556fail:
9557 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9558 drm_atomic_state_free(state);
79e53945
JB		 9559}
9560
da4a1efa 9561static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9562 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9563{
9564 struct drm_i915_private *dev_priv = dev->dev_private;
9565 u32 dpll = pipe_config->dpll_hw_state.dpll;
9566
9567 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9568 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9569 else if (HAS_PCH_SPLIT(dev))
9570 return 120000;
9571 else if (!IS_GEN2(dev))
9572 return 96000;
9573 else
9574 return 48000;
9575}
9576
79e53945 9577/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9578static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9579 struct intel_crtc_state *pipe_config)
79e53945 9580{
f1f644dc 9581 struct drm_device *dev = crtc->base.dev;
79e53945 9582 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9583 int pipe = pipe_config->cpu_transcoder;
293623f7 9584 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9585 u32 fp;
9586 intel_clock_t clock;
da4a1efa 9587 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9588
9589 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9590 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9591 else
293623f7 9592 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9593
9594 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9595 if (IS_PINEVIEW(dev)) {
9596 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9597 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9598 } else {
9599 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9600 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9601 }
9602
a6c45cf0 9603 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9604 if (IS_PINEVIEW(dev))
9605 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9606 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9607 else
9608 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9609 DPLL_FPA01_P1_POST_DIV_SHIFT);
9610
9611 switch (dpll & DPLL_MODE_MASK) {
9612 case DPLLB_MODE_DAC_SERIAL:
9613 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9614 5 : 10;
9615 break;
9616 case DPLLB_MODE_LVDS:
9617 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9618 7 : 14;
9619 break;
9620 default:
28c97730 9621 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9622 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9623 return;
79e53945
JB		 9624 }
9625
ac58c3f0 9626 if (IS_PINEVIEW(dev))
da4a1efa 9627 pineview_clock(refclk, &clock);
ac58c3f0 9628 else
da4a1efa 9629 i9xx_clock(refclk, &clock);
79e53945 9630 } else {
0fb58223 9631 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9632 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9633
9634 if (is_lvds) {
9635 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9636 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9637
9638 if (lvds & LVDS_CLKB_POWER_UP)
9639 clock.p2 = 7;
9640 else
9641 clock.p2 = 14;
79e53945
JB		 9642 } else {
9643 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9644 clock.p1 = 2;
9645 else {
9646 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9647 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9648 }
9649 if (dpll & PLL_P2_DIVIDE_BY_4)
9650 clock.p2 = 4;
9651 else
9652 clock.p2 = 2;
79e53945 9653 }
da4a1efa
VS		 9654
9655 i9xx_clock(refclk, &clock);
79e53945
JB		 9656 }
9657
18442d08
VS		 9658 /*
9659 * This value includes pixel_multiplier. We will use
241bfc38 9660 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9661 * encoder's get_config() function.
9662 */
9663 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9664}
9665
6878da05
VS		 9666int intel_dotclock_calculate(int link_freq,
9667 const struct intel_link_m_n *m_n)
f1f644dc 9668{
f1f644dc
JB		 9669 /*
9670 * The calculation for the data clock is:
1041a02f 9671 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9672 * But we want to avoid losing precison if possible, so:
1041a02f 9673 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9674 *
9675 * and the link clock is simpler:
1041a02f 9676 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9677 */
9678
6878da05
VS		 9679 if (!m_n->link_n)
9680 return 0;
f1f644dc 9681
6878da05
VS		 9682 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9683}
f1f644dc 9684
18442d08 9685static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9686 struct intel_crtc_state *pipe_config)
6878da05
VS		 9687{
9688 struct drm_device *dev = crtc->base.dev;
79e53945 9689
18442d08
VS		 9690 /* read out port_clock from the DPLL */
9691 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9692
f1f644dc 9693 /*
18442d08 9694 * This value does not include pixel_multiplier.
241bfc38 9695 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9696 * agree once we know their relationship in the encoder's
9697 * get_config() function.
79e53945 9698 */
2d112de7 9699 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9700 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9701 &pipe_config->fdi_m_n);
79e53945
JB		 9702}
9703
9704/** Returns the currently programmed mode of the given pipe. */
9705struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9706 struct drm_crtc *crtc)
9707{
548f245b 9708 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9711 struct drm_display_mode *mode;
5cec258b 9712 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9713 int htot = I915_READ(HTOTAL(cpu_transcoder));
9714 int hsync = I915_READ(HSYNC(cpu_transcoder));
9715 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9716 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9717 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9718
9719 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9720 if (!mode)
9721 return NULL;
9722
f1f644dc
JB		 9723 /*
9724 * Construct a pipe_config sufficient for getting the clock info
9725 * back out of crtc_clock_get.
9726 *
9727 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9728 * to use a real value here instead.
9729 */
293623f7 9730 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9731 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9732 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9733 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9734 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9735 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9736
773ae034 9737 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9738 mode->hdisplay = (htot & 0xffff) + 1;
9739 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9740 mode->hsync_start = (hsync & 0xffff) + 1;
9741 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9742 mode->vdisplay = (vtot & 0xffff) + 1;
9743 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9744 mode->vsync_start = (vsync & 0xffff) + 1;
9745 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9746
9747 drm_mode_set_name(mode);
79e53945
JB		 9748
9749 return mode;
9750}
9751
652c393a
JB		 9752static void intel_decrease_pllclock(struct drm_crtc *crtc)
9753{
9754 struct drm_device *dev = crtc->dev;
fbee40df 9755 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9757
baff296c 9758 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9759 return;
9760
9761 if (!dev_priv->lvds_downclock_avail)
9762 return;
9763
9764 /*
9765 * Since this is called by a timer, we should never get here in
9766 * the manual case.
9767 */
9768 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9769 int pipe = intel_crtc->pipe;
9770 int dpll_reg = DPLL(pipe);
9771 int dpll;
f6e5b160 9772
44d98a61 9773 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9774
8ac5a6d5 9775 assert_panel_unlocked(dev_priv, pipe);
652c393a 9776
dc257cf1 9777 dpll = I915_READ(dpll_reg);
652c393a
JB		 9778 dpll |= DISPLAY_RATE_SELECT_FPA1;
9779 I915_WRITE(dpll_reg, dpll);
9d0498a2 9780 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9781 dpll = I915_READ(dpll_reg);
9782 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9783 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9784 }
9785
9786}
9787
f047e395
CW		 9788void intel_mark_busy(struct drm_device *dev)
9789{
c67a470b
PZ		 9790 struct drm_i915_private *dev_priv = dev->dev_private;
9791
f62a0076
CW		 9792 if (dev_priv->mm.busy)
9793 return;
9794
43694d69 9795 intel_runtime_pm_get(dev_priv);
c67a470b 9796 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9797 if (INTEL_INFO(dev)->gen >= 6)
9798 gen6_rps_busy(dev_priv);
f62a0076 9799 dev_priv->mm.busy = true;
f047e395
CW		 9800}
9801
9802void intel_mark_idle(struct drm_device *dev)
652c393a 9803{
c67a470b 9804 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9805 struct drm_crtc *crtc;
652c393a 9806
f62a0076
CW		 9807 if (!dev_priv->mm.busy)
9808 return;
9809
9810 dev_priv->mm.busy = false;
9811
70e1e0ec 9812 for_each_crtc(dev, crtc) {
f4510a27 9813 if (!crtc->primary->fb)
652c393a
JB		 9814 continue;
9815
725a5b54 9816 intel_decrease_pllclock(crtc);
652c393a 9817 }
b29c19b6 9818
3d13ef2e 9819 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9820 gen6_rps_idle(dev->dev_private);
bb4cdd53 9821
43694d69 9822 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9823}
9824
f5de6e07
ACO		 9825static void intel_crtc_set_state(struct intel_crtc *crtc,
9826 struct intel_crtc_state *crtc_state)
9827{
9828 kfree(crtc->config);
9829 crtc->config = crtc_state;
16f3f658 9830 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9831}
9832
79e53945
JB		 9833static void intel_crtc_destroy(struct drm_crtc *crtc)
9834{
9835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9836 struct drm_device *dev = crtc->dev;
9837 struct intel_unpin_work *work;
67e77c5a 9838
5e2d7afc 9839 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9840 work = intel_crtc->unpin_work;
9841 intel_crtc->unpin_work = NULL;
5e2d7afc 9842 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9843
9844 if (work) {
9845 cancel_work_sync(&work->work);
9846 kfree(work);
9847 }
79e53945 9848
f5de6e07 9849 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9850 drm_crtc_cleanup(crtc);
67e77c5a 9851
79e53945
JB		 9852 kfree(intel_crtc);
9853}
9854
6b95a207
KH		 9855static void intel_unpin_work_fn(struct work_struct *__work)
9856{
9857 struct intel_unpin_work *work =
9858 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9859 struct drm_device *dev = work->crtc->dev;
f99d7069 9860 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9861
b4a98e57 9862 mutex_lock(&dev->struct_mutex);
82bc3b2d 9863 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9864 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9865
7ff0ebcc 9866 intel_fbc_update(dev);
f06cc1b9
JH		 9867
9868 if (work->flip_queued_req)
146d84f0 9869 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9870 mutex_unlock(&dev->struct_mutex);
9871
f99d7069 9872 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9873 drm_framebuffer_unreference(work->old_fb);
f99d7069 9874
b4a98e57
CW		 9875 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9876 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9877
6b95a207
KH		 9878 kfree(work);
9879}
9880
1afe3e9d 9881static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9882 struct drm_crtc *crtc)
6b95a207 9883{
6b95a207
KH		 9884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9885 struct intel_unpin_work *work;
6b95a207
KH		 9886 unsigned long flags;
9887
9888 /* Ignore early vblank irqs */
9889 if (intel_crtc == NULL)
9890 return;
9891
f326038a
DV		 9892 /*
9893 * This is called both by irq handlers and the reset code (to complete
9894 * lost pageflips) so needs the full irqsave spinlocks.
9895 */
6b95a207
KH		 9896 spin_lock_irqsave(&dev->event_lock, flags);
9897 work = intel_crtc->unpin_work;
e7d841ca
CW		 9898
9899 /* Ensure we don't miss a work->pending update ... */
9900 smp_rmb();
9901
9902 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9903 spin_unlock_irqrestore(&dev->event_lock, flags);
9904 return;
9905 }
9906
d6bbafa1 9907 page_flip_completed(intel_crtc);
0af7e4df 9908
6b95a207 9909 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9910}
9911
1afe3e9d
JB		 9912void intel_finish_page_flip(struct drm_device *dev, int pipe)
9913{
fbee40df 9914 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9915 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9916
49b14a5c 9917 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9918}
9919
9920void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9921{
fbee40df 9922 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9923 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9924
49b14a5c 9925 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9926}
9927
75f7f3ec
VS		 9928/* Is 'a' after or equal to 'b'? */
9929static bool g4x_flip_count_after_eq(u32 a, u32 b)
9930{
9931 return !((a - b) & 0x80000000);
9932}
9933
9934static bool page_flip_finished(struct intel_crtc *crtc)
9935{
9936 struct drm_device *dev = crtc->base.dev;
9937 struct drm_i915_private *dev_priv = dev->dev_private;
9938
bdfa7542
VS		 9939 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9940 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9941 return true;
9942
75f7f3ec
VS		 9943 /*
9944 * The relevant registers doen't exist on pre-ctg.
9945 * As the flip done interrupt doesn't trigger for mmio
9946 * flips on gmch platforms, a flip count check isn't
9947 * really needed there. But since ctg has the registers,
9948 * include it in the check anyway.
9949 */
9950 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9951 return true;
9952
9953 /*
9954 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9955 * used the same base address. In that case the mmio flip might
9956 * have completed, but the CS hasn't even executed the flip yet.
9957 *
9958 * A flip count check isn't enough as the CS might have updated
9959 * the base address just after start of vblank, but before we
9960 * managed to process the interrupt. This means we'd complete the
9961 * CS flip too soon.
9962 *
9963 * Combining both checks should get us a good enough result. It may
9964 * still happen that the CS flip has been executed, but has not
9965 * yet actually completed. But in case the base address is the same
9966 * anyway, we don't really care.
9967 */
9968 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9969 crtc->unpin_work->gtt_offset &&
9970 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9971 crtc->unpin_work->flip_count);
9972}
9973
6b95a207
KH		 9974void intel_prepare_page_flip(struct drm_device *dev, int plane)
9975{
fbee40df 9976 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9977 struct intel_crtc *intel_crtc =
9978 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9979 unsigned long flags;
9980
f326038a
DV		 9981
9982 /*
9983 * This is called both by irq handlers and the reset code (to complete
9984 * lost pageflips) so needs the full irqsave spinlocks.
9985 *
9986 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9987 * generate a page-flip completion irq, i.e. every modeset
9988 * is also accompanied by a spurious intel_prepare_page_flip().
9989 */
6b95a207 9990 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9991 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9992 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9993 spin_unlock_irqrestore(&dev->event_lock, flags);
9994}
9995
eba905b2 9996static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9997{
9998 /* Ensure that the work item is consistent when activating it ... */
9999 smp_wmb();
10000 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10001 /* and that it is marked active as soon as the irq could fire. */
10002 smp_wmb();
10003}
10004
8c9f3aaf
JB		 10005static int intel_gen2_queue_flip(struct drm_device *dev,
10006 struct drm_crtc *crtc,
10007 struct drm_framebuffer *fb,
ed8d1975 10008 struct drm_i915_gem_object *obj,
a4872ba6 10009 struct intel_engine_cs *ring,
ed8d1975 10010 uint32_t flags)
8c9f3aaf 10011{
8c9f3aaf 10012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10013 u32 flip_mask;
10014 int ret;
10015
6d90c952 10016 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10017 if (ret)
4fa62c89 10018 return ret;
8c9f3aaf
JB		 10019
10020 /* Can't queue multiple flips, so wait for the previous
10021 * one to finish before executing the next.
10022 */
10023 if (intel_crtc->plane)
10024 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10025 else
10026 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10027 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10028 intel_ring_emit(ring, MI_NOOP);
10029 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10030 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10031 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10032 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10033 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10034
10035 intel_mark_page_flip_active(intel_crtc);
09246732 10036 __intel_ring_advance(ring);
83d4092b 10037 return 0;
8c9f3aaf
JB		 10038}
10039
10040static int intel_gen3_queue_flip(struct drm_device *dev,
10041 struct drm_crtc *crtc,
10042 struct drm_framebuffer *fb,
ed8d1975 10043 struct drm_i915_gem_object *obj,
a4872ba6 10044 struct intel_engine_cs *ring,
ed8d1975 10045 uint32_t flags)
8c9f3aaf 10046{
8c9f3aaf 10047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10048 u32 flip_mask;
10049 int ret;
10050
6d90c952 10051 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10052 if (ret)
4fa62c89 10053 return ret;
8c9f3aaf
JB		 10054
10055 if (intel_crtc->plane)
10056 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10057 else
10058 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10059 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10060 intel_ring_emit(ring, MI_NOOP);
10061 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10062 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10063 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10064 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10065 intel_ring_emit(ring, MI_NOOP);
10066
e7d841ca 10067 intel_mark_page_flip_active(intel_crtc);
09246732 10068 __intel_ring_advance(ring);
83d4092b 10069 return 0;
8c9f3aaf
JB		 10070}
10071
10072static int intel_gen4_queue_flip(struct drm_device *dev,
10073 struct drm_crtc *crtc,
10074 struct drm_framebuffer *fb,
ed8d1975 10075 struct drm_i915_gem_object *obj,
a4872ba6 10076 struct intel_engine_cs *ring,
ed8d1975 10077 uint32_t flags)
8c9f3aaf
JB		 10078{
10079 struct drm_i915_private *dev_priv = dev->dev_private;
10080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10081 uint32_t pf, pipesrc;
10082 int ret;
10083
6d90c952 10084 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10085 if (ret)
4fa62c89 10086 return ret;
8c9f3aaf
JB		 10087
10088 /* i965+ uses the linear or tiled offsets from the
10089 * Display Registers (which do not change across a page-flip)
10090 * so we need only reprogram the base address.
10091 */
6d90c952
DV		 10092 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10093 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10094 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10095 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10096 obj->tiling_mode);
8c9f3aaf
JB		 10097
10098 /* XXX Enabling the panel-fitter across page-flip is so far
10099 * untested on non-native modes, so ignore it for now.
10100 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10101 */
10102 pf = 0;
10103 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10104 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10105
10106 intel_mark_page_flip_active(intel_crtc);
09246732 10107 __intel_ring_advance(ring);
83d4092b 10108 return 0;
8c9f3aaf
JB		 10109}
10110
10111static int intel_gen6_queue_flip(struct drm_device *dev,
10112 struct drm_crtc *crtc,
10113 struct drm_framebuffer *fb,
ed8d1975 10114 struct drm_i915_gem_object *obj,
a4872ba6 10115 struct intel_engine_cs *ring,
ed8d1975 10116 uint32_t flags)
8c9f3aaf
JB		 10117{
10118 struct drm_i915_private *dev_priv = dev->dev_private;
10119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10120 uint32_t pf, pipesrc;
10121 int ret;
10122
6d90c952 10123 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10124 if (ret)
4fa62c89 10125 return ret;
8c9f3aaf 10126
6d90c952
DV		 10127 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10128 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10129 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10130 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10131
dc257cf1
DV		 10132 /* Contrary to the suggestions in the documentation,
10133 * "Enable Panel Fitter" does not seem to be required when page
10134 * flipping with a non-native mode, and worse causes a normal
10135 * modeset to fail.
10136 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10137 */
10138 pf = 0;
8c9f3aaf 10139 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10140 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10141
10142 intel_mark_page_flip_active(intel_crtc);
09246732 10143 __intel_ring_advance(ring);
83d4092b 10144 return 0;
8c9f3aaf
JB		 10145}
10146
7c9017e5
JB		 10147static int intel_gen7_queue_flip(struct drm_device *dev,
10148 struct drm_crtc *crtc,
10149 struct drm_framebuffer *fb,
ed8d1975 10150 struct drm_i915_gem_object *obj,
a4872ba6 10151 struct intel_engine_cs *ring,
ed8d1975 10152 uint32_t flags)
7c9017e5 10153{
7c9017e5 10154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10155 uint32_t plane_bit = 0;
ffe74d75
CW		 10156 int len, ret;
10157
eba905b2 10158 switch (intel_crtc->plane) {
cb05d8de
DV		 10159 case PLANE_A:
10160 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10161 break;
10162 case PLANE_B:
10163 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10164 break;
10165 case PLANE_C:
10166 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10167 break;
10168 default:
10169 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10170 return -ENODEV;
cb05d8de
DV		 10171 }
10172
ffe74d75 10173 len = 4;
f476828a 10174 if (ring->id == RCS) {
ffe74d75 10175 len += 6;
f476828a
DL		 10176 /*
10177 * On Gen 8, SRM is now taking an extra dword to accommodate
10178 * 48bits addresses, and we need a NOOP for the batch size to
10179 * stay even.
10180 */
10181 if (IS_GEN8(dev))
10182 len += 2;
10183 }
ffe74d75 10184
f66fab8e
VS		 10185 /*
10186 * BSpec MI_DISPLAY_FLIP for IVB:
10187 * "The full packet must be contained within the same cache line."
10188 *
10189 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10190 * cacheline, if we ever start emitting more commands before
10191 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10192 * then do the cacheline alignment, and finally emit the
10193 * MI_DISPLAY_FLIP.
10194 */
10195 ret = intel_ring_cacheline_align(ring);
10196 if (ret)
4fa62c89 10197 return ret;
f66fab8e 10198
ffe74d75 10199 ret = intel_ring_begin(ring, len);
7c9017e5 10200 if (ret)
4fa62c89 10201 return ret;
7c9017e5 10202
ffe74d75
CW		 10203 /* Unmask the flip-done completion message. Note that the bspec says that
10204 * we should do this for both the BCS and RCS, and that we must not unmask
10205 * more than one flip event at any time (or ensure that one flip message
10206 * can be sent by waiting for flip-done prior to queueing new flips).
10207 * Experimentation says that BCS works despite DERRMR masking all
10208 * flip-done completion events and that unmasking all planes at once
10209 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10210 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10211 */
10212 if (ring->id == RCS) {
10213 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10214 intel_ring_emit(ring, DERRMR);
10215 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10216 DERRMR_PIPEB_PRI_FLIP_DONE |
10217 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10218 if (IS_GEN8(dev))
10219 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10220 MI_SRM_LRM_GLOBAL_GTT);
10221 else
10222 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10223 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10224 intel_ring_emit(ring, DERRMR);
10225 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10226 if (IS_GEN8(dev)) {
10227 intel_ring_emit(ring, 0);
10228 intel_ring_emit(ring, MI_NOOP);
10229 }
ffe74d75
CW		 10230 }
10231
cb05d8de 10232 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10233 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10234 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10235 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10236
10237 intel_mark_page_flip_active(intel_crtc);
09246732 10238 __intel_ring_advance(ring);
83d4092b 10239 return 0;
7c9017e5
JB		 10240}
10241
84c33a64
SG		 10242static bool use_mmio_flip(struct intel_engine_cs *ring,
10243 struct drm_i915_gem_object *obj)
10244{
10245 /*
10246 * This is not being used for older platforms, because
10247 * non-availability of flip done interrupt forces us to use
10248 * CS flips. Older platforms derive flip done using some clever
10249 * tricks involving the flip_pending status bits and vblank irqs.
10250 * So using MMIO flips there would disrupt this mechanism.
10251 */
10252
8e09bf83
CW		 10253 if (ring == NULL)
10254 return true;
10255
84c33a64
SG		 10256 if (INTEL_INFO(ring->dev)->gen < 5)
10257 return false;
10258
10259 if (i915.use_mmio_flip < 0)
10260 return false;
10261 else if (i915.use_mmio_flip > 0)
10262 return true;
14bf993e
OM		 10263 else if (i915.enable_execlists)
10264 return true;
84c33a64 10265 else
41c52415 10266 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10267}
10268
ff944564
DL		 10269static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10270{
10271 struct drm_device *dev = intel_crtc->base.dev;
10272 struct drm_i915_private *dev_priv = dev->dev_private;
10273 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10274 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10275 struct drm_i915_gem_object *obj = intel_fb->obj;
10276 const enum pipe pipe = intel_crtc->pipe;
10277 u32 ctl, stride;
10278
10279 ctl = I915_READ(PLANE_CTL(pipe, 0));
10280 ctl &= ~PLANE_CTL_TILED_MASK;
10281 if (obj->tiling_mode == I915_TILING_X)
10282 ctl |= PLANE_CTL_TILED_X;
10283
10284 /*
10285 * The stride is either expressed as a multiple of 64 bytes chunks for
10286 * linear buffers or in number of tiles for tiled buffers.
10287 */
10288 stride = fb->pitches[0] >> 6;
10289 if (obj->tiling_mode == I915_TILING_X)
10290 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10291
10292 /*
10293 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10294 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10295 */
10296 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10297 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10298
10299 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10300 POSTING_READ(PLANE_SURF(pipe, 0));
10301}
10302
10303static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10304{
10305 struct drm_device *dev = intel_crtc->base.dev;
10306 struct drm_i915_private *dev_priv = dev->dev_private;
10307 struct intel_framebuffer *intel_fb =
10308 to_intel_framebuffer(intel_crtc->base.primary->fb);
10309 struct drm_i915_gem_object *obj = intel_fb->obj;
10310 u32 dspcntr;
10311 u32 reg;
10312
84c33a64
SG		 10313 reg = DSPCNTR(intel_crtc->plane);
10314 dspcntr = I915_READ(reg);
10315
c5d97472
DL		 10316 if (obj->tiling_mode != I915_TILING_NONE)
10317 dspcntr |= DISPPLANE_TILED;
10318 else
10319 dspcntr &= ~DISPPLANE_TILED;
10320
84c33a64
SG		 10321 I915_WRITE(reg, dspcntr);
10322
10323 I915_WRITE(DSPSURF(intel_crtc->plane),
10324 intel_crtc->unpin_work->gtt_offset);
10325 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10326
ff944564
DL		 10327}
10328
10329/*
10330 * XXX: This is the temporary way to update the plane registers until we get
10331 * around to using the usual plane update functions for MMIO flips
10332 */
10333static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10334{
10335 struct drm_device *dev = intel_crtc->base.dev;
10336 bool atomic_update;
10337 u32 start_vbl_count;
10338
10339 intel_mark_page_flip_active(intel_crtc);
10340
10341 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10342
10343 if (INTEL_INFO(dev)->gen >= 9)
10344 skl_do_mmio_flip(intel_crtc);
10345 else
10346 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10347 ilk_do_mmio_flip(intel_crtc);
10348
9362c7c5
ACO		 10349 if (atomic_update)
10350 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10351}
10352
9362c7c5 10353static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10354{
cc8c4cc2 10355 struct intel_crtc *crtc =
9362c7c5 10356 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10357 struct intel_mmio_flip *mmio_flip;
84c33a64 10358
cc8c4cc2
JH		 10359 mmio_flip = &crtc->mmio_flip;
10360 if (mmio_flip->req)
9c654818
JH		 10361 WARN_ON(__i915_wait_request(mmio_flip->req,
10362 crtc->reset_counter,
10363 false, NULL, NULL) != 0);
84c33a64 10364
cc8c4cc2
JH		 10365 intel_do_mmio_flip(crtc);
10366 if (mmio_flip->req) {
10367 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10368 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10369 mutex_unlock(&crtc->base.dev->struct_mutex);
10370 }
84c33a64
SG		 10371}
10372
10373static int intel_queue_mmio_flip(struct drm_device *dev,
10374 struct drm_crtc *crtc,
10375 struct drm_framebuffer *fb,
10376 struct drm_i915_gem_object *obj,
10377 struct intel_engine_cs *ring,
10378 uint32_t flags)
10379{
84c33a64 10380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10381
cc8c4cc2
JH		 10382 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10383 obj->last_write_req);
536f5b5e
ACO		 10384
10385 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10386
84c33a64
SG		 10387 return 0;
10388}
10389
8c9f3aaf
JB		 10390static int intel_default_queue_flip(struct drm_device *dev,
10391 struct drm_crtc *crtc,
10392 struct drm_framebuffer *fb,
ed8d1975 10393 struct drm_i915_gem_object *obj,
a4872ba6 10394 struct intel_engine_cs *ring,
ed8d1975 10395 uint32_t flags)
8c9f3aaf
JB		 10396{
10397 return -ENODEV;
10398}
10399
d6bbafa1
CW		 10400static bool __intel_pageflip_stall_check(struct drm_device *dev,
10401 struct drm_crtc *crtc)
10402{
10403 struct drm_i915_private *dev_priv = dev->dev_private;
10404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10405 struct intel_unpin_work *work = intel_crtc->unpin_work;
10406 u32 addr;
10407
10408 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10409 return true;
10410
10411 if (!work->enable_stall_check)
10412 return false;
10413
10414 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10415 if (work->flip_queued_req &&
10416 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10417 return false;
10418
1e3feefd 10419 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10420 }
10421
1e3feefd 10422 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10423 return false;
10424
10425 /* Potential stall - if we see that the flip has happened,
10426 * assume a missed interrupt. */
10427 if (INTEL_INFO(dev)->gen >= 4)
10428 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10429 else
10430 addr = I915_READ(DSPADDR(intel_crtc->plane));
10431
10432 /* There is a potential issue here with a false positive after a flip
10433 * to the same address. We could address this by checking for a
10434 * non-incrementing frame counter.
10435 */
10436 return addr == work->gtt_offset;
10437}
10438
10439void intel_check_page_flip(struct drm_device *dev, int pipe)
10440{
10441 struct drm_i915_private *dev_priv = dev->dev_private;
10442 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10444 struct intel_unpin_work *work;
f326038a 10445
6c51d46f 10446 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10447
10448 if (crtc == NULL)
10449 return;
10450
f326038a 10451 spin_lock(&dev->event_lock);
6ad790c0
CW		 10452 work = intel_crtc->unpin_work;
10453 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10454 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10455 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10456 page_flip_completed(intel_crtc);
6ad790c0 10457 work = NULL;
d6bbafa1 10458 }
6ad790c0
CW		 10459 if (work != NULL &&
10460 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10461 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10462 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10463}
10464
6b95a207
KH		 10465static int intel_crtc_page_flip(struct drm_crtc *crtc,
10466 struct drm_framebuffer *fb,
ed8d1975
KP		 10467 struct drm_pending_vblank_event *event,
10468 uint32_t page_flip_flags)
6b95a207
KH		 10469{
10470 struct drm_device *dev = crtc->dev;
10471 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10472 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10473 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10475 struct drm_plane *primary = crtc->primary;
a071fa00 10476 enum pipe pipe = intel_crtc->pipe;
6b95a207 10477 struct intel_unpin_work *work;
a4872ba6 10478 struct intel_engine_cs *ring;
cf5d8a46 10479 bool mmio_flip;
52e68630 10480 int ret;
6b95a207 10481
2ff8fde1
MR		 10482 /*
10483 * drm_mode_page_flip_ioctl() should already catch this, but double
10484 * check to be safe. In the future we may enable pageflipping from
10485 * a disabled primary plane.
10486 */
10487 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10488 return -EBUSY;
10489
e6a595d2 10490 /* Can't change pixel format via MI display flips. */
f4510a27 10491 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10492 return -EINVAL;
10493
10494 /*
10495 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10496 * Note that pitch changes could also affect these register.
10497 */
10498 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10499 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10500 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10501 return -EINVAL;
10502
f900db47
CW		 10503 if (i915_terminally_wedged(&dev_priv->gpu_error))
10504 goto out_hang;
10505
b14c5679 10506 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10507 if (work == NULL)
10508 return -ENOMEM;
10509
6b95a207 10510 work->event = event;
b4a98e57 10511 work->crtc = crtc;
ab8d6675 10512 work->old_fb = old_fb;
6b95a207
KH		 10513 INIT_WORK(&work->work, intel_unpin_work_fn);
10514
87b6b101 10515 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10516 if (ret)
10517 goto free_work;
10518
6b95a207 10519 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10520 spin_lock_irq(&dev->event_lock);
6b95a207 10521 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10522 /* Before declaring the flip queue wedged, check if
10523 * the hardware completed the operation behind our backs.
10524 */
10525 if (__intel_pageflip_stall_check(dev, crtc)) {
10526 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10527 page_flip_completed(intel_crtc);
10528 } else {
10529 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10530 spin_unlock_irq(&dev->event_lock);
468f0b44 10531
d6bbafa1
CW		 10532 drm_crtc_vblank_put(crtc);
10533 kfree(work);
10534 return -EBUSY;
10535 }
6b95a207
KH		 10536 }
10537 intel_crtc->unpin_work = work;
5e2d7afc 10538 spin_unlock_irq(&dev->event_lock);
6b95a207 10539
b4a98e57
CW		 10540 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10541 flush_workqueue(dev_priv->wq);
10542
75dfca80 10543 /* Reference the objects for the scheduled work. */
ab8d6675 10544 drm_framebuffer_reference(work->old_fb);
05394f39 10545 drm_gem_object_reference(&obj->base);
6b95a207 10546
f4510a27 10547 crtc->primary->fb = fb;
afd65eb4 10548 update_state_fb(crtc->primary);
1ed1f968 10549
e1f99ce6 10550 work->pending_flip_obj = obj;
e1f99ce6 10551
89ed88ba
CW		 10552 ret = i915_mutex_lock_interruptible(dev);
10553 if (ret)
10554 goto cleanup;
10555
b4a98e57 10556 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10557 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10558
75f7f3ec 10559 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10560 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10561
4fa62c89
VS		 10562 if (IS_VALLEYVIEW(dev)) {
10563 ring = &dev_priv->ring[BCS];
ab8d6675 10564 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10565 /* vlv: DISPLAY_FLIP fails to change tiling */
10566 ring = NULL;
48bf5b2d 10567 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10568 ring = &dev_priv->ring[BCS];
4fa62c89 10569 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10570 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10571 if (ring == NULL || ring->id != RCS)
10572 ring = &dev_priv->ring[BCS];
10573 } else {
10574 ring = &dev_priv->ring[RCS];
10575 }
10576
cf5d8a46
CW		 10577 mmio_flip = use_mmio_flip(ring, obj);
10578
10579 /* When using CS flips, we want to emit semaphores between rings.
10580 * However, when using mmio flips we will create a task to do the
10581 * synchronisation, so all we want here is to pin the framebuffer
10582 * into the display plane and skip any waits.
10583 */
82bc3b2d 10584 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10585 crtc->primary->state,
10586 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10587 if (ret)
10588 goto cleanup_pending;
6b95a207 10589
121920fa
TU		 10590 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10591 + intel_crtc->dspaddr_offset;
4fa62c89 10592
cf5d8a46 10593 if (mmio_flip) {
84c33a64
SG		 10594 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10595 page_flip_flags);
d6bbafa1
CW		 10596 if (ret)
10597 goto cleanup_unpin;
10598
f06cc1b9
JH		 10599 i915_gem_request_assign(&work->flip_queued_req,
10600 obj->last_write_req);
d6bbafa1 10601 } else {
84c33a64 10602 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10603 page_flip_flags);
10604 if (ret)
10605 goto cleanup_unpin;
10606
f06cc1b9
JH		 10607 i915_gem_request_assign(&work->flip_queued_req,
10608 intel_ring_get_request(ring));
d6bbafa1
CW		 10609 }
10610
1e3feefd 10611 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10612 work->enable_stall_check = true;
4fa62c89 10613
ab8d6675 10614 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10615 INTEL_FRONTBUFFER_PRIMARY(pipe));
10616
7ff0ebcc 10617 intel_fbc_disable(dev);
f99d7069 10618 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10619 mutex_unlock(&dev->struct_mutex);
10620
e5510fac
JB		 10621 trace_i915_flip_request(intel_crtc->plane, obj);
10622
6b95a207 10623 return 0;
96b099fd 10624
4fa62c89 10625cleanup_unpin:
82bc3b2d 10626 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10627cleanup_pending:
b4a98e57 10628 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10629 mutex_unlock(&dev->struct_mutex);
10630cleanup:
f4510a27 10631 crtc->primary->fb = old_fb;
afd65eb4 10632 update_state_fb(crtc->primary);
89ed88ba
CW		 10633
10634 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10635 drm_framebuffer_unreference(work->old_fb);
96b099fd 10636
5e2d7afc 10637 spin_lock_irq(&dev->event_lock);
96b099fd 10638 intel_crtc->unpin_work = NULL;
5e2d7afc 10639 spin_unlock_irq(&dev->event_lock);
96b099fd 10640
87b6b101 10641 drm_crtc_vblank_put(crtc);
7317c75e 10642free_work:
96b099fd
CW		 10643 kfree(work);
10644
f900db47
CW		 10645 if (ret == -EIO) {
10646out_hang:
53a366b9 10647 ret = intel_plane_restore(primary);
f0d3dad3 10648 if (ret == 0 && event) {
5e2d7afc 10649 spin_lock_irq(&dev->event_lock);
a071fa00 10650 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10651 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10652 }
f900db47 10653 }
96b099fd 10654 return ret;
6b95a207
KH		 10655}
10656
f6e5b160 10657static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10658 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10659 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10660 .atomic_begin = intel_begin_crtc_commit,
10661 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10662};
10663
9a935856
DV		 10664/**
10665 * intel_modeset_update_staged_output_state
10666 *
10667 * Updates the staged output configuration state, e.g. after we've read out the
10668 * current hw state.
10669 */
10670static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10671{
7668851f 10672 struct intel_crtc *crtc;
9a935856
DV		 10673 struct intel_encoder *encoder;
10674 struct intel_connector *connector;
f6e5b160 10675
3a3371ff 10676 for_each_intel_connector(dev, connector) {
9a935856
DV		 10677 connector->new_encoder =
10678 to_intel_encoder(connector->base.encoder);
10679 }
f6e5b160 10680
b2784e15 10681 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10682 encoder->new_crtc =
10683 to_intel_crtc(encoder->base.crtc);
10684 }
7668851f 10685
d3fcc808 10686 for_each_intel_crtc(dev, crtc) {
83d65738 10687 crtc->new_enabled = crtc->base.state->enable;
7668851f 10688 }
f6e5b160
CW		 10689}
10690
d29b2f9d
ACO		 10691/* Transitional helper to copy current connector/encoder state to
10692 * connector->state. This is needed so that code that is partially
10693 * converted to atomic does the right thing.
10694 */
10695static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10696{
10697 struct intel_connector *connector;
10698
10699 for_each_intel_connector(dev, connector) {
10700 if (connector->base.encoder) {
10701 connector->base.state->best_encoder =
10702 connector->base.encoder;
10703 connector->base.state->crtc =
10704 connector->base.encoder->crtc;
10705 } else {
10706 connector->base.state->best_encoder = NULL;
10707 connector->base.state->crtc = NULL;
10708 }
10709 }
10710}
10711
9a935856
DV		 10712/**
10713 * intel_modeset_commit_output_state
10714 *
10715 * This function copies the stage display pipe configuration to the real one.
10716 */
10717static void intel_modeset_commit_output_state(struct drm_device *dev)
10718{
7668851f 10719 struct intel_crtc *crtc;
9a935856
DV		 10720 struct intel_encoder *encoder;
10721 struct intel_connector *connector;
f6e5b160 10722
3a3371ff 10723 for_each_intel_connector(dev, connector) {
9a935856
DV		 10724 connector->base.encoder = &connector->new_encoder->base;
10725 }
f6e5b160 10726
b2784e15 10727 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10728 encoder->base.crtc = &encoder->new_crtc->base;
10729 }
7668851f 10730
d3fcc808 10731 for_each_intel_crtc(dev, crtc) {
83d65738 10732 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10733 crtc->base.enabled = crtc->new_enabled;
10734 }
d29b2f9d
ACO		 10735
10736 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10737}
10738
050f7aeb 10739static void
eba905b2 10740connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10741 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10742{
10743 int bpp = pipe_config->pipe_bpp;
10744
10745 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10746 connector->base.base.id,
c23cc417 10747 connector->base.name);
050f7aeb
DV		 10748
10749 /* Don't use an invalid EDID bpc value */
10750 if (connector->base.display_info.bpc &&
10751 connector->base.display_info.bpc * 3 < bpp) {
10752 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10753 bpp, connector->base.display_info.bpc*3);
10754 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10755 }
10756
10757 /* Clamp bpp to 8 on screens without EDID 1.4 */
10758 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10759 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10760 bpp);
10761 pipe_config->pipe_bpp = 24;
10762 }
10763}
10764
4e53c2e0 10765static int
050f7aeb
DV		 10766compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10767 struct drm_framebuffer *fb,
5cec258b 10768 struct intel_crtc_state *pipe_config)
4e53c2e0 10769{
050f7aeb 10770 struct drm_device *dev = crtc->base.dev;
1486017f 10771 struct drm_atomic_state *state;
050f7aeb 10772 struct intel_connector *connector;
1486017f 10773 int bpp, i;
4e53c2e0 10774
d42264b1
DV		 10775 switch (fb->pixel_format) {
10776 case DRM_FORMAT_C8:
4e53c2e0
DV		 10777 bpp = 8*3; /* since we go through a colormap */
10778 break;
d42264b1
DV		 10779 case DRM_FORMAT_XRGB1555:
10780 case DRM_FORMAT_ARGB1555:
10781 /* checked in intel_framebuffer_init already */
10782 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10783 return -EINVAL;
10784 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10785 bpp = 6*3; /* min is 18bpp */
10786 break;
d42264b1
DV		 10787 case DRM_FORMAT_XBGR8888:
10788 case DRM_FORMAT_ABGR8888:
10789 /* checked in intel_framebuffer_init already */
10790 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10791 return -EINVAL;
10792 case DRM_FORMAT_XRGB8888:
10793 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10794 bpp = 8*3;
10795 break;
d42264b1
DV		 10796 case DRM_FORMAT_XRGB2101010:
10797 case DRM_FORMAT_ARGB2101010:
10798 case DRM_FORMAT_XBGR2101010:
10799 case DRM_FORMAT_ABGR2101010:
10800 /* checked in intel_framebuffer_init already */
10801 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10802 return -EINVAL;
4e53c2e0
DV		 10803 bpp = 10*3;
10804 break;
baba133a 10805 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10806 default:
10807 DRM_DEBUG_KMS("unsupported depth\n");
10808 return -EINVAL;
10809 }
10810
4e53c2e0
DV		 10811 pipe_config->pipe_bpp = bpp;
10812
1486017f
ACO		 10813 state = pipe_config->base.state;
10814
4e53c2e0 10815 /* Clamp display bpp to EDID value */
1486017f
ACO		 10816 for (i = 0; i < state->num_connector; i++) {
10817 if (!state->connectors[i])
10818 continue;
10819
10820 connector = to_intel_connector(state->connectors[i]);
10821 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 10822 continue;
10823
050f7aeb 10824 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10825 }
10826
10827 return bpp;
10828}
10829
644db711
DV		 10830static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10831{
10832 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10833 "type: 0x%x flags: 0x%x\n",
1342830c 10834 mode->crtc_clock,
644db711
DV		 10835 mode->crtc_hdisplay, mode->crtc_hsync_start,
10836 mode->crtc_hsync_end, mode->crtc_htotal,
10837 mode->crtc_vdisplay, mode->crtc_vsync_start,
10838 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10839}
10840
c0b03411 10841static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10842 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10843 const char *context)
10844{
6a60cd87
CK		 10845 struct drm_device *dev = crtc->base.dev;
10846 struct drm_plane *plane;
10847 struct intel_plane *intel_plane;
10848 struct intel_plane_state *state;
10849 struct drm_framebuffer *fb;
10850
10851 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
10852 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 10853
10854 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10855 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10856 pipe_config->pipe_bpp, pipe_config->dither);
10857 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10858 pipe_config->has_pch_encoder,
10859 pipe_config->fdi_lanes,
10860 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10861 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10862 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10863 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10864 pipe_config->has_dp_encoder,
10865 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10866 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10867 pipe_config->dp_m_n.tu);
b95af8be
VK		 10868
10869 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10870 pipe_config->has_dp_encoder,
10871 pipe_config->dp_m2_n2.gmch_m,
10872 pipe_config->dp_m2_n2.gmch_n,
10873 pipe_config->dp_m2_n2.link_m,
10874 pipe_config->dp_m2_n2.link_n,
10875 pipe_config->dp_m2_n2.tu);
10876
55072d19
DV		 10877 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10878 pipe_config->has_audio,
10879 pipe_config->has_infoframe);
10880
c0b03411 10881 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10882 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10883 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10884 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10885 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10886 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10887 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10888 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 10889 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
10890 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
10891 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 10892 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10893 pipe_config->gmch_pfit.control,
10894 pipe_config->gmch_pfit.pgm_ratios,
10895 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10896 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10897 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10898 pipe_config->pch_pfit.size,
10899 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10900 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10901 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 10902
10903 DRM_DEBUG_KMS("planes on this crtc\n");
10904 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
10905 intel_plane = to_intel_plane(plane);
10906 if (intel_plane->pipe != crtc->pipe)
10907 continue;
10908
10909 state = to_intel_plane_state(plane->state);
10910 fb = state->base.fb;
10911 if (!fb) {
10912 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
10913 "disabled, scaler_id = %d\n",
10914 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
10915 plane->base.id, intel_plane->pipe,
10916 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
10917 drm_plane_index(plane), state->scaler_id);
10918 continue;
10919 }
10920
10921 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
10922 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
10923 plane->base.id, intel_plane->pipe,
10924 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
10925 drm_plane_index(plane));
10926 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
10927 fb->base.id, fb->width, fb->height, fb->pixel_format);
10928 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
10929 state->scaler_id,
10930 state->src.x1 >> 16, state->src.y1 >> 16,
10931 drm_rect_width(&state->src) >> 16,
10932 drm_rect_height(&state->src) >> 16,
10933 state->dst.x1, state->dst.y1,
10934 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
10935 }
c0b03411
DV		 10936}
10937
bc079e8b
VS		 10938static bool encoders_cloneable(const struct intel_encoder *a,
10939 const struct intel_encoder *b)
accfc0c5 10940{
bc079e8b
VS		 10941 /* masks could be asymmetric, so check both ways */
10942 return a == b || (a->cloneable & (1 << b->type) &&
10943 b->cloneable & (1 << a->type));
10944}
10945
98a221da
ACO		 10946static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10947 struct intel_crtc *crtc,
bc079e8b
VS		 10948 struct intel_encoder *encoder)
10949{
bc079e8b 10950 struct intel_encoder *source_encoder;
98a221da
ACO		 10951 struct drm_connector_state *connector_state;
10952 int i;
10953
10954 for (i = 0; i < state->num_connector; i++) {
10955 if (!state->connectors[i])
10956 continue;
bc079e8b 10957
98a221da
ACO		 10958 connector_state = state->connector_states[i];
10959 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 10960 continue;
10961
98a221da
ACO		 10962 source_encoder =
10963 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 10964 if (!encoders_cloneable(encoder, source_encoder))
10965 return false;
10966 }
10967
10968 return true;
10969}
10970
98a221da
ACO		 10971static bool check_encoder_cloning(struct drm_atomic_state *state,
10972 struct intel_crtc *crtc)
bc079e8b 10973{
accfc0c5 10974 struct intel_encoder *encoder;
98a221da
ACO		 10975 struct drm_connector_state *connector_state;
10976 int i;
accfc0c5 10977
98a221da
ACO		 10978 for (i = 0; i < state->num_connector; i++) {
10979 if (!state->connectors[i])
accfc0c5
DV		 10980 continue;
10981
98a221da
ACO		 10982 connector_state = state->connector_states[i];
10983 if (connector_state->crtc != &crtc->base)
10984 continue;
10985
10986 encoder = to_intel_encoder(connector_state->best_encoder);
10987 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 10988 return false;
accfc0c5
DV		 10989 }
10990
bc079e8b 10991 return true;
accfc0c5
DV		 10992}
10993
5448a00d 10994static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 10995{
5448a00d
ACO		 10996 struct drm_device *dev = state->dev;
10997 struct intel_encoder *encoder;
10998 struct drm_connector_state *connector_state;
00f0b378 10999 unsigned int used_ports = 0;
5448a00d 11000 int i;
00f0b378
VS		 11001
11002 /*
11003 * Walk the connector list instead of the encoder
11004 * list to detect the problem on ddi platforms
11005 * where there's just one encoder per digital port.
11006 */
5448a00d
ACO		 11007 for (i = 0; i < state->num_connector; i++) {
11008 if (!state->connectors[i])
11009 continue;
00f0b378 11010
5448a00d
ACO		 11011 connector_state = state->connector_states[i];
11012 if (!connector_state->best_encoder)
00f0b378
VS		 11013 continue;
11014
5448a00d
ACO		 11015 encoder = to_intel_encoder(connector_state->best_encoder);
11016
11017 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11018
11019 switch (encoder->type) {
11020 unsigned int port_mask;
11021 case INTEL_OUTPUT_UNKNOWN:
11022 if (WARN_ON(!HAS_DDI(dev)))
11023 break;
11024 case INTEL_OUTPUT_DISPLAYPORT:
11025 case INTEL_OUTPUT_HDMI:
11026 case INTEL_OUTPUT_EDP:
11027 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11028
11029 /* the same port mustn't appear more than once */
11030 if (used_ports & port_mask)
11031 return false;
11032
11033 used_ports |= port_mask;
11034 default:
11035 break;
11036 }
11037 }
11038
11039 return true;
11040}
11041
83a57153
ACO		 11042static void
11043clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11044{
11045 struct drm_crtc_state tmp_state;
663a3640 11046 struct intel_crtc_scaler_state scaler_state;
83a57153 11047
663a3640 11048 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11049 tmp_state = crtc_state->base;
663a3640 11050 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11051 memset(crtc_state, 0, sizeof *crtc_state);
11052 crtc_state->base = tmp_state;
663a3640 11053 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11054}
11055
5cec258b 11056static struct intel_crtc_state *
b8cecdf5 11057intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 11058 struct drm_framebuffer *fb,
83a57153
ACO		 11059 struct drm_display_mode *mode,
11060 struct drm_atomic_state *state)
ee7b9f93 11061{
7758a113 11062 struct intel_encoder *encoder;
0b901879
ACO		 11063 struct intel_connector *connector;
11064 struct drm_connector_state *connector_state;
5cec258b 11065 struct intel_crtc_state *pipe_config;
e29c22c0 11066 int plane_bpp, ret = -EINVAL;
0b901879 11067 int i;
e29c22c0 11068 bool retry = true;
ee7b9f93 11069
98a221da 11070 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11071 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11072 return ERR_PTR(-EINVAL);
11073 }
11074
5448a00d 11075 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11076 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11077 return ERR_PTR(-EINVAL);
11078 }
11079
83a57153
ACO		 11080 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11081 if (IS_ERR(pipe_config))
11082 return pipe_config;
11083
11084 clear_intel_crtc_state(pipe_config);
7758a113 11085
07878248 11086 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11087 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11088 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11089
e143a21c
DV		 11090 pipe_config->cpu_transcoder =
11091 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11092 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11093
2960bc9c
ID		 11094 /*
11095 * Sanitize sync polarity flags based on requested ones. If neither
11096 * positive or negative polarity is requested, treat this as meaning
11097 * negative polarity.
11098 */
2d112de7 11099 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11100 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11101 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11102
2d112de7 11103 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11104 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11105 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11106
050f7aeb
DV		 11107 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11108 * plane pixel format and any sink constraints into account. Returns the
11109 * source plane bpp so that dithering can be selected on mismatches
11110 * after encoders and crtc also have had their say. */
11111 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11112 fb, pipe_config);
4e53c2e0
DV		 11113 if (plane_bpp < 0)
11114 goto fail;
11115
e41a56be
VS		 11116 /*
11117 * Determine the real pipe dimensions. Note that stereo modes can
11118 * increase the actual pipe size due to the frame doubling and
11119 * insertion of additional space for blanks between the frame. This
11120 * is stored in the crtc timings. We use the requested mode to do this
11121 * computation to clearly distinguish it from the adjusted mode, which
11122 * can be changed by the connectors in the below retry loop.
11123 */
2d112de7 11124 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11125 &pipe_config->pipe_src_w,
11126 &pipe_config->pipe_src_h);
e41a56be 11127
e29c22c0 11128encoder_retry:
ef1b460d 11129 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11130 pipe_config->port_clock = 0;
ef1b460d 11131 pipe_config->pixel_multiplier = 1;
ff9a6750 11132
135c81b8 11133 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11134 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11135 CRTC_STEREO_DOUBLE);
135c81b8 11136
7758a113
DV		 11137 /* Pass our mode to the connectors and the CRTC to give them a chance to
11138 * adjust it according to limitations or connector properties, and also
11139 * a chance to reject the mode entirely.
47f1c6c9 11140 */
0b901879
ACO		 11141 for (i = 0; i < state->num_connector; i++) {
11142 connector = to_intel_connector(state->connectors[i]);
11143 if (!connector)
11144 continue;
47f1c6c9 11145
0b901879
ACO		 11146 connector_state = state->connector_states[i];
11147 if (connector_state->crtc != crtc)
7758a113 11148 continue;
7ae89233 11149
0b901879
ACO		 11150 encoder = to_intel_encoder(connector_state->best_encoder);
11151
efea6e8e
DV		 11152 if (!(encoder->compute_config(encoder, pipe_config))) {
11153 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11154 goto fail;
11155 }
ee7b9f93 11156 }
47f1c6c9 11157
ff9a6750
DV		 11158 /* Set default port clock if not overwritten by the encoder. Needs to be
11159 * done afterwards in case the encoder adjusts the mode. */
11160 if (!pipe_config->port_clock)
2d112de7 11161 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11162 * pipe_config->pixel_multiplier;
ff9a6750 11163
a43f6e0f 11164 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11165 if (ret < 0) {
7758a113
DV		 11166 DRM_DEBUG_KMS("CRTC fixup failed\n");
11167 goto fail;
ee7b9f93 11168 }
e29c22c0
DV		 11169
11170 if (ret == RETRY) {
11171 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11172 ret = -EINVAL;
11173 goto fail;
11174 }
11175
11176 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11177 retry = false;
11178 goto encoder_retry;
11179 }
11180
4e53c2e0
DV		 11181 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
11182 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11183 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11184
b8cecdf5 11185 return pipe_config;
7758a113 11186fail:
e29c22c0 11187 return ERR_PTR(ret);
ee7b9f93 11188}
47f1c6c9 11189
e2e1ed41
DV		 11190/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11191 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11192static void
11193intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11194 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11195{
11196 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11197 struct drm_device *dev = crtc->dev;
11198 struct intel_encoder *encoder;
11199 struct intel_connector *connector;
11200 struct drm_crtc *tmp_crtc;
79e53945 11201
e2e1ed41 11202 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11203
e2e1ed41
DV		 11204 /* Check which crtcs have changed outputs connected to them, these need
11205 * to be part of the prepare_pipes mask. We don't (yet) support global
11206 * modeset across multiple crtcs, so modeset_pipes will only have one
11207 * bit set at most. */
3a3371ff 11208 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11209 if (connector->base.encoder == &connector->new_encoder->base)
11210 continue;
79e53945 11211
e2e1ed41
DV		 11212 if (connector->base.encoder) {
11213 tmp_crtc = connector->base.encoder->crtc;
11214
11215 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11216 }
11217
11218 if (connector->new_encoder)
11219 *prepare_pipes |=
11220 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11221 }
11222
b2784e15 11223 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11224 if (encoder->base.crtc == &encoder->new_crtc->base)
11225 continue;
11226
11227 if (encoder->base.crtc) {
11228 tmp_crtc = encoder->base.crtc;
11229
11230 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11231 }
11232
11233 if (encoder->new_crtc)
11234 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11235 }
11236
7668851f 11237 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11238 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11239 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11240 continue;
7e7d76c3 11241
7668851f 11242 if (!intel_crtc->new_enabled)
e2e1ed41 11243 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11244 else
11245 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11246 }
11247
e2e1ed41
DV		 11248
11249 /* set_mode is also used to update properties on life display pipes. */
11250 intel_crtc = to_intel_crtc(crtc);
7668851f 11251 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11252 *prepare_pipes |= 1 << intel_crtc->pipe;
11253
b6c5164d
DV		 11254 /*
11255 * For simplicity do a full modeset on any pipe where the output routing
11256 * changed. We could be more clever, but that would require us to be
11257 * more careful with calling the relevant encoder->mode_set functions.
11258 */
e2e1ed41
DV		 11259 if (*prepare_pipes)
11260 *modeset_pipes = *prepare_pipes;
11261
11262 /* ... and mask these out. */
11263 *modeset_pipes &= ~(*disable_pipes);
11264 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11265
11266 /*
11267 * HACK: We don't (yet) fully support global modesets. intel_set_config
11268 * obies this rule, but the modeset restore mode of
11269 * intel_modeset_setup_hw_state does not.
11270 */
11271 *modeset_pipes &= 1 << intel_crtc->pipe;
11272 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11273
11274 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11275 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11276}
79e53945 11277
ea9d758d 11278static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11279{
ea9d758d 11280 struct drm_encoder *encoder;
f6e5b160 11281 struct drm_device *dev = crtc->dev;
f6e5b160 11282
ea9d758d
DV		 11283 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11284 if (encoder->crtc == crtc)
11285 return true;
11286
11287 return false;
11288}
11289
11290static void
11291intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11292{
ba41c0de 11293 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11294 struct intel_encoder *intel_encoder;
11295 struct intel_crtc *intel_crtc;
11296 struct drm_connector *connector;
11297
ba41c0de
DV		 11298 intel_shared_dpll_commit(dev_priv);
11299
b2784e15 11300 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11301 if (!intel_encoder->base.crtc)
11302 continue;
11303
11304 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11305
11306 if (prepare_pipes & (1 << intel_crtc->pipe))
11307 intel_encoder->connectors_active = false;
11308 }
11309
11310 intel_modeset_commit_output_state(dev);
11311
7668851f 11312 /* Double check state. */
d3fcc808 11313 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11314 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11315 }
11316
11317 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11318 if (!connector->encoder || !connector->encoder->crtc)
11319 continue;
11320
11321 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11322
11323 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11324 struct drm_property *dpms_property =
11325 dev->mode_config.dpms_property;
11326
ea9d758d 11327 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11328 drm_object_property_set_value(&connector->base,
68d34720
DV		 11329 dpms_property,
11330 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11331
11332 intel_encoder = to_intel_encoder(connector->encoder);
11333 intel_encoder->connectors_active = true;
11334 }
11335 }
11336
11337}
11338
3bd26263 11339static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11340{
3bd26263 11341 int diff;
f1f644dc
JB		 11342
11343 if (clock1 == clock2)
11344 return true;
11345
11346 if (!clock1 || !clock2)
11347 return false;
11348
11349 diff = abs(clock1 - clock2);
11350
11351 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11352 return true;
11353
11354 return false;
11355}
11356
25c5b266
DV		 11357#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11358 list_for_each_entry((intel_crtc), \
11359 &(dev)->mode_config.crtc_list, \
11360 base.head) \
0973f18f 11361 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11362
0e8ffe1b 11363static bool
2fa2fe9a 11364intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11365 struct intel_crtc_state *current_config,
11366 struct intel_crtc_state *pipe_config)
0e8ffe1b 11367{
66e985c0
DV		 11368#define PIPE_CONF_CHECK_X(name) \
11369 if (current_config->name != pipe_config->name) { \
11370 DRM_ERROR("mismatch in " #name " " \
11371 "(expected 0x%08x, found 0x%08x)\n", \
11372 current_config->name, \
11373 pipe_config->name); \
11374 return false; \
11375 }
11376
08a24034
DV		 11377#define PIPE_CONF_CHECK_I(name) \
11378 if (current_config->name != pipe_config->name) { \
11379 DRM_ERROR("mismatch in " #name " " \
11380 "(expected %i, found %i)\n", \
11381 current_config->name, \
11382 pipe_config->name); \
11383 return false; \
88adfff1
DV		 11384 }
11385
b95af8be
VK		 11386/* This is required for BDW+ where there is only one set of registers for
11387 * switching between high and low RR.
11388 * This macro can be used whenever a comparison has to be made between one
11389 * hw state and multiple sw state variables.
11390 */
11391#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11392 if ((current_config->name != pipe_config->name) && \
11393 (current_config->alt_name != pipe_config->name)) { \
11394 DRM_ERROR("mismatch in " #name " " \
11395 "(expected %i or %i, found %i)\n", \
11396 current_config->name, \
11397 current_config->alt_name, \
11398 pipe_config->name); \
11399 return false; \
11400 }
11401
1bd1bd80
DV		 11402#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11403 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11404 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11405 "(expected %i, found %i)\n", \
11406 current_config->name & (mask), \
11407 pipe_config->name & (mask)); \
11408 return false; \
11409 }
11410
5e550656
VS		 11411#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11412 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11413 DRM_ERROR("mismatch in " #name " " \
11414 "(expected %i, found %i)\n", \
11415 current_config->name, \
11416 pipe_config->name); \
11417 return false; \
11418 }
11419
bb760063
DV		 11420#define PIPE_CONF_QUIRK(quirk) \
11421 ((current_config->quirks | pipe_config->quirks) & (quirk))
11422
eccb140b
DV		 11423 PIPE_CONF_CHECK_I(cpu_transcoder);
11424
08a24034
DV		 11425 PIPE_CONF_CHECK_I(has_pch_encoder);
11426 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11427 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11428 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11429 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11430 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11431 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11432
eb14cb74 11433 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11434
11435 if (INTEL_INFO(dev)->gen < 8) {
11436 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11437 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11438 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11439 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11440 PIPE_CONF_CHECK_I(dp_m_n.tu);
11441
11442 if (current_config->has_drrs) {
11443 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11444 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11445 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11446 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11447 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11448 }
11449 } else {
11450 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11451 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11452 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11453 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11454 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11455 }
eb14cb74 11456
2d112de7
ACO		 11457 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11458 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11459 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11460 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11461 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11462 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11463
2d112de7
ACO		 11464 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11465 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11466 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11467 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11468 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11469 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11470
c93f54cf 11471 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11472 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11473 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11474 IS_VALLEYVIEW(dev))
11475 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11476 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11477
9ed109a7
DV		 11478 PIPE_CONF_CHECK_I(has_audio);
11479
2d112de7 11480 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11481 DRM_MODE_FLAG_INTERLACE);
11482
bb760063 11483 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11484 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11485 DRM_MODE_FLAG_PHSYNC);
2d112de7 11486 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11487 DRM_MODE_FLAG_NHSYNC);
2d112de7 11488 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11489 DRM_MODE_FLAG_PVSYNC);
2d112de7 11490 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11491 DRM_MODE_FLAG_NVSYNC);
11492 }
045ac3b5 11493
37327abd
VS		 11494 PIPE_CONF_CHECK_I(pipe_src_w);
11495 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11496
9953599b
DV		 11497 /*
11498 * FIXME: BIOS likes to set up a cloned config with lvds+external
11499 * screen. Since we don't yet re-compute the pipe config when moving
11500 * just the lvds port away to another pipe the sw tracking won't match.
11501 *
11502 * Proper atomic modesets with recomputed global state will fix this.
11503 * Until then just don't check gmch state for inherited modes.
11504 */
11505 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11506 PIPE_CONF_CHECK_I(gmch_pfit.control);
11507 /* pfit ratios are autocomputed by the hw on gen4+ */
11508 if (INTEL_INFO(dev)->gen < 4)
11509 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11510 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11511 }
11512
fd4daa9c
CW		 11513 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11514 if (current_config->pch_pfit.enabled) {
11515 PIPE_CONF_CHECK_I(pch_pfit.pos);
11516 PIPE_CONF_CHECK_I(pch_pfit.size);
11517 }
2fa2fe9a 11518
a1b2278e
CK		 11519 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11520
e59150dc
JB		 11521 /* BDW+ don't expose a synchronous way to read the state */
11522 if (IS_HASWELL(dev))
11523 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11524
282740f7
VS		 11525 PIPE_CONF_CHECK_I(double_wide);
11526
26804afd
DV		 11527 PIPE_CONF_CHECK_X(ddi_pll_sel);
11528
c0d43d62 11529 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11530 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11531 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11532 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11533 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11534 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11535 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11536 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11537 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11538
42571aef
VS		 11539 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11540 PIPE_CONF_CHECK_I(pipe_bpp);
11541
2d112de7 11542 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11543 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11544
66e985c0 11545#undef PIPE_CONF_CHECK_X
08a24034 11546#undef PIPE_CONF_CHECK_I
b95af8be 11547#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11548#undef PIPE_CONF_CHECK_FLAGS
5e550656 11549#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11550#undef PIPE_CONF_QUIRK
88adfff1 11551
0e8ffe1b
DV		 11552 return true;
11553}
11554
08db6652
DL		 11555static void check_wm_state(struct drm_device *dev)
11556{
11557 struct drm_i915_private *dev_priv = dev->dev_private;
11558 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11559 struct intel_crtc *intel_crtc;
11560 int plane;
11561
11562 if (INTEL_INFO(dev)->gen < 9)
11563 return;
11564
11565 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11566 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11567
11568 for_each_intel_crtc(dev, intel_crtc) {
11569 struct skl_ddb_entry *hw_entry, *sw_entry;
11570 const enum pipe pipe = intel_crtc->pipe;
11571
11572 if (!intel_crtc->active)
11573 continue;
11574
11575 /* planes */
dd740780 11576 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11577 hw_entry = &hw_ddb.plane[pipe][plane];
11578 sw_entry = &sw_ddb->plane[pipe][plane];
11579
11580 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11581 continue;
11582
11583 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11584 "(expected (%u,%u), found (%u,%u))\n",
11585 pipe_name(pipe), plane + 1,
11586 sw_entry->start, sw_entry->end,
11587 hw_entry->start, hw_entry->end);
11588 }
11589
11590 /* cursor */
11591 hw_entry = &hw_ddb.cursor[pipe];
11592 sw_entry = &sw_ddb->cursor[pipe];
11593
11594 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11595 continue;
11596
11597 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11598 "(expected (%u,%u), found (%u,%u))\n",
11599 pipe_name(pipe),
11600 sw_entry->start, sw_entry->end,
11601 hw_entry->start, hw_entry->end);
11602 }
11603}
11604
91d1b4bd
DV		 11605static void
11606check_connector_state(struct drm_device *dev)
8af6cf88 11607{
8af6cf88
DV		 11608 struct intel_connector *connector;
11609
3a3371ff 11610 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11611 /* This also checks the encoder/connector hw state with the
11612 * ->get_hw_state callbacks. */
11613 intel_connector_check_state(connector);
11614
e2c719b7 11615 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11616 "connector's staged encoder doesn't match current encoder\n");
11617 }
91d1b4bd
DV		 11618}
11619
11620static void
11621check_encoder_state(struct drm_device *dev)
11622{
11623 struct intel_encoder *encoder;
11624 struct intel_connector *connector;
8af6cf88 11625
b2784e15 11626 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11627 bool enabled = false;
11628 bool active = false;
11629 enum pipe pipe, tracked_pipe;
11630
11631 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11632 encoder->base.base.id,
8e329a03 11633 encoder->base.name);
8af6cf88 11634
e2c719b7 11635 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11636 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11637 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11638 "encoder's active_connectors set, but no crtc\n");
11639
3a3371ff 11640 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11641 if (connector->base.encoder != &encoder->base)
11642 continue;
11643 enabled = true;
11644 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11645 active = true;
11646 }
0e32b39c
DA		 11647 /*
11648 * for MST connectors if we unplug the connector is gone
11649 * away but the encoder is still connected to a crtc
11650 * until a modeset happens in response to the hotplug.
11651 */
11652 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11653 continue;
11654
e2c719b7 11655 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11656 "encoder's enabled state mismatch "
11657 "(expected %i, found %i)\n",
11658 !!encoder->base.crtc, enabled);
e2c719b7 11659 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11660 "active encoder with no crtc\n");
11661
e2c719b7 11662 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11663 "encoder's computed active state doesn't match tracked active state "
11664 "(expected %i, found %i)\n", active, encoder->connectors_active);
11665
11666 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11667 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11668 "encoder's hw state doesn't match sw tracking "
11669 "(expected %i, found %i)\n",
11670 encoder->connectors_active, active);
11671
11672 if (!encoder->base.crtc)
11673 continue;
11674
11675 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11676 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11677 "active encoder's pipe doesn't match"
11678 "(expected %i, found %i)\n",
11679 tracked_pipe, pipe);
11680
11681 }
91d1b4bd
DV		 11682}
11683
11684static void
11685check_crtc_state(struct drm_device *dev)
11686{
fbee40df 11687 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11688 struct intel_crtc *crtc;
11689 struct intel_encoder *encoder;
5cec258b 11690 struct intel_crtc_state pipe_config;
8af6cf88 11691
d3fcc808 11692 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11693 bool enabled = false;
11694 bool active = false;
11695
045ac3b5
JB		 11696 memset(&pipe_config, 0, sizeof(pipe_config));
11697
8af6cf88
DV		 11698 DRM_DEBUG_KMS("[CRTC:%d]\n",
11699 crtc->base.base.id);
11700
83d65738 11701 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11702 "active crtc, but not enabled in sw tracking\n");
11703
b2784e15 11704 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11705 if (encoder->base.crtc != &crtc->base)
11706 continue;
11707 enabled = true;
11708 if (encoder->connectors_active)
11709 active = true;
11710 }
6c49f241 11711
e2c719b7 11712 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11713 "crtc's computed active state doesn't match tracked active state "
11714 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11715 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11716 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11717 "(expected %i, found %i)\n", enabled,
11718 crtc->base.state->enable);
8af6cf88 11719
0e8ffe1b
DV		 11720 active = dev_priv->display.get_pipe_config(crtc,
11721 &pipe_config);
d62cf62a 11722
b6b5d049
VS		 11723 /* hw state is inconsistent with the pipe quirk */
11724 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11725 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11726 active = crtc->active;
11727
b2784e15 11728 for_each_intel_encoder(dev, encoder) {
3eaba51c 11729 enum pipe pipe;
6c49f241
DV		 11730 if (encoder->base.crtc != &crtc->base)
11731 continue;
1d37b689 11732 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11733 encoder->get_config(encoder, &pipe_config);
11734 }
11735
e2c719b7 11736 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11737 "crtc active state doesn't match with hw state "
11738 "(expected %i, found %i)\n", crtc->active, active);
11739
c0b03411 11740 if (active &&
6e3c9717 11741 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11742 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11743 intel_dump_pipe_config(crtc, &pipe_config,
11744 "[hw state]");
6e3c9717 11745 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11746 "[sw state]");
11747 }
8af6cf88
DV		 11748 }
11749}
11750
91d1b4bd
DV		 11751static void
11752check_shared_dpll_state(struct drm_device *dev)
11753{
fbee40df 11754 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11755 struct intel_crtc *crtc;
11756 struct intel_dpll_hw_state dpll_hw_state;
11757 int i;
5358901f
DV		 11758
11759 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11760 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11761 int enabled_crtcs = 0, active_crtcs = 0;
11762 bool active;
11763
11764 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11765
11766 DRM_DEBUG_KMS("%s\n", pll->name);
11767
11768 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11769
e2c719b7 11770 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11771 "more active pll users than references: %i vs %i\n",
3e369b76 11772 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11773 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11774 "pll in active use but not on in sw tracking\n");
e2c719b7 11775 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11776 "pll in on but not on in use in sw tracking\n");
e2c719b7 11777 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11778 "pll on state mismatch (expected %i, found %i)\n",
11779 pll->on, active);
11780
d3fcc808 11781 for_each_intel_crtc(dev, crtc) {
83d65738 11782 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11783 enabled_crtcs++;
11784 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11785 active_crtcs++;
11786 }
e2c719b7 11787 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11788 "pll active crtcs mismatch (expected %i, found %i)\n",
11789 pll->active, active_crtcs);
e2c719b7 11790 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11791 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11792 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11793
e2c719b7 11794 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11795 sizeof(dpll_hw_state)),
11796 "pll hw state mismatch\n");
5358901f 11797 }
8af6cf88
DV		 11798}
11799
91d1b4bd
DV		 11800void
11801intel_modeset_check_state(struct drm_device *dev)
11802{
08db6652 11803 check_wm_state(dev);
91d1b4bd
DV		 11804 check_connector_state(dev);
11805 check_encoder_state(dev);
11806 check_crtc_state(dev);
11807 check_shared_dpll_state(dev);
11808}
11809
5cec258b 11810void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11811 int dotclock)
11812{
11813 /*
11814 * FDI already provided one idea for the dotclock.
11815 * Yell if the encoder disagrees.
11816 */
2d112de7 11817 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11818 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11819 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11820}
11821
80715b2f
VS		 11822static void update_scanline_offset(struct intel_crtc *crtc)
11823{
11824 struct drm_device *dev = crtc->base.dev;
11825
11826 /*
11827 * The scanline counter increments at the leading edge of hsync.
11828 *
11829 * On most platforms it starts counting from vtotal-1 on the
11830 * first active line. That means the scanline counter value is
11831 * always one less than what we would expect. Ie. just after
11832 * start of vblank, which also occurs at start of hsync (on the
11833 * last active line), the scanline counter will read vblank_start-1.
11834 *
11835 * On gen2 the scanline counter starts counting from 1 instead
11836 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11837 * to keep the value positive), instead of adding one.
11838 *
11839 * On HSW+ the behaviour of the scanline counter depends on the output
11840 * type. For DP ports it behaves like most other platforms, but on HDMI
11841 * there's an extra 1 line difference. So we need to add two instead of
11842 * one to the value.
11843 */
11844 if (IS_GEN2(dev)) {
6e3c9717 11845 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11846 int vtotal;
11847
11848 vtotal = mode->crtc_vtotal;
11849 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11850 vtotal /= 2;
11851
11852 crtc->scanline_offset = vtotal - 1;
11853 } else if (HAS_DDI(dev) &&
409ee761 11854 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11855 crtc->scanline_offset = 2;
11856 } else
11857 crtc->scanline_offset = 1;
11858}
11859
5cec258b 11860static struct intel_crtc_state *
7f27126e
JB		 11861intel_modeset_compute_config(struct drm_crtc *crtc,
11862 struct drm_display_mode *mode,
11863 struct drm_framebuffer *fb,
83a57153 11864 struct drm_atomic_state *state,
7f27126e
JB		 11865 unsigned *modeset_pipes,
11866 unsigned *prepare_pipes,
11867 unsigned *disable_pipes)
11868{
db7542dd 11869 struct drm_device *dev = crtc->dev;
5cec258b 11870 struct intel_crtc_state *pipe_config = NULL;
db7542dd 11871 struct intel_crtc *intel_crtc;
0b901879
ACO		 11872 int ret = 0;
11873
11874 ret = drm_atomic_add_affected_connectors(state, crtc);
11875 if (ret)
11876 return ERR_PTR(ret);
7f27126e
JB		 11877
11878 intel_modeset_affected_pipes(crtc, modeset_pipes,
11879 prepare_pipes, disable_pipes);
11880
db7542dd
ACO		 11881 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11882 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11883 if (IS_ERR(pipe_config))
11884 return pipe_config;
11885
11886 pipe_config->base.enable = false;
11887 }
7f27126e
JB		 11888
11889 /*
11890 * Note this needs changes when we start tracking multiple modes
11891 * and crtcs. At that point we'll need to compute the whole config
11892 * (i.e. one pipe_config for each crtc) rather than just the one
11893 * for this crtc.
11894 */
db7542dd
ACO		 11895 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11896 /* FIXME: For now we still expect modeset_pipes has at most
11897 * one bit set. */
11898 if (WARN_ON(&intel_crtc->base != crtc))
11899 continue;
83a57153 11900
db7542dd
ACO		 11901 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11902 if (IS_ERR(pipe_config))
11903 return pipe_config;
7f27126e 11904
304603f4
ACO		 11905 pipe_config->base.enable = true;
11906
db7542dd
ACO		 11907 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11908 "[modeset]");
11909 }
11910
11911 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 11912}
11913
225da59b 11914static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 11915 unsigned modeset_pipes,
11916 unsigned disable_pipes)
11917{
225da59b 11918 struct drm_device *dev = state->dev;
ed6739ef
ACO		 11919 struct drm_i915_private *dev_priv = to_i915(dev);
11920 unsigned clear_pipes = modeset_pipes | disable_pipes;
11921 struct intel_crtc *intel_crtc;
11922 int ret = 0;
11923
11924 if (!dev_priv->display.crtc_compute_clock)
11925 return 0;
11926
11927 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11928 if (ret)
11929 goto done;
11930
11931 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 11932 struct intel_crtc_state *crtc_state =
11933 intel_atomic_get_crtc_state(state, intel_crtc);
11934
11935 /* Modeset pipes should have a new state by now */
11936 if (WARN_ON(IS_ERR(crtc_state)))
11937 continue;
11938
ed6739ef 11939 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 11940 crtc_state);
ed6739ef
ACO		 11941 if (ret) {
11942 intel_shared_dpll_abort_config(dev_priv);
11943 goto done;
11944 }
11945 }
11946
11947done:
11948 return ret;
11949}
11950
f30da187
DV		 11951static int __intel_set_mode(struct drm_crtc *crtc,
11952 struct drm_display_mode *mode,
7f27126e 11953 int x, int y, struct drm_framebuffer *fb,
5cec258b 11954 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11955 unsigned modeset_pipes,
11956 unsigned prepare_pipes,
11957 unsigned disable_pipes)
a6778b3c
DV		 11958{
11959 struct drm_device *dev = crtc->dev;
fbee40df 11960 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11961 struct drm_display_mode *saved_mode;
304603f4 11962 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 11963 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 11964 struct intel_crtc *intel_crtc;
c0c36b94 11965 int ret = 0;
a6778b3c 11966
4b4b9238 11967 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11968 if (!saved_mode)
11969 return -ENOMEM;
a6778b3c 11970
83a57153
ACO		 11971 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11972 if (!crtc_state_copy) {
11973 ret = -ENOMEM;
11974 goto done;
11975 }
11976
3ac18232 11977 *saved_mode = crtc->mode;
a6778b3c 11978
30a970c6
JB		 11979 /*
11980 * See if the config requires any additional preparation, e.g.
11981 * to adjust global state with pipes off. We need to do this
11982 * here so we can get the modeset_pipe updated config for the new
11983 * mode set on this crtc. For other crtcs we need to use the
11984 * adjusted_mode bits in the crtc directly.
11985 */
c164f833 11986 if (IS_VALLEYVIEW(dev)) {
304603f4
ACO		 11987 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
11988 if (ret)
11989 goto done;
30a970c6 11990
c164f833
VS		 11991 /* may have added more to prepare_pipes than we should */
11992 prepare_pipes &= ~disable_pipes;
11993 }
11994
225da59b 11995 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 11996 if (ret)
11997 goto done;
8bd31e67 11998
460da916
DV		 11999 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12000 intel_crtc_disable(&intel_crtc->base);
12001
ea9d758d 12002 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 12003 if (intel_crtc->base.state->enable)
ea9d758d
DV		 12004 dev_priv->display.crtc_disable(&intel_crtc->base);
12005 }
a6778b3c 12006
6c4c86f5
DV		 12007 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12008 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12009 *
12010 * Note we'll need to fix this up when we start tracking multiple
12011 * pipes; here we assume a single modeset_pipe and only track the
12012 * single crtc and mode.
f6e5b160 12013 */
b8cecdf5 12014 if (modeset_pipes) {
25c5b266 12015 crtc->mode = *mode;
b8cecdf5
DV		 12016 /* mode_set/enable/disable functions rely on a correct pipe
12017 * config. */
f5de6e07 12018 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12019
12020 /*
12021 * Calculate and store various constants which
12022 * are later needed by vblank and swap-completion
12023 * timestamping. They are derived from true hwmode.
12024 */
12025 drm_calc_timestamping_constants(crtc,
2d112de7 12026 &pipe_config->base.adjusted_mode);
b8cecdf5 12027 }
7758a113 12028
ea9d758d
DV		 12029 /* Only after disabling all output pipelines that will be changed can we
12030 * update the the output configuration. */
12031 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12032
304603f4 12033 modeset_update_crtc_power_domains(state);
47fab737 12034
25c5b266 12035 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12036 struct drm_plane *primary = intel_crtc->base.primary;
12037 int vdisplay, hdisplay;
4c10794f 12038
455a6808 12039 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12040 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12041 fb, 0, 0,
12042 hdisplay, vdisplay,
12043 x << 16, y << 16,
12044 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12045 }
12046
12047 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12048 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12049 update_scanline_offset(intel_crtc);
12050
25c5b266 12051 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 12052 }
a6778b3c 12053
a6778b3c
DV		 12054 /* FIXME: add subpixel order */
12055done:
83d65738 12056 if (ret && crtc->state->enable)
3ac18232 12057 crtc->mode = *saved_mode;
a6778b3c 12058
83a57153
ACO		 12059 if (ret == 0 && pipe_config) {
12060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12061
12062 /* The pipe_config will be freed with the atomic state, so
12063 * make a copy. */
12064 memcpy(crtc_state_copy, intel_crtc->config,
12065 sizeof *crtc_state_copy);
12066 intel_crtc->config = crtc_state_copy;
12067 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12068 } else {
12069 kfree(crtc_state_copy);
12070 }
12071
3ac18232 12072 kfree(saved_mode);
a6778b3c 12073 return ret;
f6e5b160
CW		 12074}
12075
7f27126e
JB		 12076static int intel_set_mode_pipes(struct drm_crtc *crtc,
12077 struct drm_display_mode *mode,
12078 int x, int y, struct drm_framebuffer *fb,
5cec258b 12079 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12080 unsigned modeset_pipes,
12081 unsigned prepare_pipes,
12082 unsigned disable_pipes)
f30da187
DV		 12083{
12084 int ret;
12085
7f27126e
JB		 12086 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12087 prepare_pipes, disable_pipes);
f30da187
DV		 12088
12089 if (ret == 0)
12090 intel_modeset_check_state(crtc->dev);
12091
12092 return ret;
12093}
12094
7f27126e
JB		 12095static int intel_set_mode(struct drm_crtc *crtc,
12096 struct drm_display_mode *mode,
83a57153
ACO		 12097 int x, int y, struct drm_framebuffer *fb,
12098 struct drm_atomic_state *state)
7f27126e 12099{
5cec258b 12100 struct intel_crtc_state *pipe_config;
7f27126e 12101 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12102 int ret = 0;
7f27126e 12103
83a57153 12104 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 12105 &modeset_pipes,
12106 &prepare_pipes,
12107 &disable_pipes);
12108
83a57153
ACO		 12109 if (IS_ERR(pipe_config)) {
12110 ret = PTR_ERR(pipe_config);
12111 goto out;
12112 }
12113
12114 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12115 modeset_pipes, prepare_pipes,
12116 disable_pipes);
12117 if (ret)
12118 goto out;
7f27126e 12119
83a57153
ACO		 12120out:
12121 return ret;
7f27126e
JB		 12122}
12123
c0c36b94
CW		 12124void intel_crtc_restore_mode(struct drm_crtc *crtc)
12125{
83a57153
ACO		 12126 struct drm_device *dev = crtc->dev;
12127 struct drm_atomic_state *state;
12128 struct intel_encoder *encoder;
12129 struct intel_connector *connector;
12130 struct drm_connector_state *connector_state;
12131
12132 state = drm_atomic_state_alloc(dev);
12133 if (!state) {
12134 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12135 crtc->base.id);
12136 return;
12137 }
12138
12139 state->acquire_ctx = dev->mode_config.acquire_ctx;
12140
12141 /* The force restore path in the HW readout code relies on the staged
12142 * config still keeping the user requested config while the actual
12143 * state has been overwritten by the configuration read from HW. We
12144 * need to copy the staged config to the atomic state, otherwise the
12145 * mode set will just reapply the state the HW is already in. */
12146 for_each_intel_encoder(dev, encoder) {
12147 if (&encoder->new_crtc->base != crtc)
12148 continue;
12149
12150 for_each_intel_connector(dev, connector) {
12151 if (connector->new_encoder != encoder)
12152 continue;
12153
12154 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12155 if (IS_ERR(connector_state)) {
12156 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12157 connector->base.base.id,
12158 connector->base.name,
12159 PTR_ERR(connector_state));
12160 continue;
12161 }
12162
12163 connector_state->crtc = crtc;
12164 connector_state->best_encoder = &encoder->base;
12165 }
12166 }
12167
12168 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12169 state);
12170
12171 drm_atomic_state_free(state);
c0c36b94
CW		 12172}
12173
25c5b266
DV		 12174#undef for_each_intel_crtc_masked
12175
d9e55608
DV		 12176static void intel_set_config_free(struct intel_set_config *config)
12177{
12178 if (!config)
12179 return;
12180
1aa4b628
DV		 12181 kfree(config->save_connector_encoders);
12182 kfree(config->save_encoder_crtcs);
7668851f 12183 kfree(config->save_crtc_enabled);
d9e55608
DV		 12184 kfree(config);
12185}
12186
85f9eb71
DV		 12187static int intel_set_config_save_state(struct drm_device *dev,
12188 struct intel_set_config *config)
12189{
7668851f 12190 struct drm_crtc *crtc;
85f9eb71
DV		 12191 struct drm_encoder *encoder;
12192 struct drm_connector *connector;
12193 int count;
12194
7668851f
VS		 12195 config->save_crtc_enabled =
12196 kcalloc(dev->mode_config.num_crtc,
12197 sizeof(bool), GFP_KERNEL);
12198 if (!config->save_crtc_enabled)
12199 return -ENOMEM;
12200
1aa4b628
DV		 12201 config->save_encoder_crtcs =
12202 kcalloc(dev->mode_config.num_encoder,
12203 sizeof(struct drm_crtc *), GFP_KERNEL);
12204 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12205 return -ENOMEM;
12206
1aa4b628
DV		 12207 config->save_connector_encoders =
12208 kcalloc(dev->mode_config.num_connector,
12209 sizeof(struct drm_encoder *), GFP_KERNEL);
12210 if (!config->save_connector_encoders)
85f9eb71
DV		 12211 return -ENOMEM;
12212
12213 /* Copy data. Note that driver private data is not affected.
12214 * Should anything bad happen only the expected state is
12215 * restored, not the drivers personal bookkeeping.
12216 */
7668851f 12217 count = 0;
70e1e0ec 12218 for_each_crtc(dev, crtc) {
83d65738 12219 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12220 }
12221
85f9eb71
DV		 12222 count = 0;
12223 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12224 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12225 }
12226
12227 count = 0;
12228 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12229 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12230 }
12231
12232 return 0;
12233}
12234
12235static void intel_set_config_restore_state(struct drm_device *dev,
12236 struct intel_set_config *config)
12237{
7668851f 12238 struct intel_crtc *crtc;
9a935856
DV		 12239 struct intel_encoder *encoder;
12240 struct intel_connector *connector;
85f9eb71
DV		 12241 int count;
12242
7668851f 12243 count = 0;
d3fcc808 12244 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12245 crtc->new_enabled = config->save_crtc_enabled[count++];
12246 }
12247
85f9eb71 12248 count = 0;
b2784e15 12249 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12250 encoder->new_crtc =
12251 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12252 }
12253
12254 count = 0;
3a3371ff 12255 for_each_intel_connector(dev, connector) {
9a935856
DV		 12256 connector->new_encoder =
12257 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12258 }
12259}
12260
e3de42b6 12261static bool
2e57f47d 12262is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12263{
12264 int i;
12265
2e57f47d
CW		 12266 if (set->num_connectors == 0)
12267 return false;
12268
12269 if (WARN_ON(set->connectors == NULL))
12270 return false;
12271
12272 for (i = 0; i < set->num_connectors; i++)
12273 if (set->connectors[i]->encoder &&
12274 set->connectors[i]->encoder->crtc == set->crtc &&
12275 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12276 return true;
12277
12278 return false;
12279}
12280
5e2b584e
DV		 12281static void
12282intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12283 struct intel_set_config *config)
12284{
12285
12286 /* We should be able to check here if the fb has the same properties
12287 * and then just flip_or_move it */
2e57f47d
CW		 12288 if (is_crtc_connector_off(set)) {
12289 config->mode_changed = true;
f4510a27 12290 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12291 /*
12292 * If we have no fb, we can only flip as long as the crtc is
12293 * active, otherwise we need a full mode set. The crtc may
12294 * be active if we've only disabled the primary plane, or
12295 * in fastboot situations.
12296 */
f4510a27 12297 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12298 struct intel_crtc *intel_crtc =
12299 to_intel_crtc(set->crtc);
12300
3b150f08 12301 if (intel_crtc->active) {
319d9827
JB		 12302 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12303 config->fb_changed = true;
12304 } else {
12305 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12306 config->mode_changed = true;
12307 }
5e2b584e
DV		 12308 } else if (set->fb == NULL) {
12309 config->mode_changed = true;
72f4901e 12310 } else if (set->fb->pixel_format !=
f4510a27 12311 set->crtc->primary->fb->pixel_format) {
5e2b584e 12312 config->mode_changed = true;
e3de42b6 12313 } else {
5e2b584e 12314 config->fb_changed = true;
e3de42b6 12315 }
5e2b584e
DV		 12316 }
12317
835c5873 12318 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12319 config->fb_changed = true;
12320
12321 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12322 DRM_DEBUG_KMS("modes are different, full mode set\n");
12323 drm_mode_debug_printmodeline(&set->crtc->mode);
12324 drm_mode_debug_printmodeline(set->mode);
12325 config->mode_changed = true;
12326 }
a1d95703
CW		 12327
12328 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12329 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12330}
12331
2e431051 12332static int
9a935856
DV		 12333intel_modeset_stage_output_state(struct drm_device *dev,
12334 struct drm_mode_set *set,
944b0c76
ACO		 12335 struct intel_set_config *config,
12336 struct drm_atomic_state *state)
50f56119 12337{
9a935856 12338 struct intel_connector *connector;
944b0c76 12339 struct drm_connector_state *connector_state;
9a935856 12340 struct intel_encoder *encoder;
7668851f 12341 struct intel_crtc *crtc;
f3f08572 12342 int ro;
50f56119 12343
9abdda74 12344 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12345 * of connectors. For paranoia, double-check this. */
12346 WARN_ON(!set->fb && (set->num_connectors != 0));
12347 WARN_ON(set->fb && (set->num_connectors == 0));
12348
3a3371ff 12349 for_each_intel_connector(dev, connector) {
9a935856
DV		 12350 /* Otherwise traverse passed in connector list and get encoders
12351 * for them. */
50f56119 12352 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12353 if (set->connectors[ro] == &connector->base) {
0e32b39c 12354 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12355 break;
12356 }
12357 }
12358
9a935856
DV		 12359 /* If we disable the crtc, disable all its connectors. Also, if
12360 * the connector is on the changing crtc but not on the new
12361 * connector list, disable it. */
12362 if ((!set->fb || ro == set->num_connectors) &&
12363 connector->base.encoder &&
12364 connector->base.encoder->crtc == set->crtc) {
12365 connector->new_encoder = NULL;
12366
12367 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12368 connector->base.base.id,
c23cc417 12369 connector->base.name);
9a935856
DV		 12370 }
12371
12372
12373 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12374 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12375 connector->base.base.id,
12376 connector->base.name);
5e2b584e 12377 config->mode_changed = true;
50f56119
DV		 12378 }
12379 }
9a935856 12380 /* connector->new_encoder is now updated for all connectors. */
50f56119 12381
9a935856 12382 /* Update crtc of enabled connectors. */
3a3371ff 12383 for_each_intel_connector(dev, connector) {
7668851f
VS		 12384 struct drm_crtc *new_crtc;
12385
9a935856 12386 if (!connector->new_encoder)
50f56119
DV		 12387 continue;
12388
9a935856 12389 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12390
12391 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12392 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12393 new_crtc = set->crtc;
12394 }
12395
12396 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12397 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12398 new_crtc)) {
5e2b584e 12399 return -EINVAL;
50f56119 12400 }
0e32b39c 12401 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12402
944b0c76
ACO		 12403 connector_state =
12404 drm_atomic_get_connector_state(state, &connector->base);
12405 if (IS_ERR(connector_state))
12406 return PTR_ERR(connector_state);
12407
12408 connector_state->crtc = new_crtc;
12409 connector_state->best_encoder = &connector->new_encoder->base;
12410
9a935856
DV		 12411 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12412 connector->base.base.id,
c23cc417 12413 connector->base.name,
9a935856
DV		 12414 new_crtc->base.id);
12415 }
12416
12417 /* Check for any encoders that needs to be disabled. */
b2784e15 12418 for_each_intel_encoder(dev, encoder) {
5a65f358 12419 int num_connectors = 0;
3a3371ff 12420 for_each_intel_connector(dev, connector) {
9a935856
DV		 12421 if (connector->new_encoder == encoder) {
12422 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12423 num_connectors++;
9a935856
DV		 12424 }
12425 }
5a65f358
PZ		 12426
12427 if (num_connectors == 0)
12428 encoder->new_crtc = NULL;
12429 else if (num_connectors > 1)
12430 return -EINVAL;
12431
9a935856
DV		 12432 /* Only now check for crtc changes so we don't miss encoders
12433 * that will be disabled. */
12434 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12435 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12436 encoder->base.base.id,
12437 encoder->base.name);
5e2b584e 12438 config->mode_changed = true;
50f56119
DV		 12439 }
12440 }
9a935856 12441 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12442 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12443 connector_state =
12444 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12445 if (IS_ERR(connector_state))
12446 return PTR_ERR(connector_state);
944b0c76
ACO		 12447
12448 if (connector->new_encoder) {
0e32b39c
DA		 12449 if (connector->new_encoder != connector->encoder)
12450 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12451 } else {
12452 connector_state->crtc = NULL;
f61cccf3 12453 connector_state->best_encoder = NULL;
944b0c76 12454 }
0e32b39c 12455 }
d3fcc808 12456 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12457 crtc->new_enabled = false;
12458
b2784e15 12459 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12460 if (encoder->new_crtc == crtc) {
12461 crtc->new_enabled = true;
12462 break;
12463 }
12464 }
12465
83d65738 12466 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12467 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12468 crtc->base.base.id,
7668851f
VS		 12469 crtc->new_enabled ? "en" : "dis");
12470 config->mode_changed = true;
12471 }
12472 }
12473
2e431051
DV		 12474 return 0;
12475}
12476
7d00a1f5
VS		 12477static void disable_crtc_nofb(struct intel_crtc *crtc)
12478{
12479 struct drm_device *dev = crtc->base.dev;
12480 struct intel_encoder *encoder;
12481 struct intel_connector *connector;
12482
12483 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12484 pipe_name(crtc->pipe));
12485
3a3371ff 12486 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12487 if (connector->new_encoder &&
12488 connector->new_encoder->new_crtc == crtc)
12489 connector->new_encoder = NULL;
12490 }
12491
b2784e15 12492 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12493 if (encoder->new_crtc == crtc)
12494 encoder->new_crtc = NULL;
12495 }
12496
12497 crtc->new_enabled = false;
12498}
12499
2e431051
DV		 12500static int intel_crtc_set_config(struct drm_mode_set *set)
12501{
12502 struct drm_device *dev;
2e431051 12503 struct drm_mode_set save_set;
83a57153 12504 struct drm_atomic_state *state = NULL;
2e431051 12505 struct intel_set_config *config;
5cec258b 12506 struct intel_crtc_state *pipe_config;
50f52756 12507 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12508 int ret;
2e431051 12509
8d3e375e
DV		 12510 BUG_ON(!set);
12511 BUG_ON(!set->crtc);
12512 BUG_ON(!set->crtc->helper_private);
2e431051 12513
7e53f3a4
DV		 12514 /* Enforce sane interface api - has been abused by the fb helper. */
12515 BUG_ON(!set->mode && set->fb);
12516 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12517
2e431051
DV		 12518 if (set->fb) {
12519 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12520 set->crtc->base.id, set->fb->base.id,
12521 (int)set->num_connectors, set->x, set->y);
12522 } else {
12523 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12524 }
12525
12526 dev = set->crtc->dev;
12527
12528 ret = -ENOMEM;
12529 config = kzalloc(sizeof(*config), GFP_KERNEL);
12530 if (!config)
12531 goto out_config;
12532
12533 ret = intel_set_config_save_state(dev, config);
12534 if (ret)
12535 goto out_config;
12536
12537 save_set.crtc = set->crtc;
12538 save_set.mode = &set->crtc->mode;
12539 save_set.x = set->crtc->x;
12540 save_set.y = set->crtc->y;
f4510a27 12541 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12542
12543 /* Compute whether we need a full modeset, only an fb base update or no
12544 * change at all. In the future we might also check whether only the
12545 * mode changed, e.g. for LVDS where we only change the panel fitter in
12546 * such cases. */
12547 intel_set_config_compute_mode_changes(set, config);
12548
83a57153
ACO		 12549 state = drm_atomic_state_alloc(dev);
12550 if (!state) {
12551 ret = -ENOMEM;
12552 goto out_config;
12553 }
12554
12555 state->acquire_ctx = dev->mode_config.acquire_ctx;
12556
944b0c76 12557 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12558 if (ret)
12559 goto fail;
12560
50f52756 12561 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12562 set->fb, state,
50f52756
JB		 12563 &modeset_pipes,
12564 &prepare_pipes,
12565 &disable_pipes);
20664591 12566 if (IS_ERR(pipe_config)) {
6ac0483b 12567 ret = PTR_ERR(pipe_config);
50f52756 12568 goto fail;
20664591 12569 } else if (pipe_config) {
b9950a13 12570 if (pipe_config->has_audio !=
6e3c9717 12571 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12572 config->mode_changed = true;
12573
af15d2ce
JB		 12574 /*
12575 * Note we have an issue here with infoframes: current code
12576 * only updates them on the full mode set path per hw
12577 * requirements. So here we should be checking for any
12578 * required changes and forcing a mode set.
12579 */
20664591 12580 }
50f52756 12581
1f9954d0
JB		 12582 intel_update_pipe_size(to_intel_crtc(set->crtc));
12583
5e2b584e 12584 if (config->mode_changed) {
50f52756
JB		 12585 ret = intel_set_mode_pipes(set->crtc, set->mode,
12586 set->x, set->y, set->fb, pipe_config,
12587 modeset_pipes, prepare_pipes,
12588 disable_pipes);
5e2b584e 12589 } else if (config->fb_changed) {
3b150f08 12590 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12591 struct drm_plane *primary = set->crtc->primary;
12592 int vdisplay, hdisplay;
3b150f08 12593
455a6808 12594 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12595 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12596 0, 0, hdisplay, vdisplay,
12597 set->x << 16, set->y << 16,
12598 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12599
12600 /*
12601 * We need to make sure the primary plane is re-enabled if it
12602 * has previously been turned off.
12603 */
12604 if (!intel_crtc->primary_enabled && ret == 0) {
12605 WARN_ON(!intel_crtc->active);
fdd508a6 12606 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12607 }
12608
7ca51a3a
JB		 12609 /*
12610 * In the fastboot case this may be our only check of the
12611 * state after boot. It would be better to only do it on
12612 * the first update, but we don't have a nice way of doing that
12613 * (and really, set_config isn't used much for high freq page
12614 * flipping, so increasing its cost here shouldn't be a big
12615 * deal).
12616 */
d330a953 12617 if (i915.fastboot && ret == 0)
7ca51a3a 12618 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12619 }
12620
2d05eae1 12621 if (ret) {
bf67dfeb
DV		 12622 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12623 set->crtc->base.id, ret);
50f56119 12624fail:
2d05eae1 12625 intel_set_config_restore_state(dev, config);
50f56119 12626
83a57153
ACO		 12627 drm_atomic_state_clear(state);
12628
7d00a1f5
VS		 12629 /*
12630 * HACK: if the pipe was on, but we didn't have a framebuffer,
12631 * force the pipe off to avoid oopsing in the modeset code
12632 * due to fb==NULL. This should only happen during boot since
12633 * we don't yet reconstruct the FB from the hardware state.
12634 */
12635 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12636 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12637
2d05eae1
CW		 12638 /* Try to restore the config */
12639 if (config->mode_changed &&
12640 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12641 save_set.x, save_set.y, save_set.fb,
12642 state))
2d05eae1
CW		 12643 DRM_ERROR("failed to restore config after modeset failure\n");
12644 }
50f56119 12645
d9e55608 12646out_config:
83a57153
ACO		 12647 if (state)
12648 drm_atomic_state_free(state);
12649
d9e55608 12650 intel_set_config_free(config);
50f56119
DV		 12651 return ret;
12652}
f6e5b160
CW		 12653
12654static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12655 .gamma_set = intel_crtc_gamma_set,
50f56119 12656 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12657 .destroy = intel_crtc_destroy,
12658 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12659 .atomic_duplicate_state = intel_crtc_duplicate_state,
12660 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12661};
12662
5358901f
DV		 12663static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12664 struct intel_shared_dpll *pll,
12665 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12666{
5358901f 12667 uint32_t val;
ee7b9f93 12668
f458ebbc 12669 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12670 return false;
12671
5358901f 12672 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12673 hw_state->dpll = val;
12674 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12675 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12676
12677 return val & DPLL_VCO_ENABLE;
12678}
12679
15bdd4cf
DV		 12680static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12681 struct intel_shared_dpll *pll)
12682{
3e369b76
ACO		 12683 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12684 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12685}
12686
e7b903d2
DV		 12687static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12688 struct intel_shared_dpll *pll)
12689{
e7b903d2 12690 /* PCH refclock must be enabled first */
89eff4be 12691 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12692
3e369b76 12693 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12694
12695 /* Wait for the clocks to stabilize. */
12696 POSTING_READ(PCH_DPLL(pll->id));
12697 udelay(150);
12698
12699 /* The pixel multiplier can only be updated once the
12700 * DPLL is enabled and the clocks are stable.
12701 *
12702 * So write it again.
12703 */
3e369b76 12704 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12705 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12706 udelay(200);
12707}
12708
12709static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12710 struct intel_shared_dpll *pll)
12711{
12712 struct drm_device *dev = dev_priv->dev;
12713 struct intel_crtc *crtc;
e7b903d2
DV		 12714
12715 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12716 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12717 if (intel_crtc_to_shared_dpll(crtc) == pll)
12718 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12719 }
12720
15bdd4cf
DV		 12721 I915_WRITE(PCH_DPLL(pll->id), 0);
12722 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12723 udelay(200);
12724}
12725
46edb027
DV		 12726static char *ibx_pch_dpll_names[] = {
12727 "PCH DPLL A",
12728 "PCH DPLL B",
12729};
12730
7c74ade1 12731static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12732{
e7b903d2 12733 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12734 int i;
12735
7c74ade1 12736 dev_priv->num_shared_dpll = 2;
ee7b9f93 12737
e72f9fbf 12738 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12739 dev_priv->shared_dplls[i].id = i;
12740 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12741 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12742 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12743 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12744 dev_priv->shared_dplls[i].get_hw_state =
12745 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12746 }
12747}
12748
7c74ade1
DV		 12749static void intel_shared_dpll_init(struct drm_device *dev)
12750{
e7b903d2 12751 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12752
9cd86933
DV		 12753 if (HAS_DDI(dev))
12754 intel_ddi_pll_init(dev);
12755 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12756 ibx_pch_dpll_init(dev);
12757 else
12758 dev_priv->num_shared_dpll = 0;
12759
12760 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12761}
12762
1fc0a8f7
TU		 12763/**
12764 * intel_wm_need_update - Check whether watermarks need updating
12765 * @plane: drm plane
12766 * @state: new plane state
12767 *
12768 * Check current plane state versus the new one to determine whether
12769 * watermarks need to be recalculated.
12770 *
12771 * Returns true or false.
12772 */
12773bool intel_wm_need_update(struct drm_plane *plane,
12774 struct drm_plane_state *state)
12775{
12776 /* Update watermarks on tiling changes. */
12777 if (!plane->state->fb || !state->fb ||
12778 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12779 plane->state->rotation != state->rotation)
12780 return true;
12781
12782 return false;
12783}
12784
6beb8c23
MR		 12785/**
12786 * intel_prepare_plane_fb - Prepare fb for usage on plane
12787 * @plane: drm plane to prepare for
12788 * @fb: framebuffer to prepare for presentation
12789 *
12790 * Prepares a framebuffer for usage on a display plane. Generally this
12791 * involves pinning the underlying object and updating the frontbuffer tracking
12792 * bits. Some older platforms need special physical address handling for
12793 * cursor planes.
12794 *
12795 * Returns 0 on success, negative error code on failure.
12796 */
12797int
12798intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12799 struct drm_framebuffer *fb,
12800 const struct drm_plane_state *new_state)
465c120c
MR		 12801{
12802 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12803 struct intel_plane *intel_plane = to_intel_plane(plane);
12804 enum pipe pipe = intel_plane->pipe;
12805 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12806 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12807 unsigned frontbuffer_bits = 0;
12808 int ret = 0;
465c120c 12809
ea2c67bb 12810 if (!obj)
465c120c
MR		 12811 return 0;
12812
6beb8c23
MR		 12813 switch (plane->type) {
12814 case DRM_PLANE_TYPE_PRIMARY:
12815 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12816 break;
12817 case DRM_PLANE_TYPE_CURSOR:
12818 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12819 break;
12820 case DRM_PLANE_TYPE_OVERLAY:
12821 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12822 break;
12823 }
465c120c 12824
6beb8c23 12825 mutex_lock(&dev->struct_mutex);
465c120c 12826
6beb8c23
MR		 12827 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12828 INTEL_INFO(dev)->cursor_needs_physical) {
12829 int align = IS_I830(dev) ? 16 * 1024 : 256;
12830 ret = i915_gem_object_attach_phys(obj, align);
12831 if (ret)
12832 DRM_DEBUG_KMS("failed to attach phys object\n");
12833 } else {
82bc3b2d 12834 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12835 }
465c120c 12836
6beb8c23
MR		 12837 if (ret == 0)
12838 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12839
4c34574f 12840 mutex_unlock(&dev->struct_mutex);
465c120c 12841
6beb8c23
MR		 12842 return ret;
12843}
12844
38f3ce3a
MR		 12845/**
12846 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12847 * @plane: drm plane to clean up for
12848 * @fb: old framebuffer that was on plane
12849 *
12850 * Cleans up a framebuffer that has just been removed from a plane.
12851 */
12852void
12853intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12854 struct drm_framebuffer *fb,
12855 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12856{
12857 struct drm_device *dev = plane->dev;
12858 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12859
12860 if (WARN_ON(!obj))
12861 return;
12862
12863 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12864 !INTEL_INFO(dev)->cursor_needs_physical) {
12865 mutex_lock(&dev->struct_mutex);
82bc3b2d 12866 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12867 mutex_unlock(&dev->struct_mutex);
12868 }
465c120c
MR		 12869}
12870
12871static int
3c692a41
GP		 12872intel_check_primary_plane(struct drm_plane *plane,
12873 struct intel_plane_state *state)
12874{
32b7eeec
MR		 12875 struct drm_device *dev = plane->dev;
12876 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12877 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12878 struct intel_crtc *intel_crtc;
2b875c22 12879 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12880 struct drm_rect *dest = &state->dst;
12881 struct drm_rect *src = &state->src;
12882 const struct drm_rect *clip = &state->clip;
d8106366 12883 bool can_position = false;
465c120c
MR		 12884 int ret;
12885
ea2c67bb
MR		 12886 crtc = crtc ? crtc : plane->crtc;
12887 intel_crtc = to_intel_crtc(crtc);
12888
d8106366
SJ		 12889 if (INTEL_INFO(dev)->gen >= 9)
12890 can_position = true;
12891
c59cb179
MR		 12892 ret = drm_plane_helper_check_update(plane, crtc, fb,
12893 src, dest, clip,
12894 DRM_PLANE_HELPER_NO_SCALING,
12895 DRM_PLANE_HELPER_NO_SCALING,
d8106366
SJ		 12896 can_position, true,
12897 &state->visible);
c59cb179
MR		 12898 if (ret)
12899 return ret;
465c120c 12900
32b7eeec
MR		 12901 if (intel_crtc->active) {
12902 intel_crtc->atomic.wait_for_flips = true;
12903
12904 /*
12905 * FBC does not work on some platforms for rotated
12906 * planes, so disable it when rotation is not 0 and
12907 * update it when rotation is set back to 0.
12908 *
12909 * FIXME: This is redundant with the fbc update done in
12910 * the primary plane enable function except that that
12911 * one is done too late. We eventually need to unify
12912 * this.
12913 */
12914 if (intel_crtc->primary_enabled &&
12915 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12916 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12917 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12918 intel_crtc->atomic.disable_fbc = true;
12919 }
12920
12921 if (state->visible) {
12922 /*
12923 * BDW signals flip done immediately if the plane
12924 * is disabled, even if the plane enable is already
12925 * armed to occur at the next vblank :(
12926 */
12927 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12928 intel_crtc->atomic.wait_vblank = true;
12929 }
12930
12931 intel_crtc->atomic.fb_bits |=
12932 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12933
12934 intel_crtc->atomic.update_fbc = true;
0fda6568 12935
1fc0a8f7 12936 if (intel_wm_need_update(plane, &state->base))
0fda6568 12937 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12938 }
12939
14af293f
GP		 12940 return 0;
12941}
12942
12943static void
12944intel_commit_primary_plane(struct drm_plane *plane,
12945 struct intel_plane_state *state)
12946{
2b875c22
MR		 12947 struct drm_crtc *crtc = state->base.crtc;
12948 struct drm_framebuffer *fb = state->base.fb;
12949 struct drm_device *dev = plane->dev;
14af293f 12950 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12951 struct intel_crtc *intel_crtc;
14af293f
GP		 12952 struct drm_rect *src = &state->src;
12953
ea2c67bb
MR		 12954 crtc = crtc ? crtc : plane->crtc;
12955 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12956
12957 plane->fb = fb;
9dc806fc
MR		 12958 crtc->x = src->x1 >> 16;
12959 crtc->y = src->y1 >> 16;
ccc759dc 12960
ccc759dc 12961 if (intel_crtc->active) {
ccc759dc 12962 if (state->visible) {
ccc759dc
GP		 12963 /* FIXME: kill this fastboot hack */
12964 intel_update_pipe_size(intel_crtc);
465c120c 12965
ccc759dc 12966 intel_crtc->primary_enabled = true;
465c120c 12967
ccc759dc
GP		 12968 dev_priv->display.update_primary_plane(crtc, plane->fb,
12969 crtc->x, crtc->y);
ccc759dc
GP		 12970 } else {
12971 /*
12972 * If clipping results in a non-visible primary plane,
12973 * we'll disable the primary plane. Note that this is
12974 * a bit different than what happens if userspace
12975 * explicitly disables the plane by passing fb=0
12976 * because plane->fb still gets set and pinned.
12977 */
12978 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12979 }
ccc759dc 12980 }
465c120c
MR		 12981}
12982
32b7eeec 12983static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12984{
32b7eeec 12985 struct drm_device *dev = crtc->dev;
140fd38d 12986 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12988 struct intel_plane *intel_plane;
12989 struct drm_plane *p;
12990 unsigned fb_bits = 0;
12991
12992 /* Track fb's for any planes being disabled */
12993 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12994 intel_plane = to_intel_plane(p);
12995
12996 if (intel_crtc->atomic.disabled_planes &
12997 (1 << drm_plane_index(p))) {
12998 switch (p->type) {
12999 case DRM_PLANE_TYPE_PRIMARY:
13000 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13001 break;
13002 case DRM_PLANE_TYPE_CURSOR:
13003 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13004 break;
13005 case DRM_PLANE_TYPE_OVERLAY:
13006 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13007 break;
13008 }
3c692a41 13009
ea2c67bb
MR		 13010 mutex_lock(&dev->struct_mutex);
13011 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13012 mutex_unlock(&dev->struct_mutex);
13013 }
13014 }
3c692a41 13015
32b7eeec
MR		 13016 if (intel_crtc->atomic.wait_for_flips)
13017 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13018
32b7eeec
MR		 13019 if (intel_crtc->atomic.disable_fbc)
13020 intel_fbc_disable(dev);
3c692a41 13021
32b7eeec
MR		 13022 if (intel_crtc->atomic.pre_disable_primary)
13023 intel_pre_disable_primary(crtc);
3c692a41 13024
32b7eeec
MR		 13025 if (intel_crtc->atomic.update_wm)
13026 intel_update_watermarks(crtc);
3c692a41 13027
32b7eeec 13028 intel_runtime_pm_get(dev_priv);
3c692a41 13029
c34c9ee4
MR		 13030 /* Perform vblank evasion around commit operation */
13031 if (intel_crtc->active)
13032 intel_crtc->atomic.evade =
13033 intel_pipe_update_start(intel_crtc,
13034 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13035}
13036
13037static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13038{
13039 struct drm_device *dev = crtc->dev;
13040 struct drm_i915_private *dev_priv = dev->dev_private;
13041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13042 struct drm_plane *p;
13043
c34c9ee4
MR		 13044 if (intel_crtc->atomic.evade)
13045 intel_pipe_update_end(intel_crtc,
13046 intel_crtc->atomic.start_vbl_count);
3c692a41 13047
140fd38d 13048 intel_runtime_pm_put(dev_priv);
3c692a41 13049
32b7eeec
MR		 13050 if (intel_crtc->atomic.wait_vblank)
13051 intel_wait_for_vblank(dev, intel_crtc->pipe);
13052
13053 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13054
13055 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13056 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13057 intel_fbc_update(dev);
ccc759dc 13058 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13059 }
3c692a41 13060
32b7eeec
MR		 13061 if (intel_crtc->atomic.post_enable_primary)
13062 intel_post_enable_primary(crtc);
3c692a41 13063
32b7eeec
MR		 13064 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13065 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13066 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13067 false, false);
13068
13069 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13070}
13071
cf4c7c12 13072/**
4a3b8769
MR		 13073 * intel_plane_destroy - destroy a plane
13074 * @plane: plane to destroy
cf4c7c12 13075 *
4a3b8769
MR		 13076 * Common destruction function for all types of planes (primary, cursor,
13077 * sprite).
cf4c7c12 13078 */
4a3b8769 13079void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13080{
13081 struct intel_plane *intel_plane = to_intel_plane(plane);
13082 drm_plane_cleanup(plane);
13083 kfree(intel_plane);
13084}
13085
65a3fea0 13086const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13087 .update_plane = drm_atomic_helper_update_plane,
13088 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13089 .destroy = intel_plane_destroy,
c196e1d6 13090 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13091 .atomic_get_property = intel_plane_atomic_get_property,
13092 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13093 .atomic_duplicate_state = intel_plane_duplicate_state,
13094 .atomic_destroy_state = intel_plane_destroy_state,
13095
465c120c
MR		 13096};
13097
13098static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13099 int pipe)
13100{
13101 struct intel_plane *primary;
8e7d688b 13102 struct intel_plane_state *state;
465c120c
MR		 13103 const uint32_t *intel_primary_formats;
13104 int num_formats;
13105
13106 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13107 if (primary == NULL)
13108 return NULL;
13109
8e7d688b
MR		 13110 state = intel_create_plane_state(&primary->base);
13111 if (!state) {
ea2c67bb
MR		 13112 kfree(primary);
13113 return NULL;
13114 }
8e7d688b 13115 primary->base.state = &state->base;
ea2c67bb 13116
465c120c
MR		 13117 primary->can_scale = false;
13118 primary->max_downscale = 1;
549e2bfb 13119 state->scaler_id = -1;
465c120c
MR		 13120 primary->pipe = pipe;
13121 primary->plane = pipe;
c59cb179
MR		 13122 primary->check_plane = intel_check_primary_plane;
13123 primary->commit_plane = intel_commit_primary_plane;
08e221fb 13124 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13125 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13126 primary->plane = !pipe;
13127
13128 if (INTEL_INFO(dev)->gen <= 3) {
13129 intel_primary_formats = intel_primary_formats_gen2;
13130 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13131 } else {
13132 intel_primary_formats = intel_primary_formats_gen4;
13133 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13134 }
13135
13136 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13137 &intel_plane_funcs,
465c120c
MR		 13138 intel_primary_formats, num_formats,
13139 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13140
3b7a5119
SJ		 13141 if (INTEL_INFO(dev)->gen >= 4)
13142 intel_create_rotation_property(dev, primary);
48404c1e 13143
ea2c67bb
MR		 13144 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13145
465c120c
MR		 13146 return &primary->base;
13147}
13148
3b7a5119
SJ		 13149void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13150{
13151 if (!dev->mode_config.rotation_property) {
13152 unsigned long flags = BIT(DRM_ROTATE_0) |
13153 BIT(DRM_ROTATE_180);
13154
13155 if (INTEL_INFO(dev)->gen >= 9)
13156 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13157
13158 dev->mode_config.rotation_property =
13159 drm_mode_create_rotation_property(dev, flags);
13160 }
13161 if (dev->mode_config.rotation_property)
13162 drm_object_attach_property(&plane->base.base,
13163 dev->mode_config.rotation_property,
13164 plane->base.state->rotation);
13165}
13166
3d7d6510 13167static int
852e787c
GP		 13168intel_check_cursor_plane(struct drm_plane *plane,
13169 struct intel_plane_state *state)
3d7d6510 13170{
2b875c22 13171 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13172 struct drm_device *dev = plane->dev;
2b875c22 13173 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13174 struct drm_rect *dest = &state->dst;
13175 struct drm_rect *src = &state->src;
13176 const struct drm_rect *clip = &state->clip;
757f9a3e 13177 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13178 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13179 unsigned stride;
13180 int ret;
3d7d6510 13181
ea2c67bb
MR		 13182 crtc = crtc ? crtc : plane->crtc;
13183 intel_crtc = to_intel_crtc(crtc);
13184
757f9a3e 13185 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13186 src, dest, clip,
3d7d6510
MR		 13187 DRM_PLANE_HELPER_NO_SCALING,
13188 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13189 true, true, &state->visible);
757f9a3e
GP		 13190 if (ret)
13191 return ret;
13192
13193
13194 /* if we want to turn off the cursor ignore width and height */
13195 if (!obj)
32b7eeec 13196 goto finish;
757f9a3e 13197
757f9a3e 13198 /* Check for which cursor types we support */
ea2c67bb
MR		 13199 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13200 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13201 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13202 return -EINVAL;
13203 }
13204
ea2c67bb
MR		 13205 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13206 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13207 DRM_DEBUG_KMS("buffer is too small\n");
13208 return -ENOMEM;
13209 }
13210
3a656b54 13211 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13212 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13213 ret = -EINVAL;
13214 }
757f9a3e 13215
32b7eeec
MR		 13216finish:
13217 if (intel_crtc->active) {
3749f463 13218 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13219 intel_crtc->atomic.update_wm = true;
13220
13221 intel_crtc->atomic.fb_bits |=
13222 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13223 }
13224
757f9a3e 13225 return ret;
852e787c 13226}
3d7d6510 13227
f4a2cf29 13228static void
852e787c
GP		 13229intel_commit_cursor_plane(struct drm_plane *plane,
13230 struct intel_plane_state *state)
13231{
2b875c22 13232 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13233 struct drm_device *dev = plane->dev;
13234 struct intel_crtc *intel_crtc;
2b875c22 13235 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13236 uint32_t addr;
852e787c 13237
ea2c67bb
MR		 13238 crtc = crtc ? crtc : plane->crtc;
13239 intel_crtc = to_intel_crtc(crtc);
13240
2b875c22 13241 plane->fb = state->base.fb;
ea2c67bb
MR		 13242 crtc->cursor_x = state->base.crtc_x;
13243 crtc->cursor_y = state->base.crtc_y;
13244
a912f12f
GP		 13245 if (intel_crtc->cursor_bo == obj)
13246 goto update;
4ed91096 13247
f4a2cf29 13248 if (!obj)
a912f12f 13249 addr = 0;
f4a2cf29 13250 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13251 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13252 else
a912f12f 13253 addr = obj->phys_handle->busaddr;
852e787c 13254
a912f12f
GP		 13255 intel_crtc->cursor_addr = addr;
13256 intel_crtc->cursor_bo = obj;
13257update:
852e787c 13258
32b7eeec 13259 if (intel_crtc->active)
a912f12f 13260 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13261}
13262
3d7d6510
MR		 13263static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13264 int pipe)
13265{
13266 struct intel_plane *cursor;
8e7d688b 13267 struct intel_plane_state *state;
3d7d6510
MR		 13268
13269 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13270 if (cursor == NULL)
13271 return NULL;
13272
8e7d688b
MR		 13273 state = intel_create_plane_state(&cursor->base);
13274 if (!state) {
ea2c67bb
MR		 13275 kfree(cursor);
13276 return NULL;
13277 }
8e7d688b 13278 cursor->base.state = &state->base;
ea2c67bb 13279
3d7d6510
MR		 13280 cursor->can_scale = false;
13281 cursor->max_downscale = 1;
13282 cursor->pipe = pipe;
13283 cursor->plane = pipe;
549e2bfb 13284 state->scaler_id = -1;
c59cb179
MR		 13285 cursor->check_plane = intel_check_cursor_plane;
13286 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 13287
13288 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13289 &intel_plane_funcs,
3d7d6510
MR		 13290 intel_cursor_formats,
13291 ARRAY_SIZE(intel_cursor_formats),
13292 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13293
13294 if (INTEL_INFO(dev)->gen >= 4) {
13295 if (!dev->mode_config.rotation_property)
13296 dev->mode_config.rotation_property =
13297 drm_mode_create_rotation_property(dev,
13298 BIT(DRM_ROTATE_0) |
13299 BIT(DRM_ROTATE_180));
13300 if (dev->mode_config.rotation_property)
13301 drm_object_attach_property(&cursor->base.base,
13302 dev->mode_config.rotation_property,
8e7d688b 13303 state->base.rotation);
4398ad45
VS		 13304 }
13305
ea2c67bb
MR		 13306 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13307
3d7d6510
MR		 13308 return &cursor->base;
13309}
13310
549e2bfb
CK		 13311static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13312 struct intel_crtc_state *crtc_state)
13313{
13314 int i;
13315 struct intel_scaler *intel_scaler;
13316 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13317
13318 for (i = 0; i < intel_crtc->num_scalers; i++) {
13319 intel_scaler = &scaler_state->scalers[i];
13320 intel_scaler->in_use = 0;
13321 intel_scaler->id = i;
13322
13323 intel_scaler->mode = PS_SCALER_MODE_DYN;
13324 }
13325
13326 scaler_state->scaler_id = -1;
13327}
13328
b358d0a6 13329static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13330{
fbee40df 13331 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13332 struct intel_crtc *intel_crtc;
f5de6e07 13333 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13334 struct drm_plane *primary = NULL;
13335 struct drm_plane *cursor = NULL;
465c120c 13336 int i, ret;
79e53945 13337
955382f3 13338 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13339 if (intel_crtc == NULL)
13340 return;
13341
f5de6e07
ACO		 13342 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13343 if (!crtc_state)
13344 goto fail;
13345 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13346 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13347
549e2bfb
CK		 13348 /* initialize shared scalers */
13349 if (INTEL_INFO(dev)->gen >= 9) {
13350 if (pipe == PIPE_C)
13351 intel_crtc->num_scalers = 1;
13352 else
13353 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13354
13355 skl_init_scalers(dev, intel_crtc, crtc_state);
13356 }
13357
465c120c 13358 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13359 if (!primary)
13360 goto fail;
13361
13362 cursor = intel_cursor_plane_create(dev, pipe);
13363 if (!cursor)
13364 goto fail;
13365
465c120c 13366 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13367 cursor, &intel_crtc_funcs);
13368 if (ret)
13369 goto fail;
79e53945
JB		 13370
13371 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13372 for (i = 0; i < 256; i++) {
13373 intel_crtc->lut_r[i] = i;
13374 intel_crtc->lut_g[i] = i;
13375 intel_crtc->lut_b[i] = i;
13376 }
13377
1f1c2e24
VS		 13378 /*
13379 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13380 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13381 */
80824003
JB		 13382 intel_crtc->pipe = pipe;
13383 intel_crtc->plane = pipe;
3a77c4c4 13384 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13385 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13386 intel_crtc->plane = !pipe;
80824003
JB		 13387 }
13388
4b0e333e
CW		 13389 intel_crtc->cursor_base = ~0;
13390 intel_crtc->cursor_cntl = ~0;
dc41c154 13391 intel_crtc->cursor_size = ~0;
8d7849db 13392
22fd0fab
JB		 13393 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13394 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13395 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13396 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13397
9362c7c5
ACO		 13398 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13399
79e53945 13400 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13401
13402 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13403 return;
13404
13405fail:
13406 if (primary)
13407 drm_plane_cleanup(primary);
13408 if (cursor)
13409 drm_plane_cleanup(cursor);
f5de6e07 13410 kfree(crtc_state);
3d7d6510 13411 kfree(intel_crtc);
79e53945
JB		 13412}
13413
752aa88a
JB		 13414enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13415{
13416 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13417 struct drm_device *dev = connector->base.dev;
752aa88a 13418
51fd371b 13419 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13420
d3babd3f 13421 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13422 return INVALID_PIPE;
13423
13424 return to_intel_crtc(encoder->crtc)->pipe;
13425}
13426
08d7b3d1 13427int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13428 struct drm_file *file)
08d7b3d1 13429{
08d7b3d1 13430 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13431 struct drm_crtc *drmmode_crtc;
c05422d5 13432 struct intel_crtc *crtc;
08d7b3d1 13433
7707e653 13434 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13435
7707e653 13436 if (!drmmode_crtc) {
08d7b3d1 13437 DRM_ERROR("no such CRTC id\n");
3f2c2057 13438 return -ENOENT;
08d7b3d1
CW		 13439 }
13440
7707e653 13441 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13442 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13443
c05422d5 13444 return 0;
08d7b3d1
CW		 13445}
13446
66a9278e 13447static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13448{
66a9278e
DV		 13449 struct drm_device *dev = encoder->base.dev;
13450 struct intel_encoder *source_encoder;
79e53945 13451 int index_mask = 0;
79e53945
JB		 13452 int entry = 0;
13453
b2784e15 13454 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13455 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13456 index_mask |= (1 << entry);
13457
79e53945
JB		 13458 entry++;
13459 }
4ef69c7a 13460
79e53945
JB		 13461 return index_mask;
13462}
13463
4d302442
CW		 13464static bool has_edp_a(struct drm_device *dev)
13465{
13466 struct drm_i915_private *dev_priv = dev->dev_private;
13467
13468 if (!IS_MOBILE(dev))
13469 return false;
13470
13471 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13472 return false;
13473
e3589908 13474 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13475 return false;
13476
13477 return true;
13478}
13479
84b4e042
JB		 13480static bool intel_crt_present(struct drm_device *dev)
13481{
13482 struct drm_i915_private *dev_priv = dev->dev_private;
13483
884497ed
DL		 13484 if (INTEL_INFO(dev)->gen >= 9)
13485 return false;
13486
cf404ce4 13487 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13488 return false;
13489
13490 if (IS_CHERRYVIEW(dev))
13491 return false;
13492
13493 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13494 return false;
13495
13496 return true;
13497}
13498
79e53945
JB		 13499static void intel_setup_outputs(struct drm_device *dev)
13500{
725e30ad 13501 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13502 struct intel_encoder *encoder;
cb0953d7 13503 bool dpd_is_edp = false;
79e53945 13504
c9093354 13505 intel_lvds_init(dev);
79e53945 13506
84b4e042 13507 if (intel_crt_present(dev))
79935fca 13508 intel_crt_init(dev);
cb0953d7 13509
c776eb2e
VK		 13510 if (IS_BROXTON(dev)) {
13511 /*
13512 * FIXME: Broxton doesn't support port detection via the
13513 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13514 * detect the ports.
13515 */
13516 intel_ddi_init(dev, PORT_A);
13517 intel_ddi_init(dev, PORT_B);
13518 intel_ddi_init(dev, PORT_C);
13519 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13520 int found;
13521
de31facd
JB		 13522 /*
13523 * Haswell uses DDI functions to detect digital outputs.
13524 * On SKL pre-D0 the strap isn't connected, so we assume
13525 * it's there.
13526 */
0e72a5b5 13527 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13528 /* WaIgnoreDDIAStrap: skl */
13529 if (found ||
13530 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13531 intel_ddi_init(dev, PORT_A);
13532
13533 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13534 * register */
13535 found = I915_READ(SFUSE_STRAP);
13536
13537 if (found & SFUSE_STRAP_DDIB_DETECTED)
13538 intel_ddi_init(dev, PORT_B);
13539 if (found & SFUSE_STRAP_DDIC_DETECTED)
13540 intel_ddi_init(dev, PORT_C);
13541 if (found & SFUSE_STRAP_DDID_DETECTED)
13542 intel_ddi_init(dev, PORT_D);
13543 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13544 int found;
5d8a7752 13545 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13546
13547 if (has_edp_a(dev))
13548 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13549
dc0fa718 13550 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13551 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13552 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13553 if (!found)
e2debe91 13554 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13555 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13556 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13557 }
13558
dc0fa718 13559 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13560 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13561
dc0fa718 13562 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13563 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13564
5eb08b69 13565 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13566 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13567
270b3042 13568 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13569 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13570 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13571 /*
13572 * The DP_DETECTED bit is the latched state of the DDC
13573 * SDA pin at boot. However since eDP doesn't require DDC
13574 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13575 * eDP ports may have been muxed to an alternate function.
13576 * Thus we can't rely on the DP_DETECTED bit alone to detect
13577 * eDP ports. Consult the VBT as well as DP_DETECTED to
13578 * detect eDP ports.
13579 */
d2182a66
VS		 13580 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13581 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13582 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13583 PORT_B);
e17ac6db
VS		 13584 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13585 intel_dp_is_edp(dev, PORT_B))
13586 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13587
d2182a66
VS		 13588 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13589 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13590 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13591 PORT_C);
e17ac6db
VS		 13592 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13593 intel_dp_is_edp(dev, PORT_C))
13594 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13595
9418c1f1 13596 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13597 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13598 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13599 PORT_D);
e17ac6db
VS		 13600 /* eDP not supported on port D, so don't check VBT */
13601 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13602 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13603 }
13604
3cfca973 13605 intel_dsi_init(dev);
103a196f 13606 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13607 bool found = false;
7d57382e 13608
e2debe91 13609 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13610 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13611 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13612 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13613 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13614 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13615 }
27185ae1 13616
e7281eab 13617 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13618 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13619 }
13520b05
KH		 13620
13621 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13622
e2debe91 13623 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13624 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13625 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13626 }
27185ae1 13627
e2debe91 13628 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13629
b01f2c3a
JB		 13630 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13631 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13632 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13633 }
e7281eab 13634 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13635 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13636 }
27185ae1 13637
b01f2c3a 13638 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13639 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13640 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13641 } else if (IS_GEN2(dev))
79e53945
JB		 13642 intel_dvo_init(dev);
13643
103a196f 13644 if (SUPPORTS_TV(dev))
79e53945
JB		 13645 intel_tv_init(dev);
13646
0bc12bcb 13647 intel_psr_init(dev);
7c8f8a70 13648
b2784e15 13649 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13650 encoder->base.possible_crtcs = encoder->crtc_mask;
13651 encoder->base.possible_clones =
66a9278e 13652 intel_encoder_clones(encoder);
79e53945 13653 }
47356eb6 13654
dde86e2d 13655 intel_init_pch_refclk(dev);
270b3042
DV		 13656
13657 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13658}
13659
13660static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13661{
60a5ca01 13662 struct drm_device *dev = fb->dev;
79e53945 13663 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13664
ef2d633e 13665 drm_framebuffer_cleanup(fb);
60a5ca01 13666 mutex_lock(&dev->struct_mutex);
ef2d633e 13667 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13668 drm_gem_object_unreference(&intel_fb->obj->base);
13669 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13670 kfree(intel_fb);
13671}
13672
13673static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13674 struct drm_file *file,
79e53945
JB		 13675 unsigned int *handle)
13676{
13677 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13678 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13679
05394f39 13680 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13681}
13682
13683static const struct drm_framebuffer_funcs intel_fb_funcs = {
13684 .destroy = intel_user_framebuffer_destroy,
13685 .create_handle = intel_user_framebuffer_create_handle,
13686};
13687
b321803d
DL		 13688static
13689u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13690 uint32_t pixel_format)
13691{
13692 u32 gen = INTEL_INFO(dev)->gen;
13693
13694 if (gen >= 9) {
13695 /* "The stride in bytes must not exceed the of the size of 8K
13696 * pixels and 32K bytes."
13697 */
13698 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13699 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13700 return 32*1024;
13701 } else if (gen >= 4) {
13702 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13703 return 16*1024;
13704 else
13705 return 32*1024;
13706 } else if (gen >= 3) {
13707 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13708 return 8*1024;
13709 else
13710 return 16*1024;
13711 } else {
13712 /* XXX DSPC is limited to 4k tiled */
13713 return 8*1024;
13714 }
13715}
13716
b5ea642a
DV		 13717static int intel_framebuffer_init(struct drm_device *dev,
13718 struct intel_framebuffer *intel_fb,
13719 struct drm_mode_fb_cmd2 *mode_cmd,
13720 struct drm_i915_gem_object *obj)
79e53945 13721{
6761dd31 13722 unsigned int aligned_height;
79e53945 13723 int ret;
b321803d 13724 u32 pitch_limit, stride_alignment;
79e53945 13725
dd4916c5
DV		 13726 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13727
2a80eada
DV		 13728 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13729 /* Enforce that fb modifier and tiling mode match, but only for
13730 * X-tiled. This is needed for FBC. */
13731 if (!!(obj->tiling_mode == I915_TILING_X) !=
13732 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13733 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13734 return -EINVAL;
13735 }
13736 } else {
13737 if (obj->tiling_mode == I915_TILING_X)
13738 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13739 else if (obj->tiling_mode == I915_TILING_Y) {
13740 DRM_DEBUG("No Y tiling for legacy addfb\n");
13741 return -EINVAL;
13742 }
13743 }
13744
9a8f0a12
TU		 13745 /* Passed in modifier sanity checking. */
13746 switch (mode_cmd->modifier[0]) {
13747 case I915_FORMAT_MOD_Y_TILED:
13748 case I915_FORMAT_MOD_Yf_TILED:
13749 if (INTEL_INFO(dev)->gen < 9) {
13750 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13751 mode_cmd->modifier[0]);
13752 return -EINVAL;
13753 }
13754 case DRM_FORMAT_MOD_NONE:
13755 case I915_FORMAT_MOD_X_TILED:
13756 break;
13757 default:
c0f40428
JB		 13758 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13759 mode_cmd->modifier[0]);
57cd6508 13760 return -EINVAL;
c16ed4be 13761 }
57cd6508 13762
b321803d
DL		 13763 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13764 mode_cmd->pixel_format);
13765 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13766 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13767 mode_cmd->pitches[0], stride_alignment);
57cd6508 13768 return -EINVAL;
c16ed4be 13769 }
57cd6508 13770
b321803d
DL		 13771 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13772 mode_cmd->pixel_format);
a35cdaa0 13773 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13774 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13775 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13776 "tiled" : "linear",
a35cdaa0 13777 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13778 return -EINVAL;
c16ed4be 13779 }
5d7bd705 13780
2a80eada 13781 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13782 mode_cmd->pitches[0] != obj->stride) {
13783 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13784 mode_cmd->pitches[0], obj->stride);
5d7bd705 13785 return -EINVAL;
c16ed4be 13786 }
5d7bd705 13787
57779d06 13788 /* Reject formats not supported by any plane early. */
308e5bcb 13789 switch (mode_cmd->pixel_format) {
57779d06 13790 case DRM_FORMAT_C8:
04b3924d
VS		 13791 case DRM_FORMAT_RGB565:
13792 case DRM_FORMAT_XRGB8888:
13793 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13794 break;
13795 case DRM_FORMAT_XRGB1555:
13796 case DRM_FORMAT_ARGB1555:
c16ed4be 13797 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13798 DRM_DEBUG("unsupported pixel format: %s\n",
13799 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13800 return -EINVAL;
c16ed4be 13801 }
57779d06
VS		 13802 break;
13803 case DRM_FORMAT_XBGR8888:
13804 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13805 case DRM_FORMAT_XRGB2101010:
13806 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13807 case DRM_FORMAT_XBGR2101010:
13808 case DRM_FORMAT_ABGR2101010:
c16ed4be 13809 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13810 DRM_DEBUG("unsupported pixel format: %s\n",
13811 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13812 return -EINVAL;
c16ed4be 13813 }
b5626747 13814 break;
04b3924d
VS		 13815 case DRM_FORMAT_YUYV:
13816 case DRM_FORMAT_UYVY:
13817 case DRM_FORMAT_YVYU:
13818 case DRM_FORMAT_VYUY:
c16ed4be 13819 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13820 DRM_DEBUG("unsupported pixel format: %s\n",
13821 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13822 return -EINVAL;
c16ed4be 13823 }
57cd6508
CW		 13824 break;
13825 default:
4ee62c76
VS		 13826 DRM_DEBUG("unsupported pixel format: %s\n",
13827 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13828 return -EINVAL;
13829 }
13830
90f9a336
VS		 13831 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13832 if (mode_cmd->offsets[0] != 0)
13833 return -EINVAL;
13834
ec2c981e 13835 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13836 mode_cmd->pixel_format,
13837 mode_cmd->modifier[0]);
53155c0a
DV		 13838 /* FIXME drm helper for size checks (especially planar formats)? */
13839 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13840 return -EINVAL;
13841
c7d73f6a
DV		 13842 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13843 intel_fb->obj = obj;
80075d49 13844 intel_fb->obj->framebuffer_references++;
c7d73f6a 13845
79e53945
JB		 13846 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13847 if (ret) {
13848 DRM_ERROR("framebuffer init failed %d\n", ret);
13849 return ret;
13850 }
13851
79e53945
JB		 13852 return 0;
13853}
13854
79e53945
JB		 13855static struct drm_framebuffer *
13856intel_user_framebuffer_create(struct drm_device *dev,
13857 struct drm_file *filp,
308e5bcb 13858 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13859{
05394f39 13860 struct drm_i915_gem_object *obj;
79e53945 13861
308e5bcb
JB		 13862 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13863 mode_cmd->handles[0]));
c8725226 13864 if (&obj->base == NULL)
cce13ff7 13865 return ERR_PTR(-ENOENT);
79e53945 13866
d2dff872 13867 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13868}
13869
4520f53a 13870#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13871static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13872{
13873}
13874#endif
13875
79e53945 13876static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13877 .fb_create = intel_user_framebuffer_create,
0632fef6 13878 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13879 .atomic_check = intel_atomic_check,
13880 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13881};
13882
e70236a8
JB		 13883/* Set up chip specific display functions */
13884static void intel_init_display(struct drm_device *dev)
13885{
13886 struct drm_i915_private *dev_priv = dev->dev_private;
13887
ee9300bb
DV		 13888 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13889 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13890 else if (IS_CHERRYVIEW(dev))
13891 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13892 else if (IS_VALLEYVIEW(dev))
13893 dev_priv->display.find_dpll = vlv_find_best_dpll;
13894 else if (IS_PINEVIEW(dev))
13895 dev_priv->display.find_dpll = pnv_find_best_dpll;
13896 else
13897 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13898
bc8d7dff
DL		 13899 if (INTEL_INFO(dev)->gen >= 9) {
13900 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13901 dev_priv->display.get_initial_plane_config =
13902 skylake_get_initial_plane_config;
bc8d7dff
DL		 13903 dev_priv->display.crtc_compute_clock =
13904 haswell_crtc_compute_clock;
13905 dev_priv->display.crtc_enable = haswell_crtc_enable;
13906 dev_priv->display.crtc_disable = haswell_crtc_disable;
13907 dev_priv->display.off = ironlake_crtc_off;
13908 dev_priv->display.update_primary_plane =
13909 skylake_update_primary_plane;
13910 } else if (HAS_DDI(dev)) {
0e8ffe1b 13911 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13912 dev_priv->display.get_initial_plane_config =
13913 ironlake_get_initial_plane_config;
797d0259
ACO		 13914 dev_priv->display.crtc_compute_clock =
13915 haswell_crtc_compute_clock;
4f771f10
PZ		 13916 dev_priv->display.crtc_enable = haswell_crtc_enable;
13917 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13918 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13919 dev_priv->display.update_primary_plane =
13920 ironlake_update_primary_plane;
09b4ddf9 13921 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13922 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13923 dev_priv->display.get_initial_plane_config =
13924 ironlake_get_initial_plane_config;
3fb37703
ACO		 13925 dev_priv->display.crtc_compute_clock =
13926 ironlake_crtc_compute_clock;
76e5a89c
DV		 13927 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13928 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13929 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13930 dev_priv->display.update_primary_plane =
13931 ironlake_update_primary_plane;
89b667f8
JB		 13932 } else if (IS_VALLEYVIEW(dev)) {
13933 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13934 dev_priv->display.get_initial_plane_config =
13935 i9xx_get_initial_plane_config;
d6dfee7a 13936 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13937 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13938 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13939 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13940 dev_priv->display.update_primary_plane =
13941 i9xx_update_primary_plane;
f564048e 13942 } else {
0e8ffe1b 13943 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13944 dev_priv->display.get_initial_plane_config =
13945 i9xx_get_initial_plane_config;
d6dfee7a 13946 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13947 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13948 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13949 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13950 dev_priv->display.update_primary_plane =
13951 i9xx_update_primary_plane;
f564048e 13952 }
e70236a8 13953
e70236a8 13954 /* Returns the core display clock speed */
1652d19e
VS		 13955 if (IS_SKYLAKE(dev))
13956 dev_priv->display.get_display_clock_speed =
13957 skylake_get_display_clock_speed;
13958 else if (IS_BROADWELL(dev))
13959 dev_priv->display.get_display_clock_speed =
13960 broadwell_get_display_clock_speed;
13961 else if (IS_HASWELL(dev))
13962 dev_priv->display.get_display_clock_speed =
13963 haswell_get_display_clock_speed;
13964 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 13965 dev_priv->display.get_display_clock_speed =
13966 valleyview_get_display_clock_speed;
b37a6434
VS		 13967 else if (IS_GEN5(dev))
13968 dev_priv->display.get_display_clock_speed =
13969 ilk_get_display_clock_speed;
a7c66cd8
VS		 13970 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
13971 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13972 dev_priv->display.get_display_clock_speed =
13973 i945_get_display_clock_speed;
13974 else if (IS_I915G(dev))
13975 dev_priv->display.get_display_clock_speed =
13976 i915_get_display_clock_speed;
257a7ffc 13977 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13978 dev_priv->display.get_display_clock_speed =
13979 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13980 else if (IS_PINEVIEW(dev))
13981 dev_priv->display.get_display_clock_speed =
13982 pnv_get_display_clock_speed;
e70236a8
JB		 13983 else if (IS_I915GM(dev))
13984 dev_priv->display.get_display_clock_speed =
13985 i915gm_get_display_clock_speed;
13986 else if (IS_I865G(dev))
13987 dev_priv->display.get_display_clock_speed =
13988 i865_get_display_clock_speed;
f0f8a9ce 13989 else if (IS_I85X(dev))
e70236a8
JB		 13990 dev_priv->display.get_display_clock_speed =
13991 i855_get_display_clock_speed;
13992 else /* 852, 830 */
13993 dev_priv->display.get_display_clock_speed =
13994 i830_get_display_clock_speed;
13995
7c10a2b5 13996 if (IS_GEN5(dev)) {
3bb11b53 13997 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13998 } else if (IS_GEN6(dev)) {
13999 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14000 } else if (IS_IVYBRIDGE(dev)) {
14001 /* FIXME: detect B0+ stepping and use auto training */
14002 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14003 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14004 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14005 } else if (IS_VALLEYVIEW(dev)) {
14006 dev_priv->display.modeset_global_resources =
14007 valleyview_modeset_global_resources;
e70236a8 14008 }
8c9f3aaf 14009
8c9f3aaf
JB		 14010 switch (INTEL_INFO(dev)->gen) {
14011 case 2:
14012 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14013 break;
14014
14015 case 3:
14016 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14017 break;
14018
14019 case 4:
14020 case 5:
14021 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14022 break;
14023
14024 case 6:
14025 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14026 break;
7c9017e5 14027 case 7:
4e0bbc31 14028 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14029 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14030 break;
830c81db 14031 case 9:
ba343e02
TU		 14032 /* Drop through - unsupported since execlist only. */
14033 default:
14034 /* Default just returns -ENODEV to indicate unsupported */
14035 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14036 }
7bd688cd
JN		 14037
14038 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14039
14040 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14041}
14042
b690e96c
JB		 14043/*
14044 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14045 * resume, or other times. This quirk makes sure that's the case for
14046 * affected systems.
14047 */
0206e353 14048static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14049{
14050 struct drm_i915_private *dev_priv = dev->dev_private;
14051
14052 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14053 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14054}
14055
b6b5d049
VS		 14056static void quirk_pipeb_force(struct drm_device *dev)
14057{
14058 struct drm_i915_private *dev_priv = dev->dev_private;
14059
14060 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14061 DRM_INFO("applying pipe b force quirk\n");
14062}
14063
435793df
KP		 14064/*
14065 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14066 */
14067static void quirk_ssc_force_disable(struct drm_device *dev)
14068{
14069 struct drm_i915_private *dev_priv = dev->dev_private;
14070 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14071 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14072}
14073
4dca20ef 14074/*
5a15ab5b
CE		 14075 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14076 * brightness value
4dca20ef
CE		 14077 */
14078static void quirk_invert_brightness(struct drm_device *dev)
14079{
14080 struct drm_i915_private *dev_priv = dev->dev_private;
14081 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14082 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14083}
14084
9c72cc6f
SD		 14085/* Some VBT's incorrectly indicate no backlight is present */
14086static void quirk_backlight_present(struct drm_device *dev)
14087{
14088 struct drm_i915_private *dev_priv = dev->dev_private;
14089 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14090 DRM_INFO("applying backlight present quirk\n");
14091}
14092
b690e96c
JB		 14093struct intel_quirk {
14094 int device;
14095 int subsystem_vendor;
14096 int subsystem_device;
14097 void (*hook)(struct drm_device *dev);
14098};
14099
5f85f176
EE		 14100/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14101struct intel_dmi_quirk {
14102 void (*hook)(struct drm_device *dev);
14103 const struct dmi_system_id (*dmi_id_list)[];
14104};
14105
14106static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14107{
14108 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14109 return 1;
14110}
14111
14112static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14113 {
14114 .dmi_id_list = &(const struct dmi_system_id[]) {
14115 {
14116 .callback = intel_dmi_reverse_brightness,
14117 .ident = "NCR Corporation",
14118 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14119 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14120 },
14121 },
14122 { } /* terminating entry */
14123 },
14124 .hook = quirk_invert_brightness,
14125 },
14126};
14127
c43b5634 14128static struct intel_quirk intel_quirks[] = {
b690e96c 14129 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14130 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14131
b690e96c
JB		 14132 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14133 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14134
b690e96c
JB		 14135 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14136 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14137
5f080c0f
VS		 14138 /* 830 needs to leave pipe A & dpll A up */
14139 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14140
b6b5d049
VS		 14141 /* 830 needs to leave pipe B & dpll B up */
14142 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14143
435793df
KP		 14144 /* Lenovo U160 cannot use SSC on LVDS */
14145 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14146
14147 /* Sony Vaio Y cannot use SSC on LVDS */
14148 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14149
be505f64
AH		 14150 /* Acer Aspire 5734Z must invert backlight brightness */
14151 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14152
14153 /* Acer/eMachines G725 */
14154 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14155
14156 /* Acer/eMachines e725 */
14157 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14158
14159 /* Acer/Packard Bell NCL20 */
14160 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14161
14162 /* Acer Aspire 4736Z */
14163 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14164
14165 /* Acer Aspire 5336 */
14166 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14167
14168 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14169 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14170
dfb3d47b
SD		 14171 /* Acer C720 Chromebook (Core i3 4005U) */
14172 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14173
b2a9601c 14174 /* Apple Macbook 2,1 (Core 2 T7400) */
14175 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14176
d4967d8c
SD		 14177 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14178 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14179
14180 /* HP Chromebook 14 (Celeron 2955U) */
14181 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14182
14183 /* Dell Chromebook 11 */
14184 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14185};
14186
14187static void intel_init_quirks(struct drm_device *dev)
14188{
14189 struct pci_dev *d = dev->pdev;
14190 int i;
14191
14192 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14193 struct intel_quirk *q = &intel_quirks[i];
14194
14195 if (d->device == q->device &&
14196 (d->subsystem_vendor == q->subsystem_vendor ||
14197 q->subsystem_vendor == PCI_ANY_ID) &&
14198 (d->subsystem_device == q->subsystem_device ||
14199 q->subsystem_device == PCI_ANY_ID))
14200 q->hook(dev);
14201 }
5f85f176
EE		 14202 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14203 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14204 intel_dmi_quirks[i].hook(dev);
14205 }
b690e96c
JB		 14206}
14207
9cce37f4
JB		 14208/* Disable the VGA plane that we never use */
14209static void i915_disable_vga(struct drm_device *dev)
14210{
14211 struct drm_i915_private *dev_priv = dev->dev_private;
14212 u8 sr1;
766aa1c4 14213 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14214
2b37c616 14215 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14216 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14217 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14218 sr1 = inb(VGA_SR_DATA);
14219 outb(sr1 | 1<<5, VGA_SR_DATA);
14220 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14221 udelay(300);
14222
01f5a626 14223 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14224 POSTING_READ(vga_reg);
14225}
14226
f817586c
DV		 14227void intel_modeset_init_hw(struct drm_device *dev)
14228{
a8f78b58
ED		 14229 intel_prepare_ddi(dev);
14230
f8bf63fd
VS		 14231 if (IS_VALLEYVIEW(dev))
14232 vlv_update_cdclk(dev);
14233
f817586c
DV		 14234 intel_init_clock_gating(dev);
14235
8090c6b9 14236 intel_enable_gt_powersave(dev);
f817586c
DV		 14237}
14238
79e53945
JB		 14239void intel_modeset_init(struct drm_device *dev)
14240{
652c393a 14241 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14242 int sprite, ret;
8cc87b75 14243 enum pipe pipe;
46f297fb 14244 struct intel_crtc *crtc;
79e53945
JB		 14245
14246 drm_mode_config_init(dev);
14247
14248 dev->mode_config.min_width = 0;
14249 dev->mode_config.min_height = 0;
14250
019d96cb
DA		 14251 dev->mode_config.preferred_depth = 24;
14252 dev->mode_config.prefer_shadow = 1;
14253
25bab385
TU		 14254 dev->mode_config.allow_fb_modifiers = true;
14255
e6ecefaa 14256 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14257
b690e96c
JB		 14258 intel_init_quirks(dev);
14259
1fa61106
ED		 14260 intel_init_pm(dev);
14261
e3c74757
BW		 14262 if (INTEL_INFO(dev)->num_pipes == 0)
14263 return;
14264
e70236a8 14265 intel_init_display(dev);
7c10a2b5 14266 intel_init_audio(dev);
e70236a8 14267
a6c45cf0
CW		 14268 if (IS_GEN2(dev)) {
14269 dev->mode_config.max_width = 2048;
14270 dev->mode_config.max_height = 2048;
14271 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14272 dev->mode_config.max_width = 4096;
14273 dev->mode_config.max_height = 4096;
79e53945 14274 } else {
a6c45cf0
CW		 14275 dev->mode_config.max_width = 8192;
14276 dev->mode_config.max_height = 8192;
79e53945 14277 }
068be561 14278
dc41c154
VS		 14279 if (IS_845G(dev) || IS_I865G(dev)) {
14280 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14281 dev->mode_config.cursor_height = 1023;
14282 } else if (IS_GEN2(dev)) {
068be561
DL		 14283 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14284 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14285 } else {
14286 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14287 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14288 }
14289
5d4545ae 14290 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14291
28c97730 14292 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14293 INTEL_INFO(dev)->num_pipes,
14294 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14295
055e393f 14296 for_each_pipe(dev_priv, pipe) {
8cc87b75 14297 intel_crtc_init(dev, pipe);
3bdcfc0c 14298 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14299 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14300 if (ret)
06da8da2 14301 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14302 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14303 }
79e53945
JB		 14304 }
14305
f42bb70d
JB		 14306 intel_init_dpio(dev);
14307
e72f9fbf 14308 intel_shared_dpll_init(dev);
ee7b9f93 14309
9cce37f4
JB		 14310 /* Just disable it once at startup */
14311 i915_disable_vga(dev);
79e53945 14312 intel_setup_outputs(dev);
11be49eb
CW		 14313
14314 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14315 intel_fbc_disable(dev);
fa9fa083 14316
6e9f798d 14317 drm_modeset_lock_all(dev);
fa9fa083 14318 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14319 drm_modeset_unlock_all(dev);
46f297fb 14320
d3fcc808 14321 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14322 if (!crtc->active)
14323 continue;
14324
46f297fb 14325 /*
46f297fb
JB		 14326 * Note that reserving the BIOS fb up front prevents us
14327 * from stuffing other stolen allocations like the ring
14328 * on top. This prevents some ugliness at boot time, and
14329 * can even allow for smooth boot transitions if the BIOS
14330 * fb is large enough for the active pipe configuration.
14331 */
5724dbd1
DL		 14332 if (dev_priv->display.get_initial_plane_config) {
14333 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14334 &crtc->plane_config);
14335 /*
14336 * If the fb is shared between multiple heads, we'll
14337 * just get the first one.
14338 */
f6936e29 14339 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14340 }
46f297fb 14341 }
2c7111db
CW		 14342}
14343
7fad798e
DV		 14344static void intel_enable_pipe_a(struct drm_device *dev)
14345{
14346 struct intel_connector *connector;
14347 struct drm_connector *crt = NULL;
14348 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14349 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14350
14351 /* We can't just switch on the pipe A, we need to set things up with a
14352 * proper mode and output configuration. As a gross hack, enable pipe A
14353 * by enabling the load detect pipe once. */
3a3371ff 14354 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14355 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14356 crt = &connector->base;
14357 break;
14358 }
14359 }
14360
14361 if (!crt)
14362 return;
14363
208bf9fd 14364 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14365 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14366}
14367
fa555837
DV		 14368static bool
14369intel_check_plane_mapping(struct intel_crtc *crtc)
14370{
7eb552ae
BW		 14371 struct drm_device *dev = crtc->base.dev;
14372 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14373 u32 reg, val;
14374
7eb552ae 14375 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14376 return true;
14377
14378 reg = DSPCNTR(!crtc->plane);
14379 val = I915_READ(reg);
14380
14381 if ((val & DISPLAY_PLANE_ENABLE) &&
14382 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14383 return false;
14384
14385 return true;
14386}
14387
24929352
DV		 14388static void intel_sanitize_crtc(struct intel_crtc *crtc)
14389{
14390 struct drm_device *dev = crtc->base.dev;
14391 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14392 u32 reg;
24929352 14393
24929352 14394 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14395 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14396 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14397
d3eaf884 14398 /* restore vblank interrupts to correct state */
9625604c 14399 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14400 if (crtc->active) {
14401 update_scanline_offset(crtc);
9625604c
DV		 14402 drm_crtc_vblank_on(&crtc->base);
14403 }
d3eaf884 14404
24929352 14405 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14406 * disable the crtc (and hence change the state) if it is wrong. Note
14407 * that gen4+ has a fixed plane -> pipe mapping. */
14408 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14409 struct intel_connector *connector;
14410 bool plane;
14411
24929352
DV		 14412 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14413 crtc->base.base.id);
14414
14415 /* Pipe has the wrong plane attached and the plane is active.
14416 * Temporarily change the plane mapping and disable everything
14417 * ... */
14418 plane = crtc->plane;
14419 crtc->plane = !plane;
9c8958bc 14420 crtc->primary_enabled = true;
24929352
DV		 14421 dev_priv->display.crtc_disable(&crtc->base);
14422 crtc->plane = plane;
14423
14424 /* ... and break all links. */
3a3371ff 14425 for_each_intel_connector(dev, connector) {
24929352
DV		 14426 if (connector->encoder->base.crtc != &crtc->base)
14427 continue;
14428
7f1950fb
EE		 14429 connector->base.dpms = DRM_MODE_DPMS_OFF;
14430 connector->base.encoder = NULL;
24929352 14431 }
7f1950fb
EE		 14432 /* multiple connectors may have the same encoder:
14433 * handle them and break crtc link separately */
3a3371ff 14434 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14435 if (connector->encoder->base.crtc == &crtc->base) {
14436 connector->encoder->base.crtc = NULL;
14437 connector->encoder->connectors_active = false;
14438 }
24929352
DV		 14439
14440 WARN_ON(crtc->active);
83d65738 14441 crtc->base.state->enable = false;
24929352
DV		 14442 crtc->base.enabled = false;
14443 }
24929352 14444
7fad798e
DV		 14445 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14446 crtc->pipe == PIPE_A && !crtc->active) {
14447 /* BIOS forgot to enable pipe A, this mostly happens after
14448 * resume. Force-enable the pipe to fix this, the update_dpms
14449 * call below we restore the pipe to the right state, but leave
14450 * the required bits on. */
14451 intel_enable_pipe_a(dev);
14452 }
14453
24929352
DV		 14454 /* Adjust the state of the output pipe according to whether we
14455 * have active connectors/encoders. */
14456 intel_crtc_update_dpms(&crtc->base);
14457
83d65738 14458 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14459 struct intel_encoder *encoder;
14460
14461 /* This can happen either due to bugs in the get_hw_state
14462 * functions or because the pipe is force-enabled due to the
14463 * pipe A quirk. */
14464 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14465 crtc->base.base.id,
83d65738 14466 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14467 crtc->active ? "enabled" : "disabled");
14468
83d65738 14469 crtc->base.state->enable = crtc->active;
24929352
DV		 14470 crtc->base.enabled = crtc->active;
14471
14472 /* Because we only establish the connector -> encoder ->
14473 * crtc links if something is active, this means the
14474 * crtc is now deactivated. Break the links. connector
14475 * -> encoder links are only establish when things are
14476 * actually up, hence no need to break them. */
14477 WARN_ON(crtc->active);
14478
14479 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14480 WARN_ON(encoder->connectors_active);
14481 encoder->base.crtc = NULL;
14482 }
14483 }
c5ab3bc0 14484
a3ed6aad 14485 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14486 /*
14487 * We start out with underrun reporting disabled to avoid races.
14488 * For correct bookkeeping mark this on active crtcs.
14489 *
c5ab3bc0
DV		 14490 * Also on gmch platforms we dont have any hardware bits to
14491 * disable the underrun reporting. Which means we need to start
14492 * out with underrun reporting disabled also on inactive pipes,
14493 * since otherwise we'll complain about the garbage we read when
14494 * e.g. coming up after runtime pm.
14495 *
4cc31489
DV		 14496 * No protection against concurrent access is required - at
14497 * worst a fifo underrun happens which also sets this to false.
14498 */
14499 crtc->cpu_fifo_underrun_disabled = true;
14500 crtc->pch_fifo_underrun_disabled = true;
14501 }
24929352
DV		 14502}
14503
14504static void intel_sanitize_encoder(struct intel_encoder *encoder)
14505{
14506 struct intel_connector *connector;
14507 struct drm_device *dev = encoder->base.dev;
14508
14509 /* We need to check both for a crtc link (meaning that the
14510 * encoder is active and trying to read from a pipe) and the
14511 * pipe itself being active. */
14512 bool has_active_crtc = encoder->base.crtc &&
14513 to_intel_crtc(encoder->base.crtc)->active;
14514
14515 if (encoder->connectors_active && !has_active_crtc) {
14516 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14517 encoder->base.base.id,
8e329a03 14518 encoder->base.name);
24929352
DV		 14519
14520 /* Connector is active, but has no active pipe. This is
14521 * fallout from our resume register restoring. Disable
14522 * the encoder manually again. */
14523 if (encoder->base.crtc) {
14524 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14525 encoder->base.base.id,
8e329a03 14526 encoder->base.name);
24929352 14527 encoder->disable(encoder);
a62d1497
VS		 14528 if (encoder->post_disable)
14529 encoder->post_disable(encoder);
24929352 14530 }
7f1950fb
EE		 14531 encoder->base.crtc = NULL;
14532 encoder->connectors_active = false;
24929352
DV		 14533
14534 /* Inconsistent output/port/pipe state happens presumably due to
14535 * a bug in one of the get_hw_state functions. Or someplace else
14536 * in our code, like the register restore mess on resume. Clamp
14537 * things to off as a safer default. */
3a3371ff 14538 for_each_intel_connector(dev, connector) {
24929352
DV		 14539 if (connector->encoder != encoder)
14540 continue;
7f1950fb
EE		 14541 connector->base.dpms = DRM_MODE_DPMS_OFF;
14542 connector->base.encoder = NULL;
24929352
DV		 14543 }
14544 }
14545 /* Enabled encoders without active connectors will be fixed in
14546 * the crtc fixup. */
14547}
14548
04098753 14549void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14550{
14551 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14552 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14553
04098753
ID		 14554 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14555 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14556 i915_disable_vga(dev);
14557 }
14558}
14559
14560void i915_redisable_vga(struct drm_device *dev)
14561{
14562 struct drm_i915_private *dev_priv = dev->dev_private;
14563
8dc8a27c
PZ		 14564 /* This function can be called both from intel_modeset_setup_hw_state or
14565 * at a very early point in our resume sequence, where the power well
14566 * structures are not yet restored. Since this function is at a very
14567 * paranoid "someone might have enabled VGA while we were not looking"
14568 * level, just check if the power well is enabled instead of trying to
14569 * follow the "don't touch the power well if we don't need it" policy
14570 * the rest of the driver uses. */
f458ebbc 14571 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14572 return;
14573
04098753 14574 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14575}
14576
98ec7739
VS		 14577static bool primary_get_hw_state(struct intel_crtc *crtc)
14578{
14579 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14580
14581 if (!crtc->active)
14582 return false;
14583
14584 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14585}
14586
30e984df 14587static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14588{
14589 struct drm_i915_private *dev_priv = dev->dev_private;
14590 enum pipe pipe;
24929352
DV		 14591 struct intel_crtc *crtc;
14592 struct intel_encoder *encoder;
14593 struct intel_connector *connector;
5358901f 14594 int i;
24929352 14595
d3fcc808 14596 for_each_intel_crtc(dev, crtc) {
6e3c9717 14597 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14598
6e3c9717 14599 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14600
0e8ffe1b 14601 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14602 crtc->config);
24929352 14603
83d65738 14604 crtc->base.state->enable = crtc->active;
24929352 14605 crtc->base.enabled = crtc->active;
98ec7739 14606 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14607
14608 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14609 crtc->base.base.id,
14610 crtc->active ? "enabled" : "disabled");
14611 }
14612
5358901f
DV		 14613 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14614 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14615
3e369b76
ACO		 14616 pll->on = pll->get_hw_state(dev_priv, pll,
14617 &pll->config.hw_state);
5358901f 14618 pll->active = 0;
3e369b76 14619 pll->config.crtc_mask = 0;
d3fcc808 14620 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14621 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14622 pll->active++;
3e369b76 14623 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14624 }
5358901f 14625 }
5358901f 14626
1e6f2ddc 14627 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14628 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14629
3e369b76 14630 if (pll->config.crtc_mask)
bd2bb1b9 14631 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14632 }
14633
b2784e15 14634 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14635 pipe = 0;
14636
14637 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14638 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14639 encoder->base.crtc = &crtc->base;
6e3c9717 14640 encoder->get_config(encoder, crtc->config);
24929352
DV		 14641 } else {
14642 encoder->base.crtc = NULL;
14643 }
14644
14645 encoder->connectors_active = false;
6f2bcceb 14646 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14647 encoder->base.base.id,
8e329a03 14648 encoder->base.name,
24929352 14649 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14650 pipe_name(pipe));
24929352
DV		 14651 }
14652
3a3371ff 14653 for_each_intel_connector(dev, connector) {
24929352
DV		 14654 if (connector->get_hw_state(connector)) {
14655 connector->base.dpms = DRM_MODE_DPMS_ON;
14656 connector->encoder->connectors_active = true;
14657 connector->base.encoder = &connector->encoder->base;
14658 } else {
14659 connector->base.dpms = DRM_MODE_DPMS_OFF;
14660 connector->base.encoder = NULL;
14661 }
14662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14663 connector->base.base.id,
c23cc417 14664 connector->base.name,
24929352
DV		 14665 connector->base.encoder ? "enabled" : "disabled");
14666 }
30e984df
DV		 14667}
14668
14669/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14670 * and i915 state tracking structures. */
14671void intel_modeset_setup_hw_state(struct drm_device *dev,
14672 bool force_restore)
14673{
14674 struct drm_i915_private *dev_priv = dev->dev_private;
14675 enum pipe pipe;
30e984df
DV		 14676 struct intel_crtc *crtc;
14677 struct intel_encoder *encoder;
35c95375 14678 int i;
30e984df
DV		 14679
14680 intel_modeset_readout_hw_state(dev);
24929352 14681
babea61d
JB		 14682 /*
14683 * Now that we have the config, copy it to each CRTC struct
14684 * Note that this could go away if we move to using crtc_config
14685 * checking everywhere.
14686 */
d3fcc808 14687 for_each_intel_crtc(dev, crtc) {
d330a953 14688 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14689 intel_mode_from_pipe_config(&crtc->base.mode,
14690 crtc->config);
babea61d
JB		 14691 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14692 crtc->base.base.id);
14693 drm_mode_debug_printmodeline(&crtc->base.mode);
14694 }
14695 }
14696
24929352 14697 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14698 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14699 intel_sanitize_encoder(encoder);
14700 }
14701
055e393f 14702 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14703 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14704 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14705 intel_dump_pipe_config(crtc, crtc->config,
14706 "[setup_hw_state]");
24929352 14707 }
9a935856 14708
d29b2f9d
ACO		 14709 intel_modeset_update_connector_atomic_state(dev);
14710
35c95375
DV		 14711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14712 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14713
14714 if (!pll->on || pll->active)
14715 continue;
14716
14717 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14718
14719 pll->disable(dev_priv, pll);
14720 pll->on = false;
14721 }
14722
3078999f
PB		 14723 if (IS_GEN9(dev))
14724 skl_wm_get_hw_state(dev);
14725 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14726 ilk_wm_get_hw_state(dev);
14727
45e2b5f6 14728 if (force_restore) {
7d0bc1ea
VS		 14729 i915_redisable_vga(dev);
14730
f30da187
DV		 14731 /*
14732 * We need to use raw interfaces for restoring state to avoid
14733 * checking (bogus) intermediate states.
14734 */
055e393f 14735 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14736 struct drm_crtc *crtc =
14737 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14738
83a57153 14739 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14740 }
14741 } else {
14742 intel_modeset_update_staged_output_state(dev);
14743 }
8af6cf88
DV		 14744
14745 intel_modeset_check_state(dev);
2c7111db
CW		 14746}
14747
14748void intel_modeset_gem_init(struct drm_device *dev)
14749{
92122789 14750 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14751 struct drm_crtc *c;
2ff8fde1 14752 struct drm_i915_gem_object *obj;
484b41dd 14753
ae48434c
ID		 14754 mutex_lock(&dev->struct_mutex);
14755 intel_init_gt_powersave(dev);
14756 mutex_unlock(&dev->struct_mutex);
14757
92122789
JB		 14758 /*
14759 * There may be no VBT; and if the BIOS enabled SSC we can
14760 * just keep using it to avoid unnecessary flicker. Whereas if the
14761 * BIOS isn't using it, don't assume it will work even if the VBT
14762 * indicates as much.
14763 */
14764 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14765 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14766 DREF_SSC1_ENABLE);
14767
1833b134 14768 intel_modeset_init_hw(dev);
02e792fb
DV		 14769
14770 intel_setup_overlay(dev);
484b41dd
JB		 14771
14772 /*
14773 * Make sure any fbs we allocated at startup are properly
14774 * pinned & fenced. When we do the allocation it's too early
14775 * for this.
14776 */
14777 mutex_lock(&dev->struct_mutex);
70e1e0ec 14778 for_each_crtc(dev, c) {
2ff8fde1
MR		 14779 obj = intel_fb_obj(c->primary->fb);
14780 if (obj == NULL)
484b41dd
JB		 14781 continue;
14782
850c4cdc
TU		 14783 if (intel_pin_and_fence_fb_obj(c->primary,
14784 c->primary->fb,
82bc3b2d 14785 c->primary->state,
850c4cdc 14786 NULL)) {
484b41dd
JB		 14787 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14788 to_intel_crtc(c)->pipe);
66e514c1
DA		 14789 drm_framebuffer_unreference(c->primary->fb);
14790 c->primary->fb = NULL;
afd65eb4 14791 update_state_fb(c->primary);
484b41dd
JB		 14792 }
14793 }
14794 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14795
14796 intel_backlight_register(dev);
79e53945
JB		 14797}
14798
4932e2c3
ID		 14799void intel_connector_unregister(struct intel_connector *intel_connector)
14800{
14801 struct drm_connector *connector = &intel_connector->base;
14802
14803 intel_panel_destroy_backlight(connector);
34ea3d38 14804 drm_connector_unregister(connector);
4932e2c3
ID		 14805}
14806
79e53945
JB		 14807void intel_modeset_cleanup(struct drm_device *dev)
14808{
652c393a 14809 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14810 struct drm_connector *connector;
652c393a 14811
2eb5252e
ID		 14812 intel_disable_gt_powersave(dev);
14813
0962c3c9
VS		 14814 intel_backlight_unregister(dev);
14815
fd0c0642
DV		 14816 /*
14817 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14818 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14819 * experience fancy races otherwise.
14820 */
2aeb7d3a 14821 intel_irq_uninstall(dev_priv);
eb21b92b 14822
fd0c0642
DV		 14823 /*
14824 * Due to the hpd irq storm handling the hotplug work can re-arm the
14825 * poll handlers. Hence disable polling after hpd handling is shut down.
14826 */
f87ea761 14827 drm_kms_helper_poll_fini(dev);
fd0c0642 14828
652c393a
JB		 14829 mutex_lock(&dev->struct_mutex);
14830
723bfd70
JB		 14831 intel_unregister_dsm_handler();
14832
7ff0ebcc 14833 intel_fbc_disable(dev);
e70236a8 14834
69341a5e
KH		 14835 mutex_unlock(&dev->struct_mutex);
14836
1630fe75
CW		 14837 /* flush any delayed tasks or pending work */
14838 flush_scheduled_work();
14839
db31af1d
JN		 14840 /* destroy the backlight and sysfs files before encoders/connectors */
14841 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14842 struct intel_connector *intel_connector;
14843
14844 intel_connector = to_intel_connector(connector);
14845 intel_connector->unregister(intel_connector);
db31af1d 14846 }
d9255d57 14847
79e53945 14848 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14849
14850 intel_cleanup_overlay(dev);
ae48434c
ID		 14851
14852 mutex_lock(&dev->struct_mutex);
14853 intel_cleanup_gt_powersave(dev);
14854 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14855}
14856
f1c79df3
ZW		 14857/*
14858 * Return which encoder is currently attached for connector.
14859 */
df0e9248 14860struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14861{
df0e9248
CW		 14862 return &intel_attached_encoder(connector)->base;
14863}
f1c79df3 14864
df0e9248
CW		 14865void intel_connector_attach_encoder(struct intel_connector *connector,
14866 struct intel_encoder *encoder)
14867{
14868 connector->encoder = encoder;
14869 drm_mode_connector_attach_encoder(&connector->base,
14870 &encoder->base);
79e53945 14871}
28d52043
DA		 14872
14873/*
14874 * set vga decode state - true == enable VGA decode
14875 */
14876int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14877{
14878 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14879 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14880 u16 gmch_ctrl;
14881
75fa041d
CW		 14882 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14883 DRM_ERROR("failed to read control word\n");
14884 return -EIO;
14885 }
14886
c0cc8a55
CW		 14887 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14888 return 0;
14889
28d52043
DA		 14890 if (state)
14891 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14892 else
14893 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14894
14895 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14896 DRM_ERROR("failed to write control word\n");
14897 return -EIO;
14898 }
14899
28d52043
DA		 14900 return 0;
14901}
c4a1d9e4 14902
c4a1d9e4 14903struct intel_display_error_state {
ff57f1b0
PZ		 14904
14905 u32 power_well_driver;
14906
63b66e5b
CW		 14907 int num_transcoders;
14908
c4a1d9e4
CW		 14909 struct intel_cursor_error_state {
14910 u32 control;
14911 u32 position;
14912 u32 base;
14913 u32 size;
52331309 14914 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14915
14916 struct intel_pipe_error_state {
ddf9c536 14917 bool power_domain_on;
c4a1d9e4 14918 u32 source;
f301b1e1 14919 u32 stat;
52331309 14920 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14921
14922 struct intel_plane_error_state {
14923 u32 control;
14924 u32 stride;
14925 u32 size;
14926 u32 pos;
14927 u32 addr;
14928 u32 surface;
14929 u32 tile_offset;
52331309 14930 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14931
14932 struct intel_transcoder_error_state {
ddf9c536 14933 bool power_domain_on;
63b66e5b
CW		 14934 enum transcoder cpu_transcoder;
14935
14936 u32 conf;
14937
14938 u32 htotal;
14939 u32 hblank;
14940 u32 hsync;
14941 u32 vtotal;
14942 u32 vblank;
14943 u32 vsync;
14944 } transcoder[4];
c4a1d9e4
CW		 14945};
14946
14947struct intel_display_error_state *
14948intel_display_capture_error_state(struct drm_device *dev)
14949{
fbee40df 14950 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14951 struct intel_display_error_state *error;
63b66e5b
CW		 14952 int transcoders[] = {
14953 TRANSCODER_A,
14954 TRANSCODER_B,
14955 TRANSCODER_C,
14956 TRANSCODER_EDP,
14957 };
c4a1d9e4
CW		 14958 int i;
14959
63b66e5b
CW		 14960 if (INTEL_INFO(dev)->num_pipes == 0)
14961 return NULL;
14962
9d1cb914 14963 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14964 if (error == NULL)
14965 return NULL;
14966
190be112 14967 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14968 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14969
055e393f 14970 for_each_pipe(dev_priv, i) {
ddf9c536 14971 error->pipe[i].power_domain_on =
f458ebbc
DV		 14972 __intel_display_power_is_enabled(dev_priv,
14973 POWER_DOMAIN_PIPE(i));
ddf9c536 14974 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14975 continue;
14976
5efb3e28
VS		 14977 error->cursor[i].control = I915_READ(CURCNTR(i));
14978 error->cursor[i].position = I915_READ(CURPOS(i));
14979 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14980
14981 error->plane[i].control = I915_READ(DSPCNTR(i));
14982 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14983 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14984 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14985 error->plane[i].pos = I915_READ(DSPPOS(i));
14986 }
ca291363
PZ		 14987 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14988 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14989 if (INTEL_INFO(dev)->gen >= 4) {
14990 error->plane[i].surface = I915_READ(DSPSURF(i));
14991 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14992 }
14993
c4a1d9e4 14994 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14995
3abfce77 14996 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14997 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14998 }
14999
15000 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15001 if (HAS_DDI(dev_priv->dev))
15002 error->num_transcoders++; /* Account for eDP. */
15003
15004 for (i = 0; i < error->num_transcoders; i++) {
15005 enum transcoder cpu_transcoder = transcoders[i];
15006
ddf9c536 15007 error->transcoder[i].power_domain_on =
f458ebbc 15008 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15009 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15010 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15011 continue;
15012
63b66e5b
CW		 15013 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15014
15015 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15016 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15017 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15018 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15019 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15020 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15021 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15022 }
15023
15024 return error;
15025}
15026
edc3d884
MK		 15027#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15028
c4a1d9e4 15029void
edc3d884 15030intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15031 struct drm_device *dev,
15032 struct intel_display_error_state *error)
15033{
055e393f 15034 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15035 int i;
15036
63b66e5b
CW		 15037 if (!error)
15038 return;
15039
edc3d884 15040 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15041 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15042 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15043 error->power_well_driver);
055e393f 15044 for_each_pipe(dev_priv, i) {
edc3d884 15045 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15046 err_printf(m, " Power: %s\n",
15047 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15048 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15049 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15050
15051 err_printf(m, "Plane [%d]:\n", i);
15052 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15053 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15054 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15055 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15056 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15057 }
4b71a570 15058 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15059 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15060 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15061 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15062 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15063 }
15064
edc3d884
MK		 15065 err_printf(m, "Cursor [%d]:\n", i);
15066 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15067 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15068 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15069 }
63b66e5b
CW		 15070
15071 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15072 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15073 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15074 err_printf(m, " Power: %s\n",
15075 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15076 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15077 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15078 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15079 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15080 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15081 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15082 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15083 }
c4a1d9e4 15084}
e2fcdaa9
VS		 15085
15086void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15087{
15088 struct intel_crtc *crtc;
15089
15090 for_each_intel_crtc(dev, crtc) {
15091 struct intel_unpin_work *work;
e2fcdaa9 15092
5e2d7afc 15093 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15094
15095 work = crtc->unpin_work;
15096
15097 if (work && work->event &&
15098 work->event->base.file_priv == file) {
15099 kfree(work->event);
15100 work->event = NULL;
15101 }
15102
5e2d7afc 15103 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15104 }
15105}
Linux kernel - Deliverables
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