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drm/i915: Fix view type in warning message
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
e7457a9a 108
0e32b39c
DA		 109static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
110{
111 if (!connector->mst_port)
112 return connector->encoder;
113 else
114 return &connector->mst_port->mst_encoders[pipe]->base;
115}
116
79e53945 117typedef struct {
0206e353 118 int min, max;
79e53945
JB		 119} intel_range_t;
120
121typedef struct {
0206e353
AJ		 122 int dot_limit;
123 int p2_slow, p2_fast;
79e53945
JB		 124} intel_p2_t;
125
d4906093
ML		 126typedef struct intel_limit intel_limit_t;
127struct intel_limit {
0206e353
AJ		 128 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_p2_t p2;
d4906093 130};
79e53945 131
d2acd215
DV		 132int
133intel_pch_rawclk(struct drm_device *dev)
134{
135 struct drm_i915_private *dev_priv = dev->dev_private;
136
137 WARN_ON(!HAS_PCH_SPLIT(dev));
138
139 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
140}
141
021357ac
CW		 142static inline u32 /* units of 100MHz */
143intel_fdi_link_freq(struct drm_device *dev)
144{
8b99e68c
CW		 145 if (IS_GEN5(dev)) {
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
148 } else
149 return 27;
021357ac
CW		 150}
151
5d536e28 152static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 153 .dot = { .min = 25000, .max = 350000 },
9c333719 154 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 155 .n = { .min = 2, .max = 16 },
0206e353
AJ		 156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 163};
164
5d536e28
DV		 165static const intel_limit_t intel_limits_i8xx_dvo = {
166 .dot = { .min = 25000, .max = 350000 },
9c333719 167 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 168 .n = { .min = 2, .max = 16 },
5d536e28
DV		 169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 2, .max = 33 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 4, .p2_fast = 4 },
176};
177
e4b36699 178static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 179 .dot = { .min = 25000, .max = 350000 },
9c333719 180 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 181 .n = { .min = 2, .max = 16 },
0206e353
AJ		 182 .m = { .min = 96, .max = 140 },
183 .m1 = { .min = 18, .max = 26 },
184 .m2 = { .min = 6, .max = 16 },
185 .p = { .min = 4, .max = 128 },
186 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 187 .p2 = { .dot_limit = 165000,
188 .p2_slow = 14, .p2_fast = 7 },
e4b36699 189};
273e27ca 190
e4b36699 191static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 198 .p = { .min = 5, .max = 80 },
199 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 200 .p2 = { .dot_limit = 200000,
201 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 202};
203
204static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 205 .dot = { .min = 20000, .max = 400000 },
206 .vco = { .min = 1400000, .max = 2800000 },
207 .n = { .min = 1, .max = 6 },
208 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 209 .m1 = { .min = 8, .max = 18 },
210 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 211 .p = { .min = 7, .max = 98 },
212 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 213 .p2 = { .dot_limit = 112000,
214 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 215};
216
273e27ca 217
e4b36699 218static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 219 .dot = { .min = 25000, .max = 270000 },
220 .vco = { .min = 1750000, .max = 3500000},
221 .n = { .min = 1, .max = 4 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 10, .max = 30 },
226 .p1 = { .min = 1, .max = 3},
227 .p2 = { .dot_limit = 270000,
228 .p2_slow = 10,
229 .p2_fast = 10
044c7c41 230 },
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 234 .dot = { .min = 22000, .max = 400000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 4 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 16, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 5, .max = 80 },
241 .p1 = { .min = 1, .max = 8},
242 .p2 = { .dot_limit = 165000,
243 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 244};
245
246static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 247 .dot = { .min = 20000, .max = 115000 },
248 .vco = { .min = 1750000, .max = 3500000 },
249 .n = { .min = 1, .max = 3 },
250 .m = { .min = 104, .max = 138 },
251 .m1 = { .min = 17, .max = 23 },
252 .m2 = { .min = 5, .max = 11 },
253 .p = { .min = 28, .max = 112 },
254 .p1 = { .min = 2, .max = 8 },
255 .p2 = { .dot_limit = 0,
256 .p2_slow = 14, .p2_fast = 14
044c7c41 257 },
e4b36699
KP		 258};
259
260static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 261 .dot = { .min = 80000, .max = 224000 },
262 .vco = { .min = 1750000, .max = 3500000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 104, .max = 138 },
265 .m1 = { .min = 17, .max = 23 },
266 .m2 = { .min = 5, .max = 11 },
267 .p = { .min = 14, .max = 42 },
268 .p1 = { .min = 2, .max = 6 },
269 .p2 = { .dot_limit = 0,
270 .p2_slow = 7, .p2_fast = 7
044c7c41 271 },
e4b36699
KP		 272};
273
f2b115e6 274static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000},
276 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 277 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
273e27ca 280 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 5, .max = 80 },
284 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 285 .p2 = { .dot_limit = 200000,
286 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 287};
288
f2b115e6 289static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 290 .dot = { .min = 20000, .max = 400000 },
291 .vco = { .min = 1700000, .max = 3500000 },
292 .n = { .min = 3, .max = 6 },
293 .m = { .min = 2, .max = 256 },
294 .m1 = { .min = 0, .max = 0 },
295 .m2 = { .min = 0, .max = 254 },
296 .p = { .min = 7, .max = 112 },
297 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 298 .p2 = { .dot_limit = 112000,
299 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 300};
301
273e27ca
EA		 302/* Ironlake / Sandybridge
303 *
304 * We calculate clock using (register_value + 2) for N/M1/M2, so here
305 * the range value for them is (actual_value - 2).
306 */
b91ad0ec 307static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 5 },
311 .m = { .min = 79, .max = 127 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 5, .max = 80 },
315 .p1 = { .min = 1, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331};
332
333static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 3 },
337 .m = { .min = 79, .max = 127 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 14, .max = 56 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 344};
345
273e27ca 346/* LVDS 100mhz refclk limits. */
b91ad0ec 347static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 2 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 28, .max = 112 },
0206e353 355 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 358};
359
360static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 361 .dot = { .min = 25000, .max = 350000 },
362 .vco = { .min = 1760000, .max = 3510000 },
363 .n = { .min = 1, .max = 3 },
364 .m = { .min = 79, .max = 126 },
365 .m1 = { .min = 12, .max = 22 },
366 .m2 = { .min = 5, .max = 9 },
367 .p = { .min = 14, .max = 42 },
0206e353 368 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 369 .p2 = { .dot_limit = 225000,
370 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 371};
372
dc730512 373static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 374 /*
375 * These are the data rate limits (measured in fast clocks)
376 * since those are the strictest limits we have. The fast
377 * clock and actual rate limits are more relaxed, so checking
378 * them would make no difference.
379 */
380 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 381 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 382 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 383 .m1 = { .min = 2, .max = 3 },
384 .m2 = { .min = 11, .max = 156 },
b99ab663 385 .p1 = { .min = 2, .max = 3 },
5fdc9c49 386 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 387};
388
ef9348c8
CML		 389static const intel_limit_t intel_limits_chv = {
390 /*
391 * These are the data rate limits (measured in fast clocks)
392 * since those are the strictest limits we have. The fast
393 * clock and actual rate limits are more relaxed, so checking
394 * them would make no difference.
395 */
396 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 397 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 398 .n = { .min = 1, .max = 1 },
399 .m1 = { .min = 2, .max = 2 },
400 .m2 = { .min = 24 << 22, .max = 175 << 22 },
401 .p1 = { .min = 2, .max = 4 },
402 .p2 = { .p2_slow = 1, .p2_fast = 14 },
403};
404
6b4bf1c4
VS		 405static void vlv_clock(int refclk, intel_clock_t *clock)
406{
407 clock->m = clock->m1 * clock->m2;
408 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 409 if (WARN_ON(clock->n == 0 || clock->p == 0))
410 return;
fb03ac01
VS		 411 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
412 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 413}
414
e0638cdf
PZ		 415/**
416 * Returns whether any output on the specified pipe is of the specified type
417 */
4093561b 418bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 419{
409ee761 420 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 421 struct intel_encoder *encoder;
422
409ee761 423 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 424 if (encoder->type == type)
425 return true;
426
427 return false;
428}
429
d0737e1d
ACO		 430/**
431 * Returns whether any output on the specified pipe will have the specified
432 * type after a staged modeset is complete, i.e., the same as
433 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
434 * encoder->crtc.
435 */
a93e255f
ACO		 436static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
437 int type)
d0737e1d 438{
a93e255f
ACO		 439 struct drm_atomic_state *state = crtc_state->base.state;
440 struct drm_connector_state *connector_state;
d0737e1d 441 struct intel_encoder *encoder;
a93e255f
ACO		 442 int i, num_connectors = 0;
443
444 for (i = 0; i < state->num_connector; i++) {
445 if (!state->connectors[i])
446 continue;
447
448 connector_state = state->connector_states[i];
449 if (connector_state->crtc != crtc_state->base.crtc)
450 continue;
451
452 num_connectors++;
d0737e1d 453
a93e255f
ACO		 454 encoder = to_intel_encoder(connector_state->best_encoder);
455 if (encoder->type == type)
d0737e1d 456 return true;
a93e255f
ACO		 457 }
458
459 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 460
461 return false;
462}
463
a93e255f
ACO		 464static const intel_limit_t *
465intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 466{
a93e255f 467 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 468 const intel_limit_t *limit;
b91ad0ec 469
a93e255f 470 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 471 if (intel_is_dual_link_lvds(dev)) {
1b894b59 472 if (refclk == 100000)
b91ad0ec
ZW		 473 limit = &intel_limits_ironlake_dual_lvds_100m;
474 else
475 limit = &intel_limits_ironlake_dual_lvds;
476 } else {
1b894b59 477 if (refclk == 100000)
b91ad0ec
ZW		 478 limit = &intel_limits_ironlake_single_lvds_100m;
479 else
480 limit = &intel_limits_ironlake_single_lvds;
481 }
c6bb3538 482 } else
b91ad0ec 483 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 484
485 return limit;
486}
487
a93e255f
ACO		 488static const intel_limit_t *
489intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 490{
a93e255f 491 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 492 const intel_limit_t *limit;
493
a93e255f 494 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 495 if (intel_is_dual_link_lvds(dev))
e4b36699 496 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 497 else
e4b36699 498 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 499 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
500 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 501 limit = &intel_limits_g4x_hdmi;
a93e255f 502 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 503 limit = &intel_limits_g4x_sdvo;
044c7c41 504 } else /* The option is for other outputs */
e4b36699 505 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 506
507 return limit;
508}
509
a93e255f
ACO		 510static const intel_limit_t *
511intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 512{
a93e255f 513 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 514 const intel_limit_t *limit;
515
bad720ff 516 if (HAS_PCH_SPLIT(dev))
a93e255f 517 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 518 else if (IS_G4X(dev)) {
a93e255f 519 limit = intel_g4x_limit(crtc_state);
f2b115e6 520 } else if (IS_PINEVIEW(dev)) {
a93e255f 521 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 522 limit = &intel_limits_pineview_lvds;
2177832f 523 else
f2b115e6 524 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 525 } else if (IS_CHERRYVIEW(dev)) {
526 limit = &intel_limits_chv;
a0c4da24 527 } else if (IS_VALLEYVIEW(dev)) {
dc730512 528 limit = &intel_limits_vlv;
a6c45cf0 529 } else if (!IS_GEN2(dev)) {
a93e255f 530 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 531 limit = &intel_limits_i9xx_lvds;
532 else
533 limit = &intel_limits_i9xx_sdvo;
79e53945 534 } else {
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 536 limit = &intel_limits_i8xx_lvds;
a93e255f 537 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 538 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 539 else
540 limit = &intel_limits_i8xx_dac;
79e53945
JB		 541 }
542 return limit;
543}
544
f2b115e6
AJ		 545/* m1 is reserved as 0 in Pineview, n is a ring counter */
546static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 547{
2177832f
SL		 548 clock->m = clock->m2 + 2;
549 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
fb03ac01
VS		 552 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
553 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 554}
555
7429e9d4
DV		 556static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
557{
558 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
559}
560
ac58c3f0 561static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 562{
7429e9d4 563 clock->m = i9xx_dpll_compute_m(clock);
79e53945 564 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 565 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
566 return;
fb03ac01
VS		 567 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
568 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 569}
570
ef9348c8
CML		 571static void chv_clock(int refclk, intel_clock_t *clock)
572{
573 clock->m = clock->m1 * clock->m2;
574 clock->p = clock->p1 * clock->p2;
575 if (WARN_ON(clock->n == 0 || clock->p == 0))
576 return;
577 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
578 clock->n << 22);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
580}
581
7c04d1d9 582#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 583/**
584 * Returns whether the given set of divisors are valid for a given refclk with
585 * the given connectors.
586 */
587
1b894b59
CW		 588static bool intel_PLL_is_valid(struct drm_device *dev,
589 const intel_limit_t *limit,
590 const intel_clock_t *clock)
79e53945 591{
f01b7962
VS		 592 if (clock->n < limit->n.min || limit->n.max < clock->n)
593 INTELPllInvalid("n out of range\n");
79e53945 594 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 595 INTELPllInvalid("p1 out of range\n");
79e53945 596 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 597 INTELPllInvalid("m2 out of range\n");
79e53945 598 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 599 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 600
601 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
602 if (clock->m1 <= clock->m2)
603 INTELPllInvalid("m1 <= m2\n");
604
605 if (!IS_VALLEYVIEW(dev)) {
606 if (clock->p < limit->p.min || limit->p.max < clock->p)
607 INTELPllInvalid("p out of range\n");
608 if (clock->m < limit->m.min || limit->m.max < clock->m)
609 INTELPllInvalid("m out of range\n");
610 }
611
79e53945 612 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 613 INTELPllInvalid("vco out of range\n");
79e53945
JB		 614 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
615 * connector, etc., rather than just a single range.
616 */
617 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 618 INTELPllInvalid("dot out of range\n");
79e53945
JB		 619
620 return true;
621}
622
d4906093 623static bool
a93e255f
ACO		 624i9xx_find_best_dpll(const intel_limit_t *limit,
625 struct intel_crtc_state *crtc_state,
cec2f356
SP		 626 int target, int refclk, intel_clock_t *match_clock,
627 intel_clock_t *best_clock)
79e53945 628{
a93e255f 629 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 630 struct drm_device *dev = crtc->base.dev;
79e53945 631 intel_clock_t clock;
79e53945
JB		 632 int err = target;
633
a93e255f 634 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 635 /*
a210b028
DV		 636 * For LVDS just rely on its current settings for dual-channel.
637 * We haven't figured out how to reliably set up different
638 * single/dual channel state, if we even can.
79e53945 639 */
1974cad0 640 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
0206e353 651 memset(best_clock, 0, sizeof(*best_clock));
79e53945 652
42158660
ZY		 653 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
654 clock.m1++) {
655 for (clock.m2 = limit->m2.min;
656 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 657 if (clock.m2 >= clock.m1)
42158660
ZY		 658 break;
659 for (clock.n = limit->n.min;
660 clock.n <= limit->n.max; clock.n++) {
661 for (clock.p1 = limit->p1.min;
662 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 663 int this_err;
664
ac58c3f0
DV		 665 i9xx_clock(refclk, &clock);
666 if (!intel_PLL_is_valid(dev, limit,
667 &clock))
668 continue;
669 if (match_clock &&
670 clock.p != match_clock->p)
671 continue;
672
673 this_err = abs(clock.dot - target);
674 if (this_err < err) {
675 *best_clock = clock;
676 err = this_err;
677 }
678 }
679 }
680 }
681 }
682
683 return (err != target);
684}
685
686static bool
a93e255f
ACO		 687pnv_find_best_dpll(const intel_limit_t *limit,
688 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
79e53945 691{
a93e255f 692 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 693 struct drm_device *dev = crtc->base.dev;
79e53945 694 intel_clock_t clock;
79e53945
JB		 695 int err = target;
696
a93e255f 697 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 698 /*
a210b028
DV		 699 * For LVDS just rely on its current settings for dual-channel.
700 * We haven't figured out how to reliably set up different
701 * single/dual channel state, if we even can.
79e53945 702 */
1974cad0 703 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 720 for (clock.n = limit->n.min;
721 clock.n <= limit->n.max; clock.n++) {
722 for (clock.p1 = limit->p1.min;
723 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 724 int this_err;
725
ac58c3f0 726 pineview_clock(refclk, &clock);
1b894b59
CW		 727 if (!intel_PLL_is_valid(dev, limit,
728 &clock))
79e53945 729 continue;
cec2f356
SP		 730 if (match_clock &&
731 clock.p != match_clock->p)
732 continue;
79e53945
JB		 733
734 this_err = abs(clock.dot - target);
735 if (this_err < err) {
736 *best_clock = clock;
737 err = this_err;
738 }
739 }
740 }
741 }
742 }
743
744 return (err != target);
745}
746
d4906093 747static bool
a93e255f
ACO		 748g4x_find_best_dpll(const intel_limit_t *limit,
749 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
d4906093 752{
a93e255f 753 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 754 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 755 intel_clock_t clock;
756 int max_n;
757 bool found;
6ba770dc
AJ		 758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 760 found = false;
761
a93e255f 762 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 763 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 764 clock.p2 = limit->p2.p2_fast;
765 else
766 clock.p2 = limit->p2.p2_slow;
767 } else {
768 if (target < limit->p2.dot_limit)
769 clock.p2 = limit->p2.p2_slow;
770 else
771 clock.p2 = limit->p2.p2_fast;
772 }
773
774 memset(best_clock, 0, sizeof(*best_clock));
775 max_n = limit->n.max;
f77f13e2 776 /* based on hardware requirement, prefer smaller n to precision */
d4906093 777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 778 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 779 for (clock.m1 = limit->m1.max;
780 clock.m1 >= limit->m1.min; clock.m1--) {
781 for (clock.m2 = limit->m2.max;
782 clock.m2 >= limit->m2.min; clock.m2--) {
783 for (clock.p1 = limit->p1.max;
784 clock.p1 >= limit->p1.min; clock.p1--) {
785 int this_err;
786
ac58c3f0 787 i9xx_clock(refclk, &clock);
1b894b59
CW		 788 if (!intel_PLL_is_valid(dev, limit,
789 &clock))
d4906093 790 continue;
1b894b59
CW		 791
792 this_err = abs(clock.dot - target);
d4906093
ML		 793 if (this_err < err_most) {
794 *best_clock = clock;
795 err_most = this_err;
796 max_n = clock.n;
797 found = true;
798 }
799 }
800 }
801 }
802 }
2c07245f
ZW		 803 return found;
804}
805
d5dd62bd
ID		 806/*
807 * Check if the calculated PLL configuration is more optimal compared to the
808 * best configuration and error found so far. Return the calculated error.
809 */
810static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
811 const intel_clock_t *calculated_clock,
812 const intel_clock_t *best_clock,
813 unsigned int best_error_ppm,
814 unsigned int *error_ppm)
815{
9ca3ba01
ID		 816 /*
817 * For CHV ignore the error and consider only the P value.
818 * Prefer a bigger P value based on HW requirements.
819 */
820 if (IS_CHERRYVIEW(dev)) {
821 *error_ppm = 0;
822
823 return calculated_clock->p > best_clock->p;
824 }
825
24be4e46
ID		 826 if (WARN_ON_ONCE(!target_freq))
827 return false;
828
d5dd62bd
ID		 829 *error_ppm = div_u64(1000000ULL *
830 abs(target_freq - calculated_clock->dot),
831 target_freq);
832 /*
833 * Prefer a better P value over a better (smaller) error if the error
834 * is small. Ensure this preference for future configurations too by
835 * setting the error to 0.
836 */
837 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
838 *error_ppm = 0;
839
840 return true;
841 }
842
843 return *error_ppm + 10 < best_error_ppm;
844}
845
a0c4da24 846static bool
a93e255f
ACO		 847vlv_find_best_dpll(const intel_limit_t *limit,
848 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 849 int target, int refclk, intel_clock_t *match_clock,
850 intel_clock_t *best_clock)
a0c4da24 851{
a93e255f 852 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 853 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 854 intel_clock_t clock;
69e4f900 855 unsigned int bestppm = 1000000;
27e639bf
VS		 856 /* min update 19.2 MHz */
857 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 858 bool found = false;
a0c4da24 859
6b4bf1c4
VS		 860 target *= 5; /* fast clock */
861
862 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 863
864 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 865 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 866 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 867 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 868 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 869 clock.p = clock.p1 * clock.p2;
a0c4da24 870 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 871 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 872 unsigned int ppm;
69e4f900 873
6b4bf1c4
VS		 874 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
875 refclk * clock.m1);
876
877 vlv_clock(refclk, &clock);
43b0ac53 878
f01b7962
VS		 879 if (!intel_PLL_is_valid(dev, limit,
880 &clock))
43b0ac53
VS		 881 continue;
882
d5dd62bd
ID		 883 if (!vlv_PLL_is_optimal(dev, target,
884 &clock,
885 best_clock,
886 bestppm, &ppm))
887 continue;
6b4bf1c4 888
d5dd62bd
ID		 889 *best_clock = clock;
890 bestppm = ppm;
891 found = true;
a0c4da24
JB		 892 }
893 }
894 }
895 }
a0c4da24 896
49e497ef 897 return found;
a0c4da24 898}
a4fc5ed6 899
ef9348c8 900static bool
a93e255f
ACO		 901chv_find_best_dpll(const intel_limit_t *limit,
902 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 903 int target, int refclk, intel_clock_t *match_clock,
904 intel_clock_t *best_clock)
905{
a93e255f 906 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 907 struct drm_device *dev = crtc->base.dev;
9ca3ba01 908 unsigned int best_error_ppm;
ef9348c8
CML		 909 intel_clock_t clock;
910 uint64_t m2;
911 int found = false;
912
913 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 914 best_error_ppm = 1000000;
ef9348c8
CML		 915
916 /*
917 * Based on hardware doc, the n always set to 1, and m1 always
918 * set to 2. If requires to support 200Mhz refclk, we need to
919 * revisit this because n may not 1 anymore.
920 */
921 clock.n = 1, clock.m1 = 2;
922 target *= 5; /* fast clock */
923
924 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
925 for (clock.p2 = limit->p2.p2_fast;
926 clock.p2 >= limit->p2.p2_slow;
927 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 928 unsigned int error_ppm;
ef9348c8
CML		 929
930 clock.p = clock.p1 * clock.p2;
931
932 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
933 clock.n) << 22, refclk * clock.m1);
934
935 if (m2 > INT_MAX/clock.m1)
936 continue;
937
938 clock.m2 = m2;
939
940 chv_clock(refclk, &clock);
941
942 if (!intel_PLL_is_valid(dev, limit, &clock))
943 continue;
944
9ca3ba01
ID		 945 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
946 best_error_ppm, &error_ppm))
947 continue;
948
949 *best_clock = clock;
950 best_error_ppm = error_ppm;
951 found = true;
ef9348c8
CML		 952 }
953 }
954
955 return found;
956}
957
20ddf665
VS		 958bool intel_crtc_active(struct drm_crtc *crtc)
959{
960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
961
962 /* Be paranoid as we can arrive here with only partial
963 * state retrieved from the hardware during setup.
964 *
241bfc38 965 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 966 * as Haswell has gained clock readout/fastboot support.
967 *
66e514c1 968 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 969 * properly reconstruct framebuffers.
c3d1f436
MR		 970 *
971 * FIXME: The intel_crtc->active here should be switched to
972 * crtc->state->active once we have proper CRTC states wired up
973 * for atomic.
20ddf665 974 */
c3d1f436 975 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 976 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 977}
978
a5c961d1
PZ		 979enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
980 enum pipe pipe)
981{
982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
6e3c9717 985 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 986}
987
fbf49ea2
VS		 988static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
989{
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 reg = PIPEDSL(pipe);
992 u32 line1, line2;
993 u32 line_mask;
994
995 if (IS_GEN2(dev))
996 line_mask = DSL_LINEMASK_GEN2;
997 else
998 line_mask = DSL_LINEMASK_GEN3;
999
1000 line1 = I915_READ(reg) & line_mask;
1001 mdelay(5);
1002 line2 = I915_READ(reg) & line_mask;
1003
1004 return line1 == line2;
1005}
1006
ab7ad7f6
KP		 1007/*
1008 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1009 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1010 *
1011 * After disabling a pipe, we can't wait for vblank in the usual way,
1012 * spinning on the vblank interrupt status bit, since we won't actually
1013 * see an interrupt when the pipe is disabled.
1014 *
ab7ad7f6
KP		 1015 * On Gen4 and above:
1016 * wait for the pipe register state bit to turn off
1017 *
1018 * Otherwise:
1019 * wait for the display line value to settle (it usually
1020 * ends up stopping at the start of the next frame).
58e10eb9 1021 *
9d0498a2 1022 */
575f7ab7 1023static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1024{
575f7ab7 1025 struct drm_device *dev = crtc->base.dev;
9d0498a2 1026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1028 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1029
1030 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1031 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1032
1033 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1034 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1035 100))
284637d9 1036 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1037 } else {
ab7ad7f6 1038 /* Wait for the display line to settle */
fbf49ea2 1039 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1040 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1041 }
79e53945
JB		 1042}
1043
b0ea7d37
DL		 1044/*
1045 * ibx_digital_port_connected - is the specified port connected?
1046 * @dev_priv: i915 private structure
1047 * @port: the port to test
1048 *
1049 * Returns true if @port is connected, false otherwise.
1050 */
1051bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1052 struct intel_digital_port *port)
1053{
1054 u32 bit;
1055
c36346e3 1056 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1057 switch (port->port) {
c36346e3
DL		 1058 case PORT_B:
1059 bit = SDE_PORTB_HOTPLUG;
1060 break;
1061 case PORT_C:
1062 bit = SDE_PORTC_HOTPLUG;
1063 break;
1064 case PORT_D:
1065 bit = SDE_PORTD_HOTPLUG;
1066 break;
1067 default:
1068 return true;
1069 }
1070 } else {
eba905b2 1071 switch (port->port) {
c36346e3
DL		 1072 case PORT_B:
1073 bit = SDE_PORTB_HOTPLUG_CPT;
1074 break;
1075 case PORT_C:
1076 bit = SDE_PORTC_HOTPLUG_CPT;
1077 break;
1078 case PORT_D:
1079 bit = SDE_PORTD_HOTPLUG_CPT;
1080 break;
1081 default:
1082 return true;
1083 }
b0ea7d37
DL		 1084 }
1085
1086 return I915_READ(SDEISR) & bit;
1087}
1088
b24e7179
JB		 1089static const char *state_string(bool enabled)
1090{
1091 return enabled ? "on" : "off";
1092}
1093
1094/* Only for pre-ILK configs */
55607e8a
DV		 1095void assert_pll(struct drm_i915_private *dev_priv,
1096 enum pipe pipe, bool state)
b24e7179
JB		 1097{
1098 int reg;
1099 u32 val;
1100 bool cur_state;
1101
1102 reg = DPLL(pipe);
1103 val = I915_READ(reg);
1104 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1105 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1106 "PLL state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108}
b24e7179 1109
23538ef1
JN		 1110/* XXX: the dsi pll is shared between MIPI DSI ports */
1111static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1112{
1113 u32 val;
1114 bool cur_state;
1115
1116 mutex_lock(&dev_priv->dpio_lock);
1117 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1118 mutex_unlock(&dev_priv->dpio_lock);
1119
1120 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1121 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1122 "DSI PLL state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1126#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1127
55607e8a 1128struct intel_shared_dpll *
e2b78267
DV		 1129intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1130{
1131 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1132
6e3c9717 1133 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1134 return NULL;
1135
6e3c9717 1136 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1137}
1138
040484af 1139/* For ILK+ */
55607e8a
DV		 1140void assert_shared_dpll(struct drm_i915_private *dev_priv,
1141 struct intel_shared_dpll *pll,
1142 bool state)
040484af 1143{
040484af 1144 bool cur_state;
5358901f 1145 struct intel_dpll_hw_state hw_state;
040484af 1146
92b27b08 1147 if (WARN (!pll,
46edb027 1148 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1149 return;
ee7b9f93 1150
5358901f 1151 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1152 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1153 "%s assertion failure (expected %s, current %s)\n",
1154 pll->name, state_string(state), state_string(cur_state));
040484af 1155}
040484af
JB		 1156
1157static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159{
1160 int reg;
1161 u32 val;
1162 bool cur_state;
ad80a810
PZ		 1163 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1164 pipe);
040484af 1165
affa9354
PZ		 1166 if (HAS_DDI(dev_priv->dev)) {
1167 /* DDI does not have a specific FDI_TX register */
ad80a810 1168 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1169 val = I915_READ(reg);
ad80a810 1170 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1171 } else {
1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 cur_state = !!(val & FDI_TX_ENABLE);
1175 }
e2c719b7 1176 I915_STATE_WARN(cur_state != state,
040484af
JB		 1177 "FDI TX state assertion failure (expected %s, current %s)\n",
1178 state_string(state), state_string(cur_state));
1179}
1180#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1181#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1182
1183static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1184 enum pipe pipe, bool state)
1185{
1186 int reg;
1187 u32 val;
1188 bool cur_state;
1189
d63fa0dc
PZ		 1190 reg = FDI_RX_CTL(pipe);
1191 val = I915_READ(reg);
1192 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1193 I915_STATE_WARN(cur_state != state,
040484af
JB		 1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 state_string(state), state_string(cur_state));
1196}
1197#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202{
1203 int reg;
1204 u32 val;
1205
1206 /* ILK FDI PLL is always enabled */
3d13ef2e 1207 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1208 return;
1209
bf507ef7 1210 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1211 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1212 return;
1213
040484af
JB		 1214 reg = FDI_TX_CTL(pipe);
1215 val = I915_READ(reg);
e2c719b7 1216 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1217}
1218
55607e8a
DV		 1219void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
040484af
JB		 1221{
1222 int reg;
1223 u32 val;
55607e8a 1224 bool cur_state;
040484af
JB		 1225
1226 reg = FDI_RX_CTL(pipe);
1227 val = I915_READ(reg);
55607e8a 1228 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1229 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1230 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1231 state_string(state), state_string(cur_state));
040484af
JB		 1232}
1233
b680c37a
DV		 1234void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1235 enum pipe pipe)
ea0760cf 1236{
bedd4dba
JN		 1237 struct drm_device *dev = dev_priv->dev;
1238 int pp_reg;
ea0760cf
JB		 1239 u32 val;
1240 enum pipe panel_pipe = PIPE_A;
0de3b485 1241 bool locked = true;
ea0760cf 1242
bedd4dba
JN		 1243 if (WARN_ON(HAS_DDI(dev)))
1244 return;
1245
1246 if (HAS_PCH_SPLIT(dev)) {
1247 u32 port_sel;
1248
ea0760cf 1249 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1250 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1251
1252 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1253 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1254 panel_pipe = PIPE_B;
1255 /* XXX: else fix for eDP */
1256 } else if (IS_VALLEYVIEW(dev)) {
1257 /* presumably write lock depends on pipe, not port select */
1258 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1259 panel_pipe = pipe;
ea0760cf
JB		 1260 } else {
1261 pp_reg = PP_CONTROL;
bedd4dba
JN		 1262 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1263 panel_pipe = PIPE_B;
ea0760cf
JB		 1264 }
1265
1266 val = I915_READ(pp_reg);
1267 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1268 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1269 locked = false;
1270
e2c719b7 1271 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1272 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1273 pipe_name(pipe));
ea0760cf
JB		 1274}
1275
93ce0ba6
JN		 1276static void assert_cursor(struct drm_i915_private *dev_priv,
1277 enum pipe pipe, bool state)
1278{
1279 struct drm_device *dev = dev_priv->dev;
1280 bool cur_state;
1281
d9d82081 1282 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1283 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1284 else
5efb3e28 1285 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1286
e2c719b7 1287 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1288 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1289 pipe_name(pipe), state_string(state), state_string(cur_state));
1290}
1291#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1292#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1293
b840d907
JB		 1294void assert_pipe(struct drm_i915_private *dev_priv,
1295 enum pipe pipe, bool state)
b24e7179
JB		 1296{
1297 int reg;
1298 u32 val;
63d7bbe9 1299 bool cur_state;
702e7a56
PZ		 1300 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1301 pipe);
b24e7179 1302
b6b5d049
VS		 1303 /* if we need the pipe quirk it must be always on */
1304 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1305 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1306 state = true;
1307
f458ebbc 1308 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1309 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1310 cur_state = false;
1311 } else {
1312 reg = PIPECONF(cpu_transcoder);
1313 val = I915_READ(reg);
1314 cur_state = !!(val & PIPECONF_ENABLE);
1315 }
1316
e2c719b7 1317 I915_STATE_WARN(cur_state != state,
63d7bbe9 1318 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1319 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1320}
1321
931872fc
CW		 1322static void assert_plane(struct drm_i915_private *dev_priv,
1323 enum plane plane, bool state)
b24e7179
JB		 1324{
1325 int reg;
1326 u32 val;
931872fc 1327 bool cur_state;
b24e7179
JB		 1328
1329 reg = DSPCNTR(plane);
1330 val = I915_READ(reg);
931872fc 1331 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1332 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1333 "plane %c assertion failure (expected %s, current %s)\n",
1334 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1335}
1336
931872fc
CW		 1337#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1338#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1339
b24e7179
JB		 1340static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe)
1342{
653e1026 1343 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1344 int reg, i;
1345 u32 val;
1346 int cur_pipe;
1347
653e1026
VS		 1348 /* Primary planes are fixed to pipes on gen4+ */
1349 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1350 reg = DSPCNTR(pipe);
1351 val = I915_READ(reg);
e2c719b7 1352 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1353 "plane %c assertion failure, should be disabled but not\n",
1354 plane_name(pipe));
19ec1358 1355 return;
28c05794 1356 }
19ec1358 1357
b24e7179 1358 /* Need to check both planes against the pipe */
055e393f 1359 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1360 reg = DSPCNTR(i);
1361 val = I915_READ(reg);
1362 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1363 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1364 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1365 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1366 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1367 }
1368}
1369
19332d7a
JB		 1370static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe)
1372{
20674eef 1373 struct drm_device *dev = dev_priv->dev;
1fe47785 1374 int reg, sprite;
19332d7a
JB		 1375 u32 val;
1376
7feb8b88 1377 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1378 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1379 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1380 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1381 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1382 sprite, pipe_name(pipe));
1383 }
1384 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1385 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1386 reg = SPCNTR(pipe, sprite);
20674eef 1387 val = I915_READ(reg);
e2c719b7 1388 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1389 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1390 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1391 }
1392 } else if (INTEL_INFO(dev)->gen >= 7) {
1393 reg = SPRCTL(pipe);
19332d7a 1394 val = I915_READ(reg);
e2c719b7 1395 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1396 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1397 plane_name(pipe), pipe_name(pipe));
1398 } else if (INTEL_INFO(dev)->gen >= 5) {
1399 reg = DVSCNTR(pipe);
19332d7a 1400 val = I915_READ(reg);
e2c719b7 1401 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1402 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1403 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1404 }
1405}
1406
08c71e5e
VS		 1407static void assert_vblank_disabled(struct drm_crtc *crtc)
1408{
e2c719b7 1409 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1410 drm_crtc_vblank_put(crtc);
1411}
1412
89eff4be 1413static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1414{
1415 u32 val;
1416 bool enabled;
1417
e2c719b7 1418 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1419
92f2584a
JB		 1420 val = I915_READ(PCH_DREF_CONTROL);
1421 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1422 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1423 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1424}
1425
ab9412ba
DV		 1426static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe)
92f2584a
JB		 1428{
1429 int reg;
1430 u32 val;
1431 bool enabled;
1432
ab9412ba 1433 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1434 val = I915_READ(reg);
1435 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1436 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1437 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1438 pipe_name(pipe));
92f2584a
JB		 1439}
1440
4e634389
KP		 1441static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1443{
1444 if ((val & DP_PORT_EN) == 0)
1445 return false;
1446
1447 if (HAS_PCH_CPT(dev_priv->dev)) {
1448 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1449 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1450 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1451 return false;
44f37d1f
CML		 1452 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1453 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1454 return false;
f0575e92
KP		 1455 } else {
1456 if ((val & DP_PIPE_MASK) != (pipe << 30))
1457 return false;
1458 }
1459 return true;
1460}
1461
1519b995
KP		 1462static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe, u32 val)
1464{
dc0fa718 1465 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1466 return false;
1467
1468 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1469 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1470 return false;
44f37d1f
CML		 1471 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1472 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1473 return false;
1519b995 1474 } else {
dc0fa718 1475 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1476 return false;
1477 }
1478 return true;
1479}
1480
1481static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1482 enum pipe pipe, u32 val)
1483{
1484 if ((val & LVDS_PORT_EN) == 0)
1485 return false;
1486
1487 if (HAS_PCH_CPT(dev_priv->dev)) {
1488 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1489 return false;
1490 } else {
1491 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1492 return false;
1493 }
1494 return true;
1495}
1496
1497static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
1500 if ((val & ADPA_DAC_ENABLE) == 0)
1501 return false;
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1504 return false;
1505 } else {
1506 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1507 return false;
1508 }
1509 return true;
1510}
1511
291906f1 1512static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1513 enum pipe pipe, int reg, u32 port_sel)
291906f1 1514{
47a05eca 1515 u32 val = I915_READ(reg);
e2c719b7 1516 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1517 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1518 reg, pipe_name(pipe));
de9a35ab 1519
e2c719b7 1520 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1521 && (val & DP_PIPEB_SELECT),
de9a35ab 1522 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1523}
1524
1525static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1526 enum pipe pipe, int reg)
1527{
47a05eca 1528 u32 val = I915_READ(reg);
e2c719b7 1529 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1530 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1531 reg, pipe_name(pipe));
de9a35ab 1532
e2c719b7 1533 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1534 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1535 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1536}
1537
1538static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1539 enum pipe pipe)
1540{
1541 int reg;
1542 u32 val;
291906f1 1543
f0575e92
KP		 1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1545 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1546 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1547
1548 reg = PCH_ADPA;
1549 val = I915_READ(reg);
e2c719b7 1550 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1551 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1552 pipe_name(pipe));
291906f1
JB		 1553
1554 reg = PCH_LVDS;
1555 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1557 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 pipe_name(pipe));
291906f1 1559
e2debe91
PZ		 1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1561 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1562 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1563}
1564
40e9cf64
JB		 1565static void intel_init_dpio(struct drm_device *dev)
1566{
1567 struct drm_i915_private *dev_priv = dev->dev_private;
1568
1569 if (!IS_VALLEYVIEW(dev))
1570 return;
1571
a09caddd
CML		 1572 /*
1573 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1574 * CHV x1 PHY (DP/HDMI D)
1575 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1576 */
1577 if (IS_CHERRYVIEW(dev)) {
1578 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1580 } else {
1581 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1582 }
5382f5f3
JB		 1583}
1584
d288f65f 1585static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1586 const struct intel_crtc_state *pipe_config)
87442f73 1587{
426115cf
DV		 1588 struct drm_device *dev = crtc->base.dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 int reg = DPLL(crtc->pipe);
d288f65f 1591 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1592
426115cf 1593 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1594
1595 /* No really, not for ILK+ */
1596 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1597
1598 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1599 if (IS_MOBILE(dev_priv->dev))
426115cf 1600 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1601
426115cf
DV		 1602 I915_WRITE(reg, dpll);
1603 POSTING_READ(reg);
1604 udelay(150);
1605
1606 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1607 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1608
d288f65f 1609 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1610 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1611
1612 /* We do this three times for luck */
426115cf 1613 I915_WRITE(reg, dpll);
87442f73
DV		 1614 POSTING_READ(reg);
1615 udelay(150); /* wait for warmup */
426115cf 1616 I915_WRITE(reg, dpll);
87442f73
DV		 1617 POSTING_READ(reg);
1618 udelay(150); /* wait for warmup */
426115cf 1619 I915_WRITE(reg, dpll);
87442f73
DV		 1620 POSTING_READ(reg);
1621 udelay(150); /* wait for warmup */
1622}
1623
d288f65f 1624static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1625 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1626{
1627 struct drm_device *dev = crtc->base.dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 int pipe = crtc->pipe;
1630 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1631 u32 tmp;
1632
1633 assert_pipe_disabled(dev_priv, crtc->pipe);
1634
1635 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1636
1637 mutex_lock(&dev_priv->dpio_lock);
1638
1639 /* Enable back the 10bit clock to display controller */
1640 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1641 tmp |= DPIO_DCLKP_EN;
1642 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1643
1644 /*
1645 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1646 */
1647 udelay(1);
1648
1649 /* Enable PLL */
d288f65f 1650 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1651
1652 /* Check PLL is locked */
a11b0703 1653 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1654 DRM_ERROR("PLL %d failed to lock\n", pipe);
1655
a11b0703 1656 /* not sure when this should be written */
d288f65f 1657 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1658 POSTING_READ(DPLL_MD(pipe));
1659
9d556c99
CML		 1660 mutex_unlock(&dev_priv->dpio_lock);
1661}
1662
1c4e0274
VS		 1663static int intel_num_dvo_pipes(struct drm_device *dev)
1664{
1665 struct intel_crtc *crtc;
1666 int count = 0;
1667
1668 for_each_intel_crtc(dev, crtc)
1669 count += crtc->active &&
409ee761 1670 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1671
1672 return count;
1673}
1674
66e3d5c0 1675static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1676{
66e3d5c0
DV		 1677 struct drm_device *dev = crtc->base.dev;
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 int reg = DPLL(crtc->pipe);
6e3c9717 1680 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1681
66e3d5c0 1682 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1683
63d7bbe9 1684 /* No really, not for ILK+ */
3d13ef2e 1685 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1686
1687 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1688 if (IS_MOBILE(dev) && !IS_I830(dev))
1689 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1690
1c4e0274
VS		 1691 /* Enable DVO 2x clock on both PLLs if necessary */
1692 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1693 /*
1694 * It appears to be important that we don't enable this
1695 * for the current pipe before otherwise configuring the
1696 * PLL. No idea how this should be handled if multiple
1697 * DVO outputs are enabled simultaneosly.
1698 */
1699 dpll |= DPLL_DVO_2X_MODE;
1700 I915_WRITE(DPLL(!crtc->pipe),
1701 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1702 }
66e3d5c0
DV		 1703
1704 /* Wait for the clocks to stabilize. */
1705 POSTING_READ(reg);
1706 udelay(150);
1707
1708 if (INTEL_INFO(dev)->gen >= 4) {
1709 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1710 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1711 } else {
1712 /* The pixel multiplier can only be updated once the
1713 * DPLL is enabled and the clocks are stable.
1714 *
1715 * So write it again.
1716 */
1717 I915_WRITE(reg, dpll);
1718 }
63d7bbe9
JB		 1719
1720 /* We do this three times for luck */
66e3d5c0 1721 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1722 POSTING_READ(reg);
1723 udelay(150); /* wait for warmup */
66e3d5c0 1724 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1725 POSTING_READ(reg);
1726 udelay(150); /* wait for warmup */
66e3d5c0 1727 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1728 POSTING_READ(reg);
1729 udelay(150); /* wait for warmup */
1730}
1731
1732/**
50b44a44 1733 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1734 * @dev_priv: i915 private structure
1735 * @pipe: pipe PLL to disable
1736 *
1737 * Disable the PLL for @pipe, making sure the pipe is off first.
1738 *
1739 * Note! This is for pre-ILK only.
1740 */
1c4e0274 1741static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1742{
1c4e0274
VS		 1743 struct drm_device *dev = crtc->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
1745 enum pipe pipe = crtc->pipe;
1746
1747 /* Disable DVO 2x clock on both PLLs if necessary */
1748 if (IS_I830(dev) &&
409ee761 1749 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1750 intel_num_dvo_pipes(dev) == 1) {
1751 I915_WRITE(DPLL(PIPE_B),
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1753 I915_WRITE(DPLL(PIPE_A),
1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1755 }
1756
b6b5d049
VS		 1757 /* Don't disable pipe or pipe PLLs if needed */
1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1760 return;
1761
1762 /* Make sure the pipe isn't still relying on us */
1763 assert_pipe_disabled(dev_priv, pipe);
1764
50b44a44
DV		 1765 I915_WRITE(DPLL(pipe), 0);
1766 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1767}
1768
f6071166
JB		 1769static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1770{
1771 u32 val = 0;
1772
1773 /* Make sure the pipe isn't still relying on us */
1774 assert_pipe_disabled(dev_priv, pipe);
1775
e5cbfbfb
ID		 1776 /*
1777 * Leave integrated clock source and reference clock enabled for pipe B.
1778 * The latter is needed for VGA hotplug / manual detection.
1779 */
f6071166 1780 if (pipe == PIPE_B)
e5cbfbfb 1781 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1782 I915_WRITE(DPLL(pipe), val);
1783 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1784
1785}
1786
1787static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788{
d752048d 1789 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1790 u32 val;
1791
a11b0703
VS		 1792 /* Make sure the pipe isn't still relying on us */
1793 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1794
a11b0703 1795 /* Set PLL en = 0 */
d17ec4ce 1796 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1797 if (pipe != PIPE_A)
1798 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1799 I915_WRITE(DPLL(pipe), val);
1800 POSTING_READ(DPLL(pipe));
d752048d
VS		 1801
1802 mutex_lock(&dev_priv->dpio_lock);
1803
1804 /* Disable 10bit clock to display controller */
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1806 val &= ~DPIO_DCLKP_EN;
1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1808
61407f6d
VS		 1809 /* disable left/right clock distribution */
1810 if (pipe != PIPE_B) {
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1812 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1814 } else {
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1816 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1818 }
1819
d752048d 1820 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1821}
1822
e4607fcf
CML		 1823void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1824 struct intel_digital_port *dport)
89b667f8
JB		 1825{
1826 u32 port_mask;
00fc31b7 1827 int dpll_reg;
89b667f8 1828
e4607fcf
CML		 1829 switch (dport->port) {
1830 case PORT_B:
89b667f8 1831 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1832 dpll_reg = DPLL(0);
e4607fcf
CML		 1833 break;
1834 case PORT_C:
89b667f8 1835 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_D:
1839 port_mask = DPLL_PORTD_READY_MASK;
1840 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1841 break;
1842 default:
1843 BUG();
1844 }
89b667f8 1845
00fc31b7 1846 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1847 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1848 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1849}
1850
b14b1055
DV		 1851static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1852{
1853 struct drm_device *dev = crtc->base.dev;
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1856
be19f0ff
CW		 1857 if (WARN_ON(pll == NULL))
1858 return;
1859
3e369b76 1860 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1861 if (pll->active == 0) {
1862 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1863 WARN_ON(pll->on);
1864 assert_shared_dpll_disabled(dev_priv, pll);
1865
1866 pll->mode_set(dev_priv, pll);
1867 }
1868}
1869
92f2584a 1870/**
85b3894f 1871 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1872 * @dev_priv: i915 private structure
1873 * @pipe: pipe PLL to enable
1874 *
1875 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1876 * drives the transcoder clock.
1877 */
85b3894f 1878static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1879{
3d13ef2e
DL		 1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1883
87a875bb 1884 if (WARN_ON(pll == NULL))
48da64a8
CW		 1885 return;
1886
3e369b76 1887 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1888 return;
ee7b9f93 1889
74dd6928 1890 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1891 pll->name, pll->active, pll->on,
e2b78267 1892 crtc->base.base.id);
92f2584a 1893
cdbd2316
DV		 1894 if (pll->active++) {
1895 WARN_ON(!pll->on);
e9d6944e 1896 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1897 return;
1898 }
f4a091c7 1899 WARN_ON(pll->on);
ee7b9f93 1900
bd2bb1b9
PZ		 1901 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1902
46edb027 1903 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1904 pll->enable(dev_priv, pll);
ee7b9f93 1905 pll->on = true;
92f2584a
JB		 1906}
1907
f6daaec2 1908static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1909{
3d13ef2e
DL		 1910 struct drm_device *dev = crtc->base.dev;
1911 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1912 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1913
92f2584a 1914 /* PCH only available on ILK+ */
3d13ef2e 1915 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1916 if (WARN_ON(pll == NULL))
ee7b9f93 1917 return;
92f2584a 1918
3e369b76 1919 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1920 return;
7a419866 1921
46edb027
DV		 1922 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1923 pll->name, pll->active, pll->on,
e2b78267 1924 crtc->base.base.id);
7a419866 1925
48da64a8 1926 if (WARN_ON(pll->active == 0)) {
e9d6944e 1927 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1928 return;
1929 }
1930
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1932 WARN_ON(!pll->on);
cdbd2316 1933 if (--pll->active)
7a419866 1934 return;
ee7b9f93 1935
46edb027 1936 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1937 pll->disable(dev_priv, pll);
ee7b9f93 1938 pll->on = false;
bd2bb1b9
PZ		 1939
1940 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1941}
1942
b8a4f404
PZ		 1943static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1944 enum pipe pipe)
040484af 1945{
23670b32 1946 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1949 uint32_t reg, val, pipeconf_val;
040484af
JB		 1950
1951 /* PCH only available on ILK+ */
55522f37 1952 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1953
1954 /* Make sure PCH DPLL is enabled */
e72f9fbf 1955 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1956 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1957
1958 /* FDI must be feeding us bits for PCH ports */
1959 assert_fdi_tx_enabled(dev_priv, pipe);
1960 assert_fdi_rx_enabled(dev_priv, pipe);
1961
23670b32
DV		 1962 if (HAS_PCH_CPT(dev)) {
1963 /* Workaround: Set the timing override bit before enabling the
1964 * pch transcoder. */
1965 reg = TRANS_CHICKEN2(pipe);
1966 val = I915_READ(reg);
1967 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1968 I915_WRITE(reg, val);
59c859d6 1969 }
23670b32 1970
ab9412ba 1971 reg = PCH_TRANSCONF(pipe);
040484af 1972 val = I915_READ(reg);
5f7f726d 1973 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1974
1975 if (HAS_PCH_IBX(dev_priv->dev)) {
1976 /*
1977 * make the BPC in transcoder be consistent with
1978 * that in pipeconf reg.
1979 */
dfd07d72
DV		 1980 val &= ~PIPECONF_BPC_MASK;
1981 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1982 }
5f7f726d
PZ		 1983
1984 val &= ~TRANS_INTERLACE_MASK;
1985 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1986 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1987 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1988 val |= TRANS_LEGACY_INTERLACED_ILK;
1989 else
1990 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
040484af
JB		 1994 I915_WRITE(reg, val | TRANS_ENABLE);
1995 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1996 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1997}
1998
8fb033d7 1999static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2000 enum transcoder cpu_transcoder)
040484af 2001{
8fb033d7 2002 u32 val, pipeconf_val;
8fb033d7
PZ		 2003
2004 /* PCH only available on ILK+ */
55522f37 2005 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2006
8fb033d7 2007 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2008 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2009 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2010
223a6fdf
PZ		 2011 /* Workaround: set timing override bit. */
2012 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2013 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2014 I915_WRITE(_TRANSA_CHICKEN2, val);
2015
25f3ef11 2016 val = TRANS_ENABLE;
937bb610 2017 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2018
9a76b1c6
PZ		 2019 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2020 PIPECONF_INTERLACED_ILK)
a35f2679 2021 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2022 else
2023 val |= TRANS_PROGRESSIVE;
2024
ab9412ba
DV		 2025 I915_WRITE(LPT_TRANSCONF, val);
2026 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2027 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2028}
2029
b8a4f404
PZ		 2030static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2031 enum pipe pipe)
040484af 2032{
23670b32
DV		 2033 struct drm_device *dev = dev_priv->dev;
2034 uint32_t reg, val;
040484af
JB		 2035
2036 /* FDI relies on the transcoder */
2037 assert_fdi_tx_disabled(dev_priv, pipe);
2038 assert_fdi_rx_disabled(dev_priv, pipe);
2039
291906f1
JB		 2040 /* Ports must be off as well */
2041 assert_pch_ports_disabled(dev_priv, pipe);
2042
ab9412ba 2043 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2044 val = I915_READ(reg);
2045 val &= ~TRANS_ENABLE;
2046 I915_WRITE(reg, val);
2047 /* wait for PCH transcoder off, transcoder state */
2048 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2049 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2050
2051 if (!HAS_PCH_IBX(dev)) {
2052 /* Workaround: Clear the timing override chicken bit again. */
2053 reg = TRANS_CHICKEN2(pipe);
2054 val = I915_READ(reg);
2055 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2056 I915_WRITE(reg, val);
2057 }
040484af
JB		 2058}
2059
ab4d966c 2060static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2061{
8fb033d7
PZ		 2062 u32 val;
2063
ab9412ba 2064 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2065 val &= ~TRANS_ENABLE;
ab9412ba 2066 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2067 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2068 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2069 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2070
2071 /* Workaround: clear timing override bit. */
2072 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2074 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2075}
2076
b24e7179 2077/**
309cfea8 2078 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2079 * @crtc: crtc responsible for the pipe
b24e7179 2080 *
0372264a 2081 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2082 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2083 */
e1fdc473 2084static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2085{
0372264a
PZ		 2086 struct drm_device *dev = crtc->base.dev;
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2090 pipe);
1a240d4d 2091 enum pipe pch_transcoder;
b24e7179
JB		 2092 int reg;
2093 u32 val;
2094
58c6eaa2 2095 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2096 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2097 assert_sprites_disabled(dev_priv, pipe);
2098
681e5811 2099 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2100 pch_transcoder = TRANSCODER_A;
2101 else
2102 pch_transcoder = pipe;
2103
b24e7179
JB		 2104 /*
2105 * A pipe without a PLL won't actually be able to drive bits from
2106 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2107 * need the check.
2108 */
2109 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2111 assert_dsi_pll_enabled(dev_priv);
2112 else
2113 assert_pll_enabled(dev_priv, pipe);
040484af 2114 else {
6e3c9717 2115 if (crtc->config->has_pch_encoder) {
040484af 2116 /* if driving the PCH, we need FDI enabled */
cc391bbb 2117 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2118 assert_fdi_tx_pll_enabled(dev_priv,
2119 (enum pipe) cpu_transcoder);
040484af
JB		 2120 }
2121 /* FIXME: assert CPU port conditions for SNB+ */
2122 }
b24e7179 2123
702e7a56 2124 reg = PIPECONF(cpu_transcoder);
b24e7179 2125 val = I915_READ(reg);
7ad25d48 2126 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2129 return;
7ad25d48 2130 }
00d70b15
CW		 2131
2132 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2133 POSTING_READ(reg);
b24e7179
JB		 2134}
2135
2136/**
309cfea8 2137 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2138 * @crtc: crtc whose pipes is to be disabled
b24e7179 2139 *
575f7ab7
VS		 2140 * Disable the pipe of @crtc, making sure that various hardware
2141 * specific requirements are met, if applicable, e.g. plane
2142 * disabled, panel fitter off, etc.
b24e7179
JB		 2143 *
2144 * Will wait until the pipe has shut down before returning.
2145 */
575f7ab7 2146static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2147{
575f7ab7 2148 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2149 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2150 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2151 int reg;
2152 u32 val;
2153
2154 /*
2155 * Make sure planes won't keep trying to pump pixels to us,
2156 * or we might hang the display.
2157 */
2158 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2159 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2160 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
00d70b15
CW		 2164 if ((val & PIPECONF_ENABLE) == 0)
2165 return;
2166
67adc644
VS		 2167 /*
2168 * Double wide has implications for planes
2169 * so best keep it disabled when not needed.
2170 */
6e3c9717 2171 if (crtc->config->double_wide)
67adc644
VS		 2172 val &= ~PIPECONF_DOUBLE_WIDE;
2173
2174 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2177 val &= ~PIPECONF_ENABLE;
2178
2179 I915_WRITE(reg, val);
2180 if ((val & PIPECONF_ENABLE) == 0)
2181 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2182}
2183
d74362c9
KP		 2184/*
2185 * Plane regs are double buffered, going from enabled->disabled needs a
2186 * trigger in order to latch. The display address reg provides this.
2187 */
1dba99f4
VS		 2188void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2189 enum plane plane)
d74362c9 2190{
3d13ef2e
DL		 2191 struct drm_device *dev = dev_priv->dev;
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2193
2194 I915_WRITE(reg, I915_READ(reg));
2195 POSTING_READ(reg);
d74362c9
KP		 2196}
2197
b24e7179 2198/**
262ca2b0 2199 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2200 * @plane: plane to be enabled
2201 * @crtc: crtc for the plane
b24e7179 2202 *
fdd508a6 2203 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2204 */
fdd508a6
VS		 2205static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2206 struct drm_crtc *crtc)
b24e7179 2207{
fdd508a6
VS		 2208 struct drm_device *dev = plane->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2211
2212 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2214
98ec7739
VS		 2215 if (intel_crtc->primary_enabled)
2216 return;
0037f71c 2217
4c445e0e 2218 intel_crtc->primary_enabled = true;
939c2fe8 2219
fdd508a6
VS		 2220 dev_priv->display.update_primary_plane(crtc, plane->fb,
2221 crtc->x, crtc->y);
33c3b0d1
VS		 2222
2223 /*
2224 * BDW signals flip done immediately if the plane
2225 * is disabled, even if the plane enable is already
2226 * armed to occur at the next vblank :(
2227 */
2228 if (IS_BROADWELL(dev))
2229 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2230}
2231
b24e7179 2232/**
262ca2b0 2233 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2234 * @plane: plane to be disabled
2235 * @crtc: crtc for the plane
b24e7179 2236 *
fdd508a6 2237 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2238 */
fdd508a6
VS		 2239static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2240 struct drm_crtc *crtc)
b24e7179 2241{
fdd508a6
VS		 2242 struct drm_device *dev = plane->dev;
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2245
32b7eeec
MR		 2246 if (WARN_ON(!intel_crtc->active))
2247 return;
b24e7179 2248
98ec7739
VS		 2249 if (!intel_crtc->primary_enabled)
2250 return;
0037f71c 2251
4c445e0e 2252 intel_crtc->primary_enabled = false;
939c2fe8 2253
fdd508a6
VS		 2254 dev_priv->display.update_primary_plane(crtc, plane->fb,
2255 crtc->x, crtc->y);
b24e7179
JB		 2256}
2257
693db184
CW		 2258static bool need_vtd_wa(struct drm_device *dev)
2259{
2260#ifdef CONFIG_INTEL_IOMMU
2261 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2262 return true;
2263#endif
2264 return false;
2265}
2266
50470bb0 2267unsigned int
6761dd31
TU		 2268intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2269 uint64_t fb_format_modifier)
a57ce0b2 2270{
6761dd31
TU		 2271 unsigned int tile_height;
2272 uint32_t pixel_bytes;
a57ce0b2 2273
b5d0e9bf
DL		 2274 switch (fb_format_modifier) {
2275 case DRM_FORMAT_MOD_NONE:
2276 tile_height = 1;
2277 break;
2278 case I915_FORMAT_MOD_X_TILED:
2279 tile_height = IS_GEN2(dev) ? 16 : 8;
2280 break;
2281 case I915_FORMAT_MOD_Y_TILED:
2282 tile_height = 32;
2283 break;
2284 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2285 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2286 switch (pixel_bytes) {
b5d0e9bf 2287 default:
6761dd31 2288 case 1:
b5d0e9bf
DL		 2289 tile_height = 64;
2290 break;
6761dd31
TU		 2291 case 2:
2292 case 4:
b5d0e9bf
DL		 2293 tile_height = 32;
2294 break;
6761dd31 2295 case 8:
b5d0e9bf
DL		 2296 tile_height = 16;
2297 break;
6761dd31 2298 case 16:
b5d0e9bf
DL		 2299 WARN_ONCE(1,
2300 "128-bit pixels are not supported for display!");
2301 tile_height = 16;
2302 break;
2303 }
2304 break;
2305 default:
2306 MISSING_CASE(fb_format_modifier);
2307 tile_height = 1;
2308 break;
2309 }
091df6cb 2310
6761dd31
TU		 2311 return tile_height;
2312}
2313
2314unsigned int
2315intel_fb_align_height(struct drm_device *dev, unsigned int height,
2316 uint32_t pixel_format, uint64_t fb_format_modifier)
2317{
2318 return ALIGN(height, intel_tile_height(dev, pixel_format,
2319 fb_format_modifier));
a57ce0b2
JB		 2320}
2321
f64b98cd
TU		 2322static int
2323intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2324 const struct drm_plane_state *plane_state)
2325{
50470bb0 2326 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2327
f64b98cd
TU		 2328 *view = i915_ggtt_view_normal;
2329
50470bb0
TU		 2330 if (!plane_state)
2331 return 0;
2332
121920fa 2333 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2334 return 0;
2335
9abc4648 2336 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2337
2338 info->height = fb->height;
2339 info->pixel_format = fb->pixel_format;
2340 info->pitch = fb->pitches[0];
2341 info->fb_modifier = fb->modifier[0];
2342
f64b98cd
TU		 2343 return 0;
2344}
2345
127bd2ac 2346int
850c4cdc
TU		 2347intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2348 struct drm_framebuffer *fb,
82bc3b2d 2349 const struct drm_plane_state *plane_state,
a4872ba6 2350 struct intel_engine_cs *pipelined)
6b95a207 2351{
850c4cdc 2352 struct drm_device *dev = fb->dev;
ce453d81 2353 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2354 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2355 struct i915_ggtt_view view;
6b95a207
KH		 2356 u32 alignment;
2357 int ret;
2358
ebcdd39e
MR		 2359 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2360
7b911adc
TU		 2361 switch (fb->modifier[0]) {
2362 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2363 if (INTEL_INFO(dev)->gen >= 9)
2364 alignment = 256 * 1024;
2365 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2366 alignment = 128 * 1024;
a6c45cf0 2367 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2368 alignment = 4 * 1024;
2369 else
2370 alignment = 64 * 1024;
6b95a207 2371 break;
7b911adc 2372 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2373 if (INTEL_INFO(dev)->gen >= 9)
2374 alignment = 256 * 1024;
2375 else {
2376 /* pin() will align the object as required by fence */
2377 alignment = 0;
2378 }
6b95a207 2379 break;
7b911adc 2380 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2381 case I915_FORMAT_MOD_Yf_TILED:
2382 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2383 "Y tiling bo slipped through, driver bug!\n"))
2384 return -EINVAL;
2385 alignment = 1 * 1024 * 1024;
2386 break;
6b95a207 2387 default:
7b911adc
TU		 2388 MISSING_CASE(fb->modifier[0]);
2389 return -EINVAL;
6b95a207
KH		 2390 }
2391
f64b98cd
TU		 2392 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2393 if (ret)
2394 return ret;
2395
693db184
CW		 2396 /* Note that the w/a also requires 64 PTE of padding following the
2397 * bo. We currently fill all unused PTE with the shadow page and so
2398 * we should always have valid PTE following the scanout preventing
2399 * the VT-d warning.
2400 */
2401 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2402 alignment = 256 * 1024;
2403
d6dd6843
PZ		 2404 /*
2405 * Global gtt pte registers are special registers which actually forward
2406 * writes to a chunk of system memory. Which means that there is no risk
2407 * that the register values disappear as soon as we call
2408 * intel_runtime_pm_put(), so it is correct to wrap only the
2409 * pin/unpin/fence and not more.
2410 */
2411 intel_runtime_pm_get(dev_priv);
2412
ce453d81 2413 dev_priv->mm.interruptible = false;
e6617330 2414 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2415 &view);
48b956c5 2416 if (ret)
ce453d81 2417 goto err_interruptible;
6b95a207
KH		 2418
2419 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2420 * fence, whereas 965+ only requires a fence if using
2421 * framebuffer compression. For simplicity, we always install
2422 * a fence as the cost is not that onerous.
2423 */
06d98131 2424 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2425 if (ret)
2426 goto err_unpin;
1690e1eb 2427
9a5a53b3 2428 i915_gem_object_pin_fence(obj);
6b95a207 2429
ce453d81 2430 dev_priv->mm.interruptible = true;
d6dd6843 2431 intel_runtime_pm_put(dev_priv);
6b95a207 2432 return 0;
48b956c5
CW		 2433
2434err_unpin:
f64b98cd 2435 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2436err_interruptible:
2437 dev_priv->mm.interruptible = true;
d6dd6843 2438 intel_runtime_pm_put(dev_priv);
48b956c5 2439 return ret;
6b95a207
KH		 2440}
2441
82bc3b2d
TU		 2442static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2443 const struct drm_plane_state *plane_state)
1690e1eb 2444{
82bc3b2d 2445 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2446 struct i915_ggtt_view view;
2447 int ret;
82bc3b2d 2448
ebcdd39e
MR		 2449 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2450
f64b98cd
TU		 2451 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2452 WARN_ONCE(ret, "Couldn't get view from plane state!");
2453
1690e1eb 2454 i915_gem_object_unpin_fence(obj);
f64b98cd 2455 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2456}
2457
c2c75131
DV		 2458/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2459 * is assumed to be a power-of-two. */
bc752862
CW		 2460unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2461 unsigned int tiling_mode,
2462 unsigned int cpp,
2463 unsigned int pitch)
c2c75131 2464{
bc752862
CW		 2465 if (tiling_mode != I915_TILING_NONE) {
2466 unsigned int tile_rows, tiles;
c2c75131 2467
bc752862
CW		 2468 tile_rows = *y / 8;
2469 *y %= 8;
c2c75131 2470
bc752862
CW		 2471 tiles = *x / (512/cpp);
2472 *x %= 512/cpp;
2473
2474 return tile_rows * pitch * 8 + tiles * 4096;
2475 } else {
2476 unsigned int offset;
2477
2478 offset = *y * pitch + *x * cpp;
2479 *y = 0;
2480 *x = (offset & 4095) / cpp;
2481 return offset & -4096;
2482 }
c2c75131
DV		 2483}
2484
b35d63fa 2485static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2486{
2487 switch (format) {
2488 case DISPPLANE_8BPP:
2489 return DRM_FORMAT_C8;
2490 case DISPPLANE_BGRX555:
2491 return DRM_FORMAT_XRGB1555;
2492 case DISPPLANE_BGRX565:
2493 return DRM_FORMAT_RGB565;
2494 default:
2495 case DISPPLANE_BGRX888:
2496 return DRM_FORMAT_XRGB8888;
2497 case DISPPLANE_RGBX888:
2498 return DRM_FORMAT_XBGR8888;
2499 case DISPPLANE_BGRX101010:
2500 return DRM_FORMAT_XRGB2101010;
2501 case DISPPLANE_RGBX101010:
2502 return DRM_FORMAT_XBGR2101010;
2503 }
2504}
2505
bc8d7dff
DL		 2506static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2507{
2508 switch (format) {
2509 case PLANE_CTL_FORMAT_RGB_565:
2510 return DRM_FORMAT_RGB565;
2511 default:
2512 case PLANE_CTL_FORMAT_XRGB_8888:
2513 if (rgb_order) {
2514 if (alpha)
2515 return DRM_FORMAT_ABGR8888;
2516 else
2517 return DRM_FORMAT_XBGR8888;
2518 } else {
2519 if (alpha)
2520 return DRM_FORMAT_ARGB8888;
2521 else
2522 return DRM_FORMAT_XRGB8888;
2523 }
2524 case PLANE_CTL_FORMAT_XRGB_2101010:
2525 if (rgb_order)
2526 return DRM_FORMAT_XBGR2101010;
2527 else
2528 return DRM_FORMAT_XRGB2101010;
2529 }
2530}
2531
5724dbd1 2532static bool
f6936e29
DV		 2533intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2534 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2535{
2536 struct drm_device *dev = crtc->base.dev;
2537 struct drm_i915_gem_object *obj = NULL;
2538 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2539 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2540 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2541 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2542 PAGE_SIZE);
2543
2544 size_aligned -= base_aligned;
46f297fb 2545
ff2652ea
CW		 2546 if (plane_config->size == 0)
2547 return false;
2548
f37b5c2b
DV		 2549 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2550 base_aligned,
2551 base_aligned,
2552 size_aligned);
46f297fb 2553 if (!obj)
484b41dd 2554 return false;
46f297fb 2555
49af449b
DL		 2556 obj->tiling_mode = plane_config->tiling;
2557 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2558 obj->stride = fb->pitches[0];
46f297fb 2559
6bf129df
DL		 2560 mode_cmd.pixel_format = fb->pixel_format;
2561 mode_cmd.width = fb->width;
2562 mode_cmd.height = fb->height;
2563 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2564 mode_cmd.modifier[0] = fb->modifier[0];
2565 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2566
2567 mutex_lock(&dev->struct_mutex);
6bf129df 2568 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2569 &mode_cmd, obj)) {
46f297fb
JB		 2570 DRM_DEBUG_KMS("intel fb init failed\n");
2571 goto out_unref_obj;
2572 }
46f297fb 2573 mutex_unlock(&dev->struct_mutex);
484b41dd 2574
f6936e29 2575 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2576 return true;
46f297fb
JB		 2577
2578out_unref_obj:
2579 drm_gem_object_unreference(&obj->base);
2580 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2581 return false;
2582}
2583
afd65eb4
MR		 2584/* Update plane->state->fb to match plane->fb after driver-internal updates */
2585static void
2586update_state_fb(struct drm_plane *plane)
2587{
2588 if (plane->fb == plane->state->fb)
2589 return;
2590
2591 if (plane->state->fb)
2592 drm_framebuffer_unreference(plane->state->fb);
2593 plane->state->fb = plane->fb;
2594 if (plane->state->fb)
2595 drm_framebuffer_reference(plane->state->fb);
2596}
2597
5724dbd1 2598static void
f6936e29
DV		 2599intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2600 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2601{
2602 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2603 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2604 struct drm_crtc *c;
2605 struct intel_crtc *i;
2ff8fde1 2606 struct drm_i915_gem_object *obj;
88595ac9
DV		 2607 struct drm_plane *primary = intel_crtc->base.primary;
2608 struct drm_framebuffer *fb;
484b41dd 2609
2d14030b 2610 if (!plane_config->fb)
484b41dd
JB		 2611 return;
2612
f6936e29 2613 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2614 fb = &plane_config->fb->base;
2615 goto valid_fb;
f55548b5 2616 }
484b41dd 2617
2d14030b 2618 kfree(plane_config->fb);
484b41dd
JB		 2619
2620 /*
2621 * Failed to alloc the obj, check to see if we should share
2622 * an fb with another CRTC instead
2623 */
70e1e0ec 2624 for_each_crtc(dev, c) {
484b41dd
JB		 2625 i = to_intel_crtc(c);
2626
2627 if (c == &intel_crtc->base)
2628 continue;
2629
2ff8fde1
MR		 2630 if (!i->active)
2631 continue;
2632
88595ac9
DV		 2633 fb = c->primary->fb;
2634 if (!fb)
484b41dd
JB		 2635 continue;
2636
88595ac9 2637 obj = intel_fb_obj(fb);
2ff8fde1 2638 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2639 drm_framebuffer_reference(fb);
2640 goto valid_fb;
484b41dd
JB		 2641 }
2642 }
88595ac9
DV		 2643
2644 return;
2645
2646valid_fb:
2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2650
2651 primary->fb = fb;
2652 primary->state->crtc = &intel_crtc->base;
2653 primary->crtc = &intel_crtc->base;
2654 update_state_fb(primary);
2655 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2656}
2657
29b9bde6
DV		 2658static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2660 int x, int y)
81255565
JB		 2661{
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2665 struct drm_i915_gem_object *obj;
81255565 2666 int plane = intel_crtc->plane;
e506a0c6 2667 unsigned long linear_offset;
81255565 2668 u32 dspcntr;
f45651ba 2669 u32 reg = DSPCNTR(plane);
48404c1e 2670 int pixel_size;
f45651ba 2671
fdd508a6
VS		 2672 if (!intel_crtc->primary_enabled) {
2673 I915_WRITE(reg, 0);
2674 if (INTEL_INFO(dev)->gen >= 4)
2675 I915_WRITE(DSPSURF(plane), 0);
2676 else
2677 I915_WRITE(DSPADDR(plane), 0);
2678 POSTING_READ(reg);
2679 return;
2680 }
2681
c9ba6fad
VS		 2682 obj = intel_fb_obj(fb);
2683 if (WARN_ON(obj == NULL))
2684 return;
2685
2686 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2687
f45651ba
VS		 2688 dspcntr = DISPPLANE_GAMMA_ENABLE;
2689
fdd508a6 2690 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2691
2692 if (INTEL_INFO(dev)->gen < 4) {
2693 if (intel_crtc->pipe == PIPE_B)
2694 dspcntr |= DISPPLANE_SEL_PIPE_B;
2695
2696 /* pipesrc and dspsize control the size that is scaled from,
2697 * which should always be the user's requested size.
2698 */
2699 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2700 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2701 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2702 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2703 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2704 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2707 I915_WRITE(PRIMPOS(plane), 0);
2708 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2709 }
81255565 2710
57779d06
VS		 2711 switch (fb->pixel_format) {
2712 case DRM_FORMAT_C8:
81255565
JB		 2713 dspcntr |= DISPPLANE_8BPP;
2714 break;
57779d06
VS		 2715 case DRM_FORMAT_XRGB1555:
2716 case DRM_FORMAT_ARGB1555:
2717 dspcntr |= DISPPLANE_BGRX555;
81255565 2718 break;
57779d06
VS		 2719 case DRM_FORMAT_RGB565:
2720 dspcntr |= DISPPLANE_BGRX565;
2721 break;
2722 case DRM_FORMAT_XRGB8888:
2723 case DRM_FORMAT_ARGB8888:
2724 dspcntr |= DISPPLANE_BGRX888;
2725 break;
2726 case DRM_FORMAT_XBGR8888:
2727 case DRM_FORMAT_ABGR8888:
2728 dspcntr |= DISPPLANE_RGBX888;
2729 break;
2730 case DRM_FORMAT_XRGB2101010:
2731 case DRM_FORMAT_ARGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 case DRM_FORMAT_ABGR2101010:
2736 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2737 break;
2738 default:
baba133a 2739 BUG();
81255565 2740 }
57779d06 2741
f45651ba
VS		 2742 if (INTEL_INFO(dev)->gen >= 4 &&
2743 obj->tiling_mode != I915_TILING_NONE)
2744 dspcntr |= DISPPLANE_TILED;
81255565 2745
de1aa629
VS		 2746 if (IS_G4X(dev))
2747 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2748
b9897127 2749 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2750
c2c75131
DV		 2751 if (INTEL_INFO(dev)->gen >= 4) {
2752 intel_crtc->dspaddr_offset =
bc752862 2753 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2754 pixel_size,
bc752862 2755 fb->pitches[0]);
c2c75131
DV		 2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
e506a0c6 2758 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2759 }
e506a0c6 2760
8e7d688b 2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
6e3c9717
ACO		 2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
6e3c9717
ACO		 2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2772 }
2773
2774 I915_WRITE(reg, dspcntr);
2775
01f2c773 2776 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2777 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2778 I915_WRITE(DSPSURF(plane),
2779 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2780 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2781 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2782 } else
f343c5f6 2783 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2784 POSTING_READ(reg);
17638cd6
JB		 2785}
2786
29b9bde6
DV		 2787static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2788 struct drm_framebuffer *fb,
2789 int x, int y)
17638cd6
JB		 2790{
2791 struct drm_device *dev = crtc->dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2794 struct drm_i915_gem_object *obj;
17638cd6 2795 int plane = intel_crtc->plane;
e506a0c6 2796 unsigned long linear_offset;
17638cd6 2797 u32 dspcntr;
f45651ba 2798 u32 reg = DSPCNTR(plane);
48404c1e 2799 int pixel_size;
f45651ba 2800
fdd508a6
VS		 2801 if (!intel_crtc->primary_enabled) {
2802 I915_WRITE(reg, 0);
2803 I915_WRITE(DSPSURF(plane), 0);
2804 POSTING_READ(reg);
2805 return;
2806 }
2807
c9ba6fad
VS		 2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2810 return;
2811
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
f45651ba
VS		 2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
fdd508a6 2816 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2817
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2820
57779d06
VS		 2821 switch (fb->pixel_format) {
2822 case DRM_FORMAT_C8:
17638cd6
JB		 2823 dspcntr |= DISPPLANE_8BPP;
2824 break;
57779d06
VS		 2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2827 break;
57779d06
VS		 2828 case DRM_FORMAT_XRGB8888:
2829 case DRM_FORMAT_ARGB8888:
2830 dspcntr |= DISPPLANE_BGRX888;
2831 break;
2832 case DRM_FORMAT_XBGR8888:
2833 case DRM_FORMAT_ABGR8888:
2834 dspcntr |= DISPPLANE_RGBX888;
2835 break;
2836 case DRM_FORMAT_XRGB2101010:
2837 case DRM_FORMAT_ARGB2101010:
2838 dspcntr |= DISPPLANE_BGRX101010;
2839 break;
2840 case DRM_FORMAT_XBGR2101010:
2841 case DRM_FORMAT_ABGR2101010:
2842 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2843 break;
2844 default:
baba133a 2845 BUG();
17638cd6
JB		 2846 }
2847
2848 if (obj->tiling_mode != I915_TILING_NONE)
2849 dspcntr |= DISPPLANE_TILED;
17638cd6 2850
f45651ba 2851 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2852 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2853
b9897127 2854 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2855 intel_crtc->dspaddr_offset =
bc752862 2856 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2857 pixel_size,
bc752862 2858 fb->pitches[0]);
c2c75131 2859 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2860 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2861 dspcntr |= DISPPLANE_ROTATE_180;
2862
2863 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2864 x += (intel_crtc->config->pipe_src_w - 1);
2865 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2866
2867 /* Finding the last pixel of the last line of the display
2868 data and adding to linear_offset*/
2869 linear_offset +=
6e3c9717
ACO		 2870 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2871 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2872 }
2873 }
2874
2875 I915_WRITE(reg, dspcntr);
17638cd6 2876
01f2c773 2877 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2878 I915_WRITE(DSPSURF(plane),
2879 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2880 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2881 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2882 } else {
2883 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2884 I915_WRITE(DSPLINOFF(plane), linear_offset);
2885 }
17638cd6 2886 POSTING_READ(reg);
17638cd6
JB		 2887}
2888
b321803d
DL		 2889u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2890 uint32_t pixel_format)
2891{
2892 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2893
2894 /*
2895 * The stride is either expressed as a multiple of 64 bytes
2896 * chunks for linear buffers or in number of tiles for tiled
2897 * buffers.
2898 */
2899 switch (fb_modifier) {
2900 case DRM_FORMAT_MOD_NONE:
2901 return 64;
2902 case I915_FORMAT_MOD_X_TILED:
2903 if (INTEL_INFO(dev)->gen == 2)
2904 return 128;
2905 return 512;
2906 case I915_FORMAT_MOD_Y_TILED:
2907 /* No need to check for old gens and Y tiling since this is
2908 * about the display engine and those will be blocked before
2909 * we get here.
2910 */
2911 return 128;
2912 case I915_FORMAT_MOD_Yf_TILED:
2913 if (bits_per_pixel == 8)
2914 return 64;
2915 else
2916 return 128;
2917 default:
2918 MISSING_CASE(fb_modifier);
2919 return 64;
2920 }
2921}
2922
121920fa
TU		 2923unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2924 struct drm_i915_gem_object *obj)
2925{
9abc4648 2926 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2927
2928 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2929 view = &i915_ggtt_view_rotated;
121920fa
TU		 2930
2931 return i915_gem_obj_ggtt_offset_view(obj, view);
2932}
2933
a1b2278e
CK		 2934/*
2935 * This function detaches (aka. unbinds) unused scalers in hardware
2936 */
2937void skl_detach_scalers(struct intel_crtc *intel_crtc)
2938{
2939 struct drm_device *dev;
2940 struct drm_i915_private *dev_priv;
2941 struct intel_crtc_scaler_state *scaler_state;
2942 int i;
2943
2944 if (!intel_crtc || !intel_crtc->config)
2945 return;
2946
2947 dev = intel_crtc->base.dev;
2948 dev_priv = dev->dev_private;
2949 scaler_state = &intel_crtc->config->scaler_state;
2950
2951 /* loop through and disable scalers that aren't in use */
2952 for (i = 0; i < intel_crtc->num_scalers; i++) {
2953 if (!scaler_state->scalers[i].in_use) {
2954 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2955 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2956 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2957 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2958 intel_crtc->base.base.id, intel_crtc->pipe, i);
2959 }
2960 }
2961}
2962
70d21f0e
DL		 2963static void skylake_update_primary_plane(struct drm_crtc *crtc,
2964 struct drm_framebuffer *fb,
2965 int x, int y)
2966{
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2970 struct drm_i915_gem_object *obj;
2971 int pipe = intel_crtc->pipe;
3b7a5119
SJ		 2972 u32 plane_ctl, stride_div, stride;
2973 u32 tile_height, plane_offset, plane_size;
2974 unsigned int rotation;
2975 int x_offset, y_offset;
121920fa 2976 unsigned long surf_addr;
3b7a5119 2977 struct drm_plane *plane;
70d21f0e
DL		 2978
2979 if (!intel_crtc->primary_enabled) {
2980 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2981 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2982 POSTING_READ(PLANE_CTL(pipe, 0));
2983 return;
2984 }
2985
2986 plane_ctl = PLANE_CTL_ENABLE |
2987 PLANE_CTL_PIPE_GAMMA_ENABLE |
2988 PLANE_CTL_PIPE_CSC_ENABLE;
2989
2990 switch (fb->pixel_format) {
2991 case DRM_FORMAT_RGB565:
2992 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2993 break;
2994 case DRM_FORMAT_XRGB8888:
2995 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2996 break;
f75fb42a
JN		 2997 case DRM_FORMAT_ARGB8888:
2998 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2999 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3000 break;
70d21f0e
DL		 3001 case DRM_FORMAT_XBGR8888:
3002 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3003 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3004 break;
f75fb42a
JN		 3005 case DRM_FORMAT_ABGR8888:
3006 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3007 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3008 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3009 break;
70d21f0e
DL		 3010 case DRM_FORMAT_XRGB2101010:
3011 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3012 break;
3013 case DRM_FORMAT_XBGR2101010:
3014 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3015 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3016 break;
3017 default:
3018 BUG();
3019 }
3020
30af77c4
DV		 3021 switch (fb->modifier[0]) {
3022 case DRM_FORMAT_MOD_NONE:
70d21f0e 3023 break;
30af77c4 3024 case I915_FORMAT_MOD_X_TILED:
70d21f0e 3025 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 3026 break;
3027 case I915_FORMAT_MOD_Y_TILED:
3028 plane_ctl |= PLANE_CTL_TILED_Y;
3029 break;
3030 case I915_FORMAT_MOD_Yf_TILED:
3031 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3032 break;
3033 default:
b321803d 3034 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3035 }
3036
3037 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3b7a5119
SJ		 3038
3039 plane = crtc->primary;
3040 rotation = plane->state->rotation;
3041 switch (rotation) {
3042 case BIT(DRM_ROTATE_90):
3043 plane_ctl |= PLANE_CTL_ROTATE_90;
3044 break;
3045
3046 case BIT(DRM_ROTATE_180):
1447dde0 3047 plane_ctl |= PLANE_CTL_ROTATE_180;
3b7a5119
SJ		 3048 break;
3049
3050 case BIT(DRM_ROTATE_270):
3051 plane_ctl |= PLANE_CTL_ROTATE_270;
3052 break;
3053 }
70d21f0e 3054
b321803d
DL		 3055 obj = intel_fb_obj(fb);
3056 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3057 fb->pixel_format);
3b7a5119
SJ		 3058 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3059
3060 if (intel_rotation_90_or_270(rotation)) {
3061 /* stride = Surface height in tiles */
3062 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3063 fb->modifier[0]);
3064 stride = DIV_ROUND_UP(fb->height, tile_height);
3065 x_offset = stride * tile_height - y - (plane->state->src_h >> 16);
3066 y_offset = x;
3067 plane_size = ((plane->state->src_w >> 16) - 1) << 16 |
3068 ((plane->state->src_h >> 16) - 1);
3069 } else {
3070 stride = fb->pitches[0] / stride_div;
3071 x_offset = x;
3072 y_offset = y;
3073 plane_size = ((plane->state->src_h >> 16) - 1) << 16 |
3074 ((plane->state->src_w >> 16) - 1);
3075 }
3076 plane_offset = y_offset << 16 | x_offset;
b321803d 3077
70d21f0e 3078 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e 3079 I915_WRITE(PLANE_POS(pipe, 0), 0);
3b7a5119
SJ		 3080 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3081 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3082 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
121920fa 3083 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3084
3085 POSTING_READ(PLANE_SURF(pipe, 0));
3086}
3087
17638cd6
JB		 3088/* Assume fb object is pinned & idle & fenced and just update base pointers */
3089static int
3090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3091 int x, int y, enum mode_set_atomic state)
3092{
3093 struct drm_device *dev = crtc->dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3095
6b8e6ed0
CW		 3096 if (dev_priv->display.disable_fbc)
3097 dev_priv->display.disable_fbc(dev);
81255565 3098
29b9bde6
DV		 3099 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3100
3101 return 0;
81255565
JB		 3102}
3103
7514747d 3104static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3105{
96a02917
VS		 3106 struct drm_crtc *crtc;
3107
70e1e0ec 3108 for_each_crtc(dev, crtc) {
96a02917
VS		 3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3110 enum plane plane = intel_crtc->plane;
3111
3112 intel_prepare_page_flip(dev, plane);
3113 intel_finish_page_flip_plane(dev, plane);
3114 }
7514747d
VS		 3115}
3116
3117static void intel_update_primary_planes(struct drm_device *dev)
3118{
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120 struct drm_crtc *crtc;
96a02917 3121
70e1e0ec 3122 for_each_crtc(dev, crtc) {
96a02917
VS		 3123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3124
51fd371b 3125 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3126 /*
3127 * FIXME: Once we have proper support for primary planes (and
3128 * disabling them without disabling the entire crtc) allow again
66e514c1 3129 * a NULL crtc->primary->fb.
947fdaad 3130 */
f4510a27 3131 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3132 dev_priv->display.update_primary_plane(crtc,
66e514c1 3133 crtc->primary->fb,
262ca2b0
MR		 3134 crtc->x,
3135 crtc->y);
51fd371b 3136 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3137 }
3138}
3139
7514747d
VS		 3140void intel_prepare_reset(struct drm_device *dev)
3141{
f98ce92f
VS		 3142 struct drm_i915_private *dev_priv = to_i915(dev);
3143 struct intel_crtc *crtc;
3144
7514747d
VS		 3145 /* no reset support for gen2 */
3146 if (IS_GEN2(dev))
3147 return;
3148
3149 /* reset doesn't touch the display */
3150 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3151 return;
3152
3153 drm_modeset_lock_all(dev);
f98ce92f
VS		 3154
3155 /*
3156 * Disabling the crtcs gracefully seems nicer. Also the
3157 * g33 docs say we should at least disable all the planes.
3158 */
3159 for_each_intel_crtc(dev, crtc) {
3160 if (crtc->active)
3161 dev_priv->display.crtc_disable(&crtc->base);
3162 }
7514747d
VS		 3163}
3164
3165void intel_finish_reset(struct drm_device *dev)
3166{
3167 struct drm_i915_private *dev_priv = to_i915(dev);
3168
3169 /*
3170 * Flips in the rings will be nuked by the reset,
3171 * so complete all pending flips so that user space
3172 * will get its events and not get stuck.
3173 */
3174 intel_complete_page_flips(dev);
3175
3176 /* no reset support for gen2 */
3177 if (IS_GEN2(dev))
3178 return;
3179
3180 /* reset doesn't touch the display */
3181 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3182 /*
3183 * Flips in the rings have been nuked by the reset,
3184 * so update the base address of all primary
3185 * planes to the the last fb to make sure we're
3186 * showing the correct fb after a reset.
3187 */
3188 intel_update_primary_planes(dev);
3189 return;
3190 }
3191
3192 /*
3193 * The display has been reset as well,
3194 * so need a full re-initialization.
3195 */
3196 intel_runtime_pm_disable_interrupts(dev_priv);
3197 intel_runtime_pm_enable_interrupts(dev_priv);
3198
3199 intel_modeset_init_hw(dev);
3200
3201 spin_lock_irq(&dev_priv->irq_lock);
3202 if (dev_priv->display.hpd_irq_setup)
3203 dev_priv->display.hpd_irq_setup(dev);
3204 spin_unlock_irq(&dev_priv->irq_lock);
3205
3206 intel_modeset_setup_hw_state(dev, true);
3207
3208 intel_hpd_init(dev_priv);
3209
3210 drm_modeset_unlock_all(dev);
3211}
3212
14667a4b
CW		 3213static int
3214intel_finish_fb(struct drm_framebuffer *old_fb)
3215{
2ff8fde1 3216 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3217 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3218 bool was_interruptible = dev_priv->mm.interruptible;
3219 int ret;
3220
14667a4b
CW		 3221 /* Big Hammer, we also need to ensure that any pending
3222 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3223 * current scanout is retired before unpinning the old
3224 * framebuffer.
3225 *
3226 * This should only fail upon a hung GPU, in which case we
3227 * can safely continue.
3228 */
3229 dev_priv->mm.interruptible = false;
3230 ret = i915_gem_object_finish_gpu(obj);
3231 dev_priv->mm.interruptible = was_interruptible;
3232
3233 return ret;
3234}
3235
7d5e3799
CW		 3236static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3241 bool pending;
3242
3243 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3244 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3245 return false;
3246
5e2d7afc 3247 spin_lock_irq(&dev->event_lock);
7d5e3799 3248 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3249 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3250
3251 return pending;
3252}
3253
e30e8f75
GP		 3254static void intel_update_pipe_size(struct intel_crtc *crtc)
3255{
3256 struct drm_device *dev = crtc->base.dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 const struct drm_display_mode *adjusted_mode;
3259
3260 if (!i915.fastboot)
3261 return;
3262
3263 /*
3264 * Update pipe size and adjust fitter if needed: the reason for this is
3265 * that in compute_mode_changes we check the native mode (not the pfit
3266 * mode) to see if we can flip rather than do a full mode set. In the
3267 * fastboot case, we'll flip, but if we don't update the pipesrc and
3268 * pfit state, we'll end up with a big fb scanned out into the wrong
3269 * sized surface.
3270 *
3271 * To fix this properly, we need to hoist the checks up into
3272 * compute_mode_changes (or above), check the actual pfit state and
3273 * whether the platform allows pfit disable with pipe active, and only
3274 * then update the pipesrc and pfit state, even on the flip path.
3275 */
3276
6e3c9717 3277 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3278
3279 I915_WRITE(PIPESRC(crtc->pipe),
3280 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3281 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3282 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3283 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3284 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3285 I915_WRITE(PF_CTL(crtc->pipe), 0);
3286 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3287 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3288 }
6e3c9717
ACO		 3289 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3290 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3291}
3292
5e84e1a4
ZW		 3293static void intel_fdi_normal_train(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298 int pipe = intel_crtc->pipe;
3299 u32 reg, temp;
3300
3301 /* enable normal train */
3302 reg = FDI_TX_CTL(pipe);
3303 temp = I915_READ(reg);
61e499bf 3304 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3307 } else {
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3310 }
5e84e1a4
ZW		 3311 I915_WRITE(reg, temp);
3312
3313 reg = FDI_RX_CTL(pipe);
3314 temp = I915_READ(reg);
3315 if (HAS_PCH_CPT(dev)) {
3316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3318 } else {
3319 temp &= ~FDI_LINK_TRAIN_NONE;
3320 temp |= FDI_LINK_TRAIN_NONE;
3321 }
3322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3323
3324 /* wait one idle pattern time */
3325 POSTING_READ(reg);
3326 udelay(1000);
357555c0
JB		 3327
3328 /* IVB wants error correction enabled */
3329 if (IS_IVYBRIDGE(dev))
3330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3331 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3332}
3333
8db9d77b
ZW		 3334/* The FDI link training functions for ILK/Ibexpeak. */
3335static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3336{
3337 struct drm_device *dev = crtc->dev;
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int pipe = intel_crtc->pipe;
5eddb70b 3341 u32 reg, temp, tries;
8db9d77b 3342
1c8562f6 3343 /* FDI needs bits from pipe first */
0fc932b8 3344 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3345
e1a44743
AJ		 3346 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3347 for train result */
5eddb70b
CW		 3348 reg = FDI_RX_IMR(pipe);
3349 temp = I915_READ(reg);
e1a44743
AJ		 3350 temp &= ~FDI_RX_SYMBOL_LOCK;
3351 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3352 I915_WRITE(reg, temp);
3353 I915_READ(reg);
e1a44743
AJ		 3354 udelay(150);
3355
8db9d77b 3356 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3357 reg = FDI_TX_CTL(pipe);
3358 temp = I915_READ(reg);
627eb5a3 3359 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3360 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3363 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3364
5eddb70b
CW		 3365 reg = FDI_RX_CTL(pipe);
3366 temp = I915_READ(reg);
8db9d77b
ZW		 3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3369 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3370
3371 POSTING_READ(reg);
8db9d77b
ZW		 3372 udelay(150);
3373
5b2adf89 3374 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3375 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3376 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3377 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3378
5eddb70b 3379 reg = FDI_RX_IIR(pipe);
e1a44743 3380 for (tries = 0; tries < 5; tries++) {
5eddb70b 3381 temp = I915_READ(reg);
8db9d77b
ZW		 3382 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3383
3384 if ((temp & FDI_RX_BIT_LOCK)) {
3385 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3386 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3387 break;
3388 }
8db9d77b 3389 }
e1a44743 3390 if (tries == 5)
5eddb70b 3391 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3392
3393 /* Train 2 */
5eddb70b
CW		 3394 reg = FDI_TX_CTL(pipe);
3395 temp = I915_READ(reg);
8db9d77b
ZW		 3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3398 I915_WRITE(reg, temp);
8db9d77b 3399
5eddb70b
CW		 3400 reg = FDI_RX_CTL(pipe);
3401 temp = I915_READ(reg);
8db9d77b
ZW		 3402 temp &= ~FDI_LINK_TRAIN_NONE;
3403 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3404 I915_WRITE(reg, temp);
8db9d77b 3405
5eddb70b
CW		 3406 POSTING_READ(reg);
3407 udelay(150);
8db9d77b 3408
5eddb70b 3409 reg = FDI_RX_IIR(pipe);
e1a44743 3410 for (tries = 0; tries < 5; tries++) {
5eddb70b 3411 temp = I915_READ(reg);
8db9d77b
ZW		 3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413
3414 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3415 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3416 DRM_DEBUG_KMS("FDI train 2 done.\n");
3417 break;
3418 }
8db9d77b 3419 }
e1a44743 3420 if (tries == 5)
5eddb70b 3421 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3422
3423 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3424
8db9d77b
ZW		 3425}
3426
0206e353 3427static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3428 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3429 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3430 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3431 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3432};
3433
3434/* The FDI link training functions for SNB/Cougarpoint. */
3435static void gen6_fdi_link_train(struct drm_crtc *crtc)
3436{
3437 struct drm_device *dev = crtc->dev;
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3440 int pipe = intel_crtc->pipe;
fa37d39e 3441 u32 reg, temp, i, retry;
8db9d77b 3442
e1a44743
AJ		 3443 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3444 for train result */
5eddb70b
CW		 3445 reg = FDI_RX_IMR(pipe);
3446 temp = I915_READ(reg);
e1a44743
AJ		 3447 temp &= ~FDI_RX_SYMBOL_LOCK;
3448 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3449 I915_WRITE(reg, temp);
3450
3451 POSTING_READ(reg);
e1a44743
AJ		 3452 udelay(150);
3453
8db9d77b 3454 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
627eb5a3 3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_1;
3461 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3462 /* SNB-B */
3463 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3464 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3465
d74cf324
DV		 3466 I915_WRITE(FDI_RX_MISC(pipe),
3467 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3468
5eddb70b
CW		 3469 reg = FDI_RX_CTL(pipe);
3470 temp = I915_READ(reg);
8db9d77b
ZW		 3471 if (HAS_PCH_CPT(dev)) {
3472 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3473 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3474 } else {
3475 temp &= ~FDI_LINK_TRAIN_NONE;
3476 temp |= FDI_LINK_TRAIN_PATTERN_1;
3477 }
5eddb70b
CW		 3478 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3479
3480 POSTING_READ(reg);
8db9d77b
ZW		 3481 udelay(150);
3482
0206e353 3483 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3484 reg = FDI_TX_CTL(pipe);
3485 temp = I915_READ(reg);
8db9d77b
ZW		 3486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3488 I915_WRITE(reg, temp);
3489
3490 POSTING_READ(reg);
8db9d77b
ZW		 3491 udelay(500);
3492
fa37d39e
SP		 3493 for (retry = 0; retry < 5; retry++) {
3494 reg = FDI_RX_IIR(pipe);
3495 temp = I915_READ(reg);
3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497 if (temp & FDI_RX_BIT_LOCK) {
3498 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3499 DRM_DEBUG_KMS("FDI train 1 done.\n");
3500 break;
3501 }
3502 udelay(50);
8db9d77b 3503 }
fa37d39e
SP		 3504 if (retry < 5)
3505 break;
8db9d77b
ZW		 3506 }
3507 if (i == 4)
5eddb70b 3508 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3509
3510 /* Train 2 */
5eddb70b
CW		 3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
8db9d77b
ZW		 3513 temp &= ~FDI_LINK_TRAIN_NONE;
3514 temp |= FDI_LINK_TRAIN_PATTERN_2;
3515 if (IS_GEN6(dev)) {
3516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3517 /* SNB-B */
3518 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3519 }
5eddb70b 3520 I915_WRITE(reg, temp);
8db9d77b 3521
5eddb70b
CW		 3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
8db9d77b
ZW		 3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3527 } else {
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_2;
3530 }
5eddb70b
CW		 3531 I915_WRITE(reg, temp);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(150);
3535
0206e353 3536 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
8db9d77b
ZW		 3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3541 I915_WRITE(reg, temp);
3542
3543 POSTING_READ(reg);
8db9d77b
ZW		 3544 udelay(500);
3545
fa37d39e
SP		 3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_SYMBOL_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3552 DRM_DEBUG_KMS("FDI train 2 done.\n");
3553 break;
3554 }
3555 udelay(50);
8db9d77b 3556 }
fa37d39e
SP		 3557 if (retry < 5)
3558 break;
8db9d77b
ZW		 3559 }
3560 if (i == 4)
5eddb70b 3561 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3562
3563 DRM_DEBUG_KMS("FDI train done.\n");
3564}
3565
357555c0
JB		 3566/* Manual link training for Ivy Bridge A0 parts */
3567static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3568{
3569 struct drm_device *dev = crtc->dev;
3570 struct drm_i915_private *dev_priv = dev->dev_private;
3571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 int pipe = intel_crtc->pipe;
139ccd3f 3573 u32 reg, temp, i, j;
357555c0
JB		 3574
3575 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3576 for train result */
3577 reg = FDI_RX_IMR(pipe);
3578 temp = I915_READ(reg);
3579 temp &= ~FDI_RX_SYMBOL_LOCK;
3580 temp &= ~FDI_RX_BIT_LOCK;
3581 I915_WRITE(reg, temp);
3582
3583 POSTING_READ(reg);
3584 udelay(150);
3585
01a415fd
DV		 3586 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3587 I915_READ(FDI_RX_IIR(pipe)));
3588
139ccd3f
JB		 3589 /* Try each vswing and preemphasis setting twice before moving on */
3590 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3591 /* disable first in case we need to retry */
3592 reg = FDI_TX_CTL(pipe);
3593 temp = I915_READ(reg);
3594 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3595 temp &= ~FDI_TX_ENABLE;
3596 I915_WRITE(reg, temp);
357555c0 3597
139ccd3f
JB		 3598 reg = FDI_RX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_AUTO;
3601 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3602 temp &= ~FDI_RX_ENABLE;
3603 I915_WRITE(reg, temp);
357555c0 3604
139ccd3f 3605 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3606 reg = FDI_TX_CTL(pipe);
3607 temp = I915_READ(reg);
139ccd3f 3608 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3609 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3610 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3612 temp |= snb_b_fdi_train_param[j/2];
3613 temp |= FDI_COMPOSITE_SYNC;
3614 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3615
139ccd3f
JB		 3616 I915_WRITE(FDI_RX_MISC(pipe),
3617 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3618
139ccd3f 3619 reg = FDI_RX_CTL(pipe);
357555c0 3620 temp = I915_READ(reg);
139ccd3f
JB		 3621 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3622 temp |= FDI_COMPOSITE_SYNC;
3623 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3624
139ccd3f
JB		 3625 POSTING_READ(reg);
3626 udelay(1); /* should be 0.5us */
357555c0 3627
139ccd3f
JB		 3628 for (i = 0; i < 4; i++) {
3629 reg = FDI_RX_IIR(pipe);
3630 temp = I915_READ(reg);
3631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3632
139ccd3f
JB		 3633 if (temp & FDI_RX_BIT_LOCK ||
3634 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3635 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3636 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3637 i);
3638 break;
3639 }
3640 udelay(1); /* should be 0.5us */
3641 }
3642 if (i == 4) {
3643 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3644 continue;
3645 }
357555c0 3646
139ccd3f 3647 /* Train 2 */
357555c0
JB		 3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
139ccd3f
JB		 3650 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3651 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3652 I915_WRITE(reg, temp);
3653
3654 reg = FDI_RX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3657 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3658 I915_WRITE(reg, temp);
3659
3660 POSTING_READ(reg);
139ccd3f 3661 udelay(2); /* should be 1.5us */
357555c0 3662
139ccd3f
JB		 3663 for (i = 0; i < 4; i++) {
3664 reg = FDI_RX_IIR(pipe);
3665 temp = I915_READ(reg);
3666 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3667
139ccd3f
JB		 3668 if (temp & FDI_RX_SYMBOL_LOCK ||
3669 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3670 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3671 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3672 i);
3673 goto train_done;
3674 }
3675 udelay(2); /* should be 1.5us */
357555c0 3676 }
139ccd3f
JB		 3677 if (i == 4)
3678 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3679 }
357555c0 3680
139ccd3f 3681train_done:
357555c0
JB		 3682 DRM_DEBUG_KMS("FDI train done.\n");
3683}
3684
88cefb6c 3685static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3686{
88cefb6c 3687 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3688 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3689 int pipe = intel_crtc->pipe;
5eddb70b 3690 u32 reg, temp;
79e53945 3691
c64e311e 3692
c98e9dcf 3693 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3694 reg = FDI_RX_CTL(pipe);
3695 temp = I915_READ(reg);
627eb5a3 3696 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3698 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3699 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3700
3701 POSTING_READ(reg);
c98e9dcf
JB		 3702 udelay(200);
3703
3704 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3705 temp = I915_READ(reg);
3706 I915_WRITE(reg, temp | FDI_PCDCLK);
3707
3708 POSTING_READ(reg);
c98e9dcf
JB		 3709 udelay(200);
3710
20749730
PZ		 3711 /* Enable CPU FDI TX PLL, always on for Ironlake */
3712 reg = FDI_TX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3715 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3716
20749730
PZ		 3717 POSTING_READ(reg);
3718 udelay(100);
6be4a607 3719 }
0e23b99d
JB		 3720}
3721
88cefb6c
DV		 3722static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3723{
3724 struct drm_device *dev = intel_crtc->base.dev;
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 int pipe = intel_crtc->pipe;
3727 u32 reg, temp;
3728
3729 /* Switch from PCDclk to Rawclk */
3730 reg = FDI_RX_CTL(pipe);
3731 temp = I915_READ(reg);
3732 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3733
3734 /* Disable CPU FDI TX PLL */
3735 reg = FDI_TX_CTL(pipe);
3736 temp = I915_READ(reg);
3737 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3738
3739 POSTING_READ(reg);
3740 udelay(100);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3745
3746 /* Wait for the clocks to turn off. */
3747 POSTING_READ(reg);
3748 udelay(100);
3749}
3750
0fc932b8
JB		 3751static void ironlake_fdi_disable(struct drm_crtc *crtc)
3752{
3753 struct drm_device *dev = crtc->dev;
3754 struct drm_i915_private *dev_priv = dev->dev_private;
3755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3756 int pipe = intel_crtc->pipe;
3757 u32 reg, temp;
3758
3759 /* disable CPU FDI tx and PCH FDI rx */
3760 reg = FDI_TX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3763 POSTING_READ(reg);
3764
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(0x7 << 16);
dfd07d72 3768 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3769 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3770
3771 POSTING_READ(reg);
3772 udelay(100);
3773
3774 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3775 if (HAS_PCH_IBX(dev))
6f06ce18 3776 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3777
3778 /* still set train pattern 1 */
3779 reg = FDI_TX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~FDI_LINK_TRAIN_NONE;
3782 temp |= FDI_LINK_TRAIN_PATTERN_1;
3783 I915_WRITE(reg, temp);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 if (HAS_PCH_CPT(dev)) {
3788 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3789 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3790 } else {
3791 temp &= ~FDI_LINK_TRAIN_NONE;
3792 temp |= FDI_LINK_TRAIN_PATTERN_1;
3793 }
3794 /* BPC in FDI rx is consistent with that in PIPECONF */
3795 temp &= ~(0x07 << 16);
dfd07d72 3796 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3797 I915_WRITE(reg, temp);
3798
3799 POSTING_READ(reg);
3800 udelay(100);
3801}
3802
5dce5b93
CW		 3803bool intel_has_pending_fb_unpin(struct drm_device *dev)
3804{
3805 struct intel_crtc *crtc;
3806
3807 /* Note that we don't need to be called with mode_config.lock here
3808 * as our list of CRTC objects is static for the lifetime of the
3809 * device and so cannot disappear as we iterate. Similarly, we can
3810 * happily treat the predicates as racy, atomic checks as userspace
3811 * cannot claim and pin a new fb without at least acquring the
3812 * struct_mutex and so serialising with us.
3813 */
d3fcc808 3814 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3815 if (atomic_read(&crtc->unpin_work_count) == 0)
3816 continue;
3817
3818 if (crtc->unpin_work)
3819 intel_wait_for_vblank(dev, crtc->pipe);
3820
3821 return true;
3822 }
3823
3824 return false;
3825}
3826
d6bbafa1
CW		 3827static void page_flip_completed(struct intel_crtc *intel_crtc)
3828{
3829 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3830 struct intel_unpin_work *work = intel_crtc->unpin_work;
3831
3832 /* ensure that the unpin work is consistent wrt ->pending. */
3833 smp_rmb();
3834 intel_crtc->unpin_work = NULL;
3835
3836 if (work->event)
3837 drm_send_vblank_event(intel_crtc->base.dev,
3838 intel_crtc->pipe,
3839 work->event);
3840
3841 drm_crtc_vblank_put(&intel_crtc->base);
3842
3843 wake_up_all(&dev_priv->pending_flip_queue);
3844 queue_work(dev_priv->wq, &work->work);
3845
3846 trace_i915_flip_complete(intel_crtc->plane,
3847 work->pending_flip_obj);
3848}
3849
46a55d30 3850void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3851{
0f91128d 3852 struct drm_device *dev = crtc->dev;
5bb61643 3853 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3854
2c10d571 3855 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3856 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3857 !intel_crtc_has_pending_flip(crtc),
3858 60*HZ) == 0)) {
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3860
5e2d7afc 3861 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3862 if (intel_crtc->unpin_work) {
3863 WARN_ONCE(1, "Removing stuck page flip\n");
3864 page_flip_completed(intel_crtc);
3865 }
5e2d7afc 3866 spin_unlock_irq(&dev->event_lock);
9c787942 3867 }
5bb61643 3868
975d568a
CW		 3869 if (crtc->primary->fb) {
3870 mutex_lock(&dev->struct_mutex);
3871 intel_finish_fb(crtc->primary->fb);
3872 mutex_unlock(&dev->struct_mutex);
3873 }
e6c3a2a6
CW		 3874}
3875
e615efe4
ED		 3876/* Program iCLKIP clock to the desired frequency */
3877static void lpt_program_iclkip(struct drm_crtc *crtc)
3878{
3879 struct drm_device *dev = crtc->dev;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3881 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3882 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3883 u32 temp;
3884
09153000
DV		 3885 mutex_lock(&dev_priv->dpio_lock);
3886
e615efe4
ED		 3887 /* It is necessary to ungate the pixclk gate prior to programming
3888 * the divisors, and gate it back when it is done.
3889 */
3890 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3891
3892 /* Disable SSCCTL */
3893 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3894 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3895 SBI_SSCCTL_DISABLE,
3896 SBI_ICLK);
e615efe4
ED		 3897
3898 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3899 if (clock == 20000) {
e615efe4
ED		 3900 auxdiv = 1;
3901 divsel = 0x41;
3902 phaseinc = 0x20;
3903 } else {
3904 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3905 * but the adjusted_mode->crtc_clock in in KHz. To get the
3906 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3907 * convert the virtual clock precision to KHz here for higher
3908 * precision.
3909 */
3910 u32 iclk_virtual_root_freq = 172800 * 1000;
3911 u32 iclk_pi_range = 64;
3912 u32 desired_divisor, msb_divisor_value, pi_value;
3913
12d7ceed 3914 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3915 msb_divisor_value = desired_divisor / iclk_pi_range;
3916 pi_value = desired_divisor % iclk_pi_range;
3917
3918 auxdiv = 0;
3919 divsel = msb_divisor_value - 2;
3920 phaseinc = pi_value;
3921 }
3922
3923 /* This should not happen with any sane values */
3924 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3925 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3926 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3927 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3928
3929 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3930 clock,
e615efe4
ED		 3931 auxdiv,
3932 divsel,
3933 phasedir,
3934 phaseinc);
3935
3936 /* Program SSCDIVINTPHASE6 */
988d6ee8 3937 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3938 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3939 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3940 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3941 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3942 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3943 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3944 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3945
3946 /* Program SSCAUXDIV */
988d6ee8 3947 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3948 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3949 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3950 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3951
3952 /* Enable modulator and associated divider */
988d6ee8 3953 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3954 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3955 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3956
3957 /* Wait for initialization time */
3958 udelay(24);
3959
3960 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3961
3962 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3963}
3964
275f01b2
DV		 3965static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3966 enum pipe pch_transcoder)
3967{
3968 struct drm_device *dev = crtc->base.dev;
3969 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3970 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3971
3972 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3973 I915_READ(HTOTAL(cpu_transcoder)));
3974 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3975 I915_READ(HBLANK(cpu_transcoder)));
3976 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3977 I915_READ(HSYNC(cpu_transcoder)));
3978
3979 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3980 I915_READ(VTOTAL(cpu_transcoder)));
3981 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3982 I915_READ(VBLANK(cpu_transcoder)));
3983 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3984 I915_READ(VSYNC(cpu_transcoder)));
3985 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3986 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3987}
3988
003632d9 3989static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3990{
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 uint32_t temp;
3993
3994 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3995 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3996 return;
3997
3998 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3999 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4000
003632d9
ACO		 4001 temp &= ~FDI_BC_BIFURCATION_SELECT;
4002 if (enable)
4003 temp |= FDI_BC_BIFURCATION_SELECT;
4004
4005 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4006 I915_WRITE(SOUTH_CHICKEN1, temp);
4007 POSTING_READ(SOUTH_CHICKEN1);
4008}
4009
4010static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4011{
4012 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4013
4014 switch (intel_crtc->pipe) {
4015 case PIPE_A:
4016 break;
4017 case PIPE_B:
6e3c9717 4018 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4019 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4020 else
003632d9 4021 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4022
4023 break;
4024 case PIPE_C:
003632d9 4025 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4026
4027 break;
4028 default:
4029 BUG();
4030 }
4031}
4032
f67a559d
JB		 4033/*
4034 * Enable PCH resources required for PCH ports:
4035 * - PCH PLLs
4036 * - FDI training & RX/TX
4037 * - update transcoder timings
4038 * - DP transcoding bits
4039 * - transcoder
4040 */
4041static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 int pipe = intel_crtc->pipe;
ee7b9f93 4047 u32 reg, temp;
2c07245f 4048
ab9412ba 4049 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4050
1fbc0d78
DV		 4051 if (IS_IVYBRIDGE(dev))
4052 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4053
cd986abb
DV		 4054 /* Write the TU size bits before fdi link training, so that error
4055 * detection works. */
4056 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4057 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4058
c98e9dcf 4059 /* For PCH output, training FDI link */
674cf967 4060 dev_priv->display.fdi_link_train(crtc);
2c07245f 4061
3ad8a208
DV		 4062 /* We need to program the right clock selection before writing the pixel
4063 * mutliplier into the DPLL. */
303b81e0 4064 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4065 u32 sel;
4b645f14 4066
c98e9dcf 4067 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4068 temp |= TRANS_DPLL_ENABLE(pipe);
4069 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4070 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4071 temp |= sel;
4072 else
4073 temp &= ~sel;
c98e9dcf 4074 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4075 }
5eddb70b 4076
3ad8a208
DV		 4077 /* XXX: pch pll's can be enabled any time before we enable the PCH
4078 * transcoder, and we actually should do this to not upset any PCH
4079 * transcoder that already use the clock when we share it.
4080 *
4081 * Note that enable_shared_dpll tries to do the right thing, but
4082 * get_shared_dpll unconditionally resets the pll - we need that to have
4083 * the right LVDS enable sequence. */
85b3894f 4084 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4085
d9b6cb56
JB		 4086 /* set transcoder timing, panel must allow it */
4087 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4088 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4089
303b81e0 4090 intel_fdi_normal_train(crtc);
5e84e1a4 4091
c98e9dcf 4092 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4093 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4094 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4095 reg = TRANS_DP_CTL(pipe);
4096 temp = I915_READ(reg);
4097 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4098 TRANS_DP_SYNC_MASK |
4099 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4100 temp |= (TRANS_DP_OUTPUT_ENABLE |
4101 TRANS_DP_ENH_FRAMING);
9325c9f0 4102 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4103
4104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4105 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4106 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4107 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4108
4109 switch (intel_trans_dp_port_sel(crtc)) {
4110 case PCH_DP_B:
5eddb70b 4111 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4112 break;
4113 case PCH_DP_C:
5eddb70b 4114 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4115 break;
4116 case PCH_DP_D:
5eddb70b 4117 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4118 break;
4119 default:
e95d41e1 4120 BUG();
32f9d658 4121 }
2c07245f 4122
5eddb70b 4123 I915_WRITE(reg, temp);
6be4a607 4124 }
b52eb4dc 4125
b8a4f404 4126 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4127}
4128
1507e5bd
PZ		 4129static void lpt_pch_enable(struct drm_crtc *crtc)
4130{
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4135
ab9412ba 4136 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4137
8c52b5e8 4138 lpt_program_iclkip(crtc);
1507e5bd 4139
0540e488 4140 /* Set transcoder timing. */
275f01b2 4141 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4142
937bb610 4143 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4144}
4145
716c2e55 4146void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4147{
e2b78267 4148 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4149
4150 if (pll == NULL)
4151 return;
4152
3e369b76 4153 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4154 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4155 return;
4156 }
4157
3e369b76
ACO		 4158 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4159 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4160 WARN_ON(pll->on);
4161 WARN_ON(pll->active);
4162 }
4163
6e3c9717 4164 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4165}
4166
190f68c5
ACO		 4167struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4168 struct intel_crtc_state *crtc_state)
ee7b9f93 4169{
e2b78267 4170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4171 struct intel_shared_dpll *pll;
e2b78267 4172 enum intel_dpll_id i;
ee7b9f93 4173
98b6bd99
DV		 4174 if (HAS_PCH_IBX(dev_priv->dev)) {
4175 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4176 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4177 pll = &dev_priv->shared_dplls[i];
98b6bd99 4178
46edb027
DV		 4179 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4180 crtc->base.base.id, pll->name);
98b6bd99 4181
8bd31e67 4182 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4183
98b6bd99
DV		 4184 goto found;
4185 }
4186
e72f9fbf
DV		 4187 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4188 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4189
4190 /* Only want to check enabled timings first */
8bd31e67 4191 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4192 continue;
4193
190f68c5 4194 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4195 &pll->new_config->hw_state,
4196 sizeof(pll->new_config->hw_state)) == 0) {
4197 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4198 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4199 pll->new_config->crtc_mask,
4200 pll->active);
ee7b9f93
JB		 4201 goto found;
4202 }
4203 }
4204
4205 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4206 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4207 pll = &dev_priv->shared_dplls[i];
8bd31e67 4208 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4209 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4210 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4211 goto found;
4212 }
4213 }
4214
4215 return NULL;
4216
4217found:
8bd31e67 4218 if (pll->new_config->crtc_mask == 0)
190f68c5 4219 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4220
190f68c5 4221 crtc_state->shared_dpll = i;
46edb027
DV		 4222 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4223 pipe_name(crtc->pipe));
ee7b9f93 4224
8bd31e67 4225 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4226
ee7b9f93
JB		 4227 return pll;
4228}
4229
8bd31e67
ACO		 4230/**
4231 * intel_shared_dpll_start_config - start a new PLL staged config
4232 * @dev_priv: DRM device
4233 * @clear_pipes: mask of pipes that will have their PLLs freed
4234 *
4235 * Starts a new PLL staged config, copying the current config but
4236 * releasing the references of pipes specified in clear_pipes.
4237 */
4238static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4239 unsigned clear_pipes)
4240{
4241 struct intel_shared_dpll *pll;
4242 enum intel_dpll_id i;
4243
4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
4246
4247 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4248 GFP_KERNEL);
4249 if (!pll->new_config)
4250 goto cleanup;
4251
4252 pll->new_config->crtc_mask &= ~clear_pipes;
4253 }
4254
4255 return 0;
4256
4257cleanup:
4258 while (--i >= 0) {
4259 pll = &dev_priv->shared_dplls[i];
f354d733 4260 kfree(pll->new_config);
8bd31e67
ACO		 4261 pll->new_config = NULL;
4262 }
4263
4264 return -ENOMEM;
4265}
4266
4267static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4268{
4269 struct intel_shared_dpll *pll;
4270 enum intel_dpll_id i;
4271
4272 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4273 pll = &dev_priv->shared_dplls[i];
4274
4275 WARN_ON(pll->new_config == &pll->config);
4276
4277 pll->config = *pll->new_config;
4278 kfree(pll->new_config);
4279 pll->new_config = NULL;
4280 }
4281}
4282
4283static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4284{
4285 struct intel_shared_dpll *pll;
4286 enum intel_dpll_id i;
4287
4288 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4289 pll = &dev_priv->shared_dplls[i];
4290
4291 WARN_ON(pll->new_config == &pll->config);
4292
4293 kfree(pll->new_config);
4294 pll->new_config = NULL;
4295 }
4296}
4297
a1520318 4298static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4299{
4300 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4301 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4302 u32 temp;
4303
4304 temp = I915_READ(dslreg);
4305 udelay(500);
4306 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4307 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4308 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4309 }
4310}
4311
a1b2278e
CK		 4312/**
4313 * skl_update_scaler_users - Stages update to crtc's scaler state
4314 * @intel_crtc: crtc
4315 * @crtc_state: crtc_state
4316 * @plane: plane (NULL indicates crtc is requesting update)
4317 * @plane_state: plane's state
4318 * @force_detach: request unconditional detachment of scaler
4319 *
4320 * This function updates scaler state for requested plane or crtc.
4321 * To request scaler usage update for a plane, caller shall pass plane pointer.
4322 * To request scaler usage update for crtc, caller shall pass plane pointer
4323 * as NULL.
4324 *
4325 * Return
4326 * 0 - scaler_usage updated successfully
4327 * error - requested scaling cannot be supported or other error condition
4328 */
4329int
4330skl_update_scaler_users(
4331 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4332 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4333 int force_detach)
4334{
4335 int need_scaling;
4336 int idx;
4337 int src_w, src_h, dst_w, dst_h;
4338 int *scaler_id;
4339 struct drm_framebuffer *fb;
4340 struct intel_crtc_scaler_state *scaler_state;
4341
4342 if (!intel_crtc || !crtc_state)
4343 return 0;
4344
4345 scaler_state = &crtc_state->scaler_state;
4346
4347 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4348 fb = intel_plane ? plane_state->base.fb : NULL;
4349
4350 if (intel_plane) {
4351 src_w = drm_rect_width(&plane_state->src) >> 16;
4352 src_h = drm_rect_height(&plane_state->src) >> 16;
4353 dst_w = drm_rect_width(&plane_state->dst);
4354 dst_h = drm_rect_height(&plane_state->dst);
4355 scaler_id = &plane_state->scaler_id;
4356 } else {
4357 struct drm_display_mode *adjusted_mode =
4358 &crtc_state->base.adjusted_mode;
4359 src_w = crtc_state->pipe_src_w;
4360 src_h = crtc_state->pipe_src_h;
4361 dst_w = adjusted_mode->hdisplay;
4362 dst_h = adjusted_mode->vdisplay;
4363 scaler_id = &scaler_state->scaler_id;
4364 }
4365 need_scaling = (src_w != dst_w || src_h != dst_h);
4366
4367 /*
4368 * if plane is being disabled or scaler is no more required or force detach
4369 * - free scaler binded to this plane/crtc
4370 * - in order to do this, update crtc->scaler_usage
4371 *
4372 * Here scaler state in crtc_state is set free so that
4373 * scaler can be assigned to other user. Actual register
4374 * update to free the scaler is done in plane/panel-fit programming.
4375 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4376 */
4377 if (force_detach || !need_scaling || (intel_plane &&
4378 (!fb || !plane_state->visible))) {
4379 if (*scaler_id >= 0) {
4380 scaler_state->scaler_users &= ~(1 << idx);
4381 scaler_state->scalers[*scaler_id].in_use = 0;
4382
4383 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4384 "crtc_state = %p scaler_users = 0x%x\n",
4385 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4386 intel_plane ? intel_plane->base.base.id :
4387 intel_crtc->base.base.id, crtc_state,
4388 scaler_state->scaler_users);
4389 *scaler_id = -1;
4390 }
4391 return 0;
4392 }
4393
4394 /* range checks */
4395 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4396 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4397
4398 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4399 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4400 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4401 "size is out of scaler range\n",
4402 intel_plane ? "PLANE" : "CRTC",
4403 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4404 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4405 return -EINVAL;
4406 }
4407
4408 /* check colorkey */
4409 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4410 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4411 intel_plane->base.base.id);
4412 return -EINVAL;
4413 }
4414
4415 /* Check src format */
4416 if (intel_plane) {
4417 switch (fb->pixel_format) {
4418 case DRM_FORMAT_RGB565:
4419 case DRM_FORMAT_XBGR8888:
4420 case DRM_FORMAT_XRGB8888:
4421 case DRM_FORMAT_ABGR8888:
4422 case DRM_FORMAT_ARGB8888:
4423 case DRM_FORMAT_XRGB2101010:
4424 case DRM_FORMAT_ARGB2101010:
4425 case DRM_FORMAT_XBGR2101010:
4426 case DRM_FORMAT_ABGR2101010:
4427 case DRM_FORMAT_YUYV:
4428 case DRM_FORMAT_YVYU:
4429 case DRM_FORMAT_UYVY:
4430 case DRM_FORMAT_VYUY:
4431 break;
4432 default:
4433 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4434 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4435 return -EINVAL;
4436 }
4437 }
4438
4439 /* mark this plane as a scaler user in crtc_state */
4440 scaler_state->scaler_users |= (1 << idx);
4441 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4442 "crtc_state = %p scaler_users = 0x%x\n",
4443 intel_plane ? "PLANE" : "CRTC",
4444 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4445 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4446 return 0;
4447}
4448
4449static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4450{
4451 struct drm_device *dev = crtc->base.dev;
4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 int pipe = crtc->pipe;
a1b2278e
CK		 4454 struct intel_crtc_scaler_state *scaler_state =
4455 &crtc->config->scaler_state;
4456
4457 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4458
4459 /* To update pfit, first update scaler state */
4460 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4461 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4462 skl_detach_scalers(crtc);
4463 if (!enable)
4464 return;
bd2e244f 4465
6e3c9717 4466 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4467 int id;
4468
4469 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4470 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4471 return;
4472 }
4473
4474 id = scaler_state->scaler_id;
4475 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4476 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4477 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4478 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4479
4480 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4481 }
4482}
4483
b074cec8
JB		 4484static void ironlake_pfit_enable(struct intel_crtc *crtc)
4485{
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488 int pipe = crtc->pipe;
4489
6e3c9717 4490 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4491 /* Force use of hard-coded filter coefficients
4492 * as some pre-programmed values are broken,
4493 * e.g. x201.
4494 */
4495 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4496 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4497 PF_PIPE_SEL_IVB(pipe));
4498 else
4499 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4500 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4501 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4502 }
4503}
4504
4a3b8769 4505static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4506{
4507 struct drm_device *dev = crtc->dev;
4508 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4509 struct drm_plane *plane;
bb53d4ae
VS		 4510 struct intel_plane *intel_plane;
4511
af2b653b
MR		 4512 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4513 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4514 if (intel_plane->pipe == pipe)
4515 intel_plane_restore(&intel_plane->base);
af2b653b 4516 }
bb53d4ae
VS		 4517}
4518
0d703d4e
MR		 4519/*
4520 * Disable a plane internally without actually modifying the plane's state.
4521 * This will allow us to easily restore the plane later by just reprogramming
4522 * its state.
4523 */
4524static void disable_plane_internal(struct drm_plane *plane)
4525{
4526 struct intel_plane *intel_plane = to_intel_plane(plane);
4527 struct drm_plane_state *state =
4528 plane->funcs->atomic_duplicate_state(plane);
4529 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4530
4531 intel_state->visible = false;
4532 intel_plane->commit_plane(plane, intel_state);
4533
4534 intel_plane_destroy_state(plane, state);
4535}
4536
4a3b8769 4537static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4538{
4539 struct drm_device *dev = crtc->dev;
4540 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4541 struct drm_plane *plane;
bb53d4ae
VS		 4542 struct intel_plane *intel_plane;
4543
af2b653b
MR		 4544 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4545 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4546 if (plane->fb && intel_plane->pipe == pipe)
4547 disable_plane_internal(plane);
af2b653b 4548 }
bb53d4ae
VS		 4549}
4550
20bc8673 4551void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4552{
cea165c3
VS		 4553 struct drm_device *dev = crtc->base.dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4555
6e3c9717 4556 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4557 return;
4558
cea165c3
VS		 4559 /* We can only enable IPS after we enable a plane and wait for a vblank */
4560 intel_wait_for_vblank(dev, crtc->pipe);
4561
d77e4531 4562 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4563 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4564 mutex_lock(&dev_priv->rps.hw_lock);
4565 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4566 mutex_unlock(&dev_priv->rps.hw_lock);
4567 /* Quoting Art Runyan: "its not safe to expect any particular
4568 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4569 * mailbox." Moreover, the mailbox may return a bogus state,
4570 * so we need to just enable it and continue on.
2a114cc1
BW		 4571 */
4572 } else {
4573 I915_WRITE(IPS_CTL, IPS_ENABLE);
4574 /* The bit only becomes 1 in the next vblank, so this wait here
4575 * is essentially intel_wait_for_vblank. If we don't have this
4576 * and don't wait for vblanks until the end of crtc_enable, then
4577 * the HW state readout code will complain that the expected
4578 * IPS_CTL value is not the one we read. */
4579 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4580 DRM_ERROR("Timed out waiting for IPS enable\n");
4581 }
d77e4531
PZ		 4582}
4583
20bc8673 4584void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4585{
4586 struct drm_device *dev = crtc->base.dev;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588
6e3c9717 4589 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4590 return;
4591
4592 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4593 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4594 mutex_lock(&dev_priv->rps.hw_lock);
4595 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4596 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4597 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4598 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4599 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4600 } else {
2a114cc1 4601 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4602 POSTING_READ(IPS_CTL);
4603 }
d77e4531
PZ		 4604
4605 /* We need to wait for a vblank before we can disable the plane. */
4606 intel_wait_for_vblank(dev, crtc->pipe);
4607}
4608
4609/** Loads the palette/gamma unit for the CRTC with the prepared values */
4610static void intel_crtc_load_lut(struct drm_crtc *crtc)
4611{
4612 struct drm_device *dev = crtc->dev;
4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4615 enum pipe pipe = intel_crtc->pipe;
4616 int palreg = PALETTE(pipe);
4617 int i;
4618 bool reenable_ips = false;
4619
4620 /* The clocks have to be on to load the palette. */
83d65738 4621 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4622 return;
4623
4624 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4625 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4626 assert_dsi_pll_enabled(dev_priv);
4627 else
4628 assert_pll_enabled(dev_priv, pipe);
4629 }
4630
4631 /* use legacy palette for Ironlake */
7a1db49a 4632 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4633 palreg = LGC_PALETTE(pipe);
4634
4635 /* Workaround : Do not read or write the pipe palette/gamma data while
4636 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4637 */
6e3c9717 4638 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4639 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4640 GAMMA_MODE_MODE_SPLIT)) {
4641 hsw_disable_ips(intel_crtc);
4642 reenable_ips = true;
4643 }
4644
4645 for (i = 0; i < 256; i++) {
4646 I915_WRITE(palreg + 4 * i,
4647 (intel_crtc->lut_r[i] << 16) |
4648 (intel_crtc->lut_g[i] << 8) |
4649 intel_crtc->lut_b[i]);
4650 }
4651
4652 if (reenable_ips)
4653 hsw_enable_ips(intel_crtc);
4654}
4655
d3eedb1a
VS		 4656static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4657{
4658 if (!enable && intel_crtc->overlay) {
4659 struct drm_device *dev = intel_crtc->base.dev;
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661
4662 mutex_lock(&dev->struct_mutex);
4663 dev_priv->mm.interruptible = false;
4664 (void) intel_overlay_switch_off(intel_crtc->overlay);
4665 dev_priv->mm.interruptible = true;
4666 mutex_unlock(&dev->struct_mutex);
4667 }
4668
4669 /* Let userspace switch the overlay on again. In most cases userspace
4670 * has to recompute where to put it anyway.
4671 */
4672}
4673
d3eedb1a 4674static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4675{
4676 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 int pipe = intel_crtc->pipe;
a5c4d7bc 4679
fdd508a6 4680 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4681 intel_enable_sprite_planes(crtc);
a5c4d7bc 4682 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4683 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4684
4685 hsw_enable_ips(intel_crtc);
4686
4687 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4688 intel_fbc_update(dev);
a5c4d7bc 4689 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4690
4691 /*
4692 * FIXME: Once we grow proper nuclear flip support out of this we need
4693 * to compute the mask of flip planes precisely. For the time being
4694 * consider this a flip from a NULL plane.
4695 */
4696 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4697}
4698
d3eedb1a 4699static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4700{
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4705
4706 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4707
e35fef21 4708 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4709 intel_fbc_disable(dev);
a5c4d7bc
VS		 4710
4711 hsw_disable_ips(intel_crtc);
4712
d3eedb1a 4713 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4714 intel_crtc_update_cursor(crtc, false);
4a3b8769 4715 intel_disable_sprite_planes(crtc);
fdd508a6 4716 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4717
f99d7069
DV		 4718 /*
4719 * FIXME: Once we grow proper nuclear flip support out of this we need
4720 * to compute the mask of flip planes precisely. For the time being
4721 * consider this a flip to a NULL plane.
4722 */
4723 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4724}
4725
f67a559d
JB		 4726static void ironlake_crtc_enable(struct drm_crtc *crtc)
4727{
4728 struct drm_device *dev = crtc->dev;
4729 struct drm_i915_private *dev_priv = dev->dev_private;
4730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4731 struct intel_encoder *encoder;
f67a559d 4732 int pipe = intel_crtc->pipe;
f67a559d 4733
83d65738 4734 WARN_ON(!crtc->state->enable);
08a48469 4735
f67a559d
JB		 4736 if (intel_crtc->active)
4737 return;
4738
6e3c9717 4739 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4740 intel_prepare_shared_dpll(intel_crtc);
4741
6e3c9717 4742 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4743 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4744
4745 intel_set_pipe_timings(intel_crtc);
4746
6e3c9717 4747 if (intel_crtc->config->has_pch_encoder) {
29407aab 4748 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4749 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4750 }
4751
4752 ironlake_set_pipeconf(crtc);
4753
f67a559d 4754 intel_crtc->active = true;
8664281b 4755
a72e4c9f
DV		 4756 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4758
f6736a1a 4759 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4760 if (encoder->pre_enable)
4761 encoder->pre_enable(encoder);
f67a559d 4762
6e3c9717 4763 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4764 /* Note: FDI PLL enabling _must_ be done before we enable the
4765 * cpu pipes, hence this is separate from all the other fdi/pch
4766 * enabling. */
88cefb6c 4767 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4768 } else {
4769 assert_fdi_tx_disabled(dev_priv, pipe);
4770 assert_fdi_rx_disabled(dev_priv, pipe);
4771 }
f67a559d 4772
b074cec8 4773 ironlake_pfit_enable(intel_crtc);
f67a559d 4774
9c54c0dd
JB		 4775 /*
4776 * On ILK+ LUT must be loaded before the pipe is running but with
4777 * clocks enabled
4778 */
4779 intel_crtc_load_lut(crtc);
4780
f37fcc2a 4781 intel_update_watermarks(crtc);
e1fdc473 4782 intel_enable_pipe(intel_crtc);
f67a559d 4783
6e3c9717 4784 if (intel_crtc->config->has_pch_encoder)
f67a559d 4785 ironlake_pch_enable(crtc);
c98e9dcf 4786
f9b61ff6
DV		 4787 assert_vblank_disabled(crtc);
4788 drm_crtc_vblank_on(crtc);
4789
fa5c73b1
DV		 4790 for_each_encoder_on_crtc(dev, crtc, encoder)
4791 encoder->enable(encoder);
61b77ddd
DV		 4792
4793 if (HAS_PCH_CPT(dev))
a1520318 4794 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4795
d3eedb1a 4796 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4797}
4798
42db64ef
PZ		 4799/* IPS only exists on ULT machines and is tied to pipe A. */
4800static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4801{
f5adf94e 4802 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4803}
4804
e4916946
PZ		 4805/*
4806 * This implements the workaround described in the "notes" section of the mode
4807 * set sequence documentation. When going from no pipes or single pipe to
4808 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4809 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4810 */
4811static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4812{
4813 struct drm_device *dev = crtc->base.dev;
4814 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4815
4816 /* We want to get the other_active_crtc only if there's only 1 other
4817 * active crtc. */
d3fcc808 4818 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4819 if (!crtc_it->active || crtc_it == crtc)
4820 continue;
4821
4822 if (other_active_crtc)
4823 return;
4824
4825 other_active_crtc = crtc_it;
4826 }
4827 if (!other_active_crtc)
4828 return;
4829
4830 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4831 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4832}
4833
4f771f10
PZ		 4834static void haswell_crtc_enable(struct drm_crtc *crtc)
4835{
4836 struct drm_device *dev = crtc->dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4839 struct intel_encoder *encoder;
4840 int pipe = intel_crtc->pipe;
4f771f10 4841
83d65738 4842 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4843
4844 if (intel_crtc->active)
4845 return;
4846
df8ad70c
DV		 4847 if (intel_crtc_to_shared_dpll(intel_crtc))
4848 intel_enable_shared_dpll(intel_crtc);
4849
6e3c9717 4850 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4851 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4852
4853 intel_set_pipe_timings(intel_crtc);
4854
6e3c9717
ACO		 4855 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4856 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4857 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4858 }
4859
6e3c9717 4860 if (intel_crtc->config->has_pch_encoder) {
229fca97 4861 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4862 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4863 }
4864
4865 haswell_set_pipeconf(crtc);
4866
4867 intel_set_pipe_csc(crtc);
4868
4f771f10 4869 intel_crtc->active = true;
8664281b 4870
a72e4c9f 4871 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
4875
6e3c9717 4876 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4877 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4878 true);
4fe9467d
ID		 4879 dev_priv->display.fdi_link_train(crtc);
4880 }
4881
1f544388 4882 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4883
bd2e244f 4884 if (IS_SKYLAKE(dev))
a1b2278e 4885 skylake_pfit_update(intel_crtc, 1);
bd2e244f
JB		 4886 else
4887 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4888
4889 /*
4890 * On ILK+ LUT must be loaded before the pipe is running but with
4891 * clocks enabled
4892 */
4893 intel_crtc_load_lut(crtc);
4894
1f544388 4895 intel_ddi_set_pipe_settings(crtc);
8228c251 4896 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4897
f37fcc2a 4898 intel_update_watermarks(crtc);
e1fdc473 4899 intel_enable_pipe(intel_crtc);
42db64ef 4900
6e3c9717 4901 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4902 lpt_pch_enable(crtc);
4f771f10 4903
6e3c9717 4904 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4905 intel_ddi_set_vc_payload_alloc(crtc, true);
4906
f9b61ff6
DV		 4907 assert_vblank_disabled(crtc);
4908 drm_crtc_vblank_on(crtc);
4909
8807e55b 4910 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4911 encoder->enable(encoder);
8807e55b
JN		 4912 intel_opregion_notify_encoder(encoder, true);
4913 }
4f771f10 4914
e4916946
PZ		 4915 /* If we change the relative order between pipe/planes enabling, we need
4916 * to change the workaround. */
4917 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4918 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4919}
4920
3f8dce3a
DV		 4921static void ironlake_pfit_disable(struct intel_crtc *crtc)
4922{
4923 struct drm_device *dev = crtc->base.dev;
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 int pipe = crtc->pipe;
4926
4927 /* To avoid upsetting the power well on haswell only disable the pfit if
4928 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4929 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4930 I915_WRITE(PF_CTL(pipe), 0);
4931 I915_WRITE(PF_WIN_POS(pipe), 0);
4932 I915_WRITE(PF_WIN_SZ(pipe), 0);
4933 }
4934}
4935
6be4a607
JB		 4936static void ironlake_crtc_disable(struct drm_crtc *crtc)
4937{
4938 struct drm_device *dev = crtc->dev;
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4941 struct intel_encoder *encoder;
6be4a607 4942 int pipe = intel_crtc->pipe;
5eddb70b 4943 u32 reg, temp;
b52eb4dc 4944
f7abfe8b
CW		 4945 if (!intel_crtc->active)
4946 return;
4947
d3eedb1a 4948 intel_crtc_disable_planes(crtc);
a5c4d7bc 4949
ea9d758d
DV		 4950 for_each_encoder_on_crtc(dev, crtc, encoder)
4951 encoder->disable(encoder);
4952
f9b61ff6
DV		 4953 drm_crtc_vblank_off(crtc);
4954 assert_vblank_disabled(crtc);
4955
6e3c9717 4956 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4957 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4958
575f7ab7 4959 intel_disable_pipe(intel_crtc);
32f9d658 4960
3f8dce3a 4961 ironlake_pfit_disable(intel_crtc);
2c07245f 4962
bf49ec8c
DV		 4963 for_each_encoder_on_crtc(dev, crtc, encoder)
4964 if (encoder->post_disable)
4965 encoder->post_disable(encoder);
2c07245f 4966
6e3c9717 4967 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4968 ironlake_fdi_disable(crtc);
913d8d11 4969
d925c59a 4970 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4971
d925c59a
DV		 4972 if (HAS_PCH_CPT(dev)) {
4973 /* disable TRANS_DP_CTL */
4974 reg = TRANS_DP_CTL(pipe);
4975 temp = I915_READ(reg);
4976 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4977 TRANS_DP_PORT_SEL_MASK);
4978 temp |= TRANS_DP_PORT_SEL_NONE;
4979 I915_WRITE(reg, temp);
4980
4981 /* disable DPLL_SEL */
4982 temp = I915_READ(PCH_DPLL_SEL);
11887397 4983 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4984 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4985 }
e3421a18 4986
d925c59a 4987 /* disable PCH DPLL */
e72f9fbf 4988 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4989
d925c59a
DV		 4990 ironlake_fdi_pll_disable(intel_crtc);
4991 }
6b383a7f 4992
f7abfe8b 4993 intel_crtc->active = false;
46ba614c 4994 intel_update_watermarks(crtc);
d1ebd816
BW		 4995
4996 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4997 intel_fbc_update(dev);
d1ebd816 4998 mutex_unlock(&dev->struct_mutex);
6be4a607 4999}
1b3c7a47 5000
4f771f10 5001static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5002{
4f771f10
PZ		 5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5006 struct intel_encoder *encoder;
6e3c9717 5007 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5008
4f771f10
PZ		 5009 if (!intel_crtc->active)
5010 return;
5011
d3eedb1a 5012 intel_crtc_disable_planes(crtc);
dda9a66a 5013
8807e55b
JN		 5014 for_each_encoder_on_crtc(dev, crtc, encoder) {
5015 intel_opregion_notify_encoder(encoder, false);
4f771f10 5016 encoder->disable(encoder);
8807e55b 5017 }
4f771f10 5018
f9b61ff6
DV		 5019 drm_crtc_vblank_off(crtc);
5020 assert_vblank_disabled(crtc);
5021
6e3c9717 5022 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5023 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5024 false);
575f7ab7 5025 intel_disable_pipe(intel_crtc);
4f771f10 5026
6e3c9717 5027 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5028 intel_ddi_set_vc_payload_alloc(crtc, false);
5029
ad80a810 5030 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5031
bd2e244f 5032 if (IS_SKYLAKE(dev))
a1b2278e 5033 skylake_pfit_update(intel_crtc, 0);
bd2e244f
JB		 5034 else
5035 ironlake_pfit_disable(intel_crtc);
4f771f10 5036
1f544388 5037 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5038
6e3c9717 5039 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5040 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5041 intel_ddi_fdi_disable(crtc);
83616634 5042 }
4f771f10 5043
97b040aa
ID		 5044 for_each_encoder_on_crtc(dev, crtc, encoder)
5045 if (encoder->post_disable)
5046 encoder->post_disable(encoder);
5047
4f771f10 5048 intel_crtc->active = false;
46ba614c 5049 intel_update_watermarks(crtc);
4f771f10
PZ		 5050
5051 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5052 intel_fbc_update(dev);
4f771f10 5053 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5054
5055 if (intel_crtc_to_shared_dpll(intel_crtc))
5056 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5057}
5058
ee7b9f93
JB		 5059static void ironlake_crtc_off(struct drm_crtc *crtc)
5060{
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5062 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5063}
5064
6441ab5f 5065
2dd24552
JB		 5066static void i9xx_pfit_enable(struct intel_crtc *crtc)
5067{
5068 struct drm_device *dev = crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5070 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5071
681a8504 5072 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5073 return;
5074
2dd24552 5075 /*
c0b03411
DV		 5076 * The panel fitter should only be adjusted whilst the pipe is disabled,
5077 * according to register description and PRM.
2dd24552 5078 */
c0b03411
DV		 5079 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5080 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5081
b074cec8
JB		 5082 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5083 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5084
5085 /* Border color in case we don't scale up to the full screen. Black by
5086 * default, change to something else for debugging. */
5087 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5088}
5089
d05410f9
DA		 5090static enum intel_display_power_domain port_to_power_domain(enum port port)
5091{
5092 switch (port) {
5093 case PORT_A:
5094 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5095 case PORT_B:
5096 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5097 case PORT_C:
5098 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5099 case PORT_D:
5100 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5101 default:
5102 WARN_ON_ONCE(1);
5103 return POWER_DOMAIN_PORT_OTHER;
5104 }
5105}
5106
77d22dca
ID		 5107#define for_each_power_domain(domain, mask) \
5108 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5109 if ((1 << (domain)) & (mask))
5110
319be8ae
ID		 5111enum intel_display_power_domain
5112intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5113{
5114 struct drm_device *dev = intel_encoder->base.dev;
5115 struct intel_digital_port *intel_dig_port;
5116
5117 switch (intel_encoder->type) {
5118 case INTEL_OUTPUT_UNKNOWN:
5119 /* Only DDI platforms should ever use this output type */
5120 WARN_ON_ONCE(!HAS_DDI(dev));
5121 case INTEL_OUTPUT_DISPLAYPORT:
5122 case INTEL_OUTPUT_HDMI:
5123 case INTEL_OUTPUT_EDP:
5124 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5125 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5126 case INTEL_OUTPUT_DP_MST:
5127 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5128 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5129 case INTEL_OUTPUT_ANALOG:
5130 return POWER_DOMAIN_PORT_CRT;
5131 case INTEL_OUTPUT_DSI:
5132 return POWER_DOMAIN_PORT_DSI;
5133 default:
5134 return POWER_DOMAIN_PORT_OTHER;
5135 }
5136}
5137
5138static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5139{
319be8ae
ID		 5140 struct drm_device *dev = crtc->dev;
5141 struct intel_encoder *intel_encoder;
5142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5143 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5144 unsigned long mask;
5145 enum transcoder transcoder;
5146
5147 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5148
5149 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5150 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5151 if (intel_crtc->config->pch_pfit.enabled ||
5152 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5153 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5154
319be8ae
ID		 5155 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5156 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5157
77d22dca
ID		 5158 return mask;
5159}
5160
679dacd4 5161static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5162{
679dacd4 5163 struct drm_device *dev = state->dev;
77d22dca
ID		 5164 struct drm_i915_private *dev_priv = dev->dev_private;
5165 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5166 struct intel_crtc *crtc;
5167
5168 /*
5169 * First get all needed power domains, then put all unneeded, to avoid
5170 * any unnecessary toggling of the power wells.
5171 */
d3fcc808 5172 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5173 enum intel_display_power_domain domain;
5174
83d65738 5175 if (!crtc->base.state->enable)
77d22dca
ID		 5176 continue;
5177
319be8ae 5178 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5179
5180 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5181 intel_display_power_get(dev_priv, domain);
5182 }
5183
50f6e502 5184 if (dev_priv->display.modeset_global_resources)
679dacd4 5185 dev_priv->display.modeset_global_resources(state);
50f6e502 5186
d3fcc808 5187 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5188 enum intel_display_power_domain domain;
5189
5190 for_each_power_domain(domain, crtc->enabled_power_domains)
5191 intel_display_power_put(dev_priv, domain);
5192
5193 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5194 }
5195
5196 intel_display_set_init_power(dev_priv, false);
5197}
5198
f8437dd1
VK		 5199void broxton_set_cdclk(struct drm_device *dev, int frequency)
5200{
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202 uint32_t divider;
5203 uint32_t ratio;
5204 uint32_t current_freq;
5205 int ret;
5206
5207 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5208 switch (frequency) {
5209 case 144000:
5210 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5211 ratio = BXT_DE_PLL_RATIO(60);
5212 break;
5213 case 288000:
5214 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5215 ratio = BXT_DE_PLL_RATIO(60);
5216 break;
5217 case 384000:
5218 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5219 ratio = BXT_DE_PLL_RATIO(60);
5220 break;
5221 case 576000:
5222 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5223 ratio = BXT_DE_PLL_RATIO(60);
5224 break;
5225 case 624000:
5226 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5227 ratio = BXT_DE_PLL_RATIO(65);
5228 break;
5229 case 19200:
5230 /*
5231 * Bypass frequency with DE PLL disabled. Init ratio, divider
5232 * to suppress GCC warning.
5233 */
5234 ratio = 0;
5235 divider = 0;
5236 break;
5237 default:
5238 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5239
5240 return;
5241 }
5242
5243 mutex_lock(&dev_priv->rps.hw_lock);
5244 /* Inform power controller of upcoming frequency change */
5245 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5246 0x80000000);
5247 mutex_unlock(&dev_priv->rps.hw_lock);
5248
5249 if (ret) {
5250 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5251 ret, frequency);
5252 return;
5253 }
5254
5255 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5256 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5257 current_freq = current_freq * 500 + 1000;
5258
5259 /*
5260 * DE PLL has to be disabled when
5261 * - setting to 19.2MHz (bypass, PLL isn't used)
5262 * - before setting to 624MHz (PLL needs toggling)
5263 * - before setting to any frequency from 624MHz (PLL needs toggling)
5264 */
5265 if (frequency == 19200 || frequency == 624000 ||
5266 current_freq == 624000) {
5267 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5268 /* Timeout 200us */
5269 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5270 1))
5271 DRM_ERROR("timout waiting for DE PLL unlock\n");
5272 }
5273
5274 if (frequency != 19200) {
5275 uint32_t val;
5276
5277 val = I915_READ(BXT_DE_PLL_CTL);
5278 val &= ~BXT_DE_PLL_RATIO_MASK;
5279 val |= ratio;
5280 I915_WRITE(BXT_DE_PLL_CTL, val);
5281
5282 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5283 /* Timeout 200us */
5284 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5285 DRM_ERROR("timeout waiting for DE PLL lock\n");
5286
5287 val = I915_READ(CDCLK_CTL);
5288 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5289 val |= divider;
5290 /*
5291 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5292 * enable otherwise.
5293 */
5294 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5295 if (frequency >= 500000)
5296 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5297
5298 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5299 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5300 val |= (frequency - 1000) / 500;
5301 I915_WRITE(CDCLK_CTL, val);
5302 }
5303
5304 mutex_lock(&dev_priv->rps.hw_lock);
5305 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5306 DIV_ROUND_UP(frequency, 25000));
5307 mutex_unlock(&dev_priv->rps.hw_lock);
5308
5309 if (ret) {
5310 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5311 ret, frequency);
5312 return;
5313 }
5314
5315 dev_priv->cdclk_freq = frequency;
5316}
5317
5318void broxton_init_cdclk(struct drm_device *dev)
5319{
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 uint32_t val;
5322
5323 /*
5324 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5325 * or else the reset will hang because there is no PCH to respond.
5326 * Move the handshake programming to initialization sequence.
5327 * Previously was left up to BIOS.
5328 */
5329 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5330 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5331 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5332
5333 /* Enable PG1 for cdclk */
5334 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5335
5336 /* check if cd clock is enabled */
5337 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5338 DRM_DEBUG_KMS("Display already initialized\n");
5339 return;
5340 }
5341
5342 /*
5343 * FIXME:
5344 * - The initial CDCLK needs to be read from VBT.
5345 * Need to make this change after VBT has changes for BXT.
5346 * - check if setting the max (or any) cdclk freq is really necessary
5347 * here, it belongs to modeset time
5348 */
5349 broxton_set_cdclk(dev, 624000);
5350
5351 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5352 udelay(10);
5353
5354 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5355 DRM_ERROR("DBuf power enable timeout!\n");
5356}
5357
5358void broxton_uninit_cdclk(struct drm_device *dev)
5359{
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361
5362 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5363 udelay(10);
5364
5365 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5366 DRM_ERROR("DBuf power disable timeout!\n");
5367
5368 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5369 broxton_set_cdclk(dev, 19200);
5370
5371 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5372}
5373
dfcab17e 5374/* returns HPLL frequency in kHz */
f8bf63fd 5375static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5376{
586f49dc 5377 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5378
586f49dc
JB		 5379 /* Obtain SKU information */
5380 mutex_lock(&dev_priv->dpio_lock);
5381 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5382 CCK_FUSE_HPLL_FREQ_MASK;
5383 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5384
dfcab17e 5385 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5386}
5387
f8bf63fd
VS		 5388static void vlv_update_cdclk(struct drm_device *dev)
5389{
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391
164dfd28 5392 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5393 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5394 dev_priv->cdclk_freq);
f8bf63fd
VS		 5395
5396 /*
5397 * Program the gmbus_freq based on the cdclk frequency.
5398 * BSpec erroneously claims we should aim for 4MHz, but
5399 * in fact 1MHz is the correct frequency.
5400 */
164dfd28 5401 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5402}
5403
30a970c6
JB		 5404/* Adjust CDclk dividers to allow high res or save power if possible */
5405static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5406{
5407 struct drm_i915_private *dev_priv = dev->dev_private;
5408 u32 val, cmd;
5409
164dfd28
VK		 5410 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5411 != dev_priv->cdclk_freq);
d60c4473 5412
dfcab17e 5413 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5414 cmd = 2;
dfcab17e 5415 else if (cdclk == 266667)
30a970c6
JB		 5416 cmd = 1;
5417 else
5418 cmd = 0;
5419
5420 mutex_lock(&dev_priv->rps.hw_lock);
5421 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5422 val &= ~DSPFREQGUAR_MASK;
5423 val |= (cmd << DSPFREQGUAR_SHIFT);
5424 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5425 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5426 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5427 50)) {
5428 DRM_ERROR("timed out waiting for CDclk change\n");
5429 }
5430 mutex_unlock(&dev_priv->rps.hw_lock);
5431
dfcab17e 5432 if (cdclk == 400000) {
6bcda4f0 5433 u32 divider;
30a970c6 5434
6bcda4f0 5435 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5436
5437 mutex_lock(&dev_priv->dpio_lock);
5438 /* adjust cdclk divider */
5439 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5440 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5441 val |= divider;
5442 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5443
5444 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5445 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5446 50))
5447 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5448 mutex_unlock(&dev_priv->dpio_lock);
5449 }
5450
5451 mutex_lock(&dev_priv->dpio_lock);
5452 /* adjust self-refresh exit latency value */
5453 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5454 val &= ~0x7f;
5455
5456 /*
5457 * For high bandwidth configs, we set a higher latency in the bunit
5458 * so that the core display fetch happens in time to avoid underruns.
5459 */
dfcab17e 5460 if (cdclk == 400000)
30a970c6
JB		 5461 val |= 4500 / 250; /* 4.5 usec */
5462 else
5463 val |= 3000 / 250; /* 3.0 usec */
5464 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5465 mutex_unlock(&dev_priv->dpio_lock);
5466
f8bf63fd 5467 vlv_update_cdclk(dev);
30a970c6
JB		 5468}
5469
383c5a6a
VS		 5470static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 u32 val, cmd;
5474
164dfd28
VK		 5475 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5476 != dev_priv->cdclk_freq);
383c5a6a
VS		 5477
5478 switch (cdclk) {
383c5a6a
VS		 5479 case 333333:
5480 case 320000:
383c5a6a 5481 case 266667:
383c5a6a 5482 case 200000:
383c5a6a
VS		 5483 break;
5484 default:
5f77eeb0 5485 MISSING_CASE(cdclk);
383c5a6a
VS		 5486 return;
5487 }
5488
9d0d3fda
VS		 5489 /*
5490 * Specs are full of misinformation, but testing on actual
5491 * hardware has shown that we just need to write the desired
5492 * CCK divider into the Punit register.
5493 */
5494 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5495
383c5a6a
VS		 5496 mutex_lock(&dev_priv->rps.hw_lock);
5497 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5498 val &= ~DSPFREQGUAR_MASK_CHV;
5499 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5500 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5501 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5502 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5503 50)) {
5504 DRM_ERROR("timed out waiting for CDclk change\n");
5505 }
5506 mutex_unlock(&dev_priv->rps.hw_lock);
5507
5508 vlv_update_cdclk(dev);
5509}
5510
30a970c6
JB		 5511static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5512 int max_pixclk)
5513{
6bcda4f0 5514 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5515 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5516
30a970c6
JB		 5517 /*
5518 * Really only a few cases to deal with, as only 4 CDclks are supported:
5519 * 200MHz
5520 * 267MHz
29dc7ef3 5521 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5522 * 400MHz (VLV only)
5523 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5524 * of the lower bin and adjust if needed.
e37c67a1
VS		 5525 *
5526 * We seem to get an unstable or solid color picture at 200MHz.
5527 * Not sure what's wrong. For now use 200MHz only when all pipes
5528 * are off.
30a970c6 5529 */
6cca3195
VS		 5530 if (!IS_CHERRYVIEW(dev_priv) &&
5531 max_pixclk > freq_320*limit/100)
dfcab17e 5532 return 400000;
6cca3195 5533 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5534 return freq_320;
e37c67a1 5535 else if (max_pixclk > 0)
dfcab17e 5536 return 266667;
e37c67a1
VS		 5537 else
5538 return 200000;
30a970c6
JB		 5539}
5540
f8437dd1
VK		 5541static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5542 int max_pixclk)
5543{
5544 /*
5545 * FIXME:
5546 * - remove the guardband, it's not needed on BXT
5547 * - set 19.2MHz bypass frequency if there are no active pipes
5548 */
5549 if (max_pixclk > 576000*9/10)
5550 return 624000;
5551 else if (max_pixclk > 384000*9/10)
5552 return 576000;
5553 else if (max_pixclk > 288000*9/10)
5554 return 384000;
5555 else if (max_pixclk > 144000*9/10)
5556 return 288000;
5557 else
5558 return 144000;
5559}
5560
2f2d7aa1 5561/* compute the max pixel clock for new configuration */
304603f4 5562static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5563{
304603f4 5564 struct drm_device *dev = state->dev;
30a970c6 5565 struct intel_crtc *intel_crtc;
304603f4 5566 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5567 int max_pixclk = 0;
5568
d3fcc808 5569 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5570 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5571 if (IS_ERR(crtc_state))
5572 return PTR_ERR(crtc_state);
5573
5574 if (!crtc_state->base.enable)
5575 continue;
5576
5577 max_pixclk = max(max_pixclk,
5578 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5579 }
5580
5581 return max_pixclk;
5582}
5583
304603f4 5584static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5585 unsigned *prepare_pipes)
30a970c6 5586{
304603f4 5587 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5588 struct intel_crtc *intel_crtc;
304603f4 5589 int max_pixclk = intel_mode_max_pixclk(state);
f8437dd1 5590 int cdclk;
304603f4
ACO		 5591
5592 if (max_pixclk < 0)
5593 return max_pixclk;
30a970c6 5594
f8437dd1
VK		 5595 if (IS_VALLEYVIEW(dev_priv))
5596 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5597 else
5598 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5599
5600 if (cdclk == dev_priv->cdclk_freq)
304603f4 5601 return 0;
30a970c6 5602
2f2d7aa1 5603 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5604 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5605 if (intel_crtc->base.state->enable)
30a970c6 5606 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5607
5608 return 0;
30a970c6
JB		 5609}
5610
1e69cd74
VS		 5611static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5612{
5613 unsigned int credits, default_credits;
5614
5615 if (IS_CHERRYVIEW(dev_priv))
5616 default_credits = PFI_CREDIT(12);
5617 else
5618 default_credits = PFI_CREDIT(8);
5619
164dfd28 5620 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5621 /* CHV suggested value is 31 or 63 */
5622 if (IS_CHERRYVIEW(dev_priv))
5623 credits = PFI_CREDIT_31;
5624 else
5625 credits = PFI_CREDIT(15);
5626 } else {
5627 credits = default_credits;
5628 }
5629
5630 /*
5631 * WA - write default credits before re-programming
5632 * FIXME: should we also set the resend bit here?
5633 */
5634 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5635 default_credits);
5636
5637 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5638 credits | PFI_CREDIT_RESEND);
5639
5640 /*
5641 * FIXME is this guaranteed to clear
5642 * immediately or should we poll for it?
5643 */
5644 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5645}
5646
679dacd4 5647static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5648{
679dacd4 5649 struct drm_device *dev = state->dev;
30a970c6 5650 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5651 int max_pixclk = intel_mode_max_pixclk(state);
5652 int req_cdclk;
5653
5654 /* The only reason this can fail is if we fail to add the crtc_state
5655 * to the atomic state. But that can't happen since the call to
5656 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5657 * can't have failed otherwise the mode set would be aborted) added all
5658 * the states already. */
5659 if (WARN_ON(max_pixclk < 0))
5660 return;
5661
5662 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5663
164dfd28 5664 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5665 /*
5666 * FIXME: We can end up here with all power domains off, yet
5667 * with a CDCLK frequency other than the minimum. To account
5668 * for this take the PIPE-A power domain, which covers the HW
5669 * blocks needed for the following programming. This can be
5670 * removed once it's guaranteed that we get here either with
5671 * the minimum CDCLK set, or the required power domains
5672 * enabled.
5673 */
5674 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5675
383c5a6a
VS		 5676 if (IS_CHERRYVIEW(dev))
5677 cherryview_set_cdclk(dev, req_cdclk);
5678 else
5679 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5680
1e69cd74
VS		 5681 vlv_program_pfi_credits(dev_priv);
5682
738c05c0 5683 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5684 }
30a970c6
JB		 5685}
5686
89b667f8
JB		 5687static void valleyview_crtc_enable(struct drm_crtc *crtc)
5688{
5689 struct drm_device *dev = crtc->dev;
a72e4c9f 5690 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5692 struct intel_encoder *encoder;
5693 int pipe = intel_crtc->pipe;
23538ef1 5694 bool is_dsi;
89b667f8 5695
83d65738 5696 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5697
5698 if (intel_crtc->active)
5699 return;
5700
409ee761 5701 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5702
1ae0d137
VS		 5703 if (!is_dsi) {
5704 if (IS_CHERRYVIEW(dev))
6e3c9717 5705 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5706 else
6e3c9717 5707 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5708 }
5b18e57c 5709
6e3c9717 5710 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5711 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5712
5713 intel_set_pipe_timings(intel_crtc);
5714
c14b0485
VS		 5715 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5716 struct drm_i915_private *dev_priv = dev->dev_private;
5717
5718 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5719 I915_WRITE(CHV_CANVAS(pipe), 0);
5720 }
5721
5b18e57c
DV		 5722 i9xx_set_pipeconf(intel_crtc);
5723
89b667f8 5724 intel_crtc->active = true;
89b667f8 5725
a72e4c9f 5726 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5727
89b667f8
JB		 5728 for_each_encoder_on_crtc(dev, crtc, encoder)
5729 if (encoder->pre_pll_enable)
5730 encoder->pre_pll_enable(encoder);
5731
9d556c99
CML		 5732 if (!is_dsi) {
5733 if (IS_CHERRYVIEW(dev))
6e3c9717 5734 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5735 else
6e3c9717 5736 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5737 }
89b667f8
JB		 5738
5739 for_each_encoder_on_crtc(dev, crtc, encoder)
5740 if (encoder->pre_enable)
5741 encoder->pre_enable(encoder);
5742
2dd24552
JB		 5743 i9xx_pfit_enable(intel_crtc);
5744
63cbb074
VS		 5745 intel_crtc_load_lut(crtc);
5746
f37fcc2a 5747 intel_update_watermarks(crtc);
e1fdc473 5748 intel_enable_pipe(intel_crtc);
be6a6f8e 5749
4b3a9526
VS		 5750 assert_vblank_disabled(crtc);
5751 drm_crtc_vblank_on(crtc);
5752
f9b61ff6
DV		 5753 for_each_encoder_on_crtc(dev, crtc, encoder)
5754 encoder->enable(encoder);
5755
9ab0460b 5756 intel_crtc_enable_planes(crtc);
d40d9187 5757
56b80e1f 5758 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5759 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5760}
5761
f13c2ef3
DV		 5762static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5763{
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766
6e3c9717
ACO		 5767 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5768 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5769}
5770
0b8765c6 5771static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5772{
5773 struct drm_device *dev = crtc->dev;
a72e4c9f 5774 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5776 struct intel_encoder *encoder;
79e53945 5777 int pipe = intel_crtc->pipe;
79e53945 5778
83d65738 5779 WARN_ON(!crtc->state->enable);
08a48469 5780
f7abfe8b
CW		 5781 if (intel_crtc->active)
5782 return;
5783
f13c2ef3
DV		 5784 i9xx_set_pll_dividers(intel_crtc);
5785
6e3c9717 5786 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5787 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5788
5789 intel_set_pipe_timings(intel_crtc);
5790
5b18e57c
DV		 5791 i9xx_set_pipeconf(intel_crtc);
5792
f7abfe8b 5793 intel_crtc->active = true;
6b383a7f 5794
4a3436e8 5795 if (!IS_GEN2(dev))
a72e4c9f 5796 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5797
9d6d9f19
MK		 5798 for_each_encoder_on_crtc(dev, crtc, encoder)
5799 if (encoder->pre_enable)
5800 encoder->pre_enable(encoder);
5801
f6736a1a
DV		 5802 i9xx_enable_pll(intel_crtc);
5803
2dd24552
JB		 5804 i9xx_pfit_enable(intel_crtc);
5805
63cbb074
VS		 5806 intel_crtc_load_lut(crtc);
5807
f37fcc2a 5808 intel_update_watermarks(crtc);
e1fdc473 5809 intel_enable_pipe(intel_crtc);
be6a6f8e 5810
4b3a9526
VS		 5811 assert_vblank_disabled(crtc);
5812 drm_crtc_vblank_on(crtc);
5813
f9b61ff6
DV		 5814 for_each_encoder_on_crtc(dev, crtc, encoder)
5815 encoder->enable(encoder);
5816
9ab0460b 5817 intel_crtc_enable_planes(crtc);
d40d9187 5818
4a3436e8
VS		 5819 /*
5820 * Gen2 reports pipe underruns whenever all planes are disabled.
5821 * So don't enable underrun reporting before at least some planes
5822 * are enabled.
5823 * FIXME: Need to fix the logic to work when we turn off all planes
5824 * but leave the pipe running.
5825 */
5826 if (IS_GEN2(dev))
a72e4c9f 5827 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5828
56b80e1f 5829 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5830 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5831}
79e53945 5832
87476d63
DV		 5833static void i9xx_pfit_disable(struct intel_crtc *crtc)
5834{
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5837
6e3c9717 5838 if (!crtc->config->gmch_pfit.control)
328d8e82 5839 return;
87476d63 5840
328d8e82 5841 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5842
328d8e82
DV		 5843 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5844 I915_READ(PFIT_CONTROL));
5845 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5846}
5847
0b8765c6
JB		 5848static void i9xx_crtc_disable(struct drm_crtc *crtc)
5849{
5850 struct drm_device *dev = crtc->dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5853 struct intel_encoder *encoder;
0b8765c6 5854 int pipe = intel_crtc->pipe;
ef9c3aee 5855
f7abfe8b
CW		 5856 if (!intel_crtc->active)
5857 return;
5858
4a3436e8
VS		 5859 /*
5860 * Gen2 reports pipe underruns whenever all planes are disabled.
5861 * So diasble underrun reporting before all the planes get disabled.
5862 * FIXME: Need to fix the logic to work when we turn off all planes
5863 * but leave the pipe running.
5864 */
5865 if (IS_GEN2(dev))
a72e4c9f 5866 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5867
564ed191
ID		 5868 /*
5869 * Vblank time updates from the shadow to live plane control register
5870 * are blocked if the memory self-refresh mode is active at that
5871 * moment. So to make sure the plane gets truly disabled, disable
5872 * first the self-refresh mode. The self-refresh enable bit in turn
5873 * will be checked/applied by the HW only at the next frame start
5874 * event which is after the vblank start event, so we need to have a
5875 * wait-for-vblank between disabling the plane and the pipe.
5876 */
5877 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5878 intel_crtc_disable_planes(crtc);
5879
6304cd91
VS		 5880 /*
5881 * On gen2 planes are double buffered but the pipe isn't, so we must
5882 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5883 * We also need to wait on all gmch platforms because of the
5884 * self-refresh mode constraint explained above.
6304cd91 5885 */
564ed191 5886 intel_wait_for_vblank(dev, pipe);
6304cd91 5887
4b3a9526
VS		 5888 for_each_encoder_on_crtc(dev, crtc, encoder)
5889 encoder->disable(encoder);
5890
f9b61ff6
DV		 5891 drm_crtc_vblank_off(crtc);
5892 assert_vblank_disabled(crtc);
5893
575f7ab7 5894 intel_disable_pipe(intel_crtc);
24a1f16d 5895
87476d63 5896 i9xx_pfit_disable(intel_crtc);
24a1f16d 5897
89b667f8
JB		 5898 for_each_encoder_on_crtc(dev, crtc, encoder)
5899 if (encoder->post_disable)
5900 encoder->post_disable(encoder);
5901
409ee761 5902 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5903 if (IS_CHERRYVIEW(dev))
5904 chv_disable_pll(dev_priv, pipe);
5905 else if (IS_VALLEYVIEW(dev))
5906 vlv_disable_pll(dev_priv, pipe);
5907 else
1c4e0274 5908 i9xx_disable_pll(intel_crtc);
076ed3b2 5909 }
0b8765c6 5910
4a3436e8 5911 if (!IS_GEN2(dev))
a72e4c9f 5912 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5913
f7abfe8b 5914 intel_crtc->active = false;
46ba614c 5915 intel_update_watermarks(crtc);
f37fcc2a 5916
efa9624e 5917 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5918 intel_fbc_update(dev);
efa9624e 5919 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5920}
5921
ee7b9f93
JB		 5922static void i9xx_crtc_off(struct drm_crtc *crtc)
5923{
5924}
5925
b04c5bd6
BF		 5926/* Master function to enable/disable CRTC and corresponding power wells */
5927void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5928{
5929 struct drm_device *dev = crtc->dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5932 enum intel_display_power_domain domain;
5933 unsigned long domains;
976f8a20 5934
0e572fe7
DV		 5935 if (enable) {
5936 if (!intel_crtc->active) {
e1e9fb84
DV		 5937 domains = get_crtc_power_domains(crtc);
5938 for_each_power_domain(domain, domains)
5939 intel_display_power_get(dev_priv, domain);
5940 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5941
5942 dev_priv->display.crtc_enable(crtc);
5943 }
5944 } else {
5945 if (intel_crtc->active) {
5946 dev_priv->display.crtc_disable(crtc);
5947
e1e9fb84
DV		 5948 domains = intel_crtc->enabled_power_domains;
5949 for_each_power_domain(domain, domains)
5950 intel_display_power_put(dev_priv, domain);
5951 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5952 }
5953 }
b04c5bd6
BF		 5954}
5955
5956/**
5957 * Sets the power management mode of the pipe and plane.
5958 */
5959void intel_crtc_update_dpms(struct drm_crtc *crtc)
5960{
5961 struct drm_device *dev = crtc->dev;
5962 struct intel_encoder *intel_encoder;
5963 bool enable = false;
5964
5965 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5966 enable |= intel_encoder->connectors_active;
5967
5968 intel_crtc_control(crtc, enable);
976f8a20
DV		 5969}
5970
cdd59983
CW		 5971static void intel_crtc_disable(struct drm_crtc *crtc)
5972{
cdd59983 5973 struct drm_device *dev = crtc->dev;
976f8a20 5974 struct drm_connector *connector;
ee7b9f93 5975 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5976
976f8a20 5977 /* crtc should still be enabled when we disable it. */
83d65738 5978 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5979
5980 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5981 dev_priv->display.off(crtc);
5982
70a101f8 5983 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 5984
5985 /* Update computed state. */
5986 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5987 if (!connector->encoder || !connector->encoder->crtc)
5988 continue;
5989
5990 if (connector->encoder->crtc != crtc)
5991 continue;
5992
5993 connector->dpms = DRM_MODE_DPMS_OFF;
5994 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5995 }
5996}
5997
ea5b213a 5998void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5999{
4ef69c7a 6000 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6001
ea5b213a
CW		 6002 drm_encoder_cleanup(encoder);
6003 kfree(intel_encoder);
7e7d76c3
JB		 6004}
6005
9237329d 6006/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6007 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6008 * state of the entire output pipe. */
9237329d 6009static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6010{
5ab432ef
DV		 6011 if (mode == DRM_MODE_DPMS_ON) {
6012 encoder->connectors_active = true;
6013
b2cabb0e 6014 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6015 } else {
6016 encoder->connectors_active = false;
6017
b2cabb0e 6018 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6019 }
79e53945
JB		 6020}
6021
0a91ca29
DV		 6022/* Cross check the actual hw state with our own modeset state tracking (and it's
6023 * internal consistency). */
b980514c 6024static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6025{
0a91ca29
DV		 6026 if (connector->get_hw_state(connector)) {
6027 struct intel_encoder *encoder = connector->encoder;
6028 struct drm_crtc *crtc;
6029 bool encoder_enabled;
6030 enum pipe pipe;
6031
6032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6033 connector->base.base.id,
c23cc417 6034 connector->base.name);
0a91ca29 6035
0e32b39c
DA		 6036 /* there is no real hw state for MST connectors */
6037 if (connector->mst_port)
6038 return;
6039
e2c719b7 6040 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6041 "wrong connector dpms state\n");
e2c719b7 6042 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6043 "active connector not linked to encoder\n");
0a91ca29 6044
36cd7444 6045 if (encoder) {
e2c719b7 6046 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6047 "encoder->connectors_active not set\n");
6048
6049 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6050 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6051 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6052 return;
0a91ca29 6053
36cd7444 6054 crtc = encoder->base.crtc;
0a91ca29 6055
83d65738
MR		 6056 I915_STATE_WARN(!crtc->state->enable,
6057 "crtc not enabled\n");
e2c719b7
RC		 6058 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6059 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6060 "encoder active on the wrong pipe\n");
6061 }
0a91ca29 6062 }
79e53945
JB		 6063}
6064
9bdbd0b9
ACO		 6065int intel_connector_init(struct intel_connector *connector)
6066{
6067 struct drm_connector_state *connector_state;
6068
6069 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6070 if (!connector_state)
6071 return -ENOMEM;
6072
6073 connector->base.state = connector_state;
6074 return 0;
6075}
6076
6077struct intel_connector *intel_connector_alloc(void)
6078{
6079 struct intel_connector *connector;
6080
6081 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6082 if (!connector)
6083 return NULL;
6084
6085 if (intel_connector_init(connector) < 0) {
6086 kfree(connector);
6087 return NULL;
6088 }
6089
6090 return connector;
6091}
6092
5ab432ef
DV		 6093/* Even simpler default implementation, if there's really no special case to
6094 * consider. */
6095void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6096{
5ab432ef
DV		 6097 /* All the simple cases only support two dpms states. */
6098 if (mode != DRM_MODE_DPMS_ON)
6099 mode = DRM_MODE_DPMS_OFF;
d4270e57 6100
5ab432ef
DV		 6101 if (mode == connector->dpms)
6102 return;
6103
6104 connector->dpms = mode;
6105
6106 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6107 if (connector->encoder)
6108 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6109
b980514c 6110 intel_modeset_check_state(connector->dev);
79e53945
JB		 6111}
6112
f0947c37
DV		 6113/* Simple connector->get_hw_state implementation for encoders that support only
6114 * one connector and no cloning and hence the encoder state determines the state
6115 * of the connector. */
6116bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6117{
24929352 6118 enum pipe pipe = 0;
f0947c37 6119 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6120
f0947c37 6121 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6122}
6123
6d293983 6124static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6125{
6d293983
ACO		 6126 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6127 return crtc_state->fdi_lanes;
d272ddfa
VS		 6128
6129 return 0;
6130}
6131
6d293983 6132static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6133 struct intel_crtc_state *pipe_config)
1857e1da 6134{
6d293983
ACO		 6135 struct drm_atomic_state *state = pipe_config->base.state;
6136 struct intel_crtc *other_crtc;
6137 struct intel_crtc_state *other_crtc_state;
6138
1857e1da
DV		 6139 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6140 pipe_name(pipe), pipe_config->fdi_lanes);
6141 if (pipe_config->fdi_lanes > 4) {
6142 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6143 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6144 return -EINVAL;
1857e1da
DV		 6145 }
6146
bafb6553 6147 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6148 if (pipe_config->fdi_lanes > 2) {
6149 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6150 pipe_config->fdi_lanes);
6d293983 6151 return -EINVAL;
1857e1da 6152 } else {
6d293983 6153 return 0;
1857e1da
DV		 6154 }
6155 }
6156
6157 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6158 return 0;
1857e1da
DV		 6159
6160 /* Ivybridge 3 pipe is really complicated */
6161 switch (pipe) {
6162 case PIPE_A:
6d293983 6163 return 0;
1857e1da 6164 case PIPE_B:
6d293983
ACO		 6165 if (pipe_config->fdi_lanes <= 2)
6166 return 0;
6167
6168 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6169 other_crtc_state =
6170 intel_atomic_get_crtc_state(state, other_crtc);
6171 if (IS_ERR(other_crtc_state))
6172 return PTR_ERR(other_crtc_state);
6173
6174 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6175 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6176 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6177 return -EINVAL;
1857e1da 6178 }
6d293983 6179 return 0;
1857e1da 6180 case PIPE_C:
251cc67c
VS		 6181 if (pipe_config->fdi_lanes > 2) {
6182 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6183 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6184 return -EINVAL;
251cc67c 6185 }
6d293983
ACO		 6186
6187 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6188 other_crtc_state =
6189 intel_atomic_get_crtc_state(state, other_crtc);
6190 if (IS_ERR(other_crtc_state))
6191 return PTR_ERR(other_crtc_state);
6192
6193 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6194 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6195 return -EINVAL;
1857e1da 6196 }
6d293983 6197 return 0;
1857e1da
DV		 6198 default:
6199 BUG();
6200 }
6201}
6202
e29c22c0
DV		 6203#define RETRY 1
6204static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6205 struct intel_crtc_state *pipe_config)
877d48d5 6206{
1857e1da 6207 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6208 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6209 int lane, link_bw, fdi_dotclock, ret;
6210 bool needs_recompute = false;
877d48d5 6211
e29c22c0 6212retry:
877d48d5
DV		 6213 /* FDI is a binary signal running at ~2.7GHz, encoding
6214 * each output octet as 10 bits. The actual frequency
6215 * is stored as a divider into a 100MHz clock, and the
6216 * mode pixel clock is stored in units of 1KHz.
6217 * Hence the bw of each lane in terms of the mode signal
6218 * is:
6219 */
6220 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6221
241bfc38 6222 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6223
2bd89a07 6224 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6225 pipe_config->pipe_bpp);
6226
6227 pipe_config->fdi_lanes = lane;
6228
2bd89a07 6229 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6230 link_bw, &pipe_config->fdi_m_n);
1857e1da 6231
6d293983
ACO		 6232 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6233 intel_crtc->pipe, pipe_config);
6234 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6235 pipe_config->pipe_bpp -= 2*3;
6236 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6237 pipe_config->pipe_bpp);
6238 needs_recompute = true;
6239 pipe_config->bw_constrained = true;
6240
6241 goto retry;
6242 }
6243
6244 if (needs_recompute)
6245 return RETRY;
6246
6d293983 6247 return ret;
877d48d5
DV		 6248}
6249
42db64ef 6250static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6251 struct intel_crtc_state *pipe_config)
42db64ef 6252{
d330a953 6253 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6254 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6255 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6256}
6257
a43f6e0f 6258static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6259 struct intel_crtc_state *pipe_config)
79e53945 6260{
a43f6e0f 6261 struct drm_device *dev = crtc->base.dev;
8bd31e67 6262 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6263 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6264 int ret;
89749350 6265
ad3a4479 6266 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6267 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6268 int clock_limit =
6269 dev_priv->display.get_display_clock_speed(dev);
6270
6271 /*
6272 * Enable pixel doubling when the dot clock
6273 * is > 90% of the (display) core speed.
6274 *
b397c96b
VS		 6275 * GDG double wide on either pipe,
6276 * otherwise pipe A only.
cf532bb2 6277 */
b397c96b 6278 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6279 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6280 clock_limit *= 2;
cf532bb2 6281 pipe_config->double_wide = true;
ad3a4479
VS		 6282 }
6283
241bfc38 6284 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6285 return -EINVAL;
2c07245f 6286 }
89749350 6287
1d1d0e27
VS		 6288 /*
6289 * Pipe horizontal size must be even in:
6290 * - DVO ganged mode
6291 * - LVDS dual channel mode
6292 * - Double wide pipe
6293 */
a93e255f 6294 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6295 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6296 pipe_config->pipe_src_w &= ~1;
6297
8693a824
DL		 6298 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6299 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6300 */
6301 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6302 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6303 return -EINVAL;
44f46b42 6304
bd080ee5 6305 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 6306 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 6307 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 6308 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
6309 * for lvds. */
6310 pipe_config->pipe_bpp = 8*3;
6311 }
6312
f5adf94e 6313 if (HAS_IPS(dev))
a43f6e0f
DV		 6314 hsw_compute_ips_config(crtc, pipe_config);
6315
877d48d5 6316 if (pipe_config->has_pch_encoder)
a43f6e0f 6317 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6318
d03c93d4
CK		 6319 /* FIXME: remove below call once atomic mode set is place and all crtc
6320 * related checks called from atomic_crtc_check function */
6321 ret = 0;
6322 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6323 crtc, pipe_config->base.state);
6324 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6325
6326 return ret;
79e53945
JB		 6327}
6328
1652d19e
VS		 6329static int skylake_get_display_clock_speed(struct drm_device *dev)
6330{
6331 struct drm_i915_private *dev_priv = to_i915(dev);
6332 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6333 uint32_t cdctl = I915_READ(CDCLK_CTL);
6334 uint32_t linkrate;
6335
6336 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6337 WARN(1, "LCPLL1 not enabled\n");
6338 return 24000; /* 24MHz is the cd freq with NSSC ref */
6339 }
6340
6341 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6342 return 540000;
6343
6344 linkrate = (I915_READ(DPLL_CTRL1) &
6345 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6346
6347 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
6348 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
6349 /* vco 8640 */
6350 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6351 case CDCLK_FREQ_450_432:
6352 return 432000;
6353 case CDCLK_FREQ_337_308:
6354 return 308570;
6355 case CDCLK_FREQ_675_617:
6356 return 617140;
6357 default:
6358 WARN(1, "Unknown cd freq selection\n");
6359 }
6360 } else {
6361 /* vco 8100 */
6362 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6363 case CDCLK_FREQ_450_432:
6364 return 450000;
6365 case CDCLK_FREQ_337_308:
6366 return 337500;
6367 case CDCLK_FREQ_675_617:
6368 return 675000;
6369 default:
6370 WARN(1, "Unknown cd freq selection\n");
6371 }
6372 }
6373
6374 /* error case, do as if DPLL0 isn't enabled */
6375 return 24000;
6376}
6377
6378static int broadwell_get_display_clock_speed(struct drm_device *dev)
6379{
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381 uint32_t lcpll = I915_READ(LCPLL_CTL);
6382 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6383
6384 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6385 return 800000;
6386 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6387 return 450000;
6388 else if (freq == LCPLL_CLK_FREQ_450)
6389 return 450000;
6390 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6391 return 540000;
6392 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6393 return 337500;
6394 else
6395 return 675000;
6396}
6397
6398static int haswell_get_display_clock_speed(struct drm_device *dev)
6399{
6400 struct drm_i915_private *dev_priv = dev->dev_private;
6401 uint32_t lcpll = I915_READ(LCPLL_CTL);
6402 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6403
6404 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6405 return 800000;
6406 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6407 return 450000;
6408 else if (freq == LCPLL_CLK_FREQ_450)
6409 return 450000;
6410 else if (IS_HSW_ULT(dev))
6411 return 337500;
6412 else
6413 return 540000;
6414}
6415
25eb05fc
JB		 6416static int valleyview_get_display_clock_speed(struct drm_device *dev)
6417{
d197b7d3 6418 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6419 u32 val;
6420 int divider;
6421
6bcda4f0
VS		 6422 if (dev_priv->hpll_freq == 0)
6423 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6424
d197b7d3
VS		 6425 mutex_lock(&dev_priv->dpio_lock);
6426 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6427 mutex_unlock(&dev_priv->dpio_lock);
6428
6429 divider = val & DISPLAY_FREQUENCY_VALUES;
6430
7d007f40
VS		 6431 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6432 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6433 "cdclk change in progress\n");
6434
6bcda4f0 6435 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6436}
6437
b37a6434
VS		 6438static int ilk_get_display_clock_speed(struct drm_device *dev)
6439{
6440 return 450000;
6441}
6442
e70236a8
JB		 6443static int i945_get_display_clock_speed(struct drm_device *dev)
6444{
6445 return 400000;
6446}
79e53945 6447
e70236a8 6448static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6449{
e907f170 6450 return 333333;
e70236a8 6451}
79e53945 6452
e70236a8
JB		 6453static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6454{
6455 return 200000;
6456}
79e53945 6457
257a7ffc
DV		 6458static int pnv_get_display_clock_speed(struct drm_device *dev)
6459{
6460 u16 gcfgc = 0;
6461
6462 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6463
6464 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6465 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6466 return 266667;
257a7ffc 6467 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6468 return 333333;
257a7ffc 6469 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6470 return 444444;
257a7ffc
DV		 6471 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6472 return 200000;
6473 default:
6474 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6475 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6476 return 133333;
257a7ffc 6477 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6478 return 166667;
257a7ffc
DV		 6479 }
6480}
6481
e70236a8
JB		 6482static int i915gm_get_display_clock_speed(struct drm_device *dev)
6483{
6484 u16 gcfgc = 0;
79e53945 6485
e70236a8
JB		 6486 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6487
6488 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6489 return 133333;
e70236a8
JB		 6490 else {
6491 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6492 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6493 return 333333;
e70236a8
JB		 6494 default:
6495 case GC_DISPLAY_CLOCK_190_200_MHZ:
6496 return 190000;
79e53945 6497 }
e70236a8
JB		 6498 }
6499}
6500
6501static int i865_get_display_clock_speed(struct drm_device *dev)
6502{
e907f170 6503 return 266667;
e70236a8
JB		 6504}
6505
6506static int i855_get_display_clock_speed(struct drm_device *dev)
6507{
6508 u16 hpllcc = 0;
6509 /* Assume that the hardware is in the high speed state. This
6510 * should be the default.
6511 */
6512 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6513 case GC_CLOCK_133_200:
6514 case GC_CLOCK_100_200:
6515 return 200000;
6516 case GC_CLOCK_166_250:
6517 return 250000;
6518 case GC_CLOCK_100_133:
e907f170 6519 return 133333;
e70236a8 6520 }
79e53945 6521
e70236a8
JB		 6522 /* Shouldn't happen */
6523 return 0;
6524}
79e53945 6525
e70236a8
JB		 6526static int i830_get_display_clock_speed(struct drm_device *dev)
6527{
e907f170 6528 return 133333;
79e53945
JB		 6529}
6530
2c07245f 6531static void
a65851af 6532intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6533{
a65851af
VS		 6534 while (*num > DATA_LINK_M_N_MASK ||
6535 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6536 *num >>= 1;
6537 *den >>= 1;
6538 }
6539}
6540
a65851af
VS		 6541static void compute_m_n(unsigned int m, unsigned int n,
6542 uint32_t *ret_m, uint32_t *ret_n)
6543{
6544 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6545 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6546 intel_reduce_m_n_ratio(ret_m, ret_n);
6547}
6548
e69d0bc1
DV		 6549void
6550intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6551 int pixel_clock, int link_clock,
6552 struct intel_link_m_n *m_n)
2c07245f 6553{
e69d0bc1 6554 m_n->tu = 64;
a65851af
VS		 6555
6556 compute_m_n(bits_per_pixel * pixel_clock,
6557 link_clock * nlanes * 8,
6558 &m_n->gmch_m, &m_n->gmch_n);
6559
6560 compute_m_n(pixel_clock, link_clock,
6561 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6562}
6563
a7615030
CW		 6564static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6565{
d330a953
JN		 6566 if (i915.panel_use_ssc >= 0)
6567 return i915.panel_use_ssc != 0;
41aa3448 6568 return dev_priv->vbt.lvds_use_ssc
435793df 6569 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6570}
6571
a93e255f
ACO		 6572static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6573 int num_connectors)
c65d77d8 6574{
a93e255f 6575 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6576 struct drm_i915_private *dev_priv = dev->dev_private;
6577 int refclk;
6578
a93e255f
ACO		 6579 WARN_ON(!crtc_state->base.state);
6580
a0c4da24 6581 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6582 refclk = 100000;
a93e255f 6583 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6584 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6585 refclk = dev_priv->vbt.lvds_ssc_freq;
6586 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6587 } else if (!IS_GEN2(dev)) {
6588 refclk = 96000;
6589 } else {
6590 refclk = 48000;
6591 }
6592
6593 return refclk;
6594}
6595
7429e9d4 6596static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6597{
7df00d7a 6598 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6599}
f47709a9 6600
7429e9d4
DV		 6601static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6602{
6603 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6604}
6605
f47709a9 6606static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6607 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6608 intel_clock_t *reduced_clock)
6609{
f47709a9 6610 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6611 u32 fp, fp2 = 0;
6612
6613 if (IS_PINEVIEW(dev)) {
190f68c5 6614 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6615 if (reduced_clock)
7429e9d4 6616 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6617 } else {
190f68c5 6618 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6619 if (reduced_clock)
7429e9d4 6620 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6621 }
6622
190f68c5 6623 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6624
f47709a9 6625 crtc->lowfreq_avail = false;
a93e255f 6626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6627 reduced_clock) {
190f68c5 6628 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6629 crtc->lowfreq_avail = true;
a7516a05 6630 } else {
190f68c5 6631 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6632 }
6633}
6634
5e69f97f
CML		 6635static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6636 pipe)
89b667f8
JB		 6637{
6638 u32 reg_val;
6639
6640 /*
6641 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6642 * and set it to a reasonable value instead.
6643 */
ab3c759a 6644 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6645 reg_val &= 0xffffff00;
6646 reg_val |= 0x00000030;
ab3c759a 6647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6648
ab3c759a 6649 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6650 reg_val &= 0x8cffffff;
6651 reg_val = 0x8c000000;
ab3c759a 6652 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6653
ab3c759a 6654 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6655 reg_val &= 0xffffff00;
ab3c759a 6656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6657
ab3c759a 6658 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6659 reg_val &= 0x00ffffff;
6660 reg_val |= 0xb0000000;
ab3c759a 6661 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6662}
6663
b551842d
DV		 6664static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6665 struct intel_link_m_n *m_n)
6666{
6667 struct drm_device *dev = crtc->base.dev;
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 int pipe = crtc->pipe;
6670
e3b95f1e
DV		 6671 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6672 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6673 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6674 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6675}
6676
6677static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6678 struct intel_link_m_n *m_n,
6679 struct intel_link_m_n *m2_n2)
b551842d
DV		 6680{
6681 struct drm_device *dev = crtc->base.dev;
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683 int pipe = crtc->pipe;
6e3c9717 6684 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6685
6686 if (INTEL_INFO(dev)->gen >= 5) {
6687 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6688 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6689 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6690 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6691 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6692 * for gen < 8) and if DRRS is supported (to make sure the
6693 * registers are not unnecessarily accessed).
6694 */
44395bfe 6695 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6696 crtc->config->has_drrs) {
f769cd24
VK		 6697 I915_WRITE(PIPE_DATA_M2(transcoder),
6698 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6699 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6700 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6701 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6702 }
b551842d 6703 } else {
e3b95f1e
DV		 6704 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6705 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6706 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6707 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6708 }
6709}
6710
fe3cd48d 6711void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6712{
fe3cd48d
R		 6713 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6714
6715 if (m_n == M1_N1) {
6716 dp_m_n = &crtc->config->dp_m_n;
6717 dp_m2_n2 = &crtc->config->dp_m2_n2;
6718 } else if (m_n == M2_N2) {
6719
6720 /*
6721 * M2_N2 registers are not supported. Hence m2_n2 divider value
6722 * needs to be programmed into M1_N1.
6723 */
6724 dp_m_n = &crtc->config->dp_m2_n2;
6725 } else {
6726 DRM_ERROR("Unsupported divider value\n");
6727 return;
6728 }
6729
6e3c9717
ACO		 6730 if (crtc->config->has_pch_encoder)
6731 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6732 else
fe3cd48d 6733 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6734}
6735
d288f65f 6736static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6737 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6738{
6739 u32 dpll, dpll_md;
6740
6741 /*
6742 * Enable DPIO clock input. We should never disable the reference
6743 * clock for pipe B, since VGA hotplug / manual detection depends
6744 * on it.
6745 */
6746 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6747 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6748 /* We should never disable this, set it here for state tracking */
6749 if (crtc->pipe == PIPE_B)
6750 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6751 dpll |= DPLL_VCO_ENABLE;
d288f65f 6752 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6753
d288f65f 6754 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6755 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6756 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6757}
6758
d288f65f 6759static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6760 const struct intel_crtc_state *pipe_config)
a0c4da24 6761{
f47709a9 6762 struct drm_device *dev = crtc->base.dev;
a0c4da24 6763 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6764 int pipe = crtc->pipe;
bdd4b6a6 6765 u32 mdiv;
a0c4da24 6766 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6767 u32 coreclk, reg_val;
a0c4da24 6768
09153000
DV		 6769 mutex_lock(&dev_priv->dpio_lock);
6770
d288f65f
VS		 6771 bestn = pipe_config->dpll.n;
6772 bestm1 = pipe_config->dpll.m1;
6773 bestm2 = pipe_config->dpll.m2;
6774 bestp1 = pipe_config->dpll.p1;
6775 bestp2 = pipe_config->dpll.p2;
a0c4da24 6776
89b667f8
JB		 6777 /* See eDP HDMI DPIO driver vbios notes doc */
6778
6779 /* PLL B needs special handling */
bdd4b6a6 6780 if (pipe == PIPE_B)
5e69f97f 6781 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6782
6783 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6784 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6785
6786 /* Disable target IRef on PLL */
ab3c759a 6787 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6788 reg_val &= 0x00ffffff;
ab3c759a 6789 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6790
6791 /* Disable fast lock */
ab3c759a 6792 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6793
6794 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6795 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6796 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6797 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6798 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6799
6800 /*
6801 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6802 * but we don't support that).
6803 * Note: don't use the DAC post divider as it seems unstable.
6804 */
6805 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6806 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6807
a0c4da24 6808 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6809 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6810
89b667f8 6811 /* Set HBR and RBR LPF coefficients */
d288f65f 6812 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6813 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6814 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6815 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6816 0x009f0003);
89b667f8 6817 else
ab3c759a 6818 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6819 0x00d0000f);
6820
681a8504 6821 if (pipe_config->has_dp_encoder) {
89b667f8 6822 /* Use SSC source */
bdd4b6a6 6823 if (pipe == PIPE_A)
ab3c759a 6824 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6825 0x0df40000);
6826 else
ab3c759a 6827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6828 0x0df70000);
6829 } else { /* HDMI or VGA */
6830 /* Use bend source */
bdd4b6a6 6831 if (pipe == PIPE_A)
ab3c759a 6832 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6833 0x0df70000);
6834 else
ab3c759a 6835 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6836 0x0df40000);
6837 }
a0c4da24 6838
ab3c759a 6839 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6840 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6841 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6842 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6843 coreclk |= 0x01000000;
ab3c759a 6844 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6845
ab3c759a 6846 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6847 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6848}
6849
d288f65f 6850static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6851 struct intel_crtc_state *pipe_config)
1ae0d137 6852{
d288f65f 6853 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6854 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6855 DPLL_VCO_ENABLE;
6856 if (crtc->pipe != PIPE_A)
d288f65f 6857 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6858
d288f65f
VS		 6859 pipe_config->dpll_hw_state.dpll_md =
6860 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6861}
6862
d288f65f 6863static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6864 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6865{
6866 struct drm_device *dev = crtc->base.dev;
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868 int pipe = crtc->pipe;
6869 int dpll_reg = DPLL(crtc->pipe);
6870 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6871 u32 loopfilter, tribuf_calcntr;
9d556c99 6872 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6873 u32 dpio_val;
9cbe40c1 6874 int vco;
9d556c99 6875
d288f65f
VS		 6876 bestn = pipe_config->dpll.n;
6877 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6878 bestm1 = pipe_config->dpll.m1;
6879 bestm2 = pipe_config->dpll.m2 >> 22;
6880 bestp1 = pipe_config->dpll.p1;
6881 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6882 vco = pipe_config->dpll.vco;
a945ce7e 6883 dpio_val = 0;
9cbe40c1 6884 loopfilter = 0;
9d556c99
CML		 6885
6886 /*
6887 * Enable Refclk and SSC
6888 */
a11b0703 6889 I915_WRITE(dpll_reg,
d288f65f 6890 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6891
6892 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6893
9d556c99
CML		 6894 /* p1 and p2 divider */
6895 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6896 5 << DPIO_CHV_S1_DIV_SHIFT |
6897 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6898 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6899 1 << DPIO_CHV_K_DIV_SHIFT);
6900
6901 /* Feedback post-divider - m2 */
6902 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6903
6904 /* Feedback refclk divider - n and m1 */
6905 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6906 DPIO_CHV_M1_DIV_BY_2 |
6907 1 << DPIO_CHV_N_DIV_SHIFT);
6908
6909 /* M2 fraction division */
a945ce7e
VP		 6910 if (bestm2_frac)
6911 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6912
6913 /* M2 fraction division enable */
a945ce7e
VP		 6914 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6915 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6916 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6917 if (bestm2_frac)
6918 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6919 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6920
de3a0fde
VP		 6921 /* Program digital lock detect threshold */
6922 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6923 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6924 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6925 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6926 if (!bestm2_frac)
6927 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6928 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6929
9d556c99 6930 /* Loop filter */
9cbe40c1
VP		 6931 if (vco == 5400000) {
6932 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6933 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6934 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6935 tribuf_calcntr = 0x9;
6936 } else if (vco <= 6200000) {
6937 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6938 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6939 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6940 tribuf_calcntr = 0x9;
6941 } else if (vco <= 6480000) {
6942 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6943 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6944 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6945 tribuf_calcntr = 0x8;
6946 } else {
6947 /* Not supported. Apply the same limits as in the max case */
6948 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6949 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6950 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6951 tribuf_calcntr = 0;
6952 }
9d556c99
CML		 6953 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6954
968040b2 6955 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6956 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6957 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6958 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6959
9d556c99
CML		 6960 /* AFC Recal */
6961 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6962 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6963 DPIO_AFC_RECAL);
6964
6965 mutex_unlock(&dev_priv->dpio_lock);
6966}
6967
d288f65f
VS		 6968/**
6969 * vlv_force_pll_on - forcibly enable just the PLL
6970 * @dev_priv: i915 private structure
6971 * @pipe: pipe PLL to enable
6972 * @dpll: PLL configuration
6973 *
6974 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6975 * in cases where we need the PLL enabled even when @pipe is not going to
6976 * be enabled.
6977 */
6978void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6979 const struct dpll *dpll)
6980{
6981 struct intel_crtc *crtc =
6982 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6983 struct intel_crtc_state pipe_config = {
a93e255f 6984 .base.crtc = &crtc->base,
d288f65f
VS		 6985 .pixel_multiplier = 1,
6986 .dpll = *dpll,
6987 };
6988
6989 if (IS_CHERRYVIEW(dev)) {
6990 chv_update_pll(crtc, &pipe_config);
6991 chv_prepare_pll(crtc, &pipe_config);
6992 chv_enable_pll(crtc, &pipe_config);
6993 } else {
6994 vlv_update_pll(crtc, &pipe_config);
6995 vlv_prepare_pll(crtc, &pipe_config);
6996 vlv_enable_pll(crtc, &pipe_config);
6997 }
6998}
6999
7000/**
7001 * vlv_force_pll_off - forcibly disable just the PLL
7002 * @dev_priv: i915 private structure
7003 * @pipe: pipe PLL to disable
7004 *
7005 * Disable the PLL for @pipe. To be used in cases where we need
7006 * the PLL enabled even when @pipe is not going to be enabled.
7007 */
7008void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7009{
7010 if (IS_CHERRYVIEW(dev))
7011 chv_disable_pll(to_i915(dev), pipe);
7012 else
7013 vlv_disable_pll(to_i915(dev), pipe);
7014}
7015
f47709a9 7016static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7017 struct intel_crtc_state *crtc_state,
f47709a9 7018 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7019 int num_connectors)
7020{
f47709a9 7021 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7022 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7023 u32 dpll;
7024 bool is_sdvo;
190f68c5 7025 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7026
190f68c5 7027 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7028
a93e255f
ACO		 7029 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7030 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7031
7032 dpll = DPLL_VGA_MODE_DIS;
7033
a93e255f 7034 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7035 dpll |= DPLLB_MODE_LVDS;
7036 else
7037 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7038
ef1b460d 7039 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7040 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7041 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7042 }
198a037f
DV		 7043
7044 if (is_sdvo)
4a33e48d 7045 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7046
190f68c5 7047 if (crtc_state->has_dp_encoder)
4a33e48d 7048 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7049
7050 /* compute bitmask from p1 value */
7051 if (IS_PINEVIEW(dev))
7052 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7053 else {
7054 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7055 if (IS_G4X(dev) && reduced_clock)
7056 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7057 }
7058 switch (clock->p2) {
7059 case 5:
7060 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7061 break;
7062 case 7:
7063 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7064 break;
7065 case 10:
7066 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7067 break;
7068 case 14:
7069 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7070 break;
7071 }
7072 if (INTEL_INFO(dev)->gen >= 4)
7073 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7074
190f68c5 7075 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7076 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7077 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7078 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7079 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7080 else
7081 dpll |= PLL_REF_INPUT_DREFCLK;
7082
7083 dpll |= DPLL_VCO_ENABLE;
190f68c5 7084 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7085
eb1cbe48 7086 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7087 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7088 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7089 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7090 }
7091}
7092
f47709a9 7093static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7094 struct intel_crtc_state *crtc_state,
f47709a9 7095 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7096 int num_connectors)
7097{
f47709a9 7098 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7099 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7100 u32 dpll;
190f68c5 7101 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7102
190f68c5 7103 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7104
eb1cbe48
DV		 7105 dpll = DPLL_VGA_MODE_DIS;
7106
a93e255f 7107 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7108 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7109 } else {
7110 if (clock->p1 == 2)
7111 dpll |= PLL_P1_DIVIDE_BY_TWO;
7112 else
7113 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7114 if (clock->p2 == 4)
7115 dpll |= PLL_P2_DIVIDE_BY_4;
7116 }
7117
a93e255f 7118 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7119 dpll |= DPLL_DVO_2X_MODE;
7120
a93e255f 7121 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7122 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7123 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7124 else
7125 dpll |= PLL_REF_INPUT_DREFCLK;
7126
7127 dpll |= DPLL_VCO_ENABLE;
190f68c5 7128 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7129}
7130
8a654f3b 7131static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7132{
7133 struct drm_device *dev = intel_crtc->base.dev;
7134 struct drm_i915_private *dev_priv = dev->dev_private;
7135 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7136 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7137 struct drm_display_mode *adjusted_mode =
6e3c9717 7138 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7139 uint32_t crtc_vtotal, crtc_vblank_end;
7140 int vsyncshift = 0;
4d8a62ea
DV		 7141
7142 /* We need to be careful not to changed the adjusted mode, for otherwise
7143 * the hw state checker will get angry at the mismatch. */
7144 crtc_vtotal = adjusted_mode->crtc_vtotal;
7145 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7146
609aeaca 7147 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7148 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7149 crtc_vtotal -= 1;
7150 crtc_vblank_end -= 1;
609aeaca 7151
409ee761 7152 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7153 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7154 else
7155 vsyncshift = adjusted_mode->crtc_hsync_start -
7156 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7157 if (vsyncshift < 0)
7158 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7159 }
7160
7161 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7162 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7163
fe2b8f9d 7164 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7165 (adjusted_mode->crtc_hdisplay - 1) |
7166 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7167 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7168 (adjusted_mode->crtc_hblank_start - 1) |
7169 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7170 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7171 (adjusted_mode->crtc_hsync_start - 1) |
7172 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7173
fe2b8f9d 7174 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7175 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7176 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7177 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7178 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7179 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7180 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7181 (adjusted_mode->crtc_vsync_start - 1) |
7182 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7183
b5e508d4
PZ		 7184 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7185 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7186 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7187 * bits. */
7188 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7189 (pipe == PIPE_B || pipe == PIPE_C))
7190 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7191
b0e77b9c
PZ		 7192 /* pipesrc controls the size that is scaled from, which should
7193 * always be the user's requested size.
7194 */
7195 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7196 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7197 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7198}
7199
1bd1bd80 7200static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7201 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7202{
7203 struct drm_device *dev = crtc->base.dev;
7204 struct drm_i915_private *dev_priv = dev->dev_private;
7205 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7206 uint32_t tmp;
7207
7208 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7209 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7210 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7211 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7212 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7213 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7214 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7215 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7216 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7217
7218 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7219 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7220 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7221 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7222 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7223 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7224 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7225 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7226 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7227
7228 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7229 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7230 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7231 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7232 }
7233
7234 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7235 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7236 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7237
2d112de7
ACO		 7238 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7239 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7240}
7241
f6a83288 7242void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7243 struct intel_crtc_state *pipe_config)
babea61d 7244{
2d112de7
ACO		 7245 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7246 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7247 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7248 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7249
2d112de7
ACO		 7250 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7251 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7252 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7253 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7254
2d112de7 7255 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7256
2d112de7
ACO		 7257 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7258 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7259}
7260
84b046f3
DV		 7261static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7262{
7263 struct drm_device *dev = intel_crtc->base.dev;
7264 struct drm_i915_private *dev_priv = dev->dev_private;
7265 uint32_t pipeconf;
7266
9f11a9e4 7267 pipeconf = 0;
84b046f3 7268
b6b5d049
VS		 7269 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7270 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7271 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7272
6e3c9717 7273 if (intel_crtc->config->double_wide)
cf532bb2 7274 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7275
ff9ce46e
DV		 7276 /* only g4x and later have fancy bpc/dither controls */
7277 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7278 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7279 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7280 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7281 PIPECONF_DITHER_TYPE_SP;
84b046f3 7282
6e3c9717 7283 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7284 case 18:
7285 pipeconf |= PIPECONF_6BPC;
7286 break;
7287 case 24:
7288 pipeconf |= PIPECONF_8BPC;
7289 break;
7290 case 30:
7291 pipeconf |= PIPECONF_10BPC;
7292 break;
7293 default:
7294 /* Case prevented by intel_choose_pipe_bpp_dither. */
7295 BUG();
84b046f3
DV		 7296 }
7297 }
7298
7299 if (HAS_PIPE_CXSR(dev)) {
7300 if (intel_crtc->lowfreq_avail) {
7301 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7302 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7303 } else {
7304 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7305 }
7306 }
7307
6e3c9717 7308 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7309 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7310 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7311 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7312 else
7313 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7314 } else
84b046f3
DV		 7315 pipeconf |= PIPECONF_PROGRESSIVE;
7316
6e3c9717 7317 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7318 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7319
84b046f3
DV		 7320 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7321 POSTING_READ(PIPECONF(intel_crtc->pipe));
7322}
7323
190f68c5
ACO		 7324static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7325 struct intel_crtc_state *crtc_state)
79e53945 7326{
c7653199 7327 struct drm_device *dev = crtc->base.dev;
79e53945 7328 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7329 int refclk, num_connectors = 0;
652c393a 7330 intel_clock_t clock, reduced_clock;
a16af721 7331 bool ok, has_reduced_clock = false;
e9fd1c02 7332 bool is_lvds = false, is_dsi = false;
5eddb70b 7333 struct intel_encoder *encoder;
d4906093 7334 const intel_limit_t *limit;
55bb9992
ACO		 7335 struct drm_atomic_state *state = crtc_state->base.state;
7336 struct drm_connector_state *connector_state;
7337 int i;
79e53945 7338
55bb9992
ACO		 7339 for (i = 0; i < state->num_connector; i++) {
7340 if (!state->connectors[i])
d0737e1d
ACO		 7341 continue;
7342
55bb9992
ACO		 7343 connector_state = state->connector_states[i];
7344 if (connector_state->crtc != &crtc->base)
7345 continue;
7346
7347 encoder = to_intel_encoder(connector_state->best_encoder);
7348
5eddb70b 7349 switch (encoder->type) {
79e53945
JB		 7350 case INTEL_OUTPUT_LVDS:
7351 is_lvds = true;
7352 break;
e9fd1c02
JN		 7353 case INTEL_OUTPUT_DSI:
7354 is_dsi = true;
7355 break;
6847d71b
PZ		 7356 default:
7357 break;
79e53945 7358 }
43565a06 7359
c751ce4f 7360 num_connectors++;
79e53945
JB		 7361 }
7362
f2335330 7363 if (is_dsi)
5b18e57c 7364 return 0;
f2335330 7365
190f68c5 7366 if (!crtc_state->clock_set) {
a93e255f 7367 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7368
e9fd1c02
JN		 7369 /*
7370 * Returns a set of divisors for the desired target clock with
7371 * the given refclk, or FALSE. The returned values represent
7372 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7373 * 2) / p1 / p2.
7374 */
a93e255f
ACO		 7375 limit = intel_limit(crtc_state, refclk);
7376 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7377 crtc_state->port_clock,
e9fd1c02 7378 refclk, NULL, &clock);
f2335330 7379 if (!ok) {
e9fd1c02
JN		 7380 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7381 return -EINVAL;
7382 }
79e53945 7383
f2335330
JN		 7384 if (is_lvds && dev_priv->lvds_downclock_avail) {
7385 /*
7386 * Ensure we match the reduced clock's P to the target
7387 * clock. If the clocks don't match, we can't switch
7388 * the display clock by using the FP0/FP1. In such case
7389 * we will disable the LVDS downclock feature.
7390 */
7391 has_reduced_clock =
a93e255f 7392 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7393 dev_priv->lvds_downclock,
7394 refclk, &clock,
7395 &reduced_clock);
7396 }
7397 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7398 crtc_state->dpll.n = clock.n;
7399 crtc_state->dpll.m1 = clock.m1;
7400 crtc_state->dpll.m2 = clock.m2;
7401 crtc_state->dpll.p1 = clock.p1;
7402 crtc_state->dpll.p2 = clock.p2;
f47709a9 7403 }
7026d4ac 7404
e9fd1c02 7405 if (IS_GEN2(dev)) {
190f68c5 7406 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7407 has_reduced_clock ? &reduced_clock : NULL,
7408 num_connectors);
9d556c99 7409 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7410 chv_update_pll(crtc, crtc_state);
e9fd1c02 7411 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7412 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7413 } else {
190f68c5 7414 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7415 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7416 num_connectors);
e9fd1c02 7417 }
79e53945 7418
c8f7a0db 7419 return 0;
f564048e
EA		 7420}
7421
2fa2fe9a 7422static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7423 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7424{
7425 struct drm_device *dev = crtc->base.dev;
7426 struct drm_i915_private *dev_priv = dev->dev_private;
7427 uint32_t tmp;
7428
dc9e7dec
VS		 7429 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7430 return;
7431
2fa2fe9a 7432 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7433 if (!(tmp & PFIT_ENABLE))
7434 return;
2fa2fe9a 7435
06922821 7436 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7437 if (INTEL_INFO(dev)->gen < 4) {
7438 if (crtc->pipe != PIPE_B)
7439 return;
2fa2fe9a
DV		 7440 } else {
7441 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7442 return;
7443 }
7444
06922821 7445 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7446 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7447 if (INTEL_INFO(dev)->gen < 5)
7448 pipe_config->gmch_pfit.lvds_border_bits =
7449 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7450}
7451
acbec814 7452static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7453 struct intel_crtc_state *pipe_config)
acbec814
JB		 7454{
7455 struct drm_device *dev = crtc->base.dev;
7456 struct drm_i915_private *dev_priv = dev->dev_private;
7457 int pipe = pipe_config->cpu_transcoder;
7458 intel_clock_t clock;
7459 u32 mdiv;
662c6ecb 7460 int refclk = 100000;
acbec814 7461
f573de5a
SK		 7462 /* In case of MIPI DPLL will not even be used */
7463 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7464 return;
7465
acbec814 7466 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7467 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7468 mutex_unlock(&dev_priv->dpio_lock);
7469
7470 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7471 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7472 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7473 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7474 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7475
f646628b 7476 vlv_clock(refclk, &clock);
acbec814 7477
f646628b
VS		 7478 /* clock.dot is the fast clock */
7479 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7480}
7481
5724dbd1
DL		 7482static void
7483i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7484 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7485{
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 u32 val, base, offset;
7489 int pipe = crtc->pipe, plane = crtc->plane;
7490 int fourcc, pixel_format;
6761dd31 7491 unsigned int aligned_height;
b113d5ee 7492 struct drm_framebuffer *fb;
1b842c89 7493 struct intel_framebuffer *intel_fb;
1ad292b5 7494
42a7b088
DL		 7495 val = I915_READ(DSPCNTR(plane));
7496 if (!(val & DISPLAY_PLANE_ENABLE))
7497 return;
7498
d9806c9f 7499 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7500 if (!intel_fb) {
1ad292b5
JB		 7501 DRM_DEBUG_KMS("failed to alloc fb\n");
7502 return;
7503 }
7504
1b842c89
DL		 7505 fb = &intel_fb->base;
7506
18c5247e
DV		 7507 if (INTEL_INFO(dev)->gen >= 4) {
7508 if (val & DISPPLANE_TILED) {
49af449b 7509 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7510 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7511 }
7512 }
1ad292b5
JB		 7513
7514 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7515 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7516 fb->pixel_format = fourcc;
7517 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7518
7519 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7520 if (plane_config->tiling)
1ad292b5
JB		 7521 offset = I915_READ(DSPTILEOFF(plane));
7522 else
7523 offset = I915_READ(DSPLINOFF(plane));
7524 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7525 } else {
7526 base = I915_READ(DSPADDR(plane));
7527 }
7528 plane_config->base = base;
7529
7530 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7531 fb->width = ((val >> 16) & 0xfff) + 1;
7532 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7533
7534 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7535 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7536
b113d5ee 7537 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7538 fb->pixel_format,
7539 fb->modifier[0]);
1ad292b5 7540
f37b5c2b 7541 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7542
2844a921
DL		 7543 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7544 pipe_name(pipe), plane, fb->width, fb->height,
7545 fb->bits_per_pixel, base, fb->pitches[0],
7546 plane_config->size);
1ad292b5 7547
2d14030b 7548 plane_config->fb = intel_fb;
1ad292b5
JB		 7549}
7550
70b23a98 7551static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7552 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7553{
7554 struct drm_device *dev = crtc->base.dev;
7555 struct drm_i915_private *dev_priv = dev->dev_private;
7556 int pipe = pipe_config->cpu_transcoder;
7557 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7558 intel_clock_t clock;
7559 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7560 int refclk = 100000;
7561
7562 mutex_lock(&dev_priv->dpio_lock);
7563 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7564 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7565 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7566 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7567 mutex_unlock(&dev_priv->dpio_lock);
7568
7569 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7570 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7571 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7572 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7573 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7574
7575 chv_clock(refclk, &clock);
7576
7577 /* clock.dot is the fast clock */
7578 pipe_config->port_clock = clock.dot / 5;
7579}
7580
0e8ffe1b 7581static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7582 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7583{
7584 struct drm_device *dev = crtc->base.dev;
7585 struct drm_i915_private *dev_priv = dev->dev_private;
7586 uint32_t tmp;
7587
f458ebbc
DV		 7588 if (!intel_display_power_is_enabled(dev_priv,
7589 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7590 return false;
7591
e143a21c 7592 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7593 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7594
0e8ffe1b
DV		 7595 tmp = I915_READ(PIPECONF(crtc->pipe));
7596 if (!(tmp & PIPECONF_ENABLE))
7597 return false;
7598
42571aef
VS		 7599 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7600 switch (tmp & PIPECONF_BPC_MASK) {
7601 case PIPECONF_6BPC:
7602 pipe_config->pipe_bpp = 18;
7603 break;
7604 case PIPECONF_8BPC:
7605 pipe_config->pipe_bpp = 24;
7606 break;
7607 case PIPECONF_10BPC:
7608 pipe_config->pipe_bpp = 30;
7609 break;
7610 default:
7611 break;
7612 }
7613 }
7614
b5a9fa09
DV		 7615 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7616 pipe_config->limited_color_range = true;
7617
282740f7
VS		 7618 if (INTEL_INFO(dev)->gen < 4)
7619 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7620
1bd1bd80
DV		 7621 intel_get_pipe_timings(crtc, pipe_config);
7622
2fa2fe9a
DV		 7623 i9xx_get_pfit_config(crtc, pipe_config);
7624
6c49f241
DV		 7625 if (INTEL_INFO(dev)->gen >= 4) {
7626 tmp = I915_READ(DPLL_MD(crtc->pipe));
7627 pipe_config->pixel_multiplier =
7628 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7629 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7630 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7631 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7632 tmp = I915_READ(DPLL(crtc->pipe));
7633 pipe_config->pixel_multiplier =
7634 ((tmp & SDVO_MULTIPLIER_MASK)
7635 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7636 } else {
7637 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7638 * port and will be fixed up in the encoder->get_config
7639 * function. */
7640 pipe_config->pixel_multiplier = 1;
7641 }
8bcc2795
DV		 7642 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7643 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7644 /*
7645 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7646 * on 830. Filter it out here so that we don't
7647 * report errors due to that.
7648 */
7649 if (IS_I830(dev))
7650 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7651
8bcc2795
DV		 7652 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7653 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7654 } else {
7655 /* Mask out read-only status bits. */
7656 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7657 DPLL_PORTC_READY_MASK |
7658 DPLL_PORTB_READY_MASK);
8bcc2795 7659 }
6c49f241 7660
70b23a98
VS		 7661 if (IS_CHERRYVIEW(dev))
7662 chv_crtc_clock_get(crtc, pipe_config);
7663 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7664 vlv_crtc_clock_get(crtc, pipe_config);
7665 else
7666 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7667
0e8ffe1b
DV		 7668 return true;
7669}
7670
dde86e2d 7671static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7672{
7673 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7674 struct intel_encoder *encoder;
74cfd7ac 7675 u32 val, final;
13d83a67 7676 bool has_lvds = false;
199e5d79 7677 bool has_cpu_edp = false;
199e5d79 7678 bool has_panel = false;
99eb6a01
KP		 7679 bool has_ck505 = false;
7680 bool can_ssc = false;
13d83a67
JB		 7681
7682 /* We need to take the global config into account */
b2784e15 7683 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7684 switch (encoder->type) {
7685 case INTEL_OUTPUT_LVDS:
7686 has_panel = true;
7687 has_lvds = true;
7688 break;
7689 case INTEL_OUTPUT_EDP:
7690 has_panel = true;
2de6905f 7691 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7692 has_cpu_edp = true;
7693 break;
6847d71b
PZ		 7694 default:
7695 break;
13d83a67
JB		 7696 }
7697 }
7698
99eb6a01 7699 if (HAS_PCH_IBX(dev)) {
41aa3448 7700 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7701 can_ssc = has_ck505;
7702 } else {
7703 has_ck505 = false;
7704 can_ssc = true;
7705 }
7706
2de6905f
ID		 7707 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7708 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7709
7710 /* Ironlake: try to setup display ref clock before DPLL
7711 * enabling. This is only under driver's control after
7712 * PCH B stepping, previous chipset stepping should be
7713 * ignoring this setting.
7714 */
74cfd7ac
CW		 7715 val = I915_READ(PCH_DREF_CONTROL);
7716
7717 /* As we must carefully and slowly disable/enable each source in turn,
7718 * compute the final state we want first and check if we need to
7719 * make any changes at all.
7720 */
7721 final = val;
7722 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7723 if (has_ck505)
7724 final |= DREF_NONSPREAD_CK505_ENABLE;
7725 else
7726 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7727
7728 final &= ~DREF_SSC_SOURCE_MASK;
7729 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7730 final &= ~DREF_SSC1_ENABLE;
7731
7732 if (has_panel) {
7733 final |= DREF_SSC_SOURCE_ENABLE;
7734
7735 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7736 final |= DREF_SSC1_ENABLE;
7737
7738 if (has_cpu_edp) {
7739 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7740 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7741 else
7742 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7743 } else
7744 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7745 } else {
7746 final |= DREF_SSC_SOURCE_DISABLE;
7747 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7748 }
7749
7750 if (final == val)
7751 return;
7752
13d83a67 7753 /* Always enable nonspread source */
74cfd7ac 7754 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7755
99eb6a01 7756 if (has_ck505)
74cfd7ac 7757 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7758 else
74cfd7ac 7759 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7760
199e5d79 7761 if (has_panel) {
74cfd7ac
CW		 7762 val &= ~DREF_SSC_SOURCE_MASK;
7763 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7764
199e5d79 7765 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7766 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7767 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7768 val |= DREF_SSC1_ENABLE;
e77166b5 7769 } else
74cfd7ac 7770 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7771
7772 /* Get SSC going before enabling the outputs */
74cfd7ac 7773 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7774 POSTING_READ(PCH_DREF_CONTROL);
7775 udelay(200);
7776
74cfd7ac 7777 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7778
7779 /* Enable CPU source on CPU attached eDP */
199e5d79 7780 if (has_cpu_edp) {
99eb6a01 7781 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7782 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7783 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7784 } else
74cfd7ac 7785 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7786 } else
74cfd7ac 7787 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7788
74cfd7ac 7789 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7790 POSTING_READ(PCH_DREF_CONTROL);
7791 udelay(200);
7792 } else {
7793 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7794
74cfd7ac 7795 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7796
7797 /* Turn off CPU output */
74cfd7ac 7798 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7799
74cfd7ac 7800 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7801 POSTING_READ(PCH_DREF_CONTROL);
7802 udelay(200);
7803
7804 /* Turn off the SSC source */
74cfd7ac
CW		 7805 val &= ~DREF_SSC_SOURCE_MASK;
7806 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7807
7808 /* Turn off SSC1 */
74cfd7ac 7809 val &= ~DREF_SSC1_ENABLE;
199e5d79 7810
74cfd7ac 7811 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7812 POSTING_READ(PCH_DREF_CONTROL);
7813 udelay(200);
7814 }
74cfd7ac
CW		 7815
7816 BUG_ON(val != final);
13d83a67
JB		 7817}
7818
f31f2d55 7819static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7820{
f31f2d55 7821 uint32_t tmp;
dde86e2d 7822
0ff066a9
PZ		 7823 tmp = I915_READ(SOUTH_CHICKEN2);
7824 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7825 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7826
0ff066a9
PZ		 7827 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7828 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7829 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7830
0ff066a9
PZ		 7831 tmp = I915_READ(SOUTH_CHICKEN2);
7832 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7833 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7834
0ff066a9
PZ		 7835 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7836 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7837 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7838}
7839
7840/* WaMPhyProgramming:hsw */
7841static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7842{
7843 uint32_t tmp;
dde86e2d
PZ		 7844
7845 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7846 tmp &= ~(0xFF << 24);
7847 tmp |= (0x12 << 24);
7848 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7849
dde86e2d
PZ		 7850 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7851 tmp |= (1 << 11);
7852 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7853
7854 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7855 tmp |= (1 << 11);
7856 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7857
dde86e2d
PZ		 7858 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7859 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7860 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7861
7862 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7863 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7864 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7865
0ff066a9
PZ		 7866 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7867 tmp &= ~(7 << 13);
7868 tmp |= (5 << 13);
7869 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7870
0ff066a9
PZ		 7871 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7872 tmp &= ~(7 << 13);
7873 tmp |= (5 << 13);
7874 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7875
7876 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7877 tmp &= ~0xFF;
7878 tmp |= 0x1C;
7879 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7880
7881 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7882 tmp &= ~0xFF;
7883 tmp |= 0x1C;
7884 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7885
7886 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7887 tmp &= ~(0xFF << 16);
7888 tmp |= (0x1C << 16);
7889 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7890
7891 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7892 tmp &= ~(0xFF << 16);
7893 tmp |= (0x1C << 16);
7894 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7895
0ff066a9
PZ		 7896 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7897 tmp |= (1 << 27);
7898 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7899
0ff066a9
PZ		 7900 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7901 tmp |= (1 << 27);
7902 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7903
0ff066a9
PZ		 7904 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7905 tmp &= ~(0xF << 28);
7906 tmp |= (4 << 28);
7907 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7908
0ff066a9
PZ		 7909 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7910 tmp &= ~(0xF << 28);
7911 tmp |= (4 << 28);
7912 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7913}
7914
2fa86a1f
PZ		 7915/* Implements 3 different sequences from BSpec chapter "Display iCLK
7916 * Programming" based on the parameters passed:
7917 * - Sequence to enable CLKOUT_DP
7918 * - Sequence to enable CLKOUT_DP without spread
7919 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7920 */
7921static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7922 bool with_fdi)
f31f2d55
PZ		 7923{
7924 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7925 uint32_t reg, tmp;
7926
7927 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7928 with_spread = true;
7929 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7930 with_fdi, "LP PCH doesn't have FDI\n"))
7931 with_fdi = false;
f31f2d55
PZ		 7932
7933 mutex_lock(&dev_priv->dpio_lock);
7934
7935 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7936 tmp &= ~SBI_SSCCTL_DISABLE;
7937 tmp |= SBI_SSCCTL_PATHALT;
7938 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7939
7940 udelay(24);
7941
2fa86a1f
PZ		 7942 if (with_spread) {
7943 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7944 tmp &= ~SBI_SSCCTL_PATHALT;
7945 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7946
2fa86a1f
PZ		 7947 if (with_fdi) {
7948 lpt_reset_fdi_mphy(dev_priv);
7949 lpt_program_fdi_mphy(dev_priv);
7950 }
7951 }
dde86e2d 7952
2fa86a1f
PZ		 7953 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7954 SBI_GEN0 : SBI_DBUFF0;
7955 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7956 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7957 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7958
7959 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7960}
7961
47701c3b
PZ		 7962/* Sequence to disable CLKOUT_DP */
7963static void lpt_disable_clkout_dp(struct drm_device *dev)
7964{
7965 struct drm_i915_private *dev_priv = dev->dev_private;
7966 uint32_t reg, tmp;
7967
7968 mutex_lock(&dev_priv->dpio_lock);
7969
7970 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7971 SBI_GEN0 : SBI_DBUFF0;
7972 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7973 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7974 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7975
7976 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7977 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7978 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7979 tmp |= SBI_SSCCTL_PATHALT;
7980 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7981 udelay(32);
7982 }
7983 tmp |= SBI_SSCCTL_DISABLE;
7984 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7985 }
7986
7987 mutex_unlock(&dev_priv->dpio_lock);
7988}
7989
bf8fa3d3
PZ		 7990static void lpt_init_pch_refclk(struct drm_device *dev)
7991{
bf8fa3d3
PZ		 7992 struct intel_encoder *encoder;
7993 bool has_vga = false;
7994
b2784e15 7995 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7996 switch (encoder->type) {
7997 case INTEL_OUTPUT_ANALOG:
7998 has_vga = true;
7999 break;
6847d71b
PZ		 8000 default:
8001 break;
bf8fa3d3
PZ		 8002 }
8003 }
8004
47701c3b
PZ		 8005 if (has_vga)
8006 lpt_enable_clkout_dp(dev, true, true);
8007 else
8008 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8009}
8010
dde86e2d
PZ		 8011/*
8012 * Initialize reference clocks when the driver loads
8013 */
8014void intel_init_pch_refclk(struct drm_device *dev)
8015{
8016 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8017 ironlake_init_pch_refclk(dev);
8018 else if (HAS_PCH_LPT(dev))
8019 lpt_init_pch_refclk(dev);
8020}
8021
55bb9992 8022static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8023{
55bb9992 8024 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8025 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8026 struct drm_atomic_state *state = crtc_state->base.state;
8027 struct drm_connector_state *connector_state;
d9d444cb 8028 struct intel_encoder *encoder;
55bb9992 8029 int num_connectors = 0, i;
d9d444cb
JB		 8030 bool is_lvds = false;
8031
55bb9992
ACO		 8032 for (i = 0; i < state->num_connector; i++) {
8033 if (!state->connectors[i])
d0737e1d
ACO		 8034 continue;
8035
55bb9992
ACO		 8036 connector_state = state->connector_states[i];
8037 if (connector_state->crtc != crtc_state->base.crtc)
8038 continue;
8039
8040 encoder = to_intel_encoder(connector_state->best_encoder);
8041
d9d444cb
JB		 8042 switch (encoder->type) {
8043 case INTEL_OUTPUT_LVDS:
8044 is_lvds = true;
8045 break;
6847d71b
PZ		 8046 default:
8047 break;
d9d444cb
JB		 8048 }
8049 num_connectors++;
8050 }
8051
8052 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8053 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8054 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8055 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8056 }
8057
8058 return 120000;
8059}
8060
6ff93609 8061static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8062{
c8203565 8063 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8065 int pipe = intel_crtc->pipe;
c8203565
PZ		 8066 uint32_t val;
8067
78114071 8068 val = 0;
c8203565 8069
6e3c9717 8070 switch (intel_crtc->config->pipe_bpp) {
c8203565 8071 case 18:
dfd07d72 8072 val |= PIPECONF_6BPC;
c8203565
PZ		 8073 break;
8074 case 24:
dfd07d72 8075 val |= PIPECONF_8BPC;
c8203565
PZ		 8076 break;
8077 case 30:
dfd07d72 8078 val |= PIPECONF_10BPC;
c8203565
PZ		 8079 break;
8080 case 36:
dfd07d72 8081 val |= PIPECONF_12BPC;
c8203565
PZ		 8082 break;
8083 default:
cc769b62
PZ		 8084 /* Case prevented by intel_choose_pipe_bpp_dither. */
8085 BUG();
c8203565
PZ		 8086 }
8087
6e3c9717 8088 if (intel_crtc->config->dither)
c8203565
PZ		 8089 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8090
6e3c9717 8091 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8092 val |= PIPECONF_INTERLACED_ILK;
8093 else
8094 val |= PIPECONF_PROGRESSIVE;
8095
6e3c9717 8096 if (intel_crtc->config->limited_color_range)
3685a8f3 8097 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8098
c8203565
PZ		 8099 I915_WRITE(PIPECONF(pipe), val);
8100 POSTING_READ(PIPECONF(pipe));
8101}
8102
86d3efce
VS		 8103/*
8104 * Set up the pipe CSC unit.
8105 *
8106 * Currently only full range RGB to limited range RGB conversion
8107 * is supported, but eventually this should handle various
8108 * RGB<->YCbCr scenarios as well.
8109 */
50f3b016 8110static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8111{
8112 struct drm_device *dev = crtc->dev;
8113 struct drm_i915_private *dev_priv = dev->dev_private;
8114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8115 int pipe = intel_crtc->pipe;
8116 uint16_t coeff = 0x7800; /* 1.0 */
8117
8118 /*
8119 * TODO: Check what kind of values actually come out of the pipe
8120 * with these coeff/postoff values and adjust to get the best
8121 * accuracy. Perhaps we even need to take the bpc value into
8122 * consideration.
8123 */
8124
6e3c9717 8125 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8126 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8127
8128 /*
8129 * GY/GU and RY/RU should be the other way around according
8130 * to BSpec, but reality doesn't agree. Just set them up in
8131 * a way that results in the correct picture.
8132 */
8133 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8134 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8135
8136 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8137 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8138
8139 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8140 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8141
8142 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8143 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8144 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8145
8146 if (INTEL_INFO(dev)->gen > 6) {
8147 uint16_t postoff = 0;
8148
6e3c9717 8149 if (intel_crtc->config->limited_color_range)
32cf0cb0 8150 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8151
8152 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8153 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8154 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8155
8156 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8157 } else {
8158 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8159
6e3c9717 8160 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8161 mode |= CSC_BLACK_SCREEN_OFFSET;
8162
8163 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8164 }
8165}
8166
6ff93609 8167static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8168{
756f85cf
PZ		 8169 struct drm_device *dev = crtc->dev;
8170 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8172 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8173 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8174 uint32_t val;
8175
3eff4faa 8176 val = 0;
ee2b0b38 8177
6e3c9717 8178 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8179 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8180
6e3c9717 8181 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8182 val |= PIPECONF_INTERLACED_ILK;
8183 else
8184 val |= PIPECONF_PROGRESSIVE;
8185
702e7a56
PZ		 8186 I915_WRITE(PIPECONF(cpu_transcoder), val);
8187 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8188
8189 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8190 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8191
3cdf122c 8192 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8193 val = 0;
8194
6e3c9717 8195 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8196 case 18:
8197 val |= PIPEMISC_DITHER_6_BPC;
8198 break;
8199 case 24:
8200 val |= PIPEMISC_DITHER_8_BPC;
8201 break;
8202 case 30:
8203 val |= PIPEMISC_DITHER_10_BPC;
8204 break;
8205 case 36:
8206 val |= PIPEMISC_DITHER_12_BPC;
8207 break;
8208 default:
8209 /* Case prevented by pipe_config_set_bpp. */
8210 BUG();
8211 }
8212
6e3c9717 8213 if (intel_crtc->config->dither)
756f85cf
PZ		 8214 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8215
8216 I915_WRITE(PIPEMISC(pipe), val);
8217 }
ee2b0b38
PZ		 8218}
8219
6591c6e4 8220static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8221 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8222 intel_clock_t *clock,
8223 bool *has_reduced_clock,
8224 intel_clock_t *reduced_clock)
8225{
8226 struct drm_device *dev = crtc->dev;
8227 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8228 int refclk;
d4906093 8229 const intel_limit_t *limit;
a16af721 8230 bool ret, is_lvds = false;
79e53945 8231
a93e255f 8232 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8233
55bb9992 8234 refclk = ironlake_get_refclk(crtc_state);
79e53945 8235
d4906093
ML		 8236 /*
8237 * Returns a set of divisors for the desired target clock with the given
8238 * refclk, or FALSE. The returned values represent the clock equation:
8239 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8240 */
a93e255f
ACO		 8241 limit = intel_limit(crtc_state, refclk);
8242 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8243 crtc_state->port_clock,
ee9300bb 8244 refclk, NULL, clock);
6591c6e4
PZ		 8245 if (!ret)
8246 return false;
cda4b7d3 8247
ddc9003c 8248 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8249 /*
8250 * Ensure we match the reduced clock's P to the target clock.
8251 * If the clocks don't match, we can't switch the display clock
8252 * by using the FP0/FP1. In such case we will disable the LVDS
8253 * downclock feature.
8254 */
ee9300bb 8255 *has_reduced_clock =
a93e255f 8256 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8257 dev_priv->lvds_downclock,
8258 refclk, clock,
8259 reduced_clock);
652c393a 8260 }
61e9653f 8261
6591c6e4
PZ		 8262 return true;
8263}
8264
d4b1931c
PZ		 8265int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8266{
8267 /*
8268 * Account for spread spectrum to avoid
8269 * oversubscribing the link. Max center spread
8270 * is 2.5%; use 5% for safety's sake.
8271 */
8272 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8273 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8274}
8275
7429e9d4 8276static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8277{
7429e9d4 8278 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8279}
8280
de13a2e3 8281static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8282 struct intel_crtc_state *crtc_state,
7429e9d4 8283 u32 *fp,
9a7c7890 8284 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8285{
de13a2e3 8286 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8287 struct drm_device *dev = crtc->dev;
8288 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8289 struct drm_atomic_state *state = crtc_state->base.state;
8290 struct drm_connector_state *connector_state;
8291 struct intel_encoder *encoder;
de13a2e3 8292 uint32_t dpll;
55bb9992 8293 int factor, num_connectors = 0, i;
09ede541 8294 bool is_lvds = false, is_sdvo = false;
79e53945 8295
55bb9992
ACO		 8296 for (i = 0; i < state->num_connector; i++) {
8297 if (!state->connectors[i])
d0737e1d
ACO		 8298 continue;
8299
55bb9992
ACO		 8300 connector_state = state->connector_states[i];
8301 if (connector_state->crtc != crtc_state->base.crtc)
8302 continue;
8303
8304 encoder = to_intel_encoder(connector_state->best_encoder);
8305
8306 switch (encoder->type) {
79e53945
JB		 8307 case INTEL_OUTPUT_LVDS:
8308 is_lvds = true;
8309 break;
8310 case INTEL_OUTPUT_SDVO:
7d57382e 8311 case INTEL_OUTPUT_HDMI:
79e53945 8312 is_sdvo = true;
79e53945 8313 break;
6847d71b
PZ		 8314 default:
8315 break;
79e53945 8316 }
43565a06 8317
c751ce4f 8318 num_connectors++;
79e53945 8319 }
79e53945 8320
c1858123 8321 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8322 factor = 21;
8323 if (is_lvds) {
8324 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8325 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8326 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8327 factor = 25;
190f68c5 8328 } else if (crtc_state->sdvo_tv_clock)
8febb297 8329 factor = 20;
c1858123 8330
190f68c5 8331 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8332 *fp |= FP_CB_TUNE;
2c07245f 8333
9a7c7890
DV		 8334 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8335 *fp2 |= FP_CB_TUNE;
8336
5eddb70b 8337 dpll = 0;
2c07245f 8338
a07d6787
EA		 8339 if (is_lvds)
8340 dpll |= DPLLB_MODE_LVDS;
8341 else
8342 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8343
190f68c5 8344 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8345 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8346
8347 if (is_sdvo)
4a33e48d 8348 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8349 if (crtc_state->has_dp_encoder)
4a33e48d 8350 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8351
a07d6787 8352 /* compute bitmask from p1 value */
190f68c5 8353 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8354 /* also FPA1 */
190f68c5 8355 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8356
190f68c5 8357 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8358 case 5:
8359 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8360 break;
8361 case 7:
8362 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8363 break;
8364 case 10:
8365 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8366 break;
8367 case 14:
8368 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8369 break;
79e53945
JB		 8370 }
8371
b4c09f3b 8372 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8373 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8374 else
8375 dpll |= PLL_REF_INPUT_DREFCLK;
8376
959e16d6 8377 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8378}
8379
190f68c5
ACO		 8380static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8381 struct intel_crtc_state *crtc_state)
de13a2e3 8382{
c7653199 8383 struct drm_device *dev = crtc->base.dev;
de13a2e3 8384 intel_clock_t clock, reduced_clock;
cbbab5bd 8385 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8386 bool ok, has_reduced_clock = false;
8b47047b 8387 bool is_lvds = false;
e2b78267 8388 struct intel_shared_dpll *pll;
de13a2e3 8389
409ee761 8390 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8391
5dc5298b
PZ		 8392 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8393 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8394
190f68c5 8395 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8396 &has_reduced_clock, &reduced_clock);
190f68c5 8397 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8398 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8399 return -EINVAL;
79e53945 8400 }
f47709a9 8401 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8402 if (!crtc_state->clock_set) {
8403 crtc_state->dpll.n = clock.n;
8404 crtc_state->dpll.m1 = clock.m1;
8405 crtc_state->dpll.m2 = clock.m2;
8406 crtc_state->dpll.p1 = clock.p1;
8407 crtc_state->dpll.p2 = clock.p2;
f47709a9 8408 }
79e53945 8409
5dc5298b 8410 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8411 if (crtc_state->has_pch_encoder) {
8412 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8413 if (has_reduced_clock)
7429e9d4 8414 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8415
190f68c5 8416 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8417 &fp, &reduced_clock,
8418 has_reduced_clock ? &fp2 : NULL);
8419
190f68c5
ACO		 8420 crtc_state->dpll_hw_state.dpll = dpll;
8421 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8422 if (has_reduced_clock)
190f68c5 8423 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8424 else
190f68c5 8425 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8426
190f68c5 8427 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8428 if (pll == NULL) {
84f44ce7 8429 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8430 pipe_name(crtc->pipe));
4b645f14
JB		 8431 return -EINVAL;
8432 }
3fb37703 8433 }
79e53945 8434
ab585dea 8435 if (is_lvds && has_reduced_clock)
c7653199 8436 crtc->lowfreq_avail = true;
bcd644e0 8437 else
c7653199 8438 crtc->lowfreq_avail = false;
e2b78267 8439
c8f7a0db 8440 return 0;
79e53945
JB		 8441}
8442
eb14cb74
VS		 8443static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8444 struct intel_link_m_n *m_n)
8445{
8446 struct drm_device *dev = crtc->base.dev;
8447 struct drm_i915_private *dev_priv = dev->dev_private;
8448 enum pipe pipe = crtc->pipe;
8449
8450 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8451 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8452 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8453 & ~TU_SIZE_MASK;
8454 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8455 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8456 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8457}
8458
8459static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8460 enum transcoder transcoder,
b95af8be
VK		 8461 struct intel_link_m_n *m_n,
8462 struct intel_link_m_n *m2_n2)
72419203
DV		 8463{
8464 struct drm_device *dev = crtc->base.dev;
8465 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8466 enum pipe pipe = crtc->pipe;
72419203 8467
eb14cb74
VS		 8468 if (INTEL_INFO(dev)->gen >= 5) {
8469 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8470 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8471 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8472 & ~TU_SIZE_MASK;
8473 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8474 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8475 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8476 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8477 * gen < 8) and if DRRS is supported (to make sure the
8478 * registers are not unnecessarily read).
8479 */
8480 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8481 crtc->config->has_drrs) {
b95af8be
VK		 8482 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8483 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8484 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8485 & ~TU_SIZE_MASK;
8486 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8487 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8488 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8489 }
eb14cb74
VS		 8490 } else {
8491 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8492 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8493 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8494 & ~TU_SIZE_MASK;
8495 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8496 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8497 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8498 }
8499}
8500
8501void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8502 struct intel_crtc_state *pipe_config)
eb14cb74 8503{
681a8504 8504 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8505 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8506 else
8507 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8508 &pipe_config->dp_m_n,
8509 &pipe_config->dp_m2_n2);
eb14cb74 8510}
72419203 8511
eb14cb74 8512static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8513 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8514{
8515 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8516 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8517}
8518
bd2e244f 8519static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8520 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8521{
8522 struct drm_device *dev = crtc->base.dev;
8523 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8524 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8525 uint32_t ps_ctrl = 0;
8526 int id = -1;
8527 int i;
bd2e244f 8528
a1b2278e
CK		 8529 /* find scaler attached to this pipe */
8530 for (i = 0; i < crtc->num_scalers; i++) {
8531 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8532 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8533 id = i;
8534 pipe_config->pch_pfit.enabled = true;
8535 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8536 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8537 break;
8538 }
8539 }
bd2e244f 8540
a1b2278e
CK		 8541 scaler_state->scaler_id = id;
8542 if (id >= 0) {
8543 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8544 } else {
8545 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8546 }
8547}
8548
5724dbd1
DL		 8549static void
8550skylake_get_initial_plane_config(struct intel_crtc *crtc,
8551 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8552{
8553 struct drm_device *dev = crtc->base.dev;
8554 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8555 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8556 int pipe = crtc->pipe;
8557 int fourcc, pixel_format;
6761dd31 8558 unsigned int aligned_height;
bc8d7dff 8559 struct drm_framebuffer *fb;
1b842c89 8560 struct intel_framebuffer *intel_fb;
bc8d7dff 8561
d9806c9f 8562 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8563 if (!intel_fb) {
bc8d7dff
DL		 8564 DRM_DEBUG_KMS("failed to alloc fb\n");
8565 return;
8566 }
8567
1b842c89
DL		 8568 fb = &intel_fb->base;
8569
bc8d7dff 8570 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8571 if (!(val & PLANE_CTL_ENABLE))
8572 goto error;
8573
bc8d7dff
DL		 8574 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8575 fourcc = skl_format_to_fourcc(pixel_format,
8576 val & PLANE_CTL_ORDER_RGBX,
8577 val & PLANE_CTL_ALPHA_MASK);
8578 fb->pixel_format = fourcc;
8579 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8580
40f46283
DL		 8581 tiling = val & PLANE_CTL_TILED_MASK;
8582 switch (tiling) {
8583 case PLANE_CTL_TILED_LINEAR:
8584 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8585 break;
8586 case PLANE_CTL_TILED_X:
8587 plane_config->tiling = I915_TILING_X;
8588 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8589 break;
8590 case PLANE_CTL_TILED_Y:
8591 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8592 break;
8593 case PLANE_CTL_TILED_YF:
8594 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8595 break;
8596 default:
8597 MISSING_CASE(tiling);
8598 goto error;
8599 }
8600
bc8d7dff
DL		 8601 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8602 plane_config->base = base;
8603
8604 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8605
8606 val = I915_READ(PLANE_SIZE(pipe, 0));
8607 fb->height = ((val >> 16) & 0xfff) + 1;
8608 fb->width = ((val >> 0) & 0x1fff) + 1;
8609
8610 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8611 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8612 fb->pixel_format);
bc8d7dff
DL		 8613 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8614
8615 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8616 fb->pixel_format,
8617 fb->modifier[0]);
bc8d7dff 8618
f37b5c2b 8619 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8620
8621 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8622 pipe_name(pipe), fb->width, fb->height,
8623 fb->bits_per_pixel, base, fb->pitches[0],
8624 plane_config->size);
8625
2d14030b 8626 plane_config->fb = intel_fb;
bc8d7dff
DL		 8627 return;
8628
8629error:
8630 kfree(fb);
8631}
8632
2fa2fe9a 8633static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8634 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8635{
8636 struct drm_device *dev = crtc->base.dev;
8637 struct drm_i915_private *dev_priv = dev->dev_private;
8638 uint32_t tmp;
8639
8640 tmp = I915_READ(PF_CTL(crtc->pipe));
8641
8642 if (tmp & PF_ENABLE) {
fd4daa9c 8643 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8644 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8645 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8646
8647 /* We currently do not free assignements of panel fitters on
8648 * ivb/hsw (since we don't use the higher upscaling modes which
8649 * differentiates them) so just WARN about this case for now. */
8650 if (IS_GEN7(dev)) {
8651 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8652 PF_PIPE_SEL_IVB(crtc->pipe));
8653 }
2fa2fe9a 8654 }
79e53945
JB		 8655}
8656
5724dbd1
DL		 8657static void
8658ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8659 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8660{
8661 struct drm_device *dev = crtc->base.dev;
8662 struct drm_i915_private *dev_priv = dev->dev_private;
8663 u32 val, base, offset;
aeee5a49 8664 int pipe = crtc->pipe;
4c6baa59 8665 int fourcc, pixel_format;
6761dd31 8666 unsigned int aligned_height;
b113d5ee 8667 struct drm_framebuffer *fb;
1b842c89 8668 struct intel_framebuffer *intel_fb;
4c6baa59 8669
42a7b088
DL		 8670 val = I915_READ(DSPCNTR(pipe));
8671 if (!(val & DISPLAY_PLANE_ENABLE))
8672 return;
8673
d9806c9f 8674 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8675 if (!intel_fb) {
4c6baa59
JB		 8676 DRM_DEBUG_KMS("failed to alloc fb\n");
8677 return;
8678 }
8679
1b842c89
DL		 8680 fb = &intel_fb->base;
8681
18c5247e
DV		 8682 if (INTEL_INFO(dev)->gen >= 4) {
8683 if (val & DISPPLANE_TILED) {
49af449b 8684 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8685 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8686 }
8687 }
4c6baa59
JB		 8688
8689 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8690 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8691 fb->pixel_format = fourcc;
8692 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8693
aeee5a49 8694 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8695 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8696 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8697 } else {
49af449b 8698 if (plane_config->tiling)
aeee5a49 8699 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8700 else
aeee5a49 8701 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8702 }
8703 plane_config->base = base;
8704
8705 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8706 fb->width = ((val >> 16) & 0xfff) + 1;
8707 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8708
8709 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8710 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8711
b113d5ee 8712 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8713 fb->pixel_format,
8714 fb->modifier[0]);
4c6baa59 8715
f37b5c2b 8716 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8717
2844a921
DL		 8718 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8719 pipe_name(pipe), fb->width, fb->height,
8720 fb->bits_per_pixel, base, fb->pitches[0],
8721 plane_config->size);
b113d5ee 8722
2d14030b 8723 plane_config->fb = intel_fb;
4c6baa59
JB		 8724}
8725
0e8ffe1b 8726static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8727 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8728{
8729 struct drm_device *dev = crtc->base.dev;
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731 uint32_t tmp;
8732
f458ebbc
DV		 8733 if (!intel_display_power_is_enabled(dev_priv,
8734 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8735 return false;
8736
e143a21c 8737 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8738 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8739
0e8ffe1b
DV		 8740 tmp = I915_READ(PIPECONF(crtc->pipe));
8741 if (!(tmp & PIPECONF_ENABLE))
8742 return false;
8743
42571aef
VS		 8744 switch (tmp & PIPECONF_BPC_MASK) {
8745 case PIPECONF_6BPC:
8746 pipe_config->pipe_bpp = 18;
8747 break;
8748 case PIPECONF_8BPC:
8749 pipe_config->pipe_bpp = 24;
8750 break;
8751 case PIPECONF_10BPC:
8752 pipe_config->pipe_bpp = 30;
8753 break;
8754 case PIPECONF_12BPC:
8755 pipe_config->pipe_bpp = 36;
8756 break;
8757 default:
8758 break;
8759 }
8760
b5a9fa09
DV		 8761 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8762 pipe_config->limited_color_range = true;
8763
ab9412ba 8764 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8765 struct intel_shared_dpll *pll;
8766
88adfff1
DV		 8767 pipe_config->has_pch_encoder = true;
8768
627eb5a3
DV		 8769 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8770 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8771 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8772
8773 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8774
c0d43d62 8775 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8776 pipe_config->shared_dpll =
8777 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8778 } else {
8779 tmp = I915_READ(PCH_DPLL_SEL);
8780 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8781 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8782 else
8783 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8784 }
66e985c0
DV		 8785
8786 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8787
8788 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8789 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8790
8791 tmp = pipe_config->dpll_hw_state.dpll;
8792 pipe_config->pixel_multiplier =
8793 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8794 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8795
8796 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8797 } else {
8798 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8799 }
8800
1bd1bd80
DV		 8801 intel_get_pipe_timings(crtc, pipe_config);
8802
2fa2fe9a
DV		 8803 ironlake_get_pfit_config(crtc, pipe_config);
8804
0e8ffe1b
DV		 8805 return true;
8806}
8807
be256dc7
PZ		 8808static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8809{
8810 struct drm_device *dev = dev_priv->dev;
be256dc7 8811 struct intel_crtc *crtc;
be256dc7 8812
d3fcc808 8813 for_each_intel_crtc(dev, crtc)
e2c719b7 8814 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8815 pipe_name(crtc->pipe));
8816
e2c719b7
RC		 8817 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8818 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8819 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8820 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8821 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8822 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8823 "CPU PWM1 enabled\n");
c5107b87 8824 if (IS_HASWELL(dev))
e2c719b7 8825 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8826 "CPU PWM2 enabled\n");
e2c719b7 8827 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8828 "PCH PWM1 enabled\n");
e2c719b7 8829 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8830 "Utility pin enabled\n");
e2c719b7 8831 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8832
9926ada1
PZ		 8833 /*
8834 * In theory we can still leave IRQs enabled, as long as only the HPD
8835 * interrupts remain enabled. We used to check for that, but since it's
8836 * gen-specific and since we only disable LCPLL after we fully disable
8837 * the interrupts, the check below should be enough.
8838 */
e2c719b7 8839 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8840}
8841
9ccd5aeb
PZ		 8842static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8843{
8844 struct drm_device *dev = dev_priv->dev;
8845
8846 if (IS_HASWELL(dev))
8847 return I915_READ(D_COMP_HSW);
8848 else
8849 return I915_READ(D_COMP_BDW);
8850}
8851
3c4c9b81
PZ		 8852static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8853{
8854 struct drm_device *dev = dev_priv->dev;
8855
8856 if (IS_HASWELL(dev)) {
8857 mutex_lock(&dev_priv->rps.hw_lock);
8858 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8859 val))
f475dadf 8860 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8861 mutex_unlock(&dev_priv->rps.hw_lock);
8862 } else {
9ccd5aeb
PZ		 8863 I915_WRITE(D_COMP_BDW, val);
8864 POSTING_READ(D_COMP_BDW);
3c4c9b81 8865 }
be256dc7
PZ		 8866}
8867
8868/*
8869 * This function implements pieces of two sequences from BSpec:
8870 * - Sequence for display software to disable LCPLL
8871 * - Sequence for display software to allow package C8+
8872 * The steps implemented here are just the steps that actually touch the LCPLL
8873 * register. Callers should take care of disabling all the display engine
8874 * functions, doing the mode unset, fixing interrupts, etc.
8875 */
6ff58d53
PZ		 8876static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8877 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8878{
8879 uint32_t val;
8880
8881 assert_can_disable_lcpll(dev_priv);
8882
8883 val = I915_READ(LCPLL_CTL);
8884
8885 if (switch_to_fclk) {
8886 val |= LCPLL_CD_SOURCE_FCLK;
8887 I915_WRITE(LCPLL_CTL, val);
8888
8889 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8890 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8891 DRM_ERROR("Switching to FCLK failed\n");
8892
8893 val = I915_READ(LCPLL_CTL);
8894 }
8895
8896 val |= LCPLL_PLL_DISABLE;
8897 I915_WRITE(LCPLL_CTL, val);
8898 POSTING_READ(LCPLL_CTL);
8899
8900 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8901 DRM_ERROR("LCPLL still locked\n");
8902
9ccd5aeb 8903 val = hsw_read_dcomp(dev_priv);
be256dc7 8904 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8905 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8906 ndelay(100);
8907
9ccd5aeb
PZ		 8908 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8909 1))
be256dc7
PZ		 8910 DRM_ERROR("D_COMP RCOMP still in progress\n");
8911
8912 if (allow_power_down) {
8913 val = I915_READ(LCPLL_CTL);
8914 val |= LCPLL_POWER_DOWN_ALLOW;
8915 I915_WRITE(LCPLL_CTL, val);
8916 POSTING_READ(LCPLL_CTL);
8917 }
8918}
8919
8920/*
8921 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8922 * source.
8923 */
6ff58d53 8924static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8925{
8926 uint32_t val;
8927
8928 val = I915_READ(LCPLL_CTL);
8929
8930 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8931 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8932 return;
8933
a8a8bd54
PZ		 8934 /*
8935 * Make sure we're not on PC8 state before disabling PC8, otherwise
8936 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8937 */
59bad947 8938 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8939
be256dc7
PZ		 8940 if (val & LCPLL_POWER_DOWN_ALLOW) {
8941 val &= ~LCPLL_POWER_DOWN_ALLOW;
8942 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8943 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8944 }
8945
9ccd5aeb 8946 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8947 val |= D_COMP_COMP_FORCE;
8948 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8949 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8950
8951 val = I915_READ(LCPLL_CTL);
8952 val &= ~LCPLL_PLL_DISABLE;
8953 I915_WRITE(LCPLL_CTL, val);
8954
8955 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8956 DRM_ERROR("LCPLL not locked yet\n");
8957
8958 if (val & LCPLL_CD_SOURCE_FCLK) {
8959 val = I915_READ(LCPLL_CTL);
8960 val &= ~LCPLL_CD_SOURCE_FCLK;
8961 I915_WRITE(LCPLL_CTL, val);
8962
8963 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8964 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8965 DRM_ERROR("Switching back to LCPLL failed\n");
8966 }
215733fa 8967
59bad947 8968 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8969}
8970
765dab67
PZ		 8971/*
8972 * Package states C8 and deeper are really deep PC states that can only be
8973 * reached when all the devices on the system allow it, so even if the graphics
8974 * device allows PC8+, it doesn't mean the system will actually get to these
8975 * states. Our driver only allows PC8+ when going into runtime PM.
8976 *
8977 * The requirements for PC8+ are that all the outputs are disabled, the power
8978 * well is disabled and most interrupts are disabled, and these are also
8979 * requirements for runtime PM. When these conditions are met, we manually do
8980 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8981 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8982 * hang the machine.
8983 *
8984 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8985 * the state of some registers, so when we come back from PC8+ we need to
8986 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8987 * need to take care of the registers kept by RC6. Notice that this happens even
8988 * if we don't put the device in PCI D3 state (which is what currently happens
8989 * because of the runtime PM support).
8990 *
8991 * For more, read "Display Sequences for Package C8" on the hardware
8992 * documentation.
8993 */
a14cb6fc 8994void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8995{
c67a470b
PZ		 8996 struct drm_device *dev = dev_priv->dev;
8997 uint32_t val;
8998
c67a470b
PZ		 8999 DRM_DEBUG_KMS("Enabling package C8+\n");
9000
c67a470b
PZ		 9001 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9002 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9003 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9004 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9005 }
9006
9007 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9008 hsw_disable_lcpll(dev_priv, true, true);
9009}
9010
a14cb6fc 9011void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9012{
9013 struct drm_device *dev = dev_priv->dev;
9014 uint32_t val;
9015
c67a470b
PZ		 9016 DRM_DEBUG_KMS("Disabling package C8+\n");
9017
9018 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9019 lpt_init_pch_refclk(dev);
9020
9021 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9022 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9023 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9024 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9025 }
9026
9027 intel_prepare_ddi(dev);
c67a470b
PZ		 9028}
9029
f8437dd1
VK		 9030static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9031{
9032 struct drm_device *dev = state->dev;
9033 struct drm_i915_private *dev_priv = dev->dev_private;
9034 int max_pixclk = intel_mode_max_pixclk(state);
9035 int req_cdclk;
9036
9037 /* see the comment in valleyview_modeset_global_resources */
9038 if (WARN_ON(max_pixclk < 0))
9039 return;
9040
9041 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9042
9043 if (req_cdclk != dev_priv->cdclk_freq)
9044 broxton_set_cdclk(dev, req_cdclk);
9045}
9046
190f68c5
ACO		 9047static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9048 struct intel_crtc_state *crtc_state)
09b4ddf9 9049{
190f68c5 9050 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9051 return -EINVAL;
716c2e55 9052
c7653199 9053 crtc->lowfreq_avail = false;
644cef34 9054
c8f7a0db 9055 return 0;
79e53945
JB		 9056}
9057
96b7dfb7
S		 9058static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9059 enum port port,
5cec258b 9060 struct intel_crtc_state *pipe_config)
96b7dfb7 9061{
3148ade7 9062 u32 temp, dpll_ctl1;
96b7dfb7
S		 9063
9064 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9065 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9066
9067 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9068 case SKL_DPLL0:
9069 /*
9070 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9071 * of the shared DPLL framework and thus needs to be read out
9072 * separately
9073 */
9074 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9075 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9076 break;
96b7dfb7
S		 9077 case SKL_DPLL1:
9078 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9079 break;
9080 case SKL_DPLL2:
9081 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9082 break;
9083 case SKL_DPLL3:
9084 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9085 break;
96b7dfb7
S		 9086 }
9087}
9088
7d2c8175
DL		 9089static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9090 enum port port,
5cec258b 9091 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9092{
9093 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9094
9095 switch (pipe_config->ddi_pll_sel) {
9096 case PORT_CLK_SEL_WRPLL1:
9097 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9098 break;
9099 case PORT_CLK_SEL_WRPLL2:
9100 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9101 break;
9102 }
9103}
9104
26804afd 9105static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9106 struct intel_crtc_state *pipe_config)
26804afd
DV		 9107{
9108 struct drm_device *dev = crtc->base.dev;
9109 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9110 struct intel_shared_dpll *pll;
26804afd
DV		 9111 enum port port;
9112 uint32_t tmp;
9113
9114 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9115
9116 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9117
96b7dfb7
S		 9118 if (IS_SKYLAKE(dev))
9119 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9120 else
9121 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9122
d452c5b6
DV		 9123 if (pipe_config->shared_dpll >= 0) {
9124 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9125
9126 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9127 &pipe_config->dpll_hw_state));
9128 }
9129
26804afd
DV		 9130 /*
9131 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9132 * DDI E. So just check whether this pipe is wired to DDI E and whether
9133 * the PCH transcoder is on.
9134 */
ca370455
DL		 9135 if (INTEL_INFO(dev)->gen < 9 &&
9136 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9137 pipe_config->has_pch_encoder = true;
9138
9139 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9140 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9141 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9142
9143 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9144 }
9145}
9146
0e8ffe1b 9147static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9148 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9149{
9150 struct drm_device *dev = crtc->base.dev;
9151 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9152 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9153 uint32_t tmp;
9154
f458ebbc 9155 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9156 POWER_DOMAIN_PIPE(crtc->pipe)))
9157 return false;
9158
e143a21c 9159 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9160 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9161
eccb140b
DV		 9162 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9163 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9164 enum pipe trans_edp_pipe;
9165 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9166 default:
9167 WARN(1, "unknown pipe linked to edp transcoder\n");
9168 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9169 case TRANS_DDI_EDP_INPUT_A_ON:
9170 trans_edp_pipe = PIPE_A;
9171 break;
9172 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9173 trans_edp_pipe = PIPE_B;
9174 break;
9175 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9176 trans_edp_pipe = PIPE_C;
9177 break;
9178 }
9179
9180 if (trans_edp_pipe == crtc->pipe)
9181 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9182 }
9183
f458ebbc 9184 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9185 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9186 return false;
9187
eccb140b 9188 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9189 if (!(tmp & PIPECONF_ENABLE))
9190 return false;
9191
26804afd 9192 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9193
1bd1bd80
DV		 9194 intel_get_pipe_timings(crtc, pipe_config);
9195
a1b2278e
CK		 9196 if (INTEL_INFO(dev)->gen >= 9) {
9197 skl_init_scalers(dev, crtc, pipe_config);
9198 }
9199
2fa2fe9a 9200 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 9201 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9202 if (IS_SKYLAKE(dev))
9203 skylake_get_pfit_config(crtc, pipe_config);
9204 else
9205 ironlake_get_pfit_config(crtc, pipe_config);
a1b2278e
CK		 9206 } else {
9207 pipe_config->scaler_state.scaler_id = -1;
9208 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9209 }
88adfff1 9210
e59150dc
JB		 9211 if (IS_HASWELL(dev))
9212 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9213 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9214
ebb69c95
CT		 9215 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9216 pipe_config->pixel_multiplier =
9217 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9218 } else {
9219 pipe_config->pixel_multiplier = 1;
9220 }
6c49f241 9221
0e8ffe1b
DV		 9222 return true;
9223}
9224
560b85bb
CW		 9225static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9226{
9227 struct drm_device *dev = crtc->dev;
9228 struct drm_i915_private *dev_priv = dev->dev_private;
9229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9230 uint32_t cntl = 0, size = 0;
560b85bb 9231
dc41c154 9232 if (base) {
3dd512fb
MR		 9233 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9234 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9235 unsigned int stride = roundup_pow_of_two(width) * 4;
9236
9237 switch (stride) {
9238 default:
9239 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9240 width, stride);
9241 stride = 256;
9242 /* fallthrough */
9243 case 256:
9244 case 512:
9245 case 1024:
9246 case 2048:
9247 break;
4b0e333e
CW		 9248 }
9249
dc41c154
VS		 9250 cntl |= CURSOR_ENABLE |
9251 CURSOR_GAMMA_ENABLE |
9252 CURSOR_FORMAT_ARGB |
9253 CURSOR_STRIDE(stride);
9254
9255 size = (height << 12) | width;
4b0e333e 9256 }
560b85bb 9257
dc41c154
VS		 9258 if (intel_crtc->cursor_cntl != 0 &&
9259 (intel_crtc->cursor_base != base ||
9260 intel_crtc->cursor_size != size ||
9261 intel_crtc->cursor_cntl != cntl)) {
9262 /* On these chipsets we can only modify the base/size/stride
9263 * whilst the cursor is disabled.
9264 */
9265 I915_WRITE(_CURACNTR, 0);
4b0e333e 9266 POSTING_READ(_CURACNTR);
dc41c154 9267 intel_crtc->cursor_cntl = 0;
4b0e333e 9268 }
560b85bb 9269
99d1f387 9270 if (intel_crtc->cursor_base != base) {
9db4a9c7 9271 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9272 intel_crtc->cursor_base = base;
9273 }
4726e0b0 9274
dc41c154
VS		 9275 if (intel_crtc->cursor_size != size) {
9276 I915_WRITE(CURSIZE, size);
9277 intel_crtc->cursor_size = size;
4b0e333e 9278 }
560b85bb 9279
4b0e333e 9280 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9281 I915_WRITE(_CURACNTR, cntl);
9282 POSTING_READ(_CURACNTR);
4b0e333e 9283 intel_crtc->cursor_cntl = cntl;
560b85bb 9284 }
560b85bb
CW		 9285}
9286
560b85bb 9287static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9288{
9289 struct drm_device *dev = crtc->dev;
9290 struct drm_i915_private *dev_priv = dev->dev_private;
9291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9292 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9293 uint32_t cntl;
9294
9295 cntl = 0;
9296 if (base) {
9297 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9298 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9299 case 64:
9300 cntl |= CURSOR_MODE_64_ARGB_AX;
9301 break;
9302 case 128:
9303 cntl |= CURSOR_MODE_128_ARGB_AX;
9304 break;
9305 case 256:
9306 cntl |= CURSOR_MODE_256_ARGB_AX;
9307 break;
9308 default:
3dd512fb 9309 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9310 return;
65a21cd6 9311 }
4b0e333e 9312 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9313
9314 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9315 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9316 }
65a21cd6 9317
8e7d688b 9318 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9319 cntl |= CURSOR_ROTATE_180;
9320
4b0e333e
CW		 9321 if (intel_crtc->cursor_cntl != cntl) {
9322 I915_WRITE(CURCNTR(pipe), cntl);
9323 POSTING_READ(CURCNTR(pipe));
9324 intel_crtc->cursor_cntl = cntl;
65a21cd6 9325 }
4b0e333e 9326
65a21cd6 9327 /* and commit changes on next vblank */
5efb3e28
VS		 9328 I915_WRITE(CURBASE(pipe), base);
9329 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9330
9331 intel_crtc->cursor_base = base;
65a21cd6
JB		 9332}
9333
cda4b7d3 9334/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9335static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9336 bool on)
cda4b7d3
CW		 9337{
9338 struct drm_device *dev = crtc->dev;
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9341 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9342 int x = crtc->cursor_x;
9343 int y = crtc->cursor_y;
d6e4db15 9344 u32 base = 0, pos = 0;
cda4b7d3 9345
d6e4db15 9346 if (on)
cda4b7d3 9347 base = intel_crtc->cursor_addr;
cda4b7d3 9348
6e3c9717 9349 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9350 base = 0;
9351
6e3c9717 9352 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9353 base = 0;
9354
9355 if (x < 0) {
3dd512fb 9356 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9357 base = 0;
9358
9359 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9360 x = -x;
9361 }
9362 pos |= x << CURSOR_X_SHIFT;
9363
9364 if (y < 0) {
3dd512fb 9365 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9366 base = 0;
9367
9368 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9369 y = -y;
9370 }
9371 pos |= y << CURSOR_Y_SHIFT;
9372
4b0e333e 9373 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9374 return;
9375
5efb3e28
VS		 9376 I915_WRITE(CURPOS(pipe), pos);
9377
4398ad45
VS		 9378 /* ILK+ do this automagically */
9379 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9380 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9381 base += (intel_crtc->base.cursor->state->crtc_h *
9382 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9383 }
9384
8ac54669 9385 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9386 i845_update_cursor(crtc, base);
9387 else
9388 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9389}
9390
dc41c154
VS		 9391static bool cursor_size_ok(struct drm_device *dev,
9392 uint32_t width, uint32_t height)
9393{
9394 if (width == 0 || height == 0)
9395 return false;
9396
9397 /*
9398 * 845g/865g are special in that they are only limited by
9399 * the width of their cursors, the height is arbitrary up to
9400 * the precision of the register. Everything else requires
9401 * square cursors, limited to a few power-of-two sizes.
9402 */
9403 if (IS_845G(dev) || IS_I865G(dev)) {
9404 if ((width & 63) != 0)
9405 return false;
9406
9407 if (width > (IS_845G(dev) ? 64 : 512))
9408 return false;
9409
9410 if (height > 1023)
9411 return false;
9412 } else {
9413 switch (width | height) {
9414 case 256:
9415 case 128:
9416 if (IS_GEN2(dev))
9417 return false;
9418 case 64:
9419 break;
9420 default:
9421 return false;
9422 }
9423 }
9424
9425 return true;
9426}
9427
79e53945 9428static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9429 u16 *blue, uint32_t start, uint32_t size)
79e53945 9430{
7203425a 9431 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9433
7203425a 9434 for (i = start; i < end; i++) {
79e53945
JB		 9435 intel_crtc->lut_r[i] = red[i] >> 8;
9436 intel_crtc->lut_g[i] = green[i] >> 8;
9437 intel_crtc->lut_b[i] = blue[i] >> 8;
9438 }
9439
9440 intel_crtc_load_lut(crtc);
9441}
9442
79e53945
JB		 9443/* VESA 640x480x72Hz mode to set on the pipe */
9444static struct drm_display_mode load_detect_mode = {
9445 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9446 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9447};
9448
a8bb6818
DV		 9449struct drm_framebuffer *
9450__intel_framebuffer_create(struct drm_device *dev,
9451 struct drm_mode_fb_cmd2 *mode_cmd,
9452 struct drm_i915_gem_object *obj)
d2dff872
CW		 9453{
9454 struct intel_framebuffer *intel_fb;
9455 int ret;
9456
9457 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9458 if (!intel_fb) {
6ccb81f2 9459 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9460 return ERR_PTR(-ENOMEM);
9461 }
9462
9463 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9464 if (ret)
9465 goto err;
d2dff872
CW		 9466
9467 return &intel_fb->base;
dd4916c5 9468err:
6ccb81f2 9469 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9470 kfree(intel_fb);
9471
9472 return ERR_PTR(ret);
d2dff872
CW		 9473}
9474
b5ea642a 9475static struct drm_framebuffer *
a8bb6818
DV		 9476intel_framebuffer_create(struct drm_device *dev,
9477 struct drm_mode_fb_cmd2 *mode_cmd,
9478 struct drm_i915_gem_object *obj)
9479{
9480 struct drm_framebuffer *fb;
9481 int ret;
9482
9483 ret = i915_mutex_lock_interruptible(dev);
9484 if (ret)
9485 return ERR_PTR(ret);
9486 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9487 mutex_unlock(&dev->struct_mutex);
9488
9489 return fb;
9490}
9491
d2dff872
CW		 9492static u32
9493intel_framebuffer_pitch_for_width(int width, int bpp)
9494{
9495 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9496 return ALIGN(pitch, 64);
9497}
9498
9499static u32
9500intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9501{
9502 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9503 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9504}
9505
9506static struct drm_framebuffer *
9507intel_framebuffer_create_for_mode(struct drm_device *dev,
9508 struct drm_display_mode *mode,
9509 int depth, int bpp)
9510{
9511 struct drm_i915_gem_object *obj;
0fed39bd 9512 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9513
9514 obj = i915_gem_alloc_object(dev,
9515 intel_framebuffer_size_for_mode(mode, bpp));
9516 if (obj == NULL)
9517 return ERR_PTR(-ENOMEM);
9518
9519 mode_cmd.width = mode->hdisplay;
9520 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9521 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9522 bpp);
5ca0c34a 9523 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9524
9525 return intel_framebuffer_create(dev, &mode_cmd, obj);
9526}
9527
9528static struct drm_framebuffer *
9529mode_fits_in_fbdev(struct drm_device *dev,
9530 struct drm_display_mode *mode)
9531{
4520f53a 9532#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9533 struct drm_i915_private *dev_priv = dev->dev_private;
9534 struct drm_i915_gem_object *obj;
9535 struct drm_framebuffer *fb;
9536
4c0e5528 9537 if (!dev_priv->fbdev)
d2dff872
CW		 9538 return NULL;
9539
4c0e5528 9540 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9541 return NULL;
9542
4c0e5528
DV		 9543 obj = dev_priv->fbdev->fb->obj;
9544 BUG_ON(!obj);
9545
8bcd4553 9546 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9547 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9548 fb->bits_per_pixel))
d2dff872
CW		 9549 return NULL;
9550
01f2c773 9551 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9552 return NULL;
9553
9554 return fb;
4520f53a
DV		 9555#else
9556 return NULL;
9557#endif
d2dff872
CW		 9558}
9559
d2434ab7 9560bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9561 struct drm_display_mode *mode,
51fd371b
RC		 9562 struct intel_load_detect_pipe *old,
9563 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9564{
9565 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9566 struct intel_encoder *intel_encoder =
9567 intel_attached_encoder(connector);
79e53945 9568 struct drm_crtc *possible_crtc;
4ef69c7a 9569 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9570 struct drm_crtc *crtc = NULL;
9571 struct drm_device *dev = encoder->dev;
94352cf9 9572 struct drm_framebuffer *fb;
51fd371b 9573 struct drm_mode_config *config = &dev->mode_config;
83a57153 9574 struct drm_atomic_state *state = NULL;
944b0c76 9575 struct drm_connector_state *connector_state;
51fd371b 9576 int ret, i = -1;
79e53945 9577
d2dff872 9578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9579 connector->base.id, connector->name,
8e329a03 9580 encoder->base.id, encoder->name);
d2dff872 9581
51fd371b
RC		 9582retry:
9583 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9584 if (ret)
9585 goto fail_unlock;
6e9f798d 9586
79e53945
JB		 9587 /*
9588 * Algorithm gets a little messy:
7a5e4805 9589 *
79e53945
JB		 9590 * - if the connector already has an assigned crtc, use it (but make
9591 * sure it's on first)
7a5e4805 9592 *
79e53945
JB		 9593 * - try to find the first unused crtc that can drive this connector,
9594 * and use that if we find one
79e53945
JB		 9595 */
9596
9597 /* See if we already have a CRTC for this connector */
9598 if (encoder->crtc) {
9599 crtc = encoder->crtc;
8261b191 9600
51fd371b 9601 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9602 if (ret)
9603 goto fail_unlock;
9604 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9605 if (ret)
9606 goto fail_unlock;
7b24056b 9607
24218aac 9608 old->dpms_mode = connector->dpms;
8261b191
CW		 9609 old->load_detect_temp = false;
9610
9611 /* Make sure the crtc and connector are running */
24218aac
DV		 9612 if (connector->dpms != DRM_MODE_DPMS_ON)
9613 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9614
7173188d 9615 return true;
79e53945
JB		 9616 }
9617
9618 /* Find an unused one (if possible) */
70e1e0ec 9619 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9620 i++;
9621 if (!(encoder->possible_crtcs & (1 << i)))
9622 continue;
83d65738 9623 if (possible_crtc->state->enable)
a459249c
VS		 9624 continue;
9625 /* This can occur when applying the pipe A quirk on resume. */
9626 if (to_intel_crtc(possible_crtc)->new_enabled)
9627 continue;
9628
9629 crtc = possible_crtc;
9630 break;
79e53945
JB		 9631 }
9632
9633 /*
9634 * If we didn't find an unused CRTC, don't use any.
9635 */
9636 if (!crtc) {
7173188d 9637 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9638 goto fail_unlock;
79e53945
JB		 9639 }
9640
51fd371b
RC		 9641 ret = drm_modeset_lock(&crtc->mutex, ctx);
9642 if (ret)
4d02e2de
DV		 9643 goto fail_unlock;
9644 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9645 if (ret)
51fd371b 9646 goto fail_unlock;
fc303101
DV		 9647 intel_encoder->new_crtc = to_intel_crtc(crtc);
9648 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9649
9650 intel_crtc = to_intel_crtc(crtc);
412b61d8 9651 intel_crtc->new_enabled = true;
24218aac 9652 old->dpms_mode = connector->dpms;
8261b191 9653 old->load_detect_temp = true;
d2dff872 9654 old->release_fb = NULL;
79e53945 9655
83a57153
ACO		 9656 state = drm_atomic_state_alloc(dev);
9657 if (!state)
9658 return false;
9659
9660 state->acquire_ctx = ctx;
9661
944b0c76
ACO		 9662 connector_state = drm_atomic_get_connector_state(state, connector);
9663 if (IS_ERR(connector_state)) {
9664 ret = PTR_ERR(connector_state);
9665 goto fail;
9666 }
9667
9668 connector_state->crtc = crtc;
9669 connector_state->best_encoder = &intel_encoder->base;
9670
6492711d
CW		 9671 if (!mode)
9672 mode = &load_detect_mode;
79e53945 9673
d2dff872
CW		 9674 /* We need a framebuffer large enough to accommodate all accesses
9675 * that the plane may generate whilst we perform load detection.
9676 * We can not rely on the fbcon either being present (we get called
9677 * during its initialisation to detect all boot displays, or it may
9678 * not even exist) or that it is large enough to satisfy the
9679 * requested mode.
9680 */
94352cf9
DV		 9681 fb = mode_fits_in_fbdev(dev, mode);
9682 if (fb == NULL) {
d2dff872 9683 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9684 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9685 old->release_fb = fb;
d2dff872
CW		 9686 } else
9687 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9688 if (IS_ERR(fb)) {
d2dff872 9689 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9690 goto fail;
79e53945 9691 }
79e53945 9692
83a57153 9693 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9694 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9695 if (old->release_fb)
9696 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9697 goto fail;
79e53945 9698 }
9128b040 9699 crtc->primary->crtc = crtc;
7173188d 9700
79e53945 9701 /* let the connector get through one full cycle before testing */
9d0498a2 9702 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9703 return true;
412b61d8
VS		 9704
9705 fail:
83d65738 9706 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9707fail_unlock:
83a57153
ACO		 9708 if (state) {
9709 drm_atomic_state_free(state);
9710 state = NULL;
9711 }
9712
51fd371b
RC		 9713 if (ret == -EDEADLK) {
9714 drm_modeset_backoff(ctx);
9715 goto retry;
9716 }
9717
412b61d8 9718 return false;
79e53945
JB		 9719}
9720
d2434ab7 9721void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9722 struct intel_load_detect_pipe *old,
9723 struct drm_modeset_acquire_ctx *ctx)
79e53945 9724{
83a57153 9725 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9726 struct intel_encoder *intel_encoder =
9727 intel_attached_encoder(connector);
4ef69c7a 9728 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9729 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9731 struct drm_atomic_state *state;
944b0c76 9732 struct drm_connector_state *connector_state;
79e53945 9733
d2dff872 9734 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9735 connector->base.id, connector->name,
8e329a03 9736 encoder->base.id, encoder->name);
d2dff872 9737
8261b191 9738 if (old->load_detect_temp) {
83a57153 9739 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9740 if (!state)
9741 goto fail;
83a57153
ACO		 9742
9743 state->acquire_ctx = ctx;
9744
944b0c76
ACO		 9745 connector_state = drm_atomic_get_connector_state(state, connector);
9746 if (IS_ERR(connector_state))
9747 goto fail;
9748
fc303101
DV		 9749 to_intel_connector(connector)->new_encoder = NULL;
9750 intel_encoder->new_crtc = NULL;
412b61d8 9751 intel_crtc->new_enabled = false;
944b0c76
ACO		 9752
9753 connector_state->best_encoder = NULL;
9754 connector_state->crtc = NULL;
9755
83a57153
ACO		 9756 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9757
9758 drm_atomic_state_free(state);
d2dff872 9759
36206361
DV		 9760 if (old->release_fb) {
9761 drm_framebuffer_unregister_private(old->release_fb);
9762 drm_framebuffer_unreference(old->release_fb);
9763 }
d2dff872 9764
0622a53c 9765 return;
79e53945
JB		 9766 }
9767
c751ce4f 9768 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9769 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9770 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9771
9772 return;
9773fail:
9774 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9775 drm_atomic_state_free(state);
79e53945
JB		 9776}
9777
da4a1efa 9778static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9779 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9780{
9781 struct drm_i915_private *dev_priv = dev->dev_private;
9782 u32 dpll = pipe_config->dpll_hw_state.dpll;
9783
9784 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9785 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9786 else if (HAS_PCH_SPLIT(dev))
9787 return 120000;
9788 else if (!IS_GEN2(dev))
9789 return 96000;
9790 else
9791 return 48000;
9792}
9793
79e53945 9794/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9795static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9796 struct intel_crtc_state *pipe_config)
79e53945 9797{
f1f644dc 9798 struct drm_device *dev = crtc->base.dev;
79e53945 9799 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9800 int pipe = pipe_config->cpu_transcoder;
293623f7 9801 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9802 u32 fp;
9803 intel_clock_t clock;
da4a1efa 9804 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9805
9806 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9807 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9808 else
293623f7 9809 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9810
9811 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9812 if (IS_PINEVIEW(dev)) {
9813 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9814 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9815 } else {
9816 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9817 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9818 }
9819
a6c45cf0 9820 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9821 if (IS_PINEVIEW(dev))
9822 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9823 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9824 else
9825 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9826 DPLL_FPA01_P1_POST_DIV_SHIFT);
9827
9828 switch (dpll & DPLL_MODE_MASK) {
9829 case DPLLB_MODE_DAC_SERIAL:
9830 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9831 5 : 10;
9832 break;
9833 case DPLLB_MODE_LVDS:
9834 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9835 7 : 14;
9836 break;
9837 default:
28c97730 9838 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9839 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9840 return;
79e53945
JB		 9841 }
9842
ac58c3f0 9843 if (IS_PINEVIEW(dev))
da4a1efa 9844 pineview_clock(refclk, &clock);
ac58c3f0 9845 else
da4a1efa 9846 i9xx_clock(refclk, &clock);
79e53945 9847 } else {
0fb58223 9848 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9849 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9850
9851 if (is_lvds) {
9852 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9853 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9854
9855 if (lvds & LVDS_CLKB_POWER_UP)
9856 clock.p2 = 7;
9857 else
9858 clock.p2 = 14;
79e53945
JB		 9859 } else {
9860 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9861 clock.p1 = 2;
9862 else {
9863 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9864 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9865 }
9866 if (dpll & PLL_P2_DIVIDE_BY_4)
9867 clock.p2 = 4;
9868 else
9869 clock.p2 = 2;
79e53945 9870 }
da4a1efa
VS		 9871
9872 i9xx_clock(refclk, &clock);
79e53945
JB		 9873 }
9874
18442d08
VS		 9875 /*
9876 * This value includes pixel_multiplier. We will use
241bfc38 9877 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9878 * encoder's get_config() function.
9879 */
9880 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9881}
9882
6878da05
VS		 9883int intel_dotclock_calculate(int link_freq,
9884 const struct intel_link_m_n *m_n)
f1f644dc 9885{
f1f644dc
JB		 9886 /*
9887 * The calculation for the data clock is:
1041a02f 9888 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9889 * But we want to avoid losing precison if possible, so:
1041a02f 9890 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9891 *
9892 * and the link clock is simpler:
1041a02f 9893 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9894 */
9895
6878da05
VS		 9896 if (!m_n->link_n)
9897 return 0;
f1f644dc 9898
6878da05
VS		 9899 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9900}
f1f644dc 9901
18442d08 9902static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9903 struct intel_crtc_state *pipe_config)
6878da05
VS		 9904{
9905 struct drm_device *dev = crtc->base.dev;
79e53945 9906
18442d08
VS		 9907 /* read out port_clock from the DPLL */
9908 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9909
f1f644dc 9910 /*
18442d08 9911 * This value does not include pixel_multiplier.
241bfc38 9912 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9913 * agree once we know their relationship in the encoder's
9914 * get_config() function.
79e53945 9915 */
2d112de7 9916 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9917 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9918 &pipe_config->fdi_m_n);
79e53945
JB		 9919}
9920
9921/** Returns the currently programmed mode of the given pipe. */
9922struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9923 struct drm_crtc *crtc)
9924{
548f245b 9925 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9927 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9928 struct drm_display_mode *mode;
5cec258b 9929 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9930 int htot = I915_READ(HTOTAL(cpu_transcoder));
9931 int hsync = I915_READ(HSYNC(cpu_transcoder));
9932 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9933 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9934 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9935
9936 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9937 if (!mode)
9938 return NULL;
9939
f1f644dc
JB		 9940 /*
9941 * Construct a pipe_config sufficient for getting the clock info
9942 * back out of crtc_clock_get.
9943 *
9944 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9945 * to use a real value here instead.
9946 */
293623f7 9947 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9948 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9949 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9950 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9951 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9952 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9953
773ae034 9954 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9955 mode->hdisplay = (htot & 0xffff) + 1;
9956 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9957 mode->hsync_start = (hsync & 0xffff) + 1;
9958 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9959 mode->vdisplay = (vtot & 0xffff) + 1;
9960 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9961 mode->vsync_start = (vsync & 0xffff) + 1;
9962 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9963
9964 drm_mode_set_name(mode);
79e53945
JB		 9965
9966 return mode;
9967}
9968
652c393a
JB		 9969static void intel_decrease_pllclock(struct drm_crtc *crtc)
9970{
9971 struct drm_device *dev = crtc->dev;
fbee40df 9972 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9974
baff296c 9975 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9976 return;
9977
9978 if (!dev_priv->lvds_downclock_avail)
9979 return;
9980
9981 /*
9982 * Since this is called by a timer, we should never get here in
9983 * the manual case.
9984 */
9985 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9986 int pipe = intel_crtc->pipe;
9987 int dpll_reg = DPLL(pipe);
9988 int dpll;
f6e5b160 9989
44d98a61 9990 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9991
8ac5a6d5 9992 assert_panel_unlocked(dev_priv, pipe);
652c393a 9993
dc257cf1 9994 dpll = I915_READ(dpll_reg);
652c393a
JB		 9995 dpll |= DISPLAY_RATE_SELECT_FPA1;
9996 I915_WRITE(dpll_reg, dpll);
9d0498a2 9997 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9998 dpll = I915_READ(dpll_reg);
9999 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10000 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10001 }
10002
10003}
10004
f047e395
CW		 10005void intel_mark_busy(struct drm_device *dev)
10006{
c67a470b
PZ		 10007 struct drm_i915_private *dev_priv = dev->dev_private;
10008
f62a0076
CW		 10009 if (dev_priv->mm.busy)
10010 return;
10011
43694d69 10012 intel_runtime_pm_get(dev_priv);
c67a470b 10013 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10014 if (INTEL_INFO(dev)->gen >= 6)
10015 gen6_rps_busy(dev_priv);
f62a0076 10016 dev_priv->mm.busy = true;
f047e395
CW		 10017}
10018
10019void intel_mark_idle(struct drm_device *dev)
652c393a 10020{
c67a470b 10021 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10022 struct drm_crtc *crtc;
652c393a 10023
f62a0076
CW		 10024 if (!dev_priv->mm.busy)
10025 return;
10026
10027 dev_priv->mm.busy = false;
10028
70e1e0ec 10029 for_each_crtc(dev, crtc) {
f4510a27 10030 if (!crtc->primary->fb)
652c393a
JB		 10031 continue;
10032
725a5b54 10033 intel_decrease_pllclock(crtc);
652c393a 10034 }
b29c19b6 10035
3d13ef2e 10036 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10037 gen6_rps_idle(dev->dev_private);
bb4cdd53 10038
43694d69 10039 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10040}
10041
f5de6e07
ACO		 10042static void intel_crtc_set_state(struct intel_crtc *crtc,
10043 struct intel_crtc_state *crtc_state)
10044{
10045 kfree(crtc->config);
10046 crtc->config = crtc_state;
16f3f658 10047 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10048}
10049
79e53945
JB		 10050static void intel_crtc_destroy(struct drm_crtc *crtc)
10051{
10052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10053 struct drm_device *dev = crtc->dev;
10054 struct intel_unpin_work *work;
67e77c5a 10055
5e2d7afc 10056 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10057 work = intel_crtc->unpin_work;
10058 intel_crtc->unpin_work = NULL;
5e2d7afc 10059 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10060
10061 if (work) {
10062 cancel_work_sync(&work->work);
10063 kfree(work);
10064 }
79e53945 10065
f5de6e07 10066 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10067 drm_crtc_cleanup(crtc);
67e77c5a 10068
79e53945
JB		 10069 kfree(intel_crtc);
10070}
10071
6b95a207
KH		 10072static void intel_unpin_work_fn(struct work_struct *__work)
10073{
10074 struct intel_unpin_work *work =
10075 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10076 struct drm_device *dev = work->crtc->dev;
f99d7069 10077 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10078
b4a98e57 10079 mutex_lock(&dev->struct_mutex);
82bc3b2d 10080 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10081 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10082
7ff0ebcc 10083 intel_fbc_update(dev);
f06cc1b9
JH		 10084
10085 if (work->flip_queued_req)
146d84f0 10086 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10087 mutex_unlock(&dev->struct_mutex);
10088
f99d7069 10089 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10090 drm_framebuffer_unreference(work->old_fb);
f99d7069 10091
b4a98e57
CW		 10092 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10093 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10094
6b95a207
KH		 10095 kfree(work);
10096}
10097
1afe3e9d 10098static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10099 struct drm_crtc *crtc)
6b95a207 10100{
6b95a207
KH		 10101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10102 struct intel_unpin_work *work;
6b95a207
KH		 10103 unsigned long flags;
10104
10105 /* Ignore early vblank irqs */
10106 if (intel_crtc == NULL)
10107 return;
10108
f326038a
DV		 10109 /*
10110 * This is called both by irq handlers and the reset code (to complete
10111 * lost pageflips) so needs the full irqsave spinlocks.
10112 */
6b95a207
KH		 10113 spin_lock_irqsave(&dev->event_lock, flags);
10114 work = intel_crtc->unpin_work;
e7d841ca
CW		 10115
10116 /* Ensure we don't miss a work->pending update ... */
10117 smp_rmb();
10118
10119 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10120 spin_unlock_irqrestore(&dev->event_lock, flags);
10121 return;
10122 }
10123
d6bbafa1 10124 page_flip_completed(intel_crtc);
0af7e4df 10125
6b95a207 10126 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10127}
10128
1afe3e9d
JB		 10129void intel_finish_page_flip(struct drm_device *dev, int pipe)
10130{
fbee40df 10131 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10132 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10133
49b14a5c 10134 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10135}
10136
10137void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10138{
fbee40df 10139 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10140 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10141
49b14a5c 10142 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10143}
10144
75f7f3ec
VS		 10145/* Is 'a' after or equal to 'b'? */
10146static bool g4x_flip_count_after_eq(u32 a, u32 b)
10147{
10148 return !((a - b) & 0x80000000);
10149}
10150
10151static bool page_flip_finished(struct intel_crtc *crtc)
10152{
10153 struct drm_device *dev = crtc->base.dev;
10154 struct drm_i915_private *dev_priv = dev->dev_private;
10155
bdfa7542
VS		 10156 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10157 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10158 return true;
10159
75f7f3ec
VS		 10160 /*
10161 * The relevant registers doen't exist on pre-ctg.
10162 * As the flip done interrupt doesn't trigger for mmio
10163 * flips on gmch platforms, a flip count check isn't
10164 * really needed there. But since ctg has the registers,
10165 * include it in the check anyway.
10166 */
10167 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10168 return true;
10169
10170 /*
10171 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10172 * used the same base address. In that case the mmio flip might
10173 * have completed, but the CS hasn't even executed the flip yet.
10174 *
10175 * A flip count check isn't enough as the CS might have updated
10176 * the base address just after start of vblank, but before we
10177 * managed to process the interrupt. This means we'd complete the
10178 * CS flip too soon.
10179 *
10180 * Combining both checks should get us a good enough result. It may
10181 * still happen that the CS flip has been executed, but has not
10182 * yet actually completed. But in case the base address is the same
10183 * anyway, we don't really care.
10184 */
10185 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10186 crtc->unpin_work->gtt_offset &&
10187 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10188 crtc->unpin_work->flip_count);
10189}
10190
6b95a207
KH		 10191void intel_prepare_page_flip(struct drm_device *dev, int plane)
10192{
fbee40df 10193 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10194 struct intel_crtc *intel_crtc =
10195 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10196 unsigned long flags;
10197
f326038a
DV		 10198
10199 /*
10200 * This is called both by irq handlers and the reset code (to complete
10201 * lost pageflips) so needs the full irqsave spinlocks.
10202 *
10203 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10204 * generate a page-flip completion irq, i.e. every modeset
10205 * is also accompanied by a spurious intel_prepare_page_flip().
10206 */
6b95a207 10207 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10208 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10209 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10210 spin_unlock_irqrestore(&dev->event_lock, flags);
10211}
10212
eba905b2 10213static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10214{
10215 /* Ensure that the work item is consistent when activating it ... */
10216 smp_wmb();
10217 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10218 /* and that it is marked active as soon as the irq could fire. */
10219 smp_wmb();
10220}
10221
8c9f3aaf
JB		 10222static int intel_gen2_queue_flip(struct drm_device *dev,
10223 struct drm_crtc *crtc,
10224 struct drm_framebuffer *fb,
ed8d1975 10225 struct drm_i915_gem_object *obj,
a4872ba6 10226 struct intel_engine_cs *ring,
ed8d1975 10227 uint32_t flags)
8c9f3aaf 10228{
8c9f3aaf 10229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10230 u32 flip_mask;
10231 int ret;
10232
6d90c952 10233 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10234 if (ret)
4fa62c89 10235 return ret;
8c9f3aaf
JB		 10236
10237 /* Can't queue multiple flips, so wait for the previous
10238 * one to finish before executing the next.
10239 */
10240 if (intel_crtc->plane)
10241 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10242 else
10243 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10244 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10245 intel_ring_emit(ring, MI_NOOP);
10246 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10247 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10248 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10249 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10250 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10251
10252 intel_mark_page_flip_active(intel_crtc);
09246732 10253 __intel_ring_advance(ring);
83d4092b 10254 return 0;
8c9f3aaf
JB		 10255}
10256
10257static int intel_gen3_queue_flip(struct drm_device *dev,
10258 struct drm_crtc *crtc,
10259 struct drm_framebuffer *fb,
ed8d1975 10260 struct drm_i915_gem_object *obj,
a4872ba6 10261 struct intel_engine_cs *ring,
ed8d1975 10262 uint32_t flags)
8c9f3aaf 10263{
8c9f3aaf 10264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10265 u32 flip_mask;
10266 int ret;
10267
6d90c952 10268 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10269 if (ret)
4fa62c89 10270 return ret;
8c9f3aaf
JB		 10271
10272 if (intel_crtc->plane)
10273 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10274 else
10275 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10276 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10277 intel_ring_emit(ring, MI_NOOP);
10278 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10279 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10280 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10281 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10282 intel_ring_emit(ring, MI_NOOP);
10283
e7d841ca 10284 intel_mark_page_flip_active(intel_crtc);
09246732 10285 __intel_ring_advance(ring);
83d4092b 10286 return 0;
8c9f3aaf
JB		 10287}
10288
10289static int intel_gen4_queue_flip(struct drm_device *dev,
10290 struct drm_crtc *crtc,
10291 struct drm_framebuffer *fb,
ed8d1975 10292 struct drm_i915_gem_object *obj,
a4872ba6 10293 struct intel_engine_cs *ring,
ed8d1975 10294 uint32_t flags)
8c9f3aaf
JB		 10295{
10296 struct drm_i915_private *dev_priv = dev->dev_private;
10297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10298 uint32_t pf, pipesrc;
10299 int ret;
10300
6d90c952 10301 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10302 if (ret)
4fa62c89 10303 return ret;
8c9f3aaf
JB		 10304
10305 /* i965+ uses the linear or tiled offsets from the
10306 * Display Registers (which do not change across a page-flip)
10307 * so we need only reprogram the base address.
10308 */
6d90c952
DV		 10309 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10310 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10311 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10312 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10313 obj->tiling_mode);
8c9f3aaf
JB		 10314
10315 /* XXX Enabling the panel-fitter across page-flip is so far
10316 * untested on non-native modes, so ignore it for now.
10317 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10318 */
10319 pf = 0;
10320 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10321 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10322
10323 intel_mark_page_flip_active(intel_crtc);
09246732 10324 __intel_ring_advance(ring);
83d4092b 10325 return 0;
8c9f3aaf
JB		 10326}
10327
10328static int intel_gen6_queue_flip(struct drm_device *dev,
10329 struct drm_crtc *crtc,
10330 struct drm_framebuffer *fb,
ed8d1975 10331 struct drm_i915_gem_object *obj,
a4872ba6 10332 struct intel_engine_cs *ring,
ed8d1975 10333 uint32_t flags)
8c9f3aaf
JB		 10334{
10335 struct drm_i915_private *dev_priv = dev->dev_private;
10336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10337 uint32_t pf, pipesrc;
10338 int ret;
10339
6d90c952 10340 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10341 if (ret)
4fa62c89 10342 return ret;
8c9f3aaf 10343
6d90c952
DV		 10344 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10345 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10346 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10347 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10348
dc257cf1
DV		 10349 /* Contrary to the suggestions in the documentation,
10350 * "Enable Panel Fitter" does not seem to be required when page
10351 * flipping with a non-native mode, and worse causes a normal
10352 * modeset to fail.
10353 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10354 */
10355 pf = 0;
8c9f3aaf 10356 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10357 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10358
10359 intel_mark_page_flip_active(intel_crtc);
09246732 10360 __intel_ring_advance(ring);
83d4092b 10361 return 0;
8c9f3aaf
JB		 10362}
10363
7c9017e5
JB		 10364static int intel_gen7_queue_flip(struct drm_device *dev,
10365 struct drm_crtc *crtc,
10366 struct drm_framebuffer *fb,
ed8d1975 10367 struct drm_i915_gem_object *obj,
a4872ba6 10368 struct intel_engine_cs *ring,
ed8d1975 10369 uint32_t flags)
7c9017e5 10370{
7c9017e5 10371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10372 uint32_t plane_bit = 0;
ffe74d75
CW		 10373 int len, ret;
10374
eba905b2 10375 switch (intel_crtc->plane) {
cb05d8de
DV		 10376 case PLANE_A:
10377 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10378 break;
10379 case PLANE_B:
10380 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10381 break;
10382 case PLANE_C:
10383 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10384 break;
10385 default:
10386 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10387 return -ENODEV;
cb05d8de
DV		 10388 }
10389
ffe74d75 10390 len = 4;
f476828a 10391 if (ring->id == RCS) {
ffe74d75 10392 len += 6;
f476828a
DL		 10393 /*
10394 * On Gen 8, SRM is now taking an extra dword to accommodate
10395 * 48bits addresses, and we need a NOOP for the batch size to
10396 * stay even.
10397 */
10398 if (IS_GEN8(dev))
10399 len += 2;
10400 }
ffe74d75 10401
f66fab8e
VS		 10402 /*
10403 * BSpec MI_DISPLAY_FLIP for IVB:
10404 * "The full packet must be contained within the same cache line."
10405 *
10406 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10407 * cacheline, if we ever start emitting more commands before
10408 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10409 * then do the cacheline alignment, and finally emit the
10410 * MI_DISPLAY_FLIP.
10411 */
10412 ret = intel_ring_cacheline_align(ring);
10413 if (ret)
4fa62c89 10414 return ret;
f66fab8e 10415
ffe74d75 10416 ret = intel_ring_begin(ring, len);
7c9017e5 10417 if (ret)
4fa62c89 10418 return ret;
7c9017e5 10419
ffe74d75
CW		 10420 /* Unmask the flip-done completion message. Note that the bspec says that
10421 * we should do this for both the BCS and RCS, and that we must not unmask
10422 * more than one flip event at any time (or ensure that one flip message
10423 * can be sent by waiting for flip-done prior to queueing new flips).
10424 * Experimentation says that BCS works despite DERRMR masking all
10425 * flip-done completion events and that unmasking all planes at once
10426 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10427 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10428 */
10429 if (ring->id == RCS) {
10430 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10431 intel_ring_emit(ring, DERRMR);
10432 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10433 DERRMR_PIPEB_PRI_FLIP_DONE |
10434 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10435 if (IS_GEN8(dev))
10436 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10437 MI_SRM_LRM_GLOBAL_GTT);
10438 else
10439 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10440 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10441 intel_ring_emit(ring, DERRMR);
10442 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10443 if (IS_GEN8(dev)) {
10444 intel_ring_emit(ring, 0);
10445 intel_ring_emit(ring, MI_NOOP);
10446 }
ffe74d75
CW		 10447 }
10448
cb05d8de 10449 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10450 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10451 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10452 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10453
10454 intel_mark_page_flip_active(intel_crtc);
09246732 10455 __intel_ring_advance(ring);
83d4092b 10456 return 0;
7c9017e5
JB		 10457}
10458
84c33a64
SG		 10459static bool use_mmio_flip(struct intel_engine_cs *ring,
10460 struct drm_i915_gem_object *obj)
10461{
10462 /*
10463 * This is not being used for older platforms, because
10464 * non-availability of flip done interrupt forces us to use
10465 * CS flips. Older platforms derive flip done using some clever
10466 * tricks involving the flip_pending status bits and vblank irqs.
10467 * So using MMIO flips there would disrupt this mechanism.
10468 */
10469
8e09bf83
CW		 10470 if (ring == NULL)
10471 return true;
10472
84c33a64
SG		 10473 if (INTEL_INFO(ring->dev)->gen < 5)
10474 return false;
10475
10476 if (i915.use_mmio_flip < 0)
10477 return false;
10478 else if (i915.use_mmio_flip > 0)
10479 return true;
14bf993e
OM		 10480 else if (i915.enable_execlists)
10481 return true;
84c33a64 10482 else
41c52415 10483 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10484}
10485
ff944564
DL		 10486static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10487{
10488 struct drm_device *dev = intel_crtc->base.dev;
10489 struct drm_i915_private *dev_priv = dev->dev_private;
10490 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10491 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10492 struct drm_i915_gem_object *obj = intel_fb->obj;
10493 const enum pipe pipe = intel_crtc->pipe;
10494 u32 ctl, stride;
10495
10496 ctl = I915_READ(PLANE_CTL(pipe, 0));
10497 ctl &= ~PLANE_CTL_TILED_MASK;
10498 if (obj->tiling_mode == I915_TILING_X)
10499 ctl |= PLANE_CTL_TILED_X;
10500
10501 /*
10502 * The stride is either expressed as a multiple of 64 bytes chunks for
10503 * linear buffers or in number of tiles for tiled buffers.
10504 */
10505 stride = fb->pitches[0] >> 6;
10506 if (obj->tiling_mode == I915_TILING_X)
10507 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10508
10509 /*
10510 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10511 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10512 */
10513 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10514 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10515
10516 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10517 POSTING_READ(PLANE_SURF(pipe, 0));
10518}
10519
10520static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10521{
10522 struct drm_device *dev = intel_crtc->base.dev;
10523 struct drm_i915_private *dev_priv = dev->dev_private;
10524 struct intel_framebuffer *intel_fb =
10525 to_intel_framebuffer(intel_crtc->base.primary->fb);
10526 struct drm_i915_gem_object *obj = intel_fb->obj;
10527 u32 dspcntr;
10528 u32 reg;
10529
84c33a64
SG		 10530 reg = DSPCNTR(intel_crtc->plane);
10531 dspcntr = I915_READ(reg);
10532
c5d97472
DL		 10533 if (obj->tiling_mode != I915_TILING_NONE)
10534 dspcntr |= DISPPLANE_TILED;
10535 else
10536 dspcntr &= ~DISPPLANE_TILED;
10537
84c33a64
SG		 10538 I915_WRITE(reg, dspcntr);
10539
10540 I915_WRITE(DSPSURF(intel_crtc->plane),
10541 intel_crtc->unpin_work->gtt_offset);
10542 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10543
ff944564
DL		 10544}
10545
10546/*
10547 * XXX: This is the temporary way to update the plane registers until we get
10548 * around to using the usual plane update functions for MMIO flips
10549 */
10550static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10551{
10552 struct drm_device *dev = intel_crtc->base.dev;
10553 bool atomic_update;
10554 u32 start_vbl_count;
10555
10556 intel_mark_page_flip_active(intel_crtc);
10557
10558 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10559
10560 if (INTEL_INFO(dev)->gen >= 9)
10561 skl_do_mmio_flip(intel_crtc);
10562 else
10563 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10564 ilk_do_mmio_flip(intel_crtc);
10565
9362c7c5
ACO		 10566 if (atomic_update)
10567 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10568}
10569
9362c7c5 10570static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10571{
cc8c4cc2 10572 struct intel_crtc *crtc =
9362c7c5 10573 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10574 struct intel_mmio_flip *mmio_flip;
84c33a64 10575
cc8c4cc2
JH		 10576 mmio_flip = &crtc->mmio_flip;
10577 if (mmio_flip->req)
9c654818
JH		 10578 WARN_ON(__i915_wait_request(mmio_flip->req,
10579 crtc->reset_counter,
10580 false, NULL, NULL) != 0);
84c33a64 10581
cc8c4cc2
JH		 10582 intel_do_mmio_flip(crtc);
10583 if (mmio_flip->req) {
10584 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10585 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10586 mutex_unlock(&crtc->base.dev->struct_mutex);
10587 }
84c33a64
SG		 10588}
10589
10590static int intel_queue_mmio_flip(struct drm_device *dev,
10591 struct drm_crtc *crtc,
10592 struct drm_framebuffer *fb,
10593 struct drm_i915_gem_object *obj,
10594 struct intel_engine_cs *ring,
10595 uint32_t flags)
10596{
84c33a64 10597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10598
cc8c4cc2
JH		 10599 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10600 obj->last_write_req);
536f5b5e
ACO		 10601
10602 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10603
84c33a64
SG		 10604 return 0;
10605}
10606
8c9f3aaf
JB		 10607static int intel_default_queue_flip(struct drm_device *dev,
10608 struct drm_crtc *crtc,
10609 struct drm_framebuffer *fb,
ed8d1975 10610 struct drm_i915_gem_object *obj,
a4872ba6 10611 struct intel_engine_cs *ring,
ed8d1975 10612 uint32_t flags)
8c9f3aaf
JB		 10613{
10614 return -ENODEV;
10615}
10616
d6bbafa1
CW		 10617static bool __intel_pageflip_stall_check(struct drm_device *dev,
10618 struct drm_crtc *crtc)
10619{
10620 struct drm_i915_private *dev_priv = dev->dev_private;
10621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10622 struct intel_unpin_work *work = intel_crtc->unpin_work;
10623 u32 addr;
10624
10625 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10626 return true;
10627
10628 if (!work->enable_stall_check)
10629 return false;
10630
10631 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10632 if (work->flip_queued_req &&
10633 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10634 return false;
10635
1e3feefd 10636 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10637 }
10638
1e3feefd 10639 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10640 return false;
10641
10642 /* Potential stall - if we see that the flip has happened,
10643 * assume a missed interrupt. */
10644 if (INTEL_INFO(dev)->gen >= 4)
10645 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10646 else
10647 addr = I915_READ(DSPADDR(intel_crtc->plane));
10648
10649 /* There is a potential issue here with a false positive after a flip
10650 * to the same address. We could address this by checking for a
10651 * non-incrementing frame counter.
10652 */
10653 return addr == work->gtt_offset;
10654}
10655
10656void intel_check_page_flip(struct drm_device *dev, int pipe)
10657{
10658 struct drm_i915_private *dev_priv = dev->dev_private;
10659 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10661 struct intel_unpin_work *work;
f326038a 10662
6c51d46f 10663 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10664
10665 if (crtc == NULL)
10666 return;
10667
f326038a 10668 spin_lock(&dev->event_lock);
6ad790c0
CW		 10669 work = intel_crtc->unpin_work;
10670 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10671 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10672 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10673 page_flip_completed(intel_crtc);
6ad790c0 10674 work = NULL;
d6bbafa1 10675 }
6ad790c0
CW		 10676 if (work != NULL &&
10677 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10678 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10679 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10680}
10681
6b95a207
KH		 10682static int intel_crtc_page_flip(struct drm_crtc *crtc,
10683 struct drm_framebuffer *fb,
ed8d1975
KP		 10684 struct drm_pending_vblank_event *event,
10685 uint32_t page_flip_flags)
6b95a207
KH		 10686{
10687 struct drm_device *dev = crtc->dev;
10688 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10689 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10690 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10692 struct drm_plane *primary = crtc->primary;
a071fa00 10693 enum pipe pipe = intel_crtc->pipe;
6b95a207 10694 struct intel_unpin_work *work;
a4872ba6 10695 struct intel_engine_cs *ring;
cf5d8a46 10696 bool mmio_flip;
52e68630 10697 int ret;
6b95a207 10698
2ff8fde1
MR		 10699 /*
10700 * drm_mode_page_flip_ioctl() should already catch this, but double
10701 * check to be safe. In the future we may enable pageflipping from
10702 * a disabled primary plane.
10703 */
10704 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10705 return -EBUSY;
10706
e6a595d2 10707 /* Can't change pixel format via MI display flips. */
f4510a27 10708 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10709 return -EINVAL;
10710
10711 /*
10712 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10713 * Note that pitch changes could also affect these register.
10714 */
10715 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10716 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10717 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10718 return -EINVAL;
10719
f900db47
CW		 10720 if (i915_terminally_wedged(&dev_priv->gpu_error))
10721 goto out_hang;
10722
b14c5679 10723 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10724 if (work == NULL)
10725 return -ENOMEM;
10726
6b95a207 10727 work->event = event;
b4a98e57 10728 work->crtc = crtc;
ab8d6675 10729 work->old_fb = old_fb;
6b95a207
KH		 10730 INIT_WORK(&work->work, intel_unpin_work_fn);
10731
87b6b101 10732 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10733 if (ret)
10734 goto free_work;
10735
6b95a207 10736 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10737 spin_lock_irq(&dev->event_lock);
6b95a207 10738 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10739 /* Before declaring the flip queue wedged, check if
10740 * the hardware completed the operation behind our backs.
10741 */
10742 if (__intel_pageflip_stall_check(dev, crtc)) {
10743 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10744 page_flip_completed(intel_crtc);
10745 } else {
10746 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10747 spin_unlock_irq(&dev->event_lock);
468f0b44 10748
d6bbafa1
CW		 10749 drm_crtc_vblank_put(crtc);
10750 kfree(work);
10751 return -EBUSY;
10752 }
6b95a207
KH		 10753 }
10754 intel_crtc->unpin_work = work;
5e2d7afc 10755 spin_unlock_irq(&dev->event_lock);
6b95a207 10756
b4a98e57
CW		 10757 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10758 flush_workqueue(dev_priv->wq);
10759
75dfca80 10760 /* Reference the objects for the scheduled work. */
ab8d6675 10761 drm_framebuffer_reference(work->old_fb);
05394f39 10762 drm_gem_object_reference(&obj->base);
6b95a207 10763
f4510a27 10764 crtc->primary->fb = fb;
afd65eb4 10765 update_state_fb(crtc->primary);
1ed1f968 10766
e1f99ce6 10767 work->pending_flip_obj = obj;
e1f99ce6 10768
89ed88ba
CW		 10769 ret = i915_mutex_lock_interruptible(dev);
10770 if (ret)
10771 goto cleanup;
10772
b4a98e57 10773 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10774 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10775
75f7f3ec 10776 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10777 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10778
4fa62c89
VS		 10779 if (IS_VALLEYVIEW(dev)) {
10780 ring = &dev_priv->ring[BCS];
ab8d6675 10781 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10782 /* vlv: DISPLAY_FLIP fails to change tiling */
10783 ring = NULL;
48bf5b2d 10784 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10785 ring = &dev_priv->ring[BCS];
4fa62c89 10786 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10787 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10788 if (ring == NULL || ring->id != RCS)
10789 ring = &dev_priv->ring[BCS];
10790 } else {
10791 ring = &dev_priv->ring[RCS];
10792 }
10793
cf5d8a46
CW		 10794 mmio_flip = use_mmio_flip(ring, obj);
10795
10796 /* When using CS flips, we want to emit semaphores between rings.
10797 * However, when using mmio flips we will create a task to do the
10798 * synchronisation, so all we want here is to pin the framebuffer
10799 * into the display plane and skip any waits.
10800 */
82bc3b2d 10801 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10802 crtc->primary->state,
10803 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10804 if (ret)
10805 goto cleanup_pending;
6b95a207 10806
121920fa
TU		 10807 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10808 + intel_crtc->dspaddr_offset;
4fa62c89 10809
cf5d8a46 10810 if (mmio_flip) {
84c33a64
SG		 10811 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10812 page_flip_flags);
d6bbafa1
CW		 10813 if (ret)
10814 goto cleanup_unpin;
10815
f06cc1b9
JH		 10816 i915_gem_request_assign(&work->flip_queued_req,
10817 obj->last_write_req);
d6bbafa1 10818 } else {
84c33a64 10819 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10820 page_flip_flags);
10821 if (ret)
10822 goto cleanup_unpin;
10823
f06cc1b9
JH		 10824 i915_gem_request_assign(&work->flip_queued_req,
10825 intel_ring_get_request(ring));
d6bbafa1
CW		 10826 }
10827
1e3feefd 10828 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10829 work->enable_stall_check = true;
4fa62c89 10830
ab8d6675 10831 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10832 INTEL_FRONTBUFFER_PRIMARY(pipe));
10833
7ff0ebcc 10834 intel_fbc_disable(dev);
f99d7069 10835 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10836 mutex_unlock(&dev->struct_mutex);
10837
e5510fac
JB		 10838 trace_i915_flip_request(intel_crtc->plane, obj);
10839
6b95a207 10840 return 0;
96b099fd 10841
4fa62c89 10842cleanup_unpin:
82bc3b2d 10843 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10844cleanup_pending:
b4a98e57 10845 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10846 mutex_unlock(&dev->struct_mutex);
10847cleanup:
f4510a27 10848 crtc->primary->fb = old_fb;
afd65eb4 10849 update_state_fb(crtc->primary);
89ed88ba
CW		 10850
10851 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10852 drm_framebuffer_unreference(work->old_fb);
96b099fd 10853
5e2d7afc 10854 spin_lock_irq(&dev->event_lock);
96b099fd 10855 intel_crtc->unpin_work = NULL;
5e2d7afc 10856 spin_unlock_irq(&dev->event_lock);
96b099fd 10857
87b6b101 10858 drm_crtc_vblank_put(crtc);
7317c75e 10859free_work:
96b099fd
CW		 10860 kfree(work);
10861
f900db47
CW		 10862 if (ret == -EIO) {
10863out_hang:
53a366b9 10864 ret = intel_plane_restore(primary);
f0d3dad3 10865 if (ret == 0 && event) {
5e2d7afc 10866 spin_lock_irq(&dev->event_lock);
a071fa00 10867 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10868 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10869 }
f900db47 10870 }
96b099fd 10871 return ret;
6b95a207
KH		 10872}
10873
f6e5b160 10874static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10875 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10876 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10877 .atomic_begin = intel_begin_crtc_commit,
10878 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10879};
10880
9a935856
DV		 10881/**
10882 * intel_modeset_update_staged_output_state
10883 *
10884 * Updates the staged output configuration state, e.g. after we've read out the
10885 * current hw state.
10886 */
10887static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10888{
7668851f 10889 struct intel_crtc *crtc;
9a935856
DV		 10890 struct intel_encoder *encoder;
10891 struct intel_connector *connector;
f6e5b160 10892
3a3371ff 10893 for_each_intel_connector(dev, connector) {
9a935856
DV		 10894 connector->new_encoder =
10895 to_intel_encoder(connector->base.encoder);
10896 }
f6e5b160 10897
b2784e15 10898 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10899 encoder->new_crtc =
10900 to_intel_crtc(encoder->base.crtc);
10901 }
7668851f 10902
d3fcc808 10903 for_each_intel_crtc(dev, crtc) {
83d65738 10904 crtc->new_enabled = crtc->base.state->enable;
7668851f 10905 }
f6e5b160
CW		 10906}
10907
d29b2f9d
ACO		 10908/* Transitional helper to copy current connector/encoder state to
10909 * connector->state. This is needed so that code that is partially
10910 * converted to atomic does the right thing.
10911 */
10912static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10913{
10914 struct intel_connector *connector;
10915
10916 for_each_intel_connector(dev, connector) {
10917 if (connector->base.encoder) {
10918 connector->base.state->best_encoder =
10919 connector->base.encoder;
10920 connector->base.state->crtc =
10921 connector->base.encoder->crtc;
10922 } else {
10923 connector->base.state->best_encoder = NULL;
10924 connector->base.state->crtc = NULL;
10925 }
10926 }
10927}
10928
9a935856
DV		 10929/**
10930 * intel_modeset_commit_output_state
10931 *
10932 * This function copies the stage display pipe configuration to the real one.
10933 */
10934static void intel_modeset_commit_output_state(struct drm_device *dev)
10935{
7668851f 10936 struct intel_crtc *crtc;
9a935856
DV		 10937 struct intel_encoder *encoder;
10938 struct intel_connector *connector;
f6e5b160 10939
3a3371ff 10940 for_each_intel_connector(dev, connector) {
9a935856
DV		 10941 connector->base.encoder = &connector->new_encoder->base;
10942 }
f6e5b160 10943
b2784e15 10944 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10945 encoder->base.crtc = &encoder->new_crtc->base;
10946 }
7668851f 10947
d3fcc808 10948 for_each_intel_crtc(dev, crtc) {
83d65738 10949 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10950 crtc->base.enabled = crtc->new_enabled;
10951 }
d29b2f9d
ACO		 10952
10953 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10954}
10955
050f7aeb 10956static void
eba905b2 10957connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10958 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10959{
10960 int bpp = pipe_config->pipe_bpp;
10961
10962 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10963 connector->base.base.id,
c23cc417 10964 connector->base.name);
050f7aeb
DV		 10965
10966 /* Don't use an invalid EDID bpc value */
10967 if (connector->base.display_info.bpc &&
10968 connector->base.display_info.bpc * 3 < bpp) {
10969 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10970 bpp, connector->base.display_info.bpc*3);
10971 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10972 }
10973
10974 /* Clamp bpp to 8 on screens without EDID 1.4 */
10975 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10976 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10977 bpp);
10978 pipe_config->pipe_bpp = 24;
10979 }
10980}
10981
4e53c2e0 10982static int
050f7aeb
DV		 10983compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10984 struct drm_framebuffer *fb,
5cec258b 10985 struct intel_crtc_state *pipe_config)
4e53c2e0 10986{
050f7aeb 10987 struct drm_device *dev = crtc->base.dev;
1486017f 10988 struct drm_atomic_state *state;
050f7aeb 10989 struct intel_connector *connector;
1486017f 10990 int bpp, i;
4e53c2e0 10991
d42264b1
DV		 10992 switch (fb->pixel_format) {
10993 case DRM_FORMAT_C8:
4e53c2e0
DV		 10994 bpp = 8*3; /* since we go through a colormap */
10995 break;
d42264b1
DV		 10996 case DRM_FORMAT_XRGB1555:
10997 case DRM_FORMAT_ARGB1555:
10998 /* checked in intel_framebuffer_init already */
10999 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
11000 return -EINVAL;
11001 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 11002 bpp = 6*3; /* min is 18bpp */
11003 break;
d42264b1
DV		 11004 case DRM_FORMAT_XBGR8888:
11005 case DRM_FORMAT_ABGR8888:
11006 /* checked in intel_framebuffer_init already */
11007 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
11008 return -EINVAL;
11009 case DRM_FORMAT_XRGB8888:
11010 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 11011 bpp = 8*3;
11012 break;
d42264b1
DV		 11013 case DRM_FORMAT_XRGB2101010:
11014 case DRM_FORMAT_ARGB2101010:
11015 case DRM_FORMAT_XBGR2101010:
11016 case DRM_FORMAT_ABGR2101010:
11017 /* checked in intel_framebuffer_init already */
11018 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 11019 return -EINVAL;
4e53c2e0
DV		 11020 bpp = 10*3;
11021 break;
baba133a 11022 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 11023 default:
11024 DRM_DEBUG_KMS("unsupported depth\n");
11025 return -EINVAL;
11026 }
11027
4e53c2e0
DV		 11028 pipe_config->pipe_bpp = bpp;
11029
1486017f
ACO		 11030 state = pipe_config->base.state;
11031
4e53c2e0 11032 /* Clamp display bpp to EDID value */
1486017f
ACO		 11033 for (i = 0; i < state->num_connector; i++) {
11034 if (!state->connectors[i])
11035 continue;
11036
11037 connector = to_intel_connector(state->connectors[i]);
11038 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 11039 continue;
11040
050f7aeb 11041 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 11042 }
11043
11044 return bpp;
11045}
11046
644db711
DV		 11047static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11048{
11049 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11050 "type: 0x%x flags: 0x%x\n",
1342830c 11051 mode->crtc_clock,
644db711
DV		 11052 mode->crtc_hdisplay, mode->crtc_hsync_start,
11053 mode->crtc_hsync_end, mode->crtc_htotal,
11054 mode->crtc_vdisplay, mode->crtc_vsync_start,
11055 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11056}
11057
c0b03411 11058static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11059 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11060 const char *context)
11061{
6a60cd87
CK		 11062 struct drm_device *dev = crtc->base.dev;
11063 struct drm_plane *plane;
11064 struct intel_plane *intel_plane;
11065 struct intel_plane_state *state;
11066 struct drm_framebuffer *fb;
11067
11068 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11069 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11070
11071 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11072 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11073 pipe_config->pipe_bpp, pipe_config->dither);
11074 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11075 pipe_config->has_pch_encoder,
11076 pipe_config->fdi_lanes,
11077 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11078 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11079 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11080 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11081 pipe_config->has_dp_encoder,
11082 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11083 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11084 pipe_config->dp_m_n.tu);
b95af8be
VK		 11085
11086 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11087 pipe_config->has_dp_encoder,
11088 pipe_config->dp_m2_n2.gmch_m,
11089 pipe_config->dp_m2_n2.gmch_n,
11090 pipe_config->dp_m2_n2.link_m,
11091 pipe_config->dp_m2_n2.link_n,
11092 pipe_config->dp_m2_n2.tu);
11093
55072d19
DV		 11094 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11095 pipe_config->has_audio,
11096 pipe_config->has_infoframe);
11097
c0b03411 11098 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11099 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11100 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11101 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11102 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11103 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11104 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11105 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11106 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11107 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11108 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11109 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11110 pipe_config->gmch_pfit.control,
11111 pipe_config->gmch_pfit.pgm_ratios,
11112 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11113 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11114 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11115 pipe_config->pch_pfit.size,
11116 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11117 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11118 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11119
11120 DRM_DEBUG_KMS("planes on this crtc\n");
11121 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11122 intel_plane = to_intel_plane(plane);
11123 if (intel_plane->pipe != crtc->pipe)
11124 continue;
11125
11126 state = to_intel_plane_state(plane->state);
11127 fb = state->base.fb;
11128 if (!fb) {
11129 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11130 "disabled, scaler_id = %d\n",
11131 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11132 plane->base.id, intel_plane->pipe,
11133 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11134 drm_plane_index(plane), state->scaler_id);
11135 continue;
11136 }
11137
11138 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11139 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11140 plane->base.id, intel_plane->pipe,
11141 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11142 drm_plane_index(plane));
11143 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11144 fb->base.id, fb->width, fb->height, fb->pixel_format);
11145 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11146 state->scaler_id,
11147 state->src.x1 >> 16, state->src.y1 >> 16,
11148 drm_rect_width(&state->src) >> 16,
11149 drm_rect_height(&state->src) >> 16,
11150 state->dst.x1, state->dst.y1,
11151 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11152 }
c0b03411
DV		 11153}
11154
bc079e8b
VS		 11155static bool encoders_cloneable(const struct intel_encoder *a,
11156 const struct intel_encoder *b)
accfc0c5 11157{
bc079e8b
VS		 11158 /* masks could be asymmetric, so check both ways */
11159 return a == b || (a->cloneable & (1 << b->type) &&
11160 b->cloneable & (1 << a->type));
11161}
11162
98a221da
ACO		 11163static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11164 struct intel_crtc *crtc,
bc079e8b
VS		 11165 struct intel_encoder *encoder)
11166{
bc079e8b 11167 struct intel_encoder *source_encoder;
98a221da
ACO		 11168 struct drm_connector_state *connector_state;
11169 int i;
11170
11171 for (i = 0; i < state->num_connector; i++) {
11172 if (!state->connectors[i])
11173 continue;
bc079e8b 11174
98a221da
ACO		 11175 connector_state = state->connector_states[i];
11176 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11177 continue;
11178
98a221da
ACO		 11179 source_encoder =
11180 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11181 if (!encoders_cloneable(encoder, source_encoder))
11182 return false;
11183 }
11184
11185 return true;
11186}
11187
98a221da
ACO		 11188static bool check_encoder_cloning(struct drm_atomic_state *state,
11189 struct intel_crtc *crtc)
bc079e8b 11190{
accfc0c5 11191 struct intel_encoder *encoder;
98a221da
ACO		 11192 struct drm_connector_state *connector_state;
11193 int i;
accfc0c5 11194
98a221da
ACO		 11195 for (i = 0; i < state->num_connector; i++) {
11196 if (!state->connectors[i])
accfc0c5
DV		 11197 continue;
11198
98a221da
ACO		 11199 connector_state = state->connector_states[i];
11200 if (connector_state->crtc != &crtc->base)
11201 continue;
11202
11203 encoder = to_intel_encoder(connector_state->best_encoder);
11204 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11205 return false;
accfc0c5
DV		 11206 }
11207
bc079e8b 11208 return true;
accfc0c5
DV		 11209}
11210
5448a00d 11211static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11212{
5448a00d
ACO		 11213 struct drm_device *dev = state->dev;
11214 struct intel_encoder *encoder;
11215 struct drm_connector_state *connector_state;
00f0b378 11216 unsigned int used_ports = 0;
5448a00d 11217 int i;
00f0b378
VS		 11218
11219 /*
11220 * Walk the connector list instead of the encoder
11221 * list to detect the problem on ddi platforms
11222 * where there's just one encoder per digital port.
11223 */
5448a00d
ACO		 11224 for (i = 0; i < state->num_connector; i++) {
11225 if (!state->connectors[i])
11226 continue;
00f0b378 11227
5448a00d
ACO		 11228 connector_state = state->connector_states[i];
11229 if (!connector_state->best_encoder)
00f0b378
VS		 11230 continue;
11231
5448a00d
ACO		 11232 encoder = to_intel_encoder(connector_state->best_encoder);
11233
11234 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11235
11236 switch (encoder->type) {
11237 unsigned int port_mask;
11238 case INTEL_OUTPUT_UNKNOWN:
11239 if (WARN_ON(!HAS_DDI(dev)))
11240 break;
11241 case INTEL_OUTPUT_DISPLAYPORT:
11242 case INTEL_OUTPUT_HDMI:
11243 case INTEL_OUTPUT_EDP:
11244 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11245
11246 /* the same port mustn't appear more than once */
11247 if (used_ports & port_mask)
11248 return false;
11249
11250 used_ports |= port_mask;
11251 default:
11252 break;
11253 }
11254 }
11255
11256 return true;
11257}
11258
83a57153
ACO		 11259static void
11260clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11261{
11262 struct drm_crtc_state tmp_state;
663a3640 11263 struct intel_crtc_scaler_state scaler_state;
83a57153 11264
663a3640 11265 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11266 tmp_state = crtc_state->base;
663a3640 11267 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11268 memset(crtc_state, 0, sizeof *crtc_state);
11269 crtc_state->base = tmp_state;
663a3640 11270 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11271}
11272
5cec258b 11273static struct intel_crtc_state *
b8cecdf5 11274intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 11275 struct drm_framebuffer *fb,
83a57153
ACO		 11276 struct drm_display_mode *mode,
11277 struct drm_atomic_state *state)
ee7b9f93 11278{
7758a113 11279 struct intel_encoder *encoder;
0b901879
ACO		 11280 struct intel_connector *connector;
11281 struct drm_connector_state *connector_state;
5cec258b 11282 struct intel_crtc_state *pipe_config;
e29c22c0 11283 int plane_bpp, ret = -EINVAL;
0b901879 11284 int i;
e29c22c0 11285 bool retry = true;
ee7b9f93 11286
98a221da 11287 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11288 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11289 return ERR_PTR(-EINVAL);
11290 }
11291
5448a00d 11292 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11293 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11294 return ERR_PTR(-EINVAL);
11295 }
11296
83a57153
ACO		 11297 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11298 if (IS_ERR(pipe_config))
11299 return pipe_config;
11300
11301 clear_intel_crtc_state(pipe_config);
7758a113 11302
07878248 11303 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11304 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11305 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11306
e143a21c
DV		 11307 pipe_config->cpu_transcoder =
11308 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11309 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11310
2960bc9c
ID		 11311 /*
11312 * Sanitize sync polarity flags based on requested ones. If neither
11313 * positive or negative polarity is requested, treat this as meaning
11314 * negative polarity.
11315 */
2d112de7 11316 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11317 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11318 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11319
2d112de7 11320 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11321 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11322 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11323
050f7aeb
DV		 11324 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11325 * plane pixel format and any sink constraints into account. Returns the
11326 * source plane bpp so that dithering can be selected on mismatches
11327 * after encoders and crtc also have had their say. */
11328 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11329 fb, pipe_config);
4e53c2e0
DV		 11330 if (plane_bpp < 0)
11331 goto fail;
11332
e41a56be
VS		 11333 /*
11334 * Determine the real pipe dimensions. Note that stereo modes can
11335 * increase the actual pipe size due to the frame doubling and
11336 * insertion of additional space for blanks between the frame. This
11337 * is stored in the crtc timings. We use the requested mode to do this
11338 * computation to clearly distinguish it from the adjusted mode, which
11339 * can be changed by the connectors in the below retry loop.
11340 */
2d112de7 11341 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11342 &pipe_config->pipe_src_w,
11343 &pipe_config->pipe_src_h);
e41a56be 11344
e29c22c0 11345encoder_retry:
ef1b460d 11346 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11347 pipe_config->port_clock = 0;
ef1b460d 11348 pipe_config->pixel_multiplier = 1;
ff9a6750 11349
135c81b8 11350 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11351 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11352 CRTC_STEREO_DOUBLE);
135c81b8 11353
7758a113
DV		 11354 /* Pass our mode to the connectors and the CRTC to give them a chance to
11355 * adjust it according to limitations or connector properties, and also
11356 * a chance to reject the mode entirely.
47f1c6c9 11357 */
0b901879
ACO		 11358 for (i = 0; i < state->num_connector; i++) {
11359 connector = to_intel_connector(state->connectors[i]);
11360 if (!connector)
11361 continue;
47f1c6c9 11362
0b901879
ACO		 11363 connector_state = state->connector_states[i];
11364 if (connector_state->crtc != crtc)
7758a113 11365 continue;
7ae89233 11366
0b901879
ACO		 11367 encoder = to_intel_encoder(connector_state->best_encoder);
11368
efea6e8e
DV		 11369 if (!(encoder->compute_config(encoder, pipe_config))) {
11370 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11371 goto fail;
11372 }
ee7b9f93 11373 }
47f1c6c9 11374
ff9a6750
DV		 11375 /* Set default port clock if not overwritten by the encoder. Needs to be
11376 * done afterwards in case the encoder adjusts the mode. */
11377 if (!pipe_config->port_clock)
2d112de7 11378 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11379 * pipe_config->pixel_multiplier;
ff9a6750 11380
a43f6e0f 11381 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11382 if (ret < 0) {
7758a113
DV		 11383 DRM_DEBUG_KMS("CRTC fixup failed\n");
11384 goto fail;
ee7b9f93 11385 }
e29c22c0
DV		 11386
11387 if (ret == RETRY) {
11388 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11389 ret = -EINVAL;
11390 goto fail;
11391 }
11392
11393 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11394 retry = false;
11395 goto encoder_retry;
11396 }
11397
4e53c2e0
DV		 11398 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
11399 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11400 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11401
b8cecdf5 11402 return pipe_config;
7758a113 11403fail:
e29c22c0 11404 return ERR_PTR(ret);
ee7b9f93 11405}
47f1c6c9 11406
e2e1ed41
DV		 11407/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11408 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11409static void
11410intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11411 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11412{
11413 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11414 struct drm_device *dev = crtc->dev;
11415 struct intel_encoder *encoder;
11416 struct intel_connector *connector;
11417 struct drm_crtc *tmp_crtc;
79e53945 11418
e2e1ed41 11419 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11420
e2e1ed41
DV		 11421 /* Check which crtcs have changed outputs connected to them, these need
11422 * to be part of the prepare_pipes mask. We don't (yet) support global
11423 * modeset across multiple crtcs, so modeset_pipes will only have one
11424 * bit set at most. */
3a3371ff 11425 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11426 if (connector->base.encoder == &connector->new_encoder->base)
11427 continue;
79e53945 11428
e2e1ed41
DV		 11429 if (connector->base.encoder) {
11430 tmp_crtc = connector->base.encoder->crtc;
11431
11432 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11433 }
11434
11435 if (connector->new_encoder)
11436 *prepare_pipes |=
11437 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11438 }
11439
b2784e15 11440 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11441 if (encoder->base.crtc == &encoder->new_crtc->base)
11442 continue;
11443
11444 if (encoder->base.crtc) {
11445 tmp_crtc = encoder->base.crtc;
11446
11447 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11448 }
11449
11450 if (encoder->new_crtc)
11451 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11452 }
11453
7668851f 11454 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11455 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11456 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11457 continue;
7e7d76c3 11458
7668851f 11459 if (!intel_crtc->new_enabled)
e2e1ed41 11460 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11461 else
11462 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11463 }
11464
e2e1ed41
DV		 11465
11466 /* set_mode is also used to update properties on life display pipes. */
11467 intel_crtc = to_intel_crtc(crtc);
7668851f 11468 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11469 *prepare_pipes |= 1 << intel_crtc->pipe;
11470
b6c5164d
DV		 11471 /*
11472 * For simplicity do a full modeset on any pipe where the output routing
11473 * changed. We could be more clever, but that would require us to be
11474 * more careful with calling the relevant encoder->mode_set functions.
11475 */
e2e1ed41
DV		 11476 if (*prepare_pipes)
11477 *modeset_pipes = *prepare_pipes;
11478
11479 /* ... and mask these out. */
11480 *modeset_pipes &= ~(*disable_pipes);
11481 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11482
11483 /*
11484 * HACK: We don't (yet) fully support global modesets. intel_set_config
11485 * obies this rule, but the modeset restore mode of
11486 * intel_modeset_setup_hw_state does not.
11487 */
11488 *modeset_pipes &= 1 << intel_crtc->pipe;
11489 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11490
11491 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11492 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11493}
79e53945 11494
ea9d758d 11495static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11496{
ea9d758d 11497 struct drm_encoder *encoder;
f6e5b160 11498 struct drm_device *dev = crtc->dev;
f6e5b160 11499
ea9d758d
DV		 11500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11501 if (encoder->crtc == crtc)
11502 return true;
11503
11504 return false;
11505}
11506
11507static void
11508intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11509{
ba41c0de 11510 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11511 struct intel_encoder *intel_encoder;
11512 struct intel_crtc *intel_crtc;
11513 struct drm_connector *connector;
11514
ba41c0de
DV		 11515 intel_shared_dpll_commit(dev_priv);
11516
b2784e15 11517 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11518 if (!intel_encoder->base.crtc)
11519 continue;
11520
11521 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11522
11523 if (prepare_pipes & (1 << intel_crtc->pipe))
11524 intel_encoder->connectors_active = false;
11525 }
11526
11527 intel_modeset_commit_output_state(dev);
11528
7668851f 11529 /* Double check state. */
d3fcc808 11530 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11531 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11532 }
11533
11534 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11535 if (!connector->encoder || !connector->encoder->crtc)
11536 continue;
11537
11538 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11539
11540 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11541 struct drm_property *dpms_property =
11542 dev->mode_config.dpms_property;
11543
ea9d758d 11544 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11545 drm_object_property_set_value(&connector->base,
68d34720
DV		 11546 dpms_property,
11547 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11548
11549 intel_encoder = to_intel_encoder(connector->encoder);
11550 intel_encoder->connectors_active = true;
11551 }
11552 }
11553
11554}
11555
3bd26263 11556static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11557{
3bd26263 11558 int diff;
f1f644dc
JB		 11559
11560 if (clock1 == clock2)
11561 return true;
11562
11563 if (!clock1 || !clock2)
11564 return false;
11565
11566 diff = abs(clock1 - clock2);
11567
11568 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11569 return true;
11570
11571 return false;
11572}
11573
25c5b266
DV		 11574#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11575 list_for_each_entry((intel_crtc), \
11576 &(dev)->mode_config.crtc_list, \
11577 base.head) \
0973f18f 11578 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11579
0e8ffe1b 11580static bool
2fa2fe9a 11581intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11582 struct intel_crtc_state *current_config,
11583 struct intel_crtc_state *pipe_config)
0e8ffe1b 11584{
66e985c0
DV		 11585#define PIPE_CONF_CHECK_X(name) \
11586 if (current_config->name != pipe_config->name) { \
11587 DRM_ERROR("mismatch in " #name " " \
11588 "(expected 0x%08x, found 0x%08x)\n", \
11589 current_config->name, \
11590 pipe_config->name); \
11591 return false; \
11592 }
11593
08a24034
DV		 11594#define PIPE_CONF_CHECK_I(name) \
11595 if (current_config->name != pipe_config->name) { \
11596 DRM_ERROR("mismatch in " #name " " \
11597 "(expected %i, found %i)\n", \
11598 current_config->name, \
11599 pipe_config->name); \
11600 return false; \
88adfff1
DV		 11601 }
11602
b95af8be
VK		 11603/* This is required for BDW+ where there is only one set of registers for
11604 * switching between high and low RR.
11605 * This macro can be used whenever a comparison has to be made between one
11606 * hw state and multiple sw state variables.
11607 */
11608#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11609 if ((current_config->name != pipe_config->name) && \
11610 (current_config->alt_name != pipe_config->name)) { \
11611 DRM_ERROR("mismatch in " #name " " \
11612 "(expected %i or %i, found %i)\n", \
11613 current_config->name, \
11614 current_config->alt_name, \
11615 pipe_config->name); \
11616 return false; \
11617 }
11618
1bd1bd80
DV		 11619#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11620 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11621 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11622 "(expected %i, found %i)\n", \
11623 current_config->name & (mask), \
11624 pipe_config->name & (mask)); \
11625 return false; \
11626 }
11627
5e550656
VS		 11628#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11629 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11630 DRM_ERROR("mismatch in " #name " " \
11631 "(expected %i, found %i)\n", \
11632 current_config->name, \
11633 pipe_config->name); \
11634 return false; \
11635 }
11636
bb760063
DV		 11637#define PIPE_CONF_QUIRK(quirk) \
11638 ((current_config->quirks | pipe_config->quirks) & (quirk))
11639
eccb140b
DV		 11640 PIPE_CONF_CHECK_I(cpu_transcoder);
11641
08a24034
DV		 11642 PIPE_CONF_CHECK_I(has_pch_encoder);
11643 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11644 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11645 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11646 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11647 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11648 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11649
eb14cb74 11650 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11651
11652 if (INTEL_INFO(dev)->gen < 8) {
11653 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11654 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11655 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11656 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11657 PIPE_CONF_CHECK_I(dp_m_n.tu);
11658
11659 if (current_config->has_drrs) {
11660 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11661 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11662 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11663 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11664 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11665 }
11666 } else {
11667 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11668 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11669 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11670 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11671 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11672 }
eb14cb74 11673
2d112de7
ACO		 11674 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11675 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11676 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11677 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11678 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11679 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11680
2d112de7
ACO		 11681 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11682 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11683 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11684 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11685 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11686 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11687
c93f54cf 11688 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11689 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11690 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11691 IS_VALLEYVIEW(dev))
11692 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11693 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11694
9ed109a7
DV		 11695 PIPE_CONF_CHECK_I(has_audio);
11696
2d112de7 11697 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11698 DRM_MODE_FLAG_INTERLACE);
11699
bb760063 11700 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11701 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11702 DRM_MODE_FLAG_PHSYNC);
2d112de7 11703 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11704 DRM_MODE_FLAG_NHSYNC);
2d112de7 11705 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11706 DRM_MODE_FLAG_PVSYNC);
2d112de7 11707 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11708 DRM_MODE_FLAG_NVSYNC);
11709 }
045ac3b5 11710
37327abd
VS		 11711 PIPE_CONF_CHECK_I(pipe_src_w);
11712 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11713
9953599b
DV		 11714 /*
11715 * FIXME: BIOS likes to set up a cloned config with lvds+external
11716 * screen. Since we don't yet re-compute the pipe config when moving
11717 * just the lvds port away to another pipe the sw tracking won't match.
11718 *
11719 * Proper atomic modesets with recomputed global state will fix this.
11720 * Until then just don't check gmch state for inherited modes.
11721 */
11722 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11723 PIPE_CONF_CHECK_I(gmch_pfit.control);
11724 /* pfit ratios are autocomputed by the hw on gen4+ */
11725 if (INTEL_INFO(dev)->gen < 4)
11726 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11727 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11728 }
11729
fd4daa9c
CW		 11730 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11731 if (current_config->pch_pfit.enabled) {
11732 PIPE_CONF_CHECK_I(pch_pfit.pos);
11733 PIPE_CONF_CHECK_I(pch_pfit.size);
11734 }
2fa2fe9a 11735
a1b2278e
CK		 11736 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11737
e59150dc
JB		 11738 /* BDW+ don't expose a synchronous way to read the state */
11739 if (IS_HASWELL(dev))
11740 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11741
282740f7
VS		 11742 PIPE_CONF_CHECK_I(double_wide);
11743
26804afd
DV		 11744 PIPE_CONF_CHECK_X(ddi_pll_sel);
11745
c0d43d62 11746 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11747 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11748 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11749 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11750 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11751 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11752 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11753 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11754 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11755
42571aef
VS		 11756 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11757 PIPE_CONF_CHECK_I(pipe_bpp);
11758
2d112de7 11759 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11760 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11761
66e985c0 11762#undef PIPE_CONF_CHECK_X
08a24034 11763#undef PIPE_CONF_CHECK_I
b95af8be 11764#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11765#undef PIPE_CONF_CHECK_FLAGS
5e550656 11766#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11767#undef PIPE_CONF_QUIRK
88adfff1 11768
0e8ffe1b
DV		 11769 return true;
11770}
11771
08db6652
DL		 11772static void check_wm_state(struct drm_device *dev)
11773{
11774 struct drm_i915_private *dev_priv = dev->dev_private;
11775 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11776 struct intel_crtc *intel_crtc;
11777 int plane;
11778
11779 if (INTEL_INFO(dev)->gen < 9)
11780 return;
11781
11782 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11783 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11784
11785 for_each_intel_crtc(dev, intel_crtc) {
11786 struct skl_ddb_entry *hw_entry, *sw_entry;
11787 const enum pipe pipe = intel_crtc->pipe;
11788
11789 if (!intel_crtc->active)
11790 continue;
11791
11792 /* planes */
dd740780 11793 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11794 hw_entry = &hw_ddb.plane[pipe][plane];
11795 sw_entry = &sw_ddb->plane[pipe][plane];
11796
11797 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11798 continue;
11799
11800 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11801 "(expected (%u,%u), found (%u,%u))\n",
11802 pipe_name(pipe), plane + 1,
11803 sw_entry->start, sw_entry->end,
11804 hw_entry->start, hw_entry->end);
11805 }
11806
11807 /* cursor */
11808 hw_entry = &hw_ddb.cursor[pipe];
11809 sw_entry = &sw_ddb->cursor[pipe];
11810
11811 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11812 continue;
11813
11814 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11815 "(expected (%u,%u), found (%u,%u))\n",
11816 pipe_name(pipe),
11817 sw_entry->start, sw_entry->end,
11818 hw_entry->start, hw_entry->end);
11819 }
11820}
11821
91d1b4bd
DV		 11822static void
11823check_connector_state(struct drm_device *dev)
8af6cf88 11824{
8af6cf88
DV		 11825 struct intel_connector *connector;
11826
3a3371ff 11827 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11828 /* This also checks the encoder/connector hw state with the
11829 * ->get_hw_state callbacks. */
11830 intel_connector_check_state(connector);
11831
e2c719b7 11832 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11833 "connector's staged encoder doesn't match current encoder\n");
11834 }
91d1b4bd
DV		 11835}
11836
11837static void
11838check_encoder_state(struct drm_device *dev)
11839{
11840 struct intel_encoder *encoder;
11841 struct intel_connector *connector;
8af6cf88 11842
b2784e15 11843 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11844 bool enabled = false;
11845 bool active = false;
11846 enum pipe pipe, tracked_pipe;
11847
11848 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11849 encoder->base.base.id,
8e329a03 11850 encoder->base.name);
8af6cf88 11851
e2c719b7 11852 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11853 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11854 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11855 "encoder's active_connectors set, but no crtc\n");
11856
3a3371ff 11857 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11858 if (connector->base.encoder != &encoder->base)
11859 continue;
11860 enabled = true;
11861 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11862 active = true;
11863 }
0e32b39c
DA		 11864 /*
11865 * for MST connectors if we unplug the connector is gone
11866 * away but the encoder is still connected to a crtc
11867 * until a modeset happens in response to the hotplug.
11868 */
11869 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11870 continue;
11871
e2c719b7 11872 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11873 "encoder's enabled state mismatch "
11874 "(expected %i, found %i)\n",
11875 !!encoder->base.crtc, enabled);
e2c719b7 11876 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11877 "active encoder with no crtc\n");
11878
e2c719b7 11879 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11880 "encoder's computed active state doesn't match tracked active state "
11881 "(expected %i, found %i)\n", active, encoder->connectors_active);
11882
11883 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11884 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11885 "encoder's hw state doesn't match sw tracking "
11886 "(expected %i, found %i)\n",
11887 encoder->connectors_active, active);
11888
11889 if (!encoder->base.crtc)
11890 continue;
11891
11892 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11893 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11894 "active encoder's pipe doesn't match"
11895 "(expected %i, found %i)\n",
11896 tracked_pipe, pipe);
11897
11898 }
91d1b4bd
DV		 11899}
11900
11901static void
11902check_crtc_state(struct drm_device *dev)
11903{
fbee40df 11904 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11905 struct intel_crtc *crtc;
11906 struct intel_encoder *encoder;
5cec258b 11907 struct intel_crtc_state pipe_config;
8af6cf88 11908
d3fcc808 11909 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11910 bool enabled = false;
11911 bool active = false;
11912
045ac3b5
JB		 11913 memset(&pipe_config, 0, sizeof(pipe_config));
11914
8af6cf88
DV		 11915 DRM_DEBUG_KMS("[CRTC:%d]\n",
11916 crtc->base.base.id);
11917
83d65738 11918 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11919 "active crtc, but not enabled in sw tracking\n");
11920
b2784e15 11921 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11922 if (encoder->base.crtc != &crtc->base)
11923 continue;
11924 enabled = true;
11925 if (encoder->connectors_active)
11926 active = true;
11927 }
6c49f241 11928
e2c719b7 11929 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11930 "crtc's computed active state doesn't match tracked active state "
11931 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11932 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11933 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11934 "(expected %i, found %i)\n", enabled,
11935 crtc->base.state->enable);
8af6cf88 11936
0e8ffe1b
DV		 11937 active = dev_priv->display.get_pipe_config(crtc,
11938 &pipe_config);
d62cf62a 11939
b6b5d049
VS		 11940 /* hw state is inconsistent with the pipe quirk */
11941 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11942 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11943 active = crtc->active;
11944
b2784e15 11945 for_each_intel_encoder(dev, encoder) {
3eaba51c 11946 enum pipe pipe;
6c49f241
DV		 11947 if (encoder->base.crtc != &crtc->base)
11948 continue;
1d37b689 11949 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11950 encoder->get_config(encoder, &pipe_config);
11951 }
11952
e2c719b7 11953 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11954 "crtc active state doesn't match with hw state "
11955 "(expected %i, found %i)\n", crtc->active, active);
11956
c0b03411 11957 if (active &&
6e3c9717 11958 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11959 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11960 intel_dump_pipe_config(crtc, &pipe_config,
11961 "[hw state]");
6e3c9717 11962 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11963 "[sw state]");
11964 }
8af6cf88
DV		 11965 }
11966}
11967
91d1b4bd
DV		 11968static void
11969check_shared_dpll_state(struct drm_device *dev)
11970{
fbee40df 11971 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11972 struct intel_crtc *crtc;
11973 struct intel_dpll_hw_state dpll_hw_state;
11974 int i;
5358901f
DV		 11975
11976 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11977 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11978 int enabled_crtcs = 0, active_crtcs = 0;
11979 bool active;
11980
11981 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11982
11983 DRM_DEBUG_KMS("%s\n", pll->name);
11984
11985 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11986
e2c719b7 11987 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11988 "more active pll users than references: %i vs %i\n",
3e369b76 11989 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11990 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11991 "pll in active use but not on in sw tracking\n");
e2c719b7 11992 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11993 "pll in on but not on in use in sw tracking\n");
e2c719b7 11994 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11995 "pll on state mismatch (expected %i, found %i)\n",
11996 pll->on, active);
11997
d3fcc808 11998 for_each_intel_crtc(dev, crtc) {
83d65738 11999 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12000 enabled_crtcs++;
12001 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12002 active_crtcs++;
12003 }
e2c719b7 12004 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12005 "pll active crtcs mismatch (expected %i, found %i)\n",
12006 pll->active, active_crtcs);
e2c719b7 12007 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12008 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12009 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12010
e2c719b7 12011 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12012 sizeof(dpll_hw_state)),
12013 "pll hw state mismatch\n");
5358901f 12014 }
8af6cf88
DV		 12015}
12016
91d1b4bd
DV		 12017void
12018intel_modeset_check_state(struct drm_device *dev)
12019{
08db6652 12020 check_wm_state(dev);
91d1b4bd
DV		 12021 check_connector_state(dev);
12022 check_encoder_state(dev);
12023 check_crtc_state(dev);
12024 check_shared_dpll_state(dev);
12025}
12026
5cec258b 12027void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12028 int dotclock)
12029{
12030 /*
12031 * FDI already provided one idea for the dotclock.
12032 * Yell if the encoder disagrees.
12033 */
2d112de7 12034 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12035 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12036 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12037}
12038
80715b2f
VS		 12039static void update_scanline_offset(struct intel_crtc *crtc)
12040{
12041 struct drm_device *dev = crtc->base.dev;
12042
12043 /*
12044 * The scanline counter increments at the leading edge of hsync.
12045 *
12046 * On most platforms it starts counting from vtotal-1 on the
12047 * first active line. That means the scanline counter value is
12048 * always one less than what we would expect. Ie. just after
12049 * start of vblank, which also occurs at start of hsync (on the
12050 * last active line), the scanline counter will read vblank_start-1.
12051 *
12052 * On gen2 the scanline counter starts counting from 1 instead
12053 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12054 * to keep the value positive), instead of adding one.
12055 *
12056 * On HSW+ the behaviour of the scanline counter depends on the output
12057 * type. For DP ports it behaves like most other platforms, but on HDMI
12058 * there's an extra 1 line difference. So we need to add two instead of
12059 * one to the value.
12060 */
12061 if (IS_GEN2(dev)) {
6e3c9717 12062 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12063 int vtotal;
12064
12065 vtotal = mode->crtc_vtotal;
12066 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12067 vtotal /= 2;
12068
12069 crtc->scanline_offset = vtotal - 1;
12070 } else if (HAS_DDI(dev) &&
409ee761 12071 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12072 crtc->scanline_offset = 2;
12073 } else
12074 crtc->scanline_offset = 1;
12075}
12076
5cec258b 12077static struct intel_crtc_state *
7f27126e
JB		 12078intel_modeset_compute_config(struct drm_crtc *crtc,
12079 struct drm_display_mode *mode,
12080 struct drm_framebuffer *fb,
83a57153 12081 struct drm_atomic_state *state,
7f27126e
JB		 12082 unsigned *modeset_pipes,
12083 unsigned *prepare_pipes,
12084 unsigned *disable_pipes)
12085{
db7542dd 12086 struct drm_device *dev = crtc->dev;
5cec258b 12087 struct intel_crtc_state *pipe_config = NULL;
db7542dd 12088 struct intel_crtc *intel_crtc;
0b901879
ACO		 12089 int ret = 0;
12090
12091 ret = drm_atomic_add_affected_connectors(state, crtc);
12092 if (ret)
12093 return ERR_PTR(ret);
7f27126e
JB		 12094
12095 intel_modeset_affected_pipes(crtc, modeset_pipes,
12096 prepare_pipes, disable_pipes);
12097
db7542dd
ACO		 12098 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
12099 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12100 if (IS_ERR(pipe_config))
12101 return pipe_config;
12102
12103 pipe_config->base.enable = false;
12104 }
7f27126e
JB		 12105
12106 /*
12107 * Note this needs changes when we start tracking multiple modes
12108 * and crtcs. At that point we'll need to compute the whole config
12109 * (i.e. one pipe_config for each crtc) rather than just the one
12110 * for this crtc.
12111 */
db7542dd
ACO		 12112 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
12113 /* FIXME: For now we still expect modeset_pipes has at most
12114 * one bit set. */
12115 if (WARN_ON(&intel_crtc->base != crtc))
12116 continue;
83a57153 12117
db7542dd
ACO		 12118 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
12119 if (IS_ERR(pipe_config))
12120 return pipe_config;
7f27126e 12121
304603f4
ACO		 12122 pipe_config->base.enable = true;
12123
db7542dd
ACO		 12124 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12125 "[modeset]");
12126 }
12127
12128 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 12129}
12130
225da59b 12131static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 12132 unsigned modeset_pipes,
12133 unsigned disable_pipes)
12134{
225da59b 12135 struct drm_device *dev = state->dev;
ed6739ef
ACO		 12136 struct drm_i915_private *dev_priv = to_i915(dev);
12137 unsigned clear_pipes = modeset_pipes | disable_pipes;
12138 struct intel_crtc *intel_crtc;
12139 int ret = 0;
12140
12141 if (!dev_priv->display.crtc_compute_clock)
12142 return 0;
12143
12144 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12145 if (ret)
12146 goto done;
12147
12148 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 12149 struct intel_crtc_state *crtc_state =
12150 intel_atomic_get_crtc_state(state, intel_crtc);
12151
12152 /* Modeset pipes should have a new state by now */
12153 if (WARN_ON(IS_ERR(crtc_state)))
12154 continue;
12155
ed6739ef 12156 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 12157 crtc_state);
ed6739ef
ACO		 12158 if (ret) {
12159 intel_shared_dpll_abort_config(dev_priv);
12160 goto done;
12161 }
12162 }
12163
12164done:
12165 return ret;
12166}
12167
f30da187
DV		 12168static int __intel_set_mode(struct drm_crtc *crtc,
12169 struct drm_display_mode *mode,
7f27126e 12170 int x, int y, struct drm_framebuffer *fb,
5cec258b 12171 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12172 unsigned modeset_pipes,
12173 unsigned prepare_pipes,
12174 unsigned disable_pipes)
a6778b3c
DV		 12175{
12176 struct drm_device *dev = crtc->dev;
fbee40df 12177 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 12178 struct drm_display_mode *saved_mode;
304603f4 12179 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12180 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12181 struct intel_crtc *intel_crtc;
c0c36b94 12182 int ret = 0;
a6778b3c 12183
4b4b9238 12184 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 12185 if (!saved_mode)
12186 return -ENOMEM;
a6778b3c 12187
83a57153
ACO		 12188 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12189 if (!crtc_state_copy) {
12190 ret = -ENOMEM;
12191 goto done;
12192 }
12193
3ac18232 12194 *saved_mode = crtc->mode;
a6778b3c 12195
30a970c6
JB		 12196 /*
12197 * See if the config requires any additional preparation, e.g.
12198 * to adjust global state with pipes off. We need to do this
12199 * here so we can get the modeset_pipe updated config for the new
12200 * mode set on this crtc. For other crtcs we need to use the
12201 * adjusted_mode bits in the crtc directly.
12202 */
f8437dd1 12203 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
304603f4
ACO		 12204 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
12205 if (ret)
12206 goto done;
30a970c6 12207
c164f833
VS		 12208 /* may have added more to prepare_pipes than we should */
12209 prepare_pipes &= ~disable_pipes;
12210 }
12211
225da59b 12212 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 12213 if (ret)
12214 goto done;
8bd31e67 12215
460da916
DV		 12216 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12217 intel_crtc_disable(&intel_crtc->base);
12218
ea9d758d 12219 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 12220 if (intel_crtc->base.state->enable)
ea9d758d
DV		 12221 dev_priv->display.crtc_disable(&intel_crtc->base);
12222 }
a6778b3c 12223
6c4c86f5
DV		 12224 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12225 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12226 *
12227 * Note we'll need to fix this up when we start tracking multiple
12228 * pipes; here we assume a single modeset_pipe and only track the
12229 * single crtc and mode.
f6e5b160 12230 */
b8cecdf5 12231 if (modeset_pipes) {
25c5b266 12232 crtc->mode = *mode;
b8cecdf5
DV		 12233 /* mode_set/enable/disable functions rely on a correct pipe
12234 * config. */
f5de6e07 12235 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12236
12237 /*
12238 * Calculate and store various constants which
12239 * are later needed by vblank and swap-completion
12240 * timestamping. They are derived from true hwmode.
12241 */
12242 drm_calc_timestamping_constants(crtc,
2d112de7 12243 &pipe_config->base.adjusted_mode);
b8cecdf5 12244 }
7758a113 12245
ea9d758d
DV		 12246 /* Only after disabling all output pipelines that will be changed can we
12247 * update the the output configuration. */
12248 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12249
304603f4 12250 modeset_update_crtc_power_domains(state);
47fab737 12251
25c5b266 12252 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12253 struct drm_plane *primary = intel_crtc->base.primary;
12254 int vdisplay, hdisplay;
4c10794f 12255
455a6808 12256 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12257 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12258 fb, 0, 0,
12259 hdisplay, vdisplay,
12260 x << 16, y << 16,
12261 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12262 }
12263
12264 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12265 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12266 update_scanline_offset(intel_crtc);
12267
25c5b266 12268 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 12269 }
a6778b3c 12270
a6778b3c
DV		 12271 /* FIXME: add subpixel order */
12272done:
83d65738 12273 if (ret && crtc->state->enable)
3ac18232 12274 crtc->mode = *saved_mode;
a6778b3c 12275
83a57153
ACO		 12276 if (ret == 0 && pipe_config) {
12277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12278
12279 /* The pipe_config will be freed with the atomic state, so
12280 * make a copy. */
12281 memcpy(crtc_state_copy, intel_crtc->config,
12282 sizeof *crtc_state_copy);
12283 intel_crtc->config = crtc_state_copy;
12284 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12285 } else {
12286 kfree(crtc_state_copy);
12287 }
12288
3ac18232 12289 kfree(saved_mode);
a6778b3c 12290 return ret;
f6e5b160
CW		 12291}
12292
7f27126e
JB		 12293static int intel_set_mode_pipes(struct drm_crtc *crtc,
12294 struct drm_display_mode *mode,
12295 int x, int y, struct drm_framebuffer *fb,
5cec258b 12296 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12297 unsigned modeset_pipes,
12298 unsigned prepare_pipes,
12299 unsigned disable_pipes)
f30da187
DV		 12300{
12301 int ret;
12302
7f27126e
JB		 12303 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12304 prepare_pipes, disable_pipes);
f30da187
DV		 12305
12306 if (ret == 0)
12307 intel_modeset_check_state(crtc->dev);
12308
12309 return ret;
12310}
12311
7f27126e
JB		 12312static int intel_set_mode(struct drm_crtc *crtc,
12313 struct drm_display_mode *mode,
83a57153
ACO		 12314 int x, int y, struct drm_framebuffer *fb,
12315 struct drm_atomic_state *state)
7f27126e 12316{
5cec258b 12317 struct intel_crtc_state *pipe_config;
7f27126e 12318 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12319 int ret = 0;
7f27126e 12320
83a57153 12321 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 12322 &modeset_pipes,
12323 &prepare_pipes,
12324 &disable_pipes);
12325
83a57153
ACO		 12326 if (IS_ERR(pipe_config)) {
12327 ret = PTR_ERR(pipe_config);
12328 goto out;
12329 }
12330
12331 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12332 modeset_pipes, prepare_pipes,
12333 disable_pipes);
12334 if (ret)
12335 goto out;
7f27126e 12336
83a57153
ACO		 12337out:
12338 return ret;
7f27126e
JB		 12339}
12340
c0c36b94
CW		 12341void intel_crtc_restore_mode(struct drm_crtc *crtc)
12342{
83a57153
ACO		 12343 struct drm_device *dev = crtc->dev;
12344 struct drm_atomic_state *state;
12345 struct intel_encoder *encoder;
12346 struct intel_connector *connector;
12347 struct drm_connector_state *connector_state;
12348
12349 state = drm_atomic_state_alloc(dev);
12350 if (!state) {
12351 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12352 crtc->base.id);
12353 return;
12354 }
12355
12356 state->acquire_ctx = dev->mode_config.acquire_ctx;
12357
12358 /* The force restore path in the HW readout code relies on the staged
12359 * config still keeping the user requested config while the actual
12360 * state has been overwritten by the configuration read from HW. We
12361 * need to copy the staged config to the atomic state, otherwise the
12362 * mode set will just reapply the state the HW is already in. */
12363 for_each_intel_encoder(dev, encoder) {
12364 if (&encoder->new_crtc->base != crtc)
12365 continue;
12366
12367 for_each_intel_connector(dev, connector) {
12368 if (connector->new_encoder != encoder)
12369 continue;
12370
12371 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12372 if (IS_ERR(connector_state)) {
12373 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12374 connector->base.base.id,
12375 connector->base.name,
12376 PTR_ERR(connector_state));
12377 continue;
12378 }
12379
12380 connector_state->crtc = crtc;
12381 connector_state->best_encoder = &encoder->base;
12382 }
12383 }
12384
12385 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12386 state);
12387
12388 drm_atomic_state_free(state);
c0c36b94
CW		 12389}
12390
25c5b266
DV		 12391#undef for_each_intel_crtc_masked
12392
d9e55608
DV		 12393static void intel_set_config_free(struct intel_set_config *config)
12394{
12395 if (!config)
12396 return;
12397
1aa4b628
DV		 12398 kfree(config->save_connector_encoders);
12399 kfree(config->save_encoder_crtcs);
7668851f 12400 kfree(config->save_crtc_enabled);
d9e55608
DV		 12401 kfree(config);
12402}
12403
85f9eb71
DV		 12404static int intel_set_config_save_state(struct drm_device *dev,
12405 struct intel_set_config *config)
12406{
7668851f 12407 struct drm_crtc *crtc;
85f9eb71
DV		 12408 struct drm_encoder *encoder;
12409 struct drm_connector *connector;
12410 int count;
12411
7668851f
VS		 12412 config->save_crtc_enabled =
12413 kcalloc(dev->mode_config.num_crtc,
12414 sizeof(bool), GFP_KERNEL);
12415 if (!config->save_crtc_enabled)
12416 return -ENOMEM;
12417
1aa4b628
DV		 12418 config->save_encoder_crtcs =
12419 kcalloc(dev->mode_config.num_encoder,
12420 sizeof(struct drm_crtc *), GFP_KERNEL);
12421 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12422 return -ENOMEM;
12423
1aa4b628
DV		 12424 config->save_connector_encoders =
12425 kcalloc(dev->mode_config.num_connector,
12426 sizeof(struct drm_encoder *), GFP_KERNEL);
12427 if (!config->save_connector_encoders)
85f9eb71
DV		 12428 return -ENOMEM;
12429
12430 /* Copy data. Note that driver private data is not affected.
12431 * Should anything bad happen only the expected state is
12432 * restored, not the drivers personal bookkeeping.
12433 */
7668851f 12434 count = 0;
70e1e0ec 12435 for_each_crtc(dev, crtc) {
83d65738 12436 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12437 }
12438
85f9eb71
DV		 12439 count = 0;
12440 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12441 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12442 }
12443
12444 count = 0;
12445 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12446 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12447 }
12448
12449 return 0;
12450}
12451
12452static void intel_set_config_restore_state(struct drm_device *dev,
12453 struct intel_set_config *config)
12454{
7668851f 12455 struct intel_crtc *crtc;
9a935856
DV		 12456 struct intel_encoder *encoder;
12457 struct intel_connector *connector;
85f9eb71
DV		 12458 int count;
12459
7668851f 12460 count = 0;
d3fcc808 12461 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12462 crtc->new_enabled = config->save_crtc_enabled[count++];
12463 }
12464
85f9eb71 12465 count = 0;
b2784e15 12466 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12467 encoder->new_crtc =
12468 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12469 }
12470
12471 count = 0;
3a3371ff 12472 for_each_intel_connector(dev, connector) {
9a935856
DV		 12473 connector->new_encoder =
12474 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12475 }
12476}
12477
e3de42b6 12478static bool
2e57f47d 12479is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12480{
12481 int i;
12482
2e57f47d
CW		 12483 if (set->num_connectors == 0)
12484 return false;
12485
12486 if (WARN_ON(set->connectors == NULL))
12487 return false;
12488
12489 for (i = 0; i < set->num_connectors; i++)
12490 if (set->connectors[i]->encoder &&
12491 set->connectors[i]->encoder->crtc == set->crtc &&
12492 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12493 return true;
12494
12495 return false;
12496}
12497
5e2b584e
DV		 12498static void
12499intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12500 struct intel_set_config *config)
12501{
12502
12503 /* We should be able to check here if the fb has the same properties
12504 * and then just flip_or_move it */
2e57f47d
CW		 12505 if (is_crtc_connector_off(set)) {
12506 config->mode_changed = true;
f4510a27 12507 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12508 /*
12509 * If we have no fb, we can only flip as long as the crtc is
12510 * active, otherwise we need a full mode set. The crtc may
12511 * be active if we've only disabled the primary plane, or
12512 * in fastboot situations.
12513 */
f4510a27 12514 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12515 struct intel_crtc *intel_crtc =
12516 to_intel_crtc(set->crtc);
12517
3b150f08 12518 if (intel_crtc->active) {
319d9827
JB		 12519 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12520 config->fb_changed = true;
12521 } else {
12522 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12523 config->mode_changed = true;
12524 }
5e2b584e
DV		 12525 } else if (set->fb == NULL) {
12526 config->mode_changed = true;
72f4901e 12527 } else if (set->fb->pixel_format !=
f4510a27 12528 set->crtc->primary->fb->pixel_format) {
5e2b584e 12529 config->mode_changed = true;
e3de42b6 12530 } else {
5e2b584e 12531 config->fb_changed = true;
e3de42b6 12532 }
5e2b584e
DV		 12533 }
12534
835c5873 12535 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12536 config->fb_changed = true;
12537
12538 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12539 DRM_DEBUG_KMS("modes are different, full mode set\n");
12540 drm_mode_debug_printmodeline(&set->crtc->mode);
12541 drm_mode_debug_printmodeline(set->mode);
12542 config->mode_changed = true;
12543 }
a1d95703
CW		 12544
12545 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12546 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12547}
12548
2e431051 12549static int
9a935856
DV		 12550intel_modeset_stage_output_state(struct drm_device *dev,
12551 struct drm_mode_set *set,
944b0c76
ACO		 12552 struct intel_set_config *config,
12553 struct drm_atomic_state *state)
50f56119 12554{
9a935856 12555 struct intel_connector *connector;
944b0c76 12556 struct drm_connector_state *connector_state;
9a935856 12557 struct intel_encoder *encoder;
7668851f 12558 struct intel_crtc *crtc;
f3f08572 12559 int ro;
50f56119 12560
9abdda74 12561 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12562 * of connectors. For paranoia, double-check this. */
12563 WARN_ON(!set->fb && (set->num_connectors != 0));
12564 WARN_ON(set->fb && (set->num_connectors == 0));
12565
3a3371ff 12566 for_each_intel_connector(dev, connector) {
9a935856
DV		 12567 /* Otherwise traverse passed in connector list and get encoders
12568 * for them. */
50f56119 12569 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12570 if (set->connectors[ro] == &connector->base) {
0e32b39c 12571 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12572 break;
12573 }
12574 }
12575
9a935856
DV		 12576 /* If we disable the crtc, disable all its connectors. Also, if
12577 * the connector is on the changing crtc but not on the new
12578 * connector list, disable it. */
12579 if ((!set->fb || ro == set->num_connectors) &&
12580 connector->base.encoder &&
12581 connector->base.encoder->crtc == set->crtc) {
12582 connector->new_encoder = NULL;
12583
12584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12585 connector->base.base.id,
c23cc417 12586 connector->base.name);
9a935856
DV		 12587 }
12588
12589
12590 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12592 connector->base.base.id,
12593 connector->base.name);
5e2b584e 12594 config->mode_changed = true;
50f56119
DV		 12595 }
12596 }
9a935856 12597 /* connector->new_encoder is now updated for all connectors. */
50f56119 12598
9a935856 12599 /* Update crtc of enabled connectors. */
3a3371ff 12600 for_each_intel_connector(dev, connector) {
7668851f
VS		 12601 struct drm_crtc *new_crtc;
12602
9a935856 12603 if (!connector->new_encoder)
50f56119
DV		 12604 continue;
12605
9a935856 12606 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12607
12608 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12609 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12610 new_crtc = set->crtc;
12611 }
12612
12613 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12614 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12615 new_crtc)) {
5e2b584e 12616 return -EINVAL;
50f56119 12617 }
0e32b39c 12618 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12619
944b0c76
ACO		 12620 connector_state =
12621 drm_atomic_get_connector_state(state, &connector->base);
12622 if (IS_ERR(connector_state))
12623 return PTR_ERR(connector_state);
12624
12625 connector_state->crtc = new_crtc;
12626 connector_state->best_encoder = &connector->new_encoder->base;
12627
9a935856
DV		 12628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12629 connector->base.base.id,
c23cc417 12630 connector->base.name,
9a935856
DV		 12631 new_crtc->base.id);
12632 }
12633
12634 /* Check for any encoders that needs to be disabled. */
b2784e15 12635 for_each_intel_encoder(dev, encoder) {
5a65f358 12636 int num_connectors = 0;
3a3371ff 12637 for_each_intel_connector(dev, connector) {
9a935856
DV		 12638 if (connector->new_encoder == encoder) {
12639 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12640 num_connectors++;
9a935856
DV		 12641 }
12642 }
5a65f358
PZ		 12643
12644 if (num_connectors == 0)
12645 encoder->new_crtc = NULL;
12646 else if (num_connectors > 1)
12647 return -EINVAL;
12648
9a935856
DV		 12649 /* Only now check for crtc changes so we don't miss encoders
12650 * that will be disabled. */
12651 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12652 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12653 encoder->base.base.id,
12654 encoder->base.name);
5e2b584e 12655 config->mode_changed = true;
50f56119
DV		 12656 }
12657 }
9a935856 12658 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12659 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12660 connector_state =
12661 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12662 if (IS_ERR(connector_state))
12663 return PTR_ERR(connector_state);
944b0c76
ACO		 12664
12665 if (connector->new_encoder) {
0e32b39c
DA		 12666 if (connector->new_encoder != connector->encoder)
12667 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12668 } else {
12669 connector_state->crtc = NULL;
f61cccf3 12670 connector_state->best_encoder = NULL;
944b0c76 12671 }
0e32b39c 12672 }
d3fcc808 12673 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12674 crtc->new_enabled = false;
12675
b2784e15 12676 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12677 if (encoder->new_crtc == crtc) {
12678 crtc->new_enabled = true;
12679 break;
12680 }
12681 }
12682
83d65738 12683 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12684 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12685 crtc->base.base.id,
7668851f
VS		 12686 crtc->new_enabled ? "en" : "dis");
12687 config->mode_changed = true;
12688 }
12689 }
12690
2e431051
DV		 12691 return 0;
12692}
12693
7d00a1f5
VS		 12694static void disable_crtc_nofb(struct intel_crtc *crtc)
12695{
12696 struct drm_device *dev = crtc->base.dev;
12697 struct intel_encoder *encoder;
12698 struct intel_connector *connector;
12699
12700 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12701 pipe_name(crtc->pipe));
12702
3a3371ff 12703 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12704 if (connector->new_encoder &&
12705 connector->new_encoder->new_crtc == crtc)
12706 connector->new_encoder = NULL;
12707 }
12708
b2784e15 12709 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12710 if (encoder->new_crtc == crtc)
12711 encoder->new_crtc = NULL;
12712 }
12713
12714 crtc->new_enabled = false;
12715}
12716
2e431051
DV		 12717static int intel_crtc_set_config(struct drm_mode_set *set)
12718{
12719 struct drm_device *dev;
2e431051 12720 struct drm_mode_set save_set;
83a57153 12721 struct drm_atomic_state *state = NULL;
2e431051 12722 struct intel_set_config *config;
5cec258b 12723 struct intel_crtc_state *pipe_config;
50f52756 12724 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12725 int ret;
2e431051 12726
8d3e375e
DV		 12727 BUG_ON(!set);
12728 BUG_ON(!set->crtc);
12729 BUG_ON(!set->crtc->helper_private);
2e431051 12730
7e53f3a4
DV		 12731 /* Enforce sane interface api - has been abused by the fb helper. */
12732 BUG_ON(!set->mode && set->fb);
12733 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12734
2e431051
DV		 12735 if (set->fb) {
12736 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12737 set->crtc->base.id, set->fb->base.id,
12738 (int)set->num_connectors, set->x, set->y);
12739 } else {
12740 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12741 }
12742
12743 dev = set->crtc->dev;
12744
12745 ret = -ENOMEM;
12746 config = kzalloc(sizeof(*config), GFP_KERNEL);
12747 if (!config)
12748 goto out_config;
12749
12750 ret = intel_set_config_save_state(dev, config);
12751 if (ret)
12752 goto out_config;
12753
12754 save_set.crtc = set->crtc;
12755 save_set.mode = &set->crtc->mode;
12756 save_set.x = set->crtc->x;
12757 save_set.y = set->crtc->y;
f4510a27 12758 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12759
12760 /* Compute whether we need a full modeset, only an fb base update or no
12761 * change at all. In the future we might also check whether only the
12762 * mode changed, e.g. for LVDS where we only change the panel fitter in
12763 * such cases. */
12764 intel_set_config_compute_mode_changes(set, config);
12765
83a57153
ACO		 12766 state = drm_atomic_state_alloc(dev);
12767 if (!state) {
12768 ret = -ENOMEM;
12769 goto out_config;
12770 }
12771
12772 state->acquire_ctx = dev->mode_config.acquire_ctx;
12773
944b0c76 12774 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12775 if (ret)
12776 goto fail;
12777
50f52756 12778 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12779 set->fb, state,
50f52756
JB		 12780 &modeset_pipes,
12781 &prepare_pipes,
12782 &disable_pipes);
20664591 12783 if (IS_ERR(pipe_config)) {
6ac0483b 12784 ret = PTR_ERR(pipe_config);
50f52756 12785 goto fail;
20664591 12786 } else if (pipe_config) {
b9950a13 12787 if (pipe_config->has_audio !=
6e3c9717 12788 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12789 config->mode_changed = true;
12790
af15d2ce
JB		 12791 /*
12792 * Note we have an issue here with infoframes: current code
12793 * only updates them on the full mode set path per hw
12794 * requirements. So here we should be checking for any
12795 * required changes and forcing a mode set.
12796 */
20664591 12797 }
50f52756 12798
1f9954d0
JB		 12799 intel_update_pipe_size(to_intel_crtc(set->crtc));
12800
5e2b584e 12801 if (config->mode_changed) {
50f52756
JB		 12802 ret = intel_set_mode_pipes(set->crtc, set->mode,
12803 set->x, set->y, set->fb, pipe_config,
12804 modeset_pipes, prepare_pipes,
12805 disable_pipes);
5e2b584e 12806 } else if (config->fb_changed) {
3b150f08 12807 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12808 struct drm_plane *primary = set->crtc->primary;
12809 int vdisplay, hdisplay;
3b150f08 12810
455a6808 12811 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12812 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12813 0, 0, hdisplay, vdisplay,
12814 set->x << 16, set->y << 16,
12815 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12816
12817 /*
12818 * We need to make sure the primary plane is re-enabled if it
12819 * has previously been turned off.
12820 */
12821 if (!intel_crtc->primary_enabled && ret == 0) {
12822 WARN_ON(!intel_crtc->active);
fdd508a6 12823 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12824 }
12825
7ca51a3a
JB		 12826 /*
12827 * In the fastboot case this may be our only check of the
12828 * state after boot. It would be better to only do it on
12829 * the first update, but we don't have a nice way of doing that
12830 * (and really, set_config isn't used much for high freq page
12831 * flipping, so increasing its cost here shouldn't be a big
12832 * deal).
12833 */
d330a953 12834 if (i915.fastboot && ret == 0)
7ca51a3a 12835 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12836 }
12837
2d05eae1 12838 if (ret) {
bf67dfeb
DV		 12839 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12840 set->crtc->base.id, ret);
50f56119 12841fail:
2d05eae1 12842 intel_set_config_restore_state(dev, config);
50f56119 12843
83a57153
ACO		 12844 drm_atomic_state_clear(state);
12845
7d00a1f5
VS		 12846 /*
12847 * HACK: if the pipe was on, but we didn't have a framebuffer,
12848 * force the pipe off to avoid oopsing in the modeset code
12849 * due to fb==NULL. This should only happen during boot since
12850 * we don't yet reconstruct the FB from the hardware state.
12851 */
12852 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12853 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12854
2d05eae1
CW		 12855 /* Try to restore the config */
12856 if (config->mode_changed &&
12857 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12858 save_set.x, save_set.y, save_set.fb,
12859 state))
2d05eae1
CW		 12860 DRM_ERROR("failed to restore config after modeset failure\n");
12861 }
50f56119 12862
d9e55608 12863out_config:
83a57153
ACO		 12864 if (state)
12865 drm_atomic_state_free(state);
12866
d9e55608 12867 intel_set_config_free(config);
50f56119
DV		 12868 return ret;
12869}
f6e5b160
CW		 12870
12871static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12872 .gamma_set = intel_crtc_gamma_set,
50f56119 12873 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12874 .destroy = intel_crtc_destroy,
12875 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12876 .atomic_duplicate_state = intel_crtc_duplicate_state,
12877 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12878};
12879
5358901f
DV		 12880static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12881 struct intel_shared_dpll *pll,
12882 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12883{
5358901f 12884 uint32_t val;
ee7b9f93 12885
f458ebbc 12886 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12887 return false;
12888
5358901f 12889 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12890 hw_state->dpll = val;
12891 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12892 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12893
12894 return val & DPLL_VCO_ENABLE;
12895}
12896
15bdd4cf
DV		 12897static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12898 struct intel_shared_dpll *pll)
12899{
3e369b76
ACO		 12900 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12901 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12902}
12903
e7b903d2
DV		 12904static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12905 struct intel_shared_dpll *pll)
12906{
e7b903d2 12907 /* PCH refclock must be enabled first */
89eff4be 12908 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12909
3e369b76 12910 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12911
12912 /* Wait for the clocks to stabilize. */
12913 POSTING_READ(PCH_DPLL(pll->id));
12914 udelay(150);
12915
12916 /* The pixel multiplier can only be updated once the
12917 * DPLL is enabled and the clocks are stable.
12918 *
12919 * So write it again.
12920 */
3e369b76 12921 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12922 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12923 udelay(200);
12924}
12925
12926static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12927 struct intel_shared_dpll *pll)
12928{
12929 struct drm_device *dev = dev_priv->dev;
12930 struct intel_crtc *crtc;
e7b903d2
DV		 12931
12932 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12933 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12934 if (intel_crtc_to_shared_dpll(crtc) == pll)
12935 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12936 }
12937
15bdd4cf
DV		 12938 I915_WRITE(PCH_DPLL(pll->id), 0);
12939 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12940 udelay(200);
12941}
12942
46edb027
DV		 12943static char *ibx_pch_dpll_names[] = {
12944 "PCH DPLL A",
12945 "PCH DPLL B",
12946};
12947
7c74ade1 12948static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12949{
e7b903d2 12950 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12951 int i;
12952
7c74ade1 12953 dev_priv->num_shared_dpll = 2;
ee7b9f93 12954
e72f9fbf 12955 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12956 dev_priv->shared_dplls[i].id = i;
12957 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12958 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12959 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12960 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12961 dev_priv->shared_dplls[i].get_hw_state =
12962 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12963 }
12964}
12965
7c74ade1
DV		 12966static void intel_shared_dpll_init(struct drm_device *dev)
12967{
e7b903d2 12968 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12969
9cd86933
DV		 12970 if (HAS_DDI(dev))
12971 intel_ddi_pll_init(dev);
12972 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12973 ibx_pch_dpll_init(dev);
12974 else
12975 dev_priv->num_shared_dpll = 0;
12976
12977 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12978}
12979
1fc0a8f7
TU		 12980/**
12981 * intel_wm_need_update - Check whether watermarks need updating
12982 * @plane: drm plane
12983 * @state: new plane state
12984 *
12985 * Check current plane state versus the new one to determine whether
12986 * watermarks need to be recalculated.
12987 *
12988 * Returns true or false.
12989 */
12990bool intel_wm_need_update(struct drm_plane *plane,
12991 struct drm_plane_state *state)
12992{
12993 /* Update watermarks on tiling changes. */
12994 if (!plane->state->fb || !state->fb ||
12995 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12996 plane->state->rotation != state->rotation)
12997 return true;
12998
12999 return false;
13000}
13001
6beb8c23
MR		 13002/**
13003 * intel_prepare_plane_fb - Prepare fb for usage on plane
13004 * @plane: drm plane to prepare for
13005 * @fb: framebuffer to prepare for presentation
13006 *
13007 * Prepares a framebuffer for usage on a display plane. Generally this
13008 * involves pinning the underlying object and updating the frontbuffer tracking
13009 * bits. Some older platforms need special physical address handling for
13010 * cursor planes.
13011 *
13012 * Returns 0 on success, negative error code on failure.
13013 */
13014int
13015intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13016 struct drm_framebuffer *fb,
13017 const struct drm_plane_state *new_state)
465c120c
MR		 13018{
13019 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13020 struct intel_plane *intel_plane = to_intel_plane(plane);
13021 enum pipe pipe = intel_plane->pipe;
13022 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13023 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13024 unsigned frontbuffer_bits = 0;
13025 int ret = 0;
465c120c 13026
ea2c67bb 13027 if (!obj)
465c120c
MR		 13028 return 0;
13029
6beb8c23
MR		 13030 switch (plane->type) {
13031 case DRM_PLANE_TYPE_PRIMARY:
13032 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13033 break;
13034 case DRM_PLANE_TYPE_CURSOR:
13035 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13036 break;
13037 case DRM_PLANE_TYPE_OVERLAY:
13038 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13039 break;
13040 }
465c120c 13041
6beb8c23 13042 mutex_lock(&dev->struct_mutex);
465c120c 13043
6beb8c23
MR		 13044 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13045 INTEL_INFO(dev)->cursor_needs_physical) {
13046 int align = IS_I830(dev) ? 16 * 1024 : 256;
13047 ret = i915_gem_object_attach_phys(obj, align);
13048 if (ret)
13049 DRM_DEBUG_KMS("failed to attach phys object\n");
13050 } else {
82bc3b2d 13051 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13052 }
465c120c 13053
6beb8c23
MR		 13054 if (ret == 0)
13055 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13056
4c34574f 13057 mutex_unlock(&dev->struct_mutex);
465c120c 13058
6beb8c23
MR		 13059 return ret;
13060}
13061
38f3ce3a
MR		 13062/**
13063 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13064 * @plane: drm plane to clean up for
13065 * @fb: old framebuffer that was on plane
13066 *
13067 * Cleans up a framebuffer that has just been removed from a plane.
13068 */
13069void
13070intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13071 struct drm_framebuffer *fb,
13072 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13073{
13074 struct drm_device *dev = plane->dev;
13075 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13076
13077 if (WARN_ON(!obj))
13078 return;
13079
13080 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13081 !INTEL_INFO(dev)->cursor_needs_physical) {
13082 mutex_lock(&dev->struct_mutex);
82bc3b2d 13083 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13084 mutex_unlock(&dev->struct_mutex);
13085 }
465c120c
MR		 13086}
13087
13088static int
3c692a41
GP		 13089intel_check_primary_plane(struct drm_plane *plane,
13090 struct intel_plane_state *state)
13091{
32b7eeec
MR		 13092 struct drm_device *dev = plane->dev;
13093 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13094 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13095 struct intel_crtc *intel_crtc;
2b875c22 13096 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13097 struct drm_rect *dest = &state->dst;
13098 struct drm_rect *src = &state->src;
13099 const struct drm_rect *clip = &state->clip;
d8106366 13100 bool can_position = false;
465c120c
MR		 13101 int ret;
13102
ea2c67bb
MR		 13103 crtc = crtc ? crtc : plane->crtc;
13104 intel_crtc = to_intel_crtc(crtc);
13105
d8106366
SJ		 13106 if (INTEL_INFO(dev)->gen >= 9)
13107 can_position = true;
13108
c59cb179
MR		 13109 ret = drm_plane_helper_check_update(plane, crtc, fb,
13110 src, dest, clip,
13111 DRM_PLANE_HELPER_NO_SCALING,
13112 DRM_PLANE_HELPER_NO_SCALING,
d8106366
SJ		 13113 can_position, true,
13114 &state->visible);
c59cb179
MR		 13115 if (ret)
13116 return ret;
465c120c 13117
32b7eeec
MR		 13118 if (intel_crtc->active) {
13119 intel_crtc->atomic.wait_for_flips = true;
13120
13121 /*
13122 * FBC does not work on some platforms for rotated
13123 * planes, so disable it when rotation is not 0 and
13124 * update it when rotation is set back to 0.
13125 *
13126 * FIXME: This is redundant with the fbc update done in
13127 * the primary plane enable function except that that
13128 * one is done too late. We eventually need to unify
13129 * this.
13130 */
13131 if (intel_crtc->primary_enabled &&
13132 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13133 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13134 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13135 intel_crtc->atomic.disable_fbc = true;
13136 }
13137
13138 if (state->visible) {
13139 /*
13140 * BDW signals flip done immediately if the plane
13141 * is disabled, even if the plane enable is already
13142 * armed to occur at the next vblank :(
13143 */
13144 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
13145 intel_crtc->atomic.wait_vblank = true;
13146 }
13147
13148 intel_crtc->atomic.fb_bits |=
13149 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13150
13151 intel_crtc->atomic.update_fbc = true;
0fda6568 13152
1fc0a8f7 13153 if (intel_wm_need_update(plane, &state->base))
0fda6568 13154 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13155 }
13156
14af293f
GP		 13157 return 0;
13158}
13159
13160static void
13161intel_commit_primary_plane(struct drm_plane *plane,
13162 struct intel_plane_state *state)
13163{
2b875c22
MR		 13164 struct drm_crtc *crtc = state->base.crtc;
13165 struct drm_framebuffer *fb = state->base.fb;
13166 struct drm_device *dev = plane->dev;
14af293f 13167 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13168 struct intel_crtc *intel_crtc;
14af293f
GP		 13169 struct drm_rect *src = &state->src;
13170
ea2c67bb
MR		 13171 crtc = crtc ? crtc : plane->crtc;
13172 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13173
13174 plane->fb = fb;
9dc806fc
MR		 13175 crtc->x = src->x1 >> 16;
13176 crtc->y = src->y1 >> 16;
ccc759dc 13177
ccc759dc 13178 if (intel_crtc->active) {
ccc759dc 13179 if (state->visible) {
ccc759dc
GP		 13180 /* FIXME: kill this fastboot hack */
13181 intel_update_pipe_size(intel_crtc);
465c120c 13182
ccc759dc 13183 intel_crtc->primary_enabled = true;
465c120c 13184
ccc759dc
GP		 13185 dev_priv->display.update_primary_plane(crtc, plane->fb,
13186 crtc->x, crtc->y);
ccc759dc
GP		 13187 } else {
13188 /*
13189 * If clipping results in a non-visible primary plane,
13190 * we'll disable the primary plane. Note that this is
13191 * a bit different than what happens if userspace
13192 * explicitly disables the plane by passing fb=0
13193 * because plane->fb still gets set and pinned.
13194 */
13195 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 13196 }
ccc759dc 13197 }
465c120c
MR		 13198}
13199
32b7eeec 13200static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13201{
32b7eeec 13202 struct drm_device *dev = crtc->dev;
140fd38d 13203 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13205 struct intel_plane *intel_plane;
13206 struct drm_plane *p;
13207 unsigned fb_bits = 0;
13208
13209 /* Track fb's for any planes being disabled */
13210 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13211 intel_plane = to_intel_plane(p);
13212
13213 if (intel_crtc->atomic.disabled_planes &
13214 (1 << drm_plane_index(p))) {
13215 switch (p->type) {
13216 case DRM_PLANE_TYPE_PRIMARY:
13217 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13218 break;
13219 case DRM_PLANE_TYPE_CURSOR:
13220 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13221 break;
13222 case DRM_PLANE_TYPE_OVERLAY:
13223 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13224 break;
13225 }
3c692a41 13226
ea2c67bb
MR		 13227 mutex_lock(&dev->struct_mutex);
13228 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13229 mutex_unlock(&dev->struct_mutex);
13230 }
13231 }
3c692a41 13232
32b7eeec
MR		 13233 if (intel_crtc->atomic.wait_for_flips)
13234 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13235
32b7eeec
MR		 13236 if (intel_crtc->atomic.disable_fbc)
13237 intel_fbc_disable(dev);
3c692a41 13238
32b7eeec
MR		 13239 if (intel_crtc->atomic.pre_disable_primary)
13240 intel_pre_disable_primary(crtc);
3c692a41 13241
32b7eeec
MR		 13242 if (intel_crtc->atomic.update_wm)
13243 intel_update_watermarks(crtc);
3c692a41 13244
32b7eeec 13245 intel_runtime_pm_get(dev_priv);
3c692a41 13246
c34c9ee4
MR		 13247 /* Perform vblank evasion around commit operation */
13248 if (intel_crtc->active)
13249 intel_crtc->atomic.evade =
13250 intel_pipe_update_start(intel_crtc,
13251 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13252}
13253
13254static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13255{
13256 struct drm_device *dev = crtc->dev;
13257 struct drm_i915_private *dev_priv = dev->dev_private;
13258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13259 struct drm_plane *p;
13260
c34c9ee4
MR		 13261 if (intel_crtc->atomic.evade)
13262 intel_pipe_update_end(intel_crtc,
13263 intel_crtc->atomic.start_vbl_count);
3c692a41 13264
140fd38d 13265 intel_runtime_pm_put(dev_priv);
3c692a41 13266
32b7eeec
MR		 13267 if (intel_crtc->atomic.wait_vblank)
13268 intel_wait_for_vblank(dev, intel_crtc->pipe);
13269
13270 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13271
13272 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13273 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13274 intel_fbc_update(dev);
ccc759dc 13275 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13276 }
3c692a41 13277
32b7eeec
MR		 13278 if (intel_crtc->atomic.post_enable_primary)
13279 intel_post_enable_primary(crtc);
3c692a41 13280
32b7eeec
MR		 13281 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13282 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13283 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13284 false, false);
13285
13286 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13287}
13288
cf4c7c12 13289/**
4a3b8769
MR		 13290 * intel_plane_destroy - destroy a plane
13291 * @plane: plane to destroy
cf4c7c12 13292 *
4a3b8769
MR		 13293 * Common destruction function for all types of planes (primary, cursor,
13294 * sprite).
cf4c7c12 13295 */
4a3b8769 13296void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13297{
13298 struct intel_plane *intel_plane = to_intel_plane(plane);
13299 drm_plane_cleanup(plane);
13300 kfree(intel_plane);
13301}
13302
65a3fea0 13303const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13304 .update_plane = drm_atomic_helper_update_plane,
13305 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13306 .destroy = intel_plane_destroy,
c196e1d6 13307 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13308 .atomic_get_property = intel_plane_atomic_get_property,
13309 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13310 .atomic_duplicate_state = intel_plane_duplicate_state,
13311 .atomic_destroy_state = intel_plane_destroy_state,
13312
465c120c
MR		 13313};
13314
13315static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13316 int pipe)
13317{
13318 struct intel_plane *primary;
8e7d688b 13319 struct intel_plane_state *state;
465c120c
MR		 13320 const uint32_t *intel_primary_formats;
13321 int num_formats;
13322
13323 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13324 if (primary == NULL)
13325 return NULL;
13326
8e7d688b
MR		 13327 state = intel_create_plane_state(&primary->base);
13328 if (!state) {
ea2c67bb
MR		 13329 kfree(primary);
13330 return NULL;
13331 }
8e7d688b 13332 primary->base.state = &state->base;
ea2c67bb 13333
465c120c
MR		 13334 primary->can_scale = false;
13335 primary->max_downscale = 1;
549e2bfb 13336 state->scaler_id = -1;
465c120c
MR		 13337 primary->pipe = pipe;
13338 primary->plane = pipe;
c59cb179
MR		 13339 primary->check_plane = intel_check_primary_plane;
13340 primary->commit_plane = intel_commit_primary_plane;
08e221fb 13341 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13342 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13343 primary->plane = !pipe;
13344
13345 if (INTEL_INFO(dev)->gen <= 3) {
13346 intel_primary_formats = intel_primary_formats_gen2;
13347 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13348 } else {
13349 intel_primary_formats = intel_primary_formats_gen4;
13350 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13351 }
13352
13353 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13354 &intel_plane_funcs,
465c120c
MR		 13355 intel_primary_formats, num_formats,
13356 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13357
3b7a5119
SJ		 13358 if (INTEL_INFO(dev)->gen >= 4)
13359 intel_create_rotation_property(dev, primary);
48404c1e 13360
ea2c67bb
MR		 13361 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13362
465c120c
MR		 13363 return &primary->base;
13364}
13365
3b7a5119
SJ		 13366void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13367{
13368 if (!dev->mode_config.rotation_property) {
13369 unsigned long flags = BIT(DRM_ROTATE_0) |
13370 BIT(DRM_ROTATE_180);
13371
13372 if (INTEL_INFO(dev)->gen >= 9)
13373 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13374
13375 dev->mode_config.rotation_property =
13376 drm_mode_create_rotation_property(dev, flags);
13377 }
13378 if (dev->mode_config.rotation_property)
13379 drm_object_attach_property(&plane->base.base,
13380 dev->mode_config.rotation_property,
13381 plane->base.state->rotation);
13382}
13383
3d7d6510 13384static int
852e787c
GP		 13385intel_check_cursor_plane(struct drm_plane *plane,
13386 struct intel_plane_state *state)
3d7d6510 13387{
2b875c22 13388 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13389 struct drm_device *dev = plane->dev;
2b875c22 13390 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13391 struct drm_rect *dest = &state->dst;
13392 struct drm_rect *src = &state->src;
13393 const struct drm_rect *clip = &state->clip;
757f9a3e 13394 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13395 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13396 unsigned stride;
13397 int ret;
3d7d6510 13398
ea2c67bb
MR		 13399 crtc = crtc ? crtc : plane->crtc;
13400 intel_crtc = to_intel_crtc(crtc);
13401
757f9a3e 13402 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13403 src, dest, clip,
3d7d6510
MR		 13404 DRM_PLANE_HELPER_NO_SCALING,
13405 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13406 true, true, &state->visible);
757f9a3e
GP		 13407 if (ret)
13408 return ret;
13409
13410
13411 /* if we want to turn off the cursor ignore width and height */
13412 if (!obj)
32b7eeec 13413 goto finish;
757f9a3e 13414
757f9a3e 13415 /* Check for which cursor types we support */
ea2c67bb
MR		 13416 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13417 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13418 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13419 return -EINVAL;
13420 }
13421
ea2c67bb
MR		 13422 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13423 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13424 DRM_DEBUG_KMS("buffer is too small\n");
13425 return -ENOMEM;
13426 }
13427
3a656b54 13428 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13429 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13430 ret = -EINVAL;
13431 }
757f9a3e 13432
32b7eeec
MR		 13433finish:
13434 if (intel_crtc->active) {
3749f463 13435 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13436 intel_crtc->atomic.update_wm = true;
13437
13438 intel_crtc->atomic.fb_bits |=
13439 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13440 }
13441
757f9a3e 13442 return ret;
852e787c 13443}
3d7d6510 13444
f4a2cf29 13445static void
852e787c
GP		 13446intel_commit_cursor_plane(struct drm_plane *plane,
13447 struct intel_plane_state *state)
13448{
2b875c22 13449 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13450 struct drm_device *dev = plane->dev;
13451 struct intel_crtc *intel_crtc;
2b875c22 13452 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13453 uint32_t addr;
852e787c 13454
ea2c67bb
MR		 13455 crtc = crtc ? crtc : plane->crtc;
13456 intel_crtc = to_intel_crtc(crtc);
13457
2b875c22 13458 plane->fb = state->base.fb;
ea2c67bb
MR		 13459 crtc->cursor_x = state->base.crtc_x;
13460 crtc->cursor_y = state->base.crtc_y;
13461
a912f12f
GP		 13462 if (intel_crtc->cursor_bo == obj)
13463 goto update;
4ed91096 13464
f4a2cf29 13465 if (!obj)
a912f12f 13466 addr = 0;
f4a2cf29 13467 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13468 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13469 else
a912f12f 13470 addr = obj->phys_handle->busaddr;
852e787c 13471
a912f12f
GP		 13472 intel_crtc->cursor_addr = addr;
13473 intel_crtc->cursor_bo = obj;
13474update:
852e787c 13475
32b7eeec 13476 if (intel_crtc->active)
a912f12f 13477 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13478}
13479
3d7d6510
MR		 13480static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13481 int pipe)
13482{
13483 struct intel_plane *cursor;
8e7d688b 13484 struct intel_plane_state *state;
3d7d6510
MR		 13485
13486 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13487 if (cursor == NULL)
13488 return NULL;
13489
8e7d688b
MR		 13490 state = intel_create_plane_state(&cursor->base);
13491 if (!state) {
ea2c67bb
MR		 13492 kfree(cursor);
13493 return NULL;
13494 }
8e7d688b 13495 cursor->base.state = &state->base;
ea2c67bb 13496
3d7d6510
MR		 13497 cursor->can_scale = false;
13498 cursor->max_downscale = 1;
13499 cursor->pipe = pipe;
13500 cursor->plane = pipe;
549e2bfb 13501 state->scaler_id = -1;
c59cb179
MR		 13502 cursor->check_plane = intel_check_cursor_plane;
13503 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 13504
13505 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13506 &intel_plane_funcs,
3d7d6510
MR		 13507 intel_cursor_formats,
13508 ARRAY_SIZE(intel_cursor_formats),
13509 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13510
13511 if (INTEL_INFO(dev)->gen >= 4) {
13512 if (!dev->mode_config.rotation_property)
13513 dev->mode_config.rotation_property =
13514 drm_mode_create_rotation_property(dev,
13515 BIT(DRM_ROTATE_0) |
13516 BIT(DRM_ROTATE_180));
13517 if (dev->mode_config.rotation_property)
13518 drm_object_attach_property(&cursor->base.base,
13519 dev->mode_config.rotation_property,
8e7d688b 13520 state->base.rotation);
4398ad45
VS		 13521 }
13522
ea2c67bb
MR		 13523 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13524
3d7d6510
MR		 13525 return &cursor->base;
13526}
13527
549e2bfb
CK		 13528static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13529 struct intel_crtc_state *crtc_state)
13530{
13531 int i;
13532 struct intel_scaler *intel_scaler;
13533 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13534
13535 for (i = 0; i < intel_crtc->num_scalers; i++) {
13536 intel_scaler = &scaler_state->scalers[i];
13537 intel_scaler->in_use = 0;
13538 intel_scaler->id = i;
13539
13540 intel_scaler->mode = PS_SCALER_MODE_DYN;
13541 }
13542
13543 scaler_state->scaler_id = -1;
13544}
13545
b358d0a6 13546static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13547{
fbee40df 13548 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13549 struct intel_crtc *intel_crtc;
f5de6e07 13550 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13551 struct drm_plane *primary = NULL;
13552 struct drm_plane *cursor = NULL;
465c120c 13553 int i, ret;
79e53945 13554
955382f3 13555 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13556 if (intel_crtc == NULL)
13557 return;
13558
f5de6e07
ACO		 13559 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13560 if (!crtc_state)
13561 goto fail;
13562 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13563 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13564
549e2bfb
CK		 13565 /* initialize shared scalers */
13566 if (INTEL_INFO(dev)->gen >= 9) {
13567 if (pipe == PIPE_C)
13568 intel_crtc->num_scalers = 1;
13569 else
13570 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13571
13572 skl_init_scalers(dev, intel_crtc, crtc_state);
13573 }
13574
465c120c 13575 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13576 if (!primary)
13577 goto fail;
13578
13579 cursor = intel_cursor_plane_create(dev, pipe);
13580 if (!cursor)
13581 goto fail;
13582
465c120c 13583 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13584 cursor, &intel_crtc_funcs);
13585 if (ret)
13586 goto fail;
79e53945
JB		 13587
13588 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13589 for (i = 0; i < 256; i++) {
13590 intel_crtc->lut_r[i] = i;
13591 intel_crtc->lut_g[i] = i;
13592 intel_crtc->lut_b[i] = i;
13593 }
13594
1f1c2e24
VS		 13595 /*
13596 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13597 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13598 */
80824003
JB		 13599 intel_crtc->pipe = pipe;
13600 intel_crtc->plane = pipe;
3a77c4c4 13601 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13602 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13603 intel_crtc->plane = !pipe;
80824003
JB		 13604 }
13605
4b0e333e
CW		 13606 intel_crtc->cursor_base = ~0;
13607 intel_crtc->cursor_cntl = ~0;
dc41c154 13608 intel_crtc->cursor_size = ~0;
8d7849db 13609
22fd0fab
JB		 13610 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13611 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13612 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13613 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13614
9362c7c5
ACO		 13615 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13616
79e53945 13617 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13618
13619 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13620 return;
13621
13622fail:
13623 if (primary)
13624 drm_plane_cleanup(primary);
13625 if (cursor)
13626 drm_plane_cleanup(cursor);
f5de6e07 13627 kfree(crtc_state);
3d7d6510 13628 kfree(intel_crtc);
79e53945
JB		 13629}
13630
752aa88a
JB		 13631enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13632{
13633 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13634 struct drm_device *dev = connector->base.dev;
752aa88a 13635
51fd371b 13636 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13637
d3babd3f 13638 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13639 return INVALID_PIPE;
13640
13641 return to_intel_crtc(encoder->crtc)->pipe;
13642}
13643
08d7b3d1 13644int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13645 struct drm_file *file)
08d7b3d1 13646{
08d7b3d1 13647 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13648 struct drm_crtc *drmmode_crtc;
c05422d5 13649 struct intel_crtc *crtc;
08d7b3d1 13650
7707e653 13651 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13652
7707e653 13653 if (!drmmode_crtc) {
08d7b3d1 13654 DRM_ERROR("no such CRTC id\n");
3f2c2057 13655 return -ENOENT;
08d7b3d1
CW		 13656 }
13657
7707e653 13658 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13659 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13660
c05422d5 13661 return 0;
08d7b3d1
CW		 13662}
13663
66a9278e 13664static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13665{
66a9278e
DV		 13666 struct drm_device *dev = encoder->base.dev;
13667 struct intel_encoder *source_encoder;
79e53945 13668 int index_mask = 0;
79e53945
JB		 13669 int entry = 0;
13670
b2784e15 13671 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13672 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13673 index_mask |= (1 << entry);
13674
79e53945
JB		 13675 entry++;
13676 }
4ef69c7a 13677
79e53945
JB		 13678 return index_mask;
13679}
13680
4d302442
CW		 13681static bool has_edp_a(struct drm_device *dev)
13682{
13683 struct drm_i915_private *dev_priv = dev->dev_private;
13684
13685 if (!IS_MOBILE(dev))
13686 return false;
13687
13688 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13689 return false;
13690
e3589908 13691 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13692 return false;
13693
13694 return true;
13695}
13696
84b4e042
JB		 13697static bool intel_crt_present(struct drm_device *dev)
13698{
13699 struct drm_i915_private *dev_priv = dev->dev_private;
13700
884497ed
DL		 13701 if (INTEL_INFO(dev)->gen >= 9)
13702 return false;
13703
cf404ce4 13704 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13705 return false;
13706
13707 if (IS_CHERRYVIEW(dev))
13708 return false;
13709
13710 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13711 return false;
13712
13713 return true;
13714}
13715
79e53945
JB		 13716static void intel_setup_outputs(struct drm_device *dev)
13717{
725e30ad 13718 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13719 struct intel_encoder *encoder;
cb0953d7 13720 bool dpd_is_edp = false;
79e53945 13721
c9093354 13722 intel_lvds_init(dev);
79e53945 13723
84b4e042 13724 if (intel_crt_present(dev))
79935fca 13725 intel_crt_init(dev);
cb0953d7 13726
c776eb2e
VK		 13727 if (IS_BROXTON(dev)) {
13728 /*
13729 * FIXME: Broxton doesn't support port detection via the
13730 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13731 * detect the ports.
13732 */
13733 intel_ddi_init(dev, PORT_A);
13734 intel_ddi_init(dev, PORT_B);
13735 intel_ddi_init(dev, PORT_C);
13736 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13737 int found;
13738
de31facd
JB		 13739 /*
13740 * Haswell uses DDI functions to detect digital outputs.
13741 * On SKL pre-D0 the strap isn't connected, so we assume
13742 * it's there.
13743 */
0e72a5b5 13744 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13745 /* WaIgnoreDDIAStrap: skl */
13746 if (found ||
13747 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13748 intel_ddi_init(dev, PORT_A);
13749
13750 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13751 * register */
13752 found = I915_READ(SFUSE_STRAP);
13753
13754 if (found & SFUSE_STRAP_DDIB_DETECTED)
13755 intel_ddi_init(dev, PORT_B);
13756 if (found & SFUSE_STRAP_DDIC_DETECTED)
13757 intel_ddi_init(dev, PORT_C);
13758 if (found & SFUSE_STRAP_DDID_DETECTED)
13759 intel_ddi_init(dev, PORT_D);
13760 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13761 int found;
5d8a7752 13762 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13763
13764 if (has_edp_a(dev))
13765 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13766
dc0fa718 13767 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13768 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13769 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13770 if (!found)
e2debe91 13771 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13772 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13773 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13774 }
13775
dc0fa718 13776 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13777 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13778
dc0fa718 13779 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13780 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13781
5eb08b69 13782 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13783 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13784
270b3042 13785 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13786 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13787 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13788 /*
13789 * The DP_DETECTED bit is the latched state of the DDC
13790 * SDA pin at boot. However since eDP doesn't require DDC
13791 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13792 * eDP ports may have been muxed to an alternate function.
13793 * Thus we can't rely on the DP_DETECTED bit alone to detect
13794 * eDP ports. Consult the VBT as well as DP_DETECTED to
13795 * detect eDP ports.
13796 */
d2182a66
VS		 13797 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13798 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13799 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13800 PORT_B);
e17ac6db
VS		 13801 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13802 intel_dp_is_edp(dev, PORT_B))
13803 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13804
d2182a66
VS		 13805 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13806 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13807 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13808 PORT_C);
e17ac6db
VS		 13809 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13810 intel_dp_is_edp(dev, PORT_C))
13811 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13812
9418c1f1 13813 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13814 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13815 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13816 PORT_D);
e17ac6db
VS		 13817 /* eDP not supported on port D, so don't check VBT */
13818 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13819 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13820 }
13821
3cfca973 13822 intel_dsi_init(dev);
103a196f 13823 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13824 bool found = false;
7d57382e 13825
e2debe91 13826 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13827 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13828 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13829 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13830 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13831 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13832 }
27185ae1 13833
e7281eab 13834 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13835 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13836 }
13520b05
KH		 13837
13838 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13839
e2debe91 13840 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13841 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13842 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13843 }
27185ae1 13844
e2debe91 13845 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13846
b01f2c3a
JB		 13847 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13848 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13849 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13850 }
e7281eab 13851 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13852 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13853 }
27185ae1 13854
b01f2c3a 13855 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13856 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13857 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13858 } else if (IS_GEN2(dev))
79e53945
JB		 13859 intel_dvo_init(dev);
13860
103a196f 13861 if (SUPPORTS_TV(dev))
79e53945
JB		 13862 intel_tv_init(dev);
13863
0bc12bcb 13864 intel_psr_init(dev);
7c8f8a70 13865
b2784e15 13866 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13867 encoder->base.possible_crtcs = encoder->crtc_mask;
13868 encoder->base.possible_clones =
66a9278e 13869 intel_encoder_clones(encoder);
79e53945 13870 }
47356eb6 13871
dde86e2d 13872 intel_init_pch_refclk(dev);
270b3042
DV		 13873
13874 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13875}
13876
13877static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13878{
60a5ca01 13879 struct drm_device *dev = fb->dev;
79e53945 13880 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13881
ef2d633e 13882 drm_framebuffer_cleanup(fb);
60a5ca01 13883 mutex_lock(&dev->struct_mutex);
ef2d633e 13884 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13885 drm_gem_object_unreference(&intel_fb->obj->base);
13886 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13887 kfree(intel_fb);
13888}
13889
13890static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13891 struct drm_file *file,
79e53945
JB		 13892 unsigned int *handle)
13893{
13894 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13895 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13896
05394f39 13897 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13898}
13899
13900static const struct drm_framebuffer_funcs intel_fb_funcs = {
13901 .destroy = intel_user_framebuffer_destroy,
13902 .create_handle = intel_user_framebuffer_create_handle,
13903};
13904
b321803d
DL		 13905static
13906u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13907 uint32_t pixel_format)
13908{
13909 u32 gen = INTEL_INFO(dev)->gen;
13910
13911 if (gen >= 9) {
13912 /* "The stride in bytes must not exceed the of the size of 8K
13913 * pixels and 32K bytes."
13914 */
13915 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13916 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13917 return 32*1024;
13918 } else if (gen >= 4) {
13919 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13920 return 16*1024;
13921 else
13922 return 32*1024;
13923 } else if (gen >= 3) {
13924 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13925 return 8*1024;
13926 else
13927 return 16*1024;
13928 } else {
13929 /* XXX DSPC is limited to 4k tiled */
13930 return 8*1024;
13931 }
13932}
13933
b5ea642a
DV		 13934static int intel_framebuffer_init(struct drm_device *dev,
13935 struct intel_framebuffer *intel_fb,
13936 struct drm_mode_fb_cmd2 *mode_cmd,
13937 struct drm_i915_gem_object *obj)
79e53945 13938{
6761dd31 13939 unsigned int aligned_height;
79e53945 13940 int ret;
b321803d 13941 u32 pitch_limit, stride_alignment;
79e53945 13942
dd4916c5
DV		 13943 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13944
2a80eada
DV		 13945 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13946 /* Enforce that fb modifier and tiling mode match, but only for
13947 * X-tiled. This is needed for FBC. */
13948 if (!!(obj->tiling_mode == I915_TILING_X) !=
13949 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13950 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13951 return -EINVAL;
13952 }
13953 } else {
13954 if (obj->tiling_mode == I915_TILING_X)
13955 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13956 else if (obj->tiling_mode == I915_TILING_Y) {
13957 DRM_DEBUG("No Y tiling for legacy addfb\n");
13958 return -EINVAL;
13959 }
13960 }
13961
9a8f0a12
TU		 13962 /* Passed in modifier sanity checking. */
13963 switch (mode_cmd->modifier[0]) {
13964 case I915_FORMAT_MOD_Y_TILED:
13965 case I915_FORMAT_MOD_Yf_TILED:
13966 if (INTEL_INFO(dev)->gen < 9) {
13967 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13968 mode_cmd->modifier[0]);
13969 return -EINVAL;
13970 }
13971 case DRM_FORMAT_MOD_NONE:
13972 case I915_FORMAT_MOD_X_TILED:
13973 break;
13974 default:
c0f40428
JB		 13975 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13976 mode_cmd->modifier[0]);
57cd6508 13977 return -EINVAL;
c16ed4be 13978 }
57cd6508 13979
b321803d
DL		 13980 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13981 mode_cmd->pixel_format);
13982 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13983 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13984 mode_cmd->pitches[0], stride_alignment);
57cd6508 13985 return -EINVAL;
c16ed4be 13986 }
57cd6508 13987
b321803d
DL		 13988 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13989 mode_cmd->pixel_format);
a35cdaa0 13990 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13991 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13992 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13993 "tiled" : "linear",
a35cdaa0 13994 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13995 return -EINVAL;
c16ed4be 13996 }
5d7bd705 13997
2a80eada 13998 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13999 mode_cmd->pitches[0] != obj->stride) {
14000 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14001 mode_cmd->pitches[0], obj->stride);
5d7bd705 14002 return -EINVAL;
c16ed4be 14003 }
5d7bd705 14004
57779d06 14005 /* Reject formats not supported by any plane early. */
308e5bcb 14006 switch (mode_cmd->pixel_format) {
57779d06 14007 case DRM_FORMAT_C8:
04b3924d
VS		 14008 case DRM_FORMAT_RGB565:
14009 case DRM_FORMAT_XRGB8888:
14010 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14011 break;
14012 case DRM_FORMAT_XRGB1555:
14013 case DRM_FORMAT_ARGB1555:
c16ed4be 14014 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14015 DRM_DEBUG("unsupported pixel format: %s\n",
14016 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14017 return -EINVAL;
c16ed4be 14018 }
57779d06
VS		 14019 break;
14020 case DRM_FORMAT_XBGR8888:
14021 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14022 case DRM_FORMAT_XRGB2101010:
14023 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14024 case DRM_FORMAT_XBGR2101010:
14025 case DRM_FORMAT_ABGR2101010:
c16ed4be 14026 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14027 DRM_DEBUG("unsupported pixel format: %s\n",
14028 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14029 return -EINVAL;
c16ed4be 14030 }
b5626747 14031 break;
04b3924d
VS		 14032 case DRM_FORMAT_YUYV:
14033 case DRM_FORMAT_UYVY:
14034 case DRM_FORMAT_YVYU:
14035 case DRM_FORMAT_VYUY:
c16ed4be 14036 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14037 DRM_DEBUG("unsupported pixel format: %s\n",
14038 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14039 return -EINVAL;
c16ed4be 14040 }
57cd6508
CW		 14041 break;
14042 default:
4ee62c76
VS		 14043 DRM_DEBUG("unsupported pixel format: %s\n",
14044 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14045 return -EINVAL;
14046 }
14047
90f9a336
VS		 14048 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14049 if (mode_cmd->offsets[0] != 0)
14050 return -EINVAL;
14051
ec2c981e 14052 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14053 mode_cmd->pixel_format,
14054 mode_cmd->modifier[0]);
53155c0a
DV		 14055 /* FIXME drm helper for size checks (especially planar formats)? */
14056 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14057 return -EINVAL;
14058
c7d73f6a
DV		 14059 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14060 intel_fb->obj = obj;
80075d49 14061 intel_fb->obj->framebuffer_references++;
c7d73f6a 14062
79e53945
JB		 14063 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14064 if (ret) {
14065 DRM_ERROR("framebuffer init failed %d\n", ret);
14066 return ret;
14067 }
14068
79e53945
JB		 14069 return 0;
14070}
14071
79e53945
JB		 14072static struct drm_framebuffer *
14073intel_user_framebuffer_create(struct drm_device *dev,
14074 struct drm_file *filp,
308e5bcb 14075 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14076{
05394f39 14077 struct drm_i915_gem_object *obj;
79e53945 14078
308e5bcb
JB		 14079 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14080 mode_cmd->handles[0]));
c8725226 14081 if (&obj->base == NULL)
cce13ff7 14082 return ERR_PTR(-ENOENT);
79e53945 14083
d2dff872 14084 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14085}
14086
4520f53a 14087#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14088static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14089{
14090}
14091#endif
14092
79e53945 14093static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14094 .fb_create = intel_user_framebuffer_create,
0632fef6 14095 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14096 .atomic_check = intel_atomic_check,
14097 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14098};
14099
e70236a8
JB		 14100/* Set up chip specific display functions */
14101static void intel_init_display(struct drm_device *dev)
14102{
14103 struct drm_i915_private *dev_priv = dev->dev_private;
14104
ee9300bb
DV		 14105 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14106 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14107 else if (IS_CHERRYVIEW(dev))
14108 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14109 else if (IS_VALLEYVIEW(dev))
14110 dev_priv->display.find_dpll = vlv_find_best_dpll;
14111 else if (IS_PINEVIEW(dev))
14112 dev_priv->display.find_dpll = pnv_find_best_dpll;
14113 else
14114 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14115
bc8d7dff
DL		 14116 if (INTEL_INFO(dev)->gen >= 9) {
14117 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14118 dev_priv->display.get_initial_plane_config =
14119 skylake_get_initial_plane_config;
bc8d7dff
DL		 14120 dev_priv->display.crtc_compute_clock =
14121 haswell_crtc_compute_clock;
14122 dev_priv->display.crtc_enable = haswell_crtc_enable;
14123 dev_priv->display.crtc_disable = haswell_crtc_disable;
14124 dev_priv->display.off = ironlake_crtc_off;
14125 dev_priv->display.update_primary_plane =
14126 skylake_update_primary_plane;
14127 } else if (HAS_DDI(dev)) {
0e8ffe1b 14128 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14129 dev_priv->display.get_initial_plane_config =
14130 ironlake_get_initial_plane_config;
797d0259
ACO		 14131 dev_priv->display.crtc_compute_clock =
14132 haswell_crtc_compute_clock;
4f771f10
PZ		 14133 dev_priv->display.crtc_enable = haswell_crtc_enable;
14134 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14135 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14136 dev_priv->display.update_primary_plane =
14137 ironlake_update_primary_plane;
09b4ddf9 14138 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14139 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14140 dev_priv->display.get_initial_plane_config =
14141 ironlake_get_initial_plane_config;
3fb37703
ACO		 14142 dev_priv->display.crtc_compute_clock =
14143 ironlake_crtc_compute_clock;
76e5a89c
DV		 14144 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14145 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14146 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14147 dev_priv->display.update_primary_plane =
14148 ironlake_update_primary_plane;
89b667f8
JB		 14149 } else if (IS_VALLEYVIEW(dev)) {
14150 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14151 dev_priv->display.get_initial_plane_config =
14152 i9xx_get_initial_plane_config;
d6dfee7a 14153 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14154 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14155 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14156 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14157 dev_priv->display.update_primary_plane =
14158 i9xx_update_primary_plane;
f564048e 14159 } else {
0e8ffe1b 14160 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14161 dev_priv->display.get_initial_plane_config =
14162 i9xx_get_initial_plane_config;
d6dfee7a 14163 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14164 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14165 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14166 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14167 dev_priv->display.update_primary_plane =
14168 i9xx_update_primary_plane;
f564048e 14169 }
e70236a8 14170
e70236a8 14171 /* Returns the core display clock speed */
1652d19e
VS		 14172 if (IS_SKYLAKE(dev))
14173 dev_priv->display.get_display_clock_speed =
14174 skylake_get_display_clock_speed;
14175 else if (IS_BROADWELL(dev))
14176 dev_priv->display.get_display_clock_speed =
14177 broadwell_get_display_clock_speed;
14178 else if (IS_HASWELL(dev))
14179 dev_priv->display.get_display_clock_speed =
14180 haswell_get_display_clock_speed;
14181 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14182 dev_priv->display.get_display_clock_speed =
14183 valleyview_get_display_clock_speed;
b37a6434
VS		 14184 else if (IS_GEN5(dev))
14185 dev_priv->display.get_display_clock_speed =
14186 ilk_get_display_clock_speed;
a7c66cd8
VS		 14187 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14188 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14189 dev_priv->display.get_display_clock_speed =
14190 i945_get_display_clock_speed;
14191 else if (IS_I915G(dev))
14192 dev_priv->display.get_display_clock_speed =
14193 i915_get_display_clock_speed;
257a7ffc 14194 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14195 dev_priv->display.get_display_clock_speed =
14196 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14197 else if (IS_PINEVIEW(dev))
14198 dev_priv->display.get_display_clock_speed =
14199 pnv_get_display_clock_speed;
e70236a8
JB		 14200 else if (IS_I915GM(dev))
14201 dev_priv->display.get_display_clock_speed =
14202 i915gm_get_display_clock_speed;
14203 else if (IS_I865G(dev))
14204 dev_priv->display.get_display_clock_speed =
14205 i865_get_display_clock_speed;
f0f8a9ce 14206 else if (IS_I85X(dev))
e70236a8
JB		 14207 dev_priv->display.get_display_clock_speed =
14208 i855_get_display_clock_speed;
14209 else /* 852, 830 */
14210 dev_priv->display.get_display_clock_speed =
14211 i830_get_display_clock_speed;
14212
7c10a2b5 14213 if (IS_GEN5(dev)) {
3bb11b53 14214 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14215 } else if (IS_GEN6(dev)) {
14216 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14217 } else if (IS_IVYBRIDGE(dev)) {
14218 /* FIXME: detect B0+ stepping and use auto training */
14219 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14220 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14221 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14222 } else if (IS_VALLEYVIEW(dev)) {
14223 dev_priv->display.modeset_global_resources =
14224 valleyview_modeset_global_resources;
f8437dd1
VK		 14225 } else if (IS_BROXTON(dev)) {
14226 dev_priv->display.modeset_global_resources =
14227 broxton_modeset_global_resources;
e70236a8 14228 }
8c9f3aaf 14229
8c9f3aaf
JB		 14230 switch (INTEL_INFO(dev)->gen) {
14231 case 2:
14232 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14233 break;
14234
14235 case 3:
14236 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14237 break;
14238
14239 case 4:
14240 case 5:
14241 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14242 break;
14243
14244 case 6:
14245 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14246 break;
7c9017e5 14247 case 7:
4e0bbc31 14248 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14249 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14250 break;
830c81db 14251 case 9:
ba343e02
TU		 14252 /* Drop through - unsupported since execlist only. */
14253 default:
14254 /* Default just returns -ENODEV to indicate unsupported */
14255 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14256 }
7bd688cd
JN		 14257
14258 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14259
14260 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14261}
14262
b690e96c
JB		 14263/*
14264 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14265 * resume, or other times. This quirk makes sure that's the case for
14266 * affected systems.
14267 */
0206e353 14268static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14269{
14270 struct drm_i915_private *dev_priv = dev->dev_private;
14271
14272 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14273 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14274}
14275
b6b5d049
VS		 14276static void quirk_pipeb_force(struct drm_device *dev)
14277{
14278 struct drm_i915_private *dev_priv = dev->dev_private;
14279
14280 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14281 DRM_INFO("applying pipe b force quirk\n");
14282}
14283
435793df
KP		 14284/*
14285 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14286 */
14287static void quirk_ssc_force_disable(struct drm_device *dev)
14288{
14289 struct drm_i915_private *dev_priv = dev->dev_private;
14290 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14291 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14292}
14293
4dca20ef 14294/*
5a15ab5b
CE		 14295 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14296 * brightness value
4dca20ef
CE		 14297 */
14298static void quirk_invert_brightness(struct drm_device *dev)
14299{
14300 struct drm_i915_private *dev_priv = dev->dev_private;
14301 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14302 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14303}
14304
9c72cc6f
SD		 14305/* Some VBT's incorrectly indicate no backlight is present */
14306static void quirk_backlight_present(struct drm_device *dev)
14307{
14308 struct drm_i915_private *dev_priv = dev->dev_private;
14309 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14310 DRM_INFO("applying backlight present quirk\n");
14311}
14312
b690e96c
JB		 14313struct intel_quirk {
14314 int device;
14315 int subsystem_vendor;
14316 int subsystem_device;
14317 void (*hook)(struct drm_device *dev);
14318};
14319
5f85f176
EE		 14320/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14321struct intel_dmi_quirk {
14322 void (*hook)(struct drm_device *dev);
14323 const struct dmi_system_id (*dmi_id_list)[];
14324};
14325
14326static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14327{
14328 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14329 return 1;
14330}
14331
14332static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14333 {
14334 .dmi_id_list = &(const struct dmi_system_id[]) {
14335 {
14336 .callback = intel_dmi_reverse_brightness,
14337 .ident = "NCR Corporation",
14338 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14339 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14340 },
14341 },
14342 { } /* terminating entry */
14343 },
14344 .hook = quirk_invert_brightness,
14345 },
14346};
14347
c43b5634 14348static struct intel_quirk intel_quirks[] = {
b690e96c 14349 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14350 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14351
b690e96c
JB		 14352 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14353 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14354
b690e96c
JB		 14355 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14356 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14357
5f080c0f
VS		 14358 /* 830 needs to leave pipe A & dpll A up */
14359 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14360
b6b5d049
VS		 14361 /* 830 needs to leave pipe B & dpll B up */
14362 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14363
435793df
KP		 14364 /* Lenovo U160 cannot use SSC on LVDS */
14365 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14366
14367 /* Sony Vaio Y cannot use SSC on LVDS */
14368 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14369
be505f64
AH		 14370 /* Acer Aspire 5734Z must invert backlight brightness */
14371 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14372
14373 /* Acer/eMachines G725 */
14374 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14375
14376 /* Acer/eMachines e725 */
14377 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14378
14379 /* Acer/Packard Bell NCL20 */
14380 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14381
14382 /* Acer Aspire 4736Z */
14383 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14384
14385 /* Acer Aspire 5336 */
14386 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14387
14388 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14389 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14390
dfb3d47b
SD		 14391 /* Acer C720 Chromebook (Core i3 4005U) */
14392 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14393
b2a9601c 14394 /* Apple Macbook 2,1 (Core 2 T7400) */
14395 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14396
d4967d8c
SD		 14397 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14398 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14399
14400 /* HP Chromebook 14 (Celeron 2955U) */
14401 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14402
14403 /* Dell Chromebook 11 */
14404 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14405};
14406
14407static void intel_init_quirks(struct drm_device *dev)
14408{
14409 struct pci_dev *d = dev->pdev;
14410 int i;
14411
14412 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14413 struct intel_quirk *q = &intel_quirks[i];
14414
14415 if (d->device == q->device &&
14416 (d->subsystem_vendor == q->subsystem_vendor ||
14417 q->subsystem_vendor == PCI_ANY_ID) &&
14418 (d->subsystem_device == q->subsystem_device ||
14419 q->subsystem_device == PCI_ANY_ID))
14420 q->hook(dev);
14421 }
5f85f176
EE		 14422 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14423 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14424 intel_dmi_quirks[i].hook(dev);
14425 }
b690e96c
JB		 14426}
14427
9cce37f4
JB		 14428/* Disable the VGA plane that we never use */
14429static void i915_disable_vga(struct drm_device *dev)
14430{
14431 struct drm_i915_private *dev_priv = dev->dev_private;
14432 u8 sr1;
766aa1c4 14433 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14434
2b37c616 14435 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14436 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14437 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14438 sr1 = inb(VGA_SR_DATA);
14439 outb(sr1 | 1<<5, VGA_SR_DATA);
14440 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14441 udelay(300);
14442
01f5a626 14443 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14444 POSTING_READ(vga_reg);
14445}
14446
f817586c
DV		 14447void intel_modeset_init_hw(struct drm_device *dev)
14448{
a8f78b58
ED		 14449 intel_prepare_ddi(dev);
14450
f8bf63fd
VS		 14451 if (IS_VALLEYVIEW(dev))
14452 vlv_update_cdclk(dev);
14453
f817586c
DV		 14454 intel_init_clock_gating(dev);
14455
8090c6b9 14456 intel_enable_gt_powersave(dev);
f817586c
DV		 14457}
14458
79e53945
JB		 14459void intel_modeset_init(struct drm_device *dev)
14460{
652c393a 14461 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14462 int sprite, ret;
8cc87b75 14463 enum pipe pipe;
46f297fb 14464 struct intel_crtc *crtc;
79e53945
JB		 14465
14466 drm_mode_config_init(dev);
14467
14468 dev->mode_config.min_width = 0;
14469 dev->mode_config.min_height = 0;
14470
019d96cb
DA		 14471 dev->mode_config.preferred_depth = 24;
14472 dev->mode_config.prefer_shadow = 1;
14473
25bab385
TU		 14474 dev->mode_config.allow_fb_modifiers = true;
14475
e6ecefaa 14476 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14477
b690e96c
JB		 14478 intel_init_quirks(dev);
14479
1fa61106
ED		 14480 intel_init_pm(dev);
14481
e3c74757
BW		 14482 if (INTEL_INFO(dev)->num_pipes == 0)
14483 return;
14484
e70236a8 14485 intel_init_display(dev);
7c10a2b5 14486 intel_init_audio(dev);
e70236a8 14487
a6c45cf0
CW		 14488 if (IS_GEN2(dev)) {
14489 dev->mode_config.max_width = 2048;
14490 dev->mode_config.max_height = 2048;
14491 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14492 dev->mode_config.max_width = 4096;
14493 dev->mode_config.max_height = 4096;
79e53945 14494 } else {
a6c45cf0
CW		 14495 dev->mode_config.max_width = 8192;
14496 dev->mode_config.max_height = 8192;
79e53945 14497 }
068be561 14498
dc41c154
VS		 14499 if (IS_845G(dev) || IS_I865G(dev)) {
14500 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14501 dev->mode_config.cursor_height = 1023;
14502 } else if (IS_GEN2(dev)) {
068be561
DL		 14503 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14504 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14505 } else {
14506 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14507 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14508 }
14509
5d4545ae 14510 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14511
28c97730 14512 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14513 INTEL_INFO(dev)->num_pipes,
14514 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14515
055e393f 14516 for_each_pipe(dev_priv, pipe) {
8cc87b75 14517 intel_crtc_init(dev, pipe);
3bdcfc0c 14518 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14519 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14520 if (ret)
06da8da2 14521 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14522 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14523 }
79e53945
JB		 14524 }
14525
f42bb70d
JB		 14526 intel_init_dpio(dev);
14527
e72f9fbf 14528 intel_shared_dpll_init(dev);
ee7b9f93 14529
9cce37f4
JB		 14530 /* Just disable it once at startup */
14531 i915_disable_vga(dev);
79e53945 14532 intel_setup_outputs(dev);
11be49eb
CW		 14533
14534 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14535 intel_fbc_disable(dev);
fa9fa083 14536
6e9f798d 14537 drm_modeset_lock_all(dev);
fa9fa083 14538 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14539 drm_modeset_unlock_all(dev);
46f297fb 14540
d3fcc808 14541 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14542 if (!crtc->active)
14543 continue;
14544
46f297fb 14545 /*
46f297fb
JB		 14546 * Note that reserving the BIOS fb up front prevents us
14547 * from stuffing other stolen allocations like the ring
14548 * on top. This prevents some ugliness at boot time, and
14549 * can even allow for smooth boot transitions if the BIOS
14550 * fb is large enough for the active pipe configuration.
14551 */
5724dbd1
DL		 14552 if (dev_priv->display.get_initial_plane_config) {
14553 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14554 &crtc->plane_config);
14555 /*
14556 * If the fb is shared between multiple heads, we'll
14557 * just get the first one.
14558 */
f6936e29 14559 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14560 }
46f297fb 14561 }
2c7111db
CW		 14562}
14563
7fad798e
DV		 14564static void intel_enable_pipe_a(struct drm_device *dev)
14565{
14566 struct intel_connector *connector;
14567 struct drm_connector *crt = NULL;
14568 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14569 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14570
14571 /* We can't just switch on the pipe A, we need to set things up with a
14572 * proper mode and output configuration. As a gross hack, enable pipe A
14573 * by enabling the load detect pipe once. */
3a3371ff 14574 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14575 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14576 crt = &connector->base;
14577 break;
14578 }
14579 }
14580
14581 if (!crt)
14582 return;
14583
208bf9fd 14584 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14585 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14586}
14587
fa555837
DV		 14588static bool
14589intel_check_plane_mapping(struct intel_crtc *crtc)
14590{
7eb552ae
BW		 14591 struct drm_device *dev = crtc->base.dev;
14592 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14593 u32 reg, val;
14594
7eb552ae 14595 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14596 return true;
14597
14598 reg = DSPCNTR(!crtc->plane);
14599 val = I915_READ(reg);
14600
14601 if ((val & DISPLAY_PLANE_ENABLE) &&
14602 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14603 return false;
14604
14605 return true;
14606}
14607
24929352
DV		 14608static void intel_sanitize_crtc(struct intel_crtc *crtc)
14609{
14610 struct drm_device *dev = crtc->base.dev;
14611 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14612 u32 reg;
24929352 14613
24929352 14614 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14615 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14616 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14617
d3eaf884 14618 /* restore vblank interrupts to correct state */
9625604c 14619 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14620 if (crtc->active) {
14621 update_scanline_offset(crtc);
9625604c
DV		 14622 drm_crtc_vblank_on(&crtc->base);
14623 }
d3eaf884 14624
24929352 14625 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14626 * disable the crtc (and hence change the state) if it is wrong. Note
14627 * that gen4+ has a fixed plane -> pipe mapping. */
14628 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14629 struct intel_connector *connector;
14630 bool plane;
14631
24929352
DV		 14632 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14633 crtc->base.base.id);
14634
14635 /* Pipe has the wrong plane attached and the plane is active.
14636 * Temporarily change the plane mapping and disable everything
14637 * ... */
14638 plane = crtc->plane;
14639 crtc->plane = !plane;
9c8958bc 14640 crtc->primary_enabled = true;
24929352
DV		 14641 dev_priv->display.crtc_disable(&crtc->base);
14642 crtc->plane = plane;
14643
14644 /* ... and break all links. */
3a3371ff 14645 for_each_intel_connector(dev, connector) {
24929352
DV		 14646 if (connector->encoder->base.crtc != &crtc->base)
14647 continue;
14648
7f1950fb
EE		 14649 connector->base.dpms = DRM_MODE_DPMS_OFF;
14650 connector->base.encoder = NULL;
24929352 14651 }
7f1950fb
EE		 14652 /* multiple connectors may have the same encoder:
14653 * handle them and break crtc link separately */
3a3371ff 14654 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14655 if (connector->encoder->base.crtc == &crtc->base) {
14656 connector->encoder->base.crtc = NULL;
14657 connector->encoder->connectors_active = false;
14658 }
24929352
DV		 14659
14660 WARN_ON(crtc->active);
83d65738 14661 crtc->base.state->enable = false;
24929352
DV		 14662 crtc->base.enabled = false;
14663 }
24929352 14664
7fad798e
DV		 14665 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14666 crtc->pipe == PIPE_A && !crtc->active) {
14667 /* BIOS forgot to enable pipe A, this mostly happens after
14668 * resume. Force-enable the pipe to fix this, the update_dpms
14669 * call below we restore the pipe to the right state, but leave
14670 * the required bits on. */
14671 intel_enable_pipe_a(dev);
14672 }
14673
24929352
DV		 14674 /* Adjust the state of the output pipe according to whether we
14675 * have active connectors/encoders. */
14676 intel_crtc_update_dpms(&crtc->base);
14677
83d65738 14678 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14679 struct intel_encoder *encoder;
14680
14681 /* This can happen either due to bugs in the get_hw_state
14682 * functions or because the pipe is force-enabled due to the
14683 * pipe A quirk. */
14684 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14685 crtc->base.base.id,
83d65738 14686 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14687 crtc->active ? "enabled" : "disabled");
14688
83d65738 14689 crtc->base.state->enable = crtc->active;
24929352
DV		 14690 crtc->base.enabled = crtc->active;
14691
14692 /* Because we only establish the connector -> encoder ->
14693 * crtc links if something is active, this means the
14694 * crtc is now deactivated. Break the links. connector
14695 * -> encoder links are only establish when things are
14696 * actually up, hence no need to break them. */
14697 WARN_ON(crtc->active);
14698
14699 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14700 WARN_ON(encoder->connectors_active);
14701 encoder->base.crtc = NULL;
14702 }
14703 }
c5ab3bc0 14704
a3ed6aad 14705 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14706 /*
14707 * We start out with underrun reporting disabled to avoid races.
14708 * For correct bookkeeping mark this on active crtcs.
14709 *
c5ab3bc0
DV		 14710 * Also on gmch platforms we dont have any hardware bits to
14711 * disable the underrun reporting. Which means we need to start
14712 * out with underrun reporting disabled also on inactive pipes,
14713 * since otherwise we'll complain about the garbage we read when
14714 * e.g. coming up after runtime pm.
14715 *
4cc31489
DV		 14716 * No protection against concurrent access is required - at
14717 * worst a fifo underrun happens which also sets this to false.
14718 */
14719 crtc->cpu_fifo_underrun_disabled = true;
14720 crtc->pch_fifo_underrun_disabled = true;
14721 }
24929352
DV		 14722}
14723
14724static void intel_sanitize_encoder(struct intel_encoder *encoder)
14725{
14726 struct intel_connector *connector;
14727 struct drm_device *dev = encoder->base.dev;
14728
14729 /* We need to check both for a crtc link (meaning that the
14730 * encoder is active and trying to read from a pipe) and the
14731 * pipe itself being active. */
14732 bool has_active_crtc = encoder->base.crtc &&
14733 to_intel_crtc(encoder->base.crtc)->active;
14734
14735 if (encoder->connectors_active && !has_active_crtc) {
14736 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14737 encoder->base.base.id,
8e329a03 14738 encoder->base.name);
24929352
DV		 14739
14740 /* Connector is active, but has no active pipe. This is
14741 * fallout from our resume register restoring. Disable
14742 * the encoder manually again. */
14743 if (encoder->base.crtc) {
14744 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14745 encoder->base.base.id,
8e329a03 14746 encoder->base.name);
24929352 14747 encoder->disable(encoder);
a62d1497
VS		 14748 if (encoder->post_disable)
14749 encoder->post_disable(encoder);
24929352 14750 }
7f1950fb
EE		 14751 encoder->base.crtc = NULL;
14752 encoder->connectors_active = false;
24929352
DV		 14753
14754 /* Inconsistent output/port/pipe state happens presumably due to
14755 * a bug in one of the get_hw_state functions. Or someplace else
14756 * in our code, like the register restore mess on resume. Clamp
14757 * things to off as a safer default. */
3a3371ff 14758 for_each_intel_connector(dev, connector) {
24929352
DV		 14759 if (connector->encoder != encoder)
14760 continue;
7f1950fb
EE		 14761 connector->base.dpms = DRM_MODE_DPMS_OFF;
14762 connector->base.encoder = NULL;
24929352
DV		 14763 }
14764 }
14765 /* Enabled encoders without active connectors will be fixed in
14766 * the crtc fixup. */
14767}
14768
04098753 14769void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14770{
14771 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14772 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14773
04098753
ID		 14774 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14775 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14776 i915_disable_vga(dev);
14777 }
14778}
14779
14780void i915_redisable_vga(struct drm_device *dev)
14781{
14782 struct drm_i915_private *dev_priv = dev->dev_private;
14783
8dc8a27c
PZ		 14784 /* This function can be called both from intel_modeset_setup_hw_state or
14785 * at a very early point in our resume sequence, where the power well
14786 * structures are not yet restored. Since this function is at a very
14787 * paranoid "someone might have enabled VGA while we were not looking"
14788 * level, just check if the power well is enabled instead of trying to
14789 * follow the "don't touch the power well if we don't need it" policy
14790 * the rest of the driver uses. */
f458ebbc 14791 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14792 return;
14793
04098753 14794 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14795}
14796
98ec7739
VS		 14797static bool primary_get_hw_state(struct intel_crtc *crtc)
14798{
14799 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14800
14801 if (!crtc->active)
14802 return false;
14803
14804 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14805}
14806
30e984df 14807static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14808{
14809 struct drm_i915_private *dev_priv = dev->dev_private;
14810 enum pipe pipe;
24929352
DV		 14811 struct intel_crtc *crtc;
14812 struct intel_encoder *encoder;
14813 struct intel_connector *connector;
5358901f 14814 int i;
24929352 14815
d3fcc808 14816 for_each_intel_crtc(dev, crtc) {
6e3c9717 14817 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14818
6e3c9717 14819 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14820
0e8ffe1b 14821 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14822 crtc->config);
24929352 14823
83d65738 14824 crtc->base.state->enable = crtc->active;
24929352 14825 crtc->base.enabled = crtc->active;
98ec7739 14826 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14827
14828 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14829 crtc->base.base.id,
14830 crtc->active ? "enabled" : "disabled");
14831 }
14832
5358901f
DV		 14833 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14834 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14835
3e369b76
ACO		 14836 pll->on = pll->get_hw_state(dev_priv, pll,
14837 &pll->config.hw_state);
5358901f 14838 pll->active = 0;
3e369b76 14839 pll->config.crtc_mask = 0;
d3fcc808 14840 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14841 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14842 pll->active++;
3e369b76 14843 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14844 }
5358901f 14845 }
5358901f 14846
1e6f2ddc 14847 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14848 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14849
3e369b76 14850 if (pll->config.crtc_mask)
bd2bb1b9 14851 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14852 }
14853
b2784e15 14854 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14855 pipe = 0;
14856
14857 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14858 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14859 encoder->base.crtc = &crtc->base;
6e3c9717 14860 encoder->get_config(encoder, crtc->config);
24929352
DV		 14861 } else {
14862 encoder->base.crtc = NULL;
14863 }
14864
14865 encoder->connectors_active = false;
6f2bcceb 14866 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14867 encoder->base.base.id,
8e329a03 14868 encoder->base.name,
24929352 14869 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14870 pipe_name(pipe));
24929352
DV		 14871 }
14872
3a3371ff 14873 for_each_intel_connector(dev, connector) {
24929352
DV		 14874 if (connector->get_hw_state(connector)) {
14875 connector->base.dpms = DRM_MODE_DPMS_ON;
14876 connector->encoder->connectors_active = true;
14877 connector->base.encoder = &connector->encoder->base;
14878 } else {
14879 connector->base.dpms = DRM_MODE_DPMS_OFF;
14880 connector->base.encoder = NULL;
14881 }
14882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14883 connector->base.base.id,
c23cc417 14884 connector->base.name,
24929352
DV		 14885 connector->base.encoder ? "enabled" : "disabled");
14886 }
30e984df
DV		 14887}
14888
14889/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14890 * and i915 state tracking structures. */
14891void intel_modeset_setup_hw_state(struct drm_device *dev,
14892 bool force_restore)
14893{
14894 struct drm_i915_private *dev_priv = dev->dev_private;
14895 enum pipe pipe;
30e984df
DV		 14896 struct intel_crtc *crtc;
14897 struct intel_encoder *encoder;
35c95375 14898 int i;
30e984df
DV		 14899
14900 intel_modeset_readout_hw_state(dev);
24929352 14901
babea61d
JB		 14902 /*
14903 * Now that we have the config, copy it to each CRTC struct
14904 * Note that this could go away if we move to using crtc_config
14905 * checking everywhere.
14906 */
d3fcc808 14907 for_each_intel_crtc(dev, crtc) {
d330a953 14908 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14909 intel_mode_from_pipe_config(&crtc->base.mode,
14910 crtc->config);
babea61d
JB		 14911 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14912 crtc->base.base.id);
14913 drm_mode_debug_printmodeline(&crtc->base.mode);
14914 }
14915 }
14916
24929352 14917 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14918 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14919 intel_sanitize_encoder(encoder);
14920 }
14921
055e393f 14922 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14923 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14924 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14925 intel_dump_pipe_config(crtc, crtc->config,
14926 "[setup_hw_state]");
24929352 14927 }
9a935856 14928
d29b2f9d
ACO		 14929 intel_modeset_update_connector_atomic_state(dev);
14930
35c95375
DV		 14931 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14932 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14933
14934 if (!pll->on || pll->active)
14935 continue;
14936
14937 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14938
14939 pll->disable(dev_priv, pll);
14940 pll->on = false;
14941 }
14942
3078999f
PB		 14943 if (IS_GEN9(dev))
14944 skl_wm_get_hw_state(dev);
14945 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14946 ilk_wm_get_hw_state(dev);
14947
45e2b5f6 14948 if (force_restore) {
7d0bc1ea
VS		 14949 i915_redisable_vga(dev);
14950
f30da187
DV		 14951 /*
14952 * We need to use raw interfaces for restoring state to avoid
14953 * checking (bogus) intermediate states.
14954 */
055e393f 14955 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14956 struct drm_crtc *crtc =
14957 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14958
83a57153 14959 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14960 }
14961 } else {
14962 intel_modeset_update_staged_output_state(dev);
14963 }
8af6cf88
DV		 14964
14965 intel_modeset_check_state(dev);
2c7111db
CW		 14966}
14967
14968void intel_modeset_gem_init(struct drm_device *dev)
14969{
92122789 14970 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14971 struct drm_crtc *c;
2ff8fde1 14972 struct drm_i915_gem_object *obj;
484b41dd 14973
ae48434c
ID		 14974 mutex_lock(&dev->struct_mutex);
14975 intel_init_gt_powersave(dev);
14976 mutex_unlock(&dev->struct_mutex);
14977
92122789
JB		 14978 /*
14979 * There may be no VBT; and if the BIOS enabled SSC we can
14980 * just keep using it to avoid unnecessary flicker. Whereas if the
14981 * BIOS isn't using it, don't assume it will work even if the VBT
14982 * indicates as much.
14983 */
14984 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14985 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14986 DREF_SSC1_ENABLE);
14987
1833b134 14988 intel_modeset_init_hw(dev);
02e792fb
DV		 14989
14990 intel_setup_overlay(dev);
484b41dd
JB		 14991
14992 /*
14993 * Make sure any fbs we allocated at startup are properly
14994 * pinned & fenced. When we do the allocation it's too early
14995 * for this.
14996 */
14997 mutex_lock(&dev->struct_mutex);
70e1e0ec 14998 for_each_crtc(dev, c) {
2ff8fde1
MR		 14999 obj = intel_fb_obj(c->primary->fb);
15000 if (obj == NULL)
484b41dd
JB		 15001 continue;
15002
850c4cdc
TU		 15003 if (intel_pin_and_fence_fb_obj(c->primary,
15004 c->primary->fb,
82bc3b2d 15005 c->primary->state,
850c4cdc 15006 NULL)) {
484b41dd
JB		 15007 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15008 to_intel_crtc(c)->pipe);
66e514c1
DA		 15009 drm_framebuffer_unreference(c->primary->fb);
15010 c->primary->fb = NULL;
afd65eb4 15011 update_state_fb(c->primary);
484b41dd
JB		 15012 }
15013 }
15014 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 15015
15016 intel_backlight_register(dev);
79e53945
JB		 15017}
15018
4932e2c3
ID		 15019void intel_connector_unregister(struct intel_connector *intel_connector)
15020{
15021 struct drm_connector *connector = &intel_connector->base;
15022
15023 intel_panel_destroy_backlight(connector);
34ea3d38 15024 drm_connector_unregister(connector);
4932e2c3
ID		 15025}
15026
79e53945
JB		 15027void intel_modeset_cleanup(struct drm_device *dev)
15028{
652c393a 15029 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15030 struct drm_connector *connector;
652c393a 15031
2eb5252e
ID		 15032 intel_disable_gt_powersave(dev);
15033
0962c3c9
VS		 15034 intel_backlight_unregister(dev);
15035
fd0c0642
DV		 15036 /*
15037 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15038 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15039 * experience fancy races otherwise.
15040 */
2aeb7d3a 15041 intel_irq_uninstall(dev_priv);
eb21b92b 15042
fd0c0642
DV		 15043 /*
15044 * Due to the hpd irq storm handling the hotplug work can re-arm the
15045 * poll handlers. Hence disable polling after hpd handling is shut down.
15046 */
f87ea761 15047 drm_kms_helper_poll_fini(dev);
fd0c0642 15048
652c393a
JB		 15049 mutex_lock(&dev->struct_mutex);
15050
723bfd70
JB		 15051 intel_unregister_dsm_handler();
15052
7ff0ebcc 15053 intel_fbc_disable(dev);
e70236a8 15054
69341a5e
KH		 15055 mutex_unlock(&dev->struct_mutex);
15056
1630fe75
CW		 15057 /* flush any delayed tasks or pending work */
15058 flush_scheduled_work();
15059
db31af1d
JN		 15060 /* destroy the backlight and sysfs files before encoders/connectors */
15061 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15062 struct intel_connector *intel_connector;
15063
15064 intel_connector = to_intel_connector(connector);
15065 intel_connector->unregister(intel_connector);
db31af1d 15066 }
d9255d57 15067
79e53945 15068 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15069
15070 intel_cleanup_overlay(dev);
ae48434c
ID		 15071
15072 mutex_lock(&dev->struct_mutex);
15073 intel_cleanup_gt_powersave(dev);
15074 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15075}
15076
f1c79df3
ZW		 15077/*
15078 * Return which encoder is currently attached for connector.
15079 */
df0e9248 15080struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15081{
df0e9248
CW		 15082 return &intel_attached_encoder(connector)->base;
15083}
f1c79df3 15084
df0e9248
CW		 15085void intel_connector_attach_encoder(struct intel_connector *connector,
15086 struct intel_encoder *encoder)
15087{
15088 connector->encoder = encoder;
15089 drm_mode_connector_attach_encoder(&connector->base,
15090 &encoder->base);
79e53945 15091}
28d52043
DA		 15092
15093/*
15094 * set vga decode state - true == enable VGA decode
15095 */
15096int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15097{
15098 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15099 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15100 u16 gmch_ctrl;
15101
75fa041d
CW		 15102 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15103 DRM_ERROR("failed to read control word\n");
15104 return -EIO;
15105 }
15106
c0cc8a55
CW		 15107 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15108 return 0;
15109
28d52043
DA		 15110 if (state)
15111 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15112 else
15113 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15114
15115 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15116 DRM_ERROR("failed to write control word\n");
15117 return -EIO;
15118 }
15119
28d52043
DA		 15120 return 0;
15121}
c4a1d9e4 15122
c4a1d9e4 15123struct intel_display_error_state {
ff57f1b0
PZ		 15124
15125 u32 power_well_driver;
15126
63b66e5b
CW		 15127 int num_transcoders;
15128
c4a1d9e4
CW		 15129 struct intel_cursor_error_state {
15130 u32 control;
15131 u32 position;
15132 u32 base;
15133 u32 size;
52331309 15134 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15135
15136 struct intel_pipe_error_state {
ddf9c536 15137 bool power_domain_on;
c4a1d9e4 15138 u32 source;
f301b1e1 15139 u32 stat;
52331309 15140 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15141
15142 struct intel_plane_error_state {
15143 u32 control;
15144 u32 stride;
15145 u32 size;
15146 u32 pos;
15147 u32 addr;
15148 u32 surface;
15149 u32 tile_offset;
52331309 15150 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15151
15152 struct intel_transcoder_error_state {
ddf9c536 15153 bool power_domain_on;
63b66e5b
CW		 15154 enum transcoder cpu_transcoder;
15155
15156 u32 conf;
15157
15158 u32 htotal;
15159 u32 hblank;
15160 u32 hsync;
15161 u32 vtotal;
15162 u32 vblank;
15163 u32 vsync;
15164 } transcoder[4];
c4a1d9e4
CW		 15165};
15166
15167struct intel_display_error_state *
15168intel_display_capture_error_state(struct drm_device *dev)
15169{
fbee40df 15170 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15171 struct intel_display_error_state *error;
63b66e5b
CW		 15172 int transcoders[] = {
15173 TRANSCODER_A,
15174 TRANSCODER_B,
15175 TRANSCODER_C,
15176 TRANSCODER_EDP,
15177 };
c4a1d9e4
CW		 15178 int i;
15179
63b66e5b
CW		 15180 if (INTEL_INFO(dev)->num_pipes == 0)
15181 return NULL;
15182
9d1cb914 15183 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15184 if (error == NULL)
15185 return NULL;
15186
190be112 15187 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15188 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15189
055e393f 15190 for_each_pipe(dev_priv, i) {
ddf9c536 15191 error->pipe[i].power_domain_on =
f458ebbc
DV		 15192 __intel_display_power_is_enabled(dev_priv,
15193 POWER_DOMAIN_PIPE(i));
ddf9c536 15194 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15195 continue;
15196
5efb3e28
VS		 15197 error->cursor[i].control = I915_READ(CURCNTR(i));
15198 error->cursor[i].position = I915_READ(CURPOS(i));
15199 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15200
15201 error->plane[i].control = I915_READ(DSPCNTR(i));
15202 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15203 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15204 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15205 error->plane[i].pos = I915_READ(DSPPOS(i));
15206 }
ca291363
PZ		 15207 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15208 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15209 if (INTEL_INFO(dev)->gen >= 4) {
15210 error->plane[i].surface = I915_READ(DSPSURF(i));
15211 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15212 }
15213
c4a1d9e4 15214 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15215
3abfce77 15216 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15217 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15218 }
15219
15220 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15221 if (HAS_DDI(dev_priv->dev))
15222 error->num_transcoders++; /* Account for eDP. */
15223
15224 for (i = 0; i < error->num_transcoders; i++) {
15225 enum transcoder cpu_transcoder = transcoders[i];
15226
ddf9c536 15227 error->transcoder[i].power_domain_on =
f458ebbc 15228 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15229 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15230 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15231 continue;
15232
63b66e5b
CW		 15233 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15234
15235 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15236 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15237 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15238 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15239 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15240 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15241 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15242 }
15243
15244 return error;
15245}
15246
edc3d884
MK		 15247#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15248
c4a1d9e4 15249void
edc3d884 15250intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15251 struct drm_device *dev,
15252 struct intel_display_error_state *error)
15253{
055e393f 15254 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15255 int i;
15256
63b66e5b
CW		 15257 if (!error)
15258 return;
15259
edc3d884 15260 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15261 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15262 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15263 error->power_well_driver);
055e393f 15264 for_each_pipe(dev_priv, i) {
edc3d884 15265 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15266 err_printf(m, " Power: %s\n",
15267 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15268 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15269 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15270
15271 err_printf(m, "Plane [%d]:\n", i);
15272 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15273 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15274 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15275 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15276 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15277 }
4b71a570 15278 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15279 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15280 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15281 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15282 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15283 }
15284
edc3d884
MK		 15285 err_printf(m, "Cursor [%d]:\n", i);
15286 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15287 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15288 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15289 }
63b66e5b
CW		 15290
15291 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15292 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15293 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15294 err_printf(m, " Power: %s\n",
15295 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15296 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15297 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15298 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15299 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15300 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15301 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15302 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15303 }
c4a1d9e4 15304}
e2fcdaa9
VS		 15305
15306void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15307{
15308 struct intel_crtc *crtc;
15309
15310 for_each_intel_crtc(dev, crtc) {
15311 struct intel_unpin_work *work;
e2fcdaa9 15312
5e2d7afc 15313 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15314
15315 work = crtc->unpin_work;
15316
15317 if (work && work->event &&
15318 work->event->base.file_priv == file) {
15319 kfree(work->event);
15320 work->event = NULL;
15321 }
15322
5e2d7afc 15323 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15324 }
15325}
Linux kernel - Deliverables
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