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drm/i915: Fixup kerneldoc for struct intel_context
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
e7457a9a 110
0e32b39c
DA		 111static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
112{
113 if (!connector->mst_port)
114 return connector->encoder;
115 else
116 return &connector->mst_port->mst_encoders[pipe]->base;
117}
118
79e53945 119typedef struct {
0206e353 120 int min, max;
79e53945
JB		 121} intel_range_t;
122
123typedef struct {
0206e353
AJ		 124 int dot_limit;
125 int p2_slow, p2_fast;
79e53945
JB		 126} intel_p2_t;
127
d4906093
ML		 128typedef struct intel_limit intel_limit_t;
129struct intel_limit {
0206e353
AJ		 130 intel_range_t dot, vco, n, m, m1, m2, p, p1;
131 intel_p2_t p2;
d4906093 132};
79e53945 133
d2acd215
DV		 134int
135intel_pch_rawclk(struct drm_device *dev)
136{
137 struct drm_i915_private *dev_priv = dev->dev_private;
138
139 WARN_ON(!HAS_PCH_SPLIT(dev));
140
141 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
142}
143
021357ac
CW		 144static inline u32 /* units of 100MHz */
145intel_fdi_link_freq(struct drm_device *dev)
146{
8b99e68c
CW		 147 if (IS_GEN5(dev)) {
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
150 } else
151 return 27;
021357ac
CW		 152}
153
5d536e28 154static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 155 .dot = { .min = 25000, .max = 350000 },
9c333719 156 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 157 .n = { .min = 2, .max = 16 },
0206e353
AJ		 158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 165};
166
5d536e28
DV		 167static const intel_limit_t intel_limits_i8xx_dvo = {
168 .dot = { .min = 25000, .max = 350000 },
9c333719 169 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 170 .n = { .min = 2, .max = 16 },
5d536e28
DV		 171 .m = { .min = 96, .max = 140 },
172 .m1 = { .min = 18, .max = 26 },
173 .m2 = { .min = 6, .max = 16 },
174 .p = { .min = 4, .max = 128 },
175 .p1 = { .min = 2, .max = 33 },
176 .p2 = { .dot_limit = 165000,
177 .p2_slow = 4, .p2_fast = 4 },
178};
179
e4b36699 180static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 181 .dot = { .min = 25000, .max = 350000 },
9c333719 182 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 183 .n = { .min = 2, .max = 16 },
0206e353
AJ		 184 .m = { .min = 96, .max = 140 },
185 .m1 = { .min = 18, .max = 26 },
186 .m2 = { .min = 6, .max = 16 },
187 .p = { .min = 4, .max = 128 },
188 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 14, .p2_fast = 7 },
e4b36699 191};
273e27ca 192
e4b36699 193static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 194 .dot = { .min = 20000, .max = 400000 },
195 .vco = { .min = 1400000, .max = 2800000 },
196 .n = { .min = 1, .max = 6 },
197 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 198 .m1 = { .min = 8, .max = 18 },
199 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 200 .p = { .min = 5, .max = 80 },
201 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 202 .p2 = { .dot_limit = 200000,
203 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 207 .dot = { .min = 20000, .max = 400000 },
208 .vco = { .min = 1400000, .max = 2800000 },
209 .n = { .min = 1, .max = 6 },
210 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 211 .m1 = { .min = 8, .max = 18 },
212 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 213 .p = { .min = 7, .max = 98 },
214 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 215 .p2 = { .dot_limit = 112000,
216 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 217};
218
273e27ca 219
e4b36699 220static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 221 .dot = { .min = 25000, .max = 270000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 17, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 10, .max = 30 },
228 .p1 = { .min = 1, .max = 3},
229 .p2 = { .dot_limit = 270000,
230 .p2_slow = 10,
231 .p2_fast = 10
044c7c41 232 },
e4b36699
KP		 233};
234
235static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 236 .dot = { .min = 22000, .max = 400000 },
237 .vco = { .min = 1750000, .max = 3500000},
238 .n = { .min = 1, .max = 4 },
239 .m = { .min = 104, .max = 138 },
240 .m1 = { .min = 16, .max = 23 },
241 .m2 = { .min = 5, .max = 11 },
242 .p = { .min = 5, .max = 80 },
243 .p1 = { .min = 1, .max = 8},
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 246};
247
248static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 249 .dot = { .min = 20000, .max = 115000 },
250 .vco = { .min = 1750000, .max = 3500000 },
251 .n = { .min = 1, .max = 3 },
252 .m = { .min = 104, .max = 138 },
253 .m1 = { .min = 17, .max = 23 },
254 .m2 = { .min = 5, .max = 11 },
255 .p = { .min = 28, .max = 112 },
256 .p1 = { .min = 2, .max = 8 },
257 .p2 = { .dot_limit = 0,
258 .p2_slow = 14, .p2_fast = 14
044c7c41 259 },
e4b36699
KP		 260};
261
262static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 263 .dot = { .min = 80000, .max = 224000 },
264 .vco = { .min = 1750000, .max = 3500000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 104, .max = 138 },
267 .m1 = { .min = 17, .max = 23 },
268 .m2 = { .min = 5, .max = 11 },
269 .p = { .min = 14, .max = 42 },
270 .p1 = { .min = 2, .max = 6 },
271 .p2 = { .dot_limit = 0,
272 .p2_slow = 7, .p2_fast = 7
044c7c41 273 },
e4b36699
KP		 274};
275
f2b115e6 276static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 277 .dot = { .min = 20000, .max = 400000},
278 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 279 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 280 .n = { .min = 3, .max = 6 },
281 .m = { .min = 2, .max = 256 },
273e27ca 282 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 283 .m1 = { .min = 0, .max = 0 },
284 .m2 = { .min = 0, .max = 254 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 287 .p2 = { .dot_limit = 200000,
288 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 289};
290
f2b115e6 291static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 292 .dot = { .min = 20000, .max = 400000 },
293 .vco = { .min = 1700000, .max = 3500000 },
294 .n = { .min = 3, .max = 6 },
295 .m = { .min = 2, .max = 256 },
296 .m1 = { .min = 0, .max = 0 },
297 .m2 = { .min = 0, .max = 254 },
298 .p = { .min = 7, .max = 112 },
299 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 300 .p2 = { .dot_limit = 112000,
301 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 302};
303
273e27ca
EA		 304/* Ironlake / Sandybridge
305 *
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
308 */
b91ad0ec 309static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 310 .dot = { .min = 25000, .max = 350000 },
311 .vco = { .min = 1760000, .max = 3510000 },
312 .n = { .min = 1, .max = 5 },
313 .m = { .min = 79, .max = 127 },
314 .m1 = { .min = 12, .max = 22 },
315 .m2 = { .min = 5, .max = 9 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 225000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
b91ad0ec 322static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 118 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 127 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 56 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360};
361
362static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 363 .dot = { .min = 25000, .max = 350000 },
364 .vco = { .min = 1760000, .max = 3510000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 79, .max = 126 },
367 .m1 = { .min = 12, .max = 22 },
368 .m2 = { .min = 5, .max = 9 },
369 .p = { .min = 14, .max = 42 },
0206e353 370 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 371 .p2 = { .dot_limit = 225000,
372 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 373};
374
dc730512 375static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 383 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 384 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 385 .m1 = { .min = 2, .max = 3 },
386 .m2 = { .min = 11, .max = 156 },
b99ab663 387 .p1 = { .min = 2, .max = 3 },
5fdc9c49 388 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 389};
390
ef9348c8
CML		 391static const intel_limit_t intel_limits_chv = {
392 /*
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
397 */
398 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 399 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 400 .n = { .min = 1, .max = 1 },
401 .m1 = { .min = 2, .max = 2 },
402 .m2 = { .min = 24 << 22, .max = 175 << 22 },
403 .p1 = { .min = 2, .max = 4 },
404 .p2 = { .p2_slow = 1, .p2_fast = 14 },
405};
406
5ab7b0b7
ID		 407static const intel_limit_t intel_limits_bxt = {
408 /* FIXME: find real dot limits */
409 .dot = { .min = 0, .max = INT_MAX },
410 .vco = { .min = 4800000, .max = 6480000 },
411 .n = { .min = 1, .max = 1 },
412 .m1 = { .min = 2, .max = 2 },
413 /* FIXME: find real m2 limits */
414 .m2 = { .min = 2 << 22, .max = 255 << 22 },
415 .p1 = { .min = 2, .max = 4 },
416 .p2 = { .p2_slow = 1, .p2_fast = 20 },
417};
418
6b4bf1c4
VS		 419static void vlv_clock(int refclk, intel_clock_t *clock)
420{
421 clock->m = clock->m1 * clock->m2;
422 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 423 if (WARN_ON(clock->n == 0 || clock->p == 0))
424 return;
fb03ac01
VS		 425 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
426 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 427}
428
e0638cdf
PZ		 429/**
430 * Returns whether any output on the specified pipe is of the specified type
431 */
4093561b 432bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 433{
409ee761 434 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 435 struct intel_encoder *encoder;
436
409ee761 437 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 438 if (encoder->type == type)
439 return true;
440
441 return false;
442}
443
d0737e1d
ACO		 444/**
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
448 * encoder->crtc.
449 */
a93e255f
ACO		 450static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
451 int type)
d0737e1d 452{
a93e255f
ACO		 453 struct drm_atomic_state *state = crtc_state->base.state;
454 struct drm_connector_state *connector_state;
d0737e1d 455 struct intel_encoder *encoder;
a93e255f
ACO		 456 int i, num_connectors = 0;
457
458 for (i = 0; i < state->num_connector; i++) {
459 if (!state->connectors[i])
460 continue;
461
462 connector_state = state->connector_states[i];
463 if (connector_state->crtc != crtc_state->base.crtc)
464 continue;
465
466 num_connectors++;
d0737e1d 467
a93e255f
ACO		 468 encoder = to_intel_encoder(connector_state->best_encoder);
469 if (encoder->type == type)
d0737e1d 470 return true;
a93e255f
ACO		 471 }
472
473 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 474
475 return false;
476}
477
a93e255f
ACO		 478static const intel_limit_t *
479intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 480{
a93e255f 481 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 482 const intel_limit_t *limit;
b91ad0ec 483
a93e255f 484 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 485 if (intel_is_dual_link_lvds(dev)) {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_dual_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_dual_lvds;
490 } else {
1b894b59 491 if (refclk == 100000)
b91ad0ec
ZW		 492 limit = &intel_limits_ironlake_single_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_single_lvds;
495 }
c6bb3538 496 } else
b91ad0ec 497 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 498
499 return limit;
500}
501
a93e255f
ACO		 502static const intel_limit_t *
503intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 504{
a93e255f 505 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 506 const intel_limit_t *limit;
507
a93e255f 508 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev))
e4b36699 510 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 511 else
e4b36699 512 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 513 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
514 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 515 limit = &intel_limits_g4x_hdmi;
a93e255f 516 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 517 limit = &intel_limits_g4x_sdvo;
044c7c41 518 } else /* The option is for other outputs */
e4b36699 519 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 520
521 return limit;
522}
523
a93e255f
ACO		 524static const intel_limit_t *
525intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 526{
a93e255f 527 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 528 const intel_limit_t *limit;
529
5ab7b0b7
ID		 530 if (IS_BROXTON(dev))
531 limit = &intel_limits_bxt;
532 else if (HAS_PCH_SPLIT(dev))
a93e255f 533 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 534 else if (IS_G4X(dev)) {
a93e255f 535 limit = intel_g4x_limit(crtc_state);
f2b115e6 536 } else if (IS_PINEVIEW(dev)) {
a93e255f 537 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 538 limit = &intel_limits_pineview_lvds;
2177832f 539 else
f2b115e6 540 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 541 } else if (IS_CHERRYVIEW(dev)) {
542 limit = &intel_limits_chv;
a0c4da24 543 } else if (IS_VALLEYVIEW(dev)) {
dc730512 544 limit = &intel_limits_vlv;
a6c45cf0 545 } else if (!IS_GEN2(dev)) {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 547 limit = &intel_limits_i9xx_lvds;
548 else
549 limit = &intel_limits_i9xx_sdvo;
79e53945 550 } else {
a93e255f 551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 552 limit = &intel_limits_i8xx_lvds;
a93e255f 553 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 554 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 555 else
556 limit = &intel_limits_i8xx_dac;
79e53945
JB		 557 }
558 return limit;
559}
560
f2b115e6
AJ		 561/* m1 is reserved as 0 in Pineview, n is a ring counter */
562static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 563{
2177832f
SL		 564 clock->m = clock->m2 + 2;
565 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 566 if (WARN_ON(clock->n == 0 || clock->p == 0))
567 return;
fb03ac01
VS		 568 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
569 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 570}
571
7429e9d4
DV		 572static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
573{
574 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
575}
576
ac58c3f0 577static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 578{
7429e9d4 579 clock->m = i9xx_dpll_compute_m(clock);
79e53945 580 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 581 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
582 return;
fb03ac01
VS		 583 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
584 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 585}
586
ef9348c8
CML		 587static void chv_clock(int refclk, intel_clock_t *clock)
588{
589 clock->m = clock->m1 * clock->m2;
590 clock->p = clock->p1 * clock->p2;
591 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 return;
593 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
594 clock->n << 22);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596}
597
7c04d1d9 598#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 599/**
600 * Returns whether the given set of divisors are valid for a given refclk with
601 * the given connectors.
602 */
603
1b894b59
CW		 604static bool intel_PLL_is_valid(struct drm_device *dev,
605 const intel_limit_t *limit,
606 const intel_clock_t *clock)
79e53945 607{
f01b7962
VS		 608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
79e53945 610 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 611 INTELPllInvalid("p1 out of range\n");
79e53945 612 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 613 INTELPllInvalid("m2 out of range\n");
79e53945 614 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 615 INTELPllInvalid("m1 out of range\n");
f01b7962 616
5ab7b0b7 617 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
5ab7b0b7 621 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
79e53945 628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 629 INTELPllInvalid("vco out of range\n");
79e53945
JB		 630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 634 INTELPllInvalid("dot out of range\n");
79e53945
JB		 635
636 return true;
637}
638
d4906093 639static bool
a93e255f
ACO		 640i9xx_find_best_dpll(const intel_limit_t *limit,
641 struct intel_crtc_state *crtc_state,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
79e53945 644{
a93e255f 645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 646 struct drm_device *dev = crtc->base.dev;
79e53945 647 intel_clock_t clock;
79e53945
JB		 648 int err = target;
649
a93e255f 650 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 651 /*
a210b028
DV		 652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
79e53945 655 */
1974cad0 656 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
0206e353 667 memset(best_clock, 0, sizeof(*best_clock));
79e53945 668
42158660
ZY		 669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
670 clock.m1++) {
671 for (clock.m2 = limit->m2.min;
672 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 673 if (clock.m2 >= clock.m1)
42158660
ZY		 674 break;
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 679 int this_err;
680
ac58c3f0
DV		 681 i9xx_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
683 &clock))
684 continue;
685 if (match_clock &&
686 clock.p != match_clock->p)
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
691 *best_clock = clock;
692 err = this_err;
693 }
694 }
695 }
696 }
697 }
698
699 return (err != target);
700}
701
702static bool
a93e255f
ACO		 703pnv_find_best_dpll(const intel_limit_t *limit,
704 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
79e53945 707{
a93e255f 708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 709 struct drm_device *dev = crtc->base.dev;
79e53945 710 intel_clock_t clock;
79e53945
JB		 711 int err = target;
712
a93e255f 713 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 714 /*
a210b028
DV		 715 * For LVDS just rely on its current settings for dual-channel.
716 * We haven't figured out how to reliably set up different
717 * single/dual channel state, if we even can.
79e53945 718 */
1974cad0 719 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 720 clock.p2 = limit->p2.p2_fast;
721 else
722 clock.p2 = limit->p2.p2_slow;
723 } else {
724 if (target < limit->p2.dot_limit)
725 clock.p2 = limit->p2.p2_slow;
726 else
727 clock.p2 = limit->p2.p2_fast;
728 }
729
0206e353 730 memset(best_clock, 0, sizeof(*best_clock));
79e53945 731
42158660
ZY		 732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
733 clock.m1++) {
734 for (clock.m2 = limit->m2.min;
735 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 736 for (clock.n = limit->n.min;
737 clock.n <= limit->n.max; clock.n++) {
738 for (clock.p1 = limit->p1.min;
739 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 740 int this_err;
741
ac58c3f0 742 pineview_clock(refclk, &clock);
1b894b59
CW		 743 if (!intel_PLL_is_valid(dev, limit,
744 &clock))
79e53945 745 continue;
cec2f356
SP		 746 if (match_clock &&
747 clock.p != match_clock->p)
748 continue;
79e53945
JB		 749
750 this_err = abs(clock.dot - target);
751 if (this_err < err) {
752 *best_clock = clock;
753 err = this_err;
754 }
755 }
756 }
757 }
758 }
759
760 return (err != target);
761}
762
d4906093 763static bool
a93e255f
ACO		 764g4x_find_best_dpll(const intel_limit_t *limit,
765 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 766 int target, int refclk, intel_clock_t *match_clock,
767 intel_clock_t *best_clock)
d4906093 768{
a93e255f 769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 770 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 771 intel_clock_t clock;
772 int max_n;
773 bool found;
6ba770dc
AJ		 774 /* approximately equals target * 0.00585 */
775 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 776 found = false;
777
a93e255f 778 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 779 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 780 clock.p2 = limit->p2.p2_fast;
781 else
782 clock.p2 = limit->p2.p2_slow;
783 } else {
784 if (target < limit->p2.dot_limit)
785 clock.p2 = limit->p2.p2_slow;
786 else
787 clock.p2 = limit->p2.p2_fast;
788 }
789
790 memset(best_clock, 0, sizeof(*best_clock));
791 max_n = limit->n.max;
f77f13e2 792 /* based on hardware requirement, prefer smaller n to precision */
d4906093 793 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 794 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 795 for (clock.m1 = limit->m1.max;
796 clock.m1 >= limit->m1.min; clock.m1--) {
797 for (clock.m2 = limit->m2.max;
798 clock.m2 >= limit->m2.min; clock.m2--) {
799 for (clock.p1 = limit->p1.max;
800 clock.p1 >= limit->p1.min; clock.p1--) {
801 int this_err;
802
ac58c3f0 803 i9xx_clock(refclk, &clock);
1b894b59
CW		 804 if (!intel_PLL_is_valid(dev, limit,
805 &clock))
d4906093 806 continue;
1b894b59
CW		 807
808 this_err = abs(clock.dot - target);
d4906093
ML		 809 if (this_err < err_most) {
810 *best_clock = clock;
811 err_most = this_err;
812 max_n = clock.n;
813 found = true;
814 }
815 }
816 }
817 }
818 }
2c07245f
ZW		 819 return found;
820}
821
d5dd62bd
ID		 822/*
823 * Check if the calculated PLL configuration is more optimal compared to the
824 * best configuration and error found so far. Return the calculated error.
825 */
826static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
827 const intel_clock_t *calculated_clock,
828 const intel_clock_t *best_clock,
829 unsigned int best_error_ppm,
830 unsigned int *error_ppm)
831{
9ca3ba01
ID		 832 /*
833 * For CHV ignore the error and consider only the P value.
834 * Prefer a bigger P value based on HW requirements.
835 */
836 if (IS_CHERRYVIEW(dev)) {
837 *error_ppm = 0;
838
839 return calculated_clock->p > best_clock->p;
840 }
841
24be4e46
ID		 842 if (WARN_ON_ONCE(!target_freq))
843 return false;
844
d5dd62bd
ID		 845 *error_ppm = div_u64(1000000ULL *
846 abs(target_freq - calculated_clock->dot),
847 target_freq);
848 /*
849 * Prefer a better P value over a better (smaller) error if the error
850 * is small. Ensure this preference for future configurations too by
851 * setting the error to 0.
852 */
853 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 *error_ppm = 0;
855
856 return true;
857 }
858
859 return *error_ppm + 10 < best_error_ppm;
860}
861
a0c4da24 862static bool
a93e255f
ACO		 863vlv_find_best_dpll(const intel_limit_t *limit,
864 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 865 int target, int refclk, intel_clock_t *match_clock,
866 intel_clock_t *best_clock)
a0c4da24 867{
a93e255f 868 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 869 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 870 intel_clock_t clock;
69e4f900 871 unsigned int bestppm = 1000000;
27e639bf
VS		 872 /* min update 19.2 MHz */
873 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 874 bool found = false;
a0c4da24 875
6b4bf1c4
VS		 876 target *= 5; /* fast clock */
877
878 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 879
880 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 881 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 882 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 883 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 884 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 885 clock.p = clock.p1 * clock.p2;
a0c4da24 886 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 887 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 888 unsigned int ppm;
69e4f900 889
6b4bf1c4
VS		 890 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
891 refclk * clock.m1);
892
893 vlv_clock(refclk, &clock);
43b0ac53 894
f01b7962
VS		 895 if (!intel_PLL_is_valid(dev, limit,
896 &clock))
43b0ac53
VS		 897 continue;
898
d5dd62bd
ID		 899 if (!vlv_PLL_is_optimal(dev, target,
900 &clock,
901 best_clock,
902 bestppm, &ppm))
903 continue;
6b4bf1c4 904
d5dd62bd
ID		 905 *best_clock = clock;
906 bestppm = ppm;
907 found = true;
a0c4da24
JB		 908 }
909 }
910 }
911 }
a0c4da24 912
49e497ef 913 return found;
a0c4da24 914}
a4fc5ed6 915
ef9348c8 916static bool
a93e255f
ACO		 917chv_find_best_dpll(const intel_limit_t *limit,
918 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 919 int target, int refclk, intel_clock_t *match_clock,
920 intel_clock_t *best_clock)
921{
a93e255f 922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 923 struct drm_device *dev = crtc->base.dev;
9ca3ba01 924 unsigned int best_error_ppm;
ef9348c8
CML		 925 intel_clock_t clock;
926 uint64_t m2;
927 int found = false;
928
929 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 930 best_error_ppm = 1000000;
ef9348c8
CML		 931
932 /*
933 * Based on hardware doc, the n always set to 1, and m1 always
934 * set to 2. If requires to support 200Mhz refclk, we need to
935 * revisit this because n may not 1 anymore.
936 */
937 clock.n = 1, clock.m1 = 2;
938 target *= 5; /* fast clock */
939
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast;
942 clock.p2 >= limit->p2.p2_slow;
943 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 944 unsigned int error_ppm;
ef9348c8
CML		 945
946 clock.p = clock.p1 * clock.p2;
947
948 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
949 clock.n) << 22, refclk * clock.m1);
950
951 if (m2 > INT_MAX/clock.m1)
952 continue;
953
954 clock.m2 = m2;
955
956 chv_clock(refclk, &clock);
957
958 if (!intel_PLL_is_valid(dev, limit, &clock))
959 continue;
960
9ca3ba01
ID		 961 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
962 best_error_ppm, &error_ppm))
963 continue;
964
965 *best_clock = clock;
966 best_error_ppm = error_ppm;
967 found = true;
ef9348c8
CML		 968 }
969 }
970
971 return found;
972}
973
5ab7b0b7
ID		 974bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
975 intel_clock_t *best_clock)
976{
977 int refclk = i9xx_get_refclk(crtc_state, 0);
978
979 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
980 target_clock, refclk, NULL, best_clock);
981}
982
20ddf665
VS		 983bool intel_crtc_active(struct drm_crtc *crtc)
984{
985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
986
987 /* Be paranoid as we can arrive here with only partial
988 * state retrieved from the hardware during setup.
989 *
241bfc38 990 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 991 * as Haswell has gained clock readout/fastboot support.
992 *
66e514c1 993 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 994 * properly reconstruct framebuffers.
c3d1f436
MR		 995 *
996 * FIXME: The intel_crtc->active here should be switched to
997 * crtc->state->active once we have proper CRTC states wired up
998 * for atomic.
20ddf665 999 */
c3d1f436 1000 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1001 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1002}
1003
a5c961d1
PZ		 1004enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
6e3c9717 1010 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1011}
1012
fbf49ea2
VS		 1013static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1014{
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 u32 reg = PIPEDSL(pipe);
1017 u32 line1, line2;
1018 u32 line_mask;
1019
1020 if (IS_GEN2(dev))
1021 line_mask = DSL_LINEMASK_GEN2;
1022 else
1023 line_mask = DSL_LINEMASK_GEN3;
1024
1025 line1 = I915_READ(reg) & line_mask;
1026 mdelay(5);
1027 line2 = I915_READ(reg) & line_mask;
1028
1029 return line1 == line2;
1030}
1031
ab7ad7f6
KP		 1032/*
1033 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1034 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1035 *
1036 * After disabling a pipe, we can't wait for vblank in the usual way,
1037 * spinning on the vblank interrupt status bit, since we won't actually
1038 * see an interrupt when the pipe is disabled.
1039 *
ab7ad7f6
KP		 1040 * On Gen4 and above:
1041 * wait for the pipe register state bit to turn off
1042 *
1043 * Otherwise:
1044 * wait for the display line value to settle (it usually
1045 * ends up stopping at the start of the next frame).
58e10eb9 1046 *
9d0498a2 1047 */
575f7ab7 1048static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1049{
575f7ab7 1050 struct drm_device *dev = crtc->base.dev;
9d0498a2 1051 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1052 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1053 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1054
1055 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1056 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1057
1058 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1059 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1060 100))
284637d9 1061 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1062 } else {
ab7ad7f6 1063 /* Wait for the display line to settle */
fbf49ea2 1064 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1065 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1066 }
79e53945
JB		 1067}
1068
b0ea7d37
DL		 1069/*
1070 * ibx_digital_port_connected - is the specified port connected?
1071 * @dev_priv: i915 private structure
1072 * @port: the port to test
1073 *
1074 * Returns true if @port is connected, false otherwise.
1075 */
1076bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1077 struct intel_digital_port *port)
1078{
1079 u32 bit;
1080
c36346e3 1081 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1082 switch (port->port) {
c36346e3
DL		 1083 case PORT_B:
1084 bit = SDE_PORTB_HOTPLUG;
1085 break;
1086 case PORT_C:
1087 bit = SDE_PORTC_HOTPLUG;
1088 break;
1089 case PORT_D:
1090 bit = SDE_PORTD_HOTPLUG;
1091 break;
1092 default:
1093 return true;
1094 }
1095 } else {
eba905b2 1096 switch (port->port) {
c36346e3
DL		 1097 case PORT_B:
1098 bit = SDE_PORTB_HOTPLUG_CPT;
1099 break;
1100 case PORT_C:
1101 bit = SDE_PORTC_HOTPLUG_CPT;
1102 break;
1103 case PORT_D:
1104 bit = SDE_PORTD_HOTPLUG_CPT;
1105 break;
1106 default:
1107 return true;
1108 }
b0ea7d37
DL		 1109 }
1110
1111 return I915_READ(SDEISR) & bit;
1112}
1113
b24e7179
JB		 1114static const char *state_string(bool enabled)
1115{
1116 return enabled ? "on" : "off";
1117}
1118
1119/* Only for pre-ILK configs */
55607e8a
DV		 1120void assert_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe, bool state)
b24e7179
JB		 1122{
1123 int reg;
1124 u32 val;
1125 bool cur_state;
1126
1127 reg = DPLL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1130 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1131 "PLL state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133}
b24e7179 1134
23538ef1
JN		 1135/* XXX: the dsi pll is shared between MIPI DSI ports */
1136static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1137{
1138 u32 val;
1139 bool cur_state;
1140
1141 mutex_lock(&dev_priv->dpio_lock);
1142 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1143 mutex_unlock(&dev_priv->dpio_lock);
1144
1145 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1146 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1147 "DSI PLL state assertion failure (expected %s, current %s)\n",
1148 state_string(state), state_string(cur_state));
1149}
1150#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1151#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1152
55607e8a 1153struct intel_shared_dpll *
e2b78267
DV		 1154intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1155{
1156 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1157
6e3c9717 1158 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1159 return NULL;
1160
6e3c9717 1161 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1162}
1163
040484af 1164/* For ILK+ */
55607e8a
DV		 1165void assert_shared_dpll(struct drm_i915_private *dev_priv,
1166 struct intel_shared_dpll *pll,
1167 bool state)
040484af 1168{
040484af 1169 bool cur_state;
5358901f 1170 struct intel_dpll_hw_state hw_state;
040484af 1171
92b27b08 1172 if (WARN (!pll,
46edb027 1173 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1174 return;
ee7b9f93 1175
5358901f 1176 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1177 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1178 "%s assertion failure (expected %s, current %s)\n",
1179 pll->name, state_string(state), state_string(cur_state));
040484af 1180}
040484af
JB		 1181
1182static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1183 enum pipe pipe, bool state)
1184{
1185 int reg;
1186 u32 val;
1187 bool cur_state;
ad80a810
PZ		 1188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1189 pipe);
040484af 1190
affa9354
PZ		 1191 if (HAS_DDI(dev_priv->dev)) {
1192 /* DDI does not have a specific FDI_TX register */
ad80a810 1193 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1194 val = I915_READ(reg);
ad80a810 1195 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1196 } else {
1197 reg = FDI_TX_CTL(pipe);
1198 val = I915_READ(reg);
1199 cur_state = !!(val & FDI_TX_ENABLE);
1200 }
e2c719b7 1201 I915_STATE_WARN(cur_state != state,
040484af
JB		 1202 "FDI TX state assertion failure (expected %s, current %s)\n",
1203 state_string(state), state_string(cur_state));
1204}
1205#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1206#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1207
1208static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, bool state)
1210{
1211 int reg;
1212 u32 val;
1213 bool cur_state;
1214
d63fa0dc
PZ		 1215 reg = FDI_RX_CTL(pipe);
1216 val = I915_READ(reg);
1217 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1218 I915_STATE_WARN(cur_state != state,
040484af
JB		 1219 "FDI RX state assertion failure (expected %s, current %s)\n",
1220 state_string(state), state_string(cur_state));
1221}
1222#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1223#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1224
1225static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe)
1227{
1228 int reg;
1229 u32 val;
1230
1231 /* ILK FDI PLL is always enabled */
3d13ef2e 1232 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1233 return;
1234
bf507ef7 1235 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1236 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1237 return;
1238
040484af
JB		 1239 reg = FDI_TX_CTL(pipe);
1240 val = I915_READ(reg);
e2c719b7 1241 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1242}
1243
55607e8a
DV		 1244void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, bool state)
040484af
JB		 1246{
1247 int reg;
1248 u32 val;
55607e8a 1249 bool cur_state;
040484af
JB		 1250
1251 reg = FDI_RX_CTL(pipe);
1252 val = I915_READ(reg);
55607e8a 1253 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1254 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1255 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1256 state_string(state), state_string(cur_state));
040484af
JB		 1257}
1258
b680c37a
DV		 1259void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1260 enum pipe pipe)
ea0760cf 1261{
bedd4dba
JN		 1262 struct drm_device *dev = dev_priv->dev;
1263 int pp_reg;
ea0760cf
JB		 1264 u32 val;
1265 enum pipe panel_pipe = PIPE_A;
0de3b485 1266 bool locked = true;
ea0760cf 1267
bedd4dba
JN		 1268 if (WARN_ON(HAS_DDI(dev)))
1269 return;
1270
1271 if (HAS_PCH_SPLIT(dev)) {
1272 u32 port_sel;
1273
ea0760cf 1274 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1275 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1276
1277 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1278 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1279 panel_pipe = PIPE_B;
1280 /* XXX: else fix for eDP */
1281 } else if (IS_VALLEYVIEW(dev)) {
1282 /* presumably write lock depends on pipe, not port select */
1283 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1284 panel_pipe = pipe;
ea0760cf
JB		 1285 } else {
1286 pp_reg = PP_CONTROL;
bedd4dba
JN		 1287 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1288 panel_pipe = PIPE_B;
ea0760cf
JB		 1289 }
1290
1291 val = I915_READ(pp_reg);
1292 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1293 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1294 locked = false;
1295
e2c719b7 1296 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1297 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1298 pipe_name(pipe));
ea0760cf
JB		 1299}
1300
93ce0ba6
JN		 1301static void assert_cursor(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, bool state)
1303{
1304 struct drm_device *dev = dev_priv->dev;
1305 bool cur_state;
1306
d9d82081 1307 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1308 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1309 else
5efb3e28 1310 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1311
e2c719b7 1312 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1313 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe), state_string(state), state_string(cur_state));
1315}
1316#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1317#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1318
b840d907
JB		 1319void assert_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe, bool state)
b24e7179
JB		 1321{
1322 int reg;
1323 u32 val;
63d7bbe9 1324 bool cur_state;
702e7a56
PZ		 1325 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1326 pipe);
b24e7179 1327
b6b5d049
VS		 1328 /* if we need the pipe quirk it must be always on */
1329 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1330 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1331 state = true;
1332
f458ebbc 1333 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1334 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1335 cur_state = false;
1336 } else {
1337 reg = PIPECONF(cpu_transcoder);
1338 val = I915_READ(reg);
1339 cur_state = !!(val & PIPECONF_ENABLE);
1340 }
1341
e2c719b7 1342 I915_STATE_WARN(cur_state != state,
63d7bbe9 1343 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1344 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1345}
1346
931872fc
CW		 1347static void assert_plane(struct drm_i915_private *dev_priv,
1348 enum plane plane, bool state)
b24e7179
JB		 1349{
1350 int reg;
1351 u32 val;
931872fc 1352 bool cur_state;
b24e7179
JB		 1353
1354 reg = DSPCNTR(plane);
1355 val = I915_READ(reg);
931872fc 1356 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1357 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1358 "plane %c assertion failure (expected %s, current %s)\n",
1359 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1360}
1361
931872fc
CW		 1362#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1363#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1364
b24e7179
JB		 1365static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367{
653e1026 1368 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1369 int reg, i;
1370 u32 val;
1371 int cur_pipe;
1372
653e1026
VS		 1373 /* Primary planes are fixed to pipes on gen4+ */
1374 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1375 reg = DSPCNTR(pipe);
1376 val = I915_READ(reg);
e2c719b7 1377 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1378 "plane %c assertion failure, should be disabled but not\n",
1379 plane_name(pipe));
19ec1358 1380 return;
28c05794 1381 }
19ec1358 1382
b24e7179 1383 /* Need to check both planes against the pipe */
055e393f 1384 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1385 reg = DSPCNTR(i);
1386 val = I915_READ(reg);
1387 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1388 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1389 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1390 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1391 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1392 }
1393}
1394
19332d7a
JB		 1395static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
20674eef 1398 struct drm_device *dev = dev_priv->dev;
1fe47785 1399 int reg, sprite;
19332d7a
JB		 1400 u32 val;
1401
7feb8b88 1402 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1403 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1404 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1405 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1406 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407 sprite, pipe_name(pipe));
1408 }
1409 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1410 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1411 reg = SPCNTR(pipe, sprite);
20674eef 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1415 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1416 }
1417 } else if (INTEL_INFO(dev)->gen >= 7) {
1418 reg = SPRCTL(pipe);
19332d7a 1419 val = I915_READ(reg);
e2c719b7 1420 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1422 plane_name(pipe), pipe_name(pipe));
1423 } else if (INTEL_INFO(dev)->gen >= 5) {
1424 reg = DVSCNTR(pipe);
19332d7a 1425 val = I915_READ(reg);
e2c719b7 1426 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1427 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1428 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1429 }
1430}
1431
08c71e5e
VS		 1432static void assert_vblank_disabled(struct drm_crtc *crtc)
1433{
e2c719b7 1434 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1435 drm_crtc_vblank_put(crtc);
1436}
1437
89eff4be 1438static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1439{
1440 u32 val;
1441 bool enabled;
1442
e2c719b7 1443 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1444
92f2584a
JB		 1445 val = I915_READ(PCH_DREF_CONTROL);
1446 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1447 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1448 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1449}
1450
ab9412ba
DV		 1451static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe)
92f2584a
JB		 1453{
1454 int reg;
1455 u32 val;
1456 bool enabled;
1457
ab9412ba 1458 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1459 val = I915_READ(reg);
1460 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1461 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1462 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1463 pipe_name(pipe));
92f2584a
JB		 1464}
1465
4e634389
KP		 1466static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1468{
1469 if ((val & DP_PORT_EN) == 0)
1470 return false;
1471
1472 if (HAS_PCH_CPT(dev_priv->dev)) {
1473 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1474 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1475 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1476 return false;
44f37d1f
CML		 1477 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1478 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1479 return false;
f0575e92
KP		 1480 } else {
1481 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 return false;
1483 }
1484 return true;
1485}
1486
1519b995
KP		 1487static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1488 enum pipe pipe, u32 val)
1489{
dc0fa718 1490 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1491 return false;
1492
1493 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1494 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1495 return false;
44f37d1f
CML		 1496 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1498 return false;
1519b995 1499 } else {
dc0fa718 1500 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1501 return false;
1502 }
1503 return true;
1504}
1505
1506static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1507 enum pipe pipe, u32 val)
1508{
1509 if ((val & LVDS_PORT_EN) == 0)
1510 return false;
1511
1512 if (HAS_PCH_CPT(dev_priv->dev)) {
1513 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1514 return false;
1515 } else {
1516 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 return false;
1518 }
1519 return true;
1520}
1521
1522static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1523 enum pipe pipe, u32 val)
1524{
1525 if ((val & ADPA_DAC_ENABLE) == 0)
1526 return false;
1527 if (HAS_PCH_CPT(dev_priv->dev)) {
1528 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1529 return false;
1530 } else {
1531 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 return false;
1533 }
1534 return true;
1535}
1536
291906f1 1537static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1538 enum pipe pipe, int reg, u32 port_sel)
291906f1 1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1542 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1546 && (val & DP_PIPEB_SELECT),
de9a35ab 1547 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe, int reg)
1552{
47a05eca 1553 u32 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1555 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 reg, pipe_name(pipe));
de9a35ab 1557
e2c719b7 1558 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1559 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1560 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1561}
1562
1563static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
1565{
1566 int reg;
1567 u32 val;
291906f1 1568
f0575e92
KP		 1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1570 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1572
1573 reg = PCH_ADPA;
1574 val = I915_READ(reg);
e2c719b7 1575 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1576 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1577 pipe_name(pipe));
291906f1
JB		 1578
1579 reg = PCH_LVDS;
1580 val = I915_READ(reg);
e2c719b7 1581 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1582 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1583 pipe_name(pipe));
291906f1 1584
e2debe91
PZ		 1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1586 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1588}
1589
40e9cf64
JB		 1590static void intel_init_dpio(struct drm_device *dev)
1591{
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593
1594 if (!IS_VALLEYVIEW(dev))
1595 return;
1596
a09caddd
CML		 1597 /*
1598 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1599 * CHV x1 PHY (DP/HDMI D)
1600 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1601 */
1602 if (IS_CHERRYVIEW(dev)) {
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1605 } else {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1607 }
5382f5f3
JB		 1608}
1609
d288f65f 1610static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1611 const struct intel_crtc_state *pipe_config)
87442f73 1612{
426115cf
DV		 1613 struct drm_device *dev = crtc->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 int reg = DPLL(crtc->pipe);
d288f65f 1616 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1617
426115cf 1618 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1619
1620 /* No really, not for ILK+ */
1621 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1622
1623 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1624 if (IS_MOBILE(dev_priv->dev))
426115cf 1625 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1626
426115cf
DV		 1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1632 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1633
d288f65f 1634 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1635 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1636
1637 /* We do this three times for luck */
426115cf 1638 I915_WRITE(reg, dpll);
87442f73
DV		 1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647}
1648
d288f65f 1649static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1650 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1651{
1652 struct drm_device *dev = crtc->base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 int pipe = crtc->pipe;
1655 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1656 u32 tmp;
1657
1658 assert_pipe_disabled(dev_priv, crtc->pipe);
1659
1660 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1661
1662 mutex_lock(&dev_priv->dpio_lock);
1663
1664 /* Enable back the 10bit clock to display controller */
1665 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1666 tmp |= DPIO_DCLKP_EN;
1667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1668
1669 /*
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671 */
1672 udelay(1);
1673
1674 /* Enable PLL */
d288f65f 1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1676
1677 /* Check PLL is locked */
a11b0703 1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
a11b0703 1681 /* not sure when this should be written */
d288f65f 1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1683 POSTING_READ(DPLL_MD(pipe));
1684
9d556c99
CML		 1685 mutex_unlock(&dev_priv->dpio_lock);
1686}
1687
1c4e0274
VS		 1688static int intel_num_dvo_pipes(struct drm_device *dev)
1689{
1690 struct intel_crtc *crtc;
1691 int count = 0;
1692
1693 for_each_intel_crtc(dev, crtc)
1694 count += crtc->active &&
409ee761 1695 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1696
1697 return count;
1698}
1699
66e3d5c0 1700static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1701{
66e3d5c0
DV		 1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 int reg = DPLL(crtc->pipe);
6e3c9717 1705 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1706
66e3d5c0 1707 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1708
63d7bbe9 1709 /* No really, not for ILK+ */
3d13ef2e 1710 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1711
1712 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1713 if (IS_MOBILE(dev) && !IS_I830(dev))
1714 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1715
1c4e0274
VS		 1716 /* Enable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1718 /*
1719 * It appears to be important that we don't enable this
1720 * for the current pipe before otherwise configuring the
1721 * PLL. No idea how this should be handled if multiple
1722 * DVO outputs are enabled simultaneosly.
1723 */
1724 dpll |= DPLL_DVO_2X_MODE;
1725 I915_WRITE(DPLL(!crtc->pipe),
1726 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1727 }
66e3d5c0
DV		 1728
1729 /* Wait for the clocks to stabilize. */
1730 POSTING_READ(reg);
1731 udelay(150);
1732
1733 if (INTEL_INFO(dev)->gen >= 4) {
1734 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1735 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1736 } else {
1737 /* The pixel multiplier can only be updated once the
1738 * DPLL is enabled and the clocks are stable.
1739 *
1740 * So write it again.
1741 */
1742 I915_WRITE(reg, dpll);
1743 }
63d7bbe9
JB		 1744
1745 /* We do this three times for luck */
66e3d5c0 1746 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755}
1756
1757/**
50b44a44 1758 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe PLL to disable
1761 *
1762 * Disable the PLL for @pipe, making sure the pipe is off first.
1763 *
1764 * Note! This is for pre-ILK only.
1765 */
1c4e0274 1766static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1767{
1c4e0274
VS		 1768 struct drm_device *dev = crtc->base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 enum pipe pipe = crtc->pipe;
1771
1772 /* Disable DVO 2x clock on both PLLs if necessary */
1773 if (IS_I830(dev) &&
409ee761 1774 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1775 intel_num_dvo_pipes(dev) == 1) {
1776 I915_WRITE(DPLL(PIPE_B),
1777 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1778 I915_WRITE(DPLL(PIPE_A),
1779 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1780 }
1781
b6b5d049
VS		 1782 /* Don't disable pipe or pipe PLLs if needed */
1783 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1784 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1785 return;
1786
1787 /* Make sure the pipe isn't still relying on us */
1788 assert_pipe_disabled(dev_priv, pipe);
1789
50b44a44
DV		 1790 I915_WRITE(DPLL(pipe), 0);
1791 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1792}
1793
f6071166
JB		 1794static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1795{
1796 u32 val = 0;
1797
1798 /* Make sure the pipe isn't still relying on us */
1799 assert_pipe_disabled(dev_priv, pipe);
1800
e5cbfbfb
ID		 1801 /*
1802 * Leave integrated clock source and reference clock enabled for pipe B.
1803 * The latter is needed for VGA hotplug / manual detection.
1804 */
f6071166 1805 if (pipe == PIPE_B)
e5cbfbfb 1806 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1807 I915_WRITE(DPLL(pipe), val);
1808 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1809
1810}
1811
1812static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1813{
d752048d 1814 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1815 u32 val;
1816
a11b0703
VS		 1817 /* Make sure the pipe isn't still relying on us */
1818 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1819
a11b0703 1820 /* Set PLL en = 0 */
d17ec4ce 1821 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1822 if (pipe != PIPE_A)
1823 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824 I915_WRITE(DPLL(pipe), val);
1825 POSTING_READ(DPLL(pipe));
d752048d
VS		 1826
1827 mutex_lock(&dev_priv->dpio_lock);
1828
1829 /* Disable 10bit clock to display controller */
1830 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831 val &= ~DPIO_DCLKP_EN;
1832 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
61407f6d
VS		 1834 /* disable left/right clock distribution */
1835 if (pipe != PIPE_B) {
1836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1839 } else {
1840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1843 }
1844
d752048d 1845 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1846}
1847
e4607fcf
CML		 1848void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849 struct intel_digital_port *dport)
89b667f8
JB		 1850{
1851 u32 port_mask;
00fc31b7 1852 int dpll_reg;
89b667f8 1853
e4607fcf
CML		 1854 switch (dport->port) {
1855 case PORT_B:
89b667f8 1856 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1857 dpll_reg = DPLL(0);
e4607fcf
CML		 1858 break;
1859 case PORT_C:
89b667f8 1860 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1861 dpll_reg = DPLL(0);
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1866 break;
1867 default:
1868 BUG();
1869 }
89b667f8 1870
00fc31b7 1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1872 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1873 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1874}
1875
b14b1055
DV		 1876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
be19f0ff
CW		 1882 if (WARN_ON(pll == NULL))
1883 return;
1884
3e369b76 1885 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
92f2584a 1895/**
85b3894f 1896 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
85b3894f 1903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1904{
3d13ef2e
DL		 1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1908
87a875bb 1909 if (WARN_ON(pll == NULL))
48da64a8
CW		 1910 return;
1911
3e369b76 1912 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1913 return;
ee7b9f93 1914
74dd6928 1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1916 pll->name, pll->active, pll->on,
e2b78267 1917 crtc->base.base.id);
92f2584a 1918
cdbd2316
DV		 1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1922 return;
1923 }
f4a091c7 1924 WARN_ON(pll->on);
ee7b9f93 1925
bd2bb1b9
PZ		 1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
46edb027 1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1929 pll->enable(dev_priv, pll);
ee7b9f93 1930 pll->on = true;
92f2584a
JB		 1931}
1932
f6daaec2 1933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1934{
3d13ef2e
DL		 1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1938
92f2584a 1939 /* PCH only available on ILK+ */
3d13ef2e 1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1941 if (WARN_ON(pll == NULL))
ee7b9f93 1942 return;
92f2584a 1943
3e369b76 1944 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1945 return;
7a419866 1946
46edb027
DV		 1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
e2b78267 1949 crtc->base.base.id);
7a419866 1950
48da64a8 1951 if (WARN_ON(pll->active == 0)) {
e9d6944e 1952 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1953 return;
1954 }
1955
e9d6944e 1956 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1957 WARN_ON(!pll->on);
cdbd2316 1958 if (--pll->active)
7a419866 1959 return;
ee7b9f93 1960
46edb027 1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1962 pll->disable(dev_priv, pll);
ee7b9f93 1963 pll->on = false;
bd2bb1b9
PZ		 1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1966}
1967
b8a4f404
PZ		 1968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
040484af 1970{
23670b32 1971 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1974 uint32_t reg, val, pipeconf_val;
040484af
JB		 1975
1976 /* PCH only available on ILK+ */
55522f37 1977 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1978
1979 /* Make sure PCH DPLL is enabled */
e72f9fbf 1980 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1981 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
23670b32
DV		 1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
59c859d6 1994 }
23670b32 1995
ab9412ba 1996 reg = PCH_TRANSCONF(pipe);
040484af 1997 val = I915_READ(reg);
5f7f726d 1998 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
dfd07d72
DV		 2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2007 }
5f7f726d
PZ		 2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2011 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
040484af
JB		 2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2022}
2023
8fb033d7 2024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2025 enum transcoder cpu_transcoder)
040484af 2026{
8fb033d7 2027 u32 val, pipeconf_val;
8fb033d7
PZ		 2028
2029 /* PCH only available on ILK+ */
55522f37 2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2031
8fb033d7 2032 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2035
223a6fdf
PZ		 2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
25f3ef11 2041 val = TRANS_ENABLE;
937bb610 2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2043
9a76b1c6
PZ		 2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
a35f2679 2046 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
ab9412ba
DV		 2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2052 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2053}
2054
b8a4f404
PZ		 2055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
040484af 2057{
23670b32
DV		 2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
040484af
JB		 2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
291906f1
JB		 2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
ab9412ba 2068 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
040484af
JB		 2083}
2084
ab4d966c 2085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2086{
8fb033d7
PZ		 2087 u32 val;
2088
ab9412ba 2089 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2090 val &= ~TRANS_ENABLE;
ab9412ba 2091 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2092 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2094 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2099 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2100}
2101
b24e7179 2102/**
309cfea8 2103 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2104 * @crtc: crtc responsible for the pipe
b24e7179 2105 *
0372264a 2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2108 */
e1fdc473 2109static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2110{
0372264a
PZ		 2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
1a240d4d 2116 enum pipe pch_transcoder;
b24e7179
JB		 2117 int reg;
2118 u32 val;
2119
58c6eaa2 2120 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2121 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2122 assert_sprites_disabled(dev_priv, pipe);
2123
681e5811 2124 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
b24e7179
JB		 2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
50360403 2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
040484af 2139 else {
6e3c9717 2140 if (crtc->config->has_pch_encoder) {
040484af 2141 /* if driving the PCH, we need FDI enabled */
cc391bbb 2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
040484af
JB		 2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
b24e7179 2148
702e7a56 2149 reg = PIPECONF(cpu_transcoder);
b24e7179 2150 val = I915_READ(reg);
7ad25d48 2151 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2154 return;
7ad25d48 2155 }
00d70b15
CW		 2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2158 POSTING_READ(reg);
b24e7179
JB		 2159}
2160
2161/**
309cfea8 2162 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2163 * @crtc: crtc whose pipes is to be disabled
b24e7179 2164 *
575f7ab7
VS		 2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
b24e7179
JB		 2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
575f7ab7 2171static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2172{
575f7ab7 2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2175 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2184 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2185 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2186
702e7a56 2187 reg = PIPECONF(cpu_transcoder);
b24e7179 2188 val = I915_READ(reg);
00d70b15
CW		 2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
67adc644
VS		 2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
6e3c9717 2196 if (crtc->config->double_wide)
67adc644
VS		 2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2207}
2208
d74362c9
KP		 2209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
1dba99f4
VS		 2213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
d74362c9 2215{
3d13ef2e
DL		 2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
d74362c9
KP		 2221}
2222
b24e7179 2223/**
262ca2b0 2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
b24e7179 2227 *
fdd508a6 2228 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2229 */
fdd508a6
VS		 2230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
b24e7179 2232{
fdd508a6
VS		 2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2239
98ec7739
VS		 2240 if (intel_crtc->primary_enabled)
2241 return;
0037f71c 2242
4c445e0e 2243 intel_crtc->primary_enabled = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
33c3b0d1
VS		 2247
2248 /*
2249 * BDW signals flip done immediately if the plane
2250 * is disabled, even if the plane enable is already
2251 * armed to occur at the next vblank :(
2252 */
2253 if (IS_BROADWELL(dev))
2254 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2255}
2256
b24e7179 2257/**
262ca2b0 2258 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2259 * @plane: plane to be disabled
2260 * @crtc: crtc for the plane
b24e7179 2261 *
fdd508a6 2262 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2263 */
fdd508a6
VS		 2264static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2265 struct drm_crtc *crtc)
b24e7179 2266{
fdd508a6
VS		 2267 struct drm_device *dev = plane->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270
32b7eeec
MR		 2271 if (WARN_ON(!intel_crtc->active))
2272 return;
b24e7179 2273
98ec7739
VS		 2274 if (!intel_crtc->primary_enabled)
2275 return;
0037f71c 2276
4c445e0e 2277 intel_crtc->primary_enabled = false;
939c2fe8 2278
fdd508a6
VS		 2279 dev_priv->display.update_primary_plane(crtc, plane->fb,
2280 crtc->x, crtc->y);
b24e7179
JB		 2281}
2282
693db184
CW		 2283static bool need_vtd_wa(struct drm_device *dev)
2284{
2285#ifdef CONFIG_INTEL_IOMMU
2286 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2287 return true;
2288#endif
2289 return false;
2290}
2291
50470bb0 2292unsigned int
6761dd31
TU		 2293intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2294 uint64_t fb_format_modifier)
a57ce0b2 2295{
6761dd31
TU		 2296 unsigned int tile_height;
2297 uint32_t pixel_bytes;
a57ce0b2 2298
b5d0e9bf
DL		 2299 switch (fb_format_modifier) {
2300 case DRM_FORMAT_MOD_NONE:
2301 tile_height = 1;
2302 break;
2303 case I915_FORMAT_MOD_X_TILED:
2304 tile_height = IS_GEN2(dev) ? 16 : 8;
2305 break;
2306 case I915_FORMAT_MOD_Y_TILED:
2307 tile_height = 32;
2308 break;
2309 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2310 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2311 switch (pixel_bytes) {
b5d0e9bf 2312 default:
6761dd31 2313 case 1:
b5d0e9bf
DL		 2314 tile_height = 64;
2315 break;
6761dd31
TU		 2316 case 2:
2317 case 4:
b5d0e9bf
DL		 2318 tile_height = 32;
2319 break;
6761dd31 2320 case 8:
b5d0e9bf
DL		 2321 tile_height = 16;
2322 break;
6761dd31 2323 case 16:
b5d0e9bf
DL		 2324 WARN_ONCE(1,
2325 "128-bit pixels are not supported for display!");
2326 tile_height = 16;
2327 break;
2328 }
2329 break;
2330 default:
2331 MISSING_CASE(fb_format_modifier);
2332 tile_height = 1;
2333 break;
2334 }
091df6cb 2335
6761dd31
TU		 2336 return tile_height;
2337}
2338
2339unsigned int
2340intel_fb_align_height(struct drm_device *dev, unsigned int height,
2341 uint32_t pixel_format, uint64_t fb_format_modifier)
2342{
2343 return ALIGN(height, intel_tile_height(dev, pixel_format,
2344 fb_format_modifier));
a57ce0b2
JB		 2345}
2346
f64b98cd
TU		 2347static int
2348intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2349 const struct drm_plane_state *plane_state)
2350{
50470bb0 2351 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2352
f64b98cd
TU		 2353 *view = i915_ggtt_view_normal;
2354
50470bb0
TU		 2355 if (!plane_state)
2356 return 0;
2357
121920fa 2358 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2359 return 0;
2360
9abc4648 2361 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2362
2363 info->height = fb->height;
2364 info->pixel_format = fb->pixel_format;
2365 info->pitch = fb->pitches[0];
2366 info->fb_modifier = fb->modifier[0];
2367
f64b98cd
TU		 2368 return 0;
2369}
2370
127bd2ac 2371int
850c4cdc
TU		 2372intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2373 struct drm_framebuffer *fb,
82bc3b2d 2374 const struct drm_plane_state *plane_state,
a4872ba6 2375 struct intel_engine_cs *pipelined)
6b95a207 2376{
850c4cdc 2377 struct drm_device *dev = fb->dev;
ce453d81 2378 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2379 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2380 struct i915_ggtt_view view;
6b95a207
KH		 2381 u32 alignment;
2382 int ret;
2383
ebcdd39e
MR		 2384 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2385
7b911adc
TU		 2386 switch (fb->modifier[0]) {
2387 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2388 if (INTEL_INFO(dev)->gen >= 9)
2389 alignment = 256 * 1024;
2390 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2391 alignment = 128 * 1024;
a6c45cf0 2392 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2393 alignment = 4 * 1024;
2394 else
2395 alignment = 64 * 1024;
6b95a207 2396 break;
7b911adc 2397 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2398 if (INTEL_INFO(dev)->gen >= 9)
2399 alignment = 256 * 1024;
2400 else {
2401 /* pin() will align the object as required by fence */
2402 alignment = 0;
2403 }
6b95a207 2404 break;
7b911adc 2405 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2406 case I915_FORMAT_MOD_Yf_TILED:
2407 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2408 "Y tiling bo slipped through, driver bug!\n"))
2409 return -EINVAL;
2410 alignment = 1 * 1024 * 1024;
2411 break;
6b95a207 2412 default:
7b911adc
TU		 2413 MISSING_CASE(fb->modifier[0]);
2414 return -EINVAL;
6b95a207
KH		 2415 }
2416
f64b98cd
TU		 2417 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2418 if (ret)
2419 return ret;
2420
693db184
CW		 2421 /* Note that the w/a also requires 64 PTE of padding following the
2422 * bo. We currently fill all unused PTE with the shadow page and so
2423 * we should always have valid PTE following the scanout preventing
2424 * the VT-d warning.
2425 */
2426 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2427 alignment = 256 * 1024;
2428
d6dd6843
PZ		 2429 /*
2430 * Global gtt pte registers are special registers which actually forward
2431 * writes to a chunk of system memory. Which means that there is no risk
2432 * that the register values disappear as soon as we call
2433 * intel_runtime_pm_put(), so it is correct to wrap only the
2434 * pin/unpin/fence and not more.
2435 */
2436 intel_runtime_pm_get(dev_priv);
2437
ce453d81 2438 dev_priv->mm.interruptible = false;
e6617330 2439 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2440 &view);
48b956c5 2441 if (ret)
ce453d81 2442 goto err_interruptible;
6b95a207
KH		 2443
2444 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2445 * fence, whereas 965+ only requires a fence if using
2446 * framebuffer compression. For simplicity, we always install
2447 * a fence as the cost is not that onerous.
2448 */
06d98131 2449 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2450 if (ret)
2451 goto err_unpin;
1690e1eb 2452
9a5a53b3 2453 i915_gem_object_pin_fence(obj);
6b95a207 2454
ce453d81 2455 dev_priv->mm.interruptible = true;
d6dd6843 2456 intel_runtime_pm_put(dev_priv);
6b95a207 2457 return 0;
48b956c5
CW		 2458
2459err_unpin:
f64b98cd 2460 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2461err_interruptible:
2462 dev_priv->mm.interruptible = true;
d6dd6843 2463 intel_runtime_pm_put(dev_priv);
48b956c5 2464 return ret;
6b95a207
KH		 2465}
2466
82bc3b2d
TU		 2467static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2468 const struct drm_plane_state *plane_state)
1690e1eb 2469{
82bc3b2d 2470 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2471 struct i915_ggtt_view view;
2472 int ret;
82bc3b2d 2473
ebcdd39e
MR		 2474 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2475
f64b98cd
TU		 2476 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2477 WARN_ONCE(ret, "Couldn't get view from plane state!");
2478
1690e1eb 2479 i915_gem_object_unpin_fence(obj);
f64b98cd 2480 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2481}
2482
c2c75131
DV		 2483/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2484 * is assumed to be a power-of-two. */
bc752862
CW		 2485unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2486 unsigned int tiling_mode,
2487 unsigned int cpp,
2488 unsigned int pitch)
c2c75131 2489{
bc752862
CW		 2490 if (tiling_mode != I915_TILING_NONE) {
2491 unsigned int tile_rows, tiles;
c2c75131 2492
bc752862
CW		 2493 tile_rows = *y / 8;
2494 *y %= 8;
c2c75131 2495
bc752862
CW		 2496 tiles = *x / (512/cpp);
2497 *x %= 512/cpp;
2498
2499 return tile_rows * pitch * 8 + tiles * 4096;
2500 } else {
2501 unsigned int offset;
2502
2503 offset = *y * pitch + *x * cpp;
2504 *y = 0;
2505 *x = (offset & 4095) / cpp;
2506 return offset & -4096;
2507 }
c2c75131
DV		 2508}
2509
b35d63fa 2510static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2511{
2512 switch (format) {
2513 case DISPPLANE_8BPP:
2514 return DRM_FORMAT_C8;
2515 case DISPPLANE_BGRX555:
2516 return DRM_FORMAT_XRGB1555;
2517 case DISPPLANE_BGRX565:
2518 return DRM_FORMAT_RGB565;
2519 default:
2520 case DISPPLANE_BGRX888:
2521 return DRM_FORMAT_XRGB8888;
2522 case DISPPLANE_RGBX888:
2523 return DRM_FORMAT_XBGR8888;
2524 case DISPPLANE_BGRX101010:
2525 return DRM_FORMAT_XRGB2101010;
2526 case DISPPLANE_RGBX101010:
2527 return DRM_FORMAT_XBGR2101010;
2528 }
2529}
2530
bc8d7dff
DL		 2531static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2532{
2533 switch (format) {
2534 case PLANE_CTL_FORMAT_RGB_565:
2535 return DRM_FORMAT_RGB565;
2536 default:
2537 case PLANE_CTL_FORMAT_XRGB_8888:
2538 if (rgb_order) {
2539 if (alpha)
2540 return DRM_FORMAT_ABGR8888;
2541 else
2542 return DRM_FORMAT_XBGR8888;
2543 } else {
2544 if (alpha)
2545 return DRM_FORMAT_ARGB8888;
2546 else
2547 return DRM_FORMAT_XRGB8888;
2548 }
2549 case PLANE_CTL_FORMAT_XRGB_2101010:
2550 if (rgb_order)
2551 return DRM_FORMAT_XBGR2101010;
2552 else
2553 return DRM_FORMAT_XRGB2101010;
2554 }
2555}
2556
5724dbd1 2557static bool
f6936e29
DV		 2558intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2559 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2560{
2561 struct drm_device *dev = crtc->base.dev;
2562 struct drm_i915_gem_object *obj = NULL;
2563 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2564 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2565 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2566 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2567 PAGE_SIZE);
2568
2569 size_aligned -= base_aligned;
46f297fb 2570
ff2652ea
CW		 2571 if (plane_config->size == 0)
2572 return false;
2573
f37b5c2b
DV		 2574 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2575 base_aligned,
2576 base_aligned,
2577 size_aligned);
46f297fb 2578 if (!obj)
484b41dd 2579 return false;
46f297fb 2580
49af449b
DL		 2581 obj->tiling_mode = plane_config->tiling;
2582 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2583 obj->stride = fb->pitches[0];
46f297fb 2584
6bf129df
DL		 2585 mode_cmd.pixel_format = fb->pixel_format;
2586 mode_cmd.width = fb->width;
2587 mode_cmd.height = fb->height;
2588 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2589 mode_cmd.modifier[0] = fb->modifier[0];
2590 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2591
2592 mutex_lock(&dev->struct_mutex);
6bf129df 2593 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2594 &mode_cmd, obj)) {
46f297fb
JB		 2595 DRM_DEBUG_KMS("intel fb init failed\n");
2596 goto out_unref_obj;
2597 }
46f297fb 2598 mutex_unlock(&dev->struct_mutex);
484b41dd 2599
f6936e29 2600 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2601 return true;
46f297fb
JB		 2602
2603out_unref_obj:
2604 drm_gem_object_unreference(&obj->base);
2605 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2606 return false;
2607}
2608
afd65eb4
MR		 2609/* Update plane->state->fb to match plane->fb after driver-internal updates */
2610static void
2611update_state_fb(struct drm_plane *plane)
2612{
2613 if (plane->fb == plane->state->fb)
2614 return;
2615
2616 if (plane->state->fb)
2617 drm_framebuffer_unreference(plane->state->fb);
2618 plane->state->fb = plane->fb;
2619 if (plane->state->fb)
2620 drm_framebuffer_reference(plane->state->fb);
2621}
2622
5724dbd1 2623static void
f6936e29
DV		 2624intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2625 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2626{
2627 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2628 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2629 struct drm_crtc *c;
2630 struct intel_crtc *i;
2ff8fde1 2631 struct drm_i915_gem_object *obj;
88595ac9
DV		 2632 struct drm_plane *primary = intel_crtc->base.primary;
2633 struct drm_framebuffer *fb;
484b41dd 2634
2d14030b 2635 if (!plane_config->fb)
484b41dd
JB		 2636 return;
2637
f6936e29 2638 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2639 fb = &plane_config->fb->base;
2640 goto valid_fb;
f55548b5 2641 }
484b41dd 2642
2d14030b 2643 kfree(plane_config->fb);
484b41dd
JB		 2644
2645 /*
2646 * Failed to alloc the obj, check to see if we should share
2647 * an fb with another CRTC instead
2648 */
70e1e0ec 2649 for_each_crtc(dev, c) {
484b41dd
JB		 2650 i = to_intel_crtc(c);
2651
2652 if (c == &intel_crtc->base)
2653 continue;
2654
2ff8fde1
MR		 2655 if (!i->active)
2656 continue;
2657
88595ac9
DV		 2658 fb = c->primary->fb;
2659 if (!fb)
484b41dd
JB		 2660 continue;
2661
88595ac9 2662 obj = intel_fb_obj(fb);
2ff8fde1 2663 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2664 drm_framebuffer_reference(fb);
2665 goto valid_fb;
484b41dd
JB		 2666 }
2667 }
88595ac9
DV		 2668
2669 return;
2670
2671valid_fb:
2672 obj = intel_fb_obj(fb);
2673 if (obj->tiling_mode != I915_TILING_NONE)
2674 dev_priv->preserve_bios_swizzle = true;
2675
2676 primary->fb = fb;
2677 primary->state->crtc = &intel_crtc->base;
2678 primary->crtc = &intel_crtc->base;
2679 update_state_fb(primary);
2680 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2681}
2682
29b9bde6
DV		 2683static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2684 struct drm_framebuffer *fb,
2685 int x, int y)
81255565
JB		 2686{
2687 struct drm_device *dev = crtc->dev;
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2690 struct drm_i915_gem_object *obj;
81255565 2691 int plane = intel_crtc->plane;
e506a0c6 2692 unsigned long linear_offset;
81255565 2693 u32 dspcntr;
f45651ba 2694 u32 reg = DSPCNTR(plane);
48404c1e 2695 int pixel_size;
f45651ba 2696
fdd508a6
VS		 2697 if (!intel_crtc->primary_enabled) {
2698 I915_WRITE(reg, 0);
2699 if (INTEL_INFO(dev)->gen >= 4)
2700 I915_WRITE(DSPSURF(plane), 0);
2701 else
2702 I915_WRITE(DSPADDR(plane), 0);
2703 POSTING_READ(reg);
2704 return;
2705 }
2706
c9ba6fad
VS		 2707 obj = intel_fb_obj(fb);
2708 if (WARN_ON(obj == NULL))
2709 return;
2710
2711 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2712
f45651ba
VS		 2713 dspcntr = DISPPLANE_GAMMA_ENABLE;
2714
fdd508a6 2715 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2716
2717 if (INTEL_INFO(dev)->gen < 4) {
2718 if (intel_crtc->pipe == PIPE_B)
2719 dspcntr |= DISPPLANE_SEL_PIPE_B;
2720
2721 /* pipesrc and dspsize control the size that is scaled from,
2722 * which should always be the user's requested size.
2723 */
2724 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2725 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2726 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2727 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2728 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2729 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2730 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2731 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2732 I915_WRITE(PRIMPOS(plane), 0);
2733 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2734 }
81255565 2735
57779d06
VS		 2736 switch (fb->pixel_format) {
2737 case DRM_FORMAT_C8:
81255565
JB		 2738 dspcntr |= DISPPLANE_8BPP;
2739 break;
57779d06
VS		 2740 case DRM_FORMAT_XRGB1555:
2741 case DRM_FORMAT_ARGB1555:
2742 dspcntr |= DISPPLANE_BGRX555;
81255565 2743 break;
57779d06
VS		 2744 case DRM_FORMAT_RGB565:
2745 dspcntr |= DISPPLANE_BGRX565;
2746 break;
2747 case DRM_FORMAT_XRGB8888:
2748 case DRM_FORMAT_ARGB8888:
2749 dspcntr |= DISPPLANE_BGRX888;
2750 break;
2751 case DRM_FORMAT_XBGR8888:
2752 case DRM_FORMAT_ABGR8888:
2753 dspcntr |= DISPPLANE_RGBX888;
2754 break;
2755 case DRM_FORMAT_XRGB2101010:
2756 case DRM_FORMAT_ARGB2101010:
2757 dspcntr |= DISPPLANE_BGRX101010;
2758 break;
2759 case DRM_FORMAT_XBGR2101010:
2760 case DRM_FORMAT_ABGR2101010:
2761 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2762 break;
2763 default:
baba133a 2764 BUG();
81255565 2765 }
57779d06 2766
f45651ba
VS		 2767 if (INTEL_INFO(dev)->gen >= 4 &&
2768 obj->tiling_mode != I915_TILING_NONE)
2769 dspcntr |= DISPPLANE_TILED;
81255565 2770
de1aa629
VS		 2771 if (IS_G4X(dev))
2772 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2773
b9897127 2774 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2775
c2c75131
DV		 2776 if (INTEL_INFO(dev)->gen >= 4) {
2777 intel_crtc->dspaddr_offset =
bc752862 2778 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2779 pixel_size,
bc752862 2780 fb->pitches[0]);
c2c75131
DV		 2781 linear_offset -= intel_crtc->dspaddr_offset;
2782 } else {
e506a0c6 2783 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2784 }
e506a0c6 2785
8e7d688b 2786 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2787 dspcntr |= DISPPLANE_ROTATE_180;
2788
6e3c9717
ACO		 2789 x += (intel_crtc->config->pipe_src_w - 1);
2790 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2791
2792 /* Finding the last pixel of the last line of the display
2793 data and adding to linear_offset*/
2794 linear_offset +=
6e3c9717
ACO		 2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2797 }
2798
2799 I915_WRITE(reg, dspcntr);
2800
01f2c773 2801 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2802 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2803 I915_WRITE(DSPSURF(plane),
2804 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2805 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2806 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2807 } else
f343c5f6 2808 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2809 POSTING_READ(reg);
17638cd6
JB		 2810}
2811
29b9bde6
DV		 2812static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2813 struct drm_framebuffer *fb,
2814 int x, int y)
17638cd6
JB		 2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2819 struct drm_i915_gem_object *obj;
17638cd6 2820 int plane = intel_crtc->plane;
e506a0c6 2821 unsigned long linear_offset;
17638cd6 2822 u32 dspcntr;
f45651ba 2823 u32 reg = DSPCNTR(plane);
48404c1e 2824 int pixel_size;
f45651ba 2825
fdd508a6
VS		 2826 if (!intel_crtc->primary_enabled) {
2827 I915_WRITE(reg, 0);
2828 I915_WRITE(DSPSURF(plane), 0);
2829 POSTING_READ(reg);
2830 return;
2831 }
2832
c9ba6fad
VS		 2833 obj = intel_fb_obj(fb);
2834 if (WARN_ON(obj == NULL))
2835 return;
2836
2837 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2838
f45651ba
VS		 2839 dspcntr = DISPPLANE_GAMMA_ENABLE;
2840
fdd508a6 2841 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2842
2843 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2844 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2845
57779d06
VS		 2846 switch (fb->pixel_format) {
2847 case DRM_FORMAT_C8:
17638cd6
JB		 2848 dspcntr |= DISPPLANE_8BPP;
2849 break;
57779d06
VS		 2850 case DRM_FORMAT_RGB565:
2851 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2852 break;
57779d06
VS		 2853 case DRM_FORMAT_XRGB8888:
2854 case DRM_FORMAT_ARGB8888:
2855 dspcntr |= DISPPLANE_BGRX888;
2856 break;
2857 case DRM_FORMAT_XBGR8888:
2858 case DRM_FORMAT_ABGR8888:
2859 dspcntr |= DISPPLANE_RGBX888;
2860 break;
2861 case DRM_FORMAT_XRGB2101010:
2862 case DRM_FORMAT_ARGB2101010:
2863 dspcntr |= DISPPLANE_BGRX101010;
2864 break;
2865 case DRM_FORMAT_XBGR2101010:
2866 case DRM_FORMAT_ABGR2101010:
2867 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2868 break;
2869 default:
baba133a 2870 BUG();
17638cd6
JB		 2871 }
2872
2873 if (obj->tiling_mode != I915_TILING_NONE)
2874 dspcntr |= DISPPLANE_TILED;
17638cd6 2875
f45651ba 2876 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2877 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2878
b9897127 2879 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2880 intel_crtc->dspaddr_offset =
bc752862 2881 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2882 pixel_size,
bc752862 2883 fb->pitches[0]);
c2c75131 2884 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2885 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2886 dspcntr |= DISPPLANE_ROTATE_180;
2887
2888 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2889 x += (intel_crtc->config->pipe_src_w - 1);
2890 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2891
2892 /* Finding the last pixel of the last line of the display
2893 data and adding to linear_offset*/
2894 linear_offset +=
6e3c9717
ACO		 2895 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2896 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2897 }
2898 }
2899
2900 I915_WRITE(reg, dspcntr);
17638cd6 2901
01f2c773 2902 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2903 I915_WRITE(DSPSURF(plane),
2904 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2905 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2906 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2907 } else {
2908 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2909 I915_WRITE(DSPLINOFF(plane), linear_offset);
2910 }
17638cd6 2911 POSTING_READ(reg);
17638cd6
JB		 2912}
2913
b321803d
DL		 2914u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2915 uint32_t pixel_format)
2916{
2917 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2918
2919 /*
2920 * The stride is either expressed as a multiple of 64 bytes
2921 * chunks for linear buffers or in number of tiles for tiled
2922 * buffers.
2923 */
2924 switch (fb_modifier) {
2925 case DRM_FORMAT_MOD_NONE:
2926 return 64;
2927 case I915_FORMAT_MOD_X_TILED:
2928 if (INTEL_INFO(dev)->gen == 2)
2929 return 128;
2930 return 512;
2931 case I915_FORMAT_MOD_Y_TILED:
2932 /* No need to check for old gens and Y tiling since this is
2933 * about the display engine and those will be blocked before
2934 * we get here.
2935 */
2936 return 128;
2937 case I915_FORMAT_MOD_Yf_TILED:
2938 if (bits_per_pixel == 8)
2939 return 64;
2940 else
2941 return 128;
2942 default:
2943 MISSING_CASE(fb_modifier);
2944 return 64;
2945 }
2946}
2947
121920fa
TU		 2948unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2949 struct drm_i915_gem_object *obj)
2950{
9abc4648 2951 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2952
2953 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2954 view = &i915_ggtt_view_rotated;
121920fa
TU		 2955
2956 return i915_gem_obj_ggtt_offset_view(obj, view);
2957}
2958
a1b2278e
CK		 2959/*
2960 * This function detaches (aka. unbinds) unused scalers in hardware
2961 */
2962void skl_detach_scalers(struct intel_crtc *intel_crtc)
2963{
2964 struct drm_device *dev;
2965 struct drm_i915_private *dev_priv;
2966 struct intel_crtc_scaler_state *scaler_state;
2967 int i;
2968
2969 if (!intel_crtc || !intel_crtc->config)
2970 return;
2971
2972 dev = intel_crtc->base.dev;
2973 dev_priv = dev->dev_private;
2974 scaler_state = &intel_crtc->config->scaler_state;
2975
2976 /* loop through and disable scalers that aren't in use */
2977 for (i = 0; i < intel_crtc->num_scalers; i++) {
2978 if (!scaler_state->scalers[i].in_use) {
2979 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2980 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2981 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2982 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2983 intel_crtc->base.base.id, intel_crtc->pipe, i);
2984 }
2985 }
2986}
2987
70d21f0e
DL		 2988static void skylake_update_primary_plane(struct drm_crtc *crtc,
2989 struct drm_framebuffer *fb,
2990 int x, int y)
2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2995 struct drm_i915_gem_object *obj;
2996 int pipe = intel_crtc->pipe;
3b7a5119
SJ		 2997 u32 plane_ctl, stride_div, stride;
2998 u32 tile_height, plane_offset, plane_size;
2999 unsigned int rotation;
3000 int x_offset, y_offset;
121920fa 3001 unsigned long surf_addr;
3b7a5119 3002 struct drm_plane *plane;
70d21f0e
DL		 3003
3004 if (!intel_crtc->primary_enabled) {
3005 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3006 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3007 POSTING_READ(PLANE_CTL(pipe, 0));
3008 return;
3009 }
3010
3011 plane_ctl = PLANE_CTL_ENABLE |
3012 PLANE_CTL_PIPE_GAMMA_ENABLE |
3013 PLANE_CTL_PIPE_CSC_ENABLE;
3014
3015 switch (fb->pixel_format) {
3016 case DRM_FORMAT_RGB565:
3017 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
3018 break;
3019 case DRM_FORMAT_XRGB8888:
3020 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3021 break;
f75fb42a
JN		 3022 case DRM_FORMAT_ARGB8888:
3023 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3024 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3025 break;
70d21f0e
DL		 3026 case DRM_FORMAT_XBGR8888:
3027 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3028 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3029 break;
f75fb42a
JN		 3030 case DRM_FORMAT_ABGR8888:
3031 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3032 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3033 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3034 break;
70d21f0e
DL		 3035 case DRM_FORMAT_XRGB2101010:
3036 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3037 break;
3038 case DRM_FORMAT_XBGR2101010:
3039 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3040 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3041 break;
3042 default:
3043 BUG();
3044 }
3045
30af77c4
DV		 3046 switch (fb->modifier[0]) {
3047 case DRM_FORMAT_MOD_NONE:
70d21f0e 3048 break;
30af77c4 3049 case I915_FORMAT_MOD_X_TILED:
70d21f0e 3050 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 3051 break;
3052 case I915_FORMAT_MOD_Y_TILED:
3053 plane_ctl |= PLANE_CTL_TILED_Y;
3054 break;
3055 case I915_FORMAT_MOD_Yf_TILED:
3056 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3057 break;
3058 default:
b321803d 3059 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3060 }
3061
3062 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3b7a5119
SJ		 3063
3064 plane = crtc->primary;
3065 rotation = plane->state->rotation;
3066 switch (rotation) {
3067 case BIT(DRM_ROTATE_90):
3068 plane_ctl |= PLANE_CTL_ROTATE_90;
3069 break;
3070
3071 case BIT(DRM_ROTATE_180):
1447dde0 3072 plane_ctl |= PLANE_CTL_ROTATE_180;
3b7a5119
SJ		 3073 break;
3074
3075 case BIT(DRM_ROTATE_270):
3076 plane_ctl |= PLANE_CTL_ROTATE_270;
3077 break;
3078 }
70d21f0e 3079
b321803d
DL		 3080 obj = intel_fb_obj(fb);
3081 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3082 fb->pixel_format);
3b7a5119
SJ		 3083 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3084
3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
3087 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
3090 x_offset = stride * tile_height - y - (plane->state->src_h >> 16);
3091 y_offset = x;
3092 plane_size = ((plane->state->src_w >> 16) - 1) << 16 |
3093 ((plane->state->src_h >> 16) - 1);
3094 } else {
3095 stride = fb->pitches[0] / stride_div;
3096 x_offset = x;
3097 y_offset = y;
3098 plane_size = ((plane->state->src_h >> 16) - 1) << 16 |
3099 ((plane->state->src_w >> 16) - 1);
3100 }
3101 plane_offset = y_offset << 16 | x_offset;
b321803d 3102
70d21f0e 3103 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e 3104 I915_WRITE(PLANE_POS(pipe, 0), 0);
3b7a5119
SJ		 3105 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
121920fa 3108 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3109
3110 POSTING_READ(PLANE_SURF(pipe, 0));
3111}
3112
17638cd6
JB		 3113/* Assume fb object is pinned & idle & fenced and just update base pointers */
3114static int
3115intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3116 int x, int y, enum mode_set_atomic state)
3117{
3118 struct drm_device *dev = crtc->dev;
3119 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3120
6b8e6ed0
CW		 3121 if (dev_priv->display.disable_fbc)
3122 dev_priv->display.disable_fbc(dev);
81255565 3123
29b9bde6
DV		 3124 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3125
3126 return 0;
81255565
JB		 3127}
3128
7514747d 3129static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3130{
96a02917
VS		 3131 struct drm_crtc *crtc;
3132
70e1e0ec 3133 for_each_crtc(dev, crtc) {
96a02917
VS		 3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 enum plane plane = intel_crtc->plane;
3136
3137 intel_prepare_page_flip(dev, plane);
3138 intel_finish_page_flip_plane(dev, plane);
3139 }
7514747d
VS		 3140}
3141
3142static void intel_update_primary_planes(struct drm_device *dev)
3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct drm_crtc *crtc;
96a02917 3146
70e1e0ec 3147 for_each_crtc(dev, crtc) {
96a02917
VS		 3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149
51fd371b 3150 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3151 /*
3152 * FIXME: Once we have proper support for primary planes (and
3153 * disabling them without disabling the entire crtc) allow again
66e514c1 3154 * a NULL crtc->primary->fb.
947fdaad 3155 */
f4510a27 3156 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3157 dev_priv->display.update_primary_plane(crtc,
66e514c1 3158 crtc->primary->fb,
262ca2b0
MR		 3159 crtc->x,
3160 crtc->y);
51fd371b 3161 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3162 }
3163}
3164
7514747d
VS		 3165void intel_prepare_reset(struct drm_device *dev)
3166{
f98ce92f
VS		 3167 struct drm_i915_private *dev_priv = to_i915(dev);
3168 struct intel_crtc *crtc;
3169
7514747d
VS		 3170 /* no reset support for gen2 */
3171 if (IS_GEN2(dev))
3172 return;
3173
3174 /* reset doesn't touch the display */
3175 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3176 return;
3177
3178 drm_modeset_lock_all(dev);
f98ce92f
VS		 3179
3180 /*
3181 * Disabling the crtcs gracefully seems nicer. Also the
3182 * g33 docs say we should at least disable all the planes.
3183 */
3184 for_each_intel_crtc(dev, crtc) {
3185 if (crtc->active)
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 }
7514747d
VS		 3188}
3189
3190void intel_finish_reset(struct drm_device *dev)
3191{
3192 struct drm_i915_private *dev_priv = to_i915(dev);
3193
3194 /*
3195 * Flips in the rings will be nuked by the reset,
3196 * so complete all pending flips so that user space
3197 * will get its events and not get stuck.
3198 */
3199 intel_complete_page_flips(dev);
3200
3201 /* no reset support for gen2 */
3202 if (IS_GEN2(dev))
3203 return;
3204
3205 /* reset doesn't touch the display */
3206 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3207 /*
3208 * Flips in the rings have been nuked by the reset,
3209 * so update the base address of all primary
3210 * planes to the the last fb to make sure we're
3211 * showing the correct fb after a reset.
3212 */
3213 intel_update_primary_planes(dev);
3214 return;
3215 }
3216
3217 /*
3218 * The display has been reset as well,
3219 * so need a full re-initialization.
3220 */
3221 intel_runtime_pm_disable_interrupts(dev_priv);
3222 intel_runtime_pm_enable_interrupts(dev_priv);
3223
3224 intel_modeset_init_hw(dev);
3225
3226 spin_lock_irq(&dev_priv->irq_lock);
3227 if (dev_priv->display.hpd_irq_setup)
3228 dev_priv->display.hpd_irq_setup(dev);
3229 spin_unlock_irq(&dev_priv->irq_lock);
3230
3231 intel_modeset_setup_hw_state(dev, true);
3232
3233 intel_hpd_init(dev_priv);
3234
3235 drm_modeset_unlock_all(dev);
3236}
3237
14667a4b
CW		 3238static int
3239intel_finish_fb(struct drm_framebuffer *old_fb)
3240{
2ff8fde1 3241 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3242 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3243 bool was_interruptible = dev_priv->mm.interruptible;
3244 int ret;
3245
14667a4b
CW		 3246 /* Big Hammer, we also need to ensure that any pending
3247 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3248 * current scanout is retired before unpinning the old
3249 * framebuffer.
3250 *
3251 * This should only fail upon a hung GPU, in which case we
3252 * can safely continue.
3253 */
3254 dev_priv->mm.interruptible = false;
3255 ret = i915_gem_object_finish_gpu(obj);
3256 dev_priv->mm.interruptible = was_interruptible;
3257
3258 return ret;
3259}
3260
7d5e3799
CW		 3261static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3262{
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3266 bool pending;
3267
3268 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3269 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3270 return false;
3271
5e2d7afc 3272 spin_lock_irq(&dev->event_lock);
7d5e3799 3273 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3274 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3275
3276 return pending;
3277}
3278
e30e8f75
GP		 3279static void intel_update_pipe_size(struct intel_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->base.dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 const struct drm_display_mode *adjusted_mode;
3284
3285 if (!i915.fastboot)
3286 return;
3287
3288 /*
3289 * Update pipe size and adjust fitter if needed: the reason for this is
3290 * that in compute_mode_changes we check the native mode (not the pfit
3291 * mode) to see if we can flip rather than do a full mode set. In the
3292 * fastboot case, we'll flip, but if we don't update the pipesrc and
3293 * pfit state, we'll end up with a big fb scanned out into the wrong
3294 * sized surface.
3295 *
3296 * To fix this properly, we need to hoist the checks up into
3297 * compute_mode_changes (or above), check the actual pfit state and
3298 * whether the platform allows pfit disable with pipe active, and only
3299 * then update the pipesrc and pfit state, even on the flip path.
3300 */
3301
6e3c9717 3302 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3303
3304 I915_WRITE(PIPESRC(crtc->pipe),
3305 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3306 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3307 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3308 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3309 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3310 I915_WRITE(PF_CTL(crtc->pipe), 0);
3311 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3312 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3313 }
6e3c9717
ACO		 3314 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3315 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3316}
3317
5e84e1a4
ZW		 3318static void intel_fdi_normal_train(struct drm_crtc *crtc)
3319{
3320 struct drm_device *dev = crtc->dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 int pipe = intel_crtc->pipe;
3324 u32 reg, temp;
3325
3326 /* enable normal train */
3327 reg = FDI_TX_CTL(pipe);
3328 temp = I915_READ(reg);
61e499bf 3329 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3332 } else {
3333 temp &= ~FDI_LINK_TRAIN_NONE;
3334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3335 }
5e84e1a4
ZW		 3336 I915_WRITE(reg, temp);
3337
3338 reg = FDI_RX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 if (HAS_PCH_CPT(dev)) {
3341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3343 } else {
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_NONE;
3346 }
3347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3348
3349 /* wait one idle pattern time */
3350 POSTING_READ(reg);
3351 udelay(1000);
357555c0
JB		 3352
3353 /* IVB wants error correction enabled */
3354 if (IS_IVYBRIDGE(dev))
3355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3356 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3357}
3358
8db9d77b
ZW		 3359/* The FDI link training functions for ILK/Ibexpeak. */
3360static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3361{
3362 struct drm_device *dev = crtc->dev;
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 int pipe = intel_crtc->pipe;
5eddb70b 3366 u32 reg, temp, tries;
8db9d77b 3367
1c8562f6 3368 /* FDI needs bits from pipe first */
0fc932b8 3369 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3370
e1a44743
AJ		 3371 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3372 for train result */
5eddb70b
CW		 3373 reg = FDI_RX_IMR(pipe);
3374 temp = I915_READ(reg);
e1a44743
AJ		 3375 temp &= ~FDI_RX_SYMBOL_LOCK;
3376 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3377 I915_WRITE(reg, temp);
3378 I915_READ(reg);
e1a44743
AJ		 3379 udelay(150);
3380
8db9d77b 3381 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3382 reg = FDI_TX_CTL(pipe);
3383 temp = I915_READ(reg);
627eb5a3 3384 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3385 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3386 temp &= ~FDI_LINK_TRAIN_NONE;
3387 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3388 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3389
5eddb70b
CW		 3390 reg = FDI_RX_CTL(pipe);
3391 temp = I915_READ(reg);
8db9d77b
ZW		 3392 temp &= ~FDI_LINK_TRAIN_NONE;
3393 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3395
3396 POSTING_READ(reg);
8db9d77b
ZW		 3397 udelay(150);
3398
5b2adf89 3399 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3400 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3401 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3402 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3403
5eddb70b 3404 reg = FDI_RX_IIR(pipe);
e1a44743 3405 for (tries = 0; tries < 5; tries++) {
5eddb70b 3406 temp = I915_READ(reg);
8db9d77b
ZW		 3407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3408
3409 if ((temp & FDI_RX_BIT_LOCK)) {
3410 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3411 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3412 break;
3413 }
8db9d77b 3414 }
e1a44743 3415 if (tries == 5)
5eddb70b 3416 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3417
3418 /* Train 2 */
5eddb70b
CW		 3419 reg = FDI_TX_CTL(pipe);
3420 temp = I915_READ(reg);
8db9d77b
ZW		 3421 temp &= ~FDI_LINK_TRAIN_NONE;
3422 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3423 I915_WRITE(reg, temp);
8db9d77b 3424
5eddb70b
CW		 3425 reg = FDI_RX_CTL(pipe);
3426 temp = I915_READ(reg);
8db9d77b
ZW		 3427 temp &= ~FDI_LINK_TRAIN_NONE;
3428 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3429 I915_WRITE(reg, temp);
8db9d77b 3430
5eddb70b
CW		 3431 POSTING_READ(reg);
3432 udelay(150);
8db9d77b 3433
5eddb70b 3434 reg = FDI_RX_IIR(pipe);
e1a44743 3435 for (tries = 0; tries < 5; tries++) {
5eddb70b 3436 temp = I915_READ(reg);
8db9d77b
ZW		 3437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3438
3439 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3440 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3441 DRM_DEBUG_KMS("FDI train 2 done.\n");
3442 break;
3443 }
8db9d77b 3444 }
e1a44743 3445 if (tries == 5)
5eddb70b 3446 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3447
3448 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3449
8db9d77b
ZW		 3450}
3451
0206e353 3452static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3453 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3454 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3456 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3457};
3458
3459/* The FDI link training functions for SNB/Cougarpoint. */
3460static void gen6_fdi_link_train(struct drm_crtc *crtc)
3461{
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 int pipe = intel_crtc->pipe;
fa37d39e 3466 u32 reg, temp, i, retry;
8db9d77b 3467
e1a44743
AJ		 3468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3469 for train result */
5eddb70b
CW		 3470 reg = FDI_RX_IMR(pipe);
3471 temp = I915_READ(reg);
e1a44743
AJ		 3472 temp &= ~FDI_RX_SYMBOL_LOCK;
3473 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3474 I915_WRITE(reg, temp);
3475
3476 POSTING_READ(reg);
e1a44743
AJ		 3477 udelay(150);
3478
8db9d77b 3479 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3480 reg = FDI_TX_CTL(pipe);
3481 temp = I915_READ(reg);
627eb5a3 3482 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3483 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487 /* SNB-B */
3488 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3489 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3490
d74cf324
DV		 3491 I915_WRITE(FDI_RX_MISC(pipe),
3492 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3493
5eddb70b
CW		 3494 reg = FDI_RX_CTL(pipe);
3495 temp = I915_READ(reg);
8db9d77b
ZW		 3496 if (HAS_PCH_CPT(dev)) {
3497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3498 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3499 } else {
3500 temp &= ~FDI_LINK_TRAIN_NONE;
3501 temp |= FDI_LINK_TRAIN_PATTERN_1;
3502 }
5eddb70b
CW		 3503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3504
3505 POSTING_READ(reg);
8db9d77b
ZW		 3506 udelay(150);
3507
0206e353 3508 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3509 reg = FDI_TX_CTL(pipe);
3510 temp = I915_READ(reg);
8db9d77b
ZW		 3511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3512 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
8db9d77b
ZW		 3516 udelay(500);
3517
fa37d39e
SP		 3518 for (retry = 0; retry < 5; retry++) {
3519 reg = FDI_RX_IIR(pipe);
3520 temp = I915_READ(reg);
3521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3522 if (temp & FDI_RX_BIT_LOCK) {
3523 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3524 DRM_DEBUG_KMS("FDI train 1 done.\n");
3525 break;
3526 }
3527 udelay(50);
8db9d77b 3528 }
fa37d39e
SP		 3529 if (retry < 5)
3530 break;
8db9d77b
ZW		 3531 }
3532 if (i == 4)
5eddb70b 3533 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3534
3535 /* Train 2 */
5eddb70b
CW		 3536 reg = FDI_TX_CTL(pipe);
3537 temp = I915_READ(reg);
8db9d77b
ZW		 3538 temp &= ~FDI_LINK_TRAIN_NONE;
3539 temp |= FDI_LINK_TRAIN_PATTERN_2;
3540 if (IS_GEN6(dev)) {
3541 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3542 /* SNB-B */
3543 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3544 }
5eddb70b 3545 I915_WRITE(reg, temp);
8db9d77b 3546
5eddb70b
CW		 3547 reg = FDI_RX_CTL(pipe);
3548 temp = I915_READ(reg);
8db9d77b
ZW		 3549 if (HAS_PCH_CPT(dev)) {
3550 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3551 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3552 } else {
3553 temp &= ~FDI_LINK_TRAIN_NONE;
3554 temp |= FDI_LINK_TRAIN_PATTERN_2;
3555 }
5eddb70b
CW		 3556 I915_WRITE(reg, temp);
3557
3558 POSTING_READ(reg);
8db9d77b
ZW		 3559 udelay(150);
3560
0206e353 3561 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3562 reg = FDI_TX_CTL(pipe);
3563 temp = I915_READ(reg);
8db9d77b
ZW		 3564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3565 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3566 I915_WRITE(reg, temp);
3567
3568 POSTING_READ(reg);
8db9d77b
ZW		 3569 udelay(500);
3570
fa37d39e
SP		 3571 for (retry = 0; retry < 5; retry++) {
3572 reg = FDI_RX_IIR(pipe);
3573 temp = I915_READ(reg);
3574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3575 if (temp & FDI_RX_SYMBOL_LOCK) {
3576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3577 DRM_DEBUG_KMS("FDI train 2 done.\n");
3578 break;
3579 }
3580 udelay(50);
8db9d77b 3581 }
fa37d39e
SP		 3582 if (retry < 5)
3583 break;
8db9d77b
ZW		 3584 }
3585 if (i == 4)
5eddb70b 3586 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3587
3588 DRM_DEBUG_KMS("FDI train done.\n");
3589}
3590
357555c0
JB		 3591/* Manual link training for Ivy Bridge A0 parts */
3592static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3593{
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 int pipe = intel_crtc->pipe;
139ccd3f 3598 u32 reg, temp, i, j;
357555c0
JB		 3599
3600 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3601 for train result */
3602 reg = FDI_RX_IMR(pipe);
3603 temp = I915_READ(reg);
3604 temp &= ~FDI_RX_SYMBOL_LOCK;
3605 temp &= ~FDI_RX_BIT_LOCK;
3606 I915_WRITE(reg, temp);
3607
3608 POSTING_READ(reg);
3609 udelay(150);
3610
01a415fd
DV		 3611 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3612 I915_READ(FDI_RX_IIR(pipe)));
3613
139ccd3f
JB		 3614 /* Try each vswing and preemphasis setting twice before moving on */
3615 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3616 /* disable first in case we need to retry */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3620 temp &= ~FDI_TX_ENABLE;
3621 I915_WRITE(reg, temp);
357555c0 3622
139ccd3f
JB		 3623 reg = FDI_RX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_LINK_TRAIN_AUTO;
3626 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3627 temp &= ~FDI_RX_ENABLE;
3628 I915_WRITE(reg, temp);
357555c0 3629
139ccd3f 3630 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
139ccd3f 3633 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3634 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3635 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3636 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3637 temp |= snb_b_fdi_train_param[j/2];
3638 temp |= FDI_COMPOSITE_SYNC;
3639 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3640
139ccd3f
JB		 3641 I915_WRITE(FDI_RX_MISC(pipe),
3642 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3643
139ccd3f 3644 reg = FDI_RX_CTL(pipe);
357555c0 3645 temp = I915_READ(reg);
139ccd3f
JB		 3646 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3647 temp |= FDI_COMPOSITE_SYNC;
3648 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3649
139ccd3f
JB		 3650 POSTING_READ(reg);
3651 udelay(1); /* should be 0.5us */
357555c0 3652
139ccd3f
JB		 3653 for (i = 0; i < 4; i++) {
3654 reg = FDI_RX_IIR(pipe);
3655 temp = I915_READ(reg);
3656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3657
139ccd3f
JB		 3658 if (temp & FDI_RX_BIT_LOCK ||
3659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3661 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3662 i);
3663 break;
3664 }
3665 udelay(1); /* should be 0.5us */
3666 }
3667 if (i == 4) {
3668 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3669 continue;
3670 }
357555c0 3671
139ccd3f 3672 /* Train 2 */
357555c0
JB		 3673 reg = FDI_TX_CTL(pipe);
3674 temp = I915_READ(reg);
139ccd3f
JB		 3675 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3676 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3677 I915_WRITE(reg, temp);
3678
3679 reg = FDI_RX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3682 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3683 I915_WRITE(reg, temp);
3684
3685 POSTING_READ(reg);
139ccd3f 3686 udelay(2); /* should be 1.5us */
357555c0 3687
139ccd3f
JB		 3688 for (i = 0; i < 4; i++) {
3689 reg = FDI_RX_IIR(pipe);
3690 temp = I915_READ(reg);
3691 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3692
139ccd3f
JB		 3693 if (temp & FDI_RX_SYMBOL_LOCK ||
3694 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3695 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3696 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3697 i);
3698 goto train_done;
3699 }
3700 udelay(2); /* should be 1.5us */
357555c0 3701 }
139ccd3f
JB		 3702 if (i == 4)
3703 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3704 }
357555c0 3705
139ccd3f 3706train_done:
357555c0
JB		 3707 DRM_DEBUG_KMS("FDI train done.\n");
3708}
3709
88cefb6c 3710static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3711{
88cefb6c 3712 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3713 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3714 int pipe = intel_crtc->pipe;
5eddb70b 3715 u32 reg, temp;
79e53945 3716
c64e311e 3717
c98e9dcf 3718 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3719 reg = FDI_RX_CTL(pipe);
3720 temp = I915_READ(reg);
627eb5a3 3721 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3722 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3723 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3724 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3725
3726 POSTING_READ(reg);
c98e9dcf
JB		 3727 udelay(200);
3728
3729 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3730 temp = I915_READ(reg);
3731 I915_WRITE(reg, temp | FDI_PCDCLK);
3732
3733 POSTING_READ(reg);
c98e9dcf
JB		 3734 udelay(200);
3735
20749730
PZ		 3736 /* Enable CPU FDI TX PLL, always on for Ironlake */
3737 reg = FDI_TX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3740 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3741
20749730
PZ		 3742 POSTING_READ(reg);
3743 udelay(100);
6be4a607 3744 }
0e23b99d
JB		 3745}
3746
88cefb6c
DV		 3747static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3748{
3749 struct drm_device *dev = intel_crtc->base.dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 int pipe = intel_crtc->pipe;
3752 u32 reg, temp;
3753
3754 /* Switch from PCDclk to Rawclk */
3755 reg = FDI_RX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3758
3759 /* Disable CPU FDI TX PLL */
3760 reg = FDI_TX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3763
3764 POSTING_READ(reg);
3765 udelay(100);
3766
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3770
3771 /* Wait for the clocks to turn off. */
3772 POSTING_READ(reg);
3773 udelay(100);
3774}
3775
0fc932b8
JB		 3776static void ironlake_fdi_disable(struct drm_crtc *crtc)
3777{
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
3782 u32 reg, temp;
3783
3784 /* disable CPU FDI tx and PCH FDI rx */
3785 reg = FDI_TX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3788 POSTING_READ(reg);
3789
3790 reg = FDI_RX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~(0x7 << 16);
dfd07d72 3793 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3794 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3800 if (HAS_PCH_IBX(dev))
6f06ce18 3801 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3802
3803 /* still set train pattern 1 */
3804 reg = FDI_TX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~FDI_LINK_TRAIN_NONE;
3807 temp |= FDI_LINK_TRAIN_PATTERN_1;
3808 I915_WRITE(reg, temp);
3809
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 if (HAS_PCH_CPT(dev)) {
3813 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3814 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3815 } else {
3816 temp &= ~FDI_LINK_TRAIN_NONE;
3817 temp |= FDI_LINK_TRAIN_PATTERN_1;
3818 }
3819 /* BPC in FDI rx is consistent with that in PIPECONF */
3820 temp &= ~(0x07 << 16);
dfd07d72 3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3822 I915_WRITE(reg, temp);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826}
3827
5dce5b93
CW		 3828bool intel_has_pending_fb_unpin(struct drm_device *dev)
3829{
3830 struct intel_crtc *crtc;
3831
3832 /* Note that we don't need to be called with mode_config.lock here
3833 * as our list of CRTC objects is static for the lifetime of the
3834 * device and so cannot disappear as we iterate. Similarly, we can
3835 * happily treat the predicates as racy, atomic checks as userspace
3836 * cannot claim and pin a new fb without at least acquring the
3837 * struct_mutex and so serialising with us.
3838 */
d3fcc808 3839 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3840 if (atomic_read(&crtc->unpin_work_count) == 0)
3841 continue;
3842
3843 if (crtc->unpin_work)
3844 intel_wait_for_vblank(dev, crtc->pipe);
3845
3846 return true;
3847 }
3848
3849 return false;
3850}
3851
d6bbafa1
CW		 3852static void page_flip_completed(struct intel_crtc *intel_crtc)
3853{
3854 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3855 struct intel_unpin_work *work = intel_crtc->unpin_work;
3856
3857 /* ensure that the unpin work is consistent wrt ->pending. */
3858 smp_rmb();
3859 intel_crtc->unpin_work = NULL;
3860
3861 if (work->event)
3862 drm_send_vblank_event(intel_crtc->base.dev,
3863 intel_crtc->pipe,
3864 work->event);
3865
3866 drm_crtc_vblank_put(&intel_crtc->base);
3867
3868 wake_up_all(&dev_priv->pending_flip_queue);
3869 queue_work(dev_priv->wq, &work->work);
3870
3871 trace_i915_flip_complete(intel_crtc->plane,
3872 work->pending_flip_obj);
3873}
3874
46a55d30 3875void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3876{
0f91128d 3877 struct drm_device *dev = crtc->dev;
5bb61643 3878 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3879
2c10d571 3880 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3881 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3882 !intel_crtc_has_pending_flip(crtc),
3883 60*HZ) == 0)) {
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3885
5e2d7afc 3886 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3887 if (intel_crtc->unpin_work) {
3888 WARN_ONCE(1, "Removing stuck page flip\n");
3889 page_flip_completed(intel_crtc);
3890 }
5e2d7afc 3891 spin_unlock_irq(&dev->event_lock);
9c787942 3892 }
5bb61643 3893
975d568a
CW		 3894 if (crtc->primary->fb) {
3895 mutex_lock(&dev->struct_mutex);
3896 intel_finish_fb(crtc->primary->fb);
3897 mutex_unlock(&dev->struct_mutex);
3898 }
e6c3a2a6
CW		 3899}
3900
e615efe4
ED		 3901/* Program iCLKIP clock to the desired frequency */
3902static void lpt_program_iclkip(struct drm_crtc *crtc)
3903{
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3906 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3908 u32 temp;
3909
09153000
DV		 3910 mutex_lock(&dev_priv->dpio_lock);
3911
e615efe4
ED		 3912 /* It is necessary to ungate the pixclk gate prior to programming
3913 * the divisors, and gate it back when it is done.
3914 */
3915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3916
3917 /* Disable SSCCTL */
3918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3920 SBI_SSCCTL_DISABLE,
3921 SBI_ICLK);
e615efe4
ED		 3922
3923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3924 if (clock == 20000) {
e615efe4
ED		 3925 auxdiv = 1;
3926 divsel = 0x41;
3927 phaseinc = 0x20;
3928 } else {
3929 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3930 * but the adjusted_mode->crtc_clock in in KHz. To get the
3931 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3932 * convert the virtual clock precision to KHz here for higher
3933 * precision.
3934 */
3935 u32 iclk_virtual_root_freq = 172800 * 1000;
3936 u32 iclk_pi_range = 64;
3937 u32 desired_divisor, msb_divisor_value, pi_value;
3938
12d7ceed 3939 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3940 msb_divisor_value = desired_divisor / iclk_pi_range;
3941 pi_value = desired_divisor % iclk_pi_range;
3942
3943 auxdiv = 0;
3944 divsel = msb_divisor_value - 2;
3945 phaseinc = pi_value;
3946 }
3947
3948 /* This should not happen with any sane values */
3949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3953
3954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3955 clock,
e615efe4
ED		 3956 auxdiv,
3957 divsel,
3958 phasedir,
3959 phaseinc);
3960
3961 /* Program SSCDIVINTPHASE6 */
988d6ee8 3962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3970
3971 /* Program SSCAUXDIV */
988d6ee8 3972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3976
3977 /* Enable modulator and associated divider */
988d6ee8 3978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3979 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3981
3982 /* Wait for initialization time */
3983 udelay(24);
3984
3985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3986
3987 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3988}
3989
275f01b2
DV		 3990static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3991 enum pipe pch_transcoder)
3992{
3993 struct drm_device *dev = crtc->base.dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3995 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3996
3997 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3998 I915_READ(HTOTAL(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4000 I915_READ(HBLANK(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4002 I915_READ(HSYNC(cpu_transcoder)));
4003
4004 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4005 I915_READ(VTOTAL(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4007 I915_READ(VBLANK(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4009 I915_READ(VSYNC(cpu_transcoder)));
4010 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4011 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4012}
4013
003632d9 4014static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4015{
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 uint32_t temp;
4018
4019 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4020 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4021 return;
4022
4023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4025
003632d9
ACO		 4026 temp &= ~FDI_BC_BIFURCATION_SELECT;
4027 if (enable)
4028 temp |= FDI_BC_BIFURCATION_SELECT;
4029
4030 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4031 I915_WRITE(SOUTH_CHICKEN1, temp);
4032 POSTING_READ(SOUTH_CHICKEN1);
4033}
4034
4035static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4036{
4037 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4038
4039 switch (intel_crtc->pipe) {
4040 case PIPE_A:
4041 break;
4042 case PIPE_B:
6e3c9717 4043 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4044 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4045 else
003632d9 4046 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4047
4048 break;
4049 case PIPE_C:
003632d9 4050 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4051
4052 break;
4053 default:
4054 BUG();
4055 }
4056}
4057
f67a559d
JB		 4058/*
4059 * Enable PCH resources required for PCH ports:
4060 * - PCH PLLs
4061 * - FDI training & RX/TX
4062 * - update transcoder timings
4063 * - DP transcoding bits
4064 * - transcoder
4065 */
4066static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4067{
4068 struct drm_device *dev = crtc->dev;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4071 int pipe = intel_crtc->pipe;
ee7b9f93 4072 u32 reg, temp;
2c07245f 4073
ab9412ba 4074 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4075
1fbc0d78
DV		 4076 if (IS_IVYBRIDGE(dev))
4077 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4078
cd986abb
DV		 4079 /* Write the TU size bits before fdi link training, so that error
4080 * detection works. */
4081 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4082 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4083
c98e9dcf 4084 /* For PCH output, training FDI link */
674cf967 4085 dev_priv->display.fdi_link_train(crtc);
2c07245f 4086
3ad8a208
DV		 4087 /* We need to program the right clock selection before writing the pixel
4088 * mutliplier into the DPLL. */
303b81e0 4089 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4090 u32 sel;
4b645f14 4091
c98e9dcf 4092 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4093 temp |= TRANS_DPLL_ENABLE(pipe);
4094 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4095 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4096 temp |= sel;
4097 else
4098 temp &= ~sel;
c98e9dcf 4099 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4100 }
5eddb70b 4101
3ad8a208
DV		 4102 /* XXX: pch pll's can be enabled any time before we enable the PCH
4103 * transcoder, and we actually should do this to not upset any PCH
4104 * transcoder that already use the clock when we share it.
4105 *
4106 * Note that enable_shared_dpll tries to do the right thing, but
4107 * get_shared_dpll unconditionally resets the pll - we need that to have
4108 * the right LVDS enable sequence. */
85b3894f 4109 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4110
d9b6cb56
JB		 4111 /* set transcoder timing, panel must allow it */
4112 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4113 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4114
303b81e0 4115 intel_fdi_normal_train(crtc);
5e84e1a4 4116
c98e9dcf 4117 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4118 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4119 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4120 reg = TRANS_DP_CTL(pipe);
4121 temp = I915_READ(reg);
4122 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4123 TRANS_DP_SYNC_MASK |
4124 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4125 temp |= (TRANS_DP_OUTPUT_ENABLE |
4126 TRANS_DP_ENH_FRAMING);
9325c9f0 4127 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4128
4129 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4130 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4131 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4132 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4133
4134 switch (intel_trans_dp_port_sel(crtc)) {
4135 case PCH_DP_B:
5eddb70b 4136 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4137 break;
4138 case PCH_DP_C:
5eddb70b 4139 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4140 break;
4141 case PCH_DP_D:
5eddb70b 4142 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4143 break;
4144 default:
e95d41e1 4145 BUG();
32f9d658 4146 }
2c07245f 4147
5eddb70b 4148 I915_WRITE(reg, temp);
6be4a607 4149 }
b52eb4dc 4150
b8a4f404 4151 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4152}
4153
1507e5bd
PZ		 4154static void lpt_pch_enable(struct drm_crtc *crtc)
4155{
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4160
ab9412ba 4161 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4162
8c52b5e8 4163 lpt_program_iclkip(crtc);
1507e5bd 4164
0540e488 4165 /* Set transcoder timing. */
275f01b2 4166 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4167
937bb610 4168 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4169}
4170
716c2e55 4171void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4172{
e2b78267 4173 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4174
4175 if (pll == NULL)
4176 return;
4177
3e369b76 4178 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4179 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4180 return;
4181 }
4182
3e369b76
ACO		 4183 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4184 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4185 WARN_ON(pll->on);
4186 WARN_ON(pll->active);
4187 }
4188
6e3c9717 4189 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4190}
4191
190f68c5
ACO		 4192struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4193 struct intel_crtc_state *crtc_state)
ee7b9f93 4194{
e2b78267 4195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4196 struct intel_shared_dpll *pll;
e2b78267 4197 enum intel_dpll_id i;
ee7b9f93 4198
98b6bd99
DV		 4199 if (HAS_PCH_IBX(dev_priv->dev)) {
4200 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4201 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4202 pll = &dev_priv->shared_dplls[i];
98b6bd99 4203
46edb027
DV		 4204 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4205 crtc->base.base.id, pll->name);
98b6bd99 4206
8bd31e67 4207 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4208
98b6bd99
DV		 4209 goto found;
4210 }
4211
bcddf610
S		 4212 if (IS_BROXTON(dev_priv->dev)) {
4213 /* PLL is attached to port in bxt */
4214 struct intel_encoder *encoder;
4215 struct intel_digital_port *intel_dig_port;
4216
4217 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4218 if (WARN_ON(!encoder))
4219 return NULL;
4220
4221 intel_dig_port = enc_to_dig_port(&encoder->base);
4222 /* 1:1 mapping between ports and PLLs */
4223 i = (enum intel_dpll_id)intel_dig_port->port;
4224 pll = &dev_priv->shared_dplls[i];
4225 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4226 crtc->base.base.id, pll->name);
4227 WARN_ON(pll->new_config->crtc_mask);
4228
4229 goto found;
4230 }
4231
e72f9fbf
DV		 4232 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4233 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4234
4235 /* Only want to check enabled timings first */
8bd31e67 4236 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4237 continue;
4238
190f68c5 4239 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4240 &pll->new_config->hw_state,
4241 sizeof(pll->new_config->hw_state)) == 0) {
4242 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4243 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4244 pll->new_config->crtc_mask,
4245 pll->active);
ee7b9f93
JB		 4246 goto found;
4247 }
4248 }
4249
4250 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4251 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4252 pll = &dev_priv->shared_dplls[i];
8bd31e67 4253 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4254 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4255 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4256 goto found;
4257 }
4258 }
4259
4260 return NULL;
4261
4262found:
8bd31e67 4263 if (pll->new_config->crtc_mask == 0)
190f68c5 4264 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4265
190f68c5 4266 crtc_state->shared_dpll = i;
46edb027
DV		 4267 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4268 pipe_name(crtc->pipe));
ee7b9f93 4269
8bd31e67 4270 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4271
ee7b9f93
JB		 4272 return pll;
4273}
4274
8bd31e67
ACO		 4275/**
4276 * intel_shared_dpll_start_config - start a new PLL staged config
4277 * @dev_priv: DRM device
4278 * @clear_pipes: mask of pipes that will have their PLLs freed
4279 *
4280 * Starts a new PLL staged config, copying the current config but
4281 * releasing the references of pipes specified in clear_pipes.
4282 */
4283static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4284 unsigned clear_pipes)
4285{
4286 struct intel_shared_dpll *pll;
4287 enum intel_dpll_id i;
4288
4289 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4290 pll = &dev_priv->shared_dplls[i];
4291
4292 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4293 GFP_KERNEL);
4294 if (!pll->new_config)
4295 goto cleanup;
4296
4297 pll->new_config->crtc_mask &= ~clear_pipes;
4298 }
4299
4300 return 0;
4301
4302cleanup:
4303 while (--i >= 0) {
4304 pll = &dev_priv->shared_dplls[i];
f354d733 4305 kfree(pll->new_config);
8bd31e67
ACO		 4306 pll->new_config = NULL;
4307 }
4308
4309 return -ENOMEM;
4310}
4311
4312static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4313{
4314 struct intel_shared_dpll *pll;
4315 enum intel_dpll_id i;
4316
4317 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4318 pll = &dev_priv->shared_dplls[i];
4319
4320 WARN_ON(pll->new_config == &pll->config);
4321
4322 pll->config = *pll->new_config;
4323 kfree(pll->new_config);
4324 pll->new_config = NULL;
4325 }
4326}
4327
4328static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4329{
4330 struct intel_shared_dpll *pll;
4331 enum intel_dpll_id i;
4332
4333 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4334 pll = &dev_priv->shared_dplls[i];
4335
4336 WARN_ON(pll->new_config == &pll->config);
4337
4338 kfree(pll->new_config);
4339 pll->new_config = NULL;
4340 }
4341}
4342
a1520318 4343static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4344{
4345 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4346 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4347 u32 temp;
4348
4349 temp = I915_READ(dslreg);
4350 udelay(500);
4351 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4352 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4353 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4354 }
4355}
4356
a1b2278e
CK		 4357/**
4358 * skl_update_scaler_users - Stages update to crtc's scaler state
4359 * @intel_crtc: crtc
4360 * @crtc_state: crtc_state
4361 * @plane: plane (NULL indicates crtc is requesting update)
4362 * @plane_state: plane's state
4363 * @force_detach: request unconditional detachment of scaler
4364 *
4365 * This function updates scaler state for requested plane or crtc.
4366 * To request scaler usage update for a plane, caller shall pass plane pointer.
4367 * To request scaler usage update for crtc, caller shall pass plane pointer
4368 * as NULL.
4369 *
4370 * Return
4371 * 0 - scaler_usage updated successfully
4372 * error - requested scaling cannot be supported or other error condition
4373 */
4374int
4375skl_update_scaler_users(
4376 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4377 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4378 int force_detach)
4379{
4380 int need_scaling;
4381 int idx;
4382 int src_w, src_h, dst_w, dst_h;
4383 int *scaler_id;
4384 struct drm_framebuffer *fb;
4385 struct intel_crtc_scaler_state *scaler_state;
4386
4387 if (!intel_crtc || !crtc_state)
4388 return 0;
4389
4390 scaler_state = &crtc_state->scaler_state;
4391
4392 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4393 fb = intel_plane ? plane_state->base.fb : NULL;
4394
4395 if (intel_plane) {
4396 src_w = drm_rect_width(&plane_state->src) >> 16;
4397 src_h = drm_rect_height(&plane_state->src) >> 16;
4398 dst_w = drm_rect_width(&plane_state->dst);
4399 dst_h = drm_rect_height(&plane_state->dst);
4400 scaler_id = &plane_state->scaler_id;
4401 } else {
4402 struct drm_display_mode *adjusted_mode =
4403 &crtc_state->base.adjusted_mode;
4404 src_w = crtc_state->pipe_src_w;
4405 src_h = crtc_state->pipe_src_h;
4406 dst_w = adjusted_mode->hdisplay;
4407 dst_h = adjusted_mode->vdisplay;
4408 scaler_id = &scaler_state->scaler_id;
4409 }
4410 need_scaling = (src_w != dst_w || src_h != dst_h);
4411
4412 /*
4413 * if plane is being disabled or scaler is no more required or force detach
4414 * - free scaler binded to this plane/crtc
4415 * - in order to do this, update crtc->scaler_usage
4416 *
4417 * Here scaler state in crtc_state is set free so that
4418 * scaler can be assigned to other user. Actual register
4419 * update to free the scaler is done in plane/panel-fit programming.
4420 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4421 */
4422 if (force_detach || !need_scaling || (intel_plane &&
4423 (!fb || !plane_state->visible))) {
4424 if (*scaler_id >= 0) {
4425 scaler_state->scaler_users &= ~(1 << idx);
4426 scaler_state->scalers[*scaler_id].in_use = 0;
4427
4428 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4429 "crtc_state = %p scaler_users = 0x%x\n",
4430 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4431 intel_plane ? intel_plane->base.base.id :
4432 intel_crtc->base.base.id, crtc_state,
4433 scaler_state->scaler_users);
4434 *scaler_id = -1;
4435 }
4436 return 0;
4437 }
4438
4439 /* range checks */
4440 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4441 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4442
4443 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4444 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4445 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4446 "size is out of scaler range\n",
4447 intel_plane ? "PLANE" : "CRTC",
4448 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4449 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4450 return -EINVAL;
4451 }
4452
4453 /* check colorkey */
4454 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4455 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4456 intel_plane->base.base.id);
4457 return -EINVAL;
4458 }
4459
4460 /* Check src format */
4461 if (intel_plane) {
4462 switch (fb->pixel_format) {
4463 case DRM_FORMAT_RGB565:
4464 case DRM_FORMAT_XBGR8888:
4465 case DRM_FORMAT_XRGB8888:
4466 case DRM_FORMAT_ABGR8888:
4467 case DRM_FORMAT_ARGB8888:
4468 case DRM_FORMAT_XRGB2101010:
4469 case DRM_FORMAT_ARGB2101010:
4470 case DRM_FORMAT_XBGR2101010:
4471 case DRM_FORMAT_ABGR2101010:
4472 case DRM_FORMAT_YUYV:
4473 case DRM_FORMAT_YVYU:
4474 case DRM_FORMAT_UYVY:
4475 case DRM_FORMAT_VYUY:
4476 break;
4477 default:
4478 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4479 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4480 return -EINVAL;
4481 }
4482 }
4483
4484 /* mark this plane as a scaler user in crtc_state */
4485 scaler_state->scaler_users |= (1 << idx);
4486 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4487 "crtc_state = %p scaler_users = 0x%x\n",
4488 intel_plane ? "PLANE" : "CRTC",
4489 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4490 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4491 return 0;
4492}
4493
4494static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4495{
4496 struct drm_device *dev = crtc->base.dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 int pipe = crtc->pipe;
a1b2278e
CK		 4499 struct intel_crtc_scaler_state *scaler_state =
4500 &crtc->config->scaler_state;
4501
4502 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4503
4504 /* To update pfit, first update scaler state */
4505 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4506 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4507 skl_detach_scalers(crtc);
4508 if (!enable)
4509 return;
bd2e244f 4510
6e3c9717 4511 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4512 int id;
4513
4514 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4515 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4516 return;
4517 }
4518
4519 id = scaler_state->scaler_id;
4520 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4521 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4522 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4523 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4524
4525 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4526 }
4527}
4528
b074cec8
JB		 4529static void ironlake_pfit_enable(struct intel_crtc *crtc)
4530{
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 int pipe = crtc->pipe;
4534
6e3c9717 4535 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4536 /* Force use of hard-coded filter coefficients
4537 * as some pre-programmed values are broken,
4538 * e.g. x201.
4539 */
4540 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4541 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4542 PF_PIPE_SEL_IVB(pipe));
4543 else
4544 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4545 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4546 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4547 }
4548}
4549
4a3b8769 4550static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4551{
4552 struct drm_device *dev = crtc->dev;
4553 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4554 struct drm_plane *plane;
bb53d4ae
VS		 4555 struct intel_plane *intel_plane;
4556
af2b653b
MR		 4557 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4558 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4559 if (intel_plane->pipe == pipe)
4560 intel_plane_restore(&intel_plane->base);
af2b653b 4561 }
bb53d4ae
VS		 4562}
4563
0d703d4e
MR		 4564/*
4565 * Disable a plane internally without actually modifying the plane's state.
4566 * This will allow us to easily restore the plane later by just reprogramming
4567 * its state.
4568 */
4569static void disable_plane_internal(struct drm_plane *plane)
4570{
4571 struct intel_plane *intel_plane = to_intel_plane(plane);
4572 struct drm_plane_state *state =
4573 plane->funcs->atomic_duplicate_state(plane);
4574 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4575
4576 intel_state->visible = false;
4577 intel_plane->commit_plane(plane, intel_state);
4578
4579 intel_plane_destroy_state(plane, state);
4580}
4581
4a3b8769 4582static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4583{
4584 struct drm_device *dev = crtc->dev;
4585 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4586 struct drm_plane *plane;
bb53d4ae
VS		 4587 struct intel_plane *intel_plane;
4588
af2b653b
MR		 4589 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4590 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4591 if (plane->fb && intel_plane->pipe == pipe)
4592 disable_plane_internal(plane);
af2b653b 4593 }
bb53d4ae
VS		 4594}
4595
20bc8673 4596void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4597{
cea165c3
VS		 4598 struct drm_device *dev = crtc->base.dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4600
6e3c9717 4601 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4602 return;
4603
cea165c3
VS		 4604 /* We can only enable IPS after we enable a plane and wait for a vblank */
4605 intel_wait_for_vblank(dev, crtc->pipe);
4606
d77e4531 4607 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4608 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4609 mutex_lock(&dev_priv->rps.hw_lock);
4610 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4611 mutex_unlock(&dev_priv->rps.hw_lock);
4612 /* Quoting Art Runyan: "its not safe to expect any particular
4613 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4614 * mailbox." Moreover, the mailbox may return a bogus state,
4615 * so we need to just enable it and continue on.
2a114cc1
BW		 4616 */
4617 } else {
4618 I915_WRITE(IPS_CTL, IPS_ENABLE);
4619 /* The bit only becomes 1 in the next vblank, so this wait here
4620 * is essentially intel_wait_for_vblank. If we don't have this
4621 * and don't wait for vblanks until the end of crtc_enable, then
4622 * the HW state readout code will complain that the expected
4623 * IPS_CTL value is not the one we read. */
4624 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4625 DRM_ERROR("Timed out waiting for IPS enable\n");
4626 }
d77e4531
PZ		 4627}
4628
20bc8673 4629void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4630{
4631 struct drm_device *dev = crtc->base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633
6e3c9717 4634 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4635 return;
4636
4637 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4638 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4639 mutex_lock(&dev_priv->rps.hw_lock);
4640 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4641 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4642 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4643 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4644 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4645 } else {
2a114cc1 4646 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4647 POSTING_READ(IPS_CTL);
4648 }
d77e4531
PZ		 4649
4650 /* We need to wait for a vblank before we can disable the plane. */
4651 intel_wait_for_vblank(dev, crtc->pipe);
4652}
4653
4654/** Loads the palette/gamma unit for the CRTC with the prepared values */
4655static void intel_crtc_load_lut(struct drm_crtc *crtc)
4656{
4657 struct drm_device *dev = crtc->dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4660 enum pipe pipe = intel_crtc->pipe;
4661 int palreg = PALETTE(pipe);
4662 int i;
4663 bool reenable_ips = false;
4664
4665 /* The clocks have to be on to load the palette. */
83d65738 4666 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4667 return;
4668
50360403 4669 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4670 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4671 assert_dsi_pll_enabled(dev_priv);
4672 else
4673 assert_pll_enabled(dev_priv, pipe);
4674 }
4675
4676 /* use legacy palette for Ironlake */
7a1db49a 4677 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4678 palreg = LGC_PALETTE(pipe);
4679
4680 /* Workaround : Do not read or write the pipe palette/gamma data while
4681 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4682 */
6e3c9717 4683 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4684 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4685 GAMMA_MODE_MODE_SPLIT)) {
4686 hsw_disable_ips(intel_crtc);
4687 reenable_ips = true;
4688 }
4689
4690 for (i = 0; i < 256; i++) {
4691 I915_WRITE(palreg + 4 * i,
4692 (intel_crtc->lut_r[i] << 16) |
4693 (intel_crtc->lut_g[i] << 8) |
4694 intel_crtc->lut_b[i]);
4695 }
4696
4697 if (reenable_ips)
4698 hsw_enable_ips(intel_crtc);
4699}
4700
d3eedb1a
VS		 4701static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4702{
4703 if (!enable && intel_crtc->overlay) {
4704 struct drm_device *dev = intel_crtc->base.dev;
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706
4707 mutex_lock(&dev->struct_mutex);
4708 dev_priv->mm.interruptible = false;
4709 (void) intel_overlay_switch_off(intel_crtc->overlay);
4710 dev_priv->mm.interruptible = true;
4711 mutex_unlock(&dev->struct_mutex);
4712 }
4713
4714 /* Let userspace switch the overlay on again. In most cases userspace
4715 * has to recompute where to put it anyway.
4716 */
4717}
4718
d3eedb1a 4719static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4720{
4721 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4723 int pipe = intel_crtc->pipe;
a5c4d7bc 4724
fdd508a6 4725 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4726 intel_enable_sprite_planes(crtc);
a5c4d7bc 4727 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4728 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4729
4730 hsw_enable_ips(intel_crtc);
4731
4732 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4733 intel_fbc_update(dev);
a5c4d7bc 4734 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4735
4736 /*
4737 * FIXME: Once we grow proper nuclear flip support out of this we need
4738 * to compute the mask of flip planes precisely. For the time being
4739 * consider this a flip from a NULL plane.
4740 */
4741 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4742}
4743
d3eedb1a 4744static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4745{
4746 struct drm_device *dev = crtc->dev;
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4749 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4750
4751 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4752
e35fef21 4753 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4754 intel_fbc_disable(dev);
a5c4d7bc
VS		 4755
4756 hsw_disable_ips(intel_crtc);
4757
d3eedb1a 4758 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4759 intel_crtc_update_cursor(crtc, false);
4a3b8769 4760 intel_disable_sprite_planes(crtc);
fdd508a6 4761 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4762
f99d7069
DV		 4763 /*
4764 * FIXME: Once we grow proper nuclear flip support out of this we need
4765 * to compute the mask of flip planes precisely. For the time being
4766 * consider this a flip to a NULL plane.
4767 */
4768 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4769}
4770
f67a559d
JB		 4771static void ironlake_crtc_enable(struct drm_crtc *crtc)
4772{
4773 struct drm_device *dev = crtc->dev;
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4776 struct intel_encoder *encoder;
f67a559d 4777 int pipe = intel_crtc->pipe;
f67a559d 4778
83d65738 4779 WARN_ON(!crtc->state->enable);
08a48469 4780
f67a559d
JB		 4781 if (intel_crtc->active)
4782 return;
4783
6e3c9717 4784 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4785 intel_prepare_shared_dpll(intel_crtc);
4786
6e3c9717 4787 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4788 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4789
4790 intel_set_pipe_timings(intel_crtc);
4791
6e3c9717 4792 if (intel_crtc->config->has_pch_encoder) {
29407aab 4793 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4794 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4795 }
4796
4797 ironlake_set_pipeconf(crtc);
4798
f67a559d 4799 intel_crtc->active = true;
8664281b 4800
a72e4c9f
DV		 4801 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4802 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4803
f6736a1a 4804 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4805 if (encoder->pre_enable)
4806 encoder->pre_enable(encoder);
f67a559d 4807
6e3c9717 4808 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4809 /* Note: FDI PLL enabling _must_ be done before we enable the
4810 * cpu pipes, hence this is separate from all the other fdi/pch
4811 * enabling. */
88cefb6c 4812 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4813 } else {
4814 assert_fdi_tx_disabled(dev_priv, pipe);
4815 assert_fdi_rx_disabled(dev_priv, pipe);
4816 }
f67a559d 4817
b074cec8 4818 ironlake_pfit_enable(intel_crtc);
f67a559d 4819
9c54c0dd
JB		 4820 /*
4821 * On ILK+ LUT must be loaded before the pipe is running but with
4822 * clocks enabled
4823 */
4824 intel_crtc_load_lut(crtc);
4825
f37fcc2a 4826 intel_update_watermarks(crtc);
e1fdc473 4827 intel_enable_pipe(intel_crtc);
f67a559d 4828
6e3c9717 4829 if (intel_crtc->config->has_pch_encoder)
f67a559d 4830 ironlake_pch_enable(crtc);
c98e9dcf 4831
f9b61ff6
DV		 4832 assert_vblank_disabled(crtc);
4833 drm_crtc_vblank_on(crtc);
4834
fa5c73b1
DV		 4835 for_each_encoder_on_crtc(dev, crtc, encoder)
4836 encoder->enable(encoder);
61b77ddd
DV		 4837
4838 if (HAS_PCH_CPT(dev))
a1520318 4839 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4840
d3eedb1a 4841 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4842}
4843
42db64ef
PZ		 4844/* IPS only exists on ULT machines and is tied to pipe A. */
4845static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4846{
f5adf94e 4847 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4848}
4849
e4916946
PZ		 4850/*
4851 * This implements the workaround described in the "notes" section of the mode
4852 * set sequence documentation. When going from no pipes or single pipe to
4853 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4854 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4855 */
4856static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4857{
4858 struct drm_device *dev = crtc->base.dev;
4859 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4860
4861 /* We want to get the other_active_crtc only if there's only 1 other
4862 * active crtc. */
d3fcc808 4863 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4864 if (!crtc_it->active || crtc_it == crtc)
4865 continue;
4866
4867 if (other_active_crtc)
4868 return;
4869
4870 other_active_crtc = crtc_it;
4871 }
4872 if (!other_active_crtc)
4873 return;
4874
4875 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4876 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4877}
4878
4f771f10
PZ		 4879static void haswell_crtc_enable(struct drm_crtc *crtc)
4880{
4881 struct drm_device *dev = crtc->dev;
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4884 struct intel_encoder *encoder;
4885 int pipe = intel_crtc->pipe;
4f771f10 4886
83d65738 4887 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4888
4889 if (intel_crtc->active)
4890 return;
4891
df8ad70c
DV		 4892 if (intel_crtc_to_shared_dpll(intel_crtc))
4893 intel_enable_shared_dpll(intel_crtc);
4894
6e3c9717 4895 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4896 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4897
4898 intel_set_pipe_timings(intel_crtc);
4899
6e3c9717
ACO		 4900 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4901 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4902 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4903 }
4904
6e3c9717 4905 if (intel_crtc->config->has_pch_encoder) {
229fca97 4906 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4907 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4908 }
4909
4910 haswell_set_pipeconf(crtc);
4911
4912 intel_set_pipe_csc(crtc);
4913
4f771f10 4914 intel_crtc->active = true;
8664281b 4915
a72e4c9f 4916 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4917 for_each_encoder_on_crtc(dev, crtc, encoder)
4918 if (encoder->pre_enable)
4919 encoder->pre_enable(encoder);
4920
6e3c9717 4921 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4922 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4923 true);
4fe9467d
ID		 4924 dev_priv->display.fdi_link_train(crtc);
4925 }
4926
1f544388 4927 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4928
ff6d9f55 4929 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4930 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4931 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4932 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4933 else
4934 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4935
4936 /*
4937 * On ILK+ LUT must be loaded before the pipe is running but with
4938 * clocks enabled
4939 */
4940 intel_crtc_load_lut(crtc);
4941
1f544388 4942 intel_ddi_set_pipe_settings(crtc);
8228c251 4943 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4944
f37fcc2a 4945 intel_update_watermarks(crtc);
e1fdc473 4946 intel_enable_pipe(intel_crtc);
42db64ef 4947
6e3c9717 4948 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4949 lpt_pch_enable(crtc);
4f771f10 4950
6e3c9717 4951 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4952 intel_ddi_set_vc_payload_alloc(crtc, true);
4953
f9b61ff6
DV		 4954 assert_vblank_disabled(crtc);
4955 drm_crtc_vblank_on(crtc);
4956
8807e55b 4957 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4958 encoder->enable(encoder);
8807e55b
JN		 4959 intel_opregion_notify_encoder(encoder, true);
4960 }
4f771f10 4961
e4916946
PZ		 4962 /* If we change the relative order between pipe/planes enabling, we need
4963 * to change the workaround. */
4964 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4965 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4966}
4967
3f8dce3a
DV		 4968static void ironlake_pfit_disable(struct intel_crtc *crtc)
4969{
4970 struct drm_device *dev = crtc->base.dev;
4971 struct drm_i915_private *dev_priv = dev->dev_private;
4972 int pipe = crtc->pipe;
4973
4974 /* To avoid upsetting the power well on haswell only disable the pfit if
4975 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4976 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4977 I915_WRITE(PF_CTL(pipe), 0);
4978 I915_WRITE(PF_WIN_POS(pipe), 0);
4979 I915_WRITE(PF_WIN_SZ(pipe), 0);
4980 }
4981}
4982
6be4a607
JB		 4983static void ironlake_crtc_disable(struct drm_crtc *crtc)
4984{
4985 struct drm_device *dev = crtc->dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4988 struct intel_encoder *encoder;
6be4a607 4989 int pipe = intel_crtc->pipe;
5eddb70b 4990 u32 reg, temp;
b52eb4dc 4991
f7abfe8b
CW		 4992 if (!intel_crtc->active)
4993 return;
4994
d3eedb1a 4995 intel_crtc_disable_planes(crtc);
a5c4d7bc 4996
ea9d758d
DV		 4997 for_each_encoder_on_crtc(dev, crtc, encoder)
4998 encoder->disable(encoder);
4999
f9b61ff6
DV		 5000 drm_crtc_vblank_off(crtc);
5001 assert_vblank_disabled(crtc);
5002
6e3c9717 5003 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5004 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5005
575f7ab7 5006 intel_disable_pipe(intel_crtc);
32f9d658 5007
3f8dce3a 5008 ironlake_pfit_disable(intel_crtc);
2c07245f 5009
bf49ec8c
DV		 5010 for_each_encoder_on_crtc(dev, crtc, encoder)
5011 if (encoder->post_disable)
5012 encoder->post_disable(encoder);
2c07245f 5013
6e3c9717 5014 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5015 ironlake_fdi_disable(crtc);
913d8d11 5016
d925c59a 5017 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5018
d925c59a
DV		 5019 if (HAS_PCH_CPT(dev)) {
5020 /* disable TRANS_DP_CTL */
5021 reg = TRANS_DP_CTL(pipe);
5022 temp = I915_READ(reg);
5023 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5024 TRANS_DP_PORT_SEL_MASK);
5025 temp |= TRANS_DP_PORT_SEL_NONE;
5026 I915_WRITE(reg, temp);
5027
5028 /* disable DPLL_SEL */
5029 temp = I915_READ(PCH_DPLL_SEL);
11887397 5030 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5031 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5032 }
e3421a18 5033
d925c59a 5034 /* disable PCH DPLL */
e72f9fbf 5035 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5036
d925c59a
DV		 5037 ironlake_fdi_pll_disable(intel_crtc);
5038 }
6b383a7f 5039
f7abfe8b 5040 intel_crtc->active = false;
46ba614c 5041 intel_update_watermarks(crtc);
d1ebd816
BW		 5042
5043 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5044 intel_fbc_update(dev);
d1ebd816 5045 mutex_unlock(&dev->struct_mutex);
6be4a607 5046}
1b3c7a47 5047
4f771f10 5048static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5049{
4f771f10
PZ		 5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5053 struct intel_encoder *encoder;
6e3c9717 5054 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5055
4f771f10
PZ		 5056 if (!intel_crtc->active)
5057 return;
5058
d3eedb1a 5059 intel_crtc_disable_planes(crtc);
dda9a66a 5060
8807e55b
JN		 5061 for_each_encoder_on_crtc(dev, crtc, encoder) {
5062 intel_opregion_notify_encoder(encoder, false);
4f771f10 5063 encoder->disable(encoder);
8807e55b 5064 }
4f771f10 5065
f9b61ff6
DV		 5066 drm_crtc_vblank_off(crtc);
5067 assert_vblank_disabled(crtc);
5068
6e3c9717 5069 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5070 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5071 false);
575f7ab7 5072 intel_disable_pipe(intel_crtc);
4f771f10 5073
6e3c9717 5074 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5075 intel_ddi_set_vc_payload_alloc(crtc, false);
5076
ad80a810 5077 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5078
ff6d9f55 5079 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5080 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5081 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5082 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5083 else
5084 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5085
1f544388 5086 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5087
6e3c9717 5088 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5089 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5090 intel_ddi_fdi_disable(crtc);
83616634 5091 }
4f771f10 5092
97b040aa
ID		 5093 for_each_encoder_on_crtc(dev, crtc, encoder)
5094 if (encoder->post_disable)
5095 encoder->post_disable(encoder);
5096
4f771f10 5097 intel_crtc->active = false;
46ba614c 5098 intel_update_watermarks(crtc);
4f771f10
PZ		 5099
5100 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5101 intel_fbc_update(dev);
4f771f10 5102 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5103
5104 if (intel_crtc_to_shared_dpll(intel_crtc))
5105 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5106}
5107
ee7b9f93
JB		 5108static void ironlake_crtc_off(struct drm_crtc *crtc)
5109{
5110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5111 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5112}
5113
6441ab5f 5114
2dd24552
JB		 5115static void i9xx_pfit_enable(struct intel_crtc *crtc)
5116{
5117 struct drm_device *dev = crtc->base.dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5119 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5120
681a8504 5121 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5122 return;
5123
2dd24552 5124 /*
c0b03411
DV		 5125 * The panel fitter should only be adjusted whilst the pipe is disabled,
5126 * according to register description and PRM.
2dd24552 5127 */
c0b03411
DV		 5128 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5129 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5130
b074cec8
JB		 5131 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5132 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5133
5134 /* Border color in case we don't scale up to the full screen. Black by
5135 * default, change to something else for debugging. */
5136 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5137}
5138
d05410f9
DA		 5139static enum intel_display_power_domain port_to_power_domain(enum port port)
5140{
5141 switch (port) {
5142 case PORT_A:
5143 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5144 case PORT_B:
5145 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5146 case PORT_C:
5147 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5148 case PORT_D:
5149 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5150 default:
5151 WARN_ON_ONCE(1);
5152 return POWER_DOMAIN_PORT_OTHER;
5153 }
5154}
5155
77d22dca
ID		 5156#define for_each_power_domain(domain, mask) \
5157 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5158 if ((1 << (domain)) & (mask))
5159
319be8ae
ID		 5160enum intel_display_power_domain
5161intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5162{
5163 struct drm_device *dev = intel_encoder->base.dev;
5164 struct intel_digital_port *intel_dig_port;
5165
5166 switch (intel_encoder->type) {
5167 case INTEL_OUTPUT_UNKNOWN:
5168 /* Only DDI platforms should ever use this output type */
5169 WARN_ON_ONCE(!HAS_DDI(dev));
5170 case INTEL_OUTPUT_DISPLAYPORT:
5171 case INTEL_OUTPUT_HDMI:
5172 case INTEL_OUTPUT_EDP:
5173 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5174 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5175 case INTEL_OUTPUT_DP_MST:
5176 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5177 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5178 case INTEL_OUTPUT_ANALOG:
5179 return POWER_DOMAIN_PORT_CRT;
5180 case INTEL_OUTPUT_DSI:
5181 return POWER_DOMAIN_PORT_DSI;
5182 default:
5183 return POWER_DOMAIN_PORT_OTHER;
5184 }
5185}
5186
5187static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5188{
319be8ae
ID		 5189 struct drm_device *dev = crtc->dev;
5190 struct intel_encoder *intel_encoder;
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5193 unsigned long mask;
5194 enum transcoder transcoder;
5195
5196 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5197
5198 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5199 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5200 if (intel_crtc->config->pch_pfit.enabled ||
5201 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5202 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5203
319be8ae
ID		 5204 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5205 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5206
77d22dca
ID		 5207 return mask;
5208}
5209
679dacd4 5210static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5211{
679dacd4 5212 struct drm_device *dev = state->dev;
77d22dca
ID		 5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5215 struct intel_crtc *crtc;
5216
5217 /*
5218 * First get all needed power domains, then put all unneeded, to avoid
5219 * any unnecessary toggling of the power wells.
5220 */
d3fcc808 5221 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5222 enum intel_display_power_domain domain;
5223
83d65738 5224 if (!crtc->base.state->enable)
77d22dca
ID		 5225 continue;
5226
319be8ae 5227 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5228
5229 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5230 intel_display_power_get(dev_priv, domain);
5231 }
5232
50f6e502 5233 if (dev_priv->display.modeset_global_resources)
679dacd4 5234 dev_priv->display.modeset_global_resources(state);
50f6e502 5235
d3fcc808 5236 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5237 enum intel_display_power_domain domain;
5238
5239 for_each_power_domain(domain, crtc->enabled_power_domains)
5240 intel_display_power_put(dev_priv, domain);
5241
5242 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5243 }
5244
5245 intel_display_set_init_power(dev_priv, false);
5246}
5247
f8437dd1
VK		 5248void broxton_set_cdclk(struct drm_device *dev, int frequency)
5249{
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251 uint32_t divider;
5252 uint32_t ratio;
5253 uint32_t current_freq;
5254 int ret;
5255
5256 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5257 switch (frequency) {
5258 case 144000:
5259 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5260 ratio = BXT_DE_PLL_RATIO(60);
5261 break;
5262 case 288000:
5263 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5264 ratio = BXT_DE_PLL_RATIO(60);
5265 break;
5266 case 384000:
5267 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5268 ratio = BXT_DE_PLL_RATIO(60);
5269 break;
5270 case 576000:
5271 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5272 ratio = BXT_DE_PLL_RATIO(60);
5273 break;
5274 case 624000:
5275 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5276 ratio = BXT_DE_PLL_RATIO(65);
5277 break;
5278 case 19200:
5279 /*
5280 * Bypass frequency with DE PLL disabled. Init ratio, divider
5281 * to suppress GCC warning.
5282 */
5283 ratio = 0;
5284 divider = 0;
5285 break;
5286 default:
5287 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5288
5289 return;
5290 }
5291
5292 mutex_lock(&dev_priv->rps.hw_lock);
5293 /* Inform power controller of upcoming frequency change */
5294 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5295 0x80000000);
5296 mutex_unlock(&dev_priv->rps.hw_lock);
5297
5298 if (ret) {
5299 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5300 ret, frequency);
5301 return;
5302 }
5303
5304 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5305 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5306 current_freq = current_freq * 500 + 1000;
5307
5308 /*
5309 * DE PLL has to be disabled when
5310 * - setting to 19.2MHz (bypass, PLL isn't used)
5311 * - before setting to 624MHz (PLL needs toggling)
5312 * - before setting to any frequency from 624MHz (PLL needs toggling)
5313 */
5314 if (frequency == 19200 || frequency == 624000 ||
5315 current_freq == 624000) {
5316 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5317 /* Timeout 200us */
5318 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5319 1))
5320 DRM_ERROR("timout waiting for DE PLL unlock\n");
5321 }
5322
5323 if (frequency != 19200) {
5324 uint32_t val;
5325
5326 val = I915_READ(BXT_DE_PLL_CTL);
5327 val &= ~BXT_DE_PLL_RATIO_MASK;
5328 val |= ratio;
5329 I915_WRITE(BXT_DE_PLL_CTL, val);
5330
5331 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5332 /* Timeout 200us */
5333 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5334 DRM_ERROR("timeout waiting for DE PLL lock\n");
5335
5336 val = I915_READ(CDCLK_CTL);
5337 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5338 val |= divider;
5339 /*
5340 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5341 * enable otherwise.
5342 */
5343 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5344 if (frequency >= 500000)
5345 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5346
5347 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5348 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5349 val |= (frequency - 1000) / 500;
5350 I915_WRITE(CDCLK_CTL, val);
5351 }
5352
5353 mutex_lock(&dev_priv->rps.hw_lock);
5354 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5355 DIV_ROUND_UP(frequency, 25000));
5356 mutex_unlock(&dev_priv->rps.hw_lock);
5357
5358 if (ret) {
5359 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5360 ret, frequency);
5361 return;
5362 }
5363
5364 dev_priv->cdclk_freq = frequency;
5365}
5366
5367void broxton_init_cdclk(struct drm_device *dev)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t val;
5371
5372 /*
5373 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5374 * or else the reset will hang because there is no PCH to respond.
5375 * Move the handshake programming to initialization sequence.
5376 * Previously was left up to BIOS.
5377 */
5378 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5379 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5380 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5381
5382 /* Enable PG1 for cdclk */
5383 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5384
5385 /* check if cd clock is enabled */
5386 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5387 DRM_DEBUG_KMS("Display already initialized\n");
5388 return;
5389 }
5390
5391 /*
5392 * FIXME:
5393 * - The initial CDCLK needs to be read from VBT.
5394 * Need to make this change after VBT has changes for BXT.
5395 * - check if setting the max (or any) cdclk freq is really necessary
5396 * here, it belongs to modeset time
5397 */
5398 broxton_set_cdclk(dev, 624000);
5399
5400 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5401 udelay(10);
5402
5403 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5404 DRM_ERROR("DBuf power enable timeout!\n");
5405}
5406
5407void broxton_uninit_cdclk(struct drm_device *dev)
5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410
5411 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5412 udelay(10);
5413
5414 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5415 DRM_ERROR("DBuf power disable timeout!\n");
5416
5417 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5418 broxton_set_cdclk(dev, 19200);
5419
5420 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5421}
5422
dfcab17e 5423/* returns HPLL frequency in kHz */
f8bf63fd 5424static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5425{
586f49dc 5426 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5427
586f49dc
JB		 5428 /* Obtain SKU information */
5429 mutex_lock(&dev_priv->dpio_lock);
5430 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5431 CCK_FUSE_HPLL_FREQ_MASK;
5432 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5433
dfcab17e 5434 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5435}
5436
f8bf63fd
VS		 5437static void vlv_update_cdclk(struct drm_device *dev)
5438{
5439 struct drm_i915_private *dev_priv = dev->dev_private;
5440
164dfd28 5441 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5442 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5443 dev_priv->cdclk_freq);
f8bf63fd
VS		 5444
5445 /*
5446 * Program the gmbus_freq based on the cdclk frequency.
5447 * BSpec erroneously claims we should aim for 4MHz, but
5448 * in fact 1MHz is the correct frequency.
5449 */
164dfd28 5450 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5451}
5452
30a970c6
JB		 5453/* Adjust CDclk dividers to allow high res or save power if possible */
5454static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5455{
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 u32 val, cmd;
5458
164dfd28
VK		 5459 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5460 != dev_priv->cdclk_freq);
d60c4473 5461
dfcab17e 5462 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5463 cmd = 2;
dfcab17e 5464 else if (cdclk == 266667)
30a970c6
JB		 5465 cmd = 1;
5466 else
5467 cmd = 0;
5468
5469 mutex_lock(&dev_priv->rps.hw_lock);
5470 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5471 val &= ~DSPFREQGUAR_MASK;
5472 val |= (cmd << DSPFREQGUAR_SHIFT);
5473 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5474 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5475 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5476 50)) {
5477 DRM_ERROR("timed out waiting for CDclk change\n");
5478 }
5479 mutex_unlock(&dev_priv->rps.hw_lock);
5480
dfcab17e 5481 if (cdclk == 400000) {
6bcda4f0 5482 u32 divider;
30a970c6 5483
6bcda4f0 5484 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5485
5486 mutex_lock(&dev_priv->dpio_lock);
5487 /* adjust cdclk divider */
5488 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5489 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5490 val |= divider;
5491 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5492
5493 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5494 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5495 50))
5496 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5497 mutex_unlock(&dev_priv->dpio_lock);
5498 }
5499
5500 mutex_lock(&dev_priv->dpio_lock);
5501 /* adjust self-refresh exit latency value */
5502 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5503 val &= ~0x7f;
5504
5505 /*
5506 * For high bandwidth configs, we set a higher latency in the bunit
5507 * so that the core display fetch happens in time to avoid underruns.
5508 */
dfcab17e 5509 if (cdclk == 400000)
30a970c6
JB		 5510 val |= 4500 / 250; /* 4.5 usec */
5511 else
5512 val |= 3000 / 250; /* 3.0 usec */
5513 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5514 mutex_unlock(&dev_priv->dpio_lock);
5515
f8bf63fd 5516 vlv_update_cdclk(dev);
30a970c6
JB		 5517}
5518
383c5a6a
VS		 5519static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5520{
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522 u32 val, cmd;
5523
164dfd28
VK		 5524 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5525 != dev_priv->cdclk_freq);
383c5a6a
VS		 5526
5527 switch (cdclk) {
383c5a6a
VS		 5528 case 333333:
5529 case 320000:
383c5a6a 5530 case 266667:
383c5a6a 5531 case 200000:
383c5a6a
VS		 5532 break;
5533 default:
5f77eeb0 5534 MISSING_CASE(cdclk);
383c5a6a
VS		 5535 return;
5536 }
5537
9d0d3fda
VS		 5538 /*
5539 * Specs are full of misinformation, but testing on actual
5540 * hardware has shown that we just need to write the desired
5541 * CCK divider into the Punit register.
5542 */
5543 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5544
383c5a6a
VS		 5545 mutex_lock(&dev_priv->rps.hw_lock);
5546 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5547 val &= ~DSPFREQGUAR_MASK_CHV;
5548 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5549 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5550 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5551 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5552 50)) {
5553 DRM_ERROR("timed out waiting for CDclk change\n");
5554 }
5555 mutex_unlock(&dev_priv->rps.hw_lock);
5556
5557 vlv_update_cdclk(dev);
5558}
5559
30a970c6
JB		 5560static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5561 int max_pixclk)
5562{
6bcda4f0 5563 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5564 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5565
30a970c6
JB		 5566 /*
5567 * Really only a few cases to deal with, as only 4 CDclks are supported:
5568 * 200MHz
5569 * 267MHz
29dc7ef3 5570 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5571 * 400MHz (VLV only)
5572 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5573 * of the lower bin and adjust if needed.
e37c67a1
VS		 5574 *
5575 * We seem to get an unstable or solid color picture at 200MHz.
5576 * Not sure what's wrong. For now use 200MHz only when all pipes
5577 * are off.
30a970c6 5578 */
6cca3195
VS		 5579 if (!IS_CHERRYVIEW(dev_priv) &&
5580 max_pixclk > freq_320*limit/100)
dfcab17e 5581 return 400000;
6cca3195 5582 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5583 return freq_320;
e37c67a1 5584 else if (max_pixclk > 0)
dfcab17e 5585 return 266667;
e37c67a1
VS		 5586 else
5587 return 200000;
30a970c6
JB		 5588}
5589
f8437dd1
VK		 5590static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5591 int max_pixclk)
5592{
5593 /*
5594 * FIXME:
5595 * - remove the guardband, it's not needed on BXT
5596 * - set 19.2MHz bypass frequency if there are no active pipes
5597 */
5598 if (max_pixclk > 576000*9/10)
5599 return 624000;
5600 else if (max_pixclk > 384000*9/10)
5601 return 576000;
5602 else if (max_pixclk > 288000*9/10)
5603 return 384000;
5604 else if (max_pixclk > 144000*9/10)
5605 return 288000;
5606 else
5607 return 144000;
5608}
5609
2f2d7aa1 5610/* compute the max pixel clock for new configuration */
304603f4 5611static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5612{
304603f4 5613 struct drm_device *dev = state->dev;
30a970c6 5614 struct intel_crtc *intel_crtc;
304603f4 5615 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5616 int max_pixclk = 0;
5617
d3fcc808 5618 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5619 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5620 if (IS_ERR(crtc_state))
5621 return PTR_ERR(crtc_state);
5622
5623 if (!crtc_state->base.enable)
5624 continue;
5625
5626 max_pixclk = max(max_pixclk,
5627 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5628 }
5629
5630 return max_pixclk;
5631}
5632
304603f4 5633static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5634 unsigned *prepare_pipes)
30a970c6 5635{
304603f4 5636 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5637 struct intel_crtc *intel_crtc;
304603f4 5638 int max_pixclk = intel_mode_max_pixclk(state);
f8437dd1 5639 int cdclk;
304603f4
ACO		 5640
5641 if (max_pixclk < 0)
5642 return max_pixclk;
30a970c6 5643
f8437dd1
VK		 5644 if (IS_VALLEYVIEW(dev_priv))
5645 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5646 else
5647 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5648
5649 if (cdclk == dev_priv->cdclk_freq)
304603f4 5650 return 0;
30a970c6 5651
2f2d7aa1 5652 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5653 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5654 if (intel_crtc->base.state->enable)
30a970c6 5655 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5656
5657 return 0;
30a970c6
JB		 5658}
5659
1e69cd74
VS		 5660static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5661{
5662 unsigned int credits, default_credits;
5663
5664 if (IS_CHERRYVIEW(dev_priv))
5665 default_credits = PFI_CREDIT(12);
5666 else
5667 default_credits = PFI_CREDIT(8);
5668
164dfd28 5669 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5670 /* CHV suggested value is 31 or 63 */
5671 if (IS_CHERRYVIEW(dev_priv))
5672 credits = PFI_CREDIT_31;
5673 else
5674 credits = PFI_CREDIT(15);
5675 } else {
5676 credits = default_credits;
5677 }
5678
5679 /*
5680 * WA - write default credits before re-programming
5681 * FIXME: should we also set the resend bit here?
5682 */
5683 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5684 default_credits);
5685
5686 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5687 credits | PFI_CREDIT_RESEND);
5688
5689 /*
5690 * FIXME is this guaranteed to clear
5691 * immediately or should we poll for it?
5692 */
5693 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5694}
5695
679dacd4 5696static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5697{
679dacd4 5698 struct drm_device *dev = state->dev;
30a970c6 5699 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5700 int max_pixclk = intel_mode_max_pixclk(state);
5701 int req_cdclk;
5702
5703 /* The only reason this can fail is if we fail to add the crtc_state
5704 * to the atomic state. But that can't happen since the call to
5705 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5706 * can't have failed otherwise the mode set would be aborted) added all
5707 * the states already. */
5708 if (WARN_ON(max_pixclk < 0))
5709 return;
5710
5711 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5712
164dfd28 5713 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5714 /*
5715 * FIXME: We can end up here with all power domains off, yet
5716 * with a CDCLK frequency other than the minimum. To account
5717 * for this take the PIPE-A power domain, which covers the HW
5718 * blocks needed for the following programming. This can be
5719 * removed once it's guaranteed that we get here either with
5720 * the minimum CDCLK set, or the required power domains
5721 * enabled.
5722 */
5723 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5724
383c5a6a
VS		 5725 if (IS_CHERRYVIEW(dev))
5726 cherryview_set_cdclk(dev, req_cdclk);
5727 else
5728 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5729
1e69cd74
VS		 5730 vlv_program_pfi_credits(dev_priv);
5731
738c05c0 5732 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5733 }
30a970c6
JB		 5734}
5735
89b667f8
JB		 5736static void valleyview_crtc_enable(struct drm_crtc *crtc)
5737{
5738 struct drm_device *dev = crtc->dev;
a72e4c9f 5739 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5741 struct intel_encoder *encoder;
5742 int pipe = intel_crtc->pipe;
23538ef1 5743 bool is_dsi;
89b667f8 5744
83d65738 5745 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5746
5747 if (intel_crtc->active)
5748 return;
5749
409ee761 5750 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5751
1ae0d137
VS		 5752 if (!is_dsi) {
5753 if (IS_CHERRYVIEW(dev))
6e3c9717 5754 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5755 else
6e3c9717 5756 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5757 }
5b18e57c 5758
6e3c9717 5759 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5760 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5761
5762 intel_set_pipe_timings(intel_crtc);
5763
c14b0485
VS		 5764 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766
5767 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5768 I915_WRITE(CHV_CANVAS(pipe), 0);
5769 }
5770
5b18e57c
DV		 5771 i9xx_set_pipeconf(intel_crtc);
5772
89b667f8 5773 intel_crtc->active = true;
89b667f8 5774
a72e4c9f 5775 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5776
89b667f8
JB		 5777 for_each_encoder_on_crtc(dev, crtc, encoder)
5778 if (encoder->pre_pll_enable)
5779 encoder->pre_pll_enable(encoder);
5780
9d556c99
CML		 5781 if (!is_dsi) {
5782 if (IS_CHERRYVIEW(dev))
6e3c9717 5783 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5784 else
6e3c9717 5785 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5786 }
89b667f8
JB		 5787
5788 for_each_encoder_on_crtc(dev, crtc, encoder)
5789 if (encoder->pre_enable)
5790 encoder->pre_enable(encoder);
5791
2dd24552
JB		 5792 i9xx_pfit_enable(intel_crtc);
5793
63cbb074
VS		 5794 intel_crtc_load_lut(crtc);
5795
f37fcc2a 5796 intel_update_watermarks(crtc);
e1fdc473 5797 intel_enable_pipe(intel_crtc);
be6a6f8e 5798
4b3a9526
VS		 5799 assert_vblank_disabled(crtc);
5800 drm_crtc_vblank_on(crtc);
5801
f9b61ff6
DV		 5802 for_each_encoder_on_crtc(dev, crtc, encoder)
5803 encoder->enable(encoder);
5804
9ab0460b 5805 intel_crtc_enable_planes(crtc);
d40d9187 5806
56b80e1f 5807 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5808 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5809}
5810
f13c2ef3
DV		 5811static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5812{
5813 struct drm_device *dev = crtc->base.dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815
6e3c9717
ACO		 5816 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5817 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5818}
5819
0b8765c6 5820static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5821{
5822 struct drm_device *dev = crtc->dev;
a72e4c9f 5823 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5825 struct intel_encoder *encoder;
79e53945 5826 int pipe = intel_crtc->pipe;
79e53945 5827
83d65738 5828 WARN_ON(!crtc->state->enable);
08a48469 5829
f7abfe8b
CW		 5830 if (intel_crtc->active)
5831 return;
5832
f13c2ef3
DV		 5833 i9xx_set_pll_dividers(intel_crtc);
5834
6e3c9717 5835 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5836 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5837
5838 intel_set_pipe_timings(intel_crtc);
5839
5b18e57c
DV		 5840 i9xx_set_pipeconf(intel_crtc);
5841
f7abfe8b 5842 intel_crtc->active = true;
6b383a7f 5843
4a3436e8 5844 if (!IS_GEN2(dev))
a72e4c9f 5845 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5846
9d6d9f19
MK		 5847 for_each_encoder_on_crtc(dev, crtc, encoder)
5848 if (encoder->pre_enable)
5849 encoder->pre_enable(encoder);
5850
f6736a1a
DV		 5851 i9xx_enable_pll(intel_crtc);
5852
2dd24552
JB		 5853 i9xx_pfit_enable(intel_crtc);
5854
63cbb074
VS		 5855 intel_crtc_load_lut(crtc);
5856
f37fcc2a 5857 intel_update_watermarks(crtc);
e1fdc473 5858 intel_enable_pipe(intel_crtc);
be6a6f8e 5859
4b3a9526
VS		 5860 assert_vblank_disabled(crtc);
5861 drm_crtc_vblank_on(crtc);
5862
f9b61ff6
DV		 5863 for_each_encoder_on_crtc(dev, crtc, encoder)
5864 encoder->enable(encoder);
5865
9ab0460b 5866 intel_crtc_enable_planes(crtc);
d40d9187 5867
4a3436e8
VS		 5868 /*
5869 * Gen2 reports pipe underruns whenever all planes are disabled.
5870 * So don't enable underrun reporting before at least some planes
5871 * are enabled.
5872 * FIXME: Need to fix the logic to work when we turn off all planes
5873 * but leave the pipe running.
5874 */
5875 if (IS_GEN2(dev))
a72e4c9f 5876 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5877
56b80e1f 5878 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5879 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5880}
79e53945 5881
87476d63
DV		 5882static void i9xx_pfit_disable(struct intel_crtc *crtc)
5883{
5884 struct drm_device *dev = crtc->base.dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5886
6e3c9717 5887 if (!crtc->config->gmch_pfit.control)
328d8e82 5888 return;
87476d63 5889
328d8e82 5890 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5891
328d8e82
DV		 5892 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5893 I915_READ(PFIT_CONTROL));
5894 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5895}
5896
0b8765c6
JB		 5897static void i9xx_crtc_disable(struct drm_crtc *crtc)
5898{
5899 struct drm_device *dev = crtc->dev;
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5902 struct intel_encoder *encoder;
0b8765c6 5903 int pipe = intel_crtc->pipe;
ef9c3aee 5904
f7abfe8b
CW		 5905 if (!intel_crtc->active)
5906 return;
5907
4a3436e8
VS		 5908 /*
5909 * Gen2 reports pipe underruns whenever all planes are disabled.
5910 * So diasble underrun reporting before all the planes get disabled.
5911 * FIXME: Need to fix the logic to work when we turn off all planes
5912 * but leave the pipe running.
5913 */
5914 if (IS_GEN2(dev))
a72e4c9f 5915 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5916
564ed191
ID		 5917 /*
5918 * Vblank time updates from the shadow to live plane control register
5919 * are blocked if the memory self-refresh mode is active at that
5920 * moment. So to make sure the plane gets truly disabled, disable
5921 * first the self-refresh mode. The self-refresh enable bit in turn
5922 * will be checked/applied by the HW only at the next frame start
5923 * event which is after the vblank start event, so we need to have a
5924 * wait-for-vblank between disabling the plane and the pipe.
5925 */
5926 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5927 intel_crtc_disable_planes(crtc);
5928
6304cd91
VS		 5929 /*
5930 * On gen2 planes are double buffered but the pipe isn't, so we must
5931 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5932 * We also need to wait on all gmch platforms because of the
5933 * self-refresh mode constraint explained above.
6304cd91 5934 */
564ed191 5935 intel_wait_for_vblank(dev, pipe);
6304cd91 5936
4b3a9526
VS		 5937 for_each_encoder_on_crtc(dev, crtc, encoder)
5938 encoder->disable(encoder);
5939
f9b61ff6
DV		 5940 drm_crtc_vblank_off(crtc);
5941 assert_vblank_disabled(crtc);
5942
575f7ab7 5943 intel_disable_pipe(intel_crtc);
24a1f16d 5944
87476d63 5945 i9xx_pfit_disable(intel_crtc);
24a1f16d 5946
89b667f8
JB		 5947 for_each_encoder_on_crtc(dev, crtc, encoder)
5948 if (encoder->post_disable)
5949 encoder->post_disable(encoder);
5950
409ee761 5951 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5952 if (IS_CHERRYVIEW(dev))
5953 chv_disable_pll(dev_priv, pipe);
5954 else if (IS_VALLEYVIEW(dev))
5955 vlv_disable_pll(dev_priv, pipe);
5956 else
1c4e0274 5957 i9xx_disable_pll(intel_crtc);
076ed3b2 5958 }
0b8765c6 5959
4a3436e8 5960 if (!IS_GEN2(dev))
a72e4c9f 5961 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5962
f7abfe8b 5963 intel_crtc->active = false;
46ba614c 5964 intel_update_watermarks(crtc);
f37fcc2a 5965
efa9624e 5966 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5967 intel_fbc_update(dev);
efa9624e 5968 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5969}
5970
ee7b9f93
JB		 5971static void i9xx_crtc_off(struct drm_crtc *crtc)
5972{
5973}
5974
b04c5bd6
BF		 5975/* Master function to enable/disable CRTC and corresponding power wells */
5976void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5977{
5978 struct drm_device *dev = crtc->dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5981 enum intel_display_power_domain domain;
5982 unsigned long domains;
976f8a20 5983
0e572fe7
DV		 5984 if (enable) {
5985 if (!intel_crtc->active) {
e1e9fb84
DV		 5986 domains = get_crtc_power_domains(crtc);
5987 for_each_power_domain(domain, domains)
5988 intel_display_power_get(dev_priv, domain);
5989 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5990
5991 dev_priv->display.crtc_enable(crtc);
5992 }
5993 } else {
5994 if (intel_crtc->active) {
5995 dev_priv->display.crtc_disable(crtc);
5996
e1e9fb84
DV		 5997 domains = intel_crtc->enabled_power_domains;
5998 for_each_power_domain(domain, domains)
5999 intel_display_power_put(dev_priv, domain);
6000 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6001 }
6002 }
b04c5bd6
BF		 6003}
6004
6005/**
6006 * Sets the power management mode of the pipe and plane.
6007 */
6008void intel_crtc_update_dpms(struct drm_crtc *crtc)
6009{
6010 struct drm_device *dev = crtc->dev;
6011 struct intel_encoder *intel_encoder;
6012 bool enable = false;
6013
6014 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6015 enable |= intel_encoder->connectors_active;
6016
6017 intel_crtc_control(crtc, enable);
976f8a20
DV		 6018}
6019
cdd59983
CW		 6020static void intel_crtc_disable(struct drm_crtc *crtc)
6021{
cdd59983 6022 struct drm_device *dev = crtc->dev;
976f8a20 6023 struct drm_connector *connector;
ee7b9f93 6024 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6025
976f8a20 6026 /* crtc should still be enabled when we disable it. */
83d65738 6027 WARN_ON(!crtc->state->enable);
976f8a20
DV		 6028
6029 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6030 dev_priv->display.off(crtc);
6031
70a101f8 6032 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6033
6034 /* Update computed state. */
6035 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6036 if (!connector->encoder || !connector->encoder->crtc)
6037 continue;
6038
6039 if (connector->encoder->crtc != crtc)
6040 continue;
6041
6042 connector->dpms = DRM_MODE_DPMS_OFF;
6043 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6044 }
6045}
6046
ea5b213a 6047void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6048{
4ef69c7a 6049 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6050
ea5b213a
CW		 6051 drm_encoder_cleanup(encoder);
6052 kfree(intel_encoder);
7e7d76c3
JB		 6053}
6054
9237329d 6055/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6056 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6057 * state of the entire output pipe. */
9237329d 6058static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6059{
5ab432ef
DV		 6060 if (mode == DRM_MODE_DPMS_ON) {
6061 encoder->connectors_active = true;
6062
b2cabb0e 6063 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6064 } else {
6065 encoder->connectors_active = false;
6066
b2cabb0e 6067 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6068 }
79e53945
JB		 6069}
6070
0a91ca29
DV		 6071/* Cross check the actual hw state with our own modeset state tracking (and it's
6072 * internal consistency). */
b980514c 6073static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6074{
0a91ca29
DV		 6075 if (connector->get_hw_state(connector)) {
6076 struct intel_encoder *encoder = connector->encoder;
6077 struct drm_crtc *crtc;
6078 bool encoder_enabled;
6079 enum pipe pipe;
6080
6081 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6082 connector->base.base.id,
c23cc417 6083 connector->base.name);
0a91ca29 6084
0e32b39c
DA		 6085 /* there is no real hw state for MST connectors */
6086 if (connector->mst_port)
6087 return;
6088
e2c719b7 6089 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6090 "wrong connector dpms state\n");
e2c719b7 6091 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6092 "active connector not linked to encoder\n");
0a91ca29 6093
36cd7444 6094 if (encoder) {
e2c719b7 6095 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6096 "encoder->connectors_active not set\n");
6097
6098 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6099 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6100 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6101 return;
0a91ca29 6102
36cd7444 6103 crtc = encoder->base.crtc;
0a91ca29 6104
83d65738
MR		 6105 I915_STATE_WARN(!crtc->state->enable,
6106 "crtc not enabled\n");
e2c719b7
RC		 6107 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6108 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6109 "encoder active on the wrong pipe\n");
6110 }
0a91ca29 6111 }
79e53945
JB		 6112}
6113
9bdbd0b9
ACO		 6114int intel_connector_init(struct intel_connector *connector)
6115{
6116 struct drm_connector_state *connector_state;
6117
6118 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6119 if (!connector_state)
6120 return -ENOMEM;
6121
6122 connector->base.state = connector_state;
6123 return 0;
6124}
6125
6126struct intel_connector *intel_connector_alloc(void)
6127{
6128 struct intel_connector *connector;
6129
6130 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6131 if (!connector)
6132 return NULL;
6133
6134 if (intel_connector_init(connector) < 0) {
6135 kfree(connector);
6136 return NULL;
6137 }
6138
6139 return connector;
6140}
6141
5ab432ef
DV		 6142/* Even simpler default implementation, if there's really no special case to
6143 * consider. */
6144void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6145{
5ab432ef
DV		 6146 /* All the simple cases only support two dpms states. */
6147 if (mode != DRM_MODE_DPMS_ON)
6148 mode = DRM_MODE_DPMS_OFF;
d4270e57 6149
5ab432ef
DV		 6150 if (mode == connector->dpms)
6151 return;
6152
6153 connector->dpms = mode;
6154
6155 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6156 if (connector->encoder)
6157 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6158
b980514c 6159 intel_modeset_check_state(connector->dev);
79e53945
JB		 6160}
6161
f0947c37
DV		 6162/* Simple connector->get_hw_state implementation for encoders that support only
6163 * one connector and no cloning and hence the encoder state determines the state
6164 * of the connector. */
6165bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6166{
24929352 6167 enum pipe pipe = 0;
f0947c37 6168 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6169
f0947c37 6170 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6171}
6172
6d293983 6173static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6174{
6d293983
ACO		 6175 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6176 return crtc_state->fdi_lanes;
d272ddfa
VS		 6177
6178 return 0;
6179}
6180
6d293983 6181static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6182 struct intel_crtc_state *pipe_config)
1857e1da 6183{
6d293983
ACO		 6184 struct drm_atomic_state *state = pipe_config->base.state;
6185 struct intel_crtc *other_crtc;
6186 struct intel_crtc_state *other_crtc_state;
6187
1857e1da
DV		 6188 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6189 pipe_name(pipe), pipe_config->fdi_lanes);
6190 if (pipe_config->fdi_lanes > 4) {
6191 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6192 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6193 return -EINVAL;
1857e1da
DV		 6194 }
6195
bafb6553 6196 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6197 if (pipe_config->fdi_lanes > 2) {
6198 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6199 pipe_config->fdi_lanes);
6d293983 6200 return -EINVAL;
1857e1da 6201 } else {
6d293983 6202 return 0;
1857e1da
DV		 6203 }
6204 }
6205
6206 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6207 return 0;
1857e1da
DV		 6208
6209 /* Ivybridge 3 pipe is really complicated */
6210 switch (pipe) {
6211 case PIPE_A:
6d293983 6212 return 0;
1857e1da 6213 case PIPE_B:
6d293983
ACO		 6214 if (pipe_config->fdi_lanes <= 2)
6215 return 0;
6216
6217 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6218 other_crtc_state =
6219 intel_atomic_get_crtc_state(state, other_crtc);
6220 if (IS_ERR(other_crtc_state))
6221 return PTR_ERR(other_crtc_state);
6222
6223 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6224 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6225 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6226 return -EINVAL;
1857e1da 6227 }
6d293983 6228 return 0;
1857e1da 6229 case PIPE_C:
251cc67c
VS		 6230 if (pipe_config->fdi_lanes > 2) {
6231 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6232 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6233 return -EINVAL;
251cc67c 6234 }
6d293983
ACO		 6235
6236 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6237 other_crtc_state =
6238 intel_atomic_get_crtc_state(state, other_crtc);
6239 if (IS_ERR(other_crtc_state))
6240 return PTR_ERR(other_crtc_state);
6241
6242 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6243 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6244 return -EINVAL;
1857e1da 6245 }
6d293983 6246 return 0;
1857e1da
DV		 6247 default:
6248 BUG();
6249 }
6250}
6251
e29c22c0
DV		 6252#define RETRY 1
6253static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6254 struct intel_crtc_state *pipe_config)
877d48d5 6255{
1857e1da 6256 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6257 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6258 int lane, link_bw, fdi_dotclock, ret;
6259 bool needs_recompute = false;
877d48d5 6260
e29c22c0 6261retry:
877d48d5
DV		 6262 /* FDI is a binary signal running at ~2.7GHz, encoding
6263 * each output octet as 10 bits. The actual frequency
6264 * is stored as a divider into a 100MHz clock, and the
6265 * mode pixel clock is stored in units of 1KHz.
6266 * Hence the bw of each lane in terms of the mode signal
6267 * is:
6268 */
6269 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6270
241bfc38 6271 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6272
2bd89a07 6273 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6274 pipe_config->pipe_bpp);
6275
6276 pipe_config->fdi_lanes = lane;
6277
2bd89a07 6278 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6279 link_bw, &pipe_config->fdi_m_n);
1857e1da 6280
6d293983
ACO		 6281 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6282 intel_crtc->pipe, pipe_config);
6283 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6284 pipe_config->pipe_bpp -= 2*3;
6285 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6286 pipe_config->pipe_bpp);
6287 needs_recompute = true;
6288 pipe_config->bw_constrained = true;
6289
6290 goto retry;
6291 }
6292
6293 if (needs_recompute)
6294 return RETRY;
6295
6d293983 6296 return ret;
877d48d5
DV		 6297}
6298
42db64ef 6299static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6300 struct intel_crtc_state *pipe_config)
42db64ef 6301{
d330a953 6302 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6303 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6304 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6305}
6306
a43f6e0f 6307static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6308 struct intel_crtc_state *pipe_config)
79e53945 6309{
a43f6e0f 6310 struct drm_device *dev = crtc->base.dev;
8bd31e67 6311 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6312 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6313 int ret;
89749350 6314
ad3a4479 6315 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6316 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6317 int clock_limit =
6318 dev_priv->display.get_display_clock_speed(dev);
6319
6320 /*
6321 * Enable pixel doubling when the dot clock
6322 * is > 90% of the (display) core speed.
6323 *
b397c96b
VS		 6324 * GDG double wide on either pipe,
6325 * otherwise pipe A only.
cf532bb2 6326 */
b397c96b 6327 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6328 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6329 clock_limit *= 2;
cf532bb2 6330 pipe_config->double_wide = true;
ad3a4479
VS		 6331 }
6332
241bfc38 6333 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6334 return -EINVAL;
2c07245f 6335 }
89749350 6336
1d1d0e27
VS		 6337 /*
6338 * Pipe horizontal size must be even in:
6339 * - DVO ganged mode
6340 * - LVDS dual channel mode
6341 * - Double wide pipe
6342 */
a93e255f 6343 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6344 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6345 pipe_config->pipe_src_w &= ~1;
6346
8693a824
DL		 6347 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6348 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6349 */
6350 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6351 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6352 return -EINVAL;
44f46b42 6353
f5adf94e 6354 if (HAS_IPS(dev))
a43f6e0f
DV		 6355 hsw_compute_ips_config(crtc, pipe_config);
6356
877d48d5 6357 if (pipe_config->has_pch_encoder)
a43f6e0f 6358 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6359
d03c93d4
CK		 6360 /* FIXME: remove below call once atomic mode set is place and all crtc
6361 * related checks called from atomic_crtc_check function */
6362 ret = 0;
6363 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6364 crtc, pipe_config->base.state);
6365 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6366
6367 return ret;
79e53945
JB		 6368}
6369
1652d19e
VS		 6370static int skylake_get_display_clock_speed(struct drm_device *dev)
6371{
6372 struct drm_i915_private *dev_priv = to_i915(dev);
6373 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6374 uint32_t cdctl = I915_READ(CDCLK_CTL);
6375 uint32_t linkrate;
6376
6377 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6378 WARN(1, "LCPLL1 not enabled\n");
6379 return 24000; /* 24MHz is the cd freq with NSSC ref */
6380 }
6381
6382 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6383 return 540000;
6384
6385 linkrate = (I915_READ(DPLL_CTRL1) &
6386 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6387
6388 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
6389 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
6390 /* vco 8640 */
6391 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6392 case CDCLK_FREQ_450_432:
6393 return 432000;
6394 case CDCLK_FREQ_337_308:
6395 return 308570;
6396 case CDCLK_FREQ_675_617:
6397 return 617140;
6398 default:
6399 WARN(1, "Unknown cd freq selection\n");
6400 }
6401 } else {
6402 /* vco 8100 */
6403 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6404 case CDCLK_FREQ_450_432:
6405 return 450000;
6406 case CDCLK_FREQ_337_308:
6407 return 337500;
6408 case CDCLK_FREQ_675_617:
6409 return 675000;
6410 default:
6411 WARN(1, "Unknown cd freq selection\n");
6412 }
6413 }
6414
6415 /* error case, do as if DPLL0 isn't enabled */
6416 return 24000;
6417}
6418
6419static int broadwell_get_display_clock_speed(struct drm_device *dev)
6420{
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 uint32_t lcpll = I915_READ(LCPLL_CTL);
6423 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6424
6425 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6426 return 800000;
6427 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6428 return 450000;
6429 else if (freq == LCPLL_CLK_FREQ_450)
6430 return 450000;
6431 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6432 return 540000;
6433 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6434 return 337500;
6435 else
6436 return 675000;
6437}
6438
6439static int haswell_get_display_clock_speed(struct drm_device *dev)
6440{
6441 struct drm_i915_private *dev_priv = dev->dev_private;
6442 uint32_t lcpll = I915_READ(LCPLL_CTL);
6443 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6444
6445 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6446 return 800000;
6447 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6448 return 450000;
6449 else if (freq == LCPLL_CLK_FREQ_450)
6450 return 450000;
6451 else if (IS_HSW_ULT(dev))
6452 return 337500;
6453 else
6454 return 540000;
6455}
6456
25eb05fc
JB		 6457static int valleyview_get_display_clock_speed(struct drm_device *dev)
6458{
d197b7d3 6459 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6460 u32 val;
6461 int divider;
6462
6bcda4f0
VS		 6463 if (dev_priv->hpll_freq == 0)
6464 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6465
d197b7d3
VS		 6466 mutex_lock(&dev_priv->dpio_lock);
6467 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6468 mutex_unlock(&dev_priv->dpio_lock);
6469
6470 divider = val & DISPLAY_FREQUENCY_VALUES;
6471
7d007f40
VS		 6472 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6473 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6474 "cdclk change in progress\n");
6475
6bcda4f0 6476 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6477}
6478
b37a6434
VS		 6479static int ilk_get_display_clock_speed(struct drm_device *dev)
6480{
6481 return 450000;
6482}
6483
e70236a8
JB		 6484static int i945_get_display_clock_speed(struct drm_device *dev)
6485{
6486 return 400000;
6487}
79e53945 6488
e70236a8 6489static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6490{
e907f170 6491 return 333333;
e70236a8 6492}
79e53945 6493
e70236a8
JB		 6494static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6495{
6496 return 200000;
6497}
79e53945 6498
257a7ffc
DV		 6499static int pnv_get_display_clock_speed(struct drm_device *dev)
6500{
6501 u16 gcfgc = 0;
6502
6503 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6504
6505 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6506 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6507 return 266667;
257a7ffc 6508 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6509 return 333333;
257a7ffc 6510 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6511 return 444444;
257a7ffc
DV		 6512 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6513 return 200000;
6514 default:
6515 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6516 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6517 return 133333;
257a7ffc 6518 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6519 return 166667;
257a7ffc
DV		 6520 }
6521}
6522
e70236a8
JB		 6523static int i915gm_get_display_clock_speed(struct drm_device *dev)
6524{
6525 u16 gcfgc = 0;
79e53945 6526
e70236a8
JB		 6527 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6528
6529 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6530 return 133333;
e70236a8
JB		 6531 else {
6532 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6533 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6534 return 333333;
e70236a8
JB		 6535 default:
6536 case GC_DISPLAY_CLOCK_190_200_MHZ:
6537 return 190000;
79e53945 6538 }
e70236a8
JB		 6539 }
6540}
6541
6542static int i865_get_display_clock_speed(struct drm_device *dev)
6543{
e907f170 6544 return 266667;
e70236a8
JB		 6545}
6546
6547static int i855_get_display_clock_speed(struct drm_device *dev)
6548{
6549 u16 hpllcc = 0;
6550 /* Assume that the hardware is in the high speed state. This
6551 * should be the default.
6552 */
6553 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6554 case GC_CLOCK_133_200:
6555 case GC_CLOCK_100_200:
6556 return 200000;
6557 case GC_CLOCK_166_250:
6558 return 250000;
6559 case GC_CLOCK_100_133:
e907f170 6560 return 133333;
e70236a8 6561 }
79e53945 6562
e70236a8
JB		 6563 /* Shouldn't happen */
6564 return 0;
6565}
79e53945 6566
e70236a8
JB		 6567static int i830_get_display_clock_speed(struct drm_device *dev)
6568{
e907f170 6569 return 133333;
79e53945
JB		 6570}
6571
2c07245f 6572static void
a65851af 6573intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6574{
a65851af
VS		 6575 while (*num > DATA_LINK_M_N_MASK ||
6576 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6577 *num >>= 1;
6578 *den >>= 1;
6579 }
6580}
6581
a65851af
VS		 6582static void compute_m_n(unsigned int m, unsigned int n,
6583 uint32_t *ret_m, uint32_t *ret_n)
6584{
6585 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6586 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6587 intel_reduce_m_n_ratio(ret_m, ret_n);
6588}
6589
e69d0bc1
DV		 6590void
6591intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6592 int pixel_clock, int link_clock,
6593 struct intel_link_m_n *m_n)
2c07245f 6594{
e69d0bc1 6595 m_n->tu = 64;
a65851af
VS		 6596
6597 compute_m_n(bits_per_pixel * pixel_clock,
6598 link_clock * nlanes * 8,
6599 &m_n->gmch_m, &m_n->gmch_n);
6600
6601 compute_m_n(pixel_clock, link_clock,
6602 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6603}
6604
a7615030
CW		 6605static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6606{
d330a953
JN		 6607 if (i915.panel_use_ssc >= 0)
6608 return i915.panel_use_ssc != 0;
41aa3448 6609 return dev_priv->vbt.lvds_use_ssc
435793df 6610 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6611}
6612
a93e255f
ACO		 6613static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6614 int num_connectors)
c65d77d8 6615{
a93e255f 6616 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6617 struct drm_i915_private *dev_priv = dev->dev_private;
6618 int refclk;
6619
a93e255f
ACO		 6620 WARN_ON(!crtc_state->base.state);
6621
5ab7b0b7 6622 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6623 refclk = 100000;
a93e255f 6624 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6625 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6626 refclk = dev_priv->vbt.lvds_ssc_freq;
6627 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6628 } else if (!IS_GEN2(dev)) {
6629 refclk = 96000;
6630 } else {
6631 refclk = 48000;
6632 }
6633
6634 return refclk;
6635}
6636
7429e9d4 6637static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6638{
7df00d7a 6639 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6640}
f47709a9 6641
7429e9d4
DV		 6642static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6643{
6644 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6645}
6646
f47709a9 6647static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6648 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6649 intel_clock_t *reduced_clock)
6650{
f47709a9 6651 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6652 u32 fp, fp2 = 0;
6653
6654 if (IS_PINEVIEW(dev)) {
190f68c5 6655 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6656 if (reduced_clock)
7429e9d4 6657 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6658 } else {
190f68c5 6659 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6660 if (reduced_clock)
7429e9d4 6661 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6662 }
6663
190f68c5 6664 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6665
f47709a9 6666 crtc->lowfreq_avail = false;
a93e255f 6667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6668 reduced_clock) {
190f68c5 6669 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6670 crtc->lowfreq_avail = true;
a7516a05 6671 } else {
190f68c5 6672 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6673 }
6674}
6675
5e69f97f
CML		 6676static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6677 pipe)
89b667f8
JB		 6678{
6679 u32 reg_val;
6680
6681 /*
6682 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6683 * and set it to a reasonable value instead.
6684 */
ab3c759a 6685 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6686 reg_val &= 0xffffff00;
6687 reg_val |= 0x00000030;
ab3c759a 6688 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6689
ab3c759a 6690 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6691 reg_val &= 0x8cffffff;
6692 reg_val = 0x8c000000;
ab3c759a 6693 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6694
ab3c759a 6695 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6696 reg_val &= 0xffffff00;
ab3c759a 6697 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6698
ab3c759a 6699 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6700 reg_val &= 0x00ffffff;
6701 reg_val |= 0xb0000000;
ab3c759a 6702 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6703}
6704
b551842d
DV		 6705static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6706 struct intel_link_m_n *m_n)
6707{
6708 struct drm_device *dev = crtc->base.dev;
6709 struct drm_i915_private *dev_priv = dev->dev_private;
6710 int pipe = crtc->pipe;
6711
e3b95f1e
DV		 6712 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6713 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6714 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6715 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6716}
6717
6718static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6719 struct intel_link_m_n *m_n,
6720 struct intel_link_m_n *m2_n2)
b551842d
DV		 6721{
6722 struct drm_device *dev = crtc->base.dev;
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 int pipe = crtc->pipe;
6e3c9717 6725 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6726
6727 if (INTEL_INFO(dev)->gen >= 5) {
6728 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6729 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6730 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6731 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6732 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6733 * for gen < 8) and if DRRS is supported (to make sure the
6734 * registers are not unnecessarily accessed).
6735 */
44395bfe 6736 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6737 crtc->config->has_drrs) {
f769cd24
VK		 6738 I915_WRITE(PIPE_DATA_M2(transcoder),
6739 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6740 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6741 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6742 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6743 }
b551842d 6744 } else {
e3b95f1e
DV		 6745 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6746 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6747 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6748 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6749 }
6750}
6751
fe3cd48d 6752void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6753{
fe3cd48d
R		 6754 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6755
6756 if (m_n == M1_N1) {
6757 dp_m_n = &crtc->config->dp_m_n;
6758 dp_m2_n2 = &crtc->config->dp_m2_n2;
6759 } else if (m_n == M2_N2) {
6760
6761 /*
6762 * M2_N2 registers are not supported. Hence m2_n2 divider value
6763 * needs to be programmed into M1_N1.
6764 */
6765 dp_m_n = &crtc->config->dp_m2_n2;
6766 } else {
6767 DRM_ERROR("Unsupported divider value\n");
6768 return;
6769 }
6770
6e3c9717
ACO		 6771 if (crtc->config->has_pch_encoder)
6772 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6773 else
fe3cd48d 6774 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6775}
6776
d288f65f 6777static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6778 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6779{
6780 u32 dpll, dpll_md;
6781
6782 /*
6783 * Enable DPIO clock input. We should never disable the reference
6784 * clock for pipe B, since VGA hotplug / manual detection depends
6785 * on it.
6786 */
6787 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6788 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6789 /* We should never disable this, set it here for state tracking */
6790 if (crtc->pipe == PIPE_B)
6791 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6792 dpll |= DPLL_VCO_ENABLE;
d288f65f 6793 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6794
d288f65f 6795 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6796 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6797 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6798}
6799
d288f65f 6800static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6801 const struct intel_crtc_state *pipe_config)
a0c4da24 6802{
f47709a9 6803 struct drm_device *dev = crtc->base.dev;
a0c4da24 6804 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6805 int pipe = crtc->pipe;
bdd4b6a6 6806 u32 mdiv;
a0c4da24 6807 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6808 u32 coreclk, reg_val;
a0c4da24 6809
09153000
DV		 6810 mutex_lock(&dev_priv->dpio_lock);
6811
d288f65f
VS		 6812 bestn = pipe_config->dpll.n;
6813 bestm1 = pipe_config->dpll.m1;
6814 bestm2 = pipe_config->dpll.m2;
6815 bestp1 = pipe_config->dpll.p1;
6816 bestp2 = pipe_config->dpll.p2;
a0c4da24 6817
89b667f8
JB		 6818 /* See eDP HDMI DPIO driver vbios notes doc */
6819
6820 /* PLL B needs special handling */
bdd4b6a6 6821 if (pipe == PIPE_B)
5e69f97f 6822 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6823
6824 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6825 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6826
6827 /* Disable target IRef on PLL */
ab3c759a 6828 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6829 reg_val &= 0x00ffffff;
ab3c759a 6830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6831
6832 /* Disable fast lock */
ab3c759a 6833 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6834
6835 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6836 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6837 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6838 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6839 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6840
6841 /*
6842 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6843 * but we don't support that).
6844 * Note: don't use the DAC post divider as it seems unstable.
6845 */
6846 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6847 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6848
a0c4da24 6849 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6850 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6851
89b667f8 6852 /* Set HBR and RBR LPF coefficients */
d288f65f 6853 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6854 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6855 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6856 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6857 0x009f0003);
89b667f8 6858 else
ab3c759a 6859 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6860 0x00d0000f);
6861
681a8504 6862 if (pipe_config->has_dp_encoder) {
89b667f8 6863 /* Use SSC source */
bdd4b6a6 6864 if (pipe == PIPE_A)
ab3c759a 6865 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6866 0x0df40000);
6867 else
ab3c759a 6868 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6869 0x0df70000);
6870 } else { /* HDMI or VGA */
6871 /* Use bend source */
bdd4b6a6 6872 if (pipe == PIPE_A)
ab3c759a 6873 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6874 0x0df70000);
6875 else
ab3c759a 6876 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6877 0x0df40000);
6878 }
a0c4da24 6879
ab3c759a 6880 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6881 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6882 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6883 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6884 coreclk |= 0x01000000;
ab3c759a 6885 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6886
ab3c759a 6887 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6888 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6889}
6890
d288f65f 6891static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6892 struct intel_crtc_state *pipe_config)
1ae0d137 6893{
d288f65f 6894 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6895 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6896 DPLL_VCO_ENABLE;
6897 if (crtc->pipe != PIPE_A)
d288f65f 6898 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6899
d288f65f
VS		 6900 pipe_config->dpll_hw_state.dpll_md =
6901 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6902}
6903
d288f65f 6904static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6905 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6906{
6907 struct drm_device *dev = crtc->base.dev;
6908 struct drm_i915_private *dev_priv = dev->dev_private;
6909 int pipe = crtc->pipe;
6910 int dpll_reg = DPLL(crtc->pipe);
6911 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6912 u32 loopfilter, tribuf_calcntr;
9d556c99 6913 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6914 u32 dpio_val;
9cbe40c1 6915 int vco;
9d556c99 6916
d288f65f
VS		 6917 bestn = pipe_config->dpll.n;
6918 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6919 bestm1 = pipe_config->dpll.m1;
6920 bestm2 = pipe_config->dpll.m2 >> 22;
6921 bestp1 = pipe_config->dpll.p1;
6922 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6923 vco = pipe_config->dpll.vco;
a945ce7e 6924 dpio_val = 0;
9cbe40c1 6925 loopfilter = 0;
9d556c99
CML		 6926
6927 /*
6928 * Enable Refclk and SSC
6929 */
a11b0703 6930 I915_WRITE(dpll_reg,
d288f65f 6931 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6932
6933 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6934
9d556c99
CML		 6935 /* p1 and p2 divider */
6936 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6937 5 << DPIO_CHV_S1_DIV_SHIFT |
6938 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6939 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6940 1 << DPIO_CHV_K_DIV_SHIFT);
6941
6942 /* Feedback post-divider - m2 */
6943 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6944
6945 /* Feedback refclk divider - n and m1 */
6946 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6947 DPIO_CHV_M1_DIV_BY_2 |
6948 1 << DPIO_CHV_N_DIV_SHIFT);
6949
6950 /* M2 fraction division */
a945ce7e
VP		 6951 if (bestm2_frac)
6952 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6953
6954 /* M2 fraction division enable */
a945ce7e
VP		 6955 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6956 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6957 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6958 if (bestm2_frac)
6959 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6960 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6961
de3a0fde
VP		 6962 /* Program digital lock detect threshold */
6963 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6964 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6965 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6966 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6967 if (!bestm2_frac)
6968 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6969 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6970
9d556c99 6971 /* Loop filter */
9cbe40c1
VP		 6972 if (vco == 5400000) {
6973 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6974 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6975 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6976 tribuf_calcntr = 0x9;
6977 } else if (vco <= 6200000) {
6978 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6979 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6980 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6981 tribuf_calcntr = 0x9;
6982 } else if (vco <= 6480000) {
6983 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6984 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6985 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6986 tribuf_calcntr = 0x8;
6987 } else {
6988 /* Not supported. Apply the same limits as in the max case */
6989 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6990 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6991 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6992 tribuf_calcntr = 0;
6993 }
9d556c99
CML		 6994 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6995
968040b2 6996 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6997 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6998 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6999 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7000
9d556c99
CML		 7001 /* AFC Recal */
7002 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7003 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7004 DPIO_AFC_RECAL);
7005
7006 mutex_unlock(&dev_priv->dpio_lock);
7007}
7008
d288f65f
VS		 7009/**
7010 * vlv_force_pll_on - forcibly enable just the PLL
7011 * @dev_priv: i915 private structure
7012 * @pipe: pipe PLL to enable
7013 * @dpll: PLL configuration
7014 *
7015 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7016 * in cases where we need the PLL enabled even when @pipe is not going to
7017 * be enabled.
7018 */
7019void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7020 const struct dpll *dpll)
7021{
7022 struct intel_crtc *crtc =
7023 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7024 struct intel_crtc_state pipe_config = {
a93e255f 7025 .base.crtc = &crtc->base,
d288f65f
VS		 7026 .pixel_multiplier = 1,
7027 .dpll = *dpll,
7028 };
7029
7030 if (IS_CHERRYVIEW(dev)) {
7031 chv_update_pll(crtc, &pipe_config);
7032 chv_prepare_pll(crtc, &pipe_config);
7033 chv_enable_pll(crtc, &pipe_config);
7034 } else {
7035 vlv_update_pll(crtc, &pipe_config);
7036 vlv_prepare_pll(crtc, &pipe_config);
7037 vlv_enable_pll(crtc, &pipe_config);
7038 }
7039}
7040
7041/**
7042 * vlv_force_pll_off - forcibly disable just the PLL
7043 * @dev_priv: i915 private structure
7044 * @pipe: pipe PLL to disable
7045 *
7046 * Disable the PLL for @pipe. To be used in cases where we need
7047 * the PLL enabled even when @pipe is not going to be enabled.
7048 */
7049void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7050{
7051 if (IS_CHERRYVIEW(dev))
7052 chv_disable_pll(to_i915(dev), pipe);
7053 else
7054 vlv_disable_pll(to_i915(dev), pipe);
7055}
7056
f47709a9 7057static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7058 struct intel_crtc_state *crtc_state,
f47709a9 7059 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7060 int num_connectors)
7061{
f47709a9 7062 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7063 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7064 u32 dpll;
7065 bool is_sdvo;
190f68c5 7066 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7067
190f68c5 7068 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7069
a93e255f
ACO		 7070 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7071 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7072
7073 dpll = DPLL_VGA_MODE_DIS;
7074
a93e255f 7075 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7076 dpll |= DPLLB_MODE_LVDS;
7077 else
7078 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7079
ef1b460d 7080 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7081 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7082 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7083 }
198a037f
DV		 7084
7085 if (is_sdvo)
4a33e48d 7086 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7087
190f68c5 7088 if (crtc_state->has_dp_encoder)
4a33e48d 7089 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7090
7091 /* compute bitmask from p1 value */
7092 if (IS_PINEVIEW(dev))
7093 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7094 else {
7095 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7096 if (IS_G4X(dev) && reduced_clock)
7097 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7098 }
7099 switch (clock->p2) {
7100 case 5:
7101 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7102 break;
7103 case 7:
7104 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7105 break;
7106 case 10:
7107 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7108 break;
7109 case 14:
7110 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7111 break;
7112 }
7113 if (INTEL_INFO(dev)->gen >= 4)
7114 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7115
190f68c5 7116 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7117 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7118 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7119 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7120 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7121 else
7122 dpll |= PLL_REF_INPUT_DREFCLK;
7123
7124 dpll |= DPLL_VCO_ENABLE;
190f68c5 7125 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7126
eb1cbe48 7127 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7128 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7129 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7130 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7131 }
7132}
7133
f47709a9 7134static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7135 struct intel_crtc_state *crtc_state,
f47709a9 7136 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7137 int num_connectors)
7138{
f47709a9 7139 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7140 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7141 u32 dpll;
190f68c5 7142 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7143
190f68c5 7144 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7145
eb1cbe48
DV		 7146 dpll = DPLL_VGA_MODE_DIS;
7147
a93e255f 7148 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7149 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7150 } else {
7151 if (clock->p1 == 2)
7152 dpll |= PLL_P1_DIVIDE_BY_TWO;
7153 else
7154 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7155 if (clock->p2 == 4)
7156 dpll |= PLL_P2_DIVIDE_BY_4;
7157 }
7158
a93e255f 7159 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7160 dpll |= DPLL_DVO_2X_MODE;
7161
a93e255f 7162 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7163 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7164 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7165 else
7166 dpll |= PLL_REF_INPUT_DREFCLK;
7167
7168 dpll |= DPLL_VCO_ENABLE;
190f68c5 7169 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7170}
7171
8a654f3b 7172static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7173{
7174 struct drm_device *dev = intel_crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7177 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7178 struct drm_display_mode *adjusted_mode =
6e3c9717 7179 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7180 uint32_t crtc_vtotal, crtc_vblank_end;
7181 int vsyncshift = 0;
4d8a62ea
DV		 7182
7183 /* We need to be careful not to changed the adjusted mode, for otherwise
7184 * the hw state checker will get angry at the mismatch. */
7185 crtc_vtotal = adjusted_mode->crtc_vtotal;
7186 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7187
609aeaca 7188 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7189 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7190 crtc_vtotal -= 1;
7191 crtc_vblank_end -= 1;
609aeaca 7192
409ee761 7193 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7194 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7195 else
7196 vsyncshift = adjusted_mode->crtc_hsync_start -
7197 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7198 if (vsyncshift < 0)
7199 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7200 }
7201
7202 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7203 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7204
fe2b8f9d 7205 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7206 (adjusted_mode->crtc_hdisplay - 1) |
7207 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7208 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7209 (adjusted_mode->crtc_hblank_start - 1) |
7210 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7211 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7212 (adjusted_mode->crtc_hsync_start - 1) |
7213 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7214
fe2b8f9d 7215 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7216 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7217 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7218 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7219 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7220 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7221 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7222 (adjusted_mode->crtc_vsync_start - 1) |
7223 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7224
b5e508d4
PZ		 7225 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7226 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7227 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7228 * bits. */
7229 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7230 (pipe == PIPE_B || pipe == PIPE_C))
7231 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7232
b0e77b9c
PZ		 7233 /* pipesrc controls the size that is scaled from, which should
7234 * always be the user's requested size.
7235 */
7236 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7237 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7238 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7239}
7240
1bd1bd80 7241static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7242 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7243{
7244 struct drm_device *dev = crtc->base.dev;
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7247 uint32_t tmp;
7248
7249 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7250 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7251 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7252 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7253 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7254 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7255 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7256 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7257 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7258
7259 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7260 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7261 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7262 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7263 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7264 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7265 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7266 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7267 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7268
7269 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7270 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7271 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7272 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7273 }
7274
7275 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7276 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7277 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7278
2d112de7
ACO		 7279 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7280 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7281}
7282
f6a83288 7283void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7284 struct intel_crtc_state *pipe_config)
babea61d 7285{
2d112de7
ACO		 7286 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7287 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7288 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7289 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7290
2d112de7
ACO		 7291 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7292 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7293 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7294 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7295
2d112de7 7296 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7297
2d112de7
ACO		 7298 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7299 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7300}
7301
84b046f3
DV		 7302static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7303{
7304 struct drm_device *dev = intel_crtc->base.dev;
7305 struct drm_i915_private *dev_priv = dev->dev_private;
7306 uint32_t pipeconf;
7307
9f11a9e4 7308 pipeconf = 0;
84b046f3 7309
b6b5d049
VS		 7310 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7311 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7312 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7313
6e3c9717 7314 if (intel_crtc->config->double_wide)
cf532bb2 7315 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7316
ff9ce46e
DV		 7317 /* only g4x and later have fancy bpc/dither controls */
7318 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7319 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7320 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7321 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7322 PIPECONF_DITHER_TYPE_SP;
84b046f3 7323
6e3c9717 7324 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7325 case 18:
7326 pipeconf |= PIPECONF_6BPC;
7327 break;
7328 case 24:
7329 pipeconf |= PIPECONF_8BPC;
7330 break;
7331 case 30:
7332 pipeconf |= PIPECONF_10BPC;
7333 break;
7334 default:
7335 /* Case prevented by intel_choose_pipe_bpp_dither. */
7336 BUG();
84b046f3
DV		 7337 }
7338 }
7339
7340 if (HAS_PIPE_CXSR(dev)) {
7341 if (intel_crtc->lowfreq_avail) {
7342 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7343 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7344 } else {
7345 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7346 }
7347 }
7348
6e3c9717 7349 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7350 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7351 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7352 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7353 else
7354 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7355 } else
84b046f3
DV		 7356 pipeconf |= PIPECONF_PROGRESSIVE;
7357
6e3c9717 7358 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7359 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7360
84b046f3
DV		 7361 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7362 POSTING_READ(PIPECONF(intel_crtc->pipe));
7363}
7364
190f68c5
ACO		 7365static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7366 struct intel_crtc_state *crtc_state)
79e53945 7367{
c7653199 7368 struct drm_device *dev = crtc->base.dev;
79e53945 7369 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7370 int refclk, num_connectors = 0;
652c393a 7371 intel_clock_t clock, reduced_clock;
a16af721 7372 bool ok, has_reduced_clock = false;
e9fd1c02 7373 bool is_lvds = false, is_dsi = false;
5eddb70b 7374 struct intel_encoder *encoder;
d4906093 7375 const intel_limit_t *limit;
55bb9992
ACO		 7376 struct drm_atomic_state *state = crtc_state->base.state;
7377 struct drm_connector_state *connector_state;
7378 int i;
79e53945 7379
55bb9992
ACO		 7380 for (i = 0; i < state->num_connector; i++) {
7381 if (!state->connectors[i])
d0737e1d
ACO		 7382 continue;
7383
55bb9992
ACO		 7384 connector_state = state->connector_states[i];
7385 if (connector_state->crtc != &crtc->base)
7386 continue;
7387
7388 encoder = to_intel_encoder(connector_state->best_encoder);
7389
5eddb70b 7390 switch (encoder->type) {
79e53945
JB		 7391 case INTEL_OUTPUT_LVDS:
7392 is_lvds = true;
7393 break;
e9fd1c02
JN		 7394 case INTEL_OUTPUT_DSI:
7395 is_dsi = true;
7396 break;
6847d71b
PZ		 7397 default:
7398 break;
79e53945 7399 }
43565a06 7400
c751ce4f 7401 num_connectors++;
79e53945
JB		 7402 }
7403
f2335330 7404 if (is_dsi)
5b18e57c 7405 return 0;
f2335330 7406
190f68c5 7407 if (!crtc_state->clock_set) {
a93e255f 7408 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7409
e9fd1c02
JN		 7410 /*
7411 * Returns a set of divisors for the desired target clock with
7412 * the given refclk, or FALSE. The returned values represent
7413 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7414 * 2) / p1 / p2.
7415 */
a93e255f
ACO		 7416 limit = intel_limit(crtc_state, refclk);
7417 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7418 crtc_state->port_clock,
e9fd1c02 7419 refclk, NULL, &clock);
f2335330 7420 if (!ok) {
e9fd1c02
JN		 7421 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7422 return -EINVAL;
7423 }
79e53945 7424
f2335330
JN		 7425 if (is_lvds && dev_priv->lvds_downclock_avail) {
7426 /*
7427 * Ensure we match the reduced clock's P to the target
7428 * clock. If the clocks don't match, we can't switch
7429 * the display clock by using the FP0/FP1. In such case
7430 * we will disable the LVDS downclock feature.
7431 */
7432 has_reduced_clock =
a93e255f 7433 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7434 dev_priv->lvds_downclock,
7435 refclk, &clock,
7436 &reduced_clock);
7437 }
7438 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7439 crtc_state->dpll.n = clock.n;
7440 crtc_state->dpll.m1 = clock.m1;
7441 crtc_state->dpll.m2 = clock.m2;
7442 crtc_state->dpll.p1 = clock.p1;
7443 crtc_state->dpll.p2 = clock.p2;
f47709a9 7444 }
7026d4ac 7445
e9fd1c02 7446 if (IS_GEN2(dev)) {
190f68c5 7447 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7448 has_reduced_clock ? &reduced_clock : NULL,
7449 num_connectors);
9d556c99 7450 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7451 chv_update_pll(crtc, crtc_state);
e9fd1c02 7452 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7453 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7454 } else {
190f68c5 7455 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7456 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7457 num_connectors);
e9fd1c02 7458 }
79e53945 7459
c8f7a0db 7460 return 0;
f564048e
EA		 7461}
7462
2fa2fe9a 7463static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7464 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7465{
7466 struct drm_device *dev = crtc->base.dev;
7467 struct drm_i915_private *dev_priv = dev->dev_private;
7468 uint32_t tmp;
7469
dc9e7dec
VS		 7470 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7471 return;
7472
2fa2fe9a 7473 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7474 if (!(tmp & PFIT_ENABLE))
7475 return;
2fa2fe9a 7476
06922821 7477 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7478 if (INTEL_INFO(dev)->gen < 4) {
7479 if (crtc->pipe != PIPE_B)
7480 return;
2fa2fe9a
DV		 7481 } else {
7482 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7483 return;
7484 }
7485
06922821 7486 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7487 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7488 if (INTEL_INFO(dev)->gen < 5)
7489 pipe_config->gmch_pfit.lvds_border_bits =
7490 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7491}
7492
acbec814 7493static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7494 struct intel_crtc_state *pipe_config)
acbec814
JB		 7495{
7496 struct drm_device *dev = crtc->base.dev;
7497 struct drm_i915_private *dev_priv = dev->dev_private;
7498 int pipe = pipe_config->cpu_transcoder;
7499 intel_clock_t clock;
7500 u32 mdiv;
662c6ecb 7501 int refclk = 100000;
acbec814 7502
f573de5a
SK		 7503 /* In case of MIPI DPLL will not even be used */
7504 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7505 return;
7506
acbec814 7507 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7508 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7509 mutex_unlock(&dev_priv->dpio_lock);
7510
7511 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7512 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7513 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7514 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7515 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7516
f646628b 7517 vlv_clock(refclk, &clock);
acbec814 7518
f646628b
VS		 7519 /* clock.dot is the fast clock */
7520 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7521}
7522
5724dbd1
DL		 7523static void
7524i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7525 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7526{
7527 struct drm_device *dev = crtc->base.dev;
7528 struct drm_i915_private *dev_priv = dev->dev_private;
7529 u32 val, base, offset;
7530 int pipe = crtc->pipe, plane = crtc->plane;
7531 int fourcc, pixel_format;
6761dd31 7532 unsigned int aligned_height;
b113d5ee 7533 struct drm_framebuffer *fb;
1b842c89 7534 struct intel_framebuffer *intel_fb;
1ad292b5 7535
42a7b088
DL		 7536 val = I915_READ(DSPCNTR(plane));
7537 if (!(val & DISPLAY_PLANE_ENABLE))
7538 return;
7539
d9806c9f 7540 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7541 if (!intel_fb) {
1ad292b5
JB		 7542 DRM_DEBUG_KMS("failed to alloc fb\n");
7543 return;
7544 }
7545
1b842c89
DL		 7546 fb = &intel_fb->base;
7547
18c5247e
DV		 7548 if (INTEL_INFO(dev)->gen >= 4) {
7549 if (val & DISPPLANE_TILED) {
49af449b 7550 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7551 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7552 }
7553 }
1ad292b5
JB		 7554
7555 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7556 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7557 fb->pixel_format = fourcc;
7558 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7559
7560 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7561 if (plane_config->tiling)
1ad292b5
JB		 7562 offset = I915_READ(DSPTILEOFF(plane));
7563 else
7564 offset = I915_READ(DSPLINOFF(plane));
7565 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7566 } else {
7567 base = I915_READ(DSPADDR(plane));
7568 }
7569 plane_config->base = base;
7570
7571 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7572 fb->width = ((val >> 16) & 0xfff) + 1;
7573 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7574
7575 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7576 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7577
b113d5ee 7578 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7579 fb->pixel_format,
7580 fb->modifier[0]);
1ad292b5 7581
f37b5c2b 7582 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7583
2844a921
DL		 7584 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7585 pipe_name(pipe), plane, fb->width, fb->height,
7586 fb->bits_per_pixel, base, fb->pitches[0],
7587 plane_config->size);
1ad292b5 7588
2d14030b 7589 plane_config->fb = intel_fb;
1ad292b5
JB		 7590}
7591
70b23a98 7592static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7593 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7594{
7595 struct drm_device *dev = crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7597 int pipe = pipe_config->cpu_transcoder;
7598 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7599 intel_clock_t clock;
7600 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7601 int refclk = 100000;
7602
7603 mutex_lock(&dev_priv->dpio_lock);
7604 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7605 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7606 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7607 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7608 mutex_unlock(&dev_priv->dpio_lock);
7609
7610 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7611 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7612 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7613 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7614 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7615
7616 chv_clock(refclk, &clock);
7617
7618 /* clock.dot is the fast clock */
7619 pipe_config->port_clock = clock.dot / 5;
7620}
7621
0e8ffe1b 7622static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7623 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7624{
7625 struct drm_device *dev = crtc->base.dev;
7626 struct drm_i915_private *dev_priv = dev->dev_private;
7627 uint32_t tmp;
7628
f458ebbc
DV		 7629 if (!intel_display_power_is_enabled(dev_priv,
7630 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7631 return false;
7632
e143a21c 7633 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7634 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7635
0e8ffe1b
DV		 7636 tmp = I915_READ(PIPECONF(crtc->pipe));
7637 if (!(tmp & PIPECONF_ENABLE))
7638 return false;
7639
42571aef
VS		 7640 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7641 switch (tmp & PIPECONF_BPC_MASK) {
7642 case PIPECONF_6BPC:
7643 pipe_config->pipe_bpp = 18;
7644 break;
7645 case PIPECONF_8BPC:
7646 pipe_config->pipe_bpp = 24;
7647 break;
7648 case PIPECONF_10BPC:
7649 pipe_config->pipe_bpp = 30;
7650 break;
7651 default:
7652 break;
7653 }
7654 }
7655
b5a9fa09
DV		 7656 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7657 pipe_config->limited_color_range = true;
7658
282740f7
VS		 7659 if (INTEL_INFO(dev)->gen < 4)
7660 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7661
1bd1bd80
DV		 7662 intel_get_pipe_timings(crtc, pipe_config);
7663
2fa2fe9a
DV		 7664 i9xx_get_pfit_config(crtc, pipe_config);
7665
6c49f241
DV		 7666 if (INTEL_INFO(dev)->gen >= 4) {
7667 tmp = I915_READ(DPLL_MD(crtc->pipe));
7668 pipe_config->pixel_multiplier =
7669 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7670 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7671 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7672 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7673 tmp = I915_READ(DPLL(crtc->pipe));
7674 pipe_config->pixel_multiplier =
7675 ((tmp & SDVO_MULTIPLIER_MASK)
7676 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7677 } else {
7678 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7679 * port and will be fixed up in the encoder->get_config
7680 * function. */
7681 pipe_config->pixel_multiplier = 1;
7682 }
8bcc2795
DV		 7683 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7684 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7685 /*
7686 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7687 * on 830. Filter it out here so that we don't
7688 * report errors due to that.
7689 */
7690 if (IS_I830(dev))
7691 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7692
8bcc2795
DV		 7693 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7694 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7695 } else {
7696 /* Mask out read-only status bits. */
7697 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7698 DPLL_PORTC_READY_MASK |
7699 DPLL_PORTB_READY_MASK);
8bcc2795 7700 }
6c49f241 7701
70b23a98
VS		 7702 if (IS_CHERRYVIEW(dev))
7703 chv_crtc_clock_get(crtc, pipe_config);
7704 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7705 vlv_crtc_clock_get(crtc, pipe_config);
7706 else
7707 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7708
0e8ffe1b
DV		 7709 return true;
7710}
7711
dde86e2d 7712static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7713{
7714 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7715 struct intel_encoder *encoder;
74cfd7ac 7716 u32 val, final;
13d83a67 7717 bool has_lvds = false;
199e5d79 7718 bool has_cpu_edp = false;
199e5d79 7719 bool has_panel = false;
99eb6a01
KP		 7720 bool has_ck505 = false;
7721 bool can_ssc = false;
13d83a67
JB		 7722
7723 /* We need to take the global config into account */
b2784e15 7724 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7725 switch (encoder->type) {
7726 case INTEL_OUTPUT_LVDS:
7727 has_panel = true;
7728 has_lvds = true;
7729 break;
7730 case INTEL_OUTPUT_EDP:
7731 has_panel = true;
2de6905f 7732 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7733 has_cpu_edp = true;
7734 break;
6847d71b
PZ		 7735 default:
7736 break;
13d83a67
JB		 7737 }
7738 }
7739
99eb6a01 7740 if (HAS_PCH_IBX(dev)) {
41aa3448 7741 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7742 can_ssc = has_ck505;
7743 } else {
7744 has_ck505 = false;
7745 can_ssc = true;
7746 }
7747
2de6905f
ID		 7748 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7749 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7750
7751 /* Ironlake: try to setup display ref clock before DPLL
7752 * enabling. This is only under driver's control after
7753 * PCH B stepping, previous chipset stepping should be
7754 * ignoring this setting.
7755 */
74cfd7ac
CW		 7756 val = I915_READ(PCH_DREF_CONTROL);
7757
7758 /* As we must carefully and slowly disable/enable each source in turn,
7759 * compute the final state we want first and check if we need to
7760 * make any changes at all.
7761 */
7762 final = val;
7763 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7764 if (has_ck505)
7765 final |= DREF_NONSPREAD_CK505_ENABLE;
7766 else
7767 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7768
7769 final &= ~DREF_SSC_SOURCE_MASK;
7770 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7771 final &= ~DREF_SSC1_ENABLE;
7772
7773 if (has_panel) {
7774 final |= DREF_SSC_SOURCE_ENABLE;
7775
7776 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7777 final |= DREF_SSC1_ENABLE;
7778
7779 if (has_cpu_edp) {
7780 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7781 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7782 else
7783 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7784 } else
7785 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7786 } else {
7787 final |= DREF_SSC_SOURCE_DISABLE;
7788 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7789 }
7790
7791 if (final == val)
7792 return;
7793
13d83a67 7794 /* Always enable nonspread source */
74cfd7ac 7795 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7796
99eb6a01 7797 if (has_ck505)
74cfd7ac 7798 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7799 else
74cfd7ac 7800 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7801
199e5d79 7802 if (has_panel) {
74cfd7ac
CW		 7803 val &= ~DREF_SSC_SOURCE_MASK;
7804 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7805
199e5d79 7806 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7807 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7808 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7809 val |= DREF_SSC1_ENABLE;
e77166b5 7810 } else
74cfd7ac 7811 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7812
7813 /* Get SSC going before enabling the outputs */
74cfd7ac 7814 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7815 POSTING_READ(PCH_DREF_CONTROL);
7816 udelay(200);
7817
74cfd7ac 7818 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7819
7820 /* Enable CPU source on CPU attached eDP */
199e5d79 7821 if (has_cpu_edp) {
99eb6a01 7822 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7823 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7824 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7825 } else
74cfd7ac 7826 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7827 } else
74cfd7ac 7828 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7829
74cfd7ac 7830 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7831 POSTING_READ(PCH_DREF_CONTROL);
7832 udelay(200);
7833 } else {
7834 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7835
74cfd7ac 7836 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7837
7838 /* Turn off CPU output */
74cfd7ac 7839 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7840
74cfd7ac 7841 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7842 POSTING_READ(PCH_DREF_CONTROL);
7843 udelay(200);
7844
7845 /* Turn off the SSC source */
74cfd7ac
CW		 7846 val &= ~DREF_SSC_SOURCE_MASK;
7847 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7848
7849 /* Turn off SSC1 */
74cfd7ac 7850 val &= ~DREF_SSC1_ENABLE;
199e5d79 7851
74cfd7ac 7852 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7853 POSTING_READ(PCH_DREF_CONTROL);
7854 udelay(200);
7855 }
74cfd7ac
CW		 7856
7857 BUG_ON(val != final);
13d83a67
JB		 7858}
7859
f31f2d55 7860static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7861{
f31f2d55 7862 uint32_t tmp;
dde86e2d 7863
0ff066a9
PZ		 7864 tmp = I915_READ(SOUTH_CHICKEN2);
7865 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7866 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7867
0ff066a9
PZ		 7868 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7869 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7870 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7871
0ff066a9
PZ		 7872 tmp = I915_READ(SOUTH_CHICKEN2);
7873 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7874 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7875
0ff066a9
PZ		 7876 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7877 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7878 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7879}
7880
7881/* WaMPhyProgramming:hsw */
7882static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7883{
7884 uint32_t tmp;
dde86e2d
PZ		 7885
7886 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7887 tmp &= ~(0xFF << 24);
7888 tmp |= (0x12 << 24);
7889 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7890
dde86e2d
PZ		 7891 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7892 tmp |= (1 << 11);
7893 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7894
7895 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7896 tmp |= (1 << 11);
7897 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7898
dde86e2d
PZ		 7899 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7900 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7901 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7902
7903 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7904 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7905 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7906
0ff066a9
PZ		 7907 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7908 tmp &= ~(7 << 13);
7909 tmp |= (5 << 13);
7910 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7911
0ff066a9
PZ		 7912 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7913 tmp &= ~(7 << 13);
7914 tmp |= (5 << 13);
7915 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7916
7917 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7918 tmp &= ~0xFF;
7919 tmp |= 0x1C;
7920 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7921
7922 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7923 tmp &= ~0xFF;
7924 tmp |= 0x1C;
7925 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7926
7927 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7928 tmp &= ~(0xFF << 16);
7929 tmp |= (0x1C << 16);
7930 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7931
7932 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7933 tmp &= ~(0xFF << 16);
7934 tmp |= (0x1C << 16);
7935 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7936
0ff066a9
PZ		 7937 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7938 tmp |= (1 << 27);
7939 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7940
0ff066a9
PZ		 7941 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7942 tmp |= (1 << 27);
7943 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7944
0ff066a9
PZ		 7945 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7946 tmp &= ~(0xF << 28);
7947 tmp |= (4 << 28);
7948 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7949
0ff066a9
PZ		 7950 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7951 tmp &= ~(0xF << 28);
7952 tmp |= (4 << 28);
7953 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7954}
7955
2fa86a1f
PZ		 7956/* Implements 3 different sequences from BSpec chapter "Display iCLK
7957 * Programming" based on the parameters passed:
7958 * - Sequence to enable CLKOUT_DP
7959 * - Sequence to enable CLKOUT_DP without spread
7960 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7961 */
7962static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7963 bool with_fdi)
f31f2d55
PZ		 7964{
7965 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7966 uint32_t reg, tmp;
7967
7968 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7969 with_spread = true;
7970 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7971 with_fdi, "LP PCH doesn't have FDI\n"))
7972 with_fdi = false;
f31f2d55
PZ		 7973
7974 mutex_lock(&dev_priv->dpio_lock);
7975
7976 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7977 tmp &= ~SBI_SSCCTL_DISABLE;
7978 tmp |= SBI_SSCCTL_PATHALT;
7979 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7980
7981 udelay(24);
7982
2fa86a1f
PZ		 7983 if (with_spread) {
7984 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7985 tmp &= ~SBI_SSCCTL_PATHALT;
7986 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7987
2fa86a1f
PZ		 7988 if (with_fdi) {
7989 lpt_reset_fdi_mphy(dev_priv);
7990 lpt_program_fdi_mphy(dev_priv);
7991 }
7992 }
dde86e2d 7993
2fa86a1f
PZ		 7994 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7995 SBI_GEN0 : SBI_DBUFF0;
7996 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7997 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7998 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7999
8000 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8001}
8002
47701c3b
PZ		 8003/* Sequence to disable CLKOUT_DP */
8004static void lpt_disable_clkout_dp(struct drm_device *dev)
8005{
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007 uint32_t reg, tmp;
8008
8009 mutex_lock(&dev_priv->dpio_lock);
8010
8011 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8012 SBI_GEN0 : SBI_DBUFF0;
8013 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8014 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8015 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8016
8017 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8018 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8019 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8020 tmp |= SBI_SSCCTL_PATHALT;
8021 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8022 udelay(32);
8023 }
8024 tmp |= SBI_SSCCTL_DISABLE;
8025 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8026 }
8027
8028 mutex_unlock(&dev_priv->dpio_lock);
8029}
8030
bf8fa3d3
PZ		 8031static void lpt_init_pch_refclk(struct drm_device *dev)
8032{
bf8fa3d3
PZ		 8033 struct intel_encoder *encoder;
8034 bool has_vga = false;
8035
b2784e15 8036 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8037 switch (encoder->type) {
8038 case INTEL_OUTPUT_ANALOG:
8039 has_vga = true;
8040 break;
6847d71b
PZ		 8041 default:
8042 break;
bf8fa3d3
PZ		 8043 }
8044 }
8045
47701c3b
PZ		 8046 if (has_vga)
8047 lpt_enable_clkout_dp(dev, true, true);
8048 else
8049 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8050}
8051
dde86e2d
PZ		 8052/*
8053 * Initialize reference clocks when the driver loads
8054 */
8055void intel_init_pch_refclk(struct drm_device *dev)
8056{
8057 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8058 ironlake_init_pch_refclk(dev);
8059 else if (HAS_PCH_LPT(dev))
8060 lpt_init_pch_refclk(dev);
8061}
8062
55bb9992 8063static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8064{
55bb9992 8065 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8066 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8067 struct drm_atomic_state *state = crtc_state->base.state;
8068 struct drm_connector_state *connector_state;
d9d444cb 8069 struct intel_encoder *encoder;
55bb9992 8070 int num_connectors = 0, i;
d9d444cb
JB		 8071 bool is_lvds = false;
8072
55bb9992
ACO		 8073 for (i = 0; i < state->num_connector; i++) {
8074 if (!state->connectors[i])
d0737e1d
ACO		 8075 continue;
8076
55bb9992
ACO		 8077 connector_state = state->connector_states[i];
8078 if (connector_state->crtc != crtc_state->base.crtc)
8079 continue;
8080
8081 encoder = to_intel_encoder(connector_state->best_encoder);
8082
d9d444cb
JB		 8083 switch (encoder->type) {
8084 case INTEL_OUTPUT_LVDS:
8085 is_lvds = true;
8086 break;
6847d71b
PZ		 8087 default:
8088 break;
d9d444cb
JB		 8089 }
8090 num_connectors++;
8091 }
8092
8093 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8094 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8095 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8096 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8097 }
8098
8099 return 120000;
8100}
8101
6ff93609 8102static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8103{
c8203565 8104 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106 int pipe = intel_crtc->pipe;
c8203565
PZ		 8107 uint32_t val;
8108
78114071 8109 val = 0;
c8203565 8110
6e3c9717 8111 switch (intel_crtc->config->pipe_bpp) {
c8203565 8112 case 18:
dfd07d72 8113 val |= PIPECONF_6BPC;
c8203565
PZ		 8114 break;
8115 case 24:
dfd07d72 8116 val |= PIPECONF_8BPC;
c8203565
PZ		 8117 break;
8118 case 30:
dfd07d72 8119 val |= PIPECONF_10BPC;
c8203565
PZ		 8120 break;
8121 case 36:
dfd07d72 8122 val |= PIPECONF_12BPC;
c8203565
PZ		 8123 break;
8124 default:
cc769b62
PZ		 8125 /* Case prevented by intel_choose_pipe_bpp_dither. */
8126 BUG();
c8203565
PZ		 8127 }
8128
6e3c9717 8129 if (intel_crtc->config->dither)
c8203565
PZ		 8130 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8131
6e3c9717 8132 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8133 val |= PIPECONF_INTERLACED_ILK;
8134 else
8135 val |= PIPECONF_PROGRESSIVE;
8136
6e3c9717 8137 if (intel_crtc->config->limited_color_range)
3685a8f3 8138 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8139
c8203565
PZ		 8140 I915_WRITE(PIPECONF(pipe), val);
8141 POSTING_READ(PIPECONF(pipe));
8142}
8143
86d3efce
VS		 8144/*
8145 * Set up the pipe CSC unit.
8146 *
8147 * Currently only full range RGB to limited range RGB conversion
8148 * is supported, but eventually this should handle various
8149 * RGB<->YCbCr scenarios as well.
8150 */
50f3b016 8151static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8152{
8153 struct drm_device *dev = crtc->dev;
8154 struct drm_i915_private *dev_priv = dev->dev_private;
8155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8156 int pipe = intel_crtc->pipe;
8157 uint16_t coeff = 0x7800; /* 1.0 */
8158
8159 /*
8160 * TODO: Check what kind of values actually come out of the pipe
8161 * with these coeff/postoff values and adjust to get the best
8162 * accuracy. Perhaps we even need to take the bpc value into
8163 * consideration.
8164 */
8165
6e3c9717 8166 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8167 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8168
8169 /*
8170 * GY/GU and RY/RU should be the other way around according
8171 * to BSpec, but reality doesn't agree. Just set them up in
8172 * a way that results in the correct picture.
8173 */
8174 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8175 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8176
8177 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8178 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8179
8180 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8181 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8182
8183 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8184 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8185 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8186
8187 if (INTEL_INFO(dev)->gen > 6) {
8188 uint16_t postoff = 0;
8189
6e3c9717 8190 if (intel_crtc->config->limited_color_range)
32cf0cb0 8191 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8192
8193 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8194 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8195 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8196
8197 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8198 } else {
8199 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8200
6e3c9717 8201 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8202 mode |= CSC_BLACK_SCREEN_OFFSET;
8203
8204 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8205 }
8206}
8207
6ff93609 8208static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8209{
756f85cf
PZ		 8210 struct drm_device *dev = crtc->dev;
8211 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8213 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8214 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8215 uint32_t val;
8216
3eff4faa 8217 val = 0;
ee2b0b38 8218
6e3c9717 8219 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8220 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8221
6e3c9717 8222 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8223 val |= PIPECONF_INTERLACED_ILK;
8224 else
8225 val |= PIPECONF_PROGRESSIVE;
8226
702e7a56
PZ		 8227 I915_WRITE(PIPECONF(cpu_transcoder), val);
8228 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8229
8230 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8231 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8232
3cdf122c 8233 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8234 val = 0;
8235
6e3c9717 8236 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8237 case 18:
8238 val |= PIPEMISC_DITHER_6_BPC;
8239 break;
8240 case 24:
8241 val |= PIPEMISC_DITHER_8_BPC;
8242 break;
8243 case 30:
8244 val |= PIPEMISC_DITHER_10_BPC;
8245 break;
8246 case 36:
8247 val |= PIPEMISC_DITHER_12_BPC;
8248 break;
8249 default:
8250 /* Case prevented by pipe_config_set_bpp. */
8251 BUG();
8252 }
8253
6e3c9717 8254 if (intel_crtc->config->dither)
756f85cf
PZ		 8255 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8256
8257 I915_WRITE(PIPEMISC(pipe), val);
8258 }
ee2b0b38
PZ		 8259}
8260
6591c6e4 8261static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8262 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8263 intel_clock_t *clock,
8264 bool *has_reduced_clock,
8265 intel_clock_t *reduced_clock)
8266{
8267 struct drm_device *dev = crtc->dev;
8268 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8269 int refclk;
d4906093 8270 const intel_limit_t *limit;
a16af721 8271 bool ret, is_lvds = false;
79e53945 8272
a93e255f 8273 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8274
55bb9992 8275 refclk = ironlake_get_refclk(crtc_state);
79e53945 8276
d4906093
ML		 8277 /*
8278 * Returns a set of divisors for the desired target clock with the given
8279 * refclk, or FALSE. The returned values represent the clock equation:
8280 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8281 */
a93e255f
ACO		 8282 limit = intel_limit(crtc_state, refclk);
8283 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8284 crtc_state->port_clock,
ee9300bb 8285 refclk, NULL, clock);
6591c6e4
PZ		 8286 if (!ret)
8287 return false;
cda4b7d3 8288
ddc9003c 8289 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8290 /*
8291 * Ensure we match the reduced clock's P to the target clock.
8292 * If the clocks don't match, we can't switch the display clock
8293 * by using the FP0/FP1. In such case we will disable the LVDS
8294 * downclock feature.
8295 */
ee9300bb 8296 *has_reduced_clock =
a93e255f 8297 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8298 dev_priv->lvds_downclock,
8299 refclk, clock,
8300 reduced_clock);
652c393a 8301 }
61e9653f 8302
6591c6e4
PZ		 8303 return true;
8304}
8305
d4b1931c
PZ		 8306int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8307{
8308 /*
8309 * Account for spread spectrum to avoid
8310 * oversubscribing the link. Max center spread
8311 * is 2.5%; use 5% for safety's sake.
8312 */
8313 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8314 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8315}
8316
7429e9d4 8317static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8318{
7429e9d4 8319 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8320}
8321
de13a2e3 8322static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8323 struct intel_crtc_state *crtc_state,
7429e9d4 8324 u32 *fp,
9a7c7890 8325 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8326{
de13a2e3 8327 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8328 struct drm_device *dev = crtc->dev;
8329 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8330 struct drm_atomic_state *state = crtc_state->base.state;
8331 struct drm_connector_state *connector_state;
8332 struct intel_encoder *encoder;
de13a2e3 8333 uint32_t dpll;
55bb9992 8334 int factor, num_connectors = 0, i;
09ede541 8335 bool is_lvds = false, is_sdvo = false;
79e53945 8336
55bb9992
ACO		 8337 for (i = 0; i < state->num_connector; i++) {
8338 if (!state->connectors[i])
d0737e1d
ACO		 8339 continue;
8340
55bb9992
ACO		 8341 connector_state = state->connector_states[i];
8342 if (connector_state->crtc != crtc_state->base.crtc)
8343 continue;
8344
8345 encoder = to_intel_encoder(connector_state->best_encoder);
8346
8347 switch (encoder->type) {
79e53945
JB		 8348 case INTEL_OUTPUT_LVDS:
8349 is_lvds = true;
8350 break;
8351 case INTEL_OUTPUT_SDVO:
7d57382e 8352 case INTEL_OUTPUT_HDMI:
79e53945 8353 is_sdvo = true;
79e53945 8354 break;
6847d71b
PZ		 8355 default:
8356 break;
79e53945 8357 }
43565a06 8358
c751ce4f 8359 num_connectors++;
79e53945 8360 }
79e53945 8361
c1858123 8362 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8363 factor = 21;
8364 if (is_lvds) {
8365 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8366 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8367 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8368 factor = 25;
190f68c5 8369 } else if (crtc_state->sdvo_tv_clock)
8febb297 8370 factor = 20;
c1858123 8371
190f68c5 8372 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8373 *fp |= FP_CB_TUNE;
2c07245f 8374
9a7c7890
DV		 8375 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8376 *fp2 |= FP_CB_TUNE;
8377
5eddb70b 8378 dpll = 0;
2c07245f 8379
a07d6787
EA		 8380 if (is_lvds)
8381 dpll |= DPLLB_MODE_LVDS;
8382 else
8383 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8384
190f68c5 8385 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8386 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8387
8388 if (is_sdvo)
4a33e48d 8389 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8390 if (crtc_state->has_dp_encoder)
4a33e48d 8391 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8392
a07d6787 8393 /* compute bitmask from p1 value */
190f68c5 8394 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8395 /* also FPA1 */
190f68c5 8396 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8397
190f68c5 8398 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8399 case 5:
8400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8401 break;
8402 case 7:
8403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8404 break;
8405 case 10:
8406 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8407 break;
8408 case 14:
8409 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8410 break;
79e53945
JB		 8411 }
8412
b4c09f3b 8413 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8414 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8415 else
8416 dpll |= PLL_REF_INPUT_DREFCLK;
8417
959e16d6 8418 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8419}
8420
190f68c5
ACO		 8421static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8422 struct intel_crtc_state *crtc_state)
de13a2e3 8423{
c7653199 8424 struct drm_device *dev = crtc->base.dev;
de13a2e3 8425 intel_clock_t clock, reduced_clock;
cbbab5bd 8426 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8427 bool ok, has_reduced_clock = false;
8b47047b 8428 bool is_lvds = false;
e2b78267 8429 struct intel_shared_dpll *pll;
de13a2e3 8430
409ee761 8431 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8432
5dc5298b
PZ		 8433 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8434 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8435
190f68c5 8436 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8437 &has_reduced_clock, &reduced_clock);
190f68c5 8438 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8439 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8440 return -EINVAL;
79e53945 8441 }
f47709a9 8442 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8443 if (!crtc_state->clock_set) {
8444 crtc_state->dpll.n = clock.n;
8445 crtc_state->dpll.m1 = clock.m1;
8446 crtc_state->dpll.m2 = clock.m2;
8447 crtc_state->dpll.p1 = clock.p1;
8448 crtc_state->dpll.p2 = clock.p2;
f47709a9 8449 }
79e53945 8450
5dc5298b 8451 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8452 if (crtc_state->has_pch_encoder) {
8453 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8454 if (has_reduced_clock)
7429e9d4 8455 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8456
190f68c5 8457 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8458 &fp, &reduced_clock,
8459 has_reduced_clock ? &fp2 : NULL);
8460
190f68c5
ACO		 8461 crtc_state->dpll_hw_state.dpll = dpll;
8462 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8463 if (has_reduced_clock)
190f68c5 8464 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8465 else
190f68c5 8466 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8467
190f68c5 8468 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8469 if (pll == NULL) {
84f44ce7 8470 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8471 pipe_name(crtc->pipe));
4b645f14
JB		 8472 return -EINVAL;
8473 }
3fb37703 8474 }
79e53945 8475
ab585dea 8476 if (is_lvds && has_reduced_clock)
c7653199 8477 crtc->lowfreq_avail = true;
bcd644e0 8478 else
c7653199 8479 crtc->lowfreq_avail = false;
e2b78267 8480
c8f7a0db 8481 return 0;
79e53945
JB		 8482}
8483
eb14cb74
VS		 8484static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8485 struct intel_link_m_n *m_n)
8486{
8487 struct drm_device *dev = crtc->base.dev;
8488 struct drm_i915_private *dev_priv = dev->dev_private;
8489 enum pipe pipe = crtc->pipe;
8490
8491 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8492 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8493 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8494 & ~TU_SIZE_MASK;
8495 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8496 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8497 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8498}
8499
8500static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8501 enum transcoder transcoder,
b95af8be
VK		 8502 struct intel_link_m_n *m_n,
8503 struct intel_link_m_n *m2_n2)
72419203
DV		 8504{
8505 struct drm_device *dev = crtc->base.dev;
8506 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8507 enum pipe pipe = crtc->pipe;
72419203 8508
eb14cb74
VS		 8509 if (INTEL_INFO(dev)->gen >= 5) {
8510 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8511 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8512 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8513 & ~TU_SIZE_MASK;
8514 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8515 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8516 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8517 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8518 * gen < 8) and if DRRS is supported (to make sure the
8519 * registers are not unnecessarily read).
8520 */
8521 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8522 crtc->config->has_drrs) {
b95af8be
VK		 8523 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8524 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8525 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8526 & ~TU_SIZE_MASK;
8527 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8528 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8529 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8530 }
eb14cb74
VS		 8531 } else {
8532 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8533 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8534 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8535 & ~TU_SIZE_MASK;
8536 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8537 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8538 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8539 }
8540}
8541
8542void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8543 struct intel_crtc_state *pipe_config)
eb14cb74 8544{
681a8504 8545 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8546 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8547 else
8548 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8549 &pipe_config->dp_m_n,
8550 &pipe_config->dp_m2_n2);
eb14cb74 8551}
72419203 8552
eb14cb74 8553static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8554 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8555{
8556 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8557 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8558}
8559
bd2e244f 8560static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8561 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8562{
8563 struct drm_device *dev = crtc->base.dev;
8564 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8565 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8566 uint32_t ps_ctrl = 0;
8567 int id = -1;
8568 int i;
bd2e244f 8569
a1b2278e
CK		 8570 /* find scaler attached to this pipe */
8571 for (i = 0; i < crtc->num_scalers; i++) {
8572 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8573 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8574 id = i;
8575 pipe_config->pch_pfit.enabled = true;
8576 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8577 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8578 break;
8579 }
8580 }
bd2e244f 8581
a1b2278e
CK		 8582 scaler_state->scaler_id = id;
8583 if (id >= 0) {
8584 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8585 } else {
8586 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8587 }
8588}
8589
5724dbd1
DL		 8590static void
8591skylake_get_initial_plane_config(struct intel_crtc *crtc,
8592 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8593{
8594 struct drm_device *dev = crtc->base.dev;
8595 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8596 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8597 int pipe = crtc->pipe;
8598 int fourcc, pixel_format;
6761dd31 8599 unsigned int aligned_height;
bc8d7dff 8600 struct drm_framebuffer *fb;
1b842c89 8601 struct intel_framebuffer *intel_fb;
bc8d7dff 8602
d9806c9f 8603 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8604 if (!intel_fb) {
bc8d7dff
DL		 8605 DRM_DEBUG_KMS("failed to alloc fb\n");
8606 return;
8607 }
8608
1b842c89
DL		 8609 fb = &intel_fb->base;
8610
bc8d7dff 8611 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8612 if (!(val & PLANE_CTL_ENABLE))
8613 goto error;
8614
bc8d7dff
DL		 8615 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8616 fourcc = skl_format_to_fourcc(pixel_format,
8617 val & PLANE_CTL_ORDER_RGBX,
8618 val & PLANE_CTL_ALPHA_MASK);
8619 fb->pixel_format = fourcc;
8620 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8621
40f46283
DL		 8622 tiling = val & PLANE_CTL_TILED_MASK;
8623 switch (tiling) {
8624 case PLANE_CTL_TILED_LINEAR:
8625 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8626 break;
8627 case PLANE_CTL_TILED_X:
8628 plane_config->tiling = I915_TILING_X;
8629 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8630 break;
8631 case PLANE_CTL_TILED_Y:
8632 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8633 break;
8634 case PLANE_CTL_TILED_YF:
8635 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8636 break;
8637 default:
8638 MISSING_CASE(tiling);
8639 goto error;
8640 }
8641
bc8d7dff
DL		 8642 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8643 plane_config->base = base;
8644
8645 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8646
8647 val = I915_READ(PLANE_SIZE(pipe, 0));
8648 fb->height = ((val >> 16) & 0xfff) + 1;
8649 fb->width = ((val >> 0) & 0x1fff) + 1;
8650
8651 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8652 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8653 fb->pixel_format);
bc8d7dff
DL		 8654 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8655
8656 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8657 fb->pixel_format,
8658 fb->modifier[0]);
bc8d7dff 8659
f37b5c2b 8660 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8661
8662 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8663 pipe_name(pipe), fb->width, fb->height,
8664 fb->bits_per_pixel, base, fb->pitches[0],
8665 plane_config->size);
8666
2d14030b 8667 plane_config->fb = intel_fb;
bc8d7dff
DL		 8668 return;
8669
8670error:
8671 kfree(fb);
8672}
8673
2fa2fe9a 8674static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8675 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8676{
8677 struct drm_device *dev = crtc->base.dev;
8678 struct drm_i915_private *dev_priv = dev->dev_private;
8679 uint32_t tmp;
8680
8681 tmp = I915_READ(PF_CTL(crtc->pipe));
8682
8683 if (tmp & PF_ENABLE) {
fd4daa9c 8684 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8685 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8686 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8687
8688 /* We currently do not free assignements of panel fitters on
8689 * ivb/hsw (since we don't use the higher upscaling modes which
8690 * differentiates them) so just WARN about this case for now. */
8691 if (IS_GEN7(dev)) {
8692 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8693 PF_PIPE_SEL_IVB(crtc->pipe));
8694 }
2fa2fe9a 8695 }
79e53945
JB		 8696}
8697
5724dbd1
DL		 8698static void
8699ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8700 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8701{
8702 struct drm_device *dev = crtc->base.dev;
8703 struct drm_i915_private *dev_priv = dev->dev_private;
8704 u32 val, base, offset;
aeee5a49 8705 int pipe = crtc->pipe;
4c6baa59 8706 int fourcc, pixel_format;
6761dd31 8707 unsigned int aligned_height;
b113d5ee 8708 struct drm_framebuffer *fb;
1b842c89 8709 struct intel_framebuffer *intel_fb;
4c6baa59 8710
42a7b088
DL		 8711 val = I915_READ(DSPCNTR(pipe));
8712 if (!(val & DISPLAY_PLANE_ENABLE))
8713 return;
8714
d9806c9f 8715 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8716 if (!intel_fb) {
4c6baa59
JB		 8717 DRM_DEBUG_KMS("failed to alloc fb\n");
8718 return;
8719 }
8720
1b842c89
DL		 8721 fb = &intel_fb->base;
8722
18c5247e
DV		 8723 if (INTEL_INFO(dev)->gen >= 4) {
8724 if (val & DISPPLANE_TILED) {
49af449b 8725 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8726 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8727 }
8728 }
4c6baa59
JB		 8729
8730 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8731 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8732 fb->pixel_format = fourcc;
8733 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8734
aeee5a49 8735 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8736 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8737 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8738 } else {
49af449b 8739 if (plane_config->tiling)
aeee5a49 8740 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8741 else
aeee5a49 8742 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8743 }
8744 plane_config->base = base;
8745
8746 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8747 fb->width = ((val >> 16) & 0xfff) + 1;
8748 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8749
8750 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8751 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8752
b113d5ee 8753 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8754 fb->pixel_format,
8755 fb->modifier[0]);
4c6baa59 8756
f37b5c2b 8757 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8758
2844a921
DL		 8759 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8760 pipe_name(pipe), fb->width, fb->height,
8761 fb->bits_per_pixel, base, fb->pitches[0],
8762 plane_config->size);
b113d5ee 8763
2d14030b 8764 plane_config->fb = intel_fb;
4c6baa59
JB		 8765}
8766
0e8ffe1b 8767static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8768 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8769{
8770 struct drm_device *dev = crtc->base.dev;
8771 struct drm_i915_private *dev_priv = dev->dev_private;
8772 uint32_t tmp;
8773
f458ebbc
DV		 8774 if (!intel_display_power_is_enabled(dev_priv,
8775 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8776 return false;
8777
e143a21c 8778 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8779 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8780
0e8ffe1b
DV		 8781 tmp = I915_READ(PIPECONF(crtc->pipe));
8782 if (!(tmp & PIPECONF_ENABLE))
8783 return false;
8784
42571aef
VS		 8785 switch (tmp & PIPECONF_BPC_MASK) {
8786 case PIPECONF_6BPC:
8787 pipe_config->pipe_bpp = 18;
8788 break;
8789 case PIPECONF_8BPC:
8790 pipe_config->pipe_bpp = 24;
8791 break;
8792 case PIPECONF_10BPC:
8793 pipe_config->pipe_bpp = 30;
8794 break;
8795 case PIPECONF_12BPC:
8796 pipe_config->pipe_bpp = 36;
8797 break;
8798 default:
8799 break;
8800 }
8801
b5a9fa09
DV		 8802 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8803 pipe_config->limited_color_range = true;
8804
ab9412ba 8805 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8806 struct intel_shared_dpll *pll;
8807
88adfff1
DV		 8808 pipe_config->has_pch_encoder = true;
8809
627eb5a3
DV		 8810 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8811 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8812 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8813
8814 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8815
c0d43d62 8816 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8817 pipe_config->shared_dpll =
8818 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8819 } else {
8820 tmp = I915_READ(PCH_DPLL_SEL);
8821 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8822 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8823 else
8824 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8825 }
66e985c0
DV		 8826
8827 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8828
8829 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8830 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8831
8832 tmp = pipe_config->dpll_hw_state.dpll;
8833 pipe_config->pixel_multiplier =
8834 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8835 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8836
8837 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8838 } else {
8839 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8840 }
8841
1bd1bd80
DV		 8842 intel_get_pipe_timings(crtc, pipe_config);
8843
2fa2fe9a
DV		 8844 ironlake_get_pfit_config(crtc, pipe_config);
8845
0e8ffe1b
DV		 8846 return true;
8847}
8848
be256dc7
PZ		 8849static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8850{
8851 struct drm_device *dev = dev_priv->dev;
be256dc7 8852 struct intel_crtc *crtc;
be256dc7 8853
d3fcc808 8854 for_each_intel_crtc(dev, crtc)
e2c719b7 8855 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8856 pipe_name(crtc->pipe));
8857
e2c719b7
RC		 8858 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8859 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8860 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8861 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8862 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8863 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8864 "CPU PWM1 enabled\n");
c5107b87 8865 if (IS_HASWELL(dev))
e2c719b7 8866 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8867 "CPU PWM2 enabled\n");
e2c719b7 8868 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8869 "PCH PWM1 enabled\n");
e2c719b7 8870 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8871 "Utility pin enabled\n");
e2c719b7 8872 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8873
9926ada1
PZ		 8874 /*
8875 * In theory we can still leave IRQs enabled, as long as only the HPD
8876 * interrupts remain enabled. We used to check for that, but since it's
8877 * gen-specific and since we only disable LCPLL after we fully disable
8878 * the interrupts, the check below should be enough.
8879 */
e2c719b7 8880 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8881}
8882
9ccd5aeb
PZ		 8883static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8884{
8885 struct drm_device *dev = dev_priv->dev;
8886
8887 if (IS_HASWELL(dev))
8888 return I915_READ(D_COMP_HSW);
8889 else
8890 return I915_READ(D_COMP_BDW);
8891}
8892
3c4c9b81
PZ		 8893static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8894{
8895 struct drm_device *dev = dev_priv->dev;
8896
8897 if (IS_HASWELL(dev)) {
8898 mutex_lock(&dev_priv->rps.hw_lock);
8899 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8900 val))
f475dadf 8901 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8902 mutex_unlock(&dev_priv->rps.hw_lock);
8903 } else {
9ccd5aeb
PZ		 8904 I915_WRITE(D_COMP_BDW, val);
8905 POSTING_READ(D_COMP_BDW);
3c4c9b81 8906 }
be256dc7
PZ		 8907}
8908
8909/*
8910 * This function implements pieces of two sequences from BSpec:
8911 * - Sequence for display software to disable LCPLL
8912 * - Sequence for display software to allow package C8+
8913 * The steps implemented here are just the steps that actually touch the LCPLL
8914 * register. Callers should take care of disabling all the display engine
8915 * functions, doing the mode unset, fixing interrupts, etc.
8916 */
6ff58d53
PZ		 8917static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8918 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8919{
8920 uint32_t val;
8921
8922 assert_can_disable_lcpll(dev_priv);
8923
8924 val = I915_READ(LCPLL_CTL);
8925
8926 if (switch_to_fclk) {
8927 val |= LCPLL_CD_SOURCE_FCLK;
8928 I915_WRITE(LCPLL_CTL, val);
8929
8930 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8931 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8932 DRM_ERROR("Switching to FCLK failed\n");
8933
8934 val = I915_READ(LCPLL_CTL);
8935 }
8936
8937 val |= LCPLL_PLL_DISABLE;
8938 I915_WRITE(LCPLL_CTL, val);
8939 POSTING_READ(LCPLL_CTL);
8940
8941 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8942 DRM_ERROR("LCPLL still locked\n");
8943
9ccd5aeb 8944 val = hsw_read_dcomp(dev_priv);
be256dc7 8945 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8946 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8947 ndelay(100);
8948
9ccd5aeb
PZ		 8949 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8950 1))
be256dc7
PZ		 8951 DRM_ERROR("D_COMP RCOMP still in progress\n");
8952
8953 if (allow_power_down) {
8954 val = I915_READ(LCPLL_CTL);
8955 val |= LCPLL_POWER_DOWN_ALLOW;
8956 I915_WRITE(LCPLL_CTL, val);
8957 POSTING_READ(LCPLL_CTL);
8958 }
8959}
8960
8961/*
8962 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8963 * source.
8964 */
6ff58d53 8965static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8966{
8967 uint32_t val;
8968
8969 val = I915_READ(LCPLL_CTL);
8970
8971 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8972 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8973 return;
8974
a8a8bd54
PZ		 8975 /*
8976 * Make sure we're not on PC8 state before disabling PC8, otherwise
8977 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8978 */
59bad947 8979 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8980
be256dc7
PZ		 8981 if (val & LCPLL_POWER_DOWN_ALLOW) {
8982 val &= ~LCPLL_POWER_DOWN_ALLOW;
8983 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8984 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8985 }
8986
9ccd5aeb 8987 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8988 val |= D_COMP_COMP_FORCE;
8989 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8990 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8991
8992 val = I915_READ(LCPLL_CTL);
8993 val &= ~LCPLL_PLL_DISABLE;
8994 I915_WRITE(LCPLL_CTL, val);
8995
8996 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8997 DRM_ERROR("LCPLL not locked yet\n");
8998
8999 if (val & LCPLL_CD_SOURCE_FCLK) {
9000 val = I915_READ(LCPLL_CTL);
9001 val &= ~LCPLL_CD_SOURCE_FCLK;
9002 I915_WRITE(LCPLL_CTL, val);
9003
9004 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9005 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9006 DRM_ERROR("Switching back to LCPLL failed\n");
9007 }
215733fa 9008
59bad947 9009 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9010}
9011
765dab67
PZ		 9012/*
9013 * Package states C8 and deeper are really deep PC states that can only be
9014 * reached when all the devices on the system allow it, so even if the graphics
9015 * device allows PC8+, it doesn't mean the system will actually get to these
9016 * states. Our driver only allows PC8+ when going into runtime PM.
9017 *
9018 * The requirements for PC8+ are that all the outputs are disabled, the power
9019 * well is disabled and most interrupts are disabled, and these are also
9020 * requirements for runtime PM. When these conditions are met, we manually do
9021 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9022 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9023 * hang the machine.
9024 *
9025 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9026 * the state of some registers, so when we come back from PC8+ we need to
9027 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9028 * need to take care of the registers kept by RC6. Notice that this happens even
9029 * if we don't put the device in PCI D3 state (which is what currently happens
9030 * because of the runtime PM support).
9031 *
9032 * For more, read "Display Sequences for Package C8" on the hardware
9033 * documentation.
9034 */
a14cb6fc 9035void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9036{
c67a470b
PZ		 9037 struct drm_device *dev = dev_priv->dev;
9038 uint32_t val;
9039
c67a470b
PZ		 9040 DRM_DEBUG_KMS("Enabling package C8+\n");
9041
c67a470b
PZ		 9042 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9043 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9044 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9045 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9046 }
9047
9048 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9049 hsw_disable_lcpll(dev_priv, true, true);
9050}
9051
a14cb6fc 9052void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9053{
9054 struct drm_device *dev = dev_priv->dev;
9055 uint32_t val;
9056
c67a470b
PZ		 9057 DRM_DEBUG_KMS("Disabling package C8+\n");
9058
9059 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9060 lpt_init_pch_refclk(dev);
9061
9062 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9063 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9064 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9065 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9066 }
9067
9068 intel_prepare_ddi(dev);
c67a470b
PZ		 9069}
9070
f8437dd1
VK		 9071static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9072{
9073 struct drm_device *dev = state->dev;
9074 struct drm_i915_private *dev_priv = dev->dev_private;
9075 int max_pixclk = intel_mode_max_pixclk(state);
9076 int req_cdclk;
9077
9078 /* see the comment in valleyview_modeset_global_resources */
9079 if (WARN_ON(max_pixclk < 0))
9080 return;
9081
9082 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9083
9084 if (req_cdclk != dev_priv->cdclk_freq)
9085 broxton_set_cdclk(dev, req_cdclk);
9086}
9087
190f68c5
ACO		 9088static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9089 struct intel_crtc_state *crtc_state)
09b4ddf9 9090{
190f68c5 9091 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9092 return -EINVAL;
716c2e55 9093
c7653199 9094 crtc->lowfreq_avail = false;
644cef34 9095
c8f7a0db 9096 return 0;
79e53945
JB		 9097}
9098
3760b59c
S		 9099static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9100 enum port port,
9101 struct intel_crtc_state *pipe_config)
9102{
9103 switch (port) {
9104 case PORT_A:
9105 pipe_config->ddi_pll_sel = SKL_DPLL0;
9106 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9107 break;
9108 case PORT_B:
9109 pipe_config->ddi_pll_sel = SKL_DPLL1;
9110 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9111 break;
9112 case PORT_C:
9113 pipe_config->ddi_pll_sel = SKL_DPLL2;
9114 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9115 break;
9116 default:
9117 DRM_ERROR("Incorrect port type\n");
9118 }
9119}
9120
96b7dfb7
S		 9121static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9122 enum port port,
5cec258b 9123 struct intel_crtc_state *pipe_config)
96b7dfb7 9124{
3148ade7 9125 u32 temp, dpll_ctl1;
96b7dfb7
S		 9126
9127 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9128 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9129
9130 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9131 case SKL_DPLL0:
9132 /*
9133 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9134 * of the shared DPLL framework and thus needs to be read out
9135 * separately
9136 */
9137 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9138 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9139 break;
96b7dfb7
S		 9140 case SKL_DPLL1:
9141 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9142 break;
9143 case SKL_DPLL2:
9144 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9145 break;
9146 case SKL_DPLL3:
9147 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9148 break;
96b7dfb7
S		 9149 }
9150}
9151
7d2c8175
DL		 9152static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9153 enum port port,
5cec258b 9154 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9155{
9156 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9157
9158 switch (pipe_config->ddi_pll_sel) {
9159 case PORT_CLK_SEL_WRPLL1:
9160 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9161 break;
9162 case PORT_CLK_SEL_WRPLL2:
9163 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9164 break;
9165 }
9166}
9167
26804afd 9168static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9169 struct intel_crtc_state *pipe_config)
26804afd
DV		 9170{
9171 struct drm_device *dev = crtc->base.dev;
9172 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9173 struct intel_shared_dpll *pll;
26804afd
DV		 9174 enum port port;
9175 uint32_t tmp;
9176
9177 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9178
9179 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9180
96b7dfb7
S		 9181 if (IS_SKYLAKE(dev))
9182 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9183 else if (IS_BROXTON(dev))
9184 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9185 else
9186 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9187
d452c5b6
DV		 9188 if (pipe_config->shared_dpll >= 0) {
9189 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9190
9191 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9192 &pipe_config->dpll_hw_state));
9193 }
9194
26804afd
DV		 9195 /*
9196 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9197 * DDI E. So just check whether this pipe is wired to DDI E and whether
9198 * the PCH transcoder is on.
9199 */
ca370455
DL		 9200 if (INTEL_INFO(dev)->gen < 9 &&
9201 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9202 pipe_config->has_pch_encoder = true;
9203
9204 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9205 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9206 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9207
9208 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9209 }
9210}
9211
0e8ffe1b 9212static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9213 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9214{
9215 struct drm_device *dev = crtc->base.dev;
9216 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9217 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9218 uint32_t tmp;
9219
f458ebbc 9220 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9221 POWER_DOMAIN_PIPE(crtc->pipe)))
9222 return false;
9223
e143a21c 9224 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9225 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9226
eccb140b
DV		 9227 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9228 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9229 enum pipe trans_edp_pipe;
9230 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9231 default:
9232 WARN(1, "unknown pipe linked to edp transcoder\n");
9233 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9234 case TRANS_DDI_EDP_INPUT_A_ON:
9235 trans_edp_pipe = PIPE_A;
9236 break;
9237 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9238 trans_edp_pipe = PIPE_B;
9239 break;
9240 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9241 trans_edp_pipe = PIPE_C;
9242 break;
9243 }
9244
9245 if (trans_edp_pipe == crtc->pipe)
9246 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9247 }
9248
f458ebbc 9249 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9250 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9251 return false;
9252
eccb140b 9253 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9254 if (!(tmp & PIPECONF_ENABLE))
9255 return false;
9256
26804afd 9257 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9258
1bd1bd80
DV		 9259 intel_get_pipe_timings(crtc, pipe_config);
9260
a1b2278e
CK		 9261 if (INTEL_INFO(dev)->gen >= 9) {
9262 skl_init_scalers(dev, crtc, pipe_config);
9263 }
9264
2fa2fe9a 9265 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9266 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9267 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9268 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9269 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9270 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9271 else
9272 MISSING_CASE(INTEL_INFO(dev)->gen);
9273
a1b2278e
CK		 9274 } else {
9275 pipe_config->scaler_state.scaler_id = -1;
9276 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9277 }
88adfff1 9278
e59150dc
JB		 9279 if (IS_HASWELL(dev))
9280 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9281 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9282
ebb69c95
CT		 9283 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9284 pipe_config->pixel_multiplier =
9285 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9286 } else {
9287 pipe_config->pixel_multiplier = 1;
9288 }
6c49f241 9289
0e8ffe1b
DV		 9290 return true;
9291}
9292
560b85bb
CW		 9293static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9294{
9295 struct drm_device *dev = crtc->dev;
9296 struct drm_i915_private *dev_priv = dev->dev_private;
9297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9298 uint32_t cntl = 0, size = 0;
560b85bb 9299
dc41c154 9300 if (base) {
3dd512fb
MR		 9301 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9302 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9303 unsigned int stride = roundup_pow_of_two(width) * 4;
9304
9305 switch (stride) {
9306 default:
9307 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9308 width, stride);
9309 stride = 256;
9310 /* fallthrough */
9311 case 256:
9312 case 512:
9313 case 1024:
9314 case 2048:
9315 break;
4b0e333e
CW		 9316 }
9317
dc41c154
VS		 9318 cntl |= CURSOR_ENABLE |
9319 CURSOR_GAMMA_ENABLE |
9320 CURSOR_FORMAT_ARGB |
9321 CURSOR_STRIDE(stride);
9322
9323 size = (height << 12) | width;
4b0e333e 9324 }
560b85bb 9325
dc41c154
VS		 9326 if (intel_crtc->cursor_cntl != 0 &&
9327 (intel_crtc->cursor_base != base ||
9328 intel_crtc->cursor_size != size ||
9329 intel_crtc->cursor_cntl != cntl)) {
9330 /* On these chipsets we can only modify the base/size/stride
9331 * whilst the cursor is disabled.
9332 */
9333 I915_WRITE(_CURACNTR, 0);
4b0e333e 9334 POSTING_READ(_CURACNTR);
dc41c154 9335 intel_crtc->cursor_cntl = 0;
4b0e333e 9336 }
560b85bb 9337
99d1f387 9338 if (intel_crtc->cursor_base != base) {
9db4a9c7 9339 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9340 intel_crtc->cursor_base = base;
9341 }
4726e0b0 9342
dc41c154
VS		 9343 if (intel_crtc->cursor_size != size) {
9344 I915_WRITE(CURSIZE, size);
9345 intel_crtc->cursor_size = size;
4b0e333e 9346 }
560b85bb 9347
4b0e333e 9348 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9349 I915_WRITE(_CURACNTR, cntl);
9350 POSTING_READ(_CURACNTR);
4b0e333e 9351 intel_crtc->cursor_cntl = cntl;
560b85bb 9352 }
560b85bb
CW		 9353}
9354
560b85bb 9355static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9356{
9357 struct drm_device *dev = crtc->dev;
9358 struct drm_i915_private *dev_priv = dev->dev_private;
9359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9360 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9361 uint32_t cntl;
9362
9363 cntl = 0;
9364 if (base) {
9365 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9366 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9367 case 64:
9368 cntl |= CURSOR_MODE_64_ARGB_AX;
9369 break;
9370 case 128:
9371 cntl |= CURSOR_MODE_128_ARGB_AX;
9372 break;
9373 case 256:
9374 cntl |= CURSOR_MODE_256_ARGB_AX;
9375 break;
9376 default:
3dd512fb 9377 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9378 return;
65a21cd6 9379 }
4b0e333e 9380 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9381
9382 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9383 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9384 }
65a21cd6 9385
8e7d688b 9386 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9387 cntl |= CURSOR_ROTATE_180;
9388
4b0e333e
CW		 9389 if (intel_crtc->cursor_cntl != cntl) {
9390 I915_WRITE(CURCNTR(pipe), cntl);
9391 POSTING_READ(CURCNTR(pipe));
9392 intel_crtc->cursor_cntl = cntl;
65a21cd6 9393 }
4b0e333e 9394
65a21cd6 9395 /* and commit changes on next vblank */
5efb3e28
VS		 9396 I915_WRITE(CURBASE(pipe), base);
9397 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9398
9399 intel_crtc->cursor_base = base;
65a21cd6
JB		 9400}
9401
cda4b7d3 9402/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9403static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9404 bool on)
cda4b7d3
CW		 9405{
9406 struct drm_device *dev = crtc->dev;
9407 struct drm_i915_private *dev_priv = dev->dev_private;
9408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9409 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9410 int x = crtc->cursor_x;
9411 int y = crtc->cursor_y;
d6e4db15 9412 u32 base = 0, pos = 0;
cda4b7d3 9413
d6e4db15 9414 if (on)
cda4b7d3 9415 base = intel_crtc->cursor_addr;
cda4b7d3 9416
6e3c9717 9417 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9418 base = 0;
9419
6e3c9717 9420 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9421 base = 0;
9422
9423 if (x < 0) {
3dd512fb 9424 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9425 base = 0;
9426
9427 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9428 x = -x;
9429 }
9430 pos |= x << CURSOR_X_SHIFT;
9431
9432 if (y < 0) {
3dd512fb 9433 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9434 base = 0;
9435
9436 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9437 y = -y;
9438 }
9439 pos |= y << CURSOR_Y_SHIFT;
9440
4b0e333e 9441 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9442 return;
9443
5efb3e28
VS		 9444 I915_WRITE(CURPOS(pipe), pos);
9445
4398ad45
VS		 9446 /* ILK+ do this automagically */
9447 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9448 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9449 base += (intel_crtc->base.cursor->state->crtc_h *
9450 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9451 }
9452
8ac54669 9453 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9454 i845_update_cursor(crtc, base);
9455 else
9456 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9457}
9458
dc41c154
VS		 9459static bool cursor_size_ok(struct drm_device *dev,
9460 uint32_t width, uint32_t height)
9461{
9462 if (width == 0 || height == 0)
9463 return false;
9464
9465 /*
9466 * 845g/865g are special in that they are only limited by
9467 * the width of their cursors, the height is arbitrary up to
9468 * the precision of the register. Everything else requires
9469 * square cursors, limited to a few power-of-two sizes.
9470 */
9471 if (IS_845G(dev) || IS_I865G(dev)) {
9472 if ((width & 63) != 0)
9473 return false;
9474
9475 if (width > (IS_845G(dev) ? 64 : 512))
9476 return false;
9477
9478 if (height > 1023)
9479 return false;
9480 } else {
9481 switch (width | height) {
9482 case 256:
9483 case 128:
9484 if (IS_GEN2(dev))
9485 return false;
9486 case 64:
9487 break;
9488 default:
9489 return false;
9490 }
9491 }
9492
9493 return true;
9494}
9495
79e53945 9496static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9497 u16 *blue, uint32_t start, uint32_t size)
79e53945 9498{
7203425a 9499 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9501
7203425a 9502 for (i = start; i < end; i++) {
79e53945
JB		 9503 intel_crtc->lut_r[i] = red[i] >> 8;
9504 intel_crtc->lut_g[i] = green[i] >> 8;
9505 intel_crtc->lut_b[i] = blue[i] >> 8;
9506 }
9507
9508 intel_crtc_load_lut(crtc);
9509}
9510
79e53945
JB		 9511/* VESA 640x480x72Hz mode to set on the pipe */
9512static struct drm_display_mode load_detect_mode = {
9513 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9514 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9515};
9516
a8bb6818
DV		 9517struct drm_framebuffer *
9518__intel_framebuffer_create(struct drm_device *dev,
9519 struct drm_mode_fb_cmd2 *mode_cmd,
9520 struct drm_i915_gem_object *obj)
d2dff872
CW		 9521{
9522 struct intel_framebuffer *intel_fb;
9523 int ret;
9524
9525 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9526 if (!intel_fb) {
6ccb81f2 9527 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9528 return ERR_PTR(-ENOMEM);
9529 }
9530
9531 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9532 if (ret)
9533 goto err;
d2dff872
CW		 9534
9535 return &intel_fb->base;
dd4916c5 9536err:
6ccb81f2 9537 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9538 kfree(intel_fb);
9539
9540 return ERR_PTR(ret);
d2dff872
CW		 9541}
9542
b5ea642a 9543static struct drm_framebuffer *
a8bb6818
DV		 9544intel_framebuffer_create(struct drm_device *dev,
9545 struct drm_mode_fb_cmd2 *mode_cmd,
9546 struct drm_i915_gem_object *obj)
9547{
9548 struct drm_framebuffer *fb;
9549 int ret;
9550
9551 ret = i915_mutex_lock_interruptible(dev);
9552 if (ret)
9553 return ERR_PTR(ret);
9554 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9555 mutex_unlock(&dev->struct_mutex);
9556
9557 return fb;
9558}
9559
d2dff872
CW		 9560static u32
9561intel_framebuffer_pitch_for_width(int width, int bpp)
9562{
9563 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9564 return ALIGN(pitch, 64);
9565}
9566
9567static u32
9568intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9569{
9570 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9571 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9572}
9573
9574static struct drm_framebuffer *
9575intel_framebuffer_create_for_mode(struct drm_device *dev,
9576 struct drm_display_mode *mode,
9577 int depth, int bpp)
9578{
9579 struct drm_i915_gem_object *obj;
0fed39bd 9580 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9581
9582 obj = i915_gem_alloc_object(dev,
9583 intel_framebuffer_size_for_mode(mode, bpp));
9584 if (obj == NULL)
9585 return ERR_PTR(-ENOMEM);
9586
9587 mode_cmd.width = mode->hdisplay;
9588 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9589 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9590 bpp);
5ca0c34a 9591 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9592
9593 return intel_framebuffer_create(dev, &mode_cmd, obj);
9594}
9595
9596static struct drm_framebuffer *
9597mode_fits_in_fbdev(struct drm_device *dev,
9598 struct drm_display_mode *mode)
9599{
4520f53a 9600#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9601 struct drm_i915_private *dev_priv = dev->dev_private;
9602 struct drm_i915_gem_object *obj;
9603 struct drm_framebuffer *fb;
9604
4c0e5528 9605 if (!dev_priv->fbdev)
d2dff872
CW		 9606 return NULL;
9607
4c0e5528 9608 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9609 return NULL;
9610
4c0e5528
DV		 9611 obj = dev_priv->fbdev->fb->obj;
9612 BUG_ON(!obj);
9613
8bcd4553 9614 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9615 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9616 fb->bits_per_pixel))
d2dff872
CW		 9617 return NULL;
9618
01f2c773 9619 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9620 return NULL;
9621
9622 return fb;
4520f53a
DV		 9623#else
9624 return NULL;
9625#endif
d2dff872
CW		 9626}
9627
d2434ab7 9628bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9629 struct drm_display_mode *mode,
51fd371b
RC		 9630 struct intel_load_detect_pipe *old,
9631 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9632{
9633 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9634 struct intel_encoder *intel_encoder =
9635 intel_attached_encoder(connector);
79e53945 9636 struct drm_crtc *possible_crtc;
4ef69c7a 9637 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9638 struct drm_crtc *crtc = NULL;
9639 struct drm_device *dev = encoder->dev;
94352cf9 9640 struct drm_framebuffer *fb;
51fd371b 9641 struct drm_mode_config *config = &dev->mode_config;
83a57153 9642 struct drm_atomic_state *state = NULL;
944b0c76 9643 struct drm_connector_state *connector_state;
51fd371b 9644 int ret, i = -1;
79e53945 9645
d2dff872 9646 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9647 connector->base.id, connector->name,
8e329a03 9648 encoder->base.id, encoder->name);
d2dff872 9649
51fd371b
RC		 9650retry:
9651 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9652 if (ret)
9653 goto fail_unlock;
6e9f798d 9654
79e53945
JB		 9655 /*
9656 * Algorithm gets a little messy:
7a5e4805 9657 *
79e53945
JB		 9658 * - if the connector already has an assigned crtc, use it (but make
9659 * sure it's on first)
7a5e4805 9660 *
79e53945
JB		 9661 * - try to find the first unused crtc that can drive this connector,
9662 * and use that if we find one
79e53945
JB		 9663 */
9664
9665 /* See if we already have a CRTC for this connector */
9666 if (encoder->crtc) {
9667 crtc = encoder->crtc;
8261b191 9668
51fd371b 9669 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9670 if (ret)
9671 goto fail_unlock;
9672 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9673 if (ret)
9674 goto fail_unlock;
7b24056b 9675
24218aac 9676 old->dpms_mode = connector->dpms;
8261b191
CW		 9677 old->load_detect_temp = false;
9678
9679 /* Make sure the crtc and connector are running */
24218aac
DV		 9680 if (connector->dpms != DRM_MODE_DPMS_ON)
9681 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9682
7173188d 9683 return true;
79e53945
JB		 9684 }
9685
9686 /* Find an unused one (if possible) */
70e1e0ec 9687 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9688 i++;
9689 if (!(encoder->possible_crtcs & (1 << i)))
9690 continue;
83d65738 9691 if (possible_crtc->state->enable)
a459249c
VS		 9692 continue;
9693 /* This can occur when applying the pipe A quirk on resume. */
9694 if (to_intel_crtc(possible_crtc)->new_enabled)
9695 continue;
9696
9697 crtc = possible_crtc;
9698 break;
79e53945
JB		 9699 }
9700
9701 /*
9702 * If we didn't find an unused CRTC, don't use any.
9703 */
9704 if (!crtc) {
7173188d 9705 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9706 goto fail_unlock;
79e53945
JB		 9707 }
9708
51fd371b
RC		 9709 ret = drm_modeset_lock(&crtc->mutex, ctx);
9710 if (ret)
4d02e2de
DV		 9711 goto fail_unlock;
9712 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9713 if (ret)
51fd371b 9714 goto fail_unlock;
fc303101
DV		 9715 intel_encoder->new_crtc = to_intel_crtc(crtc);
9716 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9717
9718 intel_crtc = to_intel_crtc(crtc);
412b61d8 9719 intel_crtc->new_enabled = true;
24218aac 9720 old->dpms_mode = connector->dpms;
8261b191 9721 old->load_detect_temp = true;
d2dff872 9722 old->release_fb = NULL;
79e53945 9723
83a57153
ACO		 9724 state = drm_atomic_state_alloc(dev);
9725 if (!state)
9726 return false;
9727
9728 state->acquire_ctx = ctx;
9729
944b0c76
ACO		 9730 connector_state = drm_atomic_get_connector_state(state, connector);
9731 if (IS_ERR(connector_state)) {
9732 ret = PTR_ERR(connector_state);
9733 goto fail;
9734 }
9735
9736 connector_state->crtc = crtc;
9737 connector_state->best_encoder = &intel_encoder->base;
9738
6492711d
CW		 9739 if (!mode)
9740 mode = &load_detect_mode;
79e53945 9741
d2dff872
CW		 9742 /* We need a framebuffer large enough to accommodate all accesses
9743 * that the plane may generate whilst we perform load detection.
9744 * We can not rely on the fbcon either being present (we get called
9745 * during its initialisation to detect all boot displays, or it may
9746 * not even exist) or that it is large enough to satisfy the
9747 * requested mode.
9748 */
94352cf9
DV		 9749 fb = mode_fits_in_fbdev(dev, mode);
9750 if (fb == NULL) {
d2dff872 9751 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9752 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9753 old->release_fb = fb;
d2dff872
CW		 9754 } else
9755 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9756 if (IS_ERR(fb)) {
d2dff872 9757 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9758 goto fail;
79e53945 9759 }
79e53945 9760
83a57153 9761 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9762 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9763 if (old->release_fb)
9764 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9765 goto fail;
79e53945 9766 }
9128b040 9767 crtc->primary->crtc = crtc;
7173188d 9768
79e53945 9769 /* let the connector get through one full cycle before testing */
9d0498a2 9770 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9771 return true;
412b61d8
VS		 9772
9773 fail:
83d65738 9774 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9775fail_unlock:
83a57153
ACO		 9776 if (state) {
9777 drm_atomic_state_free(state);
9778 state = NULL;
9779 }
9780
51fd371b
RC		 9781 if (ret == -EDEADLK) {
9782 drm_modeset_backoff(ctx);
9783 goto retry;
9784 }
9785
412b61d8 9786 return false;
79e53945
JB		 9787}
9788
d2434ab7 9789void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9790 struct intel_load_detect_pipe *old,
9791 struct drm_modeset_acquire_ctx *ctx)
79e53945 9792{
83a57153 9793 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9794 struct intel_encoder *intel_encoder =
9795 intel_attached_encoder(connector);
4ef69c7a 9796 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9797 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9799 struct drm_atomic_state *state;
944b0c76 9800 struct drm_connector_state *connector_state;
79e53945 9801
d2dff872 9802 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9803 connector->base.id, connector->name,
8e329a03 9804 encoder->base.id, encoder->name);
d2dff872 9805
8261b191 9806 if (old->load_detect_temp) {
83a57153 9807 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9808 if (!state)
9809 goto fail;
83a57153
ACO		 9810
9811 state->acquire_ctx = ctx;
9812
944b0c76
ACO		 9813 connector_state = drm_atomic_get_connector_state(state, connector);
9814 if (IS_ERR(connector_state))
9815 goto fail;
9816
fc303101
DV		 9817 to_intel_connector(connector)->new_encoder = NULL;
9818 intel_encoder->new_crtc = NULL;
412b61d8 9819 intel_crtc->new_enabled = false;
944b0c76
ACO		 9820
9821 connector_state->best_encoder = NULL;
9822 connector_state->crtc = NULL;
9823
83a57153
ACO		 9824 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9825
9826 drm_atomic_state_free(state);
d2dff872 9827
36206361
DV		 9828 if (old->release_fb) {
9829 drm_framebuffer_unregister_private(old->release_fb);
9830 drm_framebuffer_unreference(old->release_fb);
9831 }
d2dff872 9832
0622a53c 9833 return;
79e53945
JB		 9834 }
9835
c751ce4f 9836 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9837 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9838 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9839
9840 return;
9841fail:
9842 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9843 drm_atomic_state_free(state);
79e53945
JB		 9844}
9845
da4a1efa 9846static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9847 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9848{
9849 struct drm_i915_private *dev_priv = dev->dev_private;
9850 u32 dpll = pipe_config->dpll_hw_state.dpll;
9851
9852 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9853 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9854 else if (HAS_PCH_SPLIT(dev))
9855 return 120000;
9856 else if (!IS_GEN2(dev))
9857 return 96000;
9858 else
9859 return 48000;
9860}
9861
79e53945 9862/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9863static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9864 struct intel_crtc_state *pipe_config)
79e53945 9865{
f1f644dc 9866 struct drm_device *dev = crtc->base.dev;
79e53945 9867 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9868 int pipe = pipe_config->cpu_transcoder;
293623f7 9869 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9870 u32 fp;
9871 intel_clock_t clock;
da4a1efa 9872 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9873
9874 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9875 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9876 else
293623f7 9877 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9878
9879 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9880 if (IS_PINEVIEW(dev)) {
9881 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9882 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9883 } else {
9884 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9885 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9886 }
9887
a6c45cf0 9888 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9889 if (IS_PINEVIEW(dev))
9890 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9891 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9892 else
9893 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9894 DPLL_FPA01_P1_POST_DIV_SHIFT);
9895
9896 switch (dpll & DPLL_MODE_MASK) {
9897 case DPLLB_MODE_DAC_SERIAL:
9898 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9899 5 : 10;
9900 break;
9901 case DPLLB_MODE_LVDS:
9902 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9903 7 : 14;
9904 break;
9905 default:
28c97730 9906 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9907 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9908 return;
79e53945
JB		 9909 }
9910
ac58c3f0 9911 if (IS_PINEVIEW(dev))
da4a1efa 9912 pineview_clock(refclk, &clock);
ac58c3f0 9913 else
da4a1efa 9914 i9xx_clock(refclk, &clock);
79e53945 9915 } else {
0fb58223 9916 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9917 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9918
9919 if (is_lvds) {
9920 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9921 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9922
9923 if (lvds & LVDS_CLKB_POWER_UP)
9924 clock.p2 = 7;
9925 else
9926 clock.p2 = 14;
79e53945
JB		 9927 } else {
9928 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9929 clock.p1 = 2;
9930 else {
9931 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9932 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9933 }
9934 if (dpll & PLL_P2_DIVIDE_BY_4)
9935 clock.p2 = 4;
9936 else
9937 clock.p2 = 2;
79e53945 9938 }
da4a1efa
VS		 9939
9940 i9xx_clock(refclk, &clock);
79e53945
JB		 9941 }
9942
18442d08
VS		 9943 /*
9944 * This value includes pixel_multiplier. We will use
241bfc38 9945 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9946 * encoder's get_config() function.
9947 */
9948 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9949}
9950
6878da05
VS		 9951int intel_dotclock_calculate(int link_freq,
9952 const struct intel_link_m_n *m_n)
f1f644dc 9953{
f1f644dc
JB		 9954 /*
9955 * The calculation for the data clock is:
1041a02f 9956 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9957 * But we want to avoid losing precison if possible, so:
1041a02f 9958 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9959 *
9960 * and the link clock is simpler:
1041a02f 9961 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9962 */
9963
6878da05
VS		 9964 if (!m_n->link_n)
9965 return 0;
f1f644dc 9966
6878da05
VS		 9967 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9968}
f1f644dc 9969
18442d08 9970static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9971 struct intel_crtc_state *pipe_config)
6878da05
VS		 9972{
9973 struct drm_device *dev = crtc->base.dev;
79e53945 9974
18442d08
VS		 9975 /* read out port_clock from the DPLL */
9976 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9977
f1f644dc 9978 /*
18442d08 9979 * This value does not include pixel_multiplier.
241bfc38 9980 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9981 * agree once we know their relationship in the encoder's
9982 * get_config() function.
79e53945 9983 */
2d112de7 9984 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9985 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9986 &pipe_config->fdi_m_n);
79e53945
JB		 9987}
9988
9989/** Returns the currently programmed mode of the given pipe. */
9990struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9991 struct drm_crtc *crtc)
9992{
548f245b 9993 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9995 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9996 struct drm_display_mode *mode;
5cec258b 9997 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9998 int htot = I915_READ(HTOTAL(cpu_transcoder));
9999 int hsync = I915_READ(HSYNC(cpu_transcoder));
10000 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10001 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10002 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10003
10004 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10005 if (!mode)
10006 return NULL;
10007
f1f644dc
JB		 10008 /*
10009 * Construct a pipe_config sufficient for getting the clock info
10010 * back out of crtc_clock_get.
10011 *
10012 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10013 * to use a real value here instead.
10014 */
293623f7 10015 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10016 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10017 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10018 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10019 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10020 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10021
773ae034 10022 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10023 mode->hdisplay = (htot & 0xffff) + 1;
10024 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10025 mode->hsync_start = (hsync & 0xffff) + 1;
10026 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10027 mode->vdisplay = (vtot & 0xffff) + 1;
10028 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10029 mode->vsync_start = (vsync & 0xffff) + 1;
10030 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10031
10032 drm_mode_set_name(mode);
79e53945
JB		 10033
10034 return mode;
10035}
10036
652c393a
JB		 10037static void intel_decrease_pllclock(struct drm_crtc *crtc)
10038{
10039 struct drm_device *dev = crtc->dev;
fbee40df 10040 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10042
baff296c 10043 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10044 return;
10045
10046 if (!dev_priv->lvds_downclock_avail)
10047 return;
10048
10049 /*
10050 * Since this is called by a timer, we should never get here in
10051 * the manual case.
10052 */
10053 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10054 int pipe = intel_crtc->pipe;
10055 int dpll_reg = DPLL(pipe);
10056 int dpll;
f6e5b160 10057
44d98a61 10058 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10059
8ac5a6d5 10060 assert_panel_unlocked(dev_priv, pipe);
652c393a 10061
dc257cf1 10062 dpll = I915_READ(dpll_reg);
652c393a
JB		 10063 dpll |= DISPLAY_RATE_SELECT_FPA1;
10064 I915_WRITE(dpll_reg, dpll);
9d0498a2 10065 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10066 dpll = I915_READ(dpll_reg);
10067 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10068 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10069 }
10070
10071}
10072
f047e395
CW		 10073void intel_mark_busy(struct drm_device *dev)
10074{
c67a470b
PZ		 10075 struct drm_i915_private *dev_priv = dev->dev_private;
10076
f62a0076
CW		 10077 if (dev_priv->mm.busy)
10078 return;
10079
43694d69 10080 intel_runtime_pm_get(dev_priv);
c67a470b 10081 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10082 if (INTEL_INFO(dev)->gen >= 6)
10083 gen6_rps_busy(dev_priv);
f62a0076 10084 dev_priv->mm.busy = true;
f047e395
CW		 10085}
10086
10087void intel_mark_idle(struct drm_device *dev)
652c393a 10088{
c67a470b 10089 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10090 struct drm_crtc *crtc;
652c393a 10091
f62a0076
CW		 10092 if (!dev_priv->mm.busy)
10093 return;
10094
10095 dev_priv->mm.busy = false;
10096
70e1e0ec 10097 for_each_crtc(dev, crtc) {
f4510a27 10098 if (!crtc->primary->fb)
652c393a
JB		 10099 continue;
10100
725a5b54 10101 intel_decrease_pllclock(crtc);
652c393a 10102 }
b29c19b6 10103
3d13ef2e 10104 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10105 gen6_rps_idle(dev->dev_private);
bb4cdd53 10106
43694d69 10107 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10108}
10109
f5de6e07
ACO		 10110static void intel_crtc_set_state(struct intel_crtc *crtc,
10111 struct intel_crtc_state *crtc_state)
10112{
10113 kfree(crtc->config);
10114 crtc->config = crtc_state;
16f3f658 10115 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10116}
10117
79e53945
JB		 10118static void intel_crtc_destroy(struct drm_crtc *crtc)
10119{
10120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10121 struct drm_device *dev = crtc->dev;
10122 struct intel_unpin_work *work;
67e77c5a 10123
5e2d7afc 10124 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10125 work = intel_crtc->unpin_work;
10126 intel_crtc->unpin_work = NULL;
5e2d7afc 10127 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10128
10129 if (work) {
10130 cancel_work_sync(&work->work);
10131 kfree(work);
10132 }
79e53945 10133
f5de6e07 10134 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10135 drm_crtc_cleanup(crtc);
67e77c5a 10136
79e53945
JB		 10137 kfree(intel_crtc);
10138}
10139
6b95a207
KH		 10140static void intel_unpin_work_fn(struct work_struct *__work)
10141{
10142 struct intel_unpin_work *work =
10143 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10144 struct drm_device *dev = work->crtc->dev;
f99d7069 10145 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10146
b4a98e57 10147 mutex_lock(&dev->struct_mutex);
82bc3b2d 10148 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10149 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10150
7ff0ebcc 10151 intel_fbc_update(dev);
f06cc1b9
JH		 10152
10153 if (work->flip_queued_req)
146d84f0 10154 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10155 mutex_unlock(&dev->struct_mutex);
10156
f99d7069 10157 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10158 drm_framebuffer_unreference(work->old_fb);
f99d7069 10159
b4a98e57
CW		 10160 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10161 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10162
6b95a207
KH		 10163 kfree(work);
10164}
10165
1afe3e9d 10166static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10167 struct drm_crtc *crtc)
6b95a207 10168{
6b95a207
KH		 10169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10170 struct intel_unpin_work *work;
6b95a207
KH		 10171 unsigned long flags;
10172
10173 /* Ignore early vblank irqs */
10174 if (intel_crtc == NULL)
10175 return;
10176
f326038a
DV		 10177 /*
10178 * This is called both by irq handlers and the reset code (to complete
10179 * lost pageflips) so needs the full irqsave spinlocks.
10180 */
6b95a207
KH		 10181 spin_lock_irqsave(&dev->event_lock, flags);
10182 work = intel_crtc->unpin_work;
e7d841ca
CW		 10183
10184 /* Ensure we don't miss a work->pending update ... */
10185 smp_rmb();
10186
10187 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10188 spin_unlock_irqrestore(&dev->event_lock, flags);
10189 return;
10190 }
10191
d6bbafa1 10192 page_flip_completed(intel_crtc);
0af7e4df 10193
6b95a207 10194 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10195}
10196
1afe3e9d
JB		 10197void intel_finish_page_flip(struct drm_device *dev, int pipe)
10198{
fbee40df 10199 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10200 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10201
49b14a5c 10202 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10203}
10204
10205void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10206{
fbee40df 10207 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10208 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10209
49b14a5c 10210 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10211}
10212
75f7f3ec
VS		 10213/* Is 'a' after or equal to 'b'? */
10214static bool g4x_flip_count_after_eq(u32 a, u32 b)
10215{
10216 return !((a - b) & 0x80000000);
10217}
10218
10219static bool page_flip_finished(struct intel_crtc *crtc)
10220{
10221 struct drm_device *dev = crtc->base.dev;
10222 struct drm_i915_private *dev_priv = dev->dev_private;
10223
bdfa7542
VS		 10224 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10225 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10226 return true;
10227
75f7f3ec
VS		 10228 /*
10229 * The relevant registers doen't exist on pre-ctg.
10230 * As the flip done interrupt doesn't trigger for mmio
10231 * flips on gmch platforms, a flip count check isn't
10232 * really needed there. But since ctg has the registers,
10233 * include it in the check anyway.
10234 */
10235 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10236 return true;
10237
10238 /*
10239 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10240 * used the same base address. In that case the mmio flip might
10241 * have completed, but the CS hasn't even executed the flip yet.
10242 *
10243 * A flip count check isn't enough as the CS might have updated
10244 * the base address just after start of vblank, but before we
10245 * managed to process the interrupt. This means we'd complete the
10246 * CS flip too soon.
10247 *
10248 * Combining both checks should get us a good enough result. It may
10249 * still happen that the CS flip has been executed, but has not
10250 * yet actually completed. But in case the base address is the same
10251 * anyway, we don't really care.
10252 */
10253 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10254 crtc->unpin_work->gtt_offset &&
10255 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10256 crtc->unpin_work->flip_count);
10257}
10258
6b95a207
KH		 10259void intel_prepare_page_flip(struct drm_device *dev, int plane)
10260{
fbee40df 10261 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10262 struct intel_crtc *intel_crtc =
10263 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10264 unsigned long flags;
10265
f326038a
DV		 10266
10267 /*
10268 * This is called both by irq handlers and the reset code (to complete
10269 * lost pageflips) so needs the full irqsave spinlocks.
10270 *
10271 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10272 * generate a page-flip completion irq, i.e. every modeset
10273 * is also accompanied by a spurious intel_prepare_page_flip().
10274 */
6b95a207 10275 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10276 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10277 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10278 spin_unlock_irqrestore(&dev->event_lock, flags);
10279}
10280
eba905b2 10281static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10282{
10283 /* Ensure that the work item is consistent when activating it ... */
10284 smp_wmb();
10285 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10286 /* and that it is marked active as soon as the irq could fire. */
10287 smp_wmb();
10288}
10289
8c9f3aaf
JB		 10290static int intel_gen2_queue_flip(struct drm_device *dev,
10291 struct drm_crtc *crtc,
10292 struct drm_framebuffer *fb,
ed8d1975 10293 struct drm_i915_gem_object *obj,
a4872ba6 10294 struct intel_engine_cs *ring,
ed8d1975 10295 uint32_t flags)
8c9f3aaf 10296{
8c9f3aaf 10297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10298 u32 flip_mask;
10299 int ret;
10300
6d90c952 10301 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10302 if (ret)
4fa62c89 10303 return ret;
8c9f3aaf
JB		 10304
10305 /* Can't queue multiple flips, so wait for the previous
10306 * one to finish before executing the next.
10307 */
10308 if (intel_crtc->plane)
10309 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10310 else
10311 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10312 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10313 intel_ring_emit(ring, MI_NOOP);
10314 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10315 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10316 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10317 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10318 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10319
10320 intel_mark_page_flip_active(intel_crtc);
09246732 10321 __intel_ring_advance(ring);
83d4092b 10322 return 0;
8c9f3aaf
JB		 10323}
10324
10325static int intel_gen3_queue_flip(struct drm_device *dev,
10326 struct drm_crtc *crtc,
10327 struct drm_framebuffer *fb,
ed8d1975 10328 struct drm_i915_gem_object *obj,
a4872ba6 10329 struct intel_engine_cs *ring,
ed8d1975 10330 uint32_t flags)
8c9f3aaf 10331{
8c9f3aaf 10332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10333 u32 flip_mask;
10334 int ret;
10335
6d90c952 10336 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10337 if (ret)
4fa62c89 10338 return ret;
8c9f3aaf
JB		 10339
10340 if (intel_crtc->plane)
10341 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10342 else
10343 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10344 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10345 intel_ring_emit(ring, MI_NOOP);
10346 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10347 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10348 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10349 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10350 intel_ring_emit(ring, MI_NOOP);
10351
e7d841ca 10352 intel_mark_page_flip_active(intel_crtc);
09246732 10353 __intel_ring_advance(ring);
83d4092b 10354 return 0;
8c9f3aaf
JB		 10355}
10356
10357static int intel_gen4_queue_flip(struct drm_device *dev,
10358 struct drm_crtc *crtc,
10359 struct drm_framebuffer *fb,
ed8d1975 10360 struct drm_i915_gem_object *obj,
a4872ba6 10361 struct intel_engine_cs *ring,
ed8d1975 10362 uint32_t flags)
8c9f3aaf
JB		 10363{
10364 struct drm_i915_private *dev_priv = dev->dev_private;
10365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10366 uint32_t pf, pipesrc;
10367 int ret;
10368
6d90c952 10369 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10370 if (ret)
4fa62c89 10371 return ret;
8c9f3aaf
JB		 10372
10373 /* i965+ uses the linear or tiled offsets from the
10374 * Display Registers (which do not change across a page-flip)
10375 * so we need only reprogram the base address.
10376 */
6d90c952
DV		 10377 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10378 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10379 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10380 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10381 obj->tiling_mode);
8c9f3aaf
JB		 10382
10383 /* XXX Enabling the panel-fitter across page-flip is so far
10384 * untested on non-native modes, so ignore it for now.
10385 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10386 */
10387 pf = 0;
10388 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10389 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10390
10391 intel_mark_page_flip_active(intel_crtc);
09246732 10392 __intel_ring_advance(ring);
83d4092b 10393 return 0;
8c9f3aaf
JB		 10394}
10395
10396static int intel_gen6_queue_flip(struct drm_device *dev,
10397 struct drm_crtc *crtc,
10398 struct drm_framebuffer *fb,
ed8d1975 10399 struct drm_i915_gem_object *obj,
a4872ba6 10400 struct intel_engine_cs *ring,
ed8d1975 10401 uint32_t flags)
8c9f3aaf
JB		 10402{
10403 struct drm_i915_private *dev_priv = dev->dev_private;
10404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10405 uint32_t pf, pipesrc;
10406 int ret;
10407
6d90c952 10408 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10409 if (ret)
4fa62c89 10410 return ret;
8c9f3aaf 10411
6d90c952
DV		 10412 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10413 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10414 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10415 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10416
dc257cf1
DV		 10417 /* Contrary to the suggestions in the documentation,
10418 * "Enable Panel Fitter" does not seem to be required when page
10419 * flipping with a non-native mode, and worse causes a normal
10420 * modeset to fail.
10421 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10422 */
10423 pf = 0;
8c9f3aaf 10424 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10425 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10426
10427 intel_mark_page_flip_active(intel_crtc);
09246732 10428 __intel_ring_advance(ring);
83d4092b 10429 return 0;
8c9f3aaf
JB		 10430}
10431
7c9017e5
JB		 10432static int intel_gen7_queue_flip(struct drm_device *dev,
10433 struct drm_crtc *crtc,
10434 struct drm_framebuffer *fb,
ed8d1975 10435 struct drm_i915_gem_object *obj,
a4872ba6 10436 struct intel_engine_cs *ring,
ed8d1975 10437 uint32_t flags)
7c9017e5 10438{
7c9017e5 10439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10440 uint32_t plane_bit = 0;
ffe74d75
CW		 10441 int len, ret;
10442
eba905b2 10443 switch (intel_crtc->plane) {
cb05d8de
DV		 10444 case PLANE_A:
10445 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10446 break;
10447 case PLANE_B:
10448 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10449 break;
10450 case PLANE_C:
10451 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10452 break;
10453 default:
10454 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10455 return -ENODEV;
cb05d8de
DV		 10456 }
10457
ffe74d75 10458 len = 4;
f476828a 10459 if (ring->id == RCS) {
ffe74d75 10460 len += 6;
f476828a
DL		 10461 /*
10462 * On Gen 8, SRM is now taking an extra dword to accommodate
10463 * 48bits addresses, and we need a NOOP for the batch size to
10464 * stay even.
10465 */
10466 if (IS_GEN8(dev))
10467 len += 2;
10468 }
ffe74d75 10469
f66fab8e
VS		 10470 /*
10471 * BSpec MI_DISPLAY_FLIP for IVB:
10472 * "The full packet must be contained within the same cache line."
10473 *
10474 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10475 * cacheline, if we ever start emitting more commands before
10476 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10477 * then do the cacheline alignment, and finally emit the
10478 * MI_DISPLAY_FLIP.
10479 */
10480 ret = intel_ring_cacheline_align(ring);
10481 if (ret)
4fa62c89 10482 return ret;
f66fab8e 10483
ffe74d75 10484 ret = intel_ring_begin(ring, len);
7c9017e5 10485 if (ret)
4fa62c89 10486 return ret;
7c9017e5 10487
ffe74d75
CW		 10488 /* Unmask the flip-done completion message. Note that the bspec says that
10489 * we should do this for both the BCS and RCS, and that we must not unmask
10490 * more than one flip event at any time (or ensure that one flip message
10491 * can be sent by waiting for flip-done prior to queueing new flips).
10492 * Experimentation says that BCS works despite DERRMR masking all
10493 * flip-done completion events and that unmasking all planes at once
10494 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10495 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10496 */
10497 if (ring->id == RCS) {
10498 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10499 intel_ring_emit(ring, DERRMR);
10500 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10501 DERRMR_PIPEB_PRI_FLIP_DONE |
10502 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10503 if (IS_GEN8(dev))
10504 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10505 MI_SRM_LRM_GLOBAL_GTT);
10506 else
10507 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10508 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10509 intel_ring_emit(ring, DERRMR);
10510 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10511 if (IS_GEN8(dev)) {
10512 intel_ring_emit(ring, 0);
10513 intel_ring_emit(ring, MI_NOOP);
10514 }
ffe74d75
CW		 10515 }
10516
cb05d8de 10517 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10518 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10519 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10520 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10521
10522 intel_mark_page_flip_active(intel_crtc);
09246732 10523 __intel_ring_advance(ring);
83d4092b 10524 return 0;
7c9017e5
JB		 10525}
10526
84c33a64
SG		 10527static bool use_mmio_flip(struct intel_engine_cs *ring,
10528 struct drm_i915_gem_object *obj)
10529{
10530 /*
10531 * This is not being used for older platforms, because
10532 * non-availability of flip done interrupt forces us to use
10533 * CS flips. Older platforms derive flip done using some clever
10534 * tricks involving the flip_pending status bits and vblank irqs.
10535 * So using MMIO flips there would disrupt this mechanism.
10536 */
10537
8e09bf83
CW		 10538 if (ring == NULL)
10539 return true;
10540
84c33a64
SG		 10541 if (INTEL_INFO(ring->dev)->gen < 5)
10542 return false;
10543
10544 if (i915.use_mmio_flip < 0)
10545 return false;
10546 else if (i915.use_mmio_flip > 0)
10547 return true;
14bf993e
OM		 10548 else if (i915.enable_execlists)
10549 return true;
84c33a64 10550 else
41c52415 10551 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10552}
10553
ff944564
DL		 10554static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10555{
10556 struct drm_device *dev = intel_crtc->base.dev;
10557 struct drm_i915_private *dev_priv = dev->dev_private;
10558 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10559 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10560 struct drm_i915_gem_object *obj = intel_fb->obj;
10561 const enum pipe pipe = intel_crtc->pipe;
10562 u32 ctl, stride;
10563
10564 ctl = I915_READ(PLANE_CTL(pipe, 0));
10565 ctl &= ~PLANE_CTL_TILED_MASK;
10566 if (obj->tiling_mode == I915_TILING_X)
10567 ctl |= PLANE_CTL_TILED_X;
10568
10569 /*
10570 * The stride is either expressed as a multiple of 64 bytes chunks for
10571 * linear buffers or in number of tiles for tiled buffers.
10572 */
10573 stride = fb->pitches[0] >> 6;
10574 if (obj->tiling_mode == I915_TILING_X)
10575 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10576
10577 /*
10578 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10579 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10580 */
10581 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10582 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10583
10584 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10585 POSTING_READ(PLANE_SURF(pipe, 0));
10586}
10587
10588static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10589{
10590 struct drm_device *dev = intel_crtc->base.dev;
10591 struct drm_i915_private *dev_priv = dev->dev_private;
10592 struct intel_framebuffer *intel_fb =
10593 to_intel_framebuffer(intel_crtc->base.primary->fb);
10594 struct drm_i915_gem_object *obj = intel_fb->obj;
10595 u32 dspcntr;
10596 u32 reg;
10597
84c33a64
SG		 10598 reg = DSPCNTR(intel_crtc->plane);
10599 dspcntr = I915_READ(reg);
10600
c5d97472
DL		 10601 if (obj->tiling_mode != I915_TILING_NONE)
10602 dspcntr |= DISPPLANE_TILED;
10603 else
10604 dspcntr &= ~DISPPLANE_TILED;
10605
84c33a64
SG		 10606 I915_WRITE(reg, dspcntr);
10607
10608 I915_WRITE(DSPSURF(intel_crtc->plane),
10609 intel_crtc->unpin_work->gtt_offset);
10610 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10611
ff944564
DL		 10612}
10613
10614/*
10615 * XXX: This is the temporary way to update the plane registers until we get
10616 * around to using the usual plane update functions for MMIO flips
10617 */
10618static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10619{
10620 struct drm_device *dev = intel_crtc->base.dev;
10621 bool atomic_update;
10622 u32 start_vbl_count;
10623
10624 intel_mark_page_flip_active(intel_crtc);
10625
10626 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10627
10628 if (INTEL_INFO(dev)->gen >= 9)
10629 skl_do_mmio_flip(intel_crtc);
10630 else
10631 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10632 ilk_do_mmio_flip(intel_crtc);
10633
9362c7c5
ACO		 10634 if (atomic_update)
10635 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10636}
10637
9362c7c5 10638static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10639{
cc8c4cc2 10640 struct intel_crtc *crtc =
9362c7c5 10641 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10642 struct intel_mmio_flip *mmio_flip;
84c33a64 10643
cc8c4cc2
JH		 10644 mmio_flip = &crtc->mmio_flip;
10645 if (mmio_flip->req)
9c654818
JH		 10646 WARN_ON(__i915_wait_request(mmio_flip->req,
10647 crtc->reset_counter,
10648 false, NULL, NULL) != 0);
84c33a64 10649
cc8c4cc2
JH		 10650 intel_do_mmio_flip(crtc);
10651 if (mmio_flip->req) {
10652 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10653 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10654 mutex_unlock(&crtc->base.dev->struct_mutex);
10655 }
84c33a64
SG		 10656}
10657
10658static int intel_queue_mmio_flip(struct drm_device *dev,
10659 struct drm_crtc *crtc,
10660 struct drm_framebuffer *fb,
10661 struct drm_i915_gem_object *obj,
10662 struct intel_engine_cs *ring,
10663 uint32_t flags)
10664{
84c33a64 10665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10666
cc8c4cc2
JH		 10667 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10668 obj->last_write_req);
536f5b5e
ACO		 10669
10670 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10671
84c33a64
SG		 10672 return 0;
10673}
10674
8c9f3aaf
JB		 10675static int intel_default_queue_flip(struct drm_device *dev,
10676 struct drm_crtc *crtc,
10677 struct drm_framebuffer *fb,
ed8d1975 10678 struct drm_i915_gem_object *obj,
a4872ba6 10679 struct intel_engine_cs *ring,
ed8d1975 10680 uint32_t flags)
8c9f3aaf
JB		 10681{
10682 return -ENODEV;
10683}
10684
d6bbafa1
CW		 10685static bool __intel_pageflip_stall_check(struct drm_device *dev,
10686 struct drm_crtc *crtc)
10687{
10688 struct drm_i915_private *dev_priv = dev->dev_private;
10689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10690 struct intel_unpin_work *work = intel_crtc->unpin_work;
10691 u32 addr;
10692
10693 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10694 return true;
10695
10696 if (!work->enable_stall_check)
10697 return false;
10698
10699 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10700 if (work->flip_queued_req &&
10701 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10702 return false;
10703
1e3feefd 10704 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10705 }
10706
1e3feefd 10707 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10708 return false;
10709
10710 /* Potential stall - if we see that the flip has happened,
10711 * assume a missed interrupt. */
10712 if (INTEL_INFO(dev)->gen >= 4)
10713 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10714 else
10715 addr = I915_READ(DSPADDR(intel_crtc->plane));
10716
10717 /* There is a potential issue here with a false positive after a flip
10718 * to the same address. We could address this by checking for a
10719 * non-incrementing frame counter.
10720 */
10721 return addr == work->gtt_offset;
10722}
10723
10724void intel_check_page_flip(struct drm_device *dev, int pipe)
10725{
10726 struct drm_i915_private *dev_priv = dev->dev_private;
10727 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10729 struct intel_unpin_work *work;
f326038a 10730
6c51d46f 10731 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10732
10733 if (crtc == NULL)
10734 return;
10735
f326038a 10736 spin_lock(&dev->event_lock);
6ad790c0
CW		 10737 work = intel_crtc->unpin_work;
10738 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10739 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10740 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10741 page_flip_completed(intel_crtc);
6ad790c0 10742 work = NULL;
d6bbafa1 10743 }
6ad790c0
CW		 10744 if (work != NULL &&
10745 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10746 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10747 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10748}
10749
6b95a207
KH		 10750static int intel_crtc_page_flip(struct drm_crtc *crtc,
10751 struct drm_framebuffer *fb,
ed8d1975
KP		 10752 struct drm_pending_vblank_event *event,
10753 uint32_t page_flip_flags)
6b95a207
KH		 10754{
10755 struct drm_device *dev = crtc->dev;
10756 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10757 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10758 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10760 struct drm_plane *primary = crtc->primary;
a071fa00 10761 enum pipe pipe = intel_crtc->pipe;
6b95a207 10762 struct intel_unpin_work *work;
a4872ba6 10763 struct intel_engine_cs *ring;
cf5d8a46 10764 bool mmio_flip;
52e68630 10765 int ret;
6b95a207 10766
2ff8fde1
MR		 10767 /*
10768 * drm_mode_page_flip_ioctl() should already catch this, but double
10769 * check to be safe. In the future we may enable pageflipping from
10770 * a disabled primary plane.
10771 */
10772 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10773 return -EBUSY;
10774
e6a595d2 10775 /* Can't change pixel format via MI display flips. */
f4510a27 10776 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10777 return -EINVAL;
10778
10779 /*
10780 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10781 * Note that pitch changes could also affect these register.
10782 */
10783 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10784 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10785 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10786 return -EINVAL;
10787
f900db47
CW		 10788 if (i915_terminally_wedged(&dev_priv->gpu_error))
10789 goto out_hang;
10790
b14c5679 10791 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10792 if (work == NULL)
10793 return -ENOMEM;
10794
6b95a207 10795 work->event = event;
b4a98e57 10796 work->crtc = crtc;
ab8d6675 10797 work->old_fb = old_fb;
6b95a207
KH		 10798 INIT_WORK(&work->work, intel_unpin_work_fn);
10799
87b6b101 10800 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10801 if (ret)
10802 goto free_work;
10803
6b95a207 10804 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10805 spin_lock_irq(&dev->event_lock);
6b95a207 10806 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10807 /* Before declaring the flip queue wedged, check if
10808 * the hardware completed the operation behind our backs.
10809 */
10810 if (__intel_pageflip_stall_check(dev, crtc)) {
10811 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10812 page_flip_completed(intel_crtc);
10813 } else {
10814 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10815 spin_unlock_irq(&dev->event_lock);
468f0b44 10816
d6bbafa1
CW		 10817 drm_crtc_vblank_put(crtc);
10818 kfree(work);
10819 return -EBUSY;
10820 }
6b95a207
KH		 10821 }
10822 intel_crtc->unpin_work = work;
5e2d7afc 10823 spin_unlock_irq(&dev->event_lock);
6b95a207 10824
b4a98e57
CW		 10825 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10826 flush_workqueue(dev_priv->wq);
10827
75dfca80 10828 /* Reference the objects for the scheduled work. */
ab8d6675 10829 drm_framebuffer_reference(work->old_fb);
05394f39 10830 drm_gem_object_reference(&obj->base);
6b95a207 10831
f4510a27 10832 crtc->primary->fb = fb;
afd65eb4 10833 update_state_fb(crtc->primary);
1ed1f968 10834
e1f99ce6 10835 work->pending_flip_obj = obj;
e1f99ce6 10836
89ed88ba
CW		 10837 ret = i915_mutex_lock_interruptible(dev);
10838 if (ret)
10839 goto cleanup;
10840
b4a98e57 10841 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10842 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10843
75f7f3ec 10844 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10845 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10846
4fa62c89
VS		 10847 if (IS_VALLEYVIEW(dev)) {
10848 ring = &dev_priv->ring[BCS];
ab8d6675 10849 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10850 /* vlv: DISPLAY_FLIP fails to change tiling */
10851 ring = NULL;
48bf5b2d 10852 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10853 ring = &dev_priv->ring[BCS];
4fa62c89 10854 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10855 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10856 if (ring == NULL || ring->id != RCS)
10857 ring = &dev_priv->ring[BCS];
10858 } else {
10859 ring = &dev_priv->ring[RCS];
10860 }
10861
cf5d8a46
CW		 10862 mmio_flip = use_mmio_flip(ring, obj);
10863
10864 /* When using CS flips, we want to emit semaphores between rings.
10865 * However, when using mmio flips we will create a task to do the
10866 * synchronisation, so all we want here is to pin the framebuffer
10867 * into the display plane and skip any waits.
10868 */
82bc3b2d 10869 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10870 crtc->primary->state,
10871 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10872 if (ret)
10873 goto cleanup_pending;
6b95a207 10874
121920fa
TU		 10875 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10876 + intel_crtc->dspaddr_offset;
4fa62c89 10877
cf5d8a46 10878 if (mmio_flip) {
84c33a64
SG		 10879 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10880 page_flip_flags);
d6bbafa1
CW		 10881 if (ret)
10882 goto cleanup_unpin;
10883
f06cc1b9
JH		 10884 i915_gem_request_assign(&work->flip_queued_req,
10885 obj->last_write_req);
d6bbafa1 10886 } else {
84c33a64 10887 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10888 page_flip_flags);
10889 if (ret)
10890 goto cleanup_unpin;
10891
f06cc1b9
JH		 10892 i915_gem_request_assign(&work->flip_queued_req,
10893 intel_ring_get_request(ring));
d6bbafa1
CW		 10894 }
10895
1e3feefd 10896 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10897 work->enable_stall_check = true;
4fa62c89 10898
ab8d6675 10899 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10900 INTEL_FRONTBUFFER_PRIMARY(pipe));
10901
7ff0ebcc 10902 intel_fbc_disable(dev);
f99d7069 10903 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10904 mutex_unlock(&dev->struct_mutex);
10905
e5510fac
JB		 10906 trace_i915_flip_request(intel_crtc->plane, obj);
10907
6b95a207 10908 return 0;
96b099fd 10909
4fa62c89 10910cleanup_unpin:
82bc3b2d 10911 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10912cleanup_pending:
b4a98e57 10913 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10914 mutex_unlock(&dev->struct_mutex);
10915cleanup:
f4510a27 10916 crtc->primary->fb = old_fb;
afd65eb4 10917 update_state_fb(crtc->primary);
89ed88ba
CW		 10918
10919 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10920 drm_framebuffer_unreference(work->old_fb);
96b099fd 10921
5e2d7afc 10922 spin_lock_irq(&dev->event_lock);
96b099fd 10923 intel_crtc->unpin_work = NULL;
5e2d7afc 10924 spin_unlock_irq(&dev->event_lock);
96b099fd 10925
87b6b101 10926 drm_crtc_vblank_put(crtc);
7317c75e 10927free_work:
96b099fd
CW		 10928 kfree(work);
10929
f900db47
CW		 10930 if (ret == -EIO) {
10931out_hang:
53a366b9 10932 ret = intel_plane_restore(primary);
f0d3dad3 10933 if (ret == 0 && event) {
5e2d7afc 10934 spin_lock_irq(&dev->event_lock);
a071fa00 10935 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10936 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10937 }
f900db47 10938 }
96b099fd 10939 return ret;
6b95a207
KH		 10940}
10941
f6e5b160 10942static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10943 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10944 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10945 .atomic_begin = intel_begin_crtc_commit,
10946 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10947};
10948
9a935856
DV		 10949/**
10950 * intel_modeset_update_staged_output_state
10951 *
10952 * Updates the staged output configuration state, e.g. after we've read out the
10953 * current hw state.
10954 */
10955static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10956{
7668851f 10957 struct intel_crtc *crtc;
9a935856
DV		 10958 struct intel_encoder *encoder;
10959 struct intel_connector *connector;
f6e5b160 10960
3a3371ff 10961 for_each_intel_connector(dev, connector) {
9a935856
DV		 10962 connector->new_encoder =
10963 to_intel_encoder(connector->base.encoder);
10964 }
f6e5b160 10965
b2784e15 10966 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10967 encoder->new_crtc =
10968 to_intel_crtc(encoder->base.crtc);
10969 }
7668851f 10970
d3fcc808 10971 for_each_intel_crtc(dev, crtc) {
83d65738 10972 crtc->new_enabled = crtc->base.state->enable;
7668851f 10973 }
f6e5b160
CW		 10974}
10975
d29b2f9d
ACO		 10976/* Transitional helper to copy current connector/encoder state to
10977 * connector->state. This is needed so that code that is partially
10978 * converted to atomic does the right thing.
10979 */
10980static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10981{
10982 struct intel_connector *connector;
10983
10984 for_each_intel_connector(dev, connector) {
10985 if (connector->base.encoder) {
10986 connector->base.state->best_encoder =
10987 connector->base.encoder;
10988 connector->base.state->crtc =
10989 connector->base.encoder->crtc;
10990 } else {
10991 connector->base.state->best_encoder = NULL;
10992 connector->base.state->crtc = NULL;
10993 }
10994 }
10995}
10996
9a935856
DV		 10997/**
10998 * intel_modeset_commit_output_state
10999 *
11000 * This function copies the stage display pipe configuration to the real one.
11001 */
11002static void intel_modeset_commit_output_state(struct drm_device *dev)
11003{
7668851f 11004 struct intel_crtc *crtc;
9a935856
DV		 11005 struct intel_encoder *encoder;
11006 struct intel_connector *connector;
f6e5b160 11007
3a3371ff 11008 for_each_intel_connector(dev, connector) {
9a935856
DV		 11009 connector->base.encoder = &connector->new_encoder->base;
11010 }
f6e5b160 11011
b2784e15 11012 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11013 encoder->base.crtc = &encoder->new_crtc->base;
11014 }
7668851f 11015
d3fcc808 11016 for_each_intel_crtc(dev, crtc) {
83d65738 11017 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 11018 crtc->base.enabled = crtc->new_enabled;
11019 }
d29b2f9d
ACO		 11020
11021 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 11022}
11023
050f7aeb 11024static void
eba905b2 11025connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11026 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11027{
11028 int bpp = pipe_config->pipe_bpp;
11029
11030 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11031 connector->base.base.id,
c23cc417 11032 connector->base.name);
050f7aeb
DV		 11033
11034 /* Don't use an invalid EDID bpc value */
11035 if (connector->base.display_info.bpc &&
11036 connector->base.display_info.bpc * 3 < bpp) {
11037 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11038 bpp, connector->base.display_info.bpc*3);
11039 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11040 }
11041
11042 /* Clamp bpp to 8 on screens without EDID 1.4 */
11043 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11044 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11045 bpp);
11046 pipe_config->pipe_bpp = 24;
11047 }
11048}
11049
4e53c2e0 11050static int
050f7aeb 11051compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11052 struct intel_crtc_state *pipe_config)
4e53c2e0 11053{
050f7aeb 11054 struct drm_device *dev = crtc->base.dev;
1486017f 11055 struct drm_atomic_state *state;
050f7aeb 11056 struct intel_connector *connector;
1486017f 11057 int bpp, i;
4e53c2e0 11058
d328c9d7 11059 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11060 bpp = 10*3;
d328c9d7
DV		 11061 else if (INTEL_INFO(dev)->gen >= 5)
11062 bpp = 12*3;
11063 else
11064 bpp = 8*3;
11065
4e53c2e0 11066
4e53c2e0
DV		 11067 pipe_config->pipe_bpp = bpp;
11068
1486017f
ACO		 11069 state = pipe_config->base.state;
11070
4e53c2e0 11071 /* Clamp display bpp to EDID value */
1486017f
ACO		 11072 for (i = 0; i < state->num_connector; i++) {
11073 if (!state->connectors[i])
11074 continue;
11075
11076 connector = to_intel_connector(state->connectors[i]);
11077 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 11078 continue;
11079
050f7aeb 11080 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 11081 }
11082
11083 return bpp;
11084}
11085
644db711
DV		 11086static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11087{
11088 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11089 "type: 0x%x flags: 0x%x\n",
1342830c 11090 mode->crtc_clock,
644db711
DV		 11091 mode->crtc_hdisplay, mode->crtc_hsync_start,
11092 mode->crtc_hsync_end, mode->crtc_htotal,
11093 mode->crtc_vdisplay, mode->crtc_vsync_start,
11094 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11095}
11096
c0b03411 11097static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11098 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11099 const char *context)
11100{
6a60cd87
CK		 11101 struct drm_device *dev = crtc->base.dev;
11102 struct drm_plane *plane;
11103 struct intel_plane *intel_plane;
11104 struct intel_plane_state *state;
11105 struct drm_framebuffer *fb;
11106
11107 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11108 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11109
11110 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11111 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11112 pipe_config->pipe_bpp, pipe_config->dither);
11113 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11114 pipe_config->has_pch_encoder,
11115 pipe_config->fdi_lanes,
11116 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11117 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11118 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11119 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11120 pipe_config->has_dp_encoder,
11121 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11122 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11123 pipe_config->dp_m_n.tu);
b95af8be
VK		 11124
11125 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11126 pipe_config->has_dp_encoder,
11127 pipe_config->dp_m2_n2.gmch_m,
11128 pipe_config->dp_m2_n2.gmch_n,
11129 pipe_config->dp_m2_n2.link_m,
11130 pipe_config->dp_m2_n2.link_n,
11131 pipe_config->dp_m2_n2.tu);
11132
55072d19
DV		 11133 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11134 pipe_config->has_audio,
11135 pipe_config->has_infoframe);
11136
c0b03411 11137 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11138 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11139 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11140 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11141 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11142 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11143 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11144 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11145 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11146 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11147 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11148 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11149 pipe_config->gmch_pfit.control,
11150 pipe_config->gmch_pfit.pgm_ratios,
11151 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11152 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11153 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11154 pipe_config->pch_pfit.size,
11155 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11156 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11157 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11158
11159 DRM_DEBUG_KMS("planes on this crtc\n");
11160 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11161 intel_plane = to_intel_plane(plane);
11162 if (intel_plane->pipe != crtc->pipe)
11163 continue;
11164
11165 state = to_intel_plane_state(plane->state);
11166 fb = state->base.fb;
11167 if (!fb) {
11168 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11169 "disabled, scaler_id = %d\n",
11170 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11171 plane->base.id, intel_plane->pipe,
11172 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11173 drm_plane_index(plane), state->scaler_id);
11174 continue;
11175 }
11176
11177 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11178 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11179 plane->base.id, intel_plane->pipe,
11180 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11181 drm_plane_index(plane));
11182 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11183 fb->base.id, fb->width, fb->height, fb->pixel_format);
11184 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11185 state->scaler_id,
11186 state->src.x1 >> 16, state->src.y1 >> 16,
11187 drm_rect_width(&state->src) >> 16,
11188 drm_rect_height(&state->src) >> 16,
11189 state->dst.x1, state->dst.y1,
11190 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11191 }
c0b03411
DV		 11192}
11193
bc079e8b
VS		 11194static bool encoders_cloneable(const struct intel_encoder *a,
11195 const struct intel_encoder *b)
accfc0c5 11196{
bc079e8b
VS		 11197 /* masks could be asymmetric, so check both ways */
11198 return a == b || (a->cloneable & (1 << b->type) &&
11199 b->cloneable & (1 << a->type));
11200}
11201
98a221da
ACO		 11202static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11203 struct intel_crtc *crtc,
bc079e8b
VS		 11204 struct intel_encoder *encoder)
11205{
bc079e8b 11206 struct intel_encoder *source_encoder;
98a221da
ACO		 11207 struct drm_connector_state *connector_state;
11208 int i;
11209
11210 for (i = 0; i < state->num_connector; i++) {
11211 if (!state->connectors[i])
11212 continue;
bc079e8b 11213
98a221da
ACO		 11214 connector_state = state->connector_states[i];
11215 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11216 continue;
11217
98a221da
ACO		 11218 source_encoder =
11219 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11220 if (!encoders_cloneable(encoder, source_encoder))
11221 return false;
11222 }
11223
11224 return true;
11225}
11226
98a221da
ACO		 11227static bool check_encoder_cloning(struct drm_atomic_state *state,
11228 struct intel_crtc *crtc)
bc079e8b 11229{
accfc0c5 11230 struct intel_encoder *encoder;
98a221da
ACO		 11231 struct drm_connector_state *connector_state;
11232 int i;
accfc0c5 11233
98a221da
ACO		 11234 for (i = 0; i < state->num_connector; i++) {
11235 if (!state->connectors[i])
accfc0c5
DV		 11236 continue;
11237
98a221da
ACO		 11238 connector_state = state->connector_states[i];
11239 if (connector_state->crtc != &crtc->base)
11240 continue;
11241
11242 encoder = to_intel_encoder(connector_state->best_encoder);
11243 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11244 return false;
accfc0c5
DV		 11245 }
11246
bc079e8b 11247 return true;
accfc0c5
DV		 11248}
11249
5448a00d 11250static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11251{
5448a00d
ACO		 11252 struct drm_device *dev = state->dev;
11253 struct intel_encoder *encoder;
11254 struct drm_connector_state *connector_state;
00f0b378 11255 unsigned int used_ports = 0;
5448a00d 11256 int i;
00f0b378
VS		 11257
11258 /*
11259 * Walk the connector list instead of the encoder
11260 * list to detect the problem on ddi platforms
11261 * where there's just one encoder per digital port.
11262 */
5448a00d
ACO		 11263 for (i = 0; i < state->num_connector; i++) {
11264 if (!state->connectors[i])
11265 continue;
00f0b378 11266
5448a00d
ACO		 11267 connector_state = state->connector_states[i];
11268 if (!connector_state->best_encoder)
00f0b378
VS		 11269 continue;
11270
5448a00d
ACO		 11271 encoder = to_intel_encoder(connector_state->best_encoder);
11272
11273 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11274
11275 switch (encoder->type) {
11276 unsigned int port_mask;
11277 case INTEL_OUTPUT_UNKNOWN:
11278 if (WARN_ON(!HAS_DDI(dev)))
11279 break;
11280 case INTEL_OUTPUT_DISPLAYPORT:
11281 case INTEL_OUTPUT_HDMI:
11282 case INTEL_OUTPUT_EDP:
11283 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11284
11285 /* the same port mustn't appear more than once */
11286 if (used_ports & port_mask)
11287 return false;
11288
11289 used_ports |= port_mask;
11290 default:
11291 break;
11292 }
11293 }
11294
11295 return true;
11296}
11297
83a57153
ACO		 11298static void
11299clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11300{
11301 struct drm_crtc_state tmp_state;
663a3640 11302 struct intel_crtc_scaler_state scaler_state;
83a57153 11303
663a3640 11304 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11305 tmp_state = crtc_state->base;
663a3640 11306 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11307 memset(crtc_state, 0, sizeof *crtc_state);
11308 crtc_state->base = tmp_state;
663a3640 11309 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11310}
11311
5cec258b 11312static struct intel_crtc_state *
b8cecdf5 11313intel_modeset_pipe_config(struct drm_crtc *crtc,
83a57153
ACO		 11314 struct drm_display_mode *mode,
11315 struct drm_atomic_state *state)
ee7b9f93 11316{
7758a113 11317 struct intel_encoder *encoder;
0b901879
ACO		 11318 struct intel_connector *connector;
11319 struct drm_connector_state *connector_state;
5cec258b 11320 struct intel_crtc_state *pipe_config;
d328c9d7 11321 int base_bpp, ret = -EINVAL;
0b901879 11322 int i;
e29c22c0 11323 bool retry = true;
ee7b9f93 11324
98a221da 11325 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11326 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11327 return ERR_PTR(-EINVAL);
11328 }
11329
5448a00d 11330 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11331 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11332 return ERR_PTR(-EINVAL);
11333 }
11334
83a57153
ACO		 11335 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11336 if (IS_ERR(pipe_config))
11337 return pipe_config;
11338
11339 clear_intel_crtc_state(pipe_config);
7758a113 11340
07878248 11341 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11342 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11343 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11344
e143a21c
DV		 11345 pipe_config->cpu_transcoder =
11346 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11347 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11348
2960bc9c
ID		 11349 /*
11350 * Sanitize sync polarity flags based on requested ones. If neither
11351 * positive or negative polarity is requested, treat this as meaning
11352 * negative polarity.
11353 */
2d112de7 11354 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11355 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11357
2d112de7 11358 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11359 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11360 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11361
050f7aeb
DV		 11362 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11363 * plane pixel format and any sink constraints into account. Returns the
11364 * source plane bpp so that dithering can be selected on mismatches
11365 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11366 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11367 pipe_config);
11368 if (base_bpp < 0)
4e53c2e0
DV		 11369 goto fail;
11370
e41a56be
VS		 11371 /*
11372 * Determine the real pipe dimensions. Note that stereo modes can
11373 * increase the actual pipe size due to the frame doubling and
11374 * insertion of additional space for blanks between the frame. This
11375 * is stored in the crtc timings. We use the requested mode to do this
11376 * computation to clearly distinguish it from the adjusted mode, which
11377 * can be changed by the connectors in the below retry loop.
11378 */
2d112de7 11379 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11380 &pipe_config->pipe_src_w,
11381 &pipe_config->pipe_src_h);
e41a56be 11382
e29c22c0 11383encoder_retry:
ef1b460d 11384 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11385 pipe_config->port_clock = 0;
ef1b460d 11386 pipe_config->pixel_multiplier = 1;
ff9a6750 11387
135c81b8 11388 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11389 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11390 CRTC_STEREO_DOUBLE);
135c81b8 11391
7758a113
DV		 11392 /* Pass our mode to the connectors and the CRTC to give them a chance to
11393 * adjust it according to limitations or connector properties, and also
11394 * a chance to reject the mode entirely.
47f1c6c9 11395 */
0b901879
ACO		 11396 for (i = 0; i < state->num_connector; i++) {
11397 connector = to_intel_connector(state->connectors[i]);
11398 if (!connector)
11399 continue;
47f1c6c9 11400
0b901879
ACO		 11401 connector_state = state->connector_states[i];
11402 if (connector_state->crtc != crtc)
7758a113 11403 continue;
7ae89233 11404
0b901879
ACO		 11405 encoder = to_intel_encoder(connector_state->best_encoder);
11406
efea6e8e
DV		 11407 if (!(encoder->compute_config(encoder, pipe_config))) {
11408 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11409 goto fail;
11410 }
ee7b9f93 11411 }
47f1c6c9 11412
ff9a6750
DV		 11413 /* Set default port clock if not overwritten by the encoder. Needs to be
11414 * done afterwards in case the encoder adjusts the mode. */
11415 if (!pipe_config->port_clock)
2d112de7 11416 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11417 * pipe_config->pixel_multiplier;
ff9a6750 11418
a43f6e0f 11419 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11420 if (ret < 0) {
7758a113
DV		 11421 DRM_DEBUG_KMS("CRTC fixup failed\n");
11422 goto fail;
ee7b9f93 11423 }
e29c22c0
DV		 11424
11425 if (ret == RETRY) {
11426 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11427 ret = -EINVAL;
11428 goto fail;
11429 }
11430
11431 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11432 retry = false;
11433 goto encoder_retry;
11434 }
11435
d328c9d7 11436 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11437 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11438 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11439
b8cecdf5 11440 return pipe_config;
7758a113 11441fail:
e29c22c0 11442 return ERR_PTR(ret);
ee7b9f93 11443}
47f1c6c9 11444
e2e1ed41
DV		 11445/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11446 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11447static void
11448intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11449 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11450{
11451 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11452 struct drm_device *dev = crtc->dev;
11453 struct intel_encoder *encoder;
11454 struct intel_connector *connector;
11455 struct drm_crtc *tmp_crtc;
79e53945 11456
e2e1ed41 11457 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11458
e2e1ed41
DV		 11459 /* Check which crtcs have changed outputs connected to them, these need
11460 * to be part of the prepare_pipes mask. We don't (yet) support global
11461 * modeset across multiple crtcs, so modeset_pipes will only have one
11462 * bit set at most. */
3a3371ff 11463 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11464 if (connector->base.encoder == &connector->new_encoder->base)
11465 continue;
79e53945 11466
e2e1ed41
DV		 11467 if (connector->base.encoder) {
11468 tmp_crtc = connector->base.encoder->crtc;
11469
11470 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11471 }
11472
11473 if (connector->new_encoder)
11474 *prepare_pipes |=
11475 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11476 }
11477
b2784e15 11478 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11479 if (encoder->base.crtc == &encoder->new_crtc->base)
11480 continue;
11481
11482 if (encoder->base.crtc) {
11483 tmp_crtc = encoder->base.crtc;
11484
11485 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11486 }
11487
11488 if (encoder->new_crtc)
11489 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11490 }
11491
7668851f 11492 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11493 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11494 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11495 continue;
7e7d76c3 11496
7668851f 11497 if (!intel_crtc->new_enabled)
e2e1ed41 11498 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11499 else
11500 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11501 }
11502
e2e1ed41
DV		 11503
11504 /* set_mode is also used to update properties on life display pipes. */
11505 intel_crtc = to_intel_crtc(crtc);
7668851f 11506 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11507 *prepare_pipes |= 1 << intel_crtc->pipe;
11508
b6c5164d
DV		 11509 /*
11510 * For simplicity do a full modeset on any pipe where the output routing
11511 * changed. We could be more clever, but that would require us to be
11512 * more careful with calling the relevant encoder->mode_set functions.
11513 */
e2e1ed41
DV		 11514 if (*prepare_pipes)
11515 *modeset_pipes = *prepare_pipes;
11516
11517 /* ... and mask these out. */
11518 *modeset_pipes &= ~(*disable_pipes);
11519 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11520
11521 /*
11522 * HACK: We don't (yet) fully support global modesets. intel_set_config
11523 * obies this rule, but the modeset restore mode of
11524 * intel_modeset_setup_hw_state does not.
11525 */
11526 *modeset_pipes &= 1 << intel_crtc->pipe;
11527 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11528
11529 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11530 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11531}
79e53945 11532
ea9d758d 11533static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11534{
ea9d758d 11535 struct drm_encoder *encoder;
f6e5b160 11536 struct drm_device *dev = crtc->dev;
f6e5b160 11537
ea9d758d
DV		 11538 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11539 if (encoder->crtc == crtc)
11540 return true;
11541
11542 return false;
11543}
11544
11545static void
11546intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11547{
ba41c0de 11548 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11549 struct intel_encoder *intel_encoder;
11550 struct intel_crtc *intel_crtc;
11551 struct drm_connector *connector;
11552
ba41c0de
DV		 11553 intel_shared_dpll_commit(dev_priv);
11554
b2784e15 11555 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11556 if (!intel_encoder->base.crtc)
11557 continue;
11558
11559 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11560
11561 if (prepare_pipes & (1 << intel_crtc->pipe))
11562 intel_encoder->connectors_active = false;
11563 }
11564
11565 intel_modeset_commit_output_state(dev);
11566
7668851f 11567 /* Double check state. */
d3fcc808 11568 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11569 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11570 }
11571
11572 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11573 if (!connector->encoder || !connector->encoder->crtc)
11574 continue;
11575
11576 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11577
11578 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11579 struct drm_property *dpms_property =
11580 dev->mode_config.dpms_property;
11581
ea9d758d 11582 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11583 drm_object_property_set_value(&connector->base,
68d34720
DV		 11584 dpms_property,
11585 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11586
11587 intel_encoder = to_intel_encoder(connector->encoder);
11588 intel_encoder->connectors_active = true;
11589 }
11590 }
11591
11592}
11593
3bd26263 11594static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11595{
3bd26263 11596 int diff;
f1f644dc
JB		 11597
11598 if (clock1 == clock2)
11599 return true;
11600
11601 if (!clock1 || !clock2)
11602 return false;
11603
11604 diff = abs(clock1 - clock2);
11605
11606 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11607 return true;
11608
11609 return false;
11610}
11611
25c5b266
DV		 11612#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11613 list_for_each_entry((intel_crtc), \
11614 &(dev)->mode_config.crtc_list, \
11615 base.head) \
0973f18f 11616 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11617
0e8ffe1b 11618static bool
2fa2fe9a 11619intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11620 struct intel_crtc_state *current_config,
11621 struct intel_crtc_state *pipe_config)
0e8ffe1b 11622{
66e985c0
DV		 11623#define PIPE_CONF_CHECK_X(name) \
11624 if (current_config->name != pipe_config->name) { \
11625 DRM_ERROR("mismatch in " #name " " \
11626 "(expected 0x%08x, found 0x%08x)\n", \
11627 current_config->name, \
11628 pipe_config->name); \
11629 return false; \
11630 }
11631
08a24034
DV		 11632#define PIPE_CONF_CHECK_I(name) \
11633 if (current_config->name != pipe_config->name) { \
11634 DRM_ERROR("mismatch in " #name " " \
11635 "(expected %i, found %i)\n", \
11636 current_config->name, \
11637 pipe_config->name); \
11638 return false; \
88adfff1
DV		 11639 }
11640
b95af8be
VK		 11641/* This is required for BDW+ where there is only one set of registers for
11642 * switching between high and low RR.
11643 * This macro can be used whenever a comparison has to be made between one
11644 * hw state and multiple sw state variables.
11645 */
11646#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11647 if ((current_config->name != pipe_config->name) && \
11648 (current_config->alt_name != pipe_config->name)) { \
11649 DRM_ERROR("mismatch in " #name " " \
11650 "(expected %i or %i, found %i)\n", \
11651 current_config->name, \
11652 current_config->alt_name, \
11653 pipe_config->name); \
11654 return false; \
11655 }
11656
1bd1bd80
DV		 11657#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11658 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11659 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11660 "(expected %i, found %i)\n", \
11661 current_config->name & (mask), \
11662 pipe_config->name & (mask)); \
11663 return false; \
11664 }
11665
5e550656
VS		 11666#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11667 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11668 DRM_ERROR("mismatch in " #name " " \
11669 "(expected %i, found %i)\n", \
11670 current_config->name, \
11671 pipe_config->name); \
11672 return false; \
11673 }
11674
bb760063
DV		 11675#define PIPE_CONF_QUIRK(quirk) \
11676 ((current_config->quirks | pipe_config->quirks) & (quirk))
11677
eccb140b
DV		 11678 PIPE_CONF_CHECK_I(cpu_transcoder);
11679
08a24034
DV		 11680 PIPE_CONF_CHECK_I(has_pch_encoder);
11681 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11682 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11683 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11684 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11685 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11686 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11687
eb14cb74 11688 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11689
11690 if (INTEL_INFO(dev)->gen < 8) {
11691 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11692 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11693 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11694 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11695 PIPE_CONF_CHECK_I(dp_m_n.tu);
11696
11697 if (current_config->has_drrs) {
11698 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11699 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11700 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11701 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11702 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11703 }
11704 } else {
11705 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11706 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11707 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11708 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11709 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11710 }
eb14cb74 11711
2d112de7
ACO		 11712 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11713 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11714 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11715 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11716 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11717 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11718
2d112de7
ACO		 11719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11722 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11723 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11724 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11725
c93f54cf 11726 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11727 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11728 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11729 IS_VALLEYVIEW(dev))
11730 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11731 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11732
9ed109a7
DV		 11733 PIPE_CONF_CHECK_I(has_audio);
11734
2d112de7 11735 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11736 DRM_MODE_FLAG_INTERLACE);
11737
bb760063 11738 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11739 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11740 DRM_MODE_FLAG_PHSYNC);
2d112de7 11741 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11742 DRM_MODE_FLAG_NHSYNC);
2d112de7 11743 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11744 DRM_MODE_FLAG_PVSYNC);
2d112de7 11745 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11746 DRM_MODE_FLAG_NVSYNC);
11747 }
045ac3b5 11748
37327abd
VS		 11749 PIPE_CONF_CHECK_I(pipe_src_w);
11750 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11751
9953599b
DV		 11752 /*
11753 * FIXME: BIOS likes to set up a cloned config with lvds+external
11754 * screen. Since we don't yet re-compute the pipe config when moving
11755 * just the lvds port away to another pipe the sw tracking won't match.
11756 *
11757 * Proper atomic modesets with recomputed global state will fix this.
11758 * Until then just don't check gmch state for inherited modes.
11759 */
11760 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11761 PIPE_CONF_CHECK_I(gmch_pfit.control);
11762 /* pfit ratios are autocomputed by the hw on gen4+ */
11763 if (INTEL_INFO(dev)->gen < 4)
11764 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11765 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11766 }
11767
fd4daa9c
CW		 11768 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11769 if (current_config->pch_pfit.enabled) {
11770 PIPE_CONF_CHECK_I(pch_pfit.pos);
11771 PIPE_CONF_CHECK_I(pch_pfit.size);
11772 }
2fa2fe9a 11773
a1b2278e
CK		 11774 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11775
e59150dc
JB		 11776 /* BDW+ don't expose a synchronous way to read the state */
11777 if (IS_HASWELL(dev))
11778 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11779
282740f7
VS		 11780 PIPE_CONF_CHECK_I(double_wide);
11781
26804afd
DV		 11782 PIPE_CONF_CHECK_X(ddi_pll_sel);
11783
c0d43d62 11784 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11785 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11786 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11787 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11788 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11789 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11790 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11791 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11792 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11793
42571aef
VS		 11794 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11795 PIPE_CONF_CHECK_I(pipe_bpp);
11796
2d112de7 11797 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11798 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11799
66e985c0 11800#undef PIPE_CONF_CHECK_X
08a24034 11801#undef PIPE_CONF_CHECK_I
b95af8be 11802#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11803#undef PIPE_CONF_CHECK_FLAGS
5e550656 11804#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11805#undef PIPE_CONF_QUIRK
88adfff1 11806
0e8ffe1b
DV		 11807 return true;
11808}
11809
08db6652
DL		 11810static void check_wm_state(struct drm_device *dev)
11811{
11812 struct drm_i915_private *dev_priv = dev->dev_private;
11813 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11814 struct intel_crtc *intel_crtc;
11815 int plane;
11816
11817 if (INTEL_INFO(dev)->gen < 9)
11818 return;
11819
11820 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11821 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11822
11823 for_each_intel_crtc(dev, intel_crtc) {
11824 struct skl_ddb_entry *hw_entry, *sw_entry;
11825 const enum pipe pipe = intel_crtc->pipe;
11826
11827 if (!intel_crtc->active)
11828 continue;
11829
11830 /* planes */
dd740780 11831 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11832 hw_entry = &hw_ddb.plane[pipe][plane];
11833 sw_entry = &sw_ddb->plane[pipe][plane];
11834
11835 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11836 continue;
11837
11838 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11839 "(expected (%u,%u), found (%u,%u))\n",
11840 pipe_name(pipe), plane + 1,
11841 sw_entry->start, sw_entry->end,
11842 hw_entry->start, hw_entry->end);
11843 }
11844
11845 /* cursor */
11846 hw_entry = &hw_ddb.cursor[pipe];
11847 sw_entry = &sw_ddb->cursor[pipe];
11848
11849 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11850 continue;
11851
11852 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11853 "(expected (%u,%u), found (%u,%u))\n",
11854 pipe_name(pipe),
11855 sw_entry->start, sw_entry->end,
11856 hw_entry->start, hw_entry->end);
11857 }
11858}
11859
91d1b4bd
DV		 11860static void
11861check_connector_state(struct drm_device *dev)
8af6cf88 11862{
8af6cf88
DV		 11863 struct intel_connector *connector;
11864
3a3371ff 11865 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11866 /* This also checks the encoder/connector hw state with the
11867 * ->get_hw_state callbacks. */
11868 intel_connector_check_state(connector);
11869
e2c719b7 11870 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11871 "connector's staged encoder doesn't match current encoder\n");
11872 }
91d1b4bd
DV		 11873}
11874
11875static void
11876check_encoder_state(struct drm_device *dev)
11877{
11878 struct intel_encoder *encoder;
11879 struct intel_connector *connector;
8af6cf88 11880
b2784e15 11881 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11882 bool enabled = false;
11883 bool active = false;
11884 enum pipe pipe, tracked_pipe;
11885
11886 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11887 encoder->base.base.id,
8e329a03 11888 encoder->base.name);
8af6cf88 11889
e2c719b7 11890 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11891 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11892 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11893 "encoder's active_connectors set, but no crtc\n");
11894
3a3371ff 11895 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11896 if (connector->base.encoder != &encoder->base)
11897 continue;
11898 enabled = true;
11899 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11900 active = true;
11901 }
0e32b39c
DA		 11902 /*
11903 * for MST connectors if we unplug the connector is gone
11904 * away but the encoder is still connected to a crtc
11905 * until a modeset happens in response to the hotplug.
11906 */
11907 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11908 continue;
11909
e2c719b7 11910 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11911 "encoder's enabled state mismatch "
11912 "(expected %i, found %i)\n",
11913 !!encoder->base.crtc, enabled);
e2c719b7 11914 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11915 "active encoder with no crtc\n");
11916
e2c719b7 11917 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11918 "encoder's computed active state doesn't match tracked active state "
11919 "(expected %i, found %i)\n", active, encoder->connectors_active);
11920
11921 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11922 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11923 "encoder's hw state doesn't match sw tracking "
11924 "(expected %i, found %i)\n",
11925 encoder->connectors_active, active);
11926
11927 if (!encoder->base.crtc)
11928 continue;
11929
11930 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11931 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11932 "active encoder's pipe doesn't match"
11933 "(expected %i, found %i)\n",
11934 tracked_pipe, pipe);
11935
11936 }
91d1b4bd
DV		 11937}
11938
11939static void
11940check_crtc_state(struct drm_device *dev)
11941{
fbee40df 11942 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11943 struct intel_crtc *crtc;
11944 struct intel_encoder *encoder;
5cec258b 11945 struct intel_crtc_state pipe_config;
8af6cf88 11946
d3fcc808 11947 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11948 bool enabled = false;
11949 bool active = false;
11950
045ac3b5
JB		 11951 memset(&pipe_config, 0, sizeof(pipe_config));
11952
8af6cf88
DV		 11953 DRM_DEBUG_KMS("[CRTC:%d]\n",
11954 crtc->base.base.id);
11955
83d65738 11956 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11957 "active crtc, but not enabled in sw tracking\n");
11958
b2784e15 11959 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11960 if (encoder->base.crtc != &crtc->base)
11961 continue;
11962 enabled = true;
11963 if (encoder->connectors_active)
11964 active = true;
11965 }
6c49f241 11966
e2c719b7 11967 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11968 "crtc's computed active state doesn't match tracked active state "
11969 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11970 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11971 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11972 "(expected %i, found %i)\n", enabled,
11973 crtc->base.state->enable);
8af6cf88 11974
0e8ffe1b
DV		 11975 active = dev_priv->display.get_pipe_config(crtc,
11976 &pipe_config);
d62cf62a 11977
b6b5d049
VS		 11978 /* hw state is inconsistent with the pipe quirk */
11979 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11980 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11981 active = crtc->active;
11982
b2784e15 11983 for_each_intel_encoder(dev, encoder) {
3eaba51c 11984 enum pipe pipe;
6c49f241
DV		 11985 if (encoder->base.crtc != &crtc->base)
11986 continue;
1d37b689 11987 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11988 encoder->get_config(encoder, &pipe_config);
11989 }
11990
e2c719b7 11991 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11992 "crtc active state doesn't match with hw state "
11993 "(expected %i, found %i)\n", crtc->active, active);
11994
c0b03411 11995 if (active &&
6e3c9717 11996 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11997 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11998 intel_dump_pipe_config(crtc, &pipe_config,
11999 "[hw state]");
6e3c9717 12000 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12001 "[sw state]");
12002 }
8af6cf88
DV		 12003 }
12004}
12005
91d1b4bd
DV		 12006static void
12007check_shared_dpll_state(struct drm_device *dev)
12008{
fbee40df 12009 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12010 struct intel_crtc *crtc;
12011 struct intel_dpll_hw_state dpll_hw_state;
12012 int i;
5358901f
DV		 12013
12014 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12015 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12016 int enabled_crtcs = 0, active_crtcs = 0;
12017 bool active;
12018
12019 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12020
12021 DRM_DEBUG_KMS("%s\n", pll->name);
12022
12023 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12024
e2c719b7 12025 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12026 "more active pll users than references: %i vs %i\n",
3e369b76 12027 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12028 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12029 "pll in active use but not on in sw tracking\n");
e2c719b7 12030 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12031 "pll in on but not on in use in sw tracking\n");
e2c719b7 12032 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12033 "pll on state mismatch (expected %i, found %i)\n",
12034 pll->on, active);
12035
d3fcc808 12036 for_each_intel_crtc(dev, crtc) {
83d65738 12037 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12038 enabled_crtcs++;
12039 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12040 active_crtcs++;
12041 }
e2c719b7 12042 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12043 "pll active crtcs mismatch (expected %i, found %i)\n",
12044 pll->active, active_crtcs);
e2c719b7 12045 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12046 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12047 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12048
e2c719b7 12049 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12050 sizeof(dpll_hw_state)),
12051 "pll hw state mismatch\n");
5358901f 12052 }
8af6cf88
DV		 12053}
12054
91d1b4bd
DV		 12055void
12056intel_modeset_check_state(struct drm_device *dev)
12057{
08db6652 12058 check_wm_state(dev);
91d1b4bd
DV		 12059 check_connector_state(dev);
12060 check_encoder_state(dev);
12061 check_crtc_state(dev);
12062 check_shared_dpll_state(dev);
12063}
12064
5cec258b 12065void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12066 int dotclock)
12067{
12068 /*
12069 * FDI already provided one idea for the dotclock.
12070 * Yell if the encoder disagrees.
12071 */
2d112de7 12072 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12073 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12074 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12075}
12076
80715b2f
VS		 12077static void update_scanline_offset(struct intel_crtc *crtc)
12078{
12079 struct drm_device *dev = crtc->base.dev;
12080
12081 /*
12082 * The scanline counter increments at the leading edge of hsync.
12083 *
12084 * On most platforms it starts counting from vtotal-1 on the
12085 * first active line. That means the scanline counter value is
12086 * always one less than what we would expect. Ie. just after
12087 * start of vblank, which also occurs at start of hsync (on the
12088 * last active line), the scanline counter will read vblank_start-1.
12089 *
12090 * On gen2 the scanline counter starts counting from 1 instead
12091 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12092 * to keep the value positive), instead of adding one.
12093 *
12094 * On HSW+ the behaviour of the scanline counter depends on the output
12095 * type. For DP ports it behaves like most other platforms, but on HDMI
12096 * there's an extra 1 line difference. So we need to add two instead of
12097 * one to the value.
12098 */
12099 if (IS_GEN2(dev)) {
6e3c9717 12100 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12101 int vtotal;
12102
12103 vtotal = mode->crtc_vtotal;
12104 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12105 vtotal /= 2;
12106
12107 crtc->scanline_offset = vtotal - 1;
12108 } else if (HAS_DDI(dev) &&
409ee761 12109 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12110 crtc->scanline_offset = 2;
12111 } else
12112 crtc->scanline_offset = 1;
12113}
12114
5cec258b 12115static struct intel_crtc_state *
7f27126e
JB		 12116intel_modeset_compute_config(struct drm_crtc *crtc,
12117 struct drm_display_mode *mode,
83a57153 12118 struct drm_atomic_state *state,
7f27126e
JB		 12119 unsigned *modeset_pipes,
12120 unsigned *prepare_pipes,
12121 unsigned *disable_pipes)
12122{
db7542dd 12123 struct drm_device *dev = crtc->dev;
5cec258b 12124 struct intel_crtc_state *pipe_config = NULL;
db7542dd 12125 struct intel_crtc *intel_crtc;
0b901879
ACO		 12126 int ret = 0;
12127
12128 ret = drm_atomic_add_affected_connectors(state, crtc);
12129 if (ret)
12130 return ERR_PTR(ret);
7f27126e
JB		 12131
12132 intel_modeset_affected_pipes(crtc, modeset_pipes,
12133 prepare_pipes, disable_pipes);
12134
db7542dd
ACO		 12135 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
12136 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12137 if (IS_ERR(pipe_config))
12138 return pipe_config;
12139
12140 pipe_config->base.enable = false;
12141 }
7f27126e
JB		 12142
12143 /*
12144 * Note this needs changes when we start tracking multiple modes
12145 * and crtcs. At that point we'll need to compute the whole config
12146 * (i.e. one pipe_config for each crtc) rather than just the one
12147 * for this crtc.
12148 */
db7542dd
ACO		 12149 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
12150 /* FIXME: For now we still expect modeset_pipes has at most
12151 * one bit set. */
12152 if (WARN_ON(&intel_crtc->base != crtc))
12153 continue;
83a57153 12154
8805aa71 12155 pipe_config = intel_modeset_pipe_config(crtc, mode, state);
db7542dd
ACO		 12156 if (IS_ERR(pipe_config))
12157 return pipe_config;
7f27126e 12158
304603f4
ACO		 12159 pipe_config->base.enable = true;
12160
db7542dd
ACO		 12161 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12162 "[modeset]");
12163 }
12164
12165 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 12166}
12167
225da59b 12168static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 12169 unsigned modeset_pipes,
12170 unsigned disable_pipes)
12171{
225da59b 12172 struct drm_device *dev = state->dev;
ed6739ef
ACO		 12173 struct drm_i915_private *dev_priv = to_i915(dev);
12174 unsigned clear_pipes = modeset_pipes | disable_pipes;
12175 struct intel_crtc *intel_crtc;
12176 int ret = 0;
12177
12178 if (!dev_priv->display.crtc_compute_clock)
12179 return 0;
12180
12181 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12182 if (ret)
12183 goto done;
12184
12185 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 12186 struct intel_crtc_state *crtc_state =
12187 intel_atomic_get_crtc_state(state, intel_crtc);
12188
12189 /* Modeset pipes should have a new state by now */
12190 if (WARN_ON(IS_ERR(crtc_state)))
12191 continue;
12192
ed6739ef 12193 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 12194 crtc_state);
ed6739ef
ACO		 12195 if (ret) {
12196 intel_shared_dpll_abort_config(dev_priv);
12197 goto done;
12198 }
12199 }
12200
12201done:
12202 return ret;
12203}
12204
f30da187
DV		 12205static int __intel_set_mode(struct drm_crtc *crtc,
12206 struct drm_display_mode *mode,
7f27126e 12207 int x, int y, struct drm_framebuffer *fb,
5cec258b 12208 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12209 unsigned modeset_pipes,
12210 unsigned prepare_pipes,
12211 unsigned disable_pipes)
a6778b3c
DV		 12212{
12213 struct drm_device *dev = crtc->dev;
fbee40df 12214 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 12215 struct drm_display_mode *saved_mode;
304603f4 12216 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12217 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12218 struct intel_crtc *intel_crtc;
c0c36b94 12219 int ret = 0;
a6778b3c 12220
4b4b9238 12221 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 12222 if (!saved_mode)
12223 return -ENOMEM;
a6778b3c 12224
83a57153
ACO		 12225 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12226 if (!crtc_state_copy) {
12227 ret = -ENOMEM;
12228 goto done;
12229 }
12230
3ac18232 12231 *saved_mode = crtc->mode;
a6778b3c 12232
30a970c6
JB		 12233 /*
12234 * See if the config requires any additional preparation, e.g.
12235 * to adjust global state with pipes off. We need to do this
12236 * here so we can get the modeset_pipe updated config for the new
12237 * mode set on this crtc. For other crtcs we need to use the
12238 * adjusted_mode bits in the crtc directly.
12239 */
f8437dd1 12240 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
304603f4
ACO		 12241 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
12242 if (ret)
12243 goto done;
30a970c6 12244
c164f833
VS		 12245 /* may have added more to prepare_pipes than we should */
12246 prepare_pipes &= ~disable_pipes;
12247 }
12248
225da59b 12249 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 12250 if (ret)
12251 goto done;
8bd31e67 12252
460da916
DV		 12253 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12254 intel_crtc_disable(&intel_crtc->base);
12255
ea9d758d 12256 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 12257 if (intel_crtc->base.state->enable)
ea9d758d
DV		 12258 dev_priv->display.crtc_disable(&intel_crtc->base);
12259 }
a6778b3c 12260
6c4c86f5
DV		 12261 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12262 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12263 *
12264 * Note we'll need to fix this up when we start tracking multiple
12265 * pipes; here we assume a single modeset_pipe and only track the
12266 * single crtc and mode.
f6e5b160 12267 */
b8cecdf5 12268 if (modeset_pipes) {
25c5b266 12269 crtc->mode = *mode;
b8cecdf5
DV		 12270 /* mode_set/enable/disable functions rely on a correct pipe
12271 * config. */
f5de6e07 12272 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12273
12274 /*
12275 * Calculate and store various constants which
12276 * are later needed by vblank and swap-completion
12277 * timestamping. They are derived from true hwmode.
12278 */
12279 drm_calc_timestamping_constants(crtc,
2d112de7 12280 &pipe_config->base.adjusted_mode);
b8cecdf5 12281 }
7758a113 12282
ea9d758d
DV		 12283 /* Only after disabling all output pipelines that will be changed can we
12284 * update the the output configuration. */
12285 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12286
304603f4 12287 modeset_update_crtc_power_domains(state);
47fab737 12288
25c5b266 12289 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12290 struct drm_plane *primary = intel_crtc->base.primary;
12291 int vdisplay, hdisplay;
4c10794f 12292
455a6808 12293 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12294 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12295 fb, 0, 0,
12296 hdisplay, vdisplay,
12297 x << 16, y << 16,
12298 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12299 }
12300
12301 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12302 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12303 update_scanline_offset(intel_crtc);
12304
25c5b266 12305 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 12306 }
a6778b3c 12307
a6778b3c
DV		 12308 /* FIXME: add subpixel order */
12309done:
83d65738 12310 if (ret && crtc->state->enable)
3ac18232 12311 crtc->mode = *saved_mode;
a6778b3c 12312
83a57153
ACO		 12313 if (ret == 0 && pipe_config) {
12314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12315
12316 /* The pipe_config will be freed with the atomic state, so
12317 * make a copy. */
12318 memcpy(crtc_state_copy, intel_crtc->config,
12319 sizeof *crtc_state_copy);
12320 intel_crtc->config = crtc_state_copy;
12321 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12322 } else {
12323 kfree(crtc_state_copy);
12324 }
12325
3ac18232 12326 kfree(saved_mode);
a6778b3c 12327 return ret;
f6e5b160
CW		 12328}
12329
7f27126e
JB		 12330static int intel_set_mode_pipes(struct drm_crtc *crtc,
12331 struct drm_display_mode *mode,
12332 int x, int y, struct drm_framebuffer *fb,
5cec258b 12333 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12334 unsigned modeset_pipes,
12335 unsigned prepare_pipes,
12336 unsigned disable_pipes)
f30da187
DV		 12337{
12338 int ret;
12339
7f27126e
JB		 12340 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12341 prepare_pipes, disable_pipes);
f30da187
DV		 12342
12343 if (ret == 0)
12344 intel_modeset_check_state(crtc->dev);
12345
12346 return ret;
12347}
12348
7f27126e
JB		 12349static int intel_set_mode(struct drm_crtc *crtc,
12350 struct drm_display_mode *mode,
83a57153
ACO		 12351 int x, int y, struct drm_framebuffer *fb,
12352 struct drm_atomic_state *state)
7f27126e 12353{
5cec258b 12354 struct intel_crtc_state *pipe_config;
7f27126e 12355 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12356 int ret = 0;
7f27126e 12357
8805aa71 12358 pipe_config = intel_modeset_compute_config(crtc, mode, state,
7f27126e
JB		 12359 &modeset_pipes,
12360 &prepare_pipes,
12361 &disable_pipes);
12362
83a57153
ACO		 12363 if (IS_ERR(pipe_config)) {
12364 ret = PTR_ERR(pipe_config);
12365 goto out;
12366 }
12367
12368 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12369 modeset_pipes, prepare_pipes,
12370 disable_pipes);
12371 if (ret)
12372 goto out;
7f27126e 12373
83a57153
ACO		 12374out:
12375 return ret;
7f27126e
JB		 12376}
12377
c0c36b94
CW		 12378void intel_crtc_restore_mode(struct drm_crtc *crtc)
12379{
83a57153
ACO		 12380 struct drm_device *dev = crtc->dev;
12381 struct drm_atomic_state *state;
12382 struct intel_encoder *encoder;
12383 struct intel_connector *connector;
12384 struct drm_connector_state *connector_state;
12385
12386 state = drm_atomic_state_alloc(dev);
12387 if (!state) {
12388 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12389 crtc->base.id);
12390 return;
12391 }
12392
12393 state->acquire_ctx = dev->mode_config.acquire_ctx;
12394
12395 /* The force restore path in the HW readout code relies on the staged
12396 * config still keeping the user requested config while the actual
12397 * state has been overwritten by the configuration read from HW. We
12398 * need to copy the staged config to the atomic state, otherwise the
12399 * mode set will just reapply the state the HW is already in. */
12400 for_each_intel_encoder(dev, encoder) {
12401 if (&encoder->new_crtc->base != crtc)
12402 continue;
12403
12404 for_each_intel_connector(dev, connector) {
12405 if (connector->new_encoder != encoder)
12406 continue;
12407
12408 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12409 if (IS_ERR(connector_state)) {
12410 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12411 connector->base.base.id,
12412 connector->base.name,
12413 PTR_ERR(connector_state));
12414 continue;
12415 }
12416
12417 connector_state->crtc = crtc;
12418 connector_state->best_encoder = &encoder->base;
12419 }
12420 }
12421
12422 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12423 state);
12424
12425 drm_atomic_state_free(state);
c0c36b94
CW		 12426}
12427
25c5b266
DV		 12428#undef for_each_intel_crtc_masked
12429
d9e55608
DV		 12430static void intel_set_config_free(struct intel_set_config *config)
12431{
12432 if (!config)
12433 return;
12434
1aa4b628
DV		 12435 kfree(config->save_connector_encoders);
12436 kfree(config->save_encoder_crtcs);
7668851f 12437 kfree(config->save_crtc_enabled);
d9e55608
DV		 12438 kfree(config);
12439}
12440
85f9eb71
DV		 12441static int intel_set_config_save_state(struct drm_device *dev,
12442 struct intel_set_config *config)
12443{
7668851f 12444 struct drm_crtc *crtc;
85f9eb71
DV		 12445 struct drm_encoder *encoder;
12446 struct drm_connector *connector;
12447 int count;
12448
7668851f
VS		 12449 config->save_crtc_enabled =
12450 kcalloc(dev->mode_config.num_crtc,
12451 sizeof(bool), GFP_KERNEL);
12452 if (!config->save_crtc_enabled)
12453 return -ENOMEM;
12454
1aa4b628
DV		 12455 config->save_encoder_crtcs =
12456 kcalloc(dev->mode_config.num_encoder,
12457 sizeof(struct drm_crtc *), GFP_KERNEL);
12458 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12459 return -ENOMEM;
12460
1aa4b628
DV		 12461 config->save_connector_encoders =
12462 kcalloc(dev->mode_config.num_connector,
12463 sizeof(struct drm_encoder *), GFP_KERNEL);
12464 if (!config->save_connector_encoders)
85f9eb71
DV		 12465 return -ENOMEM;
12466
12467 /* Copy data. Note that driver private data is not affected.
12468 * Should anything bad happen only the expected state is
12469 * restored, not the drivers personal bookkeeping.
12470 */
7668851f 12471 count = 0;
70e1e0ec 12472 for_each_crtc(dev, crtc) {
83d65738 12473 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12474 }
12475
85f9eb71
DV		 12476 count = 0;
12477 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12478 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12479 }
12480
12481 count = 0;
12482 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12483 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12484 }
12485
12486 return 0;
12487}
12488
12489static void intel_set_config_restore_state(struct drm_device *dev,
12490 struct intel_set_config *config)
12491{
7668851f 12492 struct intel_crtc *crtc;
9a935856
DV		 12493 struct intel_encoder *encoder;
12494 struct intel_connector *connector;
85f9eb71
DV		 12495 int count;
12496
7668851f 12497 count = 0;
d3fcc808 12498 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12499 crtc->new_enabled = config->save_crtc_enabled[count++];
12500 }
12501
85f9eb71 12502 count = 0;
b2784e15 12503 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12504 encoder->new_crtc =
12505 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12506 }
12507
12508 count = 0;
3a3371ff 12509 for_each_intel_connector(dev, connector) {
9a935856
DV		 12510 connector->new_encoder =
12511 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12512 }
12513}
12514
e3de42b6 12515static bool
2e57f47d 12516is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12517{
12518 int i;
12519
2e57f47d
CW		 12520 if (set->num_connectors == 0)
12521 return false;
12522
12523 if (WARN_ON(set->connectors == NULL))
12524 return false;
12525
12526 for (i = 0; i < set->num_connectors; i++)
12527 if (set->connectors[i]->encoder &&
12528 set->connectors[i]->encoder->crtc == set->crtc &&
12529 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12530 return true;
12531
12532 return false;
12533}
12534
5e2b584e
DV		 12535static void
12536intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12537 struct intel_set_config *config)
12538{
12539
12540 /* We should be able to check here if the fb has the same properties
12541 * and then just flip_or_move it */
2e57f47d
CW		 12542 if (is_crtc_connector_off(set)) {
12543 config->mode_changed = true;
f4510a27 12544 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12545 /*
12546 * If we have no fb, we can only flip as long as the crtc is
12547 * active, otherwise we need a full mode set. The crtc may
12548 * be active if we've only disabled the primary plane, or
12549 * in fastboot situations.
12550 */
f4510a27 12551 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12552 struct intel_crtc *intel_crtc =
12553 to_intel_crtc(set->crtc);
12554
3b150f08 12555 if (intel_crtc->active) {
319d9827
JB		 12556 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12557 config->fb_changed = true;
12558 } else {
12559 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12560 config->mode_changed = true;
12561 }
5e2b584e
DV		 12562 } else if (set->fb == NULL) {
12563 config->mode_changed = true;
72f4901e 12564 } else if (set->fb->pixel_format !=
f4510a27 12565 set->crtc->primary->fb->pixel_format) {
5e2b584e 12566 config->mode_changed = true;
e3de42b6 12567 } else {
5e2b584e 12568 config->fb_changed = true;
e3de42b6 12569 }
5e2b584e
DV		 12570 }
12571
835c5873 12572 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12573 config->fb_changed = true;
12574
12575 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12576 DRM_DEBUG_KMS("modes are different, full mode set\n");
12577 drm_mode_debug_printmodeline(&set->crtc->mode);
12578 drm_mode_debug_printmodeline(set->mode);
12579 config->mode_changed = true;
12580 }
a1d95703
CW		 12581
12582 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12583 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12584}
12585
2e431051 12586static int
9a935856
DV		 12587intel_modeset_stage_output_state(struct drm_device *dev,
12588 struct drm_mode_set *set,
944b0c76
ACO		 12589 struct intel_set_config *config,
12590 struct drm_atomic_state *state)
50f56119 12591{
9a935856 12592 struct intel_connector *connector;
944b0c76 12593 struct drm_connector_state *connector_state;
9a935856 12594 struct intel_encoder *encoder;
7668851f 12595 struct intel_crtc *crtc;
f3f08572 12596 int ro;
50f56119 12597
9abdda74 12598 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12599 * of connectors. For paranoia, double-check this. */
12600 WARN_ON(!set->fb && (set->num_connectors != 0));
12601 WARN_ON(set->fb && (set->num_connectors == 0));
12602
3a3371ff 12603 for_each_intel_connector(dev, connector) {
9a935856
DV		 12604 /* Otherwise traverse passed in connector list and get encoders
12605 * for them. */
50f56119 12606 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12607 if (set->connectors[ro] == &connector->base) {
0e32b39c 12608 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12609 break;
12610 }
12611 }
12612
9a935856
DV		 12613 /* If we disable the crtc, disable all its connectors. Also, if
12614 * the connector is on the changing crtc but not on the new
12615 * connector list, disable it. */
12616 if ((!set->fb || ro == set->num_connectors) &&
12617 connector->base.encoder &&
12618 connector->base.encoder->crtc == set->crtc) {
12619 connector->new_encoder = NULL;
12620
12621 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12622 connector->base.base.id,
c23cc417 12623 connector->base.name);
9a935856
DV		 12624 }
12625
12626
12627 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12629 connector->base.base.id,
12630 connector->base.name);
5e2b584e 12631 config->mode_changed = true;
50f56119
DV		 12632 }
12633 }
9a935856 12634 /* connector->new_encoder is now updated for all connectors. */
50f56119 12635
9a935856 12636 /* Update crtc of enabled connectors. */
3a3371ff 12637 for_each_intel_connector(dev, connector) {
7668851f
VS		 12638 struct drm_crtc *new_crtc;
12639
9a935856 12640 if (!connector->new_encoder)
50f56119
DV		 12641 continue;
12642
9a935856 12643 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12644
12645 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12646 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12647 new_crtc = set->crtc;
12648 }
12649
12650 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12651 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12652 new_crtc)) {
5e2b584e 12653 return -EINVAL;
50f56119 12654 }
0e32b39c 12655 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12656
944b0c76
ACO		 12657 connector_state =
12658 drm_atomic_get_connector_state(state, &connector->base);
12659 if (IS_ERR(connector_state))
12660 return PTR_ERR(connector_state);
12661
12662 connector_state->crtc = new_crtc;
12663 connector_state->best_encoder = &connector->new_encoder->base;
12664
9a935856
DV		 12665 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12666 connector->base.base.id,
c23cc417 12667 connector->base.name,
9a935856
DV		 12668 new_crtc->base.id);
12669 }
12670
12671 /* Check for any encoders that needs to be disabled. */
b2784e15 12672 for_each_intel_encoder(dev, encoder) {
5a65f358 12673 int num_connectors = 0;
3a3371ff 12674 for_each_intel_connector(dev, connector) {
9a935856
DV		 12675 if (connector->new_encoder == encoder) {
12676 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12677 num_connectors++;
9a935856
DV		 12678 }
12679 }
5a65f358
PZ		 12680
12681 if (num_connectors == 0)
12682 encoder->new_crtc = NULL;
12683 else if (num_connectors > 1)
12684 return -EINVAL;
12685
9a935856
DV		 12686 /* Only now check for crtc changes so we don't miss encoders
12687 * that will be disabled. */
12688 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12689 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12690 encoder->base.base.id,
12691 encoder->base.name);
5e2b584e 12692 config->mode_changed = true;
50f56119
DV		 12693 }
12694 }
9a935856 12695 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12696 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12697 connector_state =
12698 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12699 if (IS_ERR(connector_state))
12700 return PTR_ERR(connector_state);
944b0c76
ACO		 12701
12702 if (connector->new_encoder) {
0e32b39c
DA		 12703 if (connector->new_encoder != connector->encoder)
12704 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12705 } else {
12706 connector_state->crtc = NULL;
f61cccf3 12707 connector_state->best_encoder = NULL;
944b0c76 12708 }
0e32b39c 12709 }
d3fcc808 12710 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12711 crtc->new_enabled = false;
12712
b2784e15 12713 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12714 if (encoder->new_crtc == crtc) {
12715 crtc->new_enabled = true;
12716 break;
12717 }
12718 }
12719
83d65738 12720 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12721 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12722 crtc->base.base.id,
7668851f
VS		 12723 crtc->new_enabled ? "en" : "dis");
12724 config->mode_changed = true;
12725 }
12726 }
12727
2e431051
DV		 12728 return 0;
12729}
12730
7d00a1f5
VS		 12731static void disable_crtc_nofb(struct intel_crtc *crtc)
12732{
12733 struct drm_device *dev = crtc->base.dev;
12734 struct intel_encoder *encoder;
12735 struct intel_connector *connector;
12736
12737 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12738 pipe_name(crtc->pipe));
12739
3a3371ff 12740 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12741 if (connector->new_encoder &&
12742 connector->new_encoder->new_crtc == crtc)
12743 connector->new_encoder = NULL;
12744 }
12745
b2784e15 12746 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12747 if (encoder->new_crtc == crtc)
12748 encoder->new_crtc = NULL;
12749 }
12750
12751 crtc->new_enabled = false;
12752}
12753
2e431051
DV		 12754static int intel_crtc_set_config(struct drm_mode_set *set)
12755{
12756 struct drm_device *dev;
2e431051 12757 struct drm_mode_set save_set;
83a57153 12758 struct drm_atomic_state *state = NULL;
2e431051 12759 struct intel_set_config *config;
5cec258b 12760 struct intel_crtc_state *pipe_config;
50f52756 12761 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12762 int ret;
2e431051 12763
8d3e375e
DV		 12764 BUG_ON(!set);
12765 BUG_ON(!set->crtc);
12766 BUG_ON(!set->crtc->helper_private);
2e431051 12767
7e53f3a4
DV		 12768 /* Enforce sane interface api - has been abused by the fb helper. */
12769 BUG_ON(!set->mode && set->fb);
12770 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12771
2e431051
DV		 12772 if (set->fb) {
12773 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12774 set->crtc->base.id, set->fb->base.id,
12775 (int)set->num_connectors, set->x, set->y);
12776 } else {
12777 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12778 }
12779
12780 dev = set->crtc->dev;
12781
12782 ret = -ENOMEM;
12783 config = kzalloc(sizeof(*config), GFP_KERNEL);
12784 if (!config)
12785 goto out_config;
12786
12787 ret = intel_set_config_save_state(dev, config);
12788 if (ret)
12789 goto out_config;
12790
12791 save_set.crtc = set->crtc;
12792 save_set.mode = &set->crtc->mode;
12793 save_set.x = set->crtc->x;
12794 save_set.y = set->crtc->y;
f4510a27 12795 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12796
12797 /* Compute whether we need a full modeset, only an fb base update or no
12798 * change at all. In the future we might also check whether only the
12799 * mode changed, e.g. for LVDS where we only change the panel fitter in
12800 * such cases. */
12801 intel_set_config_compute_mode_changes(set, config);
12802
83a57153
ACO		 12803 state = drm_atomic_state_alloc(dev);
12804 if (!state) {
12805 ret = -ENOMEM;
12806 goto out_config;
12807 }
12808
12809 state->acquire_ctx = dev->mode_config.acquire_ctx;
12810
944b0c76 12811 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12812 if (ret)
12813 goto fail;
12814
50f52756 12815 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
8805aa71 12816 state,
50f52756
JB		 12817 &modeset_pipes,
12818 &prepare_pipes,
12819 &disable_pipes);
20664591 12820 if (IS_ERR(pipe_config)) {
6ac0483b 12821 ret = PTR_ERR(pipe_config);
50f52756 12822 goto fail;
20664591 12823 } else if (pipe_config) {
b9950a13 12824 if (pipe_config->has_audio !=
6e3c9717 12825 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12826 config->mode_changed = true;
12827
af15d2ce
JB		 12828 /*
12829 * Note we have an issue here with infoframes: current code
12830 * only updates them on the full mode set path per hw
12831 * requirements. So here we should be checking for any
12832 * required changes and forcing a mode set.
12833 */
20664591 12834 }
50f52756 12835
1f9954d0
JB		 12836 intel_update_pipe_size(to_intel_crtc(set->crtc));
12837
5e2b584e 12838 if (config->mode_changed) {
50f52756
JB		 12839 ret = intel_set_mode_pipes(set->crtc, set->mode,
12840 set->x, set->y, set->fb, pipe_config,
12841 modeset_pipes, prepare_pipes,
12842 disable_pipes);
5e2b584e 12843 } else if (config->fb_changed) {
3b150f08 12844 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12845 struct drm_plane *primary = set->crtc->primary;
12846 int vdisplay, hdisplay;
3b150f08 12847
455a6808 12848 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12849 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12850 0, 0, hdisplay, vdisplay,
12851 set->x << 16, set->y << 16,
12852 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12853
12854 /*
12855 * We need to make sure the primary plane is re-enabled if it
12856 * has previously been turned off.
12857 */
12858 if (!intel_crtc->primary_enabled && ret == 0) {
12859 WARN_ON(!intel_crtc->active);
fdd508a6 12860 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12861 }
12862
7ca51a3a
JB		 12863 /*
12864 * In the fastboot case this may be our only check of the
12865 * state after boot. It would be better to only do it on
12866 * the first update, but we don't have a nice way of doing that
12867 * (and really, set_config isn't used much for high freq page
12868 * flipping, so increasing its cost here shouldn't be a big
12869 * deal).
12870 */
d330a953 12871 if (i915.fastboot && ret == 0)
7ca51a3a 12872 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12873 }
12874
2d05eae1 12875 if (ret) {
bf67dfeb
DV		 12876 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12877 set->crtc->base.id, ret);
50f56119 12878fail:
2d05eae1 12879 intel_set_config_restore_state(dev, config);
50f56119 12880
83a57153
ACO		 12881 drm_atomic_state_clear(state);
12882
7d00a1f5
VS		 12883 /*
12884 * HACK: if the pipe was on, but we didn't have a framebuffer,
12885 * force the pipe off to avoid oopsing in the modeset code
12886 * due to fb==NULL. This should only happen during boot since
12887 * we don't yet reconstruct the FB from the hardware state.
12888 */
12889 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12890 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12891
2d05eae1
CW		 12892 /* Try to restore the config */
12893 if (config->mode_changed &&
12894 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12895 save_set.x, save_set.y, save_set.fb,
12896 state))
2d05eae1
CW		 12897 DRM_ERROR("failed to restore config after modeset failure\n");
12898 }
50f56119 12899
d9e55608 12900out_config:
83a57153
ACO		 12901 if (state)
12902 drm_atomic_state_free(state);
12903
d9e55608 12904 intel_set_config_free(config);
50f56119
DV		 12905 return ret;
12906}
f6e5b160
CW		 12907
12908static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12909 .gamma_set = intel_crtc_gamma_set,
50f56119 12910 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12911 .destroy = intel_crtc_destroy,
12912 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12913 .atomic_duplicate_state = intel_crtc_duplicate_state,
12914 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12915};
12916
5358901f
DV		 12917static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12918 struct intel_shared_dpll *pll,
12919 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12920{
5358901f 12921 uint32_t val;
ee7b9f93 12922
f458ebbc 12923 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12924 return false;
12925
5358901f 12926 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12927 hw_state->dpll = val;
12928 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12929 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12930
12931 return val & DPLL_VCO_ENABLE;
12932}
12933
15bdd4cf
DV		 12934static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12935 struct intel_shared_dpll *pll)
12936{
3e369b76
ACO		 12937 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12938 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12939}
12940
e7b903d2
DV		 12941static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12942 struct intel_shared_dpll *pll)
12943{
e7b903d2 12944 /* PCH refclock must be enabled first */
89eff4be 12945 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12946
3e369b76 12947 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12948
12949 /* Wait for the clocks to stabilize. */
12950 POSTING_READ(PCH_DPLL(pll->id));
12951 udelay(150);
12952
12953 /* The pixel multiplier can only be updated once the
12954 * DPLL is enabled and the clocks are stable.
12955 *
12956 * So write it again.
12957 */
3e369b76 12958 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12959 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12960 udelay(200);
12961}
12962
12963static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12964 struct intel_shared_dpll *pll)
12965{
12966 struct drm_device *dev = dev_priv->dev;
12967 struct intel_crtc *crtc;
e7b903d2
DV		 12968
12969 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12970 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12971 if (intel_crtc_to_shared_dpll(crtc) == pll)
12972 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12973 }
12974
15bdd4cf
DV		 12975 I915_WRITE(PCH_DPLL(pll->id), 0);
12976 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12977 udelay(200);
12978}
12979
46edb027
DV		 12980static char *ibx_pch_dpll_names[] = {
12981 "PCH DPLL A",
12982 "PCH DPLL B",
12983};
12984
7c74ade1 12985static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12986{
e7b903d2 12987 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12988 int i;
12989
7c74ade1 12990 dev_priv->num_shared_dpll = 2;
ee7b9f93 12991
e72f9fbf 12992 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12993 dev_priv->shared_dplls[i].id = i;
12994 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12995 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12996 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12997 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12998 dev_priv->shared_dplls[i].get_hw_state =
12999 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13000 }
13001}
13002
7c74ade1
DV		 13003static void intel_shared_dpll_init(struct drm_device *dev)
13004{
e7b903d2 13005 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13006
9cd86933
DV		 13007 if (HAS_DDI(dev))
13008 intel_ddi_pll_init(dev);
13009 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13010 ibx_pch_dpll_init(dev);
13011 else
13012 dev_priv->num_shared_dpll = 0;
13013
13014 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13015}
13016
1fc0a8f7
TU		 13017/**
13018 * intel_wm_need_update - Check whether watermarks need updating
13019 * @plane: drm plane
13020 * @state: new plane state
13021 *
13022 * Check current plane state versus the new one to determine whether
13023 * watermarks need to be recalculated.
13024 *
13025 * Returns true or false.
13026 */
13027bool intel_wm_need_update(struct drm_plane *plane,
13028 struct drm_plane_state *state)
13029{
13030 /* Update watermarks on tiling changes. */
13031 if (!plane->state->fb || !state->fb ||
13032 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13033 plane->state->rotation != state->rotation)
13034 return true;
13035
13036 return false;
13037}
13038
6beb8c23
MR		 13039/**
13040 * intel_prepare_plane_fb - Prepare fb for usage on plane
13041 * @plane: drm plane to prepare for
13042 * @fb: framebuffer to prepare for presentation
13043 *
13044 * Prepares a framebuffer for usage on a display plane. Generally this
13045 * involves pinning the underlying object and updating the frontbuffer tracking
13046 * bits. Some older platforms need special physical address handling for
13047 * cursor planes.
13048 *
13049 * Returns 0 on success, negative error code on failure.
13050 */
13051int
13052intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13053 struct drm_framebuffer *fb,
13054 const struct drm_plane_state *new_state)
465c120c
MR		 13055{
13056 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13057 struct intel_plane *intel_plane = to_intel_plane(plane);
13058 enum pipe pipe = intel_plane->pipe;
13059 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13060 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13061 unsigned frontbuffer_bits = 0;
13062 int ret = 0;
465c120c 13063
ea2c67bb 13064 if (!obj)
465c120c
MR		 13065 return 0;
13066
6beb8c23
MR		 13067 switch (plane->type) {
13068 case DRM_PLANE_TYPE_PRIMARY:
13069 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13070 break;
13071 case DRM_PLANE_TYPE_CURSOR:
13072 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13073 break;
13074 case DRM_PLANE_TYPE_OVERLAY:
13075 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13076 break;
13077 }
465c120c 13078
6beb8c23 13079 mutex_lock(&dev->struct_mutex);
465c120c 13080
6beb8c23
MR		 13081 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13082 INTEL_INFO(dev)->cursor_needs_physical) {
13083 int align = IS_I830(dev) ? 16 * 1024 : 256;
13084 ret = i915_gem_object_attach_phys(obj, align);
13085 if (ret)
13086 DRM_DEBUG_KMS("failed to attach phys object\n");
13087 } else {
82bc3b2d 13088 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13089 }
465c120c 13090
6beb8c23
MR		 13091 if (ret == 0)
13092 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13093
4c34574f 13094 mutex_unlock(&dev->struct_mutex);
465c120c 13095
6beb8c23
MR		 13096 return ret;
13097}
13098
38f3ce3a
MR		 13099/**
13100 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13101 * @plane: drm plane to clean up for
13102 * @fb: old framebuffer that was on plane
13103 *
13104 * Cleans up a framebuffer that has just been removed from a plane.
13105 */
13106void
13107intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13108 struct drm_framebuffer *fb,
13109 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13110{
13111 struct drm_device *dev = plane->dev;
13112 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13113
13114 if (WARN_ON(!obj))
13115 return;
13116
13117 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13118 !INTEL_INFO(dev)->cursor_needs_physical) {
13119 mutex_lock(&dev->struct_mutex);
82bc3b2d 13120 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13121 mutex_unlock(&dev->struct_mutex);
13122 }
465c120c
MR		 13123}
13124
13125static int
3c692a41
GP		 13126intel_check_primary_plane(struct drm_plane *plane,
13127 struct intel_plane_state *state)
13128{
32b7eeec
MR		 13129 struct drm_device *dev = plane->dev;
13130 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13131 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13132 struct intel_crtc *intel_crtc;
2b875c22 13133 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13134 struct drm_rect *dest = &state->dst;
13135 struct drm_rect *src = &state->src;
13136 const struct drm_rect *clip = &state->clip;
d8106366 13137 bool can_position = false;
465c120c
MR		 13138 int ret;
13139
ea2c67bb
MR		 13140 crtc = crtc ? crtc : plane->crtc;
13141 intel_crtc = to_intel_crtc(crtc);
13142
d8106366
SJ		 13143 if (INTEL_INFO(dev)->gen >= 9)
13144 can_position = true;
13145
c59cb179
MR		 13146 ret = drm_plane_helper_check_update(plane, crtc, fb,
13147 src, dest, clip,
13148 DRM_PLANE_HELPER_NO_SCALING,
13149 DRM_PLANE_HELPER_NO_SCALING,
d8106366
SJ		 13150 can_position, true,
13151 &state->visible);
c59cb179
MR		 13152 if (ret)
13153 return ret;
465c120c 13154
32b7eeec
MR		 13155 if (intel_crtc->active) {
13156 intel_crtc->atomic.wait_for_flips = true;
13157
13158 /*
13159 * FBC does not work on some platforms for rotated
13160 * planes, so disable it when rotation is not 0 and
13161 * update it when rotation is set back to 0.
13162 *
13163 * FIXME: This is redundant with the fbc update done in
13164 * the primary plane enable function except that that
13165 * one is done too late. We eventually need to unify
13166 * this.
13167 */
13168 if (intel_crtc->primary_enabled &&
13169 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13170 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13171 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13172 intel_crtc->atomic.disable_fbc = true;
13173 }
13174
13175 if (state->visible) {
13176 /*
13177 * BDW signals flip done immediately if the plane
13178 * is disabled, even if the plane enable is already
13179 * armed to occur at the next vblank :(
13180 */
13181 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
13182 intel_crtc->atomic.wait_vblank = true;
13183 }
13184
13185 intel_crtc->atomic.fb_bits |=
13186 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13187
13188 intel_crtc->atomic.update_fbc = true;
0fda6568 13189
1fc0a8f7 13190 if (intel_wm_need_update(plane, &state->base))
0fda6568 13191 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13192 }
13193
14af293f
GP		 13194 return 0;
13195}
13196
13197static void
13198intel_commit_primary_plane(struct drm_plane *plane,
13199 struct intel_plane_state *state)
13200{
2b875c22
MR		 13201 struct drm_crtc *crtc = state->base.crtc;
13202 struct drm_framebuffer *fb = state->base.fb;
13203 struct drm_device *dev = plane->dev;
14af293f 13204 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13205 struct intel_crtc *intel_crtc;
14af293f
GP		 13206 struct drm_rect *src = &state->src;
13207
ea2c67bb
MR		 13208 crtc = crtc ? crtc : plane->crtc;
13209 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13210
13211 plane->fb = fb;
9dc806fc
MR		 13212 crtc->x = src->x1 >> 16;
13213 crtc->y = src->y1 >> 16;
ccc759dc 13214
ccc759dc 13215 if (intel_crtc->active) {
ccc759dc 13216 if (state->visible) {
ccc759dc
GP		 13217 /* FIXME: kill this fastboot hack */
13218 intel_update_pipe_size(intel_crtc);
465c120c 13219
ccc759dc 13220 intel_crtc->primary_enabled = true;
465c120c 13221
ccc759dc
GP		 13222 dev_priv->display.update_primary_plane(crtc, plane->fb,
13223 crtc->x, crtc->y);
ccc759dc
GP		 13224 } else {
13225 /*
13226 * If clipping results in a non-visible primary plane,
13227 * we'll disable the primary plane. Note that this is
13228 * a bit different than what happens if userspace
13229 * explicitly disables the plane by passing fb=0
13230 * because plane->fb still gets set and pinned.
13231 */
13232 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 13233 }
ccc759dc 13234 }
465c120c
MR		 13235}
13236
32b7eeec 13237static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13238{
32b7eeec 13239 struct drm_device *dev = crtc->dev;
140fd38d 13240 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13242 struct intel_plane *intel_plane;
13243 struct drm_plane *p;
13244 unsigned fb_bits = 0;
13245
13246 /* Track fb's for any planes being disabled */
13247 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13248 intel_plane = to_intel_plane(p);
13249
13250 if (intel_crtc->atomic.disabled_planes &
13251 (1 << drm_plane_index(p))) {
13252 switch (p->type) {
13253 case DRM_PLANE_TYPE_PRIMARY:
13254 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13255 break;
13256 case DRM_PLANE_TYPE_CURSOR:
13257 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13258 break;
13259 case DRM_PLANE_TYPE_OVERLAY:
13260 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13261 break;
13262 }
3c692a41 13263
ea2c67bb
MR		 13264 mutex_lock(&dev->struct_mutex);
13265 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13266 mutex_unlock(&dev->struct_mutex);
13267 }
13268 }
3c692a41 13269
32b7eeec
MR		 13270 if (intel_crtc->atomic.wait_for_flips)
13271 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13272
32b7eeec
MR		 13273 if (intel_crtc->atomic.disable_fbc)
13274 intel_fbc_disable(dev);
3c692a41 13275
32b7eeec
MR		 13276 if (intel_crtc->atomic.pre_disable_primary)
13277 intel_pre_disable_primary(crtc);
3c692a41 13278
32b7eeec
MR		 13279 if (intel_crtc->atomic.update_wm)
13280 intel_update_watermarks(crtc);
3c692a41 13281
32b7eeec 13282 intel_runtime_pm_get(dev_priv);
3c692a41 13283
c34c9ee4
MR		 13284 /* Perform vblank evasion around commit operation */
13285 if (intel_crtc->active)
13286 intel_crtc->atomic.evade =
13287 intel_pipe_update_start(intel_crtc,
13288 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13289}
13290
13291static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13292{
13293 struct drm_device *dev = crtc->dev;
13294 struct drm_i915_private *dev_priv = dev->dev_private;
13295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13296 struct drm_plane *p;
13297
c34c9ee4
MR		 13298 if (intel_crtc->atomic.evade)
13299 intel_pipe_update_end(intel_crtc,
13300 intel_crtc->atomic.start_vbl_count);
3c692a41 13301
140fd38d 13302 intel_runtime_pm_put(dev_priv);
3c692a41 13303
32b7eeec
MR		 13304 if (intel_crtc->atomic.wait_vblank)
13305 intel_wait_for_vblank(dev, intel_crtc->pipe);
13306
13307 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13308
13309 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13310 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13311 intel_fbc_update(dev);
ccc759dc 13312 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13313 }
3c692a41 13314
32b7eeec
MR		 13315 if (intel_crtc->atomic.post_enable_primary)
13316 intel_post_enable_primary(crtc);
3c692a41 13317
32b7eeec
MR		 13318 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13319 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13320 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13321 false, false);
13322
13323 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13324}
13325
cf4c7c12 13326/**
4a3b8769
MR		 13327 * intel_plane_destroy - destroy a plane
13328 * @plane: plane to destroy
cf4c7c12 13329 *
4a3b8769
MR		 13330 * Common destruction function for all types of planes (primary, cursor,
13331 * sprite).
cf4c7c12 13332 */
4a3b8769 13333void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13334{
13335 struct intel_plane *intel_plane = to_intel_plane(plane);
13336 drm_plane_cleanup(plane);
13337 kfree(intel_plane);
13338}
13339
65a3fea0 13340const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13341 .update_plane = drm_atomic_helper_update_plane,
13342 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13343 .destroy = intel_plane_destroy,
c196e1d6 13344 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13345 .atomic_get_property = intel_plane_atomic_get_property,
13346 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13347 .atomic_duplicate_state = intel_plane_duplicate_state,
13348 .atomic_destroy_state = intel_plane_destroy_state,
13349
465c120c
MR		 13350};
13351
13352static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13353 int pipe)
13354{
13355 struct intel_plane *primary;
8e7d688b 13356 struct intel_plane_state *state;
465c120c
MR		 13357 const uint32_t *intel_primary_formats;
13358 int num_formats;
13359
13360 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13361 if (primary == NULL)
13362 return NULL;
13363
8e7d688b
MR		 13364 state = intel_create_plane_state(&primary->base);
13365 if (!state) {
ea2c67bb
MR		 13366 kfree(primary);
13367 return NULL;
13368 }
8e7d688b 13369 primary->base.state = &state->base;
ea2c67bb 13370
465c120c
MR		 13371 primary->can_scale = false;
13372 primary->max_downscale = 1;
549e2bfb 13373 state->scaler_id = -1;
465c120c
MR		 13374 primary->pipe = pipe;
13375 primary->plane = pipe;
c59cb179
MR		 13376 primary->check_plane = intel_check_primary_plane;
13377 primary->commit_plane = intel_commit_primary_plane;
08e221fb 13378 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13379 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13380 primary->plane = !pipe;
13381
13382 if (INTEL_INFO(dev)->gen <= 3) {
13383 intel_primary_formats = intel_primary_formats_gen2;
13384 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13385 } else {
13386 intel_primary_formats = intel_primary_formats_gen4;
13387 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13388 }
13389
13390 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13391 &intel_plane_funcs,
465c120c
MR		 13392 intel_primary_formats, num_formats,
13393 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13394
3b7a5119
SJ		 13395 if (INTEL_INFO(dev)->gen >= 4)
13396 intel_create_rotation_property(dev, primary);
48404c1e 13397
ea2c67bb
MR		 13398 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13399
465c120c
MR		 13400 return &primary->base;
13401}
13402
3b7a5119
SJ		 13403void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13404{
13405 if (!dev->mode_config.rotation_property) {
13406 unsigned long flags = BIT(DRM_ROTATE_0) |
13407 BIT(DRM_ROTATE_180);
13408
13409 if (INTEL_INFO(dev)->gen >= 9)
13410 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13411
13412 dev->mode_config.rotation_property =
13413 drm_mode_create_rotation_property(dev, flags);
13414 }
13415 if (dev->mode_config.rotation_property)
13416 drm_object_attach_property(&plane->base.base,
13417 dev->mode_config.rotation_property,
13418 plane->base.state->rotation);
13419}
13420
3d7d6510 13421static int
852e787c
GP		 13422intel_check_cursor_plane(struct drm_plane *plane,
13423 struct intel_plane_state *state)
3d7d6510 13424{
2b875c22 13425 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13426 struct drm_device *dev = plane->dev;
2b875c22 13427 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13428 struct drm_rect *dest = &state->dst;
13429 struct drm_rect *src = &state->src;
13430 const struct drm_rect *clip = &state->clip;
757f9a3e 13431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13432 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13433 unsigned stride;
13434 int ret;
3d7d6510 13435
ea2c67bb
MR		 13436 crtc = crtc ? crtc : plane->crtc;
13437 intel_crtc = to_intel_crtc(crtc);
13438
757f9a3e 13439 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13440 src, dest, clip,
3d7d6510
MR		 13441 DRM_PLANE_HELPER_NO_SCALING,
13442 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13443 true, true, &state->visible);
757f9a3e
GP		 13444 if (ret)
13445 return ret;
13446
13447
13448 /* if we want to turn off the cursor ignore width and height */
13449 if (!obj)
32b7eeec 13450 goto finish;
757f9a3e 13451
757f9a3e 13452 /* Check for which cursor types we support */
ea2c67bb
MR		 13453 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13454 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13455 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13456 return -EINVAL;
13457 }
13458
ea2c67bb
MR		 13459 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13460 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13461 DRM_DEBUG_KMS("buffer is too small\n");
13462 return -ENOMEM;
13463 }
13464
3a656b54 13465 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13466 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13467 ret = -EINVAL;
13468 }
757f9a3e 13469
32b7eeec
MR		 13470finish:
13471 if (intel_crtc->active) {
3749f463 13472 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13473 intel_crtc->atomic.update_wm = true;
13474
13475 intel_crtc->atomic.fb_bits |=
13476 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13477 }
13478
757f9a3e 13479 return ret;
852e787c 13480}
3d7d6510 13481
f4a2cf29 13482static void
852e787c
GP		 13483intel_commit_cursor_plane(struct drm_plane *plane,
13484 struct intel_plane_state *state)
13485{
2b875c22 13486 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13487 struct drm_device *dev = plane->dev;
13488 struct intel_crtc *intel_crtc;
2b875c22 13489 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13490 uint32_t addr;
852e787c 13491
ea2c67bb
MR		 13492 crtc = crtc ? crtc : plane->crtc;
13493 intel_crtc = to_intel_crtc(crtc);
13494
2b875c22 13495 plane->fb = state->base.fb;
ea2c67bb
MR		 13496 crtc->cursor_x = state->base.crtc_x;
13497 crtc->cursor_y = state->base.crtc_y;
13498
a912f12f
GP		 13499 if (intel_crtc->cursor_bo == obj)
13500 goto update;
4ed91096 13501
f4a2cf29 13502 if (!obj)
a912f12f 13503 addr = 0;
f4a2cf29 13504 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13505 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13506 else
a912f12f 13507 addr = obj->phys_handle->busaddr;
852e787c 13508
a912f12f
GP		 13509 intel_crtc->cursor_addr = addr;
13510 intel_crtc->cursor_bo = obj;
13511update:
852e787c 13512
32b7eeec 13513 if (intel_crtc->active)
a912f12f 13514 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13515}
13516
3d7d6510
MR		 13517static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13518 int pipe)
13519{
13520 struct intel_plane *cursor;
8e7d688b 13521 struct intel_plane_state *state;
3d7d6510
MR		 13522
13523 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13524 if (cursor == NULL)
13525 return NULL;
13526
8e7d688b
MR		 13527 state = intel_create_plane_state(&cursor->base);
13528 if (!state) {
ea2c67bb
MR		 13529 kfree(cursor);
13530 return NULL;
13531 }
8e7d688b 13532 cursor->base.state = &state->base;
ea2c67bb 13533
3d7d6510
MR		 13534 cursor->can_scale = false;
13535 cursor->max_downscale = 1;
13536 cursor->pipe = pipe;
13537 cursor->plane = pipe;
549e2bfb 13538 state->scaler_id = -1;
c59cb179
MR		 13539 cursor->check_plane = intel_check_cursor_plane;
13540 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 13541
13542 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13543 &intel_plane_funcs,
3d7d6510
MR		 13544 intel_cursor_formats,
13545 ARRAY_SIZE(intel_cursor_formats),
13546 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13547
13548 if (INTEL_INFO(dev)->gen >= 4) {
13549 if (!dev->mode_config.rotation_property)
13550 dev->mode_config.rotation_property =
13551 drm_mode_create_rotation_property(dev,
13552 BIT(DRM_ROTATE_0) |
13553 BIT(DRM_ROTATE_180));
13554 if (dev->mode_config.rotation_property)
13555 drm_object_attach_property(&cursor->base.base,
13556 dev->mode_config.rotation_property,
8e7d688b 13557 state->base.rotation);
4398ad45
VS		 13558 }
13559
ea2c67bb
MR		 13560 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13561
3d7d6510
MR		 13562 return &cursor->base;
13563}
13564
549e2bfb
CK		 13565static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13566 struct intel_crtc_state *crtc_state)
13567{
13568 int i;
13569 struct intel_scaler *intel_scaler;
13570 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13571
13572 for (i = 0; i < intel_crtc->num_scalers; i++) {
13573 intel_scaler = &scaler_state->scalers[i];
13574 intel_scaler->in_use = 0;
13575 intel_scaler->id = i;
13576
13577 intel_scaler->mode = PS_SCALER_MODE_DYN;
13578 }
13579
13580 scaler_state->scaler_id = -1;
13581}
13582
b358d0a6 13583static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13584{
fbee40df 13585 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13586 struct intel_crtc *intel_crtc;
f5de6e07 13587 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13588 struct drm_plane *primary = NULL;
13589 struct drm_plane *cursor = NULL;
465c120c 13590 int i, ret;
79e53945 13591
955382f3 13592 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13593 if (intel_crtc == NULL)
13594 return;
13595
f5de6e07
ACO		 13596 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13597 if (!crtc_state)
13598 goto fail;
13599 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13600 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13601
549e2bfb
CK		 13602 /* initialize shared scalers */
13603 if (INTEL_INFO(dev)->gen >= 9) {
13604 if (pipe == PIPE_C)
13605 intel_crtc->num_scalers = 1;
13606 else
13607 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13608
13609 skl_init_scalers(dev, intel_crtc, crtc_state);
13610 }
13611
465c120c 13612 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13613 if (!primary)
13614 goto fail;
13615
13616 cursor = intel_cursor_plane_create(dev, pipe);
13617 if (!cursor)
13618 goto fail;
13619
465c120c 13620 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13621 cursor, &intel_crtc_funcs);
13622 if (ret)
13623 goto fail;
79e53945
JB		 13624
13625 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13626 for (i = 0; i < 256; i++) {
13627 intel_crtc->lut_r[i] = i;
13628 intel_crtc->lut_g[i] = i;
13629 intel_crtc->lut_b[i] = i;
13630 }
13631
1f1c2e24
VS		 13632 /*
13633 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13634 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13635 */
80824003
JB		 13636 intel_crtc->pipe = pipe;
13637 intel_crtc->plane = pipe;
3a77c4c4 13638 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13639 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13640 intel_crtc->plane = !pipe;
80824003
JB		 13641 }
13642
4b0e333e
CW		 13643 intel_crtc->cursor_base = ~0;
13644 intel_crtc->cursor_cntl = ~0;
dc41c154 13645 intel_crtc->cursor_size = ~0;
8d7849db 13646
22fd0fab
JB		 13647 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13648 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13649 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13650 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13651
9362c7c5
ACO		 13652 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13653
79e53945 13654 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13655
13656 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13657 return;
13658
13659fail:
13660 if (primary)
13661 drm_plane_cleanup(primary);
13662 if (cursor)
13663 drm_plane_cleanup(cursor);
f5de6e07 13664 kfree(crtc_state);
3d7d6510 13665 kfree(intel_crtc);
79e53945
JB		 13666}
13667
752aa88a
JB		 13668enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13669{
13670 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13671 struct drm_device *dev = connector->base.dev;
752aa88a 13672
51fd371b 13673 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13674
d3babd3f 13675 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13676 return INVALID_PIPE;
13677
13678 return to_intel_crtc(encoder->crtc)->pipe;
13679}
13680
08d7b3d1 13681int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13682 struct drm_file *file)
08d7b3d1 13683{
08d7b3d1 13684 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13685 struct drm_crtc *drmmode_crtc;
c05422d5 13686 struct intel_crtc *crtc;
08d7b3d1 13687
7707e653 13688 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13689
7707e653 13690 if (!drmmode_crtc) {
08d7b3d1 13691 DRM_ERROR("no such CRTC id\n");
3f2c2057 13692 return -ENOENT;
08d7b3d1
CW		 13693 }
13694
7707e653 13695 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13696 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13697
c05422d5 13698 return 0;
08d7b3d1
CW		 13699}
13700
66a9278e 13701static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13702{
66a9278e
DV		 13703 struct drm_device *dev = encoder->base.dev;
13704 struct intel_encoder *source_encoder;
79e53945 13705 int index_mask = 0;
79e53945
JB		 13706 int entry = 0;
13707
b2784e15 13708 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13709 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13710 index_mask |= (1 << entry);
13711
79e53945
JB		 13712 entry++;
13713 }
4ef69c7a 13714
79e53945
JB		 13715 return index_mask;
13716}
13717
4d302442
CW		 13718static bool has_edp_a(struct drm_device *dev)
13719{
13720 struct drm_i915_private *dev_priv = dev->dev_private;
13721
13722 if (!IS_MOBILE(dev))
13723 return false;
13724
13725 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13726 return false;
13727
e3589908 13728 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13729 return false;
13730
13731 return true;
13732}
13733
84b4e042
JB		 13734static bool intel_crt_present(struct drm_device *dev)
13735{
13736 struct drm_i915_private *dev_priv = dev->dev_private;
13737
884497ed
DL		 13738 if (INTEL_INFO(dev)->gen >= 9)
13739 return false;
13740
cf404ce4 13741 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13742 return false;
13743
13744 if (IS_CHERRYVIEW(dev))
13745 return false;
13746
13747 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13748 return false;
13749
13750 return true;
13751}
13752
79e53945
JB		 13753static void intel_setup_outputs(struct drm_device *dev)
13754{
725e30ad 13755 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13756 struct intel_encoder *encoder;
cb0953d7 13757 bool dpd_is_edp = false;
79e53945 13758
c9093354 13759 intel_lvds_init(dev);
79e53945 13760
84b4e042 13761 if (intel_crt_present(dev))
79935fca 13762 intel_crt_init(dev);
cb0953d7 13763
c776eb2e
VK		 13764 if (IS_BROXTON(dev)) {
13765 /*
13766 * FIXME: Broxton doesn't support port detection via the
13767 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13768 * detect the ports.
13769 */
13770 intel_ddi_init(dev, PORT_A);
13771 intel_ddi_init(dev, PORT_B);
13772 intel_ddi_init(dev, PORT_C);
13773 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13774 int found;
13775
de31facd
JB		 13776 /*
13777 * Haswell uses DDI functions to detect digital outputs.
13778 * On SKL pre-D0 the strap isn't connected, so we assume
13779 * it's there.
13780 */
0e72a5b5 13781 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13782 /* WaIgnoreDDIAStrap: skl */
13783 if (found ||
13784 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13785 intel_ddi_init(dev, PORT_A);
13786
13787 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13788 * register */
13789 found = I915_READ(SFUSE_STRAP);
13790
13791 if (found & SFUSE_STRAP_DDIB_DETECTED)
13792 intel_ddi_init(dev, PORT_B);
13793 if (found & SFUSE_STRAP_DDIC_DETECTED)
13794 intel_ddi_init(dev, PORT_C);
13795 if (found & SFUSE_STRAP_DDID_DETECTED)
13796 intel_ddi_init(dev, PORT_D);
13797 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13798 int found;
5d8a7752 13799 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13800
13801 if (has_edp_a(dev))
13802 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13803
dc0fa718 13804 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13805 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13806 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13807 if (!found)
e2debe91 13808 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13809 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13810 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13811 }
13812
dc0fa718 13813 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13814 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13815
dc0fa718 13816 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13817 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13818
5eb08b69 13819 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13820 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13821
270b3042 13822 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13823 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13824 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13825 /*
13826 * The DP_DETECTED bit is the latched state of the DDC
13827 * SDA pin at boot. However since eDP doesn't require DDC
13828 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13829 * eDP ports may have been muxed to an alternate function.
13830 * Thus we can't rely on the DP_DETECTED bit alone to detect
13831 * eDP ports. Consult the VBT as well as DP_DETECTED to
13832 * detect eDP ports.
13833 */
d2182a66
VS		 13834 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13835 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13836 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13837 PORT_B);
e17ac6db
VS		 13838 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13839 intel_dp_is_edp(dev, PORT_B))
13840 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13841
d2182a66
VS		 13842 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13843 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13844 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13845 PORT_C);
e17ac6db
VS		 13846 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13847 intel_dp_is_edp(dev, PORT_C))
13848 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13849
9418c1f1 13850 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13851 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13852 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13853 PORT_D);
e17ac6db
VS		 13854 /* eDP not supported on port D, so don't check VBT */
13855 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13856 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13857 }
13858
3cfca973 13859 intel_dsi_init(dev);
103a196f 13860 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13861 bool found = false;
7d57382e 13862
e2debe91 13863 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13864 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13865 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13866 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13867 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13868 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13869 }
27185ae1 13870
e7281eab 13871 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13872 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13873 }
13520b05
KH		 13874
13875 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13876
e2debe91 13877 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13878 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13879 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13880 }
27185ae1 13881
e2debe91 13882 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13883
b01f2c3a
JB		 13884 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13885 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13886 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13887 }
e7281eab 13888 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13889 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13890 }
27185ae1 13891
b01f2c3a 13892 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13893 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13894 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13895 } else if (IS_GEN2(dev))
79e53945
JB		 13896 intel_dvo_init(dev);
13897
103a196f 13898 if (SUPPORTS_TV(dev))
79e53945
JB		 13899 intel_tv_init(dev);
13900
0bc12bcb 13901 intel_psr_init(dev);
7c8f8a70 13902
b2784e15 13903 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13904 encoder->base.possible_crtcs = encoder->crtc_mask;
13905 encoder->base.possible_clones =
66a9278e 13906 intel_encoder_clones(encoder);
79e53945 13907 }
47356eb6 13908
dde86e2d 13909 intel_init_pch_refclk(dev);
270b3042
DV		 13910
13911 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13912}
13913
13914static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13915{
60a5ca01 13916 struct drm_device *dev = fb->dev;
79e53945 13917 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13918
ef2d633e 13919 drm_framebuffer_cleanup(fb);
60a5ca01 13920 mutex_lock(&dev->struct_mutex);
ef2d633e 13921 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13922 drm_gem_object_unreference(&intel_fb->obj->base);
13923 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13924 kfree(intel_fb);
13925}
13926
13927static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13928 struct drm_file *file,
79e53945
JB		 13929 unsigned int *handle)
13930{
13931 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13932 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13933
05394f39 13934 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13935}
13936
13937static const struct drm_framebuffer_funcs intel_fb_funcs = {
13938 .destroy = intel_user_framebuffer_destroy,
13939 .create_handle = intel_user_framebuffer_create_handle,
13940};
13941
b321803d
DL		 13942static
13943u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13944 uint32_t pixel_format)
13945{
13946 u32 gen = INTEL_INFO(dev)->gen;
13947
13948 if (gen >= 9) {
13949 /* "The stride in bytes must not exceed the of the size of 8K
13950 * pixels and 32K bytes."
13951 */
13952 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13953 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13954 return 32*1024;
13955 } else if (gen >= 4) {
13956 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13957 return 16*1024;
13958 else
13959 return 32*1024;
13960 } else if (gen >= 3) {
13961 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13962 return 8*1024;
13963 else
13964 return 16*1024;
13965 } else {
13966 /* XXX DSPC is limited to 4k tiled */
13967 return 8*1024;
13968 }
13969}
13970
b5ea642a
DV		 13971static int intel_framebuffer_init(struct drm_device *dev,
13972 struct intel_framebuffer *intel_fb,
13973 struct drm_mode_fb_cmd2 *mode_cmd,
13974 struct drm_i915_gem_object *obj)
79e53945 13975{
6761dd31 13976 unsigned int aligned_height;
79e53945 13977 int ret;
b321803d 13978 u32 pitch_limit, stride_alignment;
79e53945 13979
dd4916c5
DV		 13980 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13981
2a80eada
DV		 13982 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13983 /* Enforce that fb modifier and tiling mode match, but only for
13984 * X-tiled. This is needed for FBC. */
13985 if (!!(obj->tiling_mode == I915_TILING_X) !=
13986 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13987 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13988 return -EINVAL;
13989 }
13990 } else {
13991 if (obj->tiling_mode == I915_TILING_X)
13992 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13993 else if (obj->tiling_mode == I915_TILING_Y) {
13994 DRM_DEBUG("No Y tiling for legacy addfb\n");
13995 return -EINVAL;
13996 }
13997 }
13998
9a8f0a12
TU		 13999 /* Passed in modifier sanity checking. */
14000 switch (mode_cmd->modifier[0]) {
14001 case I915_FORMAT_MOD_Y_TILED:
14002 case I915_FORMAT_MOD_Yf_TILED:
14003 if (INTEL_INFO(dev)->gen < 9) {
14004 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14005 mode_cmd->modifier[0]);
14006 return -EINVAL;
14007 }
14008 case DRM_FORMAT_MOD_NONE:
14009 case I915_FORMAT_MOD_X_TILED:
14010 break;
14011 default:
c0f40428
JB		 14012 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14013 mode_cmd->modifier[0]);
57cd6508 14014 return -EINVAL;
c16ed4be 14015 }
57cd6508 14016
b321803d
DL		 14017 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14018 mode_cmd->pixel_format);
14019 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14020 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14021 mode_cmd->pitches[0], stride_alignment);
57cd6508 14022 return -EINVAL;
c16ed4be 14023 }
57cd6508 14024
b321803d
DL		 14025 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14026 mode_cmd->pixel_format);
a35cdaa0 14027 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14028 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14029 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14030 "tiled" : "linear",
a35cdaa0 14031 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14032 return -EINVAL;
c16ed4be 14033 }
5d7bd705 14034
2a80eada 14035 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14036 mode_cmd->pitches[0] != obj->stride) {
14037 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14038 mode_cmd->pitches[0], obj->stride);
5d7bd705 14039 return -EINVAL;
c16ed4be 14040 }
5d7bd705 14041
57779d06 14042 /* Reject formats not supported by any plane early. */
308e5bcb 14043 switch (mode_cmd->pixel_format) {
57779d06 14044 case DRM_FORMAT_C8:
04b3924d
VS		 14045 case DRM_FORMAT_RGB565:
14046 case DRM_FORMAT_XRGB8888:
14047 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14048 break;
14049 case DRM_FORMAT_XRGB1555:
14050 case DRM_FORMAT_ARGB1555:
c16ed4be 14051 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14052 DRM_DEBUG("unsupported pixel format: %s\n",
14053 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14054 return -EINVAL;
c16ed4be 14055 }
57779d06
VS		 14056 break;
14057 case DRM_FORMAT_XBGR8888:
14058 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14059 case DRM_FORMAT_XRGB2101010:
14060 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14061 case DRM_FORMAT_XBGR2101010:
14062 case DRM_FORMAT_ABGR2101010:
c16ed4be 14063 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14064 DRM_DEBUG("unsupported pixel format: %s\n",
14065 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14066 return -EINVAL;
c16ed4be 14067 }
b5626747 14068 break;
04b3924d
VS		 14069 case DRM_FORMAT_YUYV:
14070 case DRM_FORMAT_UYVY:
14071 case DRM_FORMAT_YVYU:
14072 case DRM_FORMAT_VYUY:
c16ed4be 14073 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14074 DRM_DEBUG("unsupported pixel format: %s\n",
14075 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14076 return -EINVAL;
c16ed4be 14077 }
57cd6508
CW		 14078 break;
14079 default:
4ee62c76
VS		 14080 DRM_DEBUG("unsupported pixel format: %s\n",
14081 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14082 return -EINVAL;
14083 }
14084
90f9a336
VS		 14085 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14086 if (mode_cmd->offsets[0] != 0)
14087 return -EINVAL;
14088
ec2c981e 14089 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14090 mode_cmd->pixel_format,
14091 mode_cmd->modifier[0]);
53155c0a
DV		 14092 /* FIXME drm helper for size checks (especially planar formats)? */
14093 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14094 return -EINVAL;
14095
c7d73f6a
DV		 14096 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14097 intel_fb->obj = obj;
80075d49 14098 intel_fb->obj->framebuffer_references++;
c7d73f6a 14099
79e53945
JB		 14100 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14101 if (ret) {
14102 DRM_ERROR("framebuffer init failed %d\n", ret);
14103 return ret;
14104 }
14105
79e53945
JB		 14106 return 0;
14107}
14108
79e53945
JB		 14109static struct drm_framebuffer *
14110intel_user_framebuffer_create(struct drm_device *dev,
14111 struct drm_file *filp,
308e5bcb 14112 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14113{
05394f39 14114 struct drm_i915_gem_object *obj;
79e53945 14115
308e5bcb
JB		 14116 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14117 mode_cmd->handles[0]));
c8725226 14118 if (&obj->base == NULL)
cce13ff7 14119 return ERR_PTR(-ENOENT);
79e53945 14120
d2dff872 14121 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14122}
14123
4520f53a 14124#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14125static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14126{
14127}
14128#endif
14129
79e53945 14130static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14131 .fb_create = intel_user_framebuffer_create,
0632fef6 14132 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14133 .atomic_check = intel_atomic_check,
14134 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14135};
14136
e70236a8
JB		 14137/* Set up chip specific display functions */
14138static void intel_init_display(struct drm_device *dev)
14139{
14140 struct drm_i915_private *dev_priv = dev->dev_private;
14141
ee9300bb
DV		 14142 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14143 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14144 else if (IS_CHERRYVIEW(dev))
14145 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14146 else if (IS_VALLEYVIEW(dev))
14147 dev_priv->display.find_dpll = vlv_find_best_dpll;
14148 else if (IS_PINEVIEW(dev))
14149 dev_priv->display.find_dpll = pnv_find_best_dpll;
14150 else
14151 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14152
bc8d7dff
DL		 14153 if (INTEL_INFO(dev)->gen >= 9) {
14154 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14155 dev_priv->display.get_initial_plane_config =
14156 skylake_get_initial_plane_config;
bc8d7dff
DL		 14157 dev_priv->display.crtc_compute_clock =
14158 haswell_crtc_compute_clock;
14159 dev_priv->display.crtc_enable = haswell_crtc_enable;
14160 dev_priv->display.crtc_disable = haswell_crtc_disable;
14161 dev_priv->display.off = ironlake_crtc_off;
14162 dev_priv->display.update_primary_plane =
14163 skylake_update_primary_plane;
14164 } else if (HAS_DDI(dev)) {
0e8ffe1b 14165 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14166 dev_priv->display.get_initial_plane_config =
14167 ironlake_get_initial_plane_config;
797d0259
ACO		 14168 dev_priv->display.crtc_compute_clock =
14169 haswell_crtc_compute_clock;
4f771f10
PZ		 14170 dev_priv->display.crtc_enable = haswell_crtc_enable;
14171 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14172 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14173 dev_priv->display.update_primary_plane =
14174 ironlake_update_primary_plane;
09b4ddf9 14175 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14176 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14177 dev_priv->display.get_initial_plane_config =
14178 ironlake_get_initial_plane_config;
3fb37703
ACO		 14179 dev_priv->display.crtc_compute_clock =
14180 ironlake_crtc_compute_clock;
76e5a89c
DV		 14181 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14182 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14183 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14184 dev_priv->display.update_primary_plane =
14185 ironlake_update_primary_plane;
89b667f8
JB		 14186 } else if (IS_VALLEYVIEW(dev)) {
14187 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14188 dev_priv->display.get_initial_plane_config =
14189 i9xx_get_initial_plane_config;
d6dfee7a 14190 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14191 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14192 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14193 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14194 dev_priv->display.update_primary_plane =
14195 i9xx_update_primary_plane;
f564048e 14196 } else {
0e8ffe1b 14197 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14198 dev_priv->display.get_initial_plane_config =
14199 i9xx_get_initial_plane_config;
d6dfee7a 14200 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14201 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14202 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14203 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14204 dev_priv->display.update_primary_plane =
14205 i9xx_update_primary_plane;
f564048e 14206 }
e70236a8 14207
e70236a8 14208 /* Returns the core display clock speed */
1652d19e
VS		 14209 if (IS_SKYLAKE(dev))
14210 dev_priv->display.get_display_clock_speed =
14211 skylake_get_display_clock_speed;
14212 else if (IS_BROADWELL(dev))
14213 dev_priv->display.get_display_clock_speed =
14214 broadwell_get_display_clock_speed;
14215 else if (IS_HASWELL(dev))
14216 dev_priv->display.get_display_clock_speed =
14217 haswell_get_display_clock_speed;
14218 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14219 dev_priv->display.get_display_clock_speed =
14220 valleyview_get_display_clock_speed;
b37a6434
VS		 14221 else if (IS_GEN5(dev))
14222 dev_priv->display.get_display_clock_speed =
14223 ilk_get_display_clock_speed;
a7c66cd8
VS		 14224 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14225 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14226 dev_priv->display.get_display_clock_speed =
14227 i945_get_display_clock_speed;
14228 else if (IS_I915G(dev))
14229 dev_priv->display.get_display_clock_speed =
14230 i915_get_display_clock_speed;
257a7ffc 14231 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14232 dev_priv->display.get_display_clock_speed =
14233 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14234 else if (IS_PINEVIEW(dev))
14235 dev_priv->display.get_display_clock_speed =
14236 pnv_get_display_clock_speed;
e70236a8
JB		 14237 else if (IS_I915GM(dev))
14238 dev_priv->display.get_display_clock_speed =
14239 i915gm_get_display_clock_speed;
14240 else if (IS_I865G(dev))
14241 dev_priv->display.get_display_clock_speed =
14242 i865_get_display_clock_speed;
f0f8a9ce 14243 else if (IS_I85X(dev))
e70236a8
JB		 14244 dev_priv->display.get_display_clock_speed =
14245 i855_get_display_clock_speed;
14246 else /* 852, 830 */
14247 dev_priv->display.get_display_clock_speed =
14248 i830_get_display_clock_speed;
14249
7c10a2b5 14250 if (IS_GEN5(dev)) {
3bb11b53 14251 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14252 } else if (IS_GEN6(dev)) {
14253 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14254 } else if (IS_IVYBRIDGE(dev)) {
14255 /* FIXME: detect B0+ stepping and use auto training */
14256 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14257 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14258 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14259 } else if (IS_VALLEYVIEW(dev)) {
14260 dev_priv->display.modeset_global_resources =
14261 valleyview_modeset_global_resources;
f8437dd1
VK		 14262 } else if (IS_BROXTON(dev)) {
14263 dev_priv->display.modeset_global_resources =
14264 broxton_modeset_global_resources;
e70236a8 14265 }
8c9f3aaf 14266
8c9f3aaf
JB		 14267 switch (INTEL_INFO(dev)->gen) {
14268 case 2:
14269 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14270 break;
14271
14272 case 3:
14273 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14274 break;
14275
14276 case 4:
14277 case 5:
14278 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14279 break;
14280
14281 case 6:
14282 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14283 break;
7c9017e5 14284 case 7:
4e0bbc31 14285 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14286 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14287 break;
830c81db 14288 case 9:
ba343e02
TU		 14289 /* Drop through - unsupported since execlist only. */
14290 default:
14291 /* Default just returns -ENODEV to indicate unsupported */
14292 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14293 }
7bd688cd
JN		 14294
14295 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14296
14297 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14298}
14299
b690e96c
JB		 14300/*
14301 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14302 * resume, or other times. This quirk makes sure that's the case for
14303 * affected systems.
14304 */
0206e353 14305static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14306{
14307 struct drm_i915_private *dev_priv = dev->dev_private;
14308
14309 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14310 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14311}
14312
b6b5d049
VS		 14313static void quirk_pipeb_force(struct drm_device *dev)
14314{
14315 struct drm_i915_private *dev_priv = dev->dev_private;
14316
14317 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14318 DRM_INFO("applying pipe b force quirk\n");
14319}
14320
435793df
KP		 14321/*
14322 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14323 */
14324static void quirk_ssc_force_disable(struct drm_device *dev)
14325{
14326 struct drm_i915_private *dev_priv = dev->dev_private;
14327 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14328 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14329}
14330
4dca20ef 14331/*
5a15ab5b
CE		 14332 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14333 * brightness value
4dca20ef
CE		 14334 */
14335static void quirk_invert_brightness(struct drm_device *dev)
14336{
14337 struct drm_i915_private *dev_priv = dev->dev_private;
14338 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14339 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14340}
14341
9c72cc6f
SD		 14342/* Some VBT's incorrectly indicate no backlight is present */
14343static void quirk_backlight_present(struct drm_device *dev)
14344{
14345 struct drm_i915_private *dev_priv = dev->dev_private;
14346 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14347 DRM_INFO("applying backlight present quirk\n");
14348}
14349
b690e96c
JB		 14350struct intel_quirk {
14351 int device;
14352 int subsystem_vendor;
14353 int subsystem_device;
14354 void (*hook)(struct drm_device *dev);
14355};
14356
5f85f176
EE		 14357/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14358struct intel_dmi_quirk {
14359 void (*hook)(struct drm_device *dev);
14360 const struct dmi_system_id (*dmi_id_list)[];
14361};
14362
14363static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14364{
14365 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14366 return 1;
14367}
14368
14369static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14370 {
14371 .dmi_id_list = &(const struct dmi_system_id[]) {
14372 {
14373 .callback = intel_dmi_reverse_brightness,
14374 .ident = "NCR Corporation",
14375 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14376 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14377 },
14378 },
14379 { } /* terminating entry */
14380 },
14381 .hook = quirk_invert_brightness,
14382 },
14383};
14384
c43b5634 14385static struct intel_quirk intel_quirks[] = {
b690e96c 14386 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14387 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14388
b690e96c
JB		 14389 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14390 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14391
b690e96c
JB		 14392 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14393 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14394
5f080c0f
VS		 14395 /* 830 needs to leave pipe A & dpll A up */
14396 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14397
b6b5d049
VS		 14398 /* 830 needs to leave pipe B & dpll B up */
14399 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14400
435793df
KP		 14401 /* Lenovo U160 cannot use SSC on LVDS */
14402 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14403
14404 /* Sony Vaio Y cannot use SSC on LVDS */
14405 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14406
be505f64
AH		 14407 /* Acer Aspire 5734Z must invert backlight brightness */
14408 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14409
14410 /* Acer/eMachines G725 */
14411 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14412
14413 /* Acer/eMachines e725 */
14414 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14415
14416 /* Acer/Packard Bell NCL20 */
14417 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14418
14419 /* Acer Aspire 4736Z */
14420 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14421
14422 /* Acer Aspire 5336 */
14423 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14424
14425 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14426 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14427
dfb3d47b
SD		 14428 /* Acer C720 Chromebook (Core i3 4005U) */
14429 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14430
b2a9601c 14431 /* Apple Macbook 2,1 (Core 2 T7400) */
14432 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14433
d4967d8c
SD		 14434 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14435 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14436
14437 /* HP Chromebook 14 (Celeron 2955U) */
14438 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14439
14440 /* Dell Chromebook 11 */
14441 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14442};
14443
14444static void intel_init_quirks(struct drm_device *dev)
14445{
14446 struct pci_dev *d = dev->pdev;
14447 int i;
14448
14449 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14450 struct intel_quirk *q = &intel_quirks[i];
14451
14452 if (d->device == q->device &&
14453 (d->subsystem_vendor == q->subsystem_vendor ||
14454 q->subsystem_vendor == PCI_ANY_ID) &&
14455 (d->subsystem_device == q->subsystem_device ||
14456 q->subsystem_device == PCI_ANY_ID))
14457 q->hook(dev);
14458 }
5f85f176
EE		 14459 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14460 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14461 intel_dmi_quirks[i].hook(dev);
14462 }
b690e96c
JB		 14463}
14464
9cce37f4
JB		 14465/* Disable the VGA plane that we never use */
14466static void i915_disable_vga(struct drm_device *dev)
14467{
14468 struct drm_i915_private *dev_priv = dev->dev_private;
14469 u8 sr1;
766aa1c4 14470 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14471
2b37c616 14472 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14473 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14474 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14475 sr1 = inb(VGA_SR_DATA);
14476 outb(sr1 | 1<<5, VGA_SR_DATA);
14477 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14478 udelay(300);
14479
01f5a626 14480 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14481 POSTING_READ(vga_reg);
14482}
14483
f817586c
DV		 14484void intel_modeset_init_hw(struct drm_device *dev)
14485{
a8f78b58
ED		 14486 intel_prepare_ddi(dev);
14487
f8bf63fd
VS		 14488 if (IS_VALLEYVIEW(dev))
14489 vlv_update_cdclk(dev);
14490
f817586c
DV		 14491 intel_init_clock_gating(dev);
14492
8090c6b9 14493 intel_enable_gt_powersave(dev);
f817586c
DV		 14494}
14495
79e53945
JB		 14496void intel_modeset_init(struct drm_device *dev)
14497{
652c393a 14498 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14499 int sprite, ret;
8cc87b75 14500 enum pipe pipe;
46f297fb 14501 struct intel_crtc *crtc;
79e53945
JB		 14502
14503 drm_mode_config_init(dev);
14504
14505 dev->mode_config.min_width = 0;
14506 dev->mode_config.min_height = 0;
14507
019d96cb
DA		 14508 dev->mode_config.preferred_depth = 24;
14509 dev->mode_config.prefer_shadow = 1;
14510
25bab385
TU		 14511 dev->mode_config.allow_fb_modifiers = true;
14512
e6ecefaa 14513 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14514
b690e96c
JB		 14515 intel_init_quirks(dev);
14516
1fa61106
ED		 14517 intel_init_pm(dev);
14518
e3c74757
BW		 14519 if (INTEL_INFO(dev)->num_pipes == 0)
14520 return;
14521
e70236a8 14522 intel_init_display(dev);
7c10a2b5 14523 intel_init_audio(dev);
e70236a8 14524
a6c45cf0
CW		 14525 if (IS_GEN2(dev)) {
14526 dev->mode_config.max_width = 2048;
14527 dev->mode_config.max_height = 2048;
14528 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14529 dev->mode_config.max_width = 4096;
14530 dev->mode_config.max_height = 4096;
79e53945 14531 } else {
a6c45cf0
CW		 14532 dev->mode_config.max_width = 8192;
14533 dev->mode_config.max_height = 8192;
79e53945 14534 }
068be561 14535
dc41c154
VS		 14536 if (IS_845G(dev) || IS_I865G(dev)) {
14537 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14538 dev->mode_config.cursor_height = 1023;
14539 } else if (IS_GEN2(dev)) {
068be561
DL		 14540 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14541 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14542 } else {
14543 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14544 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14545 }
14546
5d4545ae 14547 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14548
28c97730 14549 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14550 INTEL_INFO(dev)->num_pipes,
14551 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14552
055e393f 14553 for_each_pipe(dev_priv, pipe) {
8cc87b75 14554 intel_crtc_init(dev, pipe);
3bdcfc0c 14555 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14556 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14557 if (ret)
06da8da2 14558 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14559 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14560 }
79e53945
JB		 14561 }
14562
f42bb70d
JB		 14563 intel_init_dpio(dev);
14564
e72f9fbf 14565 intel_shared_dpll_init(dev);
ee7b9f93 14566
9cce37f4
JB		 14567 /* Just disable it once at startup */
14568 i915_disable_vga(dev);
79e53945 14569 intel_setup_outputs(dev);
11be49eb
CW		 14570
14571 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14572 intel_fbc_disable(dev);
fa9fa083 14573
6e9f798d 14574 drm_modeset_lock_all(dev);
fa9fa083 14575 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14576 drm_modeset_unlock_all(dev);
46f297fb 14577
d3fcc808 14578 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14579 if (!crtc->active)
14580 continue;
14581
46f297fb 14582 /*
46f297fb
JB		 14583 * Note that reserving the BIOS fb up front prevents us
14584 * from stuffing other stolen allocations like the ring
14585 * on top. This prevents some ugliness at boot time, and
14586 * can even allow for smooth boot transitions if the BIOS
14587 * fb is large enough for the active pipe configuration.
14588 */
5724dbd1
DL		 14589 if (dev_priv->display.get_initial_plane_config) {
14590 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14591 &crtc->plane_config);
14592 /*
14593 * If the fb is shared between multiple heads, we'll
14594 * just get the first one.
14595 */
f6936e29 14596 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14597 }
46f297fb 14598 }
2c7111db
CW		 14599}
14600
7fad798e
DV		 14601static void intel_enable_pipe_a(struct drm_device *dev)
14602{
14603 struct intel_connector *connector;
14604 struct drm_connector *crt = NULL;
14605 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14606 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14607
14608 /* We can't just switch on the pipe A, we need to set things up with a
14609 * proper mode and output configuration. As a gross hack, enable pipe A
14610 * by enabling the load detect pipe once. */
3a3371ff 14611 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14612 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14613 crt = &connector->base;
14614 break;
14615 }
14616 }
14617
14618 if (!crt)
14619 return;
14620
208bf9fd 14621 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14622 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14623}
14624
fa555837
DV		 14625static bool
14626intel_check_plane_mapping(struct intel_crtc *crtc)
14627{
7eb552ae
BW		 14628 struct drm_device *dev = crtc->base.dev;
14629 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14630 u32 reg, val;
14631
7eb552ae 14632 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14633 return true;
14634
14635 reg = DSPCNTR(!crtc->plane);
14636 val = I915_READ(reg);
14637
14638 if ((val & DISPLAY_PLANE_ENABLE) &&
14639 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14640 return false;
14641
14642 return true;
14643}
14644
24929352
DV		 14645static void intel_sanitize_crtc(struct intel_crtc *crtc)
14646{
14647 struct drm_device *dev = crtc->base.dev;
14648 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14649 u32 reg;
24929352 14650
24929352 14651 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14652 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14653 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14654
d3eaf884 14655 /* restore vblank interrupts to correct state */
9625604c 14656 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14657 if (crtc->active) {
14658 update_scanline_offset(crtc);
9625604c
DV		 14659 drm_crtc_vblank_on(&crtc->base);
14660 }
d3eaf884 14661
24929352 14662 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14663 * disable the crtc (and hence change the state) if it is wrong. Note
14664 * that gen4+ has a fixed plane -> pipe mapping. */
14665 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14666 struct intel_connector *connector;
14667 bool plane;
14668
24929352
DV		 14669 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14670 crtc->base.base.id);
14671
14672 /* Pipe has the wrong plane attached and the plane is active.
14673 * Temporarily change the plane mapping and disable everything
14674 * ... */
14675 plane = crtc->plane;
14676 crtc->plane = !plane;
9c8958bc 14677 crtc->primary_enabled = true;
24929352
DV		 14678 dev_priv->display.crtc_disable(&crtc->base);
14679 crtc->plane = plane;
14680
14681 /* ... and break all links. */
3a3371ff 14682 for_each_intel_connector(dev, connector) {
24929352
DV		 14683 if (connector->encoder->base.crtc != &crtc->base)
14684 continue;
14685
7f1950fb
EE		 14686 connector->base.dpms = DRM_MODE_DPMS_OFF;
14687 connector->base.encoder = NULL;
24929352 14688 }
7f1950fb
EE		 14689 /* multiple connectors may have the same encoder:
14690 * handle them and break crtc link separately */
3a3371ff 14691 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14692 if (connector->encoder->base.crtc == &crtc->base) {
14693 connector->encoder->base.crtc = NULL;
14694 connector->encoder->connectors_active = false;
14695 }
24929352
DV		 14696
14697 WARN_ON(crtc->active);
83d65738 14698 crtc->base.state->enable = false;
24929352
DV		 14699 crtc->base.enabled = false;
14700 }
24929352 14701
7fad798e
DV		 14702 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14703 crtc->pipe == PIPE_A && !crtc->active) {
14704 /* BIOS forgot to enable pipe A, this mostly happens after
14705 * resume. Force-enable the pipe to fix this, the update_dpms
14706 * call below we restore the pipe to the right state, but leave
14707 * the required bits on. */
14708 intel_enable_pipe_a(dev);
14709 }
14710
24929352
DV		 14711 /* Adjust the state of the output pipe according to whether we
14712 * have active connectors/encoders. */
14713 intel_crtc_update_dpms(&crtc->base);
14714
83d65738 14715 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14716 struct intel_encoder *encoder;
14717
14718 /* This can happen either due to bugs in the get_hw_state
14719 * functions or because the pipe is force-enabled due to the
14720 * pipe A quirk. */
14721 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14722 crtc->base.base.id,
83d65738 14723 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14724 crtc->active ? "enabled" : "disabled");
14725
83d65738 14726 crtc->base.state->enable = crtc->active;
24929352
DV		 14727 crtc->base.enabled = crtc->active;
14728
14729 /* Because we only establish the connector -> encoder ->
14730 * crtc links if something is active, this means the
14731 * crtc is now deactivated. Break the links. connector
14732 * -> encoder links are only establish when things are
14733 * actually up, hence no need to break them. */
14734 WARN_ON(crtc->active);
14735
14736 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14737 WARN_ON(encoder->connectors_active);
14738 encoder->base.crtc = NULL;
14739 }
14740 }
c5ab3bc0 14741
a3ed6aad 14742 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14743 /*
14744 * We start out with underrun reporting disabled to avoid races.
14745 * For correct bookkeeping mark this on active crtcs.
14746 *
c5ab3bc0
DV		 14747 * Also on gmch platforms we dont have any hardware bits to
14748 * disable the underrun reporting. Which means we need to start
14749 * out with underrun reporting disabled also on inactive pipes,
14750 * since otherwise we'll complain about the garbage we read when
14751 * e.g. coming up after runtime pm.
14752 *
4cc31489
DV		 14753 * No protection against concurrent access is required - at
14754 * worst a fifo underrun happens which also sets this to false.
14755 */
14756 crtc->cpu_fifo_underrun_disabled = true;
14757 crtc->pch_fifo_underrun_disabled = true;
14758 }
24929352
DV		 14759}
14760
14761static void intel_sanitize_encoder(struct intel_encoder *encoder)
14762{
14763 struct intel_connector *connector;
14764 struct drm_device *dev = encoder->base.dev;
14765
14766 /* We need to check both for a crtc link (meaning that the
14767 * encoder is active and trying to read from a pipe) and the
14768 * pipe itself being active. */
14769 bool has_active_crtc = encoder->base.crtc &&
14770 to_intel_crtc(encoder->base.crtc)->active;
14771
14772 if (encoder->connectors_active && !has_active_crtc) {
14773 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14774 encoder->base.base.id,
8e329a03 14775 encoder->base.name);
24929352
DV		 14776
14777 /* Connector is active, but has no active pipe. This is
14778 * fallout from our resume register restoring. Disable
14779 * the encoder manually again. */
14780 if (encoder->base.crtc) {
14781 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14782 encoder->base.base.id,
8e329a03 14783 encoder->base.name);
24929352 14784 encoder->disable(encoder);
a62d1497
VS		 14785 if (encoder->post_disable)
14786 encoder->post_disable(encoder);
24929352 14787 }
7f1950fb
EE		 14788 encoder->base.crtc = NULL;
14789 encoder->connectors_active = false;
24929352
DV		 14790
14791 /* Inconsistent output/port/pipe state happens presumably due to
14792 * a bug in one of the get_hw_state functions. Or someplace else
14793 * in our code, like the register restore mess on resume. Clamp
14794 * things to off as a safer default. */
3a3371ff 14795 for_each_intel_connector(dev, connector) {
24929352
DV		 14796 if (connector->encoder != encoder)
14797 continue;
7f1950fb
EE		 14798 connector->base.dpms = DRM_MODE_DPMS_OFF;
14799 connector->base.encoder = NULL;
24929352
DV		 14800 }
14801 }
14802 /* Enabled encoders without active connectors will be fixed in
14803 * the crtc fixup. */
14804}
14805
04098753 14806void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14807{
14808 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14809 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14810
04098753
ID		 14811 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14812 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14813 i915_disable_vga(dev);
14814 }
14815}
14816
14817void i915_redisable_vga(struct drm_device *dev)
14818{
14819 struct drm_i915_private *dev_priv = dev->dev_private;
14820
8dc8a27c
PZ		 14821 /* This function can be called both from intel_modeset_setup_hw_state or
14822 * at a very early point in our resume sequence, where the power well
14823 * structures are not yet restored. Since this function is at a very
14824 * paranoid "someone might have enabled VGA while we were not looking"
14825 * level, just check if the power well is enabled instead of trying to
14826 * follow the "don't touch the power well if we don't need it" policy
14827 * the rest of the driver uses. */
f458ebbc 14828 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14829 return;
14830
04098753 14831 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14832}
14833
98ec7739
VS		 14834static bool primary_get_hw_state(struct intel_crtc *crtc)
14835{
14836 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14837
14838 if (!crtc->active)
14839 return false;
14840
14841 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14842}
14843
30e984df 14844static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14845{
14846 struct drm_i915_private *dev_priv = dev->dev_private;
14847 enum pipe pipe;
24929352
DV		 14848 struct intel_crtc *crtc;
14849 struct intel_encoder *encoder;
14850 struct intel_connector *connector;
5358901f 14851 int i;
24929352 14852
d3fcc808 14853 for_each_intel_crtc(dev, crtc) {
6e3c9717 14854 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14855
6e3c9717 14856 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14857
0e8ffe1b 14858 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14859 crtc->config);
24929352 14860
83d65738 14861 crtc->base.state->enable = crtc->active;
24929352 14862 crtc->base.enabled = crtc->active;
98ec7739 14863 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14864
14865 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14866 crtc->base.base.id,
14867 crtc->active ? "enabled" : "disabled");
14868 }
14869
5358901f
DV		 14870 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14871 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14872
3e369b76
ACO		 14873 pll->on = pll->get_hw_state(dev_priv, pll,
14874 &pll->config.hw_state);
5358901f 14875 pll->active = 0;
3e369b76 14876 pll->config.crtc_mask = 0;
d3fcc808 14877 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14878 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14879 pll->active++;
3e369b76 14880 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14881 }
5358901f 14882 }
5358901f 14883
1e6f2ddc 14884 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14885 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14886
3e369b76 14887 if (pll->config.crtc_mask)
bd2bb1b9 14888 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14889 }
14890
b2784e15 14891 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14892 pipe = 0;
14893
14894 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14895 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14896 encoder->base.crtc = &crtc->base;
6e3c9717 14897 encoder->get_config(encoder, crtc->config);
24929352
DV		 14898 } else {
14899 encoder->base.crtc = NULL;
14900 }
14901
14902 encoder->connectors_active = false;
6f2bcceb 14903 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14904 encoder->base.base.id,
8e329a03 14905 encoder->base.name,
24929352 14906 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14907 pipe_name(pipe));
24929352
DV		 14908 }
14909
3a3371ff 14910 for_each_intel_connector(dev, connector) {
24929352
DV		 14911 if (connector->get_hw_state(connector)) {
14912 connector->base.dpms = DRM_MODE_DPMS_ON;
14913 connector->encoder->connectors_active = true;
14914 connector->base.encoder = &connector->encoder->base;
14915 } else {
14916 connector->base.dpms = DRM_MODE_DPMS_OFF;
14917 connector->base.encoder = NULL;
14918 }
14919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14920 connector->base.base.id,
c23cc417 14921 connector->base.name,
24929352
DV		 14922 connector->base.encoder ? "enabled" : "disabled");
14923 }
30e984df
DV		 14924}
14925
14926/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14927 * and i915 state tracking structures. */
14928void intel_modeset_setup_hw_state(struct drm_device *dev,
14929 bool force_restore)
14930{
14931 struct drm_i915_private *dev_priv = dev->dev_private;
14932 enum pipe pipe;
30e984df
DV		 14933 struct intel_crtc *crtc;
14934 struct intel_encoder *encoder;
35c95375 14935 int i;
30e984df
DV		 14936
14937 intel_modeset_readout_hw_state(dev);
24929352 14938
babea61d
JB		 14939 /*
14940 * Now that we have the config, copy it to each CRTC struct
14941 * Note that this could go away if we move to using crtc_config
14942 * checking everywhere.
14943 */
d3fcc808 14944 for_each_intel_crtc(dev, crtc) {
d330a953 14945 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14946 intel_mode_from_pipe_config(&crtc->base.mode,
14947 crtc->config);
babea61d
JB		 14948 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14949 crtc->base.base.id);
14950 drm_mode_debug_printmodeline(&crtc->base.mode);
14951 }
14952 }
14953
24929352 14954 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14955 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14956 intel_sanitize_encoder(encoder);
14957 }
14958
055e393f 14959 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14960 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14961 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14962 intel_dump_pipe_config(crtc, crtc->config,
14963 "[setup_hw_state]");
24929352 14964 }
9a935856 14965
d29b2f9d
ACO		 14966 intel_modeset_update_connector_atomic_state(dev);
14967
35c95375
DV		 14968 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14969 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14970
14971 if (!pll->on || pll->active)
14972 continue;
14973
14974 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14975
14976 pll->disable(dev_priv, pll);
14977 pll->on = false;
14978 }
14979
3078999f
PB		 14980 if (IS_GEN9(dev))
14981 skl_wm_get_hw_state(dev);
14982 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14983 ilk_wm_get_hw_state(dev);
14984
45e2b5f6 14985 if (force_restore) {
7d0bc1ea
VS		 14986 i915_redisable_vga(dev);
14987
f30da187
DV		 14988 /*
14989 * We need to use raw interfaces for restoring state to avoid
14990 * checking (bogus) intermediate states.
14991 */
055e393f 14992 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14993 struct drm_crtc *crtc =
14994 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14995
83a57153 14996 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14997 }
14998 } else {
14999 intel_modeset_update_staged_output_state(dev);
15000 }
8af6cf88
DV		 15001
15002 intel_modeset_check_state(dev);
2c7111db
CW		 15003}
15004
15005void intel_modeset_gem_init(struct drm_device *dev)
15006{
92122789 15007 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15008 struct drm_crtc *c;
2ff8fde1 15009 struct drm_i915_gem_object *obj;
484b41dd 15010
ae48434c
ID		 15011 mutex_lock(&dev->struct_mutex);
15012 intel_init_gt_powersave(dev);
15013 mutex_unlock(&dev->struct_mutex);
15014
92122789
JB		 15015 /*
15016 * There may be no VBT; and if the BIOS enabled SSC we can
15017 * just keep using it to avoid unnecessary flicker. Whereas if the
15018 * BIOS isn't using it, don't assume it will work even if the VBT
15019 * indicates as much.
15020 */
15021 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15022 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15023 DREF_SSC1_ENABLE);
15024
1833b134 15025 intel_modeset_init_hw(dev);
02e792fb
DV		 15026
15027 intel_setup_overlay(dev);
484b41dd
JB		 15028
15029 /*
15030 * Make sure any fbs we allocated at startup are properly
15031 * pinned & fenced. When we do the allocation it's too early
15032 * for this.
15033 */
15034 mutex_lock(&dev->struct_mutex);
70e1e0ec 15035 for_each_crtc(dev, c) {
2ff8fde1
MR		 15036 obj = intel_fb_obj(c->primary->fb);
15037 if (obj == NULL)
484b41dd
JB		 15038 continue;
15039
850c4cdc
TU		 15040 if (intel_pin_and_fence_fb_obj(c->primary,
15041 c->primary->fb,
82bc3b2d 15042 c->primary->state,
850c4cdc 15043 NULL)) {
484b41dd
JB		 15044 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15045 to_intel_crtc(c)->pipe);
66e514c1
DA		 15046 drm_framebuffer_unreference(c->primary->fb);
15047 c->primary->fb = NULL;
afd65eb4 15048 update_state_fb(c->primary);
484b41dd
JB		 15049 }
15050 }
15051 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 15052
15053 intel_backlight_register(dev);
79e53945
JB		 15054}
15055
4932e2c3
ID		 15056void intel_connector_unregister(struct intel_connector *intel_connector)
15057{
15058 struct drm_connector *connector = &intel_connector->base;
15059
15060 intel_panel_destroy_backlight(connector);
34ea3d38 15061 drm_connector_unregister(connector);
4932e2c3
ID		 15062}
15063
79e53945
JB		 15064void intel_modeset_cleanup(struct drm_device *dev)
15065{
652c393a 15066 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15067 struct drm_connector *connector;
652c393a 15068
2eb5252e
ID		 15069 intel_disable_gt_powersave(dev);
15070
0962c3c9
VS		 15071 intel_backlight_unregister(dev);
15072
fd0c0642
DV		 15073 /*
15074 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15075 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15076 * experience fancy races otherwise.
15077 */
2aeb7d3a 15078 intel_irq_uninstall(dev_priv);
eb21b92b 15079
fd0c0642
DV		 15080 /*
15081 * Due to the hpd irq storm handling the hotplug work can re-arm the
15082 * poll handlers. Hence disable polling after hpd handling is shut down.
15083 */
f87ea761 15084 drm_kms_helper_poll_fini(dev);
fd0c0642 15085
652c393a
JB		 15086 mutex_lock(&dev->struct_mutex);
15087
723bfd70
JB		 15088 intel_unregister_dsm_handler();
15089
7ff0ebcc 15090 intel_fbc_disable(dev);
e70236a8 15091
69341a5e
KH		 15092 mutex_unlock(&dev->struct_mutex);
15093
1630fe75
CW		 15094 /* flush any delayed tasks or pending work */
15095 flush_scheduled_work();
15096
db31af1d
JN		 15097 /* destroy the backlight and sysfs files before encoders/connectors */
15098 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15099 struct intel_connector *intel_connector;
15100
15101 intel_connector = to_intel_connector(connector);
15102 intel_connector->unregister(intel_connector);
db31af1d 15103 }
d9255d57 15104
79e53945 15105 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15106
15107 intel_cleanup_overlay(dev);
ae48434c
ID		 15108
15109 mutex_lock(&dev->struct_mutex);
15110 intel_cleanup_gt_powersave(dev);
15111 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15112}
15113
f1c79df3
ZW		 15114/*
15115 * Return which encoder is currently attached for connector.
15116 */
df0e9248 15117struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15118{
df0e9248
CW		 15119 return &intel_attached_encoder(connector)->base;
15120}
f1c79df3 15121
df0e9248
CW		 15122void intel_connector_attach_encoder(struct intel_connector *connector,
15123 struct intel_encoder *encoder)
15124{
15125 connector->encoder = encoder;
15126 drm_mode_connector_attach_encoder(&connector->base,
15127 &encoder->base);
79e53945 15128}
28d52043
DA		 15129
15130/*
15131 * set vga decode state - true == enable VGA decode
15132 */
15133int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15134{
15135 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15136 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15137 u16 gmch_ctrl;
15138
75fa041d
CW		 15139 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15140 DRM_ERROR("failed to read control word\n");
15141 return -EIO;
15142 }
15143
c0cc8a55
CW		 15144 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15145 return 0;
15146
28d52043
DA		 15147 if (state)
15148 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15149 else
15150 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15151
15152 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15153 DRM_ERROR("failed to write control word\n");
15154 return -EIO;
15155 }
15156
28d52043
DA		 15157 return 0;
15158}
c4a1d9e4 15159
c4a1d9e4 15160struct intel_display_error_state {
ff57f1b0
PZ		 15161
15162 u32 power_well_driver;
15163
63b66e5b
CW		 15164 int num_transcoders;
15165
c4a1d9e4
CW		 15166 struct intel_cursor_error_state {
15167 u32 control;
15168 u32 position;
15169 u32 base;
15170 u32 size;
52331309 15171 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15172
15173 struct intel_pipe_error_state {
ddf9c536 15174 bool power_domain_on;
c4a1d9e4 15175 u32 source;
f301b1e1 15176 u32 stat;
52331309 15177 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15178
15179 struct intel_plane_error_state {
15180 u32 control;
15181 u32 stride;
15182 u32 size;
15183 u32 pos;
15184 u32 addr;
15185 u32 surface;
15186 u32 tile_offset;
52331309 15187 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15188
15189 struct intel_transcoder_error_state {
ddf9c536 15190 bool power_domain_on;
63b66e5b
CW		 15191 enum transcoder cpu_transcoder;
15192
15193 u32 conf;
15194
15195 u32 htotal;
15196 u32 hblank;
15197 u32 hsync;
15198 u32 vtotal;
15199 u32 vblank;
15200 u32 vsync;
15201 } transcoder[4];
c4a1d9e4
CW		 15202};
15203
15204struct intel_display_error_state *
15205intel_display_capture_error_state(struct drm_device *dev)
15206{
fbee40df 15207 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15208 struct intel_display_error_state *error;
63b66e5b
CW		 15209 int transcoders[] = {
15210 TRANSCODER_A,
15211 TRANSCODER_B,
15212 TRANSCODER_C,
15213 TRANSCODER_EDP,
15214 };
c4a1d9e4
CW		 15215 int i;
15216
63b66e5b
CW		 15217 if (INTEL_INFO(dev)->num_pipes == 0)
15218 return NULL;
15219
9d1cb914 15220 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15221 if (error == NULL)
15222 return NULL;
15223
190be112 15224 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15225 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15226
055e393f 15227 for_each_pipe(dev_priv, i) {
ddf9c536 15228 error->pipe[i].power_domain_on =
f458ebbc
DV		 15229 __intel_display_power_is_enabled(dev_priv,
15230 POWER_DOMAIN_PIPE(i));
ddf9c536 15231 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15232 continue;
15233
5efb3e28
VS		 15234 error->cursor[i].control = I915_READ(CURCNTR(i));
15235 error->cursor[i].position = I915_READ(CURPOS(i));
15236 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15237
15238 error->plane[i].control = I915_READ(DSPCNTR(i));
15239 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15240 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15241 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15242 error->plane[i].pos = I915_READ(DSPPOS(i));
15243 }
ca291363
PZ		 15244 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15245 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15246 if (INTEL_INFO(dev)->gen >= 4) {
15247 error->plane[i].surface = I915_READ(DSPSURF(i));
15248 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15249 }
15250
c4a1d9e4 15251 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15252
3abfce77 15253 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15254 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15255 }
15256
15257 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15258 if (HAS_DDI(dev_priv->dev))
15259 error->num_transcoders++; /* Account for eDP. */
15260
15261 for (i = 0; i < error->num_transcoders; i++) {
15262 enum transcoder cpu_transcoder = transcoders[i];
15263
ddf9c536 15264 error->transcoder[i].power_domain_on =
f458ebbc 15265 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15266 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15267 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15268 continue;
15269
63b66e5b
CW		 15270 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15271
15272 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15273 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15274 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15275 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15276 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15277 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15278 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15279 }
15280
15281 return error;
15282}
15283
edc3d884
MK		 15284#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15285
c4a1d9e4 15286void
edc3d884 15287intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15288 struct drm_device *dev,
15289 struct intel_display_error_state *error)
15290{
055e393f 15291 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15292 int i;
15293
63b66e5b
CW		 15294 if (!error)
15295 return;
15296
edc3d884 15297 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15298 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15299 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15300 error->power_well_driver);
055e393f 15301 for_each_pipe(dev_priv, i) {
edc3d884 15302 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15303 err_printf(m, " Power: %s\n",
15304 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15305 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15306 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15307
15308 err_printf(m, "Plane [%d]:\n", i);
15309 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15310 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15311 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15312 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15313 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15314 }
4b71a570 15315 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15316 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15317 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15318 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15319 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15320 }
15321
edc3d884
MK		 15322 err_printf(m, "Cursor [%d]:\n", i);
15323 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15324 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15325 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15326 }
63b66e5b
CW		 15327
15328 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15329 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15330 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15331 err_printf(m, " Power: %s\n",
15332 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15333 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15334 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15335 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15336 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15337 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15338 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15339 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15340 }
c4a1d9e4 15341}
e2fcdaa9
VS		 15342
15343void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15344{
15345 struct intel_crtc *crtc;
15346
15347 for_each_intel_crtc(dev, crtc) {
15348 struct intel_unpin_work *work;
e2fcdaa9 15349
5e2d7afc 15350 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15351
15352 work = crtc->unpin_work;
15353
15354 if (work && work->event &&
15355 work->event->base.file_priv == file) {
15356 kfree(work->event);
15357 work->event = NULL;
15358 }
15359
5e2d7afc 15360 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15361 }
15362}
Linux kernel - Deliverables
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