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drm/i915/bxt: BXT clock divider calculation
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
e7457a9a 110
0e32b39c
DA		 111static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
112{
113 if (!connector->mst_port)
114 return connector->encoder;
115 else
116 return &connector->mst_port->mst_encoders[pipe]->base;
117}
118
79e53945 119typedef struct {
0206e353 120 int min, max;
79e53945
JB		 121} intel_range_t;
122
123typedef struct {
0206e353
AJ		 124 int dot_limit;
125 int p2_slow, p2_fast;
79e53945
JB		 126} intel_p2_t;
127
d4906093
ML		 128typedef struct intel_limit intel_limit_t;
129struct intel_limit {
0206e353
AJ		 130 intel_range_t dot, vco, n, m, m1, m2, p, p1;
131 intel_p2_t p2;
d4906093 132};
79e53945 133
d2acd215
DV		 134int
135intel_pch_rawclk(struct drm_device *dev)
136{
137 struct drm_i915_private *dev_priv = dev->dev_private;
138
139 WARN_ON(!HAS_PCH_SPLIT(dev));
140
141 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
142}
143
021357ac
CW		 144static inline u32 /* units of 100MHz */
145intel_fdi_link_freq(struct drm_device *dev)
146{
8b99e68c
CW		 147 if (IS_GEN5(dev)) {
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
150 } else
151 return 27;
021357ac
CW		 152}
153
5d536e28 154static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 155 .dot = { .min = 25000, .max = 350000 },
9c333719 156 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 157 .n = { .min = 2, .max = 16 },
0206e353
AJ		 158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 165};
166
5d536e28
DV		 167static const intel_limit_t intel_limits_i8xx_dvo = {
168 .dot = { .min = 25000, .max = 350000 },
9c333719 169 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 170 .n = { .min = 2, .max = 16 },
5d536e28
DV		 171 .m = { .min = 96, .max = 140 },
172 .m1 = { .min = 18, .max = 26 },
173 .m2 = { .min = 6, .max = 16 },
174 .p = { .min = 4, .max = 128 },
175 .p1 = { .min = 2, .max = 33 },
176 .p2 = { .dot_limit = 165000,
177 .p2_slow = 4, .p2_fast = 4 },
178};
179
e4b36699 180static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 181 .dot = { .min = 25000, .max = 350000 },
9c333719 182 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 183 .n = { .min = 2, .max = 16 },
0206e353
AJ		 184 .m = { .min = 96, .max = 140 },
185 .m1 = { .min = 18, .max = 26 },
186 .m2 = { .min = 6, .max = 16 },
187 .p = { .min = 4, .max = 128 },
188 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 14, .p2_fast = 7 },
e4b36699 191};
273e27ca 192
e4b36699 193static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 194 .dot = { .min = 20000, .max = 400000 },
195 .vco = { .min = 1400000, .max = 2800000 },
196 .n = { .min = 1, .max = 6 },
197 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 198 .m1 = { .min = 8, .max = 18 },
199 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 200 .p = { .min = 5, .max = 80 },
201 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 202 .p2 = { .dot_limit = 200000,
203 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 207 .dot = { .min = 20000, .max = 400000 },
208 .vco = { .min = 1400000, .max = 2800000 },
209 .n = { .min = 1, .max = 6 },
210 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 211 .m1 = { .min = 8, .max = 18 },
212 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 213 .p = { .min = 7, .max = 98 },
214 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 215 .p2 = { .dot_limit = 112000,
216 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 217};
218
273e27ca 219
e4b36699 220static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 221 .dot = { .min = 25000, .max = 270000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 17, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 10, .max = 30 },
228 .p1 = { .min = 1, .max = 3},
229 .p2 = { .dot_limit = 270000,
230 .p2_slow = 10,
231 .p2_fast = 10
044c7c41 232 },
e4b36699
KP		 233};
234
235static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 236 .dot = { .min = 22000, .max = 400000 },
237 .vco = { .min = 1750000, .max = 3500000},
238 .n = { .min = 1, .max = 4 },
239 .m = { .min = 104, .max = 138 },
240 .m1 = { .min = 16, .max = 23 },
241 .m2 = { .min = 5, .max = 11 },
242 .p = { .min = 5, .max = 80 },
243 .p1 = { .min = 1, .max = 8},
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 246};
247
248static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 249 .dot = { .min = 20000, .max = 115000 },
250 .vco = { .min = 1750000, .max = 3500000 },
251 .n = { .min = 1, .max = 3 },
252 .m = { .min = 104, .max = 138 },
253 .m1 = { .min = 17, .max = 23 },
254 .m2 = { .min = 5, .max = 11 },
255 .p = { .min = 28, .max = 112 },
256 .p1 = { .min = 2, .max = 8 },
257 .p2 = { .dot_limit = 0,
258 .p2_slow = 14, .p2_fast = 14
044c7c41 259 },
e4b36699
KP		 260};
261
262static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 263 .dot = { .min = 80000, .max = 224000 },
264 .vco = { .min = 1750000, .max = 3500000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 104, .max = 138 },
267 .m1 = { .min = 17, .max = 23 },
268 .m2 = { .min = 5, .max = 11 },
269 .p = { .min = 14, .max = 42 },
270 .p1 = { .min = 2, .max = 6 },
271 .p2 = { .dot_limit = 0,
272 .p2_slow = 7, .p2_fast = 7
044c7c41 273 },
e4b36699
KP		 274};
275
f2b115e6 276static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 277 .dot = { .min = 20000, .max = 400000},
278 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 279 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 280 .n = { .min = 3, .max = 6 },
281 .m = { .min = 2, .max = 256 },
273e27ca 282 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 283 .m1 = { .min = 0, .max = 0 },
284 .m2 = { .min = 0, .max = 254 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 287 .p2 = { .dot_limit = 200000,
288 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 289};
290
f2b115e6 291static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 292 .dot = { .min = 20000, .max = 400000 },
293 .vco = { .min = 1700000, .max = 3500000 },
294 .n = { .min = 3, .max = 6 },
295 .m = { .min = 2, .max = 256 },
296 .m1 = { .min = 0, .max = 0 },
297 .m2 = { .min = 0, .max = 254 },
298 .p = { .min = 7, .max = 112 },
299 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 300 .p2 = { .dot_limit = 112000,
301 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 302};
303
273e27ca
EA		 304/* Ironlake / Sandybridge
305 *
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
308 */
b91ad0ec 309static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 310 .dot = { .min = 25000, .max = 350000 },
311 .vco = { .min = 1760000, .max = 3510000 },
312 .n = { .min = 1, .max = 5 },
313 .m = { .min = 79, .max = 127 },
314 .m1 = { .min = 12, .max = 22 },
315 .m2 = { .min = 5, .max = 9 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 225000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
b91ad0ec 322static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 118 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 127 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 56 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360};
361
362static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 363 .dot = { .min = 25000, .max = 350000 },
364 .vco = { .min = 1760000, .max = 3510000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 79, .max = 126 },
367 .m1 = { .min = 12, .max = 22 },
368 .m2 = { .min = 5, .max = 9 },
369 .p = { .min = 14, .max = 42 },
0206e353 370 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 371 .p2 = { .dot_limit = 225000,
372 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 373};
374
dc730512 375static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 383 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 384 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 385 .m1 = { .min = 2, .max = 3 },
386 .m2 = { .min = 11, .max = 156 },
b99ab663 387 .p1 = { .min = 2, .max = 3 },
5fdc9c49 388 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 389};
390
ef9348c8
CML		 391static const intel_limit_t intel_limits_chv = {
392 /*
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
397 */
398 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 399 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 400 .n = { .min = 1, .max = 1 },
401 .m1 = { .min = 2, .max = 2 },
402 .m2 = { .min = 24 << 22, .max = 175 << 22 },
403 .p1 = { .min = 2, .max = 4 },
404 .p2 = { .p2_slow = 1, .p2_fast = 14 },
405};
406
5ab7b0b7
ID		 407static const intel_limit_t intel_limits_bxt = {
408 /* FIXME: find real dot limits */
409 .dot = { .min = 0, .max = INT_MAX },
410 .vco = { .min = 4800000, .max = 6480000 },
411 .n = { .min = 1, .max = 1 },
412 .m1 = { .min = 2, .max = 2 },
413 /* FIXME: find real m2 limits */
414 .m2 = { .min = 2 << 22, .max = 255 << 22 },
415 .p1 = { .min = 2, .max = 4 },
416 .p2 = { .p2_slow = 1, .p2_fast = 20 },
417};
418
6b4bf1c4
VS		 419static void vlv_clock(int refclk, intel_clock_t *clock)
420{
421 clock->m = clock->m1 * clock->m2;
422 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 423 if (WARN_ON(clock->n == 0 || clock->p == 0))
424 return;
fb03ac01
VS		 425 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
426 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 427}
428
e0638cdf
PZ		 429/**
430 * Returns whether any output on the specified pipe is of the specified type
431 */
4093561b 432bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 433{
409ee761 434 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 435 struct intel_encoder *encoder;
436
409ee761 437 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 438 if (encoder->type == type)
439 return true;
440
441 return false;
442}
443
d0737e1d
ACO		 444/**
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
448 * encoder->crtc.
449 */
a93e255f
ACO		 450static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
451 int type)
d0737e1d 452{
a93e255f
ACO		 453 struct drm_atomic_state *state = crtc_state->base.state;
454 struct drm_connector_state *connector_state;
d0737e1d 455 struct intel_encoder *encoder;
a93e255f
ACO		 456 int i, num_connectors = 0;
457
458 for (i = 0; i < state->num_connector; i++) {
459 if (!state->connectors[i])
460 continue;
461
462 connector_state = state->connector_states[i];
463 if (connector_state->crtc != crtc_state->base.crtc)
464 continue;
465
466 num_connectors++;
d0737e1d 467
a93e255f
ACO		 468 encoder = to_intel_encoder(connector_state->best_encoder);
469 if (encoder->type == type)
d0737e1d 470 return true;
a93e255f
ACO		 471 }
472
473 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 474
475 return false;
476}
477
a93e255f
ACO		 478static const intel_limit_t *
479intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 480{
a93e255f 481 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 482 const intel_limit_t *limit;
b91ad0ec 483
a93e255f 484 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 485 if (intel_is_dual_link_lvds(dev)) {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_dual_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_dual_lvds;
490 } else {
1b894b59 491 if (refclk == 100000)
b91ad0ec
ZW		 492 limit = &intel_limits_ironlake_single_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_single_lvds;
495 }
c6bb3538 496 } else
b91ad0ec 497 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 498
499 return limit;
500}
501
a93e255f
ACO		 502static const intel_limit_t *
503intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 504{
a93e255f 505 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 506 const intel_limit_t *limit;
507
a93e255f 508 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev))
e4b36699 510 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 511 else
e4b36699 512 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 513 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
514 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 515 limit = &intel_limits_g4x_hdmi;
a93e255f 516 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 517 limit = &intel_limits_g4x_sdvo;
044c7c41 518 } else /* The option is for other outputs */
e4b36699 519 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 520
521 return limit;
522}
523
a93e255f
ACO		 524static const intel_limit_t *
525intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 526{
a93e255f 527 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 528 const intel_limit_t *limit;
529
5ab7b0b7
ID		 530 if (IS_BROXTON(dev))
531 limit = &intel_limits_bxt;
532 else if (HAS_PCH_SPLIT(dev))
a93e255f 533 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 534 else if (IS_G4X(dev)) {
a93e255f 535 limit = intel_g4x_limit(crtc_state);
f2b115e6 536 } else if (IS_PINEVIEW(dev)) {
a93e255f 537 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 538 limit = &intel_limits_pineview_lvds;
2177832f 539 else
f2b115e6 540 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 541 } else if (IS_CHERRYVIEW(dev)) {
542 limit = &intel_limits_chv;
a0c4da24 543 } else if (IS_VALLEYVIEW(dev)) {
dc730512 544 limit = &intel_limits_vlv;
a6c45cf0 545 } else if (!IS_GEN2(dev)) {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 547 limit = &intel_limits_i9xx_lvds;
548 else
549 limit = &intel_limits_i9xx_sdvo;
79e53945 550 } else {
a93e255f 551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 552 limit = &intel_limits_i8xx_lvds;
a93e255f 553 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 554 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 555 else
556 limit = &intel_limits_i8xx_dac;
79e53945
JB		 557 }
558 return limit;
559}
560
f2b115e6
AJ		 561/* m1 is reserved as 0 in Pineview, n is a ring counter */
562static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 563{
2177832f
SL		 564 clock->m = clock->m2 + 2;
565 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 566 if (WARN_ON(clock->n == 0 || clock->p == 0))
567 return;
fb03ac01
VS		 568 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
569 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 570}
571
7429e9d4
DV		 572static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
573{
574 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
575}
576
ac58c3f0 577static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 578{
7429e9d4 579 clock->m = i9xx_dpll_compute_m(clock);
79e53945 580 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 581 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
582 return;
fb03ac01
VS		 583 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
584 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 585}
586
ef9348c8
CML		 587static void chv_clock(int refclk, intel_clock_t *clock)
588{
589 clock->m = clock->m1 * clock->m2;
590 clock->p = clock->p1 * clock->p2;
591 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 return;
593 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
594 clock->n << 22);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596}
597
7c04d1d9 598#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 599/**
600 * Returns whether the given set of divisors are valid for a given refclk with
601 * the given connectors.
602 */
603
1b894b59
CW		 604static bool intel_PLL_is_valid(struct drm_device *dev,
605 const intel_limit_t *limit,
606 const intel_clock_t *clock)
79e53945 607{
f01b7962
VS		 608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
79e53945 610 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 611 INTELPllInvalid("p1 out of range\n");
79e53945 612 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 613 INTELPllInvalid("m2 out of range\n");
79e53945 614 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 615 INTELPllInvalid("m1 out of range\n");
f01b7962 616
5ab7b0b7 617 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
5ab7b0b7 621 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
79e53945 628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 629 INTELPllInvalid("vco out of range\n");
79e53945
JB		 630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 634 INTELPllInvalid("dot out of range\n");
79e53945
JB		 635
636 return true;
637}
638
d4906093 639static bool
a93e255f
ACO		 640i9xx_find_best_dpll(const intel_limit_t *limit,
641 struct intel_crtc_state *crtc_state,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
79e53945 644{
a93e255f 645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 646 struct drm_device *dev = crtc->base.dev;
79e53945 647 intel_clock_t clock;
79e53945
JB		 648 int err = target;
649
a93e255f 650 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 651 /*
a210b028
DV		 652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
79e53945 655 */
1974cad0 656 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
0206e353 667 memset(best_clock, 0, sizeof(*best_clock));
79e53945 668
42158660
ZY		 669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
670 clock.m1++) {
671 for (clock.m2 = limit->m2.min;
672 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 673 if (clock.m2 >= clock.m1)
42158660
ZY		 674 break;
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 679 int this_err;
680
ac58c3f0
DV		 681 i9xx_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
683 &clock))
684 continue;
685 if (match_clock &&
686 clock.p != match_clock->p)
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
691 *best_clock = clock;
692 err = this_err;
693 }
694 }
695 }
696 }
697 }
698
699 return (err != target);
700}
701
702static bool
a93e255f
ACO		 703pnv_find_best_dpll(const intel_limit_t *limit,
704 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
79e53945 707{
a93e255f 708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 709 struct drm_device *dev = crtc->base.dev;
79e53945 710 intel_clock_t clock;
79e53945
JB		 711 int err = target;
712
a93e255f 713 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 714 /*
a210b028
DV		 715 * For LVDS just rely on its current settings for dual-channel.
716 * We haven't figured out how to reliably set up different
717 * single/dual channel state, if we even can.
79e53945 718 */
1974cad0 719 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 720 clock.p2 = limit->p2.p2_fast;
721 else
722 clock.p2 = limit->p2.p2_slow;
723 } else {
724 if (target < limit->p2.dot_limit)
725 clock.p2 = limit->p2.p2_slow;
726 else
727 clock.p2 = limit->p2.p2_fast;
728 }
729
0206e353 730 memset(best_clock, 0, sizeof(*best_clock));
79e53945 731
42158660
ZY		 732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
733 clock.m1++) {
734 for (clock.m2 = limit->m2.min;
735 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 736 for (clock.n = limit->n.min;
737 clock.n <= limit->n.max; clock.n++) {
738 for (clock.p1 = limit->p1.min;
739 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 740 int this_err;
741
ac58c3f0 742 pineview_clock(refclk, &clock);
1b894b59
CW		 743 if (!intel_PLL_is_valid(dev, limit,
744 &clock))
79e53945 745 continue;
cec2f356
SP		 746 if (match_clock &&
747 clock.p != match_clock->p)
748 continue;
79e53945
JB		 749
750 this_err = abs(clock.dot - target);
751 if (this_err < err) {
752 *best_clock = clock;
753 err = this_err;
754 }
755 }
756 }
757 }
758 }
759
760 return (err != target);
761}
762
d4906093 763static bool
a93e255f
ACO		 764g4x_find_best_dpll(const intel_limit_t *limit,
765 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 766 int target, int refclk, intel_clock_t *match_clock,
767 intel_clock_t *best_clock)
d4906093 768{
a93e255f 769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 770 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 771 intel_clock_t clock;
772 int max_n;
773 bool found;
6ba770dc
AJ		 774 /* approximately equals target * 0.00585 */
775 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 776 found = false;
777
a93e255f 778 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 779 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 780 clock.p2 = limit->p2.p2_fast;
781 else
782 clock.p2 = limit->p2.p2_slow;
783 } else {
784 if (target < limit->p2.dot_limit)
785 clock.p2 = limit->p2.p2_slow;
786 else
787 clock.p2 = limit->p2.p2_fast;
788 }
789
790 memset(best_clock, 0, sizeof(*best_clock));
791 max_n = limit->n.max;
f77f13e2 792 /* based on hardware requirement, prefer smaller n to precision */
d4906093 793 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 794 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 795 for (clock.m1 = limit->m1.max;
796 clock.m1 >= limit->m1.min; clock.m1--) {
797 for (clock.m2 = limit->m2.max;
798 clock.m2 >= limit->m2.min; clock.m2--) {
799 for (clock.p1 = limit->p1.max;
800 clock.p1 >= limit->p1.min; clock.p1--) {
801 int this_err;
802
ac58c3f0 803 i9xx_clock(refclk, &clock);
1b894b59
CW		 804 if (!intel_PLL_is_valid(dev, limit,
805 &clock))
d4906093 806 continue;
1b894b59
CW		 807
808 this_err = abs(clock.dot - target);
d4906093
ML		 809 if (this_err < err_most) {
810 *best_clock = clock;
811 err_most = this_err;
812 max_n = clock.n;
813 found = true;
814 }
815 }
816 }
817 }
818 }
2c07245f
ZW		 819 return found;
820}
821
d5dd62bd
ID		 822/*
823 * Check if the calculated PLL configuration is more optimal compared to the
824 * best configuration and error found so far. Return the calculated error.
825 */
826static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
827 const intel_clock_t *calculated_clock,
828 const intel_clock_t *best_clock,
829 unsigned int best_error_ppm,
830 unsigned int *error_ppm)
831{
9ca3ba01
ID		 832 /*
833 * For CHV ignore the error and consider only the P value.
834 * Prefer a bigger P value based on HW requirements.
835 */
836 if (IS_CHERRYVIEW(dev)) {
837 *error_ppm = 0;
838
839 return calculated_clock->p > best_clock->p;
840 }
841
24be4e46
ID		 842 if (WARN_ON_ONCE(!target_freq))
843 return false;
844
d5dd62bd
ID		 845 *error_ppm = div_u64(1000000ULL *
846 abs(target_freq - calculated_clock->dot),
847 target_freq);
848 /*
849 * Prefer a better P value over a better (smaller) error if the error
850 * is small. Ensure this preference for future configurations too by
851 * setting the error to 0.
852 */
853 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 *error_ppm = 0;
855
856 return true;
857 }
858
859 return *error_ppm + 10 < best_error_ppm;
860}
861
a0c4da24 862static bool
a93e255f
ACO		 863vlv_find_best_dpll(const intel_limit_t *limit,
864 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 865 int target, int refclk, intel_clock_t *match_clock,
866 intel_clock_t *best_clock)
a0c4da24 867{
a93e255f 868 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 869 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 870 intel_clock_t clock;
69e4f900 871 unsigned int bestppm = 1000000;
27e639bf
VS		 872 /* min update 19.2 MHz */
873 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 874 bool found = false;
a0c4da24 875
6b4bf1c4
VS		 876 target *= 5; /* fast clock */
877
878 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 879
880 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 881 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 882 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 883 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 884 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 885 clock.p = clock.p1 * clock.p2;
a0c4da24 886 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 887 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 888 unsigned int ppm;
69e4f900 889
6b4bf1c4
VS		 890 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
891 refclk * clock.m1);
892
893 vlv_clock(refclk, &clock);
43b0ac53 894
f01b7962
VS		 895 if (!intel_PLL_is_valid(dev, limit,
896 &clock))
43b0ac53
VS		 897 continue;
898
d5dd62bd
ID		 899 if (!vlv_PLL_is_optimal(dev, target,
900 &clock,
901 best_clock,
902 bestppm, &ppm))
903 continue;
6b4bf1c4 904
d5dd62bd
ID		 905 *best_clock = clock;
906 bestppm = ppm;
907 found = true;
a0c4da24
JB		 908 }
909 }
910 }
911 }
a0c4da24 912
49e497ef 913 return found;
a0c4da24 914}
a4fc5ed6 915
ef9348c8 916static bool
a93e255f
ACO		 917chv_find_best_dpll(const intel_limit_t *limit,
918 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 919 int target, int refclk, intel_clock_t *match_clock,
920 intel_clock_t *best_clock)
921{
a93e255f 922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 923 struct drm_device *dev = crtc->base.dev;
9ca3ba01 924 unsigned int best_error_ppm;
ef9348c8
CML		 925 intel_clock_t clock;
926 uint64_t m2;
927 int found = false;
928
929 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 930 best_error_ppm = 1000000;
ef9348c8
CML		 931
932 /*
933 * Based on hardware doc, the n always set to 1, and m1 always
934 * set to 2. If requires to support 200Mhz refclk, we need to
935 * revisit this because n may not 1 anymore.
936 */
937 clock.n = 1, clock.m1 = 2;
938 target *= 5; /* fast clock */
939
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast;
942 clock.p2 >= limit->p2.p2_slow;
943 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 944 unsigned int error_ppm;
ef9348c8
CML		 945
946 clock.p = clock.p1 * clock.p2;
947
948 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
949 clock.n) << 22, refclk * clock.m1);
950
951 if (m2 > INT_MAX/clock.m1)
952 continue;
953
954 clock.m2 = m2;
955
956 chv_clock(refclk, &clock);
957
958 if (!intel_PLL_is_valid(dev, limit, &clock))
959 continue;
960
9ca3ba01
ID		 961 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
962 best_error_ppm, &error_ppm))
963 continue;
964
965 *best_clock = clock;
966 best_error_ppm = error_ppm;
967 found = true;
ef9348c8
CML		 968 }
969 }
970
971 return found;
972}
973
5ab7b0b7
ID		 974bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
975 intel_clock_t *best_clock)
976{
977 int refclk = i9xx_get_refclk(crtc_state, 0);
978
979 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
980 target_clock, refclk, NULL, best_clock);
981}
982
20ddf665
VS		 983bool intel_crtc_active(struct drm_crtc *crtc)
984{
985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
986
987 /* Be paranoid as we can arrive here with only partial
988 * state retrieved from the hardware during setup.
989 *
241bfc38 990 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 991 * as Haswell has gained clock readout/fastboot support.
992 *
66e514c1 993 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 994 * properly reconstruct framebuffers.
c3d1f436
MR		 995 *
996 * FIXME: The intel_crtc->active here should be switched to
997 * crtc->state->active once we have proper CRTC states wired up
998 * for atomic.
20ddf665 999 */
c3d1f436 1000 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1001 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1002}
1003
a5c961d1
PZ		 1004enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
6e3c9717 1010 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1011}
1012
fbf49ea2
VS		 1013static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1014{
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 u32 reg = PIPEDSL(pipe);
1017 u32 line1, line2;
1018 u32 line_mask;
1019
1020 if (IS_GEN2(dev))
1021 line_mask = DSL_LINEMASK_GEN2;
1022 else
1023 line_mask = DSL_LINEMASK_GEN3;
1024
1025 line1 = I915_READ(reg) & line_mask;
1026 mdelay(5);
1027 line2 = I915_READ(reg) & line_mask;
1028
1029 return line1 == line2;
1030}
1031
ab7ad7f6
KP		 1032/*
1033 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1034 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1035 *
1036 * After disabling a pipe, we can't wait for vblank in the usual way,
1037 * spinning on the vblank interrupt status bit, since we won't actually
1038 * see an interrupt when the pipe is disabled.
1039 *
ab7ad7f6
KP		 1040 * On Gen4 and above:
1041 * wait for the pipe register state bit to turn off
1042 *
1043 * Otherwise:
1044 * wait for the display line value to settle (it usually
1045 * ends up stopping at the start of the next frame).
58e10eb9 1046 *
9d0498a2 1047 */
575f7ab7 1048static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1049{
575f7ab7 1050 struct drm_device *dev = crtc->base.dev;
9d0498a2 1051 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1052 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1053 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1054
1055 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1056 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1057
1058 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1059 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1060 100))
284637d9 1061 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1062 } else {
ab7ad7f6 1063 /* Wait for the display line to settle */
fbf49ea2 1064 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1065 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1066 }
79e53945
JB		 1067}
1068
b0ea7d37
DL		 1069/*
1070 * ibx_digital_port_connected - is the specified port connected?
1071 * @dev_priv: i915 private structure
1072 * @port: the port to test
1073 *
1074 * Returns true if @port is connected, false otherwise.
1075 */
1076bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1077 struct intel_digital_port *port)
1078{
1079 u32 bit;
1080
c36346e3 1081 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1082 switch (port->port) {
c36346e3
DL		 1083 case PORT_B:
1084 bit = SDE_PORTB_HOTPLUG;
1085 break;
1086 case PORT_C:
1087 bit = SDE_PORTC_HOTPLUG;
1088 break;
1089 case PORT_D:
1090 bit = SDE_PORTD_HOTPLUG;
1091 break;
1092 default:
1093 return true;
1094 }
1095 } else {
eba905b2 1096 switch (port->port) {
c36346e3
DL		 1097 case PORT_B:
1098 bit = SDE_PORTB_HOTPLUG_CPT;
1099 break;
1100 case PORT_C:
1101 bit = SDE_PORTC_HOTPLUG_CPT;
1102 break;
1103 case PORT_D:
1104 bit = SDE_PORTD_HOTPLUG_CPT;
1105 break;
1106 default:
1107 return true;
1108 }
b0ea7d37
DL		 1109 }
1110
1111 return I915_READ(SDEISR) & bit;
1112}
1113
b24e7179
JB		 1114static const char *state_string(bool enabled)
1115{
1116 return enabled ? "on" : "off";
1117}
1118
1119/* Only for pre-ILK configs */
55607e8a
DV		 1120void assert_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe, bool state)
b24e7179
JB		 1122{
1123 int reg;
1124 u32 val;
1125 bool cur_state;
1126
1127 reg = DPLL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1130 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1131 "PLL state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133}
b24e7179 1134
23538ef1
JN		 1135/* XXX: the dsi pll is shared between MIPI DSI ports */
1136static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1137{
1138 u32 val;
1139 bool cur_state;
1140
1141 mutex_lock(&dev_priv->dpio_lock);
1142 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1143 mutex_unlock(&dev_priv->dpio_lock);
1144
1145 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1146 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1147 "DSI PLL state assertion failure (expected %s, current %s)\n",
1148 state_string(state), state_string(cur_state));
1149}
1150#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1151#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1152
55607e8a 1153struct intel_shared_dpll *
e2b78267
DV		 1154intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1155{
1156 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1157
6e3c9717 1158 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1159 return NULL;
1160
6e3c9717 1161 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1162}
1163
040484af 1164/* For ILK+ */
55607e8a
DV		 1165void assert_shared_dpll(struct drm_i915_private *dev_priv,
1166 struct intel_shared_dpll *pll,
1167 bool state)
040484af 1168{
040484af 1169 bool cur_state;
5358901f 1170 struct intel_dpll_hw_state hw_state;
040484af 1171
92b27b08 1172 if (WARN (!pll,
46edb027 1173 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1174 return;
ee7b9f93 1175
5358901f 1176 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1177 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1178 "%s assertion failure (expected %s, current %s)\n",
1179 pll->name, state_string(state), state_string(cur_state));
040484af 1180}
040484af
JB		 1181
1182static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1183 enum pipe pipe, bool state)
1184{
1185 int reg;
1186 u32 val;
1187 bool cur_state;
ad80a810
PZ		 1188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1189 pipe);
040484af 1190
affa9354
PZ		 1191 if (HAS_DDI(dev_priv->dev)) {
1192 /* DDI does not have a specific FDI_TX register */
ad80a810 1193 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1194 val = I915_READ(reg);
ad80a810 1195 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1196 } else {
1197 reg = FDI_TX_CTL(pipe);
1198 val = I915_READ(reg);
1199 cur_state = !!(val & FDI_TX_ENABLE);
1200 }
e2c719b7 1201 I915_STATE_WARN(cur_state != state,
040484af
JB		 1202 "FDI TX state assertion failure (expected %s, current %s)\n",
1203 state_string(state), state_string(cur_state));
1204}
1205#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1206#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1207
1208static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, bool state)
1210{
1211 int reg;
1212 u32 val;
1213 bool cur_state;
1214
d63fa0dc
PZ		 1215 reg = FDI_RX_CTL(pipe);
1216 val = I915_READ(reg);
1217 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1218 I915_STATE_WARN(cur_state != state,
040484af
JB		 1219 "FDI RX state assertion failure (expected %s, current %s)\n",
1220 state_string(state), state_string(cur_state));
1221}
1222#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1223#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1224
1225static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe)
1227{
1228 int reg;
1229 u32 val;
1230
1231 /* ILK FDI PLL is always enabled */
3d13ef2e 1232 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1233 return;
1234
bf507ef7 1235 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1236 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1237 return;
1238
040484af
JB		 1239 reg = FDI_TX_CTL(pipe);
1240 val = I915_READ(reg);
e2c719b7 1241 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1242}
1243
55607e8a
DV		 1244void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, bool state)
040484af
JB		 1246{
1247 int reg;
1248 u32 val;
55607e8a 1249 bool cur_state;
040484af
JB		 1250
1251 reg = FDI_RX_CTL(pipe);
1252 val = I915_READ(reg);
55607e8a 1253 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1254 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1255 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1256 state_string(state), state_string(cur_state));
040484af
JB		 1257}
1258
b680c37a
DV		 1259void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1260 enum pipe pipe)
ea0760cf 1261{
bedd4dba
JN		 1262 struct drm_device *dev = dev_priv->dev;
1263 int pp_reg;
ea0760cf
JB		 1264 u32 val;
1265 enum pipe panel_pipe = PIPE_A;
0de3b485 1266 bool locked = true;
ea0760cf 1267
bedd4dba
JN		 1268 if (WARN_ON(HAS_DDI(dev)))
1269 return;
1270
1271 if (HAS_PCH_SPLIT(dev)) {
1272 u32 port_sel;
1273
ea0760cf 1274 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1275 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1276
1277 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1278 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1279 panel_pipe = PIPE_B;
1280 /* XXX: else fix for eDP */
1281 } else if (IS_VALLEYVIEW(dev)) {
1282 /* presumably write lock depends on pipe, not port select */
1283 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1284 panel_pipe = pipe;
ea0760cf
JB		 1285 } else {
1286 pp_reg = PP_CONTROL;
bedd4dba
JN		 1287 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1288 panel_pipe = PIPE_B;
ea0760cf
JB		 1289 }
1290
1291 val = I915_READ(pp_reg);
1292 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1293 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1294 locked = false;
1295
e2c719b7 1296 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1297 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1298 pipe_name(pipe));
ea0760cf
JB		 1299}
1300
93ce0ba6
JN		 1301static void assert_cursor(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, bool state)
1303{
1304 struct drm_device *dev = dev_priv->dev;
1305 bool cur_state;
1306
d9d82081 1307 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1308 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1309 else
5efb3e28 1310 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1311
e2c719b7 1312 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1313 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe), state_string(state), state_string(cur_state));
1315}
1316#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1317#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1318
b840d907
JB		 1319void assert_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe, bool state)
b24e7179
JB		 1321{
1322 int reg;
1323 u32 val;
63d7bbe9 1324 bool cur_state;
702e7a56
PZ		 1325 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1326 pipe);
b24e7179 1327
b6b5d049
VS		 1328 /* if we need the pipe quirk it must be always on */
1329 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1330 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1331 state = true;
1332
f458ebbc 1333 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1334 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1335 cur_state = false;
1336 } else {
1337 reg = PIPECONF(cpu_transcoder);
1338 val = I915_READ(reg);
1339 cur_state = !!(val & PIPECONF_ENABLE);
1340 }
1341
e2c719b7 1342 I915_STATE_WARN(cur_state != state,
63d7bbe9 1343 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1344 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1345}
1346
931872fc
CW		 1347static void assert_plane(struct drm_i915_private *dev_priv,
1348 enum plane plane, bool state)
b24e7179
JB		 1349{
1350 int reg;
1351 u32 val;
931872fc 1352 bool cur_state;
b24e7179
JB		 1353
1354 reg = DSPCNTR(plane);
1355 val = I915_READ(reg);
931872fc 1356 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1357 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1358 "plane %c assertion failure (expected %s, current %s)\n",
1359 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1360}
1361
931872fc
CW		 1362#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1363#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1364
b24e7179
JB		 1365static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367{
653e1026 1368 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1369 int reg, i;
1370 u32 val;
1371 int cur_pipe;
1372
653e1026
VS		 1373 /* Primary planes are fixed to pipes on gen4+ */
1374 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1375 reg = DSPCNTR(pipe);
1376 val = I915_READ(reg);
e2c719b7 1377 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1378 "plane %c assertion failure, should be disabled but not\n",
1379 plane_name(pipe));
19ec1358 1380 return;
28c05794 1381 }
19ec1358 1382
b24e7179 1383 /* Need to check both planes against the pipe */
055e393f 1384 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1385 reg = DSPCNTR(i);
1386 val = I915_READ(reg);
1387 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1388 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1389 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1390 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1391 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1392 }
1393}
1394
19332d7a
JB		 1395static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
20674eef 1398 struct drm_device *dev = dev_priv->dev;
1fe47785 1399 int reg, sprite;
19332d7a
JB		 1400 u32 val;
1401
7feb8b88 1402 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1403 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1404 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1405 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1406 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407 sprite, pipe_name(pipe));
1408 }
1409 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1410 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1411 reg = SPCNTR(pipe, sprite);
20674eef 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1415 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1416 }
1417 } else if (INTEL_INFO(dev)->gen >= 7) {
1418 reg = SPRCTL(pipe);
19332d7a 1419 val = I915_READ(reg);
e2c719b7 1420 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1422 plane_name(pipe), pipe_name(pipe));
1423 } else if (INTEL_INFO(dev)->gen >= 5) {
1424 reg = DVSCNTR(pipe);
19332d7a 1425 val = I915_READ(reg);
e2c719b7 1426 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1427 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1428 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1429 }
1430}
1431
08c71e5e
VS		 1432static void assert_vblank_disabled(struct drm_crtc *crtc)
1433{
e2c719b7 1434 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1435 drm_crtc_vblank_put(crtc);
1436}
1437
89eff4be 1438static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1439{
1440 u32 val;
1441 bool enabled;
1442
e2c719b7 1443 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1444
92f2584a
JB		 1445 val = I915_READ(PCH_DREF_CONTROL);
1446 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1447 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1448 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1449}
1450
ab9412ba
DV		 1451static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe)
92f2584a
JB		 1453{
1454 int reg;
1455 u32 val;
1456 bool enabled;
1457
ab9412ba 1458 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1459 val = I915_READ(reg);
1460 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1461 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1462 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1463 pipe_name(pipe));
92f2584a
JB		 1464}
1465
4e634389
KP		 1466static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1468{
1469 if ((val & DP_PORT_EN) == 0)
1470 return false;
1471
1472 if (HAS_PCH_CPT(dev_priv->dev)) {
1473 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1474 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1475 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1476 return false;
44f37d1f
CML		 1477 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1478 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1479 return false;
f0575e92
KP		 1480 } else {
1481 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 return false;
1483 }
1484 return true;
1485}
1486
1519b995
KP		 1487static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1488 enum pipe pipe, u32 val)
1489{
dc0fa718 1490 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1491 return false;
1492
1493 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1494 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1495 return false;
44f37d1f
CML		 1496 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1498 return false;
1519b995 1499 } else {
dc0fa718 1500 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1501 return false;
1502 }
1503 return true;
1504}
1505
1506static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1507 enum pipe pipe, u32 val)
1508{
1509 if ((val & LVDS_PORT_EN) == 0)
1510 return false;
1511
1512 if (HAS_PCH_CPT(dev_priv->dev)) {
1513 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1514 return false;
1515 } else {
1516 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 return false;
1518 }
1519 return true;
1520}
1521
1522static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1523 enum pipe pipe, u32 val)
1524{
1525 if ((val & ADPA_DAC_ENABLE) == 0)
1526 return false;
1527 if (HAS_PCH_CPT(dev_priv->dev)) {
1528 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1529 return false;
1530 } else {
1531 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 return false;
1533 }
1534 return true;
1535}
1536
291906f1 1537static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1538 enum pipe pipe, int reg, u32 port_sel)
291906f1 1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1542 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1546 && (val & DP_PIPEB_SELECT),
de9a35ab 1547 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe, int reg)
1552{
47a05eca 1553 u32 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1555 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 reg, pipe_name(pipe));
de9a35ab 1557
e2c719b7 1558 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1559 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1560 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1561}
1562
1563static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
1565{
1566 int reg;
1567 u32 val;
291906f1 1568
f0575e92
KP		 1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1570 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1572
1573 reg = PCH_ADPA;
1574 val = I915_READ(reg);
e2c719b7 1575 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1576 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1577 pipe_name(pipe));
291906f1
JB		 1578
1579 reg = PCH_LVDS;
1580 val = I915_READ(reg);
e2c719b7 1581 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1582 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1583 pipe_name(pipe));
291906f1 1584
e2debe91
PZ		 1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1586 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1588}
1589
40e9cf64
JB		 1590static void intel_init_dpio(struct drm_device *dev)
1591{
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593
1594 if (!IS_VALLEYVIEW(dev))
1595 return;
1596
a09caddd
CML		 1597 /*
1598 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1599 * CHV x1 PHY (DP/HDMI D)
1600 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1601 */
1602 if (IS_CHERRYVIEW(dev)) {
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1605 } else {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1607 }
5382f5f3
JB		 1608}
1609
d288f65f 1610static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1611 const struct intel_crtc_state *pipe_config)
87442f73 1612{
426115cf
DV		 1613 struct drm_device *dev = crtc->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 int reg = DPLL(crtc->pipe);
d288f65f 1616 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1617
426115cf 1618 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1619
1620 /* No really, not for ILK+ */
1621 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1622
1623 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1624 if (IS_MOBILE(dev_priv->dev))
426115cf 1625 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1626
426115cf
DV		 1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1632 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1633
d288f65f 1634 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1635 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1636
1637 /* We do this three times for luck */
426115cf 1638 I915_WRITE(reg, dpll);
87442f73
DV		 1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647}
1648
d288f65f 1649static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1650 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1651{
1652 struct drm_device *dev = crtc->base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 int pipe = crtc->pipe;
1655 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1656 u32 tmp;
1657
1658 assert_pipe_disabled(dev_priv, crtc->pipe);
1659
1660 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1661
1662 mutex_lock(&dev_priv->dpio_lock);
1663
1664 /* Enable back the 10bit clock to display controller */
1665 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1666 tmp |= DPIO_DCLKP_EN;
1667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1668
1669 /*
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671 */
1672 udelay(1);
1673
1674 /* Enable PLL */
d288f65f 1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1676
1677 /* Check PLL is locked */
a11b0703 1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
a11b0703 1681 /* not sure when this should be written */
d288f65f 1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1683 POSTING_READ(DPLL_MD(pipe));
1684
9d556c99
CML		 1685 mutex_unlock(&dev_priv->dpio_lock);
1686}
1687
1c4e0274
VS		 1688static int intel_num_dvo_pipes(struct drm_device *dev)
1689{
1690 struct intel_crtc *crtc;
1691 int count = 0;
1692
1693 for_each_intel_crtc(dev, crtc)
1694 count += crtc->active &&
409ee761 1695 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1696
1697 return count;
1698}
1699
66e3d5c0 1700static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1701{
66e3d5c0
DV		 1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 int reg = DPLL(crtc->pipe);
6e3c9717 1705 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1706
66e3d5c0 1707 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1708
63d7bbe9 1709 /* No really, not for ILK+ */
3d13ef2e 1710 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1711
1712 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1713 if (IS_MOBILE(dev) && !IS_I830(dev))
1714 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1715
1c4e0274
VS		 1716 /* Enable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1718 /*
1719 * It appears to be important that we don't enable this
1720 * for the current pipe before otherwise configuring the
1721 * PLL. No idea how this should be handled if multiple
1722 * DVO outputs are enabled simultaneosly.
1723 */
1724 dpll |= DPLL_DVO_2X_MODE;
1725 I915_WRITE(DPLL(!crtc->pipe),
1726 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1727 }
66e3d5c0
DV		 1728
1729 /* Wait for the clocks to stabilize. */
1730 POSTING_READ(reg);
1731 udelay(150);
1732
1733 if (INTEL_INFO(dev)->gen >= 4) {
1734 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1735 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1736 } else {
1737 /* The pixel multiplier can only be updated once the
1738 * DPLL is enabled and the clocks are stable.
1739 *
1740 * So write it again.
1741 */
1742 I915_WRITE(reg, dpll);
1743 }
63d7bbe9
JB		 1744
1745 /* We do this three times for luck */
66e3d5c0 1746 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755}
1756
1757/**
50b44a44 1758 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe PLL to disable
1761 *
1762 * Disable the PLL for @pipe, making sure the pipe is off first.
1763 *
1764 * Note! This is for pre-ILK only.
1765 */
1c4e0274 1766static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1767{
1c4e0274
VS		 1768 struct drm_device *dev = crtc->base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 enum pipe pipe = crtc->pipe;
1771
1772 /* Disable DVO 2x clock on both PLLs if necessary */
1773 if (IS_I830(dev) &&
409ee761 1774 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1775 intel_num_dvo_pipes(dev) == 1) {
1776 I915_WRITE(DPLL(PIPE_B),
1777 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1778 I915_WRITE(DPLL(PIPE_A),
1779 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1780 }
1781
b6b5d049
VS		 1782 /* Don't disable pipe or pipe PLLs if needed */
1783 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1784 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1785 return;
1786
1787 /* Make sure the pipe isn't still relying on us */
1788 assert_pipe_disabled(dev_priv, pipe);
1789
50b44a44
DV		 1790 I915_WRITE(DPLL(pipe), 0);
1791 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1792}
1793
f6071166
JB		 1794static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1795{
1796 u32 val = 0;
1797
1798 /* Make sure the pipe isn't still relying on us */
1799 assert_pipe_disabled(dev_priv, pipe);
1800
e5cbfbfb
ID		 1801 /*
1802 * Leave integrated clock source and reference clock enabled for pipe B.
1803 * The latter is needed for VGA hotplug / manual detection.
1804 */
f6071166 1805 if (pipe == PIPE_B)
e5cbfbfb 1806 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1807 I915_WRITE(DPLL(pipe), val);
1808 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1809
1810}
1811
1812static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1813{
d752048d 1814 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1815 u32 val;
1816
a11b0703
VS		 1817 /* Make sure the pipe isn't still relying on us */
1818 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1819
a11b0703 1820 /* Set PLL en = 0 */
d17ec4ce 1821 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1822 if (pipe != PIPE_A)
1823 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824 I915_WRITE(DPLL(pipe), val);
1825 POSTING_READ(DPLL(pipe));
d752048d
VS		 1826
1827 mutex_lock(&dev_priv->dpio_lock);
1828
1829 /* Disable 10bit clock to display controller */
1830 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831 val &= ~DPIO_DCLKP_EN;
1832 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
61407f6d
VS		 1834 /* disable left/right clock distribution */
1835 if (pipe != PIPE_B) {
1836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1839 } else {
1840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1843 }
1844
d752048d 1845 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1846}
1847
e4607fcf
CML		 1848void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849 struct intel_digital_port *dport)
89b667f8
JB		 1850{
1851 u32 port_mask;
00fc31b7 1852 int dpll_reg;
89b667f8 1853
e4607fcf
CML		 1854 switch (dport->port) {
1855 case PORT_B:
89b667f8 1856 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1857 dpll_reg = DPLL(0);
e4607fcf
CML		 1858 break;
1859 case PORT_C:
89b667f8 1860 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1861 dpll_reg = DPLL(0);
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1866 break;
1867 default:
1868 BUG();
1869 }
89b667f8 1870
00fc31b7 1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1872 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1873 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1874}
1875
b14b1055
DV		 1876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
be19f0ff
CW		 1882 if (WARN_ON(pll == NULL))
1883 return;
1884
3e369b76 1885 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
92f2584a 1895/**
85b3894f 1896 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
85b3894f 1903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1904{
3d13ef2e
DL		 1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1908
87a875bb 1909 if (WARN_ON(pll == NULL))
48da64a8
CW		 1910 return;
1911
3e369b76 1912 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1913 return;
ee7b9f93 1914
74dd6928 1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1916 pll->name, pll->active, pll->on,
e2b78267 1917 crtc->base.base.id);
92f2584a 1918
cdbd2316
DV		 1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1922 return;
1923 }
f4a091c7 1924 WARN_ON(pll->on);
ee7b9f93 1925
bd2bb1b9
PZ		 1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
46edb027 1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1929 pll->enable(dev_priv, pll);
ee7b9f93 1930 pll->on = true;
92f2584a
JB		 1931}
1932
f6daaec2 1933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1934{
3d13ef2e
DL		 1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1938
92f2584a 1939 /* PCH only available on ILK+ */
3d13ef2e 1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1941 if (WARN_ON(pll == NULL))
ee7b9f93 1942 return;
92f2584a 1943
3e369b76 1944 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1945 return;
7a419866 1946
46edb027
DV		 1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
e2b78267 1949 crtc->base.base.id);
7a419866 1950
48da64a8 1951 if (WARN_ON(pll->active == 0)) {
e9d6944e 1952 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1953 return;
1954 }
1955
e9d6944e 1956 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1957 WARN_ON(!pll->on);
cdbd2316 1958 if (--pll->active)
7a419866 1959 return;
ee7b9f93 1960
46edb027 1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1962 pll->disable(dev_priv, pll);
ee7b9f93 1963 pll->on = false;
bd2bb1b9
PZ		 1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1966}
1967
b8a4f404
PZ		 1968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
040484af 1970{
23670b32 1971 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1974 uint32_t reg, val, pipeconf_val;
040484af
JB		 1975
1976 /* PCH only available on ILK+ */
55522f37 1977 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1978
1979 /* Make sure PCH DPLL is enabled */
e72f9fbf 1980 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1981 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
23670b32
DV		 1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
59c859d6 1994 }
23670b32 1995
ab9412ba 1996 reg = PCH_TRANSCONF(pipe);
040484af 1997 val = I915_READ(reg);
5f7f726d 1998 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
dfd07d72
DV		 2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2007 }
5f7f726d
PZ		 2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2011 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
040484af
JB		 2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2022}
2023
8fb033d7 2024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2025 enum transcoder cpu_transcoder)
040484af 2026{
8fb033d7 2027 u32 val, pipeconf_val;
8fb033d7
PZ		 2028
2029 /* PCH only available on ILK+ */
55522f37 2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2031
8fb033d7 2032 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2035
223a6fdf
PZ		 2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
25f3ef11 2041 val = TRANS_ENABLE;
937bb610 2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2043
9a76b1c6
PZ		 2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
a35f2679 2046 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
ab9412ba
DV		 2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2052 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2053}
2054
b8a4f404
PZ		 2055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
040484af 2057{
23670b32
DV		 2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
040484af
JB		 2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
291906f1
JB		 2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
ab9412ba 2068 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
040484af
JB		 2083}
2084
ab4d966c 2085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2086{
8fb033d7
PZ		 2087 u32 val;
2088
ab9412ba 2089 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2090 val &= ~TRANS_ENABLE;
ab9412ba 2091 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2092 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2094 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2099 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2100}
2101
b24e7179 2102/**
309cfea8 2103 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2104 * @crtc: crtc responsible for the pipe
b24e7179 2105 *
0372264a 2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2108 */
e1fdc473 2109static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2110{
0372264a
PZ		 2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
1a240d4d 2116 enum pipe pch_transcoder;
b24e7179
JB		 2117 int reg;
2118 u32 val;
2119
58c6eaa2 2120 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2121 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2122 assert_sprites_disabled(dev_priv, pipe);
2123
681e5811 2124 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
b24e7179
JB		 2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
2134 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
040484af 2139 else {
6e3c9717 2140 if (crtc->config->has_pch_encoder) {
040484af 2141 /* if driving the PCH, we need FDI enabled */
cc391bbb 2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
040484af
JB		 2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
b24e7179 2148
702e7a56 2149 reg = PIPECONF(cpu_transcoder);
b24e7179 2150 val = I915_READ(reg);
7ad25d48 2151 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2154 return;
7ad25d48 2155 }
00d70b15
CW		 2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2158 POSTING_READ(reg);
b24e7179
JB		 2159}
2160
2161/**
309cfea8 2162 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2163 * @crtc: crtc whose pipes is to be disabled
b24e7179 2164 *
575f7ab7
VS		 2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
b24e7179
JB		 2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
575f7ab7 2171static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2172{
575f7ab7 2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2175 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2184 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2185 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2186
702e7a56 2187 reg = PIPECONF(cpu_transcoder);
b24e7179 2188 val = I915_READ(reg);
00d70b15
CW		 2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
67adc644
VS		 2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
6e3c9717 2196 if (crtc->config->double_wide)
67adc644
VS		 2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2207}
2208
d74362c9
KP		 2209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
1dba99f4
VS		 2213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
d74362c9 2215{
3d13ef2e
DL		 2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
d74362c9
KP		 2221}
2222
b24e7179 2223/**
262ca2b0 2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
b24e7179 2227 *
fdd508a6 2228 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2229 */
fdd508a6
VS		 2230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
b24e7179 2232{
fdd508a6
VS		 2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2239
98ec7739
VS		 2240 if (intel_crtc->primary_enabled)
2241 return;
0037f71c 2242
4c445e0e 2243 intel_crtc->primary_enabled = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
33c3b0d1
VS		 2247
2248 /*
2249 * BDW signals flip done immediately if the plane
2250 * is disabled, even if the plane enable is already
2251 * armed to occur at the next vblank :(
2252 */
2253 if (IS_BROADWELL(dev))
2254 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2255}
2256
b24e7179 2257/**
262ca2b0 2258 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2259 * @plane: plane to be disabled
2260 * @crtc: crtc for the plane
b24e7179 2261 *
fdd508a6 2262 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2263 */
fdd508a6
VS		 2264static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2265 struct drm_crtc *crtc)
b24e7179 2266{
fdd508a6
VS		 2267 struct drm_device *dev = plane->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270
32b7eeec
MR		 2271 if (WARN_ON(!intel_crtc->active))
2272 return;
b24e7179 2273
98ec7739
VS		 2274 if (!intel_crtc->primary_enabled)
2275 return;
0037f71c 2276
4c445e0e 2277 intel_crtc->primary_enabled = false;
939c2fe8 2278
fdd508a6
VS		 2279 dev_priv->display.update_primary_plane(crtc, plane->fb,
2280 crtc->x, crtc->y);
b24e7179
JB		 2281}
2282
693db184
CW		 2283static bool need_vtd_wa(struct drm_device *dev)
2284{
2285#ifdef CONFIG_INTEL_IOMMU
2286 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2287 return true;
2288#endif
2289 return false;
2290}
2291
50470bb0 2292unsigned int
6761dd31
TU		 2293intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2294 uint64_t fb_format_modifier)
a57ce0b2 2295{
6761dd31
TU		 2296 unsigned int tile_height;
2297 uint32_t pixel_bytes;
a57ce0b2 2298
b5d0e9bf
DL		 2299 switch (fb_format_modifier) {
2300 case DRM_FORMAT_MOD_NONE:
2301 tile_height = 1;
2302 break;
2303 case I915_FORMAT_MOD_X_TILED:
2304 tile_height = IS_GEN2(dev) ? 16 : 8;
2305 break;
2306 case I915_FORMAT_MOD_Y_TILED:
2307 tile_height = 32;
2308 break;
2309 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2310 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2311 switch (pixel_bytes) {
b5d0e9bf 2312 default:
6761dd31 2313 case 1:
b5d0e9bf
DL		 2314 tile_height = 64;
2315 break;
6761dd31
TU		 2316 case 2:
2317 case 4:
b5d0e9bf
DL		 2318 tile_height = 32;
2319 break;
6761dd31 2320 case 8:
b5d0e9bf
DL		 2321 tile_height = 16;
2322 break;
6761dd31 2323 case 16:
b5d0e9bf
DL		 2324 WARN_ONCE(1,
2325 "128-bit pixels are not supported for display!");
2326 tile_height = 16;
2327 break;
2328 }
2329 break;
2330 default:
2331 MISSING_CASE(fb_format_modifier);
2332 tile_height = 1;
2333 break;
2334 }
091df6cb 2335
6761dd31
TU		 2336 return tile_height;
2337}
2338
2339unsigned int
2340intel_fb_align_height(struct drm_device *dev, unsigned int height,
2341 uint32_t pixel_format, uint64_t fb_format_modifier)
2342{
2343 return ALIGN(height, intel_tile_height(dev, pixel_format,
2344 fb_format_modifier));
a57ce0b2
JB		 2345}
2346
f64b98cd
TU		 2347static int
2348intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2349 const struct drm_plane_state *plane_state)
2350{
50470bb0 2351 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2352
f64b98cd
TU		 2353 *view = i915_ggtt_view_normal;
2354
50470bb0
TU		 2355 if (!plane_state)
2356 return 0;
2357
121920fa 2358 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2359 return 0;
2360
9abc4648 2361 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2362
2363 info->height = fb->height;
2364 info->pixel_format = fb->pixel_format;
2365 info->pitch = fb->pitches[0];
2366 info->fb_modifier = fb->modifier[0];
2367
f64b98cd
TU		 2368 return 0;
2369}
2370
127bd2ac 2371int
850c4cdc
TU		 2372intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2373 struct drm_framebuffer *fb,
82bc3b2d 2374 const struct drm_plane_state *plane_state,
a4872ba6 2375 struct intel_engine_cs *pipelined)
6b95a207 2376{
850c4cdc 2377 struct drm_device *dev = fb->dev;
ce453d81 2378 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2379 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2380 struct i915_ggtt_view view;
6b95a207
KH		 2381 u32 alignment;
2382 int ret;
2383
ebcdd39e
MR		 2384 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2385
7b911adc
TU		 2386 switch (fb->modifier[0]) {
2387 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2388 if (INTEL_INFO(dev)->gen >= 9)
2389 alignment = 256 * 1024;
2390 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2391 alignment = 128 * 1024;
a6c45cf0 2392 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2393 alignment = 4 * 1024;
2394 else
2395 alignment = 64 * 1024;
6b95a207 2396 break;
7b911adc 2397 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2398 if (INTEL_INFO(dev)->gen >= 9)
2399 alignment = 256 * 1024;
2400 else {
2401 /* pin() will align the object as required by fence */
2402 alignment = 0;
2403 }
6b95a207 2404 break;
7b911adc 2405 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2406 case I915_FORMAT_MOD_Yf_TILED:
2407 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2408 "Y tiling bo slipped through, driver bug!\n"))
2409 return -EINVAL;
2410 alignment = 1 * 1024 * 1024;
2411 break;
6b95a207 2412 default:
7b911adc
TU		 2413 MISSING_CASE(fb->modifier[0]);
2414 return -EINVAL;
6b95a207
KH		 2415 }
2416
f64b98cd
TU		 2417 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2418 if (ret)
2419 return ret;
2420
693db184
CW		 2421 /* Note that the w/a also requires 64 PTE of padding following the
2422 * bo. We currently fill all unused PTE with the shadow page and so
2423 * we should always have valid PTE following the scanout preventing
2424 * the VT-d warning.
2425 */
2426 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2427 alignment = 256 * 1024;
2428
d6dd6843
PZ		 2429 /*
2430 * Global gtt pte registers are special registers which actually forward
2431 * writes to a chunk of system memory. Which means that there is no risk
2432 * that the register values disappear as soon as we call
2433 * intel_runtime_pm_put(), so it is correct to wrap only the
2434 * pin/unpin/fence and not more.
2435 */
2436 intel_runtime_pm_get(dev_priv);
2437
ce453d81 2438 dev_priv->mm.interruptible = false;
e6617330 2439 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2440 &view);
48b956c5 2441 if (ret)
ce453d81 2442 goto err_interruptible;
6b95a207
KH		 2443
2444 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2445 * fence, whereas 965+ only requires a fence if using
2446 * framebuffer compression. For simplicity, we always install
2447 * a fence as the cost is not that onerous.
2448 */
06d98131 2449 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2450 if (ret)
2451 goto err_unpin;
1690e1eb 2452
9a5a53b3 2453 i915_gem_object_pin_fence(obj);
6b95a207 2454
ce453d81 2455 dev_priv->mm.interruptible = true;
d6dd6843 2456 intel_runtime_pm_put(dev_priv);
6b95a207 2457 return 0;
48b956c5
CW		 2458
2459err_unpin:
f64b98cd 2460 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2461err_interruptible:
2462 dev_priv->mm.interruptible = true;
d6dd6843 2463 intel_runtime_pm_put(dev_priv);
48b956c5 2464 return ret;
6b95a207
KH		 2465}
2466
82bc3b2d
TU		 2467static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2468 const struct drm_plane_state *plane_state)
1690e1eb 2469{
82bc3b2d 2470 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2471 struct i915_ggtt_view view;
2472 int ret;
82bc3b2d 2473
ebcdd39e
MR		 2474 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2475
f64b98cd
TU		 2476 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2477 WARN_ONCE(ret, "Couldn't get view from plane state!");
2478
1690e1eb 2479 i915_gem_object_unpin_fence(obj);
f64b98cd 2480 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2481}
2482
c2c75131
DV		 2483/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2484 * is assumed to be a power-of-two. */
bc752862
CW		 2485unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2486 unsigned int tiling_mode,
2487 unsigned int cpp,
2488 unsigned int pitch)
c2c75131 2489{
bc752862
CW		 2490 if (tiling_mode != I915_TILING_NONE) {
2491 unsigned int tile_rows, tiles;
c2c75131 2492
bc752862
CW		 2493 tile_rows = *y / 8;
2494 *y %= 8;
c2c75131 2495
bc752862
CW		 2496 tiles = *x / (512/cpp);
2497 *x %= 512/cpp;
2498
2499 return tile_rows * pitch * 8 + tiles * 4096;
2500 } else {
2501 unsigned int offset;
2502
2503 offset = *y * pitch + *x * cpp;
2504 *y = 0;
2505 *x = (offset & 4095) / cpp;
2506 return offset & -4096;
2507 }
c2c75131
DV		 2508}
2509
b35d63fa 2510static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2511{
2512 switch (format) {
2513 case DISPPLANE_8BPP:
2514 return DRM_FORMAT_C8;
2515 case DISPPLANE_BGRX555:
2516 return DRM_FORMAT_XRGB1555;
2517 case DISPPLANE_BGRX565:
2518 return DRM_FORMAT_RGB565;
2519 default:
2520 case DISPPLANE_BGRX888:
2521 return DRM_FORMAT_XRGB8888;
2522 case DISPPLANE_RGBX888:
2523 return DRM_FORMAT_XBGR8888;
2524 case DISPPLANE_BGRX101010:
2525 return DRM_FORMAT_XRGB2101010;
2526 case DISPPLANE_RGBX101010:
2527 return DRM_FORMAT_XBGR2101010;
2528 }
2529}
2530
bc8d7dff
DL		 2531static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2532{
2533 switch (format) {
2534 case PLANE_CTL_FORMAT_RGB_565:
2535 return DRM_FORMAT_RGB565;
2536 default:
2537 case PLANE_CTL_FORMAT_XRGB_8888:
2538 if (rgb_order) {
2539 if (alpha)
2540 return DRM_FORMAT_ABGR8888;
2541 else
2542 return DRM_FORMAT_XBGR8888;
2543 } else {
2544 if (alpha)
2545 return DRM_FORMAT_ARGB8888;
2546 else
2547 return DRM_FORMAT_XRGB8888;
2548 }
2549 case PLANE_CTL_FORMAT_XRGB_2101010:
2550 if (rgb_order)
2551 return DRM_FORMAT_XBGR2101010;
2552 else
2553 return DRM_FORMAT_XRGB2101010;
2554 }
2555}
2556
5724dbd1 2557static bool
f6936e29
DV		 2558intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2559 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2560{
2561 struct drm_device *dev = crtc->base.dev;
2562 struct drm_i915_gem_object *obj = NULL;
2563 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2564 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2565 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2566 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2567 PAGE_SIZE);
2568
2569 size_aligned -= base_aligned;
46f297fb 2570
ff2652ea
CW		 2571 if (plane_config->size == 0)
2572 return false;
2573
f37b5c2b
DV		 2574 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2575 base_aligned,
2576 base_aligned,
2577 size_aligned);
46f297fb 2578 if (!obj)
484b41dd 2579 return false;
46f297fb 2580
49af449b
DL		 2581 obj->tiling_mode = plane_config->tiling;
2582 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2583 obj->stride = fb->pitches[0];
46f297fb 2584
6bf129df
DL		 2585 mode_cmd.pixel_format = fb->pixel_format;
2586 mode_cmd.width = fb->width;
2587 mode_cmd.height = fb->height;
2588 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2589 mode_cmd.modifier[0] = fb->modifier[0];
2590 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2591
2592 mutex_lock(&dev->struct_mutex);
6bf129df 2593 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2594 &mode_cmd, obj)) {
46f297fb
JB		 2595 DRM_DEBUG_KMS("intel fb init failed\n");
2596 goto out_unref_obj;
2597 }
46f297fb 2598 mutex_unlock(&dev->struct_mutex);
484b41dd 2599
f6936e29 2600 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2601 return true;
46f297fb
JB		 2602
2603out_unref_obj:
2604 drm_gem_object_unreference(&obj->base);
2605 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2606 return false;
2607}
2608
afd65eb4
MR		 2609/* Update plane->state->fb to match plane->fb after driver-internal updates */
2610static void
2611update_state_fb(struct drm_plane *plane)
2612{
2613 if (plane->fb == plane->state->fb)
2614 return;
2615
2616 if (plane->state->fb)
2617 drm_framebuffer_unreference(plane->state->fb);
2618 plane->state->fb = plane->fb;
2619 if (plane->state->fb)
2620 drm_framebuffer_reference(plane->state->fb);
2621}
2622
5724dbd1 2623static void
f6936e29
DV		 2624intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2625 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2626{
2627 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2628 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2629 struct drm_crtc *c;
2630 struct intel_crtc *i;
2ff8fde1 2631 struct drm_i915_gem_object *obj;
88595ac9
DV		 2632 struct drm_plane *primary = intel_crtc->base.primary;
2633 struct drm_framebuffer *fb;
484b41dd 2634
2d14030b 2635 if (!plane_config->fb)
484b41dd
JB		 2636 return;
2637
f6936e29 2638 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2639 fb = &plane_config->fb->base;
2640 goto valid_fb;
f55548b5 2641 }
484b41dd 2642
2d14030b 2643 kfree(plane_config->fb);
484b41dd
JB		 2644
2645 /*
2646 * Failed to alloc the obj, check to see if we should share
2647 * an fb with another CRTC instead
2648 */
70e1e0ec 2649 for_each_crtc(dev, c) {
484b41dd
JB		 2650 i = to_intel_crtc(c);
2651
2652 if (c == &intel_crtc->base)
2653 continue;
2654
2ff8fde1
MR		 2655 if (!i->active)
2656 continue;
2657
88595ac9
DV		 2658 fb = c->primary->fb;
2659 if (!fb)
484b41dd
JB		 2660 continue;
2661
88595ac9 2662 obj = intel_fb_obj(fb);
2ff8fde1 2663 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2664 drm_framebuffer_reference(fb);
2665 goto valid_fb;
484b41dd
JB		 2666 }
2667 }
88595ac9
DV		 2668
2669 return;
2670
2671valid_fb:
2672 obj = intel_fb_obj(fb);
2673 if (obj->tiling_mode != I915_TILING_NONE)
2674 dev_priv->preserve_bios_swizzle = true;
2675
2676 primary->fb = fb;
2677 primary->state->crtc = &intel_crtc->base;
2678 primary->crtc = &intel_crtc->base;
2679 update_state_fb(primary);
2680 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2681}
2682
29b9bde6
DV		 2683static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2684 struct drm_framebuffer *fb,
2685 int x, int y)
81255565
JB		 2686{
2687 struct drm_device *dev = crtc->dev;
2688 struct drm_i915_private *dev_priv = dev->dev_private;
2689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2690 struct drm_i915_gem_object *obj;
81255565 2691 int plane = intel_crtc->plane;
e506a0c6 2692 unsigned long linear_offset;
81255565 2693 u32 dspcntr;
f45651ba 2694 u32 reg = DSPCNTR(plane);
48404c1e 2695 int pixel_size;
f45651ba 2696
fdd508a6
VS		 2697 if (!intel_crtc->primary_enabled) {
2698 I915_WRITE(reg, 0);
2699 if (INTEL_INFO(dev)->gen >= 4)
2700 I915_WRITE(DSPSURF(plane), 0);
2701 else
2702 I915_WRITE(DSPADDR(plane), 0);
2703 POSTING_READ(reg);
2704 return;
2705 }
2706
c9ba6fad
VS		 2707 obj = intel_fb_obj(fb);
2708 if (WARN_ON(obj == NULL))
2709 return;
2710
2711 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2712
f45651ba
VS		 2713 dspcntr = DISPPLANE_GAMMA_ENABLE;
2714
fdd508a6 2715 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2716
2717 if (INTEL_INFO(dev)->gen < 4) {
2718 if (intel_crtc->pipe == PIPE_B)
2719 dspcntr |= DISPPLANE_SEL_PIPE_B;
2720
2721 /* pipesrc and dspsize control the size that is scaled from,
2722 * which should always be the user's requested size.
2723 */
2724 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2725 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2726 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2727 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2728 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2729 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2730 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2731 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2732 I915_WRITE(PRIMPOS(plane), 0);
2733 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2734 }
81255565 2735
57779d06
VS		 2736 switch (fb->pixel_format) {
2737 case DRM_FORMAT_C8:
81255565
JB		 2738 dspcntr |= DISPPLANE_8BPP;
2739 break;
57779d06
VS		 2740 case DRM_FORMAT_XRGB1555:
2741 case DRM_FORMAT_ARGB1555:
2742 dspcntr |= DISPPLANE_BGRX555;
81255565 2743 break;
57779d06
VS		 2744 case DRM_FORMAT_RGB565:
2745 dspcntr |= DISPPLANE_BGRX565;
2746 break;
2747 case DRM_FORMAT_XRGB8888:
2748 case DRM_FORMAT_ARGB8888:
2749 dspcntr |= DISPPLANE_BGRX888;
2750 break;
2751 case DRM_FORMAT_XBGR8888:
2752 case DRM_FORMAT_ABGR8888:
2753 dspcntr |= DISPPLANE_RGBX888;
2754 break;
2755 case DRM_FORMAT_XRGB2101010:
2756 case DRM_FORMAT_ARGB2101010:
2757 dspcntr |= DISPPLANE_BGRX101010;
2758 break;
2759 case DRM_FORMAT_XBGR2101010:
2760 case DRM_FORMAT_ABGR2101010:
2761 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2762 break;
2763 default:
baba133a 2764 BUG();
81255565 2765 }
57779d06 2766
f45651ba
VS		 2767 if (INTEL_INFO(dev)->gen >= 4 &&
2768 obj->tiling_mode != I915_TILING_NONE)
2769 dspcntr |= DISPPLANE_TILED;
81255565 2770
de1aa629
VS		 2771 if (IS_G4X(dev))
2772 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2773
b9897127 2774 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2775
c2c75131
DV		 2776 if (INTEL_INFO(dev)->gen >= 4) {
2777 intel_crtc->dspaddr_offset =
bc752862 2778 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2779 pixel_size,
bc752862 2780 fb->pitches[0]);
c2c75131
DV		 2781 linear_offset -= intel_crtc->dspaddr_offset;
2782 } else {
e506a0c6 2783 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2784 }
e506a0c6 2785
8e7d688b 2786 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2787 dspcntr |= DISPPLANE_ROTATE_180;
2788
6e3c9717
ACO		 2789 x += (intel_crtc->config->pipe_src_w - 1);
2790 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2791
2792 /* Finding the last pixel of the last line of the display
2793 data and adding to linear_offset*/
2794 linear_offset +=
6e3c9717
ACO		 2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2797 }
2798
2799 I915_WRITE(reg, dspcntr);
2800
01f2c773 2801 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2802 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2803 I915_WRITE(DSPSURF(plane),
2804 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2805 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2806 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2807 } else
f343c5f6 2808 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2809 POSTING_READ(reg);
17638cd6
JB		 2810}
2811
29b9bde6
DV		 2812static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2813 struct drm_framebuffer *fb,
2814 int x, int y)
17638cd6
JB		 2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2819 struct drm_i915_gem_object *obj;
17638cd6 2820 int plane = intel_crtc->plane;
e506a0c6 2821 unsigned long linear_offset;
17638cd6 2822 u32 dspcntr;
f45651ba 2823 u32 reg = DSPCNTR(plane);
48404c1e 2824 int pixel_size;
f45651ba 2825
fdd508a6
VS		 2826 if (!intel_crtc->primary_enabled) {
2827 I915_WRITE(reg, 0);
2828 I915_WRITE(DSPSURF(plane), 0);
2829 POSTING_READ(reg);
2830 return;
2831 }
2832
c9ba6fad
VS		 2833 obj = intel_fb_obj(fb);
2834 if (WARN_ON(obj == NULL))
2835 return;
2836
2837 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2838
f45651ba
VS		 2839 dspcntr = DISPPLANE_GAMMA_ENABLE;
2840
fdd508a6 2841 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2842
2843 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2844 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2845
57779d06
VS		 2846 switch (fb->pixel_format) {
2847 case DRM_FORMAT_C8:
17638cd6
JB		 2848 dspcntr |= DISPPLANE_8BPP;
2849 break;
57779d06
VS		 2850 case DRM_FORMAT_RGB565:
2851 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2852 break;
57779d06
VS		 2853 case DRM_FORMAT_XRGB8888:
2854 case DRM_FORMAT_ARGB8888:
2855 dspcntr |= DISPPLANE_BGRX888;
2856 break;
2857 case DRM_FORMAT_XBGR8888:
2858 case DRM_FORMAT_ABGR8888:
2859 dspcntr |= DISPPLANE_RGBX888;
2860 break;
2861 case DRM_FORMAT_XRGB2101010:
2862 case DRM_FORMAT_ARGB2101010:
2863 dspcntr |= DISPPLANE_BGRX101010;
2864 break;
2865 case DRM_FORMAT_XBGR2101010:
2866 case DRM_FORMAT_ABGR2101010:
2867 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2868 break;
2869 default:
baba133a 2870 BUG();
17638cd6
JB		 2871 }
2872
2873 if (obj->tiling_mode != I915_TILING_NONE)
2874 dspcntr |= DISPPLANE_TILED;
17638cd6 2875
f45651ba 2876 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2877 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2878
b9897127 2879 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2880 intel_crtc->dspaddr_offset =
bc752862 2881 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2882 pixel_size,
bc752862 2883 fb->pitches[0]);
c2c75131 2884 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2885 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2886 dspcntr |= DISPPLANE_ROTATE_180;
2887
2888 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2889 x += (intel_crtc->config->pipe_src_w - 1);
2890 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2891
2892 /* Finding the last pixel of the last line of the display
2893 data and adding to linear_offset*/
2894 linear_offset +=
6e3c9717
ACO		 2895 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2896 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2897 }
2898 }
2899
2900 I915_WRITE(reg, dspcntr);
17638cd6 2901
01f2c773 2902 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2903 I915_WRITE(DSPSURF(plane),
2904 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2905 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2906 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2907 } else {
2908 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2909 I915_WRITE(DSPLINOFF(plane), linear_offset);
2910 }
17638cd6 2911 POSTING_READ(reg);
17638cd6
JB		 2912}
2913
b321803d
DL		 2914u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2915 uint32_t pixel_format)
2916{
2917 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2918
2919 /*
2920 * The stride is either expressed as a multiple of 64 bytes
2921 * chunks for linear buffers or in number of tiles for tiled
2922 * buffers.
2923 */
2924 switch (fb_modifier) {
2925 case DRM_FORMAT_MOD_NONE:
2926 return 64;
2927 case I915_FORMAT_MOD_X_TILED:
2928 if (INTEL_INFO(dev)->gen == 2)
2929 return 128;
2930 return 512;
2931 case I915_FORMAT_MOD_Y_TILED:
2932 /* No need to check for old gens and Y tiling since this is
2933 * about the display engine and those will be blocked before
2934 * we get here.
2935 */
2936 return 128;
2937 case I915_FORMAT_MOD_Yf_TILED:
2938 if (bits_per_pixel == 8)
2939 return 64;
2940 else
2941 return 128;
2942 default:
2943 MISSING_CASE(fb_modifier);
2944 return 64;
2945 }
2946}
2947
121920fa
TU		 2948unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2949 struct drm_i915_gem_object *obj)
2950{
9abc4648 2951 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2952
2953 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2954 view = &i915_ggtt_view_rotated;
121920fa
TU		 2955
2956 return i915_gem_obj_ggtt_offset_view(obj, view);
2957}
2958
a1b2278e
CK		 2959/*
2960 * This function detaches (aka. unbinds) unused scalers in hardware
2961 */
2962void skl_detach_scalers(struct intel_crtc *intel_crtc)
2963{
2964 struct drm_device *dev;
2965 struct drm_i915_private *dev_priv;
2966 struct intel_crtc_scaler_state *scaler_state;
2967 int i;
2968
2969 if (!intel_crtc || !intel_crtc->config)
2970 return;
2971
2972 dev = intel_crtc->base.dev;
2973 dev_priv = dev->dev_private;
2974 scaler_state = &intel_crtc->config->scaler_state;
2975
2976 /* loop through and disable scalers that aren't in use */
2977 for (i = 0; i < intel_crtc->num_scalers; i++) {
2978 if (!scaler_state->scalers[i].in_use) {
2979 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2980 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2981 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2982 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2983 intel_crtc->base.base.id, intel_crtc->pipe, i);
2984 }
2985 }
2986}
2987
70d21f0e
DL		 2988static void skylake_update_primary_plane(struct drm_crtc *crtc,
2989 struct drm_framebuffer *fb,
2990 int x, int y)
2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2995 struct drm_i915_gem_object *obj;
2996 int pipe = intel_crtc->pipe;
3b7a5119
SJ		 2997 u32 plane_ctl, stride_div, stride;
2998 u32 tile_height, plane_offset, plane_size;
2999 unsigned int rotation;
3000 int x_offset, y_offset;
121920fa 3001 unsigned long surf_addr;
3b7a5119 3002 struct drm_plane *plane;
70d21f0e
DL		 3003
3004 if (!intel_crtc->primary_enabled) {
3005 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3006 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3007 POSTING_READ(PLANE_CTL(pipe, 0));
3008 return;
3009 }
3010
3011 plane_ctl = PLANE_CTL_ENABLE |
3012 PLANE_CTL_PIPE_GAMMA_ENABLE |
3013 PLANE_CTL_PIPE_CSC_ENABLE;
3014
3015 switch (fb->pixel_format) {
3016 case DRM_FORMAT_RGB565:
3017 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
3018 break;
3019 case DRM_FORMAT_XRGB8888:
3020 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3021 break;
f75fb42a
JN		 3022 case DRM_FORMAT_ARGB8888:
3023 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3024 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3025 break;
70d21f0e
DL		 3026 case DRM_FORMAT_XBGR8888:
3027 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3028 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3029 break;
f75fb42a
JN		 3030 case DRM_FORMAT_ABGR8888:
3031 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3032 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
3033 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3034 break;
70d21f0e
DL		 3035 case DRM_FORMAT_XRGB2101010:
3036 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3037 break;
3038 case DRM_FORMAT_XBGR2101010:
3039 plane_ctl |= PLANE_CTL_ORDER_RGBX;
3040 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
3041 break;
3042 default:
3043 BUG();
3044 }
3045
30af77c4
DV		 3046 switch (fb->modifier[0]) {
3047 case DRM_FORMAT_MOD_NONE:
70d21f0e 3048 break;
30af77c4 3049 case I915_FORMAT_MOD_X_TILED:
70d21f0e 3050 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 3051 break;
3052 case I915_FORMAT_MOD_Y_TILED:
3053 plane_ctl |= PLANE_CTL_TILED_Y;
3054 break;
3055 case I915_FORMAT_MOD_Yf_TILED:
3056 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3057 break;
3058 default:
b321803d 3059 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3060 }
3061
3062 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3b7a5119
SJ		 3063
3064 plane = crtc->primary;
3065 rotation = plane->state->rotation;
3066 switch (rotation) {
3067 case BIT(DRM_ROTATE_90):
3068 plane_ctl |= PLANE_CTL_ROTATE_90;
3069 break;
3070
3071 case BIT(DRM_ROTATE_180):
1447dde0 3072 plane_ctl |= PLANE_CTL_ROTATE_180;
3b7a5119
SJ		 3073 break;
3074
3075 case BIT(DRM_ROTATE_270):
3076 plane_ctl |= PLANE_CTL_ROTATE_270;
3077 break;
3078 }
70d21f0e 3079
b321803d
DL		 3080 obj = intel_fb_obj(fb);
3081 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3082 fb->pixel_format);
3b7a5119
SJ		 3083 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3084
3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
3087 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
3090 x_offset = stride * tile_height - y - (plane->state->src_h >> 16);
3091 y_offset = x;
3092 plane_size = ((plane->state->src_w >> 16) - 1) << 16 |
3093 ((plane->state->src_h >> 16) - 1);
3094 } else {
3095 stride = fb->pitches[0] / stride_div;
3096 x_offset = x;
3097 y_offset = y;
3098 plane_size = ((plane->state->src_h >> 16) - 1) << 16 |
3099 ((plane->state->src_w >> 16) - 1);
3100 }
3101 plane_offset = y_offset << 16 | x_offset;
b321803d 3102
70d21f0e 3103 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e 3104 I915_WRITE(PLANE_POS(pipe, 0), 0);
3b7a5119
SJ		 3105 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3106 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3107 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
121920fa 3108 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3109
3110 POSTING_READ(PLANE_SURF(pipe, 0));
3111}
3112
17638cd6
JB		 3113/* Assume fb object is pinned & idle & fenced and just update base pointers */
3114static int
3115intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3116 int x, int y, enum mode_set_atomic state)
3117{
3118 struct drm_device *dev = crtc->dev;
3119 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3120
6b8e6ed0
CW		 3121 if (dev_priv->display.disable_fbc)
3122 dev_priv->display.disable_fbc(dev);
81255565 3123
29b9bde6
DV		 3124 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3125
3126 return 0;
81255565
JB		 3127}
3128
7514747d 3129static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3130{
96a02917
VS		 3131 struct drm_crtc *crtc;
3132
70e1e0ec 3133 for_each_crtc(dev, crtc) {
96a02917
VS		 3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 enum plane plane = intel_crtc->plane;
3136
3137 intel_prepare_page_flip(dev, plane);
3138 intel_finish_page_flip_plane(dev, plane);
3139 }
7514747d
VS		 3140}
3141
3142static void intel_update_primary_planes(struct drm_device *dev)
3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct drm_crtc *crtc;
96a02917 3146
70e1e0ec 3147 for_each_crtc(dev, crtc) {
96a02917
VS		 3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149
51fd371b 3150 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3151 /*
3152 * FIXME: Once we have proper support for primary planes (and
3153 * disabling them without disabling the entire crtc) allow again
66e514c1 3154 * a NULL crtc->primary->fb.
947fdaad 3155 */
f4510a27 3156 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3157 dev_priv->display.update_primary_plane(crtc,
66e514c1 3158 crtc->primary->fb,
262ca2b0
MR		 3159 crtc->x,
3160 crtc->y);
51fd371b 3161 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3162 }
3163}
3164
7514747d
VS		 3165void intel_prepare_reset(struct drm_device *dev)
3166{
f98ce92f
VS		 3167 struct drm_i915_private *dev_priv = to_i915(dev);
3168 struct intel_crtc *crtc;
3169
7514747d
VS		 3170 /* no reset support for gen2 */
3171 if (IS_GEN2(dev))
3172 return;
3173
3174 /* reset doesn't touch the display */
3175 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3176 return;
3177
3178 drm_modeset_lock_all(dev);
f98ce92f
VS		 3179
3180 /*
3181 * Disabling the crtcs gracefully seems nicer. Also the
3182 * g33 docs say we should at least disable all the planes.
3183 */
3184 for_each_intel_crtc(dev, crtc) {
3185 if (crtc->active)
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 }
7514747d
VS		 3188}
3189
3190void intel_finish_reset(struct drm_device *dev)
3191{
3192 struct drm_i915_private *dev_priv = to_i915(dev);
3193
3194 /*
3195 * Flips in the rings will be nuked by the reset,
3196 * so complete all pending flips so that user space
3197 * will get its events and not get stuck.
3198 */
3199 intel_complete_page_flips(dev);
3200
3201 /* no reset support for gen2 */
3202 if (IS_GEN2(dev))
3203 return;
3204
3205 /* reset doesn't touch the display */
3206 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3207 /*
3208 * Flips in the rings have been nuked by the reset,
3209 * so update the base address of all primary
3210 * planes to the the last fb to make sure we're
3211 * showing the correct fb after a reset.
3212 */
3213 intel_update_primary_planes(dev);
3214 return;
3215 }
3216
3217 /*
3218 * The display has been reset as well,
3219 * so need a full re-initialization.
3220 */
3221 intel_runtime_pm_disable_interrupts(dev_priv);
3222 intel_runtime_pm_enable_interrupts(dev_priv);
3223
3224 intel_modeset_init_hw(dev);
3225
3226 spin_lock_irq(&dev_priv->irq_lock);
3227 if (dev_priv->display.hpd_irq_setup)
3228 dev_priv->display.hpd_irq_setup(dev);
3229 spin_unlock_irq(&dev_priv->irq_lock);
3230
3231 intel_modeset_setup_hw_state(dev, true);
3232
3233 intel_hpd_init(dev_priv);
3234
3235 drm_modeset_unlock_all(dev);
3236}
3237
14667a4b
CW		 3238static int
3239intel_finish_fb(struct drm_framebuffer *old_fb)
3240{
2ff8fde1 3241 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3242 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3243 bool was_interruptible = dev_priv->mm.interruptible;
3244 int ret;
3245
14667a4b
CW		 3246 /* Big Hammer, we also need to ensure that any pending
3247 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3248 * current scanout is retired before unpinning the old
3249 * framebuffer.
3250 *
3251 * This should only fail upon a hung GPU, in which case we
3252 * can safely continue.
3253 */
3254 dev_priv->mm.interruptible = false;
3255 ret = i915_gem_object_finish_gpu(obj);
3256 dev_priv->mm.interruptible = was_interruptible;
3257
3258 return ret;
3259}
3260
7d5e3799
CW		 3261static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3262{
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3266 bool pending;
3267
3268 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3269 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3270 return false;
3271
5e2d7afc 3272 spin_lock_irq(&dev->event_lock);
7d5e3799 3273 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3274 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3275
3276 return pending;
3277}
3278
e30e8f75
GP		 3279static void intel_update_pipe_size(struct intel_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->base.dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 const struct drm_display_mode *adjusted_mode;
3284
3285 if (!i915.fastboot)
3286 return;
3287
3288 /*
3289 * Update pipe size and adjust fitter if needed: the reason for this is
3290 * that in compute_mode_changes we check the native mode (not the pfit
3291 * mode) to see if we can flip rather than do a full mode set. In the
3292 * fastboot case, we'll flip, but if we don't update the pipesrc and
3293 * pfit state, we'll end up with a big fb scanned out into the wrong
3294 * sized surface.
3295 *
3296 * To fix this properly, we need to hoist the checks up into
3297 * compute_mode_changes (or above), check the actual pfit state and
3298 * whether the platform allows pfit disable with pipe active, and only
3299 * then update the pipesrc and pfit state, even on the flip path.
3300 */
3301
6e3c9717 3302 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3303
3304 I915_WRITE(PIPESRC(crtc->pipe),
3305 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3306 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3307 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3308 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3309 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3310 I915_WRITE(PF_CTL(crtc->pipe), 0);
3311 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3312 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3313 }
6e3c9717
ACO		 3314 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3315 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3316}
3317
5e84e1a4
ZW		 3318static void intel_fdi_normal_train(struct drm_crtc *crtc)
3319{
3320 struct drm_device *dev = crtc->dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 int pipe = intel_crtc->pipe;
3324 u32 reg, temp;
3325
3326 /* enable normal train */
3327 reg = FDI_TX_CTL(pipe);
3328 temp = I915_READ(reg);
61e499bf 3329 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3332 } else {
3333 temp &= ~FDI_LINK_TRAIN_NONE;
3334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3335 }
5e84e1a4
ZW		 3336 I915_WRITE(reg, temp);
3337
3338 reg = FDI_RX_CTL(pipe);
3339 temp = I915_READ(reg);
3340 if (HAS_PCH_CPT(dev)) {
3341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3343 } else {
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_NONE;
3346 }
3347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3348
3349 /* wait one idle pattern time */
3350 POSTING_READ(reg);
3351 udelay(1000);
357555c0
JB		 3352
3353 /* IVB wants error correction enabled */
3354 if (IS_IVYBRIDGE(dev))
3355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3356 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3357}
3358
8db9d77b
ZW		 3359/* The FDI link training functions for ILK/Ibexpeak. */
3360static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3361{
3362 struct drm_device *dev = crtc->dev;
3363 struct drm_i915_private *dev_priv = dev->dev_private;
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 int pipe = intel_crtc->pipe;
5eddb70b 3366 u32 reg, temp, tries;
8db9d77b 3367
1c8562f6 3368 /* FDI needs bits from pipe first */
0fc932b8 3369 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3370
e1a44743
AJ		 3371 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3372 for train result */
5eddb70b
CW		 3373 reg = FDI_RX_IMR(pipe);
3374 temp = I915_READ(reg);
e1a44743
AJ		 3375 temp &= ~FDI_RX_SYMBOL_LOCK;
3376 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3377 I915_WRITE(reg, temp);
3378 I915_READ(reg);
e1a44743
AJ		 3379 udelay(150);
3380
8db9d77b 3381 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3382 reg = FDI_TX_CTL(pipe);
3383 temp = I915_READ(reg);
627eb5a3 3384 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3385 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3386 temp &= ~FDI_LINK_TRAIN_NONE;
3387 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3388 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3389
5eddb70b
CW		 3390 reg = FDI_RX_CTL(pipe);
3391 temp = I915_READ(reg);
8db9d77b
ZW		 3392 temp &= ~FDI_LINK_TRAIN_NONE;
3393 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3395
3396 POSTING_READ(reg);
8db9d77b
ZW		 3397 udelay(150);
3398
5b2adf89 3399 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3400 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3401 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3402 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3403
5eddb70b 3404 reg = FDI_RX_IIR(pipe);
e1a44743 3405 for (tries = 0; tries < 5; tries++) {
5eddb70b 3406 temp = I915_READ(reg);
8db9d77b
ZW		 3407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3408
3409 if ((temp & FDI_RX_BIT_LOCK)) {
3410 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3411 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3412 break;
3413 }
8db9d77b 3414 }
e1a44743 3415 if (tries == 5)
5eddb70b 3416 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3417
3418 /* Train 2 */
5eddb70b
CW		 3419 reg = FDI_TX_CTL(pipe);
3420 temp = I915_READ(reg);
8db9d77b
ZW		 3421 temp &= ~FDI_LINK_TRAIN_NONE;
3422 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3423 I915_WRITE(reg, temp);
8db9d77b 3424
5eddb70b
CW		 3425 reg = FDI_RX_CTL(pipe);
3426 temp = I915_READ(reg);
8db9d77b
ZW		 3427 temp &= ~FDI_LINK_TRAIN_NONE;
3428 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3429 I915_WRITE(reg, temp);
8db9d77b 3430
5eddb70b
CW		 3431 POSTING_READ(reg);
3432 udelay(150);
8db9d77b 3433
5eddb70b 3434 reg = FDI_RX_IIR(pipe);
e1a44743 3435 for (tries = 0; tries < 5; tries++) {
5eddb70b 3436 temp = I915_READ(reg);
8db9d77b
ZW		 3437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3438
3439 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3440 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3441 DRM_DEBUG_KMS("FDI train 2 done.\n");
3442 break;
3443 }
8db9d77b 3444 }
e1a44743 3445 if (tries == 5)
5eddb70b 3446 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3447
3448 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3449
8db9d77b
ZW		 3450}
3451
0206e353 3452static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3453 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3454 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3456 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3457};
3458
3459/* The FDI link training functions for SNB/Cougarpoint. */
3460static void gen6_fdi_link_train(struct drm_crtc *crtc)
3461{
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 int pipe = intel_crtc->pipe;
fa37d39e 3466 u32 reg, temp, i, retry;
8db9d77b 3467
e1a44743
AJ		 3468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3469 for train result */
5eddb70b
CW		 3470 reg = FDI_RX_IMR(pipe);
3471 temp = I915_READ(reg);
e1a44743
AJ		 3472 temp &= ~FDI_RX_SYMBOL_LOCK;
3473 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3474 I915_WRITE(reg, temp);
3475
3476 POSTING_READ(reg);
e1a44743
AJ		 3477 udelay(150);
3478
8db9d77b 3479 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3480 reg = FDI_TX_CTL(pipe);
3481 temp = I915_READ(reg);
627eb5a3 3482 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3483 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_1;
3486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3487 /* SNB-B */
3488 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3489 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3490
d74cf324
DV		 3491 I915_WRITE(FDI_RX_MISC(pipe),
3492 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3493
5eddb70b
CW		 3494 reg = FDI_RX_CTL(pipe);
3495 temp = I915_READ(reg);
8db9d77b
ZW		 3496 if (HAS_PCH_CPT(dev)) {
3497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3498 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3499 } else {
3500 temp &= ~FDI_LINK_TRAIN_NONE;
3501 temp |= FDI_LINK_TRAIN_PATTERN_1;
3502 }
5eddb70b
CW		 3503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3504
3505 POSTING_READ(reg);
8db9d77b
ZW		 3506 udelay(150);
3507
0206e353 3508 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3509 reg = FDI_TX_CTL(pipe);
3510 temp = I915_READ(reg);
8db9d77b
ZW		 3511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3512 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3513 I915_WRITE(reg, temp);
3514
3515 POSTING_READ(reg);
8db9d77b
ZW		 3516 udelay(500);
3517
fa37d39e
SP		 3518 for (retry = 0; retry < 5; retry++) {
3519 reg = FDI_RX_IIR(pipe);
3520 temp = I915_READ(reg);
3521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3522 if (temp & FDI_RX_BIT_LOCK) {
3523 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3524 DRM_DEBUG_KMS("FDI train 1 done.\n");
3525 break;
3526 }
3527 udelay(50);
8db9d77b 3528 }
fa37d39e
SP		 3529 if (retry < 5)
3530 break;
8db9d77b
ZW		 3531 }
3532 if (i == 4)
5eddb70b 3533 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3534
3535 /* Train 2 */
5eddb70b
CW		 3536 reg = FDI_TX_CTL(pipe);
3537 temp = I915_READ(reg);
8db9d77b
ZW		 3538 temp &= ~FDI_LINK_TRAIN_NONE;
3539 temp |= FDI_LINK_TRAIN_PATTERN_2;
3540 if (IS_GEN6(dev)) {
3541 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3542 /* SNB-B */
3543 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3544 }
5eddb70b 3545 I915_WRITE(reg, temp);
8db9d77b 3546
5eddb70b
CW		 3547 reg = FDI_RX_CTL(pipe);
3548 temp = I915_READ(reg);
8db9d77b
ZW		 3549 if (HAS_PCH_CPT(dev)) {
3550 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3551 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3552 } else {
3553 temp &= ~FDI_LINK_TRAIN_NONE;
3554 temp |= FDI_LINK_TRAIN_PATTERN_2;
3555 }
5eddb70b
CW		 3556 I915_WRITE(reg, temp);
3557
3558 POSTING_READ(reg);
8db9d77b
ZW		 3559 udelay(150);
3560
0206e353 3561 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3562 reg = FDI_TX_CTL(pipe);
3563 temp = I915_READ(reg);
8db9d77b
ZW		 3564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3565 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3566 I915_WRITE(reg, temp);
3567
3568 POSTING_READ(reg);
8db9d77b
ZW		 3569 udelay(500);
3570
fa37d39e
SP		 3571 for (retry = 0; retry < 5; retry++) {
3572 reg = FDI_RX_IIR(pipe);
3573 temp = I915_READ(reg);
3574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3575 if (temp & FDI_RX_SYMBOL_LOCK) {
3576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3577 DRM_DEBUG_KMS("FDI train 2 done.\n");
3578 break;
3579 }
3580 udelay(50);
8db9d77b 3581 }
fa37d39e
SP		 3582 if (retry < 5)
3583 break;
8db9d77b
ZW		 3584 }
3585 if (i == 4)
5eddb70b 3586 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3587
3588 DRM_DEBUG_KMS("FDI train done.\n");
3589}
3590
357555c0
JB		 3591/* Manual link training for Ivy Bridge A0 parts */
3592static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3593{
3594 struct drm_device *dev = crtc->dev;
3595 struct drm_i915_private *dev_priv = dev->dev_private;
3596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3597 int pipe = intel_crtc->pipe;
139ccd3f 3598 u32 reg, temp, i, j;
357555c0
JB		 3599
3600 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3601 for train result */
3602 reg = FDI_RX_IMR(pipe);
3603 temp = I915_READ(reg);
3604 temp &= ~FDI_RX_SYMBOL_LOCK;
3605 temp &= ~FDI_RX_BIT_LOCK;
3606 I915_WRITE(reg, temp);
3607
3608 POSTING_READ(reg);
3609 udelay(150);
3610
01a415fd
DV		 3611 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3612 I915_READ(FDI_RX_IIR(pipe)));
3613
139ccd3f
JB		 3614 /* Try each vswing and preemphasis setting twice before moving on */
3615 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3616 /* disable first in case we need to retry */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3620 temp &= ~FDI_TX_ENABLE;
3621 I915_WRITE(reg, temp);
357555c0 3622
139ccd3f
JB		 3623 reg = FDI_RX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_LINK_TRAIN_AUTO;
3626 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3627 temp &= ~FDI_RX_ENABLE;
3628 I915_WRITE(reg, temp);
357555c0 3629
139ccd3f 3630 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3631 reg = FDI_TX_CTL(pipe);
3632 temp = I915_READ(reg);
139ccd3f 3633 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3634 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3635 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3636 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3637 temp |= snb_b_fdi_train_param[j/2];
3638 temp |= FDI_COMPOSITE_SYNC;
3639 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3640
139ccd3f
JB		 3641 I915_WRITE(FDI_RX_MISC(pipe),
3642 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3643
139ccd3f 3644 reg = FDI_RX_CTL(pipe);
357555c0 3645 temp = I915_READ(reg);
139ccd3f
JB		 3646 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3647 temp |= FDI_COMPOSITE_SYNC;
3648 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3649
139ccd3f
JB		 3650 POSTING_READ(reg);
3651 udelay(1); /* should be 0.5us */
357555c0 3652
139ccd3f
JB		 3653 for (i = 0; i < 4; i++) {
3654 reg = FDI_RX_IIR(pipe);
3655 temp = I915_READ(reg);
3656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3657
139ccd3f
JB		 3658 if (temp & FDI_RX_BIT_LOCK ||
3659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3661 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3662 i);
3663 break;
3664 }
3665 udelay(1); /* should be 0.5us */
3666 }
3667 if (i == 4) {
3668 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3669 continue;
3670 }
357555c0 3671
139ccd3f 3672 /* Train 2 */
357555c0
JB		 3673 reg = FDI_TX_CTL(pipe);
3674 temp = I915_READ(reg);
139ccd3f
JB		 3675 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3676 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3677 I915_WRITE(reg, temp);
3678
3679 reg = FDI_RX_CTL(pipe);
3680 temp = I915_READ(reg);
3681 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3682 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3683 I915_WRITE(reg, temp);
3684
3685 POSTING_READ(reg);
139ccd3f 3686 udelay(2); /* should be 1.5us */
357555c0 3687
139ccd3f
JB		 3688 for (i = 0; i < 4; i++) {
3689 reg = FDI_RX_IIR(pipe);
3690 temp = I915_READ(reg);
3691 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3692
139ccd3f
JB		 3693 if (temp & FDI_RX_SYMBOL_LOCK ||
3694 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3695 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3696 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3697 i);
3698 goto train_done;
3699 }
3700 udelay(2); /* should be 1.5us */
357555c0 3701 }
139ccd3f
JB		 3702 if (i == 4)
3703 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3704 }
357555c0 3705
139ccd3f 3706train_done:
357555c0
JB		 3707 DRM_DEBUG_KMS("FDI train done.\n");
3708}
3709
88cefb6c 3710static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3711{
88cefb6c 3712 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3713 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3714 int pipe = intel_crtc->pipe;
5eddb70b 3715 u32 reg, temp;
79e53945 3716
c64e311e 3717
c98e9dcf 3718 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3719 reg = FDI_RX_CTL(pipe);
3720 temp = I915_READ(reg);
627eb5a3 3721 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3722 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3723 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3724 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3725
3726 POSTING_READ(reg);
c98e9dcf
JB		 3727 udelay(200);
3728
3729 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3730 temp = I915_READ(reg);
3731 I915_WRITE(reg, temp | FDI_PCDCLK);
3732
3733 POSTING_READ(reg);
c98e9dcf
JB		 3734 udelay(200);
3735
20749730
PZ		 3736 /* Enable CPU FDI TX PLL, always on for Ironlake */
3737 reg = FDI_TX_CTL(pipe);
3738 temp = I915_READ(reg);
3739 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3740 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3741
20749730
PZ		 3742 POSTING_READ(reg);
3743 udelay(100);
6be4a607 3744 }
0e23b99d
JB		 3745}
3746
88cefb6c
DV		 3747static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3748{
3749 struct drm_device *dev = intel_crtc->base.dev;
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 int pipe = intel_crtc->pipe;
3752 u32 reg, temp;
3753
3754 /* Switch from PCDclk to Rawclk */
3755 reg = FDI_RX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3758
3759 /* Disable CPU FDI TX PLL */
3760 reg = FDI_TX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3763
3764 POSTING_READ(reg);
3765 udelay(100);
3766
3767 reg = FDI_RX_CTL(pipe);
3768 temp = I915_READ(reg);
3769 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3770
3771 /* Wait for the clocks to turn off. */
3772 POSTING_READ(reg);
3773 udelay(100);
3774}
3775
0fc932b8
JB		 3776static void ironlake_fdi_disable(struct drm_crtc *crtc)
3777{
3778 struct drm_device *dev = crtc->dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3781 int pipe = intel_crtc->pipe;
3782 u32 reg, temp;
3783
3784 /* disable CPU FDI tx and PCH FDI rx */
3785 reg = FDI_TX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3788 POSTING_READ(reg);
3789
3790 reg = FDI_RX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 temp &= ~(0x7 << 16);
dfd07d72 3793 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3794 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3800 if (HAS_PCH_IBX(dev))
6f06ce18 3801 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3802
3803 /* still set train pattern 1 */
3804 reg = FDI_TX_CTL(pipe);
3805 temp = I915_READ(reg);
3806 temp &= ~FDI_LINK_TRAIN_NONE;
3807 temp |= FDI_LINK_TRAIN_PATTERN_1;
3808 I915_WRITE(reg, temp);
3809
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 if (HAS_PCH_CPT(dev)) {
3813 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3814 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3815 } else {
3816 temp &= ~FDI_LINK_TRAIN_NONE;
3817 temp |= FDI_LINK_TRAIN_PATTERN_1;
3818 }
3819 /* BPC in FDI rx is consistent with that in PIPECONF */
3820 temp &= ~(0x07 << 16);
dfd07d72 3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3822 I915_WRITE(reg, temp);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826}
3827
5dce5b93
CW		 3828bool intel_has_pending_fb_unpin(struct drm_device *dev)
3829{
3830 struct intel_crtc *crtc;
3831
3832 /* Note that we don't need to be called with mode_config.lock here
3833 * as our list of CRTC objects is static for the lifetime of the
3834 * device and so cannot disappear as we iterate. Similarly, we can
3835 * happily treat the predicates as racy, atomic checks as userspace
3836 * cannot claim and pin a new fb without at least acquring the
3837 * struct_mutex and so serialising with us.
3838 */
d3fcc808 3839 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3840 if (atomic_read(&crtc->unpin_work_count) == 0)
3841 continue;
3842
3843 if (crtc->unpin_work)
3844 intel_wait_for_vblank(dev, crtc->pipe);
3845
3846 return true;
3847 }
3848
3849 return false;
3850}
3851
d6bbafa1
CW		 3852static void page_flip_completed(struct intel_crtc *intel_crtc)
3853{
3854 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3855 struct intel_unpin_work *work = intel_crtc->unpin_work;
3856
3857 /* ensure that the unpin work is consistent wrt ->pending. */
3858 smp_rmb();
3859 intel_crtc->unpin_work = NULL;
3860
3861 if (work->event)
3862 drm_send_vblank_event(intel_crtc->base.dev,
3863 intel_crtc->pipe,
3864 work->event);
3865
3866 drm_crtc_vblank_put(&intel_crtc->base);
3867
3868 wake_up_all(&dev_priv->pending_flip_queue);
3869 queue_work(dev_priv->wq, &work->work);
3870
3871 trace_i915_flip_complete(intel_crtc->plane,
3872 work->pending_flip_obj);
3873}
3874
46a55d30 3875void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3876{
0f91128d 3877 struct drm_device *dev = crtc->dev;
5bb61643 3878 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3879
2c10d571 3880 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3881 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3882 !intel_crtc_has_pending_flip(crtc),
3883 60*HZ) == 0)) {
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3885
5e2d7afc 3886 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3887 if (intel_crtc->unpin_work) {
3888 WARN_ONCE(1, "Removing stuck page flip\n");
3889 page_flip_completed(intel_crtc);
3890 }
5e2d7afc 3891 spin_unlock_irq(&dev->event_lock);
9c787942 3892 }
5bb61643 3893
975d568a
CW		 3894 if (crtc->primary->fb) {
3895 mutex_lock(&dev->struct_mutex);
3896 intel_finish_fb(crtc->primary->fb);
3897 mutex_unlock(&dev->struct_mutex);
3898 }
e6c3a2a6
CW		 3899}
3900
e615efe4
ED		 3901/* Program iCLKIP clock to the desired frequency */
3902static void lpt_program_iclkip(struct drm_crtc *crtc)
3903{
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3906 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3908 u32 temp;
3909
09153000
DV		 3910 mutex_lock(&dev_priv->dpio_lock);
3911
e615efe4
ED		 3912 /* It is necessary to ungate the pixclk gate prior to programming
3913 * the divisors, and gate it back when it is done.
3914 */
3915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3916
3917 /* Disable SSCCTL */
3918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3920 SBI_SSCCTL_DISABLE,
3921 SBI_ICLK);
e615efe4
ED		 3922
3923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3924 if (clock == 20000) {
e615efe4
ED		 3925 auxdiv = 1;
3926 divsel = 0x41;
3927 phaseinc = 0x20;
3928 } else {
3929 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3930 * but the adjusted_mode->crtc_clock in in KHz. To get the
3931 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3932 * convert the virtual clock precision to KHz here for higher
3933 * precision.
3934 */
3935 u32 iclk_virtual_root_freq = 172800 * 1000;
3936 u32 iclk_pi_range = 64;
3937 u32 desired_divisor, msb_divisor_value, pi_value;
3938
12d7ceed 3939 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3940 msb_divisor_value = desired_divisor / iclk_pi_range;
3941 pi_value = desired_divisor % iclk_pi_range;
3942
3943 auxdiv = 0;
3944 divsel = msb_divisor_value - 2;
3945 phaseinc = pi_value;
3946 }
3947
3948 /* This should not happen with any sane values */
3949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3953
3954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3955 clock,
e615efe4
ED		 3956 auxdiv,
3957 divsel,
3958 phasedir,
3959 phaseinc);
3960
3961 /* Program SSCDIVINTPHASE6 */
988d6ee8 3962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3970
3971 /* Program SSCAUXDIV */
988d6ee8 3972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3976
3977 /* Enable modulator and associated divider */
988d6ee8 3978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3979 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3981
3982 /* Wait for initialization time */
3983 udelay(24);
3984
3985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3986
3987 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3988}
3989
275f01b2
DV		 3990static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3991 enum pipe pch_transcoder)
3992{
3993 struct drm_device *dev = crtc->base.dev;
3994 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3995 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3996
3997 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3998 I915_READ(HTOTAL(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4000 I915_READ(HBLANK(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4002 I915_READ(HSYNC(cpu_transcoder)));
4003
4004 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4005 I915_READ(VTOTAL(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4007 I915_READ(VBLANK(cpu_transcoder)));
4008 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4009 I915_READ(VSYNC(cpu_transcoder)));
4010 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4011 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4012}
4013
003632d9 4014static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4015{
4016 struct drm_i915_private *dev_priv = dev->dev_private;
4017 uint32_t temp;
4018
4019 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4020 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4021 return;
4022
4023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4025
003632d9
ACO		 4026 temp &= ~FDI_BC_BIFURCATION_SELECT;
4027 if (enable)
4028 temp |= FDI_BC_BIFURCATION_SELECT;
4029
4030 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4031 I915_WRITE(SOUTH_CHICKEN1, temp);
4032 POSTING_READ(SOUTH_CHICKEN1);
4033}
4034
4035static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4036{
4037 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4038
4039 switch (intel_crtc->pipe) {
4040 case PIPE_A:
4041 break;
4042 case PIPE_B:
6e3c9717 4043 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4044 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4045 else
003632d9 4046 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4047
4048 break;
4049 case PIPE_C:
003632d9 4050 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4051
4052 break;
4053 default:
4054 BUG();
4055 }
4056}
4057
f67a559d
JB		 4058/*
4059 * Enable PCH resources required for PCH ports:
4060 * - PCH PLLs
4061 * - FDI training & RX/TX
4062 * - update transcoder timings
4063 * - DP transcoding bits
4064 * - transcoder
4065 */
4066static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4067{
4068 struct drm_device *dev = crtc->dev;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4071 int pipe = intel_crtc->pipe;
ee7b9f93 4072 u32 reg, temp;
2c07245f 4073
ab9412ba 4074 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4075
1fbc0d78
DV		 4076 if (IS_IVYBRIDGE(dev))
4077 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4078
cd986abb
DV		 4079 /* Write the TU size bits before fdi link training, so that error
4080 * detection works. */
4081 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4082 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4083
c98e9dcf 4084 /* For PCH output, training FDI link */
674cf967 4085 dev_priv->display.fdi_link_train(crtc);
2c07245f 4086
3ad8a208
DV		 4087 /* We need to program the right clock selection before writing the pixel
4088 * mutliplier into the DPLL. */
303b81e0 4089 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4090 u32 sel;
4b645f14 4091
c98e9dcf 4092 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4093 temp |= TRANS_DPLL_ENABLE(pipe);
4094 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4095 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4096 temp |= sel;
4097 else
4098 temp &= ~sel;
c98e9dcf 4099 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4100 }
5eddb70b 4101
3ad8a208
DV		 4102 /* XXX: pch pll's can be enabled any time before we enable the PCH
4103 * transcoder, and we actually should do this to not upset any PCH
4104 * transcoder that already use the clock when we share it.
4105 *
4106 * Note that enable_shared_dpll tries to do the right thing, but
4107 * get_shared_dpll unconditionally resets the pll - we need that to have
4108 * the right LVDS enable sequence. */
85b3894f 4109 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4110
d9b6cb56
JB		 4111 /* set transcoder timing, panel must allow it */
4112 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4113 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4114
303b81e0 4115 intel_fdi_normal_train(crtc);
5e84e1a4 4116
c98e9dcf 4117 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4118 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4119 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4120 reg = TRANS_DP_CTL(pipe);
4121 temp = I915_READ(reg);
4122 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4123 TRANS_DP_SYNC_MASK |
4124 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4125 temp |= (TRANS_DP_OUTPUT_ENABLE |
4126 TRANS_DP_ENH_FRAMING);
9325c9f0 4127 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4128
4129 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4130 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4131 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4132 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4133
4134 switch (intel_trans_dp_port_sel(crtc)) {
4135 case PCH_DP_B:
5eddb70b 4136 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4137 break;
4138 case PCH_DP_C:
5eddb70b 4139 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4140 break;
4141 case PCH_DP_D:
5eddb70b 4142 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4143 break;
4144 default:
e95d41e1 4145 BUG();
32f9d658 4146 }
2c07245f 4147
5eddb70b 4148 I915_WRITE(reg, temp);
6be4a607 4149 }
b52eb4dc 4150
b8a4f404 4151 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4152}
4153
1507e5bd
PZ		 4154static void lpt_pch_enable(struct drm_crtc *crtc)
4155{
4156 struct drm_device *dev = crtc->dev;
4157 struct drm_i915_private *dev_priv = dev->dev_private;
4158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4160
ab9412ba 4161 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4162
8c52b5e8 4163 lpt_program_iclkip(crtc);
1507e5bd 4164
0540e488 4165 /* Set transcoder timing. */
275f01b2 4166 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4167
937bb610 4168 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4169}
4170
716c2e55 4171void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4172{
e2b78267 4173 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4174
4175 if (pll == NULL)
4176 return;
4177
3e369b76 4178 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4179 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4180 return;
4181 }
4182
3e369b76
ACO		 4183 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4184 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4185 WARN_ON(pll->on);
4186 WARN_ON(pll->active);
4187 }
4188
6e3c9717 4189 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4190}
4191
190f68c5
ACO		 4192struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4193 struct intel_crtc_state *crtc_state)
ee7b9f93 4194{
e2b78267 4195 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4196 struct intel_shared_dpll *pll;
e2b78267 4197 enum intel_dpll_id i;
ee7b9f93 4198
98b6bd99
DV		 4199 if (HAS_PCH_IBX(dev_priv->dev)) {
4200 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4201 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4202 pll = &dev_priv->shared_dplls[i];
98b6bd99 4203
46edb027
DV		 4204 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4205 crtc->base.base.id, pll->name);
98b6bd99 4206
8bd31e67 4207 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4208
98b6bd99
DV		 4209 goto found;
4210 }
4211
e72f9fbf
DV		 4212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4213 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4214
4215 /* Only want to check enabled timings first */
8bd31e67 4216 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4217 continue;
4218
190f68c5 4219 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4220 &pll->new_config->hw_state,
4221 sizeof(pll->new_config->hw_state)) == 0) {
4222 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4223 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4224 pll->new_config->crtc_mask,
4225 pll->active);
ee7b9f93
JB		 4226 goto found;
4227 }
4228 }
4229
4230 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4232 pll = &dev_priv->shared_dplls[i];
8bd31e67 4233 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4234 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4235 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4236 goto found;
4237 }
4238 }
4239
4240 return NULL;
4241
4242found:
8bd31e67 4243 if (pll->new_config->crtc_mask == 0)
190f68c5 4244 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4245
190f68c5 4246 crtc_state->shared_dpll = i;
46edb027
DV		 4247 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4248 pipe_name(crtc->pipe));
ee7b9f93 4249
8bd31e67 4250 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4251
ee7b9f93
JB		 4252 return pll;
4253}
4254
8bd31e67
ACO		 4255/**
4256 * intel_shared_dpll_start_config - start a new PLL staged config
4257 * @dev_priv: DRM device
4258 * @clear_pipes: mask of pipes that will have their PLLs freed
4259 *
4260 * Starts a new PLL staged config, copying the current config but
4261 * releasing the references of pipes specified in clear_pipes.
4262 */
4263static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4264 unsigned clear_pipes)
4265{
4266 struct intel_shared_dpll *pll;
4267 enum intel_dpll_id i;
4268
4269 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4270 pll = &dev_priv->shared_dplls[i];
4271
4272 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4273 GFP_KERNEL);
4274 if (!pll->new_config)
4275 goto cleanup;
4276
4277 pll->new_config->crtc_mask &= ~clear_pipes;
4278 }
4279
4280 return 0;
4281
4282cleanup:
4283 while (--i >= 0) {
4284 pll = &dev_priv->shared_dplls[i];
f354d733 4285 kfree(pll->new_config);
8bd31e67
ACO		 4286 pll->new_config = NULL;
4287 }
4288
4289 return -ENOMEM;
4290}
4291
4292static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4293{
4294 struct intel_shared_dpll *pll;
4295 enum intel_dpll_id i;
4296
4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
4299
4300 WARN_ON(pll->new_config == &pll->config);
4301
4302 pll->config = *pll->new_config;
4303 kfree(pll->new_config);
4304 pll->new_config = NULL;
4305 }
4306}
4307
4308static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4309{
4310 struct intel_shared_dpll *pll;
4311 enum intel_dpll_id i;
4312
4313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314 pll = &dev_priv->shared_dplls[i];
4315
4316 WARN_ON(pll->new_config == &pll->config);
4317
4318 kfree(pll->new_config);
4319 pll->new_config = NULL;
4320 }
4321}
4322
a1520318 4323static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4324{
4325 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4326 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4327 u32 temp;
4328
4329 temp = I915_READ(dslreg);
4330 udelay(500);
4331 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4332 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4333 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4334 }
4335}
4336
a1b2278e
CK		 4337/**
4338 * skl_update_scaler_users - Stages update to crtc's scaler state
4339 * @intel_crtc: crtc
4340 * @crtc_state: crtc_state
4341 * @plane: plane (NULL indicates crtc is requesting update)
4342 * @plane_state: plane's state
4343 * @force_detach: request unconditional detachment of scaler
4344 *
4345 * This function updates scaler state for requested plane or crtc.
4346 * To request scaler usage update for a plane, caller shall pass plane pointer.
4347 * To request scaler usage update for crtc, caller shall pass plane pointer
4348 * as NULL.
4349 *
4350 * Return
4351 * 0 - scaler_usage updated successfully
4352 * error - requested scaling cannot be supported or other error condition
4353 */
4354int
4355skl_update_scaler_users(
4356 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4357 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4358 int force_detach)
4359{
4360 int need_scaling;
4361 int idx;
4362 int src_w, src_h, dst_w, dst_h;
4363 int *scaler_id;
4364 struct drm_framebuffer *fb;
4365 struct intel_crtc_scaler_state *scaler_state;
4366
4367 if (!intel_crtc || !crtc_state)
4368 return 0;
4369
4370 scaler_state = &crtc_state->scaler_state;
4371
4372 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4373 fb = intel_plane ? plane_state->base.fb : NULL;
4374
4375 if (intel_plane) {
4376 src_w = drm_rect_width(&plane_state->src) >> 16;
4377 src_h = drm_rect_height(&plane_state->src) >> 16;
4378 dst_w = drm_rect_width(&plane_state->dst);
4379 dst_h = drm_rect_height(&plane_state->dst);
4380 scaler_id = &plane_state->scaler_id;
4381 } else {
4382 struct drm_display_mode *adjusted_mode =
4383 &crtc_state->base.adjusted_mode;
4384 src_w = crtc_state->pipe_src_w;
4385 src_h = crtc_state->pipe_src_h;
4386 dst_w = adjusted_mode->hdisplay;
4387 dst_h = adjusted_mode->vdisplay;
4388 scaler_id = &scaler_state->scaler_id;
4389 }
4390 need_scaling = (src_w != dst_w || src_h != dst_h);
4391
4392 /*
4393 * if plane is being disabled or scaler is no more required or force detach
4394 * - free scaler binded to this plane/crtc
4395 * - in order to do this, update crtc->scaler_usage
4396 *
4397 * Here scaler state in crtc_state is set free so that
4398 * scaler can be assigned to other user. Actual register
4399 * update to free the scaler is done in plane/panel-fit programming.
4400 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4401 */
4402 if (force_detach || !need_scaling || (intel_plane &&
4403 (!fb || !plane_state->visible))) {
4404 if (*scaler_id >= 0) {
4405 scaler_state->scaler_users &= ~(1 << idx);
4406 scaler_state->scalers[*scaler_id].in_use = 0;
4407
4408 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4409 "crtc_state = %p scaler_users = 0x%x\n",
4410 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4411 intel_plane ? intel_plane->base.base.id :
4412 intel_crtc->base.base.id, crtc_state,
4413 scaler_state->scaler_users);
4414 *scaler_id = -1;
4415 }
4416 return 0;
4417 }
4418
4419 /* range checks */
4420 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4421 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4422
4423 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4424 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4425 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4426 "size is out of scaler range\n",
4427 intel_plane ? "PLANE" : "CRTC",
4428 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4429 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4430 return -EINVAL;
4431 }
4432
4433 /* check colorkey */
4434 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4435 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4436 intel_plane->base.base.id);
4437 return -EINVAL;
4438 }
4439
4440 /* Check src format */
4441 if (intel_plane) {
4442 switch (fb->pixel_format) {
4443 case DRM_FORMAT_RGB565:
4444 case DRM_FORMAT_XBGR8888:
4445 case DRM_FORMAT_XRGB8888:
4446 case DRM_FORMAT_ABGR8888:
4447 case DRM_FORMAT_ARGB8888:
4448 case DRM_FORMAT_XRGB2101010:
4449 case DRM_FORMAT_ARGB2101010:
4450 case DRM_FORMAT_XBGR2101010:
4451 case DRM_FORMAT_ABGR2101010:
4452 case DRM_FORMAT_YUYV:
4453 case DRM_FORMAT_YVYU:
4454 case DRM_FORMAT_UYVY:
4455 case DRM_FORMAT_VYUY:
4456 break;
4457 default:
4458 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4459 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4460 return -EINVAL;
4461 }
4462 }
4463
4464 /* mark this plane as a scaler user in crtc_state */
4465 scaler_state->scaler_users |= (1 << idx);
4466 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4467 "crtc_state = %p scaler_users = 0x%x\n",
4468 intel_plane ? "PLANE" : "CRTC",
4469 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4470 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4471 return 0;
4472}
4473
4474static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4475{
4476 struct drm_device *dev = crtc->base.dev;
4477 struct drm_i915_private *dev_priv = dev->dev_private;
4478 int pipe = crtc->pipe;
a1b2278e
CK		 4479 struct intel_crtc_scaler_state *scaler_state =
4480 &crtc->config->scaler_state;
4481
4482 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4483
4484 /* To update pfit, first update scaler state */
4485 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4486 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4487 skl_detach_scalers(crtc);
4488 if (!enable)
4489 return;
bd2e244f 4490
6e3c9717 4491 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4492 int id;
4493
4494 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4495 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4496 return;
4497 }
4498
4499 id = scaler_state->scaler_id;
4500 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4501 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4502 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4503 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4504
4505 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4506 }
4507}
4508
b074cec8
JB		 4509static void ironlake_pfit_enable(struct intel_crtc *crtc)
4510{
4511 struct drm_device *dev = crtc->base.dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 int pipe = crtc->pipe;
4514
6e3c9717 4515 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4516 /* Force use of hard-coded filter coefficients
4517 * as some pre-programmed values are broken,
4518 * e.g. x201.
4519 */
4520 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4521 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4522 PF_PIPE_SEL_IVB(pipe));
4523 else
4524 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4525 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4526 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4527 }
4528}
4529
4a3b8769 4530static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4531{
4532 struct drm_device *dev = crtc->dev;
4533 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4534 struct drm_plane *plane;
bb53d4ae
VS		 4535 struct intel_plane *intel_plane;
4536
af2b653b
MR		 4537 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4538 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4539 if (intel_plane->pipe == pipe)
4540 intel_plane_restore(&intel_plane->base);
af2b653b 4541 }
bb53d4ae
VS		 4542}
4543
0d703d4e
MR		 4544/*
4545 * Disable a plane internally without actually modifying the plane's state.
4546 * This will allow us to easily restore the plane later by just reprogramming
4547 * its state.
4548 */
4549static void disable_plane_internal(struct drm_plane *plane)
4550{
4551 struct intel_plane *intel_plane = to_intel_plane(plane);
4552 struct drm_plane_state *state =
4553 plane->funcs->atomic_duplicate_state(plane);
4554 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4555
4556 intel_state->visible = false;
4557 intel_plane->commit_plane(plane, intel_state);
4558
4559 intel_plane_destroy_state(plane, state);
4560}
4561
4a3b8769 4562static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4563{
4564 struct drm_device *dev = crtc->dev;
4565 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4566 struct drm_plane *plane;
bb53d4ae
VS		 4567 struct intel_plane *intel_plane;
4568
af2b653b
MR		 4569 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4570 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4571 if (plane->fb && intel_plane->pipe == pipe)
4572 disable_plane_internal(plane);
af2b653b 4573 }
bb53d4ae
VS		 4574}
4575
20bc8673 4576void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4577{
cea165c3
VS		 4578 struct drm_device *dev = crtc->base.dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4580
6e3c9717 4581 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4582 return;
4583
cea165c3
VS		 4584 /* We can only enable IPS after we enable a plane and wait for a vblank */
4585 intel_wait_for_vblank(dev, crtc->pipe);
4586
d77e4531 4587 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4588 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4589 mutex_lock(&dev_priv->rps.hw_lock);
4590 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4591 mutex_unlock(&dev_priv->rps.hw_lock);
4592 /* Quoting Art Runyan: "its not safe to expect any particular
4593 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4594 * mailbox." Moreover, the mailbox may return a bogus state,
4595 * so we need to just enable it and continue on.
2a114cc1
BW		 4596 */
4597 } else {
4598 I915_WRITE(IPS_CTL, IPS_ENABLE);
4599 /* The bit only becomes 1 in the next vblank, so this wait here
4600 * is essentially intel_wait_for_vblank. If we don't have this
4601 * and don't wait for vblanks until the end of crtc_enable, then
4602 * the HW state readout code will complain that the expected
4603 * IPS_CTL value is not the one we read. */
4604 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4605 DRM_ERROR("Timed out waiting for IPS enable\n");
4606 }
d77e4531
PZ		 4607}
4608
20bc8673 4609void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4610{
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613
6e3c9717 4614 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4615 return;
4616
4617 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4618 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4619 mutex_lock(&dev_priv->rps.hw_lock);
4620 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4621 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4622 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4623 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4624 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4625 } else {
2a114cc1 4626 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4627 POSTING_READ(IPS_CTL);
4628 }
d77e4531
PZ		 4629
4630 /* We need to wait for a vblank before we can disable the plane. */
4631 intel_wait_for_vblank(dev, crtc->pipe);
4632}
4633
4634/** Loads the palette/gamma unit for the CRTC with the prepared values */
4635static void intel_crtc_load_lut(struct drm_crtc *crtc)
4636{
4637 struct drm_device *dev = crtc->dev;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4640 enum pipe pipe = intel_crtc->pipe;
4641 int palreg = PALETTE(pipe);
4642 int i;
4643 bool reenable_ips = false;
4644
4645 /* The clocks have to be on to load the palette. */
83d65738 4646 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4647 return;
4648
4649 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4650 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4651 assert_dsi_pll_enabled(dev_priv);
4652 else
4653 assert_pll_enabled(dev_priv, pipe);
4654 }
4655
4656 /* use legacy palette for Ironlake */
7a1db49a 4657 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4658 palreg = LGC_PALETTE(pipe);
4659
4660 /* Workaround : Do not read or write the pipe palette/gamma data while
4661 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4662 */
6e3c9717 4663 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4664 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4665 GAMMA_MODE_MODE_SPLIT)) {
4666 hsw_disable_ips(intel_crtc);
4667 reenable_ips = true;
4668 }
4669
4670 for (i = 0; i < 256; i++) {
4671 I915_WRITE(palreg + 4 * i,
4672 (intel_crtc->lut_r[i] << 16) |
4673 (intel_crtc->lut_g[i] << 8) |
4674 intel_crtc->lut_b[i]);
4675 }
4676
4677 if (reenable_ips)
4678 hsw_enable_ips(intel_crtc);
4679}
4680
d3eedb1a
VS		 4681static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4682{
4683 if (!enable && intel_crtc->overlay) {
4684 struct drm_device *dev = intel_crtc->base.dev;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4686
4687 mutex_lock(&dev->struct_mutex);
4688 dev_priv->mm.interruptible = false;
4689 (void) intel_overlay_switch_off(intel_crtc->overlay);
4690 dev_priv->mm.interruptible = true;
4691 mutex_unlock(&dev->struct_mutex);
4692 }
4693
4694 /* Let userspace switch the overlay on again. In most cases userspace
4695 * has to recompute where to put it anyway.
4696 */
4697}
4698
d3eedb1a 4699static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4700{
4701 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703 int pipe = intel_crtc->pipe;
a5c4d7bc 4704
fdd508a6 4705 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4706 intel_enable_sprite_planes(crtc);
a5c4d7bc 4707 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4708 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4709
4710 hsw_enable_ips(intel_crtc);
4711
4712 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4713 intel_fbc_update(dev);
a5c4d7bc 4714 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4715
4716 /*
4717 * FIXME: Once we grow proper nuclear flip support out of this we need
4718 * to compute the mask of flip planes precisely. For the time being
4719 * consider this a flip from a NULL plane.
4720 */
4721 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4722}
4723
d3eedb1a 4724static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4725{
4726 struct drm_device *dev = crtc->dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4729 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4730
4731 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4732
e35fef21 4733 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4734 intel_fbc_disable(dev);
a5c4d7bc
VS		 4735
4736 hsw_disable_ips(intel_crtc);
4737
d3eedb1a 4738 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4739 intel_crtc_update_cursor(crtc, false);
4a3b8769 4740 intel_disable_sprite_planes(crtc);
fdd508a6 4741 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4742
f99d7069
DV		 4743 /*
4744 * FIXME: Once we grow proper nuclear flip support out of this we need
4745 * to compute the mask of flip planes precisely. For the time being
4746 * consider this a flip to a NULL plane.
4747 */
4748 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4749}
4750
f67a559d
JB		 4751static void ironlake_crtc_enable(struct drm_crtc *crtc)
4752{
4753 struct drm_device *dev = crtc->dev;
4754 struct drm_i915_private *dev_priv = dev->dev_private;
4755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4756 struct intel_encoder *encoder;
f67a559d 4757 int pipe = intel_crtc->pipe;
f67a559d 4758
83d65738 4759 WARN_ON(!crtc->state->enable);
08a48469 4760
f67a559d
JB		 4761 if (intel_crtc->active)
4762 return;
4763
6e3c9717 4764 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4765 intel_prepare_shared_dpll(intel_crtc);
4766
6e3c9717 4767 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4768 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4769
4770 intel_set_pipe_timings(intel_crtc);
4771
6e3c9717 4772 if (intel_crtc->config->has_pch_encoder) {
29407aab 4773 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4774 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4775 }
4776
4777 ironlake_set_pipeconf(crtc);
4778
f67a559d 4779 intel_crtc->active = true;
8664281b 4780
a72e4c9f
DV		 4781 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4782 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4783
f6736a1a 4784 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4785 if (encoder->pre_enable)
4786 encoder->pre_enable(encoder);
f67a559d 4787
6e3c9717 4788 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4789 /* Note: FDI PLL enabling _must_ be done before we enable the
4790 * cpu pipes, hence this is separate from all the other fdi/pch
4791 * enabling. */
88cefb6c 4792 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4793 } else {
4794 assert_fdi_tx_disabled(dev_priv, pipe);
4795 assert_fdi_rx_disabled(dev_priv, pipe);
4796 }
f67a559d 4797
b074cec8 4798 ironlake_pfit_enable(intel_crtc);
f67a559d 4799
9c54c0dd
JB		 4800 /*
4801 * On ILK+ LUT must be loaded before the pipe is running but with
4802 * clocks enabled
4803 */
4804 intel_crtc_load_lut(crtc);
4805
f37fcc2a 4806 intel_update_watermarks(crtc);
e1fdc473 4807 intel_enable_pipe(intel_crtc);
f67a559d 4808
6e3c9717 4809 if (intel_crtc->config->has_pch_encoder)
f67a559d 4810 ironlake_pch_enable(crtc);
c98e9dcf 4811
f9b61ff6
DV		 4812 assert_vblank_disabled(crtc);
4813 drm_crtc_vblank_on(crtc);
4814
fa5c73b1
DV		 4815 for_each_encoder_on_crtc(dev, crtc, encoder)
4816 encoder->enable(encoder);
61b77ddd
DV		 4817
4818 if (HAS_PCH_CPT(dev))
a1520318 4819 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4820
d3eedb1a 4821 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4822}
4823
42db64ef
PZ		 4824/* IPS only exists on ULT machines and is tied to pipe A. */
4825static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4826{
f5adf94e 4827 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4828}
4829
e4916946
PZ		 4830/*
4831 * This implements the workaround described in the "notes" section of the mode
4832 * set sequence documentation. When going from no pipes or single pipe to
4833 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4834 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4835 */
4836static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4837{
4838 struct drm_device *dev = crtc->base.dev;
4839 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4840
4841 /* We want to get the other_active_crtc only if there's only 1 other
4842 * active crtc. */
d3fcc808 4843 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4844 if (!crtc_it->active || crtc_it == crtc)
4845 continue;
4846
4847 if (other_active_crtc)
4848 return;
4849
4850 other_active_crtc = crtc_it;
4851 }
4852 if (!other_active_crtc)
4853 return;
4854
4855 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4856 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4857}
4858
4f771f10
PZ		 4859static void haswell_crtc_enable(struct drm_crtc *crtc)
4860{
4861 struct drm_device *dev = crtc->dev;
4862 struct drm_i915_private *dev_priv = dev->dev_private;
4863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4864 struct intel_encoder *encoder;
4865 int pipe = intel_crtc->pipe;
4f771f10 4866
83d65738 4867 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4868
4869 if (intel_crtc->active)
4870 return;
4871
df8ad70c
DV		 4872 if (intel_crtc_to_shared_dpll(intel_crtc))
4873 intel_enable_shared_dpll(intel_crtc);
4874
6e3c9717 4875 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4876 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4877
4878 intel_set_pipe_timings(intel_crtc);
4879
6e3c9717
ACO		 4880 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4881 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4882 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4883 }
4884
6e3c9717 4885 if (intel_crtc->config->has_pch_encoder) {
229fca97 4886 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4887 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4888 }
4889
4890 haswell_set_pipeconf(crtc);
4891
4892 intel_set_pipe_csc(crtc);
4893
4f771f10 4894 intel_crtc->active = true;
8664281b 4895
a72e4c9f 4896 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4897 for_each_encoder_on_crtc(dev, crtc, encoder)
4898 if (encoder->pre_enable)
4899 encoder->pre_enable(encoder);
4900
6e3c9717 4901 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4902 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4903 true);
4fe9467d
ID		 4904 dev_priv->display.fdi_link_train(crtc);
4905 }
4906
1f544388 4907 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4908
ff6d9f55 4909 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4910 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4911 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4912 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4913 else
4914 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4915
4916 /*
4917 * On ILK+ LUT must be loaded before the pipe is running but with
4918 * clocks enabled
4919 */
4920 intel_crtc_load_lut(crtc);
4921
1f544388 4922 intel_ddi_set_pipe_settings(crtc);
8228c251 4923 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4924
f37fcc2a 4925 intel_update_watermarks(crtc);
e1fdc473 4926 intel_enable_pipe(intel_crtc);
42db64ef 4927
6e3c9717 4928 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4929 lpt_pch_enable(crtc);
4f771f10 4930
6e3c9717 4931 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4932 intel_ddi_set_vc_payload_alloc(crtc, true);
4933
f9b61ff6
DV		 4934 assert_vblank_disabled(crtc);
4935 drm_crtc_vblank_on(crtc);
4936
8807e55b 4937 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4938 encoder->enable(encoder);
8807e55b
JN		 4939 intel_opregion_notify_encoder(encoder, true);
4940 }
4f771f10 4941
e4916946
PZ		 4942 /* If we change the relative order between pipe/planes enabling, we need
4943 * to change the workaround. */
4944 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4945 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4946}
4947
3f8dce3a
DV		 4948static void ironlake_pfit_disable(struct intel_crtc *crtc)
4949{
4950 struct drm_device *dev = crtc->base.dev;
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 int pipe = crtc->pipe;
4953
4954 /* To avoid upsetting the power well on haswell only disable the pfit if
4955 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4956 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4957 I915_WRITE(PF_CTL(pipe), 0);
4958 I915_WRITE(PF_WIN_POS(pipe), 0);
4959 I915_WRITE(PF_WIN_SZ(pipe), 0);
4960 }
4961}
4962
6be4a607
JB		 4963static void ironlake_crtc_disable(struct drm_crtc *crtc)
4964{
4965 struct drm_device *dev = crtc->dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4968 struct intel_encoder *encoder;
6be4a607 4969 int pipe = intel_crtc->pipe;
5eddb70b 4970 u32 reg, temp;
b52eb4dc 4971
f7abfe8b
CW		 4972 if (!intel_crtc->active)
4973 return;
4974
d3eedb1a 4975 intel_crtc_disable_planes(crtc);
a5c4d7bc 4976
ea9d758d
DV		 4977 for_each_encoder_on_crtc(dev, crtc, encoder)
4978 encoder->disable(encoder);
4979
f9b61ff6
DV		 4980 drm_crtc_vblank_off(crtc);
4981 assert_vblank_disabled(crtc);
4982
6e3c9717 4983 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4984 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4985
575f7ab7 4986 intel_disable_pipe(intel_crtc);
32f9d658 4987
3f8dce3a 4988 ironlake_pfit_disable(intel_crtc);
2c07245f 4989
bf49ec8c
DV		 4990 for_each_encoder_on_crtc(dev, crtc, encoder)
4991 if (encoder->post_disable)
4992 encoder->post_disable(encoder);
2c07245f 4993
6e3c9717 4994 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4995 ironlake_fdi_disable(crtc);
913d8d11 4996
d925c59a 4997 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4998
d925c59a
DV		 4999 if (HAS_PCH_CPT(dev)) {
5000 /* disable TRANS_DP_CTL */
5001 reg = TRANS_DP_CTL(pipe);
5002 temp = I915_READ(reg);
5003 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5004 TRANS_DP_PORT_SEL_MASK);
5005 temp |= TRANS_DP_PORT_SEL_NONE;
5006 I915_WRITE(reg, temp);
5007
5008 /* disable DPLL_SEL */
5009 temp = I915_READ(PCH_DPLL_SEL);
11887397 5010 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5011 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5012 }
e3421a18 5013
d925c59a 5014 /* disable PCH DPLL */
e72f9fbf 5015 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5016
d925c59a
DV		 5017 ironlake_fdi_pll_disable(intel_crtc);
5018 }
6b383a7f 5019
f7abfe8b 5020 intel_crtc->active = false;
46ba614c 5021 intel_update_watermarks(crtc);
d1ebd816
BW		 5022
5023 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5024 intel_fbc_update(dev);
d1ebd816 5025 mutex_unlock(&dev->struct_mutex);
6be4a607 5026}
1b3c7a47 5027
4f771f10 5028static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5029{
4f771f10
PZ		 5030 struct drm_device *dev = crtc->dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5033 struct intel_encoder *encoder;
6e3c9717 5034 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5035
4f771f10
PZ		 5036 if (!intel_crtc->active)
5037 return;
5038
d3eedb1a 5039 intel_crtc_disable_planes(crtc);
dda9a66a 5040
8807e55b
JN		 5041 for_each_encoder_on_crtc(dev, crtc, encoder) {
5042 intel_opregion_notify_encoder(encoder, false);
4f771f10 5043 encoder->disable(encoder);
8807e55b 5044 }
4f771f10 5045
f9b61ff6
DV		 5046 drm_crtc_vblank_off(crtc);
5047 assert_vblank_disabled(crtc);
5048
6e3c9717 5049 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5050 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5051 false);
575f7ab7 5052 intel_disable_pipe(intel_crtc);
4f771f10 5053
6e3c9717 5054 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5055 intel_ddi_set_vc_payload_alloc(crtc, false);
5056
ad80a810 5057 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5058
ff6d9f55 5059 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5060 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5061 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5062 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5063 else
5064 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5065
1f544388 5066 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5067
6e3c9717 5068 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5069 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5070 intel_ddi_fdi_disable(crtc);
83616634 5071 }
4f771f10 5072
97b040aa
ID		 5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 if (encoder->post_disable)
5075 encoder->post_disable(encoder);
5076
4f771f10 5077 intel_crtc->active = false;
46ba614c 5078 intel_update_watermarks(crtc);
4f771f10
PZ		 5079
5080 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5081 intel_fbc_update(dev);
4f771f10 5082 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5083
5084 if (intel_crtc_to_shared_dpll(intel_crtc))
5085 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5086}
5087
ee7b9f93
JB		 5088static void ironlake_crtc_off(struct drm_crtc *crtc)
5089{
5090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5091 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5092}
5093
6441ab5f 5094
2dd24552
JB		 5095static void i9xx_pfit_enable(struct intel_crtc *crtc)
5096{
5097 struct drm_device *dev = crtc->base.dev;
5098 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5099 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5100
681a8504 5101 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5102 return;
5103
2dd24552 5104 /*
c0b03411
DV		 5105 * The panel fitter should only be adjusted whilst the pipe is disabled,
5106 * according to register description and PRM.
2dd24552 5107 */
c0b03411
DV		 5108 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5109 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5110
b074cec8
JB		 5111 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5112 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5113
5114 /* Border color in case we don't scale up to the full screen. Black by
5115 * default, change to something else for debugging. */
5116 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5117}
5118
d05410f9
DA		 5119static enum intel_display_power_domain port_to_power_domain(enum port port)
5120{
5121 switch (port) {
5122 case PORT_A:
5123 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5124 case PORT_B:
5125 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5126 case PORT_C:
5127 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5128 case PORT_D:
5129 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5130 default:
5131 WARN_ON_ONCE(1);
5132 return POWER_DOMAIN_PORT_OTHER;
5133 }
5134}
5135
77d22dca
ID		 5136#define for_each_power_domain(domain, mask) \
5137 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5138 if ((1 << (domain)) & (mask))
5139
319be8ae
ID		 5140enum intel_display_power_domain
5141intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5142{
5143 struct drm_device *dev = intel_encoder->base.dev;
5144 struct intel_digital_port *intel_dig_port;
5145
5146 switch (intel_encoder->type) {
5147 case INTEL_OUTPUT_UNKNOWN:
5148 /* Only DDI platforms should ever use this output type */
5149 WARN_ON_ONCE(!HAS_DDI(dev));
5150 case INTEL_OUTPUT_DISPLAYPORT:
5151 case INTEL_OUTPUT_HDMI:
5152 case INTEL_OUTPUT_EDP:
5153 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5154 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5155 case INTEL_OUTPUT_DP_MST:
5156 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5157 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5158 case INTEL_OUTPUT_ANALOG:
5159 return POWER_DOMAIN_PORT_CRT;
5160 case INTEL_OUTPUT_DSI:
5161 return POWER_DOMAIN_PORT_DSI;
5162 default:
5163 return POWER_DOMAIN_PORT_OTHER;
5164 }
5165}
5166
5167static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5168{
319be8ae
ID		 5169 struct drm_device *dev = crtc->dev;
5170 struct intel_encoder *intel_encoder;
5171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5172 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5173 unsigned long mask;
5174 enum transcoder transcoder;
5175
5176 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5177
5178 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5179 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5180 if (intel_crtc->config->pch_pfit.enabled ||
5181 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5182 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5183
319be8ae
ID		 5184 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5185 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5186
77d22dca
ID		 5187 return mask;
5188}
5189
679dacd4 5190static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5191{
679dacd4 5192 struct drm_device *dev = state->dev;
77d22dca
ID		 5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5195 struct intel_crtc *crtc;
5196
5197 /*
5198 * First get all needed power domains, then put all unneeded, to avoid
5199 * any unnecessary toggling of the power wells.
5200 */
d3fcc808 5201 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5202 enum intel_display_power_domain domain;
5203
83d65738 5204 if (!crtc->base.state->enable)
77d22dca
ID		 5205 continue;
5206
319be8ae 5207 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5208
5209 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5210 intel_display_power_get(dev_priv, domain);
5211 }
5212
50f6e502 5213 if (dev_priv->display.modeset_global_resources)
679dacd4 5214 dev_priv->display.modeset_global_resources(state);
50f6e502 5215
d3fcc808 5216 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5217 enum intel_display_power_domain domain;
5218
5219 for_each_power_domain(domain, crtc->enabled_power_domains)
5220 intel_display_power_put(dev_priv, domain);
5221
5222 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5223 }
5224
5225 intel_display_set_init_power(dev_priv, false);
5226}
5227
f8437dd1
VK		 5228void broxton_set_cdclk(struct drm_device *dev, int frequency)
5229{
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 uint32_t divider;
5232 uint32_t ratio;
5233 uint32_t current_freq;
5234 int ret;
5235
5236 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5237 switch (frequency) {
5238 case 144000:
5239 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5240 ratio = BXT_DE_PLL_RATIO(60);
5241 break;
5242 case 288000:
5243 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5244 ratio = BXT_DE_PLL_RATIO(60);
5245 break;
5246 case 384000:
5247 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5248 ratio = BXT_DE_PLL_RATIO(60);
5249 break;
5250 case 576000:
5251 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5252 ratio = BXT_DE_PLL_RATIO(60);
5253 break;
5254 case 624000:
5255 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5256 ratio = BXT_DE_PLL_RATIO(65);
5257 break;
5258 case 19200:
5259 /*
5260 * Bypass frequency with DE PLL disabled. Init ratio, divider
5261 * to suppress GCC warning.
5262 */
5263 ratio = 0;
5264 divider = 0;
5265 break;
5266 default:
5267 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5268
5269 return;
5270 }
5271
5272 mutex_lock(&dev_priv->rps.hw_lock);
5273 /* Inform power controller of upcoming frequency change */
5274 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5275 0x80000000);
5276 mutex_unlock(&dev_priv->rps.hw_lock);
5277
5278 if (ret) {
5279 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5280 ret, frequency);
5281 return;
5282 }
5283
5284 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5285 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5286 current_freq = current_freq * 500 + 1000;
5287
5288 /*
5289 * DE PLL has to be disabled when
5290 * - setting to 19.2MHz (bypass, PLL isn't used)
5291 * - before setting to 624MHz (PLL needs toggling)
5292 * - before setting to any frequency from 624MHz (PLL needs toggling)
5293 */
5294 if (frequency == 19200 || frequency == 624000 ||
5295 current_freq == 624000) {
5296 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5297 /* Timeout 200us */
5298 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5299 1))
5300 DRM_ERROR("timout waiting for DE PLL unlock\n");
5301 }
5302
5303 if (frequency != 19200) {
5304 uint32_t val;
5305
5306 val = I915_READ(BXT_DE_PLL_CTL);
5307 val &= ~BXT_DE_PLL_RATIO_MASK;
5308 val |= ratio;
5309 I915_WRITE(BXT_DE_PLL_CTL, val);
5310
5311 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5312 /* Timeout 200us */
5313 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5314 DRM_ERROR("timeout waiting for DE PLL lock\n");
5315
5316 val = I915_READ(CDCLK_CTL);
5317 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5318 val |= divider;
5319 /*
5320 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5321 * enable otherwise.
5322 */
5323 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5324 if (frequency >= 500000)
5325 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5326
5327 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5328 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5329 val |= (frequency - 1000) / 500;
5330 I915_WRITE(CDCLK_CTL, val);
5331 }
5332
5333 mutex_lock(&dev_priv->rps.hw_lock);
5334 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5335 DIV_ROUND_UP(frequency, 25000));
5336 mutex_unlock(&dev_priv->rps.hw_lock);
5337
5338 if (ret) {
5339 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5340 ret, frequency);
5341 return;
5342 }
5343
5344 dev_priv->cdclk_freq = frequency;
5345}
5346
5347void broxton_init_cdclk(struct drm_device *dev)
5348{
5349 struct drm_i915_private *dev_priv = dev->dev_private;
5350 uint32_t val;
5351
5352 /*
5353 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5354 * or else the reset will hang because there is no PCH to respond.
5355 * Move the handshake programming to initialization sequence.
5356 * Previously was left up to BIOS.
5357 */
5358 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5359 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5360 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5361
5362 /* Enable PG1 for cdclk */
5363 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5364
5365 /* check if cd clock is enabled */
5366 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5367 DRM_DEBUG_KMS("Display already initialized\n");
5368 return;
5369 }
5370
5371 /*
5372 * FIXME:
5373 * - The initial CDCLK needs to be read from VBT.
5374 * Need to make this change after VBT has changes for BXT.
5375 * - check if setting the max (or any) cdclk freq is really necessary
5376 * here, it belongs to modeset time
5377 */
5378 broxton_set_cdclk(dev, 624000);
5379
5380 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5381 udelay(10);
5382
5383 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5384 DRM_ERROR("DBuf power enable timeout!\n");
5385}
5386
5387void broxton_uninit_cdclk(struct drm_device *dev)
5388{
5389 struct drm_i915_private *dev_priv = dev->dev_private;
5390
5391 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5392 udelay(10);
5393
5394 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5395 DRM_ERROR("DBuf power disable timeout!\n");
5396
5397 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5398 broxton_set_cdclk(dev, 19200);
5399
5400 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5401}
5402
dfcab17e 5403/* returns HPLL frequency in kHz */
f8bf63fd 5404static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5405{
586f49dc 5406 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5407
586f49dc
JB		 5408 /* Obtain SKU information */
5409 mutex_lock(&dev_priv->dpio_lock);
5410 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5411 CCK_FUSE_HPLL_FREQ_MASK;
5412 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5413
dfcab17e 5414 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5415}
5416
f8bf63fd
VS		 5417static void vlv_update_cdclk(struct drm_device *dev)
5418{
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420
164dfd28 5421 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5422 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5423 dev_priv->cdclk_freq);
f8bf63fd
VS		 5424
5425 /*
5426 * Program the gmbus_freq based on the cdclk frequency.
5427 * BSpec erroneously claims we should aim for 4MHz, but
5428 * in fact 1MHz is the correct frequency.
5429 */
164dfd28 5430 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5431}
5432
30a970c6
JB		 5433/* Adjust CDclk dividers to allow high res or save power if possible */
5434static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5435{
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 u32 val, cmd;
5438
164dfd28
VK		 5439 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5440 != dev_priv->cdclk_freq);
d60c4473 5441
dfcab17e 5442 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5443 cmd = 2;
dfcab17e 5444 else if (cdclk == 266667)
30a970c6
JB		 5445 cmd = 1;
5446 else
5447 cmd = 0;
5448
5449 mutex_lock(&dev_priv->rps.hw_lock);
5450 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5451 val &= ~DSPFREQGUAR_MASK;
5452 val |= (cmd << DSPFREQGUAR_SHIFT);
5453 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5454 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5455 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5456 50)) {
5457 DRM_ERROR("timed out waiting for CDclk change\n");
5458 }
5459 mutex_unlock(&dev_priv->rps.hw_lock);
5460
dfcab17e 5461 if (cdclk == 400000) {
6bcda4f0 5462 u32 divider;
30a970c6 5463
6bcda4f0 5464 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5465
5466 mutex_lock(&dev_priv->dpio_lock);
5467 /* adjust cdclk divider */
5468 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5469 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5470 val |= divider;
5471 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5472
5473 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5474 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5475 50))
5476 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5477 mutex_unlock(&dev_priv->dpio_lock);
5478 }
5479
5480 mutex_lock(&dev_priv->dpio_lock);
5481 /* adjust self-refresh exit latency value */
5482 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5483 val &= ~0x7f;
5484
5485 /*
5486 * For high bandwidth configs, we set a higher latency in the bunit
5487 * so that the core display fetch happens in time to avoid underruns.
5488 */
dfcab17e 5489 if (cdclk == 400000)
30a970c6
JB		 5490 val |= 4500 / 250; /* 4.5 usec */
5491 else
5492 val |= 3000 / 250; /* 3.0 usec */
5493 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5494 mutex_unlock(&dev_priv->dpio_lock);
5495
f8bf63fd 5496 vlv_update_cdclk(dev);
30a970c6
JB		 5497}
5498
383c5a6a
VS		 5499static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502 u32 val, cmd;
5503
164dfd28
VK		 5504 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5505 != dev_priv->cdclk_freq);
383c5a6a
VS		 5506
5507 switch (cdclk) {
383c5a6a
VS		 5508 case 333333:
5509 case 320000:
383c5a6a 5510 case 266667:
383c5a6a 5511 case 200000:
383c5a6a
VS		 5512 break;
5513 default:
5f77eeb0 5514 MISSING_CASE(cdclk);
383c5a6a
VS		 5515 return;
5516 }
5517
9d0d3fda
VS		 5518 /*
5519 * Specs are full of misinformation, but testing on actual
5520 * hardware has shown that we just need to write the desired
5521 * CCK divider into the Punit register.
5522 */
5523 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5524
383c5a6a
VS		 5525 mutex_lock(&dev_priv->rps.hw_lock);
5526 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5527 val &= ~DSPFREQGUAR_MASK_CHV;
5528 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5529 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5530 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5531 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5532 50)) {
5533 DRM_ERROR("timed out waiting for CDclk change\n");
5534 }
5535 mutex_unlock(&dev_priv->rps.hw_lock);
5536
5537 vlv_update_cdclk(dev);
5538}
5539
30a970c6
JB		 5540static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5541 int max_pixclk)
5542{
6bcda4f0 5543 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5544 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5545
30a970c6
JB		 5546 /*
5547 * Really only a few cases to deal with, as only 4 CDclks are supported:
5548 * 200MHz
5549 * 267MHz
29dc7ef3 5550 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5551 * 400MHz (VLV only)
5552 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5553 * of the lower bin and adjust if needed.
e37c67a1
VS		 5554 *
5555 * We seem to get an unstable or solid color picture at 200MHz.
5556 * Not sure what's wrong. For now use 200MHz only when all pipes
5557 * are off.
30a970c6 5558 */
6cca3195
VS		 5559 if (!IS_CHERRYVIEW(dev_priv) &&
5560 max_pixclk > freq_320*limit/100)
dfcab17e 5561 return 400000;
6cca3195 5562 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5563 return freq_320;
e37c67a1 5564 else if (max_pixclk > 0)
dfcab17e 5565 return 266667;
e37c67a1
VS		 5566 else
5567 return 200000;
30a970c6
JB		 5568}
5569
f8437dd1
VK		 5570static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5571 int max_pixclk)
5572{
5573 /*
5574 * FIXME:
5575 * - remove the guardband, it's not needed on BXT
5576 * - set 19.2MHz bypass frequency if there are no active pipes
5577 */
5578 if (max_pixclk > 576000*9/10)
5579 return 624000;
5580 else if (max_pixclk > 384000*9/10)
5581 return 576000;
5582 else if (max_pixclk > 288000*9/10)
5583 return 384000;
5584 else if (max_pixclk > 144000*9/10)
5585 return 288000;
5586 else
5587 return 144000;
5588}
5589
2f2d7aa1 5590/* compute the max pixel clock for new configuration */
304603f4 5591static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5592{
304603f4 5593 struct drm_device *dev = state->dev;
30a970c6 5594 struct intel_crtc *intel_crtc;
304603f4 5595 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5596 int max_pixclk = 0;
5597
d3fcc808 5598 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5599 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5600 if (IS_ERR(crtc_state))
5601 return PTR_ERR(crtc_state);
5602
5603 if (!crtc_state->base.enable)
5604 continue;
5605
5606 max_pixclk = max(max_pixclk,
5607 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5608 }
5609
5610 return max_pixclk;
5611}
5612
304603f4 5613static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5614 unsigned *prepare_pipes)
30a970c6 5615{
304603f4 5616 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5617 struct intel_crtc *intel_crtc;
304603f4 5618 int max_pixclk = intel_mode_max_pixclk(state);
f8437dd1 5619 int cdclk;
304603f4
ACO		 5620
5621 if (max_pixclk < 0)
5622 return max_pixclk;
30a970c6 5623
f8437dd1
VK		 5624 if (IS_VALLEYVIEW(dev_priv))
5625 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5626 else
5627 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5628
5629 if (cdclk == dev_priv->cdclk_freq)
304603f4 5630 return 0;
30a970c6 5631
2f2d7aa1 5632 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5633 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5634 if (intel_crtc->base.state->enable)
30a970c6 5635 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5636
5637 return 0;
30a970c6
JB		 5638}
5639
1e69cd74
VS		 5640static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5641{
5642 unsigned int credits, default_credits;
5643
5644 if (IS_CHERRYVIEW(dev_priv))
5645 default_credits = PFI_CREDIT(12);
5646 else
5647 default_credits = PFI_CREDIT(8);
5648
164dfd28 5649 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5650 /* CHV suggested value is 31 or 63 */
5651 if (IS_CHERRYVIEW(dev_priv))
5652 credits = PFI_CREDIT_31;
5653 else
5654 credits = PFI_CREDIT(15);
5655 } else {
5656 credits = default_credits;
5657 }
5658
5659 /*
5660 * WA - write default credits before re-programming
5661 * FIXME: should we also set the resend bit here?
5662 */
5663 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5664 default_credits);
5665
5666 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5667 credits | PFI_CREDIT_RESEND);
5668
5669 /*
5670 * FIXME is this guaranteed to clear
5671 * immediately or should we poll for it?
5672 */
5673 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5674}
5675
679dacd4 5676static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5677{
679dacd4 5678 struct drm_device *dev = state->dev;
30a970c6 5679 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5680 int max_pixclk = intel_mode_max_pixclk(state);
5681 int req_cdclk;
5682
5683 /* The only reason this can fail is if we fail to add the crtc_state
5684 * to the atomic state. But that can't happen since the call to
5685 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5686 * can't have failed otherwise the mode set would be aborted) added all
5687 * the states already. */
5688 if (WARN_ON(max_pixclk < 0))
5689 return;
5690
5691 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5692
164dfd28 5693 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5694 /*
5695 * FIXME: We can end up here with all power domains off, yet
5696 * with a CDCLK frequency other than the minimum. To account
5697 * for this take the PIPE-A power domain, which covers the HW
5698 * blocks needed for the following programming. This can be
5699 * removed once it's guaranteed that we get here either with
5700 * the minimum CDCLK set, or the required power domains
5701 * enabled.
5702 */
5703 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5704
383c5a6a
VS		 5705 if (IS_CHERRYVIEW(dev))
5706 cherryview_set_cdclk(dev, req_cdclk);
5707 else
5708 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5709
1e69cd74
VS		 5710 vlv_program_pfi_credits(dev_priv);
5711
738c05c0 5712 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5713 }
30a970c6
JB		 5714}
5715
89b667f8
JB		 5716static void valleyview_crtc_enable(struct drm_crtc *crtc)
5717{
5718 struct drm_device *dev = crtc->dev;
a72e4c9f 5719 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5721 struct intel_encoder *encoder;
5722 int pipe = intel_crtc->pipe;
23538ef1 5723 bool is_dsi;
89b667f8 5724
83d65738 5725 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5726
5727 if (intel_crtc->active)
5728 return;
5729
409ee761 5730 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5731
1ae0d137
VS		 5732 if (!is_dsi) {
5733 if (IS_CHERRYVIEW(dev))
6e3c9717 5734 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5735 else
6e3c9717 5736 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5737 }
5b18e57c 5738
6e3c9717 5739 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5740 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5741
5742 intel_set_pipe_timings(intel_crtc);
5743
c14b0485
VS		 5744 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5745 struct drm_i915_private *dev_priv = dev->dev_private;
5746
5747 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5748 I915_WRITE(CHV_CANVAS(pipe), 0);
5749 }
5750
5b18e57c
DV		 5751 i9xx_set_pipeconf(intel_crtc);
5752
89b667f8 5753 intel_crtc->active = true;
89b667f8 5754
a72e4c9f 5755 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5756
89b667f8
JB		 5757 for_each_encoder_on_crtc(dev, crtc, encoder)
5758 if (encoder->pre_pll_enable)
5759 encoder->pre_pll_enable(encoder);
5760
9d556c99
CML		 5761 if (!is_dsi) {
5762 if (IS_CHERRYVIEW(dev))
6e3c9717 5763 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5764 else
6e3c9717 5765 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5766 }
89b667f8
JB		 5767
5768 for_each_encoder_on_crtc(dev, crtc, encoder)
5769 if (encoder->pre_enable)
5770 encoder->pre_enable(encoder);
5771
2dd24552
JB		 5772 i9xx_pfit_enable(intel_crtc);
5773
63cbb074
VS		 5774 intel_crtc_load_lut(crtc);
5775
f37fcc2a 5776 intel_update_watermarks(crtc);
e1fdc473 5777 intel_enable_pipe(intel_crtc);
be6a6f8e 5778
4b3a9526
VS		 5779 assert_vblank_disabled(crtc);
5780 drm_crtc_vblank_on(crtc);
5781
f9b61ff6
DV		 5782 for_each_encoder_on_crtc(dev, crtc, encoder)
5783 encoder->enable(encoder);
5784
9ab0460b 5785 intel_crtc_enable_planes(crtc);
d40d9187 5786
56b80e1f 5787 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5788 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5789}
5790
f13c2ef3
DV		 5791static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5792{
5793 struct drm_device *dev = crtc->base.dev;
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795
6e3c9717
ACO		 5796 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5797 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5798}
5799
0b8765c6 5800static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5801{
5802 struct drm_device *dev = crtc->dev;
a72e4c9f 5803 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5805 struct intel_encoder *encoder;
79e53945 5806 int pipe = intel_crtc->pipe;
79e53945 5807
83d65738 5808 WARN_ON(!crtc->state->enable);
08a48469 5809
f7abfe8b
CW		 5810 if (intel_crtc->active)
5811 return;
5812
f13c2ef3
DV		 5813 i9xx_set_pll_dividers(intel_crtc);
5814
6e3c9717 5815 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5816 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5817
5818 intel_set_pipe_timings(intel_crtc);
5819
5b18e57c
DV		 5820 i9xx_set_pipeconf(intel_crtc);
5821
f7abfe8b 5822 intel_crtc->active = true;
6b383a7f 5823
4a3436e8 5824 if (!IS_GEN2(dev))
a72e4c9f 5825 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5826
9d6d9f19
MK		 5827 for_each_encoder_on_crtc(dev, crtc, encoder)
5828 if (encoder->pre_enable)
5829 encoder->pre_enable(encoder);
5830
f6736a1a
DV		 5831 i9xx_enable_pll(intel_crtc);
5832
2dd24552
JB		 5833 i9xx_pfit_enable(intel_crtc);
5834
63cbb074
VS		 5835 intel_crtc_load_lut(crtc);
5836
f37fcc2a 5837 intel_update_watermarks(crtc);
e1fdc473 5838 intel_enable_pipe(intel_crtc);
be6a6f8e 5839
4b3a9526
VS		 5840 assert_vblank_disabled(crtc);
5841 drm_crtc_vblank_on(crtc);
5842
f9b61ff6
DV		 5843 for_each_encoder_on_crtc(dev, crtc, encoder)
5844 encoder->enable(encoder);
5845
9ab0460b 5846 intel_crtc_enable_planes(crtc);
d40d9187 5847
4a3436e8
VS		 5848 /*
5849 * Gen2 reports pipe underruns whenever all planes are disabled.
5850 * So don't enable underrun reporting before at least some planes
5851 * are enabled.
5852 * FIXME: Need to fix the logic to work when we turn off all planes
5853 * but leave the pipe running.
5854 */
5855 if (IS_GEN2(dev))
a72e4c9f 5856 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5857
56b80e1f 5858 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5859 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5860}
79e53945 5861
87476d63
DV		 5862static void i9xx_pfit_disable(struct intel_crtc *crtc)
5863{
5864 struct drm_device *dev = crtc->base.dev;
5865 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5866
6e3c9717 5867 if (!crtc->config->gmch_pfit.control)
328d8e82 5868 return;
87476d63 5869
328d8e82 5870 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5871
328d8e82
DV		 5872 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5873 I915_READ(PFIT_CONTROL));
5874 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5875}
5876
0b8765c6
JB		 5877static void i9xx_crtc_disable(struct drm_crtc *crtc)
5878{
5879 struct drm_device *dev = crtc->dev;
5880 struct drm_i915_private *dev_priv = dev->dev_private;
5881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5882 struct intel_encoder *encoder;
0b8765c6 5883 int pipe = intel_crtc->pipe;
ef9c3aee 5884
f7abfe8b
CW		 5885 if (!intel_crtc->active)
5886 return;
5887
4a3436e8
VS		 5888 /*
5889 * Gen2 reports pipe underruns whenever all planes are disabled.
5890 * So diasble underrun reporting before all the planes get disabled.
5891 * FIXME: Need to fix the logic to work when we turn off all planes
5892 * but leave the pipe running.
5893 */
5894 if (IS_GEN2(dev))
a72e4c9f 5895 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5896
564ed191
ID		 5897 /*
5898 * Vblank time updates from the shadow to live plane control register
5899 * are blocked if the memory self-refresh mode is active at that
5900 * moment. So to make sure the plane gets truly disabled, disable
5901 * first the self-refresh mode. The self-refresh enable bit in turn
5902 * will be checked/applied by the HW only at the next frame start
5903 * event which is after the vblank start event, so we need to have a
5904 * wait-for-vblank between disabling the plane and the pipe.
5905 */
5906 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5907 intel_crtc_disable_planes(crtc);
5908
6304cd91
VS		 5909 /*
5910 * On gen2 planes are double buffered but the pipe isn't, so we must
5911 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5912 * We also need to wait on all gmch platforms because of the
5913 * self-refresh mode constraint explained above.
6304cd91 5914 */
564ed191 5915 intel_wait_for_vblank(dev, pipe);
6304cd91 5916
4b3a9526
VS		 5917 for_each_encoder_on_crtc(dev, crtc, encoder)
5918 encoder->disable(encoder);
5919
f9b61ff6
DV		 5920 drm_crtc_vblank_off(crtc);
5921 assert_vblank_disabled(crtc);
5922
575f7ab7 5923 intel_disable_pipe(intel_crtc);
24a1f16d 5924
87476d63 5925 i9xx_pfit_disable(intel_crtc);
24a1f16d 5926
89b667f8
JB		 5927 for_each_encoder_on_crtc(dev, crtc, encoder)
5928 if (encoder->post_disable)
5929 encoder->post_disable(encoder);
5930
409ee761 5931 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5932 if (IS_CHERRYVIEW(dev))
5933 chv_disable_pll(dev_priv, pipe);
5934 else if (IS_VALLEYVIEW(dev))
5935 vlv_disable_pll(dev_priv, pipe);
5936 else
1c4e0274 5937 i9xx_disable_pll(intel_crtc);
076ed3b2 5938 }
0b8765c6 5939
4a3436e8 5940 if (!IS_GEN2(dev))
a72e4c9f 5941 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5942
f7abfe8b 5943 intel_crtc->active = false;
46ba614c 5944 intel_update_watermarks(crtc);
f37fcc2a 5945
efa9624e 5946 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5947 intel_fbc_update(dev);
efa9624e 5948 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5949}
5950
ee7b9f93
JB		 5951static void i9xx_crtc_off(struct drm_crtc *crtc)
5952{
5953}
5954
b04c5bd6
BF		 5955/* Master function to enable/disable CRTC and corresponding power wells */
5956void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5957{
5958 struct drm_device *dev = crtc->dev;
5959 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5961 enum intel_display_power_domain domain;
5962 unsigned long domains;
976f8a20 5963
0e572fe7
DV		 5964 if (enable) {
5965 if (!intel_crtc->active) {
e1e9fb84
DV		 5966 domains = get_crtc_power_domains(crtc);
5967 for_each_power_domain(domain, domains)
5968 intel_display_power_get(dev_priv, domain);
5969 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5970
5971 dev_priv->display.crtc_enable(crtc);
5972 }
5973 } else {
5974 if (intel_crtc->active) {
5975 dev_priv->display.crtc_disable(crtc);
5976
e1e9fb84
DV		 5977 domains = intel_crtc->enabled_power_domains;
5978 for_each_power_domain(domain, domains)
5979 intel_display_power_put(dev_priv, domain);
5980 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5981 }
5982 }
b04c5bd6
BF		 5983}
5984
5985/**
5986 * Sets the power management mode of the pipe and plane.
5987 */
5988void intel_crtc_update_dpms(struct drm_crtc *crtc)
5989{
5990 struct drm_device *dev = crtc->dev;
5991 struct intel_encoder *intel_encoder;
5992 bool enable = false;
5993
5994 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5995 enable |= intel_encoder->connectors_active;
5996
5997 intel_crtc_control(crtc, enable);
976f8a20
DV		 5998}
5999
cdd59983
CW		 6000static void intel_crtc_disable(struct drm_crtc *crtc)
6001{
cdd59983 6002 struct drm_device *dev = crtc->dev;
976f8a20 6003 struct drm_connector *connector;
ee7b9f93 6004 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6005
976f8a20 6006 /* crtc should still be enabled when we disable it. */
83d65738 6007 WARN_ON(!crtc->state->enable);
976f8a20
DV		 6008
6009 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6010 dev_priv->display.off(crtc);
6011
70a101f8 6012 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6013
6014 /* Update computed state. */
6015 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6016 if (!connector->encoder || !connector->encoder->crtc)
6017 continue;
6018
6019 if (connector->encoder->crtc != crtc)
6020 continue;
6021
6022 connector->dpms = DRM_MODE_DPMS_OFF;
6023 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6024 }
6025}
6026
ea5b213a 6027void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6028{
4ef69c7a 6029 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6030
ea5b213a
CW		 6031 drm_encoder_cleanup(encoder);
6032 kfree(intel_encoder);
7e7d76c3
JB		 6033}
6034
9237329d 6035/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6036 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6037 * state of the entire output pipe. */
9237329d 6038static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6039{
5ab432ef
DV		 6040 if (mode == DRM_MODE_DPMS_ON) {
6041 encoder->connectors_active = true;
6042
b2cabb0e 6043 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6044 } else {
6045 encoder->connectors_active = false;
6046
b2cabb0e 6047 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6048 }
79e53945
JB		 6049}
6050
0a91ca29
DV		 6051/* Cross check the actual hw state with our own modeset state tracking (and it's
6052 * internal consistency). */
b980514c 6053static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6054{
0a91ca29
DV		 6055 if (connector->get_hw_state(connector)) {
6056 struct intel_encoder *encoder = connector->encoder;
6057 struct drm_crtc *crtc;
6058 bool encoder_enabled;
6059 enum pipe pipe;
6060
6061 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6062 connector->base.base.id,
c23cc417 6063 connector->base.name);
0a91ca29 6064
0e32b39c
DA		 6065 /* there is no real hw state for MST connectors */
6066 if (connector->mst_port)
6067 return;
6068
e2c719b7 6069 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6070 "wrong connector dpms state\n");
e2c719b7 6071 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6072 "active connector not linked to encoder\n");
0a91ca29 6073
36cd7444 6074 if (encoder) {
e2c719b7 6075 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6076 "encoder->connectors_active not set\n");
6077
6078 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6079 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6080 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6081 return;
0a91ca29 6082
36cd7444 6083 crtc = encoder->base.crtc;
0a91ca29 6084
83d65738
MR		 6085 I915_STATE_WARN(!crtc->state->enable,
6086 "crtc not enabled\n");
e2c719b7
RC		 6087 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6088 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6089 "encoder active on the wrong pipe\n");
6090 }
0a91ca29 6091 }
79e53945
JB		 6092}
6093
9bdbd0b9
ACO		 6094int intel_connector_init(struct intel_connector *connector)
6095{
6096 struct drm_connector_state *connector_state;
6097
6098 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6099 if (!connector_state)
6100 return -ENOMEM;
6101
6102 connector->base.state = connector_state;
6103 return 0;
6104}
6105
6106struct intel_connector *intel_connector_alloc(void)
6107{
6108 struct intel_connector *connector;
6109
6110 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6111 if (!connector)
6112 return NULL;
6113
6114 if (intel_connector_init(connector) < 0) {
6115 kfree(connector);
6116 return NULL;
6117 }
6118
6119 return connector;
6120}
6121
5ab432ef
DV		 6122/* Even simpler default implementation, if there's really no special case to
6123 * consider. */
6124void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6125{
5ab432ef
DV		 6126 /* All the simple cases only support two dpms states. */
6127 if (mode != DRM_MODE_DPMS_ON)
6128 mode = DRM_MODE_DPMS_OFF;
d4270e57 6129
5ab432ef
DV		 6130 if (mode == connector->dpms)
6131 return;
6132
6133 connector->dpms = mode;
6134
6135 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6136 if (connector->encoder)
6137 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6138
b980514c 6139 intel_modeset_check_state(connector->dev);
79e53945
JB		 6140}
6141
f0947c37
DV		 6142/* Simple connector->get_hw_state implementation for encoders that support only
6143 * one connector and no cloning and hence the encoder state determines the state
6144 * of the connector. */
6145bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6146{
24929352 6147 enum pipe pipe = 0;
f0947c37 6148 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6149
f0947c37 6150 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6151}
6152
6d293983 6153static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6154{
6d293983
ACO		 6155 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6156 return crtc_state->fdi_lanes;
d272ddfa
VS		 6157
6158 return 0;
6159}
6160
6d293983 6161static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6162 struct intel_crtc_state *pipe_config)
1857e1da 6163{
6d293983
ACO		 6164 struct drm_atomic_state *state = pipe_config->base.state;
6165 struct intel_crtc *other_crtc;
6166 struct intel_crtc_state *other_crtc_state;
6167
1857e1da
DV		 6168 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6169 pipe_name(pipe), pipe_config->fdi_lanes);
6170 if (pipe_config->fdi_lanes > 4) {
6171 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6172 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6173 return -EINVAL;
1857e1da
DV		 6174 }
6175
bafb6553 6176 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6177 if (pipe_config->fdi_lanes > 2) {
6178 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6179 pipe_config->fdi_lanes);
6d293983 6180 return -EINVAL;
1857e1da 6181 } else {
6d293983 6182 return 0;
1857e1da
DV		 6183 }
6184 }
6185
6186 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6187 return 0;
1857e1da
DV		 6188
6189 /* Ivybridge 3 pipe is really complicated */
6190 switch (pipe) {
6191 case PIPE_A:
6d293983 6192 return 0;
1857e1da 6193 case PIPE_B:
6d293983
ACO		 6194 if (pipe_config->fdi_lanes <= 2)
6195 return 0;
6196
6197 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6198 other_crtc_state =
6199 intel_atomic_get_crtc_state(state, other_crtc);
6200 if (IS_ERR(other_crtc_state))
6201 return PTR_ERR(other_crtc_state);
6202
6203 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6204 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6205 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6206 return -EINVAL;
1857e1da 6207 }
6d293983 6208 return 0;
1857e1da 6209 case PIPE_C:
251cc67c
VS		 6210 if (pipe_config->fdi_lanes > 2) {
6211 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6212 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6213 return -EINVAL;
251cc67c 6214 }
6d293983
ACO		 6215
6216 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6217 other_crtc_state =
6218 intel_atomic_get_crtc_state(state, other_crtc);
6219 if (IS_ERR(other_crtc_state))
6220 return PTR_ERR(other_crtc_state);
6221
6222 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6223 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6224 return -EINVAL;
1857e1da 6225 }
6d293983 6226 return 0;
1857e1da
DV		 6227 default:
6228 BUG();
6229 }
6230}
6231
e29c22c0
DV		 6232#define RETRY 1
6233static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6234 struct intel_crtc_state *pipe_config)
877d48d5 6235{
1857e1da 6236 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6237 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6238 int lane, link_bw, fdi_dotclock, ret;
6239 bool needs_recompute = false;
877d48d5 6240
e29c22c0 6241retry:
877d48d5
DV		 6242 /* FDI is a binary signal running at ~2.7GHz, encoding
6243 * each output octet as 10 bits. The actual frequency
6244 * is stored as a divider into a 100MHz clock, and the
6245 * mode pixel clock is stored in units of 1KHz.
6246 * Hence the bw of each lane in terms of the mode signal
6247 * is:
6248 */
6249 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6250
241bfc38 6251 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6252
2bd89a07 6253 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6254 pipe_config->pipe_bpp);
6255
6256 pipe_config->fdi_lanes = lane;
6257
2bd89a07 6258 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6259 link_bw, &pipe_config->fdi_m_n);
1857e1da 6260
6d293983
ACO		 6261 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6262 intel_crtc->pipe, pipe_config);
6263 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6264 pipe_config->pipe_bpp -= 2*3;
6265 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6266 pipe_config->pipe_bpp);
6267 needs_recompute = true;
6268 pipe_config->bw_constrained = true;
6269
6270 goto retry;
6271 }
6272
6273 if (needs_recompute)
6274 return RETRY;
6275
6d293983 6276 return ret;
877d48d5
DV		 6277}
6278
42db64ef 6279static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6280 struct intel_crtc_state *pipe_config)
42db64ef 6281{
d330a953 6282 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6283 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6284 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6285}
6286
a43f6e0f 6287static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6288 struct intel_crtc_state *pipe_config)
79e53945 6289{
a43f6e0f 6290 struct drm_device *dev = crtc->base.dev;
8bd31e67 6291 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6292 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6293 int ret;
89749350 6294
ad3a4479 6295 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6296 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6297 int clock_limit =
6298 dev_priv->display.get_display_clock_speed(dev);
6299
6300 /*
6301 * Enable pixel doubling when the dot clock
6302 * is > 90% of the (display) core speed.
6303 *
b397c96b
VS		 6304 * GDG double wide on either pipe,
6305 * otherwise pipe A only.
cf532bb2 6306 */
b397c96b 6307 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6308 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6309 clock_limit *= 2;
cf532bb2 6310 pipe_config->double_wide = true;
ad3a4479
VS		 6311 }
6312
241bfc38 6313 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6314 return -EINVAL;
2c07245f 6315 }
89749350 6316
1d1d0e27
VS		 6317 /*
6318 * Pipe horizontal size must be even in:
6319 * - DVO ganged mode
6320 * - LVDS dual channel mode
6321 * - Double wide pipe
6322 */
a93e255f 6323 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6324 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6325 pipe_config->pipe_src_w &= ~1;
6326
8693a824
DL		 6327 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6328 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6329 */
6330 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6331 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6332 return -EINVAL;
44f46b42 6333
f5adf94e 6334 if (HAS_IPS(dev))
a43f6e0f
DV		 6335 hsw_compute_ips_config(crtc, pipe_config);
6336
877d48d5 6337 if (pipe_config->has_pch_encoder)
a43f6e0f 6338 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6339
d03c93d4
CK		 6340 /* FIXME: remove below call once atomic mode set is place and all crtc
6341 * related checks called from atomic_crtc_check function */
6342 ret = 0;
6343 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6344 crtc, pipe_config->base.state);
6345 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6346
6347 return ret;
79e53945
JB		 6348}
6349
1652d19e
VS		 6350static int skylake_get_display_clock_speed(struct drm_device *dev)
6351{
6352 struct drm_i915_private *dev_priv = to_i915(dev);
6353 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6354 uint32_t cdctl = I915_READ(CDCLK_CTL);
6355 uint32_t linkrate;
6356
6357 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6358 WARN(1, "LCPLL1 not enabled\n");
6359 return 24000; /* 24MHz is the cd freq with NSSC ref */
6360 }
6361
6362 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6363 return 540000;
6364
6365 linkrate = (I915_READ(DPLL_CTRL1) &
6366 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6367
6368 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
6369 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
6370 /* vco 8640 */
6371 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6372 case CDCLK_FREQ_450_432:
6373 return 432000;
6374 case CDCLK_FREQ_337_308:
6375 return 308570;
6376 case CDCLK_FREQ_675_617:
6377 return 617140;
6378 default:
6379 WARN(1, "Unknown cd freq selection\n");
6380 }
6381 } else {
6382 /* vco 8100 */
6383 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6384 case CDCLK_FREQ_450_432:
6385 return 450000;
6386 case CDCLK_FREQ_337_308:
6387 return 337500;
6388 case CDCLK_FREQ_675_617:
6389 return 675000;
6390 default:
6391 WARN(1, "Unknown cd freq selection\n");
6392 }
6393 }
6394
6395 /* error case, do as if DPLL0 isn't enabled */
6396 return 24000;
6397}
6398
6399static int broadwell_get_display_clock_speed(struct drm_device *dev)
6400{
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 uint32_t lcpll = I915_READ(LCPLL_CTL);
6403 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6404
6405 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6406 return 800000;
6407 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6408 return 450000;
6409 else if (freq == LCPLL_CLK_FREQ_450)
6410 return 450000;
6411 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6412 return 540000;
6413 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6414 return 337500;
6415 else
6416 return 675000;
6417}
6418
6419static int haswell_get_display_clock_speed(struct drm_device *dev)
6420{
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 uint32_t lcpll = I915_READ(LCPLL_CTL);
6423 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6424
6425 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6426 return 800000;
6427 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6428 return 450000;
6429 else if (freq == LCPLL_CLK_FREQ_450)
6430 return 450000;
6431 else if (IS_HSW_ULT(dev))
6432 return 337500;
6433 else
6434 return 540000;
6435}
6436
25eb05fc
JB		 6437static int valleyview_get_display_clock_speed(struct drm_device *dev)
6438{
d197b7d3 6439 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6440 u32 val;
6441 int divider;
6442
6bcda4f0
VS		 6443 if (dev_priv->hpll_freq == 0)
6444 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6445
d197b7d3
VS		 6446 mutex_lock(&dev_priv->dpio_lock);
6447 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6448 mutex_unlock(&dev_priv->dpio_lock);
6449
6450 divider = val & DISPLAY_FREQUENCY_VALUES;
6451
7d007f40
VS		 6452 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6453 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6454 "cdclk change in progress\n");
6455
6bcda4f0 6456 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6457}
6458
b37a6434
VS		 6459static int ilk_get_display_clock_speed(struct drm_device *dev)
6460{
6461 return 450000;
6462}
6463
e70236a8
JB		 6464static int i945_get_display_clock_speed(struct drm_device *dev)
6465{
6466 return 400000;
6467}
79e53945 6468
e70236a8 6469static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6470{
e907f170 6471 return 333333;
e70236a8 6472}
79e53945 6473
e70236a8
JB		 6474static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6475{
6476 return 200000;
6477}
79e53945 6478
257a7ffc
DV		 6479static int pnv_get_display_clock_speed(struct drm_device *dev)
6480{
6481 u16 gcfgc = 0;
6482
6483 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6484
6485 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6486 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6487 return 266667;
257a7ffc 6488 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6489 return 333333;
257a7ffc 6490 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6491 return 444444;
257a7ffc
DV		 6492 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6493 return 200000;
6494 default:
6495 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6496 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6497 return 133333;
257a7ffc 6498 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6499 return 166667;
257a7ffc
DV		 6500 }
6501}
6502
e70236a8
JB		 6503static int i915gm_get_display_clock_speed(struct drm_device *dev)
6504{
6505 u16 gcfgc = 0;
79e53945 6506
e70236a8
JB		 6507 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6508
6509 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6510 return 133333;
e70236a8
JB		 6511 else {
6512 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6513 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6514 return 333333;
e70236a8
JB		 6515 default:
6516 case GC_DISPLAY_CLOCK_190_200_MHZ:
6517 return 190000;
79e53945 6518 }
e70236a8
JB		 6519 }
6520}
6521
6522static int i865_get_display_clock_speed(struct drm_device *dev)
6523{
e907f170 6524 return 266667;
e70236a8
JB		 6525}
6526
6527static int i855_get_display_clock_speed(struct drm_device *dev)
6528{
6529 u16 hpllcc = 0;
6530 /* Assume that the hardware is in the high speed state. This
6531 * should be the default.
6532 */
6533 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6534 case GC_CLOCK_133_200:
6535 case GC_CLOCK_100_200:
6536 return 200000;
6537 case GC_CLOCK_166_250:
6538 return 250000;
6539 case GC_CLOCK_100_133:
e907f170 6540 return 133333;
e70236a8 6541 }
79e53945 6542
e70236a8
JB		 6543 /* Shouldn't happen */
6544 return 0;
6545}
79e53945 6546
e70236a8
JB		 6547static int i830_get_display_clock_speed(struct drm_device *dev)
6548{
e907f170 6549 return 133333;
79e53945
JB		 6550}
6551
2c07245f 6552static void
a65851af 6553intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6554{
a65851af
VS		 6555 while (*num > DATA_LINK_M_N_MASK ||
6556 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6557 *num >>= 1;
6558 *den >>= 1;
6559 }
6560}
6561
a65851af
VS		 6562static void compute_m_n(unsigned int m, unsigned int n,
6563 uint32_t *ret_m, uint32_t *ret_n)
6564{
6565 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6566 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6567 intel_reduce_m_n_ratio(ret_m, ret_n);
6568}
6569
e69d0bc1
DV		 6570void
6571intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6572 int pixel_clock, int link_clock,
6573 struct intel_link_m_n *m_n)
2c07245f 6574{
e69d0bc1 6575 m_n->tu = 64;
a65851af
VS		 6576
6577 compute_m_n(bits_per_pixel * pixel_clock,
6578 link_clock * nlanes * 8,
6579 &m_n->gmch_m, &m_n->gmch_n);
6580
6581 compute_m_n(pixel_clock, link_clock,
6582 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6583}
6584
a7615030
CW		 6585static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6586{
d330a953
JN		 6587 if (i915.panel_use_ssc >= 0)
6588 return i915.panel_use_ssc != 0;
41aa3448 6589 return dev_priv->vbt.lvds_use_ssc
435793df 6590 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6591}
6592
a93e255f
ACO		 6593static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6594 int num_connectors)
c65d77d8 6595{
a93e255f 6596 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 int refclk;
6599
a93e255f
ACO		 6600 WARN_ON(!crtc_state->base.state);
6601
5ab7b0b7 6602 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6603 refclk = 100000;
a93e255f 6604 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6605 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6606 refclk = dev_priv->vbt.lvds_ssc_freq;
6607 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6608 } else if (!IS_GEN2(dev)) {
6609 refclk = 96000;
6610 } else {
6611 refclk = 48000;
6612 }
6613
6614 return refclk;
6615}
6616
7429e9d4 6617static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6618{
7df00d7a 6619 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6620}
f47709a9 6621
7429e9d4
DV		 6622static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6623{
6624 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6625}
6626
f47709a9 6627static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6628 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6629 intel_clock_t *reduced_clock)
6630{
f47709a9 6631 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6632 u32 fp, fp2 = 0;
6633
6634 if (IS_PINEVIEW(dev)) {
190f68c5 6635 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6636 if (reduced_clock)
7429e9d4 6637 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6638 } else {
190f68c5 6639 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6640 if (reduced_clock)
7429e9d4 6641 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6642 }
6643
190f68c5 6644 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6645
f47709a9 6646 crtc->lowfreq_avail = false;
a93e255f 6647 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6648 reduced_clock) {
190f68c5 6649 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6650 crtc->lowfreq_avail = true;
a7516a05 6651 } else {
190f68c5 6652 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6653 }
6654}
6655
5e69f97f
CML		 6656static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6657 pipe)
89b667f8
JB		 6658{
6659 u32 reg_val;
6660
6661 /*
6662 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6663 * and set it to a reasonable value instead.
6664 */
ab3c759a 6665 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6666 reg_val &= 0xffffff00;
6667 reg_val |= 0x00000030;
ab3c759a 6668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6669
ab3c759a 6670 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6671 reg_val &= 0x8cffffff;
6672 reg_val = 0x8c000000;
ab3c759a 6673 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6674
ab3c759a 6675 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6676 reg_val &= 0xffffff00;
ab3c759a 6677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6678
ab3c759a 6679 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6680 reg_val &= 0x00ffffff;
6681 reg_val |= 0xb0000000;
ab3c759a 6682 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6683}
6684
b551842d
DV		 6685static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6686 struct intel_link_m_n *m_n)
6687{
6688 struct drm_device *dev = crtc->base.dev;
6689 struct drm_i915_private *dev_priv = dev->dev_private;
6690 int pipe = crtc->pipe;
6691
e3b95f1e
DV		 6692 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6693 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6694 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6695 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6696}
6697
6698static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6699 struct intel_link_m_n *m_n,
6700 struct intel_link_m_n *m2_n2)
b551842d
DV		 6701{
6702 struct drm_device *dev = crtc->base.dev;
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 int pipe = crtc->pipe;
6e3c9717 6705 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6706
6707 if (INTEL_INFO(dev)->gen >= 5) {
6708 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6709 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6710 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6711 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6712 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6713 * for gen < 8) and if DRRS is supported (to make sure the
6714 * registers are not unnecessarily accessed).
6715 */
44395bfe 6716 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6717 crtc->config->has_drrs) {
f769cd24
VK		 6718 I915_WRITE(PIPE_DATA_M2(transcoder),
6719 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6720 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6721 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6722 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6723 }
b551842d 6724 } else {
e3b95f1e
DV		 6725 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6726 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6727 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6728 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6729 }
6730}
6731
fe3cd48d 6732void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6733{
fe3cd48d
R		 6734 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6735
6736 if (m_n == M1_N1) {
6737 dp_m_n = &crtc->config->dp_m_n;
6738 dp_m2_n2 = &crtc->config->dp_m2_n2;
6739 } else if (m_n == M2_N2) {
6740
6741 /*
6742 * M2_N2 registers are not supported. Hence m2_n2 divider value
6743 * needs to be programmed into M1_N1.
6744 */
6745 dp_m_n = &crtc->config->dp_m2_n2;
6746 } else {
6747 DRM_ERROR("Unsupported divider value\n");
6748 return;
6749 }
6750
6e3c9717
ACO		 6751 if (crtc->config->has_pch_encoder)
6752 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6753 else
fe3cd48d 6754 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6755}
6756
d288f65f 6757static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6758 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6759{
6760 u32 dpll, dpll_md;
6761
6762 /*
6763 * Enable DPIO clock input. We should never disable the reference
6764 * clock for pipe B, since VGA hotplug / manual detection depends
6765 * on it.
6766 */
6767 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6768 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6769 /* We should never disable this, set it here for state tracking */
6770 if (crtc->pipe == PIPE_B)
6771 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6772 dpll |= DPLL_VCO_ENABLE;
d288f65f 6773 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6774
d288f65f 6775 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6776 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6777 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6778}
6779
d288f65f 6780static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6781 const struct intel_crtc_state *pipe_config)
a0c4da24 6782{
f47709a9 6783 struct drm_device *dev = crtc->base.dev;
a0c4da24 6784 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6785 int pipe = crtc->pipe;
bdd4b6a6 6786 u32 mdiv;
a0c4da24 6787 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6788 u32 coreclk, reg_val;
a0c4da24 6789
09153000
DV		 6790 mutex_lock(&dev_priv->dpio_lock);
6791
d288f65f
VS		 6792 bestn = pipe_config->dpll.n;
6793 bestm1 = pipe_config->dpll.m1;
6794 bestm2 = pipe_config->dpll.m2;
6795 bestp1 = pipe_config->dpll.p1;
6796 bestp2 = pipe_config->dpll.p2;
a0c4da24 6797
89b667f8
JB		 6798 /* See eDP HDMI DPIO driver vbios notes doc */
6799
6800 /* PLL B needs special handling */
bdd4b6a6 6801 if (pipe == PIPE_B)
5e69f97f 6802 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6803
6804 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6805 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6806
6807 /* Disable target IRef on PLL */
ab3c759a 6808 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6809 reg_val &= 0x00ffffff;
ab3c759a 6810 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6811
6812 /* Disable fast lock */
ab3c759a 6813 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6814
6815 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6816 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6817 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6818 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6819 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6820
6821 /*
6822 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6823 * but we don't support that).
6824 * Note: don't use the DAC post divider as it seems unstable.
6825 */
6826 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6828
a0c4da24 6829 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6831
89b667f8 6832 /* Set HBR and RBR LPF coefficients */
d288f65f 6833 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6834 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6835 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6836 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6837 0x009f0003);
89b667f8 6838 else
ab3c759a 6839 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6840 0x00d0000f);
6841
681a8504 6842 if (pipe_config->has_dp_encoder) {
89b667f8 6843 /* Use SSC source */
bdd4b6a6 6844 if (pipe == PIPE_A)
ab3c759a 6845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6846 0x0df40000);
6847 else
ab3c759a 6848 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6849 0x0df70000);
6850 } else { /* HDMI or VGA */
6851 /* Use bend source */
bdd4b6a6 6852 if (pipe == PIPE_A)
ab3c759a 6853 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6854 0x0df70000);
6855 else
ab3c759a 6856 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6857 0x0df40000);
6858 }
a0c4da24 6859
ab3c759a 6860 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6861 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6862 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6863 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6864 coreclk |= 0x01000000;
ab3c759a 6865 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6866
ab3c759a 6867 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6868 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6869}
6870
d288f65f 6871static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6872 struct intel_crtc_state *pipe_config)
1ae0d137 6873{
d288f65f 6874 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6875 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6876 DPLL_VCO_ENABLE;
6877 if (crtc->pipe != PIPE_A)
d288f65f 6878 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6879
d288f65f
VS		 6880 pipe_config->dpll_hw_state.dpll_md =
6881 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6882}
6883
d288f65f 6884static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6885 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6886{
6887 struct drm_device *dev = crtc->base.dev;
6888 struct drm_i915_private *dev_priv = dev->dev_private;
6889 int pipe = crtc->pipe;
6890 int dpll_reg = DPLL(crtc->pipe);
6891 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6892 u32 loopfilter, tribuf_calcntr;
9d556c99 6893 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6894 u32 dpio_val;
9cbe40c1 6895 int vco;
9d556c99 6896
d288f65f
VS		 6897 bestn = pipe_config->dpll.n;
6898 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6899 bestm1 = pipe_config->dpll.m1;
6900 bestm2 = pipe_config->dpll.m2 >> 22;
6901 bestp1 = pipe_config->dpll.p1;
6902 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6903 vco = pipe_config->dpll.vco;
a945ce7e 6904 dpio_val = 0;
9cbe40c1 6905 loopfilter = 0;
9d556c99
CML		 6906
6907 /*
6908 * Enable Refclk and SSC
6909 */
a11b0703 6910 I915_WRITE(dpll_reg,
d288f65f 6911 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6912
6913 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6914
9d556c99
CML		 6915 /* p1 and p2 divider */
6916 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6917 5 << DPIO_CHV_S1_DIV_SHIFT |
6918 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6919 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6920 1 << DPIO_CHV_K_DIV_SHIFT);
6921
6922 /* Feedback post-divider - m2 */
6923 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6924
6925 /* Feedback refclk divider - n and m1 */
6926 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6927 DPIO_CHV_M1_DIV_BY_2 |
6928 1 << DPIO_CHV_N_DIV_SHIFT);
6929
6930 /* M2 fraction division */
a945ce7e
VP		 6931 if (bestm2_frac)
6932 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6933
6934 /* M2 fraction division enable */
a945ce7e
VP		 6935 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6936 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6937 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6938 if (bestm2_frac)
6939 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6940 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6941
de3a0fde
VP		 6942 /* Program digital lock detect threshold */
6943 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6944 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6945 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6946 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6947 if (!bestm2_frac)
6948 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6949 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6950
9d556c99 6951 /* Loop filter */
9cbe40c1
VP		 6952 if (vco == 5400000) {
6953 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6954 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6955 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6956 tribuf_calcntr = 0x9;
6957 } else if (vco <= 6200000) {
6958 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6959 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6960 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6961 tribuf_calcntr = 0x9;
6962 } else if (vco <= 6480000) {
6963 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6964 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6965 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6966 tribuf_calcntr = 0x8;
6967 } else {
6968 /* Not supported. Apply the same limits as in the max case */
6969 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6970 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6971 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6972 tribuf_calcntr = 0;
6973 }
9d556c99
CML		 6974 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6975
968040b2 6976 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6977 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6978 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6979 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6980
9d556c99
CML		 6981 /* AFC Recal */
6982 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6983 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6984 DPIO_AFC_RECAL);
6985
6986 mutex_unlock(&dev_priv->dpio_lock);
6987}
6988
d288f65f
VS		 6989/**
6990 * vlv_force_pll_on - forcibly enable just the PLL
6991 * @dev_priv: i915 private structure
6992 * @pipe: pipe PLL to enable
6993 * @dpll: PLL configuration
6994 *
6995 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6996 * in cases where we need the PLL enabled even when @pipe is not going to
6997 * be enabled.
6998 */
6999void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7000 const struct dpll *dpll)
7001{
7002 struct intel_crtc *crtc =
7003 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7004 struct intel_crtc_state pipe_config = {
a93e255f 7005 .base.crtc = &crtc->base,
d288f65f
VS		 7006 .pixel_multiplier = 1,
7007 .dpll = *dpll,
7008 };
7009
7010 if (IS_CHERRYVIEW(dev)) {
7011 chv_update_pll(crtc, &pipe_config);
7012 chv_prepare_pll(crtc, &pipe_config);
7013 chv_enable_pll(crtc, &pipe_config);
7014 } else {
7015 vlv_update_pll(crtc, &pipe_config);
7016 vlv_prepare_pll(crtc, &pipe_config);
7017 vlv_enable_pll(crtc, &pipe_config);
7018 }
7019}
7020
7021/**
7022 * vlv_force_pll_off - forcibly disable just the PLL
7023 * @dev_priv: i915 private structure
7024 * @pipe: pipe PLL to disable
7025 *
7026 * Disable the PLL for @pipe. To be used in cases where we need
7027 * the PLL enabled even when @pipe is not going to be enabled.
7028 */
7029void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7030{
7031 if (IS_CHERRYVIEW(dev))
7032 chv_disable_pll(to_i915(dev), pipe);
7033 else
7034 vlv_disable_pll(to_i915(dev), pipe);
7035}
7036
f47709a9 7037static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7038 struct intel_crtc_state *crtc_state,
f47709a9 7039 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7040 int num_connectors)
7041{
f47709a9 7042 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7043 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7044 u32 dpll;
7045 bool is_sdvo;
190f68c5 7046 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7047
190f68c5 7048 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7049
a93e255f
ACO		 7050 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7051 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7052
7053 dpll = DPLL_VGA_MODE_DIS;
7054
a93e255f 7055 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7056 dpll |= DPLLB_MODE_LVDS;
7057 else
7058 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7059
ef1b460d 7060 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7061 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7062 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7063 }
198a037f
DV		 7064
7065 if (is_sdvo)
4a33e48d 7066 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7067
190f68c5 7068 if (crtc_state->has_dp_encoder)
4a33e48d 7069 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7070
7071 /* compute bitmask from p1 value */
7072 if (IS_PINEVIEW(dev))
7073 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7074 else {
7075 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7076 if (IS_G4X(dev) && reduced_clock)
7077 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7078 }
7079 switch (clock->p2) {
7080 case 5:
7081 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7082 break;
7083 case 7:
7084 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7085 break;
7086 case 10:
7087 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7088 break;
7089 case 14:
7090 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7091 break;
7092 }
7093 if (INTEL_INFO(dev)->gen >= 4)
7094 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7095
190f68c5 7096 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7097 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7098 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7099 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7100 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7101 else
7102 dpll |= PLL_REF_INPUT_DREFCLK;
7103
7104 dpll |= DPLL_VCO_ENABLE;
190f68c5 7105 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7106
eb1cbe48 7107 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7108 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7109 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7110 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7111 }
7112}
7113
f47709a9 7114static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7115 struct intel_crtc_state *crtc_state,
f47709a9 7116 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7117 int num_connectors)
7118{
f47709a9 7119 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7120 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7121 u32 dpll;
190f68c5 7122 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7123
190f68c5 7124 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7125
eb1cbe48
DV		 7126 dpll = DPLL_VGA_MODE_DIS;
7127
a93e255f 7128 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7129 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7130 } else {
7131 if (clock->p1 == 2)
7132 dpll |= PLL_P1_DIVIDE_BY_TWO;
7133 else
7134 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7135 if (clock->p2 == 4)
7136 dpll |= PLL_P2_DIVIDE_BY_4;
7137 }
7138
a93e255f 7139 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7140 dpll |= DPLL_DVO_2X_MODE;
7141
a93e255f 7142 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7143 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7144 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7145 else
7146 dpll |= PLL_REF_INPUT_DREFCLK;
7147
7148 dpll |= DPLL_VCO_ENABLE;
190f68c5 7149 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7150}
7151
8a654f3b 7152static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7153{
7154 struct drm_device *dev = intel_crtc->base.dev;
7155 struct drm_i915_private *dev_priv = dev->dev_private;
7156 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7157 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7158 struct drm_display_mode *adjusted_mode =
6e3c9717 7159 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7160 uint32_t crtc_vtotal, crtc_vblank_end;
7161 int vsyncshift = 0;
4d8a62ea
DV		 7162
7163 /* We need to be careful not to changed the adjusted mode, for otherwise
7164 * the hw state checker will get angry at the mismatch. */
7165 crtc_vtotal = adjusted_mode->crtc_vtotal;
7166 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7167
609aeaca 7168 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7169 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7170 crtc_vtotal -= 1;
7171 crtc_vblank_end -= 1;
609aeaca 7172
409ee761 7173 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7174 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7175 else
7176 vsyncshift = adjusted_mode->crtc_hsync_start -
7177 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7178 if (vsyncshift < 0)
7179 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7180 }
7181
7182 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7183 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7184
fe2b8f9d 7185 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7186 (adjusted_mode->crtc_hdisplay - 1) |
7187 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7188 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7189 (adjusted_mode->crtc_hblank_start - 1) |
7190 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7191 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7192 (adjusted_mode->crtc_hsync_start - 1) |
7193 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7194
fe2b8f9d 7195 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7196 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7197 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7198 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7199 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7200 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7201 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7202 (adjusted_mode->crtc_vsync_start - 1) |
7203 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7204
b5e508d4
PZ		 7205 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7206 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7207 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7208 * bits. */
7209 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7210 (pipe == PIPE_B || pipe == PIPE_C))
7211 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7212
b0e77b9c
PZ		 7213 /* pipesrc controls the size that is scaled from, which should
7214 * always be the user's requested size.
7215 */
7216 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7217 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7218 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7219}
7220
1bd1bd80 7221static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7222 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7223{
7224 struct drm_device *dev = crtc->base.dev;
7225 struct drm_i915_private *dev_priv = dev->dev_private;
7226 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7227 uint32_t tmp;
7228
7229 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7230 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7231 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7232 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7233 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7234 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7235 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7236 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7237 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7238
7239 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7240 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7241 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7242 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7243 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7244 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7245 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7246 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7247 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7248
7249 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7250 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7251 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7252 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7253 }
7254
7255 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7256 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7257 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7258
2d112de7
ACO		 7259 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7260 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7261}
7262
f6a83288 7263void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7264 struct intel_crtc_state *pipe_config)
babea61d 7265{
2d112de7
ACO		 7266 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7267 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7268 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7269 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7270
2d112de7
ACO		 7271 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7272 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7273 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7274 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7275
2d112de7 7276 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7277
2d112de7
ACO		 7278 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7279 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7280}
7281
84b046f3
DV		 7282static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7283{
7284 struct drm_device *dev = intel_crtc->base.dev;
7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 uint32_t pipeconf;
7287
9f11a9e4 7288 pipeconf = 0;
84b046f3 7289
b6b5d049
VS		 7290 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7291 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7292 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7293
6e3c9717 7294 if (intel_crtc->config->double_wide)
cf532bb2 7295 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7296
ff9ce46e
DV		 7297 /* only g4x and later have fancy bpc/dither controls */
7298 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7299 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7300 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7301 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7302 PIPECONF_DITHER_TYPE_SP;
84b046f3 7303
6e3c9717 7304 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7305 case 18:
7306 pipeconf |= PIPECONF_6BPC;
7307 break;
7308 case 24:
7309 pipeconf |= PIPECONF_8BPC;
7310 break;
7311 case 30:
7312 pipeconf |= PIPECONF_10BPC;
7313 break;
7314 default:
7315 /* Case prevented by intel_choose_pipe_bpp_dither. */
7316 BUG();
84b046f3
DV		 7317 }
7318 }
7319
7320 if (HAS_PIPE_CXSR(dev)) {
7321 if (intel_crtc->lowfreq_avail) {
7322 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7323 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7324 } else {
7325 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7326 }
7327 }
7328
6e3c9717 7329 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7330 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7331 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7332 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7333 else
7334 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7335 } else
84b046f3
DV		 7336 pipeconf |= PIPECONF_PROGRESSIVE;
7337
6e3c9717 7338 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7339 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7340
84b046f3
DV		 7341 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7342 POSTING_READ(PIPECONF(intel_crtc->pipe));
7343}
7344
190f68c5
ACO		 7345static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7346 struct intel_crtc_state *crtc_state)
79e53945 7347{
c7653199 7348 struct drm_device *dev = crtc->base.dev;
79e53945 7349 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7350 int refclk, num_connectors = 0;
652c393a 7351 intel_clock_t clock, reduced_clock;
a16af721 7352 bool ok, has_reduced_clock = false;
e9fd1c02 7353 bool is_lvds = false, is_dsi = false;
5eddb70b 7354 struct intel_encoder *encoder;
d4906093 7355 const intel_limit_t *limit;
55bb9992
ACO		 7356 struct drm_atomic_state *state = crtc_state->base.state;
7357 struct drm_connector_state *connector_state;
7358 int i;
79e53945 7359
55bb9992
ACO		 7360 for (i = 0; i < state->num_connector; i++) {
7361 if (!state->connectors[i])
d0737e1d
ACO		 7362 continue;
7363
55bb9992
ACO		 7364 connector_state = state->connector_states[i];
7365 if (connector_state->crtc != &crtc->base)
7366 continue;
7367
7368 encoder = to_intel_encoder(connector_state->best_encoder);
7369
5eddb70b 7370 switch (encoder->type) {
79e53945
JB		 7371 case INTEL_OUTPUT_LVDS:
7372 is_lvds = true;
7373 break;
e9fd1c02
JN		 7374 case INTEL_OUTPUT_DSI:
7375 is_dsi = true;
7376 break;
6847d71b
PZ		 7377 default:
7378 break;
79e53945 7379 }
43565a06 7380
c751ce4f 7381 num_connectors++;
79e53945
JB		 7382 }
7383
f2335330 7384 if (is_dsi)
5b18e57c 7385 return 0;
f2335330 7386
190f68c5 7387 if (!crtc_state->clock_set) {
a93e255f 7388 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7389
e9fd1c02
JN		 7390 /*
7391 * Returns a set of divisors for the desired target clock with
7392 * the given refclk, or FALSE. The returned values represent
7393 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7394 * 2) / p1 / p2.
7395 */
a93e255f
ACO		 7396 limit = intel_limit(crtc_state, refclk);
7397 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7398 crtc_state->port_clock,
e9fd1c02 7399 refclk, NULL, &clock);
f2335330 7400 if (!ok) {
e9fd1c02
JN		 7401 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7402 return -EINVAL;
7403 }
79e53945 7404
f2335330
JN		 7405 if (is_lvds && dev_priv->lvds_downclock_avail) {
7406 /*
7407 * Ensure we match the reduced clock's P to the target
7408 * clock. If the clocks don't match, we can't switch
7409 * the display clock by using the FP0/FP1. In such case
7410 * we will disable the LVDS downclock feature.
7411 */
7412 has_reduced_clock =
a93e255f 7413 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7414 dev_priv->lvds_downclock,
7415 refclk, &clock,
7416 &reduced_clock);
7417 }
7418 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7419 crtc_state->dpll.n = clock.n;
7420 crtc_state->dpll.m1 = clock.m1;
7421 crtc_state->dpll.m2 = clock.m2;
7422 crtc_state->dpll.p1 = clock.p1;
7423 crtc_state->dpll.p2 = clock.p2;
f47709a9 7424 }
7026d4ac 7425
e9fd1c02 7426 if (IS_GEN2(dev)) {
190f68c5 7427 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7428 has_reduced_clock ? &reduced_clock : NULL,
7429 num_connectors);
9d556c99 7430 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7431 chv_update_pll(crtc, crtc_state);
e9fd1c02 7432 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7433 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7434 } else {
190f68c5 7435 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7436 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7437 num_connectors);
e9fd1c02 7438 }
79e53945 7439
c8f7a0db 7440 return 0;
f564048e
EA		 7441}
7442
2fa2fe9a 7443static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7444 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7445{
7446 struct drm_device *dev = crtc->base.dev;
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 uint32_t tmp;
7449
dc9e7dec
VS		 7450 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7451 return;
7452
2fa2fe9a 7453 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7454 if (!(tmp & PFIT_ENABLE))
7455 return;
2fa2fe9a 7456
06922821 7457 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7458 if (INTEL_INFO(dev)->gen < 4) {
7459 if (crtc->pipe != PIPE_B)
7460 return;
2fa2fe9a
DV		 7461 } else {
7462 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7463 return;
7464 }
7465
06922821 7466 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7467 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7468 if (INTEL_INFO(dev)->gen < 5)
7469 pipe_config->gmch_pfit.lvds_border_bits =
7470 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7471}
7472
acbec814 7473static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7474 struct intel_crtc_state *pipe_config)
acbec814
JB		 7475{
7476 struct drm_device *dev = crtc->base.dev;
7477 struct drm_i915_private *dev_priv = dev->dev_private;
7478 int pipe = pipe_config->cpu_transcoder;
7479 intel_clock_t clock;
7480 u32 mdiv;
662c6ecb 7481 int refclk = 100000;
acbec814 7482
f573de5a
SK		 7483 /* In case of MIPI DPLL will not even be used */
7484 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7485 return;
7486
acbec814 7487 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7488 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7489 mutex_unlock(&dev_priv->dpio_lock);
7490
7491 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7492 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7493 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7494 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7495 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7496
f646628b 7497 vlv_clock(refclk, &clock);
acbec814 7498
f646628b
VS		 7499 /* clock.dot is the fast clock */
7500 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7501}
7502
5724dbd1
DL		 7503static void
7504i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7505 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7506{
7507 struct drm_device *dev = crtc->base.dev;
7508 struct drm_i915_private *dev_priv = dev->dev_private;
7509 u32 val, base, offset;
7510 int pipe = crtc->pipe, plane = crtc->plane;
7511 int fourcc, pixel_format;
6761dd31 7512 unsigned int aligned_height;
b113d5ee 7513 struct drm_framebuffer *fb;
1b842c89 7514 struct intel_framebuffer *intel_fb;
1ad292b5 7515
42a7b088
DL		 7516 val = I915_READ(DSPCNTR(plane));
7517 if (!(val & DISPLAY_PLANE_ENABLE))
7518 return;
7519
d9806c9f 7520 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7521 if (!intel_fb) {
1ad292b5
JB		 7522 DRM_DEBUG_KMS("failed to alloc fb\n");
7523 return;
7524 }
7525
1b842c89
DL		 7526 fb = &intel_fb->base;
7527
18c5247e
DV		 7528 if (INTEL_INFO(dev)->gen >= 4) {
7529 if (val & DISPPLANE_TILED) {
49af449b 7530 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7531 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7532 }
7533 }
1ad292b5
JB		 7534
7535 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7536 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7537 fb->pixel_format = fourcc;
7538 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7539
7540 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7541 if (plane_config->tiling)
1ad292b5
JB		 7542 offset = I915_READ(DSPTILEOFF(plane));
7543 else
7544 offset = I915_READ(DSPLINOFF(plane));
7545 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7546 } else {
7547 base = I915_READ(DSPADDR(plane));
7548 }
7549 plane_config->base = base;
7550
7551 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7552 fb->width = ((val >> 16) & 0xfff) + 1;
7553 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7554
7555 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7556 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7557
b113d5ee 7558 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7559 fb->pixel_format,
7560 fb->modifier[0]);
1ad292b5 7561
f37b5c2b 7562 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7563
2844a921
DL		 7564 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7565 pipe_name(pipe), plane, fb->width, fb->height,
7566 fb->bits_per_pixel, base, fb->pitches[0],
7567 plane_config->size);
1ad292b5 7568
2d14030b 7569 plane_config->fb = intel_fb;
1ad292b5
JB		 7570}
7571
70b23a98 7572static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7573 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7574{
7575 struct drm_device *dev = crtc->base.dev;
7576 struct drm_i915_private *dev_priv = dev->dev_private;
7577 int pipe = pipe_config->cpu_transcoder;
7578 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7579 intel_clock_t clock;
7580 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7581 int refclk = 100000;
7582
7583 mutex_lock(&dev_priv->dpio_lock);
7584 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7585 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7586 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7587 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7588 mutex_unlock(&dev_priv->dpio_lock);
7589
7590 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7591 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7592 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7593 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7594 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7595
7596 chv_clock(refclk, &clock);
7597
7598 /* clock.dot is the fast clock */
7599 pipe_config->port_clock = clock.dot / 5;
7600}
7601
0e8ffe1b 7602static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7603 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7604{
7605 struct drm_device *dev = crtc->base.dev;
7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607 uint32_t tmp;
7608
f458ebbc
DV		 7609 if (!intel_display_power_is_enabled(dev_priv,
7610 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7611 return false;
7612
e143a21c 7613 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7614 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7615
0e8ffe1b
DV		 7616 tmp = I915_READ(PIPECONF(crtc->pipe));
7617 if (!(tmp & PIPECONF_ENABLE))
7618 return false;
7619
42571aef
VS		 7620 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7621 switch (tmp & PIPECONF_BPC_MASK) {
7622 case PIPECONF_6BPC:
7623 pipe_config->pipe_bpp = 18;
7624 break;
7625 case PIPECONF_8BPC:
7626 pipe_config->pipe_bpp = 24;
7627 break;
7628 case PIPECONF_10BPC:
7629 pipe_config->pipe_bpp = 30;
7630 break;
7631 default:
7632 break;
7633 }
7634 }
7635
b5a9fa09
DV		 7636 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7637 pipe_config->limited_color_range = true;
7638
282740f7
VS		 7639 if (INTEL_INFO(dev)->gen < 4)
7640 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7641
1bd1bd80
DV		 7642 intel_get_pipe_timings(crtc, pipe_config);
7643
2fa2fe9a
DV		 7644 i9xx_get_pfit_config(crtc, pipe_config);
7645
6c49f241
DV		 7646 if (INTEL_INFO(dev)->gen >= 4) {
7647 tmp = I915_READ(DPLL_MD(crtc->pipe));
7648 pipe_config->pixel_multiplier =
7649 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7650 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7651 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7652 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7653 tmp = I915_READ(DPLL(crtc->pipe));
7654 pipe_config->pixel_multiplier =
7655 ((tmp & SDVO_MULTIPLIER_MASK)
7656 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7657 } else {
7658 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7659 * port and will be fixed up in the encoder->get_config
7660 * function. */
7661 pipe_config->pixel_multiplier = 1;
7662 }
8bcc2795
DV		 7663 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7664 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7665 /*
7666 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7667 * on 830. Filter it out here so that we don't
7668 * report errors due to that.
7669 */
7670 if (IS_I830(dev))
7671 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7672
8bcc2795
DV		 7673 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7674 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7675 } else {
7676 /* Mask out read-only status bits. */
7677 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7678 DPLL_PORTC_READY_MASK |
7679 DPLL_PORTB_READY_MASK);
8bcc2795 7680 }
6c49f241 7681
70b23a98
VS		 7682 if (IS_CHERRYVIEW(dev))
7683 chv_crtc_clock_get(crtc, pipe_config);
7684 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7685 vlv_crtc_clock_get(crtc, pipe_config);
7686 else
7687 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7688
0e8ffe1b
DV		 7689 return true;
7690}
7691
dde86e2d 7692static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7693{
7694 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7695 struct intel_encoder *encoder;
74cfd7ac 7696 u32 val, final;
13d83a67 7697 bool has_lvds = false;
199e5d79 7698 bool has_cpu_edp = false;
199e5d79 7699 bool has_panel = false;
99eb6a01
KP		 7700 bool has_ck505 = false;
7701 bool can_ssc = false;
13d83a67
JB		 7702
7703 /* We need to take the global config into account */
b2784e15 7704 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7705 switch (encoder->type) {
7706 case INTEL_OUTPUT_LVDS:
7707 has_panel = true;
7708 has_lvds = true;
7709 break;
7710 case INTEL_OUTPUT_EDP:
7711 has_panel = true;
2de6905f 7712 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7713 has_cpu_edp = true;
7714 break;
6847d71b
PZ		 7715 default:
7716 break;
13d83a67
JB		 7717 }
7718 }
7719
99eb6a01 7720 if (HAS_PCH_IBX(dev)) {
41aa3448 7721 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7722 can_ssc = has_ck505;
7723 } else {
7724 has_ck505 = false;
7725 can_ssc = true;
7726 }
7727
2de6905f
ID		 7728 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7729 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7730
7731 /* Ironlake: try to setup display ref clock before DPLL
7732 * enabling. This is only under driver's control after
7733 * PCH B stepping, previous chipset stepping should be
7734 * ignoring this setting.
7735 */
74cfd7ac
CW		 7736 val = I915_READ(PCH_DREF_CONTROL);
7737
7738 /* As we must carefully and slowly disable/enable each source in turn,
7739 * compute the final state we want first and check if we need to
7740 * make any changes at all.
7741 */
7742 final = val;
7743 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7744 if (has_ck505)
7745 final |= DREF_NONSPREAD_CK505_ENABLE;
7746 else
7747 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7748
7749 final &= ~DREF_SSC_SOURCE_MASK;
7750 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7751 final &= ~DREF_SSC1_ENABLE;
7752
7753 if (has_panel) {
7754 final |= DREF_SSC_SOURCE_ENABLE;
7755
7756 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7757 final |= DREF_SSC1_ENABLE;
7758
7759 if (has_cpu_edp) {
7760 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7761 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7762 else
7763 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7764 } else
7765 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7766 } else {
7767 final |= DREF_SSC_SOURCE_DISABLE;
7768 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7769 }
7770
7771 if (final == val)
7772 return;
7773
13d83a67 7774 /* Always enable nonspread source */
74cfd7ac 7775 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7776
99eb6a01 7777 if (has_ck505)
74cfd7ac 7778 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7779 else
74cfd7ac 7780 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7781
199e5d79 7782 if (has_panel) {
74cfd7ac
CW		 7783 val &= ~DREF_SSC_SOURCE_MASK;
7784 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7785
199e5d79 7786 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7787 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7788 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7789 val |= DREF_SSC1_ENABLE;
e77166b5 7790 } else
74cfd7ac 7791 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7792
7793 /* Get SSC going before enabling the outputs */
74cfd7ac 7794 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7795 POSTING_READ(PCH_DREF_CONTROL);
7796 udelay(200);
7797
74cfd7ac 7798 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7799
7800 /* Enable CPU source on CPU attached eDP */
199e5d79 7801 if (has_cpu_edp) {
99eb6a01 7802 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7803 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7804 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7805 } else
74cfd7ac 7806 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7807 } else
74cfd7ac 7808 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7809
74cfd7ac 7810 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7811 POSTING_READ(PCH_DREF_CONTROL);
7812 udelay(200);
7813 } else {
7814 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7815
74cfd7ac 7816 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7817
7818 /* Turn off CPU output */
74cfd7ac 7819 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7820
74cfd7ac 7821 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7822 POSTING_READ(PCH_DREF_CONTROL);
7823 udelay(200);
7824
7825 /* Turn off the SSC source */
74cfd7ac
CW		 7826 val &= ~DREF_SSC_SOURCE_MASK;
7827 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7828
7829 /* Turn off SSC1 */
74cfd7ac 7830 val &= ~DREF_SSC1_ENABLE;
199e5d79 7831
74cfd7ac 7832 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7833 POSTING_READ(PCH_DREF_CONTROL);
7834 udelay(200);
7835 }
74cfd7ac
CW		 7836
7837 BUG_ON(val != final);
13d83a67
JB		 7838}
7839
f31f2d55 7840static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7841{
f31f2d55 7842 uint32_t tmp;
dde86e2d 7843
0ff066a9
PZ		 7844 tmp = I915_READ(SOUTH_CHICKEN2);
7845 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7846 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7847
0ff066a9
PZ		 7848 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7849 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7850 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7851
0ff066a9
PZ		 7852 tmp = I915_READ(SOUTH_CHICKEN2);
7853 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7854 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7855
0ff066a9
PZ		 7856 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7857 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7858 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7859}
7860
7861/* WaMPhyProgramming:hsw */
7862static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7863{
7864 uint32_t tmp;
dde86e2d
PZ		 7865
7866 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7867 tmp &= ~(0xFF << 24);
7868 tmp |= (0x12 << 24);
7869 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7870
dde86e2d
PZ		 7871 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7872 tmp |= (1 << 11);
7873 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7874
7875 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7876 tmp |= (1 << 11);
7877 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7878
dde86e2d
PZ		 7879 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7880 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7881 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7882
7883 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7884 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7885 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7886
0ff066a9
PZ		 7887 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7888 tmp &= ~(7 << 13);
7889 tmp |= (5 << 13);
7890 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7891
0ff066a9
PZ		 7892 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7893 tmp &= ~(7 << 13);
7894 tmp |= (5 << 13);
7895 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7896
7897 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7898 tmp &= ~0xFF;
7899 tmp |= 0x1C;
7900 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7901
7902 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7903 tmp &= ~0xFF;
7904 tmp |= 0x1C;
7905 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7906
7907 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7908 tmp &= ~(0xFF << 16);
7909 tmp |= (0x1C << 16);
7910 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7911
7912 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7913 tmp &= ~(0xFF << 16);
7914 tmp |= (0x1C << 16);
7915 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7916
0ff066a9
PZ		 7917 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7918 tmp |= (1 << 27);
7919 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7920
0ff066a9
PZ		 7921 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7922 tmp |= (1 << 27);
7923 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7924
0ff066a9
PZ		 7925 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7926 tmp &= ~(0xF << 28);
7927 tmp |= (4 << 28);
7928 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7929
0ff066a9
PZ		 7930 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7931 tmp &= ~(0xF << 28);
7932 tmp |= (4 << 28);
7933 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7934}
7935
2fa86a1f
PZ		 7936/* Implements 3 different sequences from BSpec chapter "Display iCLK
7937 * Programming" based on the parameters passed:
7938 * - Sequence to enable CLKOUT_DP
7939 * - Sequence to enable CLKOUT_DP without spread
7940 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7941 */
7942static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7943 bool with_fdi)
f31f2d55
PZ		 7944{
7945 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7946 uint32_t reg, tmp;
7947
7948 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7949 with_spread = true;
7950 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7951 with_fdi, "LP PCH doesn't have FDI\n"))
7952 with_fdi = false;
f31f2d55
PZ		 7953
7954 mutex_lock(&dev_priv->dpio_lock);
7955
7956 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7957 tmp &= ~SBI_SSCCTL_DISABLE;
7958 tmp |= SBI_SSCCTL_PATHALT;
7959 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7960
7961 udelay(24);
7962
2fa86a1f
PZ		 7963 if (with_spread) {
7964 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7965 tmp &= ~SBI_SSCCTL_PATHALT;
7966 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7967
2fa86a1f
PZ		 7968 if (with_fdi) {
7969 lpt_reset_fdi_mphy(dev_priv);
7970 lpt_program_fdi_mphy(dev_priv);
7971 }
7972 }
dde86e2d 7973
2fa86a1f
PZ		 7974 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7975 SBI_GEN0 : SBI_DBUFF0;
7976 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7977 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7978 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7979
7980 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7981}
7982
47701c3b
PZ		 7983/* Sequence to disable CLKOUT_DP */
7984static void lpt_disable_clkout_dp(struct drm_device *dev)
7985{
7986 struct drm_i915_private *dev_priv = dev->dev_private;
7987 uint32_t reg, tmp;
7988
7989 mutex_lock(&dev_priv->dpio_lock);
7990
7991 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7992 SBI_GEN0 : SBI_DBUFF0;
7993 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7994 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7995 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7996
7997 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7998 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7999 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8000 tmp |= SBI_SSCCTL_PATHALT;
8001 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8002 udelay(32);
8003 }
8004 tmp |= SBI_SSCCTL_DISABLE;
8005 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8006 }
8007
8008 mutex_unlock(&dev_priv->dpio_lock);
8009}
8010
bf8fa3d3
PZ		 8011static void lpt_init_pch_refclk(struct drm_device *dev)
8012{
bf8fa3d3
PZ		 8013 struct intel_encoder *encoder;
8014 bool has_vga = false;
8015
b2784e15 8016 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8017 switch (encoder->type) {
8018 case INTEL_OUTPUT_ANALOG:
8019 has_vga = true;
8020 break;
6847d71b
PZ		 8021 default:
8022 break;
bf8fa3d3
PZ		 8023 }
8024 }
8025
47701c3b
PZ		 8026 if (has_vga)
8027 lpt_enable_clkout_dp(dev, true, true);
8028 else
8029 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8030}
8031
dde86e2d
PZ		 8032/*
8033 * Initialize reference clocks when the driver loads
8034 */
8035void intel_init_pch_refclk(struct drm_device *dev)
8036{
8037 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8038 ironlake_init_pch_refclk(dev);
8039 else if (HAS_PCH_LPT(dev))
8040 lpt_init_pch_refclk(dev);
8041}
8042
55bb9992 8043static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8044{
55bb9992 8045 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8046 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8047 struct drm_atomic_state *state = crtc_state->base.state;
8048 struct drm_connector_state *connector_state;
d9d444cb 8049 struct intel_encoder *encoder;
55bb9992 8050 int num_connectors = 0, i;
d9d444cb
JB		 8051 bool is_lvds = false;
8052
55bb9992
ACO		 8053 for (i = 0; i < state->num_connector; i++) {
8054 if (!state->connectors[i])
d0737e1d
ACO		 8055 continue;
8056
55bb9992
ACO		 8057 connector_state = state->connector_states[i];
8058 if (connector_state->crtc != crtc_state->base.crtc)
8059 continue;
8060
8061 encoder = to_intel_encoder(connector_state->best_encoder);
8062
d9d444cb
JB		 8063 switch (encoder->type) {
8064 case INTEL_OUTPUT_LVDS:
8065 is_lvds = true;
8066 break;
6847d71b
PZ		 8067 default:
8068 break;
d9d444cb
JB		 8069 }
8070 num_connectors++;
8071 }
8072
8073 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8074 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8075 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8076 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8077 }
8078
8079 return 120000;
8080}
8081
6ff93609 8082static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8083{
c8203565 8084 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8086 int pipe = intel_crtc->pipe;
c8203565
PZ		 8087 uint32_t val;
8088
78114071 8089 val = 0;
c8203565 8090
6e3c9717 8091 switch (intel_crtc->config->pipe_bpp) {
c8203565 8092 case 18:
dfd07d72 8093 val |= PIPECONF_6BPC;
c8203565
PZ		 8094 break;
8095 case 24:
dfd07d72 8096 val |= PIPECONF_8BPC;
c8203565
PZ		 8097 break;
8098 case 30:
dfd07d72 8099 val |= PIPECONF_10BPC;
c8203565
PZ		 8100 break;
8101 case 36:
dfd07d72 8102 val |= PIPECONF_12BPC;
c8203565
PZ		 8103 break;
8104 default:
cc769b62
PZ		 8105 /* Case prevented by intel_choose_pipe_bpp_dither. */
8106 BUG();
c8203565
PZ		 8107 }
8108
6e3c9717 8109 if (intel_crtc->config->dither)
c8203565
PZ		 8110 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8111
6e3c9717 8112 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8113 val |= PIPECONF_INTERLACED_ILK;
8114 else
8115 val |= PIPECONF_PROGRESSIVE;
8116
6e3c9717 8117 if (intel_crtc->config->limited_color_range)
3685a8f3 8118 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8119
c8203565
PZ		 8120 I915_WRITE(PIPECONF(pipe), val);
8121 POSTING_READ(PIPECONF(pipe));
8122}
8123
86d3efce
VS		 8124/*
8125 * Set up the pipe CSC unit.
8126 *
8127 * Currently only full range RGB to limited range RGB conversion
8128 * is supported, but eventually this should handle various
8129 * RGB<->YCbCr scenarios as well.
8130 */
50f3b016 8131static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8132{
8133 struct drm_device *dev = crtc->dev;
8134 struct drm_i915_private *dev_priv = dev->dev_private;
8135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8136 int pipe = intel_crtc->pipe;
8137 uint16_t coeff = 0x7800; /* 1.0 */
8138
8139 /*
8140 * TODO: Check what kind of values actually come out of the pipe
8141 * with these coeff/postoff values and adjust to get the best
8142 * accuracy. Perhaps we even need to take the bpc value into
8143 * consideration.
8144 */
8145
6e3c9717 8146 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8147 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8148
8149 /*
8150 * GY/GU and RY/RU should be the other way around according
8151 * to BSpec, but reality doesn't agree. Just set them up in
8152 * a way that results in the correct picture.
8153 */
8154 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8155 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8156
8157 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8158 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8159
8160 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8161 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8162
8163 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8164 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8165 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8166
8167 if (INTEL_INFO(dev)->gen > 6) {
8168 uint16_t postoff = 0;
8169
6e3c9717 8170 if (intel_crtc->config->limited_color_range)
32cf0cb0 8171 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8172
8173 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8174 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8175 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8176
8177 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8178 } else {
8179 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8180
6e3c9717 8181 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8182 mode |= CSC_BLACK_SCREEN_OFFSET;
8183
8184 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8185 }
8186}
8187
6ff93609 8188static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8189{
756f85cf
PZ		 8190 struct drm_device *dev = crtc->dev;
8191 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8193 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8194 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8195 uint32_t val;
8196
3eff4faa 8197 val = 0;
ee2b0b38 8198
6e3c9717 8199 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8200 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8201
6e3c9717 8202 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8203 val |= PIPECONF_INTERLACED_ILK;
8204 else
8205 val |= PIPECONF_PROGRESSIVE;
8206
702e7a56
PZ		 8207 I915_WRITE(PIPECONF(cpu_transcoder), val);
8208 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8209
8210 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8211 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8212
3cdf122c 8213 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8214 val = 0;
8215
6e3c9717 8216 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8217 case 18:
8218 val |= PIPEMISC_DITHER_6_BPC;
8219 break;
8220 case 24:
8221 val |= PIPEMISC_DITHER_8_BPC;
8222 break;
8223 case 30:
8224 val |= PIPEMISC_DITHER_10_BPC;
8225 break;
8226 case 36:
8227 val |= PIPEMISC_DITHER_12_BPC;
8228 break;
8229 default:
8230 /* Case prevented by pipe_config_set_bpp. */
8231 BUG();
8232 }
8233
6e3c9717 8234 if (intel_crtc->config->dither)
756f85cf
PZ		 8235 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8236
8237 I915_WRITE(PIPEMISC(pipe), val);
8238 }
ee2b0b38
PZ		 8239}
8240
6591c6e4 8241static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8242 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8243 intel_clock_t *clock,
8244 bool *has_reduced_clock,
8245 intel_clock_t *reduced_clock)
8246{
8247 struct drm_device *dev = crtc->dev;
8248 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8249 int refclk;
d4906093 8250 const intel_limit_t *limit;
a16af721 8251 bool ret, is_lvds = false;
79e53945 8252
a93e255f 8253 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8254
55bb9992 8255 refclk = ironlake_get_refclk(crtc_state);
79e53945 8256
d4906093
ML		 8257 /*
8258 * Returns a set of divisors for the desired target clock with the given
8259 * refclk, or FALSE. The returned values represent the clock equation:
8260 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8261 */
a93e255f
ACO		 8262 limit = intel_limit(crtc_state, refclk);
8263 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8264 crtc_state->port_clock,
ee9300bb 8265 refclk, NULL, clock);
6591c6e4
PZ		 8266 if (!ret)
8267 return false;
cda4b7d3 8268
ddc9003c 8269 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8270 /*
8271 * Ensure we match the reduced clock's P to the target clock.
8272 * If the clocks don't match, we can't switch the display clock
8273 * by using the FP0/FP1. In such case we will disable the LVDS
8274 * downclock feature.
8275 */
ee9300bb 8276 *has_reduced_clock =
a93e255f 8277 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8278 dev_priv->lvds_downclock,
8279 refclk, clock,
8280 reduced_clock);
652c393a 8281 }
61e9653f 8282
6591c6e4
PZ		 8283 return true;
8284}
8285
d4b1931c
PZ		 8286int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8287{
8288 /*
8289 * Account for spread spectrum to avoid
8290 * oversubscribing the link. Max center spread
8291 * is 2.5%; use 5% for safety's sake.
8292 */
8293 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8294 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8295}
8296
7429e9d4 8297static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8298{
7429e9d4 8299 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8300}
8301
de13a2e3 8302static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8303 struct intel_crtc_state *crtc_state,
7429e9d4 8304 u32 *fp,
9a7c7890 8305 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8306{
de13a2e3 8307 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8308 struct drm_device *dev = crtc->dev;
8309 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8310 struct drm_atomic_state *state = crtc_state->base.state;
8311 struct drm_connector_state *connector_state;
8312 struct intel_encoder *encoder;
de13a2e3 8313 uint32_t dpll;
55bb9992 8314 int factor, num_connectors = 0, i;
09ede541 8315 bool is_lvds = false, is_sdvo = false;
79e53945 8316
55bb9992
ACO		 8317 for (i = 0; i < state->num_connector; i++) {
8318 if (!state->connectors[i])
d0737e1d
ACO		 8319 continue;
8320
55bb9992
ACO		 8321 connector_state = state->connector_states[i];
8322 if (connector_state->crtc != crtc_state->base.crtc)
8323 continue;
8324
8325 encoder = to_intel_encoder(connector_state->best_encoder);
8326
8327 switch (encoder->type) {
79e53945
JB		 8328 case INTEL_OUTPUT_LVDS:
8329 is_lvds = true;
8330 break;
8331 case INTEL_OUTPUT_SDVO:
7d57382e 8332 case INTEL_OUTPUT_HDMI:
79e53945 8333 is_sdvo = true;
79e53945 8334 break;
6847d71b
PZ		 8335 default:
8336 break;
79e53945 8337 }
43565a06 8338
c751ce4f 8339 num_connectors++;
79e53945 8340 }
79e53945 8341
c1858123 8342 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8343 factor = 21;
8344 if (is_lvds) {
8345 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8346 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8347 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8348 factor = 25;
190f68c5 8349 } else if (crtc_state->sdvo_tv_clock)
8febb297 8350 factor = 20;
c1858123 8351
190f68c5 8352 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8353 *fp |= FP_CB_TUNE;
2c07245f 8354
9a7c7890
DV		 8355 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8356 *fp2 |= FP_CB_TUNE;
8357
5eddb70b 8358 dpll = 0;
2c07245f 8359
a07d6787
EA		 8360 if (is_lvds)
8361 dpll |= DPLLB_MODE_LVDS;
8362 else
8363 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8364
190f68c5 8365 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8366 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8367
8368 if (is_sdvo)
4a33e48d 8369 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8370 if (crtc_state->has_dp_encoder)
4a33e48d 8371 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8372
a07d6787 8373 /* compute bitmask from p1 value */
190f68c5 8374 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8375 /* also FPA1 */
190f68c5 8376 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8377
190f68c5 8378 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8379 case 5:
8380 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8381 break;
8382 case 7:
8383 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8384 break;
8385 case 10:
8386 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8387 break;
8388 case 14:
8389 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8390 break;
79e53945
JB		 8391 }
8392
b4c09f3b 8393 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8394 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8395 else
8396 dpll |= PLL_REF_INPUT_DREFCLK;
8397
959e16d6 8398 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8399}
8400
190f68c5
ACO		 8401static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8402 struct intel_crtc_state *crtc_state)
de13a2e3 8403{
c7653199 8404 struct drm_device *dev = crtc->base.dev;
de13a2e3 8405 intel_clock_t clock, reduced_clock;
cbbab5bd 8406 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8407 bool ok, has_reduced_clock = false;
8b47047b 8408 bool is_lvds = false;
e2b78267 8409 struct intel_shared_dpll *pll;
de13a2e3 8410
409ee761 8411 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8412
5dc5298b
PZ		 8413 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8414 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8415
190f68c5 8416 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8417 &has_reduced_clock, &reduced_clock);
190f68c5 8418 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8419 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8420 return -EINVAL;
79e53945 8421 }
f47709a9 8422 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8423 if (!crtc_state->clock_set) {
8424 crtc_state->dpll.n = clock.n;
8425 crtc_state->dpll.m1 = clock.m1;
8426 crtc_state->dpll.m2 = clock.m2;
8427 crtc_state->dpll.p1 = clock.p1;
8428 crtc_state->dpll.p2 = clock.p2;
f47709a9 8429 }
79e53945 8430
5dc5298b 8431 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8432 if (crtc_state->has_pch_encoder) {
8433 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8434 if (has_reduced_clock)
7429e9d4 8435 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8436
190f68c5 8437 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8438 &fp, &reduced_clock,
8439 has_reduced_clock ? &fp2 : NULL);
8440
190f68c5
ACO		 8441 crtc_state->dpll_hw_state.dpll = dpll;
8442 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8443 if (has_reduced_clock)
190f68c5 8444 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8445 else
190f68c5 8446 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8447
190f68c5 8448 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8449 if (pll == NULL) {
84f44ce7 8450 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8451 pipe_name(crtc->pipe));
4b645f14
JB		 8452 return -EINVAL;
8453 }
3fb37703 8454 }
79e53945 8455
ab585dea 8456 if (is_lvds && has_reduced_clock)
c7653199 8457 crtc->lowfreq_avail = true;
bcd644e0 8458 else
c7653199 8459 crtc->lowfreq_avail = false;
e2b78267 8460
c8f7a0db 8461 return 0;
79e53945
JB		 8462}
8463
eb14cb74
VS		 8464static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8465 struct intel_link_m_n *m_n)
8466{
8467 struct drm_device *dev = crtc->base.dev;
8468 struct drm_i915_private *dev_priv = dev->dev_private;
8469 enum pipe pipe = crtc->pipe;
8470
8471 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8472 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8473 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8474 & ~TU_SIZE_MASK;
8475 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8476 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8477 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8478}
8479
8480static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8481 enum transcoder transcoder,
b95af8be
VK		 8482 struct intel_link_m_n *m_n,
8483 struct intel_link_m_n *m2_n2)
72419203
DV		 8484{
8485 struct drm_device *dev = crtc->base.dev;
8486 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8487 enum pipe pipe = crtc->pipe;
72419203 8488
eb14cb74
VS		 8489 if (INTEL_INFO(dev)->gen >= 5) {
8490 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8491 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8492 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8493 & ~TU_SIZE_MASK;
8494 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8495 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8496 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8497 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8498 * gen < 8) and if DRRS is supported (to make sure the
8499 * registers are not unnecessarily read).
8500 */
8501 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8502 crtc->config->has_drrs) {
b95af8be
VK		 8503 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8504 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8505 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8506 & ~TU_SIZE_MASK;
8507 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8508 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8509 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8510 }
eb14cb74
VS		 8511 } else {
8512 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8513 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8514 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8515 & ~TU_SIZE_MASK;
8516 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8517 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8518 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8519 }
8520}
8521
8522void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8523 struct intel_crtc_state *pipe_config)
eb14cb74 8524{
681a8504 8525 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8526 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8527 else
8528 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8529 &pipe_config->dp_m_n,
8530 &pipe_config->dp_m2_n2);
eb14cb74 8531}
72419203 8532
eb14cb74 8533static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8534 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8535{
8536 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8537 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8538}
8539
bd2e244f 8540static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8541 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8542{
8543 struct drm_device *dev = crtc->base.dev;
8544 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8545 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8546 uint32_t ps_ctrl = 0;
8547 int id = -1;
8548 int i;
bd2e244f 8549
a1b2278e
CK		 8550 /* find scaler attached to this pipe */
8551 for (i = 0; i < crtc->num_scalers; i++) {
8552 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8553 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8554 id = i;
8555 pipe_config->pch_pfit.enabled = true;
8556 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8557 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8558 break;
8559 }
8560 }
bd2e244f 8561
a1b2278e
CK		 8562 scaler_state->scaler_id = id;
8563 if (id >= 0) {
8564 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8565 } else {
8566 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8567 }
8568}
8569
5724dbd1
DL		 8570static void
8571skylake_get_initial_plane_config(struct intel_crtc *crtc,
8572 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8573{
8574 struct drm_device *dev = crtc->base.dev;
8575 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8576 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8577 int pipe = crtc->pipe;
8578 int fourcc, pixel_format;
6761dd31 8579 unsigned int aligned_height;
bc8d7dff 8580 struct drm_framebuffer *fb;
1b842c89 8581 struct intel_framebuffer *intel_fb;
bc8d7dff 8582
d9806c9f 8583 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8584 if (!intel_fb) {
bc8d7dff
DL		 8585 DRM_DEBUG_KMS("failed to alloc fb\n");
8586 return;
8587 }
8588
1b842c89
DL		 8589 fb = &intel_fb->base;
8590
bc8d7dff 8591 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8592 if (!(val & PLANE_CTL_ENABLE))
8593 goto error;
8594
bc8d7dff
DL		 8595 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8596 fourcc = skl_format_to_fourcc(pixel_format,
8597 val & PLANE_CTL_ORDER_RGBX,
8598 val & PLANE_CTL_ALPHA_MASK);
8599 fb->pixel_format = fourcc;
8600 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8601
40f46283
DL		 8602 tiling = val & PLANE_CTL_TILED_MASK;
8603 switch (tiling) {
8604 case PLANE_CTL_TILED_LINEAR:
8605 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8606 break;
8607 case PLANE_CTL_TILED_X:
8608 plane_config->tiling = I915_TILING_X;
8609 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8610 break;
8611 case PLANE_CTL_TILED_Y:
8612 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8613 break;
8614 case PLANE_CTL_TILED_YF:
8615 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8616 break;
8617 default:
8618 MISSING_CASE(tiling);
8619 goto error;
8620 }
8621
bc8d7dff
DL		 8622 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8623 plane_config->base = base;
8624
8625 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8626
8627 val = I915_READ(PLANE_SIZE(pipe, 0));
8628 fb->height = ((val >> 16) & 0xfff) + 1;
8629 fb->width = ((val >> 0) & 0x1fff) + 1;
8630
8631 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8632 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8633 fb->pixel_format);
bc8d7dff
DL		 8634 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8635
8636 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8637 fb->pixel_format,
8638 fb->modifier[0]);
bc8d7dff 8639
f37b5c2b 8640 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8641
8642 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8643 pipe_name(pipe), fb->width, fb->height,
8644 fb->bits_per_pixel, base, fb->pitches[0],
8645 plane_config->size);
8646
2d14030b 8647 plane_config->fb = intel_fb;
bc8d7dff
DL		 8648 return;
8649
8650error:
8651 kfree(fb);
8652}
8653
2fa2fe9a 8654static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8655 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8656{
8657 struct drm_device *dev = crtc->base.dev;
8658 struct drm_i915_private *dev_priv = dev->dev_private;
8659 uint32_t tmp;
8660
8661 tmp = I915_READ(PF_CTL(crtc->pipe));
8662
8663 if (tmp & PF_ENABLE) {
fd4daa9c 8664 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8665 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8666 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8667
8668 /* We currently do not free assignements of panel fitters on
8669 * ivb/hsw (since we don't use the higher upscaling modes which
8670 * differentiates them) so just WARN about this case for now. */
8671 if (IS_GEN7(dev)) {
8672 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8673 PF_PIPE_SEL_IVB(crtc->pipe));
8674 }
2fa2fe9a 8675 }
79e53945
JB		 8676}
8677
5724dbd1
DL		 8678static void
8679ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8680 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8681{
8682 struct drm_device *dev = crtc->base.dev;
8683 struct drm_i915_private *dev_priv = dev->dev_private;
8684 u32 val, base, offset;
aeee5a49 8685 int pipe = crtc->pipe;
4c6baa59 8686 int fourcc, pixel_format;
6761dd31 8687 unsigned int aligned_height;
b113d5ee 8688 struct drm_framebuffer *fb;
1b842c89 8689 struct intel_framebuffer *intel_fb;
4c6baa59 8690
42a7b088
DL		 8691 val = I915_READ(DSPCNTR(pipe));
8692 if (!(val & DISPLAY_PLANE_ENABLE))
8693 return;
8694
d9806c9f 8695 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8696 if (!intel_fb) {
4c6baa59
JB		 8697 DRM_DEBUG_KMS("failed to alloc fb\n");
8698 return;
8699 }
8700
1b842c89
DL		 8701 fb = &intel_fb->base;
8702
18c5247e
DV		 8703 if (INTEL_INFO(dev)->gen >= 4) {
8704 if (val & DISPPLANE_TILED) {
49af449b 8705 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8706 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8707 }
8708 }
4c6baa59
JB		 8709
8710 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8711 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8712 fb->pixel_format = fourcc;
8713 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8714
aeee5a49 8715 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8716 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8717 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8718 } else {
49af449b 8719 if (plane_config->tiling)
aeee5a49 8720 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8721 else
aeee5a49 8722 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8723 }
8724 plane_config->base = base;
8725
8726 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8727 fb->width = ((val >> 16) & 0xfff) + 1;
8728 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8729
8730 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8731 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8732
b113d5ee 8733 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8734 fb->pixel_format,
8735 fb->modifier[0]);
4c6baa59 8736
f37b5c2b 8737 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8738
2844a921
DL		 8739 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8740 pipe_name(pipe), fb->width, fb->height,
8741 fb->bits_per_pixel, base, fb->pitches[0],
8742 plane_config->size);
b113d5ee 8743
2d14030b 8744 plane_config->fb = intel_fb;
4c6baa59
JB		 8745}
8746
0e8ffe1b 8747static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8748 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8749{
8750 struct drm_device *dev = crtc->base.dev;
8751 struct drm_i915_private *dev_priv = dev->dev_private;
8752 uint32_t tmp;
8753
f458ebbc
DV		 8754 if (!intel_display_power_is_enabled(dev_priv,
8755 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8756 return false;
8757
e143a21c 8758 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8759 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8760
0e8ffe1b
DV		 8761 tmp = I915_READ(PIPECONF(crtc->pipe));
8762 if (!(tmp & PIPECONF_ENABLE))
8763 return false;
8764
42571aef
VS		 8765 switch (tmp & PIPECONF_BPC_MASK) {
8766 case PIPECONF_6BPC:
8767 pipe_config->pipe_bpp = 18;
8768 break;
8769 case PIPECONF_8BPC:
8770 pipe_config->pipe_bpp = 24;
8771 break;
8772 case PIPECONF_10BPC:
8773 pipe_config->pipe_bpp = 30;
8774 break;
8775 case PIPECONF_12BPC:
8776 pipe_config->pipe_bpp = 36;
8777 break;
8778 default:
8779 break;
8780 }
8781
b5a9fa09
DV		 8782 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8783 pipe_config->limited_color_range = true;
8784
ab9412ba 8785 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8786 struct intel_shared_dpll *pll;
8787
88adfff1
DV		 8788 pipe_config->has_pch_encoder = true;
8789
627eb5a3
DV		 8790 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8791 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8792 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8793
8794 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8795
c0d43d62 8796 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8797 pipe_config->shared_dpll =
8798 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8799 } else {
8800 tmp = I915_READ(PCH_DPLL_SEL);
8801 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8802 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8803 else
8804 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8805 }
66e985c0
DV		 8806
8807 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8808
8809 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8810 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8811
8812 tmp = pipe_config->dpll_hw_state.dpll;
8813 pipe_config->pixel_multiplier =
8814 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8815 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8816
8817 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8818 } else {
8819 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8820 }
8821
1bd1bd80
DV		 8822 intel_get_pipe_timings(crtc, pipe_config);
8823
2fa2fe9a
DV		 8824 ironlake_get_pfit_config(crtc, pipe_config);
8825
0e8ffe1b
DV		 8826 return true;
8827}
8828
be256dc7
PZ		 8829static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8830{
8831 struct drm_device *dev = dev_priv->dev;
be256dc7 8832 struct intel_crtc *crtc;
be256dc7 8833
d3fcc808 8834 for_each_intel_crtc(dev, crtc)
e2c719b7 8835 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8836 pipe_name(crtc->pipe));
8837
e2c719b7
RC		 8838 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8839 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8840 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8841 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8842 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8843 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8844 "CPU PWM1 enabled\n");
c5107b87 8845 if (IS_HASWELL(dev))
e2c719b7 8846 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8847 "CPU PWM2 enabled\n");
e2c719b7 8848 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8849 "PCH PWM1 enabled\n");
e2c719b7 8850 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8851 "Utility pin enabled\n");
e2c719b7 8852 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8853
9926ada1
PZ		 8854 /*
8855 * In theory we can still leave IRQs enabled, as long as only the HPD
8856 * interrupts remain enabled. We used to check for that, but since it's
8857 * gen-specific and since we only disable LCPLL after we fully disable
8858 * the interrupts, the check below should be enough.
8859 */
e2c719b7 8860 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8861}
8862
9ccd5aeb
PZ		 8863static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8864{
8865 struct drm_device *dev = dev_priv->dev;
8866
8867 if (IS_HASWELL(dev))
8868 return I915_READ(D_COMP_HSW);
8869 else
8870 return I915_READ(D_COMP_BDW);
8871}
8872
3c4c9b81
PZ		 8873static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8874{
8875 struct drm_device *dev = dev_priv->dev;
8876
8877 if (IS_HASWELL(dev)) {
8878 mutex_lock(&dev_priv->rps.hw_lock);
8879 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8880 val))
f475dadf 8881 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8882 mutex_unlock(&dev_priv->rps.hw_lock);
8883 } else {
9ccd5aeb
PZ		 8884 I915_WRITE(D_COMP_BDW, val);
8885 POSTING_READ(D_COMP_BDW);
3c4c9b81 8886 }
be256dc7
PZ		 8887}
8888
8889/*
8890 * This function implements pieces of two sequences from BSpec:
8891 * - Sequence for display software to disable LCPLL
8892 * - Sequence for display software to allow package C8+
8893 * The steps implemented here are just the steps that actually touch the LCPLL
8894 * register. Callers should take care of disabling all the display engine
8895 * functions, doing the mode unset, fixing interrupts, etc.
8896 */
6ff58d53
PZ		 8897static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8898 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8899{
8900 uint32_t val;
8901
8902 assert_can_disable_lcpll(dev_priv);
8903
8904 val = I915_READ(LCPLL_CTL);
8905
8906 if (switch_to_fclk) {
8907 val |= LCPLL_CD_SOURCE_FCLK;
8908 I915_WRITE(LCPLL_CTL, val);
8909
8910 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8911 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8912 DRM_ERROR("Switching to FCLK failed\n");
8913
8914 val = I915_READ(LCPLL_CTL);
8915 }
8916
8917 val |= LCPLL_PLL_DISABLE;
8918 I915_WRITE(LCPLL_CTL, val);
8919 POSTING_READ(LCPLL_CTL);
8920
8921 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8922 DRM_ERROR("LCPLL still locked\n");
8923
9ccd5aeb 8924 val = hsw_read_dcomp(dev_priv);
be256dc7 8925 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8926 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8927 ndelay(100);
8928
9ccd5aeb
PZ		 8929 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8930 1))
be256dc7
PZ		 8931 DRM_ERROR("D_COMP RCOMP still in progress\n");
8932
8933 if (allow_power_down) {
8934 val = I915_READ(LCPLL_CTL);
8935 val |= LCPLL_POWER_DOWN_ALLOW;
8936 I915_WRITE(LCPLL_CTL, val);
8937 POSTING_READ(LCPLL_CTL);
8938 }
8939}
8940
8941/*
8942 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8943 * source.
8944 */
6ff58d53 8945static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8946{
8947 uint32_t val;
8948
8949 val = I915_READ(LCPLL_CTL);
8950
8951 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8952 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8953 return;
8954
a8a8bd54
PZ		 8955 /*
8956 * Make sure we're not on PC8 state before disabling PC8, otherwise
8957 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8958 */
59bad947 8959 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8960
be256dc7
PZ		 8961 if (val & LCPLL_POWER_DOWN_ALLOW) {
8962 val &= ~LCPLL_POWER_DOWN_ALLOW;
8963 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8964 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8965 }
8966
9ccd5aeb 8967 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8968 val |= D_COMP_COMP_FORCE;
8969 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8970 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8971
8972 val = I915_READ(LCPLL_CTL);
8973 val &= ~LCPLL_PLL_DISABLE;
8974 I915_WRITE(LCPLL_CTL, val);
8975
8976 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8977 DRM_ERROR("LCPLL not locked yet\n");
8978
8979 if (val & LCPLL_CD_SOURCE_FCLK) {
8980 val = I915_READ(LCPLL_CTL);
8981 val &= ~LCPLL_CD_SOURCE_FCLK;
8982 I915_WRITE(LCPLL_CTL, val);
8983
8984 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8985 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8986 DRM_ERROR("Switching back to LCPLL failed\n");
8987 }
215733fa 8988
59bad947 8989 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8990}
8991
765dab67
PZ		 8992/*
8993 * Package states C8 and deeper are really deep PC states that can only be
8994 * reached when all the devices on the system allow it, so even if the graphics
8995 * device allows PC8+, it doesn't mean the system will actually get to these
8996 * states. Our driver only allows PC8+ when going into runtime PM.
8997 *
8998 * The requirements for PC8+ are that all the outputs are disabled, the power
8999 * well is disabled and most interrupts are disabled, and these are also
9000 * requirements for runtime PM. When these conditions are met, we manually do
9001 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9002 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9003 * hang the machine.
9004 *
9005 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9006 * the state of some registers, so when we come back from PC8+ we need to
9007 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9008 * need to take care of the registers kept by RC6. Notice that this happens even
9009 * if we don't put the device in PCI D3 state (which is what currently happens
9010 * because of the runtime PM support).
9011 *
9012 * For more, read "Display Sequences for Package C8" on the hardware
9013 * documentation.
9014 */
a14cb6fc 9015void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9016{
c67a470b
PZ		 9017 struct drm_device *dev = dev_priv->dev;
9018 uint32_t val;
9019
c67a470b
PZ		 9020 DRM_DEBUG_KMS("Enabling package C8+\n");
9021
c67a470b
PZ		 9022 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9023 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9024 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9025 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9026 }
9027
9028 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9029 hsw_disable_lcpll(dev_priv, true, true);
9030}
9031
a14cb6fc 9032void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9033{
9034 struct drm_device *dev = dev_priv->dev;
9035 uint32_t val;
9036
c67a470b
PZ		 9037 DRM_DEBUG_KMS("Disabling package C8+\n");
9038
9039 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9040 lpt_init_pch_refclk(dev);
9041
9042 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9043 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9044 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9045 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9046 }
9047
9048 intel_prepare_ddi(dev);
c67a470b
PZ		 9049}
9050
f8437dd1
VK		 9051static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9052{
9053 struct drm_device *dev = state->dev;
9054 struct drm_i915_private *dev_priv = dev->dev_private;
9055 int max_pixclk = intel_mode_max_pixclk(state);
9056 int req_cdclk;
9057
9058 /* see the comment in valleyview_modeset_global_resources */
9059 if (WARN_ON(max_pixclk < 0))
9060 return;
9061
9062 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9063
9064 if (req_cdclk != dev_priv->cdclk_freq)
9065 broxton_set_cdclk(dev, req_cdclk);
9066}
9067
190f68c5
ACO		 9068static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9069 struct intel_crtc_state *crtc_state)
09b4ddf9 9070{
190f68c5 9071 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9072 return -EINVAL;
716c2e55 9073
c7653199 9074 crtc->lowfreq_avail = false;
644cef34 9075
c8f7a0db 9076 return 0;
79e53945
JB		 9077}
9078
96b7dfb7
S		 9079static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9080 enum port port,
5cec258b 9081 struct intel_crtc_state *pipe_config)
96b7dfb7 9082{
3148ade7 9083 u32 temp, dpll_ctl1;
96b7dfb7
S		 9084
9085 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9086 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9087
9088 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9089 case SKL_DPLL0:
9090 /*
9091 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9092 * of the shared DPLL framework and thus needs to be read out
9093 * separately
9094 */
9095 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9096 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9097 break;
96b7dfb7
S		 9098 case SKL_DPLL1:
9099 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9100 break;
9101 case SKL_DPLL2:
9102 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9103 break;
9104 case SKL_DPLL3:
9105 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9106 break;
96b7dfb7
S		 9107 }
9108}
9109
7d2c8175
DL		 9110static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9111 enum port port,
5cec258b 9112 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9113{
9114 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9115
9116 switch (pipe_config->ddi_pll_sel) {
9117 case PORT_CLK_SEL_WRPLL1:
9118 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9119 break;
9120 case PORT_CLK_SEL_WRPLL2:
9121 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9122 break;
9123 }
9124}
9125
26804afd 9126static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9127 struct intel_crtc_state *pipe_config)
26804afd
DV		 9128{
9129 struct drm_device *dev = crtc->base.dev;
9130 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9131 struct intel_shared_dpll *pll;
26804afd
DV		 9132 enum port port;
9133 uint32_t tmp;
9134
9135 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9136
9137 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9138
96b7dfb7
S		 9139 if (IS_SKYLAKE(dev))
9140 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9141 else
9142 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9143
d452c5b6
DV		 9144 if (pipe_config->shared_dpll >= 0) {
9145 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9146
9147 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9148 &pipe_config->dpll_hw_state));
9149 }
9150
26804afd
DV		 9151 /*
9152 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9153 * DDI E. So just check whether this pipe is wired to DDI E and whether
9154 * the PCH transcoder is on.
9155 */
ca370455
DL		 9156 if (INTEL_INFO(dev)->gen < 9 &&
9157 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9158 pipe_config->has_pch_encoder = true;
9159
9160 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9161 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9162 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9163
9164 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9165 }
9166}
9167
0e8ffe1b 9168static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9169 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9170{
9171 struct drm_device *dev = crtc->base.dev;
9172 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9173 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9174 uint32_t tmp;
9175
f458ebbc 9176 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9177 POWER_DOMAIN_PIPE(crtc->pipe)))
9178 return false;
9179
e143a21c 9180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9181 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9182
eccb140b
DV		 9183 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9184 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9185 enum pipe trans_edp_pipe;
9186 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9187 default:
9188 WARN(1, "unknown pipe linked to edp transcoder\n");
9189 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9190 case TRANS_DDI_EDP_INPUT_A_ON:
9191 trans_edp_pipe = PIPE_A;
9192 break;
9193 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9194 trans_edp_pipe = PIPE_B;
9195 break;
9196 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9197 trans_edp_pipe = PIPE_C;
9198 break;
9199 }
9200
9201 if (trans_edp_pipe == crtc->pipe)
9202 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9203 }
9204
f458ebbc 9205 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9206 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9207 return false;
9208
eccb140b 9209 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9210 if (!(tmp & PIPECONF_ENABLE))
9211 return false;
9212
26804afd 9213 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9214
1bd1bd80
DV		 9215 intel_get_pipe_timings(crtc, pipe_config);
9216
a1b2278e
CK		 9217 if (INTEL_INFO(dev)->gen >= 9) {
9218 skl_init_scalers(dev, crtc, pipe_config);
9219 }
9220
2fa2fe9a 9221 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9222 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9223 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9224 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9225 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9226 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9227 else
9228 MISSING_CASE(INTEL_INFO(dev)->gen);
9229
a1b2278e
CK		 9230 } else {
9231 pipe_config->scaler_state.scaler_id = -1;
9232 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9233 }
88adfff1 9234
e59150dc
JB		 9235 if (IS_HASWELL(dev))
9236 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9237 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9238
ebb69c95
CT		 9239 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9240 pipe_config->pixel_multiplier =
9241 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9242 } else {
9243 pipe_config->pixel_multiplier = 1;
9244 }
6c49f241 9245
0e8ffe1b
DV		 9246 return true;
9247}
9248
560b85bb
CW		 9249static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9250{
9251 struct drm_device *dev = crtc->dev;
9252 struct drm_i915_private *dev_priv = dev->dev_private;
9253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9254 uint32_t cntl = 0, size = 0;
560b85bb 9255
dc41c154 9256 if (base) {
3dd512fb
MR		 9257 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9258 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9259 unsigned int stride = roundup_pow_of_two(width) * 4;
9260
9261 switch (stride) {
9262 default:
9263 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9264 width, stride);
9265 stride = 256;
9266 /* fallthrough */
9267 case 256:
9268 case 512:
9269 case 1024:
9270 case 2048:
9271 break;
4b0e333e
CW		 9272 }
9273
dc41c154
VS		 9274 cntl |= CURSOR_ENABLE |
9275 CURSOR_GAMMA_ENABLE |
9276 CURSOR_FORMAT_ARGB |
9277 CURSOR_STRIDE(stride);
9278
9279 size = (height << 12) | width;
4b0e333e 9280 }
560b85bb 9281
dc41c154
VS		 9282 if (intel_crtc->cursor_cntl != 0 &&
9283 (intel_crtc->cursor_base != base ||
9284 intel_crtc->cursor_size != size ||
9285 intel_crtc->cursor_cntl != cntl)) {
9286 /* On these chipsets we can only modify the base/size/stride
9287 * whilst the cursor is disabled.
9288 */
9289 I915_WRITE(_CURACNTR, 0);
4b0e333e 9290 POSTING_READ(_CURACNTR);
dc41c154 9291 intel_crtc->cursor_cntl = 0;
4b0e333e 9292 }
560b85bb 9293
99d1f387 9294 if (intel_crtc->cursor_base != base) {
9db4a9c7 9295 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9296 intel_crtc->cursor_base = base;
9297 }
4726e0b0 9298
dc41c154
VS		 9299 if (intel_crtc->cursor_size != size) {
9300 I915_WRITE(CURSIZE, size);
9301 intel_crtc->cursor_size = size;
4b0e333e 9302 }
560b85bb 9303
4b0e333e 9304 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9305 I915_WRITE(_CURACNTR, cntl);
9306 POSTING_READ(_CURACNTR);
4b0e333e 9307 intel_crtc->cursor_cntl = cntl;
560b85bb 9308 }
560b85bb
CW		 9309}
9310
560b85bb 9311static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9312{
9313 struct drm_device *dev = crtc->dev;
9314 struct drm_i915_private *dev_priv = dev->dev_private;
9315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9316 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9317 uint32_t cntl;
9318
9319 cntl = 0;
9320 if (base) {
9321 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9322 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9323 case 64:
9324 cntl |= CURSOR_MODE_64_ARGB_AX;
9325 break;
9326 case 128:
9327 cntl |= CURSOR_MODE_128_ARGB_AX;
9328 break;
9329 case 256:
9330 cntl |= CURSOR_MODE_256_ARGB_AX;
9331 break;
9332 default:
3dd512fb 9333 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9334 return;
65a21cd6 9335 }
4b0e333e 9336 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9337
9338 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9339 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9340 }
65a21cd6 9341
8e7d688b 9342 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9343 cntl |= CURSOR_ROTATE_180;
9344
4b0e333e
CW		 9345 if (intel_crtc->cursor_cntl != cntl) {
9346 I915_WRITE(CURCNTR(pipe), cntl);
9347 POSTING_READ(CURCNTR(pipe));
9348 intel_crtc->cursor_cntl = cntl;
65a21cd6 9349 }
4b0e333e 9350
65a21cd6 9351 /* and commit changes on next vblank */
5efb3e28
VS		 9352 I915_WRITE(CURBASE(pipe), base);
9353 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9354
9355 intel_crtc->cursor_base = base;
65a21cd6
JB		 9356}
9357
cda4b7d3 9358/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9359static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9360 bool on)
cda4b7d3
CW		 9361{
9362 struct drm_device *dev = crtc->dev;
9363 struct drm_i915_private *dev_priv = dev->dev_private;
9364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9365 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9366 int x = crtc->cursor_x;
9367 int y = crtc->cursor_y;
d6e4db15 9368 u32 base = 0, pos = 0;
cda4b7d3 9369
d6e4db15 9370 if (on)
cda4b7d3 9371 base = intel_crtc->cursor_addr;
cda4b7d3 9372
6e3c9717 9373 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9374 base = 0;
9375
6e3c9717 9376 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9377 base = 0;
9378
9379 if (x < 0) {
3dd512fb 9380 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9381 base = 0;
9382
9383 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9384 x = -x;
9385 }
9386 pos |= x << CURSOR_X_SHIFT;
9387
9388 if (y < 0) {
3dd512fb 9389 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9390 base = 0;
9391
9392 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9393 y = -y;
9394 }
9395 pos |= y << CURSOR_Y_SHIFT;
9396
4b0e333e 9397 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9398 return;
9399
5efb3e28
VS		 9400 I915_WRITE(CURPOS(pipe), pos);
9401
4398ad45
VS		 9402 /* ILK+ do this automagically */
9403 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9404 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9405 base += (intel_crtc->base.cursor->state->crtc_h *
9406 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9407 }
9408
8ac54669 9409 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9410 i845_update_cursor(crtc, base);
9411 else
9412 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9413}
9414
dc41c154
VS		 9415static bool cursor_size_ok(struct drm_device *dev,
9416 uint32_t width, uint32_t height)
9417{
9418 if (width == 0 || height == 0)
9419 return false;
9420
9421 /*
9422 * 845g/865g are special in that they are only limited by
9423 * the width of their cursors, the height is arbitrary up to
9424 * the precision of the register. Everything else requires
9425 * square cursors, limited to a few power-of-two sizes.
9426 */
9427 if (IS_845G(dev) || IS_I865G(dev)) {
9428 if ((width & 63) != 0)
9429 return false;
9430
9431 if (width > (IS_845G(dev) ? 64 : 512))
9432 return false;
9433
9434 if (height > 1023)
9435 return false;
9436 } else {
9437 switch (width | height) {
9438 case 256:
9439 case 128:
9440 if (IS_GEN2(dev))
9441 return false;
9442 case 64:
9443 break;
9444 default:
9445 return false;
9446 }
9447 }
9448
9449 return true;
9450}
9451
79e53945 9452static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9453 u16 *blue, uint32_t start, uint32_t size)
79e53945 9454{
7203425a 9455 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9457
7203425a 9458 for (i = start; i < end; i++) {
79e53945
JB		 9459 intel_crtc->lut_r[i] = red[i] >> 8;
9460 intel_crtc->lut_g[i] = green[i] >> 8;
9461 intel_crtc->lut_b[i] = blue[i] >> 8;
9462 }
9463
9464 intel_crtc_load_lut(crtc);
9465}
9466
79e53945
JB		 9467/* VESA 640x480x72Hz mode to set on the pipe */
9468static struct drm_display_mode load_detect_mode = {
9469 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9470 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9471};
9472
a8bb6818
DV		 9473struct drm_framebuffer *
9474__intel_framebuffer_create(struct drm_device *dev,
9475 struct drm_mode_fb_cmd2 *mode_cmd,
9476 struct drm_i915_gem_object *obj)
d2dff872
CW		 9477{
9478 struct intel_framebuffer *intel_fb;
9479 int ret;
9480
9481 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9482 if (!intel_fb) {
6ccb81f2 9483 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9484 return ERR_PTR(-ENOMEM);
9485 }
9486
9487 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9488 if (ret)
9489 goto err;
d2dff872
CW		 9490
9491 return &intel_fb->base;
dd4916c5 9492err:
6ccb81f2 9493 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9494 kfree(intel_fb);
9495
9496 return ERR_PTR(ret);
d2dff872
CW		 9497}
9498
b5ea642a 9499static struct drm_framebuffer *
a8bb6818
DV		 9500intel_framebuffer_create(struct drm_device *dev,
9501 struct drm_mode_fb_cmd2 *mode_cmd,
9502 struct drm_i915_gem_object *obj)
9503{
9504 struct drm_framebuffer *fb;
9505 int ret;
9506
9507 ret = i915_mutex_lock_interruptible(dev);
9508 if (ret)
9509 return ERR_PTR(ret);
9510 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9511 mutex_unlock(&dev->struct_mutex);
9512
9513 return fb;
9514}
9515
d2dff872
CW		 9516static u32
9517intel_framebuffer_pitch_for_width(int width, int bpp)
9518{
9519 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9520 return ALIGN(pitch, 64);
9521}
9522
9523static u32
9524intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9525{
9526 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9527 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9528}
9529
9530static struct drm_framebuffer *
9531intel_framebuffer_create_for_mode(struct drm_device *dev,
9532 struct drm_display_mode *mode,
9533 int depth, int bpp)
9534{
9535 struct drm_i915_gem_object *obj;
0fed39bd 9536 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9537
9538 obj = i915_gem_alloc_object(dev,
9539 intel_framebuffer_size_for_mode(mode, bpp));
9540 if (obj == NULL)
9541 return ERR_PTR(-ENOMEM);
9542
9543 mode_cmd.width = mode->hdisplay;
9544 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9545 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9546 bpp);
5ca0c34a 9547 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9548
9549 return intel_framebuffer_create(dev, &mode_cmd, obj);
9550}
9551
9552static struct drm_framebuffer *
9553mode_fits_in_fbdev(struct drm_device *dev,
9554 struct drm_display_mode *mode)
9555{
4520f53a 9556#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9557 struct drm_i915_private *dev_priv = dev->dev_private;
9558 struct drm_i915_gem_object *obj;
9559 struct drm_framebuffer *fb;
9560
4c0e5528 9561 if (!dev_priv->fbdev)
d2dff872
CW		 9562 return NULL;
9563
4c0e5528 9564 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9565 return NULL;
9566
4c0e5528
DV		 9567 obj = dev_priv->fbdev->fb->obj;
9568 BUG_ON(!obj);
9569
8bcd4553 9570 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9571 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9572 fb->bits_per_pixel))
d2dff872
CW		 9573 return NULL;
9574
01f2c773 9575 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9576 return NULL;
9577
9578 return fb;
4520f53a
DV		 9579#else
9580 return NULL;
9581#endif
d2dff872
CW		 9582}
9583
d2434ab7 9584bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9585 struct drm_display_mode *mode,
51fd371b
RC		 9586 struct intel_load_detect_pipe *old,
9587 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9588{
9589 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9590 struct intel_encoder *intel_encoder =
9591 intel_attached_encoder(connector);
79e53945 9592 struct drm_crtc *possible_crtc;
4ef69c7a 9593 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9594 struct drm_crtc *crtc = NULL;
9595 struct drm_device *dev = encoder->dev;
94352cf9 9596 struct drm_framebuffer *fb;
51fd371b 9597 struct drm_mode_config *config = &dev->mode_config;
83a57153 9598 struct drm_atomic_state *state = NULL;
944b0c76 9599 struct drm_connector_state *connector_state;
51fd371b 9600 int ret, i = -1;
79e53945 9601
d2dff872 9602 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9603 connector->base.id, connector->name,
8e329a03 9604 encoder->base.id, encoder->name);
d2dff872 9605
51fd371b
RC		 9606retry:
9607 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9608 if (ret)
9609 goto fail_unlock;
6e9f798d 9610
79e53945
JB		 9611 /*
9612 * Algorithm gets a little messy:
7a5e4805 9613 *
79e53945
JB		 9614 * - if the connector already has an assigned crtc, use it (but make
9615 * sure it's on first)
7a5e4805 9616 *
79e53945
JB		 9617 * - try to find the first unused crtc that can drive this connector,
9618 * and use that if we find one
79e53945
JB		 9619 */
9620
9621 /* See if we already have a CRTC for this connector */
9622 if (encoder->crtc) {
9623 crtc = encoder->crtc;
8261b191 9624
51fd371b 9625 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9626 if (ret)
9627 goto fail_unlock;
9628 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9629 if (ret)
9630 goto fail_unlock;
7b24056b 9631
24218aac 9632 old->dpms_mode = connector->dpms;
8261b191
CW		 9633 old->load_detect_temp = false;
9634
9635 /* Make sure the crtc and connector are running */
24218aac
DV		 9636 if (connector->dpms != DRM_MODE_DPMS_ON)
9637 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9638
7173188d 9639 return true;
79e53945
JB		 9640 }
9641
9642 /* Find an unused one (if possible) */
70e1e0ec 9643 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9644 i++;
9645 if (!(encoder->possible_crtcs & (1 << i)))
9646 continue;
83d65738 9647 if (possible_crtc->state->enable)
a459249c
VS		 9648 continue;
9649 /* This can occur when applying the pipe A quirk on resume. */
9650 if (to_intel_crtc(possible_crtc)->new_enabled)
9651 continue;
9652
9653 crtc = possible_crtc;
9654 break;
79e53945
JB		 9655 }
9656
9657 /*
9658 * If we didn't find an unused CRTC, don't use any.
9659 */
9660 if (!crtc) {
7173188d 9661 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9662 goto fail_unlock;
79e53945
JB		 9663 }
9664
51fd371b
RC		 9665 ret = drm_modeset_lock(&crtc->mutex, ctx);
9666 if (ret)
4d02e2de
DV		 9667 goto fail_unlock;
9668 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9669 if (ret)
51fd371b 9670 goto fail_unlock;
fc303101
DV		 9671 intel_encoder->new_crtc = to_intel_crtc(crtc);
9672 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9673
9674 intel_crtc = to_intel_crtc(crtc);
412b61d8 9675 intel_crtc->new_enabled = true;
24218aac 9676 old->dpms_mode = connector->dpms;
8261b191 9677 old->load_detect_temp = true;
d2dff872 9678 old->release_fb = NULL;
79e53945 9679
83a57153
ACO		 9680 state = drm_atomic_state_alloc(dev);
9681 if (!state)
9682 return false;
9683
9684 state->acquire_ctx = ctx;
9685
944b0c76
ACO		 9686 connector_state = drm_atomic_get_connector_state(state, connector);
9687 if (IS_ERR(connector_state)) {
9688 ret = PTR_ERR(connector_state);
9689 goto fail;
9690 }
9691
9692 connector_state->crtc = crtc;
9693 connector_state->best_encoder = &intel_encoder->base;
9694
6492711d
CW		 9695 if (!mode)
9696 mode = &load_detect_mode;
79e53945 9697
d2dff872
CW		 9698 /* We need a framebuffer large enough to accommodate all accesses
9699 * that the plane may generate whilst we perform load detection.
9700 * We can not rely on the fbcon either being present (we get called
9701 * during its initialisation to detect all boot displays, or it may
9702 * not even exist) or that it is large enough to satisfy the
9703 * requested mode.
9704 */
94352cf9
DV		 9705 fb = mode_fits_in_fbdev(dev, mode);
9706 if (fb == NULL) {
d2dff872 9707 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9708 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9709 old->release_fb = fb;
d2dff872
CW		 9710 } else
9711 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9712 if (IS_ERR(fb)) {
d2dff872 9713 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9714 goto fail;
79e53945 9715 }
79e53945 9716
83a57153 9717 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9718 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9719 if (old->release_fb)
9720 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9721 goto fail;
79e53945 9722 }
9128b040 9723 crtc->primary->crtc = crtc;
7173188d 9724
79e53945 9725 /* let the connector get through one full cycle before testing */
9d0498a2 9726 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9727 return true;
412b61d8
VS		 9728
9729 fail:
83d65738 9730 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9731fail_unlock:
83a57153
ACO		 9732 if (state) {
9733 drm_atomic_state_free(state);
9734 state = NULL;
9735 }
9736
51fd371b
RC		 9737 if (ret == -EDEADLK) {
9738 drm_modeset_backoff(ctx);
9739 goto retry;
9740 }
9741
412b61d8 9742 return false;
79e53945
JB		 9743}
9744
d2434ab7 9745void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9746 struct intel_load_detect_pipe *old,
9747 struct drm_modeset_acquire_ctx *ctx)
79e53945 9748{
83a57153 9749 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9750 struct intel_encoder *intel_encoder =
9751 intel_attached_encoder(connector);
4ef69c7a 9752 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9753 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9755 struct drm_atomic_state *state;
944b0c76 9756 struct drm_connector_state *connector_state;
79e53945 9757
d2dff872 9758 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9759 connector->base.id, connector->name,
8e329a03 9760 encoder->base.id, encoder->name);
d2dff872 9761
8261b191 9762 if (old->load_detect_temp) {
83a57153 9763 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9764 if (!state)
9765 goto fail;
83a57153
ACO		 9766
9767 state->acquire_ctx = ctx;
9768
944b0c76
ACO		 9769 connector_state = drm_atomic_get_connector_state(state, connector);
9770 if (IS_ERR(connector_state))
9771 goto fail;
9772
fc303101
DV		 9773 to_intel_connector(connector)->new_encoder = NULL;
9774 intel_encoder->new_crtc = NULL;
412b61d8 9775 intel_crtc->new_enabled = false;
944b0c76
ACO		 9776
9777 connector_state->best_encoder = NULL;
9778 connector_state->crtc = NULL;
9779
83a57153
ACO		 9780 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9781
9782 drm_atomic_state_free(state);
d2dff872 9783
36206361
DV		 9784 if (old->release_fb) {
9785 drm_framebuffer_unregister_private(old->release_fb);
9786 drm_framebuffer_unreference(old->release_fb);
9787 }
d2dff872 9788
0622a53c 9789 return;
79e53945
JB		 9790 }
9791
c751ce4f 9792 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9793 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9794 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9795
9796 return;
9797fail:
9798 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9799 drm_atomic_state_free(state);
79e53945
JB		 9800}
9801
da4a1efa 9802static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9803 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9804{
9805 struct drm_i915_private *dev_priv = dev->dev_private;
9806 u32 dpll = pipe_config->dpll_hw_state.dpll;
9807
9808 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9809 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9810 else if (HAS_PCH_SPLIT(dev))
9811 return 120000;
9812 else if (!IS_GEN2(dev))
9813 return 96000;
9814 else
9815 return 48000;
9816}
9817
79e53945 9818/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9819static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9820 struct intel_crtc_state *pipe_config)
79e53945 9821{
f1f644dc 9822 struct drm_device *dev = crtc->base.dev;
79e53945 9823 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9824 int pipe = pipe_config->cpu_transcoder;
293623f7 9825 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9826 u32 fp;
9827 intel_clock_t clock;
da4a1efa 9828 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9829
9830 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9831 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9832 else
293623f7 9833 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9834
9835 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9836 if (IS_PINEVIEW(dev)) {
9837 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9838 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9839 } else {
9840 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9841 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9842 }
9843
a6c45cf0 9844 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9845 if (IS_PINEVIEW(dev))
9846 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9847 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9848 else
9849 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9850 DPLL_FPA01_P1_POST_DIV_SHIFT);
9851
9852 switch (dpll & DPLL_MODE_MASK) {
9853 case DPLLB_MODE_DAC_SERIAL:
9854 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9855 5 : 10;
9856 break;
9857 case DPLLB_MODE_LVDS:
9858 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9859 7 : 14;
9860 break;
9861 default:
28c97730 9862 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9863 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9864 return;
79e53945
JB		 9865 }
9866
ac58c3f0 9867 if (IS_PINEVIEW(dev))
da4a1efa 9868 pineview_clock(refclk, &clock);
ac58c3f0 9869 else
da4a1efa 9870 i9xx_clock(refclk, &clock);
79e53945 9871 } else {
0fb58223 9872 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9873 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9874
9875 if (is_lvds) {
9876 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9877 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9878
9879 if (lvds & LVDS_CLKB_POWER_UP)
9880 clock.p2 = 7;
9881 else
9882 clock.p2 = 14;
79e53945
JB		 9883 } else {
9884 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9885 clock.p1 = 2;
9886 else {
9887 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9888 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9889 }
9890 if (dpll & PLL_P2_DIVIDE_BY_4)
9891 clock.p2 = 4;
9892 else
9893 clock.p2 = 2;
79e53945 9894 }
da4a1efa
VS		 9895
9896 i9xx_clock(refclk, &clock);
79e53945
JB		 9897 }
9898
18442d08
VS		 9899 /*
9900 * This value includes pixel_multiplier. We will use
241bfc38 9901 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9902 * encoder's get_config() function.
9903 */
9904 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9905}
9906
6878da05
VS		 9907int intel_dotclock_calculate(int link_freq,
9908 const struct intel_link_m_n *m_n)
f1f644dc 9909{
f1f644dc
JB		 9910 /*
9911 * The calculation for the data clock is:
1041a02f 9912 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9913 * But we want to avoid losing precison if possible, so:
1041a02f 9914 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9915 *
9916 * and the link clock is simpler:
1041a02f 9917 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9918 */
9919
6878da05
VS		 9920 if (!m_n->link_n)
9921 return 0;
f1f644dc 9922
6878da05
VS		 9923 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9924}
f1f644dc 9925
18442d08 9926static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9927 struct intel_crtc_state *pipe_config)
6878da05
VS		 9928{
9929 struct drm_device *dev = crtc->base.dev;
79e53945 9930
18442d08
VS		 9931 /* read out port_clock from the DPLL */
9932 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9933
f1f644dc 9934 /*
18442d08 9935 * This value does not include pixel_multiplier.
241bfc38 9936 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9937 * agree once we know their relationship in the encoder's
9938 * get_config() function.
79e53945 9939 */
2d112de7 9940 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9941 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9942 &pipe_config->fdi_m_n);
79e53945
JB		 9943}
9944
9945/** Returns the currently programmed mode of the given pipe. */
9946struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9947 struct drm_crtc *crtc)
9948{
548f245b 9949 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9951 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9952 struct drm_display_mode *mode;
5cec258b 9953 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9954 int htot = I915_READ(HTOTAL(cpu_transcoder));
9955 int hsync = I915_READ(HSYNC(cpu_transcoder));
9956 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9957 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9958 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9959
9960 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9961 if (!mode)
9962 return NULL;
9963
f1f644dc
JB		 9964 /*
9965 * Construct a pipe_config sufficient for getting the clock info
9966 * back out of crtc_clock_get.
9967 *
9968 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9969 * to use a real value here instead.
9970 */
293623f7 9971 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9972 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9973 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9974 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9975 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9976 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9977
773ae034 9978 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9979 mode->hdisplay = (htot & 0xffff) + 1;
9980 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9981 mode->hsync_start = (hsync & 0xffff) + 1;
9982 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9983 mode->vdisplay = (vtot & 0xffff) + 1;
9984 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9985 mode->vsync_start = (vsync & 0xffff) + 1;
9986 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9987
9988 drm_mode_set_name(mode);
79e53945
JB		 9989
9990 return mode;
9991}
9992
652c393a
JB		 9993static void intel_decrease_pllclock(struct drm_crtc *crtc)
9994{
9995 struct drm_device *dev = crtc->dev;
fbee40df 9996 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9998
baff296c 9999 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10000 return;
10001
10002 if (!dev_priv->lvds_downclock_avail)
10003 return;
10004
10005 /*
10006 * Since this is called by a timer, we should never get here in
10007 * the manual case.
10008 */
10009 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10010 int pipe = intel_crtc->pipe;
10011 int dpll_reg = DPLL(pipe);
10012 int dpll;
f6e5b160 10013
44d98a61 10014 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10015
8ac5a6d5 10016 assert_panel_unlocked(dev_priv, pipe);
652c393a 10017
dc257cf1 10018 dpll = I915_READ(dpll_reg);
652c393a
JB		 10019 dpll |= DISPLAY_RATE_SELECT_FPA1;
10020 I915_WRITE(dpll_reg, dpll);
9d0498a2 10021 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10022 dpll = I915_READ(dpll_reg);
10023 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10024 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10025 }
10026
10027}
10028
f047e395
CW		 10029void intel_mark_busy(struct drm_device *dev)
10030{
c67a470b
PZ		 10031 struct drm_i915_private *dev_priv = dev->dev_private;
10032
f62a0076
CW		 10033 if (dev_priv->mm.busy)
10034 return;
10035
43694d69 10036 intel_runtime_pm_get(dev_priv);
c67a470b 10037 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10038 if (INTEL_INFO(dev)->gen >= 6)
10039 gen6_rps_busy(dev_priv);
f62a0076 10040 dev_priv->mm.busy = true;
f047e395
CW		 10041}
10042
10043void intel_mark_idle(struct drm_device *dev)
652c393a 10044{
c67a470b 10045 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10046 struct drm_crtc *crtc;
652c393a 10047
f62a0076
CW		 10048 if (!dev_priv->mm.busy)
10049 return;
10050
10051 dev_priv->mm.busy = false;
10052
70e1e0ec 10053 for_each_crtc(dev, crtc) {
f4510a27 10054 if (!crtc->primary->fb)
652c393a
JB		 10055 continue;
10056
725a5b54 10057 intel_decrease_pllclock(crtc);
652c393a 10058 }
b29c19b6 10059
3d13ef2e 10060 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10061 gen6_rps_idle(dev->dev_private);
bb4cdd53 10062
43694d69 10063 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10064}
10065
f5de6e07
ACO		 10066static void intel_crtc_set_state(struct intel_crtc *crtc,
10067 struct intel_crtc_state *crtc_state)
10068{
10069 kfree(crtc->config);
10070 crtc->config = crtc_state;
16f3f658 10071 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10072}
10073
79e53945
JB		 10074static void intel_crtc_destroy(struct drm_crtc *crtc)
10075{
10076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10077 struct drm_device *dev = crtc->dev;
10078 struct intel_unpin_work *work;
67e77c5a 10079
5e2d7afc 10080 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10081 work = intel_crtc->unpin_work;
10082 intel_crtc->unpin_work = NULL;
5e2d7afc 10083 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10084
10085 if (work) {
10086 cancel_work_sync(&work->work);
10087 kfree(work);
10088 }
79e53945 10089
f5de6e07 10090 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10091 drm_crtc_cleanup(crtc);
67e77c5a 10092
79e53945
JB		 10093 kfree(intel_crtc);
10094}
10095
6b95a207
KH		 10096static void intel_unpin_work_fn(struct work_struct *__work)
10097{
10098 struct intel_unpin_work *work =
10099 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10100 struct drm_device *dev = work->crtc->dev;
f99d7069 10101 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10102
b4a98e57 10103 mutex_lock(&dev->struct_mutex);
82bc3b2d 10104 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10105 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10106
7ff0ebcc 10107 intel_fbc_update(dev);
f06cc1b9
JH		 10108
10109 if (work->flip_queued_req)
146d84f0 10110 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10111 mutex_unlock(&dev->struct_mutex);
10112
f99d7069 10113 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10114 drm_framebuffer_unreference(work->old_fb);
f99d7069 10115
b4a98e57
CW		 10116 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10117 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10118
6b95a207
KH		 10119 kfree(work);
10120}
10121
1afe3e9d 10122static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10123 struct drm_crtc *crtc)
6b95a207 10124{
6b95a207
KH		 10125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10126 struct intel_unpin_work *work;
6b95a207
KH		 10127 unsigned long flags;
10128
10129 /* Ignore early vblank irqs */
10130 if (intel_crtc == NULL)
10131 return;
10132
f326038a
DV		 10133 /*
10134 * This is called both by irq handlers and the reset code (to complete
10135 * lost pageflips) so needs the full irqsave spinlocks.
10136 */
6b95a207
KH		 10137 spin_lock_irqsave(&dev->event_lock, flags);
10138 work = intel_crtc->unpin_work;
e7d841ca
CW		 10139
10140 /* Ensure we don't miss a work->pending update ... */
10141 smp_rmb();
10142
10143 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10144 spin_unlock_irqrestore(&dev->event_lock, flags);
10145 return;
10146 }
10147
d6bbafa1 10148 page_flip_completed(intel_crtc);
0af7e4df 10149
6b95a207 10150 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10151}
10152
1afe3e9d
JB		 10153void intel_finish_page_flip(struct drm_device *dev, int pipe)
10154{
fbee40df 10155 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10156 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10157
49b14a5c 10158 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10159}
10160
10161void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10162{
fbee40df 10163 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10164 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10165
49b14a5c 10166 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10167}
10168
75f7f3ec
VS		 10169/* Is 'a' after or equal to 'b'? */
10170static bool g4x_flip_count_after_eq(u32 a, u32 b)
10171{
10172 return !((a - b) & 0x80000000);
10173}
10174
10175static bool page_flip_finished(struct intel_crtc *crtc)
10176{
10177 struct drm_device *dev = crtc->base.dev;
10178 struct drm_i915_private *dev_priv = dev->dev_private;
10179
bdfa7542
VS		 10180 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10181 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10182 return true;
10183
75f7f3ec
VS		 10184 /*
10185 * The relevant registers doen't exist on pre-ctg.
10186 * As the flip done interrupt doesn't trigger for mmio
10187 * flips on gmch platforms, a flip count check isn't
10188 * really needed there. But since ctg has the registers,
10189 * include it in the check anyway.
10190 */
10191 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10192 return true;
10193
10194 /*
10195 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10196 * used the same base address. In that case the mmio flip might
10197 * have completed, but the CS hasn't even executed the flip yet.
10198 *
10199 * A flip count check isn't enough as the CS might have updated
10200 * the base address just after start of vblank, but before we
10201 * managed to process the interrupt. This means we'd complete the
10202 * CS flip too soon.
10203 *
10204 * Combining both checks should get us a good enough result. It may
10205 * still happen that the CS flip has been executed, but has not
10206 * yet actually completed. But in case the base address is the same
10207 * anyway, we don't really care.
10208 */
10209 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10210 crtc->unpin_work->gtt_offset &&
10211 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10212 crtc->unpin_work->flip_count);
10213}
10214
6b95a207
KH		 10215void intel_prepare_page_flip(struct drm_device *dev, int plane)
10216{
fbee40df 10217 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10218 struct intel_crtc *intel_crtc =
10219 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10220 unsigned long flags;
10221
f326038a
DV		 10222
10223 /*
10224 * This is called both by irq handlers and the reset code (to complete
10225 * lost pageflips) so needs the full irqsave spinlocks.
10226 *
10227 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10228 * generate a page-flip completion irq, i.e. every modeset
10229 * is also accompanied by a spurious intel_prepare_page_flip().
10230 */
6b95a207 10231 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10232 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10233 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10234 spin_unlock_irqrestore(&dev->event_lock, flags);
10235}
10236
eba905b2 10237static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10238{
10239 /* Ensure that the work item is consistent when activating it ... */
10240 smp_wmb();
10241 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10242 /* and that it is marked active as soon as the irq could fire. */
10243 smp_wmb();
10244}
10245
8c9f3aaf
JB		 10246static int intel_gen2_queue_flip(struct drm_device *dev,
10247 struct drm_crtc *crtc,
10248 struct drm_framebuffer *fb,
ed8d1975 10249 struct drm_i915_gem_object *obj,
a4872ba6 10250 struct intel_engine_cs *ring,
ed8d1975 10251 uint32_t flags)
8c9f3aaf 10252{
8c9f3aaf 10253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10254 u32 flip_mask;
10255 int ret;
10256
6d90c952 10257 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10258 if (ret)
4fa62c89 10259 return ret;
8c9f3aaf
JB		 10260
10261 /* Can't queue multiple flips, so wait for the previous
10262 * one to finish before executing the next.
10263 */
10264 if (intel_crtc->plane)
10265 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10266 else
10267 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10268 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10269 intel_ring_emit(ring, MI_NOOP);
10270 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10271 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10272 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10273 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10274 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10275
10276 intel_mark_page_flip_active(intel_crtc);
09246732 10277 __intel_ring_advance(ring);
83d4092b 10278 return 0;
8c9f3aaf
JB		 10279}
10280
10281static int intel_gen3_queue_flip(struct drm_device *dev,
10282 struct drm_crtc *crtc,
10283 struct drm_framebuffer *fb,
ed8d1975 10284 struct drm_i915_gem_object *obj,
a4872ba6 10285 struct intel_engine_cs *ring,
ed8d1975 10286 uint32_t flags)
8c9f3aaf 10287{
8c9f3aaf 10288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10289 u32 flip_mask;
10290 int ret;
10291
6d90c952 10292 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10293 if (ret)
4fa62c89 10294 return ret;
8c9f3aaf
JB		 10295
10296 if (intel_crtc->plane)
10297 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10298 else
10299 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10300 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10301 intel_ring_emit(ring, MI_NOOP);
10302 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10303 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10304 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10305 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10306 intel_ring_emit(ring, MI_NOOP);
10307
e7d841ca 10308 intel_mark_page_flip_active(intel_crtc);
09246732 10309 __intel_ring_advance(ring);
83d4092b 10310 return 0;
8c9f3aaf
JB		 10311}
10312
10313static int intel_gen4_queue_flip(struct drm_device *dev,
10314 struct drm_crtc *crtc,
10315 struct drm_framebuffer *fb,
ed8d1975 10316 struct drm_i915_gem_object *obj,
a4872ba6 10317 struct intel_engine_cs *ring,
ed8d1975 10318 uint32_t flags)
8c9f3aaf
JB		 10319{
10320 struct drm_i915_private *dev_priv = dev->dev_private;
10321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10322 uint32_t pf, pipesrc;
10323 int ret;
10324
6d90c952 10325 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10326 if (ret)
4fa62c89 10327 return ret;
8c9f3aaf
JB		 10328
10329 /* i965+ uses the linear or tiled offsets from the
10330 * Display Registers (which do not change across a page-flip)
10331 * so we need only reprogram the base address.
10332 */
6d90c952
DV		 10333 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10335 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10336 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10337 obj->tiling_mode);
8c9f3aaf
JB		 10338
10339 /* XXX Enabling the panel-fitter across page-flip is so far
10340 * untested on non-native modes, so ignore it for now.
10341 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10342 */
10343 pf = 0;
10344 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10345 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10346
10347 intel_mark_page_flip_active(intel_crtc);
09246732 10348 __intel_ring_advance(ring);
83d4092b 10349 return 0;
8c9f3aaf
JB		 10350}
10351
10352static int intel_gen6_queue_flip(struct drm_device *dev,
10353 struct drm_crtc *crtc,
10354 struct drm_framebuffer *fb,
ed8d1975 10355 struct drm_i915_gem_object *obj,
a4872ba6 10356 struct intel_engine_cs *ring,
ed8d1975 10357 uint32_t flags)
8c9f3aaf
JB		 10358{
10359 struct drm_i915_private *dev_priv = dev->dev_private;
10360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10361 uint32_t pf, pipesrc;
10362 int ret;
10363
6d90c952 10364 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10365 if (ret)
4fa62c89 10366 return ret;
8c9f3aaf 10367
6d90c952
DV		 10368 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10370 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10371 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10372
dc257cf1
DV		 10373 /* Contrary to the suggestions in the documentation,
10374 * "Enable Panel Fitter" does not seem to be required when page
10375 * flipping with a non-native mode, and worse causes a normal
10376 * modeset to fail.
10377 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10378 */
10379 pf = 0;
8c9f3aaf 10380 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10381 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10382
10383 intel_mark_page_flip_active(intel_crtc);
09246732 10384 __intel_ring_advance(ring);
83d4092b 10385 return 0;
8c9f3aaf
JB		 10386}
10387
7c9017e5
JB		 10388static int intel_gen7_queue_flip(struct drm_device *dev,
10389 struct drm_crtc *crtc,
10390 struct drm_framebuffer *fb,
ed8d1975 10391 struct drm_i915_gem_object *obj,
a4872ba6 10392 struct intel_engine_cs *ring,
ed8d1975 10393 uint32_t flags)
7c9017e5 10394{
7c9017e5 10395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10396 uint32_t plane_bit = 0;
ffe74d75
CW		 10397 int len, ret;
10398
eba905b2 10399 switch (intel_crtc->plane) {
cb05d8de
DV		 10400 case PLANE_A:
10401 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10402 break;
10403 case PLANE_B:
10404 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10405 break;
10406 case PLANE_C:
10407 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10408 break;
10409 default:
10410 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10411 return -ENODEV;
cb05d8de
DV		 10412 }
10413
ffe74d75 10414 len = 4;
f476828a 10415 if (ring->id == RCS) {
ffe74d75 10416 len += 6;
f476828a
DL		 10417 /*
10418 * On Gen 8, SRM is now taking an extra dword to accommodate
10419 * 48bits addresses, and we need a NOOP for the batch size to
10420 * stay even.
10421 */
10422 if (IS_GEN8(dev))
10423 len += 2;
10424 }
ffe74d75 10425
f66fab8e
VS		 10426 /*
10427 * BSpec MI_DISPLAY_FLIP for IVB:
10428 * "The full packet must be contained within the same cache line."
10429 *
10430 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10431 * cacheline, if we ever start emitting more commands before
10432 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10433 * then do the cacheline alignment, and finally emit the
10434 * MI_DISPLAY_FLIP.
10435 */
10436 ret = intel_ring_cacheline_align(ring);
10437 if (ret)
4fa62c89 10438 return ret;
f66fab8e 10439
ffe74d75 10440 ret = intel_ring_begin(ring, len);
7c9017e5 10441 if (ret)
4fa62c89 10442 return ret;
7c9017e5 10443
ffe74d75
CW		 10444 /* Unmask the flip-done completion message. Note that the bspec says that
10445 * we should do this for both the BCS and RCS, and that we must not unmask
10446 * more than one flip event at any time (or ensure that one flip message
10447 * can be sent by waiting for flip-done prior to queueing new flips).
10448 * Experimentation says that BCS works despite DERRMR masking all
10449 * flip-done completion events and that unmasking all planes at once
10450 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10451 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10452 */
10453 if (ring->id == RCS) {
10454 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10455 intel_ring_emit(ring, DERRMR);
10456 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10457 DERRMR_PIPEB_PRI_FLIP_DONE |
10458 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10459 if (IS_GEN8(dev))
10460 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10461 MI_SRM_LRM_GLOBAL_GTT);
10462 else
10463 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10464 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10465 intel_ring_emit(ring, DERRMR);
10466 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10467 if (IS_GEN8(dev)) {
10468 intel_ring_emit(ring, 0);
10469 intel_ring_emit(ring, MI_NOOP);
10470 }
ffe74d75
CW		 10471 }
10472
cb05d8de 10473 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10474 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10475 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10476 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10477
10478 intel_mark_page_flip_active(intel_crtc);
09246732 10479 __intel_ring_advance(ring);
83d4092b 10480 return 0;
7c9017e5
JB		 10481}
10482
84c33a64
SG		 10483static bool use_mmio_flip(struct intel_engine_cs *ring,
10484 struct drm_i915_gem_object *obj)
10485{
10486 /*
10487 * This is not being used for older platforms, because
10488 * non-availability of flip done interrupt forces us to use
10489 * CS flips. Older platforms derive flip done using some clever
10490 * tricks involving the flip_pending status bits and vblank irqs.
10491 * So using MMIO flips there would disrupt this mechanism.
10492 */
10493
8e09bf83
CW		 10494 if (ring == NULL)
10495 return true;
10496
84c33a64
SG		 10497 if (INTEL_INFO(ring->dev)->gen < 5)
10498 return false;
10499
10500 if (i915.use_mmio_flip < 0)
10501 return false;
10502 else if (i915.use_mmio_flip > 0)
10503 return true;
14bf993e
OM		 10504 else if (i915.enable_execlists)
10505 return true;
84c33a64 10506 else
41c52415 10507 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10508}
10509
ff944564
DL		 10510static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10511{
10512 struct drm_device *dev = intel_crtc->base.dev;
10513 struct drm_i915_private *dev_priv = dev->dev_private;
10514 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10515 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10516 struct drm_i915_gem_object *obj = intel_fb->obj;
10517 const enum pipe pipe = intel_crtc->pipe;
10518 u32 ctl, stride;
10519
10520 ctl = I915_READ(PLANE_CTL(pipe, 0));
10521 ctl &= ~PLANE_CTL_TILED_MASK;
10522 if (obj->tiling_mode == I915_TILING_X)
10523 ctl |= PLANE_CTL_TILED_X;
10524
10525 /*
10526 * The stride is either expressed as a multiple of 64 bytes chunks for
10527 * linear buffers or in number of tiles for tiled buffers.
10528 */
10529 stride = fb->pitches[0] >> 6;
10530 if (obj->tiling_mode == I915_TILING_X)
10531 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10532
10533 /*
10534 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10535 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10536 */
10537 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10538 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10539
10540 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10541 POSTING_READ(PLANE_SURF(pipe, 0));
10542}
10543
10544static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10545{
10546 struct drm_device *dev = intel_crtc->base.dev;
10547 struct drm_i915_private *dev_priv = dev->dev_private;
10548 struct intel_framebuffer *intel_fb =
10549 to_intel_framebuffer(intel_crtc->base.primary->fb);
10550 struct drm_i915_gem_object *obj = intel_fb->obj;
10551 u32 dspcntr;
10552 u32 reg;
10553
84c33a64
SG		 10554 reg = DSPCNTR(intel_crtc->plane);
10555 dspcntr = I915_READ(reg);
10556
c5d97472
DL		 10557 if (obj->tiling_mode != I915_TILING_NONE)
10558 dspcntr |= DISPPLANE_TILED;
10559 else
10560 dspcntr &= ~DISPPLANE_TILED;
10561
84c33a64
SG		 10562 I915_WRITE(reg, dspcntr);
10563
10564 I915_WRITE(DSPSURF(intel_crtc->plane),
10565 intel_crtc->unpin_work->gtt_offset);
10566 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10567
ff944564
DL		 10568}
10569
10570/*
10571 * XXX: This is the temporary way to update the plane registers until we get
10572 * around to using the usual plane update functions for MMIO flips
10573 */
10574static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10575{
10576 struct drm_device *dev = intel_crtc->base.dev;
10577 bool atomic_update;
10578 u32 start_vbl_count;
10579
10580 intel_mark_page_flip_active(intel_crtc);
10581
10582 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10583
10584 if (INTEL_INFO(dev)->gen >= 9)
10585 skl_do_mmio_flip(intel_crtc);
10586 else
10587 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10588 ilk_do_mmio_flip(intel_crtc);
10589
9362c7c5
ACO		 10590 if (atomic_update)
10591 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10592}
10593
9362c7c5 10594static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10595{
cc8c4cc2 10596 struct intel_crtc *crtc =
9362c7c5 10597 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10598 struct intel_mmio_flip *mmio_flip;
84c33a64 10599
cc8c4cc2
JH		 10600 mmio_flip = &crtc->mmio_flip;
10601 if (mmio_flip->req)
9c654818
JH		 10602 WARN_ON(__i915_wait_request(mmio_flip->req,
10603 crtc->reset_counter,
10604 false, NULL, NULL) != 0);
84c33a64 10605
cc8c4cc2
JH		 10606 intel_do_mmio_flip(crtc);
10607 if (mmio_flip->req) {
10608 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10609 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10610 mutex_unlock(&crtc->base.dev->struct_mutex);
10611 }
84c33a64
SG		 10612}
10613
10614static int intel_queue_mmio_flip(struct drm_device *dev,
10615 struct drm_crtc *crtc,
10616 struct drm_framebuffer *fb,
10617 struct drm_i915_gem_object *obj,
10618 struct intel_engine_cs *ring,
10619 uint32_t flags)
10620{
84c33a64 10621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10622
cc8c4cc2
JH		 10623 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10624 obj->last_write_req);
536f5b5e
ACO		 10625
10626 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10627
84c33a64
SG		 10628 return 0;
10629}
10630
8c9f3aaf
JB		 10631static int intel_default_queue_flip(struct drm_device *dev,
10632 struct drm_crtc *crtc,
10633 struct drm_framebuffer *fb,
ed8d1975 10634 struct drm_i915_gem_object *obj,
a4872ba6 10635 struct intel_engine_cs *ring,
ed8d1975 10636 uint32_t flags)
8c9f3aaf
JB		 10637{
10638 return -ENODEV;
10639}
10640
d6bbafa1
CW		 10641static bool __intel_pageflip_stall_check(struct drm_device *dev,
10642 struct drm_crtc *crtc)
10643{
10644 struct drm_i915_private *dev_priv = dev->dev_private;
10645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10646 struct intel_unpin_work *work = intel_crtc->unpin_work;
10647 u32 addr;
10648
10649 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10650 return true;
10651
10652 if (!work->enable_stall_check)
10653 return false;
10654
10655 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10656 if (work->flip_queued_req &&
10657 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10658 return false;
10659
1e3feefd 10660 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10661 }
10662
1e3feefd 10663 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10664 return false;
10665
10666 /* Potential stall - if we see that the flip has happened,
10667 * assume a missed interrupt. */
10668 if (INTEL_INFO(dev)->gen >= 4)
10669 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10670 else
10671 addr = I915_READ(DSPADDR(intel_crtc->plane));
10672
10673 /* There is a potential issue here with a false positive after a flip
10674 * to the same address. We could address this by checking for a
10675 * non-incrementing frame counter.
10676 */
10677 return addr == work->gtt_offset;
10678}
10679
10680void intel_check_page_flip(struct drm_device *dev, int pipe)
10681{
10682 struct drm_i915_private *dev_priv = dev->dev_private;
10683 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10685 struct intel_unpin_work *work;
f326038a 10686
6c51d46f 10687 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10688
10689 if (crtc == NULL)
10690 return;
10691
f326038a 10692 spin_lock(&dev->event_lock);
6ad790c0
CW		 10693 work = intel_crtc->unpin_work;
10694 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10695 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10696 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10697 page_flip_completed(intel_crtc);
6ad790c0 10698 work = NULL;
d6bbafa1 10699 }
6ad790c0
CW		 10700 if (work != NULL &&
10701 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10702 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10703 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10704}
10705
6b95a207
KH		 10706static int intel_crtc_page_flip(struct drm_crtc *crtc,
10707 struct drm_framebuffer *fb,
ed8d1975
KP		 10708 struct drm_pending_vblank_event *event,
10709 uint32_t page_flip_flags)
6b95a207
KH		 10710{
10711 struct drm_device *dev = crtc->dev;
10712 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10713 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10714 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10716 struct drm_plane *primary = crtc->primary;
a071fa00 10717 enum pipe pipe = intel_crtc->pipe;
6b95a207 10718 struct intel_unpin_work *work;
a4872ba6 10719 struct intel_engine_cs *ring;
cf5d8a46 10720 bool mmio_flip;
52e68630 10721 int ret;
6b95a207 10722
2ff8fde1
MR		 10723 /*
10724 * drm_mode_page_flip_ioctl() should already catch this, but double
10725 * check to be safe. In the future we may enable pageflipping from
10726 * a disabled primary plane.
10727 */
10728 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10729 return -EBUSY;
10730
e6a595d2 10731 /* Can't change pixel format via MI display flips. */
f4510a27 10732 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10733 return -EINVAL;
10734
10735 /*
10736 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10737 * Note that pitch changes could also affect these register.
10738 */
10739 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10740 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10741 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10742 return -EINVAL;
10743
f900db47
CW		 10744 if (i915_terminally_wedged(&dev_priv->gpu_error))
10745 goto out_hang;
10746
b14c5679 10747 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10748 if (work == NULL)
10749 return -ENOMEM;
10750
6b95a207 10751 work->event = event;
b4a98e57 10752 work->crtc = crtc;
ab8d6675 10753 work->old_fb = old_fb;
6b95a207
KH		 10754 INIT_WORK(&work->work, intel_unpin_work_fn);
10755
87b6b101 10756 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10757 if (ret)
10758 goto free_work;
10759
6b95a207 10760 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10761 spin_lock_irq(&dev->event_lock);
6b95a207 10762 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10763 /* Before declaring the flip queue wedged, check if
10764 * the hardware completed the operation behind our backs.
10765 */
10766 if (__intel_pageflip_stall_check(dev, crtc)) {
10767 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10768 page_flip_completed(intel_crtc);
10769 } else {
10770 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10771 spin_unlock_irq(&dev->event_lock);
468f0b44 10772
d6bbafa1
CW		 10773 drm_crtc_vblank_put(crtc);
10774 kfree(work);
10775 return -EBUSY;
10776 }
6b95a207
KH		 10777 }
10778 intel_crtc->unpin_work = work;
5e2d7afc 10779 spin_unlock_irq(&dev->event_lock);
6b95a207 10780
b4a98e57
CW		 10781 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10782 flush_workqueue(dev_priv->wq);
10783
75dfca80 10784 /* Reference the objects for the scheduled work. */
ab8d6675 10785 drm_framebuffer_reference(work->old_fb);
05394f39 10786 drm_gem_object_reference(&obj->base);
6b95a207 10787
f4510a27 10788 crtc->primary->fb = fb;
afd65eb4 10789 update_state_fb(crtc->primary);
1ed1f968 10790
e1f99ce6 10791 work->pending_flip_obj = obj;
e1f99ce6 10792
89ed88ba
CW		 10793 ret = i915_mutex_lock_interruptible(dev);
10794 if (ret)
10795 goto cleanup;
10796
b4a98e57 10797 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10798 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10799
75f7f3ec 10800 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10801 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10802
4fa62c89
VS		 10803 if (IS_VALLEYVIEW(dev)) {
10804 ring = &dev_priv->ring[BCS];
ab8d6675 10805 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10806 /* vlv: DISPLAY_FLIP fails to change tiling */
10807 ring = NULL;
48bf5b2d 10808 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10809 ring = &dev_priv->ring[BCS];
4fa62c89 10810 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10811 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10812 if (ring == NULL || ring->id != RCS)
10813 ring = &dev_priv->ring[BCS];
10814 } else {
10815 ring = &dev_priv->ring[RCS];
10816 }
10817
cf5d8a46
CW		 10818 mmio_flip = use_mmio_flip(ring, obj);
10819
10820 /* When using CS flips, we want to emit semaphores between rings.
10821 * However, when using mmio flips we will create a task to do the
10822 * synchronisation, so all we want here is to pin the framebuffer
10823 * into the display plane and skip any waits.
10824 */
82bc3b2d 10825 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10826 crtc->primary->state,
10827 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10828 if (ret)
10829 goto cleanup_pending;
6b95a207 10830
121920fa
TU		 10831 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10832 + intel_crtc->dspaddr_offset;
4fa62c89 10833
cf5d8a46 10834 if (mmio_flip) {
84c33a64
SG		 10835 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10836 page_flip_flags);
d6bbafa1
CW		 10837 if (ret)
10838 goto cleanup_unpin;
10839
f06cc1b9
JH		 10840 i915_gem_request_assign(&work->flip_queued_req,
10841 obj->last_write_req);
d6bbafa1 10842 } else {
84c33a64 10843 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10844 page_flip_flags);
10845 if (ret)
10846 goto cleanup_unpin;
10847
f06cc1b9
JH		 10848 i915_gem_request_assign(&work->flip_queued_req,
10849 intel_ring_get_request(ring));
d6bbafa1
CW		 10850 }
10851
1e3feefd 10852 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10853 work->enable_stall_check = true;
4fa62c89 10854
ab8d6675 10855 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10856 INTEL_FRONTBUFFER_PRIMARY(pipe));
10857
7ff0ebcc 10858 intel_fbc_disable(dev);
f99d7069 10859 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10860 mutex_unlock(&dev->struct_mutex);
10861
e5510fac
JB		 10862 trace_i915_flip_request(intel_crtc->plane, obj);
10863
6b95a207 10864 return 0;
96b099fd 10865
4fa62c89 10866cleanup_unpin:
82bc3b2d 10867 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10868cleanup_pending:
b4a98e57 10869 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10870 mutex_unlock(&dev->struct_mutex);
10871cleanup:
f4510a27 10872 crtc->primary->fb = old_fb;
afd65eb4 10873 update_state_fb(crtc->primary);
89ed88ba
CW		 10874
10875 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10876 drm_framebuffer_unreference(work->old_fb);
96b099fd 10877
5e2d7afc 10878 spin_lock_irq(&dev->event_lock);
96b099fd 10879 intel_crtc->unpin_work = NULL;
5e2d7afc 10880 spin_unlock_irq(&dev->event_lock);
96b099fd 10881
87b6b101 10882 drm_crtc_vblank_put(crtc);
7317c75e 10883free_work:
96b099fd
CW		 10884 kfree(work);
10885
f900db47
CW		 10886 if (ret == -EIO) {
10887out_hang:
53a366b9 10888 ret = intel_plane_restore(primary);
f0d3dad3 10889 if (ret == 0 && event) {
5e2d7afc 10890 spin_lock_irq(&dev->event_lock);
a071fa00 10891 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10892 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10893 }
f900db47 10894 }
96b099fd 10895 return ret;
6b95a207
KH		 10896}
10897
f6e5b160 10898static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10899 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10900 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10901 .atomic_begin = intel_begin_crtc_commit,
10902 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10903};
10904
9a935856
DV		 10905/**
10906 * intel_modeset_update_staged_output_state
10907 *
10908 * Updates the staged output configuration state, e.g. after we've read out the
10909 * current hw state.
10910 */
10911static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10912{
7668851f 10913 struct intel_crtc *crtc;
9a935856
DV		 10914 struct intel_encoder *encoder;
10915 struct intel_connector *connector;
f6e5b160 10916
3a3371ff 10917 for_each_intel_connector(dev, connector) {
9a935856
DV		 10918 connector->new_encoder =
10919 to_intel_encoder(connector->base.encoder);
10920 }
f6e5b160 10921
b2784e15 10922 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10923 encoder->new_crtc =
10924 to_intel_crtc(encoder->base.crtc);
10925 }
7668851f 10926
d3fcc808 10927 for_each_intel_crtc(dev, crtc) {
83d65738 10928 crtc->new_enabled = crtc->base.state->enable;
7668851f 10929 }
f6e5b160
CW		 10930}
10931
d29b2f9d
ACO		 10932/* Transitional helper to copy current connector/encoder state to
10933 * connector->state. This is needed so that code that is partially
10934 * converted to atomic does the right thing.
10935 */
10936static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10937{
10938 struct intel_connector *connector;
10939
10940 for_each_intel_connector(dev, connector) {
10941 if (connector->base.encoder) {
10942 connector->base.state->best_encoder =
10943 connector->base.encoder;
10944 connector->base.state->crtc =
10945 connector->base.encoder->crtc;
10946 } else {
10947 connector->base.state->best_encoder = NULL;
10948 connector->base.state->crtc = NULL;
10949 }
10950 }
10951}
10952
9a935856
DV		 10953/**
10954 * intel_modeset_commit_output_state
10955 *
10956 * This function copies the stage display pipe configuration to the real one.
10957 */
10958static void intel_modeset_commit_output_state(struct drm_device *dev)
10959{
7668851f 10960 struct intel_crtc *crtc;
9a935856
DV		 10961 struct intel_encoder *encoder;
10962 struct intel_connector *connector;
f6e5b160 10963
3a3371ff 10964 for_each_intel_connector(dev, connector) {
9a935856
DV		 10965 connector->base.encoder = &connector->new_encoder->base;
10966 }
f6e5b160 10967
b2784e15 10968 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10969 encoder->base.crtc = &encoder->new_crtc->base;
10970 }
7668851f 10971
d3fcc808 10972 for_each_intel_crtc(dev, crtc) {
83d65738 10973 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10974 crtc->base.enabled = crtc->new_enabled;
10975 }
d29b2f9d
ACO		 10976
10977 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10978}
10979
050f7aeb 10980static void
eba905b2 10981connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10982 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10983{
10984 int bpp = pipe_config->pipe_bpp;
10985
10986 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10987 connector->base.base.id,
c23cc417 10988 connector->base.name);
050f7aeb
DV		 10989
10990 /* Don't use an invalid EDID bpc value */
10991 if (connector->base.display_info.bpc &&
10992 connector->base.display_info.bpc * 3 < bpp) {
10993 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10994 bpp, connector->base.display_info.bpc*3);
10995 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10996 }
10997
10998 /* Clamp bpp to 8 on screens without EDID 1.4 */
10999 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11000 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11001 bpp);
11002 pipe_config->pipe_bpp = 24;
11003 }
11004}
11005
4e53c2e0 11006static int
050f7aeb 11007compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11008 struct intel_crtc_state *pipe_config)
4e53c2e0 11009{
050f7aeb 11010 struct drm_device *dev = crtc->base.dev;
1486017f 11011 struct drm_atomic_state *state;
050f7aeb 11012 struct intel_connector *connector;
1486017f 11013 int bpp, i;
4e53c2e0 11014
d328c9d7 11015 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11016 bpp = 10*3;
d328c9d7
DV		 11017 else if (INTEL_INFO(dev)->gen >= 5)
11018 bpp = 12*3;
11019 else
11020 bpp = 8*3;
11021
4e53c2e0 11022
4e53c2e0
DV		 11023 pipe_config->pipe_bpp = bpp;
11024
1486017f
ACO		 11025 state = pipe_config->base.state;
11026
4e53c2e0 11027 /* Clamp display bpp to EDID value */
1486017f
ACO		 11028 for (i = 0; i < state->num_connector; i++) {
11029 if (!state->connectors[i])
11030 continue;
11031
11032 connector = to_intel_connector(state->connectors[i]);
11033 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 11034 continue;
11035
050f7aeb 11036 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 11037 }
11038
11039 return bpp;
11040}
11041
644db711
DV		 11042static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11043{
11044 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11045 "type: 0x%x flags: 0x%x\n",
1342830c 11046 mode->crtc_clock,
644db711
DV		 11047 mode->crtc_hdisplay, mode->crtc_hsync_start,
11048 mode->crtc_hsync_end, mode->crtc_htotal,
11049 mode->crtc_vdisplay, mode->crtc_vsync_start,
11050 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11051}
11052
c0b03411 11053static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11054 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11055 const char *context)
11056{
6a60cd87
CK		 11057 struct drm_device *dev = crtc->base.dev;
11058 struct drm_plane *plane;
11059 struct intel_plane *intel_plane;
11060 struct intel_plane_state *state;
11061 struct drm_framebuffer *fb;
11062
11063 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11064 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11065
11066 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11067 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11068 pipe_config->pipe_bpp, pipe_config->dither);
11069 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11070 pipe_config->has_pch_encoder,
11071 pipe_config->fdi_lanes,
11072 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11073 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11074 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11075 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11076 pipe_config->has_dp_encoder,
11077 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11078 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11079 pipe_config->dp_m_n.tu);
b95af8be
VK		 11080
11081 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11082 pipe_config->has_dp_encoder,
11083 pipe_config->dp_m2_n2.gmch_m,
11084 pipe_config->dp_m2_n2.gmch_n,
11085 pipe_config->dp_m2_n2.link_m,
11086 pipe_config->dp_m2_n2.link_n,
11087 pipe_config->dp_m2_n2.tu);
11088
55072d19
DV		 11089 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11090 pipe_config->has_audio,
11091 pipe_config->has_infoframe);
11092
c0b03411 11093 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11094 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11095 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11096 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11097 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11098 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11099 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11100 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11101 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11102 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11103 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11104 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11105 pipe_config->gmch_pfit.control,
11106 pipe_config->gmch_pfit.pgm_ratios,
11107 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11108 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11109 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11110 pipe_config->pch_pfit.size,
11111 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11112 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11113 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11114
11115 DRM_DEBUG_KMS("planes on this crtc\n");
11116 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11117 intel_plane = to_intel_plane(plane);
11118 if (intel_plane->pipe != crtc->pipe)
11119 continue;
11120
11121 state = to_intel_plane_state(plane->state);
11122 fb = state->base.fb;
11123 if (!fb) {
11124 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11125 "disabled, scaler_id = %d\n",
11126 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11127 plane->base.id, intel_plane->pipe,
11128 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11129 drm_plane_index(plane), state->scaler_id);
11130 continue;
11131 }
11132
11133 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11134 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11135 plane->base.id, intel_plane->pipe,
11136 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11137 drm_plane_index(plane));
11138 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11139 fb->base.id, fb->width, fb->height, fb->pixel_format);
11140 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11141 state->scaler_id,
11142 state->src.x1 >> 16, state->src.y1 >> 16,
11143 drm_rect_width(&state->src) >> 16,
11144 drm_rect_height(&state->src) >> 16,
11145 state->dst.x1, state->dst.y1,
11146 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11147 }
c0b03411
DV		 11148}
11149
bc079e8b
VS		 11150static bool encoders_cloneable(const struct intel_encoder *a,
11151 const struct intel_encoder *b)
accfc0c5 11152{
bc079e8b
VS		 11153 /* masks could be asymmetric, so check both ways */
11154 return a == b || (a->cloneable & (1 << b->type) &&
11155 b->cloneable & (1 << a->type));
11156}
11157
98a221da
ACO		 11158static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11159 struct intel_crtc *crtc,
bc079e8b
VS		 11160 struct intel_encoder *encoder)
11161{
bc079e8b 11162 struct intel_encoder *source_encoder;
98a221da
ACO		 11163 struct drm_connector_state *connector_state;
11164 int i;
11165
11166 for (i = 0; i < state->num_connector; i++) {
11167 if (!state->connectors[i])
11168 continue;
bc079e8b 11169
98a221da
ACO		 11170 connector_state = state->connector_states[i];
11171 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11172 continue;
11173
98a221da
ACO		 11174 source_encoder =
11175 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11176 if (!encoders_cloneable(encoder, source_encoder))
11177 return false;
11178 }
11179
11180 return true;
11181}
11182
98a221da
ACO		 11183static bool check_encoder_cloning(struct drm_atomic_state *state,
11184 struct intel_crtc *crtc)
bc079e8b 11185{
accfc0c5 11186 struct intel_encoder *encoder;
98a221da
ACO		 11187 struct drm_connector_state *connector_state;
11188 int i;
accfc0c5 11189
98a221da
ACO		 11190 for (i = 0; i < state->num_connector; i++) {
11191 if (!state->connectors[i])
accfc0c5
DV		 11192 continue;
11193
98a221da
ACO		 11194 connector_state = state->connector_states[i];
11195 if (connector_state->crtc != &crtc->base)
11196 continue;
11197
11198 encoder = to_intel_encoder(connector_state->best_encoder);
11199 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11200 return false;
accfc0c5
DV		 11201 }
11202
bc079e8b 11203 return true;
accfc0c5
DV		 11204}
11205
5448a00d 11206static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11207{
5448a00d
ACO		 11208 struct drm_device *dev = state->dev;
11209 struct intel_encoder *encoder;
11210 struct drm_connector_state *connector_state;
00f0b378 11211 unsigned int used_ports = 0;
5448a00d 11212 int i;
00f0b378
VS		 11213
11214 /*
11215 * Walk the connector list instead of the encoder
11216 * list to detect the problem on ddi platforms
11217 * where there's just one encoder per digital port.
11218 */
5448a00d
ACO		 11219 for (i = 0; i < state->num_connector; i++) {
11220 if (!state->connectors[i])
11221 continue;
00f0b378 11222
5448a00d
ACO		 11223 connector_state = state->connector_states[i];
11224 if (!connector_state->best_encoder)
00f0b378
VS		 11225 continue;
11226
5448a00d
ACO		 11227 encoder = to_intel_encoder(connector_state->best_encoder);
11228
11229 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11230
11231 switch (encoder->type) {
11232 unsigned int port_mask;
11233 case INTEL_OUTPUT_UNKNOWN:
11234 if (WARN_ON(!HAS_DDI(dev)))
11235 break;
11236 case INTEL_OUTPUT_DISPLAYPORT:
11237 case INTEL_OUTPUT_HDMI:
11238 case INTEL_OUTPUT_EDP:
11239 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11240
11241 /* the same port mustn't appear more than once */
11242 if (used_ports & port_mask)
11243 return false;
11244
11245 used_ports |= port_mask;
11246 default:
11247 break;
11248 }
11249 }
11250
11251 return true;
11252}
11253
83a57153
ACO		 11254static void
11255clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11256{
11257 struct drm_crtc_state tmp_state;
663a3640 11258 struct intel_crtc_scaler_state scaler_state;
83a57153 11259
663a3640 11260 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11261 tmp_state = crtc_state->base;
663a3640 11262 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11263 memset(crtc_state, 0, sizeof *crtc_state);
11264 crtc_state->base = tmp_state;
663a3640 11265 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11266}
11267
5cec258b 11268static struct intel_crtc_state *
b8cecdf5 11269intel_modeset_pipe_config(struct drm_crtc *crtc,
83a57153
ACO		 11270 struct drm_display_mode *mode,
11271 struct drm_atomic_state *state)
ee7b9f93 11272{
7758a113 11273 struct intel_encoder *encoder;
0b901879
ACO		 11274 struct intel_connector *connector;
11275 struct drm_connector_state *connector_state;
5cec258b 11276 struct intel_crtc_state *pipe_config;
d328c9d7 11277 int base_bpp, ret = -EINVAL;
0b901879 11278 int i;
e29c22c0 11279 bool retry = true;
ee7b9f93 11280
98a221da 11281 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11282 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11283 return ERR_PTR(-EINVAL);
11284 }
11285
5448a00d 11286 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11287 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11288 return ERR_PTR(-EINVAL);
11289 }
11290
83a57153
ACO		 11291 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11292 if (IS_ERR(pipe_config))
11293 return pipe_config;
11294
11295 clear_intel_crtc_state(pipe_config);
7758a113 11296
07878248 11297 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11298 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11299 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11300
e143a21c
DV		 11301 pipe_config->cpu_transcoder =
11302 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11303 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11304
2960bc9c
ID		 11305 /*
11306 * Sanitize sync polarity flags based on requested ones. If neither
11307 * positive or negative polarity is requested, treat this as meaning
11308 * negative polarity.
11309 */
2d112de7 11310 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11311 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11312 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11313
2d112de7 11314 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11315 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11316 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11317
050f7aeb
DV		 11318 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11319 * plane pixel format and any sink constraints into account. Returns the
11320 * source plane bpp so that dithering can be selected on mismatches
11321 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11322 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11323 pipe_config);
11324 if (base_bpp < 0)
4e53c2e0
DV		 11325 goto fail;
11326
e41a56be
VS		 11327 /*
11328 * Determine the real pipe dimensions. Note that stereo modes can
11329 * increase the actual pipe size due to the frame doubling and
11330 * insertion of additional space for blanks between the frame. This
11331 * is stored in the crtc timings. We use the requested mode to do this
11332 * computation to clearly distinguish it from the adjusted mode, which
11333 * can be changed by the connectors in the below retry loop.
11334 */
2d112de7 11335 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11336 &pipe_config->pipe_src_w,
11337 &pipe_config->pipe_src_h);
e41a56be 11338
e29c22c0 11339encoder_retry:
ef1b460d 11340 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11341 pipe_config->port_clock = 0;
ef1b460d 11342 pipe_config->pixel_multiplier = 1;
ff9a6750 11343
135c81b8 11344 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11345 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11346 CRTC_STEREO_DOUBLE);
135c81b8 11347
7758a113
DV		 11348 /* Pass our mode to the connectors and the CRTC to give them a chance to
11349 * adjust it according to limitations or connector properties, and also
11350 * a chance to reject the mode entirely.
47f1c6c9 11351 */
0b901879
ACO		 11352 for (i = 0; i < state->num_connector; i++) {
11353 connector = to_intel_connector(state->connectors[i]);
11354 if (!connector)
11355 continue;
47f1c6c9 11356
0b901879
ACO		 11357 connector_state = state->connector_states[i];
11358 if (connector_state->crtc != crtc)
7758a113 11359 continue;
7ae89233 11360
0b901879
ACO		 11361 encoder = to_intel_encoder(connector_state->best_encoder);
11362
efea6e8e
DV		 11363 if (!(encoder->compute_config(encoder, pipe_config))) {
11364 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11365 goto fail;
11366 }
ee7b9f93 11367 }
47f1c6c9 11368
ff9a6750
DV		 11369 /* Set default port clock if not overwritten by the encoder. Needs to be
11370 * done afterwards in case the encoder adjusts the mode. */
11371 if (!pipe_config->port_clock)
2d112de7 11372 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11373 * pipe_config->pixel_multiplier;
ff9a6750 11374
a43f6e0f 11375 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11376 if (ret < 0) {
7758a113
DV		 11377 DRM_DEBUG_KMS("CRTC fixup failed\n");
11378 goto fail;
ee7b9f93 11379 }
e29c22c0
DV		 11380
11381 if (ret == RETRY) {
11382 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11383 ret = -EINVAL;
11384 goto fail;
11385 }
11386
11387 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11388 retry = false;
11389 goto encoder_retry;
11390 }
11391
d328c9d7 11392 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11393 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11394 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11395
b8cecdf5 11396 return pipe_config;
7758a113 11397fail:
e29c22c0 11398 return ERR_PTR(ret);
ee7b9f93 11399}
47f1c6c9 11400
e2e1ed41
DV		 11401/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11402 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11403static void
11404intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11405 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11406{
11407 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11408 struct drm_device *dev = crtc->dev;
11409 struct intel_encoder *encoder;
11410 struct intel_connector *connector;
11411 struct drm_crtc *tmp_crtc;
79e53945 11412
e2e1ed41 11413 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11414
e2e1ed41
DV		 11415 /* Check which crtcs have changed outputs connected to them, these need
11416 * to be part of the prepare_pipes mask. We don't (yet) support global
11417 * modeset across multiple crtcs, so modeset_pipes will only have one
11418 * bit set at most. */
3a3371ff 11419 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11420 if (connector->base.encoder == &connector->new_encoder->base)
11421 continue;
79e53945 11422
e2e1ed41
DV		 11423 if (connector->base.encoder) {
11424 tmp_crtc = connector->base.encoder->crtc;
11425
11426 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11427 }
11428
11429 if (connector->new_encoder)
11430 *prepare_pipes |=
11431 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11432 }
11433
b2784e15 11434 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11435 if (encoder->base.crtc == &encoder->new_crtc->base)
11436 continue;
11437
11438 if (encoder->base.crtc) {
11439 tmp_crtc = encoder->base.crtc;
11440
11441 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11442 }
11443
11444 if (encoder->new_crtc)
11445 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11446 }
11447
7668851f 11448 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11449 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11450 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11451 continue;
7e7d76c3 11452
7668851f 11453 if (!intel_crtc->new_enabled)
e2e1ed41 11454 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11455 else
11456 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11457 }
11458
e2e1ed41
DV		 11459
11460 /* set_mode is also used to update properties on life display pipes. */
11461 intel_crtc = to_intel_crtc(crtc);
7668851f 11462 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11463 *prepare_pipes |= 1 << intel_crtc->pipe;
11464
b6c5164d
DV		 11465 /*
11466 * For simplicity do a full modeset on any pipe where the output routing
11467 * changed. We could be more clever, but that would require us to be
11468 * more careful with calling the relevant encoder->mode_set functions.
11469 */
e2e1ed41
DV		 11470 if (*prepare_pipes)
11471 *modeset_pipes = *prepare_pipes;
11472
11473 /* ... and mask these out. */
11474 *modeset_pipes &= ~(*disable_pipes);
11475 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11476
11477 /*
11478 * HACK: We don't (yet) fully support global modesets. intel_set_config
11479 * obies this rule, but the modeset restore mode of
11480 * intel_modeset_setup_hw_state does not.
11481 */
11482 *modeset_pipes &= 1 << intel_crtc->pipe;
11483 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11484
11485 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11486 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11487}
79e53945 11488
ea9d758d 11489static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11490{
ea9d758d 11491 struct drm_encoder *encoder;
f6e5b160 11492 struct drm_device *dev = crtc->dev;
f6e5b160 11493
ea9d758d
DV		 11494 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11495 if (encoder->crtc == crtc)
11496 return true;
11497
11498 return false;
11499}
11500
11501static void
11502intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11503{
ba41c0de 11504 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11505 struct intel_encoder *intel_encoder;
11506 struct intel_crtc *intel_crtc;
11507 struct drm_connector *connector;
11508
ba41c0de
DV		 11509 intel_shared_dpll_commit(dev_priv);
11510
b2784e15 11511 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11512 if (!intel_encoder->base.crtc)
11513 continue;
11514
11515 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11516
11517 if (prepare_pipes & (1 << intel_crtc->pipe))
11518 intel_encoder->connectors_active = false;
11519 }
11520
11521 intel_modeset_commit_output_state(dev);
11522
7668851f 11523 /* Double check state. */
d3fcc808 11524 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11525 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11526 }
11527
11528 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11529 if (!connector->encoder || !connector->encoder->crtc)
11530 continue;
11531
11532 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11533
11534 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11535 struct drm_property *dpms_property =
11536 dev->mode_config.dpms_property;
11537
ea9d758d 11538 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11539 drm_object_property_set_value(&connector->base,
68d34720
DV		 11540 dpms_property,
11541 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11542
11543 intel_encoder = to_intel_encoder(connector->encoder);
11544 intel_encoder->connectors_active = true;
11545 }
11546 }
11547
11548}
11549
3bd26263 11550static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11551{
3bd26263 11552 int diff;
f1f644dc
JB		 11553
11554 if (clock1 == clock2)
11555 return true;
11556
11557 if (!clock1 || !clock2)
11558 return false;
11559
11560 diff = abs(clock1 - clock2);
11561
11562 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11563 return true;
11564
11565 return false;
11566}
11567
25c5b266
DV		 11568#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11569 list_for_each_entry((intel_crtc), \
11570 &(dev)->mode_config.crtc_list, \
11571 base.head) \
0973f18f 11572 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11573
0e8ffe1b 11574static bool
2fa2fe9a 11575intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11576 struct intel_crtc_state *current_config,
11577 struct intel_crtc_state *pipe_config)
0e8ffe1b 11578{
66e985c0
DV		 11579#define PIPE_CONF_CHECK_X(name) \
11580 if (current_config->name != pipe_config->name) { \
11581 DRM_ERROR("mismatch in " #name " " \
11582 "(expected 0x%08x, found 0x%08x)\n", \
11583 current_config->name, \
11584 pipe_config->name); \
11585 return false; \
11586 }
11587
08a24034
DV		 11588#define PIPE_CONF_CHECK_I(name) \
11589 if (current_config->name != pipe_config->name) { \
11590 DRM_ERROR("mismatch in " #name " " \
11591 "(expected %i, found %i)\n", \
11592 current_config->name, \
11593 pipe_config->name); \
11594 return false; \
88adfff1
DV		 11595 }
11596
b95af8be
VK		 11597/* This is required for BDW+ where there is only one set of registers for
11598 * switching between high and low RR.
11599 * This macro can be used whenever a comparison has to be made between one
11600 * hw state and multiple sw state variables.
11601 */
11602#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11603 if ((current_config->name != pipe_config->name) && \
11604 (current_config->alt_name != pipe_config->name)) { \
11605 DRM_ERROR("mismatch in " #name " " \
11606 "(expected %i or %i, found %i)\n", \
11607 current_config->name, \
11608 current_config->alt_name, \
11609 pipe_config->name); \
11610 return false; \
11611 }
11612
1bd1bd80
DV		 11613#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11614 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11615 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11616 "(expected %i, found %i)\n", \
11617 current_config->name & (mask), \
11618 pipe_config->name & (mask)); \
11619 return false; \
11620 }
11621
5e550656
VS		 11622#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11623 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11624 DRM_ERROR("mismatch in " #name " " \
11625 "(expected %i, found %i)\n", \
11626 current_config->name, \
11627 pipe_config->name); \
11628 return false; \
11629 }
11630
bb760063
DV		 11631#define PIPE_CONF_QUIRK(quirk) \
11632 ((current_config->quirks | pipe_config->quirks) & (quirk))
11633
eccb140b
DV		 11634 PIPE_CONF_CHECK_I(cpu_transcoder);
11635
08a24034
DV		 11636 PIPE_CONF_CHECK_I(has_pch_encoder);
11637 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11638 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11639 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11640 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11641 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11642 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11643
eb14cb74 11644 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11645
11646 if (INTEL_INFO(dev)->gen < 8) {
11647 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11648 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11649 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11650 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11651 PIPE_CONF_CHECK_I(dp_m_n.tu);
11652
11653 if (current_config->has_drrs) {
11654 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11655 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11656 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11657 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11658 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11659 }
11660 } else {
11661 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11662 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11663 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11664 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11665 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11666 }
eb14cb74 11667
2d112de7
ACO		 11668 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11669 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11670 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11671 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11672 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11673 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11674
2d112de7
ACO		 11675 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11676 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11677 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11678 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11679 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11680 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11681
c93f54cf 11682 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11683 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11684 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11685 IS_VALLEYVIEW(dev))
11686 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11687 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11688
9ed109a7
DV		 11689 PIPE_CONF_CHECK_I(has_audio);
11690
2d112de7 11691 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11692 DRM_MODE_FLAG_INTERLACE);
11693
bb760063 11694 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11695 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11696 DRM_MODE_FLAG_PHSYNC);
2d112de7 11697 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11698 DRM_MODE_FLAG_NHSYNC);
2d112de7 11699 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11700 DRM_MODE_FLAG_PVSYNC);
2d112de7 11701 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11702 DRM_MODE_FLAG_NVSYNC);
11703 }
045ac3b5 11704
37327abd
VS		 11705 PIPE_CONF_CHECK_I(pipe_src_w);
11706 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11707
9953599b
DV		 11708 /*
11709 * FIXME: BIOS likes to set up a cloned config with lvds+external
11710 * screen. Since we don't yet re-compute the pipe config when moving
11711 * just the lvds port away to another pipe the sw tracking won't match.
11712 *
11713 * Proper atomic modesets with recomputed global state will fix this.
11714 * Until then just don't check gmch state for inherited modes.
11715 */
11716 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11717 PIPE_CONF_CHECK_I(gmch_pfit.control);
11718 /* pfit ratios are autocomputed by the hw on gen4+ */
11719 if (INTEL_INFO(dev)->gen < 4)
11720 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11721 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11722 }
11723
fd4daa9c
CW		 11724 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11725 if (current_config->pch_pfit.enabled) {
11726 PIPE_CONF_CHECK_I(pch_pfit.pos);
11727 PIPE_CONF_CHECK_I(pch_pfit.size);
11728 }
2fa2fe9a 11729
a1b2278e
CK		 11730 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11731
e59150dc
JB		 11732 /* BDW+ don't expose a synchronous way to read the state */
11733 if (IS_HASWELL(dev))
11734 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11735
282740f7
VS		 11736 PIPE_CONF_CHECK_I(double_wide);
11737
26804afd
DV		 11738 PIPE_CONF_CHECK_X(ddi_pll_sel);
11739
c0d43d62 11740 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11741 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11742 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11743 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11744 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11745 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11746 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11747 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11748 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11749
42571aef
VS		 11750 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11751 PIPE_CONF_CHECK_I(pipe_bpp);
11752
2d112de7 11753 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11754 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11755
66e985c0 11756#undef PIPE_CONF_CHECK_X
08a24034 11757#undef PIPE_CONF_CHECK_I
b95af8be 11758#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11759#undef PIPE_CONF_CHECK_FLAGS
5e550656 11760#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11761#undef PIPE_CONF_QUIRK
88adfff1 11762
0e8ffe1b
DV		 11763 return true;
11764}
11765
08db6652
DL		 11766static void check_wm_state(struct drm_device *dev)
11767{
11768 struct drm_i915_private *dev_priv = dev->dev_private;
11769 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11770 struct intel_crtc *intel_crtc;
11771 int plane;
11772
11773 if (INTEL_INFO(dev)->gen < 9)
11774 return;
11775
11776 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11777 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11778
11779 for_each_intel_crtc(dev, intel_crtc) {
11780 struct skl_ddb_entry *hw_entry, *sw_entry;
11781 const enum pipe pipe = intel_crtc->pipe;
11782
11783 if (!intel_crtc->active)
11784 continue;
11785
11786 /* planes */
dd740780 11787 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11788 hw_entry = &hw_ddb.plane[pipe][plane];
11789 sw_entry = &sw_ddb->plane[pipe][plane];
11790
11791 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11792 continue;
11793
11794 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11795 "(expected (%u,%u), found (%u,%u))\n",
11796 pipe_name(pipe), plane + 1,
11797 sw_entry->start, sw_entry->end,
11798 hw_entry->start, hw_entry->end);
11799 }
11800
11801 /* cursor */
11802 hw_entry = &hw_ddb.cursor[pipe];
11803 sw_entry = &sw_ddb->cursor[pipe];
11804
11805 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11806 continue;
11807
11808 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11809 "(expected (%u,%u), found (%u,%u))\n",
11810 pipe_name(pipe),
11811 sw_entry->start, sw_entry->end,
11812 hw_entry->start, hw_entry->end);
11813 }
11814}
11815
91d1b4bd
DV		 11816static void
11817check_connector_state(struct drm_device *dev)
8af6cf88 11818{
8af6cf88
DV		 11819 struct intel_connector *connector;
11820
3a3371ff 11821 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11822 /* This also checks the encoder/connector hw state with the
11823 * ->get_hw_state callbacks. */
11824 intel_connector_check_state(connector);
11825
e2c719b7 11826 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11827 "connector's staged encoder doesn't match current encoder\n");
11828 }
91d1b4bd
DV		 11829}
11830
11831static void
11832check_encoder_state(struct drm_device *dev)
11833{
11834 struct intel_encoder *encoder;
11835 struct intel_connector *connector;
8af6cf88 11836
b2784e15 11837 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11838 bool enabled = false;
11839 bool active = false;
11840 enum pipe pipe, tracked_pipe;
11841
11842 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11843 encoder->base.base.id,
8e329a03 11844 encoder->base.name);
8af6cf88 11845
e2c719b7 11846 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11847 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11848 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11849 "encoder's active_connectors set, but no crtc\n");
11850
3a3371ff 11851 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11852 if (connector->base.encoder != &encoder->base)
11853 continue;
11854 enabled = true;
11855 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11856 active = true;
11857 }
0e32b39c
DA		 11858 /*
11859 * for MST connectors if we unplug the connector is gone
11860 * away but the encoder is still connected to a crtc
11861 * until a modeset happens in response to the hotplug.
11862 */
11863 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11864 continue;
11865
e2c719b7 11866 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11867 "encoder's enabled state mismatch "
11868 "(expected %i, found %i)\n",
11869 !!encoder->base.crtc, enabled);
e2c719b7 11870 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11871 "active encoder with no crtc\n");
11872
e2c719b7 11873 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11874 "encoder's computed active state doesn't match tracked active state "
11875 "(expected %i, found %i)\n", active, encoder->connectors_active);
11876
11877 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11878 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11879 "encoder's hw state doesn't match sw tracking "
11880 "(expected %i, found %i)\n",
11881 encoder->connectors_active, active);
11882
11883 if (!encoder->base.crtc)
11884 continue;
11885
11886 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11887 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11888 "active encoder's pipe doesn't match"
11889 "(expected %i, found %i)\n",
11890 tracked_pipe, pipe);
11891
11892 }
91d1b4bd
DV		 11893}
11894
11895static void
11896check_crtc_state(struct drm_device *dev)
11897{
fbee40df 11898 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11899 struct intel_crtc *crtc;
11900 struct intel_encoder *encoder;
5cec258b 11901 struct intel_crtc_state pipe_config;
8af6cf88 11902
d3fcc808 11903 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11904 bool enabled = false;
11905 bool active = false;
11906
045ac3b5
JB		 11907 memset(&pipe_config, 0, sizeof(pipe_config));
11908
8af6cf88
DV		 11909 DRM_DEBUG_KMS("[CRTC:%d]\n",
11910 crtc->base.base.id);
11911
83d65738 11912 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11913 "active crtc, but not enabled in sw tracking\n");
11914
b2784e15 11915 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11916 if (encoder->base.crtc != &crtc->base)
11917 continue;
11918 enabled = true;
11919 if (encoder->connectors_active)
11920 active = true;
11921 }
6c49f241 11922
e2c719b7 11923 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11924 "crtc's computed active state doesn't match tracked active state "
11925 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11926 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11927 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11928 "(expected %i, found %i)\n", enabled,
11929 crtc->base.state->enable);
8af6cf88 11930
0e8ffe1b
DV		 11931 active = dev_priv->display.get_pipe_config(crtc,
11932 &pipe_config);
d62cf62a 11933
b6b5d049
VS		 11934 /* hw state is inconsistent with the pipe quirk */
11935 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11936 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11937 active = crtc->active;
11938
b2784e15 11939 for_each_intel_encoder(dev, encoder) {
3eaba51c 11940 enum pipe pipe;
6c49f241
DV		 11941 if (encoder->base.crtc != &crtc->base)
11942 continue;
1d37b689 11943 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11944 encoder->get_config(encoder, &pipe_config);
11945 }
11946
e2c719b7 11947 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11948 "crtc active state doesn't match with hw state "
11949 "(expected %i, found %i)\n", crtc->active, active);
11950
c0b03411 11951 if (active &&
6e3c9717 11952 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11953 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11954 intel_dump_pipe_config(crtc, &pipe_config,
11955 "[hw state]");
6e3c9717 11956 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11957 "[sw state]");
11958 }
8af6cf88
DV		 11959 }
11960}
11961
91d1b4bd
DV		 11962static void
11963check_shared_dpll_state(struct drm_device *dev)
11964{
fbee40df 11965 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11966 struct intel_crtc *crtc;
11967 struct intel_dpll_hw_state dpll_hw_state;
11968 int i;
5358901f
DV		 11969
11970 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11971 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11972 int enabled_crtcs = 0, active_crtcs = 0;
11973 bool active;
11974
11975 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11976
11977 DRM_DEBUG_KMS("%s\n", pll->name);
11978
11979 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11980
e2c719b7 11981 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11982 "more active pll users than references: %i vs %i\n",
3e369b76 11983 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11984 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11985 "pll in active use but not on in sw tracking\n");
e2c719b7 11986 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11987 "pll in on but not on in use in sw tracking\n");
e2c719b7 11988 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11989 "pll on state mismatch (expected %i, found %i)\n",
11990 pll->on, active);
11991
d3fcc808 11992 for_each_intel_crtc(dev, crtc) {
83d65738 11993 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11994 enabled_crtcs++;
11995 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11996 active_crtcs++;
11997 }
e2c719b7 11998 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11999 "pll active crtcs mismatch (expected %i, found %i)\n",
12000 pll->active, active_crtcs);
e2c719b7 12001 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12002 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12003 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12004
e2c719b7 12005 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12006 sizeof(dpll_hw_state)),
12007 "pll hw state mismatch\n");
5358901f 12008 }
8af6cf88
DV		 12009}
12010
91d1b4bd
DV		 12011void
12012intel_modeset_check_state(struct drm_device *dev)
12013{
08db6652 12014 check_wm_state(dev);
91d1b4bd
DV		 12015 check_connector_state(dev);
12016 check_encoder_state(dev);
12017 check_crtc_state(dev);
12018 check_shared_dpll_state(dev);
12019}
12020
5cec258b 12021void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12022 int dotclock)
12023{
12024 /*
12025 * FDI already provided one idea for the dotclock.
12026 * Yell if the encoder disagrees.
12027 */
2d112de7 12028 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12029 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12030 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12031}
12032
80715b2f
VS		 12033static void update_scanline_offset(struct intel_crtc *crtc)
12034{
12035 struct drm_device *dev = crtc->base.dev;
12036
12037 /*
12038 * The scanline counter increments at the leading edge of hsync.
12039 *
12040 * On most platforms it starts counting from vtotal-1 on the
12041 * first active line. That means the scanline counter value is
12042 * always one less than what we would expect. Ie. just after
12043 * start of vblank, which also occurs at start of hsync (on the
12044 * last active line), the scanline counter will read vblank_start-1.
12045 *
12046 * On gen2 the scanline counter starts counting from 1 instead
12047 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12048 * to keep the value positive), instead of adding one.
12049 *
12050 * On HSW+ the behaviour of the scanline counter depends on the output
12051 * type. For DP ports it behaves like most other platforms, but on HDMI
12052 * there's an extra 1 line difference. So we need to add two instead of
12053 * one to the value.
12054 */
12055 if (IS_GEN2(dev)) {
6e3c9717 12056 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12057 int vtotal;
12058
12059 vtotal = mode->crtc_vtotal;
12060 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12061 vtotal /= 2;
12062
12063 crtc->scanline_offset = vtotal - 1;
12064 } else if (HAS_DDI(dev) &&
409ee761 12065 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12066 crtc->scanline_offset = 2;
12067 } else
12068 crtc->scanline_offset = 1;
12069}
12070
5cec258b 12071static struct intel_crtc_state *
7f27126e
JB		 12072intel_modeset_compute_config(struct drm_crtc *crtc,
12073 struct drm_display_mode *mode,
83a57153 12074 struct drm_atomic_state *state,
7f27126e
JB		 12075 unsigned *modeset_pipes,
12076 unsigned *prepare_pipes,
12077 unsigned *disable_pipes)
12078{
db7542dd 12079 struct drm_device *dev = crtc->dev;
5cec258b 12080 struct intel_crtc_state *pipe_config = NULL;
db7542dd 12081 struct intel_crtc *intel_crtc;
0b901879
ACO		 12082 int ret = 0;
12083
12084 ret = drm_atomic_add_affected_connectors(state, crtc);
12085 if (ret)
12086 return ERR_PTR(ret);
7f27126e
JB		 12087
12088 intel_modeset_affected_pipes(crtc, modeset_pipes,
12089 prepare_pipes, disable_pipes);
12090
db7542dd
ACO		 12091 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
12092 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12093 if (IS_ERR(pipe_config))
12094 return pipe_config;
12095
12096 pipe_config->base.enable = false;
12097 }
7f27126e
JB		 12098
12099 /*
12100 * Note this needs changes when we start tracking multiple modes
12101 * and crtcs. At that point we'll need to compute the whole config
12102 * (i.e. one pipe_config for each crtc) rather than just the one
12103 * for this crtc.
12104 */
db7542dd
ACO		 12105 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
12106 /* FIXME: For now we still expect modeset_pipes has at most
12107 * one bit set. */
12108 if (WARN_ON(&intel_crtc->base != crtc))
12109 continue;
83a57153 12110
8805aa71 12111 pipe_config = intel_modeset_pipe_config(crtc, mode, state);
db7542dd
ACO		 12112 if (IS_ERR(pipe_config))
12113 return pipe_config;
7f27126e 12114
304603f4
ACO		 12115 pipe_config->base.enable = true;
12116
db7542dd
ACO		 12117 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12118 "[modeset]");
12119 }
12120
12121 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 12122}
12123
225da59b 12124static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 12125 unsigned modeset_pipes,
12126 unsigned disable_pipes)
12127{
225da59b 12128 struct drm_device *dev = state->dev;
ed6739ef
ACO		 12129 struct drm_i915_private *dev_priv = to_i915(dev);
12130 unsigned clear_pipes = modeset_pipes | disable_pipes;
12131 struct intel_crtc *intel_crtc;
12132 int ret = 0;
12133
12134 if (!dev_priv->display.crtc_compute_clock)
12135 return 0;
12136
12137 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12138 if (ret)
12139 goto done;
12140
12141 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 12142 struct intel_crtc_state *crtc_state =
12143 intel_atomic_get_crtc_state(state, intel_crtc);
12144
12145 /* Modeset pipes should have a new state by now */
12146 if (WARN_ON(IS_ERR(crtc_state)))
12147 continue;
12148
ed6739ef 12149 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 12150 crtc_state);
ed6739ef
ACO		 12151 if (ret) {
12152 intel_shared_dpll_abort_config(dev_priv);
12153 goto done;
12154 }
12155 }
12156
12157done:
12158 return ret;
12159}
12160
f30da187
DV		 12161static int __intel_set_mode(struct drm_crtc *crtc,
12162 struct drm_display_mode *mode,
7f27126e 12163 int x, int y, struct drm_framebuffer *fb,
5cec258b 12164 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12165 unsigned modeset_pipes,
12166 unsigned prepare_pipes,
12167 unsigned disable_pipes)
a6778b3c
DV		 12168{
12169 struct drm_device *dev = crtc->dev;
fbee40df 12170 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 12171 struct drm_display_mode *saved_mode;
304603f4 12172 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12173 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12174 struct intel_crtc *intel_crtc;
c0c36b94 12175 int ret = 0;
a6778b3c 12176
4b4b9238 12177 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 12178 if (!saved_mode)
12179 return -ENOMEM;
a6778b3c 12180
83a57153
ACO		 12181 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12182 if (!crtc_state_copy) {
12183 ret = -ENOMEM;
12184 goto done;
12185 }
12186
3ac18232 12187 *saved_mode = crtc->mode;
a6778b3c 12188
30a970c6
JB		 12189 /*
12190 * See if the config requires any additional preparation, e.g.
12191 * to adjust global state with pipes off. We need to do this
12192 * here so we can get the modeset_pipe updated config for the new
12193 * mode set on this crtc. For other crtcs we need to use the
12194 * adjusted_mode bits in the crtc directly.
12195 */
f8437dd1 12196 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
304603f4
ACO		 12197 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
12198 if (ret)
12199 goto done;
30a970c6 12200
c164f833
VS		 12201 /* may have added more to prepare_pipes than we should */
12202 prepare_pipes &= ~disable_pipes;
12203 }
12204
225da59b 12205 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 12206 if (ret)
12207 goto done;
8bd31e67 12208
460da916
DV		 12209 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12210 intel_crtc_disable(&intel_crtc->base);
12211
ea9d758d 12212 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 12213 if (intel_crtc->base.state->enable)
ea9d758d
DV		 12214 dev_priv->display.crtc_disable(&intel_crtc->base);
12215 }
a6778b3c 12216
6c4c86f5
DV		 12217 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12218 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12219 *
12220 * Note we'll need to fix this up when we start tracking multiple
12221 * pipes; here we assume a single modeset_pipe and only track the
12222 * single crtc and mode.
f6e5b160 12223 */
b8cecdf5 12224 if (modeset_pipes) {
25c5b266 12225 crtc->mode = *mode;
b8cecdf5
DV		 12226 /* mode_set/enable/disable functions rely on a correct pipe
12227 * config. */
f5de6e07 12228 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12229
12230 /*
12231 * Calculate and store various constants which
12232 * are later needed by vblank and swap-completion
12233 * timestamping. They are derived from true hwmode.
12234 */
12235 drm_calc_timestamping_constants(crtc,
2d112de7 12236 &pipe_config->base.adjusted_mode);
b8cecdf5 12237 }
7758a113 12238
ea9d758d
DV		 12239 /* Only after disabling all output pipelines that will be changed can we
12240 * update the the output configuration. */
12241 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12242
304603f4 12243 modeset_update_crtc_power_domains(state);
47fab737 12244
25c5b266 12245 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12246 struct drm_plane *primary = intel_crtc->base.primary;
12247 int vdisplay, hdisplay;
4c10794f 12248
455a6808 12249 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12250 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12251 fb, 0, 0,
12252 hdisplay, vdisplay,
12253 x << 16, y << 16,
12254 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12255 }
12256
12257 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12258 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12259 update_scanline_offset(intel_crtc);
12260
25c5b266 12261 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 12262 }
a6778b3c 12263
a6778b3c
DV		 12264 /* FIXME: add subpixel order */
12265done:
83d65738 12266 if (ret && crtc->state->enable)
3ac18232 12267 crtc->mode = *saved_mode;
a6778b3c 12268
83a57153
ACO		 12269 if (ret == 0 && pipe_config) {
12270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12271
12272 /* The pipe_config will be freed with the atomic state, so
12273 * make a copy. */
12274 memcpy(crtc_state_copy, intel_crtc->config,
12275 sizeof *crtc_state_copy);
12276 intel_crtc->config = crtc_state_copy;
12277 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12278 } else {
12279 kfree(crtc_state_copy);
12280 }
12281
3ac18232 12282 kfree(saved_mode);
a6778b3c 12283 return ret;
f6e5b160
CW		 12284}
12285
7f27126e
JB		 12286static int intel_set_mode_pipes(struct drm_crtc *crtc,
12287 struct drm_display_mode *mode,
12288 int x, int y, struct drm_framebuffer *fb,
5cec258b 12289 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12290 unsigned modeset_pipes,
12291 unsigned prepare_pipes,
12292 unsigned disable_pipes)
f30da187
DV		 12293{
12294 int ret;
12295
7f27126e
JB		 12296 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12297 prepare_pipes, disable_pipes);
f30da187
DV		 12298
12299 if (ret == 0)
12300 intel_modeset_check_state(crtc->dev);
12301
12302 return ret;
12303}
12304
7f27126e
JB		 12305static int intel_set_mode(struct drm_crtc *crtc,
12306 struct drm_display_mode *mode,
83a57153
ACO		 12307 int x, int y, struct drm_framebuffer *fb,
12308 struct drm_atomic_state *state)
7f27126e 12309{
5cec258b 12310 struct intel_crtc_state *pipe_config;
7f27126e 12311 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12312 int ret = 0;
7f27126e 12313
8805aa71 12314 pipe_config = intel_modeset_compute_config(crtc, mode, state,
7f27126e
JB		 12315 &modeset_pipes,
12316 &prepare_pipes,
12317 &disable_pipes);
12318
83a57153
ACO		 12319 if (IS_ERR(pipe_config)) {
12320 ret = PTR_ERR(pipe_config);
12321 goto out;
12322 }
12323
12324 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12325 modeset_pipes, prepare_pipes,
12326 disable_pipes);
12327 if (ret)
12328 goto out;
7f27126e 12329
83a57153
ACO		 12330out:
12331 return ret;
7f27126e
JB		 12332}
12333
c0c36b94
CW		 12334void intel_crtc_restore_mode(struct drm_crtc *crtc)
12335{
83a57153
ACO		 12336 struct drm_device *dev = crtc->dev;
12337 struct drm_atomic_state *state;
12338 struct intel_encoder *encoder;
12339 struct intel_connector *connector;
12340 struct drm_connector_state *connector_state;
12341
12342 state = drm_atomic_state_alloc(dev);
12343 if (!state) {
12344 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12345 crtc->base.id);
12346 return;
12347 }
12348
12349 state->acquire_ctx = dev->mode_config.acquire_ctx;
12350
12351 /* The force restore path in the HW readout code relies on the staged
12352 * config still keeping the user requested config while the actual
12353 * state has been overwritten by the configuration read from HW. We
12354 * need to copy the staged config to the atomic state, otherwise the
12355 * mode set will just reapply the state the HW is already in. */
12356 for_each_intel_encoder(dev, encoder) {
12357 if (&encoder->new_crtc->base != crtc)
12358 continue;
12359
12360 for_each_intel_connector(dev, connector) {
12361 if (connector->new_encoder != encoder)
12362 continue;
12363
12364 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12365 if (IS_ERR(connector_state)) {
12366 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12367 connector->base.base.id,
12368 connector->base.name,
12369 PTR_ERR(connector_state));
12370 continue;
12371 }
12372
12373 connector_state->crtc = crtc;
12374 connector_state->best_encoder = &encoder->base;
12375 }
12376 }
12377
12378 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12379 state);
12380
12381 drm_atomic_state_free(state);
c0c36b94
CW		 12382}
12383
25c5b266
DV		 12384#undef for_each_intel_crtc_masked
12385
d9e55608
DV		 12386static void intel_set_config_free(struct intel_set_config *config)
12387{
12388 if (!config)
12389 return;
12390
1aa4b628
DV		 12391 kfree(config->save_connector_encoders);
12392 kfree(config->save_encoder_crtcs);
7668851f 12393 kfree(config->save_crtc_enabled);
d9e55608
DV		 12394 kfree(config);
12395}
12396
85f9eb71
DV		 12397static int intel_set_config_save_state(struct drm_device *dev,
12398 struct intel_set_config *config)
12399{
7668851f 12400 struct drm_crtc *crtc;
85f9eb71
DV		 12401 struct drm_encoder *encoder;
12402 struct drm_connector *connector;
12403 int count;
12404
7668851f
VS		 12405 config->save_crtc_enabled =
12406 kcalloc(dev->mode_config.num_crtc,
12407 sizeof(bool), GFP_KERNEL);
12408 if (!config->save_crtc_enabled)
12409 return -ENOMEM;
12410
1aa4b628
DV		 12411 config->save_encoder_crtcs =
12412 kcalloc(dev->mode_config.num_encoder,
12413 sizeof(struct drm_crtc *), GFP_KERNEL);
12414 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12415 return -ENOMEM;
12416
1aa4b628
DV		 12417 config->save_connector_encoders =
12418 kcalloc(dev->mode_config.num_connector,
12419 sizeof(struct drm_encoder *), GFP_KERNEL);
12420 if (!config->save_connector_encoders)
85f9eb71
DV		 12421 return -ENOMEM;
12422
12423 /* Copy data. Note that driver private data is not affected.
12424 * Should anything bad happen only the expected state is
12425 * restored, not the drivers personal bookkeeping.
12426 */
7668851f 12427 count = 0;
70e1e0ec 12428 for_each_crtc(dev, crtc) {
83d65738 12429 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12430 }
12431
85f9eb71
DV		 12432 count = 0;
12433 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12434 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12435 }
12436
12437 count = 0;
12438 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12439 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12440 }
12441
12442 return 0;
12443}
12444
12445static void intel_set_config_restore_state(struct drm_device *dev,
12446 struct intel_set_config *config)
12447{
7668851f 12448 struct intel_crtc *crtc;
9a935856
DV		 12449 struct intel_encoder *encoder;
12450 struct intel_connector *connector;
85f9eb71
DV		 12451 int count;
12452
7668851f 12453 count = 0;
d3fcc808 12454 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12455 crtc->new_enabled = config->save_crtc_enabled[count++];
12456 }
12457
85f9eb71 12458 count = 0;
b2784e15 12459 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12460 encoder->new_crtc =
12461 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12462 }
12463
12464 count = 0;
3a3371ff 12465 for_each_intel_connector(dev, connector) {
9a935856
DV		 12466 connector->new_encoder =
12467 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12468 }
12469}
12470
e3de42b6 12471static bool
2e57f47d 12472is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12473{
12474 int i;
12475
2e57f47d
CW		 12476 if (set->num_connectors == 0)
12477 return false;
12478
12479 if (WARN_ON(set->connectors == NULL))
12480 return false;
12481
12482 for (i = 0; i < set->num_connectors; i++)
12483 if (set->connectors[i]->encoder &&
12484 set->connectors[i]->encoder->crtc == set->crtc &&
12485 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12486 return true;
12487
12488 return false;
12489}
12490
5e2b584e
DV		 12491static void
12492intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12493 struct intel_set_config *config)
12494{
12495
12496 /* We should be able to check here if the fb has the same properties
12497 * and then just flip_or_move it */
2e57f47d
CW		 12498 if (is_crtc_connector_off(set)) {
12499 config->mode_changed = true;
f4510a27 12500 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12501 /*
12502 * If we have no fb, we can only flip as long as the crtc is
12503 * active, otherwise we need a full mode set. The crtc may
12504 * be active if we've only disabled the primary plane, or
12505 * in fastboot situations.
12506 */
f4510a27 12507 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12508 struct intel_crtc *intel_crtc =
12509 to_intel_crtc(set->crtc);
12510
3b150f08 12511 if (intel_crtc->active) {
319d9827
JB		 12512 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12513 config->fb_changed = true;
12514 } else {
12515 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12516 config->mode_changed = true;
12517 }
5e2b584e
DV		 12518 } else if (set->fb == NULL) {
12519 config->mode_changed = true;
72f4901e 12520 } else if (set->fb->pixel_format !=
f4510a27 12521 set->crtc->primary->fb->pixel_format) {
5e2b584e 12522 config->mode_changed = true;
e3de42b6 12523 } else {
5e2b584e 12524 config->fb_changed = true;
e3de42b6 12525 }
5e2b584e
DV		 12526 }
12527
835c5873 12528 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12529 config->fb_changed = true;
12530
12531 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12532 DRM_DEBUG_KMS("modes are different, full mode set\n");
12533 drm_mode_debug_printmodeline(&set->crtc->mode);
12534 drm_mode_debug_printmodeline(set->mode);
12535 config->mode_changed = true;
12536 }
a1d95703
CW		 12537
12538 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12539 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12540}
12541
2e431051 12542static int
9a935856
DV		 12543intel_modeset_stage_output_state(struct drm_device *dev,
12544 struct drm_mode_set *set,
944b0c76
ACO		 12545 struct intel_set_config *config,
12546 struct drm_atomic_state *state)
50f56119 12547{
9a935856 12548 struct intel_connector *connector;
944b0c76 12549 struct drm_connector_state *connector_state;
9a935856 12550 struct intel_encoder *encoder;
7668851f 12551 struct intel_crtc *crtc;
f3f08572 12552 int ro;
50f56119 12553
9abdda74 12554 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12555 * of connectors. For paranoia, double-check this. */
12556 WARN_ON(!set->fb && (set->num_connectors != 0));
12557 WARN_ON(set->fb && (set->num_connectors == 0));
12558
3a3371ff 12559 for_each_intel_connector(dev, connector) {
9a935856
DV		 12560 /* Otherwise traverse passed in connector list and get encoders
12561 * for them. */
50f56119 12562 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12563 if (set->connectors[ro] == &connector->base) {
0e32b39c 12564 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12565 break;
12566 }
12567 }
12568
9a935856
DV		 12569 /* If we disable the crtc, disable all its connectors. Also, if
12570 * the connector is on the changing crtc but not on the new
12571 * connector list, disable it. */
12572 if ((!set->fb || ro == set->num_connectors) &&
12573 connector->base.encoder &&
12574 connector->base.encoder->crtc == set->crtc) {
12575 connector->new_encoder = NULL;
12576
12577 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12578 connector->base.base.id,
c23cc417 12579 connector->base.name);
9a935856
DV		 12580 }
12581
12582
12583 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12585 connector->base.base.id,
12586 connector->base.name);
5e2b584e 12587 config->mode_changed = true;
50f56119
DV		 12588 }
12589 }
9a935856 12590 /* connector->new_encoder is now updated for all connectors. */
50f56119 12591
9a935856 12592 /* Update crtc of enabled connectors. */
3a3371ff 12593 for_each_intel_connector(dev, connector) {
7668851f
VS		 12594 struct drm_crtc *new_crtc;
12595
9a935856 12596 if (!connector->new_encoder)
50f56119
DV		 12597 continue;
12598
9a935856 12599 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12600
12601 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12602 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12603 new_crtc = set->crtc;
12604 }
12605
12606 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12607 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12608 new_crtc)) {
5e2b584e 12609 return -EINVAL;
50f56119 12610 }
0e32b39c 12611 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12612
944b0c76
ACO		 12613 connector_state =
12614 drm_atomic_get_connector_state(state, &connector->base);
12615 if (IS_ERR(connector_state))
12616 return PTR_ERR(connector_state);
12617
12618 connector_state->crtc = new_crtc;
12619 connector_state->best_encoder = &connector->new_encoder->base;
12620
9a935856
DV		 12621 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12622 connector->base.base.id,
c23cc417 12623 connector->base.name,
9a935856
DV		 12624 new_crtc->base.id);
12625 }
12626
12627 /* Check for any encoders that needs to be disabled. */
b2784e15 12628 for_each_intel_encoder(dev, encoder) {
5a65f358 12629 int num_connectors = 0;
3a3371ff 12630 for_each_intel_connector(dev, connector) {
9a935856
DV		 12631 if (connector->new_encoder == encoder) {
12632 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12633 num_connectors++;
9a935856
DV		 12634 }
12635 }
5a65f358
PZ		 12636
12637 if (num_connectors == 0)
12638 encoder->new_crtc = NULL;
12639 else if (num_connectors > 1)
12640 return -EINVAL;
12641
9a935856
DV		 12642 /* Only now check for crtc changes so we don't miss encoders
12643 * that will be disabled. */
12644 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12645 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12646 encoder->base.base.id,
12647 encoder->base.name);
5e2b584e 12648 config->mode_changed = true;
50f56119
DV		 12649 }
12650 }
9a935856 12651 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12652 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12653 connector_state =
12654 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12655 if (IS_ERR(connector_state))
12656 return PTR_ERR(connector_state);
944b0c76
ACO		 12657
12658 if (connector->new_encoder) {
0e32b39c
DA		 12659 if (connector->new_encoder != connector->encoder)
12660 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12661 } else {
12662 connector_state->crtc = NULL;
f61cccf3 12663 connector_state->best_encoder = NULL;
944b0c76 12664 }
0e32b39c 12665 }
d3fcc808 12666 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12667 crtc->new_enabled = false;
12668
b2784e15 12669 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12670 if (encoder->new_crtc == crtc) {
12671 crtc->new_enabled = true;
12672 break;
12673 }
12674 }
12675
83d65738 12676 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12677 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12678 crtc->base.base.id,
7668851f
VS		 12679 crtc->new_enabled ? "en" : "dis");
12680 config->mode_changed = true;
12681 }
12682 }
12683
2e431051
DV		 12684 return 0;
12685}
12686
7d00a1f5
VS		 12687static void disable_crtc_nofb(struct intel_crtc *crtc)
12688{
12689 struct drm_device *dev = crtc->base.dev;
12690 struct intel_encoder *encoder;
12691 struct intel_connector *connector;
12692
12693 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12694 pipe_name(crtc->pipe));
12695
3a3371ff 12696 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12697 if (connector->new_encoder &&
12698 connector->new_encoder->new_crtc == crtc)
12699 connector->new_encoder = NULL;
12700 }
12701
b2784e15 12702 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12703 if (encoder->new_crtc == crtc)
12704 encoder->new_crtc = NULL;
12705 }
12706
12707 crtc->new_enabled = false;
12708}
12709
2e431051
DV		 12710static int intel_crtc_set_config(struct drm_mode_set *set)
12711{
12712 struct drm_device *dev;
2e431051 12713 struct drm_mode_set save_set;
83a57153 12714 struct drm_atomic_state *state = NULL;
2e431051 12715 struct intel_set_config *config;
5cec258b 12716 struct intel_crtc_state *pipe_config;
50f52756 12717 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12718 int ret;
2e431051 12719
8d3e375e
DV		 12720 BUG_ON(!set);
12721 BUG_ON(!set->crtc);
12722 BUG_ON(!set->crtc->helper_private);
2e431051 12723
7e53f3a4
DV		 12724 /* Enforce sane interface api - has been abused by the fb helper. */
12725 BUG_ON(!set->mode && set->fb);
12726 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12727
2e431051
DV		 12728 if (set->fb) {
12729 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12730 set->crtc->base.id, set->fb->base.id,
12731 (int)set->num_connectors, set->x, set->y);
12732 } else {
12733 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12734 }
12735
12736 dev = set->crtc->dev;
12737
12738 ret = -ENOMEM;
12739 config = kzalloc(sizeof(*config), GFP_KERNEL);
12740 if (!config)
12741 goto out_config;
12742
12743 ret = intel_set_config_save_state(dev, config);
12744 if (ret)
12745 goto out_config;
12746
12747 save_set.crtc = set->crtc;
12748 save_set.mode = &set->crtc->mode;
12749 save_set.x = set->crtc->x;
12750 save_set.y = set->crtc->y;
f4510a27 12751 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12752
12753 /* Compute whether we need a full modeset, only an fb base update or no
12754 * change at all. In the future we might also check whether only the
12755 * mode changed, e.g. for LVDS where we only change the panel fitter in
12756 * such cases. */
12757 intel_set_config_compute_mode_changes(set, config);
12758
83a57153
ACO		 12759 state = drm_atomic_state_alloc(dev);
12760 if (!state) {
12761 ret = -ENOMEM;
12762 goto out_config;
12763 }
12764
12765 state->acquire_ctx = dev->mode_config.acquire_ctx;
12766
944b0c76 12767 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12768 if (ret)
12769 goto fail;
12770
50f52756 12771 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
8805aa71 12772 state,
50f52756
JB		 12773 &modeset_pipes,
12774 &prepare_pipes,
12775 &disable_pipes);
20664591 12776 if (IS_ERR(pipe_config)) {
6ac0483b 12777 ret = PTR_ERR(pipe_config);
50f52756 12778 goto fail;
20664591 12779 } else if (pipe_config) {
b9950a13 12780 if (pipe_config->has_audio !=
6e3c9717 12781 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12782 config->mode_changed = true;
12783
af15d2ce
JB		 12784 /*
12785 * Note we have an issue here with infoframes: current code
12786 * only updates them on the full mode set path per hw
12787 * requirements. So here we should be checking for any
12788 * required changes and forcing a mode set.
12789 */
20664591 12790 }
50f52756 12791
1f9954d0
JB		 12792 intel_update_pipe_size(to_intel_crtc(set->crtc));
12793
5e2b584e 12794 if (config->mode_changed) {
50f52756
JB		 12795 ret = intel_set_mode_pipes(set->crtc, set->mode,
12796 set->x, set->y, set->fb, pipe_config,
12797 modeset_pipes, prepare_pipes,
12798 disable_pipes);
5e2b584e 12799 } else if (config->fb_changed) {
3b150f08 12800 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12801 struct drm_plane *primary = set->crtc->primary;
12802 int vdisplay, hdisplay;
3b150f08 12803
455a6808 12804 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12805 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12806 0, 0, hdisplay, vdisplay,
12807 set->x << 16, set->y << 16,
12808 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12809
12810 /*
12811 * We need to make sure the primary plane is re-enabled if it
12812 * has previously been turned off.
12813 */
12814 if (!intel_crtc->primary_enabled && ret == 0) {
12815 WARN_ON(!intel_crtc->active);
fdd508a6 12816 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12817 }
12818
7ca51a3a
JB		 12819 /*
12820 * In the fastboot case this may be our only check of the
12821 * state after boot. It would be better to only do it on
12822 * the first update, but we don't have a nice way of doing that
12823 * (and really, set_config isn't used much for high freq page
12824 * flipping, so increasing its cost here shouldn't be a big
12825 * deal).
12826 */
d330a953 12827 if (i915.fastboot && ret == 0)
7ca51a3a 12828 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12829 }
12830
2d05eae1 12831 if (ret) {
bf67dfeb
DV		 12832 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12833 set->crtc->base.id, ret);
50f56119 12834fail:
2d05eae1 12835 intel_set_config_restore_state(dev, config);
50f56119 12836
83a57153
ACO		 12837 drm_atomic_state_clear(state);
12838
7d00a1f5
VS		 12839 /*
12840 * HACK: if the pipe was on, but we didn't have a framebuffer,
12841 * force the pipe off to avoid oopsing in the modeset code
12842 * due to fb==NULL. This should only happen during boot since
12843 * we don't yet reconstruct the FB from the hardware state.
12844 */
12845 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12846 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12847
2d05eae1
CW		 12848 /* Try to restore the config */
12849 if (config->mode_changed &&
12850 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12851 save_set.x, save_set.y, save_set.fb,
12852 state))
2d05eae1
CW		 12853 DRM_ERROR("failed to restore config after modeset failure\n");
12854 }
50f56119 12855
d9e55608 12856out_config:
83a57153
ACO		 12857 if (state)
12858 drm_atomic_state_free(state);
12859
d9e55608 12860 intel_set_config_free(config);
50f56119
DV		 12861 return ret;
12862}
f6e5b160
CW		 12863
12864static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12865 .gamma_set = intel_crtc_gamma_set,
50f56119 12866 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12867 .destroy = intel_crtc_destroy,
12868 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12869 .atomic_duplicate_state = intel_crtc_duplicate_state,
12870 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12871};
12872
5358901f
DV		 12873static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12874 struct intel_shared_dpll *pll,
12875 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12876{
5358901f 12877 uint32_t val;
ee7b9f93 12878
f458ebbc 12879 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12880 return false;
12881
5358901f 12882 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12883 hw_state->dpll = val;
12884 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12885 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12886
12887 return val & DPLL_VCO_ENABLE;
12888}
12889
15bdd4cf
DV		 12890static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12891 struct intel_shared_dpll *pll)
12892{
3e369b76
ACO		 12893 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12894 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12895}
12896
e7b903d2
DV		 12897static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12898 struct intel_shared_dpll *pll)
12899{
e7b903d2 12900 /* PCH refclock must be enabled first */
89eff4be 12901 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12902
3e369b76 12903 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12904
12905 /* Wait for the clocks to stabilize. */
12906 POSTING_READ(PCH_DPLL(pll->id));
12907 udelay(150);
12908
12909 /* The pixel multiplier can only be updated once the
12910 * DPLL is enabled and the clocks are stable.
12911 *
12912 * So write it again.
12913 */
3e369b76 12914 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12915 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12916 udelay(200);
12917}
12918
12919static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12920 struct intel_shared_dpll *pll)
12921{
12922 struct drm_device *dev = dev_priv->dev;
12923 struct intel_crtc *crtc;
e7b903d2
DV		 12924
12925 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12926 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12927 if (intel_crtc_to_shared_dpll(crtc) == pll)
12928 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12929 }
12930
15bdd4cf
DV		 12931 I915_WRITE(PCH_DPLL(pll->id), 0);
12932 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12933 udelay(200);
12934}
12935
46edb027
DV		 12936static char *ibx_pch_dpll_names[] = {
12937 "PCH DPLL A",
12938 "PCH DPLL B",
12939};
12940
7c74ade1 12941static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12942{
e7b903d2 12943 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12944 int i;
12945
7c74ade1 12946 dev_priv->num_shared_dpll = 2;
ee7b9f93 12947
e72f9fbf 12948 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12949 dev_priv->shared_dplls[i].id = i;
12950 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12951 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12952 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12953 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12954 dev_priv->shared_dplls[i].get_hw_state =
12955 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12956 }
12957}
12958
7c74ade1
DV		 12959static void intel_shared_dpll_init(struct drm_device *dev)
12960{
e7b903d2 12961 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12962
9cd86933
DV		 12963 if (HAS_DDI(dev))
12964 intel_ddi_pll_init(dev);
12965 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12966 ibx_pch_dpll_init(dev);
12967 else
12968 dev_priv->num_shared_dpll = 0;
12969
12970 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12971}
12972
1fc0a8f7
TU		 12973/**
12974 * intel_wm_need_update - Check whether watermarks need updating
12975 * @plane: drm plane
12976 * @state: new plane state
12977 *
12978 * Check current plane state versus the new one to determine whether
12979 * watermarks need to be recalculated.
12980 *
12981 * Returns true or false.
12982 */
12983bool intel_wm_need_update(struct drm_plane *plane,
12984 struct drm_plane_state *state)
12985{
12986 /* Update watermarks on tiling changes. */
12987 if (!plane->state->fb || !state->fb ||
12988 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12989 plane->state->rotation != state->rotation)
12990 return true;
12991
12992 return false;
12993}
12994
6beb8c23
MR		 12995/**
12996 * intel_prepare_plane_fb - Prepare fb for usage on plane
12997 * @plane: drm plane to prepare for
12998 * @fb: framebuffer to prepare for presentation
12999 *
13000 * Prepares a framebuffer for usage on a display plane. Generally this
13001 * involves pinning the underlying object and updating the frontbuffer tracking
13002 * bits. Some older platforms need special physical address handling for
13003 * cursor planes.
13004 *
13005 * Returns 0 on success, negative error code on failure.
13006 */
13007int
13008intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13009 struct drm_framebuffer *fb,
13010 const struct drm_plane_state *new_state)
465c120c
MR		 13011{
13012 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13013 struct intel_plane *intel_plane = to_intel_plane(plane);
13014 enum pipe pipe = intel_plane->pipe;
13015 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13016 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13017 unsigned frontbuffer_bits = 0;
13018 int ret = 0;
465c120c 13019
ea2c67bb 13020 if (!obj)
465c120c
MR		 13021 return 0;
13022
6beb8c23
MR		 13023 switch (plane->type) {
13024 case DRM_PLANE_TYPE_PRIMARY:
13025 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13026 break;
13027 case DRM_PLANE_TYPE_CURSOR:
13028 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13029 break;
13030 case DRM_PLANE_TYPE_OVERLAY:
13031 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13032 break;
13033 }
465c120c 13034
6beb8c23 13035 mutex_lock(&dev->struct_mutex);
465c120c 13036
6beb8c23
MR		 13037 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13038 INTEL_INFO(dev)->cursor_needs_physical) {
13039 int align = IS_I830(dev) ? 16 * 1024 : 256;
13040 ret = i915_gem_object_attach_phys(obj, align);
13041 if (ret)
13042 DRM_DEBUG_KMS("failed to attach phys object\n");
13043 } else {
82bc3b2d 13044 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13045 }
465c120c 13046
6beb8c23
MR		 13047 if (ret == 0)
13048 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13049
4c34574f 13050 mutex_unlock(&dev->struct_mutex);
465c120c 13051
6beb8c23
MR		 13052 return ret;
13053}
13054
38f3ce3a
MR		 13055/**
13056 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13057 * @plane: drm plane to clean up for
13058 * @fb: old framebuffer that was on plane
13059 *
13060 * Cleans up a framebuffer that has just been removed from a plane.
13061 */
13062void
13063intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13064 struct drm_framebuffer *fb,
13065 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13066{
13067 struct drm_device *dev = plane->dev;
13068 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13069
13070 if (WARN_ON(!obj))
13071 return;
13072
13073 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13074 !INTEL_INFO(dev)->cursor_needs_physical) {
13075 mutex_lock(&dev->struct_mutex);
82bc3b2d 13076 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13077 mutex_unlock(&dev->struct_mutex);
13078 }
465c120c
MR		 13079}
13080
13081static int
3c692a41
GP		 13082intel_check_primary_plane(struct drm_plane *plane,
13083 struct intel_plane_state *state)
13084{
32b7eeec
MR		 13085 struct drm_device *dev = plane->dev;
13086 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13087 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13088 struct intel_crtc *intel_crtc;
2b875c22 13089 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13090 struct drm_rect *dest = &state->dst;
13091 struct drm_rect *src = &state->src;
13092 const struct drm_rect *clip = &state->clip;
d8106366 13093 bool can_position = false;
465c120c
MR		 13094 int ret;
13095
ea2c67bb
MR		 13096 crtc = crtc ? crtc : plane->crtc;
13097 intel_crtc = to_intel_crtc(crtc);
13098
d8106366
SJ		 13099 if (INTEL_INFO(dev)->gen >= 9)
13100 can_position = true;
13101
c59cb179
MR		 13102 ret = drm_plane_helper_check_update(plane, crtc, fb,
13103 src, dest, clip,
13104 DRM_PLANE_HELPER_NO_SCALING,
13105 DRM_PLANE_HELPER_NO_SCALING,
d8106366
SJ		 13106 can_position, true,
13107 &state->visible);
c59cb179
MR		 13108 if (ret)
13109 return ret;
465c120c 13110
32b7eeec
MR		 13111 if (intel_crtc->active) {
13112 intel_crtc->atomic.wait_for_flips = true;
13113
13114 /*
13115 * FBC does not work on some platforms for rotated
13116 * planes, so disable it when rotation is not 0 and
13117 * update it when rotation is set back to 0.
13118 *
13119 * FIXME: This is redundant with the fbc update done in
13120 * the primary plane enable function except that that
13121 * one is done too late. We eventually need to unify
13122 * this.
13123 */
13124 if (intel_crtc->primary_enabled &&
13125 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13126 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13127 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13128 intel_crtc->atomic.disable_fbc = true;
13129 }
13130
13131 if (state->visible) {
13132 /*
13133 * BDW signals flip done immediately if the plane
13134 * is disabled, even if the plane enable is already
13135 * armed to occur at the next vblank :(
13136 */
13137 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
13138 intel_crtc->atomic.wait_vblank = true;
13139 }
13140
13141 intel_crtc->atomic.fb_bits |=
13142 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13143
13144 intel_crtc->atomic.update_fbc = true;
0fda6568 13145
1fc0a8f7 13146 if (intel_wm_need_update(plane, &state->base))
0fda6568 13147 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13148 }
13149
14af293f
GP		 13150 return 0;
13151}
13152
13153static void
13154intel_commit_primary_plane(struct drm_plane *plane,
13155 struct intel_plane_state *state)
13156{
2b875c22
MR		 13157 struct drm_crtc *crtc = state->base.crtc;
13158 struct drm_framebuffer *fb = state->base.fb;
13159 struct drm_device *dev = plane->dev;
14af293f 13160 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13161 struct intel_crtc *intel_crtc;
14af293f
GP		 13162 struct drm_rect *src = &state->src;
13163
ea2c67bb
MR		 13164 crtc = crtc ? crtc : plane->crtc;
13165 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13166
13167 plane->fb = fb;
9dc806fc
MR		 13168 crtc->x = src->x1 >> 16;
13169 crtc->y = src->y1 >> 16;
ccc759dc 13170
ccc759dc 13171 if (intel_crtc->active) {
ccc759dc 13172 if (state->visible) {
ccc759dc
GP		 13173 /* FIXME: kill this fastboot hack */
13174 intel_update_pipe_size(intel_crtc);
465c120c 13175
ccc759dc 13176 intel_crtc->primary_enabled = true;
465c120c 13177
ccc759dc
GP		 13178 dev_priv->display.update_primary_plane(crtc, plane->fb,
13179 crtc->x, crtc->y);
ccc759dc
GP		 13180 } else {
13181 /*
13182 * If clipping results in a non-visible primary plane,
13183 * we'll disable the primary plane. Note that this is
13184 * a bit different than what happens if userspace
13185 * explicitly disables the plane by passing fb=0
13186 * because plane->fb still gets set and pinned.
13187 */
13188 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 13189 }
ccc759dc 13190 }
465c120c
MR		 13191}
13192
32b7eeec 13193static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13194{
32b7eeec 13195 struct drm_device *dev = crtc->dev;
140fd38d 13196 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13198 struct intel_plane *intel_plane;
13199 struct drm_plane *p;
13200 unsigned fb_bits = 0;
13201
13202 /* Track fb's for any planes being disabled */
13203 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13204 intel_plane = to_intel_plane(p);
13205
13206 if (intel_crtc->atomic.disabled_planes &
13207 (1 << drm_plane_index(p))) {
13208 switch (p->type) {
13209 case DRM_PLANE_TYPE_PRIMARY:
13210 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13211 break;
13212 case DRM_PLANE_TYPE_CURSOR:
13213 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13214 break;
13215 case DRM_PLANE_TYPE_OVERLAY:
13216 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13217 break;
13218 }
3c692a41 13219
ea2c67bb
MR		 13220 mutex_lock(&dev->struct_mutex);
13221 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13222 mutex_unlock(&dev->struct_mutex);
13223 }
13224 }
3c692a41 13225
32b7eeec
MR		 13226 if (intel_crtc->atomic.wait_for_flips)
13227 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13228
32b7eeec
MR		 13229 if (intel_crtc->atomic.disable_fbc)
13230 intel_fbc_disable(dev);
3c692a41 13231
32b7eeec
MR		 13232 if (intel_crtc->atomic.pre_disable_primary)
13233 intel_pre_disable_primary(crtc);
3c692a41 13234
32b7eeec
MR		 13235 if (intel_crtc->atomic.update_wm)
13236 intel_update_watermarks(crtc);
3c692a41 13237
32b7eeec 13238 intel_runtime_pm_get(dev_priv);
3c692a41 13239
c34c9ee4
MR		 13240 /* Perform vblank evasion around commit operation */
13241 if (intel_crtc->active)
13242 intel_crtc->atomic.evade =
13243 intel_pipe_update_start(intel_crtc,
13244 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13245}
13246
13247static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13248{
13249 struct drm_device *dev = crtc->dev;
13250 struct drm_i915_private *dev_priv = dev->dev_private;
13251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13252 struct drm_plane *p;
13253
c34c9ee4
MR		 13254 if (intel_crtc->atomic.evade)
13255 intel_pipe_update_end(intel_crtc,
13256 intel_crtc->atomic.start_vbl_count);
3c692a41 13257
140fd38d 13258 intel_runtime_pm_put(dev_priv);
3c692a41 13259
32b7eeec
MR		 13260 if (intel_crtc->atomic.wait_vblank)
13261 intel_wait_for_vblank(dev, intel_crtc->pipe);
13262
13263 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13264
13265 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13266 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13267 intel_fbc_update(dev);
ccc759dc 13268 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13269 }
3c692a41 13270
32b7eeec
MR		 13271 if (intel_crtc->atomic.post_enable_primary)
13272 intel_post_enable_primary(crtc);
3c692a41 13273
32b7eeec
MR		 13274 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13275 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13276 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13277 false, false);
13278
13279 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13280}
13281
cf4c7c12 13282/**
4a3b8769
MR		 13283 * intel_plane_destroy - destroy a plane
13284 * @plane: plane to destroy
cf4c7c12 13285 *
4a3b8769
MR		 13286 * Common destruction function for all types of planes (primary, cursor,
13287 * sprite).
cf4c7c12 13288 */
4a3b8769 13289void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13290{
13291 struct intel_plane *intel_plane = to_intel_plane(plane);
13292 drm_plane_cleanup(plane);
13293 kfree(intel_plane);
13294}
13295
65a3fea0 13296const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13297 .update_plane = drm_atomic_helper_update_plane,
13298 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13299 .destroy = intel_plane_destroy,
c196e1d6 13300 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13301 .atomic_get_property = intel_plane_atomic_get_property,
13302 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13303 .atomic_duplicate_state = intel_plane_duplicate_state,
13304 .atomic_destroy_state = intel_plane_destroy_state,
13305
465c120c
MR		 13306};
13307
13308static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13309 int pipe)
13310{
13311 struct intel_plane *primary;
8e7d688b 13312 struct intel_plane_state *state;
465c120c
MR		 13313 const uint32_t *intel_primary_formats;
13314 int num_formats;
13315
13316 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13317 if (primary == NULL)
13318 return NULL;
13319
8e7d688b
MR		 13320 state = intel_create_plane_state(&primary->base);
13321 if (!state) {
ea2c67bb
MR		 13322 kfree(primary);
13323 return NULL;
13324 }
8e7d688b 13325 primary->base.state = &state->base;
ea2c67bb 13326
465c120c
MR		 13327 primary->can_scale = false;
13328 primary->max_downscale = 1;
549e2bfb 13329 state->scaler_id = -1;
465c120c
MR		 13330 primary->pipe = pipe;
13331 primary->plane = pipe;
c59cb179
MR		 13332 primary->check_plane = intel_check_primary_plane;
13333 primary->commit_plane = intel_commit_primary_plane;
08e221fb 13334 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13335 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13336 primary->plane = !pipe;
13337
13338 if (INTEL_INFO(dev)->gen <= 3) {
13339 intel_primary_formats = intel_primary_formats_gen2;
13340 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13341 } else {
13342 intel_primary_formats = intel_primary_formats_gen4;
13343 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13344 }
13345
13346 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13347 &intel_plane_funcs,
465c120c
MR		 13348 intel_primary_formats, num_formats,
13349 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13350
3b7a5119
SJ		 13351 if (INTEL_INFO(dev)->gen >= 4)
13352 intel_create_rotation_property(dev, primary);
48404c1e 13353
ea2c67bb
MR		 13354 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13355
465c120c
MR		 13356 return &primary->base;
13357}
13358
3b7a5119
SJ		 13359void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13360{
13361 if (!dev->mode_config.rotation_property) {
13362 unsigned long flags = BIT(DRM_ROTATE_0) |
13363 BIT(DRM_ROTATE_180);
13364
13365 if (INTEL_INFO(dev)->gen >= 9)
13366 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13367
13368 dev->mode_config.rotation_property =
13369 drm_mode_create_rotation_property(dev, flags);
13370 }
13371 if (dev->mode_config.rotation_property)
13372 drm_object_attach_property(&plane->base.base,
13373 dev->mode_config.rotation_property,
13374 plane->base.state->rotation);
13375}
13376
3d7d6510 13377static int
852e787c
GP		 13378intel_check_cursor_plane(struct drm_plane *plane,
13379 struct intel_plane_state *state)
3d7d6510 13380{
2b875c22 13381 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13382 struct drm_device *dev = plane->dev;
2b875c22 13383 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13384 struct drm_rect *dest = &state->dst;
13385 struct drm_rect *src = &state->src;
13386 const struct drm_rect *clip = &state->clip;
757f9a3e 13387 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13388 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13389 unsigned stride;
13390 int ret;
3d7d6510 13391
ea2c67bb
MR		 13392 crtc = crtc ? crtc : plane->crtc;
13393 intel_crtc = to_intel_crtc(crtc);
13394
757f9a3e 13395 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13396 src, dest, clip,
3d7d6510
MR		 13397 DRM_PLANE_HELPER_NO_SCALING,
13398 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13399 true, true, &state->visible);
757f9a3e
GP		 13400 if (ret)
13401 return ret;
13402
13403
13404 /* if we want to turn off the cursor ignore width and height */
13405 if (!obj)
32b7eeec 13406 goto finish;
757f9a3e 13407
757f9a3e 13408 /* Check for which cursor types we support */
ea2c67bb
MR		 13409 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13410 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13411 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13412 return -EINVAL;
13413 }
13414
ea2c67bb
MR		 13415 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13416 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13417 DRM_DEBUG_KMS("buffer is too small\n");
13418 return -ENOMEM;
13419 }
13420
3a656b54 13421 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13422 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13423 ret = -EINVAL;
13424 }
757f9a3e 13425
32b7eeec
MR		 13426finish:
13427 if (intel_crtc->active) {
3749f463 13428 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13429 intel_crtc->atomic.update_wm = true;
13430
13431 intel_crtc->atomic.fb_bits |=
13432 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13433 }
13434
757f9a3e 13435 return ret;
852e787c 13436}
3d7d6510 13437
f4a2cf29 13438static void
852e787c
GP		 13439intel_commit_cursor_plane(struct drm_plane *plane,
13440 struct intel_plane_state *state)
13441{
2b875c22 13442 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13443 struct drm_device *dev = plane->dev;
13444 struct intel_crtc *intel_crtc;
2b875c22 13445 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13446 uint32_t addr;
852e787c 13447
ea2c67bb
MR		 13448 crtc = crtc ? crtc : plane->crtc;
13449 intel_crtc = to_intel_crtc(crtc);
13450
2b875c22 13451 plane->fb = state->base.fb;
ea2c67bb
MR		 13452 crtc->cursor_x = state->base.crtc_x;
13453 crtc->cursor_y = state->base.crtc_y;
13454
a912f12f
GP		 13455 if (intel_crtc->cursor_bo == obj)
13456 goto update;
4ed91096 13457
f4a2cf29 13458 if (!obj)
a912f12f 13459 addr = 0;
f4a2cf29 13460 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13461 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13462 else
a912f12f 13463 addr = obj->phys_handle->busaddr;
852e787c 13464
a912f12f
GP		 13465 intel_crtc->cursor_addr = addr;
13466 intel_crtc->cursor_bo = obj;
13467update:
852e787c 13468
32b7eeec 13469 if (intel_crtc->active)
a912f12f 13470 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13471}
13472
3d7d6510
MR		 13473static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13474 int pipe)
13475{
13476 struct intel_plane *cursor;
8e7d688b 13477 struct intel_plane_state *state;
3d7d6510
MR		 13478
13479 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13480 if (cursor == NULL)
13481 return NULL;
13482
8e7d688b
MR		 13483 state = intel_create_plane_state(&cursor->base);
13484 if (!state) {
ea2c67bb
MR		 13485 kfree(cursor);
13486 return NULL;
13487 }
8e7d688b 13488 cursor->base.state = &state->base;
ea2c67bb 13489
3d7d6510
MR		 13490 cursor->can_scale = false;
13491 cursor->max_downscale = 1;
13492 cursor->pipe = pipe;
13493 cursor->plane = pipe;
549e2bfb 13494 state->scaler_id = -1;
c59cb179
MR		 13495 cursor->check_plane = intel_check_cursor_plane;
13496 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 13497
13498 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13499 &intel_plane_funcs,
3d7d6510
MR		 13500 intel_cursor_formats,
13501 ARRAY_SIZE(intel_cursor_formats),
13502 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13503
13504 if (INTEL_INFO(dev)->gen >= 4) {
13505 if (!dev->mode_config.rotation_property)
13506 dev->mode_config.rotation_property =
13507 drm_mode_create_rotation_property(dev,
13508 BIT(DRM_ROTATE_0) |
13509 BIT(DRM_ROTATE_180));
13510 if (dev->mode_config.rotation_property)
13511 drm_object_attach_property(&cursor->base.base,
13512 dev->mode_config.rotation_property,
8e7d688b 13513 state->base.rotation);
4398ad45
VS		 13514 }
13515
ea2c67bb
MR		 13516 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13517
3d7d6510
MR		 13518 return &cursor->base;
13519}
13520
549e2bfb
CK		 13521static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13522 struct intel_crtc_state *crtc_state)
13523{
13524 int i;
13525 struct intel_scaler *intel_scaler;
13526 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13527
13528 for (i = 0; i < intel_crtc->num_scalers; i++) {
13529 intel_scaler = &scaler_state->scalers[i];
13530 intel_scaler->in_use = 0;
13531 intel_scaler->id = i;
13532
13533 intel_scaler->mode = PS_SCALER_MODE_DYN;
13534 }
13535
13536 scaler_state->scaler_id = -1;
13537}
13538
b358d0a6 13539static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13540{
fbee40df 13541 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13542 struct intel_crtc *intel_crtc;
f5de6e07 13543 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13544 struct drm_plane *primary = NULL;
13545 struct drm_plane *cursor = NULL;
465c120c 13546 int i, ret;
79e53945 13547
955382f3 13548 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13549 if (intel_crtc == NULL)
13550 return;
13551
f5de6e07
ACO		 13552 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13553 if (!crtc_state)
13554 goto fail;
13555 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13556 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13557
549e2bfb
CK		 13558 /* initialize shared scalers */
13559 if (INTEL_INFO(dev)->gen >= 9) {
13560 if (pipe == PIPE_C)
13561 intel_crtc->num_scalers = 1;
13562 else
13563 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13564
13565 skl_init_scalers(dev, intel_crtc, crtc_state);
13566 }
13567
465c120c 13568 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13569 if (!primary)
13570 goto fail;
13571
13572 cursor = intel_cursor_plane_create(dev, pipe);
13573 if (!cursor)
13574 goto fail;
13575
465c120c 13576 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13577 cursor, &intel_crtc_funcs);
13578 if (ret)
13579 goto fail;
79e53945
JB		 13580
13581 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13582 for (i = 0; i < 256; i++) {
13583 intel_crtc->lut_r[i] = i;
13584 intel_crtc->lut_g[i] = i;
13585 intel_crtc->lut_b[i] = i;
13586 }
13587
1f1c2e24
VS		 13588 /*
13589 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13590 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13591 */
80824003
JB		 13592 intel_crtc->pipe = pipe;
13593 intel_crtc->plane = pipe;
3a77c4c4 13594 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13595 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13596 intel_crtc->plane = !pipe;
80824003
JB		 13597 }
13598
4b0e333e
CW		 13599 intel_crtc->cursor_base = ~0;
13600 intel_crtc->cursor_cntl = ~0;
dc41c154 13601 intel_crtc->cursor_size = ~0;
8d7849db 13602
22fd0fab
JB		 13603 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13604 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13605 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13606 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13607
9362c7c5
ACO		 13608 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13609
79e53945 13610 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13611
13612 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13613 return;
13614
13615fail:
13616 if (primary)
13617 drm_plane_cleanup(primary);
13618 if (cursor)
13619 drm_plane_cleanup(cursor);
f5de6e07 13620 kfree(crtc_state);
3d7d6510 13621 kfree(intel_crtc);
79e53945
JB		 13622}
13623
752aa88a
JB		 13624enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13625{
13626 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13627 struct drm_device *dev = connector->base.dev;
752aa88a 13628
51fd371b 13629 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13630
d3babd3f 13631 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13632 return INVALID_PIPE;
13633
13634 return to_intel_crtc(encoder->crtc)->pipe;
13635}
13636
08d7b3d1 13637int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13638 struct drm_file *file)
08d7b3d1 13639{
08d7b3d1 13640 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13641 struct drm_crtc *drmmode_crtc;
c05422d5 13642 struct intel_crtc *crtc;
08d7b3d1 13643
7707e653 13644 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13645
7707e653 13646 if (!drmmode_crtc) {
08d7b3d1 13647 DRM_ERROR("no such CRTC id\n");
3f2c2057 13648 return -ENOENT;
08d7b3d1
CW		 13649 }
13650
7707e653 13651 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13652 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13653
c05422d5 13654 return 0;
08d7b3d1
CW		 13655}
13656
66a9278e 13657static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13658{
66a9278e
DV		 13659 struct drm_device *dev = encoder->base.dev;
13660 struct intel_encoder *source_encoder;
79e53945 13661 int index_mask = 0;
79e53945
JB		 13662 int entry = 0;
13663
b2784e15 13664 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13665 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13666 index_mask |= (1 << entry);
13667
79e53945
JB		 13668 entry++;
13669 }
4ef69c7a 13670
79e53945
JB		 13671 return index_mask;
13672}
13673
4d302442
CW		 13674static bool has_edp_a(struct drm_device *dev)
13675{
13676 struct drm_i915_private *dev_priv = dev->dev_private;
13677
13678 if (!IS_MOBILE(dev))
13679 return false;
13680
13681 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13682 return false;
13683
e3589908 13684 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13685 return false;
13686
13687 return true;
13688}
13689
84b4e042
JB		 13690static bool intel_crt_present(struct drm_device *dev)
13691{
13692 struct drm_i915_private *dev_priv = dev->dev_private;
13693
884497ed
DL		 13694 if (INTEL_INFO(dev)->gen >= 9)
13695 return false;
13696
cf404ce4 13697 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13698 return false;
13699
13700 if (IS_CHERRYVIEW(dev))
13701 return false;
13702
13703 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13704 return false;
13705
13706 return true;
13707}
13708
79e53945
JB		 13709static void intel_setup_outputs(struct drm_device *dev)
13710{
725e30ad 13711 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13712 struct intel_encoder *encoder;
cb0953d7 13713 bool dpd_is_edp = false;
79e53945 13714
c9093354 13715 intel_lvds_init(dev);
79e53945 13716
84b4e042 13717 if (intel_crt_present(dev))
79935fca 13718 intel_crt_init(dev);
cb0953d7 13719
c776eb2e
VK		 13720 if (IS_BROXTON(dev)) {
13721 /*
13722 * FIXME: Broxton doesn't support port detection via the
13723 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13724 * detect the ports.
13725 */
13726 intel_ddi_init(dev, PORT_A);
13727 intel_ddi_init(dev, PORT_B);
13728 intel_ddi_init(dev, PORT_C);
13729 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13730 int found;
13731
de31facd
JB		 13732 /*
13733 * Haswell uses DDI functions to detect digital outputs.
13734 * On SKL pre-D0 the strap isn't connected, so we assume
13735 * it's there.
13736 */
0e72a5b5 13737 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13738 /* WaIgnoreDDIAStrap: skl */
13739 if (found ||
13740 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13741 intel_ddi_init(dev, PORT_A);
13742
13743 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13744 * register */
13745 found = I915_READ(SFUSE_STRAP);
13746
13747 if (found & SFUSE_STRAP_DDIB_DETECTED)
13748 intel_ddi_init(dev, PORT_B);
13749 if (found & SFUSE_STRAP_DDIC_DETECTED)
13750 intel_ddi_init(dev, PORT_C);
13751 if (found & SFUSE_STRAP_DDID_DETECTED)
13752 intel_ddi_init(dev, PORT_D);
13753 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13754 int found;
5d8a7752 13755 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13756
13757 if (has_edp_a(dev))
13758 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13759
dc0fa718 13760 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13761 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13762 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13763 if (!found)
e2debe91 13764 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13765 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13766 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13767 }
13768
dc0fa718 13769 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13770 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13771
dc0fa718 13772 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13773 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13774
5eb08b69 13775 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13776 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13777
270b3042 13778 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13779 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13780 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13781 /*
13782 * The DP_DETECTED bit is the latched state of the DDC
13783 * SDA pin at boot. However since eDP doesn't require DDC
13784 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13785 * eDP ports may have been muxed to an alternate function.
13786 * Thus we can't rely on the DP_DETECTED bit alone to detect
13787 * eDP ports. Consult the VBT as well as DP_DETECTED to
13788 * detect eDP ports.
13789 */
d2182a66
VS		 13790 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13791 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13792 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13793 PORT_B);
e17ac6db
VS		 13794 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13795 intel_dp_is_edp(dev, PORT_B))
13796 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13797
d2182a66
VS		 13798 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13799 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13800 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13801 PORT_C);
e17ac6db
VS		 13802 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13803 intel_dp_is_edp(dev, PORT_C))
13804 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13805
9418c1f1 13806 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13807 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13808 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13809 PORT_D);
e17ac6db
VS		 13810 /* eDP not supported on port D, so don't check VBT */
13811 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13812 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13813 }
13814
3cfca973 13815 intel_dsi_init(dev);
103a196f 13816 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13817 bool found = false;
7d57382e 13818
e2debe91 13819 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13820 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13821 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13822 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13823 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13824 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13825 }
27185ae1 13826
e7281eab 13827 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13828 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13829 }
13520b05
KH		 13830
13831 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13832
e2debe91 13833 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13834 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13835 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13836 }
27185ae1 13837
e2debe91 13838 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13839
b01f2c3a
JB		 13840 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13841 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13842 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13843 }
e7281eab 13844 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13845 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13846 }
27185ae1 13847
b01f2c3a 13848 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13849 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13850 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13851 } else if (IS_GEN2(dev))
79e53945
JB		 13852 intel_dvo_init(dev);
13853
103a196f 13854 if (SUPPORTS_TV(dev))
79e53945
JB		 13855 intel_tv_init(dev);
13856
0bc12bcb 13857 intel_psr_init(dev);
7c8f8a70 13858
b2784e15 13859 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13860 encoder->base.possible_crtcs = encoder->crtc_mask;
13861 encoder->base.possible_clones =
66a9278e 13862 intel_encoder_clones(encoder);
79e53945 13863 }
47356eb6 13864
dde86e2d 13865 intel_init_pch_refclk(dev);
270b3042
DV		 13866
13867 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13868}
13869
13870static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13871{
60a5ca01 13872 struct drm_device *dev = fb->dev;
79e53945 13873 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13874
ef2d633e 13875 drm_framebuffer_cleanup(fb);
60a5ca01 13876 mutex_lock(&dev->struct_mutex);
ef2d633e 13877 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13878 drm_gem_object_unreference(&intel_fb->obj->base);
13879 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13880 kfree(intel_fb);
13881}
13882
13883static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13884 struct drm_file *file,
79e53945
JB		 13885 unsigned int *handle)
13886{
13887 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13888 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13889
05394f39 13890 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13891}
13892
13893static const struct drm_framebuffer_funcs intel_fb_funcs = {
13894 .destroy = intel_user_framebuffer_destroy,
13895 .create_handle = intel_user_framebuffer_create_handle,
13896};
13897
b321803d
DL		 13898static
13899u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13900 uint32_t pixel_format)
13901{
13902 u32 gen = INTEL_INFO(dev)->gen;
13903
13904 if (gen >= 9) {
13905 /* "The stride in bytes must not exceed the of the size of 8K
13906 * pixels and 32K bytes."
13907 */
13908 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13909 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13910 return 32*1024;
13911 } else if (gen >= 4) {
13912 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13913 return 16*1024;
13914 else
13915 return 32*1024;
13916 } else if (gen >= 3) {
13917 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13918 return 8*1024;
13919 else
13920 return 16*1024;
13921 } else {
13922 /* XXX DSPC is limited to 4k tiled */
13923 return 8*1024;
13924 }
13925}
13926
b5ea642a
DV		 13927static int intel_framebuffer_init(struct drm_device *dev,
13928 struct intel_framebuffer *intel_fb,
13929 struct drm_mode_fb_cmd2 *mode_cmd,
13930 struct drm_i915_gem_object *obj)
79e53945 13931{
6761dd31 13932 unsigned int aligned_height;
79e53945 13933 int ret;
b321803d 13934 u32 pitch_limit, stride_alignment;
79e53945 13935
dd4916c5
DV		 13936 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13937
2a80eada
DV		 13938 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13939 /* Enforce that fb modifier and tiling mode match, but only for
13940 * X-tiled. This is needed for FBC. */
13941 if (!!(obj->tiling_mode == I915_TILING_X) !=
13942 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13943 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13944 return -EINVAL;
13945 }
13946 } else {
13947 if (obj->tiling_mode == I915_TILING_X)
13948 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13949 else if (obj->tiling_mode == I915_TILING_Y) {
13950 DRM_DEBUG("No Y tiling for legacy addfb\n");
13951 return -EINVAL;
13952 }
13953 }
13954
9a8f0a12
TU		 13955 /* Passed in modifier sanity checking. */
13956 switch (mode_cmd->modifier[0]) {
13957 case I915_FORMAT_MOD_Y_TILED:
13958 case I915_FORMAT_MOD_Yf_TILED:
13959 if (INTEL_INFO(dev)->gen < 9) {
13960 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13961 mode_cmd->modifier[0]);
13962 return -EINVAL;
13963 }
13964 case DRM_FORMAT_MOD_NONE:
13965 case I915_FORMAT_MOD_X_TILED:
13966 break;
13967 default:
c0f40428
JB		 13968 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13969 mode_cmd->modifier[0]);
57cd6508 13970 return -EINVAL;
c16ed4be 13971 }
57cd6508 13972
b321803d
DL		 13973 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13974 mode_cmd->pixel_format);
13975 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13976 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13977 mode_cmd->pitches[0], stride_alignment);
57cd6508 13978 return -EINVAL;
c16ed4be 13979 }
57cd6508 13980
b321803d
DL		 13981 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13982 mode_cmd->pixel_format);
a35cdaa0 13983 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13984 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13985 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13986 "tiled" : "linear",
a35cdaa0 13987 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13988 return -EINVAL;
c16ed4be 13989 }
5d7bd705 13990
2a80eada 13991 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13992 mode_cmd->pitches[0] != obj->stride) {
13993 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13994 mode_cmd->pitches[0], obj->stride);
5d7bd705 13995 return -EINVAL;
c16ed4be 13996 }
5d7bd705 13997
57779d06 13998 /* Reject formats not supported by any plane early. */
308e5bcb 13999 switch (mode_cmd->pixel_format) {
57779d06 14000 case DRM_FORMAT_C8:
04b3924d
VS		 14001 case DRM_FORMAT_RGB565:
14002 case DRM_FORMAT_XRGB8888:
14003 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14004 break;
14005 case DRM_FORMAT_XRGB1555:
14006 case DRM_FORMAT_ARGB1555:
c16ed4be 14007 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14008 DRM_DEBUG("unsupported pixel format: %s\n",
14009 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14010 return -EINVAL;
c16ed4be 14011 }
57779d06
VS		 14012 break;
14013 case DRM_FORMAT_XBGR8888:
14014 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14015 case DRM_FORMAT_XRGB2101010:
14016 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14017 case DRM_FORMAT_XBGR2101010:
14018 case DRM_FORMAT_ABGR2101010:
c16ed4be 14019 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14020 DRM_DEBUG("unsupported pixel format: %s\n",
14021 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14022 return -EINVAL;
c16ed4be 14023 }
b5626747 14024 break;
04b3924d
VS		 14025 case DRM_FORMAT_YUYV:
14026 case DRM_FORMAT_UYVY:
14027 case DRM_FORMAT_YVYU:
14028 case DRM_FORMAT_VYUY:
c16ed4be 14029 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14030 DRM_DEBUG("unsupported pixel format: %s\n",
14031 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14032 return -EINVAL;
c16ed4be 14033 }
57cd6508
CW		 14034 break;
14035 default:
4ee62c76
VS		 14036 DRM_DEBUG("unsupported pixel format: %s\n",
14037 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14038 return -EINVAL;
14039 }
14040
90f9a336
VS		 14041 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14042 if (mode_cmd->offsets[0] != 0)
14043 return -EINVAL;
14044
ec2c981e 14045 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14046 mode_cmd->pixel_format,
14047 mode_cmd->modifier[0]);
53155c0a
DV		 14048 /* FIXME drm helper for size checks (especially planar formats)? */
14049 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14050 return -EINVAL;
14051
c7d73f6a
DV		 14052 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14053 intel_fb->obj = obj;
80075d49 14054 intel_fb->obj->framebuffer_references++;
c7d73f6a 14055
79e53945
JB		 14056 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14057 if (ret) {
14058 DRM_ERROR("framebuffer init failed %d\n", ret);
14059 return ret;
14060 }
14061
79e53945
JB		 14062 return 0;
14063}
14064
79e53945
JB		 14065static struct drm_framebuffer *
14066intel_user_framebuffer_create(struct drm_device *dev,
14067 struct drm_file *filp,
308e5bcb 14068 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14069{
05394f39 14070 struct drm_i915_gem_object *obj;
79e53945 14071
308e5bcb
JB		 14072 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14073 mode_cmd->handles[0]));
c8725226 14074 if (&obj->base == NULL)
cce13ff7 14075 return ERR_PTR(-ENOENT);
79e53945 14076
d2dff872 14077 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14078}
14079
4520f53a 14080#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14081static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14082{
14083}
14084#endif
14085
79e53945 14086static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14087 .fb_create = intel_user_framebuffer_create,
0632fef6 14088 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14089 .atomic_check = intel_atomic_check,
14090 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14091};
14092
e70236a8
JB		 14093/* Set up chip specific display functions */
14094static void intel_init_display(struct drm_device *dev)
14095{
14096 struct drm_i915_private *dev_priv = dev->dev_private;
14097
ee9300bb
DV		 14098 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14099 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14100 else if (IS_CHERRYVIEW(dev))
14101 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14102 else if (IS_VALLEYVIEW(dev))
14103 dev_priv->display.find_dpll = vlv_find_best_dpll;
14104 else if (IS_PINEVIEW(dev))
14105 dev_priv->display.find_dpll = pnv_find_best_dpll;
14106 else
14107 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14108
bc8d7dff
DL		 14109 if (INTEL_INFO(dev)->gen >= 9) {
14110 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14111 dev_priv->display.get_initial_plane_config =
14112 skylake_get_initial_plane_config;
bc8d7dff
DL		 14113 dev_priv->display.crtc_compute_clock =
14114 haswell_crtc_compute_clock;
14115 dev_priv->display.crtc_enable = haswell_crtc_enable;
14116 dev_priv->display.crtc_disable = haswell_crtc_disable;
14117 dev_priv->display.off = ironlake_crtc_off;
14118 dev_priv->display.update_primary_plane =
14119 skylake_update_primary_plane;
14120 } else if (HAS_DDI(dev)) {
0e8ffe1b 14121 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14122 dev_priv->display.get_initial_plane_config =
14123 ironlake_get_initial_plane_config;
797d0259
ACO		 14124 dev_priv->display.crtc_compute_clock =
14125 haswell_crtc_compute_clock;
4f771f10
PZ		 14126 dev_priv->display.crtc_enable = haswell_crtc_enable;
14127 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14128 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14129 dev_priv->display.update_primary_plane =
14130 ironlake_update_primary_plane;
09b4ddf9 14131 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14132 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14133 dev_priv->display.get_initial_plane_config =
14134 ironlake_get_initial_plane_config;
3fb37703
ACO		 14135 dev_priv->display.crtc_compute_clock =
14136 ironlake_crtc_compute_clock;
76e5a89c
DV		 14137 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14138 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14139 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14140 dev_priv->display.update_primary_plane =
14141 ironlake_update_primary_plane;
89b667f8
JB		 14142 } else if (IS_VALLEYVIEW(dev)) {
14143 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14144 dev_priv->display.get_initial_plane_config =
14145 i9xx_get_initial_plane_config;
d6dfee7a 14146 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14147 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14148 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14149 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14150 dev_priv->display.update_primary_plane =
14151 i9xx_update_primary_plane;
f564048e 14152 } else {
0e8ffe1b 14153 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14154 dev_priv->display.get_initial_plane_config =
14155 i9xx_get_initial_plane_config;
d6dfee7a 14156 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14157 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14158 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14159 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14160 dev_priv->display.update_primary_plane =
14161 i9xx_update_primary_plane;
f564048e 14162 }
e70236a8 14163
e70236a8 14164 /* Returns the core display clock speed */
1652d19e
VS		 14165 if (IS_SKYLAKE(dev))
14166 dev_priv->display.get_display_clock_speed =
14167 skylake_get_display_clock_speed;
14168 else if (IS_BROADWELL(dev))
14169 dev_priv->display.get_display_clock_speed =
14170 broadwell_get_display_clock_speed;
14171 else if (IS_HASWELL(dev))
14172 dev_priv->display.get_display_clock_speed =
14173 haswell_get_display_clock_speed;
14174 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14175 dev_priv->display.get_display_clock_speed =
14176 valleyview_get_display_clock_speed;
b37a6434
VS		 14177 else if (IS_GEN5(dev))
14178 dev_priv->display.get_display_clock_speed =
14179 ilk_get_display_clock_speed;
a7c66cd8
VS		 14180 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14181 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14182 dev_priv->display.get_display_clock_speed =
14183 i945_get_display_clock_speed;
14184 else if (IS_I915G(dev))
14185 dev_priv->display.get_display_clock_speed =
14186 i915_get_display_clock_speed;
257a7ffc 14187 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14188 dev_priv->display.get_display_clock_speed =
14189 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14190 else if (IS_PINEVIEW(dev))
14191 dev_priv->display.get_display_clock_speed =
14192 pnv_get_display_clock_speed;
e70236a8
JB		 14193 else if (IS_I915GM(dev))
14194 dev_priv->display.get_display_clock_speed =
14195 i915gm_get_display_clock_speed;
14196 else if (IS_I865G(dev))
14197 dev_priv->display.get_display_clock_speed =
14198 i865_get_display_clock_speed;
f0f8a9ce 14199 else if (IS_I85X(dev))
e70236a8
JB		 14200 dev_priv->display.get_display_clock_speed =
14201 i855_get_display_clock_speed;
14202 else /* 852, 830 */
14203 dev_priv->display.get_display_clock_speed =
14204 i830_get_display_clock_speed;
14205
7c10a2b5 14206 if (IS_GEN5(dev)) {
3bb11b53 14207 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14208 } else if (IS_GEN6(dev)) {
14209 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14210 } else if (IS_IVYBRIDGE(dev)) {
14211 /* FIXME: detect B0+ stepping and use auto training */
14212 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14213 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14214 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14215 } else if (IS_VALLEYVIEW(dev)) {
14216 dev_priv->display.modeset_global_resources =
14217 valleyview_modeset_global_resources;
f8437dd1
VK		 14218 } else if (IS_BROXTON(dev)) {
14219 dev_priv->display.modeset_global_resources =
14220 broxton_modeset_global_resources;
e70236a8 14221 }
8c9f3aaf 14222
8c9f3aaf
JB		 14223 switch (INTEL_INFO(dev)->gen) {
14224 case 2:
14225 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14226 break;
14227
14228 case 3:
14229 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14230 break;
14231
14232 case 4:
14233 case 5:
14234 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14235 break;
14236
14237 case 6:
14238 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14239 break;
7c9017e5 14240 case 7:
4e0bbc31 14241 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14242 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14243 break;
830c81db 14244 case 9:
ba343e02
TU		 14245 /* Drop through - unsupported since execlist only. */
14246 default:
14247 /* Default just returns -ENODEV to indicate unsupported */
14248 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14249 }
7bd688cd
JN		 14250
14251 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14252
14253 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14254}
14255
b690e96c
JB		 14256/*
14257 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14258 * resume, or other times. This quirk makes sure that's the case for
14259 * affected systems.
14260 */
0206e353 14261static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14262{
14263 struct drm_i915_private *dev_priv = dev->dev_private;
14264
14265 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14266 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14267}
14268
b6b5d049
VS		 14269static void quirk_pipeb_force(struct drm_device *dev)
14270{
14271 struct drm_i915_private *dev_priv = dev->dev_private;
14272
14273 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14274 DRM_INFO("applying pipe b force quirk\n");
14275}
14276
435793df
KP		 14277/*
14278 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14279 */
14280static void quirk_ssc_force_disable(struct drm_device *dev)
14281{
14282 struct drm_i915_private *dev_priv = dev->dev_private;
14283 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14284 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14285}
14286
4dca20ef 14287/*
5a15ab5b
CE		 14288 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14289 * brightness value
4dca20ef
CE		 14290 */
14291static void quirk_invert_brightness(struct drm_device *dev)
14292{
14293 struct drm_i915_private *dev_priv = dev->dev_private;
14294 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14295 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14296}
14297
9c72cc6f
SD		 14298/* Some VBT's incorrectly indicate no backlight is present */
14299static void quirk_backlight_present(struct drm_device *dev)
14300{
14301 struct drm_i915_private *dev_priv = dev->dev_private;
14302 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14303 DRM_INFO("applying backlight present quirk\n");
14304}
14305
b690e96c
JB		 14306struct intel_quirk {
14307 int device;
14308 int subsystem_vendor;
14309 int subsystem_device;
14310 void (*hook)(struct drm_device *dev);
14311};
14312
5f85f176
EE		 14313/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14314struct intel_dmi_quirk {
14315 void (*hook)(struct drm_device *dev);
14316 const struct dmi_system_id (*dmi_id_list)[];
14317};
14318
14319static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14320{
14321 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14322 return 1;
14323}
14324
14325static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14326 {
14327 .dmi_id_list = &(const struct dmi_system_id[]) {
14328 {
14329 .callback = intel_dmi_reverse_brightness,
14330 .ident = "NCR Corporation",
14331 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14332 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14333 },
14334 },
14335 { } /* terminating entry */
14336 },
14337 .hook = quirk_invert_brightness,
14338 },
14339};
14340
c43b5634 14341static struct intel_quirk intel_quirks[] = {
b690e96c 14342 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14343 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14344
b690e96c
JB		 14345 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14346 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14347
b690e96c
JB		 14348 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14349 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14350
5f080c0f
VS		 14351 /* 830 needs to leave pipe A & dpll A up */
14352 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14353
b6b5d049
VS		 14354 /* 830 needs to leave pipe B & dpll B up */
14355 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14356
435793df
KP		 14357 /* Lenovo U160 cannot use SSC on LVDS */
14358 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14359
14360 /* Sony Vaio Y cannot use SSC on LVDS */
14361 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14362
be505f64
AH		 14363 /* Acer Aspire 5734Z must invert backlight brightness */
14364 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14365
14366 /* Acer/eMachines G725 */
14367 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14368
14369 /* Acer/eMachines e725 */
14370 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14371
14372 /* Acer/Packard Bell NCL20 */
14373 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14374
14375 /* Acer Aspire 4736Z */
14376 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14377
14378 /* Acer Aspire 5336 */
14379 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14380
14381 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14382 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14383
dfb3d47b
SD		 14384 /* Acer C720 Chromebook (Core i3 4005U) */
14385 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14386
b2a9601c 14387 /* Apple Macbook 2,1 (Core 2 T7400) */
14388 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14389
d4967d8c
SD		 14390 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14391 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14392
14393 /* HP Chromebook 14 (Celeron 2955U) */
14394 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14395
14396 /* Dell Chromebook 11 */
14397 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14398};
14399
14400static void intel_init_quirks(struct drm_device *dev)
14401{
14402 struct pci_dev *d = dev->pdev;
14403 int i;
14404
14405 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14406 struct intel_quirk *q = &intel_quirks[i];
14407
14408 if (d->device == q->device &&
14409 (d->subsystem_vendor == q->subsystem_vendor ||
14410 q->subsystem_vendor == PCI_ANY_ID) &&
14411 (d->subsystem_device == q->subsystem_device ||
14412 q->subsystem_device == PCI_ANY_ID))
14413 q->hook(dev);
14414 }
5f85f176
EE		 14415 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14416 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14417 intel_dmi_quirks[i].hook(dev);
14418 }
b690e96c
JB		 14419}
14420
9cce37f4
JB		 14421/* Disable the VGA plane that we never use */
14422static void i915_disable_vga(struct drm_device *dev)
14423{
14424 struct drm_i915_private *dev_priv = dev->dev_private;
14425 u8 sr1;
766aa1c4 14426 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14427
2b37c616 14428 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14429 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14430 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14431 sr1 = inb(VGA_SR_DATA);
14432 outb(sr1 | 1<<5, VGA_SR_DATA);
14433 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14434 udelay(300);
14435
01f5a626 14436 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14437 POSTING_READ(vga_reg);
14438}
14439
f817586c
DV		 14440void intel_modeset_init_hw(struct drm_device *dev)
14441{
a8f78b58
ED		 14442 intel_prepare_ddi(dev);
14443
f8bf63fd
VS		 14444 if (IS_VALLEYVIEW(dev))
14445 vlv_update_cdclk(dev);
14446
f817586c
DV		 14447 intel_init_clock_gating(dev);
14448
8090c6b9 14449 intel_enable_gt_powersave(dev);
f817586c
DV		 14450}
14451
79e53945
JB		 14452void intel_modeset_init(struct drm_device *dev)
14453{
652c393a 14454 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14455 int sprite, ret;
8cc87b75 14456 enum pipe pipe;
46f297fb 14457 struct intel_crtc *crtc;
79e53945
JB		 14458
14459 drm_mode_config_init(dev);
14460
14461 dev->mode_config.min_width = 0;
14462 dev->mode_config.min_height = 0;
14463
019d96cb
DA		 14464 dev->mode_config.preferred_depth = 24;
14465 dev->mode_config.prefer_shadow = 1;
14466
25bab385
TU		 14467 dev->mode_config.allow_fb_modifiers = true;
14468
e6ecefaa 14469 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14470
b690e96c
JB		 14471 intel_init_quirks(dev);
14472
1fa61106
ED		 14473 intel_init_pm(dev);
14474
e3c74757
BW		 14475 if (INTEL_INFO(dev)->num_pipes == 0)
14476 return;
14477
e70236a8 14478 intel_init_display(dev);
7c10a2b5 14479 intel_init_audio(dev);
e70236a8 14480
a6c45cf0
CW		 14481 if (IS_GEN2(dev)) {
14482 dev->mode_config.max_width = 2048;
14483 dev->mode_config.max_height = 2048;
14484 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14485 dev->mode_config.max_width = 4096;
14486 dev->mode_config.max_height = 4096;
79e53945 14487 } else {
a6c45cf0
CW		 14488 dev->mode_config.max_width = 8192;
14489 dev->mode_config.max_height = 8192;
79e53945 14490 }
068be561 14491
dc41c154
VS		 14492 if (IS_845G(dev) || IS_I865G(dev)) {
14493 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14494 dev->mode_config.cursor_height = 1023;
14495 } else if (IS_GEN2(dev)) {
068be561
DL		 14496 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14497 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14498 } else {
14499 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14500 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14501 }
14502
5d4545ae 14503 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14504
28c97730 14505 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14506 INTEL_INFO(dev)->num_pipes,
14507 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14508
055e393f 14509 for_each_pipe(dev_priv, pipe) {
8cc87b75 14510 intel_crtc_init(dev, pipe);
3bdcfc0c 14511 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14512 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14513 if (ret)
06da8da2 14514 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14515 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14516 }
79e53945
JB		 14517 }
14518
f42bb70d
JB		 14519 intel_init_dpio(dev);
14520
e72f9fbf 14521 intel_shared_dpll_init(dev);
ee7b9f93 14522
9cce37f4
JB		 14523 /* Just disable it once at startup */
14524 i915_disable_vga(dev);
79e53945 14525 intel_setup_outputs(dev);
11be49eb
CW		 14526
14527 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14528 intel_fbc_disable(dev);
fa9fa083 14529
6e9f798d 14530 drm_modeset_lock_all(dev);
fa9fa083 14531 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14532 drm_modeset_unlock_all(dev);
46f297fb 14533
d3fcc808 14534 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14535 if (!crtc->active)
14536 continue;
14537
46f297fb 14538 /*
46f297fb
JB		 14539 * Note that reserving the BIOS fb up front prevents us
14540 * from stuffing other stolen allocations like the ring
14541 * on top. This prevents some ugliness at boot time, and
14542 * can even allow for smooth boot transitions if the BIOS
14543 * fb is large enough for the active pipe configuration.
14544 */
5724dbd1
DL		 14545 if (dev_priv->display.get_initial_plane_config) {
14546 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14547 &crtc->plane_config);
14548 /*
14549 * If the fb is shared between multiple heads, we'll
14550 * just get the first one.
14551 */
f6936e29 14552 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14553 }
46f297fb 14554 }
2c7111db
CW		 14555}
14556
7fad798e
DV		 14557static void intel_enable_pipe_a(struct drm_device *dev)
14558{
14559 struct intel_connector *connector;
14560 struct drm_connector *crt = NULL;
14561 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14562 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14563
14564 /* We can't just switch on the pipe A, we need to set things up with a
14565 * proper mode and output configuration. As a gross hack, enable pipe A
14566 * by enabling the load detect pipe once. */
3a3371ff 14567 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14568 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14569 crt = &connector->base;
14570 break;
14571 }
14572 }
14573
14574 if (!crt)
14575 return;
14576
208bf9fd 14577 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14578 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14579}
14580
fa555837
DV		 14581static bool
14582intel_check_plane_mapping(struct intel_crtc *crtc)
14583{
7eb552ae
BW		 14584 struct drm_device *dev = crtc->base.dev;
14585 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14586 u32 reg, val;
14587
7eb552ae 14588 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14589 return true;
14590
14591 reg = DSPCNTR(!crtc->plane);
14592 val = I915_READ(reg);
14593
14594 if ((val & DISPLAY_PLANE_ENABLE) &&
14595 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14596 return false;
14597
14598 return true;
14599}
14600
24929352
DV		 14601static void intel_sanitize_crtc(struct intel_crtc *crtc)
14602{
14603 struct drm_device *dev = crtc->base.dev;
14604 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14605 u32 reg;
24929352 14606
24929352 14607 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14608 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14609 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14610
d3eaf884 14611 /* restore vblank interrupts to correct state */
9625604c 14612 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14613 if (crtc->active) {
14614 update_scanline_offset(crtc);
9625604c
DV		 14615 drm_crtc_vblank_on(&crtc->base);
14616 }
d3eaf884 14617
24929352 14618 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14619 * disable the crtc (and hence change the state) if it is wrong. Note
14620 * that gen4+ has a fixed plane -> pipe mapping. */
14621 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14622 struct intel_connector *connector;
14623 bool plane;
14624
24929352
DV		 14625 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14626 crtc->base.base.id);
14627
14628 /* Pipe has the wrong plane attached and the plane is active.
14629 * Temporarily change the plane mapping and disable everything
14630 * ... */
14631 plane = crtc->plane;
14632 crtc->plane = !plane;
9c8958bc 14633 crtc->primary_enabled = true;
24929352
DV		 14634 dev_priv->display.crtc_disable(&crtc->base);
14635 crtc->plane = plane;
14636
14637 /* ... and break all links. */
3a3371ff 14638 for_each_intel_connector(dev, connector) {
24929352
DV		 14639 if (connector->encoder->base.crtc != &crtc->base)
14640 continue;
14641
7f1950fb
EE		 14642 connector->base.dpms = DRM_MODE_DPMS_OFF;
14643 connector->base.encoder = NULL;
24929352 14644 }
7f1950fb
EE		 14645 /* multiple connectors may have the same encoder:
14646 * handle them and break crtc link separately */
3a3371ff 14647 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14648 if (connector->encoder->base.crtc == &crtc->base) {
14649 connector->encoder->base.crtc = NULL;
14650 connector->encoder->connectors_active = false;
14651 }
24929352
DV		 14652
14653 WARN_ON(crtc->active);
83d65738 14654 crtc->base.state->enable = false;
24929352
DV		 14655 crtc->base.enabled = false;
14656 }
24929352 14657
7fad798e
DV		 14658 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14659 crtc->pipe == PIPE_A && !crtc->active) {
14660 /* BIOS forgot to enable pipe A, this mostly happens after
14661 * resume. Force-enable the pipe to fix this, the update_dpms
14662 * call below we restore the pipe to the right state, but leave
14663 * the required bits on. */
14664 intel_enable_pipe_a(dev);
14665 }
14666
24929352
DV		 14667 /* Adjust the state of the output pipe according to whether we
14668 * have active connectors/encoders. */
14669 intel_crtc_update_dpms(&crtc->base);
14670
83d65738 14671 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14672 struct intel_encoder *encoder;
14673
14674 /* This can happen either due to bugs in the get_hw_state
14675 * functions or because the pipe is force-enabled due to the
14676 * pipe A quirk. */
14677 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14678 crtc->base.base.id,
83d65738 14679 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14680 crtc->active ? "enabled" : "disabled");
14681
83d65738 14682 crtc->base.state->enable = crtc->active;
24929352
DV		 14683 crtc->base.enabled = crtc->active;
14684
14685 /* Because we only establish the connector -> encoder ->
14686 * crtc links if something is active, this means the
14687 * crtc is now deactivated. Break the links. connector
14688 * -> encoder links are only establish when things are
14689 * actually up, hence no need to break them. */
14690 WARN_ON(crtc->active);
14691
14692 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14693 WARN_ON(encoder->connectors_active);
14694 encoder->base.crtc = NULL;
14695 }
14696 }
c5ab3bc0 14697
a3ed6aad 14698 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14699 /*
14700 * We start out with underrun reporting disabled to avoid races.
14701 * For correct bookkeeping mark this on active crtcs.
14702 *
c5ab3bc0
DV		 14703 * Also on gmch platforms we dont have any hardware bits to
14704 * disable the underrun reporting. Which means we need to start
14705 * out with underrun reporting disabled also on inactive pipes,
14706 * since otherwise we'll complain about the garbage we read when
14707 * e.g. coming up after runtime pm.
14708 *
4cc31489
DV		 14709 * No protection against concurrent access is required - at
14710 * worst a fifo underrun happens which also sets this to false.
14711 */
14712 crtc->cpu_fifo_underrun_disabled = true;
14713 crtc->pch_fifo_underrun_disabled = true;
14714 }
24929352
DV		 14715}
14716
14717static void intel_sanitize_encoder(struct intel_encoder *encoder)
14718{
14719 struct intel_connector *connector;
14720 struct drm_device *dev = encoder->base.dev;
14721
14722 /* We need to check both for a crtc link (meaning that the
14723 * encoder is active and trying to read from a pipe) and the
14724 * pipe itself being active. */
14725 bool has_active_crtc = encoder->base.crtc &&
14726 to_intel_crtc(encoder->base.crtc)->active;
14727
14728 if (encoder->connectors_active && !has_active_crtc) {
14729 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14730 encoder->base.base.id,
8e329a03 14731 encoder->base.name);
24929352
DV		 14732
14733 /* Connector is active, but has no active pipe. This is
14734 * fallout from our resume register restoring. Disable
14735 * the encoder manually again. */
14736 if (encoder->base.crtc) {
14737 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14738 encoder->base.base.id,
8e329a03 14739 encoder->base.name);
24929352 14740 encoder->disable(encoder);
a62d1497
VS		 14741 if (encoder->post_disable)
14742 encoder->post_disable(encoder);
24929352 14743 }
7f1950fb
EE		 14744 encoder->base.crtc = NULL;
14745 encoder->connectors_active = false;
24929352
DV		 14746
14747 /* Inconsistent output/port/pipe state happens presumably due to
14748 * a bug in one of the get_hw_state functions. Or someplace else
14749 * in our code, like the register restore mess on resume. Clamp
14750 * things to off as a safer default. */
3a3371ff 14751 for_each_intel_connector(dev, connector) {
24929352
DV		 14752 if (connector->encoder != encoder)
14753 continue;
7f1950fb
EE		 14754 connector->base.dpms = DRM_MODE_DPMS_OFF;
14755 connector->base.encoder = NULL;
24929352
DV		 14756 }
14757 }
14758 /* Enabled encoders without active connectors will be fixed in
14759 * the crtc fixup. */
14760}
14761
04098753 14762void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14763{
14764 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14765 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14766
04098753
ID		 14767 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14768 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14769 i915_disable_vga(dev);
14770 }
14771}
14772
14773void i915_redisable_vga(struct drm_device *dev)
14774{
14775 struct drm_i915_private *dev_priv = dev->dev_private;
14776
8dc8a27c
PZ		 14777 /* This function can be called both from intel_modeset_setup_hw_state or
14778 * at a very early point in our resume sequence, where the power well
14779 * structures are not yet restored. Since this function is at a very
14780 * paranoid "someone might have enabled VGA while we were not looking"
14781 * level, just check if the power well is enabled instead of trying to
14782 * follow the "don't touch the power well if we don't need it" policy
14783 * the rest of the driver uses. */
f458ebbc 14784 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14785 return;
14786
04098753 14787 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14788}
14789
98ec7739
VS		 14790static bool primary_get_hw_state(struct intel_crtc *crtc)
14791{
14792 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14793
14794 if (!crtc->active)
14795 return false;
14796
14797 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14798}
14799
30e984df 14800static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14801{
14802 struct drm_i915_private *dev_priv = dev->dev_private;
14803 enum pipe pipe;
24929352
DV		 14804 struct intel_crtc *crtc;
14805 struct intel_encoder *encoder;
14806 struct intel_connector *connector;
5358901f 14807 int i;
24929352 14808
d3fcc808 14809 for_each_intel_crtc(dev, crtc) {
6e3c9717 14810 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14811
6e3c9717 14812 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14813
0e8ffe1b 14814 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14815 crtc->config);
24929352 14816
83d65738 14817 crtc->base.state->enable = crtc->active;
24929352 14818 crtc->base.enabled = crtc->active;
98ec7739 14819 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14820
14821 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14822 crtc->base.base.id,
14823 crtc->active ? "enabled" : "disabled");
14824 }
14825
5358901f
DV		 14826 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14827 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14828
3e369b76
ACO		 14829 pll->on = pll->get_hw_state(dev_priv, pll,
14830 &pll->config.hw_state);
5358901f 14831 pll->active = 0;
3e369b76 14832 pll->config.crtc_mask = 0;
d3fcc808 14833 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14834 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14835 pll->active++;
3e369b76 14836 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14837 }
5358901f 14838 }
5358901f 14839
1e6f2ddc 14840 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14841 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14842
3e369b76 14843 if (pll->config.crtc_mask)
bd2bb1b9 14844 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14845 }
14846
b2784e15 14847 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14848 pipe = 0;
14849
14850 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14851 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14852 encoder->base.crtc = &crtc->base;
6e3c9717 14853 encoder->get_config(encoder, crtc->config);
24929352
DV		 14854 } else {
14855 encoder->base.crtc = NULL;
14856 }
14857
14858 encoder->connectors_active = false;
6f2bcceb 14859 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14860 encoder->base.base.id,
8e329a03 14861 encoder->base.name,
24929352 14862 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14863 pipe_name(pipe));
24929352
DV		 14864 }
14865
3a3371ff 14866 for_each_intel_connector(dev, connector) {
24929352
DV		 14867 if (connector->get_hw_state(connector)) {
14868 connector->base.dpms = DRM_MODE_DPMS_ON;
14869 connector->encoder->connectors_active = true;
14870 connector->base.encoder = &connector->encoder->base;
14871 } else {
14872 connector->base.dpms = DRM_MODE_DPMS_OFF;
14873 connector->base.encoder = NULL;
14874 }
14875 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14876 connector->base.base.id,
c23cc417 14877 connector->base.name,
24929352
DV		 14878 connector->base.encoder ? "enabled" : "disabled");
14879 }
30e984df
DV		 14880}
14881
14882/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14883 * and i915 state tracking structures. */
14884void intel_modeset_setup_hw_state(struct drm_device *dev,
14885 bool force_restore)
14886{
14887 struct drm_i915_private *dev_priv = dev->dev_private;
14888 enum pipe pipe;
30e984df
DV		 14889 struct intel_crtc *crtc;
14890 struct intel_encoder *encoder;
35c95375 14891 int i;
30e984df
DV		 14892
14893 intel_modeset_readout_hw_state(dev);
24929352 14894
babea61d
JB		 14895 /*
14896 * Now that we have the config, copy it to each CRTC struct
14897 * Note that this could go away if we move to using crtc_config
14898 * checking everywhere.
14899 */
d3fcc808 14900 for_each_intel_crtc(dev, crtc) {
d330a953 14901 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14902 intel_mode_from_pipe_config(&crtc->base.mode,
14903 crtc->config);
babea61d
JB		 14904 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14905 crtc->base.base.id);
14906 drm_mode_debug_printmodeline(&crtc->base.mode);
14907 }
14908 }
14909
24929352 14910 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14911 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14912 intel_sanitize_encoder(encoder);
14913 }
14914
055e393f 14915 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14916 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14917 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14918 intel_dump_pipe_config(crtc, crtc->config,
14919 "[setup_hw_state]");
24929352 14920 }
9a935856 14921
d29b2f9d
ACO		 14922 intel_modeset_update_connector_atomic_state(dev);
14923
35c95375
DV		 14924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14925 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14926
14927 if (!pll->on || pll->active)
14928 continue;
14929
14930 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14931
14932 pll->disable(dev_priv, pll);
14933 pll->on = false;
14934 }
14935
3078999f
PB		 14936 if (IS_GEN9(dev))
14937 skl_wm_get_hw_state(dev);
14938 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14939 ilk_wm_get_hw_state(dev);
14940
45e2b5f6 14941 if (force_restore) {
7d0bc1ea
VS		 14942 i915_redisable_vga(dev);
14943
f30da187
DV		 14944 /*
14945 * We need to use raw interfaces for restoring state to avoid
14946 * checking (bogus) intermediate states.
14947 */
055e393f 14948 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14949 struct drm_crtc *crtc =
14950 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14951
83a57153 14952 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14953 }
14954 } else {
14955 intel_modeset_update_staged_output_state(dev);
14956 }
8af6cf88
DV		 14957
14958 intel_modeset_check_state(dev);
2c7111db
CW		 14959}
14960
14961void intel_modeset_gem_init(struct drm_device *dev)
14962{
92122789 14963 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14964 struct drm_crtc *c;
2ff8fde1 14965 struct drm_i915_gem_object *obj;
484b41dd 14966
ae48434c
ID		 14967 mutex_lock(&dev->struct_mutex);
14968 intel_init_gt_powersave(dev);
14969 mutex_unlock(&dev->struct_mutex);
14970
92122789
JB		 14971 /*
14972 * There may be no VBT; and if the BIOS enabled SSC we can
14973 * just keep using it to avoid unnecessary flicker. Whereas if the
14974 * BIOS isn't using it, don't assume it will work even if the VBT
14975 * indicates as much.
14976 */
14977 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14978 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14979 DREF_SSC1_ENABLE);
14980
1833b134 14981 intel_modeset_init_hw(dev);
02e792fb
DV		 14982
14983 intel_setup_overlay(dev);
484b41dd
JB		 14984
14985 /*
14986 * Make sure any fbs we allocated at startup are properly
14987 * pinned & fenced. When we do the allocation it's too early
14988 * for this.
14989 */
14990 mutex_lock(&dev->struct_mutex);
70e1e0ec 14991 for_each_crtc(dev, c) {
2ff8fde1
MR		 14992 obj = intel_fb_obj(c->primary->fb);
14993 if (obj == NULL)
484b41dd
JB		 14994 continue;
14995
850c4cdc
TU		 14996 if (intel_pin_and_fence_fb_obj(c->primary,
14997 c->primary->fb,
82bc3b2d 14998 c->primary->state,
850c4cdc 14999 NULL)) {
484b41dd
JB		 15000 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15001 to_intel_crtc(c)->pipe);
66e514c1
DA		 15002 drm_framebuffer_unreference(c->primary->fb);
15003 c->primary->fb = NULL;
afd65eb4 15004 update_state_fb(c->primary);
484b41dd
JB		 15005 }
15006 }
15007 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 15008
15009 intel_backlight_register(dev);
79e53945
JB		 15010}
15011
4932e2c3
ID		 15012void intel_connector_unregister(struct intel_connector *intel_connector)
15013{
15014 struct drm_connector *connector = &intel_connector->base;
15015
15016 intel_panel_destroy_backlight(connector);
34ea3d38 15017 drm_connector_unregister(connector);
4932e2c3
ID		 15018}
15019
79e53945
JB		 15020void intel_modeset_cleanup(struct drm_device *dev)
15021{
652c393a 15022 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15023 struct drm_connector *connector;
652c393a 15024
2eb5252e
ID		 15025 intel_disable_gt_powersave(dev);
15026
0962c3c9
VS		 15027 intel_backlight_unregister(dev);
15028
fd0c0642
DV		 15029 /*
15030 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15031 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15032 * experience fancy races otherwise.
15033 */
2aeb7d3a 15034 intel_irq_uninstall(dev_priv);
eb21b92b 15035
fd0c0642
DV		 15036 /*
15037 * Due to the hpd irq storm handling the hotplug work can re-arm the
15038 * poll handlers. Hence disable polling after hpd handling is shut down.
15039 */
f87ea761 15040 drm_kms_helper_poll_fini(dev);
fd0c0642 15041
652c393a
JB		 15042 mutex_lock(&dev->struct_mutex);
15043
723bfd70
JB		 15044 intel_unregister_dsm_handler();
15045
7ff0ebcc 15046 intel_fbc_disable(dev);
e70236a8 15047
69341a5e
KH		 15048 mutex_unlock(&dev->struct_mutex);
15049
1630fe75
CW		 15050 /* flush any delayed tasks or pending work */
15051 flush_scheduled_work();
15052
db31af1d
JN		 15053 /* destroy the backlight and sysfs files before encoders/connectors */
15054 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15055 struct intel_connector *intel_connector;
15056
15057 intel_connector = to_intel_connector(connector);
15058 intel_connector->unregister(intel_connector);
db31af1d 15059 }
d9255d57 15060
79e53945 15061 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15062
15063 intel_cleanup_overlay(dev);
ae48434c
ID		 15064
15065 mutex_lock(&dev->struct_mutex);
15066 intel_cleanup_gt_powersave(dev);
15067 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15068}
15069
f1c79df3
ZW		 15070/*
15071 * Return which encoder is currently attached for connector.
15072 */
df0e9248 15073struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15074{
df0e9248
CW		 15075 return &intel_attached_encoder(connector)->base;
15076}
f1c79df3 15077
df0e9248
CW		 15078void intel_connector_attach_encoder(struct intel_connector *connector,
15079 struct intel_encoder *encoder)
15080{
15081 connector->encoder = encoder;
15082 drm_mode_connector_attach_encoder(&connector->base,
15083 &encoder->base);
79e53945 15084}
28d52043
DA		 15085
15086/*
15087 * set vga decode state - true == enable VGA decode
15088 */
15089int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15090{
15091 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15092 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15093 u16 gmch_ctrl;
15094
75fa041d
CW		 15095 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15096 DRM_ERROR("failed to read control word\n");
15097 return -EIO;
15098 }
15099
c0cc8a55
CW		 15100 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15101 return 0;
15102
28d52043
DA		 15103 if (state)
15104 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15105 else
15106 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15107
15108 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15109 DRM_ERROR("failed to write control word\n");
15110 return -EIO;
15111 }
15112
28d52043
DA		 15113 return 0;
15114}
c4a1d9e4 15115
c4a1d9e4 15116struct intel_display_error_state {
ff57f1b0
PZ		 15117
15118 u32 power_well_driver;
15119
63b66e5b
CW		 15120 int num_transcoders;
15121
c4a1d9e4
CW		 15122 struct intel_cursor_error_state {
15123 u32 control;
15124 u32 position;
15125 u32 base;
15126 u32 size;
52331309 15127 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15128
15129 struct intel_pipe_error_state {
ddf9c536 15130 bool power_domain_on;
c4a1d9e4 15131 u32 source;
f301b1e1 15132 u32 stat;
52331309 15133 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15134
15135 struct intel_plane_error_state {
15136 u32 control;
15137 u32 stride;
15138 u32 size;
15139 u32 pos;
15140 u32 addr;
15141 u32 surface;
15142 u32 tile_offset;
52331309 15143 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15144
15145 struct intel_transcoder_error_state {
ddf9c536 15146 bool power_domain_on;
63b66e5b
CW		 15147 enum transcoder cpu_transcoder;
15148
15149 u32 conf;
15150
15151 u32 htotal;
15152 u32 hblank;
15153 u32 hsync;
15154 u32 vtotal;
15155 u32 vblank;
15156 u32 vsync;
15157 } transcoder[4];
c4a1d9e4
CW		 15158};
15159
15160struct intel_display_error_state *
15161intel_display_capture_error_state(struct drm_device *dev)
15162{
fbee40df 15163 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15164 struct intel_display_error_state *error;
63b66e5b
CW		 15165 int transcoders[] = {
15166 TRANSCODER_A,
15167 TRANSCODER_B,
15168 TRANSCODER_C,
15169 TRANSCODER_EDP,
15170 };
c4a1d9e4
CW		 15171 int i;
15172
63b66e5b
CW		 15173 if (INTEL_INFO(dev)->num_pipes == 0)
15174 return NULL;
15175
9d1cb914 15176 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15177 if (error == NULL)
15178 return NULL;
15179
190be112 15180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15181 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15182
055e393f 15183 for_each_pipe(dev_priv, i) {
ddf9c536 15184 error->pipe[i].power_domain_on =
f458ebbc
DV		 15185 __intel_display_power_is_enabled(dev_priv,
15186 POWER_DOMAIN_PIPE(i));
ddf9c536 15187 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15188 continue;
15189
5efb3e28
VS		 15190 error->cursor[i].control = I915_READ(CURCNTR(i));
15191 error->cursor[i].position = I915_READ(CURPOS(i));
15192 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15193
15194 error->plane[i].control = I915_READ(DSPCNTR(i));
15195 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15196 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15197 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15198 error->plane[i].pos = I915_READ(DSPPOS(i));
15199 }
ca291363
PZ		 15200 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15201 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15202 if (INTEL_INFO(dev)->gen >= 4) {
15203 error->plane[i].surface = I915_READ(DSPSURF(i));
15204 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15205 }
15206
c4a1d9e4 15207 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15208
3abfce77 15209 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15210 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15211 }
15212
15213 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15214 if (HAS_DDI(dev_priv->dev))
15215 error->num_transcoders++; /* Account for eDP. */
15216
15217 for (i = 0; i < error->num_transcoders; i++) {
15218 enum transcoder cpu_transcoder = transcoders[i];
15219
ddf9c536 15220 error->transcoder[i].power_domain_on =
f458ebbc 15221 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15222 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15223 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15224 continue;
15225
63b66e5b
CW		 15226 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15227
15228 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15229 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15230 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15231 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15232 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15233 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15234 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15235 }
15236
15237 return error;
15238}
15239
edc3d884
MK		 15240#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15241
c4a1d9e4 15242void
edc3d884 15243intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15244 struct drm_device *dev,
15245 struct intel_display_error_state *error)
15246{
055e393f 15247 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15248 int i;
15249
63b66e5b
CW		 15250 if (!error)
15251 return;
15252
edc3d884 15253 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15254 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15255 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15256 error->power_well_driver);
055e393f 15257 for_each_pipe(dev_priv, i) {
edc3d884 15258 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15259 err_printf(m, " Power: %s\n",
15260 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15261 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15262 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15263
15264 err_printf(m, "Plane [%d]:\n", i);
15265 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15266 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15267 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15268 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15269 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15270 }
4b71a570 15271 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15272 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15273 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15274 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15275 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15276 }
15277
edc3d884
MK		 15278 err_printf(m, "Cursor [%d]:\n", i);
15279 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15280 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15281 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15282 }
63b66e5b
CW		 15283
15284 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15285 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15286 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15287 err_printf(m, " Power: %s\n",
15288 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15289 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15290 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15291 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15292 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15293 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15294 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15295 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15296 }
c4a1d9e4 15297}
e2fcdaa9
VS		 15298
15299void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15300{
15301 struct intel_crtc *crtc;
15302
15303 for_each_intel_crtc(dev, crtc) {
15304 struct intel_unpin_work *work;
e2fcdaa9 15305
5e2d7afc 15306 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15307
15308 work = crtc->unpin_work;
15309
15310 if (work && work->event &&
15311 work->event->base.file_priv == file) {
15312 kfree(work->event);
15313 work->event = NULL;
15314 }
15315
5e2d7afc 15316 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15317 }
15318}
Linux kernel - Deliverables
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