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drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP .get_config()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB		 89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV		 93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
5ab7b0b7
ID		 401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
e6292556 404 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
cdba954e
ACO		 413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
fc596660 416 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 417}
418
e0638cdf
PZ		 419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
4093561b 422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 423{
409ee761 424 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 425 struct intel_encoder *encoder;
426
409ee761 427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
d0737e1d
ACO		 434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
a93e255f
ACO		 440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
d0737e1d 442{
a93e255f 443 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 444 struct drm_connector *connector;
a93e255f 445 struct drm_connector_state *connector_state;
d0737e1d 446 struct intel_encoder *encoder;
a93e255f
ACO		 447 int i, num_connectors = 0;
448
da3ced29 449 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
d0737e1d 454
a93e255f
ACO		 455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
d0737e1d 457 return true;
a93e255f
ACO		 458 }
459
460 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 461
462 return false;
463}
464
a93e255f
ACO		 465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 467{
a93e255f 468 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 469 const intel_limit_t *limit;
b91ad0ec 470
a93e255f 471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 472 if (intel_is_dual_link_lvds(dev)) {
1b894b59 473 if (refclk == 100000)
b91ad0ec
ZW		 474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
c6bb3538 483 } else
b91ad0ec 484 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 485
486 return limit;
487}
488
a93e255f
ACO		 489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 491{
a93e255f 492 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 493 const intel_limit_t *limit;
494
a93e255f 495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 496 if (intel_is_dual_link_lvds(dev))
e4b36699 497 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 498 else
e4b36699 499 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 502 limit = &intel_limits_g4x_hdmi;
a93e255f 503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 504 limit = &intel_limits_g4x_sdvo;
044c7c41 505 } else /* The option is for other outputs */
e4b36699 506 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 507
508 return limit;
509}
510
a93e255f
ACO		 511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 513{
a93e255f 514 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 515 const intel_limit_t *limit;
516
5ab7b0b7
ID		 517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
a93e255f 520 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 521 else if (IS_G4X(dev)) {
a93e255f 522 limit = intel_g4x_limit(crtc_state);
f2b115e6 523 } else if (IS_PINEVIEW(dev)) {
a93e255f 524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 525 limit = &intel_limits_pineview_lvds;
2177832f 526 else
f2b115e6 527 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
a0c4da24 530 } else if (IS_VALLEYVIEW(dev)) {
dc730512 531 limit = &intel_limits_vlv;
a6c45cf0 532 } else if (!IS_GEN2(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
79e53945 537 } else {
a93e255f 538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 539 limit = &intel_limits_i8xx_lvds;
a93e255f 540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 541 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 542 else
543 limit = &intel_limits_i8xx_dac;
79e53945
JB		 544 }
545 return limit;
546}
547
dccbea3b
ID		 548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
f2b115e6 556/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 558{
2177832f
SL		 559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
ed5ca77e 561 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 562 return 0;
fb03ac01
VS		 563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 565
566 return clock->dot;
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
dccbea3b 574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 579 return 0;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 582
583 return clock->dot;
79e53945
JB		 584}
585
dccbea3b 586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 591 return 0;
589eca67
ID		 592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 594
595 return clock->dot / 5;
589eca67
ID		 596}
597
dccbea3b 598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 603 return 0;
ef9348c8
CML		 604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 607
608 return clock->dot / 5;
ef9348c8
CML		 609}
610
7c04d1d9 611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
1b894b59
CW		 617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
79e53945 620{
f01b7962
VS		 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 624 INTELPllInvalid("p1 out of range\n");
79e53945 625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 626 INTELPllInvalid("m2 out of range\n");
79e53945 627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 628 INTELPllInvalid("m1 out of range\n");
f01b7962 629
5ab7b0b7 630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
5ab7b0b7 634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
79e53945 641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 642 INTELPllInvalid("vco out of range\n");
79e53945
JB		 643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 647 INTELPllInvalid("dot out of range\n");
79e53945
JB		 648
649 return true;
650}
651
3b1429d9
VS		 652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
79e53945 656{
3b1429d9 657 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 658
a93e255f 659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 660 /*
a210b028
DV		 661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
79e53945 664 */
1974cad0 665 if (intel_is_dual_link_lvds(dev))
3b1429d9 666 return limit->p2.p2_fast;
79e53945 667 else
3b1429d9 668 return limit->p2.p2_slow;
79e53945
JB		 669 } else {
670 if (target < limit->p2.dot_limit)
3b1429d9 671 return limit->p2.p2_slow;
79e53945 672 else
3b1429d9 673 return limit->p2.p2_fast;
79e53945 674 }
3b1429d9
VS		 675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
79e53945 686
0206e353 687 memset(best_clock, 0, sizeof(*best_clock));
79e53945 688
3b1429d9
VS		 689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 695 if (clock.m2 >= clock.m1)
42158660
ZY		 696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 701 int this_err;
702
dccbea3b 703 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
a93e255f
ACO		 725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
79e53945 729{
3b1429d9 730 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 731 intel_clock_t clock;
79e53945
JB		 732 int err = target;
733
0206e353 734 memset(best_clock, 0, sizeof(*best_clock));
79e53945 735
3b1429d9
VS		 736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
42158660
ZY		 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 746 int this_err;
747
dccbea3b 748 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
79e53945 751 continue;
cec2f356
SP		 752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
79e53945
JB		 755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
d4906093 769static bool
a93e255f
ACO		 770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
d4906093 774{
3b1429d9 775 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 776 intel_clock_t clock;
777 int max_n;
3b1429d9 778 bool found = false;
6ba770dc
AJ		 779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 781
782 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
d4906093 786 max_n = limit->n.max;
f77f13e2 787 /* based on hardware requirement, prefer smaller n to precision */
d4906093 788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 789 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
dccbea3b 798 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
d4906093 801 continue;
1b894b59
CW		 802
803 this_err = abs(clock.dot - target);
d4906093
ML		 804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
2c07245f
ZW		 814 return found;
815}
816
d5dd62bd
ID		 817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
9ca3ba01
ID		 827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
24be4e46
ID		 837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
d5dd62bd
ID		 840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
a0c4da24 857static bool
a93e255f
ACO		 858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
a0c4da24 862{
a93e255f 863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 864 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 865 intel_clock_t clock;
69e4f900 866 unsigned int bestppm = 1000000;
27e639bf
VS		 867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 869 bool found = false;
a0c4da24 870
6b4bf1c4
VS		 871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 874
875 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 880 clock.p = clock.p1 * clock.p2;
a0c4da24 881 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 883 unsigned int ppm;
69e4f900 884
6b4bf1c4
VS		 885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
dccbea3b 888 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 889
f01b7962
VS		 890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
43b0ac53
VS		 892 continue;
893
d5dd62bd
ID		 894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
6b4bf1c4 899
d5dd62bd
ID		 900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
a0c4da24
JB		 903 }
904 }
905 }
906 }
a0c4da24 907
49e497ef 908 return found;
a0c4da24 909}
a4fc5ed6 910
ef9348c8 911static bool
a93e255f
ACO		 912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
a93e255f 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 918 struct drm_device *dev = crtc->base.dev;
9ca3ba01 919 unsigned int best_error_ppm;
ef9348c8
CML		 920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 925 best_error_ppm = 1000000;
ef9348c8
CML		 926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 939 unsigned int error_ppm;
ef9348c8
CML		 940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
dccbea3b 951 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
9ca3ba01
ID		 956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
ef9348c8
CML		 963 }
964 }
965
966 return found;
967}
968
5ab7b0b7
ID		 969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
20ddf665
VS		 978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
241bfc38 985 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 986 * as Haswell has gained clock readout/fastboot support.
987 *
66e514c1 988 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 989 * properly reconstruct framebuffers.
c3d1f436
MR		 990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
20ddf665 994 */
c3d1f436 995 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 996 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 997}
998
a5c961d1
PZ		 999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
6e3c9717 1005 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1006}
1007
fbf49ea2
VS		 1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1021 msleep(5);
fbf49ea2
VS		 1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
ab7ad7f6
KP		 1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1029 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
ab7ad7f6
KP		 1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
58e10eb9 1041 *
9d0498a2 1042 */
575f7ab7 1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1044{
575f7ab7 1045 struct drm_device *dev = crtc->base.dev;
9d0498a2 1046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1048 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1051 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1052
1053 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
284637d9 1056 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1057 } else {
ab7ad7f6 1058 /* Wait for the display line to settle */
fbf49ea2 1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 }
79e53945
JB		 1062}
1063
b0ea7d37
DL		 1064/*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073{
1074 u32 bit;
1075
c36346e3 1076 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1077 switch (port->port) {
c36346e3
DL		 1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
eba905b2 1091 switch (port->port) {
c36346e3
DL		 1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 default:
1102 return true;
1103 }
b0ea7d37
DL		 1104 }
1105
1106 return I915_READ(SDEISR) & bit;
1107}
1108
b24e7179
JB		 1109static const char *state_string(bool enabled)
1110{
1111 return enabled ? "on" : "off";
1112}
1113
1114/* Only for pre-ILK configs */
55607e8a
DV		 1115void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
b24e7179
JB		 1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121
1122 reg = DPLL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1125 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1128}
b24e7179 1129
23538ef1
JN		 1130/* XXX: the dsi pll is shared between MIPI DSI ports */
1131static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132{
1133 u32 val;
1134 bool cur_state;
1135
a580516d 1136 mutex_lock(&dev_priv->sb_lock);
23538ef1 1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1138 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1139
1140 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1141 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1144}
1145#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
55607e8a 1148struct intel_shared_dpll *
e2b78267
DV		 1149intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150{
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
6e3c9717 1153 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1154 return NULL;
1155
6e3c9717 1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1157}
1158
040484af 1159/* For ILK+ */
55607e8a
DV		 1160void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1162 bool state)
040484af 1163{
040484af 1164 bool cur_state;
5358901f 1165 struct intel_dpll_hw_state hw_state;
040484af 1166
92b27b08 1167 if (WARN (!pll,
46edb027 1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1169 return;
ee7b9f93 1170
5358901f 1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1172 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
040484af 1175}
040484af
JB		 1176
1177static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179{
1180 int reg;
1181 u32 val;
1182 bool cur_state;
ad80a810
PZ		 1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184 pipe);
040484af 1185
affa9354
PZ		 1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
ad80a810 1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1189 val = I915_READ(reg);
ad80a810 1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1191 } else {
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1195 }
e2c719b7 1196 I915_STATE_WARN(cur_state != state,
040484af
JB		 1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1199}
1200#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205{
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209
d63fa0dc
PZ		 1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1213 I915_STATE_WARN(cur_state != state,
040484af
JB		 1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1216}
1217#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe)
1222{
1223 int reg;
1224 u32 val;
1225
1226 /* ILK FDI PLL is always enabled */
3d13ef2e 1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1228 return;
1229
bf507ef7 1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1231 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1232 return;
1233
040484af
JB		 1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
e2c719b7 1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1237}
1238
55607e8a
DV		 1239void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
040484af
JB		 1241{
1242 int reg;
1243 u32 val;
55607e8a 1244 bool cur_state;
040484af
JB		 1245
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
55607e8a 1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1249 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
040484af
JB		 1252}
1253
b680c37a
DV		 1254void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
ea0760cf 1256{
bedd4dba
JN		 1257 struct drm_device *dev = dev_priv->dev;
1258 int pp_reg;
ea0760cf
JB		 1259 u32 val;
1260 enum pipe panel_pipe = PIPE_A;
0de3b485 1261 bool locked = true;
ea0760cf 1262
bedd4dba
JN		 1263 if (WARN_ON(HAS_DDI(dev)))
1264 return;
1265
1266 if (HAS_PCH_SPLIT(dev)) {
1267 u32 port_sel;
1268
ea0760cf 1269 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279 panel_pipe = pipe;
ea0760cf
JB		 1280 } else {
1281 pp_reg = PP_CONTROL;
bedd4dba
JN		 1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
ea0760cf
JB		 1284 }
1285
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1289 locked = false;
1290
e2c719b7 1291 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1292 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1293 pipe_name(pipe));
ea0760cf
JB		 1294}
1295
93ce0ba6
JN		 1296static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1298{
1299 struct drm_device *dev = dev_priv->dev;
1300 bool cur_state;
1301
d9d82081 1302 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1304 else
5efb3e28 1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1306
e2c719b7 1307 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1310}
1311#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
b840d907
JB		 1314void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
b24e7179
JB		 1316{
1317 int reg;
1318 u32 val;
63d7bbe9 1319 bool cur_state;
702e7a56
PZ		 1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321 pipe);
b24e7179 1322
b6b5d049
VS		 1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1326 state = true;
1327
f458ebbc 1328 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1330 cur_state = false;
1331 } else {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1335 }
1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
63d7bbe9 1338 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1339 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1340}
1341
931872fc
CW		 1342static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
b24e7179
JB		 1344{
1345 int reg;
1346 u32 val;
931872fc 1347 bool cur_state;
b24e7179
JB		 1348
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
931872fc 1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1352 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1355}
1356
931872fc
CW		 1357#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
b24e7179
JB		 1360static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362{
653e1026 1363 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1364 int reg, i;
1365 u32 val;
1366 int cur_pipe;
1367
653e1026
VS		 1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
e2c719b7 1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1373 "plane %c assertion failure, should be disabled but not\n",
1374 plane_name(pipe));
19ec1358 1375 return;
28c05794 1376 }
19ec1358 1377
b24e7179 1378 /* Need to check both planes against the pipe */
055e393f 1379 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1380 reg = DSPCNTR(i);
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1387 }
1388}
1389
19332d7a
JB		 1390static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392{
20674eef 1393 struct drm_device *dev = dev_priv->dev;
1fe47785 1394 int reg, sprite;
19332d7a
JB		 1395 u32 val;
1396
7feb8b88 1397 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1398 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1399 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1403 }
1404 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1406 reg = SPCNTR(pipe, sprite);
20674eef 1407 val = I915_READ(reg);
e2c719b7 1408 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1410 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1411 }
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1413 reg = SPRCTL(pipe);
19332d7a 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
19332d7a 1420 val = I915_READ(reg);
e2c719b7 1421 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1423 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1424 }
1425}
1426
08c71e5e
VS		 1427static void assert_vblank_disabled(struct drm_crtc *crtc)
1428{
e2c719b7 1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1430 drm_crtc_vblank_put(crtc);
1431}
1432
89eff4be 1433static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1434{
1435 u32 val;
1436 bool enabled;
1437
e2c719b7 1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1439
92f2584a
JB		 1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1444}
1445
ab9412ba
DV		 1446static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe)
92f2584a
JB		 1448{
1449 int reg;
1450 u32 val;
1451 bool enabled;
1452
ab9412ba 1453 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1456 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458 pipe_name(pipe));
92f2584a
JB		 1459}
1460
4e634389
KP		 1461static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1463{
1464 if ((val & DP_PORT_EN) == 0)
1465 return false;
1466
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471 return false;
44f37d1f
CML		 1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474 return false;
f0575e92
KP		 1475 } else {
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 return false;
1478 }
1479 return true;
1480}
1481
1519b995
KP		 1482static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1484{
dc0fa718 1485 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1486 return false;
1487
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1490 return false;
44f37d1f
CML		 1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493 return false;
1519b995 1494 } else {
dc0fa718 1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1496 return false;
1497 }
1498 return true;
1499}
1500
1501static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1503{
1504 if ((val & LVDS_PORT_EN) == 0)
1505 return false;
1506
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509 return false;
1510 } else {
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 return false;
1513 }
1514 return true;
1515}
1516
1517static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519{
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1521 return false;
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
291906f1 1532static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1533 enum pipe pipe, int reg, u32 port_sel)
291906f1 1534{
47a05eca 1535 u32 val = I915_READ(reg);
e2c719b7 1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1538 reg, pipe_name(pipe));
de9a35ab 1539
e2c719b7 1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1541 && (val & DP_PIPEB_SELECT),
de9a35ab 1542 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1543}
1544
1545static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1547{
47a05eca 1548 u32 val = I915_READ(reg);
e2c719b7 1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1551 reg, pipe_name(pipe));
de9a35ab 1552
e2c719b7 1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1554 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1555 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1556}
1557
1558static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe)
1560{
1561 int reg;
1562 u32 val;
291906f1 1563
f0575e92
KP		 1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1567
1568 reg = PCH_ADPA;
1569 val = I915_READ(reg);
e2c719b7 1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1572 pipe_name(pipe));
291906f1
JB		 1573
1574 reg = PCH_LVDS;
1575 val = I915_READ(reg);
e2c719b7 1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1578 pipe_name(pipe));
291906f1 1579
e2debe91
PZ		 1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1583}
1584
40e9cf64
JB		 1585static void intel_init_dpio(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 if (!IS_VALLEYVIEW(dev))
1590 return;
1591
a09caddd
CML		 1592 /*
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596 */
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600 } else {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602 }
5382f5f3
JB		 1603}
1604
d288f65f 1605static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1606 const struct intel_crtc_state *pipe_config)
87442f73 1607{
426115cf
DV		 1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
d288f65f 1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1612
426115cf 1613 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1614
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1619 if (IS_MOBILE(dev_priv->dev))
426115cf 1620 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1621
426115cf
DV		 1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150);
1625
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
d288f65f 1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1630 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1631
1632 /* We do this three times for luck */
426115cf 1633 I915_WRITE(reg, dpll);
87442f73
DV		 1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642}
1643
d288f65f 1644static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1645 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1646{
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1651 u32 tmp;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
a580516d 1657 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1658
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
54433e91
VS		 1664 mutex_unlock(&dev_priv->sb_lock);
1665
9d556c99
CML		 1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
d288f65f 1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1673
1674 /* Check PLL is locked */
a11b0703 1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
a11b0703 1678 /* not sure when this should be written */
d288f65f 1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1680 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1681}
1682
1c4e0274
VS		 1683static int intel_num_dvo_pipes(struct drm_device *dev)
1684{
1685 struct intel_crtc *crtc;
1686 int count = 0;
1687
1688 for_each_intel_crtc(dev, crtc)
3538b9df 1689 count += crtc->base.state->active &&
409ee761 1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1691
1692 return count;
1693}
1694
66e3d5c0 1695static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1696{
66e3d5c0
DV		 1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
6e3c9717 1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1701
66e3d5c0 1702 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1703
63d7bbe9 1704 /* No really, not for ILK+ */
3d13ef2e 1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1706
1707 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1710
1c4e0274
VS		 1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713 /*
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1718 */
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722 }
66e3d5c0
DV		 1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1730 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
63d7bbe9
JB		 1739
1740 /* We do this three times for luck */
66e3d5c0 1741 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750}
1751
1752/**
50b44a44 1753 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1c4e0274 1761static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1762{
1c4e0274
VS		 1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
409ee761 1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1770 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
b6b5d049
VS		 1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
b8afb911 1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1786 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1787}
1788
f6071166
JB		 1789static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790{
b8afb911 1791 u32 val;
f6071166
JB		 1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
e5cbfbfb
ID		 1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
b8afb911 1800 val = DPLL_VGA_MODE_DIS;
f6071166 1801 if (pipe == PIPE_B)
60bfe44f 1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1805
1806}
1807
1808static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809{
d752048d 1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1811 u32 val;
1812
a11b0703
VS		 1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1815
a11b0703 1816 /* Set PLL en = 0 */
60bfe44f
VS		 1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
d752048d 1823
a580516d 1824 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
61407f6d
VS		 1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
a580516d 1842 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1843}
1844
e4607fcf 1845void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
89b667f8
JB		 1848{
1849 u32 port_mask;
00fc31b7 1850 int dpll_reg;
89b667f8 1851
e4607fcf
CML		 1852 switch (dport->port) {
1853 case PORT_B:
89b667f8 1854 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1855 dpll_reg = DPLL(0);
e4607fcf
CML		 1856 break;
1857 case PORT_C:
89b667f8 1858 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1859 dpll_reg = DPLL(0);
9b6de0a1 1860 expected_mask <<= 4;
00fc31b7
CML		 1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1865 break;
1866 default:
1867 BUG();
1868 }
89b667f8 1869
9b6de0a1
VS		 1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1873}
1874
b14b1055
DV		 1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
be19f0ff
CW		 1881 if (WARN_ON(pll == NULL))
1882 return;
1883
3e369b76 1884 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
92f2584a 1894/**
85b3894f 1895 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
85b3894f 1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1903{
3d13ef2e
DL		 1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1907
87a875bb 1908 if (WARN_ON(pll == NULL))
48da64a8
CW		 1909 return;
1910
3e369b76 1911 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1912 return;
ee7b9f93 1913
74dd6928 1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1915 pll->name, pll->active, pll->on,
e2b78267 1916 crtc->base.base.id);
92f2584a 1917
cdbd2316
DV		 1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
e9d6944e 1920 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1921 return;
1922 }
f4a091c7 1923 WARN_ON(pll->on);
ee7b9f93 1924
bd2bb1b9
PZ		 1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
46edb027 1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1928 pll->enable(dev_priv, pll);
ee7b9f93 1929 pll->on = true;
92f2584a
JB		 1930}
1931
f6daaec2 1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1933{
3d13ef2e
DL		 1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1937
92f2584a 1938 /* PCH only available on ILK+ */
80aa9312
JB		 1939 if (INTEL_INFO(dev)->gen < 5)
1940 return;
1941
eddfcbcd
ML		 1942 if (pll == NULL)
1943 return;
92f2584a 1944
eddfcbcd 1945 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1946 return;
7a419866 1947
46edb027
DV		 1948 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949 pll->name, pll->active, pll->on,
e2b78267 1950 crtc->base.base.id);
7a419866 1951
48da64a8 1952 if (WARN_ON(pll->active == 0)) {
e9d6944e 1953 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1954 return;
1955 }
1956
e9d6944e 1957 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1958 WARN_ON(!pll->on);
cdbd2316 1959 if (--pll->active)
7a419866 1960 return;
ee7b9f93 1961
46edb027 1962 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1963 pll->disable(dev_priv, pll);
ee7b9f93 1964 pll->on = false;
bd2bb1b9
PZ		 1965
1966 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1967}
1968
b8a4f404
PZ		 1969static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 enum pipe pipe)
040484af 1971{
23670b32 1972 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1975 uint32_t reg, val, pipeconf_val;
040484af
JB		 1976
1977 /* PCH only available on ILK+ */
55522f37 1978 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1979
1980 /* Make sure PCH DPLL is enabled */
e72f9fbf 1981 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1982 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1983
1984 /* FDI must be feeding us bits for PCH ports */
1985 assert_fdi_tx_enabled(dev_priv, pipe);
1986 assert_fdi_rx_enabled(dev_priv, pipe);
1987
23670b32
DV		 1988 if (HAS_PCH_CPT(dev)) {
1989 /* Workaround: Set the timing override bit before enabling the
1990 * pch transcoder. */
1991 reg = TRANS_CHICKEN2(pipe);
1992 val = I915_READ(reg);
1993 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994 I915_WRITE(reg, val);
59c859d6 1995 }
23670b32 1996
ab9412ba 1997 reg = PCH_TRANSCONF(pipe);
040484af 1998 val = I915_READ(reg);
5f7f726d 1999 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2000
2001 if (HAS_PCH_IBX(dev_priv->dev)) {
2002 /*
c5de7c6f
VS		 2003 * Make the BPC in transcoder be consistent with
2004 * that in pipeconf reg. For HDMI we must use 8bpc
2005 * here for both 8bpc and 12bpc.
e9bcff5c 2006 */
dfd07d72 2007 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2008 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009 val |= PIPECONF_8BPC;
2010 else
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2012 }
5f7f726d
PZ		 2013
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2016 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2019 else
2020 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2021 else
2022 val |= TRANS_PROGRESSIVE;
2023
040484af
JB		 2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2027}
2028
8fb033d7 2029static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2030 enum transcoder cpu_transcoder)
040484af 2031{
8fb033d7 2032 u32 val, pipeconf_val;
8fb033d7
PZ		 2033
2034 /* PCH only available on ILK+ */
55522f37 2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2036
8fb033d7 2037 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2040
223a6fdf
PZ		 2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045
25f3ef11 2046 val = TRANS_ENABLE;
937bb610 2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2048
9a76b1c6
PZ		 2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
a35f2679 2051 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2052 else
2053 val |= TRANS_PROGRESSIVE;
2054
ab9412ba
DV		 2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2057 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2058}
2059
b8a4f404
PZ		 2060static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
040484af 2062{
23670b32
DV		 2063 struct drm_device *dev = dev_priv->dev;
2064 uint32_t reg, val;
040484af
JB		 2065
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2069
291906f1
JB		 2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2072
ab9412ba 2073 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2080
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2087 }
040484af
JB		 2088}
2089
ab4d966c 2090static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2091{
8fb033d7
PZ		 2092 u32 val;
2093
ab9412ba 2094 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2095 val &= ~TRANS_ENABLE;
ab9412ba 2096 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2097 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2099 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2100
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2104 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2105}
2106
b24e7179 2107/**
309cfea8 2108 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2109 * @crtc: crtc responsible for the pipe
b24e7179 2110 *
0372264a 2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2113 */
e1fdc473 2114static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2115{
0372264a
PZ		 2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120 pipe);
1a240d4d 2121 enum pipe pch_transcoder;
b24e7179
JB		 2122 int reg;
2123 u32 val;
2124
9e2ee2dd
VS		 2125 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
58c6eaa2 2127 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2128 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2129 assert_sprites_disabled(dev_priv, pipe);
2130
681e5811 2131 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2132 pch_transcoder = TRANSCODER_A;
2133 else
2134 pch_transcoder = pipe;
2135
b24e7179
JB		 2136 /*
2137 * A pipe without a PLL won't actually be able to drive bits from
2138 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 * need the check.
2140 */
50360403 2141 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2143 assert_dsi_pll_enabled(dev_priv);
2144 else
2145 assert_pll_enabled(dev_priv, pipe);
040484af 2146 else {
6e3c9717 2147 if (crtc->config->has_pch_encoder) {
040484af 2148 /* if driving the PCH, we need FDI enabled */
cc391bbb 2149 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2150 assert_fdi_tx_pll_enabled(dev_priv,
2151 (enum pipe) cpu_transcoder);
040484af
JB		 2152 }
2153 /* FIXME: assert CPU port conditions for SNB+ */
2154 }
b24e7179 2155
702e7a56 2156 reg = PIPECONF(cpu_transcoder);
b24e7179 2157 val = I915_READ(reg);
7ad25d48 2158 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2159 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2161 return;
7ad25d48 2162 }
00d70b15
CW		 2163
2164 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2165 POSTING_READ(reg);
b24e7179
JB		 2166}
2167
2168/**
309cfea8 2169 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2170 * @crtc: crtc whose pipes is to be disabled
b24e7179 2171 *
575f7ab7
VS		 2172 * Disable the pipe of @crtc, making sure that various hardware
2173 * specific requirements are met, if applicable, e.g. plane
2174 * disabled, panel fitter off, etc.
b24e7179
JB		 2175 *
2176 * Will wait until the pipe has shut down before returning.
2177 */
575f7ab7 2178static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2179{
575f7ab7 2180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2181 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2182 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2183 int reg;
2184 u32 val;
2185
9e2ee2dd
VS		 2186 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
b24e7179
JB		 2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2193 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2194 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2195
702e7a56 2196 reg = PIPECONF(cpu_transcoder);
b24e7179 2197 val = I915_READ(reg);
00d70b15
CW		 2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
67adc644
VS		 2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
6e3c9717 2205 if (crtc->config->double_wide)
67adc644
VS		 2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2216}
2217
693db184
CW		 2218static bool need_vtd_wa(struct drm_device *dev)
2219{
2220#ifdef CONFIG_INTEL_IOMMU
2221 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222 return true;
2223#endif
2224 return false;
2225}
2226
50470bb0 2227unsigned int
6761dd31
TU		 2228intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229 uint64_t fb_format_modifier)
a57ce0b2 2230{
6761dd31
TU		 2231 unsigned int tile_height;
2232 uint32_t pixel_bytes;
a57ce0b2 2233
b5d0e9bf
DL		 2234 switch (fb_format_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2236 tile_height = 1;
2237 break;
2238 case I915_FORMAT_MOD_X_TILED:
2239 tile_height = IS_GEN2(dev) ? 16 : 8;
2240 break;
2241 case I915_FORMAT_MOD_Y_TILED:
2242 tile_height = 32;
2243 break;
2244 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2245 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246 switch (pixel_bytes) {
b5d0e9bf 2247 default:
6761dd31 2248 case 1:
b5d0e9bf
DL		 2249 tile_height = 64;
2250 break;
6761dd31
TU		 2251 case 2:
2252 case 4:
b5d0e9bf
DL		 2253 tile_height = 32;
2254 break;
6761dd31 2255 case 8:
b5d0e9bf
DL		 2256 tile_height = 16;
2257 break;
6761dd31 2258 case 16:
b5d0e9bf
DL		 2259 WARN_ONCE(1,
2260 "128-bit pixels are not supported for display!");
2261 tile_height = 16;
2262 break;
2263 }
2264 break;
2265 default:
2266 MISSING_CASE(fb_format_modifier);
2267 tile_height = 1;
2268 break;
2269 }
091df6cb 2270
6761dd31
TU		 2271 return tile_height;
2272}
2273
2274unsigned int
2275intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276 uint32_t pixel_format, uint64_t fb_format_modifier)
2277{
2278 return ALIGN(height, intel_tile_height(dev, pixel_format,
2279 fb_format_modifier));
a57ce0b2
JB		 2280}
2281
f64b98cd
TU		 2282static int
2283intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285{
50470bb0 2286 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2287 unsigned int tile_height, tile_pitch;
50470bb0 2288
f64b98cd
TU		 2289 *view = i915_ggtt_view_normal;
2290
50470bb0
TU		 2291 if (!plane_state)
2292 return 0;
2293
121920fa 2294 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2295 return 0;
2296
9abc4648 2297 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2298
2299 info->height = fb->height;
2300 info->pixel_format = fb->pixel_format;
2301 info->pitch = fb->pitches[0];
2302 info->fb_modifier = fb->modifier[0];
2303
84fe03f7
TU		 2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0]);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
f64b98cd
TU		 2311 return 0;
2312}
2313
4e9a86b6
VS		 2314static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315{
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
985b8bb4
VS		 2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
44c5905e 2324 return 0;
4e9a86b6
VS		 2325}
2326
127bd2ac 2327int
850c4cdc
TU		 2328intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
82bc3b2d 2330 const struct drm_plane_state *plane_state,
91af127f
JH		 2331 struct intel_engine_cs *pipelined,
2332 struct drm_i915_gem_request **pipelined_request)
6b95a207 2333{
850c4cdc 2334 struct drm_device *dev = fb->dev;
ce453d81 2335 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2337 struct i915_ggtt_view view;
6b95a207
KH		 2338 u32 alignment;
2339 int ret;
2340
ebcdd39e
MR		 2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
7b911adc
TU		 2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2345 alignment = intel_linear_alignment(dev_priv);
6b95a207 2346 break;
7b911adc 2347 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else {
2351 /* pin() will align the object as required by fence */
2352 alignment = 0;
2353 }
6b95a207 2354 break;
7b911adc 2355 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2356 case I915_FORMAT_MOD_Yf_TILED:
2357 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358 "Y tiling bo slipped through, driver bug!\n"))
2359 return -EINVAL;
2360 alignment = 1 * 1024 * 1024;
2361 break;
6b95a207 2362 default:
7b911adc
TU		 2363 MISSING_CASE(fb->modifier[0]);
2364 return -EINVAL;
6b95a207
KH		 2365 }
2366
f64b98cd
TU		 2367 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368 if (ret)
2369 return ret;
2370
693db184
CW		 2371 /* Note that the w/a also requires 64 PTE of padding following the
2372 * bo. We currently fill all unused PTE with the shadow page and so
2373 * we should always have valid PTE following the scanout preventing
2374 * the VT-d warning.
2375 */
2376 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377 alignment = 256 * 1024;
2378
d6dd6843
PZ		 2379 /*
2380 * Global gtt pte registers are special registers which actually forward
2381 * writes to a chunk of system memory. Which means that there is no risk
2382 * that the register values disappear as soon as we call
2383 * intel_runtime_pm_put(), so it is correct to wrap only the
2384 * pin/unpin/fence and not more.
2385 */
2386 intel_runtime_pm_get(dev_priv);
2387
ce453d81 2388 dev_priv->mm.interruptible = false;
e6617330 2389 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2390 pipelined_request, &view);
48b956c5 2391 if (ret)
ce453d81 2392 goto err_interruptible;
6b95a207
KH		 2393
2394 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395 * fence, whereas 965+ only requires a fence if using
2396 * framebuffer compression. For simplicity, we always install
2397 * a fence as the cost is not that onerous.
2398 */
06d98131 2399 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2400 if (ret == -EDEADLK) {
2401 /*
2402 * -EDEADLK means there are no free fences
2403 * no pending flips.
2404 *
2405 * This is propagated to atomic, but it uses
2406 * -EDEADLK to force a locking recovery, so
2407 * change the returned error to -EBUSY.
2408 */
2409 ret = -EBUSY;
2410 goto err_unpin;
2411 } else if (ret)
9a5a53b3 2412 goto err_unpin;
1690e1eb 2413
9a5a53b3 2414 i915_gem_object_pin_fence(obj);
6b95a207 2415
ce453d81 2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
6b95a207 2418 return 0;
48b956c5
CW		 2419
2420err_unpin:
f64b98cd 2421 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2422err_interruptible:
2423 dev_priv->mm.interruptible = true;
d6dd6843 2424 intel_runtime_pm_put(dev_priv);
48b956c5 2425 return ret;
6b95a207
KH		 2426}
2427
82bc3b2d
TU		 2428static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
1690e1eb 2430{
82bc3b2d 2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2432 struct i915_ggtt_view view;
2433 int ret;
82bc3b2d 2434
ebcdd39e
MR		 2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
f64b98cd
TU		 2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
1690e1eb 2440 i915_gem_object_unpin_fence(obj);
f64b98cd 2441 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2442}
2443
c2c75131
DV		 2444/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2446unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2447 int *x, int *y,
bc752862
CW		 2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
c2c75131 2451{
bc752862
CW		 2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
c2c75131 2454
bc752862
CW		 2455 tile_rows = *y / 8;
2456 *y %= 8;
c2c75131 2457
bc752862
CW		 2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
4e9a86b6 2463 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2464 unsigned int offset;
2465
2466 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2467 *y = (offset & alignment) / pitch;
2468 *x = ((offset & alignment) - *y * pitch) / cpp;
2469 return offset & ~alignment;
bc752862 2470 }
c2c75131
DV		 2471}
2472
b35d63fa 2473static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2474{
2475 switch (format) {
2476 case DISPPLANE_8BPP:
2477 return DRM_FORMAT_C8;
2478 case DISPPLANE_BGRX555:
2479 return DRM_FORMAT_XRGB1555;
2480 case DISPPLANE_BGRX565:
2481 return DRM_FORMAT_RGB565;
2482 default:
2483 case DISPPLANE_BGRX888:
2484 return DRM_FORMAT_XRGB8888;
2485 case DISPPLANE_RGBX888:
2486 return DRM_FORMAT_XBGR8888;
2487 case DISPPLANE_BGRX101010:
2488 return DRM_FORMAT_XRGB2101010;
2489 case DISPPLANE_RGBX101010:
2490 return DRM_FORMAT_XBGR2101010;
2491 }
2492}
2493
bc8d7dff
DL		 2494static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2495{
2496 switch (format) {
2497 case PLANE_CTL_FORMAT_RGB_565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case PLANE_CTL_FORMAT_XRGB_8888:
2501 if (rgb_order) {
2502 if (alpha)
2503 return DRM_FORMAT_ABGR8888;
2504 else
2505 return DRM_FORMAT_XBGR8888;
2506 } else {
2507 if (alpha)
2508 return DRM_FORMAT_ARGB8888;
2509 else
2510 return DRM_FORMAT_XRGB8888;
2511 }
2512 case PLANE_CTL_FORMAT_XRGB_2101010:
2513 if (rgb_order)
2514 return DRM_FORMAT_XBGR2101010;
2515 else
2516 return DRM_FORMAT_XRGB2101010;
2517 }
2518}
2519
5724dbd1 2520static bool
f6936e29
DV		 2521intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2522 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2523{
2524 struct drm_device *dev = crtc->base.dev;
2525 struct drm_i915_gem_object *obj = NULL;
2526 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2527 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2528 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2529 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2530 PAGE_SIZE);
2531
2532 size_aligned -= base_aligned;
46f297fb 2533
ff2652ea
CW		 2534 if (plane_config->size == 0)
2535 return false;
2536
f37b5c2b
DV		 2537 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538 base_aligned,
2539 base_aligned,
2540 size_aligned);
46f297fb 2541 if (!obj)
484b41dd 2542 return false;
46f297fb 2543
49af449b
DL		 2544 obj->tiling_mode = plane_config->tiling;
2545 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2546 obj->stride = fb->pitches[0];
46f297fb 2547
6bf129df
DL		 2548 mode_cmd.pixel_format = fb->pixel_format;
2549 mode_cmd.width = fb->width;
2550 mode_cmd.height = fb->height;
2551 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2552 mode_cmd.modifier[0] = fb->modifier[0];
2553 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2554
2555 mutex_lock(&dev->struct_mutex);
6bf129df 2556 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2557 &mode_cmd, obj)) {
46f297fb
JB		 2558 DRM_DEBUG_KMS("intel fb init failed\n");
2559 goto out_unref_obj;
2560 }
46f297fb 2561 mutex_unlock(&dev->struct_mutex);
484b41dd 2562
f6936e29 2563 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2564 return true;
46f297fb
JB		 2565
2566out_unref_obj:
2567 drm_gem_object_unreference(&obj->base);
2568 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2569 return false;
2570}
2571
afd65eb4
MR		 2572/* Update plane->state->fb to match plane->fb after driver-internal updates */
2573static void
2574update_state_fb(struct drm_plane *plane)
2575{
2576 if (plane->fb == plane->state->fb)
2577 return;
2578
2579 if (plane->state->fb)
2580 drm_framebuffer_unreference(plane->state->fb);
2581 plane->state->fb = plane->fb;
2582 if (plane->state->fb)
2583 drm_framebuffer_reference(plane->state->fb);
2584}
2585
5724dbd1 2586static void
f6936e29
DV		 2587intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2589{
2590 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2591 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2592 struct drm_crtc *c;
2593 struct intel_crtc *i;
2ff8fde1 2594 struct drm_i915_gem_object *obj;
88595ac9 2595 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2596 struct drm_plane_state *plane_state = primary->state;
88595ac9 2597 struct drm_framebuffer *fb;
484b41dd 2598
2d14030b 2599 if (!plane_config->fb)
484b41dd
JB		 2600 return;
2601
f6936e29 2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2603 fb = &plane_config->fb->base;
2604 goto valid_fb;
f55548b5 2605 }
484b41dd 2606
2d14030b 2607 kfree(plane_config->fb);
484b41dd
JB		 2608
2609 /*
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2612 */
70e1e0ec 2613 for_each_crtc(dev, c) {
484b41dd
JB		 2614 i = to_intel_crtc(c);
2615
2616 if (c == &intel_crtc->base)
2617 continue;
2618
2ff8fde1
MR		 2619 if (!i->active)
2620 continue;
2621
88595ac9
DV		 2622 fb = c->primary->fb;
2623 if (!fb)
484b41dd
JB		 2624 continue;
2625
88595ac9 2626 obj = intel_fb_obj(fb);
2ff8fde1 2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2628 drm_framebuffer_reference(fb);
2629 goto valid_fb;
484b41dd
JB		 2630 }
2631 }
88595ac9
DV		 2632
2633 return;
2634
2635valid_fb:
be5651f2
ML		 2636 plane_state->src_x = plane_state->src_y = 0;
2637 plane_state->src_w = fb->width << 16;
2638 plane_state->src_h = fb->height << 16;
2639
2640 plane_state->crtc_x = plane_state->src_y = 0;
2641 plane_state->crtc_w = fb->width;
2642 plane_state->crtc_h = fb->height;
2643
88595ac9
DV		 2644 obj = intel_fb_obj(fb);
2645 if (obj->tiling_mode != I915_TILING_NONE)
2646 dev_priv->preserve_bios_swizzle = true;
2647
be5651f2
ML		 2648 drm_framebuffer_reference(fb);
2649 primary->fb = primary->state->fb = fb;
36750f28 2650 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2651 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2652 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2653}
2654
29b9bde6
DV		 2655static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656 struct drm_framebuffer *fb,
2657 int x, int y)
81255565
JB		 2658{
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2662 struct drm_plane *primary = crtc->primary;
2663 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2664 struct drm_i915_gem_object *obj;
81255565 2665 int plane = intel_crtc->plane;
e506a0c6 2666 unsigned long linear_offset;
81255565 2667 u32 dspcntr;
f45651ba 2668 u32 reg = DSPCNTR(plane);
48404c1e 2669 int pixel_size;
f45651ba 2670
b70709a6 2671 if (!visible || !fb) {
fdd508a6
VS		 2672 I915_WRITE(reg, 0);
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2675 else
2676 I915_WRITE(DSPADDR(plane), 0);
2677 POSTING_READ(reg);
2678 return;
2679 }
2680
c9ba6fad
VS		 2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2683 return;
2684
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
f45651ba
VS		 2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
fdd508a6 2689 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2690
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2697 */
2698 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2701 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2708 }
81255565 2709
57779d06
VS		 2710 switch (fb->pixel_format) {
2711 case DRM_FORMAT_C8:
81255565
JB		 2712 dspcntr |= DISPPLANE_8BPP;
2713 break;
57779d06 2714 case DRM_FORMAT_XRGB1555:
57779d06 2715 dspcntr |= DISPPLANE_BGRX555;
81255565 2716 break;
57779d06
VS		 2717 case DRM_FORMAT_RGB565:
2718 dspcntr |= DISPPLANE_BGRX565;
2719 break;
2720 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX888;
2722 break;
2723 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2724 dspcntr |= DISPPLANE_RGBX888;
2725 break;
2726 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2727 dspcntr |= DISPPLANE_BGRX101010;
2728 break;
2729 case DRM_FORMAT_XBGR2101010:
57779d06 2730 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2731 break;
2732 default:
baba133a 2733 BUG();
81255565 2734 }
57779d06 2735
f45651ba
VS		 2736 if (INTEL_INFO(dev)->gen >= 4 &&
2737 obj->tiling_mode != I915_TILING_NONE)
2738 dspcntr |= DISPPLANE_TILED;
81255565 2739
de1aa629
VS		 2740 if (IS_G4X(dev))
2741 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
b9897127 2743 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2744
c2c75131
DV		 2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2747 intel_gen4_compute_page_offset(dev_priv,
2748 &x, &y, obj->tiling_mode,
b9897127 2749 pixel_size,
bc752862 2750 fb->pitches[0]);
c2c75131
DV		 2751 linear_offset -= intel_crtc->dspaddr_offset;
2752 } else {
e506a0c6 2753 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2754 }
e506a0c6 2755
8e7d688b 2756 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2757 dspcntr |= DISPPLANE_ROTATE_180;
2758
6e3c9717
ACO		 2759 x += (intel_crtc->config->pipe_src_w - 1);
2760 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2761
2762 /* Finding the last pixel of the last line of the display
2763 data and adding to linear_offset*/
2764 linear_offset +=
6e3c9717
ACO		 2765 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2767 }
2768
2769 I915_WRITE(reg, dspcntr);
2770
01f2c773 2771 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2772 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2773 I915_WRITE(DSPSURF(plane),
2774 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2776 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2777 } else
f343c5f6 2778 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2779 POSTING_READ(reg);
17638cd6
JB		 2780}
2781
29b9bde6
DV		 2782static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783 struct drm_framebuffer *fb,
2784 int x, int y)
17638cd6
JB		 2785{
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2789 struct drm_plane *primary = crtc->primary;
2790 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2791 struct drm_i915_gem_object *obj;
17638cd6 2792 int plane = intel_crtc->plane;
e506a0c6 2793 unsigned long linear_offset;
17638cd6 2794 u32 dspcntr;
f45651ba 2795 u32 reg = DSPCNTR(plane);
48404c1e 2796 int pixel_size;
f45651ba 2797
b70709a6 2798 if (!visible || !fb) {
fdd508a6
VS		 2799 I915_WRITE(reg, 0);
2800 I915_WRITE(DSPSURF(plane), 0);
2801 POSTING_READ(reg);
2802 return;
2803 }
2804
c9ba6fad
VS		 2805 obj = intel_fb_obj(fb);
2806 if (WARN_ON(obj == NULL))
2807 return;
2808
2809 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
f45651ba
VS		 2811 dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
fdd508a6 2813 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2814
2815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2817
57779d06
VS		 2818 switch (fb->pixel_format) {
2819 case DRM_FORMAT_C8:
17638cd6
JB		 2820 dspcntr |= DISPPLANE_8BPP;
2821 break;
57779d06
VS		 2822 case DRM_FORMAT_RGB565:
2823 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2824 break;
57779d06 2825 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_BGRX888;
2827 break;
2828 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2829 dspcntr |= DISPPLANE_RGBX888;
2830 break;
2831 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2832 dspcntr |= DISPPLANE_BGRX101010;
2833 break;
2834 case DRM_FORMAT_XBGR2101010:
57779d06 2835 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2836 break;
2837 default:
baba133a 2838 BUG();
17638cd6
JB		 2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
17638cd6 2843
f45651ba 2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2846
b9897127 2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2848 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2849 intel_gen4_compute_page_offset(dev_priv,
2850 &x, &y, obj->tiling_mode,
b9897127 2851 pixel_size,
bc752862 2852 fb->pitches[0]);
c2c75131 2853 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2854 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2855 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2858 x += (intel_crtc->config->pipe_src_w - 1);
2859 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2860
2861 /* Finding the last pixel of the last line of the display
2862 data and adding to linear_offset*/
2863 linear_offset +=
6e3c9717
ACO		 2864 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2866 }
2867 }
2868
2869 I915_WRITE(reg, dspcntr);
17638cd6 2870
01f2c773 2871 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2872 I915_WRITE(DSPSURF(plane),
2873 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2874 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2875 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876 } else {
2877 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879 }
17638cd6 2880 POSTING_READ(reg);
17638cd6
JB		 2881}
2882
b321803d
DL		 2883u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884 uint32_t pixel_format)
2885{
2886 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888 /*
2889 * The stride is either expressed as a multiple of 64 bytes
2890 * chunks for linear buffers or in number of tiles for tiled
2891 * buffers.
2892 */
2893 switch (fb_modifier) {
2894 case DRM_FORMAT_MOD_NONE:
2895 return 64;
2896 case I915_FORMAT_MOD_X_TILED:
2897 if (INTEL_INFO(dev)->gen == 2)
2898 return 128;
2899 return 512;
2900 case I915_FORMAT_MOD_Y_TILED:
2901 /* No need to check for old gens and Y tiling since this is
2902 * about the display engine and those will be blocked before
2903 * we get here.
2904 */
2905 return 128;
2906 case I915_FORMAT_MOD_Yf_TILED:
2907 if (bits_per_pixel == 8)
2908 return 64;
2909 else
2910 return 128;
2911 default:
2912 MISSING_CASE(fb_modifier);
2913 return 64;
2914 }
2915}
2916
121920fa
TU		 2917unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2918 struct drm_i915_gem_object *obj)
2919{
9abc4648 2920 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2921
2922 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2923 view = &i915_ggtt_view_rotated;
121920fa
TU		 2924
2925 return i915_gem_obj_ggtt_offset_view(obj, view);
2926}
2927
e435d6e5
ML		 2928static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2929{
2930 struct drm_device *dev = intel_crtc->base.dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2934 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2935 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2936 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2937 intel_crtc->base.base.id, intel_crtc->pipe, id);
2938}
2939
a1b2278e
CK		 2940/*
2941 * This function detaches (aka. unbinds) unused scalers in hardware
2942 */
0583236e 2943static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2944{
a1b2278e
CK		 2945 struct intel_crtc_scaler_state *scaler_state;
2946 int i;
2947
a1b2278e
CK		 2948 scaler_state = &intel_crtc->config->scaler_state;
2949
2950 /* loop through and disable scalers that aren't in use */
2951 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2952 if (!scaler_state->scalers[i].in_use)
2953 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2954 }
2955}
2956
6156a456 2957u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2958{
6156a456 2959 switch (pixel_format) {
d161cf7a 2960 case DRM_FORMAT_C8:
c34ce3d1 2961 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2962 case DRM_FORMAT_RGB565:
c34ce3d1 2963 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2964 case DRM_FORMAT_XBGR8888:
c34ce3d1 2965 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2966 case DRM_FORMAT_XRGB8888:
c34ce3d1 2967 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2968 /*
2969 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2970 * to be already pre-multiplied. We need to add a knob (or a different
2971 * DRM_FORMAT) for user-space to configure that.
2972 */
f75fb42a 2973 case DRM_FORMAT_ABGR8888:
c34ce3d1 2974 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2976 case DRM_FORMAT_ARGB8888:
c34ce3d1 2977 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2979 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2980 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2981 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2982 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2983 case DRM_FORMAT_YUYV:
c34ce3d1 2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2985 case DRM_FORMAT_YVYU:
c34ce3d1 2986 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2987 case DRM_FORMAT_UYVY:
c34ce3d1 2988 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2989 case DRM_FORMAT_VYUY:
c34ce3d1 2990 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2991 default:
4249eeef 2992 MISSING_CASE(pixel_format);
70d21f0e 2993 }
8cfcba41 2994
c34ce3d1 2995 return 0;
6156a456 2996}
70d21f0e 2997
6156a456
CK		 2998u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2999{
6156a456 3000 switch (fb_modifier) {
30af77c4 3001 case DRM_FORMAT_MOD_NONE:
70d21f0e 3002 break;
30af77c4 3003 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3004 return PLANE_CTL_TILED_X;
b321803d 3005 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3006 return PLANE_CTL_TILED_Y;
b321803d 3007 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3008 return PLANE_CTL_TILED_YF;
70d21f0e 3009 default:
6156a456 3010 MISSING_CASE(fb_modifier);
70d21f0e 3011 }
8cfcba41 3012
c34ce3d1 3013 return 0;
6156a456 3014}
70d21f0e 3015
6156a456
CK		 3016u32 skl_plane_ctl_rotation(unsigned int rotation)
3017{
3b7a5119 3018 switch (rotation) {
6156a456
CK		 3019 case BIT(DRM_ROTATE_0):
3020 break;
1e8df167
SJ		 3021 /*
3022 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3023 * while i915 HW rotation is clockwise, thats why this swapping.
3024 */
3b7a5119 3025 case BIT(DRM_ROTATE_90):
1e8df167 3026 return PLANE_CTL_ROTATE_270;
3b7a5119 3027 case BIT(DRM_ROTATE_180):
c34ce3d1 3028 return PLANE_CTL_ROTATE_180;
3b7a5119 3029 case BIT(DRM_ROTATE_270):
1e8df167 3030 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3031 default:
3032 MISSING_CASE(rotation);
3033 }
3034
c34ce3d1 3035 return 0;
6156a456
CK		 3036}
3037
3038static void skylake_update_primary_plane(struct drm_crtc *crtc,
3039 struct drm_framebuffer *fb,
3040 int x, int y)
3041{
3042 struct drm_device *dev = crtc->dev;
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3045 struct drm_plane *plane = crtc->primary;
3046 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3047 struct drm_i915_gem_object *obj;
3048 int pipe = intel_crtc->pipe;
3049 u32 plane_ctl, stride_div, stride;
3050 u32 tile_height, plane_offset, plane_size;
3051 unsigned int rotation;
3052 int x_offset, y_offset;
3053 unsigned long surf_addr;
6156a456
CK		 3054 struct intel_crtc_state *crtc_state = intel_crtc->config;
3055 struct intel_plane_state *plane_state;
3056 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3057 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3058 int scaler_id = -1;
3059
6156a456
CK		 3060 plane_state = to_intel_plane_state(plane->state);
3061
b70709a6 3062 if (!visible || !fb) {
6156a456
CK		 3063 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3064 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3065 POSTING_READ(PLANE_CTL(pipe, 0));
3066 return;
3b7a5119 3067 }
70d21f0e 3068
6156a456
CK		 3069 plane_ctl = PLANE_CTL_ENABLE |
3070 PLANE_CTL_PIPE_GAMMA_ENABLE |
3071 PLANE_CTL_PIPE_CSC_ENABLE;
3072
3073 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3074 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3075 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3076
3077 rotation = plane->state->rotation;
3078 plane_ctl |= skl_plane_ctl_rotation(rotation);
3079
b321803d
DL		 3080 obj = intel_fb_obj(fb);
3081 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3082 fb->pixel_format);
3b7a5119
SJ		 3083 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3084
6156a456
CK		 3085 /*
3086 * FIXME: intel_plane_state->src, dst aren't set when transitional
3087 * update_plane helpers are called from legacy paths.
3088 * Once full atomic crtc is available, below check can be avoided.
3089 */
3090 if (drm_rect_width(&plane_state->src)) {
3091 scaler_id = plane_state->scaler_id;
3092 src_x = plane_state->src.x1 >> 16;
3093 src_y = plane_state->src.y1 >> 16;
3094 src_w = drm_rect_width(&plane_state->src) >> 16;
3095 src_h = drm_rect_height(&plane_state->src) >> 16;
3096 dst_x = plane_state->dst.x1;
3097 dst_y = plane_state->dst.y1;
3098 dst_w = drm_rect_width(&plane_state->dst);
3099 dst_h = drm_rect_height(&plane_state->dst);
3100
3101 WARN_ON(x != src_x || y != src_y);
3102 } else {
3103 src_w = intel_crtc->config->pipe_src_w;
3104 src_h = intel_crtc->config->pipe_src_h;
3105 }
3106
3b7a5119
SJ		 3107 if (intel_rotation_90_or_270(rotation)) {
3108 /* stride = Surface height in tiles */
2614f17d 3109 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3110 fb->modifier[0]);
3111 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3112 x_offset = stride * tile_height - y - src_h;
3b7a5119 3113 y_offset = x;
6156a456 3114 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3115 } else {
3116 stride = fb->pitches[0] / stride_div;
3117 x_offset = x;
3118 y_offset = y;
6156a456 3119 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3120 }
3121 plane_offset = y_offset << 16 | x_offset;
b321803d 3122
70d21f0e 3123 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3124 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3125 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3126 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3127
3128 if (scaler_id >= 0) {
3129 uint32_t ps_ctrl = 0;
3130
3131 WARN_ON(!dst_w || !dst_h);
3132 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3133 crtc_state->scaler_state.scalers[scaler_id].mode;
3134 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3135 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3136 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3137 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3138 I915_WRITE(PLANE_POS(pipe, 0), 0);
3139 } else {
3140 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3141 }
3142
121920fa 3143 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3144
3145 POSTING_READ(PLANE_SURF(pipe, 0));
3146}
3147
17638cd6
JB		 3148/* Assume fb object is pinned & idle & fenced and just update base pointers */
3149static int
3150intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3151 int x, int y, enum mode_set_atomic state)
3152{
3153 struct drm_device *dev = crtc->dev;
3154 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3155
ff2a3117 3156 if (dev_priv->fbc.disable_fbc)
7733b49b 3157 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3158
29b9bde6
DV		 3159 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3160
3161 return 0;
81255565
JB		 3162}
3163
7514747d 3164static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3165{
96a02917
VS		 3166 struct drm_crtc *crtc;
3167
70e1e0ec 3168 for_each_crtc(dev, crtc) {
96a02917
VS		 3169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3170 enum plane plane = intel_crtc->plane;
3171
3172 intel_prepare_page_flip(dev, plane);
3173 intel_finish_page_flip_plane(dev, plane);
3174 }
7514747d
VS		 3175}
3176
3177static void intel_update_primary_planes(struct drm_device *dev)
3178{
3179 struct drm_i915_private *dev_priv = dev->dev_private;
3180 struct drm_crtc *crtc;
96a02917 3181
70e1e0ec 3182 for_each_crtc(dev, crtc) {
96a02917
VS		 3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184
51fd371b 3185 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3186 /*
3187 * FIXME: Once we have proper support for primary planes (and
3188 * disabling them without disabling the entire crtc) allow again
66e514c1 3189 * a NULL crtc->primary->fb.
947fdaad 3190 */
f4510a27 3191 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3192 dev_priv->display.update_primary_plane(crtc,
66e514c1 3193 crtc->primary->fb,
262ca2b0
MR		 3194 crtc->x,
3195 crtc->y);
51fd371b 3196 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3197 }
3198}
3199
7514747d
VS		 3200void intel_prepare_reset(struct drm_device *dev)
3201{
3202 /* no reset support for gen2 */
3203 if (IS_GEN2(dev))
3204 return;
3205
3206 /* reset doesn't touch the display */
3207 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3208 return;
3209
3210 drm_modeset_lock_all(dev);
f98ce92f
VS		 3211 /*
3212 * Disabling the crtcs gracefully seems nicer. Also the
3213 * g33 docs say we should at least disable all the planes.
3214 */
6b72d486 3215 intel_display_suspend(dev);
7514747d
VS		 3216}
3217
3218void intel_finish_reset(struct drm_device *dev)
3219{
3220 struct drm_i915_private *dev_priv = to_i915(dev);
3221
3222 /*
3223 * Flips in the rings will be nuked by the reset,
3224 * so complete all pending flips so that user space
3225 * will get its events and not get stuck.
3226 */
3227 intel_complete_page_flips(dev);
3228
3229 /* no reset support for gen2 */
3230 if (IS_GEN2(dev))
3231 return;
3232
3233 /* reset doesn't touch the display */
3234 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3235 /*
3236 * Flips in the rings have been nuked by the reset,
3237 * so update the base address of all primary
3238 * planes to the the last fb to make sure we're
3239 * showing the correct fb after a reset.
3240 */
3241 intel_update_primary_planes(dev);
3242 return;
3243 }
3244
3245 /*
3246 * The display has been reset as well,
3247 * so need a full re-initialization.
3248 */
3249 intel_runtime_pm_disable_interrupts(dev_priv);
3250 intel_runtime_pm_enable_interrupts(dev_priv);
3251
3252 intel_modeset_init_hw(dev);
3253
3254 spin_lock_irq(&dev_priv->irq_lock);
3255 if (dev_priv->display.hpd_irq_setup)
3256 dev_priv->display.hpd_irq_setup(dev);
3257 spin_unlock_irq(&dev_priv->irq_lock);
3258
043e9bda 3259 intel_display_resume(dev);
7514747d
VS		 3260
3261 intel_hpd_init(dev_priv);
3262
3263 drm_modeset_unlock_all(dev);
3264}
3265
2e2f351d 3266static void
14667a4b
CW		 3267intel_finish_fb(struct drm_framebuffer *old_fb)
3268{
2ff8fde1 3269 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3270 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3271 bool was_interruptible = dev_priv->mm.interruptible;
3272 int ret;
3273
14667a4b
CW		 3274 /* Big Hammer, we also need to ensure that any pending
3275 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3276 * current scanout is retired before unpinning the old
2e2f351d
CW		 3277 * framebuffer. Note that we rely on userspace rendering
3278 * into the buffer attached to the pipe they are waiting
3279 * on. If not, userspace generates a GPU hang with IPEHR
3280 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3281 *
3282 * This should only fail upon a hung GPU, in which case we
3283 * can safely continue.
3284 */
3285 dev_priv->mm.interruptible = false;
2e2f351d 3286 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3287 dev_priv->mm.interruptible = was_interruptible;
3288
2e2f351d 3289 WARN_ON(ret);
14667a4b
CW		 3290}
3291
7d5e3799
CW		 3292static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3293{
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3297 bool pending;
3298
3299 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3300 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3301 return false;
3302
5e2d7afc 3303 spin_lock_irq(&dev->event_lock);
7d5e3799 3304 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3305 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3306
3307 return pending;
3308}
3309
e30e8f75
GP		 3310static void intel_update_pipe_size(struct intel_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->base.dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 const struct drm_display_mode *adjusted_mode;
3315
3316 if (!i915.fastboot)
3317 return;
3318
3319 /*
3320 * Update pipe size and adjust fitter if needed: the reason for this is
3321 * that in compute_mode_changes we check the native mode (not the pfit
3322 * mode) to see if we can flip rather than do a full mode set. In the
3323 * fastboot case, we'll flip, but if we don't update the pipesrc and
3324 * pfit state, we'll end up with a big fb scanned out into the wrong
3325 * sized surface.
3326 *
3327 * To fix this properly, we need to hoist the checks up into
3328 * compute_mode_changes (or above), check the actual pfit state and
3329 * whether the platform allows pfit disable with pipe active, and only
3330 * then update the pipesrc and pfit state, even on the flip path.
3331 */
3332
6e3c9717 3333 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3334
3335 I915_WRITE(PIPESRC(crtc->pipe),
3336 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3337 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3338 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3339 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3340 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3341 I915_WRITE(PF_CTL(crtc->pipe), 0);
3342 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3344 }
6e3c9717
ACO		 3345 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3346 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3347}
3348
5e84e1a4
ZW		 3349static void intel_fdi_normal_train(struct drm_crtc *crtc)
3350{
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 int pipe = intel_crtc->pipe;
3355 u32 reg, temp;
3356
3357 /* enable normal train */
3358 reg = FDI_TX_CTL(pipe);
3359 temp = I915_READ(reg);
61e499bf 3360 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3361 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3366 }
5e84e1a4
ZW		 3367 I915_WRITE(reg, temp);
3368
3369 reg = FDI_RX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 if (HAS_PCH_CPT(dev)) {
3372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374 } else {
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_NONE;
3377 }
3378 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380 /* wait one idle pattern time */
3381 POSTING_READ(reg);
3382 udelay(1000);
357555c0
JB		 3383
3384 /* IVB wants error correction enabled */
3385 if (IS_IVYBRIDGE(dev))
3386 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3388}
3389
8db9d77b
ZW		 3390/* The FDI link training functions for ILK/Ibexpeak. */
3391static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392{
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
5eddb70b 3397 u32 reg, temp, tries;
8db9d77b 3398
1c8562f6 3399 /* FDI needs bits from pipe first */
0fc932b8 3400 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3401
e1a44743
AJ		 3402 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3403 for train result */
5eddb70b
CW		 3404 reg = FDI_RX_IMR(pipe);
3405 temp = I915_READ(reg);
e1a44743
AJ		 3406 temp &= ~FDI_RX_SYMBOL_LOCK;
3407 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3408 I915_WRITE(reg, temp);
3409 I915_READ(reg);
e1a44743
AJ		 3410 udelay(150);
3411
8db9d77b 3412 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3413 reg = FDI_TX_CTL(pipe);
3414 temp = I915_READ(reg);
627eb5a3 3415 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3416 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3419 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3420
5eddb70b
CW		 3421 reg = FDI_RX_CTL(pipe);
3422 temp = I915_READ(reg);
8db9d77b
ZW		 3423 temp &= ~FDI_LINK_TRAIN_NONE;
3424 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3425 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3426
3427 POSTING_READ(reg);
8db9d77b
ZW		 3428 udelay(150);
3429
5b2adf89 3430 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3433 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3434
5eddb70b 3435 reg = FDI_RX_IIR(pipe);
e1a44743 3436 for (tries = 0; tries < 5; tries++) {
5eddb70b 3437 temp = I915_READ(reg);
8db9d77b
ZW		 3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439
3440 if ((temp & FDI_RX_BIT_LOCK)) {
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3442 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3443 break;
3444 }
8db9d77b 3445 }
e1a44743 3446 if (tries == 5)
5eddb70b 3447 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3448
3449 /* Train 2 */
5eddb70b
CW		 3450 reg = FDI_TX_CTL(pipe);
3451 temp = I915_READ(reg);
8db9d77b
ZW		 3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3454 I915_WRITE(reg, temp);
8db9d77b 3455
5eddb70b
CW		 3456 reg = FDI_RX_CTL(pipe);
3457 temp = I915_READ(reg);
8db9d77b
ZW		 3458 temp &= ~FDI_LINK_TRAIN_NONE;
3459 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3460 I915_WRITE(reg, temp);
8db9d77b 3461
5eddb70b
CW		 3462 POSTING_READ(reg);
3463 udelay(150);
8db9d77b 3464
5eddb70b 3465 reg = FDI_RX_IIR(pipe);
e1a44743 3466 for (tries = 0; tries < 5; tries++) {
5eddb70b 3467 temp = I915_READ(reg);
8db9d77b
ZW		 3468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3471 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3472 DRM_DEBUG_KMS("FDI train 2 done.\n");
3473 break;
3474 }
8db9d77b 3475 }
e1a44743 3476 if (tries == 5)
5eddb70b 3477 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3478
3479 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3480
8db9d77b
ZW		 3481}
3482
0206e353 3483static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3484 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3485 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3486 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3487 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3488};
3489
3490/* The FDI link training functions for SNB/Cougarpoint. */
3491static void gen6_fdi_link_train(struct drm_crtc *crtc)
3492{
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496 int pipe = intel_crtc->pipe;
fa37d39e 3497 u32 reg, temp, i, retry;
8db9d77b 3498
e1a44743
AJ		 3499 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3500 for train result */
5eddb70b
CW		 3501 reg = FDI_RX_IMR(pipe);
3502 temp = I915_READ(reg);
e1a44743
AJ		 3503 temp &= ~FDI_RX_SYMBOL_LOCK;
3504 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3505 I915_WRITE(reg, temp);
3506
3507 POSTING_READ(reg);
e1a44743
AJ		 3508 udelay(150);
3509
8db9d77b 3510 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3511 reg = FDI_TX_CTL(pipe);
3512 temp = I915_READ(reg);
627eb5a3 3513 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3514 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3515 temp &= ~FDI_LINK_TRAIN_NONE;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1;
3517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518 /* SNB-B */
3519 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3520 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3521
d74cf324
DV		 3522 I915_WRITE(FDI_RX_MISC(pipe),
3523 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3524
5eddb70b
CW		 3525 reg = FDI_RX_CTL(pipe);
3526 temp = I915_READ(reg);
8db9d77b
ZW		 3527 if (HAS_PCH_CPT(dev)) {
3528 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3530 } else {
3531 temp &= ~FDI_LINK_TRAIN_NONE;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1;
3533 }
5eddb70b
CW		 3534 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3535
3536 POSTING_READ(reg);
8db9d77b
ZW		 3537 udelay(150);
3538
0206e353 3539 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
8db9d77b
ZW		 3542 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3543 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3544 I915_WRITE(reg, temp);
3545
3546 POSTING_READ(reg);
8db9d77b
ZW		 3547 udelay(500);
3548
fa37d39e
SP		 3549 for (retry = 0; retry < 5; retry++) {
3550 reg = FDI_RX_IIR(pipe);
3551 temp = I915_READ(reg);
3552 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3553 if (temp & FDI_RX_BIT_LOCK) {
3554 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3555 DRM_DEBUG_KMS("FDI train 1 done.\n");
3556 break;
3557 }
3558 udelay(50);
8db9d77b 3559 }
fa37d39e
SP		 3560 if (retry < 5)
3561 break;
8db9d77b
ZW		 3562 }
3563 if (i == 4)
5eddb70b 3564 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3565
3566 /* Train 2 */
5eddb70b
CW		 3567 reg = FDI_TX_CTL(pipe);
3568 temp = I915_READ(reg);
8db9d77b
ZW		 3569 temp &= ~FDI_LINK_TRAIN_NONE;
3570 temp |= FDI_LINK_TRAIN_PATTERN_2;
3571 if (IS_GEN6(dev)) {
3572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3573 /* SNB-B */
3574 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3575 }
5eddb70b 3576 I915_WRITE(reg, temp);
8db9d77b 3577
5eddb70b
CW		 3578 reg = FDI_RX_CTL(pipe);
3579 temp = I915_READ(reg);
8db9d77b
ZW		 3580 if (HAS_PCH_CPT(dev)) {
3581 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3583 } else {
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 }
5eddb70b
CW		 3587 I915_WRITE(reg, temp);
3588
3589 POSTING_READ(reg);
8db9d77b
ZW		 3590 udelay(150);
3591
0206e353 3592 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3593 reg = FDI_TX_CTL(pipe);
3594 temp = I915_READ(reg);
8db9d77b
ZW		 3595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3596 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3597 I915_WRITE(reg, temp);
3598
3599 POSTING_READ(reg);
8db9d77b
ZW		 3600 udelay(500);
3601
fa37d39e
SP		 3602 for (retry = 0; retry < 5; retry++) {
3603 reg = FDI_RX_IIR(pipe);
3604 temp = I915_READ(reg);
3605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3606 if (temp & FDI_RX_SYMBOL_LOCK) {
3607 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3608 DRM_DEBUG_KMS("FDI train 2 done.\n");
3609 break;
3610 }
3611 udelay(50);
8db9d77b 3612 }
fa37d39e
SP		 3613 if (retry < 5)
3614 break;
8db9d77b
ZW		 3615 }
3616 if (i == 4)
5eddb70b 3617 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3618
3619 DRM_DEBUG_KMS("FDI train done.\n");
3620}
3621
357555c0
JB		 3622/* Manual link training for Ivy Bridge A0 parts */
3623static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3624{
3625 struct drm_device *dev = crtc->dev;
3626 struct drm_i915_private *dev_priv = dev->dev_private;
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 int pipe = intel_crtc->pipe;
139ccd3f 3629 u32 reg, temp, i, j;
357555c0
JB		 3630
3631 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3632 for train result */
3633 reg = FDI_RX_IMR(pipe);
3634 temp = I915_READ(reg);
3635 temp &= ~FDI_RX_SYMBOL_LOCK;
3636 temp &= ~FDI_RX_BIT_LOCK;
3637 I915_WRITE(reg, temp);
3638
3639 POSTING_READ(reg);
3640 udelay(150);
3641
01a415fd
DV		 3642 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3643 I915_READ(FDI_RX_IIR(pipe)));
3644
139ccd3f
JB		 3645 /* Try each vswing and preemphasis setting twice before moving on */
3646 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3647 /* disable first in case we need to retry */
3648 reg = FDI_TX_CTL(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3651 temp &= ~FDI_TX_ENABLE;
3652 I915_WRITE(reg, temp);
357555c0 3653
139ccd3f
JB		 3654 reg = FDI_RX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~FDI_LINK_TRAIN_AUTO;
3657 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3658 temp &= ~FDI_RX_ENABLE;
3659 I915_WRITE(reg, temp);
357555c0 3660
139ccd3f 3661 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3662 reg = FDI_TX_CTL(pipe);
3663 temp = I915_READ(reg);
139ccd3f 3664 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3665 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3668 temp |= snb_b_fdi_train_param[j/2];
3669 temp |= FDI_COMPOSITE_SYNC;
3670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3671
139ccd3f
JB		 3672 I915_WRITE(FDI_RX_MISC(pipe),
3673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3674
139ccd3f 3675 reg = FDI_RX_CTL(pipe);
357555c0 3676 temp = I915_READ(reg);
139ccd3f
JB		 3677 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3678 temp |= FDI_COMPOSITE_SYNC;
3679 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3680
139ccd3f
JB		 3681 POSTING_READ(reg);
3682 udelay(1); /* should be 0.5us */
357555c0 3683
139ccd3f
JB		 3684 for (i = 0; i < 4; i++) {
3685 reg = FDI_RX_IIR(pipe);
3686 temp = I915_READ(reg);
3687 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3688
139ccd3f
JB		 3689 if (temp & FDI_RX_BIT_LOCK ||
3690 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3691 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3692 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3693 i);
3694 break;
3695 }
3696 udelay(1); /* should be 0.5us */
3697 }
3698 if (i == 4) {
3699 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3700 continue;
3701 }
357555c0 3702
139ccd3f 3703 /* Train 2 */
357555c0
JB		 3704 reg = FDI_TX_CTL(pipe);
3705 temp = I915_READ(reg);
139ccd3f
JB		 3706 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3707 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3708 I915_WRITE(reg, temp);
3709
3710 reg = FDI_RX_CTL(pipe);
3711 temp = I915_READ(reg);
3712 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3713 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3714 I915_WRITE(reg, temp);
3715
3716 POSTING_READ(reg);
139ccd3f 3717 udelay(2); /* should be 1.5us */
357555c0 3718
139ccd3f
JB		 3719 for (i = 0; i < 4; i++) {
3720 reg = FDI_RX_IIR(pipe);
3721 temp = I915_READ(reg);
3722 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3723
139ccd3f
JB		 3724 if (temp & FDI_RX_SYMBOL_LOCK ||
3725 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3726 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3727 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3728 i);
3729 goto train_done;
3730 }
3731 udelay(2); /* should be 1.5us */
357555c0 3732 }
139ccd3f
JB		 3733 if (i == 4)
3734 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3735 }
357555c0 3736
139ccd3f 3737train_done:
357555c0
JB		 3738 DRM_DEBUG_KMS("FDI train done.\n");
3739}
3740
88cefb6c 3741static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3742{
88cefb6c 3743 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3744 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3745 int pipe = intel_crtc->pipe;
5eddb70b 3746 u32 reg, temp;
79e53945 3747
c64e311e 3748
c98e9dcf 3749 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
627eb5a3 3752 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3753 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3754 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3755 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3756
3757 POSTING_READ(reg);
c98e9dcf
JB		 3758 udelay(200);
3759
3760 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3761 temp = I915_READ(reg);
3762 I915_WRITE(reg, temp | FDI_PCDCLK);
3763
3764 POSTING_READ(reg);
c98e9dcf
JB		 3765 udelay(200);
3766
20749730
PZ		 3767 /* Enable CPU FDI TX PLL, always on for Ironlake */
3768 reg = FDI_TX_CTL(pipe);
3769 temp = I915_READ(reg);
3770 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3771 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3772
20749730
PZ		 3773 POSTING_READ(reg);
3774 udelay(100);
6be4a607 3775 }
0e23b99d
JB		 3776}
3777
88cefb6c
DV		 3778static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3779{
3780 struct drm_device *dev = intel_crtc->base.dev;
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 int pipe = intel_crtc->pipe;
3783 u32 reg, temp;
3784
3785 /* Switch from PCDclk to Rawclk */
3786 reg = FDI_RX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3789
3790 /* Disable CPU FDI TX PLL */
3791 reg = FDI_TX_CTL(pipe);
3792 temp = I915_READ(reg);
3793 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3794
3795 POSTING_READ(reg);
3796 udelay(100);
3797
3798 reg = FDI_RX_CTL(pipe);
3799 temp = I915_READ(reg);
3800 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3801
3802 /* Wait for the clocks to turn off. */
3803 POSTING_READ(reg);
3804 udelay(100);
3805}
3806
0fc932b8
JB		 3807static void ironlake_fdi_disable(struct drm_crtc *crtc)
3808{
3809 struct drm_device *dev = crtc->dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812 int pipe = intel_crtc->pipe;
3813 u32 reg, temp;
3814
3815 /* disable CPU FDI tx and PCH FDI rx */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3819 POSTING_READ(reg);
3820
3821 reg = FDI_RX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 temp &= ~(0x7 << 16);
dfd07d72 3824 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3825 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3831 if (HAS_PCH_IBX(dev))
6f06ce18 3832 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3833
3834 /* still set train pattern 1 */
3835 reg = FDI_TX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 temp &= ~FDI_LINK_TRAIN_NONE;
3838 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839 I915_WRITE(reg, temp);
3840
3841 reg = FDI_RX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 if (HAS_PCH_CPT(dev)) {
3844 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3846 } else {
3847 temp &= ~FDI_LINK_TRAIN_NONE;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1;
3849 }
3850 /* BPC in FDI rx is consistent with that in PIPECONF */
3851 temp &= ~(0x07 << 16);
dfd07d72 3852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3853 I915_WRITE(reg, temp);
3854
3855 POSTING_READ(reg);
3856 udelay(100);
3857}
3858
5dce5b93
CW		 3859bool intel_has_pending_fb_unpin(struct drm_device *dev)
3860{
3861 struct intel_crtc *crtc;
3862
3863 /* Note that we don't need to be called with mode_config.lock here
3864 * as our list of CRTC objects is static for the lifetime of the
3865 * device and so cannot disappear as we iterate. Similarly, we can
3866 * happily treat the predicates as racy, atomic checks as userspace
3867 * cannot claim and pin a new fb without at least acquring the
3868 * struct_mutex and so serialising with us.
3869 */
d3fcc808 3870 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3871 if (atomic_read(&crtc->unpin_work_count) == 0)
3872 continue;
3873
3874 if (crtc->unpin_work)
3875 intel_wait_for_vblank(dev, crtc->pipe);
3876
3877 return true;
3878 }
3879
3880 return false;
3881}
3882
d6bbafa1
CW		 3883static void page_flip_completed(struct intel_crtc *intel_crtc)
3884{
3885 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3886 struct intel_unpin_work *work = intel_crtc->unpin_work;
3887
3888 /* ensure that the unpin work is consistent wrt ->pending. */
3889 smp_rmb();
3890 intel_crtc->unpin_work = NULL;
3891
3892 if (work->event)
3893 drm_send_vblank_event(intel_crtc->base.dev,
3894 intel_crtc->pipe,
3895 work->event);
3896
3897 drm_crtc_vblank_put(&intel_crtc->base);
3898
3899 wake_up_all(&dev_priv->pending_flip_queue);
3900 queue_work(dev_priv->wq, &work->work);
3901
3902 trace_i915_flip_complete(intel_crtc->plane,
3903 work->pending_flip_obj);
3904}
3905
46a55d30 3906void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3907{
0f91128d 3908 struct drm_device *dev = crtc->dev;
5bb61643 3909 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3910
2c10d571 3911 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3912 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3913 !intel_crtc_has_pending_flip(crtc),
3914 60*HZ) == 0)) {
3915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3916
5e2d7afc 3917 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3918 if (intel_crtc->unpin_work) {
3919 WARN_ONCE(1, "Removing stuck page flip\n");
3920 page_flip_completed(intel_crtc);
3921 }
5e2d7afc 3922 spin_unlock_irq(&dev->event_lock);
9c787942 3923 }
5bb61643 3924
975d568a
CW		 3925 if (crtc->primary->fb) {
3926 mutex_lock(&dev->struct_mutex);
3927 intel_finish_fb(crtc->primary->fb);
3928 mutex_unlock(&dev->struct_mutex);
3929 }
e6c3a2a6
CW		 3930}
3931
e615efe4
ED		 3932/* Program iCLKIP clock to the desired frequency */
3933static void lpt_program_iclkip(struct drm_crtc *crtc)
3934{
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3937 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3938 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3939 u32 temp;
3940
a580516d 3941 mutex_lock(&dev_priv->sb_lock);
09153000 3942
e615efe4
ED		 3943 /* It is necessary to ungate the pixclk gate prior to programming
3944 * the divisors, and gate it back when it is done.
3945 */
3946 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3947
3948 /* Disable SSCCTL */
3949 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3950 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3951 SBI_SSCCTL_DISABLE,
3952 SBI_ICLK);
e615efe4
ED		 3953
3954 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3955 if (clock == 20000) {
e615efe4
ED		 3956 auxdiv = 1;
3957 divsel = 0x41;
3958 phaseinc = 0x20;
3959 } else {
3960 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3961 * but the adjusted_mode->crtc_clock in in KHz. To get the
3962 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3963 * convert the virtual clock precision to KHz here for higher
3964 * precision.
3965 */
3966 u32 iclk_virtual_root_freq = 172800 * 1000;
3967 u32 iclk_pi_range = 64;
3968 u32 desired_divisor, msb_divisor_value, pi_value;
3969
12d7ceed 3970 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3971 msb_divisor_value = desired_divisor / iclk_pi_range;
3972 pi_value = desired_divisor % iclk_pi_range;
3973
3974 auxdiv = 0;
3975 divsel = msb_divisor_value - 2;
3976 phaseinc = pi_value;
3977 }
3978
3979 /* This should not happen with any sane values */
3980 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3981 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3982 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3983 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3984
3985 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3986 clock,
e615efe4
ED		 3987 auxdiv,
3988 divsel,
3989 phasedir,
3990 phaseinc);
3991
3992 /* Program SSCDIVINTPHASE6 */
988d6ee8 3993 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3994 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3995 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3996 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3997 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3998 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3999 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4000 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4001
4002 /* Program SSCAUXDIV */
988d6ee8 4003 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4004 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4005 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4006 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4007
4008 /* Enable modulator and associated divider */
988d6ee8 4009 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4010 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4011 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4012
4013 /* Wait for initialization time */
4014 udelay(24);
4015
4016 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4017
a580516d 4018 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4019}
4020
275f01b2
DV		 4021static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4022 enum pipe pch_transcoder)
4023{
4024 struct drm_device *dev = crtc->base.dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4026 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4027
4028 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4029 I915_READ(HTOTAL(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4031 I915_READ(HBLANK(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4033 I915_READ(HSYNC(cpu_transcoder)));
4034
4035 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4036 I915_READ(VTOTAL(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4038 I915_READ(VBLANK(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4040 I915_READ(VSYNC(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4042 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4043}
4044
003632d9 4045static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4046{
4047 struct drm_i915_private *dev_priv = dev->dev_private;
4048 uint32_t temp;
4049
4050 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4051 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4052 return;
4053
4054 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4056
003632d9
ACO		 4057 temp &= ~FDI_BC_BIFURCATION_SELECT;
4058 if (enable)
4059 temp |= FDI_BC_BIFURCATION_SELECT;
4060
4061 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4062 I915_WRITE(SOUTH_CHICKEN1, temp);
4063 POSTING_READ(SOUTH_CHICKEN1);
4064}
4065
4066static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4067{
4068 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4069
4070 switch (intel_crtc->pipe) {
4071 case PIPE_A:
4072 break;
4073 case PIPE_B:
6e3c9717 4074 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4075 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4076 else
003632d9 4077 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4078
4079 break;
4080 case PIPE_C:
003632d9 4081 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4082
4083 break;
4084 default:
4085 BUG();
4086 }
4087}
4088
f67a559d
JB		 4089/*
4090 * Enable PCH resources required for PCH ports:
4091 * - PCH PLLs
4092 * - FDI training & RX/TX
4093 * - update transcoder timings
4094 * - DP transcoding bits
4095 * - transcoder
4096 */
4097static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4098{
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102 int pipe = intel_crtc->pipe;
ee7b9f93 4103 u32 reg, temp;
2c07245f 4104
ab9412ba 4105 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4106
1fbc0d78
DV		 4107 if (IS_IVYBRIDGE(dev))
4108 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4109
cd986abb
DV		 4110 /* Write the TU size bits before fdi link training, so that error
4111 * detection works. */
4112 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4113 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4114
c98e9dcf 4115 /* For PCH output, training FDI link */
674cf967 4116 dev_priv->display.fdi_link_train(crtc);
2c07245f 4117
3ad8a208
DV		 4118 /* We need to program the right clock selection before writing the pixel
4119 * mutliplier into the DPLL. */
303b81e0 4120 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4121 u32 sel;
4b645f14 4122
c98e9dcf 4123 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4124 temp |= TRANS_DPLL_ENABLE(pipe);
4125 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4126 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4127 temp |= sel;
4128 else
4129 temp &= ~sel;
c98e9dcf 4130 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4131 }
5eddb70b 4132
3ad8a208
DV		 4133 /* XXX: pch pll's can be enabled any time before we enable the PCH
4134 * transcoder, and we actually should do this to not upset any PCH
4135 * transcoder that already use the clock when we share it.
4136 *
4137 * Note that enable_shared_dpll tries to do the right thing, but
4138 * get_shared_dpll unconditionally resets the pll - we need that to have
4139 * the right LVDS enable sequence. */
85b3894f 4140 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4141
d9b6cb56
JB		 4142 /* set transcoder timing, panel must allow it */
4143 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4144 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4145
303b81e0 4146 intel_fdi_normal_train(crtc);
5e84e1a4 4147
c98e9dcf 4148 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4149 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4150 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4151 reg = TRANS_DP_CTL(pipe);
4152 temp = I915_READ(reg);
4153 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4154 TRANS_DP_SYNC_MASK |
4155 TRANS_DP_BPC_MASK);
e3ef4479 4156 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4157 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4158
4159 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4160 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4161 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4162 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4163
4164 switch (intel_trans_dp_port_sel(crtc)) {
4165 case PCH_DP_B:
5eddb70b 4166 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4167 break;
4168 case PCH_DP_C:
5eddb70b 4169 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4170 break;
4171 case PCH_DP_D:
5eddb70b 4172 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4173 break;
4174 default:
e95d41e1 4175 BUG();
32f9d658 4176 }
2c07245f 4177
5eddb70b 4178 I915_WRITE(reg, temp);
6be4a607 4179 }
b52eb4dc 4180
b8a4f404 4181 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4182}
4183
1507e5bd
PZ		 4184static void lpt_pch_enable(struct drm_crtc *crtc)
4185{
4186 struct drm_device *dev = crtc->dev;
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4189 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4190
ab9412ba 4191 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4192
8c52b5e8 4193 lpt_program_iclkip(crtc);
1507e5bd 4194
0540e488 4195 /* Set transcoder timing. */
275f01b2 4196 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4197
937bb610 4198 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4199}
4200
190f68c5
ACO		 4201struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4202 struct intel_crtc_state *crtc_state)
ee7b9f93 4203{
e2b78267 4204 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4205 struct intel_shared_dpll *pll;
de419ab6 4206 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4207 enum intel_dpll_id i;
ee7b9f93 4208
de419ab6
ML		 4209 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4210
98b6bd99
DV		 4211 if (HAS_PCH_IBX(dev_priv->dev)) {
4212 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4213 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4214 pll = &dev_priv->shared_dplls[i];
98b6bd99 4215
46edb027
DV		 4216 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4217 crtc->base.base.id, pll->name);
98b6bd99 4218
de419ab6 4219 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4220
98b6bd99
DV		 4221 goto found;
4222 }
4223
bcddf610
S		 4224 if (IS_BROXTON(dev_priv->dev)) {
4225 /* PLL is attached to port in bxt */
4226 struct intel_encoder *encoder;
4227 struct intel_digital_port *intel_dig_port;
4228
4229 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4230 if (WARN_ON(!encoder))
4231 return NULL;
4232
4233 intel_dig_port = enc_to_dig_port(&encoder->base);
4234 /* 1:1 mapping between ports and PLLs */
4235 i = (enum intel_dpll_id)intel_dig_port->port;
4236 pll = &dev_priv->shared_dplls[i];
4237 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4238 crtc->base.base.id, pll->name);
de419ab6 4239 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4240
4241 goto found;
4242 }
4243
e72f9fbf
DV		 4244 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4245 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4246
4247 /* Only want to check enabled timings first */
de419ab6 4248 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4249 continue;
4250
190f68c5 4251 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4252 &shared_dpll[i].hw_state,
4253 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4254 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4255 crtc->base.base.id, pll->name,
de419ab6 4256 shared_dpll[i].crtc_mask,
8bd31e67 4257 pll->active);
ee7b9f93
JB		 4258 goto found;
4259 }
4260 }
4261
4262 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4263 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4264 pll = &dev_priv->shared_dplls[i];
de419ab6 4265 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4266 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4267 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4268 goto found;
4269 }
4270 }
4271
4272 return NULL;
4273
4274found:
de419ab6
ML		 4275 if (shared_dpll[i].crtc_mask == 0)
4276 shared_dpll[i].hw_state =
4277 crtc_state->dpll_hw_state;
f2a69f44 4278
190f68c5 4279 crtc_state->shared_dpll = i;
46edb027
DV		 4280 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4281 pipe_name(crtc->pipe));
ee7b9f93 4282
de419ab6 4283 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4284
ee7b9f93
JB		 4285 return pll;
4286}
4287
de419ab6 4288static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4289{
de419ab6
ML		 4290 struct drm_i915_private *dev_priv = to_i915(state->dev);
4291 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4292 struct intel_shared_dpll *pll;
4293 enum intel_dpll_id i;
4294
de419ab6
ML		 4295 if (!to_intel_atomic_state(state)->dpll_set)
4296 return;
8bd31e67 4297
de419ab6 4298 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4300 pll = &dev_priv->shared_dplls[i];
de419ab6 4301 pll->config = shared_dpll[i];
8bd31e67
ACO		 4302 }
4303}
4304
a1520318 4305static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4306{
4307 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4308 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4309 u32 temp;
4310
4311 temp = I915_READ(dslreg);
4312 udelay(500);
4313 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4314 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4315 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4316 }
4317}
4318
86adf9d7
ML		 4319static int
4320skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4321 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4322 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4323{
86adf9d7
ML		 4324 struct intel_crtc_scaler_state *scaler_state =
4325 &crtc_state->scaler_state;
4326 struct intel_crtc *intel_crtc =
4327 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4328 int need_scaling;
6156a456
CK		 4329
4330 need_scaling = intel_rotation_90_or_270(rotation) ?
4331 (src_h != dst_w || src_w != dst_h):
4332 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4333
4334 /*
4335 * if plane is being disabled or scaler is no more required or force detach
4336 * - free scaler binded to this plane/crtc
4337 * - in order to do this, update crtc->scaler_usage
4338 *
4339 * Here scaler state in crtc_state is set free so that
4340 * scaler can be assigned to other user. Actual register
4341 * update to free the scaler is done in plane/panel-fit programming.
4342 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4343 */
86adf9d7 4344 if (force_detach || !need_scaling) {
a1b2278e 4345 if (*scaler_id >= 0) {
86adf9d7 4346 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4347 scaler_state->scalers[*scaler_id].in_use = 0;
4348
86adf9d7
ML		 4349 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4350 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4351 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4352 scaler_state->scaler_users);
4353 *scaler_id = -1;
4354 }
4355 return 0;
4356 }
4357
4358 /* range checks */
4359 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4360 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4361
4362 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4363 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4364 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4365 "size is out of scaler range\n",
86adf9d7 4366 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4367 return -EINVAL;
4368 }
4369
86adf9d7
ML		 4370 /* mark this plane as a scaler user in crtc_state */
4371 scaler_state->scaler_users |= (1 << scaler_user);
4372 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4373 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4374 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4375 scaler_state->scaler_users);
4376
4377 return 0;
4378}
4379
4380/**
4381 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4382 *
4383 * @state: crtc's scaler state
86adf9d7
ML		 4384 *
4385 * Return
4386 * 0 - scaler_usage updated successfully
4387 * error - requested scaling cannot be supported or other error condition
4388 */
e435d6e5 4389int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4390{
4391 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4392 struct drm_display_mode *adjusted_mode =
4393 &state->base.adjusted_mode;
4394
4395 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4396 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4397
e435d6e5 4398 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4399 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4400 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4401 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4402}
4403
4404/**
4405 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4406 *
4407 * @state: crtc's scaler state
86adf9d7
ML		 4408 * @plane_state: atomic plane state to update
4409 *
4410 * Return
4411 * 0 - scaler_usage updated successfully
4412 * error - requested scaling cannot be supported or other error condition
4413 */
da20eabd
ML		 4414static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4415 struct intel_plane_state *plane_state)
86adf9d7
ML		 4416{
4417
4418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4419 struct intel_plane *intel_plane =
4420 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4421 struct drm_framebuffer *fb = plane_state->base.fb;
4422 int ret;
4423
4424 bool force_detach = !fb || !plane_state->visible;
4425
4426 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4427 intel_plane->base.base.id, intel_crtc->pipe,
4428 drm_plane_index(&intel_plane->base));
4429
4430 ret = skl_update_scaler(crtc_state, force_detach,
4431 drm_plane_index(&intel_plane->base),
4432 &plane_state->scaler_id,
4433 plane_state->base.rotation,
4434 drm_rect_width(&plane_state->src) >> 16,
4435 drm_rect_height(&plane_state->src) >> 16,
4436 drm_rect_width(&plane_state->dst),
4437 drm_rect_height(&plane_state->dst));
4438
4439 if (ret || plane_state->scaler_id < 0)
4440 return ret;
4441
a1b2278e 4442 /* check colorkey */
818ed961 4443 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4444 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4445 intel_plane->base.base.id);
a1b2278e
CK		 4446 return -EINVAL;
4447 }
4448
4449 /* Check src format */
86adf9d7
ML		 4450 switch (fb->pixel_format) {
4451 case DRM_FORMAT_RGB565:
4452 case DRM_FORMAT_XBGR8888:
4453 case DRM_FORMAT_XRGB8888:
4454 case DRM_FORMAT_ABGR8888:
4455 case DRM_FORMAT_ARGB8888:
4456 case DRM_FORMAT_XRGB2101010:
4457 case DRM_FORMAT_XBGR2101010:
4458 case DRM_FORMAT_YUYV:
4459 case DRM_FORMAT_YVYU:
4460 case DRM_FORMAT_UYVY:
4461 case DRM_FORMAT_VYUY:
4462 break;
4463 default:
4464 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4465 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4466 return -EINVAL;
a1b2278e
CK		 4467 }
4468
a1b2278e
CK		 4469 return 0;
4470}
4471
e435d6e5
ML		 4472static void skylake_scaler_disable(struct intel_crtc *crtc)
4473{
4474 int i;
4475
4476 for (i = 0; i < crtc->num_scalers; i++)
4477 skl_detach_scaler(crtc, i);
4478}
4479
4480static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4481{
4482 struct drm_device *dev = crtc->base.dev;
4483 struct drm_i915_private *dev_priv = dev->dev_private;
4484 int pipe = crtc->pipe;
a1b2278e
CK		 4485 struct intel_crtc_scaler_state *scaler_state =
4486 &crtc->config->scaler_state;
4487
4488 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4489
6e3c9717 4490 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4491 int id;
4492
4493 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4494 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4495 return;
4496 }
4497
4498 id = scaler_state->scaler_id;
4499 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4500 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4501 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4502 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4503
4504 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4505 }
4506}
4507
b074cec8
JB		 4508static void ironlake_pfit_enable(struct intel_crtc *crtc)
4509{
4510 struct drm_device *dev = crtc->base.dev;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 int pipe = crtc->pipe;
4513
6e3c9717 4514 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4515 /* Force use of hard-coded filter coefficients
4516 * as some pre-programmed values are broken,
4517 * e.g. x201.
4518 */
4519 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4520 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4521 PF_PIPE_SEL_IVB(pipe));
4522 else
4523 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4524 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4525 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4526 }
4527}
4528
20bc8673 4529void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4530{
cea165c3
VS		 4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4533
6e3c9717 4534 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4535 return;
4536
cea165c3
VS		 4537 /* We can only enable IPS after we enable a plane and wait for a vblank */
4538 intel_wait_for_vblank(dev, crtc->pipe);
4539
d77e4531 4540 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4541 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4542 mutex_lock(&dev_priv->rps.hw_lock);
4543 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4544 mutex_unlock(&dev_priv->rps.hw_lock);
4545 /* Quoting Art Runyan: "its not safe to expect any particular
4546 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4547 * mailbox." Moreover, the mailbox may return a bogus state,
4548 * so we need to just enable it and continue on.
2a114cc1
BW		 4549 */
4550 } else {
4551 I915_WRITE(IPS_CTL, IPS_ENABLE);
4552 /* The bit only becomes 1 in the next vblank, so this wait here
4553 * is essentially intel_wait_for_vblank. If we don't have this
4554 * and don't wait for vblanks until the end of crtc_enable, then
4555 * the HW state readout code will complain that the expected
4556 * IPS_CTL value is not the one we read. */
4557 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4558 DRM_ERROR("Timed out waiting for IPS enable\n");
4559 }
d77e4531
PZ		 4560}
4561
20bc8673 4562void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4563{
4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566
6e3c9717 4567 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4568 return;
4569
4570 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4571 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4572 mutex_lock(&dev_priv->rps.hw_lock);
4573 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4574 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4575 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4576 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4577 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4578 } else {
2a114cc1 4579 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4580 POSTING_READ(IPS_CTL);
4581 }
d77e4531
PZ		 4582
4583 /* We need to wait for a vblank before we can disable the plane. */
4584 intel_wait_for_vblank(dev, crtc->pipe);
4585}
4586
4587/** Loads the palette/gamma unit for the CRTC with the prepared values */
4588static void intel_crtc_load_lut(struct drm_crtc *crtc)
4589{
4590 struct drm_device *dev = crtc->dev;
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4593 enum pipe pipe = intel_crtc->pipe;
4594 int palreg = PALETTE(pipe);
4595 int i;
4596 bool reenable_ips = false;
4597
4598 /* The clocks have to be on to load the palette. */
53d9f4e9 4599 if (!crtc->state->active)
d77e4531
PZ		 4600 return;
4601
50360403 4602 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4603 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4604 assert_dsi_pll_enabled(dev_priv);
4605 else
4606 assert_pll_enabled(dev_priv, pipe);
4607 }
4608
4609 /* use legacy palette for Ironlake */
7a1db49a 4610 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4611 palreg = LGC_PALETTE(pipe);
4612
4613 /* Workaround : Do not read or write the pipe palette/gamma data while
4614 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4615 */
6e3c9717 4616 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4617 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4618 GAMMA_MODE_MODE_SPLIT)) {
4619 hsw_disable_ips(intel_crtc);
4620 reenable_ips = true;
4621 }
4622
4623 for (i = 0; i < 256; i++) {
4624 I915_WRITE(palreg + 4 * i,
4625 (intel_crtc->lut_r[i] << 16) |
4626 (intel_crtc->lut_g[i] << 8) |
4627 intel_crtc->lut_b[i]);
4628 }
4629
4630 if (reenable_ips)
4631 hsw_enable_ips(intel_crtc);
4632}
4633
7cac945f 4634static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4635{
7cac945f 4636 if (intel_crtc->overlay) {
d3eedb1a
VS		 4637 struct drm_device *dev = intel_crtc->base.dev;
4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639
4640 mutex_lock(&dev->struct_mutex);
4641 dev_priv->mm.interruptible = false;
4642 (void) intel_overlay_switch_off(intel_crtc->overlay);
4643 dev_priv->mm.interruptible = true;
4644 mutex_unlock(&dev->struct_mutex);
4645 }
4646
4647 /* Let userspace switch the overlay on again. In most cases userspace
4648 * has to recompute where to put it anyway.
4649 */
4650}
4651
87d4300a
ML		 4652/**
4653 * intel_post_enable_primary - Perform operations after enabling primary plane
4654 * @crtc: the CRTC whose primary plane was just enabled
4655 *
4656 * Performs potentially sleeping operations that must be done after the primary
4657 * plane is enabled, such as updating FBC and IPS. Note that this may be
4658 * called due to an explicit primary plane update, or due to an implicit
4659 * re-enable that is caused when a sprite plane is updated to no longer
4660 * completely hide the primary plane.
4661 */
4662static void
4663intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4664{
4665 struct drm_device *dev = crtc->dev;
87d4300a 4666 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668 int pipe = intel_crtc->pipe;
a5c4d7bc 4669
87d4300a
ML		 4670 /*
4671 * BDW signals flip done immediately if the plane
4672 * is disabled, even if the plane enable is already
4673 * armed to occur at the next vblank :(
4674 */
4675 if (IS_BROADWELL(dev))
4676 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4677
87d4300a
ML		 4678 /*
4679 * FIXME IPS should be fine as long as one plane is
4680 * enabled, but in practice it seems to have problems
4681 * when going from primary only to sprite only and vice
4682 * versa.
4683 */
a5c4d7bc
VS		 4684 hsw_enable_ips(intel_crtc);
4685
f99d7069 4686 /*
87d4300a
ML		 4687 * Gen2 reports pipe underruns whenever all planes are disabled.
4688 * So don't enable underrun reporting before at least some planes
4689 * are enabled.
4690 * FIXME: Need to fix the logic to work when we turn off all planes
4691 * but leave the pipe running.
f99d7069 4692 */
87d4300a
ML		 4693 if (IS_GEN2(dev))
4694 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4695
4696 /* Underruns don't raise interrupts, so check manually. */
4697 if (HAS_GMCH_DISPLAY(dev))
4698 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4699}
4700
87d4300a
ML		 4701/**
4702 * intel_pre_disable_primary - Perform operations before disabling primary plane
4703 * @crtc: the CRTC whose primary plane is to be disabled
4704 *
4705 * Performs potentially sleeping operations that must be done before the
4706 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4707 * be called due to an explicit primary plane update, or due to an implicit
4708 * disable that is caused when a sprite plane completely hides the primary
4709 * plane.
4710 */
4711static void
4712intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4713{
4714 struct drm_device *dev = crtc->dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4717 int pipe = intel_crtc->pipe;
a5c4d7bc 4718
87d4300a
ML		 4719 /*
4720 * Gen2 reports pipe underruns whenever all planes are disabled.
4721 * So diasble underrun reporting before all the planes get disabled.
4722 * FIXME: Need to fix the logic to work when we turn off all planes
4723 * but leave the pipe running.
4724 */
4725 if (IS_GEN2(dev))
4726 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4727
87d4300a
ML		 4728 /*
4729 * Vblank time updates from the shadow to live plane control register
4730 * are blocked if the memory self-refresh mode is active at that
4731 * moment. So to make sure the plane gets truly disabled, disable
4732 * first the self-refresh mode. The self-refresh enable bit in turn
4733 * will be checked/applied by the HW only at the next frame start
4734 * event which is after the vblank start event, so we need to have a
4735 * wait-for-vblank between disabling the plane and the pipe.
4736 */
262cd2e1 4737 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4738 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4739 dev_priv->wm.vlv.cxsr = false;
4740 intel_wait_for_vblank(dev, pipe);
4741 }
87d4300a 4742
87d4300a
ML		 4743 /*
4744 * FIXME IPS should be fine as long as one plane is
4745 * enabled, but in practice it seems to have problems
4746 * when going from primary only to sprite only and vice
4747 * versa.
4748 */
a5c4d7bc 4749 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4750}
4751
ac21b225
ML		 4752static void intel_post_plane_update(struct intel_crtc *crtc)
4753{
4754 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4755 struct drm_device *dev = crtc->base.dev;
7733b49b 4756 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4757 struct drm_plane *plane;
4758
4759 if (atomic->wait_vblank)
4760 intel_wait_for_vblank(dev, crtc->pipe);
4761
4762 intel_frontbuffer_flip(dev, atomic->fb_bits);
4763
852eb00d
VS		 4764 if (atomic->disable_cxsr)
4765 crtc->wm.cxsr_allowed = true;
4766
f015c551
VS		 4767 if (crtc->atomic.update_wm_post)
4768 intel_update_watermarks(&crtc->base);
4769
c80ac854 4770 if (atomic->update_fbc)
7733b49b 4771 intel_fbc_update(dev_priv);
ac21b225
ML		 4772
4773 if (atomic->post_enable_primary)
4774 intel_post_enable_primary(&crtc->base);
4775
4776 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4777 intel_update_sprite_watermarks(plane, &crtc->base,
4778 0, 0, 0, false, false);
4779
4780 memset(atomic, 0, sizeof(*atomic));
4781}
4782
4783static void intel_pre_plane_update(struct intel_crtc *crtc)
4784{
4785 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4786 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4787 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4788 struct drm_plane *p;
4789
4790 /* Track fb's for any planes being disabled */
ac21b225
ML		 4791 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4792 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4793
4794 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4795 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4796 plane->frontbuffer_bit);
ac21b225
ML		 4797 mutex_unlock(&dev->struct_mutex);
4798 }
4799
4800 if (atomic->wait_for_flips)
4801 intel_crtc_wait_for_pending_flips(&crtc->base);
4802
c80ac854 4803 if (atomic->disable_fbc)
25ad93fd 4804 intel_fbc_disable_crtc(crtc);
ac21b225 4805
066cf55b
RV		 4806 if (crtc->atomic.disable_ips)
4807 hsw_disable_ips(crtc);
4808
ac21b225
ML		 4809 if (atomic->pre_disable_primary)
4810 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4811
4812 if (atomic->disable_cxsr) {
4813 crtc->wm.cxsr_allowed = false;
4814 intel_set_memory_cxsr(dev_priv, false);
4815 }
ac21b225
ML		 4816}
4817
d032ffa0 4818static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4819{
4820 struct drm_device *dev = crtc->dev;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4822 struct drm_plane *p;
87d4300a
ML		 4823 int pipe = intel_crtc->pipe;
4824
7cac945f 4825 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4826
d032ffa0
ML		 4827 drm_for_each_plane_mask(p, dev, plane_mask)
4828 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4829
f99d7069
DV		 4830 /*
4831 * FIXME: Once we grow proper nuclear flip support out of this we need
4832 * to compute the mask of flip planes precisely. For the time being
4833 * consider this a flip to a NULL plane.
4834 */
4835 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4836}
4837
f67a559d
JB		 4838static void ironlake_crtc_enable(struct drm_crtc *crtc)
4839{
4840 struct drm_device *dev = crtc->dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
4842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4843 struct intel_encoder *encoder;
f67a559d 4844 int pipe = intel_crtc->pipe;
f67a559d 4845
53d9f4e9 4846 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4847 return;
4848
6e3c9717 4849 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4850 intel_prepare_shared_dpll(intel_crtc);
4851
6e3c9717 4852 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4853 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4854
4855 intel_set_pipe_timings(intel_crtc);
4856
6e3c9717 4857 if (intel_crtc->config->has_pch_encoder) {
29407aab 4858 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4859 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4860 }
4861
4862 ironlake_set_pipeconf(crtc);
4863
f67a559d 4864 intel_crtc->active = true;
8664281b 4865
a72e4c9f
DV		 4866 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4867 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4868
f6736a1a 4869 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4870 if (encoder->pre_enable)
4871 encoder->pre_enable(encoder);
f67a559d 4872
6e3c9717 4873 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4874 /* Note: FDI PLL enabling _must_ be done before we enable the
4875 * cpu pipes, hence this is separate from all the other fdi/pch
4876 * enabling. */
88cefb6c 4877 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4878 } else {
4879 assert_fdi_tx_disabled(dev_priv, pipe);
4880 assert_fdi_rx_disabled(dev_priv, pipe);
4881 }
f67a559d 4882
b074cec8 4883 ironlake_pfit_enable(intel_crtc);
f67a559d 4884
9c54c0dd
JB		 4885 /*
4886 * On ILK+ LUT must be loaded before the pipe is running but with
4887 * clocks enabled
4888 */
4889 intel_crtc_load_lut(crtc);
4890
f37fcc2a 4891 intel_update_watermarks(crtc);
e1fdc473 4892 intel_enable_pipe(intel_crtc);
f67a559d 4893
6e3c9717 4894 if (intel_crtc->config->has_pch_encoder)
f67a559d 4895 ironlake_pch_enable(crtc);
c98e9dcf 4896
f9b61ff6
DV		 4897 assert_vblank_disabled(crtc);
4898 drm_crtc_vblank_on(crtc);
4899
fa5c73b1
DV		 4900 for_each_encoder_on_crtc(dev, crtc, encoder)
4901 encoder->enable(encoder);
61b77ddd
DV		 4902
4903 if (HAS_PCH_CPT(dev))
a1520318 4904 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4905}
4906
42db64ef
PZ		 4907/* IPS only exists on ULT machines and is tied to pipe A. */
4908static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4909{
f5adf94e 4910 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4911}
4912
4f771f10
PZ		 4913static void haswell_crtc_enable(struct drm_crtc *crtc)
4914{
4915 struct drm_device *dev = crtc->dev;
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4918 struct intel_encoder *encoder;
99d736a2
ML		 4919 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4920 struct intel_crtc_state *pipe_config =
4921 to_intel_crtc_state(crtc->state);
4f771f10 4922
53d9f4e9 4923 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4924 return;
4925
df8ad70c
DV		 4926 if (intel_crtc_to_shared_dpll(intel_crtc))
4927 intel_enable_shared_dpll(intel_crtc);
4928
6e3c9717 4929 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4930 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4931
4932 intel_set_pipe_timings(intel_crtc);
4933
6e3c9717
ACO		 4934 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4935 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4936 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4937 }
4938
6e3c9717 4939 if (intel_crtc->config->has_pch_encoder) {
229fca97 4940 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4941 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4942 }
4943
4944 haswell_set_pipeconf(crtc);
4945
4946 intel_set_pipe_csc(crtc);
4947
4f771f10 4948 intel_crtc->active = true;
8664281b 4949
a72e4c9f 4950 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4951 for_each_encoder_on_crtc(dev, crtc, encoder)
4952 if (encoder->pre_enable)
4953 encoder->pre_enable(encoder);
4954
6e3c9717 4955 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4956 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4957 true);
4fe9467d
ID		 4958 dev_priv->display.fdi_link_train(crtc);
4959 }
4960
1f544388 4961 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4962
ff6d9f55 4963 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4964 skylake_pfit_enable(intel_crtc);
ff6d9f55 4965 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4966 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4967 else
4968 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4969
4970 /*
4971 * On ILK+ LUT must be loaded before the pipe is running but with
4972 * clocks enabled
4973 */
4974 intel_crtc_load_lut(crtc);
4975
1f544388 4976 intel_ddi_set_pipe_settings(crtc);
8228c251 4977 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4978
f37fcc2a 4979 intel_update_watermarks(crtc);
e1fdc473 4980 intel_enable_pipe(intel_crtc);
42db64ef 4981
6e3c9717 4982 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4983 lpt_pch_enable(crtc);
4f771f10 4984
6e3c9717 4985 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4986 intel_ddi_set_vc_payload_alloc(crtc, true);
4987
f9b61ff6
DV		 4988 assert_vblank_disabled(crtc);
4989 drm_crtc_vblank_on(crtc);
4990
8807e55b 4991 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4992 encoder->enable(encoder);
8807e55b
JN		 4993 intel_opregion_notify_encoder(encoder, true);
4994 }
4f771f10 4995
e4916946
PZ		 4996 /* If we change the relative order between pipe/planes enabling, we need
4997 * to change the workaround. */
99d736a2
ML		 4998 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4999 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5000 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5001 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5002 }
4f771f10
PZ		 5003}
5004
3f8dce3a
DV		 5005static void ironlake_pfit_disable(struct intel_crtc *crtc)
5006{
5007 struct drm_device *dev = crtc->base.dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 int pipe = crtc->pipe;
5010
5011 /* To avoid upsetting the power well on haswell only disable the pfit if
5012 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5013 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5014 I915_WRITE(PF_CTL(pipe), 0);
5015 I915_WRITE(PF_WIN_POS(pipe), 0);
5016 I915_WRITE(PF_WIN_SZ(pipe), 0);
5017 }
5018}
5019
6be4a607
JB		 5020static void ironlake_crtc_disable(struct drm_crtc *crtc)
5021{
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5025 struct intel_encoder *encoder;
6be4a607 5026 int pipe = intel_crtc->pipe;
5eddb70b 5027 u32 reg, temp;
b52eb4dc 5028
ea9d758d
DV		 5029 for_each_encoder_on_crtc(dev, crtc, encoder)
5030 encoder->disable(encoder);
5031
f9b61ff6
DV		 5032 drm_crtc_vblank_off(crtc);
5033 assert_vblank_disabled(crtc);
5034
6e3c9717 5035 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5036 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5037
575f7ab7 5038 intel_disable_pipe(intel_crtc);
32f9d658 5039
3f8dce3a 5040 ironlake_pfit_disable(intel_crtc);
2c07245f 5041
5a74f70a
VS		 5042 if (intel_crtc->config->has_pch_encoder)
5043 ironlake_fdi_disable(crtc);
5044
bf49ec8c
DV		 5045 for_each_encoder_on_crtc(dev, crtc, encoder)
5046 if (encoder->post_disable)
5047 encoder->post_disable(encoder);
2c07245f 5048
6e3c9717 5049 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5050 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5051
d925c59a
DV		 5052 if (HAS_PCH_CPT(dev)) {
5053 /* disable TRANS_DP_CTL */
5054 reg = TRANS_DP_CTL(pipe);
5055 temp = I915_READ(reg);
5056 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057 TRANS_DP_PORT_SEL_MASK);
5058 temp |= TRANS_DP_PORT_SEL_NONE;
5059 I915_WRITE(reg, temp);
5060
5061 /* disable DPLL_SEL */
5062 temp = I915_READ(PCH_DPLL_SEL);
11887397 5063 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5064 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5065 }
e3421a18 5066
d925c59a
DV		 5067 ironlake_fdi_pll_disable(intel_crtc);
5068 }
e4ca0612
PJ		 5069
5070 intel_crtc->active = false;
5071 intel_update_watermarks(crtc);
6be4a607 5072}
1b3c7a47 5073
4f771f10 5074static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5075{
4f771f10
PZ		 5076 struct drm_device *dev = crtc->dev;
5077 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5079 struct intel_encoder *encoder;
6e3c9717 5080 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5081
8807e55b
JN		 5082 for_each_encoder_on_crtc(dev, crtc, encoder) {
5083 intel_opregion_notify_encoder(encoder, false);
4f771f10 5084 encoder->disable(encoder);
8807e55b 5085 }
4f771f10 5086
f9b61ff6
DV		 5087 drm_crtc_vblank_off(crtc);
5088 assert_vblank_disabled(crtc);
5089
6e3c9717 5090 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5091 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5092 false);
575f7ab7 5093 intel_disable_pipe(intel_crtc);
4f771f10 5094
6e3c9717 5095 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5096 intel_ddi_set_vc_payload_alloc(crtc, false);
5097
ad80a810 5098 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5099
ff6d9f55 5100 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5101 skylake_scaler_disable(intel_crtc);
ff6d9f55 5102 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5103 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5104 else
5105 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5106
1f544388 5107 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5108
6e3c9717 5109 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5110 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5111 intel_ddi_fdi_disable(crtc);
83616634 5112 }
4f771f10 5113
97b040aa
ID		 5114 for_each_encoder_on_crtc(dev, crtc, encoder)
5115 if (encoder->post_disable)
5116 encoder->post_disable(encoder);
e4ca0612
PJ		 5117
5118 intel_crtc->active = false;
5119 intel_update_watermarks(crtc);
4f771f10
PZ		 5120}
5121
2dd24552
JB		 5122static void i9xx_pfit_enable(struct intel_crtc *crtc)
5123{
5124 struct drm_device *dev = crtc->base.dev;
5125 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5126 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5127
681a8504 5128 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5129 return;
5130
2dd24552 5131 /*
c0b03411
DV		 5132 * The panel fitter should only be adjusted whilst the pipe is disabled,
5133 * according to register description and PRM.
2dd24552 5134 */
c0b03411
DV		 5135 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5136 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5137
b074cec8
JB		 5138 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5139 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5140
5141 /* Border color in case we don't scale up to the full screen. Black by
5142 * default, change to something else for debugging. */
5143 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5144}
5145
d05410f9
DA		 5146static enum intel_display_power_domain port_to_power_domain(enum port port)
5147{
5148 switch (port) {
5149 case PORT_A:
a513e3d7 5150 case PORT_E:
d05410f9
DA		 5151 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5152 case PORT_B:
5153 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5154 case PORT_C:
5155 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5156 case PORT_D:
5157 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5158 default:
5159 WARN_ON_ONCE(1);
5160 return POWER_DOMAIN_PORT_OTHER;
5161 }
5162}
5163
77d22dca
ID		 5164#define for_each_power_domain(domain, mask) \
5165 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5166 if ((1 << (domain)) & (mask))
5167
319be8ae
ID		 5168enum intel_display_power_domain
5169intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5170{
5171 struct drm_device *dev = intel_encoder->base.dev;
5172 struct intel_digital_port *intel_dig_port;
5173
5174 switch (intel_encoder->type) {
5175 case INTEL_OUTPUT_UNKNOWN:
5176 /* Only DDI platforms should ever use this output type */
5177 WARN_ON_ONCE(!HAS_DDI(dev));
5178 case INTEL_OUTPUT_DISPLAYPORT:
5179 case INTEL_OUTPUT_HDMI:
5180 case INTEL_OUTPUT_EDP:
5181 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5182 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5183 case INTEL_OUTPUT_DP_MST:
5184 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5185 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5186 case INTEL_OUTPUT_ANALOG:
5187 return POWER_DOMAIN_PORT_CRT;
5188 case INTEL_OUTPUT_DSI:
5189 return POWER_DOMAIN_PORT_DSI;
5190 default:
5191 return POWER_DOMAIN_PORT_OTHER;
5192 }
5193}
5194
5195static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5196{
319be8ae
ID		 5197 struct drm_device *dev = crtc->dev;
5198 struct intel_encoder *intel_encoder;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5201 unsigned long mask;
5202 enum transcoder transcoder;
5203
292b990e
ML		 5204 if (!crtc->state->active)
5205 return 0;
5206
77d22dca
ID		 5207 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5208
5209 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5210 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5211 if (intel_crtc->config->pch_pfit.enabled ||
5212 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5213 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5214
319be8ae
ID		 5215 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5216 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5217
77d22dca
ID		 5218 return mask;
5219}
5220
292b990e 5221static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5222{
292b990e
ML		 5223 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5225 enum intel_display_power_domain domain;
5226 unsigned long domains, new_domains, old_domains;
77d22dca 5227
292b990e
ML		 5228 old_domains = intel_crtc->enabled_power_domains;
5229 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5230
292b990e
ML		 5231 domains = new_domains & ~old_domains;
5232
5233 for_each_power_domain(domain, domains)
5234 intel_display_power_get(dev_priv, domain);
5235
5236 return old_domains & ~new_domains;
5237}
5238
5239static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5240 unsigned long domains)
5241{
5242 enum intel_display_power_domain domain;
5243
5244 for_each_power_domain(domain, domains)
5245 intel_display_power_put(dev_priv, domain);
5246}
77d22dca 5247
292b990e
ML		 5248static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5249{
5250 struct drm_device *dev = state->dev;
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252 unsigned long put_domains[I915_MAX_PIPES] = {};
5253 struct drm_crtc_state *crtc_state;
5254 struct drm_crtc *crtc;
5255 int i;
77d22dca 5256
292b990e
ML		 5257 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5258 if (needs_modeset(crtc->state))
5259 put_domains[to_intel_crtc(crtc)->pipe] =
5260 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5261 }
5262
27c329ed
ML		 5263 if (dev_priv->display.modeset_commit_cdclk) {
5264 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5265
5266 if (cdclk != dev_priv->cdclk_freq &&
5267 !WARN_ON(!state->allow_modeset))
5268 dev_priv->display.modeset_commit_cdclk(state);
5269 }
50f6e502 5270
292b990e
ML		 5271 for (i = 0; i < I915_MAX_PIPES; i++)
5272 if (put_domains[i])
5273 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5274}
5275
560a7ae4
DL		 5276static void intel_update_max_cdclk(struct drm_device *dev)
5277{
5278 struct drm_i915_private *dev_priv = dev->dev_private;
5279
5280 if (IS_SKYLAKE(dev)) {
5281 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5282
5283 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5284 dev_priv->max_cdclk_freq = 675000;
5285 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5286 dev_priv->max_cdclk_freq = 540000;
5287 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5288 dev_priv->max_cdclk_freq = 450000;
5289 else
5290 dev_priv->max_cdclk_freq = 337500;
5291 } else if (IS_BROADWELL(dev)) {
5292 /*
5293 * FIXME with extra cooling we can allow
5294 * 540 MHz for ULX and 675 Mhz for ULT.
5295 * How can we know if extra cooling is
5296 * available? PCI ID, VTB, something else?
5297 */
5298 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5299 dev_priv->max_cdclk_freq = 450000;
5300 else if (IS_BDW_ULX(dev))
5301 dev_priv->max_cdclk_freq = 450000;
5302 else if (IS_BDW_ULT(dev))
5303 dev_priv->max_cdclk_freq = 540000;
5304 else
5305 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5306 } else if (IS_CHERRYVIEW(dev)) {
5307 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5308 } else if (IS_VALLEYVIEW(dev)) {
5309 dev_priv->max_cdclk_freq = 400000;
5310 } else {
5311 /* otherwise assume cdclk is fixed */
5312 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5313 }
5314
5315 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5316 dev_priv->max_cdclk_freq);
5317}
5318
5319static void intel_update_cdclk(struct drm_device *dev)
5320{
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322
5323 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5324 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5325 dev_priv->cdclk_freq);
5326
5327 /*
5328 * Program the gmbus_freq based on the cdclk frequency.
5329 * BSpec erroneously claims we should aim for 4MHz, but
5330 * in fact 1MHz is the correct frequency.
5331 */
5332 if (IS_VALLEYVIEW(dev)) {
5333 /*
5334 * Program the gmbus_freq based on the cdclk frequency.
5335 * BSpec erroneously claims we should aim for 4MHz, but
5336 * in fact 1MHz is the correct frequency.
5337 */
5338 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5339 }
5340
5341 if (dev_priv->max_cdclk_freq == 0)
5342 intel_update_max_cdclk(dev);
5343}
5344
70d0c574 5345static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5346{
5347 struct drm_i915_private *dev_priv = dev->dev_private;
5348 uint32_t divider;
5349 uint32_t ratio;
5350 uint32_t current_freq;
5351 int ret;
5352
5353 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5354 switch (frequency) {
5355 case 144000:
5356 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5357 ratio = BXT_DE_PLL_RATIO(60);
5358 break;
5359 case 288000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 384000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 576000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 624000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(65);
5374 break;
5375 case 19200:
5376 /*
5377 * Bypass frequency with DE PLL disabled. Init ratio, divider
5378 * to suppress GCC warning.
5379 */
5380 ratio = 0;
5381 divider = 0;
5382 break;
5383 default:
5384 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5385
5386 return;
5387 }
5388
5389 mutex_lock(&dev_priv->rps.hw_lock);
5390 /* Inform power controller of upcoming frequency change */
5391 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5392 0x80000000);
5393 mutex_unlock(&dev_priv->rps.hw_lock);
5394
5395 if (ret) {
5396 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5397 ret, frequency);
5398 return;
5399 }
5400
5401 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5402 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5403 current_freq = current_freq * 500 + 1000;
5404
5405 /*
5406 * DE PLL has to be disabled when
5407 * - setting to 19.2MHz (bypass, PLL isn't used)
5408 * - before setting to 624MHz (PLL needs toggling)
5409 * - before setting to any frequency from 624MHz (PLL needs toggling)
5410 */
5411 if (frequency == 19200 || frequency == 624000 ||
5412 current_freq == 624000) {
5413 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5414 /* Timeout 200us */
5415 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5416 1))
5417 DRM_ERROR("timout waiting for DE PLL unlock\n");
5418 }
5419
5420 if (frequency != 19200) {
5421 uint32_t val;
5422
5423 val = I915_READ(BXT_DE_PLL_CTL);
5424 val &= ~BXT_DE_PLL_RATIO_MASK;
5425 val |= ratio;
5426 I915_WRITE(BXT_DE_PLL_CTL, val);
5427
5428 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5429 /* Timeout 200us */
5430 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5431 DRM_ERROR("timeout waiting for DE PLL lock\n");
5432
5433 val = I915_READ(CDCLK_CTL);
5434 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5435 val |= divider;
5436 /*
5437 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5438 * enable otherwise.
5439 */
5440 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5441 if (frequency >= 500000)
5442 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5443
5444 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5445 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5446 val |= (frequency - 1000) / 500;
5447 I915_WRITE(CDCLK_CTL, val);
5448 }
5449
5450 mutex_lock(&dev_priv->rps.hw_lock);
5451 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5452 DIV_ROUND_UP(frequency, 25000));
5453 mutex_unlock(&dev_priv->rps.hw_lock);
5454
5455 if (ret) {
5456 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5457 ret, frequency);
5458 return;
5459 }
5460
a47871bd 5461 intel_update_cdclk(dev);
f8437dd1
VK		 5462}
5463
5464void broxton_init_cdclk(struct drm_device *dev)
5465{
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 uint32_t val;
5468
5469 /*
5470 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5471 * or else the reset will hang because there is no PCH to respond.
5472 * Move the handshake programming to initialization sequence.
5473 * Previously was left up to BIOS.
5474 */
5475 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5476 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5477 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5478
5479 /* Enable PG1 for cdclk */
5480 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5481
5482 /* check if cd clock is enabled */
5483 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5484 DRM_DEBUG_KMS("Display already initialized\n");
5485 return;
5486 }
5487
5488 /*
5489 * FIXME:
5490 * - The initial CDCLK needs to be read from VBT.
5491 * Need to make this change after VBT has changes for BXT.
5492 * - check if setting the max (or any) cdclk freq is really necessary
5493 * here, it belongs to modeset time
5494 */
5495 broxton_set_cdclk(dev, 624000);
5496
5497 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5498 POSTING_READ(DBUF_CTL);
5499
f8437dd1
VK		 5500 udelay(10);
5501
5502 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5503 DRM_ERROR("DBuf power enable timeout!\n");
5504}
5505
5506void broxton_uninit_cdclk(struct drm_device *dev)
5507{
5508 struct drm_i915_private *dev_priv = dev->dev_private;
5509
5510 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5511 POSTING_READ(DBUF_CTL);
5512
f8437dd1
VK		 5513 udelay(10);
5514
5515 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5516 DRM_ERROR("DBuf power disable timeout!\n");
5517
5518 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5519 broxton_set_cdclk(dev, 19200);
5520
5521 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5522}
5523
5d96d8af
DL		 5524static const struct skl_cdclk_entry {
5525 unsigned int freq;
5526 unsigned int vco;
5527} skl_cdclk_frequencies[] = {
5528 { .freq = 308570, .vco = 8640 },
5529 { .freq = 337500, .vco = 8100 },
5530 { .freq = 432000, .vco = 8640 },
5531 { .freq = 450000, .vco = 8100 },
5532 { .freq = 540000, .vco = 8100 },
5533 { .freq = 617140, .vco = 8640 },
5534 { .freq = 675000, .vco = 8100 },
5535};
5536
5537static unsigned int skl_cdclk_decimal(unsigned int freq)
5538{
5539 return (freq - 1000) / 500;
5540}
5541
5542static unsigned int skl_cdclk_get_vco(unsigned int freq)
5543{
5544 unsigned int i;
5545
5546 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5547 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5548
5549 if (e->freq == freq)
5550 return e->vco;
5551 }
5552
5553 return 8100;
5554}
5555
5556static void
5557skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5558{
5559 unsigned int min_freq;
5560 u32 val;
5561
5562 /* select the minimum CDCLK before enabling DPLL 0 */
5563 val = I915_READ(CDCLK_CTL);
5564 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5565 val |= CDCLK_FREQ_337_308;
5566
5567 if (required_vco == 8640)
5568 min_freq = 308570;
5569 else
5570 min_freq = 337500;
5571
5572 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5573
5574 I915_WRITE(CDCLK_CTL, val);
5575 POSTING_READ(CDCLK_CTL);
5576
5577 /*
5578 * We always enable DPLL0 with the lowest link rate possible, but still
5579 * taking into account the VCO required to operate the eDP panel at the
5580 * desired frequency. The usual DP link rates operate with a VCO of
5581 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5582 * The modeset code is responsible for the selection of the exact link
5583 * rate later on, with the constraint of choosing a frequency that
5584 * works with required_vco.
5585 */
5586 val = I915_READ(DPLL_CTRL1);
5587
5588 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5589 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5590 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5591 if (required_vco == 8640)
5592 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5593 SKL_DPLL0);
5594 else
5595 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5596 SKL_DPLL0);
5597
5598 I915_WRITE(DPLL_CTRL1, val);
5599 POSTING_READ(DPLL_CTRL1);
5600
5601 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5602
5603 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5604 DRM_ERROR("DPLL0 not locked\n");
5605}
5606
5607static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5608{
5609 int ret;
5610 u32 val;
5611
5612 /* inform PCU we want to change CDCLK */
5613 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5614 mutex_lock(&dev_priv->rps.hw_lock);
5615 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5616 mutex_unlock(&dev_priv->rps.hw_lock);
5617
5618 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5619}
5620
5621static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5622{
5623 unsigned int i;
5624
5625 for (i = 0; i < 15; i++) {
5626 if (skl_cdclk_pcu_ready(dev_priv))
5627 return true;
5628 udelay(10);
5629 }
5630
5631 return false;
5632}
5633
5634static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5635{
560a7ae4 5636 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5637 u32 freq_select, pcu_ack;
5638
5639 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5640
5641 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5642 DRM_ERROR("failed to inform PCU about cdclk change\n");
5643 return;
5644 }
5645
5646 /* set CDCLK_CTL */
5647 switch(freq) {
5648 case 450000:
5649 case 432000:
5650 freq_select = CDCLK_FREQ_450_432;
5651 pcu_ack = 1;
5652 break;
5653 case 540000:
5654 freq_select = CDCLK_FREQ_540;
5655 pcu_ack = 2;
5656 break;
5657 case 308570:
5658 case 337500:
5659 default:
5660 freq_select = CDCLK_FREQ_337_308;
5661 pcu_ack = 0;
5662 break;
5663 case 617140:
5664 case 675000:
5665 freq_select = CDCLK_FREQ_675_617;
5666 pcu_ack = 3;
5667 break;
5668 }
5669
5670 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5671 POSTING_READ(CDCLK_CTL);
5672
5673 /* inform PCU of the change */
5674 mutex_lock(&dev_priv->rps.hw_lock);
5675 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5676 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5677
5678 intel_update_cdclk(dev);
5d96d8af
DL		 5679}
5680
5681void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5682{
5683 /* disable DBUF power */
5684 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5685 POSTING_READ(DBUF_CTL);
5686
5687 udelay(10);
5688
5689 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5690 DRM_ERROR("DBuf power disable timeout\n");
5691
5692 /* disable DPLL0 */
5693 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5694 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5695 DRM_ERROR("Couldn't disable DPLL0\n");
5696
5697 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5698}
5699
5700void skl_init_cdclk(struct drm_i915_private *dev_priv)
5701{
5702 u32 val;
5703 unsigned int required_vco;
5704
5705 /* enable PCH reset handshake */
5706 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5707 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5708
5709 /* enable PG1 and Misc I/O */
5710 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5711
5712 /* DPLL0 already enabed !? */
5713 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5714 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5715 return;
5716 }
5717
5718 /* enable DPLL0 */
5719 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5720 skl_dpll0_enable(dev_priv, required_vco);
5721
5722 /* set CDCLK to the frequency the BIOS chose */
5723 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5724
5725 /* enable DBUF power */
5726 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5727 POSTING_READ(DBUF_CTL);
5728
5729 udelay(10);
5730
5731 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5732 DRM_ERROR("DBuf power enable timeout\n");
5733}
5734
dfcab17e 5735/* returns HPLL frequency in kHz */
f8bf63fd 5736static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5737{
586f49dc 5738 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5739
586f49dc 5740 /* Obtain SKU information */
a580516d 5741 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5742 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5743 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5744 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5745
dfcab17e 5746 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5747}
5748
5749/* Adjust CDclk dividers to allow high res or save power if possible */
5750static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5751{
5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753 u32 val, cmd;
5754
164dfd28
VK		 5755 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5756 != dev_priv->cdclk_freq);
d60c4473 5757
dfcab17e 5758 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5759 cmd = 2;
dfcab17e 5760 else if (cdclk == 266667)
30a970c6
JB		 5761 cmd = 1;
5762 else
5763 cmd = 0;
5764
5765 mutex_lock(&dev_priv->rps.hw_lock);
5766 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5767 val &= ~DSPFREQGUAR_MASK;
5768 val |= (cmd << DSPFREQGUAR_SHIFT);
5769 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5770 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5771 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5772 50)) {
5773 DRM_ERROR("timed out waiting for CDclk change\n");
5774 }
5775 mutex_unlock(&dev_priv->rps.hw_lock);
5776
54433e91
VS		 5777 mutex_lock(&dev_priv->sb_lock);
5778
dfcab17e 5779 if (cdclk == 400000) {
6bcda4f0 5780 u32 divider;
30a970c6 5781
6bcda4f0 5782 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5783
30a970c6
JB		 5784 /* adjust cdclk divider */
5785 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5786 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5787 val |= divider;
5788 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5789
5790 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5791 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5792 50))
5793 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5794 }
5795
30a970c6
JB		 5796 /* adjust self-refresh exit latency value */
5797 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5798 val &= ~0x7f;
5799
5800 /*
5801 * For high bandwidth configs, we set a higher latency in the bunit
5802 * so that the core display fetch happens in time to avoid underruns.
5803 */
dfcab17e 5804 if (cdclk == 400000)
30a970c6
JB		 5805 val |= 4500 / 250; /* 4.5 usec */
5806 else
5807 val |= 3000 / 250; /* 3.0 usec */
5808 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5809
a580516d 5810 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5811
b6283055 5812 intel_update_cdclk(dev);
30a970c6
JB		 5813}
5814
383c5a6a
VS		 5815static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5816{
5817 struct drm_i915_private *dev_priv = dev->dev_private;
5818 u32 val, cmd;
5819
164dfd28
VK		 5820 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5821 != dev_priv->cdclk_freq);
383c5a6a
VS		 5822
5823 switch (cdclk) {
383c5a6a
VS		 5824 case 333333:
5825 case 320000:
383c5a6a 5826 case 266667:
383c5a6a 5827 case 200000:
383c5a6a
VS		 5828 break;
5829 default:
5f77eeb0 5830 MISSING_CASE(cdclk);
383c5a6a
VS		 5831 return;
5832 }
5833
9d0d3fda
VS		 5834 /*
5835 * Specs are full of misinformation, but testing on actual
5836 * hardware has shown that we just need to write the desired
5837 * CCK divider into the Punit register.
5838 */
5839 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5840
383c5a6a
VS		 5841 mutex_lock(&dev_priv->rps.hw_lock);
5842 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5843 val &= ~DSPFREQGUAR_MASK_CHV;
5844 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5845 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5846 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5847 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5848 50)) {
5849 DRM_ERROR("timed out waiting for CDclk change\n");
5850 }
5851 mutex_unlock(&dev_priv->rps.hw_lock);
5852
b6283055 5853 intel_update_cdclk(dev);
383c5a6a
VS		 5854}
5855
30a970c6
JB		 5856static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5857 int max_pixclk)
5858{
6bcda4f0 5859 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5860 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5861
30a970c6
JB		 5862 /*
5863 * Really only a few cases to deal with, as only 4 CDclks are supported:
5864 * 200MHz
5865 * 267MHz
29dc7ef3 5866 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5867 * 400MHz (VLV only)
5868 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5869 * of the lower bin and adjust if needed.
e37c67a1
VS		 5870 *
5871 * We seem to get an unstable or solid color picture at 200MHz.
5872 * Not sure what's wrong. For now use 200MHz only when all pipes
5873 * are off.
30a970c6 5874 */
6cca3195
VS		 5875 if (!IS_CHERRYVIEW(dev_priv) &&
5876 max_pixclk > freq_320*limit/100)
dfcab17e 5877 return 400000;
6cca3195 5878 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5879 return freq_320;
e37c67a1 5880 else if (max_pixclk > 0)
dfcab17e 5881 return 266667;
e37c67a1
VS		 5882 else
5883 return 200000;
30a970c6
JB		 5884}
5885
f8437dd1
VK		 5886static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5887 int max_pixclk)
5888{
5889 /*
5890 * FIXME:
5891 * - remove the guardband, it's not needed on BXT
5892 * - set 19.2MHz bypass frequency if there are no active pipes
5893 */
5894 if (max_pixclk > 576000*9/10)
5895 return 624000;
5896 else if (max_pixclk > 384000*9/10)
5897 return 576000;
5898 else if (max_pixclk > 288000*9/10)
5899 return 384000;
5900 else if (max_pixclk > 144000*9/10)
5901 return 288000;
5902 else
5903 return 144000;
5904}
5905
a821fc46
ACO		 5906/* Compute the max pixel clock for new configuration. Uses atomic state if
5907 * that's non-NULL, look at current state otherwise. */
5908static int intel_mode_max_pixclk(struct drm_device *dev,
5909 struct drm_atomic_state *state)
30a970c6 5910{
30a970c6 5911 struct intel_crtc *intel_crtc;
304603f4 5912 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5913 int max_pixclk = 0;
5914
d3fcc808 5915 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5916 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5917 if (IS_ERR(crtc_state))
5918 return PTR_ERR(crtc_state);
5919
5920 if (!crtc_state->base.enable)
5921 continue;
5922
5923 max_pixclk = max(max_pixclk,
5924 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5925 }
5926
5927 return max_pixclk;
5928}
5929
27c329ed 5930static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5931{
27c329ed
ML		 5932 struct drm_device *dev = state->dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5935
304603f4
ACO		 5936 if (max_pixclk < 0)
5937 return max_pixclk;
30a970c6 5938
27c329ed
ML		 5939 to_intel_atomic_state(state)->cdclk =
5940 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5941
27c329ed
ML		 5942 return 0;
5943}
304603f4 5944
27c329ed
ML		 5945static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5946{
5947 struct drm_device *dev = state->dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5950
27c329ed
ML		 5951 if (max_pixclk < 0)
5952 return max_pixclk;
85a96e7a 5953
27c329ed
ML		 5954 to_intel_atomic_state(state)->cdclk =
5955 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5956
27c329ed 5957 return 0;
30a970c6
JB		 5958}
5959
1e69cd74
VS		 5960static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5961{
5962 unsigned int credits, default_credits;
5963
5964 if (IS_CHERRYVIEW(dev_priv))
5965 default_credits = PFI_CREDIT(12);
5966 else
5967 default_credits = PFI_CREDIT(8);
5968
164dfd28 5969 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5970 /* CHV suggested value is 31 or 63 */
5971 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5972 credits = PFI_CREDIT_63;
1e69cd74
VS		 5973 else
5974 credits = PFI_CREDIT(15);
5975 } else {
5976 credits = default_credits;
5977 }
5978
5979 /*
5980 * WA - write default credits before re-programming
5981 * FIXME: should we also set the resend bit here?
5982 */
5983 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5984 default_credits);
5985
5986 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5987 credits | PFI_CREDIT_RESEND);
5988
5989 /*
5990 * FIXME is this guaranteed to clear
5991 * immediately or should we poll for it?
5992 */
5993 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5994}
5995
27c329ed 5996static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5997{
a821fc46 5998 struct drm_device *dev = old_state->dev;
27c329ed 5999 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6000 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6001
27c329ed
ML		 6002 /*
6003 * FIXME: We can end up here with all power domains off, yet
6004 * with a CDCLK frequency other than the minimum. To account
6005 * for this take the PIPE-A power domain, which covers the HW
6006 * blocks needed for the following programming. This can be
6007 * removed once it's guaranteed that we get here either with
6008 * the minimum CDCLK set, or the required power domains
6009 * enabled.
6010 */
6011 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6012
27c329ed
ML		 6013 if (IS_CHERRYVIEW(dev))
6014 cherryview_set_cdclk(dev, req_cdclk);
6015 else
6016 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6017
27c329ed 6018 vlv_program_pfi_credits(dev_priv);
1e69cd74 6019
27c329ed 6020 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6021}
6022
89b667f8
JB		 6023static void valleyview_crtc_enable(struct drm_crtc *crtc)
6024{
6025 struct drm_device *dev = crtc->dev;
a72e4c9f 6026 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6028 struct intel_encoder *encoder;
6029 int pipe = intel_crtc->pipe;
23538ef1 6030 bool is_dsi;
89b667f8 6031
53d9f4e9 6032 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6033 return;
6034
409ee761 6035 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6036
1ae0d137
VS		 6037 if (!is_dsi) {
6038 if (IS_CHERRYVIEW(dev))
6e3c9717 6039 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6040 else
6e3c9717 6041 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6042 }
5b18e57c 6043
6e3c9717 6044 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6045 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6046
6047 intel_set_pipe_timings(intel_crtc);
6048
c14b0485
VS		 6049 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051
6052 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6053 I915_WRITE(CHV_CANVAS(pipe), 0);
6054 }
6055
5b18e57c
DV		 6056 i9xx_set_pipeconf(intel_crtc);
6057
89b667f8 6058 intel_crtc->active = true;
89b667f8 6059
a72e4c9f 6060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6061
89b667f8
JB		 6062 for_each_encoder_on_crtc(dev, crtc, encoder)
6063 if (encoder->pre_pll_enable)
6064 encoder->pre_pll_enable(encoder);
6065
9d556c99
CML		 6066 if (!is_dsi) {
6067 if (IS_CHERRYVIEW(dev))
6e3c9717 6068 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6069 else
6e3c9717 6070 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6071 }
89b667f8
JB		 6072
6073 for_each_encoder_on_crtc(dev, crtc, encoder)
6074 if (encoder->pre_enable)
6075 encoder->pre_enable(encoder);
6076
2dd24552
JB		 6077 i9xx_pfit_enable(intel_crtc);
6078
63cbb074
VS		 6079 intel_crtc_load_lut(crtc);
6080
e1fdc473 6081 intel_enable_pipe(intel_crtc);
be6a6f8e 6082
4b3a9526
VS		 6083 assert_vblank_disabled(crtc);
6084 drm_crtc_vblank_on(crtc);
6085
f9b61ff6
DV		 6086 for_each_encoder_on_crtc(dev, crtc, encoder)
6087 encoder->enable(encoder);
89b667f8
JB		 6088}
6089
f13c2ef3
DV		 6090static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6091{
6092 struct drm_device *dev = crtc->base.dev;
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094
6e3c9717
ACO		 6095 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6096 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6097}
6098
0b8765c6 6099static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6100{
6101 struct drm_device *dev = crtc->dev;
a72e4c9f 6102 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6104 struct intel_encoder *encoder;
79e53945 6105 int pipe = intel_crtc->pipe;
79e53945 6106
53d9f4e9 6107 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6108 return;
6109
f13c2ef3
DV		 6110 i9xx_set_pll_dividers(intel_crtc);
6111
6e3c9717 6112 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6113 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6114
6115 intel_set_pipe_timings(intel_crtc);
6116
5b18e57c
DV		 6117 i9xx_set_pipeconf(intel_crtc);
6118
f7abfe8b 6119 intel_crtc->active = true;
6b383a7f 6120
4a3436e8 6121 if (!IS_GEN2(dev))
a72e4c9f 6122 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6123
9d6d9f19
MK		 6124 for_each_encoder_on_crtc(dev, crtc, encoder)
6125 if (encoder->pre_enable)
6126 encoder->pre_enable(encoder);
6127
f6736a1a
DV		 6128 i9xx_enable_pll(intel_crtc);
6129
2dd24552
JB		 6130 i9xx_pfit_enable(intel_crtc);
6131
63cbb074
VS		 6132 intel_crtc_load_lut(crtc);
6133
f37fcc2a 6134 intel_update_watermarks(crtc);
e1fdc473 6135 intel_enable_pipe(intel_crtc);
be6a6f8e 6136
4b3a9526
VS		 6137 assert_vblank_disabled(crtc);
6138 drm_crtc_vblank_on(crtc);
6139
f9b61ff6
DV		 6140 for_each_encoder_on_crtc(dev, crtc, encoder)
6141 encoder->enable(encoder);
0b8765c6 6142}
79e53945 6143
87476d63
DV		 6144static void i9xx_pfit_disable(struct intel_crtc *crtc)
6145{
6146 struct drm_device *dev = crtc->base.dev;
6147 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6148
6e3c9717 6149 if (!crtc->config->gmch_pfit.control)
328d8e82 6150 return;
87476d63 6151
328d8e82 6152 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6153
328d8e82
DV		 6154 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6155 I915_READ(PFIT_CONTROL));
6156 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6157}
6158
0b8765c6
JB		 6159static void i9xx_crtc_disable(struct drm_crtc *crtc)
6160{
6161 struct drm_device *dev = crtc->dev;
6162 struct drm_i915_private *dev_priv = dev->dev_private;
6163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6164 struct intel_encoder *encoder;
0b8765c6 6165 int pipe = intel_crtc->pipe;
ef9c3aee 6166
6304cd91
VS		 6167 /*
6168 * On gen2 planes are double buffered but the pipe isn't, so we must
6169 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6170 * We also need to wait on all gmch platforms because of the
6171 * self-refresh mode constraint explained above.
6304cd91 6172 */
564ed191 6173 intel_wait_for_vblank(dev, pipe);
6304cd91 6174
4b3a9526
VS		 6175 for_each_encoder_on_crtc(dev, crtc, encoder)
6176 encoder->disable(encoder);
6177
f9b61ff6
DV		 6178 drm_crtc_vblank_off(crtc);
6179 assert_vblank_disabled(crtc);
6180
575f7ab7 6181 intel_disable_pipe(intel_crtc);
24a1f16d 6182
87476d63 6183 i9xx_pfit_disable(intel_crtc);
24a1f16d 6184
89b667f8
JB		 6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 if (encoder->post_disable)
6187 encoder->post_disable(encoder);
6188
409ee761 6189 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6190 if (IS_CHERRYVIEW(dev))
6191 chv_disable_pll(dev_priv, pipe);
6192 else if (IS_VALLEYVIEW(dev))
6193 vlv_disable_pll(dev_priv, pipe);
6194 else
1c4e0274 6195 i9xx_disable_pll(intel_crtc);
076ed3b2 6196 }
0b8765c6 6197
4a3436e8 6198 if (!IS_GEN2(dev))
a72e4c9f 6199 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6200
6201 intel_crtc->active = false;
6202 intel_update_watermarks(crtc);
0b8765c6
JB		 6203}
6204
b17d48e2
ML		 6205static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6206{
6207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6208 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6209 enum intel_display_power_domain domain;
6210 unsigned long domains;
6211
6212 if (!intel_crtc->active)
6213 return;
6214
a539205a
ML		 6215 if (to_intel_plane_state(crtc->primary->state)->visible) {
6216 intel_crtc_wait_for_pending_flips(crtc);
6217 intel_pre_disable_primary(crtc);
6218 }
6219
d032ffa0 6220 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6221 dev_priv->display.crtc_disable(crtc);
1f7457b1 6222 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6223
6224 domains = intel_crtc->enabled_power_domains;
6225 for_each_power_domain(domain, domains)
6226 intel_display_power_put(dev_priv, domain);
6227 intel_crtc->enabled_power_domains = 0;
6228}
6229
6b72d486
ML		 6230/*
6231 * turn all crtc's off, but do not adjust state
6232 * This has to be paired with a call to intel_modeset_setup_hw_state.
6233 */
70e0bd74 6234int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6235{
70e0bd74
ML		 6236 struct drm_mode_config *config = &dev->mode_config;
6237 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6238 struct drm_atomic_state *state;
6b72d486 6239 struct drm_crtc *crtc;
70e0bd74
ML		 6240 unsigned crtc_mask = 0;
6241 int ret = 0;
6242
6243 if (WARN_ON(!ctx))
6244 return 0;
6245
6246 lockdep_assert_held(&ctx->ww_ctx);
6247 state = drm_atomic_state_alloc(dev);
6248 if (WARN_ON(!state))
6249 return -ENOMEM;
6250
6251 state->acquire_ctx = ctx;
6252 state->allow_modeset = true;
6253
6254 for_each_crtc(dev, crtc) {
6255 struct drm_crtc_state *crtc_state =
6256 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6257
70e0bd74
ML		 6258 ret = PTR_ERR_OR_ZERO(crtc_state);
6259 if (ret)
6260 goto free;
6261
6262 if (!crtc_state->active)
6263 continue;
6264
6265 crtc_state->active = false;
6266 crtc_mask |= 1 << drm_crtc_index(crtc);
6267 }
6268
6269 if (crtc_mask) {
74c090b1 6270 ret = drm_atomic_commit(state);
70e0bd74
ML		 6271
6272 if (!ret) {
6273 for_each_crtc(dev, crtc)
6274 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6275 crtc->state->active = true;
6276
6277 return ret;
6278 }
6279 }
6280
6281free:
6282 if (ret)
6283 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6284 drm_atomic_state_free(state);
6285 return ret;
ee7b9f93
JB		 6286}
6287
ea5b213a 6288void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6289{
4ef69c7a 6290 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6291
ea5b213a
CW		 6292 drm_encoder_cleanup(encoder);
6293 kfree(intel_encoder);
7e7d76c3
JB		 6294}
6295
0a91ca29
DV		 6296/* Cross check the actual hw state with our own modeset state tracking (and it's
6297 * internal consistency). */
b980514c 6298static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6299{
35dd3c64
ML		 6300 struct drm_crtc *crtc = connector->base.state->crtc;
6301
6302 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6303 connector->base.base.id,
6304 connector->base.name);
6305
0a91ca29 6306 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6307 struct drm_encoder *encoder = &connector->encoder->base;
6308 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6309
35dd3c64
ML		 6310 I915_STATE_WARN(!crtc,
6311 "connector enabled without attached crtc\n");
0a91ca29 6312
35dd3c64
ML		 6313 if (!crtc)
6314 return;
6315
6316 I915_STATE_WARN(!crtc->state->active,
6317 "connector is active, but attached crtc isn't\n");
6318
6319 if (!encoder)
6320 return;
6321
6322 I915_STATE_WARN(conn_state->best_encoder != encoder,
6323 "atomic encoder doesn't match attached encoder\n");
6324
6325 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6326 "attached encoder crtc differs from connector crtc\n");
6327 } else {
4d688a2a
ML		 6328 I915_STATE_WARN(crtc && crtc->state->active,
6329 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6330 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6331 "best encoder set without crtc!\n");
0a91ca29 6332 }
79e53945
JB		 6333}
6334
08d9bc92
ACO		 6335int intel_connector_init(struct intel_connector *connector)
6336{
6337 struct drm_connector_state *connector_state;
6338
6339 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6340 if (!connector_state)
6341 return -ENOMEM;
6342
6343 connector->base.state = connector_state;
6344 return 0;
6345}
6346
6347struct intel_connector *intel_connector_alloc(void)
6348{
6349 struct intel_connector *connector;
6350
6351 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6352 if (!connector)
6353 return NULL;
6354
6355 if (intel_connector_init(connector) < 0) {
6356 kfree(connector);
6357 return NULL;
6358 }
6359
6360 return connector;
6361}
6362
f0947c37
DV		 6363/* Simple connector->get_hw_state implementation for encoders that support only
6364 * one connector and no cloning and hence the encoder state determines the state
6365 * of the connector. */
6366bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6367{
24929352 6368 enum pipe pipe = 0;
f0947c37 6369 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6370
f0947c37 6371 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6372}
6373
6d293983 6374static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6375{
6d293983
ACO		 6376 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6377 return crtc_state->fdi_lanes;
d272ddfa
VS		 6378
6379 return 0;
6380}
6381
6d293983 6382static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6383 struct intel_crtc_state *pipe_config)
1857e1da 6384{
6d293983
ACO		 6385 struct drm_atomic_state *state = pipe_config->base.state;
6386 struct intel_crtc *other_crtc;
6387 struct intel_crtc_state *other_crtc_state;
6388
1857e1da
DV		 6389 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6390 pipe_name(pipe), pipe_config->fdi_lanes);
6391 if (pipe_config->fdi_lanes > 4) {
6392 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6393 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6394 return -EINVAL;
1857e1da
DV		 6395 }
6396
bafb6553 6397 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6398 if (pipe_config->fdi_lanes > 2) {
6399 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6400 pipe_config->fdi_lanes);
6d293983 6401 return -EINVAL;
1857e1da 6402 } else {
6d293983 6403 return 0;
1857e1da
DV		 6404 }
6405 }
6406
6407 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6408 return 0;
1857e1da
DV		 6409
6410 /* Ivybridge 3 pipe is really complicated */
6411 switch (pipe) {
6412 case PIPE_A:
6d293983 6413 return 0;
1857e1da 6414 case PIPE_B:
6d293983
ACO		 6415 if (pipe_config->fdi_lanes <= 2)
6416 return 0;
6417
6418 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6419 other_crtc_state =
6420 intel_atomic_get_crtc_state(state, other_crtc);
6421 if (IS_ERR(other_crtc_state))
6422 return PTR_ERR(other_crtc_state);
6423
6424 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6425 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6426 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6427 return -EINVAL;
1857e1da 6428 }
6d293983 6429 return 0;
1857e1da 6430 case PIPE_C:
251cc67c
VS		 6431 if (pipe_config->fdi_lanes > 2) {
6432 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6433 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6434 return -EINVAL;
251cc67c 6435 }
6d293983
ACO		 6436
6437 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6438 other_crtc_state =
6439 intel_atomic_get_crtc_state(state, other_crtc);
6440 if (IS_ERR(other_crtc_state))
6441 return PTR_ERR(other_crtc_state);
6442
6443 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6444 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6445 return -EINVAL;
1857e1da 6446 }
6d293983 6447 return 0;
1857e1da
DV		 6448 default:
6449 BUG();
6450 }
6451}
6452
e29c22c0
DV		 6453#define RETRY 1
6454static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6455 struct intel_crtc_state *pipe_config)
877d48d5 6456{
1857e1da 6457 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6458 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6459 int lane, link_bw, fdi_dotclock, ret;
6460 bool needs_recompute = false;
877d48d5 6461
e29c22c0 6462retry:
877d48d5
DV		 6463 /* FDI is a binary signal running at ~2.7GHz, encoding
6464 * each output octet as 10 bits. The actual frequency
6465 * is stored as a divider into a 100MHz clock, and the
6466 * mode pixel clock is stored in units of 1KHz.
6467 * Hence the bw of each lane in terms of the mode signal
6468 * is:
6469 */
6470 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6471
241bfc38 6472 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6473
2bd89a07 6474 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6475 pipe_config->pipe_bpp);
6476
6477 pipe_config->fdi_lanes = lane;
6478
2bd89a07 6479 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6480 link_bw, &pipe_config->fdi_m_n);
1857e1da 6481
6d293983
ACO		 6482 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6483 intel_crtc->pipe, pipe_config);
6484 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6485 pipe_config->pipe_bpp -= 2*3;
6486 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6487 pipe_config->pipe_bpp);
6488 needs_recompute = true;
6489 pipe_config->bw_constrained = true;
6490
6491 goto retry;
6492 }
6493
6494 if (needs_recompute)
6495 return RETRY;
6496
6d293983 6497 return ret;
877d48d5
DV		 6498}
6499
8cfb3407
VS		 6500static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6501 struct intel_crtc_state *pipe_config)
6502{
6503 if (pipe_config->pipe_bpp > 24)
6504 return false;
6505
6506 /* HSW can handle pixel rate up to cdclk? */
6507 if (IS_HASWELL(dev_priv->dev))
6508 return true;
6509
6510 /*
b432e5cf
VS		 6511 * We compare against max which means we must take
6512 * the increased cdclk requirement into account when
6513 * calculating the new cdclk.
6514 *
6515 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6516 */
6517 return ilk_pipe_pixel_rate(pipe_config) <=
6518 dev_priv->max_cdclk_freq * 95 / 100;
6519}
6520
42db64ef 6521static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6522 struct intel_crtc_state *pipe_config)
42db64ef 6523{
8cfb3407
VS		 6524 struct drm_device *dev = crtc->base.dev;
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526
d330a953 6527 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6528 hsw_crtc_supports_ips(crtc) &&
6529 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6530}
6531
a43f6e0f 6532static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6533 struct intel_crtc_state *pipe_config)
79e53945 6534{
a43f6e0f 6535 struct drm_device *dev = crtc->base.dev;
8bd31e67 6536 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6537 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6538
ad3a4479 6539 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6540 if (INTEL_INFO(dev)->gen < 4) {
44913155 6541 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6542
6543 /*
6544 * Enable pixel doubling when the dot clock
6545 * is > 90% of the (display) core speed.
6546 *
b397c96b
VS		 6547 * GDG double wide on either pipe,
6548 * otherwise pipe A only.
cf532bb2 6549 */
b397c96b 6550 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6551 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6552 clock_limit *= 2;
cf532bb2 6553 pipe_config->double_wide = true;
ad3a4479
VS		 6554 }
6555
241bfc38 6556 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6557 return -EINVAL;
2c07245f 6558 }
89749350 6559
1d1d0e27
VS		 6560 /*
6561 * Pipe horizontal size must be even in:
6562 * - DVO ganged mode
6563 * - LVDS dual channel mode
6564 * - Double wide pipe
6565 */
a93e255f 6566 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6567 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6568 pipe_config->pipe_src_w &= ~1;
6569
8693a824
DL		 6570 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6571 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6572 */
6573 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6574 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6575 return -EINVAL;
44f46b42 6576
f5adf94e 6577 if (HAS_IPS(dev))
a43f6e0f
DV		 6578 hsw_compute_ips_config(crtc, pipe_config);
6579
877d48d5 6580 if (pipe_config->has_pch_encoder)
a43f6e0f 6581 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6582
cf5a15be 6583 return 0;
79e53945
JB		 6584}
6585
1652d19e
VS		 6586static int skylake_get_display_clock_speed(struct drm_device *dev)
6587{
6588 struct drm_i915_private *dev_priv = to_i915(dev);
6589 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6590 uint32_t cdctl = I915_READ(CDCLK_CTL);
6591 uint32_t linkrate;
6592
414355a7 6593 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6594 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6595
6596 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6597 return 540000;
6598
6599 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6600 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6601
71cd8423
DL		 6602 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6603 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6604 /* vco 8640 */
6605 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6606 case CDCLK_FREQ_450_432:
6607 return 432000;
6608 case CDCLK_FREQ_337_308:
6609 return 308570;
6610 case CDCLK_FREQ_675_617:
6611 return 617140;
6612 default:
6613 WARN(1, "Unknown cd freq selection\n");
6614 }
6615 } else {
6616 /* vco 8100 */
6617 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6618 case CDCLK_FREQ_450_432:
6619 return 450000;
6620 case CDCLK_FREQ_337_308:
6621 return 337500;
6622 case CDCLK_FREQ_675_617:
6623 return 675000;
6624 default:
6625 WARN(1, "Unknown cd freq selection\n");
6626 }
6627 }
6628
6629 /* error case, do as if DPLL0 isn't enabled */
6630 return 24000;
6631}
6632
acd3f3d3
BP		 6633static int broxton_get_display_clock_speed(struct drm_device *dev)
6634{
6635 struct drm_i915_private *dev_priv = to_i915(dev);
6636 uint32_t cdctl = I915_READ(CDCLK_CTL);
6637 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6638 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6639 int cdclk;
6640
6641 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6642 return 19200;
6643
6644 cdclk = 19200 * pll_ratio / 2;
6645
6646 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6647 case BXT_CDCLK_CD2X_DIV_SEL_1:
6648 return cdclk; /* 576MHz or 624MHz */
6649 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6650 return cdclk * 2 / 3; /* 384MHz */
6651 case BXT_CDCLK_CD2X_DIV_SEL_2:
6652 return cdclk / 2; /* 288MHz */
6653 case BXT_CDCLK_CD2X_DIV_SEL_4:
6654 return cdclk / 4; /* 144MHz */
6655 }
6656
6657 /* error case, do as if DE PLL isn't enabled */
6658 return 19200;
6659}
6660
1652d19e
VS		 6661static int broadwell_get_display_clock_speed(struct drm_device *dev)
6662{
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 uint32_t lcpll = I915_READ(LCPLL_CTL);
6665 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6666
6667 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6668 return 800000;
6669 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6670 return 450000;
6671 else if (freq == LCPLL_CLK_FREQ_450)
6672 return 450000;
6673 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6674 return 540000;
6675 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6676 return 337500;
6677 else
6678 return 675000;
6679}
6680
6681static int haswell_get_display_clock_speed(struct drm_device *dev)
6682{
6683 struct drm_i915_private *dev_priv = dev->dev_private;
6684 uint32_t lcpll = I915_READ(LCPLL_CTL);
6685 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6686
6687 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6688 return 800000;
6689 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6690 return 450000;
6691 else if (freq == LCPLL_CLK_FREQ_450)
6692 return 450000;
6693 else if (IS_HSW_ULT(dev))
6694 return 337500;
6695 else
6696 return 540000;
79e53945
JB		 6697}
6698
25eb05fc
JB		 6699static int valleyview_get_display_clock_speed(struct drm_device *dev)
6700{
d197b7d3 6701 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6702 u32 val;
6703 int divider;
6704
6bcda4f0
VS		 6705 if (dev_priv->hpll_freq == 0)
6706 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6707
a580516d 6708 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6709 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6710 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6711
6712 divider = val & DISPLAY_FREQUENCY_VALUES;
6713
7d007f40
VS		 6714 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6715 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6716 "cdclk change in progress\n");
6717
6bcda4f0 6718 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6719}
6720
b37a6434
VS		 6721static int ilk_get_display_clock_speed(struct drm_device *dev)
6722{
6723 return 450000;
6724}
6725
e70236a8
JB		 6726static int i945_get_display_clock_speed(struct drm_device *dev)
6727{
6728 return 400000;
6729}
79e53945 6730
e70236a8 6731static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6732{
e907f170 6733 return 333333;
e70236a8 6734}
79e53945 6735
e70236a8
JB		 6736static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6737{
6738 return 200000;
6739}
79e53945 6740
257a7ffc
DV		 6741static int pnv_get_display_clock_speed(struct drm_device *dev)
6742{
6743 u16 gcfgc = 0;
6744
6745 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6746
6747 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6748 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6749 return 266667;
257a7ffc 6750 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6751 return 333333;
257a7ffc 6752 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6753 return 444444;
257a7ffc
DV		 6754 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6755 return 200000;
6756 default:
6757 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6758 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6759 return 133333;
257a7ffc 6760 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6761 return 166667;
257a7ffc
DV		 6762 }
6763}
6764
e70236a8
JB		 6765static int i915gm_get_display_clock_speed(struct drm_device *dev)
6766{
6767 u16 gcfgc = 0;
79e53945 6768
e70236a8
JB		 6769 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6770
6771 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6772 return 133333;
e70236a8
JB		 6773 else {
6774 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6775 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6776 return 333333;
e70236a8
JB		 6777 default:
6778 case GC_DISPLAY_CLOCK_190_200_MHZ:
6779 return 190000;
79e53945 6780 }
e70236a8
JB		 6781 }
6782}
6783
6784static int i865_get_display_clock_speed(struct drm_device *dev)
6785{
e907f170 6786 return 266667;
e70236a8
JB		 6787}
6788
1b1d2716 6789static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6790{
6791 u16 hpllcc = 0;
1b1d2716 6792
65cd2b3f
VS		 6793 /*
6794 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6795 * encoding is different :(
6796 * FIXME is this the right way to detect 852GM/852GMV?
6797 */
6798 if (dev->pdev->revision == 0x1)
6799 return 133333;
6800
1b1d2716
VS		 6801 pci_bus_read_config_word(dev->pdev->bus,
6802 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6803
e70236a8
JB		 6804 /* Assume that the hardware is in the high speed state. This
6805 * should be the default.
6806 */
6807 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6808 case GC_CLOCK_133_200:
1b1d2716 6809 case GC_CLOCK_133_200_2:
e70236a8
JB		 6810 case GC_CLOCK_100_200:
6811 return 200000;
6812 case GC_CLOCK_166_250:
6813 return 250000;
6814 case GC_CLOCK_100_133:
e907f170 6815 return 133333;
1b1d2716
VS		 6816 case GC_CLOCK_133_266:
6817 case GC_CLOCK_133_266_2:
6818 case GC_CLOCK_166_266:
6819 return 266667;
e70236a8 6820 }
79e53945 6821
e70236a8
JB		 6822 /* Shouldn't happen */
6823 return 0;
6824}
79e53945 6825
e70236a8
JB		 6826static int i830_get_display_clock_speed(struct drm_device *dev)
6827{
e907f170 6828 return 133333;
79e53945
JB		 6829}
6830
34edce2f
VS		 6831static unsigned int intel_hpll_vco(struct drm_device *dev)
6832{
6833 struct drm_i915_private *dev_priv = dev->dev_private;
6834 static const unsigned int blb_vco[8] = {
6835 [0] = 3200000,
6836 [1] = 4000000,
6837 [2] = 5333333,
6838 [3] = 4800000,
6839 [4] = 6400000,
6840 };
6841 static const unsigned int pnv_vco[8] = {
6842 [0] = 3200000,
6843 [1] = 4000000,
6844 [2] = 5333333,
6845 [3] = 4800000,
6846 [4] = 2666667,
6847 };
6848 static const unsigned int cl_vco[8] = {
6849 [0] = 3200000,
6850 [1] = 4000000,
6851 [2] = 5333333,
6852 [3] = 6400000,
6853 [4] = 3333333,
6854 [5] = 3566667,
6855 [6] = 4266667,
6856 };
6857 static const unsigned int elk_vco[8] = {
6858 [0] = 3200000,
6859 [1] = 4000000,
6860 [2] = 5333333,
6861 [3] = 4800000,
6862 };
6863 static const unsigned int ctg_vco[8] = {
6864 [0] = 3200000,
6865 [1] = 4000000,
6866 [2] = 5333333,
6867 [3] = 6400000,
6868 [4] = 2666667,
6869 [5] = 4266667,
6870 };
6871 const unsigned int *vco_table;
6872 unsigned int vco;
6873 uint8_t tmp = 0;
6874
6875 /* FIXME other chipsets? */
6876 if (IS_GM45(dev))
6877 vco_table = ctg_vco;
6878 else if (IS_G4X(dev))
6879 vco_table = elk_vco;
6880 else if (IS_CRESTLINE(dev))
6881 vco_table = cl_vco;
6882 else if (IS_PINEVIEW(dev))
6883 vco_table = pnv_vco;
6884 else if (IS_G33(dev))
6885 vco_table = blb_vco;
6886 else
6887 return 0;
6888
6889 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6890
6891 vco = vco_table[tmp & 0x7];
6892 if (vco == 0)
6893 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6894 else
6895 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6896
6897 return vco;
6898}
6899
6900static int gm45_get_display_clock_speed(struct drm_device *dev)
6901{
6902 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6903 uint16_t tmp = 0;
6904
6905 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6906
6907 cdclk_sel = (tmp >> 12) & 0x1;
6908
6909 switch (vco) {
6910 case 2666667:
6911 case 4000000:
6912 case 5333333:
6913 return cdclk_sel ? 333333 : 222222;
6914 case 3200000:
6915 return cdclk_sel ? 320000 : 228571;
6916 default:
6917 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6918 return 222222;
6919 }
6920}
6921
6922static int i965gm_get_display_clock_speed(struct drm_device *dev)
6923{
6924 static const uint8_t div_3200[] = { 16, 10, 8 };
6925 static const uint8_t div_4000[] = { 20, 12, 10 };
6926 static const uint8_t div_5333[] = { 24, 16, 14 };
6927 const uint8_t *div_table;
6928 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6929 uint16_t tmp = 0;
6930
6931 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6932
6933 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6934
6935 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6936 goto fail;
6937
6938 switch (vco) {
6939 case 3200000:
6940 div_table = div_3200;
6941 break;
6942 case 4000000:
6943 div_table = div_4000;
6944 break;
6945 case 5333333:
6946 div_table = div_5333;
6947 break;
6948 default:
6949 goto fail;
6950 }
6951
6952 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6953
caf4e252 6954fail:
34edce2f
VS		 6955 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6956 return 200000;
6957}
6958
6959static int g33_get_display_clock_speed(struct drm_device *dev)
6960{
6961 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6962 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6963 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6964 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6965 const uint8_t *div_table;
6966 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6967 uint16_t tmp = 0;
6968
6969 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6970
6971 cdclk_sel = (tmp >> 4) & 0x7;
6972
6973 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6974 goto fail;
6975
6976 switch (vco) {
6977 case 3200000:
6978 div_table = div_3200;
6979 break;
6980 case 4000000:
6981 div_table = div_4000;
6982 break;
6983 case 4800000:
6984 div_table = div_4800;
6985 break;
6986 case 5333333:
6987 div_table = div_5333;
6988 break;
6989 default:
6990 goto fail;
6991 }
6992
6993 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6994
caf4e252 6995fail:
34edce2f
VS		 6996 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6997 return 190476;
6998}
6999
2c07245f 7000static void
a65851af 7001intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7002{
a65851af
VS		 7003 while (*num > DATA_LINK_M_N_MASK ||
7004 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7005 *num >>= 1;
7006 *den >>= 1;
7007 }
7008}
7009
a65851af
VS		 7010static void compute_m_n(unsigned int m, unsigned int n,
7011 uint32_t *ret_m, uint32_t *ret_n)
7012{
7013 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7014 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7015 intel_reduce_m_n_ratio(ret_m, ret_n);
7016}
7017
e69d0bc1
DV		 7018void
7019intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7020 int pixel_clock, int link_clock,
7021 struct intel_link_m_n *m_n)
2c07245f 7022{
e69d0bc1 7023 m_n->tu = 64;
a65851af
VS		 7024
7025 compute_m_n(bits_per_pixel * pixel_clock,
7026 link_clock * nlanes * 8,
7027 &m_n->gmch_m, &m_n->gmch_n);
7028
7029 compute_m_n(pixel_clock, link_clock,
7030 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7031}
7032
a7615030
CW		 7033static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7034{
d330a953
JN		 7035 if (i915.panel_use_ssc >= 0)
7036 return i915.panel_use_ssc != 0;
41aa3448 7037 return dev_priv->vbt.lvds_use_ssc
435793df 7038 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7039}
7040
a93e255f
ACO		 7041static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7042 int num_connectors)
c65d77d8 7043{
a93e255f 7044 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7045 struct drm_i915_private *dev_priv = dev->dev_private;
7046 int refclk;
7047
a93e255f
ACO		 7048 WARN_ON(!crtc_state->base.state);
7049
5ab7b0b7 7050 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7051 refclk = 100000;
a93e255f 7052 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7053 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7054 refclk = dev_priv->vbt.lvds_ssc_freq;
7055 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7056 } else if (!IS_GEN2(dev)) {
7057 refclk = 96000;
7058 } else {
7059 refclk = 48000;
7060 }
7061
7062 return refclk;
7063}
7064
7429e9d4 7065static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7066{
7df00d7a 7067 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7068}
f47709a9 7069
7429e9d4
DV		 7070static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7071{
7072 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7073}
7074
f47709a9 7075static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7076 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7077 intel_clock_t *reduced_clock)
7078{
f47709a9 7079 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7080 u32 fp, fp2 = 0;
7081
7082 if (IS_PINEVIEW(dev)) {
190f68c5 7083 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7084 if (reduced_clock)
7429e9d4 7085 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7086 } else {
190f68c5 7087 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7088 if (reduced_clock)
7429e9d4 7089 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7090 }
7091
190f68c5 7092 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7093
f47709a9 7094 crtc->lowfreq_avail = false;
a93e255f 7095 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7096 reduced_clock) {
190f68c5 7097 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7098 crtc->lowfreq_avail = true;
a7516a05 7099 } else {
190f68c5 7100 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7101 }
7102}
7103
5e69f97f
CML		 7104static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7105 pipe)
89b667f8
JB		 7106{
7107 u32 reg_val;
7108
7109 /*
7110 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7111 * and set it to a reasonable value instead.
7112 */
ab3c759a 7113 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7114 reg_val &= 0xffffff00;
7115 reg_val |= 0x00000030;
ab3c759a 7116 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7117
ab3c759a 7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7119 reg_val &= 0x8cffffff;
7120 reg_val = 0x8c000000;
ab3c759a 7121 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7122
ab3c759a 7123 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7124 reg_val &= 0xffffff00;
ab3c759a 7125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7126
ab3c759a 7127 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7128 reg_val &= 0x00ffffff;
7129 reg_val |= 0xb0000000;
ab3c759a 7130 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7131}
7132
b551842d
DV		 7133static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7134 struct intel_link_m_n *m_n)
7135{
7136 struct drm_device *dev = crtc->base.dev;
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 int pipe = crtc->pipe;
7139
e3b95f1e
DV		 7140 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7141 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7142 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7143 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7144}
7145
7146static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7147 struct intel_link_m_n *m_n,
7148 struct intel_link_m_n *m2_n2)
b551842d
DV		 7149{
7150 struct drm_device *dev = crtc->base.dev;
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 int pipe = crtc->pipe;
6e3c9717 7153 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7154
7155 if (INTEL_INFO(dev)->gen >= 5) {
7156 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7157 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7158 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7159 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7160 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7161 * for gen < 8) and if DRRS is supported (to make sure the
7162 * registers are not unnecessarily accessed).
7163 */
44395bfe 7164 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7165 crtc->config->has_drrs) {
f769cd24
VK		 7166 I915_WRITE(PIPE_DATA_M2(transcoder),
7167 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7168 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7169 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7170 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7171 }
b551842d 7172 } else {
e3b95f1e
DV		 7173 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7174 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7175 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7176 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7177 }
7178}
7179
fe3cd48d 7180void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7181{
fe3cd48d
R		 7182 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7183
7184 if (m_n == M1_N1) {
7185 dp_m_n = &crtc->config->dp_m_n;
7186 dp_m2_n2 = &crtc->config->dp_m2_n2;
7187 } else if (m_n == M2_N2) {
7188
7189 /*
7190 * M2_N2 registers are not supported. Hence m2_n2 divider value
7191 * needs to be programmed into M1_N1.
7192 */
7193 dp_m_n = &crtc->config->dp_m2_n2;
7194 } else {
7195 DRM_ERROR("Unsupported divider value\n");
7196 return;
7197 }
7198
6e3c9717
ACO		 7199 if (crtc->config->has_pch_encoder)
7200 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7201 else
fe3cd48d 7202 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7203}
7204
251ac862
DV		 7205static void vlv_compute_dpll(struct intel_crtc *crtc,
7206 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7207{
7208 u32 dpll, dpll_md;
7209
7210 /*
7211 * Enable DPIO clock input. We should never disable the reference
7212 * clock for pipe B, since VGA hotplug / manual detection depends
7213 * on it.
7214 */
60bfe44f
VS		 7215 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7216 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7217 /* We should never disable this, set it here for state tracking */
7218 if (crtc->pipe == PIPE_B)
7219 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7220 dpll |= DPLL_VCO_ENABLE;
d288f65f 7221 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7222
d288f65f 7223 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7224 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7225 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7226}
7227
d288f65f 7228static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7229 const struct intel_crtc_state *pipe_config)
a0c4da24 7230{
f47709a9 7231 struct drm_device *dev = crtc->base.dev;
a0c4da24 7232 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7233 int pipe = crtc->pipe;
bdd4b6a6 7234 u32 mdiv;
a0c4da24 7235 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7236 u32 coreclk, reg_val;
a0c4da24 7237
a580516d 7238 mutex_lock(&dev_priv->sb_lock);
09153000 7239
d288f65f
VS		 7240 bestn = pipe_config->dpll.n;
7241 bestm1 = pipe_config->dpll.m1;
7242 bestm2 = pipe_config->dpll.m2;
7243 bestp1 = pipe_config->dpll.p1;
7244 bestp2 = pipe_config->dpll.p2;
a0c4da24 7245
89b667f8
JB		 7246 /* See eDP HDMI DPIO driver vbios notes doc */
7247
7248 /* PLL B needs special handling */
bdd4b6a6 7249 if (pipe == PIPE_B)
5e69f97f 7250 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7251
7252 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7253 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7254
7255 /* Disable target IRef on PLL */
ab3c759a 7256 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7257 reg_val &= 0x00ffffff;
ab3c759a 7258 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7259
7260 /* Disable fast lock */
ab3c759a 7261 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7262
7263 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7264 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7265 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7266 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7267 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7268
7269 /*
7270 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7271 * but we don't support that).
7272 * Note: don't use the DAC post divider as it seems unstable.
7273 */
7274 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7276
a0c4da24 7277 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7279
89b667f8 7280 /* Set HBR and RBR LPF coefficients */
d288f65f 7281 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7283 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7285 0x009f0003);
89b667f8 7286 else
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7288 0x00d0000f);
7289
681a8504 7290 if (pipe_config->has_dp_encoder) {
89b667f8 7291 /* Use SSC source */
bdd4b6a6 7292 if (pipe == PIPE_A)
ab3c759a 7293 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7294 0x0df40000);
7295 else
ab3c759a 7296 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7297 0x0df70000);
7298 } else { /* HDMI or VGA */
7299 /* Use bend source */
bdd4b6a6 7300 if (pipe == PIPE_A)
ab3c759a 7301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7302 0x0df70000);
7303 else
ab3c759a 7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7305 0x0df40000);
7306 }
a0c4da24 7307
ab3c759a 7308 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7309 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7310 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7311 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7312 coreclk |= 0x01000000;
ab3c759a 7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7314
ab3c759a 7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7316 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7317}
7318
251ac862
DV		 7319static void chv_compute_dpll(struct intel_crtc *crtc,
7320 struct intel_crtc_state *pipe_config)
1ae0d137 7321{
60bfe44f
VS		 7322 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7323 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7324 DPLL_VCO_ENABLE;
7325 if (crtc->pipe != PIPE_A)
d288f65f 7326 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7327
d288f65f
VS		 7328 pipe_config->dpll_hw_state.dpll_md =
7329 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7330}
7331
d288f65f 7332static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7333 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7334{
7335 struct drm_device *dev = crtc->base.dev;
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7337 int pipe = crtc->pipe;
7338 int dpll_reg = DPLL(crtc->pipe);
7339 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7340 u32 loopfilter, tribuf_calcntr;
9d556c99 7341 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7342 u32 dpio_val;
9cbe40c1 7343 int vco;
9d556c99 7344
d288f65f
VS		 7345 bestn = pipe_config->dpll.n;
7346 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7347 bestm1 = pipe_config->dpll.m1;
7348 bestm2 = pipe_config->dpll.m2 >> 22;
7349 bestp1 = pipe_config->dpll.p1;
7350 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7351 vco = pipe_config->dpll.vco;
a945ce7e 7352 dpio_val = 0;
9cbe40c1 7353 loopfilter = 0;
9d556c99
CML		 7354
7355 /*
7356 * Enable Refclk and SSC
7357 */
a11b0703 7358 I915_WRITE(dpll_reg,
d288f65f 7359 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7360
a580516d 7361 mutex_lock(&dev_priv->sb_lock);
9d556c99 7362
9d556c99
CML		 7363 /* p1 and p2 divider */
7364 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7365 5 << DPIO_CHV_S1_DIV_SHIFT |
7366 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7367 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7368 1 << DPIO_CHV_K_DIV_SHIFT);
7369
7370 /* Feedback post-divider - m2 */
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7372
7373 /* Feedback refclk divider - n and m1 */
7374 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7375 DPIO_CHV_M1_DIV_BY_2 |
7376 1 << DPIO_CHV_N_DIV_SHIFT);
7377
7378 /* M2 fraction division */
a945ce7e
VP		 7379 if (bestm2_frac)
7380 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7381
7382 /* M2 fraction division enable */
a945ce7e
VP		 7383 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7384 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7385 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7386 if (bestm2_frac)
7387 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7389
de3a0fde
VP		 7390 /* Program digital lock detect threshold */
7391 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7392 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7393 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7394 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7395 if (!bestm2_frac)
7396 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7397 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7398
9d556c99 7399 /* Loop filter */
9cbe40c1
VP		 7400 if (vco == 5400000) {
7401 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7402 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7403 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7404 tribuf_calcntr = 0x9;
7405 } else if (vco <= 6200000) {
7406 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7407 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7408 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7409 tribuf_calcntr = 0x9;
7410 } else if (vco <= 6480000) {
7411 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7412 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7413 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7414 tribuf_calcntr = 0x8;
7415 } else {
7416 /* Not supported. Apply the same limits as in the max case */
7417 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7418 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7419 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7420 tribuf_calcntr = 0;
7421 }
9d556c99
CML		 7422 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7423
968040b2 7424 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7425 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7426 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7427 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7428
9d556c99
CML		 7429 /* AFC Recal */
7430 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7431 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7432 DPIO_AFC_RECAL);
7433
a580516d 7434 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7435}
7436
d288f65f
VS		 7437/**
7438 * vlv_force_pll_on - forcibly enable just the PLL
7439 * @dev_priv: i915 private structure
7440 * @pipe: pipe PLL to enable
7441 * @dpll: PLL configuration
7442 *
7443 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7444 * in cases where we need the PLL enabled even when @pipe is not going to
7445 * be enabled.
7446 */
7447void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7448 const struct dpll *dpll)
7449{
7450 struct intel_crtc *crtc =
7451 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7452 struct intel_crtc_state pipe_config = {
a93e255f 7453 .base.crtc = &crtc->base,
d288f65f
VS		 7454 .pixel_multiplier = 1,
7455 .dpll = *dpll,
7456 };
7457
7458 if (IS_CHERRYVIEW(dev)) {
251ac862 7459 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7460 chv_prepare_pll(crtc, &pipe_config);
7461 chv_enable_pll(crtc, &pipe_config);
7462 } else {
251ac862 7463 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7464 vlv_prepare_pll(crtc, &pipe_config);
7465 vlv_enable_pll(crtc, &pipe_config);
7466 }
7467}
7468
7469/**
7470 * vlv_force_pll_off - forcibly disable just the PLL
7471 * @dev_priv: i915 private structure
7472 * @pipe: pipe PLL to disable
7473 *
7474 * Disable the PLL for @pipe. To be used in cases where we need
7475 * the PLL enabled even when @pipe is not going to be enabled.
7476 */
7477void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7478{
7479 if (IS_CHERRYVIEW(dev))
7480 chv_disable_pll(to_i915(dev), pipe);
7481 else
7482 vlv_disable_pll(to_i915(dev), pipe);
7483}
7484
251ac862
DV		 7485static void i9xx_compute_dpll(struct intel_crtc *crtc,
7486 struct intel_crtc_state *crtc_state,
7487 intel_clock_t *reduced_clock,
7488 int num_connectors)
eb1cbe48 7489{
f47709a9 7490 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7491 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7492 u32 dpll;
7493 bool is_sdvo;
190f68c5 7494 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7495
190f68c5 7496 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7497
a93e255f
ACO		 7498 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7499 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7500
7501 dpll = DPLL_VGA_MODE_DIS;
7502
a93e255f 7503 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7504 dpll |= DPLLB_MODE_LVDS;
7505 else
7506 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7507
ef1b460d 7508 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7509 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7510 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7511 }
198a037f
DV		 7512
7513 if (is_sdvo)
4a33e48d 7514 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7515
190f68c5 7516 if (crtc_state->has_dp_encoder)
4a33e48d 7517 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7518
7519 /* compute bitmask from p1 value */
7520 if (IS_PINEVIEW(dev))
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7522 else {
7523 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7524 if (IS_G4X(dev) && reduced_clock)
7525 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7526 }
7527 switch (clock->p2) {
7528 case 5:
7529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7530 break;
7531 case 7:
7532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7533 break;
7534 case 10:
7535 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7536 break;
7537 case 14:
7538 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7539 break;
7540 }
7541 if (INTEL_INFO(dev)->gen >= 4)
7542 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7543
190f68c5 7544 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7545 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7546 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7547 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7548 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7549 else
7550 dpll |= PLL_REF_INPUT_DREFCLK;
7551
7552 dpll |= DPLL_VCO_ENABLE;
190f68c5 7553 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7554
eb1cbe48 7555 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7556 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7557 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7558 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7559 }
7560}
7561
251ac862
DV		 7562static void i8xx_compute_dpll(struct intel_crtc *crtc,
7563 struct intel_crtc_state *crtc_state,
7564 intel_clock_t *reduced_clock,
7565 int num_connectors)
eb1cbe48 7566{
f47709a9 7567 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7568 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7569 u32 dpll;
190f68c5 7570 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7571
190f68c5 7572 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7573
eb1cbe48
DV		 7574 dpll = DPLL_VGA_MODE_DIS;
7575
a93e255f 7576 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7577 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7578 } else {
7579 if (clock->p1 == 2)
7580 dpll |= PLL_P1_DIVIDE_BY_TWO;
7581 else
7582 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7583 if (clock->p2 == 4)
7584 dpll |= PLL_P2_DIVIDE_BY_4;
7585 }
7586
a93e255f 7587 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7588 dpll |= DPLL_DVO_2X_MODE;
7589
a93e255f 7590 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7591 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7592 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7593 else
7594 dpll |= PLL_REF_INPUT_DREFCLK;
7595
7596 dpll |= DPLL_VCO_ENABLE;
190f68c5 7597 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7598}
7599
8a654f3b 7600static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7601{
7602 struct drm_device *dev = intel_crtc->base.dev;
7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7605 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7606 struct drm_display_mode *adjusted_mode =
6e3c9717 7607 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7608 uint32_t crtc_vtotal, crtc_vblank_end;
7609 int vsyncshift = 0;
4d8a62ea
DV		 7610
7611 /* We need to be careful not to changed the adjusted mode, for otherwise
7612 * the hw state checker will get angry at the mismatch. */
7613 crtc_vtotal = adjusted_mode->crtc_vtotal;
7614 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7615
609aeaca 7616 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7617 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7618 crtc_vtotal -= 1;
7619 crtc_vblank_end -= 1;
609aeaca 7620
409ee761 7621 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7622 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7623 else
7624 vsyncshift = adjusted_mode->crtc_hsync_start -
7625 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7626 if (vsyncshift < 0)
7627 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7628 }
7629
7630 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7631 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7632
fe2b8f9d 7633 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7634 (adjusted_mode->crtc_hdisplay - 1) |
7635 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7636 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7637 (adjusted_mode->crtc_hblank_start - 1) |
7638 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7639 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7640 (adjusted_mode->crtc_hsync_start - 1) |
7641 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7642
fe2b8f9d 7643 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7644 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7645 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7646 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7647 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7648 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7649 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7650 (adjusted_mode->crtc_vsync_start - 1) |
7651 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7652
b5e508d4
PZ		 7653 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7654 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7655 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7656 * bits. */
7657 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7658 (pipe == PIPE_B || pipe == PIPE_C))
7659 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7660
b0e77b9c
PZ		 7661 /* pipesrc controls the size that is scaled from, which should
7662 * always be the user's requested size.
7663 */
7664 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7665 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7666 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7667}
7668
1bd1bd80 7669static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7670 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7671{
7672 struct drm_device *dev = crtc->base.dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7675 uint32_t tmp;
7676
7677 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7678 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7680 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7681 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7683 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7684 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7685 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7686
7687 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7688 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7690 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7691 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7693 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7694 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7695 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7696
7697 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7698 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7699 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7700 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7701 }
7702
7703 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7704 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7705 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7706
2d112de7
ACO		 7707 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7708 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7709}
7710
f6a83288 7711void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7712 struct intel_crtc_state *pipe_config)
babea61d 7713{
2d112de7
ACO		 7714 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7715 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7716 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7717 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7718
2d112de7
ACO		 7719 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7720 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7721 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7722 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7723
2d112de7 7724 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7725 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7726
2d112de7
ACO		 7727 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7728 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7729
7730 mode->hsync = drm_mode_hsync(mode);
7731 mode->vrefresh = drm_mode_vrefresh(mode);
7732 drm_mode_set_name(mode);
babea61d
JB		 7733}
7734
84b046f3
DV		 7735static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7736{
7737 struct drm_device *dev = intel_crtc->base.dev;
7738 struct drm_i915_private *dev_priv = dev->dev_private;
7739 uint32_t pipeconf;
7740
9f11a9e4 7741 pipeconf = 0;
84b046f3 7742
b6b5d049
VS		 7743 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7744 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7745 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7746
6e3c9717 7747 if (intel_crtc->config->double_wide)
cf532bb2 7748 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7749
ff9ce46e
DV		 7750 /* only g4x and later have fancy bpc/dither controls */
7751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7753 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7754 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7755 PIPECONF_DITHER_TYPE_SP;
84b046f3 7756
6e3c9717 7757 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7758 case 18:
7759 pipeconf |= PIPECONF_6BPC;
7760 break;
7761 case 24:
7762 pipeconf |= PIPECONF_8BPC;
7763 break;
7764 case 30:
7765 pipeconf |= PIPECONF_10BPC;
7766 break;
7767 default:
7768 /* Case prevented by intel_choose_pipe_bpp_dither. */
7769 BUG();
84b046f3
DV		 7770 }
7771 }
7772
7773 if (HAS_PIPE_CXSR(dev)) {
7774 if (intel_crtc->lowfreq_avail) {
7775 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7777 } else {
7778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7779 }
7780 }
7781
6e3c9717 7782 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7783 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7784 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7785 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7786 else
7787 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7788 } else
84b046f3
DV		 7789 pipeconf |= PIPECONF_PROGRESSIVE;
7790
6e3c9717 7791 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7792 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7793
84b046f3
DV		 7794 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7795 POSTING_READ(PIPECONF(intel_crtc->pipe));
7796}
7797
190f68c5
ACO		 7798static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7799 struct intel_crtc_state *crtc_state)
79e53945 7800{
c7653199 7801 struct drm_device *dev = crtc->base.dev;
79e53945 7802 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7803 int refclk, num_connectors = 0;
c329a4ec
DV		 7804 intel_clock_t clock;
7805 bool ok;
7806 bool is_dsi = false;
5eddb70b 7807 struct intel_encoder *encoder;
d4906093 7808 const intel_limit_t *limit;
55bb9992 7809 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7810 struct drm_connector *connector;
55bb9992
ACO		 7811 struct drm_connector_state *connector_state;
7812 int i;
79e53945 7813
dd3cd74a
ACO		 7814 memset(&crtc_state->dpll_hw_state, 0,
7815 sizeof(crtc_state->dpll_hw_state));
7816
da3ced29 7817 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7818 if (connector_state->crtc != &crtc->base)
7819 continue;
7820
7821 encoder = to_intel_encoder(connector_state->best_encoder);
7822
5eddb70b 7823 switch (encoder->type) {
e9fd1c02
JN		 7824 case INTEL_OUTPUT_DSI:
7825 is_dsi = true;
7826 break;
6847d71b
PZ		 7827 default:
7828 break;
79e53945 7829 }
43565a06 7830
c751ce4f 7831 num_connectors++;
79e53945
JB		 7832 }
7833
f2335330 7834 if (is_dsi)
5b18e57c 7835 return 0;
f2335330 7836
190f68c5 7837 if (!crtc_state->clock_set) {
a93e255f 7838 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7839
e9fd1c02
JN		 7840 /*
7841 * Returns a set of divisors for the desired target clock with
7842 * the given refclk, or FALSE. The returned values represent
7843 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7844 * 2) / p1 / p2.
7845 */
a93e255f
ACO		 7846 limit = intel_limit(crtc_state, refclk);
7847 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7848 crtc_state->port_clock,
e9fd1c02 7849 refclk, NULL, &clock);
f2335330 7850 if (!ok) {
e9fd1c02
JN		 7851 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7852 return -EINVAL;
7853 }
79e53945 7854
f2335330 7855 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7856 crtc_state->dpll.n = clock.n;
7857 crtc_state->dpll.m1 = clock.m1;
7858 crtc_state->dpll.m2 = clock.m2;
7859 crtc_state->dpll.p1 = clock.p1;
7860 crtc_state->dpll.p2 = clock.p2;
f47709a9 7861 }
7026d4ac 7862
e9fd1c02 7863 if (IS_GEN2(dev)) {
c329a4ec 7864 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7865 num_connectors);
9d556c99 7866 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7867 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7868 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7869 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7870 } else {
c329a4ec 7871 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7872 num_connectors);
e9fd1c02 7873 }
79e53945 7874
c8f7a0db 7875 return 0;
f564048e
EA		 7876}
7877
2fa2fe9a 7878static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7879 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7880{
7881 struct drm_device *dev = crtc->base.dev;
7882 struct drm_i915_private *dev_priv = dev->dev_private;
7883 uint32_t tmp;
7884
dc9e7dec
VS		 7885 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7886 return;
7887
2fa2fe9a 7888 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7889 if (!(tmp & PFIT_ENABLE))
7890 return;
2fa2fe9a 7891
06922821 7892 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7893 if (INTEL_INFO(dev)->gen < 4) {
7894 if (crtc->pipe != PIPE_B)
7895 return;
2fa2fe9a
DV		 7896 } else {
7897 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7898 return;
7899 }
7900
06922821 7901 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7902 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7903 if (INTEL_INFO(dev)->gen < 5)
7904 pipe_config->gmch_pfit.lvds_border_bits =
7905 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7906}
7907
acbec814 7908static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7909 struct intel_crtc_state *pipe_config)
acbec814
JB		 7910{
7911 struct drm_device *dev = crtc->base.dev;
7912 struct drm_i915_private *dev_priv = dev->dev_private;
7913 int pipe = pipe_config->cpu_transcoder;
7914 intel_clock_t clock;
7915 u32 mdiv;
662c6ecb 7916 int refclk = 100000;
acbec814 7917
f573de5a
SK		 7918 /* In case of MIPI DPLL will not even be used */
7919 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7920 return;
7921
a580516d 7922 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7923 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7924 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7925
7926 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7927 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7928 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7929 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7930 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7931
dccbea3b 7932 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7933}
7934
5724dbd1
DL		 7935static void
7936i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7937 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7938{
7939 struct drm_device *dev = crtc->base.dev;
7940 struct drm_i915_private *dev_priv = dev->dev_private;
7941 u32 val, base, offset;
7942 int pipe = crtc->pipe, plane = crtc->plane;
7943 int fourcc, pixel_format;
6761dd31 7944 unsigned int aligned_height;
b113d5ee 7945 struct drm_framebuffer *fb;
1b842c89 7946 struct intel_framebuffer *intel_fb;
1ad292b5 7947
42a7b088
DL		 7948 val = I915_READ(DSPCNTR(plane));
7949 if (!(val & DISPLAY_PLANE_ENABLE))
7950 return;
7951
d9806c9f 7952 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7953 if (!intel_fb) {
1ad292b5
JB		 7954 DRM_DEBUG_KMS("failed to alloc fb\n");
7955 return;
7956 }
7957
1b842c89
DL		 7958 fb = &intel_fb->base;
7959
18c5247e
DV		 7960 if (INTEL_INFO(dev)->gen >= 4) {
7961 if (val & DISPPLANE_TILED) {
49af449b 7962 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7963 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7964 }
7965 }
1ad292b5
JB		 7966
7967 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7968 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7969 fb->pixel_format = fourcc;
7970 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7971
7972 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7973 if (plane_config->tiling)
1ad292b5
JB		 7974 offset = I915_READ(DSPTILEOFF(plane));
7975 else
7976 offset = I915_READ(DSPLINOFF(plane));
7977 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7978 } else {
7979 base = I915_READ(DSPADDR(plane));
7980 }
7981 plane_config->base = base;
7982
7983 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7984 fb->width = ((val >> 16) & 0xfff) + 1;
7985 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7986
7987 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7988 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7989
b113d5ee 7990 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7991 fb->pixel_format,
7992 fb->modifier[0]);
1ad292b5 7993
f37b5c2b 7994 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7995
2844a921
DL		 7996 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7997 pipe_name(pipe), plane, fb->width, fb->height,
7998 fb->bits_per_pixel, base, fb->pitches[0],
7999 plane_config->size);
1ad292b5 8000
2d14030b 8001 plane_config->fb = intel_fb;
1ad292b5
JB		 8002}
8003
70b23a98 8004static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8005 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8006{
8007 struct drm_device *dev = crtc->base.dev;
8008 struct drm_i915_private *dev_priv = dev->dev_private;
8009 int pipe = pipe_config->cpu_transcoder;
8010 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8011 intel_clock_t clock;
0d7b6b11 8012 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8013 int refclk = 100000;
8014
a580516d 8015 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8016 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8017 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8018 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8019 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8020 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8021 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8022
8023 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8024 clock.m2 = (pll_dw0 & 0xff) << 22;
8025 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8026 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8027 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8028 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8029 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8030
dccbea3b 8031 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8032}
8033
0e8ffe1b 8034static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8035 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8036{
8037 struct drm_device *dev = crtc->base.dev;
8038 struct drm_i915_private *dev_priv = dev->dev_private;
8039 uint32_t tmp;
8040
f458ebbc
DV		 8041 if (!intel_display_power_is_enabled(dev_priv,
8042 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8043 return false;
8044
e143a21c 8045 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8046 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8047
0e8ffe1b
DV		 8048 tmp = I915_READ(PIPECONF(crtc->pipe));
8049 if (!(tmp & PIPECONF_ENABLE))
8050 return false;
8051
42571aef
VS		 8052 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8053 switch (tmp & PIPECONF_BPC_MASK) {
8054 case PIPECONF_6BPC:
8055 pipe_config->pipe_bpp = 18;
8056 break;
8057 case PIPECONF_8BPC:
8058 pipe_config->pipe_bpp = 24;
8059 break;
8060 case PIPECONF_10BPC:
8061 pipe_config->pipe_bpp = 30;
8062 break;
8063 default:
8064 break;
8065 }
8066 }
8067
b5a9fa09
DV		 8068 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8069 pipe_config->limited_color_range = true;
8070
282740f7
VS		 8071 if (INTEL_INFO(dev)->gen < 4)
8072 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8073
1bd1bd80
DV		 8074 intel_get_pipe_timings(crtc, pipe_config);
8075
2fa2fe9a
DV		 8076 i9xx_get_pfit_config(crtc, pipe_config);
8077
6c49f241
DV		 8078 if (INTEL_INFO(dev)->gen >= 4) {
8079 tmp = I915_READ(DPLL_MD(crtc->pipe));
8080 pipe_config->pixel_multiplier =
8081 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8082 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8083 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8084 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8085 tmp = I915_READ(DPLL(crtc->pipe));
8086 pipe_config->pixel_multiplier =
8087 ((tmp & SDVO_MULTIPLIER_MASK)
8088 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8089 } else {
8090 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8091 * port and will be fixed up in the encoder->get_config
8092 * function. */
8093 pipe_config->pixel_multiplier = 1;
8094 }
8bcc2795
DV		 8095 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8096 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8097 /*
8098 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8099 * on 830. Filter it out here so that we don't
8100 * report errors due to that.
8101 */
8102 if (IS_I830(dev))
8103 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8104
8bcc2795
DV		 8105 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8106 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8107 } else {
8108 /* Mask out read-only status bits. */
8109 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8110 DPLL_PORTC_READY_MASK |
8111 DPLL_PORTB_READY_MASK);
8bcc2795 8112 }
6c49f241 8113
70b23a98
VS		 8114 if (IS_CHERRYVIEW(dev))
8115 chv_crtc_clock_get(crtc, pipe_config);
8116 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8117 vlv_crtc_clock_get(crtc, pipe_config);
8118 else
8119 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8120
0e8ffe1b
DV		 8121 return true;
8122}
8123
dde86e2d 8124static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8125{
8126 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8127 struct intel_encoder *encoder;
74cfd7ac 8128 u32 val, final;
13d83a67 8129 bool has_lvds = false;
199e5d79 8130 bool has_cpu_edp = false;
199e5d79 8131 bool has_panel = false;
99eb6a01
KP		 8132 bool has_ck505 = false;
8133 bool can_ssc = false;
13d83a67
JB		 8134
8135 /* We need to take the global config into account */
b2784e15 8136 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8137 switch (encoder->type) {
8138 case INTEL_OUTPUT_LVDS:
8139 has_panel = true;
8140 has_lvds = true;
8141 break;
8142 case INTEL_OUTPUT_EDP:
8143 has_panel = true;
2de6905f 8144 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8145 has_cpu_edp = true;
8146 break;
6847d71b
PZ		 8147 default:
8148 break;
13d83a67
JB		 8149 }
8150 }
8151
99eb6a01 8152 if (HAS_PCH_IBX(dev)) {
41aa3448 8153 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8154 can_ssc = has_ck505;
8155 } else {
8156 has_ck505 = false;
8157 can_ssc = true;
8158 }
8159
2de6905f
ID		 8160 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8161 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8162
8163 /* Ironlake: try to setup display ref clock before DPLL
8164 * enabling. This is only under driver's control after
8165 * PCH B stepping, previous chipset stepping should be
8166 * ignoring this setting.
8167 */
74cfd7ac
CW		 8168 val = I915_READ(PCH_DREF_CONTROL);
8169
8170 /* As we must carefully and slowly disable/enable each source in turn,
8171 * compute the final state we want first and check if we need to
8172 * make any changes at all.
8173 */
8174 final = val;
8175 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8176 if (has_ck505)
8177 final |= DREF_NONSPREAD_CK505_ENABLE;
8178 else
8179 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8180
8181 final &= ~DREF_SSC_SOURCE_MASK;
8182 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8183 final &= ~DREF_SSC1_ENABLE;
8184
8185 if (has_panel) {
8186 final |= DREF_SSC_SOURCE_ENABLE;
8187
8188 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8189 final |= DREF_SSC1_ENABLE;
8190
8191 if (has_cpu_edp) {
8192 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8193 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8194 else
8195 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8196 } else
8197 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8198 } else {
8199 final |= DREF_SSC_SOURCE_DISABLE;
8200 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8201 }
8202
8203 if (final == val)
8204 return;
8205
13d83a67 8206 /* Always enable nonspread source */
74cfd7ac 8207 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8208
99eb6a01 8209 if (has_ck505)
74cfd7ac 8210 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8211 else
74cfd7ac 8212 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8213
199e5d79 8214 if (has_panel) {
74cfd7ac
CW		 8215 val &= ~DREF_SSC_SOURCE_MASK;
8216 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8217
199e5d79 8218 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8219 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8220 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8221 val |= DREF_SSC1_ENABLE;
e77166b5 8222 } else
74cfd7ac 8223 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8224
8225 /* Get SSC going before enabling the outputs */
74cfd7ac 8226 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8227 POSTING_READ(PCH_DREF_CONTROL);
8228 udelay(200);
8229
74cfd7ac 8230 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8231
8232 /* Enable CPU source on CPU attached eDP */
199e5d79 8233 if (has_cpu_edp) {
99eb6a01 8234 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8235 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8236 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8237 } else
74cfd7ac 8238 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8239 } else
74cfd7ac 8240 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8241
74cfd7ac 8242 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8243 POSTING_READ(PCH_DREF_CONTROL);
8244 udelay(200);
8245 } else {
8246 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8247
74cfd7ac 8248 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8249
8250 /* Turn off CPU output */
74cfd7ac 8251 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8252
74cfd7ac 8253 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8254 POSTING_READ(PCH_DREF_CONTROL);
8255 udelay(200);
8256
8257 /* Turn off the SSC source */
74cfd7ac
CW		 8258 val &= ~DREF_SSC_SOURCE_MASK;
8259 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8260
8261 /* Turn off SSC1 */
74cfd7ac 8262 val &= ~DREF_SSC1_ENABLE;
199e5d79 8263
74cfd7ac 8264 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8265 POSTING_READ(PCH_DREF_CONTROL);
8266 udelay(200);
8267 }
74cfd7ac
CW		 8268
8269 BUG_ON(val != final);
13d83a67
JB		 8270}
8271
f31f2d55 8272static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8273{
f31f2d55 8274 uint32_t tmp;
dde86e2d 8275
0ff066a9
PZ		 8276 tmp = I915_READ(SOUTH_CHICKEN2);
8277 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8278 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8279
0ff066a9
PZ		 8280 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8281 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8282 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8283
0ff066a9
PZ		 8284 tmp = I915_READ(SOUTH_CHICKEN2);
8285 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8286 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8287
0ff066a9
PZ		 8288 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8289 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8290 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8291}
8292
8293/* WaMPhyProgramming:hsw */
8294static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8295{
8296 uint32_t tmp;
dde86e2d
PZ		 8297
8298 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8299 tmp &= ~(0xFF << 24);
8300 tmp |= (0x12 << 24);
8301 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8302
dde86e2d
PZ		 8303 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8304 tmp |= (1 << 11);
8305 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8306
8307 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8308 tmp |= (1 << 11);
8309 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8310
dde86e2d
PZ		 8311 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8312 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8313 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8314
8315 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8316 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8317 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8318
0ff066a9
PZ		 8319 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8320 tmp &= ~(7 << 13);
8321 tmp |= (5 << 13);
8322 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8323
0ff066a9
PZ		 8324 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8325 tmp &= ~(7 << 13);
8326 tmp |= (5 << 13);
8327 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8328
8329 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8330 tmp &= ~0xFF;
8331 tmp |= 0x1C;
8332 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8333
8334 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8335 tmp &= ~0xFF;
8336 tmp |= 0x1C;
8337 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8338
8339 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8340 tmp &= ~(0xFF << 16);
8341 tmp |= (0x1C << 16);
8342 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8343
8344 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8345 tmp &= ~(0xFF << 16);
8346 tmp |= (0x1C << 16);
8347 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8348
0ff066a9
PZ		 8349 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8350 tmp |= (1 << 27);
8351 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8352
0ff066a9
PZ		 8353 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8354 tmp |= (1 << 27);
8355 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8356
0ff066a9
PZ		 8357 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8358 tmp &= ~(0xF << 28);
8359 tmp |= (4 << 28);
8360 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8361
0ff066a9
PZ		 8362 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8363 tmp &= ~(0xF << 28);
8364 tmp |= (4 << 28);
8365 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8366}
8367
2fa86a1f
PZ		 8368/* Implements 3 different sequences from BSpec chapter "Display iCLK
8369 * Programming" based on the parameters passed:
8370 * - Sequence to enable CLKOUT_DP
8371 * - Sequence to enable CLKOUT_DP without spread
8372 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8373 */
8374static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8375 bool with_fdi)
f31f2d55
PZ		 8376{
8377 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8378 uint32_t reg, tmp;
8379
8380 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8381 with_spread = true;
8382 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8383 with_fdi, "LP PCH doesn't have FDI\n"))
8384 with_fdi = false;
f31f2d55 8385
a580516d 8386 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8387
8388 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8389 tmp &= ~SBI_SSCCTL_DISABLE;
8390 tmp |= SBI_SSCCTL_PATHALT;
8391 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8392
8393 udelay(24);
8394
2fa86a1f
PZ		 8395 if (with_spread) {
8396 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8397 tmp &= ~SBI_SSCCTL_PATHALT;
8398 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8399
2fa86a1f
PZ		 8400 if (with_fdi) {
8401 lpt_reset_fdi_mphy(dev_priv);
8402 lpt_program_fdi_mphy(dev_priv);
8403 }
8404 }
dde86e2d 8405
2fa86a1f
PZ		 8406 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8407 SBI_GEN0 : SBI_DBUFF0;
8408 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8409 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8410 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8411
a580516d 8412 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8413}
8414
47701c3b
PZ		 8415/* Sequence to disable CLKOUT_DP */
8416static void lpt_disable_clkout_dp(struct drm_device *dev)
8417{
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8419 uint32_t reg, tmp;
8420
a580516d 8421 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8422
8423 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8424 SBI_GEN0 : SBI_DBUFF0;
8425 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8426 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8427 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8428
8429 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8430 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8431 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8432 tmp |= SBI_SSCCTL_PATHALT;
8433 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8434 udelay(32);
8435 }
8436 tmp |= SBI_SSCCTL_DISABLE;
8437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8438 }
8439
a580516d 8440 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8441}
8442
bf8fa3d3
PZ		 8443static void lpt_init_pch_refclk(struct drm_device *dev)
8444{
bf8fa3d3
PZ		 8445 struct intel_encoder *encoder;
8446 bool has_vga = false;
8447
b2784e15 8448 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8449 switch (encoder->type) {
8450 case INTEL_OUTPUT_ANALOG:
8451 has_vga = true;
8452 break;
6847d71b
PZ		 8453 default:
8454 break;
bf8fa3d3
PZ		 8455 }
8456 }
8457
47701c3b
PZ		 8458 if (has_vga)
8459 lpt_enable_clkout_dp(dev, true, true);
8460 else
8461 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8462}
8463
dde86e2d
PZ		 8464/*
8465 * Initialize reference clocks when the driver loads
8466 */
8467void intel_init_pch_refclk(struct drm_device *dev)
8468{
8469 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8470 ironlake_init_pch_refclk(dev);
8471 else if (HAS_PCH_LPT(dev))
8472 lpt_init_pch_refclk(dev);
8473}
8474
55bb9992 8475static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8476{
55bb9992 8477 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8478 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8479 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8480 struct drm_connector *connector;
55bb9992 8481 struct drm_connector_state *connector_state;
d9d444cb 8482 struct intel_encoder *encoder;
55bb9992 8483 int num_connectors = 0, i;
d9d444cb
JB		 8484 bool is_lvds = false;
8485
da3ced29 8486 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8487 if (connector_state->crtc != crtc_state->base.crtc)
8488 continue;
8489
8490 encoder = to_intel_encoder(connector_state->best_encoder);
8491
d9d444cb
JB		 8492 switch (encoder->type) {
8493 case INTEL_OUTPUT_LVDS:
8494 is_lvds = true;
8495 break;
6847d71b
PZ		 8496 default:
8497 break;
d9d444cb
JB		 8498 }
8499 num_connectors++;
8500 }
8501
8502 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8503 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8504 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8505 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8506 }
8507
8508 return 120000;
8509}
8510
6ff93609 8511static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8512{
c8203565 8513 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8515 int pipe = intel_crtc->pipe;
c8203565
PZ		 8516 uint32_t val;
8517
78114071 8518 val = 0;
c8203565 8519
6e3c9717 8520 switch (intel_crtc->config->pipe_bpp) {
c8203565 8521 case 18:
dfd07d72 8522 val |= PIPECONF_6BPC;
c8203565
PZ		 8523 break;
8524 case 24:
dfd07d72 8525 val |= PIPECONF_8BPC;
c8203565
PZ		 8526 break;
8527 case 30:
dfd07d72 8528 val |= PIPECONF_10BPC;
c8203565
PZ		 8529 break;
8530 case 36:
dfd07d72 8531 val |= PIPECONF_12BPC;
c8203565
PZ		 8532 break;
8533 default:
cc769b62
PZ		 8534 /* Case prevented by intel_choose_pipe_bpp_dither. */
8535 BUG();
c8203565
PZ		 8536 }
8537
6e3c9717 8538 if (intel_crtc->config->dither)
c8203565
PZ		 8539 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8540
6e3c9717 8541 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8542 val |= PIPECONF_INTERLACED_ILK;
8543 else
8544 val |= PIPECONF_PROGRESSIVE;
8545
6e3c9717 8546 if (intel_crtc->config->limited_color_range)
3685a8f3 8547 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8548
c8203565
PZ		 8549 I915_WRITE(PIPECONF(pipe), val);
8550 POSTING_READ(PIPECONF(pipe));
8551}
8552
86d3efce
VS		 8553/*
8554 * Set up the pipe CSC unit.
8555 *
8556 * Currently only full range RGB to limited range RGB conversion
8557 * is supported, but eventually this should handle various
8558 * RGB<->YCbCr scenarios as well.
8559 */
50f3b016 8560static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8561{
8562 struct drm_device *dev = crtc->dev;
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8565 int pipe = intel_crtc->pipe;
8566 uint16_t coeff = 0x7800; /* 1.0 */
8567
8568 /*
8569 * TODO: Check what kind of values actually come out of the pipe
8570 * with these coeff/postoff values and adjust to get the best
8571 * accuracy. Perhaps we even need to take the bpc value into
8572 * consideration.
8573 */
8574
6e3c9717 8575 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8576 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8577
8578 /*
8579 * GY/GU and RY/RU should be the other way around according
8580 * to BSpec, but reality doesn't agree. Just set them up in
8581 * a way that results in the correct picture.
8582 */
8583 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8584 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8585
8586 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8587 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8588
8589 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8590 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8591
8592 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8593 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8595
8596 if (INTEL_INFO(dev)->gen > 6) {
8597 uint16_t postoff = 0;
8598
6e3c9717 8599 if (intel_crtc->config->limited_color_range)
32cf0cb0 8600 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8601
8602 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8603 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8605
8606 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8607 } else {
8608 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8609
6e3c9717 8610 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8611 mode |= CSC_BLACK_SCREEN_OFFSET;
8612
8613 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8614 }
8615}
8616
6ff93609 8617static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8618{
756f85cf
PZ		 8619 struct drm_device *dev = crtc->dev;
8620 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8622 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8623 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8624 uint32_t val;
8625
3eff4faa 8626 val = 0;
ee2b0b38 8627
6e3c9717 8628 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8629 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8630
6e3c9717 8631 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8632 val |= PIPECONF_INTERLACED_ILK;
8633 else
8634 val |= PIPECONF_PROGRESSIVE;
8635
702e7a56
PZ		 8636 I915_WRITE(PIPECONF(cpu_transcoder), val);
8637 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8638
8639 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8640 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8641
3cdf122c 8642 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8643 val = 0;
8644
6e3c9717 8645 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8646 case 18:
8647 val |= PIPEMISC_DITHER_6_BPC;
8648 break;
8649 case 24:
8650 val |= PIPEMISC_DITHER_8_BPC;
8651 break;
8652 case 30:
8653 val |= PIPEMISC_DITHER_10_BPC;
8654 break;
8655 case 36:
8656 val |= PIPEMISC_DITHER_12_BPC;
8657 break;
8658 default:
8659 /* Case prevented by pipe_config_set_bpp. */
8660 BUG();
8661 }
8662
6e3c9717 8663 if (intel_crtc->config->dither)
756f85cf
PZ		 8664 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8665
8666 I915_WRITE(PIPEMISC(pipe), val);
8667 }
ee2b0b38
PZ		 8668}
8669
6591c6e4 8670static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8671 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8672 intel_clock_t *clock,
8673 bool *has_reduced_clock,
8674 intel_clock_t *reduced_clock)
8675{
8676 struct drm_device *dev = crtc->dev;
8677 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8678 int refclk;
d4906093 8679 const intel_limit_t *limit;
c329a4ec 8680 bool ret;
79e53945 8681
55bb9992 8682 refclk = ironlake_get_refclk(crtc_state);
79e53945 8683
d4906093
ML		 8684 /*
8685 * Returns a set of divisors for the desired target clock with the given
8686 * refclk, or FALSE. The returned values represent the clock equation:
8687 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8688 */
a93e255f
ACO		 8689 limit = intel_limit(crtc_state, refclk);
8690 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8691 crtc_state->port_clock,
ee9300bb 8692 refclk, NULL, clock);
6591c6e4
PZ		 8693 if (!ret)
8694 return false;
cda4b7d3 8695
6591c6e4
PZ		 8696 return true;
8697}
8698
d4b1931c
PZ		 8699int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8700{
8701 /*
8702 * Account for spread spectrum to avoid
8703 * oversubscribing the link. Max center spread
8704 * is 2.5%; use 5% for safety's sake.
8705 */
8706 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8707 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8708}
8709
7429e9d4 8710static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8711{
7429e9d4 8712 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8713}
8714
de13a2e3 8715static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8716 struct intel_crtc_state *crtc_state,
7429e9d4 8717 u32 *fp,
9a7c7890 8718 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8719{
de13a2e3 8720 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8721 struct drm_device *dev = crtc->dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8723 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8724 struct drm_connector *connector;
55bb9992
ACO		 8725 struct drm_connector_state *connector_state;
8726 struct intel_encoder *encoder;
de13a2e3 8727 uint32_t dpll;
55bb9992 8728 int factor, num_connectors = 0, i;
09ede541 8729 bool is_lvds = false, is_sdvo = false;
79e53945 8730
da3ced29 8731 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8732 if (connector_state->crtc != crtc_state->base.crtc)
8733 continue;
8734
8735 encoder = to_intel_encoder(connector_state->best_encoder);
8736
8737 switch (encoder->type) {
79e53945
JB		 8738 case INTEL_OUTPUT_LVDS:
8739 is_lvds = true;
8740 break;
8741 case INTEL_OUTPUT_SDVO:
7d57382e 8742 case INTEL_OUTPUT_HDMI:
79e53945 8743 is_sdvo = true;
79e53945 8744 break;
6847d71b
PZ		 8745 default:
8746 break;
79e53945 8747 }
43565a06 8748
c751ce4f 8749 num_connectors++;
79e53945 8750 }
79e53945 8751
c1858123 8752 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8753 factor = 21;
8754 if (is_lvds) {
8755 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8757 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8758 factor = 25;
190f68c5 8759 } else if (crtc_state->sdvo_tv_clock)
8febb297 8760 factor = 20;
c1858123 8761
190f68c5 8762 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8763 *fp |= FP_CB_TUNE;
2c07245f 8764
9a7c7890
DV		 8765 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8766 *fp2 |= FP_CB_TUNE;
8767
5eddb70b 8768 dpll = 0;
2c07245f 8769
a07d6787
EA		 8770 if (is_lvds)
8771 dpll |= DPLLB_MODE_LVDS;
8772 else
8773 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8774
190f68c5 8775 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8776 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8777
8778 if (is_sdvo)
4a33e48d 8779 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8780 if (crtc_state->has_dp_encoder)
4a33e48d 8781 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8782
a07d6787 8783 /* compute bitmask from p1 value */
190f68c5 8784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8785 /* also FPA1 */
190f68c5 8786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8787
190f68c5 8788 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8789 case 5:
8790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8791 break;
8792 case 7:
8793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8794 break;
8795 case 10:
8796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8797 break;
8798 case 14:
8799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8800 break;
79e53945
JB		 8801 }
8802
b4c09f3b 8803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8805 else
8806 dpll |= PLL_REF_INPUT_DREFCLK;
8807
959e16d6 8808 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8809}
8810
190f68c5
ACO		 8811static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8812 struct intel_crtc_state *crtc_state)
de13a2e3 8813{
c7653199 8814 struct drm_device *dev = crtc->base.dev;
de13a2e3 8815 intel_clock_t clock, reduced_clock;
cbbab5bd 8816 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8817 bool ok, has_reduced_clock = false;
8b47047b 8818 bool is_lvds = false;
e2b78267 8819 struct intel_shared_dpll *pll;
de13a2e3 8820
dd3cd74a
ACO		 8821 memset(&crtc_state->dpll_hw_state, 0,
8822 sizeof(crtc_state->dpll_hw_state));
8823
409ee761 8824 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8825
5dc5298b
PZ		 8826 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8827 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8828
190f68c5 8829 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8830 &has_reduced_clock, &reduced_clock);
190f68c5 8831 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8832 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8833 return -EINVAL;
79e53945 8834 }
f47709a9 8835 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8836 if (!crtc_state->clock_set) {
8837 crtc_state->dpll.n = clock.n;
8838 crtc_state->dpll.m1 = clock.m1;
8839 crtc_state->dpll.m2 = clock.m2;
8840 crtc_state->dpll.p1 = clock.p1;
8841 crtc_state->dpll.p2 = clock.p2;
f47709a9 8842 }
79e53945 8843
5dc5298b 8844 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8845 if (crtc_state->has_pch_encoder) {
8846 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8847 if (has_reduced_clock)
7429e9d4 8848 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8849
190f68c5 8850 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8851 &fp, &reduced_clock,
8852 has_reduced_clock ? &fp2 : NULL);
8853
190f68c5
ACO		 8854 crtc_state->dpll_hw_state.dpll = dpll;
8855 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8856 if (has_reduced_clock)
190f68c5 8857 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8858 else
190f68c5 8859 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8860
190f68c5 8861 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8862 if (pll == NULL) {
84f44ce7 8863 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8864 pipe_name(crtc->pipe));
4b645f14
JB		 8865 return -EINVAL;
8866 }
3fb37703 8867 }
79e53945 8868
ab585dea 8869 if (is_lvds && has_reduced_clock)
c7653199 8870 crtc->lowfreq_avail = true;
bcd644e0 8871 else
c7653199 8872 crtc->lowfreq_avail = false;
e2b78267 8873
c8f7a0db 8874 return 0;
79e53945
JB		 8875}
8876
eb14cb74
VS		 8877static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8878 struct intel_link_m_n *m_n)
8879{
8880 struct drm_device *dev = crtc->base.dev;
8881 struct drm_i915_private *dev_priv = dev->dev_private;
8882 enum pipe pipe = crtc->pipe;
8883
8884 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8885 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8886 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8887 & ~TU_SIZE_MASK;
8888 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8889 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8890 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8891}
8892
8893static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8894 enum transcoder transcoder,
b95af8be
VK		 8895 struct intel_link_m_n *m_n,
8896 struct intel_link_m_n *m2_n2)
72419203
DV		 8897{
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8900 enum pipe pipe = crtc->pipe;
72419203 8901
eb14cb74
VS		 8902 if (INTEL_INFO(dev)->gen >= 5) {
8903 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8904 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8905 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8906 & ~TU_SIZE_MASK;
8907 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8908 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8909 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8910 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8911 * gen < 8) and if DRRS is supported (to make sure the
8912 * registers are not unnecessarily read).
8913 */
8914 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8915 crtc->config->has_drrs) {
b95af8be
VK		 8916 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8917 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8918 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8919 & ~TU_SIZE_MASK;
8920 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8921 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8922 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923 }
eb14cb74
VS		 8924 } else {
8925 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8926 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8927 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8928 & ~TU_SIZE_MASK;
8929 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8930 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8931 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8932 }
8933}
8934
8935void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8936 struct intel_crtc_state *pipe_config)
eb14cb74 8937{
681a8504 8938 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8939 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8940 else
8941 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8942 &pipe_config->dp_m_n,
8943 &pipe_config->dp_m2_n2);
eb14cb74 8944}
72419203 8945
eb14cb74 8946static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8947 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8948{
8949 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8950 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8951}
8952
bd2e244f 8953static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8954 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8955{
8956 struct drm_device *dev = crtc->base.dev;
8957 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8958 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8959 uint32_t ps_ctrl = 0;
8960 int id = -1;
8961 int i;
bd2e244f 8962
a1b2278e
CK		 8963 /* find scaler attached to this pipe */
8964 for (i = 0; i < crtc->num_scalers; i++) {
8965 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8966 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8967 id = i;
8968 pipe_config->pch_pfit.enabled = true;
8969 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8970 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8971 break;
8972 }
8973 }
bd2e244f 8974
a1b2278e
CK		 8975 scaler_state->scaler_id = id;
8976 if (id >= 0) {
8977 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8978 } else {
8979 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8980 }
8981}
8982
5724dbd1
DL		 8983static void
8984skylake_get_initial_plane_config(struct intel_crtc *crtc,
8985 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8986{
8987 struct drm_device *dev = crtc->base.dev;
8988 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8989 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8990 int pipe = crtc->pipe;
8991 int fourcc, pixel_format;
6761dd31 8992 unsigned int aligned_height;
bc8d7dff 8993 struct drm_framebuffer *fb;
1b842c89 8994 struct intel_framebuffer *intel_fb;
bc8d7dff 8995
d9806c9f 8996 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8997 if (!intel_fb) {
bc8d7dff
DL		 8998 DRM_DEBUG_KMS("failed to alloc fb\n");
8999 return;
9000 }
9001
1b842c89
DL		 9002 fb = &intel_fb->base;
9003
bc8d7dff 9004 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9005 if (!(val & PLANE_CTL_ENABLE))
9006 goto error;
9007
bc8d7dff
DL		 9008 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9009 fourcc = skl_format_to_fourcc(pixel_format,
9010 val & PLANE_CTL_ORDER_RGBX,
9011 val & PLANE_CTL_ALPHA_MASK);
9012 fb->pixel_format = fourcc;
9013 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9014
40f46283
DL		 9015 tiling = val & PLANE_CTL_TILED_MASK;
9016 switch (tiling) {
9017 case PLANE_CTL_TILED_LINEAR:
9018 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9019 break;
9020 case PLANE_CTL_TILED_X:
9021 plane_config->tiling = I915_TILING_X;
9022 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9023 break;
9024 case PLANE_CTL_TILED_Y:
9025 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9026 break;
9027 case PLANE_CTL_TILED_YF:
9028 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9029 break;
9030 default:
9031 MISSING_CASE(tiling);
9032 goto error;
9033 }
9034
bc8d7dff
DL		 9035 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9036 plane_config->base = base;
9037
9038 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9039
9040 val = I915_READ(PLANE_SIZE(pipe, 0));
9041 fb->height = ((val >> 16) & 0xfff) + 1;
9042 fb->width = ((val >> 0) & 0x1fff) + 1;
9043
9044 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9045 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9046 fb->pixel_format);
bc8d7dff
DL		 9047 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9048
9049 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9050 fb->pixel_format,
9051 fb->modifier[0]);
bc8d7dff 9052
f37b5c2b 9053 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9054
9055 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9056 pipe_name(pipe), fb->width, fb->height,
9057 fb->bits_per_pixel, base, fb->pitches[0],
9058 plane_config->size);
9059
2d14030b 9060 plane_config->fb = intel_fb;
bc8d7dff
DL		 9061 return;
9062
9063error:
9064 kfree(fb);
9065}
9066
2fa2fe9a 9067static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9068 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9069{
9070 struct drm_device *dev = crtc->base.dev;
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 uint32_t tmp;
9073
9074 tmp = I915_READ(PF_CTL(crtc->pipe));
9075
9076 if (tmp & PF_ENABLE) {
fd4daa9c 9077 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9080
9081 /* We currently do not free assignements of panel fitters on
9082 * ivb/hsw (since we don't use the higher upscaling modes which
9083 * differentiates them) so just WARN about this case for now. */
9084 if (IS_GEN7(dev)) {
9085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9086 PF_PIPE_SEL_IVB(crtc->pipe));
9087 }
2fa2fe9a 9088 }
79e53945
JB		 9089}
9090
5724dbd1
DL		 9091static void
9092ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9093 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9094{
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 u32 val, base, offset;
aeee5a49 9098 int pipe = crtc->pipe;
4c6baa59 9099 int fourcc, pixel_format;
6761dd31 9100 unsigned int aligned_height;
b113d5ee 9101 struct drm_framebuffer *fb;
1b842c89 9102 struct intel_framebuffer *intel_fb;
4c6baa59 9103
42a7b088
DL		 9104 val = I915_READ(DSPCNTR(pipe));
9105 if (!(val & DISPLAY_PLANE_ENABLE))
9106 return;
9107
d9806c9f 9108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9109 if (!intel_fb) {
4c6baa59
JB		 9110 DRM_DEBUG_KMS("failed to alloc fb\n");
9111 return;
9112 }
9113
1b842c89
DL		 9114 fb = &intel_fb->base;
9115
18c5247e
DV		 9116 if (INTEL_INFO(dev)->gen >= 4) {
9117 if (val & DISPPLANE_TILED) {
49af449b 9118 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9119 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9120 }
9121 }
4c6baa59
JB		 9122
9123 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9124 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9125 fb->pixel_format = fourcc;
9126 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9127
aeee5a49 9128 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9129 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9130 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9131 } else {
49af449b 9132 if (plane_config->tiling)
aeee5a49 9133 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9134 else
aeee5a49 9135 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9136 }
9137 plane_config->base = base;
9138
9139 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9140 fb->width = ((val >> 16) & 0xfff) + 1;
9141 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9142
9143 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9144 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9145
b113d5ee 9146 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9147 fb->pixel_format,
9148 fb->modifier[0]);
4c6baa59 9149
f37b5c2b 9150 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9151
2844a921
DL		 9152 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9153 pipe_name(pipe), fb->width, fb->height,
9154 fb->bits_per_pixel, base, fb->pitches[0],
9155 plane_config->size);
b113d5ee 9156
2d14030b 9157 plane_config->fb = intel_fb;
4c6baa59
JB		 9158}
9159
0e8ffe1b 9160static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9161 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9162{
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 uint32_t tmp;
9166
f458ebbc
DV		 9167 if (!intel_display_power_is_enabled(dev_priv,
9168 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9169 return false;
9170
e143a21c 9171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9173
0e8ffe1b
DV		 9174 tmp = I915_READ(PIPECONF(crtc->pipe));
9175 if (!(tmp & PIPECONF_ENABLE))
9176 return false;
9177
42571aef
VS		 9178 switch (tmp & PIPECONF_BPC_MASK) {
9179 case PIPECONF_6BPC:
9180 pipe_config->pipe_bpp = 18;
9181 break;
9182 case PIPECONF_8BPC:
9183 pipe_config->pipe_bpp = 24;
9184 break;
9185 case PIPECONF_10BPC:
9186 pipe_config->pipe_bpp = 30;
9187 break;
9188 case PIPECONF_12BPC:
9189 pipe_config->pipe_bpp = 36;
9190 break;
9191 default:
9192 break;
9193 }
9194
b5a9fa09
DV		 9195 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9196 pipe_config->limited_color_range = true;
9197
ab9412ba 9198 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9199 struct intel_shared_dpll *pll;
9200
88adfff1
DV		 9201 pipe_config->has_pch_encoder = true;
9202
627eb5a3
DV		 9203 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9204 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9205 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9206
9207 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9208
c0d43d62 9209 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9210 pipe_config->shared_dpll =
9211 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9212 } else {
9213 tmp = I915_READ(PCH_DPLL_SEL);
9214 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9216 else
9217 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9218 }
66e985c0
DV		 9219
9220 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9221
9222 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9223 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9224
9225 tmp = pipe_config->dpll_hw_state.dpll;
9226 pipe_config->pixel_multiplier =
9227 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9228 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9229
9230 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9231 } else {
9232 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9233 }
9234
1bd1bd80
DV		 9235 intel_get_pipe_timings(crtc, pipe_config);
9236
2fa2fe9a
DV		 9237 ironlake_get_pfit_config(crtc, pipe_config);
9238
0e8ffe1b
DV		 9239 return true;
9240}
9241
be256dc7
PZ		 9242static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9243{
9244 struct drm_device *dev = dev_priv->dev;
be256dc7 9245 struct intel_crtc *crtc;
be256dc7 9246
d3fcc808 9247 for_each_intel_crtc(dev, crtc)
e2c719b7 9248 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9249 pipe_name(crtc->pipe));
9250
e2c719b7
RC		 9251 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9252 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9253 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9255 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9256 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9257 "CPU PWM1 enabled\n");
c5107b87 9258 if (IS_HASWELL(dev))
e2c719b7 9259 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9260 "CPU PWM2 enabled\n");
e2c719b7 9261 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9262 "PCH PWM1 enabled\n");
e2c719b7 9263 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9264 "Utility pin enabled\n");
e2c719b7 9265 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9266
9926ada1
PZ		 9267 /*
9268 * In theory we can still leave IRQs enabled, as long as only the HPD
9269 * interrupts remain enabled. We used to check for that, but since it's
9270 * gen-specific and since we only disable LCPLL after we fully disable
9271 * the interrupts, the check below should be enough.
9272 */
e2c719b7 9273 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9274}
9275
9ccd5aeb
PZ		 9276static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9277{
9278 struct drm_device *dev = dev_priv->dev;
9279
9280 if (IS_HASWELL(dev))
9281 return I915_READ(D_COMP_HSW);
9282 else
9283 return I915_READ(D_COMP_BDW);
9284}
9285
3c4c9b81
PZ		 9286static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9287{
9288 struct drm_device *dev = dev_priv->dev;
9289
9290 if (IS_HASWELL(dev)) {
9291 mutex_lock(&dev_priv->rps.hw_lock);
9292 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9293 val))
f475dadf 9294 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9295 mutex_unlock(&dev_priv->rps.hw_lock);
9296 } else {
9ccd5aeb
PZ		 9297 I915_WRITE(D_COMP_BDW, val);
9298 POSTING_READ(D_COMP_BDW);
3c4c9b81 9299 }
be256dc7
PZ		 9300}
9301
9302/*
9303 * This function implements pieces of two sequences from BSpec:
9304 * - Sequence for display software to disable LCPLL
9305 * - Sequence for display software to allow package C8+
9306 * The steps implemented here are just the steps that actually touch the LCPLL
9307 * register. Callers should take care of disabling all the display engine
9308 * functions, doing the mode unset, fixing interrupts, etc.
9309 */
6ff58d53
PZ		 9310static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9311 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9312{
9313 uint32_t val;
9314
9315 assert_can_disable_lcpll(dev_priv);
9316
9317 val = I915_READ(LCPLL_CTL);
9318
9319 if (switch_to_fclk) {
9320 val |= LCPLL_CD_SOURCE_FCLK;
9321 I915_WRITE(LCPLL_CTL, val);
9322
9323 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9324 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9325 DRM_ERROR("Switching to FCLK failed\n");
9326
9327 val = I915_READ(LCPLL_CTL);
9328 }
9329
9330 val |= LCPLL_PLL_DISABLE;
9331 I915_WRITE(LCPLL_CTL, val);
9332 POSTING_READ(LCPLL_CTL);
9333
9334 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9335 DRM_ERROR("LCPLL still locked\n");
9336
9ccd5aeb 9337 val = hsw_read_dcomp(dev_priv);
be256dc7 9338 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9339 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9340 ndelay(100);
9341
9ccd5aeb
PZ		 9342 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9343 1))
be256dc7
PZ		 9344 DRM_ERROR("D_COMP RCOMP still in progress\n");
9345
9346 if (allow_power_down) {
9347 val = I915_READ(LCPLL_CTL);
9348 val |= LCPLL_POWER_DOWN_ALLOW;
9349 I915_WRITE(LCPLL_CTL, val);
9350 POSTING_READ(LCPLL_CTL);
9351 }
9352}
9353
9354/*
9355 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9356 * source.
9357 */
6ff58d53 9358static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9359{
9360 uint32_t val;
9361
9362 val = I915_READ(LCPLL_CTL);
9363
9364 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9365 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9366 return;
9367
a8a8bd54
PZ		 9368 /*
9369 * Make sure we're not on PC8 state before disabling PC8, otherwise
9370 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9371 */
59bad947 9372 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9373
be256dc7
PZ		 9374 if (val & LCPLL_POWER_DOWN_ALLOW) {
9375 val &= ~LCPLL_POWER_DOWN_ALLOW;
9376 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9377 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9378 }
9379
9ccd5aeb 9380 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9381 val |= D_COMP_COMP_FORCE;
9382 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9383 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9384
9385 val = I915_READ(LCPLL_CTL);
9386 val &= ~LCPLL_PLL_DISABLE;
9387 I915_WRITE(LCPLL_CTL, val);
9388
9389 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9390 DRM_ERROR("LCPLL not locked yet\n");
9391
9392 if (val & LCPLL_CD_SOURCE_FCLK) {
9393 val = I915_READ(LCPLL_CTL);
9394 val &= ~LCPLL_CD_SOURCE_FCLK;
9395 I915_WRITE(LCPLL_CTL, val);
9396
9397 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9398 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9399 DRM_ERROR("Switching back to LCPLL failed\n");
9400 }
215733fa 9401
59bad947 9402 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9403 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9404}
9405
765dab67
PZ		 9406/*
9407 * Package states C8 and deeper are really deep PC states that can only be
9408 * reached when all the devices on the system allow it, so even if the graphics
9409 * device allows PC8+, it doesn't mean the system will actually get to these
9410 * states. Our driver only allows PC8+ when going into runtime PM.
9411 *
9412 * The requirements for PC8+ are that all the outputs are disabled, the power
9413 * well is disabled and most interrupts are disabled, and these are also
9414 * requirements for runtime PM. When these conditions are met, we manually do
9415 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9416 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9417 * hang the machine.
9418 *
9419 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9420 * the state of some registers, so when we come back from PC8+ we need to
9421 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9422 * need to take care of the registers kept by RC6. Notice that this happens even
9423 * if we don't put the device in PCI D3 state (which is what currently happens
9424 * because of the runtime PM support).
9425 *
9426 * For more, read "Display Sequences for Package C8" on the hardware
9427 * documentation.
9428 */
a14cb6fc 9429void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9430{
c67a470b
PZ		 9431 struct drm_device *dev = dev_priv->dev;
9432 uint32_t val;
9433
c67a470b
PZ		 9434 DRM_DEBUG_KMS("Enabling package C8+\n");
9435
c67a470b
PZ		 9436 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9437 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9438 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9439 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9440 }
9441
9442 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9443 hsw_disable_lcpll(dev_priv, true, true);
9444}
9445
a14cb6fc 9446void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9447{
9448 struct drm_device *dev = dev_priv->dev;
9449 uint32_t val;
9450
c67a470b
PZ		 9451 DRM_DEBUG_KMS("Disabling package C8+\n");
9452
9453 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9454 lpt_init_pch_refclk(dev);
9455
9456 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9457 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9458 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9459 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9460 }
9461
9462 intel_prepare_ddi(dev);
c67a470b
PZ		 9463}
9464
27c329ed 9465static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9466{
a821fc46 9467 struct drm_device *dev = old_state->dev;
27c329ed 9468 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9469
27c329ed 9470 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9471}
9472
b432e5cf 9473/* compute the max rate for new configuration */
27c329ed 9474static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9475{
b432e5cf 9476 struct intel_crtc *intel_crtc;
27c329ed 9477 struct intel_crtc_state *crtc_state;
b432e5cf 9478 int max_pixel_rate = 0;
b432e5cf 9479
27c329ed
ML		 9480 for_each_intel_crtc(state->dev, intel_crtc) {
9481 int pixel_rate;
9482
9483 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9484 if (IS_ERR(crtc_state))
9485 return PTR_ERR(crtc_state);
9486
9487 if (!crtc_state->base.enable)
b432e5cf
VS		 9488 continue;
9489
27c329ed 9490 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9491
9492 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9493 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9494 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9495
9496 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9497 }
9498
9499 return max_pixel_rate;
9500}
9501
9502static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9503{
9504 struct drm_i915_private *dev_priv = dev->dev_private;
9505 uint32_t val, data;
9506 int ret;
9507
9508 if (WARN((I915_READ(LCPLL_CTL) &
9509 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9510 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9511 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9512 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9513 "trying to change cdclk frequency with cdclk not enabled\n"))
9514 return;
9515
9516 mutex_lock(&dev_priv->rps.hw_lock);
9517 ret = sandybridge_pcode_write(dev_priv,
9518 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9519 mutex_unlock(&dev_priv->rps.hw_lock);
9520 if (ret) {
9521 DRM_ERROR("failed to inform pcode about cdclk change\n");
9522 return;
9523 }
9524
9525 val = I915_READ(LCPLL_CTL);
9526 val |= LCPLL_CD_SOURCE_FCLK;
9527 I915_WRITE(LCPLL_CTL, val);
9528
9529 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9530 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9531 DRM_ERROR("Switching to FCLK failed\n");
9532
9533 val = I915_READ(LCPLL_CTL);
9534 val &= ~LCPLL_CLK_FREQ_MASK;
9535
9536 switch (cdclk) {
9537 case 450000:
9538 val |= LCPLL_CLK_FREQ_450;
9539 data = 0;
9540 break;
9541 case 540000:
9542 val |= LCPLL_CLK_FREQ_54O_BDW;
9543 data = 1;
9544 break;
9545 case 337500:
9546 val |= LCPLL_CLK_FREQ_337_5_BDW;
9547 data = 2;
9548 break;
9549 case 675000:
9550 val |= LCPLL_CLK_FREQ_675_BDW;
9551 data = 3;
9552 break;
9553 default:
9554 WARN(1, "invalid cdclk frequency\n");
9555 return;
9556 }
9557
9558 I915_WRITE(LCPLL_CTL, val);
9559
9560 val = I915_READ(LCPLL_CTL);
9561 val &= ~LCPLL_CD_SOURCE_FCLK;
9562 I915_WRITE(LCPLL_CTL, val);
9563
9564 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9565 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9566 DRM_ERROR("Switching back to LCPLL failed\n");
9567
9568 mutex_lock(&dev_priv->rps.hw_lock);
9569 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9570 mutex_unlock(&dev_priv->rps.hw_lock);
9571
9572 intel_update_cdclk(dev);
9573
9574 WARN(cdclk != dev_priv->cdclk_freq,
9575 "cdclk requested %d kHz but got %d kHz\n",
9576 cdclk, dev_priv->cdclk_freq);
9577}
9578
27c329ed 9579static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9580{
27c329ed
ML		 9581 struct drm_i915_private *dev_priv = to_i915(state->dev);
9582 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9583 int cdclk;
9584
9585 /*
9586 * FIXME should also account for plane ratio
9587 * once 64bpp pixel formats are supported.
9588 */
27c329ed 9589 if (max_pixclk > 540000)
b432e5cf 9590 cdclk = 675000;
27c329ed 9591 else if (max_pixclk > 450000)
b432e5cf 9592 cdclk = 540000;
27c329ed 9593 else if (max_pixclk > 337500)
b432e5cf
VS		 9594 cdclk = 450000;
9595 else
9596 cdclk = 337500;
9597
9598 /*
9599 * FIXME move the cdclk caclulation to
9600 * compute_config() so we can fail gracegully.
9601 */
9602 if (cdclk > dev_priv->max_cdclk_freq) {
9603 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9604 cdclk, dev_priv->max_cdclk_freq);
9605 cdclk = dev_priv->max_cdclk_freq;
9606 }
9607
27c329ed 9608 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9609
9610 return 0;
9611}
9612
27c329ed 9613static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9614{
27c329ed
ML		 9615 struct drm_device *dev = old_state->dev;
9616 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9617
27c329ed 9618 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9619}
9620
190f68c5
ACO		 9621static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9622 struct intel_crtc_state *crtc_state)
09b4ddf9 9623{
190f68c5 9624 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9625 return -EINVAL;
716c2e55 9626
c7653199 9627 crtc->lowfreq_avail = false;
644cef34 9628
c8f7a0db 9629 return 0;
79e53945
JB		 9630}
9631
3760b59c
S		 9632static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9633 enum port port,
9634 struct intel_crtc_state *pipe_config)
9635{
9636 switch (port) {
9637 case PORT_A:
9638 pipe_config->ddi_pll_sel = SKL_DPLL0;
9639 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9640 break;
9641 case PORT_B:
9642 pipe_config->ddi_pll_sel = SKL_DPLL1;
9643 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9644 break;
9645 case PORT_C:
9646 pipe_config->ddi_pll_sel = SKL_DPLL2;
9647 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9648 break;
9649 default:
9650 DRM_ERROR("Incorrect port type\n");
9651 }
9652}
9653
96b7dfb7
S		 9654static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9655 enum port port,
5cec258b 9656 struct intel_crtc_state *pipe_config)
96b7dfb7 9657{
3148ade7 9658 u32 temp, dpll_ctl1;
96b7dfb7
S		 9659
9660 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9661 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9662
9663 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9664 case SKL_DPLL0:
9665 /*
9666 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9667 * of the shared DPLL framework and thus needs to be read out
9668 * separately
9669 */
9670 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9671 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9672 break;
96b7dfb7
S		 9673 case SKL_DPLL1:
9674 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9675 break;
9676 case SKL_DPLL2:
9677 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9678 break;
9679 case SKL_DPLL3:
9680 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9681 break;
96b7dfb7
S		 9682 }
9683}
9684
7d2c8175
DL		 9685static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9686 enum port port,
5cec258b 9687 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9688{
9689 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9690
9691 switch (pipe_config->ddi_pll_sel) {
9692 case PORT_CLK_SEL_WRPLL1:
9693 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9694 break;
9695 case PORT_CLK_SEL_WRPLL2:
9696 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9697 break;
9698 }
9699}
9700
26804afd 9701static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9702 struct intel_crtc_state *pipe_config)
26804afd
DV		 9703{
9704 struct drm_device *dev = crtc->base.dev;
9705 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9706 struct intel_shared_dpll *pll;
26804afd
DV		 9707 enum port port;
9708 uint32_t tmp;
9709
9710 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9711
9712 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9713
96b7dfb7
S		 9714 if (IS_SKYLAKE(dev))
9715 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9716 else if (IS_BROXTON(dev))
9717 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9718 else
9719 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9720
d452c5b6
DV		 9721 if (pipe_config->shared_dpll >= 0) {
9722 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9723
9724 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9725 &pipe_config->dpll_hw_state));
9726 }
9727
26804afd
DV		 9728 /*
9729 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9730 * DDI E. So just check whether this pipe is wired to DDI E and whether
9731 * the PCH transcoder is on.
9732 */
ca370455
DL		 9733 if (INTEL_INFO(dev)->gen < 9 &&
9734 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9735 pipe_config->has_pch_encoder = true;
9736
9737 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9738 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9739 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9740
9741 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9742 }
9743}
9744
0e8ffe1b 9745static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9746 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9747{
9748 struct drm_device *dev = crtc->base.dev;
9749 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9750 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9751 uint32_t tmp;
9752
f458ebbc 9753 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9754 POWER_DOMAIN_PIPE(crtc->pipe)))
9755 return false;
9756
e143a21c 9757 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9758 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9759
eccb140b
DV		 9760 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9761 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9762 enum pipe trans_edp_pipe;
9763 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9764 default:
9765 WARN(1, "unknown pipe linked to edp transcoder\n");
9766 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9767 case TRANS_DDI_EDP_INPUT_A_ON:
9768 trans_edp_pipe = PIPE_A;
9769 break;
9770 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9771 trans_edp_pipe = PIPE_B;
9772 break;
9773 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9774 trans_edp_pipe = PIPE_C;
9775 break;
9776 }
9777
9778 if (trans_edp_pipe == crtc->pipe)
9779 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9780 }
9781
f458ebbc 9782 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9783 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9784 return false;
9785
eccb140b 9786 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9787 if (!(tmp & PIPECONF_ENABLE))
9788 return false;
9789
26804afd 9790 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9791
1bd1bd80
DV		 9792 intel_get_pipe_timings(crtc, pipe_config);
9793
a1b2278e
CK		 9794 if (INTEL_INFO(dev)->gen >= 9) {
9795 skl_init_scalers(dev, crtc, pipe_config);
9796 }
9797
2fa2fe9a 9798 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9799
9800 if (INTEL_INFO(dev)->gen >= 9) {
9801 pipe_config->scaler_state.scaler_id = -1;
9802 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9803 }
9804
bd2e244f 9805 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9806 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9807 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9808 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9809 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9810 else
9811 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9812 }
88adfff1 9813
e59150dc
JB		 9814 if (IS_HASWELL(dev))
9815 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9816 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9817
ebb69c95
CT		 9818 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9819 pipe_config->pixel_multiplier =
9820 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9821 } else {
9822 pipe_config->pixel_multiplier = 1;
9823 }
6c49f241 9824
0e8ffe1b
DV		 9825 return true;
9826}
9827
560b85bb
CW		 9828static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9829{
9830 struct drm_device *dev = crtc->dev;
9831 struct drm_i915_private *dev_priv = dev->dev_private;
9832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9833 uint32_t cntl = 0, size = 0;
560b85bb 9834
dc41c154 9835 if (base) {
3dd512fb
MR		 9836 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9837 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9838 unsigned int stride = roundup_pow_of_two(width) * 4;
9839
9840 switch (stride) {
9841 default:
9842 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9843 width, stride);
9844 stride = 256;
9845 /* fallthrough */
9846 case 256:
9847 case 512:
9848 case 1024:
9849 case 2048:
9850 break;
4b0e333e
CW		 9851 }
9852
dc41c154
VS		 9853 cntl |= CURSOR_ENABLE |
9854 CURSOR_GAMMA_ENABLE |
9855 CURSOR_FORMAT_ARGB |
9856 CURSOR_STRIDE(stride);
9857
9858 size = (height << 12) | width;
4b0e333e 9859 }
560b85bb 9860
dc41c154
VS		 9861 if (intel_crtc->cursor_cntl != 0 &&
9862 (intel_crtc->cursor_base != base ||
9863 intel_crtc->cursor_size != size ||
9864 intel_crtc->cursor_cntl != cntl)) {
9865 /* On these chipsets we can only modify the base/size/stride
9866 * whilst the cursor is disabled.
9867 */
9868 I915_WRITE(_CURACNTR, 0);
4b0e333e 9869 POSTING_READ(_CURACNTR);
dc41c154 9870 intel_crtc->cursor_cntl = 0;
4b0e333e 9871 }
560b85bb 9872
99d1f387 9873 if (intel_crtc->cursor_base != base) {
9db4a9c7 9874 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9875 intel_crtc->cursor_base = base;
9876 }
4726e0b0 9877
dc41c154
VS		 9878 if (intel_crtc->cursor_size != size) {
9879 I915_WRITE(CURSIZE, size);
9880 intel_crtc->cursor_size = size;
4b0e333e 9881 }
560b85bb 9882
4b0e333e 9883 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9884 I915_WRITE(_CURACNTR, cntl);
9885 POSTING_READ(_CURACNTR);
4b0e333e 9886 intel_crtc->cursor_cntl = cntl;
560b85bb 9887 }
560b85bb
CW		 9888}
9889
560b85bb 9890static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9891{
9892 struct drm_device *dev = crtc->dev;
9893 struct drm_i915_private *dev_priv = dev->dev_private;
9894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9895 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9896 uint32_t cntl;
9897
9898 cntl = 0;
9899 if (base) {
9900 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9901 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9902 case 64:
9903 cntl |= CURSOR_MODE_64_ARGB_AX;
9904 break;
9905 case 128:
9906 cntl |= CURSOR_MODE_128_ARGB_AX;
9907 break;
9908 case 256:
9909 cntl |= CURSOR_MODE_256_ARGB_AX;
9910 break;
9911 default:
3dd512fb 9912 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9913 return;
65a21cd6 9914 }
4b0e333e 9915 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9916
9917 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9918 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9919 }
65a21cd6 9920
8e7d688b 9921 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9922 cntl |= CURSOR_ROTATE_180;
9923
4b0e333e
CW		 9924 if (intel_crtc->cursor_cntl != cntl) {
9925 I915_WRITE(CURCNTR(pipe), cntl);
9926 POSTING_READ(CURCNTR(pipe));
9927 intel_crtc->cursor_cntl = cntl;
65a21cd6 9928 }
4b0e333e 9929
65a21cd6 9930 /* and commit changes on next vblank */
5efb3e28
VS		 9931 I915_WRITE(CURBASE(pipe), base);
9932 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9933
9934 intel_crtc->cursor_base = base;
65a21cd6
JB		 9935}
9936
cda4b7d3 9937/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9938static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9939 bool on)
cda4b7d3
CW		 9940{
9941 struct drm_device *dev = crtc->dev;
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9945 int x = crtc->cursor_x;
9946 int y = crtc->cursor_y;
d6e4db15 9947 u32 base = 0, pos = 0;
cda4b7d3 9948
d6e4db15 9949 if (on)
cda4b7d3 9950 base = intel_crtc->cursor_addr;
cda4b7d3 9951
6e3c9717 9952 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9953 base = 0;
9954
6e3c9717 9955 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9956 base = 0;
9957
9958 if (x < 0) {
3dd512fb 9959 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9960 base = 0;
9961
9962 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9963 x = -x;
9964 }
9965 pos |= x << CURSOR_X_SHIFT;
9966
9967 if (y < 0) {
3dd512fb 9968 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9969 base = 0;
9970
9971 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9972 y = -y;
9973 }
9974 pos |= y << CURSOR_Y_SHIFT;
9975
4b0e333e 9976 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9977 return;
9978
5efb3e28
VS		 9979 I915_WRITE(CURPOS(pipe), pos);
9980
4398ad45
VS		 9981 /* ILK+ do this automagically */
9982 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9983 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9984 base += (intel_crtc->base.cursor->state->crtc_h *
9985 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9986 }
9987
8ac54669 9988 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9989 i845_update_cursor(crtc, base);
9990 else
9991 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9992}
9993
dc41c154
VS		 9994static bool cursor_size_ok(struct drm_device *dev,
9995 uint32_t width, uint32_t height)
9996{
9997 if (width == 0 || height == 0)
9998 return false;
9999
10000 /*
10001 * 845g/865g are special in that they are only limited by
10002 * the width of their cursors, the height is arbitrary up to
10003 * the precision of the register. Everything else requires
10004 * square cursors, limited to a few power-of-two sizes.
10005 */
10006 if (IS_845G(dev) || IS_I865G(dev)) {
10007 if ((width & 63) != 0)
10008 return false;
10009
10010 if (width > (IS_845G(dev) ? 64 : 512))
10011 return false;
10012
10013 if (height > 1023)
10014 return false;
10015 } else {
10016 switch (width | height) {
10017 case 256:
10018 case 128:
10019 if (IS_GEN2(dev))
10020 return false;
10021 case 64:
10022 break;
10023 default:
10024 return false;
10025 }
10026 }
10027
10028 return true;
10029}
10030
79e53945 10031static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10032 u16 *blue, uint32_t start, uint32_t size)
79e53945 10033{
7203425a 10034 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10036
7203425a 10037 for (i = start; i < end; i++) {
79e53945
JB		 10038 intel_crtc->lut_r[i] = red[i] >> 8;
10039 intel_crtc->lut_g[i] = green[i] >> 8;
10040 intel_crtc->lut_b[i] = blue[i] >> 8;
10041 }
10042
10043 intel_crtc_load_lut(crtc);
10044}
10045
79e53945
JB		 10046/* VESA 640x480x72Hz mode to set on the pipe */
10047static struct drm_display_mode load_detect_mode = {
10048 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10049 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10050};
10051
a8bb6818
DV		 10052struct drm_framebuffer *
10053__intel_framebuffer_create(struct drm_device *dev,
10054 struct drm_mode_fb_cmd2 *mode_cmd,
10055 struct drm_i915_gem_object *obj)
d2dff872
CW		 10056{
10057 struct intel_framebuffer *intel_fb;
10058 int ret;
10059
10060 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10061 if (!intel_fb) {
6ccb81f2 10062 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10063 return ERR_PTR(-ENOMEM);
10064 }
10065
10066 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10067 if (ret)
10068 goto err;
d2dff872
CW		 10069
10070 return &intel_fb->base;
dd4916c5 10071err:
6ccb81f2 10072 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10073 kfree(intel_fb);
10074
10075 return ERR_PTR(ret);
d2dff872
CW		 10076}
10077
b5ea642a 10078static struct drm_framebuffer *
a8bb6818
DV		 10079intel_framebuffer_create(struct drm_device *dev,
10080 struct drm_mode_fb_cmd2 *mode_cmd,
10081 struct drm_i915_gem_object *obj)
10082{
10083 struct drm_framebuffer *fb;
10084 int ret;
10085
10086 ret = i915_mutex_lock_interruptible(dev);
10087 if (ret)
10088 return ERR_PTR(ret);
10089 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10090 mutex_unlock(&dev->struct_mutex);
10091
10092 return fb;
10093}
10094
d2dff872
CW		 10095static u32
10096intel_framebuffer_pitch_for_width(int width, int bpp)
10097{
10098 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10099 return ALIGN(pitch, 64);
10100}
10101
10102static u32
10103intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10104{
10105 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10106 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10107}
10108
10109static struct drm_framebuffer *
10110intel_framebuffer_create_for_mode(struct drm_device *dev,
10111 struct drm_display_mode *mode,
10112 int depth, int bpp)
10113{
10114 struct drm_i915_gem_object *obj;
0fed39bd 10115 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10116
10117 obj = i915_gem_alloc_object(dev,
10118 intel_framebuffer_size_for_mode(mode, bpp));
10119 if (obj == NULL)
10120 return ERR_PTR(-ENOMEM);
10121
10122 mode_cmd.width = mode->hdisplay;
10123 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10124 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10125 bpp);
5ca0c34a 10126 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10127
10128 return intel_framebuffer_create(dev, &mode_cmd, obj);
10129}
10130
10131static struct drm_framebuffer *
10132mode_fits_in_fbdev(struct drm_device *dev,
10133 struct drm_display_mode *mode)
10134{
4520f53a 10135#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10136 struct drm_i915_private *dev_priv = dev->dev_private;
10137 struct drm_i915_gem_object *obj;
10138 struct drm_framebuffer *fb;
10139
4c0e5528 10140 if (!dev_priv->fbdev)
d2dff872
CW		 10141 return NULL;
10142
4c0e5528 10143 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10144 return NULL;
10145
4c0e5528
DV		 10146 obj = dev_priv->fbdev->fb->obj;
10147 BUG_ON(!obj);
10148
8bcd4553 10149 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10150 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10151 fb->bits_per_pixel))
d2dff872
CW		 10152 return NULL;
10153
01f2c773 10154 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10155 return NULL;
10156
10157 return fb;
4520f53a
DV		 10158#else
10159 return NULL;
10160#endif
d2dff872
CW		 10161}
10162
d3a40d1b
ACO		 10163static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10164 struct drm_crtc *crtc,
10165 struct drm_display_mode *mode,
10166 struct drm_framebuffer *fb,
10167 int x, int y)
10168{
10169 struct drm_plane_state *plane_state;
10170 int hdisplay, vdisplay;
10171 int ret;
10172
10173 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10174 if (IS_ERR(plane_state))
10175 return PTR_ERR(plane_state);
10176
10177 if (mode)
10178 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10179 else
10180 hdisplay = vdisplay = 0;
10181
10182 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10183 if (ret)
10184 return ret;
10185 drm_atomic_set_fb_for_plane(plane_state, fb);
10186 plane_state->crtc_x = 0;
10187 plane_state->crtc_y = 0;
10188 plane_state->crtc_w = hdisplay;
10189 plane_state->crtc_h = vdisplay;
10190 plane_state->src_x = x << 16;
10191 plane_state->src_y = y << 16;
10192 plane_state->src_w = hdisplay << 16;
10193 plane_state->src_h = vdisplay << 16;
10194
10195 return 0;
10196}
10197
d2434ab7 10198bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10199 struct drm_display_mode *mode,
51fd371b
RC		 10200 struct intel_load_detect_pipe *old,
10201 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10202{
10203 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10204 struct intel_encoder *intel_encoder =
10205 intel_attached_encoder(connector);
79e53945 10206 struct drm_crtc *possible_crtc;
4ef69c7a 10207 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10208 struct drm_crtc *crtc = NULL;
10209 struct drm_device *dev = encoder->dev;
94352cf9 10210 struct drm_framebuffer *fb;
51fd371b 10211 struct drm_mode_config *config = &dev->mode_config;
83a57153 10212 struct drm_atomic_state *state = NULL;
944b0c76 10213 struct drm_connector_state *connector_state;
4be07317 10214 struct intel_crtc_state *crtc_state;
51fd371b 10215 int ret, i = -1;
79e53945 10216
d2dff872 10217 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10218 connector->base.id, connector->name,
8e329a03 10219 encoder->base.id, encoder->name);
d2dff872 10220
51fd371b
RC		 10221retry:
10222 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10223 if (ret)
ad3c558f 10224 goto fail;
6e9f798d 10225
79e53945
JB		 10226 /*
10227 * Algorithm gets a little messy:
7a5e4805 10228 *
79e53945
JB		 10229 * - if the connector already has an assigned crtc, use it (but make
10230 * sure it's on first)
7a5e4805 10231 *
79e53945
JB		 10232 * - try to find the first unused crtc that can drive this connector,
10233 * and use that if we find one
79e53945
JB		 10234 */
10235
10236 /* See if we already have a CRTC for this connector */
10237 if (encoder->crtc) {
10238 crtc = encoder->crtc;
8261b191 10239
51fd371b 10240 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10241 if (ret)
ad3c558f 10242 goto fail;
4d02e2de 10243 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10244 if (ret)
ad3c558f 10245 goto fail;
7b24056b 10246
24218aac 10247 old->dpms_mode = connector->dpms;
8261b191
CW		 10248 old->load_detect_temp = false;
10249
10250 /* Make sure the crtc and connector are running */
24218aac
DV		 10251 if (connector->dpms != DRM_MODE_DPMS_ON)
10252 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10253
7173188d 10254 return true;
79e53945
JB		 10255 }
10256
10257 /* Find an unused one (if possible) */
70e1e0ec 10258 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10259 i++;
10260 if (!(encoder->possible_crtcs & (1 << i)))
10261 continue;
83d65738 10262 if (possible_crtc->state->enable)
a459249c 10263 continue;
a459249c
VS		 10264
10265 crtc = possible_crtc;
10266 break;
79e53945
JB		 10267 }
10268
10269 /*
10270 * If we didn't find an unused CRTC, don't use any.
10271 */
10272 if (!crtc) {
7173188d 10273 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10274 goto fail;
79e53945
JB		 10275 }
10276
51fd371b
RC		 10277 ret = drm_modeset_lock(&crtc->mutex, ctx);
10278 if (ret)
ad3c558f 10279 goto fail;
4d02e2de
DV		 10280 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10281 if (ret)
ad3c558f 10282 goto fail;
79e53945
JB		 10283
10284 intel_crtc = to_intel_crtc(crtc);
24218aac 10285 old->dpms_mode = connector->dpms;
8261b191 10286 old->load_detect_temp = true;
d2dff872 10287 old->release_fb = NULL;
79e53945 10288
83a57153
ACO		 10289 state = drm_atomic_state_alloc(dev);
10290 if (!state)
10291 return false;
10292
10293 state->acquire_ctx = ctx;
10294
944b0c76
ACO		 10295 connector_state = drm_atomic_get_connector_state(state, connector);
10296 if (IS_ERR(connector_state)) {
10297 ret = PTR_ERR(connector_state);
10298 goto fail;
10299 }
10300
10301 connector_state->crtc = crtc;
10302 connector_state->best_encoder = &intel_encoder->base;
10303
4be07317
ACO		 10304 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10305 if (IS_ERR(crtc_state)) {
10306 ret = PTR_ERR(crtc_state);
10307 goto fail;
10308 }
10309
49d6fa21 10310 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10311
6492711d
CW		 10312 if (!mode)
10313 mode = &load_detect_mode;
79e53945 10314
d2dff872
CW		 10315 /* We need a framebuffer large enough to accommodate all accesses
10316 * that the plane may generate whilst we perform load detection.
10317 * We can not rely on the fbcon either being present (we get called
10318 * during its initialisation to detect all boot displays, or it may
10319 * not even exist) or that it is large enough to satisfy the
10320 * requested mode.
10321 */
94352cf9
DV		 10322 fb = mode_fits_in_fbdev(dev, mode);
10323 if (fb == NULL) {
d2dff872 10324 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10325 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10326 old->release_fb = fb;
d2dff872
CW		 10327 } else
10328 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10329 if (IS_ERR(fb)) {
d2dff872 10330 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10331 goto fail;
79e53945 10332 }
79e53945 10333
d3a40d1b
ACO		 10334 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10335 if (ret)
10336 goto fail;
10337
8c7b5ccb
ACO		 10338 drm_mode_copy(&crtc_state->base.mode, mode);
10339
74c090b1 10340 if (drm_atomic_commit(state)) {
6492711d 10341 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10342 if (old->release_fb)
10343 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10344 goto fail;
79e53945 10345 }
9128b040 10346 crtc->primary->crtc = crtc;
7173188d 10347
79e53945 10348 /* let the connector get through one full cycle before testing */
9d0498a2 10349 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10350 return true;
412b61d8 10351
ad3c558f 10352fail:
e5d958ef
ACO		 10353 drm_atomic_state_free(state);
10354 state = NULL;
83a57153 10355
51fd371b
RC		 10356 if (ret == -EDEADLK) {
10357 drm_modeset_backoff(ctx);
10358 goto retry;
10359 }
10360
412b61d8 10361 return false;
79e53945
JB		 10362}
10363
d2434ab7 10364void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10365 struct intel_load_detect_pipe *old,
10366 struct drm_modeset_acquire_ctx *ctx)
79e53945 10367{
83a57153 10368 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10369 struct intel_encoder *intel_encoder =
10370 intel_attached_encoder(connector);
4ef69c7a 10371 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10372 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10374 struct drm_atomic_state *state;
944b0c76 10375 struct drm_connector_state *connector_state;
4be07317 10376 struct intel_crtc_state *crtc_state;
d3a40d1b 10377 int ret;
79e53945 10378
d2dff872 10379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10380 connector->base.id, connector->name,
8e329a03 10381 encoder->base.id, encoder->name);
d2dff872 10382
8261b191 10383 if (old->load_detect_temp) {
83a57153 10384 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10385 if (!state)
10386 goto fail;
83a57153
ACO		 10387
10388 state->acquire_ctx = ctx;
10389
944b0c76
ACO		 10390 connector_state = drm_atomic_get_connector_state(state, connector);
10391 if (IS_ERR(connector_state))
10392 goto fail;
10393
4be07317
ACO		 10394 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10395 if (IS_ERR(crtc_state))
10396 goto fail;
10397
944b0c76
ACO		 10398 connector_state->best_encoder = NULL;
10399 connector_state->crtc = NULL;
10400
49d6fa21 10401 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10402
d3a40d1b
ACO		 10403 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10404 0, 0);
10405 if (ret)
10406 goto fail;
10407
74c090b1 10408 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10409 if (ret)
10410 goto fail;
d2dff872 10411
36206361
DV		 10412 if (old->release_fb) {
10413 drm_framebuffer_unregister_private(old->release_fb);
10414 drm_framebuffer_unreference(old->release_fb);
10415 }
d2dff872 10416
0622a53c 10417 return;
79e53945
JB		 10418 }
10419
c751ce4f 10420 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10421 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10422 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10423
10424 return;
10425fail:
10426 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10427 drm_atomic_state_free(state);
79e53945
JB		 10428}
10429
da4a1efa 10430static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10431 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10432{
10433 struct drm_i915_private *dev_priv = dev->dev_private;
10434 u32 dpll = pipe_config->dpll_hw_state.dpll;
10435
10436 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10437 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10438 else if (HAS_PCH_SPLIT(dev))
10439 return 120000;
10440 else if (!IS_GEN2(dev))
10441 return 96000;
10442 else
10443 return 48000;
10444}
10445
79e53945 10446/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10447static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10448 struct intel_crtc_state *pipe_config)
79e53945 10449{
f1f644dc 10450 struct drm_device *dev = crtc->base.dev;
79e53945 10451 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10452 int pipe = pipe_config->cpu_transcoder;
293623f7 10453 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10454 u32 fp;
10455 intel_clock_t clock;
dccbea3b 10456 int port_clock;
da4a1efa 10457 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10458
10459 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10460 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10461 else
293623f7 10462 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10463
10464 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10465 if (IS_PINEVIEW(dev)) {
10466 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10467 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10468 } else {
10469 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10470 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471 }
10472
a6c45cf0 10473 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10474 if (IS_PINEVIEW(dev))
10475 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10476 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10477 else
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10479 DPLL_FPA01_P1_POST_DIV_SHIFT);
10480
10481 switch (dpll & DPLL_MODE_MASK) {
10482 case DPLLB_MODE_DAC_SERIAL:
10483 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10484 5 : 10;
10485 break;
10486 case DPLLB_MODE_LVDS:
10487 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10488 7 : 14;
10489 break;
10490 default:
28c97730 10491 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10492 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10493 return;
79e53945
JB		 10494 }
10495
ac58c3f0 10496 if (IS_PINEVIEW(dev))
dccbea3b 10497 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10498 else
dccbea3b 10499 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10500 } else {
0fb58223 10501 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10502 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10503
10504 if (is_lvds) {
10505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10506 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10507
10508 if (lvds & LVDS_CLKB_POWER_UP)
10509 clock.p2 = 7;
10510 else
10511 clock.p2 = 14;
79e53945
JB		 10512 } else {
10513 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10514 clock.p1 = 2;
10515 else {
10516 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10517 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10518 }
10519 if (dpll & PLL_P2_DIVIDE_BY_4)
10520 clock.p2 = 4;
10521 else
10522 clock.p2 = 2;
79e53945 10523 }
da4a1efa 10524
dccbea3b 10525 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10526 }
10527
18442d08
VS		 10528 /*
10529 * This value includes pixel_multiplier. We will use
241bfc38 10530 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10531 * encoder's get_config() function.
10532 */
dccbea3b 10533 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10534}
10535
6878da05
VS		 10536int intel_dotclock_calculate(int link_freq,
10537 const struct intel_link_m_n *m_n)
f1f644dc 10538{
f1f644dc
JB		 10539 /*
10540 * The calculation for the data clock is:
1041a02f 10541 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10542 * But we want to avoid losing precison if possible, so:
1041a02f 10543 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10544 *
10545 * and the link clock is simpler:
1041a02f 10546 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10547 */
10548
6878da05
VS		 10549 if (!m_n->link_n)
10550 return 0;
f1f644dc 10551
6878da05
VS		 10552 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10553}
f1f644dc 10554
18442d08 10555static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10556 struct intel_crtc_state *pipe_config)
6878da05
VS		 10557{
10558 struct drm_device *dev = crtc->base.dev;
79e53945 10559
18442d08
VS		 10560 /* read out port_clock from the DPLL */
10561 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10562
f1f644dc 10563 /*
18442d08 10564 * This value does not include pixel_multiplier.
241bfc38 10565 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10566 * agree once we know their relationship in the encoder's
10567 * get_config() function.
79e53945 10568 */
2d112de7 10569 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10570 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10571 &pipe_config->fdi_m_n);
79e53945
JB		 10572}
10573
10574/** Returns the currently programmed mode of the given pipe. */
10575struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10576 struct drm_crtc *crtc)
10577{
548f245b 10578 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10580 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10581 struct drm_display_mode *mode;
5cec258b 10582 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10583 int htot = I915_READ(HTOTAL(cpu_transcoder));
10584 int hsync = I915_READ(HSYNC(cpu_transcoder));
10585 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10586 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10587 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10588
10589 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10590 if (!mode)
10591 return NULL;
10592
f1f644dc
JB		 10593 /*
10594 * Construct a pipe_config sufficient for getting the clock info
10595 * back out of crtc_clock_get.
10596 *
10597 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10598 * to use a real value here instead.
10599 */
293623f7 10600 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10601 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10602 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10603 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10604 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10605 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10606
773ae034 10607 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10608 mode->hdisplay = (htot & 0xffff) + 1;
10609 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10610 mode->hsync_start = (hsync & 0xffff) + 1;
10611 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10612 mode->vdisplay = (vtot & 0xffff) + 1;
10613 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10614 mode->vsync_start = (vsync & 0xffff) + 1;
10615 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10616
10617 drm_mode_set_name(mode);
79e53945
JB		 10618
10619 return mode;
10620}
10621
f047e395
CW		 10622void intel_mark_busy(struct drm_device *dev)
10623{
c67a470b
PZ		 10624 struct drm_i915_private *dev_priv = dev->dev_private;
10625
f62a0076
CW		 10626 if (dev_priv->mm.busy)
10627 return;
10628
43694d69 10629 intel_runtime_pm_get(dev_priv);
c67a470b 10630 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10631 if (INTEL_INFO(dev)->gen >= 6)
10632 gen6_rps_busy(dev_priv);
f62a0076 10633 dev_priv->mm.busy = true;
f047e395
CW		 10634}
10635
10636void intel_mark_idle(struct drm_device *dev)
652c393a 10637{
c67a470b 10638 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10639
f62a0076
CW		 10640 if (!dev_priv->mm.busy)
10641 return;
10642
10643 dev_priv->mm.busy = false;
10644
3d13ef2e 10645 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10646 gen6_rps_idle(dev->dev_private);
bb4cdd53 10647
43694d69 10648 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10649}
10650
79e53945
JB		 10651static void intel_crtc_destroy(struct drm_crtc *crtc)
10652{
10653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10654 struct drm_device *dev = crtc->dev;
10655 struct intel_unpin_work *work;
67e77c5a 10656
5e2d7afc 10657 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10658 work = intel_crtc->unpin_work;
10659 intel_crtc->unpin_work = NULL;
5e2d7afc 10660 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10661
10662 if (work) {
10663 cancel_work_sync(&work->work);
10664 kfree(work);
10665 }
79e53945
JB		 10666
10667 drm_crtc_cleanup(crtc);
67e77c5a 10668
79e53945
JB		 10669 kfree(intel_crtc);
10670}
10671
6b95a207
KH		 10672static void intel_unpin_work_fn(struct work_struct *__work)
10673{
10674 struct intel_unpin_work *work =
10675 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10676 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10677 struct drm_device *dev = crtc->base.dev;
10678 struct drm_plane *primary = crtc->base.primary;
6b95a207 10679
b4a98e57 10680 mutex_lock(&dev->struct_mutex);
a9ff8714 10681 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10682 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10683
f06cc1b9 10684 if (work->flip_queued_req)
146d84f0 10685 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10686 mutex_unlock(&dev->struct_mutex);
10687
a9ff8714 10688 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10689 drm_framebuffer_unreference(work->old_fb);
f99d7069 10690
a9ff8714
VS		 10691 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10692 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10693
6b95a207
KH		 10694 kfree(work);
10695}
10696
1afe3e9d 10697static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10698 struct drm_crtc *crtc)
6b95a207 10699{
6b95a207
KH		 10700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10701 struct intel_unpin_work *work;
6b95a207
KH		 10702 unsigned long flags;
10703
10704 /* Ignore early vblank irqs */
10705 if (intel_crtc == NULL)
10706 return;
10707
f326038a
DV		 10708 /*
10709 * This is called both by irq handlers and the reset code (to complete
10710 * lost pageflips) so needs the full irqsave spinlocks.
10711 */
6b95a207
KH		 10712 spin_lock_irqsave(&dev->event_lock, flags);
10713 work = intel_crtc->unpin_work;
e7d841ca
CW		 10714
10715 /* Ensure we don't miss a work->pending update ... */
10716 smp_rmb();
10717
10718 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10719 spin_unlock_irqrestore(&dev->event_lock, flags);
10720 return;
10721 }
10722
d6bbafa1 10723 page_flip_completed(intel_crtc);
0af7e4df 10724
6b95a207 10725 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10726}
10727
1afe3e9d
JB		 10728void intel_finish_page_flip(struct drm_device *dev, int pipe)
10729{
fbee40df 10730 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10731 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10732
49b14a5c 10733 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10734}
10735
10736void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10737{
fbee40df 10738 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10739 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10740
49b14a5c 10741 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10742}
10743
75f7f3ec
VS		 10744/* Is 'a' after or equal to 'b'? */
10745static bool g4x_flip_count_after_eq(u32 a, u32 b)
10746{
10747 return !((a - b) & 0x80000000);
10748}
10749
10750static bool page_flip_finished(struct intel_crtc *crtc)
10751{
10752 struct drm_device *dev = crtc->base.dev;
10753 struct drm_i915_private *dev_priv = dev->dev_private;
10754
bdfa7542
VS		 10755 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10756 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10757 return true;
10758
75f7f3ec
VS		 10759 /*
10760 * The relevant registers doen't exist on pre-ctg.
10761 * As the flip done interrupt doesn't trigger for mmio
10762 * flips on gmch platforms, a flip count check isn't
10763 * really needed there. But since ctg has the registers,
10764 * include it in the check anyway.
10765 */
10766 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10767 return true;
10768
10769 /*
10770 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10771 * used the same base address. In that case the mmio flip might
10772 * have completed, but the CS hasn't even executed the flip yet.
10773 *
10774 * A flip count check isn't enough as the CS might have updated
10775 * the base address just after start of vblank, but before we
10776 * managed to process the interrupt. This means we'd complete the
10777 * CS flip too soon.
10778 *
10779 * Combining both checks should get us a good enough result. It may
10780 * still happen that the CS flip has been executed, but has not
10781 * yet actually completed. But in case the base address is the same
10782 * anyway, we don't really care.
10783 */
10784 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10785 crtc->unpin_work->gtt_offset &&
10786 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10787 crtc->unpin_work->flip_count);
10788}
10789
6b95a207
KH		 10790void intel_prepare_page_flip(struct drm_device *dev, int plane)
10791{
fbee40df 10792 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10793 struct intel_crtc *intel_crtc =
10794 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10795 unsigned long flags;
10796
f326038a
DV		 10797
10798 /*
10799 * This is called both by irq handlers and the reset code (to complete
10800 * lost pageflips) so needs the full irqsave spinlocks.
10801 *
10802 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10803 * generate a page-flip completion irq, i.e. every modeset
10804 * is also accompanied by a spurious intel_prepare_page_flip().
10805 */
6b95a207 10806 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10807 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10808 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10809 spin_unlock_irqrestore(&dev->event_lock, flags);
10810}
10811
eba905b2 10812static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10813{
10814 /* Ensure that the work item is consistent when activating it ... */
10815 smp_wmb();
10816 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10817 /* and that it is marked active as soon as the irq could fire. */
10818 smp_wmb();
10819}
10820
8c9f3aaf
JB		 10821static int intel_gen2_queue_flip(struct drm_device *dev,
10822 struct drm_crtc *crtc,
10823 struct drm_framebuffer *fb,
ed8d1975 10824 struct drm_i915_gem_object *obj,
6258fbe2 10825 struct drm_i915_gem_request *req,
ed8d1975 10826 uint32_t flags)
8c9f3aaf 10827{
6258fbe2 10828 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10830 u32 flip_mask;
10831 int ret;
10832
5fb9de1a 10833 ret = intel_ring_begin(req, 6);
8c9f3aaf 10834 if (ret)
4fa62c89 10835 return ret;
8c9f3aaf
JB		 10836
10837 /* Can't queue multiple flips, so wait for the previous
10838 * one to finish before executing the next.
10839 */
10840 if (intel_crtc->plane)
10841 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10842 else
10843 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10844 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10845 intel_ring_emit(ring, MI_NOOP);
10846 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10847 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10848 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10849 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10850 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10851
10852 intel_mark_page_flip_active(intel_crtc);
83d4092b 10853 return 0;
8c9f3aaf
JB		 10854}
10855
10856static int intel_gen3_queue_flip(struct drm_device *dev,
10857 struct drm_crtc *crtc,
10858 struct drm_framebuffer *fb,
ed8d1975 10859 struct drm_i915_gem_object *obj,
6258fbe2 10860 struct drm_i915_gem_request *req,
ed8d1975 10861 uint32_t flags)
8c9f3aaf 10862{
6258fbe2 10863 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10865 u32 flip_mask;
10866 int ret;
10867
5fb9de1a 10868 ret = intel_ring_begin(req, 6);
8c9f3aaf 10869 if (ret)
4fa62c89 10870 return ret;
8c9f3aaf
JB		 10871
10872 if (intel_crtc->plane)
10873 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10874 else
10875 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10876 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10877 intel_ring_emit(ring, MI_NOOP);
10878 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10879 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10880 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10881 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10882 intel_ring_emit(ring, MI_NOOP);
10883
e7d841ca 10884 intel_mark_page_flip_active(intel_crtc);
83d4092b 10885 return 0;
8c9f3aaf
JB		 10886}
10887
10888static int intel_gen4_queue_flip(struct drm_device *dev,
10889 struct drm_crtc *crtc,
10890 struct drm_framebuffer *fb,
ed8d1975 10891 struct drm_i915_gem_object *obj,
6258fbe2 10892 struct drm_i915_gem_request *req,
ed8d1975 10893 uint32_t flags)
8c9f3aaf 10894{
6258fbe2 10895 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10896 struct drm_i915_private *dev_priv = dev->dev_private;
10897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10898 uint32_t pf, pipesrc;
10899 int ret;
10900
5fb9de1a 10901 ret = intel_ring_begin(req, 4);
8c9f3aaf 10902 if (ret)
4fa62c89 10903 return ret;
8c9f3aaf
JB		 10904
10905 /* i965+ uses the linear or tiled offsets from the
10906 * Display Registers (which do not change across a page-flip)
10907 * so we need only reprogram the base address.
10908 */
6d90c952
DV		 10909 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10910 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10911 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10912 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10913 obj->tiling_mode);
8c9f3aaf
JB		 10914
10915 /* XXX Enabling the panel-fitter across page-flip is so far
10916 * untested on non-native modes, so ignore it for now.
10917 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10918 */
10919 pf = 0;
10920 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10921 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10922
10923 intel_mark_page_flip_active(intel_crtc);
83d4092b 10924 return 0;
8c9f3aaf
JB		 10925}
10926
10927static int intel_gen6_queue_flip(struct drm_device *dev,
10928 struct drm_crtc *crtc,
10929 struct drm_framebuffer *fb,
ed8d1975 10930 struct drm_i915_gem_object *obj,
6258fbe2 10931 struct drm_i915_gem_request *req,
ed8d1975 10932 uint32_t flags)
8c9f3aaf 10933{
6258fbe2 10934 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10935 struct drm_i915_private *dev_priv = dev->dev_private;
10936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10937 uint32_t pf, pipesrc;
10938 int ret;
10939
5fb9de1a 10940 ret = intel_ring_begin(req, 4);
8c9f3aaf 10941 if (ret)
4fa62c89 10942 return ret;
8c9f3aaf 10943
6d90c952
DV		 10944 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10945 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10946 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10947 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10948
dc257cf1
DV		 10949 /* Contrary to the suggestions in the documentation,
10950 * "Enable Panel Fitter" does not seem to be required when page
10951 * flipping with a non-native mode, and worse causes a normal
10952 * modeset to fail.
10953 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10954 */
10955 pf = 0;
8c9f3aaf 10956 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10957 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10958
10959 intel_mark_page_flip_active(intel_crtc);
83d4092b 10960 return 0;
8c9f3aaf
JB		 10961}
10962
7c9017e5
JB		 10963static int intel_gen7_queue_flip(struct drm_device *dev,
10964 struct drm_crtc *crtc,
10965 struct drm_framebuffer *fb,
ed8d1975 10966 struct drm_i915_gem_object *obj,
6258fbe2 10967 struct drm_i915_gem_request *req,
ed8d1975 10968 uint32_t flags)
7c9017e5 10969{
6258fbe2 10970 struct intel_engine_cs *ring = req->ring;
7c9017e5 10971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10972 uint32_t plane_bit = 0;
ffe74d75
CW		 10973 int len, ret;
10974
eba905b2 10975 switch (intel_crtc->plane) {
cb05d8de
DV		 10976 case PLANE_A:
10977 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10978 break;
10979 case PLANE_B:
10980 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10981 break;
10982 case PLANE_C:
10983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10984 break;
10985 default:
10986 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10987 return -ENODEV;
cb05d8de
DV		 10988 }
10989
ffe74d75 10990 len = 4;
f476828a 10991 if (ring->id == RCS) {
ffe74d75 10992 len += 6;
f476828a
DL		 10993 /*
10994 * On Gen 8, SRM is now taking an extra dword to accommodate
10995 * 48bits addresses, and we need a NOOP for the batch size to
10996 * stay even.
10997 */
10998 if (IS_GEN8(dev))
10999 len += 2;
11000 }
ffe74d75 11001
f66fab8e
VS		 11002 /*
11003 * BSpec MI_DISPLAY_FLIP for IVB:
11004 * "The full packet must be contained within the same cache line."
11005 *
11006 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11007 * cacheline, if we ever start emitting more commands before
11008 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11009 * then do the cacheline alignment, and finally emit the
11010 * MI_DISPLAY_FLIP.
11011 */
bba09b12 11012 ret = intel_ring_cacheline_align(req);
f66fab8e 11013 if (ret)
4fa62c89 11014 return ret;
f66fab8e 11015
5fb9de1a 11016 ret = intel_ring_begin(req, len);
7c9017e5 11017 if (ret)
4fa62c89 11018 return ret;
7c9017e5 11019
ffe74d75
CW		 11020 /* Unmask the flip-done completion message. Note that the bspec says that
11021 * we should do this for both the BCS and RCS, and that we must not unmask
11022 * more than one flip event at any time (or ensure that one flip message
11023 * can be sent by waiting for flip-done prior to queueing new flips).
11024 * Experimentation says that BCS works despite DERRMR masking all
11025 * flip-done completion events and that unmasking all planes at once
11026 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11027 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11028 */
11029 if (ring->id == RCS) {
11030 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11031 intel_ring_emit(ring, DERRMR);
11032 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11033 DERRMR_PIPEB_PRI_FLIP_DONE |
11034 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11035 if (IS_GEN8(dev))
11036 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11037 MI_SRM_LRM_GLOBAL_GTT);
11038 else
11039 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11040 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11041 intel_ring_emit(ring, DERRMR);
11042 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11043 if (IS_GEN8(dev)) {
11044 intel_ring_emit(ring, 0);
11045 intel_ring_emit(ring, MI_NOOP);
11046 }
ffe74d75
CW		 11047 }
11048
cb05d8de 11049 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11050 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11051 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11052 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11053
11054 intel_mark_page_flip_active(intel_crtc);
83d4092b 11055 return 0;
7c9017e5
JB		 11056}
11057
84c33a64
SG		 11058static bool use_mmio_flip(struct intel_engine_cs *ring,
11059 struct drm_i915_gem_object *obj)
11060{
11061 /*
11062 * This is not being used for older platforms, because
11063 * non-availability of flip done interrupt forces us to use
11064 * CS flips. Older platforms derive flip done using some clever
11065 * tricks involving the flip_pending status bits and vblank irqs.
11066 * So using MMIO flips there would disrupt this mechanism.
11067 */
11068
8e09bf83
CW		 11069 if (ring == NULL)
11070 return true;
11071
84c33a64
SG		 11072 if (INTEL_INFO(ring->dev)->gen < 5)
11073 return false;
11074
11075 if (i915.use_mmio_flip < 0)
11076 return false;
11077 else if (i915.use_mmio_flip > 0)
11078 return true;
14bf993e
OM		 11079 else if (i915.enable_execlists)
11080 return true;
84c33a64 11081 else
b4716185 11082 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11083}
11084
ff944564
DL		 11085static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11086{
11087 struct drm_device *dev = intel_crtc->base.dev;
11088 struct drm_i915_private *dev_priv = dev->dev_private;
11089 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11090 const enum pipe pipe = intel_crtc->pipe;
11091 u32 ctl, stride;
11092
11093 ctl = I915_READ(PLANE_CTL(pipe, 0));
11094 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11095 switch (fb->modifier[0]) {
11096 case DRM_FORMAT_MOD_NONE:
11097 break;
11098 case I915_FORMAT_MOD_X_TILED:
ff944564 11099 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11100 break;
11101 case I915_FORMAT_MOD_Y_TILED:
11102 ctl |= PLANE_CTL_TILED_Y;
11103 break;
11104 case I915_FORMAT_MOD_Yf_TILED:
11105 ctl |= PLANE_CTL_TILED_YF;
11106 break;
11107 default:
11108 MISSING_CASE(fb->modifier[0]);
11109 }
ff944564
DL		 11110
11111 /*
11112 * The stride is either expressed as a multiple of 64 bytes chunks for
11113 * linear buffers or in number of tiles for tiled buffers.
11114 */
2ebef630
TU		 11115 stride = fb->pitches[0] /
11116 intel_fb_stride_alignment(dev, fb->modifier[0],
11117 fb->pixel_format);
ff944564
DL		 11118
11119 /*
11120 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11121 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11122 */
11123 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11125
11126 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11127 POSTING_READ(PLANE_SURF(pipe, 0));
11128}
11129
11130static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11131{
11132 struct drm_device *dev = intel_crtc->base.dev;
11133 struct drm_i915_private *dev_priv = dev->dev_private;
11134 struct intel_framebuffer *intel_fb =
11135 to_intel_framebuffer(intel_crtc->base.primary->fb);
11136 struct drm_i915_gem_object *obj = intel_fb->obj;
11137 u32 dspcntr;
11138 u32 reg;
11139
84c33a64
SG		 11140 reg = DSPCNTR(intel_crtc->plane);
11141 dspcntr = I915_READ(reg);
11142
c5d97472
DL		 11143 if (obj->tiling_mode != I915_TILING_NONE)
11144 dspcntr |= DISPPLANE_TILED;
11145 else
11146 dspcntr &= ~DISPPLANE_TILED;
11147
84c33a64
SG		 11148 I915_WRITE(reg, dspcntr);
11149
11150 I915_WRITE(DSPSURF(intel_crtc->plane),
11151 intel_crtc->unpin_work->gtt_offset);
11152 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11153
ff944564
DL		 11154}
11155
11156/*
11157 * XXX: This is the temporary way to update the plane registers until we get
11158 * around to using the usual plane update functions for MMIO flips
11159 */
11160static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11161{
11162 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11163 u32 start_vbl_count;
11164
11165 intel_mark_page_flip_active(intel_crtc);
11166
8f539a83 11167 intel_pipe_update_start(intel_crtc, &start_vbl_count);
ff944564
DL		 11168
11169 if (INTEL_INFO(dev)->gen >= 9)
11170 skl_do_mmio_flip(intel_crtc);
11171 else
11172 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11173 ilk_do_mmio_flip(intel_crtc);
11174
8f539a83 11175 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11176}
11177
9362c7c5 11178static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11179{
b2cfe0ab
CW		 11180 struct intel_mmio_flip *mmio_flip =
11181 container_of(work, struct intel_mmio_flip, work);
84c33a64 11182
eed29a5b
DV		 11183 if (mmio_flip->req)
11184 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11185 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11186 false, NULL,
11187 &mmio_flip->i915->rps.mmioflips));
84c33a64 11188
b2cfe0ab
CW		 11189 intel_do_mmio_flip(mmio_flip->crtc);
11190
eed29a5b 11191 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11192 kfree(mmio_flip);
84c33a64
SG		 11193}
11194
11195static int intel_queue_mmio_flip(struct drm_device *dev,
11196 struct drm_crtc *crtc,
11197 struct drm_framebuffer *fb,
11198 struct drm_i915_gem_object *obj,
11199 struct intel_engine_cs *ring,
11200 uint32_t flags)
11201{
b2cfe0ab
CW		 11202 struct intel_mmio_flip *mmio_flip;
11203
11204 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11205 if (mmio_flip == NULL)
11206 return -ENOMEM;
84c33a64 11207
bcafc4e3 11208 mmio_flip->i915 = to_i915(dev);
eed29a5b 11209 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11210 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11211
b2cfe0ab
CW		 11212 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11213 schedule_work(&mmio_flip->work);
84c33a64 11214
84c33a64
SG		 11215 return 0;
11216}
11217
8c9f3aaf
JB		 11218static int intel_default_queue_flip(struct drm_device *dev,
11219 struct drm_crtc *crtc,
11220 struct drm_framebuffer *fb,
ed8d1975 11221 struct drm_i915_gem_object *obj,
6258fbe2 11222 struct drm_i915_gem_request *req,
ed8d1975 11223 uint32_t flags)
8c9f3aaf
JB		 11224{
11225 return -ENODEV;
11226}
11227
d6bbafa1
CW		 11228static bool __intel_pageflip_stall_check(struct drm_device *dev,
11229 struct drm_crtc *crtc)
11230{
11231 struct drm_i915_private *dev_priv = dev->dev_private;
11232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11233 struct intel_unpin_work *work = intel_crtc->unpin_work;
11234 u32 addr;
11235
11236 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11237 return true;
11238
908565c2
CW		 11239 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11240 return false;
11241
d6bbafa1
CW		 11242 if (!work->enable_stall_check)
11243 return false;
11244
11245 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11246 if (work->flip_queued_req &&
11247 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11248 return false;
11249
1e3feefd 11250 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11251 }
11252
1e3feefd 11253 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11254 return false;
11255
11256 /* Potential stall - if we see that the flip has happened,
11257 * assume a missed interrupt. */
11258 if (INTEL_INFO(dev)->gen >= 4)
11259 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11260 else
11261 addr = I915_READ(DSPADDR(intel_crtc->plane));
11262
11263 /* There is a potential issue here with a false positive after a flip
11264 * to the same address. We could address this by checking for a
11265 * non-incrementing frame counter.
11266 */
11267 return addr == work->gtt_offset;
11268}
11269
11270void intel_check_page_flip(struct drm_device *dev, int pipe)
11271{
11272 struct drm_i915_private *dev_priv = dev->dev_private;
11273 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11275 struct intel_unpin_work *work;
f326038a 11276
6c51d46f 11277 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11278
11279 if (crtc == NULL)
11280 return;
11281
f326038a 11282 spin_lock(&dev->event_lock);
6ad790c0
CW		 11283 work = intel_crtc->unpin_work;
11284 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11285 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11286 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11287 page_flip_completed(intel_crtc);
6ad790c0 11288 work = NULL;
d6bbafa1 11289 }
6ad790c0
CW		 11290 if (work != NULL &&
11291 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11292 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11293 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11294}
11295
6b95a207
KH		 11296static int intel_crtc_page_flip(struct drm_crtc *crtc,
11297 struct drm_framebuffer *fb,
ed8d1975
KP		 11298 struct drm_pending_vblank_event *event,
11299 uint32_t page_flip_flags)
6b95a207
KH		 11300{
11301 struct drm_device *dev = crtc->dev;
11302 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11303 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11304 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11306 struct drm_plane *primary = crtc->primary;
a071fa00 11307 enum pipe pipe = intel_crtc->pipe;
6b95a207 11308 struct intel_unpin_work *work;
a4872ba6 11309 struct intel_engine_cs *ring;
cf5d8a46 11310 bool mmio_flip;
91af127f 11311 struct drm_i915_gem_request *request = NULL;
52e68630 11312 int ret;
6b95a207 11313
2ff8fde1
MR		 11314 /*
11315 * drm_mode_page_flip_ioctl() should already catch this, but double
11316 * check to be safe. In the future we may enable pageflipping from
11317 * a disabled primary plane.
11318 */
11319 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11320 return -EBUSY;
11321
e6a595d2 11322 /* Can't change pixel format via MI display flips. */
f4510a27 11323 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11324 return -EINVAL;
11325
11326 /*
11327 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11328 * Note that pitch changes could also affect these register.
11329 */
11330 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11331 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11332 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11333 return -EINVAL;
11334
f900db47
CW		 11335 if (i915_terminally_wedged(&dev_priv->gpu_error))
11336 goto out_hang;
11337
b14c5679 11338 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11339 if (work == NULL)
11340 return -ENOMEM;
11341
6b95a207 11342 work->event = event;
b4a98e57 11343 work->crtc = crtc;
ab8d6675 11344 work->old_fb = old_fb;
6b95a207
KH		 11345 INIT_WORK(&work->work, intel_unpin_work_fn);
11346
87b6b101 11347 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11348 if (ret)
11349 goto free_work;
11350
6b95a207 11351 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11352 spin_lock_irq(&dev->event_lock);
6b95a207 11353 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11354 /* Before declaring the flip queue wedged, check if
11355 * the hardware completed the operation behind our backs.
11356 */
11357 if (__intel_pageflip_stall_check(dev, crtc)) {
11358 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11359 page_flip_completed(intel_crtc);
11360 } else {
11361 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11362 spin_unlock_irq(&dev->event_lock);
468f0b44 11363
d6bbafa1
CW		 11364 drm_crtc_vblank_put(crtc);
11365 kfree(work);
11366 return -EBUSY;
11367 }
6b95a207
KH		 11368 }
11369 intel_crtc->unpin_work = work;
5e2d7afc 11370 spin_unlock_irq(&dev->event_lock);
6b95a207 11371
b4a98e57
CW		 11372 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11373 flush_workqueue(dev_priv->wq);
11374
75dfca80 11375 /* Reference the objects for the scheduled work. */
ab8d6675 11376 drm_framebuffer_reference(work->old_fb);
05394f39 11377 drm_gem_object_reference(&obj->base);
6b95a207 11378
f4510a27 11379 crtc->primary->fb = fb;
afd65eb4 11380 update_state_fb(crtc->primary);
1ed1f968 11381
e1f99ce6 11382 work->pending_flip_obj = obj;
e1f99ce6 11383
89ed88ba
CW		 11384 ret = i915_mutex_lock_interruptible(dev);
11385 if (ret)
11386 goto cleanup;
11387
b4a98e57 11388 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11389 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11390
75f7f3ec 11391 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11392 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11393
4fa62c89
VS		 11394 if (IS_VALLEYVIEW(dev)) {
11395 ring = &dev_priv->ring[BCS];
ab8d6675 11396 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11397 /* vlv: DISPLAY_FLIP fails to change tiling */
11398 ring = NULL;
48bf5b2d 11399 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11400 ring = &dev_priv->ring[BCS];
4fa62c89 11401 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11402 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11403 if (ring == NULL || ring->id != RCS)
11404 ring = &dev_priv->ring[BCS];
11405 } else {
11406 ring = &dev_priv->ring[RCS];
11407 }
11408
cf5d8a46
CW		 11409 mmio_flip = use_mmio_flip(ring, obj);
11410
11411 /* When using CS flips, we want to emit semaphores between rings.
11412 * However, when using mmio flips we will create a task to do the
11413 * synchronisation, so all we want here is to pin the framebuffer
11414 * into the display plane and skip any waits.
11415 */
82bc3b2d 11416 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11417 crtc->primary->state,
91af127f 11418 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11419 if (ret)
11420 goto cleanup_pending;
6b95a207 11421
121920fa
TU		 11422 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11423 + intel_crtc->dspaddr_offset;
4fa62c89 11424
cf5d8a46 11425 if (mmio_flip) {
84c33a64
SG		 11426 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11427 page_flip_flags);
d6bbafa1
CW		 11428 if (ret)
11429 goto cleanup_unpin;
11430
f06cc1b9
JH		 11431 i915_gem_request_assign(&work->flip_queued_req,
11432 obj->last_write_req);
d6bbafa1 11433 } else {
6258fbe2
JH		 11434 if (!request) {
11435 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11436 if (ret)
11437 goto cleanup_unpin;
11438 }
11439
11440 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11441 page_flip_flags);
11442 if (ret)
11443 goto cleanup_unpin;
11444
6258fbe2 11445 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11446 }
11447
91af127f 11448 if (request)
75289874 11449 i915_add_request_no_flush(request);
91af127f 11450
1e3feefd 11451 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11452 work->enable_stall_check = true;
4fa62c89 11453
ab8d6675 11454 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11455 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11456 mutex_unlock(&dev->struct_mutex);
a071fa00 11457
4e1e26f1 11458 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11459 intel_frontbuffer_flip_prepare(dev,
11460 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11461
e5510fac
JB		 11462 trace_i915_flip_request(intel_crtc->plane, obj);
11463
6b95a207 11464 return 0;
96b099fd 11465
4fa62c89 11466cleanup_unpin:
82bc3b2d 11467 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11468cleanup_pending:
91af127f
JH		 11469 if (request)
11470 i915_gem_request_cancel(request);
b4a98e57 11471 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11472 mutex_unlock(&dev->struct_mutex);
11473cleanup:
f4510a27 11474 crtc->primary->fb = old_fb;
afd65eb4 11475 update_state_fb(crtc->primary);
89ed88ba
CW		 11476
11477 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11478 drm_framebuffer_unreference(work->old_fb);
96b099fd 11479
5e2d7afc 11480 spin_lock_irq(&dev->event_lock);
96b099fd 11481 intel_crtc->unpin_work = NULL;
5e2d7afc 11482 spin_unlock_irq(&dev->event_lock);
96b099fd 11483
87b6b101 11484 drm_crtc_vblank_put(crtc);
7317c75e 11485free_work:
96b099fd
CW		 11486 kfree(work);
11487
f900db47 11488 if (ret == -EIO) {
02e0efb5
ML		 11489 struct drm_atomic_state *state;
11490 struct drm_plane_state *plane_state;
11491
f900db47 11492out_hang:
02e0efb5
ML		 11493 state = drm_atomic_state_alloc(dev);
11494 if (!state)
11495 return -ENOMEM;
11496 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11497
11498retry:
11499 plane_state = drm_atomic_get_plane_state(state, primary);
11500 ret = PTR_ERR_OR_ZERO(plane_state);
11501 if (!ret) {
11502 drm_atomic_set_fb_for_plane(plane_state, fb);
11503
11504 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11505 if (!ret)
11506 ret = drm_atomic_commit(state);
11507 }
11508
11509 if (ret == -EDEADLK) {
11510 drm_modeset_backoff(state->acquire_ctx);
11511 drm_atomic_state_clear(state);
11512 goto retry;
11513 }
11514
11515 if (ret)
11516 drm_atomic_state_free(state);
11517
f0d3dad3 11518 if (ret == 0 && event) {
5e2d7afc 11519 spin_lock_irq(&dev->event_lock);
a071fa00 11520 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11521 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11522 }
f900db47 11523 }
96b099fd 11524 return ret;
6b95a207
KH		 11525}
11526
da20eabd
ML		 11527
11528/**
11529 * intel_wm_need_update - Check whether watermarks need updating
11530 * @plane: drm plane
11531 * @state: new plane state
11532 *
11533 * Check current plane state versus the new one to determine whether
11534 * watermarks need to be recalculated.
11535 *
11536 * Returns true or false.
11537 */
11538static bool intel_wm_need_update(struct drm_plane *plane,
11539 struct drm_plane_state *state)
11540{
11541 /* Update watermarks on tiling changes. */
11542 if (!plane->state->fb || !state->fb ||
11543 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11544 plane->state->rotation != state->rotation)
11545 return true;
11546
11547 if (plane->state->crtc_w != state->crtc_w)
11548 return true;
11549
11550 return false;
11551}
11552
11553int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11554 struct drm_plane_state *plane_state)
11555{
11556 struct drm_crtc *crtc = crtc_state->crtc;
11557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11558 struct drm_plane *plane = plane_state->plane;
11559 struct drm_device *dev = crtc->dev;
11560 struct drm_i915_private *dev_priv = dev->dev_private;
11561 struct intel_plane_state *old_plane_state =
11562 to_intel_plane_state(plane->state);
11563 int idx = intel_crtc->base.base.id, ret;
11564 int i = drm_plane_index(plane);
11565 bool mode_changed = needs_modeset(crtc_state);
11566 bool was_crtc_enabled = crtc->state->active;
11567 bool is_crtc_enabled = crtc_state->active;
11568
11569 bool turn_off, turn_on, visible, was_visible;
11570 struct drm_framebuffer *fb = plane_state->fb;
11571
11572 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11573 plane->type != DRM_PLANE_TYPE_CURSOR) {
11574 ret = skl_update_scaler_plane(
11575 to_intel_crtc_state(crtc_state),
11576 to_intel_plane_state(plane_state));
11577 if (ret)
11578 return ret;
11579 }
11580
11581 /*
11582 * Disabling a plane is always okay; we just need to update
11583 * fb tracking in a special way since cleanup_fb() won't
11584 * get called by the plane helpers.
11585 */
11586 if (old_plane_state->base.fb && !fb)
11587 intel_crtc->atomic.disabled_planes |= 1 << i;
11588
da20eabd
ML		 11589 was_visible = old_plane_state->visible;
11590 visible = to_intel_plane_state(plane_state)->visible;
11591
11592 if (!was_crtc_enabled && WARN_ON(was_visible))
11593 was_visible = false;
11594
11595 if (!is_crtc_enabled && WARN_ON(visible))
11596 visible = false;
11597
11598 if (!was_visible && !visible)
11599 return 0;
11600
11601 turn_off = was_visible && (!visible || mode_changed);
11602 turn_on = visible && (!was_visible || mode_changed);
11603
11604 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11605 plane->base.id, fb ? fb->base.id : -1);
11606
11607 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11608 plane->base.id, was_visible, visible,
11609 turn_off, turn_on, mode_changed);
11610
852eb00d 11611 if (turn_on) {
f015c551 11612 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11613 /* must disable cxsr around plane enable/disable */
11614 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11615 intel_crtc->atomic.disable_cxsr = true;
11616 /* to potentially re-enable cxsr */
11617 intel_crtc->atomic.wait_vblank = true;
11618 intel_crtc->atomic.update_wm_post = true;
11619 }
11620 } else if (turn_off) {
f015c551 11621 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11622 /* must disable cxsr around plane enable/disable */
11623 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11624 if (is_crtc_enabled)
11625 intel_crtc->atomic.wait_vblank = true;
11626 intel_crtc->atomic.disable_cxsr = true;
11627 }
11628 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11629 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11630 }
da20eabd 11631
a9ff8714
VS		 11632 if (visible)
11633 intel_crtc->atomic.fb_bits |=
11634 to_intel_plane(plane)->frontbuffer_bit;
11635
da20eabd
ML		 11636 switch (plane->type) {
11637 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11638 intel_crtc->atomic.wait_for_flips = true;
11639 intel_crtc->atomic.pre_disable_primary = turn_off;
11640 intel_crtc->atomic.post_enable_primary = turn_on;
11641
066cf55b
RV		 11642 if (turn_off) {
11643 /*
11644 * FIXME: Actually if we will still have any other
11645 * plane enabled on the pipe we could let IPS enabled
11646 * still, but for now lets consider that when we make
11647 * primary invisible by setting DSPCNTR to 0 on
11648 * update_primary_plane function IPS needs to be
11649 * disable.
11650 */
11651 intel_crtc->atomic.disable_ips = true;
11652
da20eabd 11653 intel_crtc->atomic.disable_fbc = true;
066cf55b 11654 }
da20eabd
ML		 11655
11656 /*
11657 * FBC does not work on some platforms for rotated
11658 * planes, so disable it when rotation is not 0 and
11659 * update it when rotation is set back to 0.
11660 *
11661 * FIXME: This is redundant with the fbc update done in
11662 * the primary plane enable function except that that
11663 * one is done too late. We eventually need to unify
11664 * this.
11665 */
11666
11667 if (visible &&
11668 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11669 dev_priv->fbc.crtc == intel_crtc &&
11670 plane_state->rotation != BIT(DRM_ROTATE_0))
11671 intel_crtc->atomic.disable_fbc = true;
11672
11673 /*
11674 * BDW signals flip done immediately if the plane
11675 * is disabled, even if the plane enable is already
11676 * armed to occur at the next vblank :(
11677 */
11678 if (turn_on && IS_BROADWELL(dev))
11679 intel_crtc->atomic.wait_vblank = true;
11680
11681 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11682 break;
11683 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11684 break;
11685 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11686 if (turn_off && !mode_changed) {
da20eabd
ML		 11687 intel_crtc->atomic.wait_vblank = true;
11688 intel_crtc->atomic.update_sprite_watermarks |=
11689 1 << i;
11690 }
da20eabd
ML		 11691 }
11692 return 0;
11693}
11694
6d3a1ce7
ML		 11695static bool encoders_cloneable(const struct intel_encoder *a,
11696 const struct intel_encoder *b)
11697{
11698 /* masks could be asymmetric, so check both ways */
11699 return a == b || (a->cloneable & (1 << b->type) &&
11700 b->cloneable & (1 << a->type));
11701}
11702
11703static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11704 struct intel_crtc *crtc,
11705 struct intel_encoder *encoder)
11706{
11707 struct intel_encoder *source_encoder;
11708 struct drm_connector *connector;
11709 struct drm_connector_state *connector_state;
11710 int i;
11711
11712 for_each_connector_in_state(state, connector, connector_state, i) {
11713 if (connector_state->crtc != &crtc->base)
11714 continue;
11715
11716 source_encoder =
11717 to_intel_encoder(connector_state->best_encoder);
11718 if (!encoders_cloneable(encoder, source_encoder))
11719 return false;
11720 }
11721
11722 return true;
11723}
11724
11725static bool check_encoder_cloning(struct drm_atomic_state *state,
11726 struct intel_crtc *crtc)
11727{
11728 struct intel_encoder *encoder;
11729 struct drm_connector *connector;
11730 struct drm_connector_state *connector_state;
11731 int i;
11732
11733 for_each_connector_in_state(state, connector, connector_state, i) {
11734 if (connector_state->crtc != &crtc->base)
11735 continue;
11736
11737 encoder = to_intel_encoder(connector_state->best_encoder);
11738 if (!check_single_encoder_cloning(state, crtc, encoder))
11739 return false;
11740 }
11741
11742 return true;
11743}
11744
11745static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11746 struct drm_crtc_state *crtc_state)
11747{
cf5a15be 11748 struct drm_device *dev = crtc->dev;
ad421372 11749 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11751 struct intel_crtc_state *pipe_config =
11752 to_intel_crtc_state(crtc_state);
6d3a1ce7 11753 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11754 int ret;
6d3a1ce7
ML		 11755 bool mode_changed = needs_modeset(crtc_state);
11756
11757 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11758 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11759 return -EINVAL;
11760 }
11761
852eb00d
VS		 11762 if (mode_changed && !crtc_state->active)
11763 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11764
ad421372
ML		 11765 if (mode_changed && crtc_state->enable &&
11766 dev_priv->display.crtc_compute_clock &&
11767 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11768 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11769 pipe_config);
11770 if (ret)
11771 return ret;
11772 }
11773
e435d6e5
ML		 11774 ret = 0;
11775 if (INTEL_INFO(dev)->gen >= 9) {
11776 if (mode_changed)
11777 ret = skl_update_scaler_crtc(pipe_config);
11778
11779 if (!ret)
11780 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11781 pipe_config);
11782 }
11783
11784 return ret;
6d3a1ce7
ML		 11785}
11786
65b38e0d 11787static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11788 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11789 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11790 .atomic_begin = intel_begin_crtc_commit,
11791 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11792 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11793};
11794
d29b2f9d
ACO		 11795static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11796{
11797 struct intel_connector *connector;
11798
11799 for_each_intel_connector(dev, connector) {
11800 if (connector->base.encoder) {
11801 connector->base.state->best_encoder =
11802 connector->base.encoder;
11803 connector->base.state->crtc =
11804 connector->base.encoder->crtc;
11805 } else {
11806 connector->base.state->best_encoder = NULL;
11807 connector->base.state->crtc = NULL;
11808 }
11809 }
11810}
11811
050f7aeb 11812static void
eba905b2 11813connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11814 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11815{
11816 int bpp = pipe_config->pipe_bpp;
11817
11818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11819 connector->base.base.id,
c23cc417 11820 connector->base.name);
050f7aeb
DV		 11821
11822 /* Don't use an invalid EDID bpc value */
11823 if (connector->base.display_info.bpc &&
11824 connector->base.display_info.bpc * 3 < bpp) {
11825 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11826 bpp, connector->base.display_info.bpc*3);
11827 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11828 }
11829
11830 /* Clamp bpp to 8 on screens without EDID 1.4 */
11831 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11832 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11833 bpp);
11834 pipe_config->pipe_bpp = 24;
11835 }
11836}
11837
4e53c2e0 11838static int
050f7aeb 11839compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11840 struct intel_crtc_state *pipe_config)
4e53c2e0 11841{
050f7aeb 11842 struct drm_device *dev = crtc->base.dev;
1486017f 11843 struct drm_atomic_state *state;
da3ced29
ACO		 11844 struct drm_connector *connector;
11845 struct drm_connector_state *connector_state;
1486017f 11846 int bpp, i;
4e53c2e0 11847
d328c9d7 11848 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11849 bpp = 10*3;
d328c9d7
DV		 11850 else if (INTEL_INFO(dev)->gen >= 5)
11851 bpp = 12*3;
11852 else
11853 bpp = 8*3;
11854
4e53c2e0 11855
4e53c2e0
DV		 11856 pipe_config->pipe_bpp = bpp;
11857
1486017f
ACO		 11858 state = pipe_config->base.state;
11859
4e53c2e0 11860 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11861 for_each_connector_in_state(state, connector, connector_state, i) {
11862 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11863 continue;
11864
da3ced29
ACO		 11865 connected_sink_compute_bpp(to_intel_connector(connector),
11866 pipe_config);
4e53c2e0
DV		 11867 }
11868
11869 return bpp;
11870}
11871
644db711
DV		 11872static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11873{
11874 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11875 "type: 0x%x flags: 0x%x\n",
1342830c 11876 mode->crtc_clock,
644db711
DV		 11877 mode->crtc_hdisplay, mode->crtc_hsync_start,
11878 mode->crtc_hsync_end, mode->crtc_htotal,
11879 mode->crtc_vdisplay, mode->crtc_vsync_start,
11880 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11881}
11882
c0b03411 11883static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11884 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11885 const char *context)
11886{
6a60cd87
CK		 11887 struct drm_device *dev = crtc->base.dev;
11888 struct drm_plane *plane;
11889 struct intel_plane *intel_plane;
11890 struct intel_plane_state *state;
11891 struct drm_framebuffer *fb;
11892
11893 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11894 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11895
11896 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11897 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11898 pipe_config->pipe_bpp, pipe_config->dither);
11899 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11900 pipe_config->has_pch_encoder,
11901 pipe_config->fdi_lanes,
11902 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11903 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11904 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11905 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11906 pipe_config->has_dp_encoder,
11907 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11908 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11909 pipe_config->dp_m_n.tu);
b95af8be
VK		 11910
11911 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11912 pipe_config->has_dp_encoder,
11913 pipe_config->dp_m2_n2.gmch_m,
11914 pipe_config->dp_m2_n2.gmch_n,
11915 pipe_config->dp_m2_n2.link_m,
11916 pipe_config->dp_m2_n2.link_n,
11917 pipe_config->dp_m2_n2.tu);
11918
55072d19
DV		 11919 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11920 pipe_config->has_audio,
11921 pipe_config->has_infoframe);
11922
c0b03411 11923 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11924 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11925 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11926 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11927 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11928 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11929 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11930 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11931 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11932 crtc->num_scalers,
11933 pipe_config->scaler_state.scaler_users,
11934 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11935 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11936 pipe_config->gmch_pfit.control,
11937 pipe_config->gmch_pfit.pgm_ratios,
11938 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11939 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11940 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11941 pipe_config->pch_pfit.size,
11942 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11943 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11944 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11945
415ff0f6 11946 if (IS_BROXTON(dev)) {
05712c15 11947 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11948 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11949 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ebb0,
05712c15 11952 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11953 pipe_config->dpll_hw_state.pll0,
11954 pipe_config->dpll_hw_state.pll1,
11955 pipe_config->dpll_hw_state.pll2,
11956 pipe_config->dpll_hw_state.pll3,
11957 pipe_config->dpll_hw_state.pll6,
11958 pipe_config->dpll_hw_state.pll8,
05712c15 11959 pipe_config->dpll_hw_state.pll9,
c8453338 11960 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11961 pipe_config->dpll_hw_state.pcsdw12);
11962 } else if (IS_SKYLAKE(dev)) {
11963 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11964 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11965 pipe_config->ddi_pll_sel,
11966 pipe_config->dpll_hw_state.ctrl1,
11967 pipe_config->dpll_hw_state.cfgcr1,
11968 pipe_config->dpll_hw_state.cfgcr2);
11969 } else if (HAS_DDI(dev)) {
11970 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11971 pipe_config->ddi_pll_sel,
11972 pipe_config->dpll_hw_state.wrpll);
11973 } else {
11974 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11975 "fp0: 0x%x, fp1: 0x%x\n",
11976 pipe_config->dpll_hw_state.dpll,
11977 pipe_config->dpll_hw_state.dpll_md,
11978 pipe_config->dpll_hw_state.fp0,
11979 pipe_config->dpll_hw_state.fp1);
11980 }
11981
6a60cd87
CK		 11982 DRM_DEBUG_KMS("planes on this crtc\n");
11983 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11984 intel_plane = to_intel_plane(plane);
11985 if (intel_plane->pipe != crtc->pipe)
11986 continue;
11987
11988 state = to_intel_plane_state(plane->state);
11989 fb = state->base.fb;
11990 if (!fb) {
11991 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11992 "disabled, scaler_id = %d\n",
11993 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11994 plane->base.id, intel_plane->pipe,
11995 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11996 drm_plane_index(plane), state->scaler_id);
11997 continue;
11998 }
11999
12000 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12001 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12002 plane->base.id, intel_plane->pipe,
12003 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12004 drm_plane_index(plane));
12005 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12006 fb->base.id, fb->width, fb->height, fb->pixel_format);
12007 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12008 state->scaler_id,
12009 state->src.x1 >> 16, state->src.y1 >> 16,
12010 drm_rect_width(&state->src) >> 16,
12011 drm_rect_height(&state->src) >> 16,
12012 state->dst.x1, state->dst.y1,
12013 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12014 }
c0b03411
DV		 12015}
12016
5448a00d 12017static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12018{
5448a00d
ACO		 12019 struct drm_device *dev = state->dev;
12020 struct intel_encoder *encoder;
da3ced29 12021 struct drm_connector *connector;
5448a00d 12022 struct drm_connector_state *connector_state;
00f0b378 12023 unsigned int used_ports = 0;
5448a00d 12024 int i;
00f0b378
VS		 12025
12026 /*
12027 * Walk the connector list instead of the encoder
12028 * list to detect the problem on ddi platforms
12029 * where there's just one encoder per digital port.
12030 */
da3ced29 12031 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12032 if (!connector_state->best_encoder)
00f0b378
VS		 12033 continue;
12034
5448a00d
ACO		 12035 encoder = to_intel_encoder(connector_state->best_encoder);
12036
12037 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12038
12039 switch (encoder->type) {
12040 unsigned int port_mask;
12041 case INTEL_OUTPUT_UNKNOWN:
12042 if (WARN_ON(!HAS_DDI(dev)))
12043 break;
12044 case INTEL_OUTPUT_DISPLAYPORT:
12045 case INTEL_OUTPUT_HDMI:
12046 case INTEL_OUTPUT_EDP:
12047 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12048
12049 /* the same port mustn't appear more than once */
12050 if (used_ports & port_mask)
12051 return false;
12052
12053 used_ports |= port_mask;
12054 default:
12055 break;
12056 }
12057 }
12058
12059 return true;
12060}
12061
83a57153
ACO		 12062static void
12063clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12064{
12065 struct drm_crtc_state tmp_state;
663a3640 12066 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12067 struct intel_dpll_hw_state dpll_hw_state;
12068 enum intel_dpll_id shared_dpll;
8504c74c 12069 uint32_t ddi_pll_sel;
c4e2d043 12070 bool force_thru;
83a57153 12071
7546a384
ACO		 12072 /* FIXME: before the switch to atomic started, a new pipe_config was
12073 * kzalloc'd. Code that depends on any field being zero should be
12074 * fixed, so that the crtc_state can be safely duplicated. For now,
12075 * only fields that are know to not cause problems are preserved. */
12076
83a57153 12077 tmp_state = crtc_state->base;
663a3640 12078 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12079 shared_dpll = crtc_state->shared_dpll;
12080 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12081 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12082 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12083
83a57153 12084 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12085
83a57153 12086 crtc_state->base = tmp_state;
663a3640 12087 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12088 crtc_state->shared_dpll = shared_dpll;
12089 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12090 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12091 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12092}
12093
548ee15b 12094static int
b8cecdf5 12095intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12096 struct intel_crtc_state *pipe_config)
ee7b9f93 12097{
b359283a 12098 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12099 struct intel_encoder *encoder;
da3ced29 12100 struct drm_connector *connector;
0b901879 12101 struct drm_connector_state *connector_state;
d328c9d7 12102 int base_bpp, ret = -EINVAL;
0b901879 12103 int i;
e29c22c0 12104 bool retry = true;
ee7b9f93 12105
83a57153 12106 clear_intel_crtc_state(pipe_config);
7758a113 12107
e143a21c
DV		 12108 pipe_config->cpu_transcoder =
12109 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12110
2960bc9c
ID		 12111 /*
12112 * Sanitize sync polarity flags based on requested ones. If neither
12113 * positive or negative polarity is requested, treat this as meaning
12114 * negative polarity.
12115 */
2d112de7 12116 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12117 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12119
2d112de7 12120 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12121 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12123
050f7aeb
DV		 12124 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12125 * plane pixel format and any sink constraints into account. Returns the
12126 * source plane bpp so that dithering can be selected on mismatches
12127 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12128 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12129 pipe_config);
12130 if (base_bpp < 0)
4e53c2e0
DV		 12131 goto fail;
12132
e41a56be
VS		 12133 /*
12134 * Determine the real pipe dimensions. Note that stereo modes can
12135 * increase the actual pipe size due to the frame doubling and
12136 * insertion of additional space for blanks between the frame. This
12137 * is stored in the crtc timings. We use the requested mode to do this
12138 * computation to clearly distinguish it from the adjusted mode, which
12139 * can be changed by the connectors in the below retry loop.
12140 */
2d112de7 12141 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12142 &pipe_config->pipe_src_w,
12143 &pipe_config->pipe_src_h);
e41a56be 12144
e29c22c0 12145encoder_retry:
ef1b460d 12146 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12147 pipe_config->port_clock = 0;
ef1b460d 12148 pipe_config->pixel_multiplier = 1;
ff9a6750 12149
135c81b8 12150 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12151 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12152 CRTC_STEREO_DOUBLE);
135c81b8 12153
7758a113
DV		 12154 /* Pass our mode to the connectors and the CRTC to give them a chance to
12155 * adjust it according to limitations or connector properties, and also
12156 * a chance to reject the mode entirely.
47f1c6c9 12157 */
da3ced29 12158 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12159 if (connector_state->crtc != crtc)
7758a113 12160 continue;
7ae89233 12161
0b901879
ACO		 12162 encoder = to_intel_encoder(connector_state->best_encoder);
12163
efea6e8e
DV		 12164 if (!(encoder->compute_config(encoder, pipe_config))) {
12165 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12166 goto fail;
12167 }
ee7b9f93 12168 }
47f1c6c9 12169
ff9a6750
DV		 12170 /* Set default port clock if not overwritten by the encoder. Needs to be
12171 * done afterwards in case the encoder adjusts the mode. */
12172 if (!pipe_config->port_clock)
2d112de7 12173 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12174 * pipe_config->pixel_multiplier;
ff9a6750 12175
a43f6e0f 12176 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12177 if (ret < 0) {
7758a113
DV		 12178 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 goto fail;
ee7b9f93 12180 }
e29c22c0
DV		 12181
12182 if (ret == RETRY) {
12183 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12184 ret = -EINVAL;
12185 goto fail;
12186 }
12187
12188 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12189 retry = false;
12190 goto encoder_retry;
12191 }
12192
e8fa4270
DV		 12193 /* Dithering seems to not pass-through bits correctly when it should, so
12194 * only enable it on 6bpc panels. */
12195 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
4e53c2e0 12196 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12197 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12198
7758a113 12199fail:
548ee15b 12200 return ret;
ee7b9f93 12201}
47f1c6c9 12202
ea9d758d 12203static void
4740b0f2 12204intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12205{
0a9ab303
ACO		 12206 struct drm_crtc *crtc;
12207 struct drm_crtc_state *crtc_state;
8a75d157 12208 int i;
ea9d758d 12209
7668851f 12210 /* Double check state. */
8a75d157 12211 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12212 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12213
12214 /* Update hwmode for vblank functions */
12215 if (crtc->state->active)
12216 crtc->hwmode = crtc->state->adjusted_mode;
12217 else
12218 crtc->hwmode.crtc_clock = 0;
ea9d758d 12219 }
ea9d758d
DV		 12220}
12221
3bd26263 12222static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12223{
3bd26263 12224 int diff;
f1f644dc
JB		 12225
12226 if (clock1 == clock2)
12227 return true;
12228
12229 if (!clock1 || !clock2)
12230 return false;
12231
12232 diff = abs(clock1 - clock2);
12233
12234 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12235 return true;
12236
12237 return false;
12238}
12239
25c5b266
DV		 12240#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12241 list_for_each_entry((intel_crtc), \
12242 &(dev)->mode_config.crtc_list, \
12243 base.head) \
0973f18f 12244 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12245
cfb23ed6
ML		 12246
12247static bool
12248intel_compare_m_n(unsigned int m, unsigned int n,
12249 unsigned int m2, unsigned int n2,
12250 bool exact)
12251{
12252 if (m == m2 && n == n2)
12253 return true;
12254
12255 if (exact || !m || !n || !m2 || !n2)
12256 return false;
12257
12258 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12259
12260 if (m > m2) {
12261 while (m > m2) {
12262 m2 <<= 1;
12263 n2 <<= 1;
12264 }
12265 } else if (m < m2) {
12266 while (m < m2) {
12267 m <<= 1;
12268 n <<= 1;
12269 }
12270 }
12271
12272 return m == m2 && n == n2;
12273}
12274
12275static bool
12276intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12277 struct intel_link_m_n *m2_n2,
12278 bool adjust)
12279{
12280 if (m_n->tu == m2_n2->tu &&
12281 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12282 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12283 intel_compare_m_n(m_n->link_m, m_n->link_n,
12284 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12285 if (adjust)
12286 *m2_n2 = *m_n;
12287
12288 return true;
12289 }
12290
12291 return false;
12292}
12293
0e8ffe1b 12294static bool
2fa2fe9a 12295intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12296 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12297 struct intel_crtc_state *pipe_config,
12298 bool adjust)
0e8ffe1b 12299{
cfb23ed6
ML		 12300 bool ret = true;
12301
12302#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12303 do { \
12304 if (!adjust) \
12305 DRM_ERROR(fmt, ##__VA_ARGS__); \
12306 else \
12307 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12308 } while (0)
12309
66e985c0
DV		 12310#define PIPE_CONF_CHECK_X(name) \
12311 if (current_config->name != pipe_config->name) { \
cfb23ed6 12312 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12313 "(expected 0x%08x, found 0x%08x)\n", \
12314 current_config->name, \
12315 pipe_config->name); \
cfb23ed6 12316 ret = false; \
66e985c0
DV		 12317 }
12318
08a24034
DV		 12319#define PIPE_CONF_CHECK_I(name) \
12320 if (current_config->name != pipe_config->name) { \
cfb23ed6 12321 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12322 "(expected %i, found %i)\n", \
12323 current_config->name, \
12324 pipe_config->name); \
cfb23ed6
ML		 12325 ret = false; \
12326 }
12327
12328#define PIPE_CONF_CHECK_M_N(name) \
12329 if (!intel_compare_link_m_n(&current_config->name, \
12330 &pipe_config->name,\
12331 adjust)) { \
12332 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12333 "(expected tu %i gmch %i/%i link %i/%i, " \
12334 "found tu %i, gmch %i/%i link %i/%i)\n", \
12335 current_config->name.tu, \
12336 current_config->name.gmch_m, \
12337 current_config->name.gmch_n, \
12338 current_config->name.link_m, \
12339 current_config->name.link_n, \
12340 pipe_config->name.tu, \
12341 pipe_config->name.gmch_m, \
12342 pipe_config->name.gmch_n, \
12343 pipe_config->name.link_m, \
12344 pipe_config->name.link_n); \
12345 ret = false; \
12346 }
12347
12348#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12349 if (!intel_compare_link_m_n(&current_config->name, \
12350 &pipe_config->name, adjust) && \
12351 !intel_compare_link_m_n(&current_config->alt_name, \
12352 &pipe_config->name, adjust)) { \
12353 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12354 "(expected tu %i gmch %i/%i link %i/%i, " \
12355 "or tu %i gmch %i/%i link %i/%i, " \
12356 "found tu %i, gmch %i/%i link %i/%i)\n", \
12357 current_config->name.tu, \
12358 current_config->name.gmch_m, \
12359 current_config->name.gmch_n, \
12360 current_config->name.link_m, \
12361 current_config->name.link_n, \
12362 current_config->alt_name.tu, \
12363 current_config->alt_name.gmch_m, \
12364 current_config->alt_name.gmch_n, \
12365 current_config->alt_name.link_m, \
12366 current_config->alt_name.link_n, \
12367 pipe_config->name.tu, \
12368 pipe_config->name.gmch_m, \
12369 pipe_config->name.gmch_n, \
12370 pipe_config->name.link_m, \
12371 pipe_config->name.link_n); \
12372 ret = false; \
88adfff1
DV		 12373 }
12374
b95af8be
VK		 12375/* This is required for BDW+ where there is only one set of registers for
12376 * switching between high and low RR.
12377 * This macro can be used whenever a comparison has to be made between one
12378 * hw state and multiple sw state variables.
12379 */
12380#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12381 if ((current_config->name != pipe_config->name) && \
12382 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12383 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12384 "(expected %i or %i, found %i)\n", \
12385 current_config->name, \
12386 current_config->alt_name, \
12387 pipe_config->name); \
cfb23ed6 12388 ret = false; \
b95af8be
VK		 12389 }
12390
1bd1bd80
DV		 12391#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12392 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12393 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12394 "(expected %i, found %i)\n", \
12395 current_config->name & (mask), \
12396 pipe_config->name & (mask)); \
cfb23ed6 12397 ret = false; \
1bd1bd80
DV		 12398 }
12399
5e550656
VS		 12400#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12401 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12402 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12403 "(expected %i, found %i)\n", \
12404 current_config->name, \
12405 pipe_config->name); \
cfb23ed6 12406 ret = false; \
5e550656
VS		 12407 }
12408
bb760063
DV		 12409#define PIPE_CONF_QUIRK(quirk) \
12410 ((current_config->quirks | pipe_config->quirks) & (quirk))
12411
eccb140b
DV		 12412 PIPE_CONF_CHECK_I(cpu_transcoder);
12413
08a24034
DV		 12414 PIPE_CONF_CHECK_I(has_pch_encoder);
12415 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12416 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12417
eb14cb74 12418 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12419
12420 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12421 PIPE_CONF_CHECK_M_N(dp_m_n);
12422
12423 PIPE_CONF_CHECK_I(has_drrs);
12424 if (current_config->has_drrs)
12425 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12426 } else
12427 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12428
2d112de7
ACO		 12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12435
2d112de7
ACO		 12436 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12440 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12441 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12442
c93f54cf 12443 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12444 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12445 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12446 IS_VALLEYVIEW(dev))
12447 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12448 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12449
9ed109a7
DV		 12450 PIPE_CONF_CHECK_I(has_audio);
12451
2d112de7 12452 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12453 DRM_MODE_FLAG_INTERLACE);
12454
bb760063 12455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12456 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12457 DRM_MODE_FLAG_PHSYNC);
2d112de7 12458 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12459 DRM_MODE_FLAG_NHSYNC);
2d112de7 12460 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12461 DRM_MODE_FLAG_PVSYNC);
2d112de7 12462 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12463 DRM_MODE_FLAG_NVSYNC);
12464 }
045ac3b5 12465
37327abd
VS		 12466 PIPE_CONF_CHECK_I(pipe_src_w);
12467 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12468
e2ff2d4a
DV		 12469 PIPE_CONF_CHECK_I(gmch_pfit.control);
12470 /* pfit ratios are autocomputed by the hw on gen4+ */
12471 if (INTEL_INFO(dev)->gen < 4)
12472 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12473 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9953599b 12474
fd4daa9c
CW		 12475 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12476 if (current_config->pch_pfit.enabled) {
12477 PIPE_CONF_CHECK_I(pch_pfit.pos);
12478 PIPE_CONF_CHECK_I(pch_pfit.size);
12479 }
2fa2fe9a 12480
a1b2278e
CK		 12481 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12482
e59150dc
JB		 12483 /* BDW+ don't expose a synchronous way to read the state */
12484 if (IS_HASWELL(dev))
12485 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12486
282740f7
VS		 12487 PIPE_CONF_CHECK_I(double_wide);
12488
26804afd
DV		 12489 PIPE_CONF_CHECK_X(ddi_pll_sel);
12490
c0d43d62 12491 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12492 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12493 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12494 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12495 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12496 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12497 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12498 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12499 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12500
42571aef
VS		 12501 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12502 PIPE_CONF_CHECK_I(pipe_bpp);
12503
2d112de7 12504 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12505 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12506
66e985c0 12507#undef PIPE_CONF_CHECK_X
08a24034 12508#undef PIPE_CONF_CHECK_I
b95af8be 12509#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12510#undef PIPE_CONF_CHECK_FLAGS
5e550656 12511#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12512#undef PIPE_CONF_QUIRK
cfb23ed6 12513#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12514
cfb23ed6 12515 return ret;
0e8ffe1b
DV		 12516}
12517
08db6652
DL		 12518static void check_wm_state(struct drm_device *dev)
12519{
12520 struct drm_i915_private *dev_priv = dev->dev_private;
12521 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12522 struct intel_crtc *intel_crtc;
12523 int plane;
12524
12525 if (INTEL_INFO(dev)->gen < 9)
12526 return;
12527
12528 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12529 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12530
12531 for_each_intel_crtc(dev, intel_crtc) {
12532 struct skl_ddb_entry *hw_entry, *sw_entry;
12533 const enum pipe pipe = intel_crtc->pipe;
12534
12535 if (!intel_crtc->active)
12536 continue;
12537
12538 /* planes */
dd740780 12539 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12540 hw_entry = &hw_ddb.plane[pipe][plane];
12541 sw_entry = &sw_ddb->plane[pipe][plane];
12542
12543 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12544 continue;
12545
12546 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12547 "(expected (%u,%u), found (%u,%u))\n",
12548 pipe_name(pipe), plane + 1,
12549 sw_entry->start, sw_entry->end,
12550 hw_entry->start, hw_entry->end);
12551 }
12552
12553 /* cursor */
12554 hw_entry = &hw_ddb.cursor[pipe];
12555 sw_entry = &sw_ddb->cursor[pipe];
12556
12557 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12558 continue;
12559
12560 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12561 "(expected (%u,%u), found (%u,%u))\n",
12562 pipe_name(pipe),
12563 sw_entry->start, sw_entry->end,
12564 hw_entry->start, hw_entry->end);
12565 }
12566}
12567
91d1b4bd 12568static void
35dd3c64
ML		 12569check_connector_state(struct drm_device *dev,
12570 struct drm_atomic_state *old_state)
8af6cf88 12571{
35dd3c64
ML		 12572 struct drm_connector_state *old_conn_state;
12573 struct drm_connector *connector;
12574 int i;
8af6cf88 12575
35dd3c64
ML		 12576 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12577 struct drm_encoder *encoder = connector->encoder;
12578 struct drm_connector_state *state = connector->state;
ad3c558f 12579
8af6cf88
DV		 12580 /* This also checks the encoder/connector hw state with the
12581 * ->get_hw_state callbacks. */
35dd3c64 12582 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12583
ad3c558f 12584 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12585 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12586 }
91d1b4bd
DV		 12587}
12588
12589static void
12590check_encoder_state(struct drm_device *dev)
12591{
12592 struct intel_encoder *encoder;
12593 struct intel_connector *connector;
8af6cf88 12594
b2784e15 12595 for_each_intel_encoder(dev, encoder) {
8af6cf88 12596 bool enabled = false;
4d20cd86 12597 enum pipe pipe;
8af6cf88
DV		 12598
12599 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12600 encoder->base.base.id,
8e329a03 12601 encoder->base.name);
8af6cf88 12602
3a3371ff 12603 for_each_intel_connector(dev, connector) {
4d20cd86 12604 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12605 continue;
12606 enabled = true;
ad3c558f
ML		 12607
12608 I915_STATE_WARN(connector->base.state->crtc !=
12609 encoder->base.crtc,
12610 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12611 }
0e32b39c 12612
e2c719b7 12613 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12614 "encoder's enabled state mismatch "
12615 "(expected %i, found %i)\n",
12616 !!encoder->base.crtc, enabled);
7c60d198
ML		 12617
12618 if (!encoder->base.crtc) {
4d20cd86 12619 bool active;
7c60d198 12620
4d20cd86
ML		 12621 active = encoder->get_hw_state(encoder, &pipe);
12622 I915_STATE_WARN(active,
12623 "encoder detached but still enabled on pipe %c.\n",
12624 pipe_name(pipe));
7c60d198 12625 }
8af6cf88 12626 }
91d1b4bd
DV		 12627}
12628
12629static void
4d20cd86 12630check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12631{
fbee40df 12632 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12633 struct intel_encoder *encoder;
4d20cd86
ML		 12634 struct drm_crtc_state *old_crtc_state;
12635 struct drm_crtc *crtc;
12636 int i;
8af6cf88 12637
4d20cd86
ML		 12638 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12640 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12641 bool active;
8af6cf88 12642
4d20cd86
ML		 12643 if (!needs_modeset(crtc->state))
12644 continue;
045ac3b5 12645
4d20cd86
ML		 12646 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12647 pipe_config = to_intel_crtc_state(old_crtc_state);
12648 memset(pipe_config, 0, sizeof(*pipe_config));
12649 pipe_config->base.crtc = crtc;
12650 pipe_config->base.state = old_state;
8af6cf88 12651
4d20cd86
ML		 12652 DRM_DEBUG_KMS("[CRTC:%d]\n",
12653 crtc->base.id);
8af6cf88 12654
4d20cd86
ML		 12655 active = dev_priv->display.get_pipe_config(intel_crtc,
12656 pipe_config);
d62cf62a 12657
b6b5d049 12658 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12659 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12660 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12661 active = crtc->state->active;
6c49f241 12662
4d20cd86 12663 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12664 "crtc active state doesn't match with hw state "
4d20cd86 12665 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12666
4d20cd86 12667 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12668 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12669 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12670
12671 for_each_encoder_on_crtc(dev, crtc, encoder) {
12672 enum pipe pipe;
12673
12674 active = encoder->get_hw_state(encoder, &pipe);
12675 I915_STATE_WARN(active != crtc->state->active,
12676 "[ENCODER:%i] active %i with crtc active %i\n",
12677 encoder->base.base.id, active, crtc->state->active);
12678
12679 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12680 "Encoder connected to wrong pipe %c\n",
12681 pipe_name(pipe));
12682
12683 if (active)
12684 encoder->get_config(encoder, pipe_config);
12685 }
53d9f4e9 12686
4d20cd86 12687 if (!crtc->state->active)
cfb23ed6
ML		 12688 continue;
12689
4d20cd86
ML		 12690 sw_config = to_intel_crtc_state(crtc->state);
12691 if (!intel_pipe_config_compare(dev, sw_config,
12692 pipe_config, false)) {
e2c719b7 12693 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12694 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12695 "[hw state]");
4d20cd86 12696 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12697 "[sw state]");
12698 }
8af6cf88
DV		 12699 }
12700}
12701
91d1b4bd
DV		 12702static void
12703check_shared_dpll_state(struct drm_device *dev)
12704{
fbee40df 12705 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12706 struct intel_crtc *crtc;
12707 struct intel_dpll_hw_state dpll_hw_state;
12708 int i;
5358901f
DV		 12709
12710 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12711 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12712 int enabled_crtcs = 0, active_crtcs = 0;
12713 bool active;
12714
12715 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12716
12717 DRM_DEBUG_KMS("%s\n", pll->name);
12718
12719 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12720
e2c719b7 12721 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12722 "more active pll users than references: %i vs %i\n",
3e369b76 12723 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12724 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12725 "pll in active use but not on in sw tracking\n");
e2c719b7 12726 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12727 "pll in on but not on in use in sw tracking\n");
e2c719b7 12728 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12729 "pll on state mismatch (expected %i, found %i)\n",
12730 pll->on, active);
12731
d3fcc808 12732 for_each_intel_crtc(dev, crtc) {
83d65738 12733 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12734 enabled_crtcs++;
12735 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12736 active_crtcs++;
12737 }
e2c719b7 12738 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12739 "pll active crtcs mismatch (expected %i, found %i)\n",
12740 pll->active, active_crtcs);
e2c719b7 12741 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12742 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12743 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12744
e2c719b7 12745 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12746 sizeof(dpll_hw_state)),
12747 "pll hw state mismatch\n");
5358901f 12748 }
8af6cf88
DV		 12749}
12750
ee165b1a
ML		 12751static void
12752intel_modeset_check_state(struct drm_device *dev,
12753 struct drm_atomic_state *old_state)
91d1b4bd 12754{
08db6652 12755 check_wm_state(dev);
35dd3c64 12756 check_connector_state(dev, old_state);
91d1b4bd 12757 check_encoder_state(dev);
4d20cd86 12758 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12759 check_shared_dpll_state(dev);
12760}
12761
5cec258b 12762void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12763 int dotclock)
12764{
12765 /*
12766 * FDI already provided one idea for the dotclock.
12767 * Yell if the encoder disagrees.
12768 */
2d112de7 12769 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12770 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12771 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12772}
12773
80715b2f
VS		 12774static void update_scanline_offset(struct intel_crtc *crtc)
12775{
12776 struct drm_device *dev = crtc->base.dev;
12777
12778 /*
12779 * The scanline counter increments at the leading edge of hsync.
12780 *
12781 * On most platforms it starts counting from vtotal-1 on the
12782 * first active line. That means the scanline counter value is
12783 * always one less than what we would expect. Ie. just after
12784 * start of vblank, which also occurs at start of hsync (on the
12785 * last active line), the scanline counter will read vblank_start-1.
12786 *
12787 * On gen2 the scanline counter starts counting from 1 instead
12788 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12789 * to keep the value positive), instead of adding one.
12790 *
12791 * On HSW+ the behaviour of the scanline counter depends on the output
12792 * type. For DP ports it behaves like most other platforms, but on HDMI
12793 * there's an extra 1 line difference. So we need to add two instead of
12794 * one to the value.
12795 */
12796 if (IS_GEN2(dev)) {
6e3c9717 12797 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12798 int vtotal;
12799
12800 vtotal = mode->crtc_vtotal;
12801 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12802 vtotal /= 2;
12803
12804 crtc->scanline_offset = vtotal - 1;
12805 } else if (HAS_DDI(dev) &&
409ee761 12806 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12807 crtc->scanline_offset = 2;
12808 } else
12809 crtc->scanline_offset = 1;
12810}
12811
ad421372 12812static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12813{
225da59b 12814 struct drm_device *dev = state->dev;
ed6739ef 12815 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12816 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12817 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12818 struct intel_crtc_state *intel_crtc_state;
12819 struct drm_crtc *crtc;
12820 struct drm_crtc_state *crtc_state;
0a9ab303 12821 int i;
ed6739ef
ACO		 12822
12823 if (!dev_priv->display.crtc_compute_clock)
ad421372 12824 return;
ed6739ef 12825
0a9ab303 12826 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12827 int dpll;
12828
0a9ab303 12829 intel_crtc = to_intel_crtc(crtc);
4978cc93 12830 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12831 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12832
ad421372 12833 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12834 continue;
12835
ad421372 12836 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12837
ad421372
ML		 12838 if (!shared_dpll)
12839 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12840
ad421372
ML		 12841 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12842 }
ed6739ef
ACO		 12843}
12844
99d736a2
ML		 12845/*
12846 * This implements the workaround described in the "notes" section of the mode
12847 * set sequence documentation. When going from no pipes or single pipe to
12848 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12849 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12850 */
12851static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12852{
12853 struct drm_crtc_state *crtc_state;
12854 struct intel_crtc *intel_crtc;
12855 struct drm_crtc *crtc;
12856 struct intel_crtc_state *first_crtc_state = NULL;
12857 struct intel_crtc_state *other_crtc_state = NULL;
12858 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12859 int i;
12860
12861 /* look at all crtc's that are going to be enabled in during modeset */
12862 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12863 intel_crtc = to_intel_crtc(crtc);
12864
12865 if (!crtc_state->active || !needs_modeset(crtc_state))
12866 continue;
12867
12868 if (first_crtc_state) {
12869 other_crtc_state = to_intel_crtc_state(crtc_state);
12870 break;
12871 } else {
12872 first_crtc_state = to_intel_crtc_state(crtc_state);
12873 first_pipe = intel_crtc->pipe;
12874 }
12875 }
12876
12877 /* No workaround needed? */
12878 if (!first_crtc_state)
12879 return 0;
12880
12881 /* w/a possibly needed, check how many crtc's are already enabled. */
12882 for_each_intel_crtc(state->dev, intel_crtc) {
12883 struct intel_crtc_state *pipe_config;
12884
12885 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12886 if (IS_ERR(pipe_config))
12887 return PTR_ERR(pipe_config);
12888
12889 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12890
12891 if (!pipe_config->base.active ||
12892 needs_modeset(&pipe_config->base))
12893 continue;
12894
12895 /* 2 or more enabled crtcs means no need for w/a */
12896 if (enabled_pipe != INVALID_PIPE)
12897 return 0;
12898
12899 enabled_pipe = intel_crtc->pipe;
12900 }
12901
12902 if (enabled_pipe != INVALID_PIPE)
12903 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12904 else if (other_crtc_state)
12905 other_crtc_state->hsw_workaround_pipe = first_pipe;
12906
12907 return 0;
12908}
12909
27c329ed
ML		 12910static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12911{
12912 struct drm_crtc *crtc;
12913 struct drm_crtc_state *crtc_state;
12914 int ret = 0;
12915
12916 /* add all active pipes to the state */
12917 for_each_crtc(state->dev, crtc) {
12918 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12919 if (IS_ERR(crtc_state))
12920 return PTR_ERR(crtc_state);
12921
12922 if (!crtc_state->active || needs_modeset(crtc_state))
12923 continue;
12924
12925 crtc_state->mode_changed = true;
12926
12927 ret = drm_atomic_add_affected_connectors(state, crtc);
12928 if (ret)
12929 break;
12930
12931 ret = drm_atomic_add_affected_planes(state, crtc);
12932 if (ret)
12933 break;
12934 }
12935
12936 return ret;
12937}
12938
12939
c347a676 12940static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12941{
12942 struct drm_device *dev = state->dev;
27c329ed 12943 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12944 int ret;
12945
b359283a
ML		 12946 if (!check_digital_port_conflicts(state)) {
12947 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12948 return -EINVAL;
12949 }
12950
054518dd
ACO		 12951 /*
12952 * See if the config requires any additional preparation, e.g.
12953 * to adjust global state with pipes off. We need to do this
12954 * here so we can get the modeset_pipe updated config for the new
12955 * mode set on this crtc. For other crtcs we need to use the
12956 * adjusted_mode bits in the crtc directly.
12957 */
27c329ed
ML		 12958 if (dev_priv->display.modeset_calc_cdclk) {
12959 unsigned int cdclk;
b432e5cf 12960
27c329ed
ML		 12961 ret = dev_priv->display.modeset_calc_cdclk(state);
12962
12963 cdclk = to_intel_atomic_state(state)->cdclk;
12964 if (!ret && cdclk != dev_priv->cdclk_freq)
12965 ret = intel_modeset_all_pipes(state);
12966
12967 if (ret < 0)
054518dd 12968 return ret;
27c329ed
ML		 12969 } else
12970 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12971
ad421372 12972 intel_modeset_clear_plls(state);
054518dd 12973
99d736a2 12974 if (IS_HASWELL(dev))
ad421372 12975 return haswell_mode_set_planes_workaround(state);
99d736a2 12976
ad421372 12977 return 0;
c347a676
ACO		 12978}
12979
74c090b1
ML		 12980/**
12981 * intel_atomic_check - validate state object
12982 * @dev: drm device
12983 * @state: state to validate
12984 */
12985static int intel_atomic_check(struct drm_device *dev,
12986 struct drm_atomic_state *state)
c347a676
ACO		 12987{
12988 struct drm_crtc *crtc;
12989 struct drm_crtc_state *crtc_state;
12990 int ret, i;
61333b60 12991 bool any_ms = false;
c347a676 12992
74c090b1 12993 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12994 if (ret)
12995 return ret;
12996
c347a676 12997 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12998 struct intel_crtc_state *pipe_config =
12999 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13000
13001 /* Catch I915_MODE_FLAG_INHERITED */
13002 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13003 crtc_state->mode_changed = true;
cfb23ed6 13004
61333b60
ML		 13005 if (!crtc_state->enable) {
13006 if (needs_modeset(crtc_state))
13007 any_ms = true;
c347a676 13008 continue;
61333b60 13009 }
c347a676 13010
26495481 13011 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13012 continue;
13013
26495481
DV		 13014 /* FIXME: For only active_changed we shouldn't need to do any
13015 * state recomputation at all. */
13016
1ed51de9
DV		 13017 ret = drm_atomic_add_affected_connectors(state, crtc);
13018 if (ret)
13019 return ret;
b359283a 13020
cfb23ed6 13021 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13022 if (ret)
13023 return ret;
13024
26495481
DV		 13025 if (i915.fastboot &&
13026 intel_pipe_config_compare(state->dev,
cfb23ed6 13027 to_intel_crtc_state(crtc->state),
1ed51de9 13028 pipe_config, true)) {
26495481
DV		 13029 crtc_state->mode_changed = false;
13030 }
13031
13032 if (needs_modeset(crtc_state)) {
13033 any_ms = true;
cfb23ed6
ML		 13034
13035 ret = drm_atomic_add_affected_planes(state, crtc);
13036 if (ret)
13037 return ret;
13038 }
61333b60 13039
26495481
DV		 13040 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13041 needs_modeset(crtc_state) ?
13042 "[modeset]" : "[fastset]");
c347a676
ACO		 13043 }
13044
61333b60
ML		 13045 if (any_ms) {
13046 ret = intel_modeset_checks(state);
13047
13048 if (ret)
13049 return ret;
27c329ed
ML		 13050 } else
13051 to_intel_atomic_state(state)->cdclk =
13052 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13053
13054 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13055}
13056
74c090b1
ML		 13057/**
13058 * intel_atomic_commit - commit validated state object
13059 * @dev: DRM device
13060 * @state: the top-level driver state object
13061 * @async: asynchronous commit
13062 *
13063 * This function commits a top-level state object that has been validated
13064 * with drm_atomic_helper_check().
13065 *
13066 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13067 * we can only handle plane-related operations and do not yet support
13068 * asynchronous commit.
13069 *
13070 * RETURNS
13071 * Zero for success or -errno.
13072 */
13073static int intel_atomic_commit(struct drm_device *dev,
13074 struct drm_atomic_state *state,
13075 bool async)
a6778b3c 13076{
fbee40df 13077 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13078 struct drm_crtc *crtc;
13079 struct drm_crtc_state *crtc_state;
c0c36b94 13080 int ret = 0;
0a9ab303 13081 int i;
61333b60 13082 bool any_ms = false;
a6778b3c 13083
74c090b1
ML		 13084 if (async) {
13085 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13086 return -EINVAL;
13087 }
13088
d4afb8cc
ACO		 13089 ret = drm_atomic_helper_prepare_planes(dev, state);
13090 if (ret)
13091 return ret;
13092
1c5e19f8
ML		 13093 drm_atomic_helper_swap_state(dev, state);
13094
0a9ab303 13095 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13097
61333b60
ML		 13098 if (!needs_modeset(crtc->state))
13099 continue;
13100
13101 any_ms = true;
a539205a 13102 intel_pre_plane_update(intel_crtc);
460da916 13103
a539205a
ML		 13104 if (crtc_state->active) {
13105 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13106 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13107 intel_crtc->active = false;
13108 intel_disable_shared_dpll(intel_crtc);
a539205a 13109 }
b8cecdf5 13110 }
7758a113 13111
ea9d758d
DV		 13112 /* Only after disabling all output pipelines that will be changed can we
13113 * update the the output configuration. */
4740b0f2 13114 intel_modeset_update_crtc_state(state);
f6e5b160 13115
4740b0f2
ML		 13116 if (any_ms) {
13117 intel_shared_dpll_commit(state);
13118
13119 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13120 modeset_update_crtc_power_domains(state);
4740b0f2 13121 }
47fab737 13122
a6778b3c 13123 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13124 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13126 bool modeset = needs_modeset(crtc->state);
13127
13128 if (modeset && crtc->state->active) {
a539205a
ML		 13129 update_scanline_offset(to_intel_crtc(crtc));
13130 dev_priv->display.crtc_enable(crtc);
13131 }
80715b2f 13132
f6ac4b2a
ML		 13133 if (!modeset)
13134 intel_pre_plane_update(intel_crtc);
13135
a539205a 13136 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13137 intel_post_plane_update(intel_crtc);
80715b2f 13138 }
a6778b3c 13139
a6778b3c 13140 /* FIXME: add subpixel order */
83a57153 13141
74c090b1 13142 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13143 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13144
74c090b1 13145 if (any_ms)
ee165b1a
ML		 13146 intel_modeset_check_state(dev, state);
13147
13148 drm_atomic_state_free(state);
f30da187 13149
74c090b1 13150 return 0;
7f27126e
JB		 13151}
13152
c0c36b94
CW		 13153void intel_crtc_restore_mode(struct drm_crtc *crtc)
13154{
83a57153
ACO		 13155 struct drm_device *dev = crtc->dev;
13156 struct drm_atomic_state *state;
e694eb02 13157 struct drm_crtc_state *crtc_state;
2bfb4627 13158 int ret;
83a57153
ACO		 13159
13160 state = drm_atomic_state_alloc(dev);
13161 if (!state) {
e694eb02 13162 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13163 crtc->base.id);
13164 return;
13165 }
13166
e694eb02 13167 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13168
e694eb02
ML		 13169retry:
13170 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13171 ret = PTR_ERR_OR_ZERO(crtc_state);
13172 if (!ret) {
13173 if (!crtc_state->active)
13174 goto out;
83a57153 13175
e694eb02 13176 crtc_state->mode_changed = true;
74c090b1 13177 ret = drm_atomic_commit(state);
83a57153
ACO		 13178 }
13179
e694eb02
ML		 13180 if (ret == -EDEADLK) {
13181 drm_atomic_state_clear(state);
13182 drm_modeset_backoff(state->acquire_ctx);
13183 goto retry;
4ed9fb37 13184 }
4be07317 13185
2bfb4627 13186 if (ret)
e694eb02 13187out:
2bfb4627 13188 drm_atomic_state_free(state);
c0c36b94
CW		 13189}
13190
25c5b266
DV		 13191#undef for_each_intel_crtc_masked
13192
f6e5b160 13193static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13194 .gamma_set = intel_crtc_gamma_set,
74c090b1 13195 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13196 .destroy = intel_crtc_destroy,
13197 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13198 .atomic_duplicate_state = intel_crtc_duplicate_state,
13199 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13200};
13201
5358901f
DV		 13202static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13203 struct intel_shared_dpll *pll,
13204 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13205{
5358901f 13206 uint32_t val;
ee7b9f93 13207
f458ebbc 13208 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13209 return false;
13210
5358901f 13211 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13212 hw_state->dpll = val;
13213 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13214 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13215
13216 return val & DPLL_VCO_ENABLE;
13217}
13218
15bdd4cf
DV		 13219static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13220 struct intel_shared_dpll *pll)
13221{
3e369b76
ACO		 13222 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13223 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13224}
13225
e7b903d2
DV		 13226static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13227 struct intel_shared_dpll *pll)
13228{
e7b903d2 13229 /* PCH refclock must be enabled first */
89eff4be 13230 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13231
3e369b76 13232 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13233
13234 /* Wait for the clocks to stabilize. */
13235 POSTING_READ(PCH_DPLL(pll->id));
13236 udelay(150);
13237
13238 /* The pixel multiplier can only be updated once the
13239 * DPLL is enabled and the clocks are stable.
13240 *
13241 * So write it again.
13242 */
3e369b76 13243 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13244 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13245 udelay(200);
13246}
13247
13248static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13249 struct intel_shared_dpll *pll)
13250{
13251 struct drm_device *dev = dev_priv->dev;
13252 struct intel_crtc *crtc;
e7b903d2
DV		 13253
13254 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13255 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13256 if (intel_crtc_to_shared_dpll(crtc) == pll)
13257 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13258 }
13259
15bdd4cf
DV		 13260 I915_WRITE(PCH_DPLL(pll->id), 0);
13261 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13262 udelay(200);
13263}
13264
46edb027
DV		 13265static char *ibx_pch_dpll_names[] = {
13266 "PCH DPLL A",
13267 "PCH DPLL B",
13268};
13269
7c74ade1 13270static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13271{
e7b903d2 13272 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13273 int i;
13274
7c74ade1 13275 dev_priv->num_shared_dpll = 2;
ee7b9f93 13276
e72f9fbf 13277 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13278 dev_priv->shared_dplls[i].id = i;
13279 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13280 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13281 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13282 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13283 dev_priv->shared_dplls[i].get_hw_state =
13284 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13285 }
13286}
13287
7c74ade1
DV		 13288static void intel_shared_dpll_init(struct drm_device *dev)
13289{
e7b903d2 13290 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13291
b6283055
VS		 13292 intel_update_cdclk(dev);
13293
9cd86933
DV		 13294 if (HAS_DDI(dev))
13295 intel_ddi_pll_init(dev);
13296 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13297 ibx_pch_dpll_init(dev);
13298 else
13299 dev_priv->num_shared_dpll = 0;
13300
13301 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13302}
13303
6beb8c23
MR		 13304/**
13305 * intel_prepare_plane_fb - Prepare fb for usage on plane
13306 * @plane: drm plane to prepare for
13307 * @fb: framebuffer to prepare for presentation
13308 *
13309 * Prepares a framebuffer for usage on a display plane. Generally this
13310 * involves pinning the underlying object and updating the frontbuffer tracking
13311 * bits. Some older platforms need special physical address handling for
13312 * cursor planes.
13313 *
13314 * Returns 0 on success, negative error code on failure.
13315 */
13316int
13317intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13318 struct drm_framebuffer *fb,
13319 const struct drm_plane_state *new_state)
465c120c
MR		 13320{
13321 struct drm_device *dev = plane->dev;
6beb8c23 13322 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13323 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13324 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13325 int ret = 0;
465c120c 13326
ea2c67bb 13327 if (!obj)
465c120c
MR		 13328 return 0;
13329
6beb8c23 13330 mutex_lock(&dev->struct_mutex);
465c120c 13331
6beb8c23
MR		 13332 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13333 INTEL_INFO(dev)->cursor_needs_physical) {
13334 int align = IS_I830(dev) ? 16 * 1024 : 256;
13335 ret = i915_gem_object_attach_phys(obj, align);
13336 if (ret)
13337 DRM_DEBUG_KMS("failed to attach phys object\n");
13338 } else {
91af127f 13339 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13340 }
465c120c 13341
6beb8c23 13342 if (ret == 0)
a9ff8714 13343 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13344
4c34574f 13345 mutex_unlock(&dev->struct_mutex);
465c120c 13346
6beb8c23
MR		 13347 return ret;
13348}
13349
38f3ce3a
MR		 13350/**
13351 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13352 * @plane: drm plane to clean up for
13353 * @fb: old framebuffer that was on plane
13354 *
13355 * Cleans up a framebuffer that has just been removed from a plane.
13356 */
13357void
13358intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13359 struct drm_framebuffer *fb,
13360 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13361{
13362 struct drm_device *dev = plane->dev;
13363 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13364
13365 if (WARN_ON(!obj))
13366 return;
13367
13368 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13369 !INTEL_INFO(dev)->cursor_needs_physical) {
13370 mutex_lock(&dev->struct_mutex);
82bc3b2d 13371 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13372 mutex_unlock(&dev->struct_mutex);
13373 }
465c120c
MR		 13374}
13375
6156a456
CK		 13376int
13377skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13378{
13379 int max_scale;
13380 struct drm_device *dev;
13381 struct drm_i915_private *dev_priv;
13382 int crtc_clock, cdclk;
13383
13384 if (!intel_crtc || !crtc_state)
13385 return DRM_PLANE_HELPER_NO_SCALING;
13386
13387 dev = intel_crtc->base.dev;
13388 dev_priv = dev->dev_private;
13389 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13390 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13391
13392 if (!crtc_clock || !cdclk)
13393 return DRM_PLANE_HELPER_NO_SCALING;
13394
13395 /*
13396 * skl max scale is lower of:
13397 * close to 3 but not 3, -1 is for that purpose
13398 * or
13399 * cdclk/crtc_clock
13400 */
13401 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13402
13403 return max_scale;
13404}
13405
465c120c 13406static int
3c692a41 13407intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13408 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13409 struct intel_plane_state *state)
13410{
2b875c22
MR		 13411 struct drm_crtc *crtc = state->base.crtc;
13412 struct drm_framebuffer *fb = state->base.fb;
6156a456 13413 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13414 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13415 bool can_position = false;
465c120c 13416
061e4b8d
ML		 13417 /* use scaler when colorkey is not required */
13418 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13419 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13420 min_scale = 1;
13421 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13422 can_position = true;
6156a456 13423 }
d8106366 13424
061e4b8d
ML		 13425 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13426 &state->dst, &state->clip,
da20eabd
ML		 13427 min_scale, max_scale,
13428 can_position, true,
13429 &state->visible);
14af293f
GP		 13430}
13431
13432static void
13433intel_commit_primary_plane(struct drm_plane *plane,
13434 struct intel_plane_state *state)
13435{
2b875c22
MR		 13436 struct drm_crtc *crtc = state->base.crtc;
13437 struct drm_framebuffer *fb = state->base.fb;
13438 struct drm_device *dev = plane->dev;
14af293f 13439 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13440 struct intel_crtc *intel_crtc;
14af293f
GP		 13441 struct drm_rect *src = &state->src;
13442
ea2c67bb
MR		 13443 crtc = crtc ? crtc : plane->crtc;
13444 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13445
13446 plane->fb = fb;
9dc806fc
MR		 13447 crtc->x = src->x1 >> 16;
13448 crtc->y = src->y1 >> 16;
ccc759dc 13449
a539205a 13450 if (!crtc->state->active)
302d19ac 13451 return;
465c120c 13452
302d19ac
ML		 13453 if (state->visible)
13454 /* FIXME: kill this fastboot hack */
13455 intel_update_pipe_size(intel_crtc);
13456
13457 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13458}
13459
a8ad0d8e
ML		 13460static void
13461intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13462 struct drm_crtc *crtc)
a8ad0d8e
ML		 13463{
13464 struct drm_device *dev = plane->dev;
13465 struct drm_i915_private *dev_priv = dev->dev_private;
13466
a8ad0d8e
ML		 13467 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13468}
13469
613d2b27
ML		 13470static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13471 struct drm_crtc_state *old_crtc_state)
3c692a41 13472{
32b7eeec 13473 struct drm_device *dev = crtc->dev;
3c692a41 13474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13475
f015c551 13476 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13477 intel_update_watermarks(crtc);
3c692a41 13478
c34c9ee4 13479 /* Perform vblank evasion around commit operation */
a539205a 13480 if (crtc->state->active)
8f539a83 13481 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
0583236e
ML		 13482
13483 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13484 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13485}
13486
613d2b27
ML		 13487static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13488 struct drm_crtc_state *old_crtc_state)
32b7eeec 13489{
32b7eeec 13490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13491
8f539a83
ML		 13492 if (crtc->state->active)
13493 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
3c692a41
GP		 13494}
13495
cf4c7c12 13496/**
4a3b8769
MR		 13497 * intel_plane_destroy - destroy a plane
13498 * @plane: plane to destroy
cf4c7c12 13499 *
4a3b8769
MR		 13500 * Common destruction function for all types of planes (primary, cursor,
13501 * sprite).
cf4c7c12 13502 */
4a3b8769 13503void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13504{
13505 struct intel_plane *intel_plane = to_intel_plane(plane);
13506 drm_plane_cleanup(plane);
13507 kfree(intel_plane);
13508}
13509
65a3fea0 13510const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13511 .update_plane = drm_atomic_helper_update_plane,
13512 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13513 .destroy = intel_plane_destroy,
c196e1d6 13514 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13515 .atomic_get_property = intel_plane_atomic_get_property,
13516 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13517 .atomic_duplicate_state = intel_plane_duplicate_state,
13518 .atomic_destroy_state = intel_plane_destroy_state,
13519
465c120c
MR		 13520};
13521
13522static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13523 int pipe)
13524{
13525 struct intel_plane *primary;
8e7d688b 13526 struct intel_plane_state *state;
465c120c
MR		 13527 const uint32_t *intel_primary_formats;
13528 int num_formats;
13529
13530 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13531 if (primary == NULL)
13532 return NULL;
13533
8e7d688b
MR		 13534 state = intel_create_plane_state(&primary->base);
13535 if (!state) {
ea2c67bb
MR		 13536 kfree(primary);
13537 return NULL;
13538 }
8e7d688b 13539 primary->base.state = &state->base;
ea2c67bb 13540
465c120c
MR		 13541 primary->can_scale = false;
13542 primary->max_downscale = 1;
6156a456
CK		 13543 if (INTEL_INFO(dev)->gen >= 9) {
13544 primary->can_scale = true;
af99ceda 13545 state->scaler_id = -1;
6156a456 13546 }
465c120c
MR		 13547 primary->pipe = pipe;
13548 primary->plane = pipe;
a9ff8714 13549 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13550 primary->check_plane = intel_check_primary_plane;
13551 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13552 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13553 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13554 primary->plane = !pipe;
13555
6c0fd451
DL		 13556 if (INTEL_INFO(dev)->gen >= 9) {
13557 intel_primary_formats = skl_primary_formats;
13558 num_formats = ARRAY_SIZE(skl_primary_formats);
13559 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13560 intel_primary_formats = i965_primary_formats;
13561 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13562 } else {
13563 intel_primary_formats = i8xx_primary_formats;
13564 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13565 }
13566
13567 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13568 &intel_plane_funcs,
465c120c
MR		 13569 intel_primary_formats, num_formats,
13570 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13571
3b7a5119
SJ		 13572 if (INTEL_INFO(dev)->gen >= 4)
13573 intel_create_rotation_property(dev, primary);
48404c1e 13574
ea2c67bb
MR		 13575 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13576
465c120c
MR		 13577 return &primary->base;
13578}
13579
3b7a5119
SJ		 13580void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13581{
13582 if (!dev->mode_config.rotation_property) {
13583 unsigned long flags = BIT(DRM_ROTATE_0) |
13584 BIT(DRM_ROTATE_180);
13585
13586 if (INTEL_INFO(dev)->gen >= 9)
13587 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13588
13589 dev->mode_config.rotation_property =
13590 drm_mode_create_rotation_property(dev, flags);
13591 }
13592 if (dev->mode_config.rotation_property)
13593 drm_object_attach_property(&plane->base.base,
13594 dev->mode_config.rotation_property,
13595 plane->base.state->rotation);
13596}
13597
3d7d6510 13598static int
852e787c 13599intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13600 struct intel_crtc_state *crtc_state,
852e787c 13601 struct intel_plane_state *state)
3d7d6510 13602{
061e4b8d 13603 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13604 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13605 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13606 unsigned stride;
13607 int ret;
3d7d6510 13608
061e4b8d
ML		 13609 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13610 &state->dst, &state->clip,
3d7d6510
MR		 13611 DRM_PLANE_HELPER_NO_SCALING,
13612 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13613 true, true, &state->visible);
757f9a3e
GP		 13614 if (ret)
13615 return ret;
13616
757f9a3e
GP		 13617 /* if we want to turn off the cursor ignore width and height */
13618 if (!obj)
da20eabd 13619 return 0;
757f9a3e 13620
757f9a3e 13621 /* Check for which cursor types we support */
061e4b8d 13622 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13623 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13624 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13625 return -EINVAL;
13626 }
13627
ea2c67bb
MR		 13628 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13629 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13630 DRM_DEBUG_KMS("buffer is too small\n");
13631 return -ENOMEM;
13632 }
13633
3a656b54 13634 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13635 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13636 return -EINVAL;
32b7eeec
MR		 13637 }
13638
da20eabd 13639 return 0;
852e787c 13640}
3d7d6510 13641
a8ad0d8e
ML		 13642static void
13643intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13644 struct drm_crtc *crtc)
a8ad0d8e 13645{
a8ad0d8e
ML		 13646 intel_crtc_update_cursor(crtc, false);
13647}
13648
f4a2cf29 13649static void
852e787c
GP		 13650intel_commit_cursor_plane(struct drm_plane *plane,
13651 struct intel_plane_state *state)
13652{
2b875c22 13653 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13654 struct drm_device *dev = plane->dev;
13655 struct intel_crtc *intel_crtc;
2b875c22 13656 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13657 uint32_t addr;
852e787c 13658
ea2c67bb
MR		 13659 crtc = crtc ? crtc : plane->crtc;
13660 intel_crtc = to_intel_crtc(crtc);
13661
2b875c22 13662 plane->fb = state->base.fb;
ea2c67bb
MR		 13663 crtc->cursor_x = state->base.crtc_x;
13664 crtc->cursor_y = state->base.crtc_y;
13665
a912f12f
GP		 13666 if (intel_crtc->cursor_bo == obj)
13667 goto update;
4ed91096 13668
f4a2cf29 13669 if (!obj)
a912f12f 13670 addr = 0;
f4a2cf29 13671 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13672 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13673 else
a912f12f 13674 addr = obj->phys_handle->busaddr;
852e787c 13675
a912f12f
GP		 13676 intel_crtc->cursor_addr = addr;
13677 intel_crtc->cursor_bo = obj;
852e787c 13678
302d19ac 13679update:
a539205a 13680 if (crtc->state->active)
a912f12f 13681 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13682}
13683
3d7d6510
MR		 13684static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13685 int pipe)
13686{
13687 struct intel_plane *cursor;
8e7d688b 13688 struct intel_plane_state *state;
3d7d6510
MR		 13689
13690 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13691 if (cursor == NULL)
13692 return NULL;
13693
8e7d688b
MR		 13694 state = intel_create_plane_state(&cursor->base);
13695 if (!state) {
ea2c67bb
MR		 13696 kfree(cursor);
13697 return NULL;
13698 }
8e7d688b 13699 cursor->base.state = &state->base;
ea2c67bb 13700
3d7d6510
MR		 13701 cursor->can_scale = false;
13702 cursor->max_downscale = 1;
13703 cursor->pipe = pipe;
13704 cursor->plane = pipe;
a9ff8714 13705 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13706 cursor->check_plane = intel_check_cursor_plane;
13707 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13708 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13709
13710 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13711 &intel_plane_funcs,
3d7d6510
MR		 13712 intel_cursor_formats,
13713 ARRAY_SIZE(intel_cursor_formats),
13714 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13715
13716 if (INTEL_INFO(dev)->gen >= 4) {
13717 if (!dev->mode_config.rotation_property)
13718 dev->mode_config.rotation_property =
13719 drm_mode_create_rotation_property(dev,
13720 BIT(DRM_ROTATE_0) |
13721 BIT(DRM_ROTATE_180));
13722 if (dev->mode_config.rotation_property)
13723 drm_object_attach_property(&cursor->base.base,
13724 dev->mode_config.rotation_property,
8e7d688b 13725 state->base.rotation);
4398ad45
VS		 13726 }
13727
af99ceda
CK		 13728 if (INTEL_INFO(dev)->gen >=9)
13729 state->scaler_id = -1;
13730
ea2c67bb
MR		 13731 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13732
3d7d6510
MR		 13733 return &cursor->base;
13734}
13735
549e2bfb
CK		 13736static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13737 struct intel_crtc_state *crtc_state)
13738{
13739 int i;
13740 struct intel_scaler *intel_scaler;
13741 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13742
13743 for (i = 0; i < intel_crtc->num_scalers; i++) {
13744 intel_scaler = &scaler_state->scalers[i];
13745 intel_scaler->in_use = 0;
549e2bfb
CK		 13746 intel_scaler->mode = PS_SCALER_MODE_DYN;
13747 }
13748
13749 scaler_state->scaler_id = -1;
13750}
13751
b358d0a6 13752static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13753{
fbee40df 13754 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13755 struct intel_crtc *intel_crtc;
f5de6e07 13756 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13757 struct drm_plane *primary = NULL;
13758 struct drm_plane *cursor = NULL;
465c120c 13759 int i, ret;
79e53945 13760
955382f3 13761 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13762 if (intel_crtc == NULL)
13763 return;
13764
f5de6e07
ACO		 13765 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13766 if (!crtc_state)
13767 goto fail;
550acefd
ACO		 13768 intel_crtc->config = crtc_state;
13769 intel_crtc->base.state = &crtc_state->base;
07878248 13770 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13771
549e2bfb
CK		 13772 /* initialize shared scalers */
13773 if (INTEL_INFO(dev)->gen >= 9) {
13774 if (pipe == PIPE_C)
13775 intel_crtc->num_scalers = 1;
13776 else
13777 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13778
13779 skl_init_scalers(dev, intel_crtc, crtc_state);
13780 }
13781
465c120c 13782 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13783 if (!primary)
13784 goto fail;
13785
13786 cursor = intel_cursor_plane_create(dev, pipe);
13787 if (!cursor)
13788 goto fail;
13789
465c120c 13790 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13791 cursor, &intel_crtc_funcs);
13792 if (ret)
13793 goto fail;
79e53945
JB		 13794
13795 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13796 for (i = 0; i < 256; i++) {
13797 intel_crtc->lut_r[i] = i;
13798 intel_crtc->lut_g[i] = i;
13799 intel_crtc->lut_b[i] = i;
13800 }
13801
1f1c2e24
VS		 13802 /*
13803 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13804 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13805 */
80824003
JB		 13806 intel_crtc->pipe = pipe;
13807 intel_crtc->plane = pipe;
3a77c4c4 13808 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13809 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13810 intel_crtc->plane = !pipe;
80824003
JB		 13811 }
13812
4b0e333e
CW		 13813 intel_crtc->cursor_base = ~0;
13814 intel_crtc->cursor_cntl = ~0;
dc41c154 13815 intel_crtc->cursor_size = ~0;
8d7849db 13816
852eb00d
VS		 13817 intel_crtc->wm.cxsr_allowed = true;
13818
22fd0fab
JB		 13819 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13820 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13821 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13822 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13823
79e53945 13824 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13825
13826 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13827 return;
13828
13829fail:
13830 if (primary)
13831 drm_plane_cleanup(primary);
13832 if (cursor)
13833 drm_plane_cleanup(cursor);
f5de6e07 13834 kfree(crtc_state);
3d7d6510 13835 kfree(intel_crtc);
79e53945
JB		 13836}
13837
752aa88a
JB		 13838enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13839{
13840 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13841 struct drm_device *dev = connector->base.dev;
752aa88a 13842
51fd371b 13843 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13844
d3babd3f 13845 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13846 return INVALID_PIPE;
13847
13848 return to_intel_crtc(encoder->crtc)->pipe;
13849}
13850
08d7b3d1 13851int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13852 struct drm_file *file)
08d7b3d1 13853{
08d7b3d1 13854 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13855 struct drm_crtc *drmmode_crtc;
c05422d5 13856 struct intel_crtc *crtc;
08d7b3d1 13857
7707e653 13858 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13859
7707e653 13860 if (!drmmode_crtc) {
08d7b3d1 13861 DRM_ERROR("no such CRTC id\n");
3f2c2057 13862 return -ENOENT;
08d7b3d1
CW		 13863 }
13864
7707e653 13865 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13866 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13867
c05422d5 13868 return 0;
08d7b3d1
CW		 13869}
13870
66a9278e 13871static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13872{
66a9278e
DV		 13873 struct drm_device *dev = encoder->base.dev;
13874 struct intel_encoder *source_encoder;
79e53945 13875 int index_mask = 0;
79e53945
JB		 13876 int entry = 0;
13877
b2784e15 13878 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13879 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13880 index_mask |= (1 << entry);
13881
79e53945
JB		 13882 entry++;
13883 }
4ef69c7a 13884
79e53945
JB		 13885 return index_mask;
13886}
13887
4d302442
CW		 13888static bool has_edp_a(struct drm_device *dev)
13889{
13890 struct drm_i915_private *dev_priv = dev->dev_private;
13891
13892 if (!IS_MOBILE(dev))
13893 return false;
13894
13895 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13896 return false;
13897
e3589908 13898 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13899 return false;
13900
13901 return true;
13902}
13903
84b4e042
JB		 13904static bool intel_crt_present(struct drm_device *dev)
13905{
13906 struct drm_i915_private *dev_priv = dev->dev_private;
13907
884497ed
DL		 13908 if (INTEL_INFO(dev)->gen >= 9)
13909 return false;
13910
cf404ce4 13911 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13912 return false;
13913
13914 if (IS_CHERRYVIEW(dev))
13915 return false;
13916
13917 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13918 return false;
13919
13920 return true;
13921}
13922
79e53945
JB		 13923static void intel_setup_outputs(struct drm_device *dev)
13924{
725e30ad 13925 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13926 struct intel_encoder *encoder;
cb0953d7 13927 bool dpd_is_edp = false;
79e53945 13928
c9093354 13929 intel_lvds_init(dev);
79e53945 13930
84b4e042 13931 if (intel_crt_present(dev))
79935fca 13932 intel_crt_init(dev);
cb0953d7 13933
c776eb2e
VK		 13934 if (IS_BROXTON(dev)) {
13935 /*
13936 * FIXME: Broxton doesn't support port detection via the
13937 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13938 * detect the ports.
13939 */
13940 intel_ddi_init(dev, PORT_A);
13941 intel_ddi_init(dev, PORT_B);
13942 intel_ddi_init(dev, PORT_C);
13943 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13944 int found;
13945
de31facd
JB		 13946 /*
13947 * Haswell uses DDI functions to detect digital outputs.
13948 * On SKL pre-D0 the strap isn't connected, so we assume
13949 * it's there.
13950 */
0e72a5b5 13951 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13952 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13953 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13954 intel_ddi_init(dev, PORT_A);
13955
13956 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13957 * register */
13958 found = I915_READ(SFUSE_STRAP);
13959
13960 if (found & SFUSE_STRAP_DDIB_DETECTED)
13961 intel_ddi_init(dev, PORT_B);
13962 if (found & SFUSE_STRAP_DDIC_DETECTED)
13963 intel_ddi_init(dev, PORT_C);
13964 if (found & SFUSE_STRAP_DDID_DETECTED)
13965 intel_ddi_init(dev, PORT_D);
13966 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13967 int found;
5d8a7752 13968 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13969
13970 if (has_edp_a(dev))
13971 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13972
dc0fa718 13973 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13974 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13975 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13976 if (!found)
e2debe91 13977 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13978 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13979 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13980 }
13981
dc0fa718 13982 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13983 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13984
dc0fa718 13985 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13986 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13987
5eb08b69 13988 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13989 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13990
270b3042 13991 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13992 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13993 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13994 /*
13995 * The DP_DETECTED bit is the latched state of the DDC
13996 * SDA pin at boot. However since eDP doesn't require DDC
13997 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13998 * eDP ports may have been muxed to an alternate function.
13999 * Thus we can't rely on the DP_DETECTED bit alone to detect
14000 * eDP ports. Consult the VBT as well as DP_DETECTED to
14001 * detect eDP ports.
14002 */
d2182a66
VS		 14003 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14004 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14005 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14006 PORT_B);
e17ac6db
VS		 14007 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14008 intel_dp_is_edp(dev, PORT_B))
14009 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14010
d2182a66
VS		 14011 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14012 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14013 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14014 PORT_C);
e17ac6db
VS		 14015 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14016 intel_dp_is_edp(dev, PORT_C))
14017 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14018
9418c1f1 14019 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14020 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14021 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14022 PORT_D);
e17ac6db
VS		 14023 /* eDP not supported on port D, so don't check VBT */
14024 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14025 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14026 }
14027
3cfca973 14028 intel_dsi_init(dev);
09da55dc 14029 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14030 bool found = false;
7d57382e 14031
e2debe91 14032 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14033 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14034 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14035 if (!found && IS_G4X(dev)) {
b01f2c3a 14036 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14037 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14038 }
27185ae1 14039
3fec3d2f 14040 if (!found && IS_G4X(dev))
ab9d7c30 14041 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14042 }
13520b05
KH		 14043
14044 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14045
e2debe91 14046 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14047 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14048 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14049 }
27185ae1 14050
e2debe91 14051 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14052
3fec3d2f 14053 if (IS_G4X(dev)) {
b01f2c3a 14054 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14055 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14056 }
3fec3d2f 14057 if (IS_G4X(dev))
ab9d7c30 14058 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14059 }
27185ae1 14060
3fec3d2f 14061 if (IS_G4X(dev) &&
e7281eab 14062 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14063 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14064 } else if (IS_GEN2(dev))
79e53945
JB		 14065 intel_dvo_init(dev);
14066
103a196f 14067 if (SUPPORTS_TV(dev))
79e53945
JB		 14068 intel_tv_init(dev);
14069
0bc12bcb 14070 intel_psr_init(dev);
7c8f8a70 14071
b2784e15 14072 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14073 encoder->base.possible_crtcs = encoder->crtc_mask;
14074 encoder->base.possible_clones =
66a9278e 14075 intel_encoder_clones(encoder);
79e53945 14076 }
47356eb6 14077
dde86e2d 14078 intel_init_pch_refclk(dev);
270b3042
DV		 14079
14080 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14081}
14082
14083static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14084{
60a5ca01 14085 struct drm_device *dev = fb->dev;
79e53945 14086 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14087
ef2d633e 14088 drm_framebuffer_cleanup(fb);
60a5ca01 14089 mutex_lock(&dev->struct_mutex);
ef2d633e 14090 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14091 drm_gem_object_unreference(&intel_fb->obj->base);
14092 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14093 kfree(intel_fb);
14094}
14095
14096static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14097 struct drm_file *file,
79e53945
JB		 14098 unsigned int *handle)
14099{
14100 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14101 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14102
05394f39 14103 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14104}
14105
86c98588
RV		 14106static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14107 struct drm_file *file,
14108 unsigned flags, unsigned color,
14109 struct drm_clip_rect *clips,
14110 unsigned num_clips)
14111{
14112 struct drm_device *dev = fb->dev;
14113 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14114 struct drm_i915_gem_object *obj = intel_fb->obj;
14115
14116 mutex_lock(&dev->struct_mutex);
74b4ea1e 14117 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14118 mutex_unlock(&dev->struct_mutex);
14119
14120 return 0;
14121}
14122
79e53945
JB		 14123static const struct drm_framebuffer_funcs intel_fb_funcs = {
14124 .destroy = intel_user_framebuffer_destroy,
14125 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14126 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14127};
14128
b321803d
DL		 14129static
14130u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14131 uint32_t pixel_format)
14132{
14133 u32 gen = INTEL_INFO(dev)->gen;
14134
14135 if (gen >= 9) {
14136 /* "The stride in bytes must not exceed the of the size of 8K
14137 * pixels and 32K bytes."
14138 */
14139 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14140 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14141 return 32*1024;
14142 } else if (gen >= 4) {
14143 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14144 return 16*1024;
14145 else
14146 return 32*1024;
14147 } else if (gen >= 3) {
14148 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14149 return 8*1024;
14150 else
14151 return 16*1024;
14152 } else {
14153 /* XXX DSPC is limited to 4k tiled */
14154 return 8*1024;
14155 }
14156}
14157
b5ea642a
DV		 14158static int intel_framebuffer_init(struct drm_device *dev,
14159 struct intel_framebuffer *intel_fb,
14160 struct drm_mode_fb_cmd2 *mode_cmd,
14161 struct drm_i915_gem_object *obj)
79e53945 14162{
6761dd31 14163 unsigned int aligned_height;
79e53945 14164 int ret;
b321803d 14165 u32 pitch_limit, stride_alignment;
79e53945 14166
dd4916c5
DV		 14167 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14168
2a80eada
DV		 14169 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14170 /* Enforce that fb modifier and tiling mode match, but only for
14171 * X-tiled. This is needed for FBC. */
14172 if (!!(obj->tiling_mode == I915_TILING_X) !=
14173 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14174 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14175 return -EINVAL;
14176 }
14177 } else {
14178 if (obj->tiling_mode == I915_TILING_X)
14179 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14180 else if (obj->tiling_mode == I915_TILING_Y) {
14181 DRM_DEBUG("No Y tiling for legacy addfb\n");
14182 return -EINVAL;
14183 }
14184 }
14185
9a8f0a12
TU		 14186 /* Passed in modifier sanity checking. */
14187 switch (mode_cmd->modifier[0]) {
14188 case I915_FORMAT_MOD_Y_TILED:
14189 case I915_FORMAT_MOD_Yf_TILED:
14190 if (INTEL_INFO(dev)->gen < 9) {
14191 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14192 mode_cmd->modifier[0]);
14193 return -EINVAL;
14194 }
14195 case DRM_FORMAT_MOD_NONE:
14196 case I915_FORMAT_MOD_X_TILED:
14197 break;
14198 default:
c0f40428
JB		 14199 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14200 mode_cmd->modifier[0]);
57cd6508 14201 return -EINVAL;
c16ed4be 14202 }
57cd6508 14203
b321803d
DL		 14204 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14205 mode_cmd->pixel_format);
14206 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14207 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14208 mode_cmd->pitches[0], stride_alignment);
57cd6508 14209 return -EINVAL;
c16ed4be 14210 }
57cd6508 14211
b321803d
DL		 14212 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14213 mode_cmd->pixel_format);
a35cdaa0 14214 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14215 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14216 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14217 "tiled" : "linear",
a35cdaa0 14218 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14219 return -EINVAL;
c16ed4be 14220 }
5d7bd705 14221
2a80eada 14222 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14223 mode_cmd->pitches[0] != obj->stride) {
14224 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14225 mode_cmd->pitches[0], obj->stride);
5d7bd705 14226 return -EINVAL;
c16ed4be 14227 }
5d7bd705 14228
57779d06 14229 /* Reject formats not supported by any plane early. */
308e5bcb 14230 switch (mode_cmd->pixel_format) {
57779d06 14231 case DRM_FORMAT_C8:
04b3924d
VS		 14232 case DRM_FORMAT_RGB565:
14233 case DRM_FORMAT_XRGB8888:
14234 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14235 break;
14236 case DRM_FORMAT_XRGB1555:
c16ed4be 14237 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14238 DRM_DEBUG("unsupported pixel format: %s\n",
14239 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14240 return -EINVAL;
c16ed4be 14241 }
57779d06 14242 break;
57779d06 14243 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14244 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14245 DRM_DEBUG("unsupported pixel format: %s\n",
14246 drm_get_format_name(mode_cmd->pixel_format));
14247 return -EINVAL;
14248 }
14249 break;
14250 case DRM_FORMAT_XBGR8888:
04b3924d 14251 case DRM_FORMAT_XRGB2101010:
57779d06 14252 case DRM_FORMAT_XBGR2101010:
c16ed4be 14253 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14254 DRM_DEBUG("unsupported pixel format: %s\n",
14255 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14256 return -EINVAL;
c16ed4be 14257 }
b5626747 14258 break;
7531208b
DL		 14259 case DRM_FORMAT_ABGR2101010:
14260 if (!IS_VALLEYVIEW(dev)) {
14261 DRM_DEBUG("unsupported pixel format: %s\n",
14262 drm_get_format_name(mode_cmd->pixel_format));
14263 return -EINVAL;
14264 }
14265 break;
04b3924d
VS		 14266 case DRM_FORMAT_YUYV:
14267 case DRM_FORMAT_UYVY:
14268 case DRM_FORMAT_YVYU:
14269 case DRM_FORMAT_VYUY:
c16ed4be 14270 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14271 DRM_DEBUG("unsupported pixel format: %s\n",
14272 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14273 return -EINVAL;
c16ed4be 14274 }
57cd6508
CW		 14275 break;
14276 default:
4ee62c76
VS		 14277 DRM_DEBUG("unsupported pixel format: %s\n",
14278 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14279 return -EINVAL;
14280 }
14281
90f9a336
VS		 14282 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14283 if (mode_cmd->offsets[0] != 0)
14284 return -EINVAL;
14285
ec2c981e 14286 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14287 mode_cmd->pixel_format,
14288 mode_cmd->modifier[0]);
53155c0a
DV		 14289 /* FIXME drm helper for size checks (especially planar formats)? */
14290 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14291 return -EINVAL;
14292
c7d73f6a
DV		 14293 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14294 intel_fb->obj = obj;
80075d49 14295 intel_fb->obj->framebuffer_references++;
c7d73f6a 14296
79e53945
JB		 14297 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14298 if (ret) {
14299 DRM_ERROR("framebuffer init failed %d\n", ret);
14300 return ret;
14301 }
14302
79e53945
JB		 14303 return 0;
14304}
14305
79e53945
JB		 14306static struct drm_framebuffer *
14307intel_user_framebuffer_create(struct drm_device *dev,
14308 struct drm_file *filp,
308e5bcb 14309 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14310{
05394f39 14311 struct drm_i915_gem_object *obj;
79e53945 14312
308e5bcb
JB		 14313 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14314 mode_cmd->handles[0]));
c8725226 14315 if (&obj->base == NULL)
cce13ff7 14316 return ERR_PTR(-ENOENT);
79e53945 14317
d2dff872 14318 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14319}
14320
4520f53a 14321#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14322static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14323{
14324}
14325#endif
14326
79e53945 14327static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14328 .fb_create = intel_user_framebuffer_create,
0632fef6 14329 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14330 .atomic_check = intel_atomic_check,
14331 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14332 .atomic_state_alloc = intel_atomic_state_alloc,
14333 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14334};
14335
e70236a8
JB		 14336/* Set up chip specific display functions */
14337static void intel_init_display(struct drm_device *dev)
14338{
14339 struct drm_i915_private *dev_priv = dev->dev_private;
14340
ee9300bb
DV		 14341 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14342 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14343 else if (IS_CHERRYVIEW(dev))
14344 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14345 else if (IS_VALLEYVIEW(dev))
14346 dev_priv->display.find_dpll = vlv_find_best_dpll;
14347 else if (IS_PINEVIEW(dev))
14348 dev_priv->display.find_dpll = pnv_find_best_dpll;
14349 else
14350 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14351
bc8d7dff
DL		 14352 if (INTEL_INFO(dev)->gen >= 9) {
14353 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14354 dev_priv->display.get_initial_plane_config =
14355 skylake_get_initial_plane_config;
bc8d7dff
DL		 14356 dev_priv->display.crtc_compute_clock =
14357 haswell_crtc_compute_clock;
14358 dev_priv->display.crtc_enable = haswell_crtc_enable;
14359 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14360 dev_priv->display.update_primary_plane =
14361 skylake_update_primary_plane;
14362 } else if (HAS_DDI(dev)) {
0e8ffe1b 14363 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14364 dev_priv->display.get_initial_plane_config =
14365 ironlake_get_initial_plane_config;
797d0259
ACO		 14366 dev_priv->display.crtc_compute_clock =
14367 haswell_crtc_compute_clock;
4f771f10
PZ		 14368 dev_priv->display.crtc_enable = haswell_crtc_enable;
14369 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14370 dev_priv->display.update_primary_plane =
14371 ironlake_update_primary_plane;
09b4ddf9 14372 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14373 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14374 dev_priv->display.get_initial_plane_config =
14375 ironlake_get_initial_plane_config;
3fb37703
ACO		 14376 dev_priv->display.crtc_compute_clock =
14377 ironlake_crtc_compute_clock;
76e5a89c
DV		 14378 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14379 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14380 dev_priv->display.update_primary_plane =
14381 ironlake_update_primary_plane;
89b667f8
JB		 14382 } else if (IS_VALLEYVIEW(dev)) {
14383 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14384 dev_priv->display.get_initial_plane_config =
14385 i9xx_get_initial_plane_config;
d6dfee7a 14386 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14387 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14388 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14389 dev_priv->display.update_primary_plane =
14390 i9xx_update_primary_plane;
f564048e 14391 } else {
0e8ffe1b 14392 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14393 dev_priv->display.get_initial_plane_config =
14394 i9xx_get_initial_plane_config;
d6dfee7a 14395 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14396 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14397 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14398 dev_priv->display.update_primary_plane =
14399 i9xx_update_primary_plane;
f564048e 14400 }
e70236a8 14401
e70236a8 14402 /* Returns the core display clock speed */
1652d19e
VS		 14403 if (IS_SKYLAKE(dev))
14404 dev_priv->display.get_display_clock_speed =
14405 skylake_get_display_clock_speed;
acd3f3d3
BP		 14406 else if (IS_BROXTON(dev))
14407 dev_priv->display.get_display_clock_speed =
14408 broxton_get_display_clock_speed;
1652d19e
VS		 14409 else if (IS_BROADWELL(dev))
14410 dev_priv->display.get_display_clock_speed =
14411 broadwell_get_display_clock_speed;
14412 else if (IS_HASWELL(dev))
14413 dev_priv->display.get_display_clock_speed =
14414 haswell_get_display_clock_speed;
14415 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14416 dev_priv->display.get_display_clock_speed =
14417 valleyview_get_display_clock_speed;
b37a6434
VS		 14418 else if (IS_GEN5(dev))
14419 dev_priv->display.get_display_clock_speed =
14420 ilk_get_display_clock_speed;
a7c66cd8 14421 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14422 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14423 dev_priv->display.get_display_clock_speed =
14424 i945_get_display_clock_speed;
34edce2f
VS		 14425 else if (IS_GM45(dev))
14426 dev_priv->display.get_display_clock_speed =
14427 gm45_get_display_clock_speed;
14428 else if (IS_CRESTLINE(dev))
14429 dev_priv->display.get_display_clock_speed =
14430 i965gm_get_display_clock_speed;
14431 else if (IS_PINEVIEW(dev))
14432 dev_priv->display.get_display_clock_speed =
14433 pnv_get_display_clock_speed;
14434 else if (IS_G33(dev) || IS_G4X(dev))
14435 dev_priv->display.get_display_clock_speed =
14436 g33_get_display_clock_speed;
e70236a8
JB		 14437 else if (IS_I915G(dev))
14438 dev_priv->display.get_display_clock_speed =
14439 i915_get_display_clock_speed;
257a7ffc 14440 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14441 dev_priv->display.get_display_clock_speed =
14442 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14443 else if (IS_PINEVIEW(dev))
14444 dev_priv->display.get_display_clock_speed =
14445 pnv_get_display_clock_speed;
e70236a8
JB		 14446 else if (IS_I915GM(dev))
14447 dev_priv->display.get_display_clock_speed =
14448 i915gm_get_display_clock_speed;
14449 else if (IS_I865G(dev))
14450 dev_priv->display.get_display_clock_speed =
14451 i865_get_display_clock_speed;
f0f8a9ce 14452 else if (IS_I85X(dev))
e70236a8 14453 dev_priv->display.get_display_clock_speed =
1b1d2716 14454 i85x_get_display_clock_speed;
623e01e5
VS		 14455 else { /* 830 */
14456 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14457 dev_priv->display.get_display_clock_speed =
14458 i830_get_display_clock_speed;
623e01e5 14459 }
e70236a8 14460
7c10a2b5 14461 if (IS_GEN5(dev)) {
3bb11b53 14462 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14463 } else if (IS_GEN6(dev)) {
14464 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14465 } else if (IS_IVYBRIDGE(dev)) {
14466 /* FIXME: detect B0+ stepping and use auto training */
14467 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14468 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14469 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14470 if (IS_BROADWELL(dev)) {
14471 dev_priv->display.modeset_commit_cdclk =
14472 broadwell_modeset_commit_cdclk;
14473 dev_priv->display.modeset_calc_cdclk =
14474 broadwell_modeset_calc_cdclk;
14475 }
30a970c6 14476 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14477 dev_priv->display.modeset_commit_cdclk =
14478 valleyview_modeset_commit_cdclk;
14479 dev_priv->display.modeset_calc_cdclk =
14480 valleyview_modeset_calc_cdclk;
f8437dd1 14481 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14482 dev_priv->display.modeset_commit_cdclk =
14483 broxton_modeset_commit_cdclk;
14484 dev_priv->display.modeset_calc_cdclk =
14485 broxton_modeset_calc_cdclk;
e70236a8 14486 }
8c9f3aaf 14487
8c9f3aaf
JB		 14488 switch (INTEL_INFO(dev)->gen) {
14489 case 2:
14490 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14491 break;
14492
14493 case 3:
14494 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14495 break;
14496
14497 case 4:
14498 case 5:
14499 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14500 break;
14501
14502 case 6:
14503 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14504 break;
7c9017e5 14505 case 7:
4e0bbc31 14506 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14507 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14508 break;
830c81db 14509 case 9:
ba343e02
TU		 14510 /* Drop through - unsupported since execlist only. */
14511 default:
14512 /* Default just returns -ENODEV to indicate unsupported */
14513 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14514 }
7bd688cd
JN		 14515
14516 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14517
14518 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14519}
14520
b690e96c
JB		 14521/*
14522 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14523 * resume, or other times. This quirk makes sure that's the case for
14524 * affected systems.
14525 */
0206e353 14526static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14527{
14528 struct drm_i915_private *dev_priv = dev->dev_private;
14529
14530 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14531 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14532}
14533
b6b5d049
VS		 14534static void quirk_pipeb_force(struct drm_device *dev)
14535{
14536 struct drm_i915_private *dev_priv = dev->dev_private;
14537
14538 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14539 DRM_INFO("applying pipe b force quirk\n");
14540}
14541
435793df
KP		 14542/*
14543 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14544 */
14545static void quirk_ssc_force_disable(struct drm_device *dev)
14546{
14547 struct drm_i915_private *dev_priv = dev->dev_private;
14548 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14549 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14550}
14551
4dca20ef 14552/*
5a15ab5b
CE		 14553 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14554 * brightness value
4dca20ef
CE		 14555 */
14556static void quirk_invert_brightness(struct drm_device *dev)
14557{
14558 struct drm_i915_private *dev_priv = dev->dev_private;
14559 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14560 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14561}
14562
9c72cc6f
SD		 14563/* Some VBT's incorrectly indicate no backlight is present */
14564static void quirk_backlight_present(struct drm_device *dev)
14565{
14566 struct drm_i915_private *dev_priv = dev->dev_private;
14567 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14568 DRM_INFO("applying backlight present quirk\n");
14569}
14570
b690e96c
JB		 14571struct intel_quirk {
14572 int device;
14573 int subsystem_vendor;
14574 int subsystem_device;
14575 void (*hook)(struct drm_device *dev);
14576};
14577
5f85f176
EE		 14578/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14579struct intel_dmi_quirk {
14580 void (*hook)(struct drm_device *dev);
14581 const struct dmi_system_id (*dmi_id_list)[];
14582};
14583
14584static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14585{
14586 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14587 return 1;
14588}
14589
14590static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14591 {
14592 .dmi_id_list = &(const struct dmi_system_id[]) {
14593 {
14594 .callback = intel_dmi_reverse_brightness,
14595 .ident = "NCR Corporation",
14596 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14597 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14598 },
14599 },
14600 { } /* terminating entry */
14601 },
14602 .hook = quirk_invert_brightness,
14603 },
14604};
14605
c43b5634 14606static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14607 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14608 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14609
b690e96c
JB		 14610 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14611 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14612
5f080c0f
VS		 14613 /* 830 needs to leave pipe A & dpll A up */
14614 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14615
b6b5d049
VS		 14616 /* 830 needs to leave pipe B & dpll B up */
14617 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14618
435793df
KP		 14619 /* Lenovo U160 cannot use SSC on LVDS */
14620 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14621
14622 /* Sony Vaio Y cannot use SSC on LVDS */
14623 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14624
be505f64
AH		 14625 /* Acer Aspire 5734Z must invert backlight brightness */
14626 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14627
14628 /* Acer/eMachines G725 */
14629 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14630
14631 /* Acer/eMachines e725 */
14632 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14633
14634 /* Acer/Packard Bell NCL20 */
14635 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14636
14637 /* Acer Aspire 4736Z */
14638 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14639
14640 /* Acer Aspire 5336 */
14641 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14642
14643 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14644 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14645
dfb3d47b
SD		 14646 /* Acer C720 Chromebook (Core i3 4005U) */
14647 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14648
b2a9601c 14649 /* Apple Macbook 2,1 (Core 2 T7400) */
14650 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14651
d4967d8c
SD		 14652 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14653 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14654
14655 /* HP Chromebook 14 (Celeron 2955U) */
14656 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14657
14658 /* Dell Chromebook 11 */
14659 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14660};
14661
14662static void intel_init_quirks(struct drm_device *dev)
14663{
14664 struct pci_dev *d = dev->pdev;
14665 int i;
14666
14667 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14668 struct intel_quirk *q = &intel_quirks[i];
14669
14670 if (d->device == q->device &&
14671 (d->subsystem_vendor == q->subsystem_vendor ||
14672 q->subsystem_vendor == PCI_ANY_ID) &&
14673 (d->subsystem_device == q->subsystem_device ||
14674 q->subsystem_device == PCI_ANY_ID))
14675 q->hook(dev);
14676 }
5f85f176
EE		 14677 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14678 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14679 intel_dmi_quirks[i].hook(dev);
14680 }
b690e96c
JB		 14681}
14682
9cce37f4
JB		 14683/* Disable the VGA plane that we never use */
14684static void i915_disable_vga(struct drm_device *dev)
14685{
14686 struct drm_i915_private *dev_priv = dev->dev_private;
14687 u8 sr1;
766aa1c4 14688 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14689
2b37c616 14690 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14691 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14692 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14693 sr1 = inb(VGA_SR_DATA);
14694 outb(sr1 | 1<<5, VGA_SR_DATA);
14695 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14696 udelay(300);
14697
01f5a626 14698 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14699 POSTING_READ(vga_reg);
14700}
14701
f817586c
DV		 14702void intel_modeset_init_hw(struct drm_device *dev)
14703{
b6283055 14704 intel_update_cdclk(dev);
a8f78b58 14705 intel_prepare_ddi(dev);
f817586c 14706 intel_init_clock_gating(dev);
8090c6b9 14707 intel_enable_gt_powersave(dev);
f817586c
DV		 14708}
14709
79e53945
JB		 14710void intel_modeset_init(struct drm_device *dev)
14711{
652c393a 14712 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14713 int sprite, ret;
8cc87b75 14714 enum pipe pipe;
46f297fb 14715 struct intel_crtc *crtc;
79e53945
JB		 14716
14717 drm_mode_config_init(dev);
14718
14719 dev->mode_config.min_width = 0;
14720 dev->mode_config.min_height = 0;
14721
019d96cb
DA		 14722 dev->mode_config.preferred_depth = 24;
14723 dev->mode_config.prefer_shadow = 1;
14724
25bab385
TU		 14725 dev->mode_config.allow_fb_modifiers = true;
14726
e6ecefaa 14727 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14728
b690e96c
JB		 14729 intel_init_quirks(dev);
14730
1fa61106
ED		 14731 intel_init_pm(dev);
14732
e3c74757
BW		 14733 if (INTEL_INFO(dev)->num_pipes == 0)
14734 return;
14735
e70236a8 14736 intel_init_display(dev);
7c10a2b5 14737 intel_init_audio(dev);
e70236a8 14738
a6c45cf0
CW		 14739 if (IS_GEN2(dev)) {
14740 dev->mode_config.max_width = 2048;
14741 dev->mode_config.max_height = 2048;
14742 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14743 dev->mode_config.max_width = 4096;
14744 dev->mode_config.max_height = 4096;
79e53945 14745 } else {
a6c45cf0
CW		 14746 dev->mode_config.max_width = 8192;
14747 dev->mode_config.max_height = 8192;
79e53945 14748 }
068be561 14749
dc41c154
VS		 14750 if (IS_845G(dev) || IS_I865G(dev)) {
14751 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14752 dev->mode_config.cursor_height = 1023;
14753 } else if (IS_GEN2(dev)) {
068be561
DL		 14754 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14755 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14756 } else {
14757 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14758 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14759 }
14760
5d4545ae 14761 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14762
28c97730 14763 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14764 INTEL_INFO(dev)->num_pipes,
14765 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14766
055e393f 14767 for_each_pipe(dev_priv, pipe) {
8cc87b75 14768 intel_crtc_init(dev, pipe);
3bdcfc0c 14769 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14770 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14771 if (ret)
06da8da2 14772 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14773 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14774 }
79e53945
JB		 14775 }
14776
f42bb70d
JB		 14777 intel_init_dpio(dev);
14778
e72f9fbf 14779 intel_shared_dpll_init(dev);
ee7b9f93 14780
9cce37f4
JB		 14781 /* Just disable it once at startup */
14782 i915_disable_vga(dev);
79e53945 14783 intel_setup_outputs(dev);
11be49eb
CW		 14784
14785 /* Just in case the BIOS is doing something questionable. */
7733b49b 14786 intel_fbc_disable(dev_priv);
fa9fa083 14787
6e9f798d 14788 drm_modeset_lock_all(dev);
043e9bda 14789 intel_modeset_setup_hw_state(dev);
6e9f798d 14790 drm_modeset_unlock_all(dev);
46f297fb 14791
d3fcc808 14792 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14793 struct intel_initial_plane_config plane_config = {};
14794
46f297fb
JB		 14795 if (!crtc->active)
14796 continue;
14797
46f297fb 14798 /*
46f297fb
JB		 14799 * Note that reserving the BIOS fb up front prevents us
14800 * from stuffing other stolen allocations like the ring
14801 * on top. This prevents some ugliness at boot time, and
14802 * can even allow for smooth boot transitions if the BIOS
14803 * fb is large enough for the active pipe configuration.
14804 */
eeebeac5
ML		 14805 dev_priv->display.get_initial_plane_config(crtc,
14806 &plane_config);
14807
14808 /*
14809 * If the fb is shared between multiple heads, we'll
14810 * just get the first one.
14811 */
14812 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14813 }
2c7111db
CW		 14814}
14815
7fad798e
DV		 14816static void intel_enable_pipe_a(struct drm_device *dev)
14817{
14818 struct intel_connector *connector;
14819 struct drm_connector *crt = NULL;
14820 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14821 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14822
14823 /* We can't just switch on the pipe A, we need to set things up with a
14824 * proper mode and output configuration. As a gross hack, enable pipe A
14825 * by enabling the load detect pipe once. */
3a3371ff 14826 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14827 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14828 crt = &connector->base;
14829 break;
14830 }
14831 }
14832
14833 if (!crt)
14834 return;
14835
208bf9fd 14836 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14837 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14838}
14839
fa555837
DV		 14840static bool
14841intel_check_plane_mapping(struct intel_crtc *crtc)
14842{
7eb552ae
BW		 14843 struct drm_device *dev = crtc->base.dev;
14844 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14845 u32 reg, val;
14846
7eb552ae 14847 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14848 return true;
14849
14850 reg = DSPCNTR(!crtc->plane);
14851 val = I915_READ(reg);
14852
14853 if ((val & DISPLAY_PLANE_ENABLE) &&
14854 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14855 return false;
14856
14857 return true;
14858}
14859
24929352
DV		 14860static void intel_sanitize_crtc(struct intel_crtc *crtc)
14861{
14862 struct drm_device *dev = crtc->base.dev;
14863 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 14864 struct intel_encoder *encoder;
fa555837 14865 u32 reg;
b17d48e2 14866 bool enable;
24929352 14867
24929352 14868 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14869 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14870 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14871
d3eaf884 14872 /* restore vblank interrupts to correct state */
9625604c 14873 drm_crtc_vblank_reset(&crtc->base);
d297e103 14874 if (crtc->active) {
3a03dfb0 14875 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14876 update_scanline_offset(crtc);
9625604c
DV		 14877 drm_crtc_vblank_on(&crtc->base);
14878 }
d3eaf884 14879
24929352 14880 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14881 * disable the crtc (and hence change the state) if it is wrong. Note
14882 * that gen4+ has a fixed plane -> pipe mapping. */
14883 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14884 bool plane;
14885
24929352
DV		 14886 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14887 crtc->base.base.id);
14888
14889 /* Pipe has the wrong plane attached and the plane is active.
14890 * Temporarily change the plane mapping and disable everything
14891 * ... */
14892 plane = crtc->plane;
b70709a6 14893 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14894 crtc->plane = !plane;
b17d48e2 14895 intel_crtc_disable_noatomic(&crtc->base);
24929352 14896 crtc->plane = plane;
24929352 14897 }
24929352 14898
7fad798e
DV		 14899 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14900 crtc->pipe == PIPE_A && !crtc->active) {
14901 /* BIOS forgot to enable pipe A, this mostly happens after
14902 * resume. Force-enable the pipe to fix this, the update_dpms
14903 * call below we restore the pipe to the right state, but leave
14904 * the required bits on. */
14905 intel_enable_pipe_a(dev);
14906 }
14907
24929352
DV		 14908 /* Adjust the state of the output pipe according to whether we
14909 * have active connectors/encoders. */
b17d48e2 14910 enable = false;
873ffe69
ML		 14911 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14912 enable = true;
14913 break;
14914 }
24929352 14915
b17d48e2
ML		 14916 if (!enable)
14917 intel_crtc_disable_noatomic(&crtc->base);
24929352 14918
53d9f4e9 14919 if (crtc->active != crtc->base.state->active) {
24929352
DV		 14920
14921 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14922 * functions or because of calls to intel_crtc_disable_noatomic,
14923 * or because the pipe is force-enabled due to the
24929352
DV		 14924 * pipe A quirk. */
14925 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14926 crtc->base.base.id,
83d65738 14927 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14928 crtc->active ? "enabled" : "disabled");
14929
4be40c98 14930 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14931 crtc->base.state->active = crtc->active;
24929352
DV		 14932 crtc->base.enabled = crtc->active;
14933
14934 /* Because we only establish the connector -> encoder ->
14935 * crtc links if something is active, this means the
14936 * crtc is now deactivated. Break the links. connector
14937 * -> encoder links are only establish when things are
14938 * actually up, hence no need to break them. */
14939 WARN_ON(crtc->active);
14940
2d406bb0 14941 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14942 encoder->base.crtc = NULL;
24929352 14943 }
c5ab3bc0 14944
a3ed6aad 14945 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14946 /*
14947 * We start out with underrun reporting disabled to avoid races.
14948 * For correct bookkeeping mark this on active crtcs.
14949 *
c5ab3bc0
DV		 14950 * Also on gmch platforms we dont have any hardware bits to
14951 * disable the underrun reporting. Which means we need to start
14952 * out with underrun reporting disabled also on inactive pipes,
14953 * since otherwise we'll complain about the garbage we read when
14954 * e.g. coming up after runtime pm.
14955 *
4cc31489
DV		 14956 * No protection against concurrent access is required - at
14957 * worst a fifo underrun happens which also sets this to false.
14958 */
14959 crtc->cpu_fifo_underrun_disabled = true;
14960 crtc->pch_fifo_underrun_disabled = true;
14961 }
24929352
DV		 14962}
14963
14964static void intel_sanitize_encoder(struct intel_encoder *encoder)
14965{
14966 struct intel_connector *connector;
14967 struct drm_device *dev = encoder->base.dev;
873ffe69 14968 bool active = false;
24929352
DV		 14969
14970 /* We need to check both for a crtc link (meaning that the
14971 * encoder is active and trying to read from a pipe) and the
14972 * pipe itself being active. */
14973 bool has_active_crtc = encoder->base.crtc &&
14974 to_intel_crtc(encoder->base.crtc)->active;
14975
873ffe69
ML		 14976 for_each_intel_connector(dev, connector) {
14977 if (connector->base.encoder != &encoder->base)
14978 continue;
14979
14980 active = true;
14981 break;
14982 }
14983
14984 if (active && !has_active_crtc) {
24929352
DV		 14985 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14986 encoder->base.base.id,
8e329a03 14987 encoder->base.name);
24929352
DV		 14988
14989 /* Connector is active, but has no active pipe. This is
14990 * fallout from our resume register restoring. Disable
14991 * the encoder manually again. */
14992 if (encoder->base.crtc) {
14993 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14994 encoder->base.base.id,
8e329a03 14995 encoder->base.name);
24929352 14996 encoder->disable(encoder);
a62d1497
VS		 14997 if (encoder->post_disable)
14998 encoder->post_disable(encoder);
24929352 14999 }
7f1950fb 15000 encoder->base.crtc = NULL;
24929352
DV		 15001
15002 /* Inconsistent output/port/pipe state happens presumably due to
15003 * a bug in one of the get_hw_state functions. Or someplace else
15004 * in our code, like the register restore mess on resume. Clamp
15005 * things to off as a safer default. */
3a3371ff 15006 for_each_intel_connector(dev, connector) {
24929352
DV		 15007 if (connector->encoder != encoder)
15008 continue;
7f1950fb
EE		 15009 connector->base.dpms = DRM_MODE_DPMS_OFF;
15010 connector->base.encoder = NULL;
24929352
DV		 15011 }
15012 }
15013 /* Enabled encoders without active connectors will be fixed in
15014 * the crtc fixup. */
15015}
15016
04098753 15017void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15018{
15019 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15020 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15021
04098753
ID		 15022 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15023 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15024 i915_disable_vga(dev);
15025 }
15026}
15027
15028void i915_redisable_vga(struct drm_device *dev)
15029{
15030 struct drm_i915_private *dev_priv = dev->dev_private;
15031
8dc8a27c
PZ		 15032 /* This function can be called both from intel_modeset_setup_hw_state or
15033 * at a very early point in our resume sequence, where the power well
15034 * structures are not yet restored. Since this function is at a very
15035 * paranoid "someone might have enabled VGA while we were not looking"
15036 * level, just check if the power well is enabled instead of trying to
15037 * follow the "don't touch the power well if we don't need it" policy
15038 * the rest of the driver uses. */
f458ebbc 15039 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15040 return;
15041
04098753 15042 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15043}
15044
98ec7739
VS		 15045static bool primary_get_hw_state(struct intel_crtc *crtc)
15046{
15047 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15048
d032ffa0
ML		 15049 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15050}
15051
15052static void readout_plane_state(struct intel_crtc *crtc,
15053 struct intel_crtc_state *crtc_state)
15054{
15055 struct intel_plane *p;
4cf0ebbd 15056 struct intel_plane_state *plane_state;
d032ffa0
ML		 15057 bool active = crtc_state->base.active;
15058
d032ffa0 15059 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15060 if (crtc->pipe != p->pipe)
15061 continue;
15062
4cf0ebbd 15063 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15064
4cf0ebbd
ML		 15065 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15066 plane_state->visible = primary_get_hw_state(crtc);
15067 else {
15068 if (active)
15069 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15070
4cf0ebbd 15071 plane_state->visible = false;
d032ffa0
ML		 15072 }
15073 }
98ec7739
VS		 15074}
15075
30e984df 15076static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15077{
15078 struct drm_i915_private *dev_priv = dev->dev_private;
15079 enum pipe pipe;
24929352
DV		 15080 struct intel_crtc *crtc;
15081 struct intel_encoder *encoder;
15082 struct intel_connector *connector;
5358901f 15083 int i;
24929352 15084
d3fcc808 15085 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15086 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15087 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15088 crtc->config->base.crtc = &crtc->base;
3b117c8f 15089
0e8ffe1b 15090 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15091 crtc->config);
24929352 15092
49d6fa21 15093 crtc->base.state->active = crtc->active;
24929352 15094 crtc->base.enabled = crtc->active;
b70709a6 15095
5c1e3426
ML		 15096 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15097 if (crtc->base.state->active) {
15098 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15099 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15100 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15101
15102 /*
15103 * The initial mode needs to be set in order to keep
15104 * the atomic core happy. It wants a valid mode if the
15105 * crtc's enabled, so we do the above call.
15106 *
15107 * At this point some state updated by the connectors
15108 * in their ->detect() callback has not run yet, so
15109 * no recalculation can be done yet.
15110 *
15111 * Even if we could do a recalculation and modeset
15112 * right now it would cause a double modeset if
15113 * fbdev or userspace chooses a different initial mode.
15114 *
5c1e3426
ML		 15115 * If that happens, someone indicated they wanted a
15116 * mode change, which means it's safe to do a full
15117 * recalculation.
15118 */
1ed51de9 15119 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15120 }
15121
15122 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15123 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15124
15125 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15126 crtc->base.base.id,
15127 crtc->active ? "enabled" : "disabled");
15128 }
15129
5358901f
DV		 15130 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15131 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15132
3e369b76
ACO		 15133 pll->on = pll->get_hw_state(dev_priv, pll,
15134 &pll->config.hw_state);
5358901f 15135 pll->active = 0;
3e369b76 15136 pll->config.crtc_mask = 0;
d3fcc808 15137 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15138 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15139 pll->active++;
3e369b76 15140 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15141 }
5358901f 15142 }
5358901f 15143
1e6f2ddc 15144 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15145 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15146
3e369b76 15147 if (pll->config.crtc_mask)
bd2bb1b9 15148 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15149 }
15150
b2784e15 15151 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15152 pipe = 0;
15153
15154 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15155 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15156 encoder->base.crtc = &crtc->base;
6e3c9717 15157 encoder->get_config(encoder, crtc->config);
24929352
DV		 15158 } else {
15159 encoder->base.crtc = NULL;
15160 }
15161
6f2bcceb 15162 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15163 encoder->base.base.id,
8e329a03 15164 encoder->base.name,
24929352 15165 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15166 pipe_name(pipe));
24929352
DV		 15167 }
15168
3a3371ff 15169 for_each_intel_connector(dev, connector) {
24929352
DV		 15170 if (connector->get_hw_state(connector)) {
15171 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15172 connector->base.encoder = &connector->encoder->base;
15173 } else {
15174 connector->base.dpms = DRM_MODE_DPMS_OFF;
15175 connector->base.encoder = NULL;
15176 }
15177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15178 connector->base.base.id,
c23cc417 15179 connector->base.name,
24929352
DV		 15180 connector->base.encoder ? "enabled" : "disabled");
15181 }
30e984df
DV		 15182}
15183
043e9bda
ML		 15184/* Scan out the current hw modeset state,
15185 * and sanitizes it to the current state
15186 */
15187static void
15188intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15189{
15190 struct drm_i915_private *dev_priv = dev->dev_private;
15191 enum pipe pipe;
30e984df
DV		 15192 struct intel_crtc *crtc;
15193 struct intel_encoder *encoder;
35c95375 15194 int i;
30e984df
DV		 15195
15196 intel_modeset_readout_hw_state(dev);
24929352
DV		 15197
15198 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15199 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15200 intel_sanitize_encoder(encoder);
15201 }
15202
055e393f 15203 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15204 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15205 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15206 intel_dump_pipe_config(crtc, crtc->config,
15207 "[setup_hw_state]");
24929352 15208 }
9a935856 15209
d29b2f9d
ACO		 15210 intel_modeset_update_connector_atomic_state(dev);
15211
35c95375
DV		 15212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15213 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15214
15215 if (!pll->on || pll->active)
15216 continue;
15217
15218 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15219
15220 pll->disable(dev_priv, pll);
15221 pll->on = false;
15222 }
15223
26e1fe4f 15224 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15225 vlv_wm_get_hw_state(dev);
15226 else if (IS_GEN9(dev))
3078999f
PB		 15227 skl_wm_get_hw_state(dev);
15228 else if (HAS_PCH_SPLIT(dev))
243e6a44 15229 ilk_wm_get_hw_state(dev);
292b990e
ML		 15230
15231 for_each_intel_crtc(dev, crtc) {
15232 unsigned long put_domains;
15233
15234 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15235 if (WARN_ON(put_domains))
15236 modeset_put_power_domains(dev_priv, put_domains);
15237 }
15238 intel_display_set_init_power(dev_priv, false);
043e9bda 15239}
7d0bc1ea 15240
043e9bda
ML		 15241void intel_display_resume(struct drm_device *dev)
15242{
15243 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15244 struct intel_connector *conn;
15245 struct intel_plane *plane;
15246 struct drm_crtc *crtc;
15247 int ret;
f30da187 15248
043e9bda
ML		 15249 if (!state)
15250 return;
15251
15252 state->acquire_ctx = dev->mode_config.acquire_ctx;
15253
15254 /* preserve complete old state, including dpll */
15255 intel_atomic_get_shared_dpll_state(state);
15256
15257 for_each_crtc(dev, crtc) {
15258 struct drm_crtc_state *crtc_state =
15259 drm_atomic_get_crtc_state(state, crtc);
15260
15261 ret = PTR_ERR_OR_ZERO(crtc_state);
15262 if (ret)
15263 goto err;
15264
15265 /* force a restore */
15266 crtc_state->mode_changed = true;
45e2b5f6 15267 }
8af6cf88 15268
043e9bda
ML		 15269 for_each_intel_plane(dev, plane) {
15270 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15271 if (ret)
15272 goto err;
15273 }
15274
15275 for_each_intel_connector(dev, conn) {
15276 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15277 if (ret)
15278 goto err;
15279 }
15280
15281 intel_modeset_setup_hw_state(dev);
15282
15283 i915_redisable_vga(dev);
74c090b1 15284 ret = drm_atomic_commit(state);
043e9bda
ML		 15285 if (!ret)
15286 return;
15287
15288err:
15289 DRM_ERROR("Restoring old state failed with %i\n", ret);
15290 drm_atomic_state_free(state);
2c7111db
CW		 15291}
15292
15293void intel_modeset_gem_init(struct drm_device *dev)
15294{
92122789 15295 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15296 struct drm_crtc *c;
2ff8fde1 15297 struct drm_i915_gem_object *obj;
e0d6149b 15298 int ret;
484b41dd 15299
ae48434c
ID		 15300 mutex_lock(&dev->struct_mutex);
15301 intel_init_gt_powersave(dev);
15302 mutex_unlock(&dev->struct_mutex);
15303
92122789
JB		 15304 /*
15305 * There may be no VBT; and if the BIOS enabled SSC we can
15306 * just keep using it to avoid unnecessary flicker. Whereas if the
15307 * BIOS isn't using it, don't assume it will work even if the VBT
15308 * indicates as much.
15309 */
15310 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15311 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15312 DREF_SSC1_ENABLE);
15313
1833b134 15314 intel_modeset_init_hw(dev);
02e792fb
DV		 15315
15316 intel_setup_overlay(dev);
484b41dd
JB		 15317
15318 /*
15319 * Make sure any fbs we allocated at startup are properly
15320 * pinned & fenced. When we do the allocation it's too early
15321 * for this.
15322 */
70e1e0ec 15323 for_each_crtc(dev, c) {
2ff8fde1
MR		 15324 obj = intel_fb_obj(c->primary->fb);
15325 if (obj == NULL)
484b41dd
JB		 15326 continue;
15327
e0d6149b
TU		 15328 mutex_lock(&dev->struct_mutex);
15329 ret = intel_pin_and_fence_fb_obj(c->primary,
15330 c->primary->fb,
15331 c->primary->state,
91af127f 15332 NULL, NULL);
e0d6149b
TU		 15333 mutex_unlock(&dev->struct_mutex);
15334 if (ret) {
484b41dd
JB		 15335 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15336 to_intel_crtc(c)->pipe);
66e514c1
DA		 15337 drm_framebuffer_unreference(c->primary->fb);
15338 c->primary->fb = NULL;
36750f28 15339 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15340 update_state_fb(c->primary);
36750f28 15341 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15342 }
15343 }
0962c3c9
VS		 15344
15345 intel_backlight_register(dev);
79e53945
JB		 15346}
15347
4932e2c3
ID		 15348void intel_connector_unregister(struct intel_connector *intel_connector)
15349{
15350 struct drm_connector *connector = &intel_connector->base;
15351
15352 intel_panel_destroy_backlight(connector);
34ea3d38 15353 drm_connector_unregister(connector);
4932e2c3
ID		 15354}
15355
79e53945
JB		 15356void intel_modeset_cleanup(struct drm_device *dev)
15357{
652c393a 15358 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15359 struct drm_connector *connector;
652c393a 15360
2eb5252e
ID		 15361 intel_disable_gt_powersave(dev);
15362
0962c3c9
VS		 15363 intel_backlight_unregister(dev);
15364
fd0c0642
DV		 15365 /*
15366 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15367 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15368 * experience fancy races otherwise.
15369 */
2aeb7d3a 15370 intel_irq_uninstall(dev_priv);
eb21b92b 15371
fd0c0642
DV		 15372 /*
15373 * Due to the hpd irq storm handling the hotplug work can re-arm the
15374 * poll handlers. Hence disable polling after hpd handling is shut down.
15375 */
f87ea761 15376 drm_kms_helper_poll_fini(dev);
fd0c0642 15377
723bfd70
JB		 15378 intel_unregister_dsm_handler();
15379
7733b49b 15380 intel_fbc_disable(dev_priv);
69341a5e 15381
1630fe75
CW		 15382 /* flush any delayed tasks or pending work */
15383 flush_scheduled_work();
15384
db31af1d
JN		 15385 /* destroy the backlight and sysfs files before encoders/connectors */
15386 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15387 struct intel_connector *intel_connector;
15388
15389 intel_connector = to_intel_connector(connector);
15390 intel_connector->unregister(intel_connector);
db31af1d 15391 }
d9255d57 15392
79e53945 15393 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15394
15395 intel_cleanup_overlay(dev);
ae48434c
ID		 15396
15397 mutex_lock(&dev->struct_mutex);
15398 intel_cleanup_gt_powersave(dev);
15399 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15400}
15401
f1c79df3
ZW		 15402/*
15403 * Return which encoder is currently attached for connector.
15404 */
df0e9248 15405struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15406{
df0e9248
CW		 15407 return &intel_attached_encoder(connector)->base;
15408}
f1c79df3 15409
df0e9248
CW		 15410void intel_connector_attach_encoder(struct intel_connector *connector,
15411 struct intel_encoder *encoder)
15412{
15413 connector->encoder = encoder;
15414 drm_mode_connector_attach_encoder(&connector->base,
15415 &encoder->base);
79e53945 15416}
28d52043
DA		 15417
15418/*
15419 * set vga decode state - true == enable VGA decode
15420 */
15421int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15422{
15423 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15424 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15425 u16 gmch_ctrl;
15426
75fa041d
CW		 15427 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15428 DRM_ERROR("failed to read control word\n");
15429 return -EIO;
15430 }
15431
c0cc8a55
CW		 15432 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15433 return 0;
15434
28d52043
DA		 15435 if (state)
15436 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15437 else
15438 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15439
15440 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15441 DRM_ERROR("failed to write control word\n");
15442 return -EIO;
15443 }
15444
28d52043
DA		 15445 return 0;
15446}
c4a1d9e4 15447
c4a1d9e4 15448struct intel_display_error_state {
ff57f1b0
PZ		 15449
15450 u32 power_well_driver;
15451
63b66e5b
CW		 15452 int num_transcoders;
15453
c4a1d9e4
CW		 15454 struct intel_cursor_error_state {
15455 u32 control;
15456 u32 position;
15457 u32 base;
15458 u32 size;
52331309 15459 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15460
15461 struct intel_pipe_error_state {
ddf9c536 15462 bool power_domain_on;
c4a1d9e4 15463 u32 source;
f301b1e1 15464 u32 stat;
52331309 15465 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15466
15467 struct intel_plane_error_state {
15468 u32 control;
15469 u32 stride;
15470 u32 size;
15471 u32 pos;
15472 u32 addr;
15473 u32 surface;
15474 u32 tile_offset;
52331309 15475 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15476
15477 struct intel_transcoder_error_state {
ddf9c536 15478 bool power_domain_on;
63b66e5b
CW		 15479 enum transcoder cpu_transcoder;
15480
15481 u32 conf;
15482
15483 u32 htotal;
15484 u32 hblank;
15485 u32 hsync;
15486 u32 vtotal;
15487 u32 vblank;
15488 u32 vsync;
15489 } transcoder[4];
c4a1d9e4
CW		 15490};
15491
15492struct intel_display_error_state *
15493intel_display_capture_error_state(struct drm_device *dev)
15494{
fbee40df 15495 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15496 struct intel_display_error_state *error;
63b66e5b
CW		 15497 int transcoders[] = {
15498 TRANSCODER_A,
15499 TRANSCODER_B,
15500 TRANSCODER_C,
15501 TRANSCODER_EDP,
15502 };
c4a1d9e4
CW		 15503 int i;
15504
63b66e5b
CW		 15505 if (INTEL_INFO(dev)->num_pipes == 0)
15506 return NULL;
15507
9d1cb914 15508 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15509 if (error == NULL)
15510 return NULL;
15511
190be112 15512 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15513 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15514
055e393f 15515 for_each_pipe(dev_priv, i) {
ddf9c536 15516 error->pipe[i].power_domain_on =
f458ebbc
DV		 15517 __intel_display_power_is_enabled(dev_priv,
15518 POWER_DOMAIN_PIPE(i));
ddf9c536 15519 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15520 continue;
15521
5efb3e28
VS		 15522 error->cursor[i].control = I915_READ(CURCNTR(i));
15523 error->cursor[i].position = I915_READ(CURPOS(i));
15524 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15525
15526 error->plane[i].control = I915_READ(DSPCNTR(i));
15527 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15528 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15529 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15530 error->plane[i].pos = I915_READ(DSPPOS(i));
15531 }
ca291363
PZ		 15532 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15533 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15534 if (INTEL_INFO(dev)->gen >= 4) {
15535 error->plane[i].surface = I915_READ(DSPSURF(i));
15536 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15537 }
15538
c4a1d9e4 15539 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15540
3abfce77 15541 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15542 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15543 }
15544
15545 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15546 if (HAS_DDI(dev_priv->dev))
15547 error->num_transcoders++; /* Account for eDP. */
15548
15549 for (i = 0; i < error->num_transcoders; i++) {
15550 enum transcoder cpu_transcoder = transcoders[i];
15551
ddf9c536 15552 error->transcoder[i].power_domain_on =
f458ebbc 15553 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15554 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15555 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15556 continue;
15557
63b66e5b
CW		 15558 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15559
15560 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15561 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15562 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15563 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15564 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15565 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15566 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15567 }
15568
15569 return error;
15570}
15571
edc3d884
MK		 15572#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15573
c4a1d9e4 15574void
edc3d884 15575intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15576 struct drm_device *dev,
15577 struct intel_display_error_state *error)
15578{
055e393f 15579 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15580 int i;
15581
63b66e5b
CW		 15582 if (!error)
15583 return;
15584
edc3d884 15585 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15586 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15587 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15588 error->power_well_driver);
055e393f 15589 for_each_pipe(dev_priv, i) {
edc3d884 15590 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15591 err_printf(m, " Power: %s\n",
15592 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15593 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15594 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15595
15596 err_printf(m, "Plane [%d]:\n", i);
15597 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15598 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15599 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15600 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15601 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15602 }
4b71a570 15603 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15604 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15605 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15606 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15607 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15608 }
15609
edc3d884
MK		 15610 err_printf(m, "Cursor [%d]:\n", i);
15611 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15612 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15613 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15614 }
63b66e5b
CW		 15615
15616 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15617 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15618 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15619 err_printf(m, " Power: %s\n",
15620 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15621 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15622 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15623 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15624 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15625 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15626 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15627 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15628 }
c4a1d9e4 15629}
e2fcdaa9
VS		 15630
15631void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15632{
15633 struct intel_crtc *crtc;
15634
15635 for_each_intel_crtc(dev, crtc) {
15636 struct intel_unpin_work *work;
e2fcdaa9 15637
5e2d7afc 15638 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15639
15640 work = crtc->unpin_work;
15641
15642 if (work && work->event &&
15643 work->event->base.file_priv == file) {
15644 kfree(work->event);
15645 work->event = NULL;
15646 }
15647
5e2d7afc 15648 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15649 }
15650}
Linux kernel - Deliverables
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