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drm/i915/skl: Adding DDI_E power well domain
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB		 89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV		 93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
5ab7b0b7
ID		 401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
e6292556 404 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
cdba954e
ACO		 413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
fc596660 416 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 417}
418
e0638cdf
PZ		 419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
4093561b 422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 423{
409ee761 424 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 425 struct intel_encoder *encoder;
426
409ee761 427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
d0737e1d
ACO		 434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
a93e255f
ACO		 440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
d0737e1d 442{
a93e255f 443 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 444 struct drm_connector *connector;
a93e255f 445 struct drm_connector_state *connector_state;
d0737e1d 446 struct intel_encoder *encoder;
a93e255f
ACO		 447 int i, num_connectors = 0;
448
da3ced29 449 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
d0737e1d 454
a93e255f
ACO		 455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
d0737e1d 457 return true;
a93e255f
ACO		 458 }
459
460 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 461
462 return false;
463}
464
a93e255f
ACO		 465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 467{
a93e255f 468 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 469 const intel_limit_t *limit;
b91ad0ec 470
a93e255f 471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 472 if (intel_is_dual_link_lvds(dev)) {
1b894b59 473 if (refclk == 100000)
b91ad0ec
ZW		 474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
c6bb3538 483 } else
b91ad0ec 484 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 485
486 return limit;
487}
488
a93e255f
ACO		 489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 491{
a93e255f 492 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 493 const intel_limit_t *limit;
494
a93e255f 495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 496 if (intel_is_dual_link_lvds(dev))
e4b36699 497 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 498 else
e4b36699 499 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 502 limit = &intel_limits_g4x_hdmi;
a93e255f 503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 504 limit = &intel_limits_g4x_sdvo;
044c7c41 505 } else /* The option is for other outputs */
e4b36699 506 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 507
508 return limit;
509}
510
a93e255f
ACO		 511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 513{
a93e255f 514 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 515 const intel_limit_t *limit;
516
5ab7b0b7
ID		 517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
a93e255f 520 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 521 else if (IS_G4X(dev)) {
a93e255f 522 limit = intel_g4x_limit(crtc_state);
f2b115e6 523 } else if (IS_PINEVIEW(dev)) {
a93e255f 524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 525 limit = &intel_limits_pineview_lvds;
2177832f 526 else
f2b115e6 527 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
a0c4da24 530 } else if (IS_VALLEYVIEW(dev)) {
dc730512 531 limit = &intel_limits_vlv;
a6c45cf0 532 } else if (!IS_GEN2(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
79e53945 537 } else {
a93e255f 538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 539 limit = &intel_limits_i8xx_lvds;
a93e255f 540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 541 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 542 else
543 limit = &intel_limits_i8xx_dac;
79e53945
JB		 544 }
545 return limit;
546}
547
dccbea3b
ID		 548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
f2b115e6 556/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 558{
2177832f
SL		 559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
ed5ca77e 561 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 562 return 0;
fb03ac01
VS		 563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 565
566 return clock->dot;
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
dccbea3b 574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 579 return 0;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 582
583 return clock->dot;
79e53945
JB		 584}
585
dccbea3b 586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 591 return 0;
589eca67
ID		 592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 594
595 return clock->dot / 5;
589eca67
ID		 596}
597
dccbea3b 598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 603 return 0;
ef9348c8
CML		 604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 607
608 return clock->dot / 5;
ef9348c8
CML		 609}
610
7c04d1d9 611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
1b894b59
CW		 617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
79e53945 620{
f01b7962
VS		 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 624 INTELPllInvalid("p1 out of range\n");
79e53945 625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 626 INTELPllInvalid("m2 out of range\n");
79e53945 627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 628 INTELPllInvalid("m1 out of range\n");
f01b7962 629
5ab7b0b7 630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
5ab7b0b7 634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
79e53945 641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 642 INTELPllInvalid("vco out of range\n");
79e53945
JB		 643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 647 INTELPllInvalid("dot out of range\n");
79e53945
JB		 648
649 return true;
650}
651
3b1429d9
VS		 652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
79e53945 656{
3b1429d9 657 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 658
a93e255f 659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 660 /*
a210b028
DV		 661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
79e53945 664 */
1974cad0 665 if (intel_is_dual_link_lvds(dev))
3b1429d9 666 return limit->p2.p2_fast;
79e53945 667 else
3b1429d9 668 return limit->p2.p2_slow;
79e53945
JB		 669 } else {
670 if (target < limit->p2.dot_limit)
3b1429d9 671 return limit->p2.p2_slow;
79e53945 672 else
3b1429d9 673 return limit->p2.p2_fast;
79e53945 674 }
3b1429d9
VS		 675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
79e53945 686
0206e353 687 memset(best_clock, 0, sizeof(*best_clock));
79e53945 688
3b1429d9
VS		 689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 695 if (clock.m2 >= clock.m1)
42158660
ZY		 696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 701 int this_err;
702
dccbea3b 703 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
a93e255f
ACO		 725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
79e53945 729{
3b1429d9 730 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 731 intel_clock_t clock;
79e53945
JB		 732 int err = target;
733
0206e353 734 memset(best_clock, 0, sizeof(*best_clock));
79e53945 735
3b1429d9
VS		 736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
42158660
ZY		 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 746 int this_err;
747
dccbea3b 748 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
79e53945 751 continue;
cec2f356
SP		 752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
79e53945
JB		 755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
d4906093 769static bool
a93e255f
ACO		 770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
d4906093 774{
3b1429d9 775 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 776 intel_clock_t clock;
777 int max_n;
3b1429d9 778 bool found = false;
6ba770dc
AJ		 779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 781
782 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
d4906093 786 max_n = limit->n.max;
f77f13e2 787 /* based on hardware requirement, prefer smaller n to precision */
d4906093 788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 789 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
dccbea3b 798 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
d4906093 801 continue;
1b894b59
CW		 802
803 this_err = abs(clock.dot - target);
d4906093
ML		 804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
2c07245f
ZW		 814 return found;
815}
816
d5dd62bd
ID		 817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
9ca3ba01
ID		 827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
24be4e46
ID		 837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
d5dd62bd
ID		 840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
a0c4da24 857static bool
a93e255f
ACO		 858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
a0c4da24 862{
a93e255f 863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 864 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 865 intel_clock_t clock;
69e4f900 866 unsigned int bestppm = 1000000;
27e639bf
VS		 867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 869 bool found = false;
a0c4da24 870
6b4bf1c4
VS		 871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 874
875 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 880 clock.p = clock.p1 * clock.p2;
a0c4da24 881 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 883 unsigned int ppm;
69e4f900 884
6b4bf1c4
VS		 885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
dccbea3b 888 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 889
f01b7962
VS		 890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
43b0ac53
VS		 892 continue;
893
d5dd62bd
ID		 894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
6b4bf1c4 899
d5dd62bd
ID		 900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
a0c4da24
JB		 903 }
904 }
905 }
906 }
a0c4da24 907
49e497ef 908 return found;
a0c4da24 909}
a4fc5ed6 910
ef9348c8 911static bool
a93e255f
ACO		 912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
a93e255f 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 918 struct drm_device *dev = crtc->base.dev;
9ca3ba01 919 unsigned int best_error_ppm;
ef9348c8
CML		 920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 925 best_error_ppm = 1000000;
ef9348c8
CML		 926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 939 unsigned int error_ppm;
ef9348c8
CML		 940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
dccbea3b 951 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
9ca3ba01
ID		 956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
ef9348c8
CML		 963 }
964 }
965
966 return found;
967}
968
5ab7b0b7
ID		 969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
20ddf665
VS		 978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
241bfc38 985 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 986 * as Haswell has gained clock readout/fastboot support.
987 *
66e514c1 988 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 989 * properly reconstruct framebuffers.
c3d1f436
MR		 990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
20ddf665 994 */
c3d1f436 995 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 996 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 997}
998
a5c961d1
PZ		 999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
6e3c9717 1005 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1006}
1007
fbf49ea2
VS		 1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1021 msleep(5);
fbf49ea2
VS		 1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
ab7ad7f6
KP		 1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1029 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
ab7ad7f6
KP		 1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
58e10eb9 1041 *
9d0498a2 1042 */
575f7ab7 1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1044{
575f7ab7 1045 struct drm_device *dev = crtc->base.dev;
9d0498a2 1046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1048 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1051 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1052
1053 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
284637d9 1056 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1057 } else {
ab7ad7f6 1058 /* Wait for the display line to settle */
fbf49ea2 1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 }
79e53945
JB		 1062}
1063
b0ea7d37
DL		 1064/*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073{
1074 u32 bit;
1075
c36346e3 1076 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1077 switch (port->port) {
c36346e3
DL		 1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
eba905b2 1091 switch (port->port) {
c36346e3
DL		 1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
26951caf
XZ		 1101 case PORT_E:
1102 bit = SDE_PORTE_HOTPLUG_SPT;
1103 break;
c36346e3
DL		 1104 default:
1105 return true;
1106 }
b0ea7d37
DL		 1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110}
1111
b24e7179
JB		 1112static const char *state_string(bool enabled)
1113{
1114 return enabled ? "on" : "off";
1115}
1116
1117/* Only for pre-ILK configs */
55607e8a
DV		 1118void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
b24e7179
JB		 1120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1128 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131}
b24e7179 1132
23538ef1
JN		 1133/* XXX: the dsi pll is shared between MIPI DSI ports */
1134static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135{
1136 u32 val;
1137 bool cur_state;
1138
a580516d 1139 mutex_lock(&dev_priv->sb_lock);
23538ef1 1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1141 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1142
1143 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1144 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147}
1148#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
55607e8a 1151struct intel_shared_dpll *
e2b78267
DV		 1152intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153{
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
6e3c9717 1156 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1157 return NULL;
1158
6e3c9717 1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1160}
1161
040484af 1162/* For ILK+ */
55607e8a
DV		 1163void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
040484af 1166{
040484af 1167 bool cur_state;
5358901f 1168 struct intel_dpll_hw_state hw_state;
040484af 1169
92b27b08 1170 if (WARN (!pll,
46edb027 1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1172 return;
ee7b9f93 1173
5358901f 1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1175 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
040484af 1178}
040484af
JB		 1179
1180static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182{
1183 int reg;
1184 u32 val;
1185 bool cur_state;
ad80a810
PZ		 1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
040484af 1188
affa9354
PZ		 1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
ad80a810 1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1192 val = I915_READ(reg);
ad80a810 1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
e2c719b7 1199 I915_STATE_WARN(cur_state != state,
040484af
JB		 1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202}
1203#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208{
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
d63fa0dc
PZ		 1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1216 I915_STATE_WARN(cur_state != state,
040484af
JB		 1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219}
1220#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225{
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
3d13ef2e 1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1231 return;
1232
bf507ef7 1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1234 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1235 return;
1236
040484af
JB		 1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
e2c719b7 1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1240}
1241
55607e8a
DV		 1242void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
040484af
JB		 1244{
1245 int reg;
1246 u32 val;
55607e8a 1247 bool cur_state;
040484af
JB		 1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
55607e8a 1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1252 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
040484af
JB		 1255}
1256
b680c37a
DV		 1257void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
ea0760cf 1259{
bedd4dba
JN		 1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
ea0760cf
JB		 1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
0de3b485 1264 bool locked = true;
ea0760cf 1265
bedd4dba
JN		 1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
ea0760cf 1272 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
ea0760cf
JB		 1283 } else {
1284 pp_reg = PP_CONTROL;
bedd4dba
JN		 1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
ea0760cf
JB		 1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1292 locked = false;
1293
e2c719b7 1294 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1295 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1296 pipe_name(pipe));
ea0760cf
JB		 1297}
1298
93ce0ba6
JN		 1299static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301{
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
d9d82081 1305 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1307 else
5efb3e28 1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1309
e2c719b7 1310 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313}
1314#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
b840d907
JB		 1317void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
b24e7179
JB		 1319{
1320 int reg;
1321 u32 val;
63d7bbe9 1322 bool cur_state;
702e7a56
PZ		 1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
b24e7179 1325
b6b5d049
VS		 1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1329 state = true;
1330
f458ebbc 1331 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
e2c719b7 1340 I915_STATE_WARN(cur_state != state,
63d7bbe9 1341 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1342 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1343}
1344
931872fc
CW		 1345static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
b24e7179
JB		 1347{
1348 int reg;
1349 u32 val;
931872fc 1350 bool cur_state;
b24e7179
JB		 1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
931872fc 1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1355 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1358}
1359
931872fc
CW		 1360#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
b24e7179
JB		 1363static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365{
653e1026 1366 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
653e1026
VS		 1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
e2c719b7 1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
19ec1358 1378 return;
28c05794 1379 }
19ec1358 1380
b24e7179 1381 /* Need to check both planes against the pipe */
055e393f 1382 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1390 }
1391}
1392
19332d7a
JB		 1393static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395{
20674eef 1396 struct drm_device *dev = dev_priv->dev;
1fe47785 1397 int reg, sprite;
19332d7a
JB		 1398 u32 val;
1399
7feb8b88 1400 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1401 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1402 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1408 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1409 reg = SPCNTR(pipe, sprite);
20674eef 1410 val = I915_READ(reg);
e2c719b7 1411 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1413 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
19332d7a 1417 val = I915_READ(reg);
e2c719b7 1418 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
19332d7a 1423 val = I915_READ(reg);
e2c719b7 1424 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1426 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1427 }
1428}
1429
08c71e5e
VS		 1430static void assert_vblank_disabled(struct drm_crtc *crtc)
1431{
e2c719b7 1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1433 drm_crtc_vblank_put(crtc);
1434}
1435
89eff4be 1436static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1437{
1438 u32 val;
1439 bool enabled;
1440
e2c719b7 1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1442
92f2584a
JB		 1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1447}
1448
ab9412ba
DV		 1449static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
92f2584a
JB		 1451{
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
ab9412ba 1456 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1459 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
92f2584a
JB		 1462}
1463
4e634389
KP		 1464static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1466{
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
44f37d1f
CML		 1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
f0575e92
KP		 1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483}
1484
1519b995
KP		 1485static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487{
dc0fa718 1488 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1493 return false;
44f37d1f
CML		 1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1519b995 1497 } else {
dc0fa718 1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1499 return false;
1500 }
1501 return true;
1502}
1503
1504static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506{
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522{
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
291906f1 1535static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1536 enum pipe pipe, int reg, u32 port_sel)
291906f1 1537{
47a05eca 1538 u32 val = I915_READ(reg);
e2c719b7 1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1541 reg, pipe_name(pipe));
de9a35ab 1542
e2c719b7 1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1544 && (val & DP_PIPEB_SELECT),
de9a35ab 1545 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1546}
1547
1548static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550{
47a05eca 1551 u32 val = I915_READ(reg);
e2c719b7 1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1554 reg, pipe_name(pipe));
de9a35ab 1555
e2c719b7 1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1557 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1558 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1559}
1560
1561static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
291906f1 1566
f0575e92
KP		 1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
e2c719b7 1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1575 pipe_name(pipe));
291906f1
JB		 1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
e2c719b7 1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1581 pipe_name(pipe));
291906f1 1582
e2debe91
PZ		 1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1586}
1587
40e9cf64
JB		 1588static void intel_init_dpio(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
a09caddd
CML		 1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
5382f5f3
JB		 1606}
1607
d288f65f 1608static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1609 const struct intel_crtc_state *pipe_config)
87442f73 1610{
426115cf
DV		 1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
d288f65f 1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1615
426115cf 1616 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1622 if (IS_MOBILE(dev_priv->dev))
426115cf 1623 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1624
426115cf
DV		 1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
d288f65f 1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1633 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1634
1635 /* We do this three times for luck */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
426115cf 1642 I915_WRITE(reg, dpll);
87442f73
DV		 1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645}
1646
d288f65f 1647static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1648 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1649{
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
a580516d 1660 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
54433e91
VS		 1667 mutex_unlock(&dev_priv->sb_lock);
1668
9d556c99
CML		 1669 /*
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671 */
1672 udelay(1);
1673
1674 /* Enable PLL */
d288f65f 1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1676
1677 /* Check PLL is locked */
a11b0703 1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
a11b0703 1681 /* not sure when this should be written */
d288f65f 1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1683 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1684}
1685
1c4e0274
VS		 1686static int intel_num_dvo_pipes(struct drm_device *dev)
1687{
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
3538b9df 1692 count += crtc->base.state->active &&
409ee761 1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1694
1695 return count;
1696}
1697
66e3d5c0 1698static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1699{
66e3d5c0
DV		 1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
6e3c9717 1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1704
66e3d5c0 1705 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1706
63d7bbe9 1707 /* No really, not for ILK+ */
3d13ef2e 1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1709
1710 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1713
1c4e0274
VS		 1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
66e3d5c0
DV		 1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1733 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
63d7bbe9
JB		 1742
1743 /* We do this three times for luck */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
66e3d5c0 1750 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753}
1754
1755/**
50b44a44 1756 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1c4e0274 1764static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1765{
1c4e0274
VS		 1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
409ee761 1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1773 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
b6b5d049
VS		 1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
b8afb911 1788 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1789 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1790}
1791
f6071166
JB		 1792static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793{
b8afb911 1794 u32 val;
f6071166
JB		 1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
e5cbfbfb
ID		 1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
b8afb911 1803 val = DPLL_VGA_MODE_DIS;
f6071166 1804 if (pipe == PIPE_B)
60bfe44f 1805 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1806 I915_WRITE(DPLL(pipe), val);
1807 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1808
1809}
1810
1811static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812{
d752048d 1813 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1814 u32 val;
1815
a11b0703
VS		 1816 /* Make sure the pipe isn't still relying on us */
1817 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1818
a11b0703 1819 /* Set PLL en = 0 */
60bfe44f
VS		 1820 val = DPLL_SSC_REF_CLK_CHV |
1821 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1822 if (pipe != PIPE_A)
1823 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824 I915_WRITE(DPLL(pipe), val);
1825 POSTING_READ(DPLL(pipe));
d752048d 1826
a580516d 1827 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1828
1829 /* Disable 10bit clock to display controller */
1830 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831 val &= ~DPIO_DCLKP_EN;
1832 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
61407f6d
VS		 1834 /* disable left/right clock distribution */
1835 if (pipe != PIPE_B) {
1836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1839 } else {
1840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1843 }
1844
a580516d 1845 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1846}
1847
e4607fcf 1848void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1849 struct intel_digital_port *dport,
1850 unsigned int expected_mask)
89b667f8
JB		 1851{
1852 u32 port_mask;
00fc31b7 1853 int dpll_reg;
89b667f8 1854
e4607fcf
CML		 1855 switch (dport->port) {
1856 case PORT_B:
89b667f8 1857 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1858 dpll_reg = DPLL(0);
e4607fcf
CML		 1859 break;
1860 case PORT_C:
89b667f8 1861 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1862 dpll_reg = DPLL(0);
9b6de0a1 1863 expected_mask <<= 4;
00fc31b7
CML		 1864 break;
1865 case PORT_D:
1866 port_mask = DPLL_PORTD_READY_MASK;
1867 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1868 break;
1869 default:
1870 BUG();
1871 }
89b667f8 1872
9b6de0a1
VS		 1873 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1874 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1875 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1876}
1877
b14b1055
DV		 1878static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1879{
1880 struct drm_device *dev = crtc->base.dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1883
be19f0ff
CW		 1884 if (WARN_ON(pll == NULL))
1885 return;
1886
3e369b76 1887 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1888 if (pll->active == 0) {
1889 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1890 WARN_ON(pll->on);
1891 assert_shared_dpll_disabled(dev_priv, pll);
1892
1893 pll->mode_set(dev_priv, pll);
1894 }
1895}
1896
92f2584a 1897/**
85b3894f 1898 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1899 * @dev_priv: i915 private structure
1900 * @pipe: pipe PLL to enable
1901 *
1902 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1903 * drives the transcoder clock.
1904 */
85b3894f 1905static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1906{
3d13ef2e
DL		 1907 struct drm_device *dev = crtc->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1909 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1910
87a875bb 1911 if (WARN_ON(pll == NULL))
48da64a8
CW		 1912 return;
1913
3e369b76 1914 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1915 return;
ee7b9f93 1916
74dd6928 1917 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1918 pll->name, pll->active, pll->on,
e2b78267 1919 crtc->base.base.id);
92f2584a 1920
cdbd2316
DV		 1921 if (pll->active++) {
1922 WARN_ON(!pll->on);
e9d6944e 1923 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1924 return;
1925 }
f4a091c7 1926 WARN_ON(pll->on);
ee7b9f93 1927
bd2bb1b9
PZ		 1928 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1929
46edb027 1930 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1931 pll->enable(dev_priv, pll);
ee7b9f93 1932 pll->on = true;
92f2584a
JB		 1933}
1934
f6daaec2 1935static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1936{
3d13ef2e
DL		 1937 struct drm_device *dev = crtc->base.dev;
1938 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1939 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1940
92f2584a 1941 /* PCH only available on ILK+ */
80aa9312
JB		 1942 if (INTEL_INFO(dev)->gen < 5)
1943 return;
1944
eddfcbcd
ML		 1945 if (pll == NULL)
1946 return;
92f2584a 1947
eddfcbcd 1948 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
c5de7c6f
VS		 2006 * Make the BPC in transcoder be consistent with
2007 * that in pipeconf reg. For HDMI we must use 8bpc
2008 * here for both 8bpc and 12bpc.
e9bcff5c 2009 */
dfd07d72 2010 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2011 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2012 val |= PIPECONF_8BPC;
2013 else
2014 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2015 }
5f7f726d
PZ		 2016
2017 val &= ~TRANS_INTERLACE_MASK;
2018 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2019 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2020 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2021 val |= TRANS_LEGACY_INTERLACED_ILK;
2022 else
2023 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2024 else
2025 val |= TRANS_PROGRESSIVE;
2026
040484af
JB		 2027 I915_WRITE(reg, val | TRANS_ENABLE);
2028 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2029 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2030}
2031
8fb033d7 2032static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2033 enum transcoder cpu_transcoder)
040484af 2034{
8fb033d7 2035 u32 val, pipeconf_val;
8fb033d7
PZ		 2036
2037 /* PCH only available on ILK+ */
55522f37 2038 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2039
8fb033d7 2040 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2041 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2042 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2043
223a6fdf
PZ		 2044 /* Workaround: set timing override bit. */
2045 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2046 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2047 I915_WRITE(_TRANSA_CHICKEN2, val);
2048
25f3ef11 2049 val = TRANS_ENABLE;
937bb610 2050 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2051
9a76b1c6
PZ		 2052 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2053 PIPECONF_INTERLACED_ILK)
a35f2679 2054 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2055 else
2056 val |= TRANS_PROGRESSIVE;
2057
ab9412ba
DV		 2058 I915_WRITE(LPT_TRANSCONF, val);
2059 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2060 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2061}
2062
b8a4f404
PZ		 2063static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2064 enum pipe pipe)
040484af 2065{
23670b32
DV		 2066 struct drm_device *dev = dev_priv->dev;
2067 uint32_t reg, val;
040484af
JB		 2068
2069 /* FDI relies on the transcoder */
2070 assert_fdi_tx_disabled(dev_priv, pipe);
2071 assert_fdi_rx_disabled(dev_priv, pipe);
2072
291906f1
JB		 2073 /* Ports must be off as well */
2074 assert_pch_ports_disabled(dev_priv, pipe);
2075
ab9412ba 2076 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2077 val = I915_READ(reg);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(reg, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2082 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2083
2084 if (!HAS_PCH_IBX(dev)) {
2085 /* Workaround: Clear the timing override chicken bit again. */
2086 reg = TRANS_CHICKEN2(pipe);
2087 val = I915_READ(reg);
2088 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2089 I915_WRITE(reg, val);
2090 }
040484af
JB		 2091}
2092
ab4d966c 2093static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2094{
8fb033d7
PZ		 2095 u32 val;
2096
ab9412ba 2097 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2098 val &= ~TRANS_ENABLE;
ab9412ba 2099 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2100 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2101 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2102 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2103
2104 /* Workaround: clear timing override bit. */
2105 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2106 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2107 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2108}
2109
b24e7179 2110/**
309cfea8 2111 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2112 * @crtc: crtc responsible for the pipe
b24e7179 2113 *
0372264a 2114 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2115 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2116 */
e1fdc473 2117static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2118{
0372264a
PZ		 2119 struct drm_device *dev = crtc->base.dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2123 pipe);
1a240d4d 2124 enum pipe pch_transcoder;
b24e7179
JB		 2125 int reg;
2126 u32 val;
2127
9e2ee2dd
VS		 2128 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2129
58c6eaa2 2130 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2131 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2132 assert_sprites_disabled(dev_priv, pipe);
2133
681e5811 2134 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2135 pch_transcoder = TRANSCODER_A;
2136 else
2137 pch_transcoder = pipe;
2138
b24e7179
JB		 2139 /*
2140 * A pipe without a PLL won't actually be able to drive bits from
2141 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2142 * need the check.
2143 */
50360403 2144 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2145 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2146 assert_dsi_pll_enabled(dev_priv);
2147 else
2148 assert_pll_enabled(dev_priv, pipe);
040484af 2149 else {
6e3c9717 2150 if (crtc->config->has_pch_encoder) {
040484af 2151 /* if driving the PCH, we need FDI enabled */
cc391bbb 2152 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2153 assert_fdi_tx_pll_enabled(dev_priv,
2154 (enum pipe) cpu_transcoder);
040484af
JB		 2155 }
2156 /* FIXME: assert CPU port conditions for SNB+ */
2157 }
b24e7179 2158
702e7a56 2159 reg = PIPECONF(cpu_transcoder);
b24e7179 2160 val = I915_READ(reg);
7ad25d48 2161 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2162 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2163 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2164 return;
7ad25d48 2165 }
00d70b15
CW		 2166
2167 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2168 POSTING_READ(reg);
b24e7179
JB		 2169}
2170
2171/**
309cfea8 2172 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2173 * @crtc: crtc whose pipes is to be disabled
b24e7179 2174 *
575f7ab7
VS		 2175 * Disable the pipe of @crtc, making sure that various hardware
2176 * specific requirements are met, if applicable, e.g. plane
2177 * disabled, panel fitter off, etc.
b24e7179
JB		 2178 *
2179 * Will wait until the pipe has shut down before returning.
2180 */
575f7ab7 2181static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2182{
575f7ab7 2183 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2184 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2185 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2186 int reg;
2187 u32 val;
2188
9e2ee2dd
VS		 2189 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2190
b24e7179
JB		 2191 /*
2192 * Make sure planes won't keep trying to pump pixels to us,
2193 * or we might hang the display.
2194 */
2195 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2196 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2197 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2198
702e7a56 2199 reg = PIPECONF(cpu_transcoder);
b24e7179 2200 val = I915_READ(reg);
00d70b15
CW		 2201 if ((val & PIPECONF_ENABLE) == 0)
2202 return;
2203
67adc644
VS		 2204 /*
2205 * Double wide has implications for planes
2206 * so best keep it disabled when not needed.
2207 */
6e3c9717 2208 if (crtc->config->double_wide)
67adc644
VS		 2209 val &= ~PIPECONF_DOUBLE_WIDE;
2210
2211 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2212 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2213 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2214 val &= ~PIPECONF_ENABLE;
2215
2216 I915_WRITE(reg, val);
2217 if ((val & PIPECONF_ENABLE) == 0)
2218 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2219}
2220
693db184
CW		 2221static bool need_vtd_wa(struct drm_device *dev)
2222{
2223#ifdef CONFIG_INTEL_IOMMU
2224 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2225 return true;
2226#endif
2227 return false;
2228}
2229
50470bb0 2230unsigned int
6761dd31
TU		 2231intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2232 uint64_t fb_format_modifier)
a57ce0b2 2233{
6761dd31
TU		 2234 unsigned int tile_height;
2235 uint32_t pixel_bytes;
a57ce0b2 2236
b5d0e9bf
DL		 2237 switch (fb_format_modifier) {
2238 case DRM_FORMAT_MOD_NONE:
2239 tile_height = 1;
2240 break;
2241 case I915_FORMAT_MOD_X_TILED:
2242 tile_height = IS_GEN2(dev) ? 16 : 8;
2243 break;
2244 case I915_FORMAT_MOD_Y_TILED:
2245 tile_height = 32;
2246 break;
2247 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2248 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2249 switch (pixel_bytes) {
b5d0e9bf 2250 default:
6761dd31 2251 case 1:
b5d0e9bf
DL		 2252 tile_height = 64;
2253 break;
6761dd31
TU		 2254 case 2:
2255 case 4:
b5d0e9bf
DL		 2256 tile_height = 32;
2257 break;
6761dd31 2258 case 8:
b5d0e9bf
DL		 2259 tile_height = 16;
2260 break;
6761dd31 2261 case 16:
b5d0e9bf
DL		 2262 WARN_ONCE(1,
2263 "128-bit pixels are not supported for display!");
2264 tile_height = 16;
2265 break;
2266 }
2267 break;
2268 default:
2269 MISSING_CASE(fb_format_modifier);
2270 tile_height = 1;
2271 break;
2272 }
091df6cb 2273
6761dd31
TU		 2274 return tile_height;
2275}
2276
2277unsigned int
2278intel_fb_align_height(struct drm_device *dev, unsigned int height,
2279 uint32_t pixel_format, uint64_t fb_format_modifier)
2280{
2281 return ALIGN(height, intel_tile_height(dev, pixel_format,
2282 fb_format_modifier));
a57ce0b2
JB		 2283}
2284
f64b98cd
TU		 2285static int
2286intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2287 const struct drm_plane_state *plane_state)
2288{
50470bb0 2289 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2290 unsigned int tile_height, tile_pitch;
50470bb0 2291
f64b98cd
TU		 2292 *view = i915_ggtt_view_normal;
2293
50470bb0
TU		 2294 if (!plane_state)
2295 return 0;
2296
121920fa 2297 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2298 return 0;
2299
9abc4648 2300 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2301
2302 info->height = fb->height;
2303 info->pixel_format = fb->pixel_format;
2304 info->pitch = fb->pitches[0];
2305 info->fb_modifier = fb->modifier[0];
2306
84fe03f7
TU		 2307 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2308 fb->modifier[0]);
2309 tile_pitch = PAGE_SIZE / tile_height;
2310 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2311 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2312 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2313
f64b98cd
TU		 2314 return 0;
2315}
2316
4e9a86b6
VS		 2317static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2318{
2319 if (INTEL_INFO(dev_priv)->gen >= 9)
2320 return 256 * 1024;
985b8bb4
VS		 2321 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2322 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2323 return 128 * 1024;
2324 else if (INTEL_INFO(dev_priv)->gen >= 4)
2325 return 4 * 1024;
2326 else
44c5905e 2327 return 0;
4e9a86b6
VS		 2328}
2329
127bd2ac 2330int
850c4cdc
TU		 2331intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2332 struct drm_framebuffer *fb,
82bc3b2d 2333 const struct drm_plane_state *plane_state,
91af127f
JH		 2334 struct intel_engine_cs *pipelined,
2335 struct drm_i915_gem_request **pipelined_request)
6b95a207 2336{
850c4cdc 2337 struct drm_device *dev = fb->dev;
ce453d81 2338 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2339 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2340 struct i915_ggtt_view view;
6b95a207
KH		 2341 u32 alignment;
2342 int ret;
2343
ebcdd39e
MR		 2344 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2345
7b911adc
TU		 2346 switch (fb->modifier[0]) {
2347 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2348 alignment = intel_linear_alignment(dev_priv);
6b95a207 2349 break;
7b911adc 2350 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2353 else {
2354 /* pin() will align the object as required by fence */
2355 alignment = 0;
2356 }
6b95a207 2357 break;
7b911adc 2358 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2362 return -EINVAL;
2363 alignment = 1 * 1024 * 1024;
2364 break;
6b95a207 2365 default:
7b911adc
TU		 2366 MISSING_CASE(fb->modifier[0]);
2367 return -EINVAL;
6b95a207
KH		 2368 }
2369
f64b98cd
TU		 2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371 if (ret)
2372 return ret;
2373
693db184
CW		 2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2377 * the VT-d warning.
2378 */
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2381
d6dd6843
PZ		 2382 /*
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2388 */
2389 intel_runtime_pm_get(dev_priv);
2390
ce453d81 2391 dev_priv->mm.interruptible = false;
e6617330 2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2393 pipelined_request, &view);
48b956c5 2394 if (ret)
ce453d81 2395 goto err_interruptible;
6b95a207
KH		 2396
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2401 */
06d98131 2402 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2403 if (ret == -EDEADLK) {
2404 /*
2405 * -EDEADLK means there are no free fences
2406 * no pending flips.
2407 *
2408 * This is propagated to atomic, but it uses
2409 * -EDEADLK to force a locking recovery, so
2410 * change the returned error to -EBUSY.
2411 */
2412 ret = -EBUSY;
2413 goto err_unpin;
2414 } else if (ret)
9a5a53b3 2415 goto err_unpin;
1690e1eb 2416
9a5a53b3 2417 i915_gem_object_pin_fence(obj);
6b95a207 2418
ce453d81 2419 dev_priv->mm.interruptible = true;
d6dd6843 2420 intel_runtime_pm_put(dev_priv);
6b95a207 2421 return 0;
48b956c5
CW		 2422
2423err_unpin:
f64b98cd 2424 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2425err_interruptible:
2426 dev_priv->mm.interruptible = true;
d6dd6843 2427 intel_runtime_pm_put(dev_priv);
48b956c5 2428 return ret;
6b95a207
KH		 2429}
2430
82bc3b2d
TU		 2431static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2432 const struct drm_plane_state *plane_state)
1690e1eb 2433{
82bc3b2d 2434 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2435 struct i915_ggtt_view view;
2436 int ret;
82bc3b2d 2437
ebcdd39e
MR		 2438 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2439
f64b98cd
TU		 2440 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2441 WARN_ONCE(ret, "Couldn't get view from plane state!");
2442
1690e1eb 2443 i915_gem_object_unpin_fence(obj);
f64b98cd 2444 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2445}
2446
c2c75131
DV		 2447/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2448 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2449unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2450 int *x, int *y,
bc752862
CW		 2451 unsigned int tiling_mode,
2452 unsigned int cpp,
2453 unsigned int pitch)
c2c75131 2454{
bc752862
CW		 2455 if (tiling_mode != I915_TILING_NONE) {
2456 unsigned int tile_rows, tiles;
c2c75131 2457
bc752862
CW		 2458 tile_rows = *y / 8;
2459 *y %= 8;
c2c75131 2460
bc752862
CW		 2461 tiles = *x / (512/cpp);
2462 *x %= 512/cpp;
2463
2464 return tile_rows * pitch * 8 + tiles * 4096;
2465 } else {
4e9a86b6 2466 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2470 *y = (offset & alignment) / pitch;
2471 *x = ((offset & alignment) - *y * pitch) / cpp;
2472 return offset & ~alignment;
bc752862 2473 }
c2c75131
DV		 2474}
2475
b35d63fa 2476static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2477{
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495}
2496
bc8d7dff
DL		 2497static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498{
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521}
2522
5724dbd1 2523static bool
f6936e29
DV		 2524intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2526{
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2530 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
46f297fb 2536
ff2652ea
CW		 2537 if (plane_config->size == 0)
2538 return false;
2539
f37b5c2b
DV		 2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
46f297fb 2544 if (!obj)
484b41dd 2545 return false;
46f297fb 2546
49af449b
DL		 2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2549 obj->stride = fb->pitches[0];
46f297fb 2550
6bf129df
DL		 2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2557
2558 mutex_lock(&dev->struct_mutex);
6bf129df 2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2560 &mode_cmd, obj)) {
46f297fb
JB		 2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
46f297fb 2564 mutex_unlock(&dev->struct_mutex);
484b41dd 2565
f6936e29 2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2567 return true;
46f297fb
JB		 2568
2569out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2572 return false;
2573}
2574
afd65eb4
MR		 2575/* Update plane->state->fb to match plane->fb after driver-internal updates */
2576static void
2577update_state_fb(struct drm_plane *plane)
2578{
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587}
2588
5724dbd1 2589static void
f6936e29
DV		 2590intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2592{
2593 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2594 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2ff8fde1 2597 struct drm_i915_gem_object *obj;
88595ac9 2598 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2599 struct drm_plane_state *plane_state = primary->state;
88595ac9 2600 struct drm_framebuffer *fb;
484b41dd 2601
2d14030b 2602 if (!plane_config->fb)
484b41dd
JB		 2603 return;
2604
f6936e29 2605 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2606 fb = &plane_config->fb->base;
2607 goto valid_fb;
f55548b5 2608 }
484b41dd 2609
2d14030b 2610 kfree(plane_config->fb);
484b41dd
JB		 2611
2612 /*
2613 * Failed to alloc the obj, check to see if we should share
2614 * an fb with another CRTC instead
2615 */
70e1e0ec 2616 for_each_crtc(dev, c) {
484b41dd
JB		 2617 i = to_intel_crtc(c);
2618
2619 if (c == &intel_crtc->base)
2620 continue;
2621
2ff8fde1
MR		 2622 if (!i->active)
2623 continue;
2624
88595ac9
DV		 2625 fb = c->primary->fb;
2626 if (!fb)
484b41dd
JB		 2627 continue;
2628
88595ac9 2629 obj = intel_fb_obj(fb);
2ff8fde1 2630 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2631 drm_framebuffer_reference(fb);
2632 goto valid_fb;
484b41dd
JB		 2633 }
2634 }
88595ac9
DV		 2635
2636 return;
2637
2638valid_fb:
be5651f2
ML		 2639 plane_state->src_x = plane_state->src_y = 0;
2640 plane_state->src_w = fb->width << 16;
2641 plane_state->src_h = fb->height << 16;
2642
2643 plane_state->crtc_x = plane_state->src_y = 0;
2644 plane_state->crtc_w = fb->width;
2645 plane_state->crtc_h = fb->height;
2646
88595ac9
DV		 2647 obj = intel_fb_obj(fb);
2648 if (obj->tiling_mode != I915_TILING_NONE)
2649 dev_priv->preserve_bios_swizzle = true;
2650
be5651f2
ML		 2651 drm_framebuffer_reference(fb);
2652 primary->fb = primary->state->fb = fb;
36750f28 2653 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2654 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2655 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2656}
2657
29b9bde6
DV		 2658static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2659 struct drm_framebuffer *fb,
2660 int x, int y)
81255565
JB		 2661{
2662 struct drm_device *dev = crtc->dev;
2663 struct drm_i915_private *dev_priv = dev->dev_private;
2664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2665 struct drm_plane *primary = crtc->primary;
2666 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2667 struct drm_i915_gem_object *obj;
81255565 2668 int plane = intel_crtc->plane;
e506a0c6 2669 unsigned long linear_offset;
81255565 2670 u32 dspcntr;
f45651ba 2671 u32 reg = DSPCNTR(plane);
48404c1e 2672 int pixel_size;
f45651ba 2673
b70709a6 2674 if (!visible || !fb) {
fdd508a6
VS		 2675 I915_WRITE(reg, 0);
2676 if (INTEL_INFO(dev)->gen >= 4)
2677 I915_WRITE(DSPSURF(plane), 0);
2678 else
2679 I915_WRITE(DSPADDR(plane), 0);
2680 POSTING_READ(reg);
2681 return;
2682 }
2683
c9ba6fad
VS		 2684 obj = intel_fb_obj(fb);
2685 if (WARN_ON(obj == NULL))
2686 return;
2687
2688 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2689
f45651ba
VS		 2690 dspcntr = DISPPLANE_GAMMA_ENABLE;
2691
fdd508a6 2692 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2693
2694 if (INTEL_INFO(dev)->gen < 4) {
2695 if (intel_crtc->pipe == PIPE_B)
2696 dspcntr |= DISPPLANE_SEL_PIPE_B;
2697
2698 /* pipesrc and dspsize control the size that is scaled from,
2699 * which should always be the user's requested size.
2700 */
2701 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2702 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2703 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2704 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2705 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2706 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2707 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2708 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2709 I915_WRITE(PRIMPOS(plane), 0);
2710 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2711 }
81255565 2712
57779d06
VS		 2713 switch (fb->pixel_format) {
2714 case DRM_FORMAT_C8:
81255565
JB		 2715 dspcntr |= DISPPLANE_8BPP;
2716 break;
57779d06 2717 case DRM_FORMAT_XRGB1555:
57779d06 2718 dspcntr |= DISPPLANE_BGRX555;
81255565 2719 break;
57779d06
VS		 2720 case DRM_FORMAT_RGB565:
2721 dspcntr |= DISPPLANE_BGRX565;
2722 break;
2723 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2724 dspcntr |= DISPPLANE_BGRX888;
2725 break;
2726 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2727 dspcntr |= DISPPLANE_RGBX888;
2728 break;
2729 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2730 dspcntr |= DISPPLANE_BGRX101010;
2731 break;
2732 case DRM_FORMAT_XBGR2101010:
57779d06 2733 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2734 break;
2735 default:
baba133a 2736 BUG();
81255565 2737 }
57779d06 2738
f45651ba
VS		 2739 if (INTEL_INFO(dev)->gen >= 4 &&
2740 obj->tiling_mode != I915_TILING_NONE)
2741 dspcntr |= DISPPLANE_TILED;
81255565 2742
de1aa629
VS		 2743 if (IS_G4X(dev))
2744 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2745
b9897127 2746 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2747
c2c75131
DV		 2748 if (INTEL_INFO(dev)->gen >= 4) {
2749 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2750 intel_gen4_compute_page_offset(dev_priv,
2751 &x, &y, obj->tiling_mode,
b9897127 2752 pixel_size,
bc752862 2753 fb->pitches[0]);
c2c75131
DV		 2754 linear_offset -= intel_crtc->dspaddr_offset;
2755 } else {
e506a0c6 2756 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2757 }
e506a0c6 2758
8e7d688b 2759 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2760 dspcntr |= DISPPLANE_ROTATE_180;
2761
6e3c9717
ACO		 2762 x += (intel_crtc->config->pipe_src_w - 1);
2763 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2764
2765 /* Finding the last pixel of the last line of the display
2766 data and adding to linear_offset*/
2767 linear_offset +=
6e3c9717
ACO		 2768 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2769 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2770 }
2771
2772 I915_WRITE(reg, dspcntr);
2773
01f2c773 2774 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2775 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2776 I915_WRITE(DSPSURF(plane),
2777 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2778 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2779 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2780 } else
f343c5f6 2781 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2782 POSTING_READ(reg);
17638cd6
JB		 2783}
2784
29b9bde6
DV		 2785static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2786 struct drm_framebuffer *fb,
2787 int x, int y)
17638cd6
JB		 2788{
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2792 struct drm_plane *primary = crtc->primary;
2793 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2794 struct drm_i915_gem_object *obj;
17638cd6 2795 int plane = intel_crtc->plane;
e506a0c6 2796 unsigned long linear_offset;
17638cd6 2797 u32 dspcntr;
f45651ba 2798 u32 reg = DSPCNTR(plane);
48404c1e 2799 int pixel_size;
f45651ba 2800
b70709a6 2801 if (!visible || !fb) {
fdd508a6
VS		 2802 I915_WRITE(reg, 0);
2803 I915_WRITE(DSPSURF(plane), 0);
2804 POSTING_READ(reg);
2805 return;
2806 }
2807
c9ba6fad
VS		 2808 obj = intel_fb_obj(fb);
2809 if (WARN_ON(obj == NULL))
2810 return;
2811
2812 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2813
f45651ba
VS		 2814 dspcntr = DISPPLANE_GAMMA_ENABLE;
2815
fdd508a6 2816 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2817
2818 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2819 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2820
57779d06
VS		 2821 switch (fb->pixel_format) {
2822 case DRM_FORMAT_C8:
17638cd6
JB		 2823 dspcntr |= DISPPLANE_8BPP;
2824 break;
57779d06
VS		 2825 case DRM_FORMAT_RGB565:
2826 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2827 break;
57779d06 2828 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2829 dspcntr |= DISPPLANE_BGRX888;
2830 break;
2831 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2832 dspcntr |= DISPPLANE_RGBX888;
2833 break;
2834 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2835 dspcntr |= DISPPLANE_BGRX101010;
2836 break;
2837 case DRM_FORMAT_XBGR2101010:
57779d06 2838 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2839 break;
2840 default:
baba133a 2841 BUG();
17638cd6
JB		 2842 }
2843
2844 if (obj->tiling_mode != I915_TILING_NONE)
2845 dspcntr |= DISPPLANE_TILED;
17638cd6 2846
f45651ba 2847 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2848 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2849
b9897127 2850 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2851 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2852 intel_gen4_compute_page_offset(dev_priv,
2853 &x, &y, obj->tiling_mode,
b9897127 2854 pixel_size,
bc752862 2855 fb->pitches[0]);
c2c75131 2856 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2857 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2858 dspcntr |= DISPPLANE_ROTATE_180;
2859
2860 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2861 x += (intel_crtc->config->pipe_src_w - 1);
2862 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2863
2864 /* Finding the last pixel of the last line of the display
2865 data and adding to linear_offset*/
2866 linear_offset +=
6e3c9717
ACO		 2867 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2868 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2869 }
2870 }
2871
2872 I915_WRITE(reg, dspcntr);
17638cd6 2873
01f2c773 2874 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2875 I915_WRITE(DSPSURF(plane),
2876 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2877 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2878 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2879 } else {
2880 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881 I915_WRITE(DSPLINOFF(plane), linear_offset);
2882 }
17638cd6 2883 POSTING_READ(reg);
17638cd6
JB		 2884}
2885
b321803d
DL		 2886u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887 uint32_t pixel_format)
2888{
2889 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2890
2891 /*
2892 * The stride is either expressed as a multiple of 64 bytes
2893 * chunks for linear buffers or in number of tiles for tiled
2894 * buffers.
2895 */
2896 switch (fb_modifier) {
2897 case DRM_FORMAT_MOD_NONE:
2898 return 64;
2899 case I915_FORMAT_MOD_X_TILED:
2900 if (INTEL_INFO(dev)->gen == 2)
2901 return 128;
2902 return 512;
2903 case I915_FORMAT_MOD_Y_TILED:
2904 /* No need to check for old gens and Y tiling since this is
2905 * about the display engine and those will be blocked before
2906 * we get here.
2907 */
2908 return 128;
2909 case I915_FORMAT_MOD_Yf_TILED:
2910 if (bits_per_pixel == 8)
2911 return 64;
2912 else
2913 return 128;
2914 default:
2915 MISSING_CASE(fb_modifier);
2916 return 64;
2917 }
2918}
2919
121920fa
TU		 2920unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2921 struct drm_i915_gem_object *obj)
2922{
9abc4648 2923 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2924
2925 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2926 view = &i915_ggtt_view_rotated;
121920fa
TU		 2927
2928 return i915_gem_obj_ggtt_offset_view(obj, view);
2929}
2930
e435d6e5
ML		 2931static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2932{
2933 struct drm_device *dev = intel_crtc->base.dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935
2936 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2937 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2938 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2939 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2940 intel_crtc->base.base.id, intel_crtc->pipe, id);
2941}
2942
a1b2278e
CK		 2943/*
2944 * This function detaches (aka. unbinds) unused scalers in hardware
2945 */
0583236e 2946static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2947{
a1b2278e
CK		 2948 struct intel_crtc_scaler_state *scaler_state;
2949 int i;
2950
a1b2278e
CK		 2951 scaler_state = &intel_crtc->config->scaler_state;
2952
2953 /* loop through and disable scalers that aren't in use */
2954 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2955 if (!scaler_state->scalers[i].in_use)
2956 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2957 }
2958}
2959
6156a456 2960u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2961{
6156a456 2962 switch (pixel_format) {
d161cf7a 2963 case DRM_FORMAT_C8:
c34ce3d1 2964 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2965 case DRM_FORMAT_RGB565:
c34ce3d1 2966 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2967 case DRM_FORMAT_XBGR8888:
c34ce3d1 2968 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2969 case DRM_FORMAT_XRGB8888:
c34ce3d1 2970 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2971 /*
2972 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2973 * to be already pre-multiplied. We need to add a knob (or a different
2974 * DRM_FORMAT) for user-space to configure that.
2975 */
f75fb42a 2976 case DRM_FORMAT_ABGR8888:
c34ce3d1 2977 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2979 case DRM_FORMAT_ARGB8888:
c34ce3d1 2980 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2981 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2982 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2983 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2984 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2985 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2986 case DRM_FORMAT_YUYV:
c34ce3d1 2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2988 case DRM_FORMAT_YVYU:
c34ce3d1 2989 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2990 case DRM_FORMAT_UYVY:
c34ce3d1 2991 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2992 case DRM_FORMAT_VYUY:
c34ce3d1 2993 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2994 default:
4249eeef 2995 MISSING_CASE(pixel_format);
70d21f0e 2996 }
8cfcba41 2997
c34ce3d1 2998 return 0;
6156a456 2999}
70d21f0e 3000
6156a456
CK		 3001u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3002{
6156a456 3003 switch (fb_modifier) {
30af77c4 3004 case DRM_FORMAT_MOD_NONE:
70d21f0e 3005 break;
30af77c4 3006 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3007 return PLANE_CTL_TILED_X;
b321803d 3008 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3009 return PLANE_CTL_TILED_Y;
b321803d 3010 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3011 return PLANE_CTL_TILED_YF;
70d21f0e 3012 default:
6156a456 3013 MISSING_CASE(fb_modifier);
70d21f0e 3014 }
8cfcba41 3015
c34ce3d1 3016 return 0;
6156a456 3017}
70d21f0e 3018
6156a456
CK		 3019u32 skl_plane_ctl_rotation(unsigned int rotation)
3020{
3b7a5119 3021 switch (rotation) {
6156a456
CK		 3022 case BIT(DRM_ROTATE_0):
3023 break;
1e8df167
SJ		 3024 /*
3025 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3026 * while i915 HW rotation is clockwise, thats why this swapping.
3027 */
3b7a5119 3028 case BIT(DRM_ROTATE_90):
1e8df167 3029 return PLANE_CTL_ROTATE_270;
3b7a5119 3030 case BIT(DRM_ROTATE_180):
c34ce3d1 3031 return PLANE_CTL_ROTATE_180;
3b7a5119 3032 case BIT(DRM_ROTATE_270):
1e8df167 3033 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3034 default:
3035 MISSING_CASE(rotation);
3036 }
3037
c34ce3d1 3038 return 0;
6156a456
CK		 3039}
3040
3041static void skylake_update_primary_plane(struct drm_crtc *crtc,
3042 struct drm_framebuffer *fb,
3043 int x, int y)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3048 struct drm_plane *plane = crtc->primary;
3049 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3050 struct drm_i915_gem_object *obj;
3051 int pipe = intel_crtc->pipe;
3052 u32 plane_ctl, stride_div, stride;
3053 u32 tile_height, plane_offset, plane_size;
3054 unsigned int rotation;
3055 int x_offset, y_offset;
3056 unsigned long surf_addr;
6156a456
CK		 3057 struct intel_crtc_state *crtc_state = intel_crtc->config;
3058 struct intel_plane_state *plane_state;
3059 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3060 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3061 int scaler_id = -1;
3062
6156a456
CK		 3063 plane_state = to_intel_plane_state(plane->state);
3064
b70709a6 3065 if (!visible || !fb) {
6156a456
CK		 3066 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3067 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3068 POSTING_READ(PLANE_CTL(pipe, 0));
3069 return;
3b7a5119 3070 }
70d21f0e 3071
6156a456
CK		 3072 plane_ctl = PLANE_CTL_ENABLE |
3073 PLANE_CTL_PIPE_GAMMA_ENABLE |
3074 PLANE_CTL_PIPE_CSC_ENABLE;
3075
3076 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3077 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3078 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3079
3080 rotation = plane->state->rotation;
3081 plane_ctl |= skl_plane_ctl_rotation(rotation);
3082
b321803d
DL		 3083 obj = intel_fb_obj(fb);
3084 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3085 fb->pixel_format);
3b7a5119
SJ		 3086 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3087
6156a456
CK		 3088 /*
3089 * FIXME: intel_plane_state->src, dst aren't set when transitional
3090 * update_plane helpers are called from legacy paths.
3091 * Once full atomic crtc is available, below check can be avoided.
3092 */
3093 if (drm_rect_width(&plane_state->src)) {
3094 scaler_id = plane_state->scaler_id;
3095 src_x = plane_state->src.x1 >> 16;
3096 src_y = plane_state->src.y1 >> 16;
3097 src_w = drm_rect_width(&plane_state->src) >> 16;
3098 src_h = drm_rect_height(&plane_state->src) >> 16;
3099 dst_x = plane_state->dst.x1;
3100 dst_y = plane_state->dst.y1;
3101 dst_w = drm_rect_width(&plane_state->dst);
3102 dst_h = drm_rect_height(&plane_state->dst);
3103
3104 WARN_ON(x != src_x || y != src_y);
3105 } else {
3106 src_w = intel_crtc->config->pipe_src_w;
3107 src_h = intel_crtc->config->pipe_src_h;
3108 }
3109
3b7a5119
SJ		 3110 if (intel_rotation_90_or_270(rotation)) {
3111 /* stride = Surface height in tiles */
2614f17d 3112 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3113 fb->modifier[0]);
3114 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3115 x_offset = stride * tile_height - y - src_h;
3b7a5119 3116 y_offset = x;
6156a456 3117 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3118 } else {
3119 stride = fb->pitches[0] / stride_div;
3120 x_offset = x;
3121 y_offset = y;
6156a456 3122 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3123 }
3124 plane_offset = y_offset << 16 | x_offset;
b321803d 3125
70d21f0e 3126 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3127 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3128 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3129 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3130
3131 if (scaler_id >= 0) {
3132 uint32_t ps_ctrl = 0;
3133
3134 WARN_ON(!dst_w || !dst_h);
3135 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3136 crtc_state->scaler_state.scalers[scaler_id].mode;
3137 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3138 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3139 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3140 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3141 I915_WRITE(PLANE_POS(pipe, 0), 0);
3142 } else {
3143 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3144 }
3145
121920fa 3146 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3147
3148 POSTING_READ(PLANE_SURF(pipe, 0));
3149}
3150
17638cd6
JB		 3151/* Assume fb object is pinned & idle & fenced and just update base pointers */
3152static int
3153intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3154 int x, int y, enum mode_set_atomic state)
3155{
3156 struct drm_device *dev = crtc->dev;
3157 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3158
ff2a3117 3159 if (dev_priv->fbc.disable_fbc)
7733b49b 3160 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3161
29b9bde6
DV		 3162 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3163
3164 return 0;
81255565
JB		 3165}
3166
7514747d 3167static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3168{
96a02917
VS		 3169 struct drm_crtc *crtc;
3170
70e1e0ec 3171 for_each_crtc(dev, crtc) {
96a02917
VS		 3172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173 enum plane plane = intel_crtc->plane;
3174
3175 intel_prepare_page_flip(dev, plane);
3176 intel_finish_page_flip_plane(dev, plane);
3177 }
7514747d
VS		 3178}
3179
3180static void intel_update_primary_planes(struct drm_device *dev)
3181{
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 struct drm_crtc *crtc;
96a02917 3184
70e1e0ec 3185 for_each_crtc(dev, crtc) {
96a02917
VS		 3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187
51fd371b 3188 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3189 /*
3190 * FIXME: Once we have proper support for primary planes (and
3191 * disabling them without disabling the entire crtc) allow again
66e514c1 3192 * a NULL crtc->primary->fb.
947fdaad 3193 */
f4510a27 3194 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3195 dev_priv->display.update_primary_plane(crtc,
66e514c1 3196 crtc->primary->fb,
262ca2b0
MR		 3197 crtc->x,
3198 crtc->y);
51fd371b 3199 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3200 }
3201}
3202
7514747d
VS		 3203void intel_prepare_reset(struct drm_device *dev)
3204{
3205 /* no reset support for gen2 */
3206 if (IS_GEN2(dev))
3207 return;
3208
3209 /* reset doesn't touch the display */
3210 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3211 return;
3212
3213 drm_modeset_lock_all(dev);
f98ce92f
VS		 3214 /*
3215 * Disabling the crtcs gracefully seems nicer. Also the
3216 * g33 docs say we should at least disable all the planes.
3217 */
6b72d486 3218 intel_display_suspend(dev);
7514747d
VS		 3219}
3220
3221void intel_finish_reset(struct drm_device *dev)
3222{
3223 struct drm_i915_private *dev_priv = to_i915(dev);
3224
3225 /*
3226 * Flips in the rings will be nuked by the reset,
3227 * so complete all pending flips so that user space
3228 * will get its events and not get stuck.
3229 */
3230 intel_complete_page_flips(dev);
3231
3232 /* no reset support for gen2 */
3233 if (IS_GEN2(dev))
3234 return;
3235
3236 /* reset doesn't touch the display */
3237 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3238 /*
3239 * Flips in the rings have been nuked by the reset,
3240 * so update the base address of all primary
3241 * planes to the the last fb to make sure we're
3242 * showing the correct fb after a reset.
3243 */
3244 intel_update_primary_planes(dev);
3245 return;
3246 }
3247
3248 /*
3249 * The display has been reset as well,
3250 * so need a full re-initialization.
3251 */
3252 intel_runtime_pm_disable_interrupts(dev_priv);
3253 intel_runtime_pm_enable_interrupts(dev_priv);
3254
3255 intel_modeset_init_hw(dev);
3256
3257 spin_lock_irq(&dev_priv->irq_lock);
3258 if (dev_priv->display.hpd_irq_setup)
3259 dev_priv->display.hpd_irq_setup(dev);
3260 spin_unlock_irq(&dev_priv->irq_lock);
3261
043e9bda 3262 intel_display_resume(dev);
7514747d
VS		 3263
3264 intel_hpd_init(dev_priv);
3265
3266 drm_modeset_unlock_all(dev);
3267}
3268
2e2f351d 3269static void
14667a4b
CW		 3270intel_finish_fb(struct drm_framebuffer *old_fb)
3271{
2ff8fde1 3272 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3273 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3274 bool was_interruptible = dev_priv->mm.interruptible;
3275 int ret;
3276
14667a4b
CW		 3277 /* Big Hammer, we also need to ensure that any pending
3278 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3279 * current scanout is retired before unpinning the old
2e2f351d
CW		 3280 * framebuffer. Note that we rely on userspace rendering
3281 * into the buffer attached to the pipe they are waiting
3282 * on. If not, userspace generates a GPU hang with IPEHR
3283 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3284 *
3285 * This should only fail upon a hung GPU, in which case we
3286 * can safely continue.
3287 */
3288 dev_priv->mm.interruptible = false;
2e2f351d 3289 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3290 dev_priv->mm.interruptible = was_interruptible;
3291
2e2f351d 3292 WARN_ON(ret);
14667a4b
CW		 3293}
3294
7d5e3799
CW		 3295static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3296{
3297 struct drm_device *dev = crtc->dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3300 bool pending;
3301
3302 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3303 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3304 return false;
3305
5e2d7afc 3306 spin_lock_irq(&dev->event_lock);
7d5e3799 3307 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3308 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3309
3310 return pending;
3311}
3312
e30e8f75
GP		 3313static void intel_update_pipe_size(struct intel_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->base.dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 const struct drm_display_mode *adjusted_mode;
3318
3319 if (!i915.fastboot)
3320 return;
3321
3322 /*
3323 * Update pipe size and adjust fitter if needed: the reason for this is
3324 * that in compute_mode_changes we check the native mode (not the pfit
3325 * mode) to see if we can flip rather than do a full mode set. In the
3326 * fastboot case, we'll flip, but if we don't update the pipesrc and
3327 * pfit state, we'll end up with a big fb scanned out into the wrong
3328 * sized surface.
3329 *
3330 * To fix this properly, we need to hoist the checks up into
3331 * compute_mode_changes (or above), check the actual pfit state and
3332 * whether the platform allows pfit disable with pipe active, and only
3333 * then update the pipesrc and pfit state, even on the flip path.
3334 */
3335
6e3c9717 3336 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3337
3338 I915_WRITE(PIPESRC(crtc->pipe),
3339 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3340 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3341 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3342 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3343 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3344 I915_WRITE(PF_CTL(crtc->pipe), 0);
3345 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3346 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3347 }
6e3c9717
ACO		 3348 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3349 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3350}
3351
5e84e1a4
ZW		 3352static void intel_fdi_normal_train(struct drm_crtc *crtc)
3353{
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 int pipe = intel_crtc->pipe;
3358 u32 reg, temp;
3359
3360 /* enable normal train */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
61e499bf 3363 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3364 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3365 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3366 } else {
3367 temp &= ~FDI_LINK_TRAIN_NONE;
3368 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3369 }
5e84e1a4
ZW		 3370 I915_WRITE(reg, temp);
3371
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 if (HAS_PCH_CPT(dev)) {
3375 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3376 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3377 } else {
3378 temp &= ~FDI_LINK_TRAIN_NONE;
3379 temp |= FDI_LINK_TRAIN_NONE;
3380 }
3381 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3382
3383 /* wait one idle pattern time */
3384 POSTING_READ(reg);
3385 udelay(1000);
357555c0
JB		 3386
3387 /* IVB wants error correction enabled */
3388 if (IS_IVYBRIDGE(dev))
3389 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3390 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3391}
3392
8db9d77b
ZW		 3393/* The FDI link training functions for ILK/Ibexpeak. */
3394static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 int pipe = intel_crtc->pipe;
5eddb70b 3400 u32 reg, temp, tries;
8db9d77b 3401
1c8562f6 3402 /* FDI needs bits from pipe first */
0fc932b8 3403 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3404
e1a44743
AJ		 3405 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3406 for train result */
5eddb70b
CW		 3407 reg = FDI_RX_IMR(pipe);
3408 temp = I915_READ(reg);
e1a44743
AJ		 3409 temp &= ~FDI_RX_SYMBOL_LOCK;
3410 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3411 I915_WRITE(reg, temp);
3412 I915_READ(reg);
e1a44743
AJ		 3413 udelay(150);
3414
8db9d77b 3415 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
627eb5a3 3418 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3419 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3422 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3423
5eddb70b
CW		 3424 reg = FDI_RX_CTL(pipe);
3425 temp = I915_READ(reg);
8db9d77b
ZW		 3426 temp &= ~FDI_LINK_TRAIN_NONE;
3427 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3428 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3429
3430 POSTING_READ(reg);
8db9d77b
ZW		 3431 udelay(150);
3432
5b2adf89 3433 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3434 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3435 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3436 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3437
5eddb70b 3438 reg = FDI_RX_IIR(pipe);
e1a44743 3439 for (tries = 0; tries < 5; tries++) {
5eddb70b 3440 temp = I915_READ(reg);
8db9d77b
ZW		 3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443 if ((temp & FDI_RX_BIT_LOCK)) {
3444 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3445 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3446 break;
3447 }
8db9d77b 3448 }
e1a44743 3449 if (tries == 5)
5eddb70b 3450 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3451
3452 /* Train 2 */
5eddb70b
CW		 3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3457 I915_WRITE(reg, temp);
8db9d77b 3458
5eddb70b
CW		 3459 reg = FDI_RX_CTL(pipe);
3460 temp = I915_READ(reg);
8db9d77b
ZW		 3461 temp &= ~FDI_LINK_TRAIN_NONE;
3462 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3463 I915_WRITE(reg, temp);
8db9d77b 3464
5eddb70b
CW		 3465 POSTING_READ(reg);
3466 udelay(150);
8db9d77b 3467
5eddb70b 3468 reg = FDI_RX_IIR(pipe);
e1a44743 3469 for (tries = 0; tries < 5; tries++) {
5eddb70b 3470 temp = I915_READ(reg);
8db9d77b
ZW		 3471 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3472
3473 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3474 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3475 DRM_DEBUG_KMS("FDI train 2 done.\n");
3476 break;
3477 }
8db9d77b 3478 }
e1a44743 3479 if (tries == 5)
5eddb70b 3480 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3481
3482 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3483
8db9d77b
ZW		 3484}
3485
0206e353 3486static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3487 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3488 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3489 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3490 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3491};
3492
3493/* The FDI link training functions for SNB/Cougarpoint. */
3494static void gen6_fdi_link_train(struct drm_crtc *crtc)
3495{
3496 struct drm_device *dev = crtc->dev;
3497 struct drm_i915_private *dev_priv = dev->dev_private;
3498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3499 int pipe = intel_crtc->pipe;
fa37d39e 3500 u32 reg, temp, i, retry;
8db9d77b 3501
e1a44743
AJ		 3502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3503 for train result */
5eddb70b
CW		 3504 reg = FDI_RX_IMR(pipe);
3505 temp = I915_READ(reg);
e1a44743
AJ		 3506 temp &= ~FDI_RX_SYMBOL_LOCK;
3507 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3508 I915_WRITE(reg, temp);
3509
3510 POSTING_READ(reg);
e1a44743
AJ		 3511 udelay(150);
3512
8db9d77b 3513 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3514 reg = FDI_TX_CTL(pipe);
3515 temp = I915_READ(reg);
627eb5a3 3516 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3517 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3521 /* SNB-B */
3522 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3523 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3524
d74cf324
DV		 3525 I915_WRITE(FDI_RX_MISC(pipe),
3526 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3527
5eddb70b
CW		 3528 reg = FDI_RX_CTL(pipe);
3529 temp = I915_READ(reg);
8db9d77b
ZW		 3530 if (HAS_PCH_CPT(dev)) {
3531 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3533 } else {
3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_1;
3536 }
5eddb70b
CW		 3537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3538
3539 POSTING_READ(reg);
8db9d77b
ZW		 3540 udelay(150);
3541
0206e353 3542 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
8db9d77b
ZW		 3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3547 I915_WRITE(reg, temp);
3548
3549 POSTING_READ(reg);
8db9d77b
ZW		 3550 udelay(500);
3551
fa37d39e
SP		 3552 for (retry = 0; retry < 5; retry++) {
3553 reg = FDI_RX_IIR(pipe);
3554 temp = I915_READ(reg);
3555 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3556 if (temp & FDI_RX_BIT_LOCK) {
3557 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3558 DRM_DEBUG_KMS("FDI train 1 done.\n");
3559 break;
3560 }
3561 udelay(50);
8db9d77b 3562 }
fa37d39e
SP		 3563 if (retry < 5)
3564 break;
8db9d77b
ZW		 3565 }
3566 if (i == 4)
5eddb70b 3567 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3568
3569 /* Train 2 */
5eddb70b
CW		 3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
8db9d77b
ZW		 3572 temp &= ~FDI_LINK_TRAIN_NONE;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2;
3574 if (IS_GEN6(dev)) {
3575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3576 /* SNB-B */
3577 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3578 }
5eddb70b 3579 I915_WRITE(reg, temp);
8db9d77b 3580
5eddb70b
CW		 3581 reg = FDI_RX_CTL(pipe);
3582 temp = I915_READ(reg);
8db9d77b
ZW		 3583 if (HAS_PCH_CPT(dev)) {
3584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3586 } else {
3587 temp &= ~FDI_LINK_TRAIN_NONE;
3588 temp |= FDI_LINK_TRAIN_PATTERN_2;
3589 }
5eddb70b
CW		 3590 I915_WRITE(reg, temp);
3591
3592 POSTING_READ(reg);
8db9d77b
ZW		 3593 udelay(150);
3594
0206e353 3595 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
8db9d77b
ZW		 3598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3599 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
8db9d77b
ZW		 3603 udelay(500);
3604
fa37d39e
SP		 3605 for (retry = 0; retry < 5; retry++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609 if (temp & FDI_RX_SYMBOL_LOCK) {
3610 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3611 DRM_DEBUG_KMS("FDI train 2 done.\n");
3612 break;
3613 }
3614 udelay(50);
8db9d77b 3615 }
fa37d39e
SP		 3616 if (retry < 5)
3617 break;
8db9d77b
ZW		 3618 }
3619 if (i == 4)
5eddb70b 3620 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3621
3622 DRM_DEBUG_KMS("FDI train done.\n");
3623}
3624
357555c0
JB		 3625/* Manual link training for Ivy Bridge A0 parts */
3626static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3627{
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3631 int pipe = intel_crtc->pipe;
139ccd3f 3632 u32 reg, temp, i, j;
357555c0
JB		 3633
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635 for train result */
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3641
3642 POSTING_READ(reg);
3643 udelay(150);
3644
01a415fd
DV		 3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3647
139ccd3f
JB		 3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
357555c0 3656
139ccd3f
JB		 3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
357555c0 3663
139ccd3f 3664 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
139ccd3f 3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3674
139ccd3f
JB		 3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3677
139ccd3f 3678 reg = FDI_RX_CTL(pipe);
357555c0 3679 temp = I915_READ(reg);
139ccd3f
JB		 3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3683
139ccd3f
JB		 3684 POSTING_READ(reg);
3685 udelay(1); /* should be 0.5us */
357555c0 3686
139ccd3f
JB		 3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3691
139ccd3f
JB		 3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696 i);
3697 break;
3698 }
3699 udelay(1); /* should be 0.5us */
3700 }
3701 if (i == 4) {
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703 continue;
3704 }
357555c0 3705
139ccd3f 3706 /* Train 2 */
357555c0
JB		 3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
139ccd3f
JB		 3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3717 I915_WRITE(reg, temp);
3718
3719 POSTING_READ(reg);
139ccd3f 3720 udelay(2); /* should be 1.5us */
357555c0 3721
139ccd3f
JB		 3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3726
139ccd3f
JB		 3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731 i);
3732 goto train_done;
3733 }
3734 udelay(2); /* should be 1.5us */
357555c0 3735 }
139ccd3f
JB		 3736 if (i == 4)
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3738 }
357555c0 3739
139ccd3f 3740train_done:
357555c0
JB		 3741 DRM_DEBUG_KMS("FDI train done.\n");
3742}
3743
88cefb6c 3744static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3745{
88cefb6c 3746 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3747 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3748 int pipe = intel_crtc->pipe;
5eddb70b 3749 u32 reg, temp;
79e53945 3750
c64e311e 3751
c98e9dcf 3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
627eb5a3 3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760 POSTING_READ(reg);
c98e9dcf
JB		 3761 udelay(200);
3762
3763 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767 POSTING_READ(reg);
c98e9dcf
JB		 3768 udelay(200);
3769
20749730
PZ		 3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3775
20749730
PZ		 3776 POSTING_READ(reg);
3777 udelay(100);
6be4a607 3778 }
0e23b99d
JB		 3779}
3780
88cefb6c
DV		 3781static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782{
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3786 u32 reg, temp;
3787
3788 /* Switch from PCDclk to Rawclk */
3789 reg = FDI_RX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3792
3793 /* Disable CPU FDI TX PLL */
3794 reg = FDI_TX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3797
3798 POSTING_READ(reg);
3799 udelay(100);
3800
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3804
3805 /* Wait for the clocks to turn off. */
3806 POSTING_READ(reg);
3807 udelay(100);
3808}
3809
0fc932b8
JB		 3810static void ironlake_fdi_disable(struct drm_crtc *crtc)
3811{
3812 struct drm_device *dev = crtc->dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3815 int pipe = intel_crtc->pipe;
3816 u32 reg, temp;
3817
3818 /* disable CPU FDI tx and PCH FDI rx */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3822 POSTING_READ(reg);
3823
3824 reg = FDI_RX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~(0x7 << 16);
dfd07d72 3827 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3829
3830 POSTING_READ(reg);
3831 udelay(100);
3832
3833 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3834 if (HAS_PCH_IBX(dev))
6f06ce18 3835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3836
3837 /* still set train pattern 1 */
3838 reg = FDI_TX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1;
3842 I915_WRITE(reg, temp);
3843
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 if (HAS_PCH_CPT(dev)) {
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849 } else {
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852 }
3853 /* BPC in FDI rx is consistent with that in PIPECONF */
3854 temp &= ~(0x07 << 16);
dfd07d72 3855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3856 I915_WRITE(reg, temp);
3857
3858 POSTING_READ(reg);
3859 udelay(100);
3860}
3861
5dce5b93
CW		 3862bool intel_has_pending_fb_unpin(struct drm_device *dev)
3863{
3864 struct intel_crtc *crtc;
3865
3866 /* Note that we don't need to be called with mode_config.lock here
3867 * as our list of CRTC objects is static for the lifetime of the
3868 * device and so cannot disappear as we iterate. Similarly, we can
3869 * happily treat the predicates as racy, atomic checks as userspace
3870 * cannot claim and pin a new fb without at least acquring the
3871 * struct_mutex and so serialising with us.
3872 */
d3fcc808 3873 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3874 if (atomic_read(&crtc->unpin_work_count) == 0)
3875 continue;
3876
3877 if (crtc->unpin_work)
3878 intel_wait_for_vblank(dev, crtc->pipe);
3879
3880 return true;
3881 }
3882
3883 return false;
3884}
3885
d6bbafa1
CW		 3886static void page_flip_completed(struct intel_crtc *intel_crtc)
3887{
3888 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3889 struct intel_unpin_work *work = intel_crtc->unpin_work;
3890
3891 /* ensure that the unpin work is consistent wrt ->pending. */
3892 smp_rmb();
3893 intel_crtc->unpin_work = NULL;
3894
3895 if (work->event)
3896 drm_send_vblank_event(intel_crtc->base.dev,
3897 intel_crtc->pipe,
3898 work->event);
3899
3900 drm_crtc_vblank_put(&intel_crtc->base);
3901
3902 wake_up_all(&dev_priv->pending_flip_queue);
3903 queue_work(dev_priv->wq, &work->work);
3904
3905 trace_i915_flip_complete(intel_crtc->plane,
3906 work->pending_flip_obj);
3907}
3908
46a55d30 3909void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3910{
0f91128d 3911 struct drm_device *dev = crtc->dev;
5bb61643 3912 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3913
2c10d571 3914 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3915 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3916 !intel_crtc_has_pending_flip(crtc),
3917 60*HZ) == 0)) {
3918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3919
5e2d7afc 3920 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3921 if (intel_crtc->unpin_work) {
3922 WARN_ONCE(1, "Removing stuck page flip\n");
3923 page_flip_completed(intel_crtc);
3924 }
5e2d7afc 3925 spin_unlock_irq(&dev->event_lock);
9c787942 3926 }
5bb61643 3927
975d568a
CW		 3928 if (crtc->primary->fb) {
3929 mutex_lock(&dev->struct_mutex);
3930 intel_finish_fb(crtc->primary->fb);
3931 mutex_unlock(&dev->struct_mutex);
3932 }
e6c3a2a6
CW		 3933}
3934
e615efe4
ED		 3935/* Program iCLKIP clock to the desired frequency */
3936static void lpt_program_iclkip(struct drm_crtc *crtc)
3937{
3938 struct drm_device *dev = crtc->dev;
3939 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3940 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3941 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3942 u32 temp;
3943
a580516d 3944 mutex_lock(&dev_priv->sb_lock);
09153000 3945
e615efe4
ED		 3946 /* It is necessary to ungate the pixclk gate prior to programming
3947 * the divisors, and gate it back when it is done.
3948 */
3949 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3950
3951 /* Disable SSCCTL */
3952 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3953 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3954 SBI_SSCCTL_DISABLE,
3955 SBI_ICLK);
e615efe4
ED		 3956
3957 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3958 if (clock == 20000) {
e615efe4
ED		 3959 auxdiv = 1;
3960 divsel = 0x41;
3961 phaseinc = 0x20;
3962 } else {
3963 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3964 * but the adjusted_mode->crtc_clock in in KHz. To get the
3965 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3966 * convert the virtual clock precision to KHz here for higher
3967 * precision.
3968 */
3969 u32 iclk_virtual_root_freq = 172800 * 1000;
3970 u32 iclk_pi_range = 64;
3971 u32 desired_divisor, msb_divisor_value, pi_value;
3972
12d7ceed 3973 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3974 msb_divisor_value = desired_divisor / iclk_pi_range;
3975 pi_value = desired_divisor % iclk_pi_range;
3976
3977 auxdiv = 0;
3978 divsel = msb_divisor_value - 2;
3979 phaseinc = pi_value;
3980 }
3981
3982 /* This should not happen with any sane values */
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3984 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3985 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3986 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3987
3988 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3989 clock,
e615efe4
ED		 3990 auxdiv,
3991 divsel,
3992 phasedir,
3993 phaseinc);
3994
3995 /* Program SSCDIVINTPHASE6 */
988d6ee8 3996 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3997 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3999 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4000 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4001 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4002 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4003 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4004
4005 /* Program SSCAUXDIV */
988d6ee8 4006 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4007 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4008 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4009 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4010
4011 /* Enable modulator and associated divider */
988d6ee8 4012 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4013 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4014 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4015
4016 /* Wait for initialization time */
4017 udelay(24);
4018
4019 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4020
a580516d 4021 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4022}
4023
275f01b2
DV		 4024static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4025 enum pipe pch_transcoder)
4026{
4027 struct drm_device *dev = crtc->base.dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4029 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4030
4031 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4032 I915_READ(HTOTAL(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4034 I915_READ(HBLANK(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4036 I915_READ(HSYNC(cpu_transcoder)));
4037
4038 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4039 I915_READ(VTOTAL(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4041 I915_READ(VBLANK(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4043 I915_READ(VSYNC(cpu_transcoder)));
4044 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4045 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4046}
4047
003632d9 4048static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4049{
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 uint32_t temp;
4052
4053 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4054 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4055 return;
4056
4057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4059
003632d9
ACO		 4060 temp &= ~FDI_BC_BIFURCATION_SELECT;
4061 if (enable)
4062 temp |= FDI_BC_BIFURCATION_SELECT;
4063
4064 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4065 I915_WRITE(SOUTH_CHICKEN1, temp);
4066 POSTING_READ(SOUTH_CHICKEN1);
4067}
4068
4069static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4070{
4071 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4072
4073 switch (intel_crtc->pipe) {
4074 case PIPE_A:
4075 break;
4076 case PIPE_B:
6e3c9717 4077 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4079 else
003632d9 4080 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4081
4082 break;
4083 case PIPE_C:
003632d9 4084 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4085
4086 break;
4087 default:
4088 BUG();
4089 }
4090}
4091
f67a559d
JB		 4092/*
4093 * Enable PCH resources required for PCH ports:
4094 * - PCH PLLs
4095 * - FDI training & RX/TX
4096 * - update transcoder timings
4097 * - DP transcoding bits
4098 * - transcoder
4099 */
4100static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4101{
4102 struct drm_device *dev = crtc->dev;
4103 struct drm_i915_private *dev_priv = dev->dev_private;
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 int pipe = intel_crtc->pipe;
ee7b9f93 4106 u32 reg, temp;
2c07245f 4107
ab9412ba 4108 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4109
1fbc0d78
DV		 4110 if (IS_IVYBRIDGE(dev))
4111 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4112
cd986abb
DV		 4113 /* Write the TU size bits before fdi link training, so that error
4114 * detection works. */
4115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4117
c98e9dcf 4118 /* For PCH output, training FDI link */
674cf967 4119 dev_priv->display.fdi_link_train(crtc);
2c07245f 4120
3ad8a208
DV		 4121 /* We need to program the right clock selection before writing the pixel
4122 * mutliplier into the DPLL. */
303b81e0 4123 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4124 u32 sel;
4b645f14 4125
c98e9dcf 4126 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4127 temp |= TRANS_DPLL_ENABLE(pipe);
4128 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4129 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4130 temp |= sel;
4131 else
4132 temp &= ~sel;
c98e9dcf 4133 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4134 }
5eddb70b 4135
3ad8a208
DV		 4136 /* XXX: pch pll's can be enabled any time before we enable the PCH
4137 * transcoder, and we actually should do this to not upset any PCH
4138 * transcoder that already use the clock when we share it.
4139 *
4140 * Note that enable_shared_dpll tries to do the right thing, but
4141 * get_shared_dpll unconditionally resets the pll - we need that to have
4142 * the right LVDS enable sequence. */
85b3894f 4143 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4144
d9b6cb56
JB		 4145 /* set transcoder timing, panel must allow it */
4146 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4147 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4148
303b81e0 4149 intel_fdi_normal_train(crtc);
5e84e1a4 4150
c98e9dcf 4151 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4152 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4153 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4154 reg = TRANS_DP_CTL(pipe);
4155 temp = I915_READ(reg);
4156 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4157 TRANS_DP_SYNC_MASK |
4158 TRANS_DP_BPC_MASK);
e3ef4479 4159 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4160 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4161
4162 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4163 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4164 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4165 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4166
4167 switch (intel_trans_dp_port_sel(crtc)) {
4168 case PCH_DP_B:
5eddb70b 4169 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4170 break;
4171 case PCH_DP_C:
5eddb70b 4172 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4173 break;
4174 case PCH_DP_D:
5eddb70b 4175 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4176 break;
4177 default:
e95d41e1 4178 BUG();
32f9d658 4179 }
2c07245f 4180
5eddb70b 4181 I915_WRITE(reg, temp);
6be4a607 4182 }
b52eb4dc 4183
b8a4f404 4184 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4185}
4186
1507e5bd
PZ		 4187static void lpt_pch_enable(struct drm_crtc *crtc)
4188{
4189 struct drm_device *dev = crtc->dev;
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4192 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4193
ab9412ba 4194 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4195
8c52b5e8 4196 lpt_program_iclkip(crtc);
1507e5bd 4197
0540e488 4198 /* Set transcoder timing. */
275f01b2 4199 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4200
937bb610 4201 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4202}
4203
190f68c5
ACO		 4204struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4205 struct intel_crtc_state *crtc_state)
ee7b9f93 4206{
e2b78267 4207 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4208 struct intel_shared_dpll *pll;
de419ab6 4209 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4210 enum intel_dpll_id i;
ee7b9f93 4211
de419ab6
ML		 4212 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4213
98b6bd99
DV		 4214 if (HAS_PCH_IBX(dev_priv->dev)) {
4215 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4216 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4217 pll = &dev_priv->shared_dplls[i];
98b6bd99 4218
46edb027
DV		 4219 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4220 crtc->base.base.id, pll->name);
98b6bd99 4221
de419ab6 4222 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4223
98b6bd99
DV		 4224 goto found;
4225 }
4226
bcddf610
S		 4227 if (IS_BROXTON(dev_priv->dev)) {
4228 /* PLL is attached to port in bxt */
4229 struct intel_encoder *encoder;
4230 struct intel_digital_port *intel_dig_port;
4231
4232 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4233 if (WARN_ON(!encoder))
4234 return NULL;
4235
4236 intel_dig_port = enc_to_dig_port(&encoder->base);
4237 /* 1:1 mapping between ports and PLLs */
4238 i = (enum intel_dpll_id)intel_dig_port->port;
4239 pll = &dev_priv->shared_dplls[i];
4240 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4241 crtc->base.base.id, pll->name);
de419ab6 4242 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4243
4244 goto found;
4245 }
4246
e72f9fbf
DV		 4247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4248 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4249
4250 /* Only want to check enabled timings first */
de419ab6 4251 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4252 continue;
4253
190f68c5 4254 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4255 &shared_dpll[i].hw_state,
4256 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4257 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4258 crtc->base.base.id, pll->name,
de419ab6 4259 shared_dpll[i].crtc_mask,
8bd31e67 4260 pll->active);
ee7b9f93
JB		 4261 goto found;
4262 }
4263 }
4264
4265 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4266 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4267 pll = &dev_priv->shared_dplls[i];
de419ab6 4268 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4269 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4270 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4271 goto found;
4272 }
4273 }
4274
4275 return NULL;
4276
4277found:
de419ab6
ML		 4278 if (shared_dpll[i].crtc_mask == 0)
4279 shared_dpll[i].hw_state =
4280 crtc_state->dpll_hw_state;
f2a69f44 4281
190f68c5 4282 crtc_state->shared_dpll = i;
46edb027
DV		 4283 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4284 pipe_name(crtc->pipe));
ee7b9f93 4285
de419ab6 4286 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4287
ee7b9f93
JB		 4288 return pll;
4289}
4290
de419ab6 4291static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4292{
de419ab6
ML		 4293 struct drm_i915_private *dev_priv = to_i915(state->dev);
4294 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4295 struct intel_shared_dpll *pll;
4296 enum intel_dpll_id i;
4297
de419ab6
ML		 4298 if (!to_intel_atomic_state(state)->dpll_set)
4299 return;
8bd31e67 4300
de419ab6 4301 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303 pll = &dev_priv->shared_dplls[i];
de419ab6 4304 pll->config = shared_dpll[i];
8bd31e67
ACO		 4305 }
4306}
4307
a1520318 4308static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4309{
4310 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4311 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4312 u32 temp;
4313
4314 temp = I915_READ(dslreg);
4315 udelay(500);
4316 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4317 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4318 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4319 }
4320}
4321
86adf9d7
ML		 4322static int
4323skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4324 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4325 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4326{
86adf9d7
ML		 4327 struct intel_crtc_scaler_state *scaler_state =
4328 &crtc_state->scaler_state;
4329 struct intel_crtc *intel_crtc =
4330 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4331 int need_scaling;
6156a456
CK		 4332
4333 need_scaling = intel_rotation_90_or_270(rotation) ?
4334 (src_h != dst_w || src_w != dst_h):
4335 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4336
4337 /*
4338 * if plane is being disabled or scaler is no more required or force detach
4339 * - free scaler binded to this plane/crtc
4340 * - in order to do this, update crtc->scaler_usage
4341 *
4342 * Here scaler state in crtc_state is set free so that
4343 * scaler can be assigned to other user. Actual register
4344 * update to free the scaler is done in plane/panel-fit programming.
4345 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4346 */
86adf9d7 4347 if (force_detach || !need_scaling) {
a1b2278e 4348 if (*scaler_id >= 0) {
86adf9d7 4349 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4350 scaler_state->scalers[*scaler_id].in_use = 0;
4351
86adf9d7
ML		 4352 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4353 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4354 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4355 scaler_state->scaler_users);
4356 *scaler_id = -1;
4357 }
4358 return 0;
4359 }
4360
4361 /* range checks */
4362 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4363 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4364
4365 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4366 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4367 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4368 "size is out of scaler range\n",
86adf9d7 4369 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4370 return -EINVAL;
4371 }
4372
86adf9d7
ML		 4373 /* mark this plane as a scaler user in crtc_state */
4374 scaler_state->scaler_users |= (1 << scaler_user);
4375 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4376 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4377 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4378 scaler_state->scaler_users);
4379
4380 return 0;
4381}
4382
4383/**
4384 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4385 *
4386 * @state: crtc's scaler state
86adf9d7
ML		 4387 *
4388 * Return
4389 * 0 - scaler_usage updated successfully
4390 * error - requested scaling cannot be supported or other error condition
4391 */
e435d6e5 4392int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4393{
4394 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4395 struct drm_display_mode *adjusted_mode =
4396 &state->base.adjusted_mode;
4397
4398 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4399 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4400
e435d6e5 4401 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4402 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4403 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4404 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4405}
4406
4407/**
4408 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4409 *
4410 * @state: crtc's scaler state
86adf9d7
ML		 4411 * @plane_state: atomic plane state to update
4412 *
4413 * Return
4414 * 0 - scaler_usage updated successfully
4415 * error - requested scaling cannot be supported or other error condition
4416 */
da20eabd
ML		 4417static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4418 struct intel_plane_state *plane_state)
86adf9d7
ML		 4419{
4420
4421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4422 struct intel_plane *intel_plane =
4423 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4424 struct drm_framebuffer *fb = plane_state->base.fb;
4425 int ret;
4426
4427 bool force_detach = !fb || !plane_state->visible;
4428
4429 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4430 intel_plane->base.base.id, intel_crtc->pipe,
4431 drm_plane_index(&intel_plane->base));
4432
4433 ret = skl_update_scaler(crtc_state, force_detach,
4434 drm_plane_index(&intel_plane->base),
4435 &plane_state->scaler_id,
4436 plane_state->base.rotation,
4437 drm_rect_width(&plane_state->src) >> 16,
4438 drm_rect_height(&plane_state->src) >> 16,
4439 drm_rect_width(&plane_state->dst),
4440 drm_rect_height(&plane_state->dst));
4441
4442 if (ret || plane_state->scaler_id < 0)
4443 return ret;
4444
a1b2278e 4445 /* check colorkey */
818ed961 4446 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4447 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4448 intel_plane->base.base.id);
a1b2278e
CK		 4449 return -EINVAL;
4450 }
4451
4452 /* Check src format */
86adf9d7
ML		 4453 switch (fb->pixel_format) {
4454 case DRM_FORMAT_RGB565:
4455 case DRM_FORMAT_XBGR8888:
4456 case DRM_FORMAT_XRGB8888:
4457 case DRM_FORMAT_ABGR8888:
4458 case DRM_FORMAT_ARGB8888:
4459 case DRM_FORMAT_XRGB2101010:
4460 case DRM_FORMAT_XBGR2101010:
4461 case DRM_FORMAT_YUYV:
4462 case DRM_FORMAT_YVYU:
4463 case DRM_FORMAT_UYVY:
4464 case DRM_FORMAT_VYUY:
4465 break;
4466 default:
4467 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4468 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4469 return -EINVAL;
a1b2278e
CK		 4470 }
4471
a1b2278e
CK		 4472 return 0;
4473}
4474
e435d6e5
ML		 4475static void skylake_scaler_disable(struct intel_crtc *crtc)
4476{
4477 int i;
4478
4479 for (i = 0; i < crtc->num_scalers; i++)
4480 skl_detach_scaler(crtc, i);
4481}
4482
4483static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4484{
4485 struct drm_device *dev = crtc->base.dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 int pipe = crtc->pipe;
a1b2278e
CK		 4488 struct intel_crtc_scaler_state *scaler_state =
4489 &crtc->config->scaler_state;
4490
4491 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4492
6e3c9717 4493 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4494 int id;
4495
4496 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4497 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4498 return;
4499 }
4500
4501 id = scaler_state->scaler_id;
4502 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4503 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4504 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4505 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4506
4507 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4508 }
4509}
4510
b074cec8
JB		 4511static void ironlake_pfit_enable(struct intel_crtc *crtc)
4512{
4513 struct drm_device *dev = crtc->base.dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 int pipe = crtc->pipe;
4516
6e3c9717 4517 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4518 /* Force use of hard-coded filter coefficients
4519 * as some pre-programmed values are broken,
4520 * e.g. x201.
4521 */
4522 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4523 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4524 PF_PIPE_SEL_IVB(pipe));
4525 else
4526 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4527 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4528 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4529 }
4530}
4531
20bc8673 4532void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4533{
cea165c3
VS		 4534 struct drm_device *dev = crtc->base.dev;
4535 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4536
6e3c9717 4537 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4538 return;
4539
cea165c3
VS		 4540 /* We can only enable IPS after we enable a plane and wait for a vblank */
4541 intel_wait_for_vblank(dev, crtc->pipe);
4542
d77e4531 4543 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4544 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4545 mutex_lock(&dev_priv->rps.hw_lock);
4546 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4547 mutex_unlock(&dev_priv->rps.hw_lock);
4548 /* Quoting Art Runyan: "its not safe to expect any particular
4549 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4550 * mailbox." Moreover, the mailbox may return a bogus state,
4551 * so we need to just enable it and continue on.
2a114cc1
BW		 4552 */
4553 } else {
4554 I915_WRITE(IPS_CTL, IPS_ENABLE);
4555 /* The bit only becomes 1 in the next vblank, so this wait here
4556 * is essentially intel_wait_for_vblank. If we don't have this
4557 * and don't wait for vblanks until the end of crtc_enable, then
4558 * the HW state readout code will complain that the expected
4559 * IPS_CTL value is not the one we read. */
4560 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4561 DRM_ERROR("Timed out waiting for IPS enable\n");
4562 }
d77e4531
PZ		 4563}
4564
20bc8673 4565void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4566{
4567 struct drm_device *dev = crtc->base.dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569
6e3c9717 4570 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4571 return;
4572
4573 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4574 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4575 mutex_lock(&dev_priv->rps.hw_lock);
4576 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4577 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4578 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4579 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4580 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4581 } else {
2a114cc1 4582 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4583 POSTING_READ(IPS_CTL);
4584 }
d77e4531
PZ		 4585
4586 /* We need to wait for a vblank before we can disable the plane. */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4588}
4589
4590/** Loads the palette/gamma unit for the CRTC with the prepared values */
4591static void intel_crtc_load_lut(struct drm_crtc *crtc)
4592{
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 enum pipe pipe = intel_crtc->pipe;
4597 int palreg = PALETTE(pipe);
4598 int i;
4599 bool reenable_ips = false;
4600
4601 /* The clocks have to be on to load the palette. */
53d9f4e9 4602 if (!crtc->state->active)
d77e4531
PZ		 4603 return;
4604
50360403 4605 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4606 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4607 assert_dsi_pll_enabled(dev_priv);
4608 else
4609 assert_pll_enabled(dev_priv, pipe);
4610 }
4611
4612 /* use legacy palette for Ironlake */
7a1db49a 4613 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4614 palreg = LGC_PALETTE(pipe);
4615
4616 /* Workaround : Do not read or write the pipe palette/gamma data while
4617 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4618 */
6e3c9717 4619 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4620 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4621 GAMMA_MODE_MODE_SPLIT)) {
4622 hsw_disable_ips(intel_crtc);
4623 reenable_ips = true;
4624 }
4625
4626 for (i = 0; i < 256; i++) {
4627 I915_WRITE(palreg + 4 * i,
4628 (intel_crtc->lut_r[i] << 16) |
4629 (intel_crtc->lut_g[i] << 8) |
4630 intel_crtc->lut_b[i]);
4631 }
4632
4633 if (reenable_ips)
4634 hsw_enable_ips(intel_crtc);
4635}
4636
7cac945f 4637static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4638{
7cac945f 4639 if (intel_crtc->overlay) {
d3eedb1a
VS		 4640 struct drm_device *dev = intel_crtc->base.dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642
4643 mutex_lock(&dev->struct_mutex);
4644 dev_priv->mm.interruptible = false;
4645 (void) intel_overlay_switch_off(intel_crtc->overlay);
4646 dev_priv->mm.interruptible = true;
4647 mutex_unlock(&dev->struct_mutex);
4648 }
4649
4650 /* Let userspace switch the overlay on again. In most cases userspace
4651 * has to recompute where to put it anyway.
4652 */
4653}
4654
87d4300a
ML		 4655/**
4656 * intel_post_enable_primary - Perform operations after enabling primary plane
4657 * @crtc: the CRTC whose primary plane was just enabled
4658 *
4659 * Performs potentially sleeping operations that must be done after the primary
4660 * plane is enabled, such as updating FBC and IPS. Note that this may be
4661 * called due to an explicit primary plane update, or due to an implicit
4662 * re-enable that is caused when a sprite plane is updated to no longer
4663 * completely hide the primary plane.
4664 */
4665static void
4666intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4667{
4668 struct drm_device *dev = crtc->dev;
87d4300a 4669 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4671 int pipe = intel_crtc->pipe;
a5c4d7bc 4672
87d4300a
ML		 4673 /*
4674 * BDW signals flip done immediately if the plane
4675 * is disabled, even if the plane enable is already
4676 * armed to occur at the next vblank :(
4677 */
4678 if (IS_BROADWELL(dev))
4679 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4680
87d4300a
ML		 4681 /*
4682 * FIXME IPS should be fine as long as one plane is
4683 * enabled, but in practice it seems to have problems
4684 * when going from primary only to sprite only and vice
4685 * versa.
4686 */
a5c4d7bc
VS		 4687 hsw_enable_ips(intel_crtc);
4688
f99d7069 4689 /*
87d4300a
ML		 4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4692 * are enabled.
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
f99d7069 4695 */
87d4300a
ML		 4696 if (IS_GEN2(dev))
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4702}
4703
87d4300a
ML		 4704/**
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4707 *
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4712 * plane.
4713 */
4714static void
4715intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4716{
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
a5c4d7bc 4721
87d4300a
ML		 4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4727 */
4728 if (IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4730
87d4300a
ML		 4731 /*
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4739 */
262cd2e1 4740 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4741 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4742 dev_priv->wm.vlv.cxsr = false;
4743 intel_wait_for_vblank(dev, pipe);
4744 }
87d4300a 4745
87d4300a
ML		 4746 /*
4747 * FIXME IPS should be fine as long as one plane is
4748 * enabled, but in practice it seems to have problems
4749 * when going from primary only to sprite only and vice
4750 * versa.
4751 */
a5c4d7bc 4752 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4753}
4754
ac21b225
ML		 4755static void intel_post_plane_update(struct intel_crtc *crtc)
4756{
4757 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4758 struct drm_device *dev = crtc->base.dev;
7733b49b 4759 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4760 struct drm_plane *plane;
4761
4762 if (atomic->wait_vblank)
4763 intel_wait_for_vblank(dev, crtc->pipe);
4764
4765 intel_frontbuffer_flip(dev, atomic->fb_bits);
4766
852eb00d
VS		 4767 if (atomic->disable_cxsr)
4768 crtc->wm.cxsr_allowed = true;
4769
f015c551
VS		 4770 if (crtc->atomic.update_wm_post)
4771 intel_update_watermarks(&crtc->base);
4772
c80ac854 4773 if (atomic->update_fbc)
7733b49b 4774 intel_fbc_update(dev_priv);
ac21b225
ML		 4775
4776 if (atomic->post_enable_primary)
4777 intel_post_enable_primary(&crtc->base);
4778
4779 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4780 intel_update_sprite_watermarks(plane, &crtc->base,
4781 0, 0, 0, false, false);
4782
4783 memset(atomic, 0, sizeof(*atomic));
4784}
4785
4786static void intel_pre_plane_update(struct intel_crtc *crtc)
4787{
4788 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4789 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4790 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4791 struct drm_plane *p;
4792
4793 /* Track fb's for any planes being disabled */
ac21b225
ML		 4794 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4795 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4796
4797 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4798 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4799 plane->frontbuffer_bit);
ac21b225
ML		 4800 mutex_unlock(&dev->struct_mutex);
4801 }
4802
4803 if (atomic->wait_for_flips)
4804 intel_crtc_wait_for_pending_flips(&crtc->base);
4805
c80ac854 4806 if (atomic->disable_fbc)
25ad93fd 4807 intel_fbc_disable_crtc(crtc);
ac21b225 4808
066cf55b
RV		 4809 if (crtc->atomic.disable_ips)
4810 hsw_disable_ips(crtc);
4811
ac21b225
ML		 4812 if (atomic->pre_disable_primary)
4813 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4814
4815 if (atomic->disable_cxsr) {
4816 crtc->wm.cxsr_allowed = false;
4817 intel_set_memory_cxsr(dev_priv, false);
4818 }
ac21b225
ML		 4819}
4820
d032ffa0 4821static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4822{
4823 struct drm_device *dev = crtc->dev;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4825 struct drm_plane *p;
87d4300a
ML		 4826 int pipe = intel_crtc->pipe;
4827
7cac945f 4828 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4829
d032ffa0
ML		 4830 drm_for_each_plane_mask(p, dev, plane_mask)
4831 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4832
f99d7069
DV		 4833 /*
4834 * FIXME: Once we grow proper nuclear flip support out of this we need
4835 * to compute the mask of flip planes precisely. For the time being
4836 * consider this a flip to a NULL plane.
4837 */
4838 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4839}
4840
f67a559d
JB		 4841static void ironlake_crtc_enable(struct drm_crtc *crtc)
4842{
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4846 struct intel_encoder *encoder;
f67a559d 4847 int pipe = intel_crtc->pipe;
f67a559d 4848
53d9f4e9 4849 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4850 return;
4851
6e3c9717 4852 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4853 intel_prepare_shared_dpll(intel_crtc);
4854
6e3c9717 4855 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4856 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4857
4858 intel_set_pipe_timings(intel_crtc);
4859
6e3c9717 4860 if (intel_crtc->config->has_pch_encoder) {
29407aab 4861 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4862 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4863 }
4864
4865 ironlake_set_pipeconf(crtc);
4866
f67a559d 4867 intel_crtc->active = true;
8664281b 4868
a72e4c9f
DV		 4869 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4870 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4871
f6736a1a 4872 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4873 if (encoder->pre_enable)
4874 encoder->pre_enable(encoder);
f67a559d 4875
6e3c9717 4876 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4877 /* Note: FDI PLL enabling _must_ be done before we enable the
4878 * cpu pipes, hence this is separate from all the other fdi/pch
4879 * enabling. */
88cefb6c 4880 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4881 } else {
4882 assert_fdi_tx_disabled(dev_priv, pipe);
4883 assert_fdi_rx_disabled(dev_priv, pipe);
4884 }
f67a559d 4885
b074cec8 4886 ironlake_pfit_enable(intel_crtc);
f67a559d 4887
9c54c0dd
JB		 4888 /*
4889 * On ILK+ LUT must be loaded before the pipe is running but with
4890 * clocks enabled
4891 */
4892 intel_crtc_load_lut(crtc);
4893
f37fcc2a 4894 intel_update_watermarks(crtc);
e1fdc473 4895 intel_enable_pipe(intel_crtc);
f67a559d 4896
6e3c9717 4897 if (intel_crtc->config->has_pch_encoder)
f67a559d 4898 ironlake_pch_enable(crtc);
c98e9dcf 4899
f9b61ff6
DV		 4900 assert_vblank_disabled(crtc);
4901 drm_crtc_vblank_on(crtc);
4902
fa5c73b1
DV		 4903 for_each_encoder_on_crtc(dev, crtc, encoder)
4904 encoder->enable(encoder);
61b77ddd
DV		 4905
4906 if (HAS_PCH_CPT(dev))
a1520318 4907 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4908}
4909
42db64ef
PZ		 4910/* IPS only exists on ULT machines and is tied to pipe A. */
4911static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4912{
f5adf94e 4913 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4914}
4915
4f771f10
PZ		 4916static void haswell_crtc_enable(struct drm_crtc *crtc)
4917{
4918 struct drm_device *dev = crtc->dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921 struct intel_encoder *encoder;
99d736a2
ML		 4922 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4923 struct intel_crtc_state *pipe_config =
4924 to_intel_crtc_state(crtc->state);
4f771f10 4925
53d9f4e9 4926 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4927 return;
4928
df8ad70c
DV		 4929 if (intel_crtc_to_shared_dpll(intel_crtc))
4930 intel_enable_shared_dpll(intel_crtc);
4931
6e3c9717 4932 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4933 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4934
4935 intel_set_pipe_timings(intel_crtc);
4936
6e3c9717
ACO		 4937 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4938 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4939 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4940 }
4941
6e3c9717 4942 if (intel_crtc->config->has_pch_encoder) {
229fca97 4943 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4944 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4945 }
4946
4947 haswell_set_pipeconf(crtc);
4948
4949 intel_set_pipe_csc(crtc);
4950
4f771f10 4951 intel_crtc->active = true;
8664281b 4952
a72e4c9f 4953 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4954 for_each_encoder_on_crtc(dev, crtc, encoder)
4955 if (encoder->pre_enable)
4956 encoder->pre_enable(encoder);
4957
6e3c9717 4958 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4959 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4960 true);
4fe9467d
ID		 4961 dev_priv->display.fdi_link_train(crtc);
4962 }
4963
1f544388 4964 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4965
ff6d9f55 4966 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4967 skylake_pfit_enable(intel_crtc);
ff6d9f55 4968 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4969 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4970 else
4971 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4972
4973 /*
4974 * On ILK+ LUT must be loaded before the pipe is running but with
4975 * clocks enabled
4976 */
4977 intel_crtc_load_lut(crtc);
4978
1f544388 4979 intel_ddi_set_pipe_settings(crtc);
8228c251 4980 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4981
f37fcc2a 4982 intel_update_watermarks(crtc);
e1fdc473 4983 intel_enable_pipe(intel_crtc);
42db64ef 4984
6e3c9717 4985 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4986 lpt_pch_enable(crtc);
4f771f10 4987
6e3c9717 4988 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4989 intel_ddi_set_vc_payload_alloc(crtc, true);
4990
f9b61ff6
DV		 4991 assert_vblank_disabled(crtc);
4992 drm_crtc_vblank_on(crtc);
4993
8807e55b 4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4995 encoder->enable(encoder);
8807e55b
JN		 4996 intel_opregion_notify_encoder(encoder, true);
4997 }
4f771f10 4998
e4916946
PZ		 4999 /* If we change the relative order between pipe/planes enabling, we need
5000 * to change the workaround. */
99d736a2
ML		 5001 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5002 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5003 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5004 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5005 }
4f771f10
PZ		 5006}
5007
3f8dce3a
DV		 5008static void ironlake_pfit_disable(struct intel_crtc *crtc)
5009{
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 int pipe = crtc->pipe;
5013
5014 /* To avoid upsetting the power well on haswell only disable the pfit if
5015 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5016 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5017 I915_WRITE(PF_CTL(pipe), 0);
5018 I915_WRITE(PF_WIN_POS(pipe), 0);
5019 I915_WRITE(PF_WIN_SZ(pipe), 0);
5020 }
5021}
5022
6be4a607
JB		 5023static void ironlake_crtc_disable(struct drm_crtc *crtc)
5024{
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5028 struct intel_encoder *encoder;
6be4a607 5029 int pipe = intel_crtc->pipe;
5eddb70b 5030 u32 reg, temp;
b52eb4dc 5031
ea9d758d
DV		 5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 encoder->disable(encoder);
5034
f9b61ff6
DV		 5035 drm_crtc_vblank_off(crtc);
5036 assert_vblank_disabled(crtc);
5037
6e3c9717 5038 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5039 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5040
575f7ab7 5041 intel_disable_pipe(intel_crtc);
32f9d658 5042
3f8dce3a 5043 ironlake_pfit_disable(intel_crtc);
2c07245f 5044
5a74f70a
VS		 5045 if (intel_crtc->config->has_pch_encoder)
5046 ironlake_fdi_disable(crtc);
5047
bf49ec8c
DV		 5048 for_each_encoder_on_crtc(dev, crtc, encoder)
5049 if (encoder->post_disable)
5050 encoder->post_disable(encoder);
2c07245f 5051
6e3c9717 5052 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5053 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5054
d925c59a
DV		 5055 if (HAS_PCH_CPT(dev)) {
5056 /* disable TRANS_DP_CTL */
5057 reg = TRANS_DP_CTL(pipe);
5058 temp = I915_READ(reg);
5059 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5060 TRANS_DP_PORT_SEL_MASK);
5061 temp |= TRANS_DP_PORT_SEL_NONE;
5062 I915_WRITE(reg, temp);
5063
5064 /* disable DPLL_SEL */
5065 temp = I915_READ(PCH_DPLL_SEL);
11887397 5066 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5067 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5068 }
e3421a18 5069
d925c59a
DV		 5070 ironlake_fdi_pll_disable(intel_crtc);
5071 }
e4ca0612
PJ		 5072
5073 intel_crtc->active = false;
5074 intel_update_watermarks(crtc);
6be4a607 5075}
1b3c7a47 5076
4f771f10 5077static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5078{
4f771f10
PZ		 5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5082 struct intel_encoder *encoder;
6e3c9717 5083 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5084
8807e55b
JN		 5085 for_each_encoder_on_crtc(dev, crtc, encoder) {
5086 intel_opregion_notify_encoder(encoder, false);
4f771f10 5087 encoder->disable(encoder);
8807e55b 5088 }
4f771f10 5089
f9b61ff6
DV		 5090 drm_crtc_vblank_off(crtc);
5091 assert_vblank_disabled(crtc);
5092
6e3c9717 5093 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5094 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5095 false);
575f7ab7 5096 intel_disable_pipe(intel_crtc);
4f771f10 5097
6e3c9717 5098 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5099 intel_ddi_set_vc_payload_alloc(crtc, false);
5100
ad80a810 5101 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5102
ff6d9f55 5103 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5104 skylake_scaler_disable(intel_crtc);
ff6d9f55 5105 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5106 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5107 else
5108 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5109
1f544388 5110 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5111
6e3c9717 5112 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5113 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5114 intel_ddi_fdi_disable(crtc);
83616634 5115 }
4f771f10 5116
97b040aa
ID		 5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 if (encoder->post_disable)
5119 encoder->post_disable(encoder);
e4ca0612
PJ		 5120
5121 intel_crtc->active = false;
5122 intel_update_watermarks(crtc);
4f771f10
PZ		 5123}
5124
2dd24552
JB		 5125static void i9xx_pfit_enable(struct intel_crtc *crtc)
5126{
5127 struct drm_device *dev = crtc->base.dev;
5128 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5129 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5130
681a8504 5131 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5132 return;
5133
2dd24552 5134 /*
c0b03411
DV		 5135 * The panel fitter should only be adjusted whilst the pipe is disabled,
5136 * according to register description and PRM.
2dd24552 5137 */
c0b03411
DV		 5138 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5139 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5140
b074cec8
JB		 5141 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5142 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5143
5144 /* Border color in case we don't scale up to the full screen. Black by
5145 * default, change to something else for debugging. */
5146 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5147}
5148
d05410f9
DA		 5149static enum intel_display_power_domain port_to_power_domain(enum port port)
5150{
5151 switch (port) {
5152 case PORT_A:
5153 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5154 case PORT_B:
5155 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5156 case PORT_C:
5157 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5158 case PORT_D:
5159 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5160 case PORT_E:
5161 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5162 default:
5163 WARN_ON_ONCE(1);
5164 return POWER_DOMAIN_PORT_OTHER;
5165 }
5166}
5167
77d22dca
ID		 5168#define for_each_power_domain(domain, mask) \
5169 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5170 if ((1 << (domain)) & (mask))
5171
319be8ae
ID		 5172enum intel_display_power_domain
5173intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5174{
5175 struct drm_device *dev = intel_encoder->base.dev;
5176 struct intel_digital_port *intel_dig_port;
5177
5178 switch (intel_encoder->type) {
5179 case INTEL_OUTPUT_UNKNOWN:
5180 /* Only DDI platforms should ever use this output type */
5181 WARN_ON_ONCE(!HAS_DDI(dev));
5182 case INTEL_OUTPUT_DISPLAYPORT:
5183 case INTEL_OUTPUT_HDMI:
5184 case INTEL_OUTPUT_EDP:
5185 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5186 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5187 case INTEL_OUTPUT_DP_MST:
5188 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5189 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5190 case INTEL_OUTPUT_ANALOG:
5191 return POWER_DOMAIN_PORT_CRT;
5192 case INTEL_OUTPUT_DSI:
5193 return POWER_DOMAIN_PORT_DSI;
5194 default:
5195 return POWER_DOMAIN_PORT_OTHER;
5196 }
5197}
5198
5199static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5200{
319be8ae
ID		 5201 struct drm_device *dev = crtc->dev;
5202 struct intel_encoder *intel_encoder;
5203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5205 unsigned long mask;
5206 enum transcoder transcoder;
5207
292b990e
ML		 5208 if (!crtc->state->active)
5209 return 0;
5210
77d22dca
ID		 5211 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5212
5213 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5214 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5215 if (intel_crtc->config->pch_pfit.enabled ||
5216 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5217 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5218
319be8ae
ID		 5219 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5220 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5221
77d22dca
ID		 5222 return mask;
5223}
5224
292b990e 5225static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5226{
292b990e
ML		 5227 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5229 enum intel_display_power_domain domain;
5230 unsigned long domains, new_domains, old_domains;
77d22dca 5231
292b990e
ML		 5232 old_domains = intel_crtc->enabled_power_domains;
5233 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5234
292b990e
ML		 5235 domains = new_domains & ~old_domains;
5236
5237 for_each_power_domain(domain, domains)
5238 intel_display_power_get(dev_priv, domain);
5239
5240 return old_domains & ~new_domains;
5241}
5242
5243static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5244 unsigned long domains)
5245{
5246 enum intel_display_power_domain domain;
5247
5248 for_each_power_domain(domain, domains)
5249 intel_display_power_put(dev_priv, domain);
5250}
77d22dca 5251
292b990e
ML		 5252static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5253{
5254 struct drm_device *dev = state->dev;
5255 struct drm_i915_private *dev_priv = dev->dev_private;
5256 unsigned long put_domains[I915_MAX_PIPES] = {};
5257 struct drm_crtc_state *crtc_state;
5258 struct drm_crtc *crtc;
5259 int i;
77d22dca 5260
292b990e
ML		 5261 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5262 if (needs_modeset(crtc->state))
5263 put_domains[to_intel_crtc(crtc)->pipe] =
5264 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5265 }
5266
27c329ed
ML		 5267 if (dev_priv->display.modeset_commit_cdclk) {
5268 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5269
5270 if (cdclk != dev_priv->cdclk_freq &&
5271 !WARN_ON(!state->allow_modeset))
5272 dev_priv->display.modeset_commit_cdclk(state);
5273 }
50f6e502 5274
292b990e
ML		 5275 for (i = 0; i < I915_MAX_PIPES; i++)
5276 if (put_domains[i])
5277 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5278}
5279
560a7ae4
DL		 5280static void intel_update_max_cdclk(struct drm_device *dev)
5281{
5282 struct drm_i915_private *dev_priv = dev->dev_private;
5283
5284 if (IS_SKYLAKE(dev)) {
5285 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5286
5287 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5288 dev_priv->max_cdclk_freq = 675000;
5289 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5290 dev_priv->max_cdclk_freq = 540000;
5291 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5292 dev_priv->max_cdclk_freq = 450000;
5293 else
5294 dev_priv->max_cdclk_freq = 337500;
5295 } else if (IS_BROADWELL(dev)) {
5296 /*
5297 * FIXME with extra cooling we can allow
5298 * 540 MHz for ULX and 675 Mhz for ULT.
5299 * How can we know if extra cooling is
5300 * available? PCI ID, VTB, something else?
5301 */
5302 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5303 dev_priv->max_cdclk_freq = 450000;
5304 else if (IS_BDW_ULX(dev))
5305 dev_priv->max_cdclk_freq = 450000;
5306 else if (IS_BDW_ULT(dev))
5307 dev_priv->max_cdclk_freq = 540000;
5308 else
5309 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5310 } else if (IS_CHERRYVIEW(dev)) {
5311 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5312 } else if (IS_VALLEYVIEW(dev)) {
5313 dev_priv->max_cdclk_freq = 400000;
5314 } else {
5315 /* otherwise assume cdclk is fixed */
5316 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5317 }
5318
5319 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5320 dev_priv->max_cdclk_freq);
5321}
5322
5323static void intel_update_cdclk(struct drm_device *dev)
5324{
5325 struct drm_i915_private *dev_priv = dev->dev_private;
5326
5327 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5328 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5329 dev_priv->cdclk_freq);
5330
5331 /*
5332 * Program the gmbus_freq based on the cdclk frequency.
5333 * BSpec erroneously claims we should aim for 4MHz, but
5334 * in fact 1MHz is the correct frequency.
5335 */
5336 if (IS_VALLEYVIEW(dev)) {
5337 /*
5338 * Program the gmbus_freq based on the cdclk frequency.
5339 * BSpec erroneously claims we should aim for 4MHz, but
5340 * in fact 1MHz is the correct frequency.
5341 */
5342 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5343 }
5344
5345 if (dev_priv->max_cdclk_freq == 0)
5346 intel_update_max_cdclk(dev);
5347}
5348
70d0c574 5349static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5350{
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 uint32_t divider;
5353 uint32_t ratio;
5354 uint32_t current_freq;
5355 int ret;
5356
5357 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5358 switch (frequency) {
5359 case 144000:
5360 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5361 ratio = BXT_DE_PLL_RATIO(60);
5362 break;
5363 case 288000:
5364 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5365 ratio = BXT_DE_PLL_RATIO(60);
5366 break;
5367 case 384000:
5368 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5369 ratio = BXT_DE_PLL_RATIO(60);
5370 break;
5371 case 576000:
5372 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5373 ratio = BXT_DE_PLL_RATIO(60);
5374 break;
5375 case 624000:
5376 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5377 ratio = BXT_DE_PLL_RATIO(65);
5378 break;
5379 case 19200:
5380 /*
5381 * Bypass frequency with DE PLL disabled. Init ratio, divider
5382 * to suppress GCC warning.
5383 */
5384 ratio = 0;
5385 divider = 0;
5386 break;
5387 default:
5388 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5389
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->rps.hw_lock);
5394 /* Inform power controller of upcoming frequency change */
5395 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5396 0x80000000);
5397 mutex_unlock(&dev_priv->rps.hw_lock);
5398
5399 if (ret) {
5400 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5401 ret, frequency);
5402 return;
5403 }
5404
5405 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5406 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5407 current_freq = current_freq * 500 + 1000;
5408
5409 /*
5410 * DE PLL has to be disabled when
5411 * - setting to 19.2MHz (bypass, PLL isn't used)
5412 * - before setting to 624MHz (PLL needs toggling)
5413 * - before setting to any frequency from 624MHz (PLL needs toggling)
5414 */
5415 if (frequency == 19200 || frequency == 624000 ||
5416 current_freq == 624000) {
5417 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5418 /* Timeout 200us */
5419 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5420 1))
5421 DRM_ERROR("timout waiting for DE PLL unlock\n");
5422 }
5423
5424 if (frequency != 19200) {
5425 uint32_t val;
5426
5427 val = I915_READ(BXT_DE_PLL_CTL);
5428 val &= ~BXT_DE_PLL_RATIO_MASK;
5429 val |= ratio;
5430 I915_WRITE(BXT_DE_PLL_CTL, val);
5431
5432 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5433 /* Timeout 200us */
5434 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5435 DRM_ERROR("timeout waiting for DE PLL lock\n");
5436
5437 val = I915_READ(CDCLK_CTL);
5438 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5439 val |= divider;
5440 /*
5441 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5442 * enable otherwise.
5443 */
5444 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5445 if (frequency >= 500000)
5446 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447
5448 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5449 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5450 val |= (frequency - 1000) / 500;
5451 I915_WRITE(CDCLK_CTL, val);
5452 }
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5456 DIV_ROUND_UP(frequency, 25000));
5457 mutex_unlock(&dev_priv->rps.hw_lock);
5458
5459 if (ret) {
5460 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5461 ret, frequency);
5462 return;
5463 }
5464
a47871bd 5465 intel_update_cdclk(dev);
f8437dd1
VK		 5466}
5467
5468void broxton_init_cdclk(struct drm_device *dev)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 uint32_t val;
5472
5473 /*
5474 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5475 * or else the reset will hang because there is no PCH to respond.
5476 * Move the handshake programming to initialization sequence.
5477 * Previously was left up to BIOS.
5478 */
5479 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5480 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5481 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5482
5483 /* Enable PG1 for cdclk */
5484 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5485
5486 /* check if cd clock is enabled */
5487 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5488 DRM_DEBUG_KMS("Display already initialized\n");
5489 return;
5490 }
5491
5492 /*
5493 * FIXME:
5494 * - The initial CDCLK needs to be read from VBT.
5495 * Need to make this change after VBT has changes for BXT.
5496 * - check if setting the max (or any) cdclk freq is really necessary
5497 * here, it belongs to modeset time
5498 */
5499 broxton_set_cdclk(dev, 624000);
5500
5501 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5502 POSTING_READ(DBUF_CTL);
5503
f8437dd1
VK		 5504 udelay(10);
5505
5506 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5507 DRM_ERROR("DBuf power enable timeout!\n");
5508}
5509
5510void broxton_uninit_cdclk(struct drm_device *dev)
5511{
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5515 POSTING_READ(DBUF_CTL);
5516
f8437dd1
VK		 5517 udelay(10);
5518
5519 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5520 DRM_ERROR("DBuf power disable timeout!\n");
5521
5522 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5523 broxton_set_cdclk(dev, 19200);
5524
5525 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5526}
5527
5d96d8af
DL		 5528static const struct skl_cdclk_entry {
5529 unsigned int freq;
5530 unsigned int vco;
5531} skl_cdclk_frequencies[] = {
5532 { .freq = 308570, .vco = 8640 },
5533 { .freq = 337500, .vco = 8100 },
5534 { .freq = 432000, .vco = 8640 },
5535 { .freq = 450000, .vco = 8100 },
5536 { .freq = 540000, .vco = 8100 },
5537 { .freq = 617140, .vco = 8640 },
5538 { .freq = 675000, .vco = 8100 },
5539};
5540
5541static unsigned int skl_cdclk_decimal(unsigned int freq)
5542{
5543 return (freq - 1000) / 500;
5544}
5545
5546static unsigned int skl_cdclk_get_vco(unsigned int freq)
5547{
5548 unsigned int i;
5549
5550 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5551 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5552
5553 if (e->freq == freq)
5554 return e->vco;
5555 }
5556
5557 return 8100;
5558}
5559
5560static void
5561skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5562{
5563 unsigned int min_freq;
5564 u32 val;
5565
5566 /* select the minimum CDCLK before enabling DPLL 0 */
5567 val = I915_READ(CDCLK_CTL);
5568 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5569 val |= CDCLK_FREQ_337_308;
5570
5571 if (required_vco == 8640)
5572 min_freq = 308570;
5573 else
5574 min_freq = 337500;
5575
5576 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5577
5578 I915_WRITE(CDCLK_CTL, val);
5579 POSTING_READ(CDCLK_CTL);
5580
5581 /*
5582 * We always enable DPLL0 with the lowest link rate possible, but still
5583 * taking into account the VCO required to operate the eDP panel at the
5584 * desired frequency. The usual DP link rates operate with a VCO of
5585 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5586 * The modeset code is responsible for the selection of the exact link
5587 * rate later on, with the constraint of choosing a frequency that
5588 * works with required_vco.
5589 */
5590 val = I915_READ(DPLL_CTRL1);
5591
5592 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5593 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5594 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5595 if (required_vco == 8640)
5596 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5597 SKL_DPLL0);
5598 else
5599 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5600 SKL_DPLL0);
5601
5602 I915_WRITE(DPLL_CTRL1, val);
5603 POSTING_READ(DPLL_CTRL1);
5604
5605 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5606
5607 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5608 DRM_ERROR("DPLL0 not locked\n");
5609}
5610
5611static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5612{
5613 int ret;
5614 u32 val;
5615
5616 /* inform PCU we want to change CDCLK */
5617 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5618 mutex_lock(&dev_priv->rps.hw_lock);
5619 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5620 mutex_unlock(&dev_priv->rps.hw_lock);
5621
5622 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5623}
5624
5625static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5626{
5627 unsigned int i;
5628
5629 for (i = 0; i < 15; i++) {
5630 if (skl_cdclk_pcu_ready(dev_priv))
5631 return true;
5632 udelay(10);
5633 }
5634
5635 return false;
5636}
5637
5638static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5639{
560a7ae4 5640 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5641 u32 freq_select, pcu_ack;
5642
5643 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5644
5645 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5646 DRM_ERROR("failed to inform PCU about cdclk change\n");
5647 return;
5648 }
5649
5650 /* set CDCLK_CTL */
5651 switch(freq) {
5652 case 450000:
5653 case 432000:
5654 freq_select = CDCLK_FREQ_450_432;
5655 pcu_ack = 1;
5656 break;
5657 case 540000:
5658 freq_select = CDCLK_FREQ_540;
5659 pcu_ack = 2;
5660 break;
5661 case 308570:
5662 case 337500:
5663 default:
5664 freq_select = CDCLK_FREQ_337_308;
5665 pcu_ack = 0;
5666 break;
5667 case 617140:
5668 case 675000:
5669 freq_select = CDCLK_FREQ_675_617;
5670 pcu_ack = 3;
5671 break;
5672 }
5673
5674 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5675 POSTING_READ(CDCLK_CTL);
5676
5677 /* inform PCU of the change */
5678 mutex_lock(&dev_priv->rps.hw_lock);
5679 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5680 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5681
5682 intel_update_cdclk(dev);
5d96d8af
DL		 5683}
5684
5685void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5686{
5687 /* disable DBUF power */
5688 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5689 POSTING_READ(DBUF_CTL);
5690
5691 udelay(10);
5692
5693 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5694 DRM_ERROR("DBuf power disable timeout\n");
5695
5696 /* disable DPLL0 */
5697 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5698 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5699 DRM_ERROR("Couldn't disable DPLL0\n");
5700
5701 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5702}
5703
5704void skl_init_cdclk(struct drm_i915_private *dev_priv)
5705{
5706 u32 val;
5707 unsigned int required_vco;
5708
5709 /* enable PCH reset handshake */
5710 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5711 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5712
5713 /* enable PG1 and Misc I/O */
5714 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5715
39d9b85a
GW		 5716 /* DPLL0 not enabled (happens on early BIOS versions) */
5717 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5718 /* enable DPLL0 */
5719 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5720 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5721 }
5722
5d96d8af
DL		 5723 /* set CDCLK to the frequency the BIOS chose */
5724 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5725
5726 /* enable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5733 DRM_ERROR("DBuf power enable timeout\n");
5734}
5735
dfcab17e 5736/* returns HPLL frequency in kHz */
f8bf63fd 5737static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5738{
586f49dc 5739 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5740
586f49dc 5741 /* Obtain SKU information */
a580516d 5742 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5743 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5744 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5745 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5746
dfcab17e 5747 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5748}
5749
5750/* Adjust CDclk dividers to allow high res or save power if possible */
5751static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5752{
5753 struct drm_i915_private *dev_priv = dev->dev_private;
5754 u32 val, cmd;
5755
164dfd28
VK		 5756 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5757 != dev_priv->cdclk_freq);
d60c4473 5758
dfcab17e 5759 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5760 cmd = 2;
dfcab17e 5761 else if (cdclk == 266667)
30a970c6
JB		 5762 cmd = 1;
5763 else
5764 cmd = 0;
5765
5766 mutex_lock(&dev_priv->rps.hw_lock);
5767 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5768 val &= ~DSPFREQGUAR_MASK;
5769 val |= (cmd << DSPFREQGUAR_SHIFT);
5770 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5771 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5772 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5773 50)) {
5774 DRM_ERROR("timed out waiting for CDclk change\n");
5775 }
5776 mutex_unlock(&dev_priv->rps.hw_lock);
5777
54433e91
VS		 5778 mutex_lock(&dev_priv->sb_lock);
5779
dfcab17e 5780 if (cdclk == 400000) {
6bcda4f0 5781 u32 divider;
30a970c6 5782
6bcda4f0 5783 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5784
30a970c6
JB		 5785 /* adjust cdclk divider */
5786 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5787 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5788 val |= divider;
5789 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5790
5791 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5792 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5793 50))
5794 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5795 }
5796
30a970c6
JB		 5797 /* adjust self-refresh exit latency value */
5798 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5799 val &= ~0x7f;
5800
5801 /*
5802 * For high bandwidth configs, we set a higher latency in the bunit
5803 * so that the core display fetch happens in time to avoid underruns.
5804 */
dfcab17e 5805 if (cdclk == 400000)
30a970c6
JB		 5806 val |= 4500 / 250; /* 4.5 usec */
5807 else
5808 val |= 3000 / 250; /* 3.0 usec */
5809 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5810
a580516d 5811 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5812
b6283055 5813 intel_update_cdclk(dev);
30a970c6
JB		 5814}
5815
383c5a6a
VS		 5816static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5817{
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 u32 val, cmd;
5820
164dfd28
VK		 5821 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5822 != dev_priv->cdclk_freq);
383c5a6a
VS		 5823
5824 switch (cdclk) {
383c5a6a
VS		 5825 case 333333:
5826 case 320000:
383c5a6a 5827 case 266667:
383c5a6a 5828 case 200000:
383c5a6a
VS		 5829 break;
5830 default:
5f77eeb0 5831 MISSING_CASE(cdclk);
383c5a6a
VS		 5832 return;
5833 }
5834
9d0d3fda
VS		 5835 /*
5836 * Specs are full of misinformation, but testing on actual
5837 * hardware has shown that we just need to write the desired
5838 * CCK divider into the Punit register.
5839 */
5840 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5841
383c5a6a
VS		 5842 mutex_lock(&dev_priv->rps.hw_lock);
5843 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5844 val &= ~DSPFREQGUAR_MASK_CHV;
5845 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5846 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5847 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5848 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5849 50)) {
5850 DRM_ERROR("timed out waiting for CDclk change\n");
5851 }
5852 mutex_unlock(&dev_priv->rps.hw_lock);
5853
b6283055 5854 intel_update_cdclk(dev);
383c5a6a
VS		 5855}
5856
30a970c6
JB		 5857static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5858 int max_pixclk)
5859{
6bcda4f0 5860 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5861 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5862
30a970c6
JB		 5863 /*
5864 * Really only a few cases to deal with, as only 4 CDclks are supported:
5865 * 200MHz
5866 * 267MHz
29dc7ef3 5867 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5868 * 400MHz (VLV only)
5869 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5870 * of the lower bin and adjust if needed.
e37c67a1
VS		 5871 *
5872 * We seem to get an unstable or solid color picture at 200MHz.
5873 * Not sure what's wrong. For now use 200MHz only when all pipes
5874 * are off.
30a970c6 5875 */
6cca3195
VS		 5876 if (!IS_CHERRYVIEW(dev_priv) &&
5877 max_pixclk > freq_320*limit/100)
dfcab17e 5878 return 400000;
6cca3195 5879 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5880 return freq_320;
e37c67a1 5881 else if (max_pixclk > 0)
dfcab17e 5882 return 266667;
e37c67a1
VS		 5883 else
5884 return 200000;
30a970c6
JB		 5885}
5886
f8437dd1
VK		 5887static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5888 int max_pixclk)
5889{
5890 /*
5891 * FIXME:
5892 * - remove the guardband, it's not needed on BXT
5893 * - set 19.2MHz bypass frequency if there are no active pipes
5894 */
5895 if (max_pixclk > 576000*9/10)
5896 return 624000;
5897 else if (max_pixclk > 384000*9/10)
5898 return 576000;
5899 else if (max_pixclk > 288000*9/10)
5900 return 384000;
5901 else if (max_pixclk > 144000*9/10)
5902 return 288000;
5903 else
5904 return 144000;
5905}
5906
a821fc46
ACO		 5907/* Compute the max pixel clock for new configuration. Uses atomic state if
5908 * that's non-NULL, look at current state otherwise. */
5909static int intel_mode_max_pixclk(struct drm_device *dev,
5910 struct drm_atomic_state *state)
30a970c6 5911{
30a970c6 5912 struct intel_crtc *intel_crtc;
304603f4 5913 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5914 int max_pixclk = 0;
5915
d3fcc808 5916 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5917 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5918 if (IS_ERR(crtc_state))
5919 return PTR_ERR(crtc_state);
5920
5921 if (!crtc_state->base.enable)
5922 continue;
5923
5924 max_pixclk = max(max_pixclk,
5925 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5926 }
5927
5928 return max_pixclk;
5929}
5930
27c329ed 5931static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5932{
27c329ed
ML		 5933 struct drm_device *dev = state->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5936
304603f4
ACO		 5937 if (max_pixclk < 0)
5938 return max_pixclk;
30a970c6 5939
27c329ed
ML		 5940 to_intel_atomic_state(state)->cdclk =
5941 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5942
27c329ed
ML		 5943 return 0;
5944}
304603f4 5945
27c329ed
ML		 5946static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5947{
5948 struct drm_device *dev = state->dev;
5949 struct drm_i915_private *dev_priv = dev->dev_private;
5950 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5951
27c329ed
ML		 5952 if (max_pixclk < 0)
5953 return max_pixclk;
85a96e7a 5954
27c329ed
ML		 5955 to_intel_atomic_state(state)->cdclk =
5956 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5957
27c329ed 5958 return 0;
30a970c6
JB		 5959}
5960
1e69cd74
VS		 5961static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5962{
5963 unsigned int credits, default_credits;
5964
5965 if (IS_CHERRYVIEW(dev_priv))
5966 default_credits = PFI_CREDIT(12);
5967 else
5968 default_credits = PFI_CREDIT(8);
5969
164dfd28 5970 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5971 /* CHV suggested value is 31 or 63 */
5972 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5973 credits = PFI_CREDIT_63;
1e69cd74
VS		 5974 else
5975 credits = PFI_CREDIT(15);
5976 } else {
5977 credits = default_credits;
5978 }
5979
5980 /*
5981 * WA - write default credits before re-programming
5982 * FIXME: should we also set the resend bit here?
5983 */
5984 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985 default_credits);
5986
5987 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5988 credits | PFI_CREDIT_RESEND);
5989
5990 /*
5991 * FIXME is this guaranteed to clear
5992 * immediately or should we poll for it?
5993 */
5994 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5995}
5996
27c329ed 5997static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5998{
a821fc46 5999 struct drm_device *dev = old_state->dev;
27c329ed 6000 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6001 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6002
27c329ed
ML		 6003 /*
6004 * FIXME: We can end up here with all power domains off, yet
6005 * with a CDCLK frequency other than the minimum. To account
6006 * for this take the PIPE-A power domain, which covers the HW
6007 * blocks needed for the following programming. This can be
6008 * removed once it's guaranteed that we get here either with
6009 * the minimum CDCLK set, or the required power domains
6010 * enabled.
6011 */
6012 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6013
27c329ed
ML		 6014 if (IS_CHERRYVIEW(dev))
6015 cherryview_set_cdclk(dev, req_cdclk);
6016 else
6017 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6018
27c329ed 6019 vlv_program_pfi_credits(dev_priv);
1e69cd74 6020
27c329ed 6021 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6022}
6023
89b667f8
JB		 6024static void valleyview_crtc_enable(struct drm_crtc *crtc)
6025{
6026 struct drm_device *dev = crtc->dev;
a72e4c9f 6027 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6029 struct intel_encoder *encoder;
6030 int pipe = intel_crtc->pipe;
23538ef1 6031 bool is_dsi;
89b667f8 6032
53d9f4e9 6033 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6034 return;
6035
409ee761 6036 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6037
1ae0d137
VS		 6038 if (!is_dsi) {
6039 if (IS_CHERRYVIEW(dev))
6e3c9717 6040 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6041 else
6e3c9717 6042 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6043 }
5b18e57c 6044
6e3c9717 6045 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6046 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6047
6048 intel_set_pipe_timings(intel_crtc);
6049
c14b0485
VS		 6050 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6051 struct drm_i915_private *dev_priv = dev->dev_private;
6052
6053 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6054 I915_WRITE(CHV_CANVAS(pipe), 0);
6055 }
6056
5b18e57c
DV		 6057 i9xx_set_pipeconf(intel_crtc);
6058
89b667f8 6059 intel_crtc->active = true;
89b667f8 6060
a72e4c9f 6061 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6062
89b667f8
JB		 6063 for_each_encoder_on_crtc(dev, crtc, encoder)
6064 if (encoder->pre_pll_enable)
6065 encoder->pre_pll_enable(encoder);
6066
9d556c99
CML		 6067 if (!is_dsi) {
6068 if (IS_CHERRYVIEW(dev))
6e3c9717 6069 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6070 else
6e3c9717 6071 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6072 }
89b667f8
JB		 6073
6074 for_each_encoder_on_crtc(dev, crtc, encoder)
6075 if (encoder->pre_enable)
6076 encoder->pre_enable(encoder);
6077
2dd24552
JB		 6078 i9xx_pfit_enable(intel_crtc);
6079
63cbb074
VS		 6080 intel_crtc_load_lut(crtc);
6081
e1fdc473 6082 intel_enable_pipe(intel_crtc);
be6a6f8e 6083
4b3a9526
VS		 6084 assert_vblank_disabled(crtc);
6085 drm_crtc_vblank_on(crtc);
6086
f9b61ff6
DV		 6087 for_each_encoder_on_crtc(dev, crtc, encoder)
6088 encoder->enable(encoder);
89b667f8
JB		 6089}
6090
f13c2ef3
DV		 6091static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6092{
6093 struct drm_device *dev = crtc->base.dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095
6e3c9717
ACO		 6096 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6097 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6098}
6099
0b8765c6 6100static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6101{
6102 struct drm_device *dev = crtc->dev;
a72e4c9f 6103 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6105 struct intel_encoder *encoder;
79e53945 6106 int pipe = intel_crtc->pipe;
79e53945 6107
53d9f4e9 6108 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6109 return;
6110
f13c2ef3
DV		 6111 i9xx_set_pll_dividers(intel_crtc);
6112
6e3c9717 6113 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6114 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6115
6116 intel_set_pipe_timings(intel_crtc);
6117
5b18e57c
DV		 6118 i9xx_set_pipeconf(intel_crtc);
6119
f7abfe8b 6120 intel_crtc->active = true;
6b383a7f 6121
4a3436e8 6122 if (!IS_GEN2(dev))
a72e4c9f 6123 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6124
9d6d9f19
MK		 6125 for_each_encoder_on_crtc(dev, crtc, encoder)
6126 if (encoder->pre_enable)
6127 encoder->pre_enable(encoder);
6128
f6736a1a
DV		 6129 i9xx_enable_pll(intel_crtc);
6130
2dd24552
JB		 6131 i9xx_pfit_enable(intel_crtc);
6132
63cbb074
VS		 6133 intel_crtc_load_lut(crtc);
6134
f37fcc2a 6135 intel_update_watermarks(crtc);
e1fdc473 6136 intel_enable_pipe(intel_crtc);
be6a6f8e 6137
4b3a9526
VS		 6138 assert_vblank_disabled(crtc);
6139 drm_crtc_vblank_on(crtc);
6140
f9b61ff6
DV		 6141 for_each_encoder_on_crtc(dev, crtc, encoder)
6142 encoder->enable(encoder);
0b8765c6 6143}
79e53945 6144
87476d63
DV		 6145static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146{
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6149
6e3c9717 6150 if (!crtc->config->gmch_pfit.control)
328d8e82 6151 return;
87476d63 6152
328d8e82 6153 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6154
328d8e82
DV		 6155 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6156 I915_READ(PFIT_CONTROL));
6157 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6158}
6159
0b8765c6
JB		 6160static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161{
6162 struct drm_device *dev = crtc->dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6165 struct intel_encoder *encoder;
0b8765c6 6166 int pipe = intel_crtc->pipe;
ef9c3aee 6167
6304cd91
VS		 6168 /*
6169 * On gen2 planes are double buffered but the pipe isn't, so we must
6170 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6171 * We also need to wait on all gmch platforms because of the
6172 * self-refresh mode constraint explained above.
6304cd91 6173 */
564ed191 6174 intel_wait_for_vblank(dev, pipe);
6304cd91 6175
4b3a9526
VS		 6176 for_each_encoder_on_crtc(dev, crtc, encoder)
6177 encoder->disable(encoder);
6178
f9b61ff6
DV		 6179 drm_crtc_vblank_off(crtc);
6180 assert_vblank_disabled(crtc);
6181
575f7ab7 6182 intel_disable_pipe(intel_crtc);
24a1f16d 6183
87476d63 6184 i9xx_pfit_disable(intel_crtc);
24a1f16d 6185
89b667f8
JB		 6186 for_each_encoder_on_crtc(dev, crtc, encoder)
6187 if (encoder->post_disable)
6188 encoder->post_disable(encoder);
6189
409ee761 6190 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6191 if (IS_CHERRYVIEW(dev))
6192 chv_disable_pll(dev_priv, pipe);
6193 else if (IS_VALLEYVIEW(dev))
6194 vlv_disable_pll(dev_priv, pipe);
6195 else
1c4e0274 6196 i9xx_disable_pll(intel_crtc);
076ed3b2 6197 }
0b8765c6 6198
4a3436e8 6199 if (!IS_GEN2(dev))
a72e4c9f 6200 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6201
6202 intel_crtc->active = false;
6203 intel_update_watermarks(crtc);
0b8765c6
JB		 6204}
6205
b17d48e2
ML		 6206static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6207{
6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6210 enum intel_display_power_domain domain;
6211 unsigned long domains;
6212
6213 if (!intel_crtc->active)
6214 return;
6215
a539205a
ML		 6216 if (to_intel_plane_state(crtc->primary->state)->visible) {
6217 intel_crtc_wait_for_pending_flips(crtc);
6218 intel_pre_disable_primary(crtc);
6219 }
6220
d032ffa0 6221 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6222 dev_priv->display.crtc_disable(crtc);
1f7457b1 6223 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6224
6225 domains = intel_crtc->enabled_power_domains;
6226 for_each_power_domain(domain, domains)
6227 intel_display_power_put(dev_priv, domain);
6228 intel_crtc->enabled_power_domains = 0;
6229}
6230
6b72d486
ML		 6231/*
6232 * turn all crtc's off, but do not adjust state
6233 * This has to be paired with a call to intel_modeset_setup_hw_state.
6234 */
70e0bd74 6235int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6236{
70e0bd74
ML		 6237 struct drm_mode_config *config = &dev->mode_config;
6238 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6239 struct drm_atomic_state *state;
6b72d486 6240 struct drm_crtc *crtc;
70e0bd74
ML		 6241 unsigned crtc_mask = 0;
6242 int ret = 0;
6243
6244 if (WARN_ON(!ctx))
6245 return 0;
6246
6247 lockdep_assert_held(&ctx->ww_ctx);
6248 state = drm_atomic_state_alloc(dev);
6249 if (WARN_ON(!state))
6250 return -ENOMEM;
6251
6252 state->acquire_ctx = ctx;
6253 state->allow_modeset = true;
6254
6255 for_each_crtc(dev, crtc) {
6256 struct drm_crtc_state *crtc_state =
6257 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6258
70e0bd74
ML		 6259 ret = PTR_ERR_OR_ZERO(crtc_state);
6260 if (ret)
6261 goto free;
6262
6263 if (!crtc_state->active)
6264 continue;
6265
6266 crtc_state->active = false;
6267 crtc_mask |= 1 << drm_crtc_index(crtc);
6268 }
6269
6270 if (crtc_mask) {
74c090b1 6271 ret = drm_atomic_commit(state);
70e0bd74
ML		 6272
6273 if (!ret) {
6274 for_each_crtc(dev, crtc)
6275 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6276 crtc->state->active = true;
6277
6278 return ret;
6279 }
6280 }
6281
6282free:
6283 if (ret)
6284 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6285 drm_atomic_state_free(state);
6286 return ret;
ee7b9f93
JB		 6287}
6288
ea5b213a 6289void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6290{
4ef69c7a 6291 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6292
ea5b213a
CW		 6293 drm_encoder_cleanup(encoder);
6294 kfree(intel_encoder);
7e7d76c3
JB		 6295}
6296
0a91ca29
DV		 6297/* Cross check the actual hw state with our own modeset state tracking (and it's
6298 * internal consistency). */
b980514c 6299static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6300{
35dd3c64
ML		 6301 struct drm_crtc *crtc = connector->base.state->crtc;
6302
6303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6304 connector->base.base.id,
6305 connector->base.name);
6306
0a91ca29 6307 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6308 struct drm_encoder *encoder = &connector->encoder->base;
6309 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6310
35dd3c64
ML		 6311 I915_STATE_WARN(!crtc,
6312 "connector enabled without attached crtc\n");
0a91ca29 6313
35dd3c64 6314 if (!crtc)
0e32b39c
DA		 6315 return;
6316
35dd3c64
ML		 6317 I915_STATE_WARN(!crtc->state->active,
6318 "connector is active, but attached crtc isn't\n");
36cd7444 6319
35dd3c64
ML		 6320 if (!encoder)
6321 return;
0a91ca29 6322
35dd3c64
ML		 6323 I915_STATE_WARN(conn_state->best_encoder != encoder,
6324 "atomic encoder doesn't match attached encoder\n");
0a91ca29 6325
35dd3c64
ML		 6326 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6327 "attached encoder crtc differs from connector crtc\n");
6328 } else {
4d688a2a
ML		 6329 I915_STATE_WARN(crtc && crtc->state->active,
6330 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6331 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6332 "best encoder set without crtc!\n");
0a91ca29 6333 }
79e53945
JB		 6334}
6335
08d9bc92
ACO		 6336int intel_connector_init(struct intel_connector *connector)
6337{
6338 struct drm_connector_state *connector_state;
6339
6340 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6341 if (!connector_state)
6342 return -ENOMEM;
6343
6344 connector->base.state = connector_state;
6345 return 0;
6346}
6347
6348struct intel_connector *intel_connector_alloc(void)
6349{
6350 struct intel_connector *connector;
6351
6352 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6353 if (!connector)
6354 return NULL;
6355
6356 if (intel_connector_init(connector) < 0) {
6357 kfree(connector);
6358 return NULL;
6359 }
6360
6361 return connector;
6362}
6363
f0947c37
DV		 6364/* Simple connector->get_hw_state implementation for encoders that support only
6365 * one connector and no cloning and hence the encoder state determines the state
6366 * of the connector. */
6367bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6368{
24929352 6369 enum pipe pipe = 0;
f0947c37 6370 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6371
f0947c37 6372 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6373}
6374
6d293983 6375static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6376{
6d293983
ACO		 6377 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6378 return crtc_state->fdi_lanes;
d272ddfa
VS		 6379
6380 return 0;
6381}
6382
6d293983 6383static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6384 struct intel_crtc_state *pipe_config)
1857e1da 6385{
6d293983
ACO		 6386 struct drm_atomic_state *state = pipe_config->base.state;
6387 struct intel_crtc *other_crtc;
6388 struct intel_crtc_state *other_crtc_state;
6389
1857e1da
DV		 6390 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6391 pipe_name(pipe), pipe_config->fdi_lanes);
6392 if (pipe_config->fdi_lanes > 4) {
6393 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6394 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6395 return -EINVAL;
1857e1da
DV		 6396 }
6397
bafb6553 6398 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6399 if (pipe_config->fdi_lanes > 2) {
6400 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6401 pipe_config->fdi_lanes);
6d293983 6402 return -EINVAL;
1857e1da 6403 } else {
6d293983 6404 return 0;
1857e1da
DV		 6405 }
6406 }
6407
6408 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6409 return 0;
1857e1da
DV		 6410
6411 /* Ivybridge 3 pipe is really complicated */
6412 switch (pipe) {
6413 case PIPE_A:
6d293983 6414 return 0;
1857e1da 6415 case PIPE_B:
6d293983
ACO		 6416 if (pipe_config->fdi_lanes <= 2)
6417 return 0;
6418
6419 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6420 other_crtc_state =
6421 intel_atomic_get_crtc_state(state, other_crtc);
6422 if (IS_ERR(other_crtc_state))
6423 return PTR_ERR(other_crtc_state);
6424
6425 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6426 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6427 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6428 return -EINVAL;
1857e1da 6429 }
6d293983 6430 return 0;
1857e1da 6431 case PIPE_C:
251cc67c
VS		 6432 if (pipe_config->fdi_lanes > 2) {
6433 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6434 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6435 return -EINVAL;
251cc67c 6436 }
6d293983
ACO		 6437
6438 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6439 other_crtc_state =
6440 intel_atomic_get_crtc_state(state, other_crtc);
6441 if (IS_ERR(other_crtc_state))
6442 return PTR_ERR(other_crtc_state);
6443
6444 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6445 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6446 return -EINVAL;
1857e1da 6447 }
6d293983 6448 return 0;
1857e1da
DV		 6449 default:
6450 BUG();
6451 }
6452}
6453
e29c22c0
DV		 6454#define RETRY 1
6455static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6456 struct intel_crtc_state *pipe_config)
877d48d5 6457{
1857e1da 6458 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6459 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6460 int lane, link_bw, fdi_dotclock, ret;
6461 bool needs_recompute = false;
877d48d5 6462
e29c22c0 6463retry:
877d48d5
DV		 6464 /* FDI is a binary signal running at ~2.7GHz, encoding
6465 * each output octet as 10 bits. The actual frequency
6466 * is stored as a divider into a 100MHz clock, and the
6467 * mode pixel clock is stored in units of 1KHz.
6468 * Hence the bw of each lane in terms of the mode signal
6469 * is:
6470 */
6471 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6472
241bfc38 6473 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6474
2bd89a07 6475 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6476 pipe_config->pipe_bpp);
6477
6478 pipe_config->fdi_lanes = lane;
6479
2bd89a07 6480 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6481 link_bw, &pipe_config->fdi_m_n);
1857e1da 6482
6d293983
ACO		 6483 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6484 intel_crtc->pipe, pipe_config);
6485 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6486 pipe_config->pipe_bpp -= 2*3;
6487 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6488 pipe_config->pipe_bpp);
6489 needs_recompute = true;
6490 pipe_config->bw_constrained = true;
6491
6492 goto retry;
6493 }
6494
6495 if (needs_recompute)
6496 return RETRY;
6497
6d293983 6498 return ret;
877d48d5
DV		 6499}
6500
8cfb3407
VS		 6501static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6502 struct intel_crtc_state *pipe_config)
6503{
6504 if (pipe_config->pipe_bpp > 24)
6505 return false;
6506
6507 /* HSW can handle pixel rate up to cdclk? */
6508 if (IS_HASWELL(dev_priv->dev))
6509 return true;
6510
6511 /*
b432e5cf
VS		 6512 * We compare against max which means we must take
6513 * the increased cdclk requirement into account when
6514 * calculating the new cdclk.
6515 *
6516 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6517 */
6518 return ilk_pipe_pixel_rate(pipe_config) <=
6519 dev_priv->max_cdclk_freq * 95 / 100;
6520}
6521
42db64ef 6522static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6523 struct intel_crtc_state *pipe_config)
42db64ef 6524{
8cfb3407
VS		 6525 struct drm_device *dev = crtc->base.dev;
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527
d330a953 6528 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6529 hsw_crtc_supports_ips(crtc) &&
6530 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6531}
6532
a43f6e0f 6533static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6534 struct intel_crtc_state *pipe_config)
79e53945 6535{
a43f6e0f 6536 struct drm_device *dev = crtc->base.dev;
8bd31e67 6537 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6538 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6539
ad3a4479 6540 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6541 if (INTEL_INFO(dev)->gen < 4) {
44913155 6542 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6543
6544 /*
6545 * Enable pixel doubling when the dot clock
6546 * is > 90% of the (display) core speed.
6547 *
b397c96b
VS		 6548 * GDG double wide on either pipe,
6549 * otherwise pipe A only.
cf532bb2 6550 */
b397c96b 6551 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6552 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6553 clock_limit *= 2;
cf532bb2 6554 pipe_config->double_wide = true;
ad3a4479
VS		 6555 }
6556
241bfc38 6557 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6558 return -EINVAL;
2c07245f 6559 }
89749350 6560
1d1d0e27
VS		 6561 /*
6562 * Pipe horizontal size must be even in:
6563 * - DVO ganged mode
6564 * - LVDS dual channel mode
6565 * - Double wide pipe
6566 */
a93e255f 6567 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6568 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6569 pipe_config->pipe_src_w &= ~1;
6570
8693a824
DL		 6571 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6572 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6573 */
6574 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6575 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6576 return -EINVAL;
44f46b42 6577
f5adf94e 6578 if (HAS_IPS(dev))
a43f6e0f
DV		 6579 hsw_compute_ips_config(crtc, pipe_config);
6580
877d48d5 6581 if (pipe_config->has_pch_encoder)
a43f6e0f 6582 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6583
cf5a15be 6584 return 0;
79e53945
JB		 6585}
6586
1652d19e
VS		 6587static int skylake_get_display_clock_speed(struct drm_device *dev)
6588{
6589 struct drm_i915_private *dev_priv = to_i915(dev);
6590 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6591 uint32_t cdctl = I915_READ(CDCLK_CTL);
6592 uint32_t linkrate;
6593
414355a7 6594 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6595 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6596
6597 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6598 return 540000;
6599
6600 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6601 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6602
71cd8423
DL		 6603 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6604 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6605 /* vco 8640 */
6606 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6607 case CDCLK_FREQ_450_432:
6608 return 432000;
6609 case CDCLK_FREQ_337_308:
6610 return 308570;
6611 case CDCLK_FREQ_675_617:
6612 return 617140;
6613 default:
6614 WARN(1, "Unknown cd freq selection\n");
6615 }
6616 } else {
6617 /* vco 8100 */
6618 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6619 case CDCLK_FREQ_450_432:
6620 return 450000;
6621 case CDCLK_FREQ_337_308:
6622 return 337500;
6623 case CDCLK_FREQ_675_617:
6624 return 675000;
6625 default:
6626 WARN(1, "Unknown cd freq selection\n");
6627 }
6628 }
6629
6630 /* error case, do as if DPLL0 isn't enabled */
6631 return 24000;
6632}
6633
acd3f3d3
BP		 6634static int broxton_get_display_clock_speed(struct drm_device *dev)
6635{
6636 struct drm_i915_private *dev_priv = to_i915(dev);
6637 uint32_t cdctl = I915_READ(CDCLK_CTL);
6638 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6639 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6640 int cdclk;
6641
6642 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6643 return 19200;
6644
6645 cdclk = 19200 * pll_ratio / 2;
6646
6647 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6648 case BXT_CDCLK_CD2X_DIV_SEL_1:
6649 return cdclk; /* 576MHz or 624MHz */
6650 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6651 return cdclk * 2 / 3; /* 384MHz */
6652 case BXT_CDCLK_CD2X_DIV_SEL_2:
6653 return cdclk / 2; /* 288MHz */
6654 case BXT_CDCLK_CD2X_DIV_SEL_4:
6655 return cdclk / 4; /* 144MHz */
6656 }
6657
6658 /* error case, do as if DE PLL isn't enabled */
6659 return 19200;
6660}
6661
1652d19e
VS		 6662static int broadwell_get_display_clock_speed(struct drm_device *dev)
6663{
6664 struct drm_i915_private *dev_priv = dev->dev_private;
6665 uint32_t lcpll = I915_READ(LCPLL_CTL);
6666 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6667
6668 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6669 return 800000;
6670 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6671 return 450000;
6672 else if (freq == LCPLL_CLK_FREQ_450)
6673 return 450000;
6674 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6675 return 540000;
6676 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6677 return 337500;
6678 else
6679 return 675000;
6680}
6681
6682static int haswell_get_display_clock_speed(struct drm_device *dev)
6683{
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685 uint32_t lcpll = I915_READ(LCPLL_CTL);
6686 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6687
6688 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6689 return 800000;
6690 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6691 return 450000;
6692 else if (freq == LCPLL_CLK_FREQ_450)
6693 return 450000;
6694 else if (IS_HSW_ULT(dev))
6695 return 337500;
6696 else
6697 return 540000;
79e53945
JB		 6698}
6699
25eb05fc
JB		 6700static int valleyview_get_display_clock_speed(struct drm_device *dev)
6701{
d197b7d3 6702 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6703 u32 val;
6704 int divider;
6705
6bcda4f0
VS		 6706 if (dev_priv->hpll_freq == 0)
6707 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6708
a580516d 6709 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6710 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6711 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6712
6713 divider = val & DISPLAY_FREQUENCY_VALUES;
6714
7d007f40
VS		 6715 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6716 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6717 "cdclk change in progress\n");
6718
6bcda4f0 6719 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6720}
6721
b37a6434
VS		 6722static int ilk_get_display_clock_speed(struct drm_device *dev)
6723{
6724 return 450000;
6725}
6726
e70236a8
JB		 6727static int i945_get_display_clock_speed(struct drm_device *dev)
6728{
6729 return 400000;
6730}
79e53945 6731
e70236a8 6732static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6733{
e907f170 6734 return 333333;
e70236a8 6735}
79e53945 6736
e70236a8
JB		 6737static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6738{
6739 return 200000;
6740}
79e53945 6741
257a7ffc
DV		 6742static int pnv_get_display_clock_speed(struct drm_device *dev)
6743{
6744 u16 gcfgc = 0;
6745
6746 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747
6748 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6749 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6750 return 266667;
257a7ffc 6751 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6752 return 333333;
257a7ffc 6753 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6754 return 444444;
257a7ffc
DV		 6755 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6756 return 200000;
6757 default:
6758 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6759 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6760 return 133333;
257a7ffc 6761 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6762 return 166667;
257a7ffc
DV		 6763 }
6764}
6765
e70236a8
JB		 6766static int i915gm_get_display_clock_speed(struct drm_device *dev)
6767{
6768 u16 gcfgc = 0;
79e53945 6769
e70236a8
JB		 6770 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771
6772 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6773 return 133333;
e70236a8
JB		 6774 else {
6775 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6776 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6777 return 333333;
e70236a8
JB		 6778 default:
6779 case GC_DISPLAY_CLOCK_190_200_MHZ:
6780 return 190000;
79e53945 6781 }
e70236a8
JB		 6782 }
6783}
6784
6785static int i865_get_display_clock_speed(struct drm_device *dev)
6786{
e907f170 6787 return 266667;
e70236a8
JB		 6788}
6789
1b1d2716 6790static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6791{
6792 u16 hpllcc = 0;
1b1d2716 6793
65cd2b3f
VS		 6794 /*
6795 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6796 * encoding is different :(
6797 * FIXME is this the right way to detect 852GM/852GMV?
6798 */
6799 if (dev->pdev->revision == 0x1)
6800 return 133333;
6801
1b1d2716
VS		 6802 pci_bus_read_config_word(dev->pdev->bus,
6803 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6804
e70236a8
JB		 6805 /* Assume that the hardware is in the high speed state. This
6806 * should be the default.
6807 */
6808 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6809 case GC_CLOCK_133_200:
1b1d2716 6810 case GC_CLOCK_133_200_2:
e70236a8
JB		 6811 case GC_CLOCK_100_200:
6812 return 200000;
6813 case GC_CLOCK_166_250:
6814 return 250000;
6815 case GC_CLOCK_100_133:
e907f170 6816 return 133333;
1b1d2716
VS		 6817 case GC_CLOCK_133_266:
6818 case GC_CLOCK_133_266_2:
6819 case GC_CLOCK_166_266:
6820 return 266667;
e70236a8 6821 }
79e53945 6822
e70236a8
JB		 6823 /* Shouldn't happen */
6824 return 0;
6825}
79e53945 6826
e70236a8
JB		 6827static int i830_get_display_clock_speed(struct drm_device *dev)
6828{
e907f170 6829 return 133333;
79e53945
JB		 6830}
6831
34edce2f
VS		 6832static unsigned int intel_hpll_vco(struct drm_device *dev)
6833{
6834 struct drm_i915_private *dev_priv = dev->dev_private;
6835 static const unsigned int blb_vco[8] = {
6836 [0] = 3200000,
6837 [1] = 4000000,
6838 [2] = 5333333,
6839 [3] = 4800000,
6840 [4] = 6400000,
6841 };
6842 static const unsigned int pnv_vco[8] = {
6843 [0] = 3200000,
6844 [1] = 4000000,
6845 [2] = 5333333,
6846 [3] = 4800000,
6847 [4] = 2666667,
6848 };
6849 static const unsigned int cl_vco[8] = {
6850 [0] = 3200000,
6851 [1] = 4000000,
6852 [2] = 5333333,
6853 [3] = 6400000,
6854 [4] = 3333333,
6855 [5] = 3566667,
6856 [6] = 4266667,
6857 };
6858 static const unsigned int elk_vco[8] = {
6859 [0] = 3200000,
6860 [1] = 4000000,
6861 [2] = 5333333,
6862 [3] = 4800000,
6863 };
6864 static const unsigned int ctg_vco[8] = {
6865 [0] = 3200000,
6866 [1] = 4000000,
6867 [2] = 5333333,
6868 [3] = 6400000,
6869 [4] = 2666667,
6870 [5] = 4266667,
6871 };
6872 const unsigned int *vco_table;
6873 unsigned int vco;
6874 uint8_t tmp = 0;
6875
6876 /* FIXME other chipsets? */
6877 if (IS_GM45(dev))
6878 vco_table = ctg_vco;
6879 else if (IS_G4X(dev))
6880 vco_table = elk_vco;
6881 else if (IS_CRESTLINE(dev))
6882 vco_table = cl_vco;
6883 else if (IS_PINEVIEW(dev))
6884 vco_table = pnv_vco;
6885 else if (IS_G33(dev))
6886 vco_table = blb_vco;
6887 else
6888 return 0;
6889
6890 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6891
6892 vco = vco_table[tmp & 0x7];
6893 if (vco == 0)
6894 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6895 else
6896 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6897
6898 return vco;
6899}
6900
6901static int gm45_get_display_clock_speed(struct drm_device *dev)
6902{
6903 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6904 uint16_t tmp = 0;
6905
6906 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6907
6908 cdclk_sel = (tmp >> 12) & 0x1;
6909
6910 switch (vco) {
6911 case 2666667:
6912 case 4000000:
6913 case 5333333:
6914 return cdclk_sel ? 333333 : 222222;
6915 case 3200000:
6916 return cdclk_sel ? 320000 : 228571;
6917 default:
6918 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6919 return 222222;
6920 }
6921}
6922
6923static int i965gm_get_display_clock_speed(struct drm_device *dev)
6924{
6925 static const uint8_t div_3200[] = { 16, 10, 8 };
6926 static const uint8_t div_4000[] = { 20, 12, 10 };
6927 static const uint8_t div_5333[] = { 24, 16, 14 };
6928 const uint8_t *div_table;
6929 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6930 uint16_t tmp = 0;
6931
6932 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6933
6934 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6935
6936 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6937 goto fail;
6938
6939 switch (vco) {
6940 case 3200000:
6941 div_table = div_3200;
6942 break;
6943 case 4000000:
6944 div_table = div_4000;
6945 break;
6946 case 5333333:
6947 div_table = div_5333;
6948 break;
6949 default:
6950 goto fail;
6951 }
6952
6953 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6954
caf4e252 6955fail:
34edce2f
VS		 6956 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6957 return 200000;
6958}
6959
6960static int g33_get_display_clock_speed(struct drm_device *dev)
6961{
6962 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6963 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6964 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6965 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6966 const uint8_t *div_table;
6967 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6968 uint16_t tmp = 0;
6969
6970 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6971
6972 cdclk_sel = (tmp >> 4) & 0x7;
6973
6974 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6975 goto fail;
6976
6977 switch (vco) {
6978 case 3200000:
6979 div_table = div_3200;
6980 break;
6981 case 4000000:
6982 div_table = div_4000;
6983 break;
6984 case 4800000:
6985 div_table = div_4800;
6986 break;
6987 case 5333333:
6988 div_table = div_5333;
6989 break;
6990 default:
6991 goto fail;
6992 }
6993
6994 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6995
caf4e252 6996fail:
34edce2f
VS		 6997 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6998 return 190476;
6999}
7000
2c07245f 7001static void
a65851af 7002intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7003{
a65851af
VS		 7004 while (*num > DATA_LINK_M_N_MASK ||
7005 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7006 *num >>= 1;
7007 *den >>= 1;
7008 }
7009}
7010
a65851af
VS		 7011static void compute_m_n(unsigned int m, unsigned int n,
7012 uint32_t *ret_m, uint32_t *ret_n)
7013{
7014 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7015 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7016 intel_reduce_m_n_ratio(ret_m, ret_n);
7017}
7018
e69d0bc1
DV		 7019void
7020intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7021 int pixel_clock, int link_clock,
7022 struct intel_link_m_n *m_n)
2c07245f 7023{
e69d0bc1 7024 m_n->tu = 64;
a65851af
VS		 7025
7026 compute_m_n(bits_per_pixel * pixel_clock,
7027 link_clock * nlanes * 8,
7028 &m_n->gmch_m, &m_n->gmch_n);
7029
7030 compute_m_n(pixel_clock, link_clock,
7031 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7032}
7033
a7615030
CW		 7034static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7035{
d330a953
JN		 7036 if (i915.panel_use_ssc >= 0)
7037 return i915.panel_use_ssc != 0;
41aa3448 7038 return dev_priv->vbt.lvds_use_ssc
435793df 7039 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7040}
7041
a93e255f
ACO		 7042static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7043 int num_connectors)
c65d77d8 7044{
a93e255f 7045 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 int refclk;
7048
a93e255f
ACO		 7049 WARN_ON(!crtc_state->base.state);
7050
5ab7b0b7 7051 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7052 refclk = 100000;
a93e255f 7053 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7054 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7055 refclk = dev_priv->vbt.lvds_ssc_freq;
7056 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7057 } else if (!IS_GEN2(dev)) {
7058 refclk = 96000;
7059 } else {
7060 refclk = 48000;
7061 }
7062
7063 return refclk;
7064}
7065
7429e9d4 7066static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7067{
7df00d7a 7068 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7069}
f47709a9 7070
7429e9d4
DV		 7071static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7072{
7073 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7074}
7075
f47709a9 7076static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7077 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7078 intel_clock_t *reduced_clock)
7079{
f47709a9 7080 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7081 u32 fp, fp2 = 0;
7082
7083 if (IS_PINEVIEW(dev)) {
190f68c5 7084 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7085 if (reduced_clock)
7429e9d4 7086 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7087 } else {
190f68c5 7088 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7089 if (reduced_clock)
7429e9d4 7090 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7091 }
7092
190f68c5 7093 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7094
f47709a9 7095 crtc->lowfreq_avail = false;
a93e255f 7096 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7097 reduced_clock) {
190f68c5 7098 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7099 crtc->lowfreq_avail = true;
a7516a05 7100 } else {
190f68c5 7101 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7102 }
7103}
7104
5e69f97f
CML		 7105static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7106 pipe)
89b667f8
JB		 7107{
7108 u32 reg_val;
7109
7110 /*
7111 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7112 * and set it to a reasonable value instead.
7113 */
ab3c759a 7114 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7115 reg_val &= 0xffffff00;
7116 reg_val |= 0x00000030;
ab3c759a 7117 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7118
ab3c759a 7119 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7120 reg_val &= 0x8cffffff;
7121 reg_val = 0x8c000000;
ab3c759a 7122 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7123
ab3c759a 7124 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7125 reg_val &= 0xffffff00;
ab3c759a 7126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7127
ab3c759a 7128 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7129 reg_val &= 0x00ffffff;
7130 reg_val |= 0xb0000000;
ab3c759a 7131 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7132}
7133
b551842d
DV		 7134static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7135 struct intel_link_m_n *m_n)
7136{
7137 struct drm_device *dev = crtc->base.dev;
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139 int pipe = crtc->pipe;
7140
e3b95f1e
DV		 7141 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7142 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7143 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7144 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7145}
7146
7147static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7148 struct intel_link_m_n *m_n,
7149 struct intel_link_m_n *m2_n2)
b551842d
DV		 7150{
7151 struct drm_device *dev = crtc->base.dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 int pipe = crtc->pipe;
6e3c9717 7154 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7155
7156 if (INTEL_INFO(dev)->gen >= 5) {
7157 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7158 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7159 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7160 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7161 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7162 * for gen < 8) and if DRRS is supported (to make sure the
7163 * registers are not unnecessarily accessed).
7164 */
44395bfe 7165 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7166 crtc->config->has_drrs) {
f769cd24
VK		 7167 I915_WRITE(PIPE_DATA_M2(transcoder),
7168 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7169 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7170 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7171 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7172 }
b551842d 7173 } else {
e3b95f1e
DV		 7174 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7176 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7177 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7178 }
7179}
7180
fe3cd48d 7181void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7182{
fe3cd48d
R		 7183 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7184
7185 if (m_n == M1_N1) {
7186 dp_m_n = &crtc->config->dp_m_n;
7187 dp_m2_n2 = &crtc->config->dp_m2_n2;
7188 } else if (m_n == M2_N2) {
7189
7190 /*
7191 * M2_N2 registers are not supported. Hence m2_n2 divider value
7192 * needs to be programmed into M1_N1.
7193 */
7194 dp_m_n = &crtc->config->dp_m2_n2;
7195 } else {
7196 DRM_ERROR("Unsupported divider value\n");
7197 return;
7198 }
7199
6e3c9717
ACO		 7200 if (crtc->config->has_pch_encoder)
7201 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7202 else
fe3cd48d 7203 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7204}
7205
251ac862
DV		 7206static void vlv_compute_dpll(struct intel_crtc *crtc,
7207 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7208{
7209 u32 dpll, dpll_md;
7210
7211 /*
7212 * Enable DPIO clock input. We should never disable the reference
7213 * clock for pipe B, since VGA hotplug / manual detection depends
7214 * on it.
7215 */
60bfe44f
VS		 7216 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7217 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7218 /* We should never disable this, set it here for state tracking */
7219 if (crtc->pipe == PIPE_B)
7220 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7221 dpll |= DPLL_VCO_ENABLE;
d288f65f 7222 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7223
d288f65f 7224 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7225 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7226 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7227}
7228
d288f65f 7229static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7230 const struct intel_crtc_state *pipe_config)
a0c4da24 7231{
f47709a9 7232 struct drm_device *dev = crtc->base.dev;
a0c4da24 7233 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7234 int pipe = crtc->pipe;
bdd4b6a6 7235 u32 mdiv;
a0c4da24 7236 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7237 u32 coreclk, reg_val;
a0c4da24 7238
a580516d 7239 mutex_lock(&dev_priv->sb_lock);
09153000 7240
d288f65f
VS		 7241 bestn = pipe_config->dpll.n;
7242 bestm1 = pipe_config->dpll.m1;
7243 bestm2 = pipe_config->dpll.m2;
7244 bestp1 = pipe_config->dpll.p1;
7245 bestp2 = pipe_config->dpll.p2;
a0c4da24 7246
89b667f8
JB		 7247 /* See eDP HDMI DPIO driver vbios notes doc */
7248
7249 /* PLL B needs special handling */
bdd4b6a6 7250 if (pipe == PIPE_B)
5e69f97f 7251 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7252
7253 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7254 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7255
7256 /* Disable target IRef on PLL */
ab3c759a 7257 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7258 reg_val &= 0x00ffffff;
ab3c759a 7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7260
7261 /* Disable fast lock */
ab3c759a 7262 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7263
7264 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7265 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7266 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7267 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7268 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7269
7270 /*
7271 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7272 * but we don't support that).
7273 * Note: don't use the DAC post divider as it seems unstable.
7274 */
7275 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7277
a0c4da24 7278 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7279 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7280
89b667f8 7281 /* Set HBR and RBR LPF coefficients */
d288f65f 7282 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7283 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7284 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7286 0x009f0003);
89b667f8 7287 else
ab3c759a 7288 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7289 0x00d0000f);
7290
681a8504 7291 if (pipe_config->has_dp_encoder) {
89b667f8 7292 /* Use SSC source */
bdd4b6a6 7293 if (pipe == PIPE_A)
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7295 0x0df40000);
7296 else
ab3c759a 7297 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7298 0x0df70000);
7299 } else { /* HDMI or VGA */
7300 /* Use bend source */
bdd4b6a6 7301 if (pipe == PIPE_A)
ab3c759a 7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7303 0x0df70000);
7304 else
ab3c759a 7305 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7306 0x0df40000);
7307 }
a0c4da24 7308
ab3c759a 7309 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7310 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7311 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7312 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7313 coreclk |= 0x01000000;
ab3c759a 7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7315
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7317 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7318}
7319
251ac862
DV		 7320static void chv_compute_dpll(struct intel_crtc *crtc,
7321 struct intel_crtc_state *pipe_config)
1ae0d137 7322{
60bfe44f
VS		 7323 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7324 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7325 DPLL_VCO_ENABLE;
7326 if (crtc->pipe != PIPE_A)
d288f65f 7327 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7328
d288f65f
VS		 7329 pipe_config->dpll_hw_state.dpll_md =
7330 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7331}
7332
d288f65f 7333static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7334 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7335{
7336 struct drm_device *dev = crtc->base.dev;
7337 struct drm_i915_private *dev_priv = dev->dev_private;
7338 int pipe = crtc->pipe;
7339 int dpll_reg = DPLL(crtc->pipe);
7340 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7341 u32 loopfilter, tribuf_calcntr;
9d556c99 7342 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7343 u32 dpio_val;
9cbe40c1 7344 int vco;
9d556c99 7345
d288f65f
VS		 7346 bestn = pipe_config->dpll.n;
7347 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7348 bestm1 = pipe_config->dpll.m1;
7349 bestm2 = pipe_config->dpll.m2 >> 22;
7350 bestp1 = pipe_config->dpll.p1;
7351 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7352 vco = pipe_config->dpll.vco;
a945ce7e 7353 dpio_val = 0;
9cbe40c1 7354 loopfilter = 0;
9d556c99
CML		 7355
7356 /*
7357 * Enable Refclk and SSC
7358 */
a11b0703 7359 I915_WRITE(dpll_reg,
d288f65f 7360 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7361
a580516d 7362 mutex_lock(&dev_priv->sb_lock);
9d556c99 7363
9d556c99
CML		 7364 /* p1 and p2 divider */
7365 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7366 5 << DPIO_CHV_S1_DIV_SHIFT |
7367 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7368 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7369 1 << DPIO_CHV_K_DIV_SHIFT);
7370
7371 /* Feedback post-divider - m2 */
7372 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7373
7374 /* Feedback refclk divider - n and m1 */
7375 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7376 DPIO_CHV_M1_DIV_BY_2 |
7377 1 << DPIO_CHV_N_DIV_SHIFT);
7378
7379 /* M2 fraction division */
a945ce7e
VP		 7380 if (bestm2_frac)
7381 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7382
7383 /* M2 fraction division enable */
a945ce7e
VP		 7384 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7385 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7386 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7387 if (bestm2_frac)
7388 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7389 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7390
de3a0fde
VP		 7391 /* Program digital lock detect threshold */
7392 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7393 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7394 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7395 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7396 if (!bestm2_frac)
7397 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7399
9d556c99 7400 /* Loop filter */
9cbe40c1
VP		 7401 if (vco == 5400000) {
7402 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x9;
7406 } else if (vco <= 6200000) {
7407 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7408 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7409 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7410 tribuf_calcntr = 0x9;
7411 } else if (vco <= 6480000) {
7412 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7413 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7414 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7415 tribuf_calcntr = 0x8;
7416 } else {
7417 /* Not supported. Apply the same limits as in the max case */
7418 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7419 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7420 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7421 tribuf_calcntr = 0;
7422 }
9d556c99
CML		 7423 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7424
968040b2 7425 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7426 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7427 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7429
9d556c99
CML		 7430 /* AFC Recal */
7431 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7432 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7433 DPIO_AFC_RECAL);
7434
a580516d 7435 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7436}
7437
d288f65f
VS		 7438/**
7439 * vlv_force_pll_on - forcibly enable just the PLL
7440 * @dev_priv: i915 private structure
7441 * @pipe: pipe PLL to enable
7442 * @dpll: PLL configuration
7443 *
7444 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7445 * in cases where we need the PLL enabled even when @pipe is not going to
7446 * be enabled.
7447 */
7448void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7449 const struct dpll *dpll)
7450{
7451 struct intel_crtc *crtc =
7452 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7453 struct intel_crtc_state pipe_config = {
a93e255f 7454 .base.crtc = &crtc->base,
d288f65f
VS		 7455 .pixel_multiplier = 1,
7456 .dpll = *dpll,
7457 };
7458
7459 if (IS_CHERRYVIEW(dev)) {
251ac862 7460 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7461 chv_prepare_pll(crtc, &pipe_config);
7462 chv_enable_pll(crtc, &pipe_config);
7463 } else {
251ac862 7464 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7465 vlv_prepare_pll(crtc, &pipe_config);
7466 vlv_enable_pll(crtc, &pipe_config);
7467 }
7468}
7469
7470/**
7471 * vlv_force_pll_off - forcibly disable just the PLL
7472 * @dev_priv: i915 private structure
7473 * @pipe: pipe PLL to disable
7474 *
7475 * Disable the PLL for @pipe. To be used in cases where we need
7476 * the PLL enabled even when @pipe is not going to be enabled.
7477 */
7478void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7479{
7480 if (IS_CHERRYVIEW(dev))
7481 chv_disable_pll(to_i915(dev), pipe);
7482 else
7483 vlv_disable_pll(to_i915(dev), pipe);
7484}
7485
251ac862
DV		 7486static void i9xx_compute_dpll(struct intel_crtc *crtc,
7487 struct intel_crtc_state *crtc_state,
7488 intel_clock_t *reduced_clock,
7489 int num_connectors)
eb1cbe48 7490{
f47709a9 7491 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7492 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7493 u32 dpll;
7494 bool is_sdvo;
190f68c5 7495 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7496
190f68c5 7497 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7498
a93e255f
ACO		 7499 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7500 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7501
7502 dpll = DPLL_VGA_MODE_DIS;
7503
a93e255f 7504 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7505 dpll |= DPLLB_MODE_LVDS;
7506 else
7507 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7508
ef1b460d 7509 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7510 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7511 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7512 }
198a037f
DV		 7513
7514 if (is_sdvo)
4a33e48d 7515 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7516
190f68c5 7517 if (crtc_state->has_dp_encoder)
4a33e48d 7518 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7519
7520 /* compute bitmask from p1 value */
7521 if (IS_PINEVIEW(dev))
7522 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7523 else {
7524 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7525 if (IS_G4X(dev) && reduced_clock)
7526 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7527 }
7528 switch (clock->p2) {
7529 case 5:
7530 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7531 break;
7532 case 7:
7533 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7534 break;
7535 case 10:
7536 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7537 break;
7538 case 14:
7539 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7540 break;
7541 }
7542 if (INTEL_INFO(dev)->gen >= 4)
7543 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7544
190f68c5 7545 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7546 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7547 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7548 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7549 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7550 else
7551 dpll |= PLL_REF_INPUT_DREFCLK;
7552
7553 dpll |= DPLL_VCO_ENABLE;
190f68c5 7554 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7555
eb1cbe48 7556 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7557 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7558 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7559 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7560 }
7561}
7562
251ac862
DV		 7563static void i8xx_compute_dpll(struct intel_crtc *crtc,
7564 struct intel_crtc_state *crtc_state,
7565 intel_clock_t *reduced_clock,
7566 int num_connectors)
eb1cbe48 7567{
f47709a9 7568 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7569 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7570 u32 dpll;
190f68c5 7571 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7572
190f68c5 7573 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7574
eb1cbe48
DV		 7575 dpll = DPLL_VGA_MODE_DIS;
7576
a93e255f 7577 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7578 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7579 } else {
7580 if (clock->p1 == 2)
7581 dpll |= PLL_P1_DIVIDE_BY_TWO;
7582 else
7583 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7584 if (clock->p2 == 4)
7585 dpll |= PLL_P2_DIVIDE_BY_4;
7586 }
7587
a93e255f 7588 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7589 dpll |= DPLL_DVO_2X_MODE;
7590
a93e255f 7591 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7592 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7593 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7594 else
7595 dpll |= PLL_REF_INPUT_DREFCLK;
7596
7597 dpll |= DPLL_VCO_ENABLE;
190f68c5 7598 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7599}
7600
8a654f3b 7601static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7602{
7603 struct drm_device *dev = intel_crtc->base.dev;
7604 struct drm_i915_private *dev_priv = dev->dev_private;
7605 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7606 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7607 struct drm_display_mode *adjusted_mode =
6e3c9717 7608 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7609 uint32_t crtc_vtotal, crtc_vblank_end;
7610 int vsyncshift = 0;
4d8a62ea
DV		 7611
7612 /* We need to be careful not to changed the adjusted mode, for otherwise
7613 * the hw state checker will get angry at the mismatch. */
7614 crtc_vtotal = adjusted_mode->crtc_vtotal;
7615 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7616
609aeaca 7617 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7618 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7619 crtc_vtotal -= 1;
7620 crtc_vblank_end -= 1;
609aeaca 7621
409ee761 7622 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7623 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7624 else
7625 vsyncshift = adjusted_mode->crtc_hsync_start -
7626 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7627 if (vsyncshift < 0)
7628 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7629 }
7630
7631 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7632 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7633
fe2b8f9d 7634 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7635 (adjusted_mode->crtc_hdisplay - 1) |
7636 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7637 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7638 (adjusted_mode->crtc_hblank_start - 1) |
7639 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7640 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7641 (adjusted_mode->crtc_hsync_start - 1) |
7642 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7643
fe2b8f9d 7644 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7645 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7646 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7647 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7648 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7649 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7650 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7651 (adjusted_mode->crtc_vsync_start - 1) |
7652 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7653
b5e508d4
PZ		 7654 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7655 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7656 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7657 * bits. */
7658 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7659 (pipe == PIPE_B || pipe == PIPE_C))
7660 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7661
b0e77b9c
PZ		 7662 /* pipesrc controls the size that is scaled from, which should
7663 * always be the user's requested size.
7664 */
7665 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7666 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7667 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7668}
7669
1bd1bd80 7670static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7671 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7672{
7673 struct drm_device *dev = crtc->base.dev;
7674 struct drm_i915_private *dev_priv = dev->dev_private;
7675 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7676 uint32_t tmp;
7677
7678 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7679 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7681 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7682 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7684 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7685 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7686 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7687
7688 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7689 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7691 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7692 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7694 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7695 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7696 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7697
7698 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7699 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7700 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7701 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7702 }
7703
7704 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7705 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7706 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7707
2d112de7
ACO		 7708 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7709 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7710}
7711
f6a83288 7712void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7713 struct intel_crtc_state *pipe_config)
babea61d 7714{
2d112de7
ACO		 7715 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7716 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7717 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7718 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7719
2d112de7
ACO		 7720 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7721 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7722 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7723 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7724
2d112de7 7725 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7726 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7727
2d112de7
ACO		 7728 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7729 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7730
7731 mode->hsync = drm_mode_hsync(mode);
7732 mode->vrefresh = drm_mode_vrefresh(mode);
7733 drm_mode_set_name(mode);
babea61d
JB		 7734}
7735
84b046f3
DV		 7736static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7737{
7738 struct drm_device *dev = intel_crtc->base.dev;
7739 struct drm_i915_private *dev_priv = dev->dev_private;
7740 uint32_t pipeconf;
7741
9f11a9e4 7742 pipeconf = 0;
84b046f3 7743
b6b5d049
VS		 7744 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7745 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7746 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7747
6e3c9717 7748 if (intel_crtc->config->double_wide)
cf532bb2 7749 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7750
ff9ce46e
DV		 7751 /* only g4x and later have fancy bpc/dither controls */
7752 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7753 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7754 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7755 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7756 PIPECONF_DITHER_TYPE_SP;
84b046f3 7757
6e3c9717 7758 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7759 case 18:
7760 pipeconf |= PIPECONF_6BPC;
7761 break;
7762 case 24:
7763 pipeconf |= PIPECONF_8BPC;
7764 break;
7765 case 30:
7766 pipeconf |= PIPECONF_10BPC;
7767 break;
7768 default:
7769 /* Case prevented by intel_choose_pipe_bpp_dither. */
7770 BUG();
84b046f3
DV		 7771 }
7772 }
7773
7774 if (HAS_PIPE_CXSR(dev)) {
7775 if (intel_crtc->lowfreq_avail) {
7776 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7777 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7778 } else {
7779 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7780 }
7781 }
7782
6e3c9717 7783 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7784 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7785 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7786 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7787 else
7788 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7789 } else
84b046f3
DV		 7790 pipeconf |= PIPECONF_PROGRESSIVE;
7791
6e3c9717 7792 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7793 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7794
84b046f3
DV		 7795 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7796 POSTING_READ(PIPECONF(intel_crtc->pipe));
7797}
7798
190f68c5
ACO		 7799static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7800 struct intel_crtc_state *crtc_state)
79e53945 7801{
c7653199 7802 struct drm_device *dev = crtc->base.dev;
79e53945 7803 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7804 int refclk, num_connectors = 0;
c329a4ec
DV		 7805 intel_clock_t clock;
7806 bool ok;
7807 bool is_dsi = false;
5eddb70b 7808 struct intel_encoder *encoder;
d4906093 7809 const intel_limit_t *limit;
55bb9992 7810 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7811 struct drm_connector *connector;
55bb9992
ACO		 7812 struct drm_connector_state *connector_state;
7813 int i;
79e53945 7814
dd3cd74a
ACO		 7815 memset(&crtc_state->dpll_hw_state, 0,
7816 sizeof(crtc_state->dpll_hw_state));
7817
da3ced29 7818 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7819 if (connector_state->crtc != &crtc->base)
7820 continue;
7821
7822 encoder = to_intel_encoder(connector_state->best_encoder);
7823
5eddb70b 7824 switch (encoder->type) {
e9fd1c02
JN		 7825 case INTEL_OUTPUT_DSI:
7826 is_dsi = true;
7827 break;
6847d71b
PZ		 7828 default:
7829 break;
79e53945 7830 }
43565a06 7831
c751ce4f 7832 num_connectors++;
79e53945
JB		 7833 }
7834
f2335330 7835 if (is_dsi)
5b18e57c 7836 return 0;
f2335330 7837
190f68c5 7838 if (!crtc_state->clock_set) {
a93e255f 7839 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7840
e9fd1c02
JN		 7841 /*
7842 * Returns a set of divisors for the desired target clock with
7843 * the given refclk, or FALSE. The returned values represent
7844 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7845 * 2) / p1 / p2.
7846 */
a93e255f
ACO		 7847 limit = intel_limit(crtc_state, refclk);
7848 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7849 crtc_state->port_clock,
e9fd1c02 7850 refclk, NULL, &clock);
f2335330 7851 if (!ok) {
e9fd1c02
JN		 7852 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7853 return -EINVAL;
7854 }
79e53945 7855
f2335330 7856 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7857 crtc_state->dpll.n = clock.n;
7858 crtc_state->dpll.m1 = clock.m1;
7859 crtc_state->dpll.m2 = clock.m2;
7860 crtc_state->dpll.p1 = clock.p1;
7861 crtc_state->dpll.p2 = clock.p2;
f47709a9 7862 }
7026d4ac 7863
e9fd1c02 7864 if (IS_GEN2(dev)) {
c329a4ec 7865 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7866 num_connectors);
9d556c99 7867 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7868 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7869 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7870 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7871 } else {
c329a4ec 7872 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7873 num_connectors);
e9fd1c02 7874 }
79e53945 7875
c8f7a0db 7876 return 0;
f564048e
EA		 7877}
7878
2fa2fe9a 7879static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7880 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7881{
7882 struct drm_device *dev = crtc->base.dev;
7883 struct drm_i915_private *dev_priv = dev->dev_private;
7884 uint32_t tmp;
7885
dc9e7dec
VS		 7886 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7887 return;
7888
2fa2fe9a 7889 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7890 if (!(tmp & PFIT_ENABLE))
7891 return;
2fa2fe9a 7892
06922821 7893 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7894 if (INTEL_INFO(dev)->gen < 4) {
7895 if (crtc->pipe != PIPE_B)
7896 return;
2fa2fe9a
DV		 7897 } else {
7898 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7899 return;
7900 }
7901
06922821 7902 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7903 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7904 if (INTEL_INFO(dev)->gen < 5)
7905 pipe_config->gmch_pfit.lvds_border_bits =
7906 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7907}
7908
acbec814 7909static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7910 struct intel_crtc_state *pipe_config)
acbec814
JB		 7911{
7912 struct drm_device *dev = crtc->base.dev;
7913 struct drm_i915_private *dev_priv = dev->dev_private;
7914 int pipe = pipe_config->cpu_transcoder;
7915 intel_clock_t clock;
7916 u32 mdiv;
662c6ecb 7917 int refclk = 100000;
acbec814 7918
f573de5a
SK		 7919 /* In case of MIPI DPLL will not even be used */
7920 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7921 return;
7922
a580516d 7923 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7924 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7925 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7926
7927 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7928 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7929 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7930 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7931 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7932
dccbea3b 7933 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7934}
7935
5724dbd1
DL		 7936static void
7937i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7938 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7939{
7940 struct drm_device *dev = crtc->base.dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942 u32 val, base, offset;
7943 int pipe = crtc->pipe, plane = crtc->plane;
7944 int fourcc, pixel_format;
6761dd31 7945 unsigned int aligned_height;
b113d5ee 7946 struct drm_framebuffer *fb;
1b842c89 7947 struct intel_framebuffer *intel_fb;
1ad292b5 7948
42a7b088
DL		 7949 val = I915_READ(DSPCNTR(plane));
7950 if (!(val & DISPLAY_PLANE_ENABLE))
7951 return;
7952
d9806c9f 7953 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7954 if (!intel_fb) {
1ad292b5
JB		 7955 DRM_DEBUG_KMS("failed to alloc fb\n");
7956 return;
7957 }
7958
1b842c89
DL		 7959 fb = &intel_fb->base;
7960
18c5247e
DV		 7961 if (INTEL_INFO(dev)->gen >= 4) {
7962 if (val & DISPPLANE_TILED) {
49af449b 7963 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7964 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7965 }
7966 }
1ad292b5
JB		 7967
7968 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7969 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7970 fb->pixel_format = fourcc;
7971 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7972
7973 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7974 if (plane_config->tiling)
1ad292b5
JB		 7975 offset = I915_READ(DSPTILEOFF(plane));
7976 else
7977 offset = I915_READ(DSPLINOFF(plane));
7978 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7979 } else {
7980 base = I915_READ(DSPADDR(plane));
7981 }
7982 plane_config->base = base;
7983
7984 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7985 fb->width = ((val >> 16) & 0xfff) + 1;
7986 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7987
7988 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7989 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7990
b113d5ee 7991 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7992 fb->pixel_format,
7993 fb->modifier[0]);
1ad292b5 7994
f37b5c2b 7995 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7996
2844a921
DL		 7997 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7998 pipe_name(pipe), plane, fb->width, fb->height,
7999 fb->bits_per_pixel, base, fb->pitches[0],
8000 plane_config->size);
1ad292b5 8001
2d14030b 8002 plane_config->fb = intel_fb;
1ad292b5
JB		 8003}
8004
70b23a98 8005static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8006 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8007{
8008 struct drm_device *dev = crtc->base.dev;
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 int pipe = pipe_config->cpu_transcoder;
8011 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8012 intel_clock_t clock;
0d7b6b11 8013 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8014 int refclk = 100000;
8015
a580516d 8016 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8017 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8018 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8019 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8020 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8021 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8022 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8023
8024 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8025 clock.m2 = (pll_dw0 & 0xff) << 22;
8026 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8027 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8028 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8029 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8030 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8031
dccbea3b 8032 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8033}
8034
0e8ffe1b 8035static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8036 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8037{
8038 struct drm_device *dev = crtc->base.dev;
8039 struct drm_i915_private *dev_priv = dev->dev_private;
8040 uint32_t tmp;
8041
f458ebbc
DV		 8042 if (!intel_display_power_is_enabled(dev_priv,
8043 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8044 return false;
8045
e143a21c 8046 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8047 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8048
0e8ffe1b
DV		 8049 tmp = I915_READ(PIPECONF(crtc->pipe));
8050 if (!(tmp & PIPECONF_ENABLE))
8051 return false;
8052
42571aef
VS		 8053 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8054 switch (tmp & PIPECONF_BPC_MASK) {
8055 case PIPECONF_6BPC:
8056 pipe_config->pipe_bpp = 18;
8057 break;
8058 case PIPECONF_8BPC:
8059 pipe_config->pipe_bpp = 24;
8060 break;
8061 case PIPECONF_10BPC:
8062 pipe_config->pipe_bpp = 30;
8063 break;
8064 default:
8065 break;
8066 }
8067 }
8068
b5a9fa09
DV		 8069 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8070 pipe_config->limited_color_range = true;
8071
282740f7
VS		 8072 if (INTEL_INFO(dev)->gen < 4)
8073 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8074
1bd1bd80
DV		 8075 intel_get_pipe_timings(crtc, pipe_config);
8076
2fa2fe9a
DV		 8077 i9xx_get_pfit_config(crtc, pipe_config);
8078
6c49f241
DV		 8079 if (INTEL_INFO(dev)->gen >= 4) {
8080 tmp = I915_READ(DPLL_MD(crtc->pipe));
8081 pipe_config->pixel_multiplier =
8082 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8083 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8084 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8085 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8086 tmp = I915_READ(DPLL(crtc->pipe));
8087 pipe_config->pixel_multiplier =
8088 ((tmp & SDVO_MULTIPLIER_MASK)
8089 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8090 } else {
8091 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8092 * port and will be fixed up in the encoder->get_config
8093 * function. */
8094 pipe_config->pixel_multiplier = 1;
8095 }
8bcc2795
DV		 8096 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8097 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8098 /*
8099 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8100 * on 830. Filter it out here so that we don't
8101 * report errors due to that.
8102 */
8103 if (IS_I830(dev))
8104 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8105
8bcc2795
DV		 8106 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8107 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8108 } else {
8109 /* Mask out read-only status bits. */
8110 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8111 DPLL_PORTC_READY_MASK |
8112 DPLL_PORTB_READY_MASK);
8bcc2795 8113 }
6c49f241 8114
70b23a98
VS		 8115 if (IS_CHERRYVIEW(dev))
8116 chv_crtc_clock_get(crtc, pipe_config);
8117 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8118 vlv_crtc_clock_get(crtc, pipe_config);
8119 else
8120 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8121
0e8ffe1b
DV		 8122 return true;
8123}
8124
dde86e2d 8125static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8126{
8127 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8128 struct intel_encoder *encoder;
74cfd7ac 8129 u32 val, final;
13d83a67 8130 bool has_lvds = false;
199e5d79 8131 bool has_cpu_edp = false;
199e5d79 8132 bool has_panel = false;
99eb6a01
KP		 8133 bool has_ck505 = false;
8134 bool can_ssc = false;
13d83a67
JB		 8135
8136 /* We need to take the global config into account */
b2784e15 8137 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8138 switch (encoder->type) {
8139 case INTEL_OUTPUT_LVDS:
8140 has_panel = true;
8141 has_lvds = true;
8142 break;
8143 case INTEL_OUTPUT_EDP:
8144 has_panel = true;
2de6905f 8145 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8146 has_cpu_edp = true;
8147 break;
6847d71b
PZ		 8148 default:
8149 break;
13d83a67
JB		 8150 }
8151 }
8152
99eb6a01 8153 if (HAS_PCH_IBX(dev)) {
41aa3448 8154 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8155 can_ssc = has_ck505;
8156 } else {
8157 has_ck505 = false;
8158 can_ssc = true;
8159 }
8160
2de6905f
ID		 8161 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8162 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8163
8164 /* Ironlake: try to setup display ref clock before DPLL
8165 * enabling. This is only under driver's control after
8166 * PCH B stepping, previous chipset stepping should be
8167 * ignoring this setting.
8168 */
74cfd7ac
CW		 8169 val = I915_READ(PCH_DREF_CONTROL);
8170
8171 /* As we must carefully and slowly disable/enable each source in turn,
8172 * compute the final state we want first and check if we need to
8173 * make any changes at all.
8174 */
8175 final = val;
8176 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8177 if (has_ck505)
8178 final |= DREF_NONSPREAD_CK505_ENABLE;
8179 else
8180 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8181
8182 final &= ~DREF_SSC_SOURCE_MASK;
8183 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8184 final &= ~DREF_SSC1_ENABLE;
8185
8186 if (has_panel) {
8187 final |= DREF_SSC_SOURCE_ENABLE;
8188
8189 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8190 final |= DREF_SSC1_ENABLE;
8191
8192 if (has_cpu_edp) {
8193 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8194 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8195 else
8196 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8197 } else
8198 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8199 } else {
8200 final |= DREF_SSC_SOURCE_DISABLE;
8201 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8202 }
8203
8204 if (final == val)
8205 return;
8206
13d83a67 8207 /* Always enable nonspread source */
74cfd7ac 8208 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8209
99eb6a01 8210 if (has_ck505)
74cfd7ac 8211 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8212 else
74cfd7ac 8213 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8214
199e5d79 8215 if (has_panel) {
74cfd7ac
CW		 8216 val &= ~DREF_SSC_SOURCE_MASK;
8217 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8218
199e5d79 8219 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8220 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8221 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8222 val |= DREF_SSC1_ENABLE;
e77166b5 8223 } else
74cfd7ac 8224 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8225
8226 /* Get SSC going before enabling the outputs */
74cfd7ac 8227 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8228 POSTING_READ(PCH_DREF_CONTROL);
8229 udelay(200);
8230
74cfd7ac 8231 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8232
8233 /* Enable CPU source on CPU attached eDP */
199e5d79 8234 if (has_cpu_edp) {
99eb6a01 8235 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8236 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8237 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8238 } else
74cfd7ac 8239 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8240 } else
74cfd7ac 8241 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8242
74cfd7ac 8243 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8244 POSTING_READ(PCH_DREF_CONTROL);
8245 udelay(200);
8246 } else {
8247 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8248
74cfd7ac 8249 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8250
8251 /* Turn off CPU output */
74cfd7ac 8252 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8253
74cfd7ac 8254 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8255 POSTING_READ(PCH_DREF_CONTROL);
8256 udelay(200);
8257
8258 /* Turn off the SSC source */
74cfd7ac
CW		 8259 val &= ~DREF_SSC_SOURCE_MASK;
8260 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8261
8262 /* Turn off SSC1 */
74cfd7ac 8263 val &= ~DREF_SSC1_ENABLE;
199e5d79 8264
74cfd7ac 8265 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8266 POSTING_READ(PCH_DREF_CONTROL);
8267 udelay(200);
8268 }
74cfd7ac
CW		 8269
8270 BUG_ON(val != final);
13d83a67
JB		 8271}
8272
f31f2d55 8273static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8274{
f31f2d55 8275 uint32_t tmp;
dde86e2d 8276
0ff066a9
PZ		 8277 tmp = I915_READ(SOUTH_CHICKEN2);
8278 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8279 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8280
0ff066a9
PZ		 8281 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8282 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8283 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8284
0ff066a9
PZ		 8285 tmp = I915_READ(SOUTH_CHICKEN2);
8286 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8287 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8288
0ff066a9
PZ		 8289 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8290 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8291 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8292}
8293
8294/* WaMPhyProgramming:hsw */
8295static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8296{
8297 uint32_t tmp;
dde86e2d
PZ		 8298
8299 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8300 tmp &= ~(0xFF << 24);
8301 tmp |= (0x12 << 24);
8302 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8303
dde86e2d
PZ		 8304 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8305 tmp |= (1 << 11);
8306 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8307
8308 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8309 tmp |= (1 << 11);
8310 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8311
dde86e2d
PZ		 8312 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8313 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8314 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8315
8316 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8317 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8318 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8319
0ff066a9
PZ		 8320 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8321 tmp &= ~(7 << 13);
8322 tmp |= (5 << 13);
8323 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8324
0ff066a9
PZ		 8325 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8326 tmp &= ~(7 << 13);
8327 tmp |= (5 << 13);
8328 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8329
8330 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8331 tmp &= ~0xFF;
8332 tmp |= 0x1C;
8333 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8334
8335 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8336 tmp &= ~0xFF;
8337 tmp |= 0x1C;
8338 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8339
8340 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8341 tmp &= ~(0xFF << 16);
8342 tmp |= (0x1C << 16);
8343 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8344
8345 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8346 tmp &= ~(0xFF << 16);
8347 tmp |= (0x1C << 16);
8348 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8349
0ff066a9
PZ		 8350 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8351 tmp |= (1 << 27);
8352 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8353
0ff066a9
PZ		 8354 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8355 tmp |= (1 << 27);
8356 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8357
0ff066a9
PZ		 8358 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8359 tmp &= ~(0xF << 28);
8360 tmp |= (4 << 28);
8361 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8362
0ff066a9
PZ		 8363 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8364 tmp &= ~(0xF << 28);
8365 tmp |= (4 << 28);
8366 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8367}
8368
2fa86a1f
PZ		 8369/* Implements 3 different sequences from BSpec chapter "Display iCLK
8370 * Programming" based on the parameters passed:
8371 * - Sequence to enable CLKOUT_DP
8372 * - Sequence to enable CLKOUT_DP without spread
8373 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8374 */
8375static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8376 bool with_fdi)
f31f2d55
PZ		 8377{
8378 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8379 uint32_t reg, tmp;
8380
8381 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8382 with_spread = true;
8383 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8384 with_fdi, "LP PCH doesn't have FDI\n"))
8385 with_fdi = false;
f31f2d55 8386
a580516d 8387 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8388
8389 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8390 tmp &= ~SBI_SSCCTL_DISABLE;
8391 tmp |= SBI_SSCCTL_PATHALT;
8392 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8393
8394 udelay(24);
8395
2fa86a1f
PZ		 8396 if (with_spread) {
8397 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8398 tmp &= ~SBI_SSCCTL_PATHALT;
8399 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8400
2fa86a1f
PZ		 8401 if (with_fdi) {
8402 lpt_reset_fdi_mphy(dev_priv);
8403 lpt_program_fdi_mphy(dev_priv);
8404 }
8405 }
dde86e2d 8406
2fa86a1f
PZ		 8407 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8408 SBI_GEN0 : SBI_DBUFF0;
8409 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8410 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8411 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8412
a580516d 8413 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8414}
8415
47701c3b
PZ		 8416/* Sequence to disable CLKOUT_DP */
8417static void lpt_disable_clkout_dp(struct drm_device *dev)
8418{
8419 struct drm_i915_private *dev_priv = dev->dev_private;
8420 uint32_t reg, tmp;
8421
a580516d 8422 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8423
8424 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8425 SBI_GEN0 : SBI_DBUFF0;
8426 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8427 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8428 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8429
8430 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8431 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8432 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8433 tmp |= SBI_SSCCTL_PATHALT;
8434 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8435 udelay(32);
8436 }
8437 tmp |= SBI_SSCCTL_DISABLE;
8438 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8439 }
8440
a580516d 8441 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8442}
8443
bf8fa3d3
PZ		 8444static void lpt_init_pch_refclk(struct drm_device *dev)
8445{
bf8fa3d3
PZ		 8446 struct intel_encoder *encoder;
8447 bool has_vga = false;
8448
b2784e15 8449 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8450 switch (encoder->type) {
8451 case INTEL_OUTPUT_ANALOG:
8452 has_vga = true;
8453 break;
6847d71b
PZ		 8454 default:
8455 break;
bf8fa3d3
PZ		 8456 }
8457 }
8458
47701c3b
PZ		 8459 if (has_vga)
8460 lpt_enable_clkout_dp(dev, true, true);
8461 else
8462 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8463}
8464
dde86e2d
PZ		 8465/*
8466 * Initialize reference clocks when the driver loads
8467 */
8468void intel_init_pch_refclk(struct drm_device *dev)
8469{
8470 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8471 ironlake_init_pch_refclk(dev);
8472 else if (HAS_PCH_LPT(dev))
8473 lpt_init_pch_refclk(dev);
8474}
8475
55bb9992 8476static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8477{
55bb9992 8478 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8479 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8480 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8481 struct drm_connector *connector;
55bb9992 8482 struct drm_connector_state *connector_state;
d9d444cb 8483 struct intel_encoder *encoder;
55bb9992 8484 int num_connectors = 0, i;
d9d444cb
JB		 8485 bool is_lvds = false;
8486
da3ced29 8487 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8488 if (connector_state->crtc != crtc_state->base.crtc)
8489 continue;
8490
8491 encoder = to_intel_encoder(connector_state->best_encoder);
8492
d9d444cb
JB		 8493 switch (encoder->type) {
8494 case INTEL_OUTPUT_LVDS:
8495 is_lvds = true;
8496 break;
6847d71b
PZ		 8497 default:
8498 break;
d9d444cb
JB		 8499 }
8500 num_connectors++;
8501 }
8502
8503 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8504 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8505 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8506 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8507 }
8508
8509 return 120000;
8510}
8511
6ff93609 8512static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8513{
c8203565 8514 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8516 int pipe = intel_crtc->pipe;
c8203565
PZ		 8517 uint32_t val;
8518
78114071 8519 val = 0;
c8203565 8520
6e3c9717 8521 switch (intel_crtc->config->pipe_bpp) {
c8203565 8522 case 18:
dfd07d72 8523 val |= PIPECONF_6BPC;
c8203565
PZ		 8524 break;
8525 case 24:
dfd07d72 8526 val |= PIPECONF_8BPC;
c8203565
PZ		 8527 break;
8528 case 30:
dfd07d72 8529 val |= PIPECONF_10BPC;
c8203565
PZ		 8530 break;
8531 case 36:
dfd07d72 8532 val |= PIPECONF_12BPC;
c8203565
PZ		 8533 break;
8534 default:
cc769b62
PZ		 8535 /* Case prevented by intel_choose_pipe_bpp_dither. */
8536 BUG();
c8203565
PZ		 8537 }
8538
6e3c9717 8539 if (intel_crtc->config->dither)
c8203565
PZ		 8540 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8541
6e3c9717 8542 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8543 val |= PIPECONF_INTERLACED_ILK;
8544 else
8545 val |= PIPECONF_PROGRESSIVE;
8546
6e3c9717 8547 if (intel_crtc->config->limited_color_range)
3685a8f3 8548 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8549
c8203565
PZ		 8550 I915_WRITE(PIPECONF(pipe), val);
8551 POSTING_READ(PIPECONF(pipe));
8552}
8553
86d3efce
VS		 8554/*
8555 * Set up the pipe CSC unit.
8556 *
8557 * Currently only full range RGB to limited range RGB conversion
8558 * is supported, but eventually this should handle various
8559 * RGB<->YCbCr scenarios as well.
8560 */
50f3b016 8561static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8562{
8563 struct drm_device *dev = crtc->dev;
8564 struct drm_i915_private *dev_priv = dev->dev_private;
8565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8566 int pipe = intel_crtc->pipe;
8567 uint16_t coeff = 0x7800; /* 1.0 */
8568
8569 /*
8570 * TODO: Check what kind of values actually come out of the pipe
8571 * with these coeff/postoff values and adjust to get the best
8572 * accuracy. Perhaps we even need to take the bpc value into
8573 * consideration.
8574 */
8575
6e3c9717 8576 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8577 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8578
8579 /*
8580 * GY/GU and RY/RU should be the other way around according
8581 * to BSpec, but reality doesn't agree. Just set them up in
8582 * a way that results in the correct picture.
8583 */
8584 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8585 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8586
8587 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8588 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8589
8590 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8591 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8592
8593 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8594 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8595 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8596
8597 if (INTEL_INFO(dev)->gen > 6) {
8598 uint16_t postoff = 0;
8599
6e3c9717 8600 if (intel_crtc->config->limited_color_range)
32cf0cb0 8601 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8602
8603 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8604 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8605 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8606
8607 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8608 } else {
8609 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8610
6e3c9717 8611 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8612 mode |= CSC_BLACK_SCREEN_OFFSET;
8613
8614 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8615 }
8616}
8617
6ff93609 8618static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8619{
756f85cf
PZ		 8620 struct drm_device *dev = crtc->dev;
8621 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8623 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8624 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8625 uint32_t val;
8626
3eff4faa 8627 val = 0;
ee2b0b38 8628
6e3c9717 8629 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8630 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8631
6e3c9717 8632 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8633 val |= PIPECONF_INTERLACED_ILK;
8634 else
8635 val |= PIPECONF_PROGRESSIVE;
8636
702e7a56
PZ		 8637 I915_WRITE(PIPECONF(cpu_transcoder), val);
8638 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8639
8640 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8641 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8642
3cdf122c 8643 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8644 val = 0;
8645
6e3c9717 8646 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8647 case 18:
8648 val |= PIPEMISC_DITHER_6_BPC;
8649 break;
8650 case 24:
8651 val |= PIPEMISC_DITHER_8_BPC;
8652 break;
8653 case 30:
8654 val |= PIPEMISC_DITHER_10_BPC;
8655 break;
8656 case 36:
8657 val |= PIPEMISC_DITHER_12_BPC;
8658 break;
8659 default:
8660 /* Case prevented by pipe_config_set_bpp. */
8661 BUG();
8662 }
8663
6e3c9717 8664 if (intel_crtc->config->dither)
756f85cf
PZ		 8665 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8666
8667 I915_WRITE(PIPEMISC(pipe), val);
8668 }
ee2b0b38
PZ		 8669}
8670
6591c6e4 8671static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8672 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8673 intel_clock_t *clock,
8674 bool *has_reduced_clock,
8675 intel_clock_t *reduced_clock)
8676{
8677 struct drm_device *dev = crtc->dev;
8678 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8679 int refclk;
d4906093 8680 const intel_limit_t *limit;
c329a4ec 8681 bool ret;
79e53945 8682
55bb9992 8683 refclk = ironlake_get_refclk(crtc_state);
79e53945 8684
d4906093
ML		 8685 /*
8686 * Returns a set of divisors for the desired target clock with the given
8687 * refclk, or FALSE. The returned values represent the clock equation:
8688 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8689 */
a93e255f
ACO		 8690 limit = intel_limit(crtc_state, refclk);
8691 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8692 crtc_state->port_clock,
ee9300bb 8693 refclk, NULL, clock);
6591c6e4
PZ		 8694 if (!ret)
8695 return false;
cda4b7d3 8696
6591c6e4
PZ		 8697 return true;
8698}
8699
d4b1931c
PZ		 8700int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8701{
8702 /*
8703 * Account for spread spectrum to avoid
8704 * oversubscribing the link. Max center spread
8705 * is 2.5%; use 5% for safety's sake.
8706 */
8707 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8708 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8709}
8710
7429e9d4 8711static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8712{
7429e9d4 8713 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8714}
8715
de13a2e3 8716static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8717 struct intel_crtc_state *crtc_state,
7429e9d4 8718 u32 *fp,
9a7c7890 8719 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8720{
de13a2e3 8721 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8722 struct drm_device *dev = crtc->dev;
8723 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8724 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8725 struct drm_connector *connector;
55bb9992
ACO		 8726 struct drm_connector_state *connector_state;
8727 struct intel_encoder *encoder;
de13a2e3 8728 uint32_t dpll;
55bb9992 8729 int factor, num_connectors = 0, i;
09ede541 8730 bool is_lvds = false, is_sdvo = false;
79e53945 8731
da3ced29 8732 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8733 if (connector_state->crtc != crtc_state->base.crtc)
8734 continue;
8735
8736 encoder = to_intel_encoder(connector_state->best_encoder);
8737
8738 switch (encoder->type) {
79e53945
JB		 8739 case INTEL_OUTPUT_LVDS:
8740 is_lvds = true;
8741 break;
8742 case INTEL_OUTPUT_SDVO:
7d57382e 8743 case INTEL_OUTPUT_HDMI:
79e53945 8744 is_sdvo = true;
79e53945 8745 break;
6847d71b
PZ		 8746 default:
8747 break;
79e53945 8748 }
43565a06 8749
c751ce4f 8750 num_connectors++;
79e53945 8751 }
79e53945 8752
c1858123 8753 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8754 factor = 21;
8755 if (is_lvds) {
8756 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8757 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8758 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8759 factor = 25;
190f68c5 8760 } else if (crtc_state->sdvo_tv_clock)
8febb297 8761 factor = 20;
c1858123 8762
190f68c5 8763 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8764 *fp |= FP_CB_TUNE;
2c07245f 8765
9a7c7890
DV		 8766 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8767 *fp2 |= FP_CB_TUNE;
8768
5eddb70b 8769 dpll = 0;
2c07245f 8770
a07d6787
EA		 8771 if (is_lvds)
8772 dpll |= DPLLB_MODE_LVDS;
8773 else
8774 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8775
190f68c5 8776 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8777 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8778
8779 if (is_sdvo)
4a33e48d 8780 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8781 if (crtc_state->has_dp_encoder)
4a33e48d 8782 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8783
a07d6787 8784 /* compute bitmask from p1 value */
190f68c5 8785 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8786 /* also FPA1 */
190f68c5 8787 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8788
190f68c5 8789 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8790 case 5:
8791 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8792 break;
8793 case 7:
8794 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8795 break;
8796 case 10:
8797 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8798 break;
8799 case 14:
8800 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8801 break;
79e53945
JB		 8802 }
8803
b4c09f3b 8804 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8805 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8806 else
8807 dpll |= PLL_REF_INPUT_DREFCLK;
8808
959e16d6 8809 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8810}
8811
190f68c5
ACO		 8812static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8813 struct intel_crtc_state *crtc_state)
de13a2e3 8814{
c7653199 8815 struct drm_device *dev = crtc->base.dev;
de13a2e3 8816 intel_clock_t clock, reduced_clock;
cbbab5bd 8817 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8818 bool ok, has_reduced_clock = false;
8b47047b 8819 bool is_lvds = false;
e2b78267 8820 struct intel_shared_dpll *pll;
de13a2e3 8821
dd3cd74a
ACO		 8822 memset(&crtc_state->dpll_hw_state, 0,
8823 sizeof(crtc_state->dpll_hw_state));
8824
409ee761 8825 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8826
5dc5298b
PZ		 8827 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8828 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8829
190f68c5 8830 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8831 &has_reduced_clock, &reduced_clock);
190f68c5 8832 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8833 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8834 return -EINVAL;
79e53945 8835 }
f47709a9 8836 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8837 if (!crtc_state->clock_set) {
8838 crtc_state->dpll.n = clock.n;
8839 crtc_state->dpll.m1 = clock.m1;
8840 crtc_state->dpll.m2 = clock.m2;
8841 crtc_state->dpll.p1 = clock.p1;
8842 crtc_state->dpll.p2 = clock.p2;
f47709a9 8843 }
79e53945 8844
5dc5298b 8845 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8846 if (crtc_state->has_pch_encoder) {
8847 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8848 if (has_reduced_clock)
7429e9d4 8849 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8850
190f68c5 8851 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8852 &fp, &reduced_clock,
8853 has_reduced_clock ? &fp2 : NULL);
8854
190f68c5
ACO		 8855 crtc_state->dpll_hw_state.dpll = dpll;
8856 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8857 if (has_reduced_clock)
190f68c5 8858 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8859 else
190f68c5 8860 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8861
190f68c5 8862 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8863 if (pll == NULL) {
84f44ce7 8864 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8865 pipe_name(crtc->pipe));
4b645f14
JB		 8866 return -EINVAL;
8867 }
3fb37703 8868 }
79e53945 8869
ab585dea 8870 if (is_lvds && has_reduced_clock)
c7653199 8871 crtc->lowfreq_avail = true;
bcd644e0 8872 else
c7653199 8873 crtc->lowfreq_avail = false;
e2b78267 8874
c8f7a0db 8875 return 0;
79e53945
JB		 8876}
8877
eb14cb74
VS		 8878static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8879 struct intel_link_m_n *m_n)
8880{
8881 struct drm_device *dev = crtc->base.dev;
8882 struct drm_i915_private *dev_priv = dev->dev_private;
8883 enum pipe pipe = crtc->pipe;
8884
8885 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8886 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8887 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8888 & ~TU_SIZE_MASK;
8889 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8890 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8891 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8892}
8893
8894static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8895 enum transcoder transcoder,
b95af8be
VK		 8896 struct intel_link_m_n *m_n,
8897 struct intel_link_m_n *m2_n2)
72419203
DV		 8898{
8899 struct drm_device *dev = crtc->base.dev;
8900 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8901 enum pipe pipe = crtc->pipe;
72419203 8902
eb14cb74
VS		 8903 if (INTEL_INFO(dev)->gen >= 5) {
8904 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8905 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8906 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8907 & ~TU_SIZE_MASK;
8908 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8909 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8910 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8911 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8912 * gen < 8) and if DRRS is supported (to make sure the
8913 * registers are not unnecessarily read).
8914 */
8915 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8916 crtc->config->has_drrs) {
b95af8be
VK		 8917 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8918 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8919 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8920 & ~TU_SIZE_MASK;
8921 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8922 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8923 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8924 }
eb14cb74
VS		 8925 } else {
8926 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8927 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8928 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8929 & ~TU_SIZE_MASK;
8930 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8931 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8932 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8933 }
8934}
8935
8936void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8937 struct intel_crtc_state *pipe_config)
eb14cb74 8938{
681a8504 8939 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8940 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8941 else
8942 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8943 &pipe_config->dp_m_n,
8944 &pipe_config->dp_m2_n2);
eb14cb74 8945}
72419203 8946
eb14cb74 8947static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8948 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8949{
8950 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8951 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8952}
8953
bd2e244f 8954static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8955 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8956{
8957 struct drm_device *dev = crtc->base.dev;
8958 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8959 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8960 uint32_t ps_ctrl = 0;
8961 int id = -1;
8962 int i;
bd2e244f 8963
a1b2278e
CK		 8964 /* find scaler attached to this pipe */
8965 for (i = 0; i < crtc->num_scalers; i++) {
8966 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8967 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8968 id = i;
8969 pipe_config->pch_pfit.enabled = true;
8970 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8971 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8972 break;
8973 }
8974 }
bd2e244f 8975
a1b2278e
CK		 8976 scaler_state->scaler_id = id;
8977 if (id >= 0) {
8978 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8979 } else {
8980 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8981 }
8982}
8983
5724dbd1
DL		 8984static void
8985skylake_get_initial_plane_config(struct intel_crtc *crtc,
8986 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8987{
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8990 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8991 int pipe = crtc->pipe;
8992 int fourcc, pixel_format;
6761dd31 8993 unsigned int aligned_height;
bc8d7dff 8994 struct drm_framebuffer *fb;
1b842c89 8995 struct intel_framebuffer *intel_fb;
bc8d7dff 8996
d9806c9f 8997 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8998 if (!intel_fb) {
bc8d7dff
DL		 8999 DRM_DEBUG_KMS("failed to alloc fb\n");
9000 return;
9001 }
9002
1b842c89
DL		 9003 fb = &intel_fb->base;
9004
bc8d7dff 9005 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9006 if (!(val & PLANE_CTL_ENABLE))
9007 goto error;
9008
bc8d7dff
DL		 9009 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9010 fourcc = skl_format_to_fourcc(pixel_format,
9011 val & PLANE_CTL_ORDER_RGBX,
9012 val & PLANE_CTL_ALPHA_MASK);
9013 fb->pixel_format = fourcc;
9014 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9015
40f46283
DL		 9016 tiling = val & PLANE_CTL_TILED_MASK;
9017 switch (tiling) {
9018 case PLANE_CTL_TILED_LINEAR:
9019 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9020 break;
9021 case PLANE_CTL_TILED_X:
9022 plane_config->tiling = I915_TILING_X;
9023 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9024 break;
9025 case PLANE_CTL_TILED_Y:
9026 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9027 break;
9028 case PLANE_CTL_TILED_YF:
9029 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9030 break;
9031 default:
9032 MISSING_CASE(tiling);
9033 goto error;
9034 }
9035
bc8d7dff
DL		 9036 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9037 plane_config->base = base;
9038
9039 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9040
9041 val = I915_READ(PLANE_SIZE(pipe, 0));
9042 fb->height = ((val >> 16) & 0xfff) + 1;
9043 fb->width = ((val >> 0) & 0x1fff) + 1;
9044
9045 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9046 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9047 fb->pixel_format);
bc8d7dff
DL		 9048 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9049
9050 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9051 fb->pixel_format,
9052 fb->modifier[0]);
bc8d7dff 9053
f37b5c2b 9054 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9055
9056 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9057 pipe_name(pipe), fb->width, fb->height,
9058 fb->bits_per_pixel, base, fb->pitches[0],
9059 plane_config->size);
9060
2d14030b 9061 plane_config->fb = intel_fb;
bc8d7dff
DL		 9062 return;
9063
9064error:
9065 kfree(fb);
9066}
9067
2fa2fe9a 9068static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9069 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9070{
9071 struct drm_device *dev = crtc->base.dev;
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 uint32_t tmp;
9074
9075 tmp = I915_READ(PF_CTL(crtc->pipe));
9076
9077 if (tmp & PF_ENABLE) {
fd4daa9c 9078 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9079 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9080 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9081
9082 /* We currently do not free assignements of panel fitters on
9083 * ivb/hsw (since we don't use the higher upscaling modes which
9084 * differentiates them) so just WARN about this case for now. */
9085 if (IS_GEN7(dev)) {
9086 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9087 PF_PIPE_SEL_IVB(crtc->pipe));
9088 }
2fa2fe9a 9089 }
79e53945
JB		 9090}
9091
5724dbd1
DL		 9092static void
9093ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9094 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9095{
9096 struct drm_device *dev = crtc->base.dev;
9097 struct drm_i915_private *dev_priv = dev->dev_private;
9098 u32 val, base, offset;
aeee5a49 9099 int pipe = crtc->pipe;
4c6baa59 9100 int fourcc, pixel_format;
6761dd31 9101 unsigned int aligned_height;
b113d5ee 9102 struct drm_framebuffer *fb;
1b842c89 9103 struct intel_framebuffer *intel_fb;
4c6baa59 9104
42a7b088
DL		 9105 val = I915_READ(DSPCNTR(pipe));
9106 if (!(val & DISPLAY_PLANE_ENABLE))
9107 return;
9108
d9806c9f 9109 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9110 if (!intel_fb) {
4c6baa59
JB		 9111 DRM_DEBUG_KMS("failed to alloc fb\n");
9112 return;
9113 }
9114
1b842c89
DL		 9115 fb = &intel_fb->base;
9116
18c5247e
DV		 9117 if (INTEL_INFO(dev)->gen >= 4) {
9118 if (val & DISPPLANE_TILED) {
49af449b 9119 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9120 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9121 }
9122 }
4c6baa59
JB		 9123
9124 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9125 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9126 fb->pixel_format = fourcc;
9127 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9128
aeee5a49 9129 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9130 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9131 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9132 } else {
49af449b 9133 if (plane_config->tiling)
aeee5a49 9134 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9135 else
aeee5a49 9136 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9137 }
9138 plane_config->base = base;
9139
9140 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9141 fb->width = ((val >> 16) & 0xfff) + 1;
9142 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9143
9144 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9145 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9146
b113d5ee 9147 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9148 fb->pixel_format,
9149 fb->modifier[0]);
4c6baa59 9150
f37b5c2b 9151 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9152
2844a921
DL		 9153 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9154 pipe_name(pipe), fb->width, fb->height,
9155 fb->bits_per_pixel, base, fb->pitches[0],
9156 plane_config->size);
b113d5ee 9157
2d14030b 9158 plane_config->fb = intel_fb;
4c6baa59
JB		 9159}
9160
0e8ffe1b 9161static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9162 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9163{
9164 struct drm_device *dev = crtc->base.dev;
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9166 uint32_t tmp;
9167
f458ebbc
DV		 9168 if (!intel_display_power_is_enabled(dev_priv,
9169 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9170 return false;
9171
e143a21c 9172 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9173 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9174
0e8ffe1b
DV		 9175 tmp = I915_READ(PIPECONF(crtc->pipe));
9176 if (!(tmp & PIPECONF_ENABLE))
9177 return false;
9178
42571aef
VS		 9179 switch (tmp & PIPECONF_BPC_MASK) {
9180 case PIPECONF_6BPC:
9181 pipe_config->pipe_bpp = 18;
9182 break;
9183 case PIPECONF_8BPC:
9184 pipe_config->pipe_bpp = 24;
9185 break;
9186 case PIPECONF_10BPC:
9187 pipe_config->pipe_bpp = 30;
9188 break;
9189 case PIPECONF_12BPC:
9190 pipe_config->pipe_bpp = 36;
9191 break;
9192 default:
9193 break;
9194 }
9195
b5a9fa09
DV		 9196 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9197 pipe_config->limited_color_range = true;
9198
ab9412ba 9199 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9200 struct intel_shared_dpll *pll;
9201
88adfff1
DV		 9202 pipe_config->has_pch_encoder = true;
9203
627eb5a3
DV		 9204 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9205 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9206 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9207
9208 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9209
c0d43d62 9210 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9211 pipe_config->shared_dpll =
9212 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9213 } else {
9214 tmp = I915_READ(PCH_DPLL_SEL);
9215 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9216 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9217 else
9218 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9219 }
66e985c0
DV		 9220
9221 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9222
9223 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9224 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9225
9226 tmp = pipe_config->dpll_hw_state.dpll;
9227 pipe_config->pixel_multiplier =
9228 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9229 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9230
9231 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9232 } else {
9233 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9234 }
9235
1bd1bd80
DV		 9236 intel_get_pipe_timings(crtc, pipe_config);
9237
2fa2fe9a
DV		 9238 ironlake_get_pfit_config(crtc, pipe_config);
9239
0e8ffe1b
DV		 9240 return true;
9241}
9242
be256dc7
PZ		 9243static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9244{
9245 struct drm_device *dev = dev_priv->dev;
be256dc7 9246 struct intel_crtc *crtc;
be256dc7 9247
d3fcc808 9248 for_each_intel_crtc(dev, crtc)
e2c719b7 9249 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9250 pipe_name(crtc->pipe));
9251
e2c719b7
RC		 9252 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9253 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9254 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9255 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9256 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9257 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9258 "CPU PWM1 enabled\n");
c5107b87 9259 if (IS_HASWELL(dev))
e2c719b7 9260 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9261 "CPU PWM2 enabled\n");
e2c719b7 9262 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9263 "PCH PWM1 enabled\n");
e2c719b7 9264 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9265 "Utility pin enabled\n");
e2c719b7 9266 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9267
9926ada1
PZ		 9268 /*
9269 * In theory we can still leave IRQs enabled, as long as only the HPD
9270 * interrupts remain enabled. We used to check for that, but since it's
9271 * gen-specific and since we only disable LCPLL after we fully disable
9272 * the interrupts, the check below should be enough.
9273 */
e2c719b7 9274 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9275}
9276
9ccd5aeb
PZ		 9277static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9278{
9279 struct drm_device *dev = dev_priv->dev;
9280
9281 if (IS_HASWELL(dev))
9282 return I915_READ(D_COMP_HSW);
9283 else
9284 return I915_READ(D_COMP_BDW);
9285}
9286
3c4c9b81
PZ		 9287static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9288{
9289 struct drm_device *dev = dev_priv->dev;
9290
9291 if (IS_HASWELL(dev)) {
9292 mutex_lock(&dev_priv->rps.hw_lock);
9293 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9294 val))
f475dadf 9295 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9296 mutex_unlock(&dev_priv->rps.hw_lock);
9297 } else {
9ccd5aeb
PZ		 9298 I915_WRITE(D_COMP_BDW, val);
9299 POSTING_READ(D_COMP_BDW);
3c4c9b81 9300 }
be256dc7
PZ		 9301}
9302
9303/*
9304 * This function implements pieces of two sequences from BSpec:
9305 * - Sequence for display software to disable LCPLL
9306 * - Sequence for display software to allow package C8+
9307 * The steps implemented here are just the steps that actually touch the LCPLL
9308 * register. Callers should take care of disabling all the display engine
9309 * functions, doing the mode unset, fixing interrupts, etc.
9310 */
6ff58d53
PZ		 9311static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9312 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9313{
9314 uint32_t val;
9315
9316 assert_can_disable_lcpll(dev_priv);
9317
9318 val = I915_READ(LCPLL_CTL);
9319
9320 if (switch_to_fclk) {
9321 val |= LCPLL_CD_SOURCE_FCLK;
9322 I915_WRITE(LCPLL_CTL, val);
9323
9324 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9325 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9326 DRM_ERROR("Switching to FCLK failed\n");
9327
9328 val = I915_READ(LCPLL_CTL);
9329 }
9330
9331 val |= LCPLL_PLL_DISABLE;
9332 I915_WRITE(LCPLL_CTL, val);
9333 POSTING_READ(LCPLL_CTL);
9334
9335 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9336 DRM_ERROR("LCPLL still locked\n");
9337
9ccd5aeb 9338 val = hsw_read_dcomp(dev_priv);
be256dc7 9339 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9340 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9341 ndelay(100);
9342
9ccd5aeb
PZ		 9343 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9344 1))
be256dc7
PZ		 9345 DRM_ERROR("D_COMP RCOMP still in progress\n");
9346
9347 if (allow_power_down) {
9348 val = I915_READ(LCPLL_CTL);
9349 val |= LCPLL_POWER_DOWN_ALLOW;
9350 I915_WRITE(LCPLL_CTL, val);
9351 POSTING_READ(LCPLL_CTL);
9352 }
9353}
9354
9355/*
9356 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9357 * source.
9358 */
6ff58d53 9359static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9360{
9361 uint32_t val;
9362
9363 val = I915_READ(LCPLL_CTL);
9364
9365 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9366 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9367 return;
9368
a8a8bd54
PZ		 9369 /*
9370 * Make sure we're not on PC8 state before disabling PC8, otherwise
9371 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9372 */
59bad947 9373 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9374
be256dc7
PZ		 9375 if (val & LCPLL_POWER_DOWN_ALLOW) {
9376 val &= ~LCPLL_POWER_DOWN_ALLOW;
9377 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9378 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9379 }
9380
9ccd5aeb 9381 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9382 val |= D_COMP_COMP_FORCE;
9383 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9384 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9385
9386 val = I915_READ(LCPLL_CTL);
9387 val &= ~LCPLL_PLL_DISABLE;
9388 I915_WRITE(LCPLL_CTL, val);
9389
9390 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9391 DRM_ERROR("LCPLL not locked yet\n");
9392
9393 if (val & LCPLL_CD_SOURCE_FCLK) {
9394 val = I915_READ(LCPLL_CTL);
9395 val &= ~LCPLL_CD_SOURCE_FCLK;
9396 I915_WRITE(LCPLL_CTL, val);
9397
9398 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9399 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9400 DRM_ERROR("Switching back to LCPLL failed\n");
9401 }
215733fa 9402
59bad947 9403 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9404 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9405}
9406
765dab67
PZ		 9407/*
9408 * Package states C8 and deeper are really deep PC states that can only be
9409 * reached when all the devices on the system allow it, so even if the graphics
9410 * device allows PC8+, it doesn't mean the system will actually get to these
9411 * states. Our driver only allows PC8+ when going into runtime PM.
9412 *
9413 * The requirements for PC8+ are that all the outputs are disabled, the power
9414 * well is disabled and most interrupts are disabled, and these are also
9415 * requirements for runtime PM. When these conditions are met, we manually do
9416 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9417 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9418 * hang the machine.
9419 *
9420 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9421 * the state of some registers, so when we come back from PC8+ we need to
9422 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9423 * need to take care of the registers kept by RC6. Notice that this happens even
9424 * if we don't put the device in PCI D3 state (which is what currently happens
9425 * because of the runtime PM support).
9426 *
9427 * For more, read "Display Sequences for Package C8" on the hardware
9428 * documentation.
9429 */
a14cb6fc 9430void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9431{
c67a470b
PZ		 9432 struct drm_device *dev = dev_priv->dev;
9433 uint32_t val;
9434
c67a470b
PZ		 9435 DRM_DEBUG_KMS("Enabling package C8+\n");
9436
c67a470b
PZ		 9437 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9438 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9439 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9440 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9441 }
9442
9443 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9444 hsw_disable_lcpll(dev_priv, true, true);
9445}
9446
a14cb6fc 9447void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9448{
9449 struct drm_device *dev = dev_priv->dev;
9450 uint32_t val;
9451
c67a470b
PZ		 9452 DRM_DEBUG_KMS("Disabling package C8+\n");
9453
9454 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9455 lpt_init_pch_refclk(dev);
9456
9457 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9459 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9461 }
9462
9463 intel_prepare_ddi(dev);
c67a470b
PZ		 9464}
9465
27c329ed 9466static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9467{
a821fc46 9468 struct drm_device *dev = old_state->dev;
27c329ed 9469 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9470
27c329ed 9471 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9472}
9473
b432e5cf 9474/* compute the max rate for new configuration */
27c329ed 9475static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9476{
b432e5cf 9477 struct intel_crtc *intel_crtc;
27c329ed 9478 struct intel_crtc_state *crtc_state;
b432e5cf 9479 int max_pixel_rate = 0;
b432e5cf 9480
27c329ed
ML		 9481 for_each_intel_crtc(state->dev, intel_crtc) {
9482 int pixel_rate;
9483
9484 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9485 if (IS_ERR(crtc_state))
9486 return PTR_ERR(crtc_state);
9487
9488 if (!crtc_state->base.enable)
b432e5cf
VS		 9489 continue;
9490
27c329ed 9491 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9492
9493 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9494 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9495 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9496
9497 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9498 }
9499
9500 return max_pixel_rate;
9501}
9502
9503static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9504{
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506 uint32_t val, data;
9507 int ret;
9508
9509 if (WARN((I915_READ(LCPLL_CTL) &
9510 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9511 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9512 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9513 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9514 "trying to change cdclk frequency with cdclk not enabled\n"))
9515 return;
9516
9517 mutex_lock(&dev_priv->rps.hw_lock);
9518 ret = sandybridge_pcode_write(dev_priv,
9519 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9520 mutex_unlock(&dev_priv->rps.hw_lock);
9521 if (ret) {
9522 DRM_ERROR("failed to inform pcode about cdclk change\n");
9523 return;
9524 }
9525
9526 val = I915_READ(LCPLL_CTL);
9527 val |= LCPLL_CD_SOURCE_FCLK;
9528 I915_WRITE(LCPLL_CTL, val);
9529
9530 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9531 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9532 DRM_ERROR("Switching to FCLK failed\n");
9533
9534 val = I915_READ(LCPLL_CTL);
9535 val &= ~LCPLL_CLK_FREQ_MASK;
9536
9537 switch (cdclk) {
9538 case 450000:
9539 val |= LCPLL_CLK_FREQ_450;
9540 data = 0;
9541 break;
9542 case 540000:
9543 val |= LCPLL_CLK_FREQ_54O_BDW;
9544 data = 1;
9545 break;
9546 case 337500:
9547 val |= LCPLL_CLK_FREQ_337_5_BDW;
9548 data = 2;
9549 break;
9550 case 675000:
9551 val |= LCPLL_CLK_FREQ_675_BDW;
9552 data = 3;
9553 break;
9554 default:
9555 WARN(1, "invalid cdclk frequency\n");
9556 return;
9557 }
9558
9559 I915_WRITE(LCPLL_CTL, val);
9560
9561 val = I915_READ(LCPLL_CTL);
9562 val &= ~LCPLL_CD_SOURCE_FCLK;
9563 I915_WRITE(LCPLL_CTL, val);
9564
9565 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9566 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9567 DRM_ERROR("Switching back to LCPLL failed\n");
9568
9569 mutex_lock(&dev_priv->rps.hw_lock);
9570 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9571 mutex_unlock(&dev_priv->rps.hw_lock);
9572
9573 intel_update_cdclk(dev);
9574
9575 WARN(cdclk != dev_priv->cdclk_freq,
9576 "cdclk requested %d kHz but got %d kHz\n",
9577 cdclk, dev_priv->cdclk_freq);
9578}
9579
27c329ed 9580static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9581{
27c329ed
ML		 9582 struct drm_i915_private *dev_priv = to_i915(state->dev);
9583 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9584 int cdclk;
9585
9586 /*
9587 * FIXME should also account for plane ratio
9588 * once 64bpp pixel formats are supported.
9589 */
27c329ed 9590 if (max_pixclk > 540000)
b432e5cf 9591 cdclk = 675000;
27c329ed 9592 else if (max_pixclk > 450000)
b432e5cf 9593 cdclk = 540000;
27c329ed 9594 else if (max_pixclk > 337500)
b432e5cf
VS		 9595 cdclk = 450000;
9596 else
9597 cdclk = 337500;
9598
9599 /*
9600 * FIXME move the cdclk caclulation to
9601 * compute_config() so we can fail gracegully.
9602 */
9603 if (cdclk > dev_priv->max_cdclk_freq) {
9604 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9605 cdclk, dev_priv->max_cdclk_freq);
9606 cdclk = dev_priv->max_cdclk_freq;
9607 }
9608
27c329ed 9609 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9610
9611 return 0;
9612}
9613
27c329ed 9614static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9615{
27c329ed
ML		 9616 struct drm_device *dev = old_state->dev;
9617 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9618
27c329ed 9619 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9620}
9621
190f68c5
ACO		 9622static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9623 struct intel_crtc_state *crtc_state)
09b4ddf9 9624{
190f68c5 9625 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9626 return -EINVAL;
716c2e55 9627
c7653199 9628 crtc->lowfreq_avail = false;
644cef34 9629
c8f7a0db 9630 return 0;
79e53945
JB		 9631}
9632
3760b59c
S		 9633static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9634 enum port port,
9635 struct intel_crtc_state *pipe_config)
9636{
9637 switch (port) {
9638 case PORT_A:
9639 pipe_config->ddi_pll_sel = SKL_DPLL0;
9640 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9641 break;
9642 case PORT_B:
9643 pipe_config->ddi_pll_sel = SKL_DPLL1;
9644 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9645 break;
9646 case PORT_C:
9647 pipe_config->ddi_pll_sel = SKL_DPLL2;
9648 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9649 break;
9650 default:
9651 DRM_ERROR("Incorrect port type\n");
9652 }
9653}
9654
96b7dfb7
S		 9655static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9656 enum port port,
5cec258b 9657 struct intel_crtc_state *pipe_config)
96b7dfb7 9658{
3148ade7 9659 u32 temp, dpll_ctl1;
96b7dfb7
S		 9660
9661 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9662 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9663
9664 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9665 case SKL_DPLL0:
9666 /*
9667 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9668 * of the shared DPLL framework and thus needs to be read out
9669 * separately
9670 */
9671 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9672 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9673 break;
96b7dfb7
S		 9674 case SKL_DPLL1:
9675 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9676 break;
9677 case SKL_DPLL2:
9678 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9679 break;
9680 case SKL_DPLL3:
9681 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9682 break;
96b7dfb7
S		 9683 }
9684}
9685
7d2c8175
DL		 9686static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9687 enum port port,
5cec258b 9688 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9689{
9690 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9691
9692 switch (pipe_config->ddi_pll_sel) {
9693 case PORT_CLK_SEL_WRPLL1:
9694 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9695 break;
9696 case PORT_CLK_SEL_WRPLL2:
9697 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9698 break;
9699 }
9700}
9701
26804afd 9702static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9703 struct intel_crtc_state *pipe_config)
26804afd
DV		 9704{
9705 struct drm_device *dev = crtc->base.dev;
9706 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9707 struct intel_shared_dpll *pll;
26804afd
DV		 9708 enum port port;
9709 uint32_t tmp;
9710
9711 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9712
9713 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9714
96b7dfb7
S		 9715 if (IS_SKYLAKE(dev))
9716 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9717 else if (IS_BROXTON(dev))
9718 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9719 else
9720 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9721
d452c5b6
DV		 9722 if (pipe_config->shared_dpll >= 0) {
9723 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9724
9725 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9726 &pipe_config->dpll_hw_state));
9727 }
9728
26804afd
DV		 9729 /*
9730 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9731 * DDI E. So just check whether this pipe is wired to DDI E and whether
9732 * the PCH transcoder is on.
9733 */
ca370455
DL		 9734 if (INTEL_INFO(dev)->gen < 9 &&
9735 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9736 pipe_config->has_pch_encoder = true;
9737
9738 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9739 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9740 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9741
9742 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9743 }
9744}
9745
0e8ffe1b 9746static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9747 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9748{
9749 struct drm_device *dev = crtc->base.dev;
9750 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9751 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9752 uint32_t tmp;
9753
f458ebbc 9754 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9755 POWER_DOMAIN_PIPE(crtc->pipe)))
9756 return false;
9757
e143a21c 9758 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9759 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9760
eccb140b
DV		 9761 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9762 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9763 enum pipe trans_edp_pipe;
9764 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9765 default:
9766 WARN(1, "unknown pipe linked to edp transcoder\n");
9767 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9768 case TRANS_DDI_EDP_INPUT_A_ON:
9769 trans_edp_pipe = PIPE_A;
9770 break;
9771 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9772 trans_edp_pipe = PIPE_B;
9773 break;
9774 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9775 trans_edp_pipe = PIPE_C;
9776 break;
9777 }
9778
9779 if (trans_edp_pipe == crtc->pipe)
9780 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9781 }
9782
f458ebbc 9783 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9784 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9785 return false;
9786
eccb140b 9787 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9788 if (!(tmp & PIPECONF_ENABLE))
9789 return false;
9790
26804afd 9791 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9792
1bd1bd80
DV		 9793 intel_get_pipe_timings(crtc, pipe_config);
9794
a1b2278e
CK		 9795 if (INTEL_INFO(dev)->gen >= 9) {
9796 skl_init_scalers(dev, crtc, pipe_config);
9797 }
9798
2fa2fe9a 9799 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9800
9801 if (INTEL_INFO(dev)->gen >= 9) {
9802 pipe_config->scaler_state.scaler_id = -1;
9803 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9804 }
9805
bd2e244f 9806 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9807 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9808 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9809 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9810 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9811 else
9812 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9813 }
88adfff1 9814
e59150dc
JB		 9815 if (IS_HASWELL(dev))
9816 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9817 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9818
ebb69c95
CT		 9819 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9820 pipe_config->pixel_multiplier =
9821 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9822 } else {
9823 pipe_config->pixel_multiplier = 1;
9824 }
6c49f241 9825
0e8ffe1b
DV		 9826 return true;
9827}
9828
560b85bb
CW		 9829static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9830{
9831 struct drm_device *dev = crtc->dev;
9832 struct drm_i915_private *dev_priv = dev->dev_private;
9833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9834 uint32_t cntl = 0, size = 0;
560b85bb 9835
dc41c154 9836 if (base) {
3dd512fb
MR		 9837 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9838 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9839 unsigned int stride = roundup_pow_of_two(width) * 4;
9840
9841 switch (stride) {
9842 default:
9843 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9844 width, stride);
9845 stride = 256;
9846 /* fallthrough */
9847 case 256:
9848 case 512:
9849 case 1024:
9850 case 2048:
9851 break;
4b0e333e
CW		 9852 }
9853
dc41c154
VS		 9854 cntl |= CURSOR_ENABLE |
9855 CURSOR_GAMMA_ENABLE |
9856 CURSOR_FORMAT_ARGB |
9857 CURSOR_STRIDE(stride);
9858
9859 size = (height << 12) | width;
4b0e333e 9860 }
560b85bb 9861
dc41c154
VS		 9862 if (intel_crtc->cursor_cntl != 0 &&
9863 (intel_crtc->cursor_base != base ||
9864 intel_crtc->cursor_size != size ||
9865 intel_crtc->cursor_cntl != cntl)) {
9866 /* On these chipsets we can only modify the base/size/stride
9867 * whilst the cursor is disabled.
9868 */
9869 I915_WRITE(_CURACNTR, 0);
4b0e333e 9870 POSTING_READ(_CURACNTR);
dc41c154 9871 intel_crtc->cursor_cntl = 0;
4b0e333e 9872 }
560b85bb 9873
99d1f387 9874 if (intel_crtc->cursor_base != base) {
9db4a9c7 9875 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9876 intel_crtc->cursor_base = base;
9877 }
4726e0b0 9878
dc41c154
VS		 9879 if (intel_crtc->cursor_size != size) {
9880 I915_WRITE(CURSIZE, size);
9881 intel_crtc->cursor_size = size;
4b0e333e 9882 }
560b85bb 9883
4b0e333e 9884 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9885 I915_WRITE(_CURACNTR, cntl);
9886 POSTING_READ(_CURACNTR);
4b0e333e 9887 intel_crtc->cursor_cntl = cntl;
560b85bb 9888 }
560b85bb
CW		 9889}
9890
560b85bb 9891static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9892{
9893 struct drm_device *dev = crtc->dev;
9894 struct drm_i915_private *dev_priv = dev->dev_private;
9895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9896 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9897 uint32_t cntl;
9898
9899 cntl = 0;
9900 if (base) {
9901 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9902 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9903 case 64:
9904 cntl |= CURSOR_MODE_64_ARGB_AX;
9905 break;
9906 case 128:
9907 cntl |= CURSOR_MODE_128_ARGB_AX;
9908 break;
9909 case 256:
9910 cntl |= CURSOR_MODE_256_ARGB_AX;
9911 break;
9912 default:
3dd512fb 9913 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9914 return;
65a21cd6 9915 }
4b0e333e 9916 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9917
9918 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9919 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9920 }
65a21cd6 9921
8e7d688b 9922 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9923 cntl |= CURSOR_ROTATE_180;
9924
4b0e333e
CW		 9925 if (intel_crtc->cursor_cntl != cntl) {
9926 I915_WRITE(CURCNTR(pipe), cntl);
9927 POSTING_READ(CURCNTR(pipe));
9928 intel_crtc->cursor_cntl = cntl;
65a21cd6 9929 }
4b0e333e 9930
65a21cd6 9931 /* and commit changes on next vblank */
5efb3e28
VS		 9932 I915_WRITE(CURBASE(pipe), base);
9933 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9934
9935 intel_crtc->cursor_base = base;
65a21cd6
JB		 9936}
9937
cda4b7d3 9938/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9939static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9940 bool on)
cda4b7d3
CW		 9941{
9942 struct drm_device *dev = crtc->dev;
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9945 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9946 int x = crtc->cursor_x;
9947 int y = crtc->cursor_y;
d6e4db15 9948 u32 base = 0, pos = 0;
cda4b7d3 9949
d6e4db15 9950 if (on)
cda4b7d3 9951 base = intel_crtc->cursor_addr;
cda4b7d3 9952
6e3c9717 9953 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9954 base = 0;
9955
6e3c9717 9956 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9957 base = 0;
9958
9959 if (x < 0) {
3dd512fb 9960 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9961 base = 0;
9962
9963 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9964 x = -x;
9965 }
9966 pos |= x << CURSOR_X_SHIFT;
9967
9968 if (y < 0) {
3dd512fb 9969 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9970 base = 0;
9971
9972 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9973 y = -y;
9974 }
9975 pos |= y << CURSOR_Y_SHIFT;
9976
4b0e333e 9977 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9978 return;
9979
5efb3e28
VS		 9980 I915_WRITE(CURPOS(pipe), pos);
9981
4398ad45
VS		 9982 /* ILK+ do this automagically */
9983 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9984 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9985 base += (intel_crtc->base.cursor->state->crtc_h *
9986 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9987 }
9988
8ac54669 9989 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9990 i845_update_cursor(crtc, base);
9991 else
9992 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9993}
9994
dc41c154
VS		 9995static bool cursor_size_ok(struct drm_device *dev,
9996 uint32_t width, uint32_t height)
9997{
9998 if (width == 0 || height == 0)
9999 return false;
10000
10001 /*
10002 * 845g/865g are special in that they are only limited by
10003 * the width of their cursors, the height is arbitrary up to
10004 * the precision of the register. Everything else requires
10005 * square cursors, limited to a few power-of-two sizes.
10006 */
10007 if (IS_845G(dev) || IS_I865G(dev)) {
10008 if ((width & 63) != 0)
10009 return false;
10010
10011 if (width > (IS_845G(dev) ? 64 : 512))
10012 return false;
10013
10014 if (height > 1023)
10015 return false;
10016 } else {
10017 switch (width | height) {
10018 case 256:
10019 case 128:
10020 if (IS_GEN2(dev))
10021 return false;
10022 case 64:
10023 break;
10024 default:
10025 return false;
10026 }
10027 }
10028
10029 return true;
10030}
10031
79e53945 10032static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10033 u16 *blue, uint32_t start, uint32_t size)
79e53945 10034{
7203425a 10035 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10037
7203425a 10038 for (i = start; i < end; i++) {
79e53945
JB		 10039 intel_crtc->lut_r[i] = red[i] >> 8;
10040 intel_crtc->lut_g[i] = green[i] >> 8;
10041 intel_crtc->lut_b[i] = blue[i] >> 8;
10042 }
10043
10044 intel_crtc_load_lut(crtc);
10045}
10046
79e53945
JB		 10047/* VESA 640x480x72Hz mode to set on the pipe */
10048static struct drm_display_mode load_detect_mode = {
10049 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10050 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10051};
10052
a8bb6818
DV		 10053struct drm_framebuffer *
10054__intel_framebuffer_create(struct drm_device *dev,
10055 struct drm_mode_fb_cmd2 *mode_cmd,
10056 struct drm_i915_gem_object *obj)
d2dff872
CW		 10057{
10058 struct intel_framebuffer *intel_fb;
10059 int ret;
10060
10061 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10062 if (!intel_fb) {
6ccb81f2 10063 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10064 return ERR_PTR(-ENOMEM);
10065 }
10066
10067 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10068 if (ret)
10069 goto err;
d2dff872
CW		 10070
10071 return &intel_fb->base;
dd4916c5 10072err:
6ccb81f2 10073 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10074 kfree(intel_fb);
10075
10076 return ERR_PTR(ret);
d2dff872
CW		 10077}
10078
b5ea642a 10079static struct drm_framebuffer *
a8bb6818
DV		 10080intel_framebuffer_create(struct drm_device *dev,
10081 struct drm_mode_fb_cmd2 *mode_cmd,
10082 struct drm_i915_gem_object *obj)
10083{
10084 struct drm_framebuffer *fb;
10085 int ret;
10086
10087 ret = i915_mutex_lock_interruptible(dev);
10088 if (ret)
10089 return ERR_PTR(ret);
10090 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10091 mutex_unlock(&dev->struct_mutex);
10092
10093 return fb;
10094}
10095
d2dff872
CW		 10096static u32
10097intel_framebuffer_pitch_for_width(int width, int bpp)
10098{
10099 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10100 return ALIGN(pitch, 64);
10101}
10102
10103static u32
10104intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10105{
10106 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10107 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10108}
10109
10110static struct drm_framebuffer *
10111intel_framebuffer_create_for_mode(struct drm_device *dev,
10112 struct drm_display_mode *mode,
10113 int depth, int bpp)
10114{
10115 struct drm_i915_gem_object *obj;
0fed39bd 10116 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10117
10118 obj = i915_gem_alloc_object(dev,
10119 intel_framebuffer_size_for_mode(mode, bpp));
10120 if (obj == NULL)
10121 return ERR_PTR(-ENOMEM);
10122
10123 mode_cmd.width = mode->hdisplay;
10124 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10125 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10126 bpp);
5ca0c34a 10127 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10128
10129 return intel_framebuffer_create(dev, &mode_cmd, obj);
10130}
10131
10132static struct drm_framebuffer *
10133mode_fits_in_fbdev(struct drm_device *dev,
10134 struct drm_display_mode *mode)
10135{
0695726e 10136#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10137 struct drm_i915_private *dev_priv = dev->dev_private;
10138 struct drm_i915_gem_object *obj;
10139 struct drm_framebuffer *fb;
10140
4c0e5528 10141 if (!dev_priv->fbdev)
d2dff872
CW		 10142 return NULL;
10143
4c0e5528 10144 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10145 return NULL;
10146
4c0e5528
DV		 10147 obj = dev_priv->fbdev->fb->obj;
10148 BUG_ON(!obj);
10149
8bcd4553 10150 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10151 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10152 fb->bits_per_pixel))
d2dff872
CW		 10153 return NULL;
10154
01f2c773 10155 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10156 return NULL;
10157
10158 return fb;
4520f53a
DV		 10159#else
10160 return NULL;
10161#endif
d2dff872
CW		 10162}
10163
d3a40d1b
ACO		 10164static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10165 struct drm_crtc *crtc,
10166 struct drm_display_mode *mode,
10167 struct drm_framebuffer *fb,
10168 int x, int y)
10169{
10170 struct drm_plane_state *plane_state;
10171 int hdisplay, vdisplay;
10172 int ret;
10173
10174 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10175 if (IS_ERR(plane_state))
10176 return PTR_ERR(plane_state);
10177
10178 if (mode)
10179 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10180 else
10181 hdisplay = vdisplay = 0;
10182
10183 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10184 if (ret)
10185 return ret;
10186 drm_atomic_set_fb_for_plane(plane_state, fb);
10187 plane_state->crtc_x = 0;
10188 plane_state->crtc_y = 0;
10189 plane_state->crtc_w = hdisplay;
10190 plane_state->crtc_h = vdisplay;
10191 plane_state->src_x = x << 16;
10192 plane_state->src_y = y << 16;
10193 plane_state->src_w = hdisplay << 16;
10194 plane_state->src_h = vdisplay << 16;
10195
10196 return 0;
10197}
10198
d2434ab7 10199bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10200 struct drm_display_mode *mode,
51fd371b
RC		 10201 struct intel_load_detect_pipe *old,
10202 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10203{
10204 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10205 struct intel_encoder *intel_encoder =
10206 intel_attached_encoder(connector);
79e53945 10207 struct drm_crtc *possible_crtc;
4ef69c7a 10208 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10209 struct drm_crtc *crtc = NULL;
10210 struct drm_device *dev = encoder->dev;
94352cf9 10211 struct drm_framebuffer *fb;
51fd371b 10212 struct drm_mode_config *config = &dev->mode_config;
83a57153 10213 struct drm_atomic_state *state = NULL;
944b0c76 10214 struct drm_connector_state *connector_state;
4be07317 10215 struct intel_crtc_state *crtc_state;
51fd371b 10216 int ret, i = -1;
79e53945 10217
d2dff872 10218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10219 connector->base.id, connector->name,
8e329a03 10220 encoder->base.id, encoder->name);
d2dff872 10221
51fd371b
RC		 10222retry:
10223 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10224 if (ret)
ad3c558f 10225 goto fail;
6e9f798d 10226
79e53945
JB		 10227 /*
10228 * Algorithm gets a little messy:
7a5e4805 10229 *
79e53945
JB		 10230 * - if the connector already has an assigned crtc, use it (but make
10231 * sure it's on first)
7a5e4805 10232 *
79e53945
JB		 10233 * - try to find the first unused crtc that can drive this connector,
10234 * and use that if we find one
79e53945
JB		 10235 */
10236
10237 /* See if we already have a CRTC for this connector */
10238 if (encoder->crtc) {
10239 crtc = encoder->crtc;
8261b191 10240
51fd371b 10241 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10242 if (ret)
ad3c558f 10243 goto fail;
4d02e2de 10244 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10245 if (ret)
ad3c558f 10246 goto fail;
7b24056b 10247
24218aac 10248 old->dpms_mode = connector->dpms;
8261b191
CW		 10249 old->load_detect_temp = false;
10250
10251 /* Make sure the crtc and connector are running */
24218aac
DV		 10252 if (connector->dpms != DRM_MODE_DPMS_ON)
10253 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10254
7173188d 10255 return true;
79e53945
JB		 10256 }
10257
10258 /* Find an unused one (if possible) */
70e1e0ec 10259 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10260 i++;
10261 if (!(encoder->possible_crtcs & (1 << i)))
10262 continue;
83d65738 10263 if (possible_crtc->state->enable)
a459249c 10264 continue;
a459249c
VS		 10265
10266 crtc = possible_crtc;
10267 break;
79e53945
JB		 10268 }
10269
10270 /*
10271 * If we didn't find an unused CRTC, don't use any.
10272 */
10273 if (!crtc) {
7173188d 10274 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10275 goto fail;
79e53945
JB		 10276 }
10277
51fd371b
RC		 10278 ret = drm_modeset_lock(&crtc->mutex, ctx);
10279 if (ret)
ad3c558f 10280 goto fail;
4d02e2de
DV		 10281 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10282 if (ret)
ad3c558f 10283 goto fail;
79e53945
JB		 10284
10285 intel_crtc = to_intel_crtc(crtc);
24218aac 10286 old->dpms_mode = connector->dpms;
8261b191 10287 old->load_detect_temp = true;
d2dff872 10288 old->release_fb = NULL;
79e53945 10289
83a57153
ACO		 10290 state = drm_atomic_state_alloc(dev);
10291 if (!state)
10292 return false;
10293
10294 state->acquire_ctx = ctx;
10295
944b0c76
ACO		 10296 connector_state = drm_atomic_get_connector_state(state, connector);
10297 if (IS_ERR(connector_state)) {
10298 ret = PTR_ERR(connector_state);
10299 goto fail;
10300 }
10301
10302 connector_state->crtc = crtc;
10303 connector_state->best_encoder = &intel_encoder->base;
10304
4be07317
ACO		 10305 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10306 if (IS_ERR(crtc_state)) {
10307 ret = PTR_ERR(crtc_state);
10308 goto fail;
10309 }
10310
49d6fa21 10311 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10312
6492711d
CW		 10313 if (!mode)
10314 mode = &load_detect_mode;
79e53945 10315
d2dff872
CW		 10316 /* We need a framebuffer large enough to accommodate all accesses
10317 * that the plane may generate whilst we perform load detection.
10318 * We can not rely on the fbcon either being present (we get called
10319 * during its initialisation to detect all boot displays, or it may
10320 * not even exist) or that it is large enough to satisfy the
10321 * requested mode.
10322 */
94352cf9
DV		 10323 fb = mode_fits_in_fbdev(dev, mode);
10324 if (fb == NULL) {
d2dff872 10325 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10326 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10327 old->release_fb = fb;
d2dff872
CW		 10328 } else
10329 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10330 if (IS_ERR(fb)) {
d2dff872 10331 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10332 goto fail;
79e53945 10333 }
79e53945 10334
d3a40d1b
ACO		 10335 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10336 if (ret)
10337 goto fail;
10338
8c7b5ccb
ACO		 10339 drm_mode_copy(&crtc_state->base.mode, mode);
10340
74c090b1 10341 if (drm_atomic_commit(state)) {
6492711d 10342 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10343 if (old->release_fb)
10344 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10345 goto fail;
79e53945 10346 }
9128b040 10347 crtc->primary->crtc = crtc;
7173188d 10348
79e53945 10349 /* let the connector get through one full cycle before testing */
9d0498a2 10350 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10351 return true;
412b61d8 10352
ad3c558f 10353fail:
e5d958ef
ACO		 10354 drm_atomic_state_free(state);
10355 state = NULL;
83a57153 10356
51fd371b
RC		 10357 if (ret == -EDEADLK) {
10358 drm_modeset_backoff(ctx);
10359 goto retry;
10360 }
10361
412b61d8 10362 return false;
79e53945
JB		 10363}
10364
d2434ab7 10365void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10366 struct intel_load_detect_pipe *old,
10367 struct drm_modeset_acquire_ctx *ctx)
79e53945 10368{
83a57153 10369 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10370 struct intel_encoder *intel_encoder =
10371 intel_attached_encoder(connector);
4ef69c7a 10372 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10373 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10375 struct drm_atomic_state *state;
944b0c76 10376 struct drm_connector_state *connector_state;
4be07317 10377 struct intel_crtc_state *crtc_state;
d3a40d1b 10378 int ret;
79e53945 10379
d2dff872 10380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10381 connector->base.id, connector->name,
8e329a03 10382 encoder->base.id, encoder->name);
d2dff872 10383
8261b191 10384 if (old->load_detect_temp) {
83a57153 10385 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10386 if (!state)
10387 goto fail;
83a57153
ACO		 10388
10389 state->acquire_ctx = ctx;
10390
944b0c76
ACO		 10391 connector_state = drm_atomic_get_connector_state(state, connector);
10392 if (IS_ERR(connector_state))
10393 goto fail;
10394
4be07317
ACO		 10395 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10396 if (IS_ERR(crtc_state))
10397 goto fail;
10398
944b0c76
ACO		 10399 connector_state->best_encoder = NULL;
10400 connector_state->crtc = NULL;
10401
49d6fa21 10402 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10403
d3a40d1b
ACO		 10404 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10405 0, 0);
10406 if (ret)
10407 goto fail;
10408
74c090b1 10409 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10410 if (ret)
10411 goto fail;
d2dff872 10412
36206361
DV		 10413 if (old->release_fb) {
10414 drm_framebuffer_unregister_private(old->release_fb);
10415 drm_framebuffer_unreference(old->release_fb);
10416 }
d2dff872 10417
0622a53c 10418 return;
79e53945
JB		 10419 }
10420
c751ce4f 10421 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10422 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10423 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10424
10425 return;
10426fail:
10427 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10428 drm_atomic_state_free(state);
79e53945
JB		 10429}
10430
da4a1efa 10431static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10432 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10433{
10434 struct drm_i915_private *dev_priv = dev->dev_private;
10435 u32 dpll = pipe_config->dpll_hw_state.dpll;
10436
10437 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10438 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10439 else if (HAS_PCH_SPLIT(dev))
10440 return 120000;
10441 else if (!IS_GEN2(dev))
10442 return 96000;
10443 else
10444 return 48000;
10445}
10446
79e53945 10447/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10448static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10449 struct intel_crtc_state *pipe_config)
79e53945 10450{
f1f644dc 10451 struct drm_device *dev = crtc->base.dev;
79e53945 10452 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10453 int pipe = pipe_config->cpu_transcoder;
293623f7 10454 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10455 u32 fp;
10456 intel_clock_t clock;
dccbea3b 10457 int port_clock;
da4a1efa 10458 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10459
10460 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10461 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10462 else
293623f7 10463 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10464
10465 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10466 if (IS_PINEVIEW(dev)) {
10467 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10468 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10469 } else {
10470 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10471 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10472 }
10473
a6c45cf0 10474 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10475 if (IS_PINEVIEW(dev))
10476 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10477 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10478 else
10479 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10480 DPLL_FPA01_P1_POST_DIV_SHIFT);
10481
10482 switch (dpll & DPLL_MODE_MASK) {
10483 case DPLLB_MODE_DAC_SERIAL:
10484 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10485 5 : 10;
10486 break;
10487 case DPLLB_MODE_LVDS:
10488 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10489 7 : 14;
10490 break;
10491 default:
28c97730 10492 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10493 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10494 return;
79e53945
JB		 10495 }
10496
ac58c3f0 10497 if (IS_PINEVIEW(dev))
dccbea3b 10498 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10499 else
dccbea3b 10500 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10501 } else {
0fb58223 10502 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10503 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10504
10505 if (is_lvds) {
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10508
10509 if (lvds & LVDS_CLKB_POWER_UP)
10510 clock.p2 = 7;
10511 else
10512 clock.p2 = 14;
79e53945
JB		 10513 } else {
10514 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10515 clock.p1 = 2;
10516 else {
10517 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10518 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10519 }
10520 if (dpll & PLL_P2_DIVIDE_BY_4)
10521 clock.p2 = 4;
10522 else
10523 clock.p2 = 2;
79e53945 10524 }
da4a1efa 10525
dccbea3b 10526 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10527 }
10528
18442d08
VS		 10529 /*
10530 * This value includes pixel_multiplier. We will use
241bfc38 10531 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10532 * encoder's get_config() function.
10533 */
dccbea3b 10534 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10535}
10536
6878da05
VS		 10537int intel_dotclock_calculate(int link_freq,
10538 const struct intel_link_m_n *m_n)
f1f644dc 10539{
f1f644dc
JB		 10540 /*
10541 * The calculation for the data clock is:
1041a02f 10542 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10543 * But we want to avoid losing precison if possible, so:
1041a02f 10544 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10545 *
10546 * and the link clock is simpler:
1041a02f 10547 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10548 */
10549
6878da05
VS		 10550 if (!m_n->link_n)
10551 return 0;
f1f644dc 10552
6878da05
VS		 10553 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10554}
f1f644dc 10555
18442d08 10556static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10557 struct intel_crtc_state *pipe_config)
6878da05
VS		 10558{
10559 struct drm_device *dev = crtc->base.dev;
79e53945 10560
18442d08
VS		 10561 /* read out port_clock from the DPLL */
10562 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10563
f1f644dc 10564 /*
18442d08 10565 * This value does not include pixel_multiplier.
241bfc38 10566 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10567 * agree once we know their relationship in the encoder's
10568 * get_config() function.
79e53945 10569 */
2d112de7 10570 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10571 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10572 &pipe_config->fdi_m_n);
79e53945
JB		 10573}
10574
10575/** Returns the currently programmed mode of the given pipe. */
10576struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10577 struct drm_crtc *crtc)
10578{
548f245b 10579 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10581 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10582 struct drm_display_mode *mode;
5cec258b 10583 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10584 int htot = I915_READ(HTOTAL(cpu_transcoder));
10585 int hsync = I915_READ(HSYNC(cpu_transcoder));
10586 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10587 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10588 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10589
10590 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10591 if (!mode)
10592 return NULL;
10593
f1f644dc
JB		 10594 /*
10595 * Construct a pipe_config sufficient for getting the clock info
10596 * back out of crtc_clock_get.
10597 *
10598 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10599 * to use a real value here instead.
10600 */
293623f7 10601 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10602 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10603 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10604 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10605 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10606 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10607
773ae034 10608 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10609 mode->hdisplay = (htot & 0xffff) + 1;
10610 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10611 mode->hsync_start = (hsync & 0xffff) + 1;
10612 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10613 mode->vdisplay = (vtot & 0xffff) + 1;
10614 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10615 mode->vsync_start = (vsync & 0xffff) + 1;
10616 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10617
10618 drm_mode_set_name(mode);
79e53945
JB		 10619
10620 return mode;
10621}
10622
f047e395
CW		 10623void intel_mark_busy(struct drm_device *dev)
10624{
c67a470b
PZ		 10625 struct drm_i915_private *dev_priv = dev->dev_private;
10626
f62a0076
CW		 10627 if (dev_priv->mm.busy)
10628 return;
10629
43694d69 10630 intel_runtime_pm_get(dev_priv);
c67a470b 10631 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10632 if (INTEL_INFO(dev)->gen >= 6)
10633 gen6_rps_busy(dev_priv);
f62a0076 10634 dev_priv->mm.busy = true;
f047e395
CW		 10635}
10636
10637void intel_mark_idle(struct drm_device *dev)
652c393a 10638{
c67a470b 10639 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10640
f62a0076
CW		 10641 if (!dev_priv->mm.busy)
10642 return;
10643
10644 dev_priv->mm.busy = false;
10645
3d13ef2e 10646 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10647 gen6_rps_idle(dev->dev_private);
bb4cdd53 10648
43694d69 10649 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10650}
10651
79e53945
JB		 10652static void intel_crtc_destroy(struct drm_crtc *crtc)
10653{
10654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10655 struct drm_device *dev = crtc->dev;
10656 struct intel_unpin_work *work;
67e77c5a 10657
5e2d7afc 10658 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10659 work = intel_crtc->unpin_work;
10660 intel_crtc->unpin_work = NULL;
5e2d7afc 10661 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10662
10663 if (work) {
10664 cancel_work_sync(&work->work);
10665 kfree(work);
10666 }
79e53945
JB		 10667
10668 drm_crtc_cleanup(crtc);
67e77c5a 10669
79e53945
JB		 10670 kfree(intel_crtc);
10671}
10672
6b95a207
KH		 10673static void intel_unpin_work_fn(struct work_struct *__work)
10674{
10675 struct intel_unpin_work *work =
10676 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10677 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10678 struct drm_device *dev = crtc->base.dev;
10679 struct drm_plane *primary = crtc->base.primary;
6b95a207 10680
b4a98e57 10681 mutex_lock(&dev->struct_mutex);
a9ff8714 10682 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10683 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10684
f06cc1b9 10685 if (work->flip_queued_req)
146d84f0 10686 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10687 mutex_unlock(&dev->struct_mutex);
10688
a9ff8714 10689 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10690 drm_framebuffer_unreference(work->old_fb);
f99d7069 10691
a9ff8714
VS		 10692 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10693 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10694
6b95a207
KH		 10695 kfree(work);
10696}
10697
1afe3e9d 10698static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10699 struct drm_crtc *crtc)
6b95a207 10700{
6b95a207
KH		 10701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702 struct intel_unpin_work *work;
6b95a207
KH		 10703 unsigned long flags;
10704
10705 /* Ignore early vblank irqs */
10706 if (intel_crtc == NULL)
10707 return;
10708
f326038a
DV		 10709 /*
10710 * This is called both by irq handlers and the reset code (to complete
10711 * lost pageflips) so needs the full irqsave spinlocks.
10712 */
6b95a207
KH		 10713 spin_lock_irqsave(&dev->event_lock, flags);
10714 work = intel_crtc->unpin_work;
e7d841ca
CW		 10715
10716 /* Ensure we don't miss a work->pending update ... */
10717 smp_rmb();
10718
10719 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10720 spin_unlock_irqrestore(&dev->event_lock, flags);
10721 return;
10722 }
10723
d6bbafa1 10724 page_flip_completed(intel_crtc);
0af7e4df 10725
6b95a207 10726 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10727}
10728
1afe3e9d
JB		 10729void intel_finish_page_flip(struct drm_device *dev, int pipe)
10730{
fbee40df 10731 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10732 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10733
49b14a5c 10734 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10735}
10736
10737void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10738{
fbee40df 10739 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10740 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10741
49b14a5c 10742 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10743}
10744
75f7f3ec
VS		 10745/* Is 'a' after or equal to 'b'? */
10746static bool g4x_flip_count_after_eq(u32 a, u32 b)
10747{
10748 return !((a - b) & 0x80000000);
10749}
10750
10751static bool page_flip_finished(struct intel_crtc *crtc)
10752{
10753 struct drm_device *dev = crtc->base.dev;
10754 struct drm_i915_private *dev_priv = dev->dev_private;
10755
bdfa7542
VS		 10756 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10757 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10758 return true;
10759
75f7f3ec
VS		 10760 /*
10761 * The relevant registers doen't exist on pre-ctg.
10762 * As the flip done interrupt doesn't trigger for mmio
10763 * flips on gmch platforms, a flip count check isn't
10764 * really needed there. But since ctg has the registers,
10765 * include it in the check anyway.
10766 */
10767 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10768 return true;
10769
10770 /*
10771 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10772 * used the same base address. In that case the mmio flip might
10773 * have completed, but the CS hasn't even executed the flip yet.
10774 *
10775 * A flip count check isn't enough as the CS might have updated
10776 * the base address just after start of vblank, but before we
10777 * managed to process the interrupt. This means we'd complete the
10778 * CS flip too soon.
10779 *
10780 * Combining both checks should get us a good enough result. It may
10781 * still happen that the CS flip has been executed, but has not
10782 * yet actually completed. But in case the base address is the same
10783 * anyway, we don't really care.
10784 */
10785 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10786 crtc->unpin_work->gtt_offset &&
10787 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10788 crtc->unpin_work->flip_count);
10789}
10790
6b95a207
KH		 10791void intel_prepare_page_flip(struct drm_device *dev, int plane)
10792{
fbee40df 10793 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10794 struct intel_crtc *intel_crtc =
10795 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10796 unsigned long flags;
10797
f326038a
DV		 10798
10799 /*
10800 * This is called both by irq handlers and the reset code (to complete
10801 * lost pageflips) so needs the full irqsave spinlocks.
10802 *
10803 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10804 * generate a page-flip completion irq, i.e. every modeset
10805 * is also accompanied by a spurious intel_prepare_page_flip().
10806 */
6b95a207 10807 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10808 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10809 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10810 spin_unlock_irqrestore(&dev->event_lock, flags);
10811}
10812
eba905b2 10813static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10814{
10815 /* Ensure that the work item is consistent when activating it ... */
10816 smp_wmb();
10817 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10818 /* and that it is marked active as soon as the irq could fire. */
10819 smp_wmb();
10820}
10821
8c9f3aaf
JB		 10822static int intel_gen2_queue_flip(struct drm_device *dev,
10823 struct drm_crtc *crtc,
10824 struct drm_framebuffer *fb,
ed8d1975 10825 struct drm_i915_gem_object *obj,
6258fbe2 10826 struct drm_i915_gem_request *req,
ed8d1975 10827 uint32_t flags)
8c9f3aaf 10828{
6258fbe2 10829 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10831 u32 flip_mask;
10832 int ret;
10833
5fb9de1a 10834 ret = intel_ring_begin(req, 6);
8c9f3aaf 10835 if (ret)
4fa62c89 10836 return ret;
8c9f3aaf
JB		 10837
10838 /* Can't queue multiple flips, so wait for the previous
10839 * one to finish before executing the next.
10840 */
10841 if (intel_crtc->plane)
10842 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10843 else
10844 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10845 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10846 intel_ring_emit(ring, MI_NOOP);
10847 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10848 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10849 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10850 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10851 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10852
10853 intel_mark_page_flip_active(intel_crtc);
83d4092b 10854 return 0;
8c9f3aaf
JB		 10855}
10856
10857static int intel_gen3_queue_flip(struct drm_device *dev,
10858 struct drm_crtc *crtc,
10859 struct drm_framebuffer *fb,
ed8d1975 10860 struct drm_i915_gem_object *obj,
6258fbe2 10861 struct drm_i915_gem_request *req,
ed8d1975 10862 uint32_t flags)
8c9f3aaf 10863{
6258fbe2 10864 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10866 u32 flip_mask;
10867 int ret;
10868
5fb9de1a 10869 ret = intel_ring_begin(req, 6);
8c9f3aaf 10870 if (ret)
4fa62c89 10871 return ret;
8c9f3aaf
JB		 10872
10873 if (intel_crtc->plane)
10874 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10875 else
10876 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10877 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10878 intel_ring_emit(ring, MI_NOOP);
10879 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10880 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10881 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10882 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10883 intel_ring_emit(ring, MI_NOOP);
10884
e7d841ca 10885 intel_mark_page_flip_active(intel_crtc);
83d4092b 10886 return 0;
8c9f3aaf
JB		 10887}
10888
10889static int intel_gen4_queue_flip(struct drm_device *dev,
10890 struct drm_crtc *crtc,
10891 struct drm_framebuffer *fb,
ed8d1975 10892 struct drm_i915_gem_object *obj,
6258fbe2 10893 struct drm_i915_gem_request *req,
ed8d1975 10894 uint32_t flags)
8c9f3aaf 10895{
6258fbe2 10896 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10897 struct drm_i915_private *dev_priv = dev->dev_private;
10898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899 uint32_t pf, pipesrc;
10900 int ret;
10901
5fb9de1a 10902 ret = intel_ring_begin(req, 4);
8c9f3aaf 10903 if (ret)
4fa62c89 10904 return ret;
8c9f3aaf
JB		 10905
10906 /* i965+ uses the linear or tiled offsets from the
10907 * Display Registers (which do not change across a page-flip)
10908 * so we need only reprogram the base address.
10909 */
6d90c952
DV		 10910 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10911 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10912 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10913 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10914 obj->tiling_mode);
8c9f3aaf
JB		 10915
10916 /* XXX Enabling the panel-fitter across page-flip is so far
10917 * untested on non-native modes, so ignore it for now.
10918 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10919 */
10920 pf = 0;
10921 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10922 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10923
10924 intel_mark_page_flip_active(intel_crtc);
83d4092b 10925 return 0;
8c9f3aaf
JB		 10926}
10927
10928static int intel_gen6_queue_flip(struct drm_device *dev,
10929 struct drm_crtc *crtc,
10930 struct drm_framebuffer *fb,
ed8d1975 10931 struct drm_i915_gem_object *obj,
6258fbe2 10932 struct drm_i915_gem_request *req,
ed8d1975 10933 uint32_t flags)
8c9f3aaf 10934{
6258fbe2 10935 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10936 struct drm_i915_private *dev_priv = dev->dev_private;
10937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10938 uint32_t pf, pipesrc;
10939 int ret;
10940
5fb9de1a 10941 ret = intel_ring_begin(req, 4);
8c9f3aaf 10942 if (ret)
4fa62c89 10943 return ret;
8c9f3aaf 10944
6d90c952
DV		 10945 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10946 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10947 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10948 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10949
dc257cf1
DV		 10950 /* Contrary to the suggestions in the documentation,
10951 * "Enable Panel Fitter" does not seem to be required when page
10952 * flipping with a non-native mode, and worse causes a normal
10953 * modeset to fail.
10954 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10955 */
10956 pf = 0;
8c9f3aaf 10957 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10958 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10959
10960 intel_mark_page_flip_active(intel_crtc);
83d4092b 10961 return 0;
8c9f3aaf
JB		 10962}
10963
7c9017e5
JB		 10964static int intel_gen7_queue_flip(struct drm_device *dev,
10965 struct drm_crtc *crtc,
10966 struct drm_framebuffer *fb,
ed8d1975 10967 struct drm_i915_gem_object *obj,
6258fbe2 10968 struct drm_i915_gem_request *req,
ed8d1975 10969 uint32_t flags)
7c9017e5 10970{
6258fbe2 10971 struct intel_engine_cs *ring = req->ring;
7c9017e5 10972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10973 uint32_t plane_bit = 0;
ffe74d75
CW		 10974 int len, ret;
10975
eba905b2 10976 switch (intel_crtc->plane) {
cb05d8de
DV		 10977 case PLANE_A:
10978 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10979 break;
10980 case PLANE_B:
10981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10982 break;
10983 case PLANE_C:
10984 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10985 break;
10986 default:
10987 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10988 return -ENODEV;
cb05d8de
DV		 10989 }
10990
ffe74d75 10991 len = 4;
f476828a 10992 if (ring->id == RCS) {
ffe74d75 10993 len += 6;
f476828a
DL		 10994 /*
10995 * On Gen 8, SRM is now taking an extra dword to accommodate
10996 * 48bits addresses, and we need a NOOP for the batch size to
10997 * stay even.
10998 */
10999 if (IS_GEN8(dev))
11000 len += 2;
11001 }
ffe74d75 11002
f66fab8e
VS		 11003 /*
11004 * BSpec MI_DISPLAY_FLIP for IVB:
11005 * "The full packet must be contained within the same cache line."
11006 *
11007 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11008 * cacheline, if we ever start emitting more commands before
11009 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11010 * then do the cacheline alignment, and finally emit the
11011 * MI_DISPLAY_FLIP.
11012 */
bba09b12 11013 ret = intel_ring_cacheline_align(req);
f66fab8e 11014 if (ret)
4fa62c89 11015 return ret;
f66fab8e 11016
5fb9de1a 11017 ret = intel_ring_begin(req, len);
7c9017e5 11018 if (ret)
4fa62c89 11019 return ret;
7c9017e5 11020
ffe74d75
CW		 11021 /* Unmask the flip-done completion message. Note that the bspec says that
11022 * we should do this for both the BCS and RCS, and that we must not unmask
11023 * more than one flip event at any time (or ensure that one flip message
11024 * can be sent by waiting for flip-done prior to queueing new flips).
11025 * Experimentation says that BCS works despite DERRMR masking all
11026 * flip-done completion events and that unmasking all planes at once
11027 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11028 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11029 */
11030 if (ring->id == RCS) {
11031 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11032 intel_ring_emit(ring, DERRMR);
11033 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11034 DERRMR_PIPEB_PRI_FLIP_DONE |
11035 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11036 if (IS_GEN8(dev))
11037 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11038 MI_SRM_LRM_GLOBAL_GTT);
11039 else
11040 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11041 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11042 intel_ring_emit(ring, DERRMR);
11043 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11044 if (IS_GEN8(dev)) {
11045 intel_ring_emit(ring, 0);
11046 intel_ring_emit(ring, MI_NOOP);
11047 }
ffe74d75
CW		 11048 }
11049
cb05d8de 11050 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11051 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11052 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11053 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11054
11055 intel_mark_page_flip_active(intel_crtc);
83d4092b 11056 return 0;
7c9017e5
JB		 11057}
11058
84c33a64
SG		 11059static bool use_mmio_flip(struct intel_engine_cs *ring,
11060 struct drm_i915_gem_object *obj)
11061{
11062 /*
11063 * This is not being used for older platforms, because
11064 * non-availability of flip done interrupt forces us to use
11065 * CS flips. Older platforms derive flip done using some clever
11066 * tricks involving the flip_pending status bits and vblank irqs.
11067 * So using MMIO flips there would disrupt this mechanism.
11068 */
11069
8e09bf83
CW		 11070 if (ring == NULL)
11071 return true;
11072
84c33a64
SG		 11073 if (INTEL_INFO(ring->dev)->gen < 5)
11074 return false;
11075
11076 if (i915.use_mmio_flip < 0)
11077 return false;
11078 else if (i915.use_mmio_flip > 0)
11079 return true;
14bf993e
OM		 11080 else if (i915.enable_execlists)
11081 return true;
84c33a64 11082 else
b4716185 11083 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11084}
11085
ff944564
DL		 11086static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11087{
11088 struct drm_device *dev = intel_crtc->base.dev;
11089 struct drm_i915_private *dev_priv = dev->dev_private;
11090 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11091 const enum pipe pipe = intel_crtc->pipe;
11092 u32 ctl, stride;
11093
11094 ctl = I915_READ(PLANE_CTL(pipe, 0));
11095 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11096 switch (fb->modifier[0]) {
11097 case DRM_FORMAT_MOD_NONE:
11098 break;
11099 case I915_FORMAT_MOD_X_TILED:
ff944564 11100 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11101 break;
11102 case I915_FORMAT_MOD_Y_TILED:
11103 ctl |= PLANE_CTL_TILED_Y;
11104 break;
11105 case I915_FORMAT_MOD_Yf_TILED:
11106 ctl |= PLANE_CTL_TILED_YF;
11107 break;
11108 default:
11109 MISSING_CASE(fb->modifier[0]);
11110 }
ff944564
DL		 11111
11112 /*
11113 * The stride is either expressed as a multiple of 64 bytes chunks for
11114 * linear buffers or in number of tiles for tiled buffers.
11115 */
2ebef630
TU		 11116 stride = fb->pitches[0] /
11117 intel_fb_stride_alignment(dev, fb->modifier[0],
11118 fb->pixel_format);
ff944564
DL		 11119
11120 /*
11121 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11122 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11123 */
11124 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11125 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11126
11127 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11128 POSTING_READ(PLANE_SURF(pipe, 0));
11129}
11130
11131static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11132{
11133 struct drm_device *dev = intel_crtc->base.dev;
11134 struct drm_i915_private *dev_priv = dev->dev_private;
11135 struct intel_framebuffer *intel_fb =
11136 to_intel_framebuffer(intel_crtc->base.primary->fb);
11137 struct drm_i915_gem_object *obj = intel_fb->obj;
11138 u32 dspcntr;
11139 u32 reg;
11140
84c33a64
SG		 11141 reg = DSPCNTR(intel_crtc->plane);
11142 dspcntr = I915_READ(reg);
11143
c5d97472
DL		 11144 if (obj->tiling_mode != I915_TILING_NONE)
11145 dspcntr |= DISPPLANE_TILED;
11146 else
11147 dspcntr &= ~DISPPLANE_TILED;
11148
84c33a64
SG		 11149 I915_WRITE(reg, dspcntr);
11150
11151 I915_WRITE(DSPSURF(intel_crtc->plane),
11152 intel_crtc->unpin_work->gtt_offset);
11153 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11154
ff944564
DL		 11155}
11156
11157/*
11158 * XXX: This is the temporary way to update the plane registers until we get
11159 * around to using the usual plane update functions for MMIO flips
11160 */
11161static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11162{
11163 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11164 u32 start_vbl_count;
11165
11166 intel_mark_page_flip_active(intel_crtc);
11167
8f539a83 11168 intel_pipe_update_start(intel_crtc, &start_vbl_count);
ff944564
DL		 11169
11170 if (INTEL_INFO(dev)->gen >= 9)
11171 skl_do_mmio_flip(intel_crtc);
11172 else
11173 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11174 ilk_do_mmio_flip(intel_crtc);
11175
8f539a83 11176 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11177}
11178
9362c7c5 11179static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11180{
b2cfe0ab
CW		 11181 struct intel_mmio_flip *mmio_flip =
11182 container_of(work, struct intel_mmio_flip, work);
84c33a64 11183
eed29a5b
DV		 11184 if (mmio_flip->req)
11185 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11186 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11187 false, NULL,
11188 &mmio_flip->i915->rps.mmioflips));
84c33a64 11189
b2cfe0ab
CW		 11190 intel_do_mmio_flip(mmio_flip->crtc);
11191
eed29a5b 11192 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11193 kfree(mmio_flip);
84c33a64
SG		 11194}
11195
11196static int intel_queue_mmio_flip(struct drm_device *dev,
11197 struct drm_crtc *crtc,
11198 struct drm_framebuffer *fb,
11199 struct drm_i915_gem_object *obj,
11200 struct intel_engine_cs *ring,
11201 uint32_t flags)
11202{
b2cfe0ab
CW		 11203 struct intel_mmio_flip *mmio_flip;
11204
11205 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11206 if (mmio_flip == NULL)
11207 return -ENOMEM;
84c33a64 11208
bcafc4e3 11209 mmio_flip->i915 = to_i915(dev);
eed29a5b 11210 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11211 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11212
b2cfe0ab
CW		 11213 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11214 schedule_work(&mmio_flip->work);
84c33a64 11215
84c33a64
SG		 11216 return 0;
11217}
11218
8c9f3aaf
JB		 11219static int intel_default_queue_flip(struct drm_device *dev,
11220 struct drm_crtc *crtc,
11221 struct drm_framebuffer *fb,
ed8d1975 11222 struct drm_i915_gem_object *obj,
6258fbe2 11223 struct drm_i915_gem_request *req,
ed8d1975 11224 uint32_t flags)
8c9f3aaf
JB		 11225{
11226 return -ENODEV;
11227}
11228
d6bbafa1
CW		 11229static bool __intel_pageflip_stall_check(struct drm_device *dev,
11230 struct drm_crtc *crtc)
11231{
11232 struct drm_i915_private *dev_priv = dev->dev_private;
11233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11234 struct intel_unpin_work *work = intel_crtc->unpin_work;
11235 u32 addr;
11236
11237 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11238 return true;
11239
11240 if (!work->enable_stall_check)
11241 return false;
11242
11243 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11244 if (work->flip_queued_req &&
11245 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11246 return false;
11247
1e3feefd 11248 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11249 }
11250
1e3feefd 11251 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11252 return false;
11253
11254 /* Potential stall - if we see that the flip has happened,
11255 * assume a missed interrupt. */
11256 if (INTEL_INFO(dev)->gen >= 4)
11257 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11258 else
11259 addr = I915_READ(DSPADDR(intel_crtc->plane));
11260
11261 /* There is a potential issue here with a false positive after a flip
11262 * to the same address. We could address this by checking for a
11263 * non-incrementing frame counter.
11264 */
11265 return addr == work->gtt_offset;
11266}
11267
11268void intel_check_page_flip(struct drm_device *dev, int pipe)
11269{
11270 struct drm_i915_private *dev_priv = dev->dev_private;
11271 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11273 struct intel_unpin_work *work;
f326038a 11274
6c51d46f 11275 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11276
11277 if (crtc == NULL)
11278 return;
11279
f326038a 11280 spin_lock(&dev->event_lock);
6ad790c0
CW		 11281 work = intel_crtc->unpin_work;
11282 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11283 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11284 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11285 page_flip_completed(intel_crtc);
6ad790c0 11286 work = NULL;
d6bbafa1 11287 }
6ad790c0
CW		 11288 if (work != NULL &&
11289 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11290 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11291 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11292}
11293
6b95a207
KH		 11294static int intel_crtc_page_flip(struct drm_crtc *crtc,
11295 struct drm_framebuffer *fb,
ed8d1975
KP		 11296 struct drm_pending_vblank_event *event,
11297 uint32_t page_flip_flags)
6b95a207
KH		 11298{
11299 struct drm_device *dev = crtc->dev;
11300 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11301 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11302 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11304 struct drm_plane *primary = crtc->primary;
a071fa00 11305 enum pipe pipe = intel_crtc->pipe;
6b95a207 11306 struct intel_unpin_work *work;
a4872ba6 11307 struct intel_engine_cs *ring;
cf5d8a46 11308 bool mmio_flip;
91af127f 11309 struct drm_i915_gem_request *request = NULL;
52e68630 11310 int ret;
6b95a207 11311
2ff8fde1
MR		 11312 /*
11313 * drm_mode_page_flip_ioctl() should already catch this, but double
11314 * check to be safe. In the future we may enable pageflipping from
11315 * a disabled primary plane.
11316 */
11317 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11318 return -EBUSY;
11319
e6a595d2 11320 /* Can't change pixel format via MI display flips. */
f4510a27 11321 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11322 return -EINVAL;
11323
11324 /*
11325 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11326 * Note that pitch changes could also affect these register.
11327 */
11328 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11329 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11330 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11331 return -EINVAL;
11332
f900db47
CW		 11333 if (i915_terminally_wedged(&dev_priv->gpu_error))
11334 goto out_hang;
11335
b14c5679 11336 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11337 if (work == NULL)
11338 return -ENOMEM;
11339
6b95a207 11340 work->event = event;
b4a98e57 11341 work->crtc = crtc;
ab8d6675 11342 work->old_fb = old_fb;
6b95a207
KH		 11343 INIT_WORK(&work->work, intel_unpin_work_fn);
11344
87b6b101 11345 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11346 if (ret)
11347 goto free_work;
11348
6b95a207 11349 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11350 spin_lock_irq(&dev->event_lock);
6b95a207 11351 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11352 /* Before declaring the flip queue wedged, check if
11353 * the hardware completed the operation behind our backs.
11354 */
11355 if (__intel_pageflip_stall_check(dev, crtc)) {
11356 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11357 page_flip_completed(intel_crtc);
11358 } else {
11359 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11360 spin_unlock_irq(&dev->event_lock);
468f0b44 11361
d6bbafa1
CW		 11362 drm_crtc_vblank_put(crtc);
11363 kfree(work);
11364 return -EBUSY;
11365 }
6b95a207
KH		 11366 }
11367 intel_crtc->unpin_work = work;
5e2d7afc 11368 spin_unlock_irq(&dev->event_lock);
6b95a207 11369
b4a98e57
CW		 11370 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11371 flush_workqueue(dev_priv->wq);
11372
75dfca80 11373 /* Reference the objects for the scheduled work. */
ab8d6675 11374 drm_framebuffer_reference(work->old_fb);
05394f39 11375 drm_gem_object_reference(&obj->base);
6b95a207 11376
f4510a27 11377 crtc->primary->fb = fb;
afd65eb4 11378 update_state_fb(crtc->primary);
1ed1f968 11379
e1f99ce6 11380 work->pending_flip_obj = obj;
e1f99ce6 11381
89ed88ba
CW		 11382 ret = i915_mutex_lock_interruptible(dev);
11383 if (ret)
11384 goto cleanup;
11385
b4a98e57 11386 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11387 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11388
75f7f3ec 11389 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11390 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11391
4fa62c89
VS		 11392 if (IS_VALLEYVIEW(dev)) {
11393 ring = &dev_priv->ring[BCS];
ab8d6675 11394 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11395 /* vlv: DISPLAY_FLIP fails to change tiling */
11396 ring = NULL;
48bf5b2d 11397 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11398 ring = &dev_priv->ring[BCS];
4fa62c89 11399 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11400 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11401 if (ring == NULL || ring->id != RCS)
11402 ring = &dev_priv->ring[BCS];
11403 } else {
11404 ring = &dev_priv->ring[RCS];
11405 }
11406
cf5d8a46
CW		 11407 mmio_flip = use_mmio_flip(ring, obj);
11408
11409 /* When using CS flips, we want to emit semaphores between rings.
11410 * However, when using mmio flips we will create a task to do the
11411 * synchronisation, so all we want here is to pin the framebuffer
11412 * into the display plane and skip any waits.
11413 */
82bc3b2d 11414 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11415 crtc->primary->state,
91af127f 11416 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11417 if (ret)
11418 goto cleanup_pending;
6b95a207 11419
121920fa
TU		 11420 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11421 + intel_crtc->dspaddr_offset;
4fa62c89 11422
cf5d8a46 11423 if (mmio_flip) {
84c33a64
SG		 11424 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11425 page_flip_flags);
d6bbafa1
CW		 11426 if (ret)
11427 goto cleanup_unpin;
11428
f06cc1b9
JH		 11429 i915_gem_request_assign(&work->flip_queued_req,
11430 obj->last_write_req);
d6bbafa1 11431 } else {
6258fbe2
JH		 11432 if (!request) {
11433 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11434 if (ret)
11435 goto cleanup_unpin;
11436 }
11437
11438 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11439 page_flip_flags);
11440 if (ret)
11441 goto cleanup_unpin;
11442
6258fbe2 11443 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11444 }
11445
91af127f 11446 if (request)
75289874 11447 i915_add_request_no_flush(request);
91af127f 11448
1e3feefd 11449 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11450 work->enable_stall_check = true;
4fa62c89 11451
ab8d6675 11452 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11453 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11454 mutex_unlock(&dev->struct_mutex);
a071fa00 11455
4e1e26f1 11456 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11457 intel_frontbuffer_flip_prepare(dev,
11458 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11459
e5510fac
JB		 11460 trace_i915_flip_request(intel_crtc->plane, obj);
11461
6b95a207 11462 return 0;
96b099fd 11463
4fa62c89 11464cleanup_unpin:
82bc3b2d 11465 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11466cleanup_pending:
91af127f
JH		 11467 if (request)
11468 i915_gem_request_cancel(request);
b4a98e57 11469 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11470 mutex_unlock(&dev->struct_mutex);
11471cleanup:
f4510a27 11472 crtc->primary->fb = old_fb;
afd65eb4 11473 update_state_fb(crtc->primary);
89ed88ba
CW		 11474
11475 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11476 drm_framebuffer_unreference(work->old_fb);
96b099fd 11477
5e2d7afc 11478 spin_lock_irq(&dev->event_lock);
96b099fd 11479 intel_crtc->unpin_work = NULL;
5e2d7afc 11480 spin_unlock_irq(&dev->event_lock);
96b099fd 11481
87b6b101 11482 drm_crtc_vblank_put(crtc);
7317c75e 11483free_work:
96b099fd
CW		 11484 kfree(work);
11485
f900db47 11486 if (ret == -EIO) {
02e0efb5
ML		 11487 struct drm_atomic_state *state;
11488 struct drm_plane_state *plane_state;
11489
f900db47 11490out_hang:
02e0efb5
ML		 11491 state = drm_atomic_state_alloc(dev);
11492 if (!state)
11493 return -ENOMEM;
11494 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11495
11496retry:
11497 plane_state = drm_atomic_get_plane_state(state, primary);
11498 ret = PTR_ERR_OR_ZERO(plane_state);
11499 if (!ret) {
11500 drm_atomic_set_fb_for_plane(plane_state, fb);
11501
11502 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11503 if (!ret)
11504 ret = drm_atomic_commit(state);
11505 }
11506
11507 if (ret == -EDEADLK) {
11508 drm_modeset_backoff(state->acquire_ctx);
11509 drm_atomic_state_clear(state);
11510 goto retry;
11511 }
11512
11513 if (ret)
11514 drm_atomic_state_free(state);
11515
f0d3dad3 11516 if (ret == 0 && event) {
5e2d7afc 11517 spin_lock_irq(&dev->event_lock);
a071fa00 11518 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11519 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11520 }
f900db47 11521 }
96b099fd 11522 return ret;
6b95a207
KH		 11523}
11524
da20eabd
ML		 11525
11526/**
11527 * intel_wm_need_update - Check whether watermarks need updating
11528 * @plane: drm plane
11529 * @state: new plane state
11530 *
11531 * Check current plane state versus the new one to determine whether
11532 * watermarks need to be recalculated.
11533 *
11534 * Returns true or false.
11535 */
11536static bool intel_wm_need_update(struct drm_plane *plane,
11537 struct drm_plane_state *state)
11538{
11539 /* Update watermarks on tiling changes. */
11540 if (!plane->state->fb || !state->fb ||
11541 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11542 plane->state->rotation != state->rotation)
11543 return true;
11544
11545 if (plane->state->crtc_w != state->crtc_w)
11546 return true;
11547
11548 return false;
11549}
11550
11551int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11552 struct drm_plane_state *plane_state)
11553{
11554 struct drm_crtc *crtc = crtc_state->crtc;
11555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11556 struct drm_plane *plane = plane_state->plane;
11557 struct drm_device *dev = crtc->dev;
11558 struct drm_i915_private *dev_priv = dev->dev_private;
11559 struct intel_plane_state *old_plane_state =
11560 to_intel_plane_state(plane->state);
11561 int idx = intel_crtc->base.base.id, ret;
11562 int i = drm_plane_index(plane);
11563 bool mode_changed = needs_modeset(crtc_state);
11564 bool was_crtc_enabled = crtc->state->active;
11565 bool is_crtc_enabled = crtc_state->active;
11566
11567 bool turn_off, turn_on, visible, was_visible;
11568 struct drm_framebuffer *fb = plane_state->fb;
11569
11570 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11571 plane->type != DRM_PLANE_TYPE_CURSOR) {
11572 ret = skl_update_scaler_plane(
11573 to_intel_crtc_state(crtc_state),
11574 to_intel_plane_state(plane_state));
11575 if (ret)
11576 return ret;
11577 }
11578
11579 /*
11580 * Disabling a plane is always okay; we just need to update
11581 * fb tracking in a special way since cleanup_fb() won't
11582 * get called by the plane helpers.
11583 */
11584 if (old_plane_state->base.fb && !fb)
11585 intel_crtc->atomic.disabled_planes |= 1 << i;
11586
da20eabd
ML		 11587 was_visible = old_plane_state->visible;
11588 visible = to_intel_plane_state(plane_state)->visible;
11589
11590 if (!was_crtc_enabled && WARN_ON(was_visible))
11591 was_visible = false;
11592
11593 if (!is_crtc_enabled && WARN_ON(visible))
11594 visible = false;
11595
11596 if (!was_visible && !visible)
11597 return 0;
11598
11599 turn_off = was_visible && (!visible || mode_changed);
11600 turn_on = visible && (!was_visible || mode_changed);
11601
11602 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11603 plane->base.id, fb ? fb->base.id : -1);
11604
11605 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11606 plane->base.id, was_visible, visible,
11607 turn_off, turn_on, mode_changed);
11608
852eb00d 11609 if (turn_on) {
f015c551 11610 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11611 /* must disable cxsr around plane enable/disable */
11612 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11613 intel_crtc->atomic.disable_cxsr = true;
11614 /* to potentially re-enable cxsr */
11615 intel_crtc->atomic.wait_vblank = true;
11616 intel_crtc->atomic.update_wm_post = true;
11617 }
11618 } else if (turn_off) {
f015c551 11619 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11620 /* must disable cxsr around plane enable/disable */
11621 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11622 if (is_crtc_enabled)
11623 intel_crtc->atomic.wait_vblank = true;
11624 intel_crtc->atomic.disable_cxsr = true;
11625 }
11626 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11627 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11628 }
da20eabd 11629
a9ff8714
VS		 11630 if (visible)
11631 intel_crtc->atomic.fb_bits |=
11632 to_intel_plane(plane)->frontbuffer_bit;
11633
da20eabd
ML		 11634 switch (plane->type) {
11635 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11636 intel_crtc->atomic.wait_for_flips = true;
11637 intel_crtc->atomic.pre_disable_primary = turn_off;
11638 intel_crtc->atomic.post_enable_primary = turn_on;
11639
066cf55b
RV		 11640 if (turn_off) {
11641 /*
11642 * FIXME: Actually if we will still have any other
11643 * plane enabled on the pipe we could let IPS enabled
11644 * still, but for now lets consider that when we make
11645 * primary invisible by setting DSPCNTR to 0 on
11646 * update_primary_plane function IPS needs to be
11647 * disable.
11648 */
11649 intel_crtc->atomic.disable_ips = true;
11650
da20eabd 11651 intel_crtc->atomic.disable_fbc = true;
066cf55b 11652 }
da20eabd
ML		 11653
11654 /*
11655 * FBC does not work on some platforms for rotated
11656 * planes, so disable it when rotation is not 0 and
11657 * update it when rotation is set back to 0.
11658 *
11659 * FIXME: This is redundant with the fbc update done in
11660 * the primary plane enable function except that that
11661 * one is done too late. We eventually need to unify
11662 * this.
11663 */
11664
11665 if (visible &&
11666 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11667 dev_priv->fbc.crtc == intel_crtc &&
11668 plane_state->rotation != BIT(DRM_ROTATE_0))
11669 intel_crtc->atomic.disable_fbc = true;
11670
11671 /*
11672 * BDW signals flip done immediately if the plane
11673 * is disabled, even if the plane enable is already
11674 * armed to occur at the next vblank :(
11675 */
11676 if (turn_on && IS_BROADWELL(dev))
11677 intel_crtc->atomic.wait_vblank = true;
11678
11679 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11680 break;
11681 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11682 break;
11683 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11684 if (turn_off && !mode_changed) {
da20eabd
ML		 11685 intel_crtc->atomic.wait_vblank = true;
11686 intel_crtc->atomic.update_sprite_watermarks |=
11687 1 << i;
11688 }
da20eabd
ML		 11689 }
11690 return 0;
11691}
11692
6d3a1ce7
ML		 11693static bool encoders_cloneable(const struct intel_encoder *a,
11694 const struct intel_encoder *b)
11695{
11696 /* masks could be asymmetric, so check both ways */
11697 return a == b || (a->cloneable & (1 << b->type) &&
11698 b->cloneable & (1 << a->type));
11699}
11700
11701static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11702 struct intel_crtc *crtc,
11703 struct intel_encoder *encoder)
11704{
11705 struct intel_encoder *source_encoder;
11706 struct drm_connector *connector;
11707 struct drm_connector_state *connector_state;
11708 int i;
11709
11710 for_each_connector_in_state(state, connector, connector_state, i) {
11711 if (connector_state->crtc != &crtc->base)
11712 continue;
11713
11714 source_encoder =
11715 to_intel_encoder(connector_state->best_encoder);
11716 if (!encoders_cloneable(encoder, source_encoder))
11717 return false;
11718 }
11719
11720 return true;
11721}
11722
11723static bool check_encoder_cloning(struct drm_atomic_state *state,
11724 struct intel_crtc *crtc)
11725{
11726 struct intel_encoder *encoder;
11727 struct drm_connector *connector;
11728 struct drm_connector_state *connector_state;
11729 int i;
11730
11731 for_each_connector_in_state(state, connector, connector_state, i) {
11732 if (connector_state->crtc != &crtc->base)
11733 continue;
11734
11735 encoder = to_intel_encoder(connector_state->best_encoder);
11736 if (!check_single_encoder_cloning(state, crtc, encoder))
11737 return false;
11738 }
11739
11740 return true;
11741}
11742
11743static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11744 struct drm_crtc_state *crtc_state)
11745{
cf5a15be 11746 struct drm_device *dev = crtc->dev;
ad421372 11747 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11749 struct intel_crtc_state *pipe_config =
11750 to_intel_crtc_state(crtc_state);
6d3a1ce7 11751 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11752 int ret;
6d3a1ce7
ML		 11753 bool mode_changed = needs_modeset(crtc_state);
11754
11755 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11756 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11757 return -EINVAL;
11758 }
11759
852eb00d
VS		 11760 if (mode_changed && !crtc_state->active)
11761 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11762
ad421372
ML		 11763 if (mode_changed && crtc_state->enable &&
11764 dev_priv->display.crtc_compute_clock &&
11765 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11766 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11767 pipe_config);
11768 if (ret)
11769 return ret;
11770 }
11771
e435d6e5
ML		 11772 ret = 0;
11773 if (INTEL_INFO(dev)->gen >= 9) {
11774 if (mode_changed)
11775 ret = skl_update_scaler_crtc(pipe_config);
11776
11777 if (!ret)
11778 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11779 pipe_config);
11780 }
11781
11782 return ret;
6d3a1ce7
ML		 11783}
11784
65b38e0d 11785static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11786 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11787 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11788 .atomic_begin = intel_begin_crtc_commit,
11789 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11790 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11791};
11792
d29b2f9d
ACO		 11793static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11794{
11795 struct intel_connector *connector;
11796
11797 for_each_intel_connector(dev, connector) {
11798 if (connector->base.encoder) {
11799 connector->base.state->best_encoder =
11800 connector->base.encoder;
11801 connector->base.state->crtc =
11802 connector->base.encoder->crtc;
11803 } else {
11804 connector->base.state->best_encoder = NULL;
11805 connector->base.state->crtc = NULL;
11806 }
11807 }
11808}
11809
050f7aeb 11810static void
eba905b2 11811connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11812 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11813{
11814 int bpp = pipe_config->pipe_bpp;
11815
11816 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11817 connector->base.base.id,
c23cc417 11818 connector->base.name);
050f7aeb
DV		 11819
11820 /* Don't use an invalid EDID bpc value */
11821 if (connector->base.display_info.bpc &&
11822 connector->base.display_info.bpc * 3 < bpp) {
11823 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11824 bpp, connector->base.display_info.bpc*3);
11825 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11826 }
11827
11828 /* Clamp bpp to 8 on screens without EDID 1.4 */
11829 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11830 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11831 bpp);
11832 pipe_config->pipe_bpp = 24;
11833 }
11834}
11835
4e53c2e0 11836static int
050f7aeb 11837compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11838 struct intel_crtc_state *pipe_config)
4e53c2e0 11839{
050f7aeb 11840 struct drm_device *dev = crtc->base.dev;
1486017f 11841 struct drm_atomic_state *state;
da3ced29
ACO		 11842 struct drm_connector *connector;
11843 struct drm_connector_state *connector_state;
1486017f 11844 int bpp, i;
4e53c2e0 11845
d328c9d7 11846 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11847 bpp = 10*3;
d328c9d7
DV		 11848 else if (INTEL_INFO(dev)->gen >= 5)
11849 bpp = 12*3;
11850 else
11851 bpp = 8*3;
11852
4e53c2e0 11853
4e53c2e0
DV		 11854 pipe_config->pipe_bpp = bpp;
11855
1486017f
ACO		 11856 state = pipe_config->base.state;
11857
4e53c2e0 11858 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11859 for_each_connector_in_state(state, connector, connector_state, i) {
11860 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11861 continue;
11862
da3ced29
ACO		 11863 connected_sink_compute_bpp(to_intel_connector(connector),
11864 pipe_config);
4e53c2e0
DV		 11865 }
11866
11867 return bpp;
11868}
11869
644db711
DV		 11870static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11871{
11872 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11873 "type: 0x%x flags: 0x%x\n",
1342830c 11874 mode->crtc_clock,
644db711
DV		 11875 mode->crtc_hdisplay, mode->crtc_hsync_start,
11876 mode->crtc_hsync_end, mode->crtc_htotal,
11877 mode->crtc_vdisplay, mode->crtc_vsync_start,
11878 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11879}
11880
c0b03411 11881static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11882 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11883 const char *context)
11884{
6a60cd87
CK		 11885 struct drm_device *dev = crtc->base.dev;
11886 struct drm_plane *plane;
11887 struct intel_plane *intel_plane;
11888 struct intel_plane_state *state;
11889 struct drm_framebuffer *fb;
11890
11891 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11892 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11893
11894 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11895 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11896 pipe_config->pipe_bpp, pipe_config->dither);
11897 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11898 pipe_config->has_pch_encoder,
11899 pipe_config->fdi_lanes,
11900 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11901 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11902 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11903 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11904 pipe_config->has_dp_encoder,
11905 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11906 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11907 pipe_config->dp_m_n.tu);
b95af8be
VK		 11908
11909 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11910 pipe_config->has_dp_encoder,
11911 pipe_config->dp_m2_n2.gmch_m,
11912 pipe_config->dp_m2_n2.gmch_n,
11913 pipe_config->dp_m2_n2.link_m,
11914 pipe_config->dp_m2_n2.link_n,
11915 pipe_config->dp_m2_n2.tu);
11916
55072d19
DV		 11917 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11918 pipe_config->has_audio,
11919 pipe_config->has_infoframe);
11920
c0b03411 11921 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11922 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11923 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11924 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11925 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11926 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11927 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11928 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11929 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11930 crtc->num_scalers,
11931 pipe_config->scaler_state.scaler_users,
11932 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11933 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11934 pipe_config->gmch_pfit.control,
11935 pipe_config->gmch_pfit.pgm_ratios,
11936 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11937 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11938 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11939 pipe_config->pch_pfit.size,
11940 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11941 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11942 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11943
415ff0f6 11944 if (IS_BROXTON(dev)) {
05712c15 11945 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11946 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11947 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11948 pipe_config->ddi_pll_sel,
11949 pipe_config->dpll_hw_state.ebb0,
05712c15 11950 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11951 pipe_config->dpll_hw_state.pll0,
11952 pipe_config->dpll_hw_state.pll1,
11953 pipe_config->dpll_hw_state.pll2,
11954 pipe_config->dpll_hw_state.pll3,
11955 pipe_config->dpll_hw_state.pll6,
11956 pipe_config->dpll_hw_state.pll8,
05712c15 11957 pipe_config->dpll_hw_state.pll9,
c8453338 11958 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11959 pipe_config->dpll_hw_state.pcsdw12);
11960 } else if (IS_SKYLAKE(dev)) {
11961 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11962 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11963 pipe_config->ddi_pll_sel,
11964 pipe_config->dpll_hw_state.ctrl1,
11965 pipe_config->dpll_hw_state.cfgcr1,
11966 pipe_config->dpll_hw_state.cfgcr2);
11967 } else if (HAS_DDI(dev)) {
11968 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11969 pipe_config->ddi_pll_sel,
11970 pipe_config->dpll_hw_state.wrpll);
11971 } else {
11972 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11973 "fp0: 0x%x, fp1: 0x%x\n",
11974 pipe_config->dpll_hw_state.dpll,
11975 pipe_config->dpll_hw_state.dpll_md,
11976 pipe_config->dpll_hw_state.fp0,
11977 pipe_config->dpll_hw_state.fp1);
11978 }
11979
6a60cd87
CK		 11980 DRM_DEBUG_KMS("planes on this crtc\n");
11981 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11982 intel_plane = to_intel_plane(plane);
11983 if (intel_plane->pipe != crtc->pipe)
11984 continue;
11985
11986 state = to_intel_plane_state(plane->state);
11987 fb = state->base.fb;
11988 if (!fb) {
11989 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11990 "disabled, scaler_id = %d\n",
11991 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11992 plane->base.id, intel_plane->pipe,
11993 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11994 drm_plane_index(plane), state->scaler_id);
11995 continue;
11996 }
11997
11998 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11999 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12000 plane->base.id, intel_plane->pipe,
12001 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12002 drm_plane_index(plane));
12003 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12004 fb->base.id, fb->width, fb->height, fb->pixel_format);
12005 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12006 state->scaler_id,
12007 state->src.x1 >> 16, state->src.y1 >> 16,
12008 drm_rect_width(&state->src) >> 16,
12009 drm_rect_height(&state->src) >> 16,
12010 state->dst.x1, state->dst.y1,
12011 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12012 }
c0b03411
DV		 12013}
12014
5448a00d 12015static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12016{
5448a00d
ACO		 12017 struct drm_device *dev = state->dev;
12018 struct intel_encoder *encoder;
da3ced29 12019 struct drm_connector *connector;
5448a00d 12020 struct drm_connector_state *connector_state;
00f0b378 12021 unsigned int used_ports = 0;
5448a00d 12022 int i;
00f0b378
VS		 12023
12024 /*
12025 * Walk the connector list instead of the encoder
12026 * list to detect the problem on ddi platforms
12027 * where there's just one encoder per digital port.
12028 */
da3ced29 12029 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12030 if (!connector_state->best_encoder)
00f0b378
VS		 12031 continue;
12032
5448a00d
ACO		 12033 encoder = to_intel_encoder(connector_state->best_encoder);
12034
12035 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12036
12037 switch (encoder->type) {
12038 unsigned int port_mask;
12039 case INTEL_OUTPUT_UNKNOWN:
12040 if (WARN_ON(!HAS_DDI(dev)))
12041 break;
12042 case INTEL_OUTPUT_DISPLAYPORT:
12043 case INTEL_OUTPUT_HDMI:
12044 case INTEL_OUTPUT_EDP:
12045 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12046
12047 /* the same port mustn't appear more than once */
12048 if (used_ports & port_mask)
12049 return false;
12050
12051 used_ports |= port_mask;
12052 default:
12053 break;
12054 }
12055 }
12056
12057 return true;
12058}
12059
83a57153
ACO		 12060static void
12061clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12062{
12063 struct drm_crtc_state tmp_state;
663a3640 12064 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12065 struct intel_dpll_hw_state dpll_hw_state;
12066 enum intel_dpll_id shared_dpll;
8504c74c 12067 uint32_t ddi_pll_sel;
c4e2d043 12068 bool force_thru;
83a57153 12069
7546a384
ACO		 12070 /* FIXME: before the switch to atomic started, a new pipe_config was
12071 * kzalloc'd. Code that depends on any field being zero should be
12072 * fixed, so that the crtc_state can be safely duplicated. For now,
12073 * only fields that are know to not cause problems are preserved. */
12074
83a57153 12075 tmp_state = crtc_state->base;
663a3640 12076 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12077 shared_dpll = crtc_state->shared_dpll;
12078 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12079 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12080 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12081
83a57153 12082 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12083
83a57153 12084 crtc_state->base = tmp_state;
663a3640 12085 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12086 crtc_state->shared_dpll = shared_dpll;
12087 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12088 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12089 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12090}
12091
548ee15b 12092static int
b8cecdf5 12093intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12094 struct intel_crtc_state *pipe_config)
ee7b9f93 12095{
b359283a 12096 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12097 struct intel_encoder *encoder;
da3ced29 12098 struct drm_connector *connector;
0b901879 12099 struct drm_connector_state *connector_state;
d328c9d7 12100 int base_bpp, ret = -EINVAL;
0b901879 12101 int i;
e29c22c0 12102 bool retry = true;
ee7b9f93 12103
83a57153 12104 clear_intel_crtc_state(pipe_config);
7758a113 12105
e143a21c
DV		 12106 pipe_config->cpu_transcoder =
12107 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12108
2960bc9c
ID		 12109 /*
12110 * Sanitize sync polarity flags based on requested ones. If neither
12111 * positive or negative polarity is requested, treat this as meaning
12112 * negative polarity.
12113 */
2d112de7 12114 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12115 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12116 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12117
2d112de7 12118 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12119 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12120 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12121
050f7aeb
DV		 12122 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12123 * plane pixel format and any sink constraints into account. Returns the
12124 * source plane bpp so that dithering can be selected on mismatches
12125 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12126 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12127 pipe_config);
12128 if (base_bpp < 0)
4e53c2e0
DV		 12129 goto fail;
12130
e41a56be
VS		 12131 /*
12132 * Determine the real pipe dimensions. Note that stereo modes can
12133 * increase the actual pipe size due to the frame doubling and
12134 * insertion of additional space for blanks between the frame. This
12135 * is stored in the crtc timings. We use the requested mode to do this
12136 * computation to clearly distinguish it from the adjusted mode, which
12137 * can be changed by the connectors in the below retry loop.
12138 */
2d112de7 12139 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12140 &pipe_config->pipe_src_w,
12141 &pipe_config->pipe_src_h);
e41a56be 12142
e29c22c0 12143encoder_retry:
ef1b460d 12144 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12145 pipe_config->port_clock = 0;
ef1b460d 12146 pipe_config->pixel_multiplier = 1;
ff9a6750 12147
135c81b8 12148 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12149 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12150 CRTC_STEREO_DOUBLE);
135c81b8 12151
7758a113
DV		 12152 /* Pass our mode to the connectors and the CRTC to give them a chance to
12153 * adjust it according to limitations or connector properties, and also
12154 * a chance to reject the mode entirely.
47f1c6c9 12155 */
da3ced29 12156 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12157 if (connector_state->crtc != crtc)
7758a113 12158 continue;
7ae89233 12159
0b901879
ACO		 12160 encoder = to_intel_encoder(connector_state->best_encoder);
12161
efea6e8e
DV		 12162 if (!(encoder->compute_config(encoder, pipe_config))) {
12163 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12164 goto fail;
12165 }
ee7b9f93 12166 }
47f1c6c9 12167
ff9a6750
DV		 12168 /* Set default port clock if not overwritten by the encoder. Needs to be
12169 * done afterwards in case the encoder adjusts the mode. */
12170 if (!pipe_config->port_clock)
2d112de7 12171 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12172 * pipe_config->pixel_multiplier;
ff9a6750 12173
a43f6e0f 12174 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12175 if (ret < 0) {
7758a113
DV		 12176 DRM_DEBUG_KMS("CRTC fixup failed\n");
12177 goto fail;
ee7b9f93 12178 }
e29c22c0
DV		 12179
12180 if (ret == RETRY) {
12181 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12182 ret = -EINVAL;
12183 goto fail;
12184 }
12185
12186 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12187 retry = false;
12188 goto encoder_retry;
12189 }
12190
e8fa4270
DV		 12191 /* Dithering seems to not pass-through bits correctly when it should, so
12192 * only enable it on 6bpc panels. */
12193 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
4e53c2e0 12194 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12195 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12196
7758a113 12197fail:
548ee15b 12198 return ret;
ee7b9f93 12199}
47f1c6c9 12200
ea9d758d 12201static void
4740b0f2 12202intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12203{
0a9ab303
ACO		 12204 struct drm_crtc *crtc;
12205 struct drm_crtc_state *crtc_state;
8a75d157 12206 int i;
ea9d758d 12207
7668851f 12208 /* Double check state. */
8a75d157 12209 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12210 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12211
12212 /* Update hwmode for vblank functions */
12213 if (crtc->state->active)
12214 crtc->hwmode = crtc->state->adjusted_mode;
12215 else
12216 crtc->hwmode.crtc_clock = 0;
ea9d758d 12217 }
ea9d758d
DV		 12218}
12219
3bd26263 12220static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12221{
3bd26263 12222 int diff;
f1f644dc
JB		 12223
12224 if (clock1 == clock2)
12225 return true;
12226
12227 if (!clock1 || !clock2)
12228 return false;
12229
12230 diff = abs(clock1 - clock2);
12231
12232 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12233 return true;
12234
12235 return false;
12236}
12237
25c5b266
DV		 12238#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12239 list_for_each_entry((intel_crtc), \
12240 &(dev)->mode_config.crtc_list, \
12241 base.head) \
0973f18f 12242 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12243
cfb23ed6
ML		 12244
12245static bool
12246intel_compare_m_n(unsigned int m, unsigned int n,
12247 unsigned int m2, unsigned int n2,
12248 bool exact)
12249{
12250 if (m == m2 && n == n2)
12251 return true;
12252
12253 if (exact || !m || !n || !m2 || !n2)
12254 return false;
12255
12256 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12257
12258 if (m > m2) {
12259 while (m > m2) {
12260 m2 <<= 1;
12261 n2 <<= 1;
12262 }
12263 } else if (m < m2) {
12264 while (m < m2) {
12265 m <<= 1;
12266 n <<= 1;
12267 }
12268 }
12269
12270 return m == m2 && n == n2;
12271}
12272
12273static bool
12274intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12275 struct intel_link_m_n *m2_n2,
12276 bool adjust)
12277{
12278 if (m_n->tu == m2_n2->tu &&
12279 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12280 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12281 intel_compare_m_n(m_n->link_m, m_n->link_n,
12282 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12283 if (adjust)
12284 *m2_n2 = *m_n;
12285
12286 return true;
12287 }
12288
12289 return false;
12290}
12291
0e8ffe1b 12292static bool
2fa2fe9a 12293intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12294 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12295 struct intel_crtc_state *pipe_config,
12296 bool adjust)
0e8ffe1b 12297{
cfb23ed6
ML		 12298 bool ret = true;
12299
12300#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12301 do { \
12302 if (!adjust) \
12303 DRM_ERROR(fmt, ##__VA_ARGS__); \
12304 else \
12305 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12306 } while (0)
12307
66e985c0
DV		 12308#define PIPE_CONF_CHECK_X(name) \
12309 if (current_config->name != pipe_config->name) { \
cfb23ed6 12310 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12311 "(expected 0x%08x, found 0x%08x)\n", \
12312 current_config->name, \
12313 pipe_config->name); \
cfb23ed6 12314 ret = false; \
66e985c0
DV		 12315 }
12316
08a24034
DV		 12317#define PIPE_CONF_CHECK_I(name) \
12318 if (current_config->name != pipe_config->name) { \
cfb23ed6 12319 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12320 "(expected %i, found %i)\n", \
12321 current_config->name, \
12322 pipe_config->name); \
cfb23ed6
ML		 12323 ret = false; \
12324 }
12325
12326#define PIPE_CONF_CHECK_M_N(name) \
12327 if (!intel_compare_link_m_n(&current_config->name, \
12328 &pipe_config->name,\
12329 adjust)) { \
12330 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12331 "(expected tu %i gmch %i/%i link %i/%i, " \
12332 "found tu %i, gmch %i/%i link %i/%i)\n", \
12333 current_config->name.tu, \
12334 current_config->name.gmch_m, \
12335 current_config->name.gmch_n, \
12336 current_config->name.link_m, \
12337 current_config->name.link_n, \
12338 pipe_config->name.tu, \
12339 pipe_config->name.gmch_m, \
12340 pipe_config->name.gmch_n, \
12341 pipe_config->name.link_m, \
12342 pipe_config->name.link_n); \
12343 ret = false; \
12344 }
12345
12346#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12347 if (!intel_compare_link_m_n(&current_config->name, \
12348 &pipe_config->name, adjust) && \
12349 !intel_compare_link_m_n(&current_config->alt_name, \
12350 &pipe_config->name, adjust)) { \
12351 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12352 "(expected tu %i gmch %i/%i link %i/%i, " \
12353 "or tu %i gmch %i/%i link %i/%i, " \
12354 "found tu %i, gmch %i/%i link %i/%i)\n", \
12355 current_config->name.tu, \
12356 current_config->name.gmch_m, \
12357 current_config->name.gmch_n, \
12358 current_config->name.link_m, \
12359 current_config->name.link_n, \
12360 current_config->alt_name.tu, \
12361 current_config->alt_name.gmch_m, \
12362 current_config->alt_name.gmch_n, \
12363 current_config->alt_name.link_m, \
12364 current_config->alt_name.link_n, \
12365 pipe_config->name.tu, \
12366 pipe_config->name.gmch_m, \
12367 pipe_config->name.gmch_n, \
12368 pipe_config->name.link_m, \
12369 pipe_config->name.link_n); \
12370 ret = false; \
88adfff1
DV		 12371 }
12372
b95af8be
VK		 12373/* This is required for BDW+ where there is only one set of registers for
12374 * switching between high and low RR.
12375 * This macro can be used whenever a comparison has to be made between one
12376 * hw state and multiple sw state variables.
12377 */
12378#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12379 if ((current_config->name != pipe_config->name) && \
12380 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12381 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12382 "(expected %i or %i, found %i)\n", \
12383 current_config->name, \
12384 current_config->alt_name, \
12385 pipe_config->name); \
cfb23ed6 12386 ret = false; \
b95af8be
VK		 12387 }
12388
1bd1bd80
DV		 12389#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12390 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12391 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12392 "(expected %i, found %i)\n", \
12393 current_config->name & (mask), \
12394 pipe_config->name & (mask)); \
cfb23ed6 12395 ret = false; \
1bd1bd80
DV		 12396 }
12397
5e550656
VS		 12398#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12399 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12400 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12401 "(expected %i, found %i)\n", \
12402 current_config->name, \
12403 pipe_config->name); \
cfb23ed6 12404 ret = false; \
5e550656
VS		 12405 }
12406
bb760063
DV		 12407#define PIPE_CONF_QUIRK(quirk) \
12408 ((current_config->quirks | pipe_config->quirks) & (quirk))
12409
eccb140b
DV		 12410 PIPE_CONF_CHECK_I(cpu_transcoder);
12411
08a24034
DV		 12412 PIPE_CONF_CHECK_I(has_pch_encoder);
12413 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12414 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12415
eb14cb74 12416 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12417
12418 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12419 PIPE_CONF_CHECK_M_N(dp_m_n);
12420
12421 PIPE_CONF_CHECK_I(has_drrs);
12422 if (current_config->has_drrs)
12423 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12424 } else
12425 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12426
2d112de7
ACO		 12427 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12428 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12429 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12433
2d112de7
ACO		 12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12435 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12436 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12440
c93f54cf 12441 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12442 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12443 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12444 IS_VALLEYVIEW(dev))
12445 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12446 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12447
9ed109a7
DV		 12448 PIPE_CONF_CHECK_I(has_audio);
12449
2d112de7 12450 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12451 DRM_MODE_FLAG_INTERLACE);
12452
bb760063 12453 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12454 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12455 DRM_MODE_FLAG_PHSYNC);
2d112de7 12456 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12457 DRM_MODE_FLAG_NHSYNC);
2d112de7 12458 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12459 DRM_MODE_FLAG_PVSYNC);
2d112de7 12460 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12461 DRM_MODE_FLAG_NVSYNC);
12462 }
045ac3b5 12463
37327abd
VS		 12464 PIPE_CONF_CHECK_I(pipe_src_w);
12465 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12466
e2ff2d4a
DV		 12467 PIPE_CONF_CHECK_I(gmch_pfit.control);
12468 /* pfit ratios are autocomputed by the hw on gen4+ */
12469 if (INTEL_INFO(dev)->gen < 4)
12470 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12471 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9953599b 12472
fd4daa9c
CW		 12473 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12474 if (current_config->pch_pfit.enabled) {
12475 PIPE_CONF_CHECK_I(pch_pfit.pos);
12476 PIPE_CONF_CHECK_I(pch_pfit.size);
12477 }
2fa2fe9a 12478
a1b2278e
CK		 12479 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12480
e59150dc
JB		 12481 /* BDW+ don't expose a synchronous way to read the state */
12482 if (IS_HASWELL(dev))
12483 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12484
282740f7
VS		 12485 PIPE_CONF_CHECK_I(double_wide);
12486
26804afd
DV		 12487 PIPE_CONF_CHECK_X(ddi_pll_sel);
12488
c0d43d62 12489 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12490 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12491 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12492 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12493 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12494 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12495 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12497 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12498
42571aef
VS		 12499 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12500 PIPE_CONF_CHECK_I(pipe_bpp);
12501
2d112de7 12502 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12503 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12504
66e985c0 12505#undef PIPE_CONF_CHECK_X
08a24034 12506#undef PIPE_CONF_CHECK_I
b95af8be 12507#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12508#undef PIPE_CONF_CHECK_FLAGS
5e550656 12509#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12510#undef PIPE_CONF_QUIRK
cfb23ed6 12511#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12512
cfb23ed6 12513 return ret;
0e8ffe1b
DV		 12514}
12515
08db6652
DL		 12516static void check_wm_state(struct drm_device *dev)
12517{
12518 struct drm_i915_private *dev_priv = dev->dev_private;
12519 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12520 struct intel_crtc *intel_crtc;
12521 int plane;
12522
12523 if (INTEL_INFO(dev)->gen < 9)
12524 return;
12525
12526 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12527 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12528
12529 for_each_intel_crtc(dev, intel_crtc) {
12530 struct skl_ddb_entry *hw_entry, *sw_entry;
12531 const enum pipe pipe = intel_crtc->pipe;
12532
12533 if (!intel_crtc->active)
12534 continue;
12535
12536 /* planes */
dd740780 12537 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12538 hw_entry = &hw_ddb.plane[pipe][plane];
12539 sw_entry = &sw_ddb->plane[pipe][plane];
12540
12541 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12542 continue;
12543
12544 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12545 "(expected (%u,%u), found (%u,%u))\n",
12546 pipe_name(pipe), plane + 1,
12547 sw_entry->start, sw_entry->end,
12548 hw_entry->start, hw_entry->end);
12549 }
12550
12551 /* cursor */
12552 hw_entry = &hw_ddb.cursor[pipe];
12553 sw_entry = &sw_ddb->cursor[pipe];
12554
12555 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12556 continue;
12557
12558 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12559 "(expected (%u,%u), found (%u,%u))\n",
12560 pipe_name(pipe),
12561 sw_entry->start, sw_entry->end,
12562 hw_entry->start, hw_entry->end);
12563 }
12564}
12565
91d1b4bd 12566static void
35dd3c64
ML		 12567check_connector_state(struct drm_device *dev,
12568 struct drm_atomic_state *old_state)
8af6cf88 12569{
35dd3c64
ML		 12570 struct drm_connector_state *old_conn_state;
12571 struct drm_connector *connector;
12572 int i;
8af6cf88 12573
35dd3c64
ML		 12574 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12575 struct drm_encoder *encoder = connector->encoder;
12576 struct drm_connector_state *state = connector->state;
ad3c558f 12577
8af6cf88
DV		 12578 /* This also checks the encoder/connector hw state with the
12579 * ->get_hw_state callbacks. */
35dd3c64 12580 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12581
ad3c558f 12582 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12583 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12584 }
91d1b4bd
DV		 12585}
12586
12587static void
12588check_encoder_state(struct drm_device *dev)
12589{
12590 struct intel_encoder *encoder;
12591 struct intel_connector *connector;
8af6cf88 12592
b2784e15 12593 for_each_intel_encoder(dev, encoder) {
8af6cf88 12594 bool enabled = false;
4d20cd86 12595 enum pipe pipe;
8af6cf88
DV		 12596
12597 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12598 encoder->base.base.id,
8e329a03 12599 encoder->base.name);
8af6cf88 12600
3a3371ff 12601 for_each_intel_connector(dev, connector) {
4d20cd86 12602 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12603 continue;
12604 enabled = true;
ad3c558f
ML		 12605
12606 I915_STATE_WARN(connector->base.state->crtc !=
12607 encoder->base.crtc,
12608 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12609 }
0e32b39c 12610
e2c719b7 12611 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12612 "encoder's enabled state mismatch "
12613 "(expected %i, found %i)\n",
12614 !!encoder->base.crtc, enabled);
8af6cf88 12615
7c60d198 12616 if (!encoder->base.crtc) {
4d20cd86 12617 bool active;
8af6cf88 12618
4d20cd86
ML		 12619 active = encoder->get_hw_state(encoder, &pipe);
12620 I915_STATE_WARN(active,
12621 "encoder detached but still enabled on pipe %c.\n",
12622 pipe_name(pipe));
7c60d198 12623 }
8af6cf88 12624 }
91d1b4bd
DV		 12625}
12626
12627static void
4d20cd86 12628check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12629{
fbee40df 12630 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12631 struct intel_encoder *encoder;
4d20cd86
ML		 12632 struct drm_crtc_state *old_crtc_state;
12633 struct drm_crtc *crtc;
12634 int i;
8af6cf88 12635
4d20cd86
ML		 12636 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12638 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12639 bool active;
8af6cf88 12640
4d20cd86
ML		 12641 if (!needs_modeset(crtc->state))
12642 continue;
045ac3b5 12643
4d20cd86
ML		 12644 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12645 pipe_config = to_intel_crtc_state(old_crtc_state);
12646 memset(pipe_config, 0, sizeof(*pipe_config));
12647 pipe_config->base.crtc = crtc;
12648 pipe_config->base.state = old_state;
8af6cf88 12649
4d20cd86
ML		 12650 DRM_DEBUG_KMS("[CRTC:%d]\n",
12651 crtc->base.id);
8af6cf88 12652
4d20cd86
ML		 12653 active = dev_priv->display.get_pipe_config(intel_crtc,
12654 pipe_config);
6c49f241 12655
b6b5d049 12656 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12657 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12658 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12659 active = crtc->state->active;
8af6cf88 12660
4d20cd86 12661 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12662 "crtc active state doesn't match with hw state "
4d20cd86 12663 "(expected %i, found %i)\n", crtc->state->active, active);
d62cf62a 12664
4d20cd86 12665 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12666 "transitional active state does not match atomic hw state "
4d20cd86 12667 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
d62cf62a 12668
4d20cd86 12669 for_each_encoder_on_crtc(dev, crtc, encoder) {
3eaba51c 12670 enum pipe pipe;
6c49f241 12671
4d20cd86
ML		 12672 active = encoder->get_hw_state(encoder, &pipe);
12673 I915_STATE_WARN(active != crtc->state->active,
12674 "[ENCODER:%i] active %i with crtc active %i\n",
12675 encoder->base.base.id, active, crtc->state->active);
0e8ffe1b 12676
4d20cd86
ML		 12677 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12678 "Encoder connected to wrong pipe %c\n",
12679 pipe_name(pipe));
53d9f4e9 12680
4d20cd86
ML		 12681 if (active)
12682 encoder->get_config(encoder, pipe_config);
12683 }
53d9f4e9 12684
4d20cd86 12685 if (!crtc->state->active)
cfb23ed6
ML		 12686 continue;
12687
4d20cd86
ML		 12688 sw_config = to_intel_crtc_state(crtc->state);
12689 if (!intel_pipe_config_compare(dev, sw_config,
12690 pipe_config, false)) {
e2c719b7 12691 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12692 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12693 "[hw state]");
4d20cd86 12694 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12695 "[sw state]");
12696 }
8af6cf88
DV		 12697 }
12698}
12699
91d1b4bd
DV		 12700static void
12701check_shared_dpll_state(struct drm_device *dev)
12702{
fbee40df 12703 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12704 struct intel_crtc *crtc;
12705 struct intel_dpll_hw_state dpll_hw_state;
12706 int i;
5358901f
DV		 12707
12708 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12709 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12710 int enabled_crtcs = 0, active_crtcs = 0;
12711 bool active;
12712
12713 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12714
12715 DRM_DEBUG_KMS("%s\n", pll->name);
12716
12717 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12718
e2c719b7 12719 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12720 "more active pll users than references: %i vs %i\n",
3e369b76 12721 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12722 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12723 "pll in active use but not on in sw tracking\n");
e2c719b7 12724 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12725 "pll in on but not on in use in sw tracking\n");
e2c719b7 12726 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12727 "pll on state mismatch (expected %i, found %i)\n",
12728 pll->on, active);
12729
d3fcc808 12730 for_each_intel_crtc(dev, crtc) {
83d65738 12731 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12732 enabled_crtcs++;
12733 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12734 active_crtcs++;
12735 }
e2c719b7 12736 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12737 "pll active crtcs mismatch (expected %i, found %i)\n",
12738 pll->active, active_crtcs);
e2c719b7 12739 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12740 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12741 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12742
e2c719b7 12743 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12744 sizeof(dpll_hw_state)),
12745 "pll hw state mismatch\n");
5358901f 12746 }
8af6cf88
DV		 12747}
12748
ee165b1a
ML		 12749static void
12750intel_modeset_check_state(struct drm_device *dev,
12751 struct drm_atomic_state *old_state)
91d1b4bd 12752{
08db6652 12753 check_wm_state(dev);
35dd3c64 12754 check_connector_state(dev, old_state);
91d1b4bd 12755 check_encoder_state(dev);
4d20cd86 12756 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12757 check_shared_dpll_state(dev);
12758}
12759
5cec258b 12760void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12761 int dotclock)
12762{
12763 /*
12764 * FDI already provided one idea for the dotclock.
12765 * Yell if the encoder disagrees.
12766 */
2d112de7 12767 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12768 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12769 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12770}
12771
80715b2f
VS		 12772static void update_scanline_offset(struct intel_crtc *crtc)
12773{
12774 struct drm_device *dev = crtc->base.dev;
12775
12776 /*
12777 * The scanline counter increments at the leading edge of hsync.
12778 *
12779 * On most platforms it starts counting from vtotal-1 on the
12780 * first active line. That means the scanline counter value is
12781 * always one less than what we would expect. Ie. just after
12782 * start of vblank, which also occurs at start of hsync (on the
12783 * last active line), the scanline counter will read vblank_start-1.
12784 *
12785 * On gen2 the scanline counter starts counting from 1 instead
12786 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12787 * to keep the value positive), instead of adding one.
12788 *
12789 * On HSW+ the behaviour of the scanline counter depends on the output
12790 * type. For DP ports it behaves like most other platforms, but on HDMI
12791 * there's an extra 1 line difference. So we need to add two instead of
12792 * one to the value.
12793 */
12794 if (IS_GEN2(dev)) {
6e3c9717 12795 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12796 int vtotal;
12797
12798 vtotal = mode->crtc_vtotal;
12799 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12800 vtotal /= 2;
12801
12802 crtc->scanline_offset = vtotal - 1;
12803 } else if (HAS_DDI(dev) &&
409ee761 12804 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12805 crtc->scanline_offset = 2;
12806 } else
12807 crtc->scanline_offset = 1;
12808}
12809
ad421372 12810static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12811{
225da59b 12812 struct drm_device *dev = state->dev;
ed6739ef 12813 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12814 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12815 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12816 struct intel_crtc_state *intel_crtc_state;
12817 struct drm_crtc *crtc;
12818 struct drm_crtc_state *crtc_state;
0a9ab303 12819 int i;
ed6739ef
ACO		 12820
12821 if (!dev_priv->display.crtc_compute_clock)
ad421372 12822 return;
ed6739ef 12823
0a9ab303 12824 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12825 int dpll;
12826
0a9ab303 12827 intel_crtc = to_intel_crtc(crtc);
4978cc93 12828 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12829 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12830
ad421372 12831 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12832 continue;
12833
ad421372 12834 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12835
ad421372
ML		 12836 if (!shared_dpll)
12837 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12838
ad421372
ML		 12839 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12840 }
ed6739ef
ACO		 12841}
12842
99d736a2
ML		 12843/*
12844 * This implements the workaround described in the "notes" section of the mode
12845 * set sequence documentation. When going from no pipes or single pipe to
12846 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12847 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12848 */
12849static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12850{
12851 struct drm_crtc_state *crtc_state;
12852 struct intel_crtc *intel_crtc;
12853 struct drm_crtc *crtc;
12854 struct intel_crtc_state *first_crtc_state = NULL;
12855 struct intel_crtc_state *other_crtc_state = NULL;
12856 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12857 int i;
12858
12859 /* look at all crtc's that are going to be enabled in during modeset */
12860 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12861 intel_crtc = to_intel_crtc(crtc);
12862
12863 if (!crtc_state->active || !needs_modeset(crtc_state))
12864 continue;
12865
12866 if (first_crtc_state) {
12867 other_crtc_state = to_intel_crtc_state(crtc_state);
12868 break;
12869 } else {
12870 first_crtc_state = to_intel_crtc_state(crtc_state);
12871 first_pipe = intel_crtc->pipe;
12872 }
12873 }
12874
12875 /* No workaround needed? */
12876 if (!first_crtc_state)
12877 return 0;
12878
12879 /* w/a possibly needed, check how many crtc's are already enabled. */
12880 for_each_intel_crtc(state->dev, intel_crtc) {
12881 struct intel_crtc_state *pipe_config;
12882
12883 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12884 if (IS_ERR(pipe_config))
12885 return PTR_ERR(pipe_config);
12886
12887 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12888
12889 if (!pipe_config->base.active ||
12890 needs_modeset(&pipe_config->base))
12891 continue;
12892
12893 /* 2 or more enabled crtcs means no need for w/a */
12894 if (enabled_pipe != INVALID_PIPE)
12895 return 0;
12896
12897 enabled_pipe = intel_crtc->pipe;
12898 }
12899
12900 if (enabled_pipe != INVALID_PIPE)
12901 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12902 else if (other_crtc_state)
12903 other_crtc_state->hsw_workaround_pipe = first_pipe;
12904
12905 return 0;
12906}
12907
27c329ed
ML		 12908static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12909{
12910 struct drm_crtc *crtc;
12911 struct drm_crtc_state *crtc_state;
12912 int ret = 0;
12913
12914 /* add all active pipes to the state */
12915 for_each_crtc(state->dev, crtc) {
12916 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12917 if (IS_ERR(crtc_state))
12918 return PTR_ERR(crtc_state);
12919
12920 if (!crtc_state->active || needs_modeset(crtc_state))
12921 continue;
12922
12923 crtc_state->mode_changed = true;
12924
12925 ret = drm_atomic_add_affected_connectors(state, crtc);
12926 if (ret)
12927 break;
12928
12929 ret = drm_atomic_add_affected_planes(state, crtc);
12930 if (ret)
12931 break;
12932 }
12933
12934 return ret;
12935}
12936
12937
c347a676 12938static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12939{
12940 struct drm_device *dev = state->dev;
27c329ed 12941 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12942 int ret;
12943
b359283a
ML		 12944 if (!check_digital_port_conflicts(state)) {
12945 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12946 return -EINVAL;
12947 }
12948
054518dd
ACO		 12949 /*
12950 * See if the config requires any additional preparation, e.g.
12951 * to adjust global state with pipes off. We need to do this
12952 * here so we can get the modeset_pipe updated config for the new
12953 * mode set on this crtc. For other crtcs we need to use the
12954 * adjusted_mode bits in the crtc directly.
12955 */
27c329ed
ML		 12956 if (dev_priv->display.modeset_calc_cdclk) {
12957 unsigned int cdclk;
b432e5cf 12958
27c329ed
ML		 12959 ret = dev_priv->display.modeset_calc_cdclk(state);
12960
12961 cdclk = to_intel_atomic_state(state)->cdclk;
12962 if (!ret && cdclk != dev_priv->cdclk_freq)
12963 ret = intel_modeset_all_pipes(state);
12964
12965 if (ret < 0)
054518dd 12966 return ret;
27c329ed
ML		 12967 } else
12968 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12969
ad421372 12970 intel_modeset_clear_plls(state);
054518dd 12971
99d736a2 12972 if (IS_HASWELL(dev))
ad421372 12973 return haswell_mode_set_planes_workaround(state);
99d736a2 12974
ad421372 12975 return 0;
c347a676
ACO		 12976}
12977
74c090b1
ML		 12978/**
12979 * intel_atomic_check - validate state object
12980 * @dev: drm device
12981 * @state: state to validate
12982 */
12983static int intel_atomic_check(struct drm_device *dev,
12984 struct drm_atomic_state *state)
c347a676
ACO		 12985{
12986 struct drm_crtc *crtc;
12987 struct drm_crtc_state *crtc_state;
12988 int ret, i;
61333b60 12989 bool any_ms = false;
c347a676 12990
74c090b1 12991 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12992 if (ret)
12993 return ret;
12994
c347a676 12995 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12996 struct intel_crtc_state *pipe_config =
12997 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 12998
12999 /* Catch I915_MODE_FLAG_INHERITED */
13000 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13001 crtc_state->mode_changed = true;
cfb23ed6 13002
61333b60
ML		 13003 if (!crtc_state->enable) {
13004 if (needs_modeset(crtc_state))
13005 any_ms = true;
c347a676 13006 continue;
61333b60 13007 }
c347a676 13008
26495481 13009 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13010 continue;
13011
26495481
DV		 13012 /* FIXME: For only active_changed we shouldn't need to do any
13013 * state recomputation at all. */
13014
1ed51de9
DV		 13015 ret = drm_atomic_add_affected_connectors(state, crtc);
13016 if (ret)
13017 return ret;
b359283a 13018
cfb23ed6 13019 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13020 if (ret)
13021 return ret;
13022
26495481
DV		 13023 if (i915.fastboot &&
13024 intel_pipe_config_compare(state->dev,
cfb23ed6 13025 to_intel_crtc_state(crtc->state),
1ed51de9 13026 pipe_config, true)) {
26495481
DV		 13027 crtc_state->mode_changed = false;
13028 }
13029
13030 if (needs_modeset(crtc_state)) {
13031 any_ms = true;
cfb23ed6
ML		 13032
13033 ret = drm_atomic_add_affected_planes(state, crtc);
13034 if (ret)
13035 return ret;
13036 }
61333b60 13037
26495481
DV		 13038 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13039 needs_modeset(crtc_state) ?
13040 "[modeset]" : "[fastset]");
c347a676
ACO		 13041 }
13042
61333b60
ML		 13043 if (any_ms) {
13044 ret = intel_modeset_checks(state);
13045
13046 if (ret)
13047 return ret;
27c329ed
ML		 13048 } else
13049 to_intel_atomic_state(state)->cdclk =
13050 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13051
13052 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13053}
13054
74c090b1
ML		 13055/**
13056 * intel_atomic_commit - commit validated state object
13057 * @dev: DRM device
13058 * @state: the top-level driver state object
13059 * @async: asynchronous commit
13060 *
13061 * This function commits a top-level state object that has been validated
13062 * with drm_atomic_helper_check().
13063 *
13064 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13065 * we can only handle plane-related operations and do not yet support
13066 * asynchronous commit.
13067 *
13068 * RETURNS
13069 * Zero for success or -errno.
13070 */
13071static int intel_atomic_commit(struct drm_device *dev,
13072 struct drm_atomic_state *state,
13073 bool async)
a6778b3c 13074{
fbee40df 13075 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13076 struct drm_crtc *crtc;
13077 struct drm_crtc_state *crtc_state;
c0c36b94 13078 int ret = 0;
0a9ab303 13079 int i;
61333b60 13080 bool any_ms = false;
a6778b3c 13081
74c090b1
ML		 13082 if (async) {
13083 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13084 return -EINVAL;
13085 }
13086
d4afb8cc
ACO		 13087 ret = drm_atomic_helper_prepare_planes(dev, state);
13088 if (ret)
13089 return ret;
13090
1c5e19f8
ML		 13091 drm_atomic_helper_swap_state(dev, state);
13092
0a9ab303 13093 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13095
61333b60
ML		 13096 if (!needs_modeset(crtc->state))
13097 continue;
13098
13099 any_ms = true;
a539205a 13100 intel_pre_plane_update(intel_crtc);
460da916 13101
a539205a
ML		 13102 if (crtc_state->active) {
13103 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13104 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13105 intel_crtc->active = false;
13106 intel_disable_shared_dpll(intel_crtc);
a539205a 13107 }
b8cecdf5 13108 }
7758a113 13109
ea9d758d
DV		 13110 /* Only after disabling all output pipelines that will be changed can we
13111 * update the the output configuration. */
4740b0f2 13112 intel_modeset_update_crtc_state(state);
f6e5b160 13113
4740b0f2
ML		 13114 if (any_ms) {
13115 intel_shared_dpll_commit(state);
13116
13117 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13118 modeset_update_crtc_power_domains(state);
4740b0f2 13119 }
47fab737 13120
a6778b3c 13121 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13122 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13124 bool modeset = needs_modeset(crtc->state);
13125
13126 if (modeset && crtc->state->active) {
a539205a
ML		 13127 update_scanline_offset(to_intel_crtc(crtc));
13128 dev_priv->display.crtc_enable(crtc);
13129 }
80715b2f 13130
f6ac4b2a
ML		 13131 if (!modeset)
13132 intel_pre_plane_update(intel_crtc);
13133
a539205a 13134 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13135 intel_post_plane_update(intel_crtc);
80715b2f 13136 }
a6778b3c 13137
a6778b3c 13138 /* FIXME: add subpixel order */
83a57153 13139
74c090b1 13140 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13141 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13142
74c090b1 13143 if (any_ms)
ee165b1a
ML		 13144 intel_modeset_check_state(dev, state);
13145
13146 drm_atomic_state_free(state);
f30da187 13147
74c090b1 13148 return 0;
7f27126e
JB		 13149}
13150
c0c36b94
CW		 13151void intel_crtc_restore_mode(struct drm_crtc *crtc)
13152{
83a57153
ACO		 13153 struct drm_device *dev = crtc->dev;
13154 struct drm_atomic_state *state;
e694eb02 13155 struct drm_crtc_state *crtc_state;
2bfb4627 13156 int ret;
83a57153
ACO		 13157
13158 state = drm_atomic_state_alloc(dev);
13159 if (!state) {
e694eb02 13160 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13161 crtc->base.id);
13162 return;
13163 }
13164
e694eb02 13165 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13166
e694eb02
ML		 13167retry:
13168 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13169 ret = PTR_ERR_OR_ZERO(crtc_state);
13170 if (!ret) {
13171 if (!crtc_state->active)
13172 goto out;
83a57153 13173
e694eb02 13174 crtc_state->mode_changed = true;
74c090b1 13175 ret = drm_atomic_commit(state);
83a57153
ACO		 13176 }
13177
e694eb02
ML		 13178 if (ret == -EDEADLK) {
13179 drm_atomic_state_clear(state);
13180 drm_modeset_backoff(state->acquire_ctx);
13181 goto retry;
4ed9fb37 13182 }
4be07317 13183
2bfb4627 13184 if (ret)
e694eb02 13185out:
2bfb4627 13186 drm_atomic_state_free(state);
c0c36b94
CW		 13187}
13188
25c5b266
DV		 13189#undef for_each_intel_crtc_masked
13190
f6e5b160 13191static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13192 .gamma_set = intel_crtc_gamma_set,
74c090b1 13193 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13194 .destroy = intel_crtc_destroy,
13195 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13196 .atomic_duplicate_state = intel_crtc_duplicate_state,
13197 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13198};
13199
5358901f
DV		 13200static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13201 struct intel_shared_dpll *pll,
13202 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13203{
5358901f 13204 uint32_t val;
ee7b9f93 13205
f458ebbc 13206 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13207 return false;
13208
5358901f 13209 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13210 hw_state->dpll = val;
13211 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13212 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13213
13214 return val & DPLL_VCO_ENABLE;
13215}
13216
15bdd4cf
DV		 13217static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13218 struct intel_shared_dpll *pll)
13219{
3e369b76
ACO		 13220 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13221 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13222}
13223
e7b903d2
DV		 13224static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13225 struct intel_shared_dpll *pll)
13226{
e7b903d2 13227 /* PCH refclock must be enabled first */
89eff4be 13228 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13229
3e369b76 13230 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13231
13232 /* Wait for the clocks to stabilize. */
13233 POSTING_READ(PCH_DPLL(pll->id));
13234 udelay(150);
13235
13236 /* The pixel multiplier can only be updated once the
13237 * DPLL is enabled and the clocks are stable.
13238 *
13239 * So write it again.
13240 */
3e369b76 13241 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13242 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13243 udelay(200);
13244}
13245
13246static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13247 struct intel_shared_dpll *pll)
13248{
13249 struct drm_device *dev = dev_priv->dev;
13250 struct intel_crtc *crtc;
e7b903d2
DV		 13251
13252 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13253 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13254 if (intel_crtc_to_shared_dpll(crtc) == pll)
13255 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13256 }
13257
15bdd4cf
DV		 13258 I915_WRITE(PCH_DPLL(pll->id), 0);
13259 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13260 udelay(200);
13261}
13262
46edb027
DV		 13263static char *ibx_pch_dpll_names[] = {
13264 "PCH DPLL A",
13265 "PCH DPLL B",
13266};
13267
7c74ade1 13268static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13269{
e7b903d2 13270 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13271 int i;
13272
7c74ade1 13273 dev_priv->num_shared_dpll = 2;
ee7b9f93 13274
e72f9fbf 13275 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13276 dev_priv->shared_dplls[i].id = i;
13277 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13278 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13279 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13280 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13281 dev_priv->shared_dplls[i].get_hw_state =
13282 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13283 }
13284}
13285
7c74ade1
DV		 13286static void intel_shared_dpll_init(struct drm_device *dev)
13287{
e7b903d2 13288 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13289
b6283055
VS		 13290 intel_update_cdclk(dev);
13291
9cd86933
DV		 13292 if (HAS_DDI(dev))
13293 intel_ddi_pll_init(dev);
13294 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13295 ibx_pch_dpll_init(dev);
13296 else
13297 dev_priv->num_shared_dpll = 0;
13298
13299 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13300}
13301
6beb8c23
MR		 13302/**
13303 * intel_prepare_plane_fb - Prepare fb for usage on plane
13304 * @plane: drm plane to prepare for
13305 * @fb: framebuffer to prepare for presentation
13306 *
13307 * Prepares a framebuffer for usage on a display plane. Generally this
13308 * involves pinning the underlying object and updating the frontbuffer tracking
13309 * bits. Some older platforms need special physical address handling for
13310 * cursor planes.
13311 *
13312 * Returns 0 on success, negative error code on failure.
13313 */
13314int
13315intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13316 struct drm_framebuffer *fb,
13317 const struct drm_plane_state *new_state)
465c120c
MR		 13318{
13319 struct drm_device *dev = plane->dev;
6beb8c23 13320 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13321 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13322 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13323 int ret = 0;
465c120c 13324
ea2c67bb 13325 if (!obj)
465c120c
MR		 13326 return 0;
13327
6beb8c23 13328 mutex_lock(&dev->struct_mutex);
465c120c 13329
6beb8c23
MR		 13330 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13331 INTEL_INFO(dev)->cursor_needs_physical) {
13332 int align = IS_I830(dev) ? 16 * 1024 : 256;
13333 ret = i915_gem_object_attach_phys(obj, align);
13334 if (ret)
13335 DRM_DEBUG_KMS("failed to attach phys object\n");
13336 } else {
91af127f 13337 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13338 }
465c120c 13339
6beb8c23 13340 if (ret == 0)
a9ff8714 13341 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13342
4c34574f 13343 mutex_unlock(&dev->struct_mutex);
465c120c 13344
6beb8c23
MR		 13345 return ret;
13346}
13347
38f3ce3a
MR		 13348/**
13349 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13350 * @plane: drm plane to clean up for
13351 * @fb: old framebuffer that was on plane
13352 *
13353 * Cleans up a framebuffer that has just been removed from a plane.
13354 */
13355void
13356intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13357 struct drm_framebuffer *fb,
13358 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13359{
13360 struct drm_device *dev = plane->dev;
13361 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13362
13363 if (WARN_ON(!obj))
13364 return;
13365
13366 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13367 !INTEL_INFO(dev)->cursor_needs_physical) {
13368 mutex_lock(&dev->struct_mutex);
82bc3b2d 13369 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13370 mutex_unlock(&dev->struct_mutex);
13371 }
465c120c
MR		 13372}
13373
6156a456
CK		 13374int
13375skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13376{
13377 int max_scale;
13378 struct drm_device *dev;
13379 struct drm_i915_private *dev_priv;
13380 int crtc_clock, cdclk;
13381
13382 if (!intel_crtc || !crtc_state)
13383 return DRM_PLANE_HELPER_NO_SCALING;
13384
13385 dev = intel_crtc->base.dev;
13386 dev_priv = dev->dev_private;
13387 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13388 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13389
13390 if (!crtc_clock || !cdclk)
13391 return DRM_PLANE_HELPER_NO_SCALING;
13392
13393 /*
13394 * skl max scale is lower of:
13395 * close to 3 but not 3, -1 is for that purpose
13396 * or
13397 * cdclk/crtc_clock
13398 */
13399 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13400
13401 return max_scale;
13402}
13403
465c120c 13404static int
3c692a41 13405intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13406 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13407 struct intel_plane_state *state)
13408{
2b875c22
MR		 13409 struct drm_crtc *crtc = state->base.crtc;
13410 struct drm_framebuffer *fb = state->base.fb;
6156a456 13411 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13412 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13413 bool can_position = false;
465c120c 13414
061e4b8d
ML		 13415 /* use scaler when colorkey is not required */
13416 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13417 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13418 min_scale = 1;
13419 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13420 can_position = true;
6156a456 13421 }
d8106366 13422
061e4b8d
ML		 13423 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13424 &state->dst, &state->clip,
da20eabd
ML		 13425 min_scale, max_scale,
13426 can_position, true,
13427 &state->visible);
14af293f
GP		 13428}
13429
13430static void
13431intel_commit_primary_plane(struct drm_plane *plane,
13432 struct intel_plane_state *state)
13433{
2b875c22
MR		 13434 struct drm_crtc *crtc = state->base.crtc;
13435 struct drm_framebuffer *fb = state->base.fb;
13436 struct drm_device *dev = plane->dev;
14af293f 13437 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13438 struct intel_crtc *intel_crtc;
14af293f
GP		 13439 struct drm_rect *src = &state->src;
13440
ea2c67bb
MR		 13441 crtc = crtc ? crtc : plane->crtc;
13442 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13443
13444 plane->fb = fb;
9dc806fc
MR		 13445 crtc->x = src->x1 >> 16;
13446 crtc->y = src->y1 >> 16;
ccc759dc 13447
a539205a 13448 if (!crtc->state->active)
302d19ac 13449 return;
465c120c 13450
302d19ac
ML		 13451 if (state->visible)
13452 /* FIXME: kill this fastboot hack */
13453 intel_update_pipe_size(intel_crtc);
13454
13455 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13456}
13457
a8ad0d8e
ML		 13458static void
13459intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13460 struct drm_crtc *crtc)
a8ad0d8e
ML		 13461{
13462 struct drm_device *dev = plane->dev;
13463 struct drm_i915_private *dev_priv = dev->dev_private;
13464
a8ad0d8e
ML		 13465 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13466}
13467
613d2b27
ML		 13468static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13469 struct drm_crtc_state *old_crtc_state)
3c692a41 13470{
32b7eeec 13471 struct drm_device *dev = crtc->dev;
3c692a41 13472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13473
f015c551 13474 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13475 intel_update_watermarks(crtc);
3c692a41 13476
c34c9ee4 13477 /* Perform vblank evasion around commit operation */
a539205a 13478 if (crtc->state->active)
8f539a83 13479 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
0583236e
ML		 13480
13481 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13482 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13483}
13484
613d2b27
ML		 13485static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13486 struct drm_crtc_state *old_crtc_state)
32b7eeec 13487{
32b7eeec 13488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13489
8f539a83
ML		 13490 if (crtc->state->active)
13491 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
3c692a41
GP		 13492}
13493
cf4c7c12 13494/**
4a3b8769
MR		 13495 * intel_plane_destroy - destroy a plane
13496 * @plane: plane to destroy
cf4c7c12 13497 *
4a3b8769
MR		 13498 * Common destruction function for all types of planes (primary, cursor,
13499 * sprite).
cf4c7c12 13500 */
4a3b8769 13501void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13502{
13503 struct intel_plane *intel_plane = to_intel_plane(plane);
13504 drm_plane_cleanup(plane);
13505 kfree(intel_plane);
13506}
13507
65a3fea0 13508const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13509 .update_plane = drm_atomic_helper_update_plane,
13510 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13511 .destroy = intel_plane_destroy,
c196e1d6 13512 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13513 .atomic_get_property = intel_plane_atomic_get_property,
13514 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13515 .atomic_duplicate_state = intel_plane_duplicate_state,
13516 .atomic_destroy_state = intel_plane_destroy_state,
13517
465c120c
MR		 13518};
13519
13520static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13521 int pipe)
13522{
13523 struct intel_plane *primary;
8e7d688b 13524 struct intel_plane_state *state;
465c120c 13525 const uint32_t *intel_primary_formats;
45e3743a 13526 unsigned int num_formats;
465c120c
MR		 13527
13528 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13529 if (primary == NULL)
13530 return NULL;
13531
8e7d688b
MR		 13532 state = intel_create_plane_state(&primary->base);
13533 if (!state) {
ea2c67bb
MR		 13534 kfree(primary);
13535 return NULL;
13536 }
8e7d688b 13537 primary->base.state = &state->base;
ea2c67bb 13538
465c120c
MR		 13539 primary->can_scale = false;
13540 primary->max_downscale = 1;
6156a456
CK		 13541 if (INTEL_INFO(dev)->gen >= 9) {
13542 primary->can_scale = true;
af99ceda 13543 state->scaler_id = -1;
6156a456 13544 }
465c120c
MR		 13545 primary->pipe = pipe;
13546 primary->plane = pipe;
a9ff8714 13547 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13548 primary->check_plane = intel_check_primary_plane;
13549 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13550 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13551 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13552 primary->plane = !pipe;
13553
6c0fd451
DL		 13554 if (INTEL_INFO(dev)->gen >= 9) {
13555 intel_primary_formats = skl_primary_formats;
13556 num_formats = ARRAY_SIZE(skl_primary_formats);
13557 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13558 intel_primary_formats = i965_primary_formats;
13559 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13560 } else {
13561 intel_primary_formats = i8xx_primary_formats;
13562 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13563 }
13564
13565 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13566 &intel_plane_funcs,
465c120c
MR		 13567 intel_primary_formats, num_formats,
13568 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13569
3b7a5119
SJ		 13570 if (INTEL_INFO(dev)->gen >= 4)
13571 intel_create_rotation_property(dev, primary);
48404c1e 13572
ea2c67bb
MR		 13573 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13574
465c120c
MR		 13575 return &primary->base;
13576}
13577
3b7a5119
SJ		 13578void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13579{
13580 if (!dev->mode_config.rotation_property) {
13581 unsigned long flags = BIT(DRM_ROTATE_0) |
13582 BIT(DRM_ROTATE_180);
13583
13584 if (INTEL_INFO(dev)->gen >= 9)
13585 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13586
13587 dev->mode_config.rotation_property =
13588 drm_mode_create_rotation_property(dev, flags);
13589 }
13590 if (dev->mode_config.rotation_property)
13591 drm_object_attach_property(&plane->base.base,
13592 dev->mode_config.rotation_property,
13593 plane->base.state->rotation);
13594}
13595
3d7d6510 13596static int
852e787c 13597intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13598 struct intel_crtc_state *crtc_state,
852e787c 13599 struct intel_plane_state *state)
3d7d6510 13600{
061e4b8d 13601 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13602 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13603 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13604 unsigned stride;
13605 int ret;
3d7d6510 13606
061e4b8d
ML		 13607 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13608 &state->dst, &state->clip,
3d7d6510
MR		 13609 DRM_PLANE_HELPER_NO_SCALING,
13610 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13611 true, true, &state->visible);
757f9a3e
GP		 13612 if (ret)
13613 return ret;
13614
757f9a3e
GP		 13615 /* if we want to turn off the cursor ignore width and height */
13616 if (!obj)
da20eabd 13617 return 0;
757f9a3e 13618
757f9a3e 13619 /* Check for which cursor types we support */
061e4b8d 13620 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13621 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13622 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13623 return -EINVAL;
13624 }
13625
ea2c67bb
MR		 13626 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13627 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13628 DRM_DEBUG_KMS("buffer is too small\n");
13629 return -ENOMEM;
13630 }
13631
3a656b54 13632 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13633 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13634 return -EINVAL;
32b7eeec
MR		 13635 }
13636
da20eabd 13637 return 0;
852e787c 13638}
3d7d6510 13639
a8ad0d8e
ML		 13640static void
13641intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13642 struct drm_crtc *crtc)
a8ad0d8e 13643{
a8ad0d8e
ML		 13644 intel_crtc_update_cursor(crtc, false);
13645}
13646
f4a2cf29 13647static void
852e787c
GP		 13648intel_commit_cursor_plane(struct drm_plane *plane,
13649 struct intel_plane_state *state)
13650{
2b875c22 13651 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13652 struct drm_device *dev = plane->dev;
13653 struct intel_crtc *intel_crtc;
2b875c22 13654 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13655 uint32_t addr;
852e787c 13656
ea2c67bb
MR		 13657 crtc = crtc ? crtc : plane->crtc;
13658 intel_crtc = to_intel_crtc(crtc);
13659
2b875c22 13660 plane->fb = state->base.fb;
ea2c67bb
MR		 13661 crtc->cursor_x = state->base.crtc_x;
13662 crtc->cursor_y = state->base.crtc_y;
13663
a912f12f
GP		 13664 if (intel_crtc->cursor_bo == obj)
13665 goto update;
4ed91096 13666
f4a2cf29 13667 if (!obj)
a912f12f 13668 addr = 0;
f4a2cf29 13669 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13670 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13671 else
a912f12f 13672 addr = obj->phys_handle->busaddr;
852e787c 13673
a912f12f
GP		 13674 intel_crtc->cursor_addr = addr;
13675 intel_crtc->cursor_bo = obj;
852e787c 13676
302d19ac 13677update:
a539205a 13678 if (crtc->state->active)
a912f12f 13679 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13680}
13681
3d7d6510
MR		 13682static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13683 int pipe)
13684{
13685 struct intel_plane *cursor;
8e7d688b 13686 struct intel_plane_state *state;
3d7d6510
MR		 13687
13688 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13689 if (cursor == NULL)
13690 return NULL;
13691
8e7d688b
MR		 13692 state = intel_create_plane_state(&cursor->base);
13693 if (!state) {
ea2c67bb
MR		 13694 kfree(cursor);
13695 return NULL;
13696 }
8e7d688b 13697 cursor->base.state = &state->base;
ea2c67bb 13698
3d7d6510
MR		 13699 cursor->can_scale = false;
13700 cursor->max_downscale = 1;
13701 cursor->pipe = pipe;
13702 cursor->plane = pipe;
a9ff8714 13703 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13704 cursor->check_plane = intel_check_cursor_plane;
13705 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13706 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13707
13708 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13709 &intel_plane_funcs,
3d7d6510
MR		 13710 intel_cursor_formats,
13711 ARRAY_SIZE(intel_cursor_formats),
13712 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13713
13714 if (INTEL_INFO(dev)->gen >= 4) {
13715 if (!dev->mode_config.rotation_property)
13716 dev->mode_config.rotation_property =
13717 drm_mode_create_rotation_property(dev,
13718 BIT(DRM_ROTATE_0) |
13719 BIT(DRM_ROTATE_180));
13720 if (dev->mode_config.rotation_property)
13721 drm_object_attach_property(&cursor->base.base,
13722 dev->mode_config.rotation_property,
8e7d688b 13723 state->base.rotation);
4398ad45
VS		 13724 }
13725
af99ceda
CK		 13726 if (INTEL_INFO(dev)->gen >=9)
13727 state->scaler_id = -1;
13728
ea2c67bb
MR		 13729 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13730
3d7d6510
MR		 13731 return &cursor->base;
13732}
13733
549e2bfb
CK		 13734static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13735 struct intel_crtc_state *crtc_state)
13736{
13737 int i;
13738 struct intel_scaler *intel_scaler;
13739 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13740
13741 for (i = 0; i < intel_crtc->num_scalers; i++) {
13742 intel_scaler = &scaler_state->scalers[i];
13743 intel_scaler->in_use = 0;
549e2bfb
CK		 13744 intel_scaler->mode = PS_SCALER_MODE_DYN;
13745 }
13746
13747 scaler_state->scaler_id = -1;
13748}
13749
b358d0a6 13750static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13751{
fbee40df 13752 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13753 struct intel_crtc *intel_crtc;
f5de6e07 13754 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13755 struct drm_plane *primary = NULL;
13756 struct drm_plane *cursor = NULL;
465c120c 13757 int i, ret;
79e53945 13758
955382f3 13759 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13760 if (intel_crtc == NULL)
13761 return;
13762
f5de6e07
ACO		 13763 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13764 if (!crtc_state)
13765 goto fail;
550acefd
ACO		 13766 intel_crtc->config = crtc_state;
13767 intel_crtc->base.state = &crtc_state->base;
07878248 13768 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13769
549e2bfb
CK		 13770 /* initialize shared scalers */
13771 if (INTEL_INFO(dev)->gen >= 9) {
13772 if (pipe == PIPE_C)
13773 intel_crtc->num_scalers = 1;
13774 else
13775 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13776
13777 skl_init_scalers(dev, intel_crtc, crtc_state);
13778 }
13779
465c120c 13780 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13781 if (!primary)
13782 goto fail;
13783
13784 cursor = intel_cursor_plane_create(dev, pipe);
13785 if (!cursor)
13786 goto fail;
13787
465c120c 13788 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13789 cursor, &intel_crtc_funcs);
13790 if (ret)
13791 goto fail;
79e53945
JB		 13792
13793 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13794 for (i = 0; i < 256; i++) {
13795 intel_crtc->lut_r[i] = i;
13796 intel_crtc->lut_g[i] = i;
13797 intel_crtc->lut_b[i] = i;
13798 }
13799
1f1c2e24
VS		 13800 /*
13801 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13802 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13803 */
80824003
JB		 13804 intel_crtc->pipe = pipe;
13805 intel_crtc->plane = pipe;
3a77c4c4 13806 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13807 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13808 intel_crtc->plane = !pipe;
80824003
JB		 13809 }
13810
4b0e333e
CW		 13811 intel_crtc->cursor_base = ~0;
13812 intel_crtc->cursor_cntl = ~0;
dc41c154 13813 intel_crtc->cursor_size = ~0;
8d7849db 13814
852eb00d
VS		 13815 intel_crtc->wm.cxsr_allowed = true;
13816
22fd0fab
JB		 13817 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13818 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13819 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13820 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13821
79e53945 13822 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13823
13824 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13825 return;
13826
13827fail:
13828 if (primary)
13829 drm_plane_cleanup(primary);
13830 if (cursor)
13831 drm_plane_cleanup(cursor);
f5de6e07 13832 kfree(crtc_state);
3d7d6510 13833 kfree(intel_crtc);
79e53945
JB		 13834}
13835
752aa88a
JB		 13836enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13837{
13838 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13839 struct drm_device *dev = connector->base.dev;
752aa88a 13840
51fd371b 13841 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13842
d3babd3f 13843 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13844 return INVALID_PIPE;
13845
13846 return to_intel_crtc(encoder->crtc)->pipe;
13847}
13848
08d7b3d1 13849int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13850 struct drm_file *file)
08d7b3d1 13851{
08d7b3d1 13852 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13853 struct drm_crtc *drmmode_crtc;
c05422d5 13854 struct intel_crtc *crtc;
08d7b3d1 13855
7707e653 13856 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13857
7707e653 13858 if (!drmmode_crtc) {
08d7b3d1 13859 DRM_ERROR("no such CRTC id\n");
3f2c2057 13860 return -ENOENT;
08d7b3d1
CW		 13861 }
13862
7707e653 13863 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13864 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13865
c05422d5 13866 return 0;
08d7b3d1
CW		 13867}
13868
66a9278e 13869static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13870{
66a9278e
DV		 13871 struct drm_device *dev = encoder->base.dev;
13872 struct intel_encoder *source_encoder;
79e53945 13873 int index_mask = 0;
79e53945
JB		 13874 int entry = 0;
13875
b2784e15 13876 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13877 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13878 index_mask |= (1 << entry);
13879
79e53945
JB		 13880 entry++;
13881 }
4ef69c7a 13882
79e53945
JB		 13883 return index_mask;
13884}
13885
4d302442
CW		 13886static bool has_edp_a(struct drm_device *dev)
13887{
13888 struct drm_i915_private *dev_priv = dev->dev_private;
13889
13890 if (!IS_MOBILE(dev))
13891 return false;
13892
13893 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13894 return false;
13895
e3589908 13896 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13897 return false;
13898
13899 return true;
13900}
13901
84b4e042
JB		 13902static bool intel_crt_present(struct drm_device *dev)
13903{
13904 struct drm_i915_private *dev_priv = dev->dev_private;
13905
884497ed
DL		 13906 if (INTEL_INFO(dev)->gen >= 9)
13907 return false;
13908
cf404ce4 13909 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13910 return false;
13911
13912 if (IS_CHERRYVIEW(dev))
13913 return false;
13914
13915 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13916 return false;
13917
13918 return true;
13919}
13920
79e53945
JB		 13921static void intel_setup_outputs(struct drm_device *dev)
13922{
725e30ad 13923 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13924 struct intel_encoder *encoder;
cb0953d7 13925 bool dpd_is_edp = false;
79e53945 13926
c9093354 13927 intel_lvds_init(dev);
79e53945 13928
84b4e042 13929 if (intel_crt_present(dev))
79935fca 13930 intel_crt_init(dev);
cb0953d7 13931
c776eb2e
VK		 13932 if (IS_BROXTON(dev)) {
13933 /*
13934 * FIXME: Broxton doesn't support port detection via the
13935 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13936 * detect the ports.
13937 */
13938 intel_ddi_init(dev, PORT_A);
13939 intel_ddi_init(dev, PORT_B);
13940 intel_ddi_init(dev, PORT_C);
13941 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13942 int found;
13943
de31facd
JB		 13944 /*
13945 * Haswell uses DDI functions to detect digital outputs.
13946 * On SKL pre-D0 the strap isn't connected, so we assume
13947 * it's there.
13948 */
0e72a5b5 13949 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13950 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13951 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13952 intel_ddi_init(dev, PORT_A);
13953
13954 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13955 * register */
13956 found = I915_READ(SFUSE_STRAP);
13957
13958 if (found & SFUSE_STRAP_DDIB_DETECTED)
13959 intel_ddi_init(dev, PORT_B);
13960 if (found & SFUSE_STRAP_DDIC_DETECTED)
13961 intel_ddi_init(dev, PORT_C);
13962 if (found & SFUSE_STRAP_DDID_DETECTED)
13963 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 13964 /*
13965 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13966 */
13967 if (IS_SKYLAKE(dev) &&
13968 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13969 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13970 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13971 intel_ddi_init(dev, PORT_E);
13972
0e72a5b5 13973 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13974 int found;
5d8a7752 13975 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13976
13977 if (has_edp_a(dev))
13978 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13979
dc0fa718 13980 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13981 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13982 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13983 if (!found)
e2debe91 13984 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13985 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13986 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13987 }
13988
dc0fa718 13989 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13990 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13991
dc0fa718 13992 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13993 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13994
5eb08b69 13995 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13996 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13997
270b3042 13998 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13999 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14000 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14001 /*
14002 * The DP_DETECTED bit is the latched state of the DDC
14003 * SDA pin at boot. However since eDP doesn't require DDC
14004 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14005 * eDP ports may have been muxed to an alternate function.
14006 * Thus we can't rely on the DP_DETECTED bit alone to detect
14007 * eDP ports. Consult the VBT as well as DP_DETECTED to
14008 * detect eDP ports.
14009 */
d2182a66
VS		 14010 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14011 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14012 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14013 PORT_B);
e17ac6db
VS		 14014 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14015 intel_dp_is_edp(dev, PORT_B))
14016 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14017
d2182a66
VS		 14018 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14019 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14020 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14021 PORT_C);
e17ac6db
VS		 14022 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14023 intel_dp_is_edp(dev, PORT_C))
14024 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14025
9418c1f1 14026 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14027 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14028 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14029 PORT_D);
e17ac6db
VS		 14030 /* eDP not supported on port D, so don't check VBT */
14031 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14032 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14033 }
14034
3cfca973 14035 intel_dsi_init(dev);
09da55dc 14036 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14037 bool found = false;
7d57382e 14038
e2debe91 14039 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14040 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14041 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14042 if (!found && IS_G4X(dev)) {
b01f2c3a 14043 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14044 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14045 }
27185ae1 14046
3fec3d2f 14047 if (!found && IS_G4X(dev))
ab9d7c30 14048 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14049 }
13520b05
KH		 14050
14051 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14052
e2debe91 14053 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14054 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14055 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14056 }
27185ae1 14057
e2debe91 14058 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14059
3fec3d2f 14060 if (IS_G4X(dev)) {
b01f2c3a 14061 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14062 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14063 }
3fec3d2f 14064 if (IS_G4X(dev))
ab9d7c30 14065 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14066 }
27185ae1 14067
3fec3d2f 14068 if (IS_G4X(dev) &&
e7281eab 14069 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14070 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14071 } else if (IS_GEN2(dev))
79e53945
JB		 14072 intel_dvo_init(dev);
14073
103a196f 14074 if (SUPPORTS_TV(dev))
79e53945
JB		 14075 intel_tv_init(dev);
14076
0bc12bcb 14077 intel_psr_init(dev);
7c8f8a70 14078
b2784e15 14079 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14080 encoder->base.possible_crtcs = encoder->crtc_mask;
14081 encoder->base.possible_clones =
66a9278e 14082 intel_encoder_clones(encoder);
79e53945 14083 }
47356eb6 14084
dde86e2d 14085 intel_init_pch_refclk(dev);
270b3042
DV		 14086
14087 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14088}
14089
14090static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14091{
60a5ca01 14092 struct drm_device *dev = fb->dev;
79e53945 14093 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14094
ef2d633e 14095 drm_framebuffer_cleanup(fb);
60a5ca01 14096 mutex_lock(&dev->struct_mutex);
ef2d633e 14097 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14098 drm_gem_object_unreference(&intel_fb->obj->base);
14099 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14100 kfree(intel_fb);
14101}
14102
14103static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14104 struct drm_file *file,
79e53945
JB		 14105 unsigned int *handle)
14106{
14107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14108 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14109
05394f39 14110 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14111}
14112
86c98588
RV		 14113static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14114 struct drm_file *file,
14115 unsigned flags, unsigned color,
14116 struct drm_clip_rect *clips,
14117 unsigned num_clips)
14118{
14119 struct drm_device *dev = fb->dev;
14120 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14121 struct drm_i915_gem_object *obj = intel_fb->obj;
14122
14123 mutex_lock(&dev->struct_mutex);
74b4ea1e 14124 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14125 mutex_unlock(&dev->struct_mutex);
14126
14127 return 0;
14128}
14129
79e53945
JB		 14130static const struct drm_framebuffer_funcs intel_fb_funcs = {
14131 .destroy = intel_user_framebuffer_destroy,
14132 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14133 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14134};
14135
b321803d
DL		 14136static
14137u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14138 uint32_t pixel_format)
14139{
14140 u32 gen = INTEL_INFO(dev)->gen;
14141
14142 if (gen >= 9) {
14143 /* "The stride in bytes must not exceed the of the size of 8K
14144 * pixels and 32K bytes."
14145 */
14146 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14147 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14148 return 32*1024;
14149 } else if (gen >= 4) {
14150 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14151 return 16*1024;
14152 else
14153 return 32*1024;
14154 } else if (gen >= 3) {
14155 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14156 return 8*1024;
14157 else
14158 return 16*1024;
14159 } else {
14160 /* XXX DSPC is limited to 4k tiled */
14161 return 8*1024;
14162 }
14163}
14164
b5ea642a
DV		 14165static int intel_framebuffer_init(struct drm_device *dev,
14166 struct intel_framebuffer *intel_fb,
14167 struct drm_mode_fb_cmd2 *mode_cmd,
14168 struct drm_i915_gem_object *obj)
79e53945 14169{
6761dd31 14170 unsigned int aligned_height;
79e53945 14171 int ret;
b321803d 14172 u32 pitch_limit, stride_alignment;
79e53945 14173
dd4916c5
DV		 14174 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14175
2a80eada
DV		 14176 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14177 /* Enforce that fb modifier and tiling mode match, but only for
14178 * X-tiled. This is needed for FBC. */
14179 if (!!(obj->tiling_mode == I915_TILING_X) !=
14180 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14181 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14182 return -EINVAL;
14183 }
14184 } else {
14185 if (obj->tiling_mode == I915_TILING_X)
14186 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14187 else if (obj->tiling_mode == I915_TILING_Y) {
14188 DRM_DEBUG("No Y tiling for legacy addfb\n");
14189 return -EINVAL;
14190 }
14191 }
14192
9a8f0a12
TU		 14193 /* Passed in modifier sanity checking. */
14194 switch (mode_cmd->modifier[0]) {
14195 case I915_FORMAT_MOD_Y_TILED:
14196 case I915_FORMAT_MOD_Yf_TILED:
14197 if (INTEL_INFO(dev)->gen < 9) {
14198 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14199 mode_cmd->modifier[0]);
14200 return -EINVAL;
14201 }
14202 case DRM_FORMAT_MOD_NONE:
14203 case I915_FORMAT_MOD_X_TILED:
14204 break;
14205 default:
c0f40428
JB		 14206 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14207 mode_cmd->modifier[0]);
57cd6508 14208 return -EINVAL;
c16ed4be 14209 }
57cd6508 14210
b321803d
DL		 14211 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14212 mode_cmd->pixel_format);
14213 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14214 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14215 mode_cmd->pitches[0], stride_alignment);
57cd6508 14216 return -EINVAL;
c16ed4be 14217 }
57cd6508 14218
b321803d
DL		 14219 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14220 mode_cmd->pixel_format);
a35cdaa0 14221 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14222 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14223 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14224 "tiled" : "linear",
a35cdaa0 14225 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14226 return -EINVAL;
c16ed4be 14227 }
5d7bd705 14228
2a80eada 14229 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14230 mode_cmd->pitches[0] != obj->stride) {
14231 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14232 mode_cmd->pitches[0], obj->stride);
5d7bd705 14233 return -EINVAL;
c16ed4be 14234 }
5d7bd705 14235
57779d06 14236 /* Reject formats not supported by any plane early. */
308e5bcb 14237 switch (mode_cmd->pixel_format) {
57779d06 14238 case DRM_FORMAT_C8:
04b3924d
VS		 14239 case DRM_FORMAT_RGB565:
14240 case DRM_FORMAT_XRGB8888:
14241 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14242 break;
14243 case DRM_FORMAT_XRGB1555:
c16ed4be 14244 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14245 DRM_DEBUG("unsupported pixel format: %s\n",
14246 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14247 return -EINVAL;
c16ed4be 14248 }
57779d06 14249 break;
57779d06 14250 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14251 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14252 DRM_DEBUG("unsupported pixel format: %s\n",
14253 drm_get_format_name(mode_cmd->pixel_format));
14254 return -EINVAL;
14255 }
14256 break;
14257 case DRM_FORMAT_XBGR8888:
04b3924d 14258 case DRM_FORMAT_XRGB2101010:
57779d06 14259 case DRM_FORMAT_XBGR2101010:
c16ed4be 14260 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14261 DRM_DEBUG("unsupported pixel format: %s\n",
14262 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14263 return -EINVAL;
c16ed4be 14264 }
b5626747 14265 break;
7531208b
DL		 14266 case DRM_FORMAT_ABGR2101010:
14267 if (!IS_VALLEYVIEW(dev)) {
14268 DRM_DEBUG("unsupported pixel format: %s\n",
14269 drm_get_format_name(mode_cmd->pixel_format));
14270 return -EINVAL;
14271 }
14272 break;
04b3924d
VS		 14273 case DRM_FORMAT_YUYV:
14274 case DRM_FORMAT_UYVY:
14275 case DRM_FORMAT_YVYU:
14276 case DRM_FORMAT_VYUY:
c16ed4be 14277 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14278 DRM_DEBUG("unsupported pixel format: %s\n",
14279 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14280 return -EINVAL;
c16ed4be 14281 }
57cd6508
CW		 14282 break;
14283 default:
4ee62c76
VS		 14284 DRM_DEBUG("unsupported pixel format: %s\n",
14285 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14286 return -EINVAL;
14287 }
14288
90f9a336
VS		 14289 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14290 if (mode_cmd->offsets[0] != 0)
14291 return -EINVAL;
14292
ec2c981e 14293 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14294 mode_cmd->pixel_format,
14295 mode_cmd->modifier[0]);
53155c0a
DV		 14296 /* FIXME drm helper for size checks (especially planar formats)? */
14297 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14298 return -EINVAL;
14299
c7d73f6a
DV		 14300 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14301 intel_fb->obj = obj;
80075d49 14302 intel_fb->obj->framebuffer_references++;
c7d73f6a 14303
79e53945
JB		 14304 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14305 if (ret) {
14306 DRM_ERROR("framebuffer init failed %d\n", ret);
14307 return ret;
14308 }
14309
79e53945
JB		 14310 return 0;
14311}
14312
79e53945
JB		 14313static struct drm_framebuffer *
14314intel_user_framebuffer_create(struct drm_device *dev,
14315 struct drm_file *filp,
308e5bcb 14316 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14317{
05394f39 14318 struct drm_i915_gem_object *obj;
79e53945 14319
308e5bcb
JB		 14320 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14321 mode_cmd->handles[0]));
c8725226 14322 if (&obj->base == NULL)
cce13ff7 14323 return ERR_PTR(-ENOENT);
79e53945 14324
d2dff872 14325 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14326}
14327
0695726e 14328#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14329static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14330{
14331}
14332#endif
14333
79e53945 14334static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14335 .fb_create = intel_user_framebuffer_create,
0632fef6 14336 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14337 .atomic_check = intel_atomic_check,
14338 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14339 .atomic_state_alloc = intel_atomic_state_alloc,
14340 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14341};
14342
e70236a8
JB		 14343/* Set up chip specific display functions */
14344static void intel_init_display(struct drm_device *dev)
14345{
14346 struct drm_i915_private *dev_priv = dev->dev_private;
14347
ee9300bb
DV		 14348 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14349 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14350 else if (IS_CHERRYVIEW(dev))
14351 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14352 else if (IS_VALLEYVIEW(dev))
14353 dev_priv->display.find_dpll = vlv_find_best_dpll;
14354 else if (IS_PINEVIEW(dev))
14355 dev_priv->display.find_dpll = pnv_find_best_dpll;
14356 else
14357 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14358
bc8d7dff
DL		 14359 if (INTEL_INFO(dev)->gen >= 9) {
14360 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14361 dev_priv->display.get_initial_plane_config =
14362 skylake_get_initial_plane_config;
bc8d7dff
DL		 14363 dev_priv->display.crtc_compute_clock =
14364 haswell_crtc_compute_clock;
14365 dev_priv->display.crtc_enable = haswell_crtc_enable;
14366 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14367 dev_priv->display.update_primary_plane =
14368 skylake_update_primary_plane;
14369 } else if (HAS_DDI(dev)) {
0e8ffe1b 14370 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14371 dev_priv->display.get_initial_plane_config =
14372 ironlake_get_initial_plane_config;
797d0259
ACO		 14373 dev_priv->display.crtc_compute_clock =
14374 haswell_crtc_compute_clock;
4f771f10
PZ		 14375 dev_priv->display.crtc_enable = haswell_crtc_enable;
14376 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14377 dev_priv->display.update_primary_plane =
14378 ironlake_update_primary_plane;
09b4ddf9 14379 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14380 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14381 dev_priv->display.get_initial_plane_config =
14382 ironlake_get_initial_plane_config;
3fb37703
ACO		 14383 dev_priv->display.crtc_compute_clock =
14384 ironlake_crtc_compute_clock;
76e5a89c
DV		 14385 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14386 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14387 dev_priv->display.update_primary_plane =
14388 ironlake_update_primary_plane;
89b667f8
JB		 14389 } else if (IS_VALLEYVIEW(dev)) {
14390 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14391 dev_priv->display.get_initial_plane_config =
14392 i9xx_get_initial_plane_config;
d6dfee7a 14393 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14394 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14395 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14396 dev_priv->display.update_primary_plane =
14397 i9xx_update_primary_plane;
f564048e 14398 } else {
0e8ffe1b 14399 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14400 dev_priv->display.get_initial_plane_config =
14401 i9xx_get_initial_plane_config;
d6dfee7a 14402 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14403 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14404 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14405 dev_priv->display.update_primary_plane =
14406 i9xx_update_primary_plane;
f564048e 14407 }
e70236a8 14408
e70236a8 14409 /* Returns the core display clock speed */
1652d19e
VS		 14410 if (IS_SKYLAKE(dev))
14411 dev_priv->display.get_display_clock_speed =
14412 skylake_get_display_clock_speed;
acd3f3d3
BP		 14413 else if (IS_BROXTON(dev))
14414 dev_priv->display.get_display_clock_speed =
14415 broxton_get_display_clock_speed;
1652d19e
VS		 14416 else if (IS_BROADWELL(dev))
14417 dev_priv->display.get_display_clock_speed =
14418 broadwell_get_display_clock_speed;
14419 else if (IS_HASWELL(dev))
14420 dev_priv->display.get_display_clock_speed =
14421 haswell_get_display_clock_speed;
14422 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14423 dev_priv->display.get_display_clock_speed =
14424 valleyview_get_display_clock_speed;
b37a6434
VS		 14425 else if (IS_GEN5(dev))
14426 dev_priv->display.get_display_clock_speed =
14427 ilk_get_display_clock_speed;
a7c66cd8 14428 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14429 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14430 dev_priv->display.get_display_clock_speed =
14431 i945_get_display_clock_speed;
34edce2f
VS		 14432 else if (IS_GM45(dev))
14433 dev_priv->display.get_display_clock_speed =
14434 gm45_get_display_clock_speed;
14435 else if (IS_CRESTLINE(dev))
14436 dev_priv->display.get_display_clock_speed =
14437 i965gm_get_display_clock_speed;
14438 else if (IS_PINEVIEW(dev))
14439 dev_priv->display.get_display_clock_speed =
14440 pnv_get_display_clock_speed;
14441 else if (IS_G33(dev) || IS_G4X(dev))
14442 dev_priv->display.get_display_clock_speed =
14443 g33_get_display_clock_speed;
e70236a8
JB		 14444 else if (IS_I915G(dev))
14445 dev_priv->display.get_display_clock_speed =
14446 i915_get_display_clock_speed;
257a7ffc 14447 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14448 dev_priv->display.get_display_clock_speed =
14449 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14450 else if (IS_PINEVIEW(dev))
14451 dev_priv->display.get_display_clock_speed =
14452 pnv_get_display_clock_speed;
e70236a8
JB		 14453 else if (IS_I915GM(dev))
14454 dev_priv->display.get_display_clock_speed =
14455 i915gm_get_display_clock_speed;
14456 else if (IS_I865G(dev))
14457 dev_priv->display.get_display_clock_speed =
14458 i865_get_display_clock_speed;
f0f8a9ce 14459 else if (IS_I85X(dev))
e70236a8 14460 dev_priv->display.get_display_clock_speed =
1b1d2716 14461 i85x_get_display_clock_speed;
623e01e5
VS		 14462 else { /* 830 */
14463 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14464 dev_priv->display.get_display_clock_speed =
14465 i830_get_display_clock_speed;
623e01e5 14466 }
e70236a8 14467
7c10a2b5 14468 if (IS_GEN5(dev)) {
3bb11b53 14469 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14470 } else if (IS_GEN6(dev)) {
14471 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14472 } else if (IS_IVYBRIDGE(dev)) {
14473 /* FIXME: detect B0+ stepping and use auto training */
14474 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14475 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14476 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14477 if (IS_BROADWELL(dev)) {
14478 dev_priv->display.modeset_commit_cdclk =
14479 broadwell_modeset_commit_cdclk;
14480 dev_priv->display.modeset_calc_cdclk =
14481 broadwell_modeset_calc_cdclk;
14482 }
30a970c6 14483 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14484 dev_priv->display.modeset_commit_cdclk =
14485 valleyview_modeset_commit_cdclk;
14486 dev_priv->display.modeset_calc_cdclk =
14487 valleyview_modeset_calc_cdclk;
f8437dd1 14488 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14489 dev_priv->display.modeset_commit_cdclk =
14490 broxton_modeset_commit_cdclk;
14491 dev_priv->display.modeset_calc_cdclk =
14492 broxton_modeset_calc_cdclk;
e70236a8 14493 }
8c9f3aaf 14494
8c9f3aaf
JB		 14495 switch (INTEL_INFO(dev)->gen) {
14496 case 2:
14497 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14498 break;
14499
14500 case 3:
14501 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14502 break;
14503
14504 case 4:
14505 case 5:
14506 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14507 break;
14508
14509 case 6:
14510 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14511 break;
7c9017e5 14512 case 7:
4e0bbc31 14513 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14514 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14515 break;
830c81db 14516 case 9:
ba343e02
TU		 14517 /* Drop through - unsupported since execlist only. */
14518 default:
14519 /* Default just returns -ENODEV to indicate unsupported */
14520 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14521 }
7bd688cd
JN		 14522
14523 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14524
14525 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14526}
14527
b690e96c
JB		 14528/*
14529 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14530 * resume, or other times. This quirk makes sure that's the case for
14531 * affected systems.
14532 */
0206e353 14533static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14534{
14535 struct drm_i915_private *dev_priv = dev->dev_private;
14536
14537 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14538 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14539}
14540
b6b5d049
VS		 14541static void quirk_pipeb_force(struct drm_device *dev)
14542{
14543 struct drm_i915_private *dev_priv = dev->dev_private;
14544
14545 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14546 DRM_INFO("applying pipe b force quirk\n");
14547}
14548
435793df
KP		 14549/*
14550 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14551 */
14552static void quirk_ssc_force_disable(struct drm_device *dev)
14553{
14554 struct drm_i915_private *dev_priv = dev->dev_private;
14555 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14556 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14557}
14558
4dca20ef 14559/*
5a15ab5b
CE		 14560 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14561 * brightness value
4dca20ef
CE		 14562 */
14563static void quirk_invert_brightness(struct drm_device *dev)
14564{
14565 struct drm_i915_private *dev_priv = dev->dev_private;
14566 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14567 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14568}
14569
9c72cc6f
SD		 14570/* Some VBT's incorrectly indicate no backlight is present */
14571static void quirk_backlight_present(struct drm_device *dev)
14572{
14573 struct drm_i915_private *dev_priv = dev->dev_private;
14574 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14575 DRM_INFO("applying backlight present quirk\n");
14576}
14577
b690e96c
JB		 14578struct intel_quirk {
14579 int device;
14580 int subsystem_vendor;
14581 int subsystem_device;
14582 void (*hook)(struct drm_device *dev);
14583};
14584
5f85f176
EE		 14585/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14586struct intel_dmi_quirk {
14587 void (*hook)(struct drm_device *dev);
14588 const struct dmi_system_id (*dmi_id_list)[];
14589};
14590
14591static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14592{
14593 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14594 return 1;
14595}
14596
14597static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14598 {
14599 .dmi_id_list = &(const struct dmi_system_id[]) {
14600 {
14601 .callback = intel_dmi_reverse_brightness,
14602 .ident = "NCR Corporation",
14603 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14604 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14605 },
14606 },
14607 { } /* terminating entry */
14608 },
14609 .hook = quirk_invert_brightness,
14610 },
14611};
14612
c43b5634 14613static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14614 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14615 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14616
b690e96c
JB		 14617 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14618 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14619
5f080c0f
VS		 14620 /* 830 needs to leave pipe A & dpll A up */
14621 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14622
b6b5d049
VS		 14623 /* 830 needs to leave pipe B & dpll B up */
14624 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14625
435793df
KP		 14626 /* Lenovo U160 cannot use SSC on LVDS */
14627 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14628
14629 /* Sony Vaio Y cannot use SSC on LVDS */
14630 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14631
be505f64
AH		 14632 /* Acer Aspire 5734Z must invert backlight brightness */
14633 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14634
14635 /* Acer/eMachines G725 */
14636 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14637
14638 /* Acer/eMachines e725 */
14639 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14640
14641 /* Acer/Packard Bell NCL20 */
14642 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14643
14644 /* Acer Aspire 4736Z */
14645 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14646
14647 /* Acer Aspire 5336 */
14648 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14649
14650 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14651 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14652
dfb3d47b
SD		 14653 /* Acer C720 Chromebook (Core i3 4005U) */
14654 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14655
b2a9601c 14656 /* Apple Macbook 2,1 (Core 2 T7400) */
14657 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14658
d4967d8c
SD		 14659 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14660 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14661
14662 /* HP Chromebook 14 (Celeron 2955U) */
14663 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14664
14665 /* Dell Chromebook 11 */
14666 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14667};
14668
14669static void intel_init_quirks(struct drm_device *dev)
14670{
14671 struct pci_dev *d = dev->pdev;
14672 int i;
14673
14674 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14675 struct intel_quirk *q = &intel_quirks[i];
14676
14677 if (d->device == q->device &&
14678 (d->subsystem_vendor == q->subsystem_vendor ||
14679 q->subsystem_vendor == PCI_ANY_ID) &&
14680 (d->subsystem_device == q->subsystem_device ||
14681 q->subsystem_device == PCI_ANY_ID))
14682 q->hook(dev);
14683 }
5f85f176
EE		 14684 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14685 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14686 intel_dmi_quirks[i].hook(dev);
14687 }
b690e96c
JB		 14688}
14689
9cce37f4
JB		 14690/* Disable the VGA plane that we never use */
14691static void i915_disable_vga(struct drm_device *dev)
14692{
14693 struct drm_i915_private *dev_priv = dev->dev_private;
14694 u8 sr1;
766aa1c4 14695 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14696
2b37c616 14697 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14698 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14699 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14700 sr1 = inb(VGA_SR_DATA);
14701 outb(sr1 | 1<<5, VGA_SR_DATA);
14702 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14703 udelay(300);
14704
01f5a626 14705 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14706 POSTING_READ(vga_reg);
14707}
14708
f817586c
DV		 14709void intel_modeset_init_hw(struct drm_device *dev)
14710{
b6283055 14711 intel_update_cdclk(dev);
a8f78b58 14712 intel_prepare_ddi(dev);
f817586c 14713 intel_init_clock_gating(dev);
8090c6b9 14714 intel_enable_gt_powersave(dev);
f817586c
DV		 14715}
14716
79e53945
JB		 14717void intel_modeset_init(struct drm_device *dev)
14718{
652c393a 14719 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14720 int sprite, ret;
8cc87b75 14721 enum pipe pipe;
46f297fb 14722 struct intel_crtc *crtc;
79e53945
JB		 14723
14724 drm_mode_config_init(dev);
14725
14726 dev->mode_config.min_width = 0;
14727 dev->mode_config.min_height = 0;
14728
019d96cb
DA		 14729 dev->mode_config.preferred_depth = 24;
14730 dev->mode_config.prefer_shadow = 1;
14731
25bab385
TU		 14732 dev->mode_config.allow_fb_modifiers = true;
14733
e6ecefaa 14734 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14735
b690e96c
JB		 14736 intel_init_quirks(dev);
14737
1fa61106
ED		 14738 intel_init_pm(dev);
14739
e3c74757
BW		 14740 if (INTEL_INFO(dev)->num_pipes == 0)
14741 return;
14742
e70236a8 14743 intel_init_display(dev);
7c10a2b5 14744 intel_init_audio(dev);
e70236a8 14745
a6c45cf0
CW		 14746 if (IS_GEN2(dev)) {
14747 dev->mode_config.max_width = 2048;
14748 dev->mode_config.max_height = 2048;
14749 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14750 dev->mode_config.max_width = 4096;
14751 dev->mode_config.max_height = 4096;
79e53945 14752 } else {
a6c45cf0
CW		 14753 dev->mode_config.max_width = 8192;
14754 dev->mode_config.max_height = 8192;
79e53945 14755 }
068be561 14756
dc41c154
VS		 14757 if (IS_845G(dev) || IS_I865G(dev)) {
14758 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14759 dev->mode_config.cursor_height = 1023;
14760 } else if (IS_GEN2(dev)) {
068be561
DL		 14761 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14762 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14763 } else {
14764 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14765 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14766 }
14767
5d4545ae 14768 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14769
28c97730 14770 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14771 INTEL_INFO(dev)->num_pipes,
14772 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14773
055e393f 14774 for_each_pipe(dev_priv, pipe) {
8cc87b75 14775 intel_crtc_init(dev, pipe);
3bdcfc0c 14776 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14777 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14778 if (ret)
06da8da2 14779 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14780 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14781 }
79e53945
JB		 14782 }
14783
f42bb70d
JB		 14784 intel_init_dpio(dev);
14785
e72f9fbf 14786 intel_shared_dpll_init(dev);
ee7b9f93 14787
9cce37f4
JB		 14788 /* Just disable it once at startup */
14789 i915_disable_vga(dev);
79e53945 14790 intel_setup_outputs(dev);
11be49eb
CW		 14791
14792 /* Just in case the BIOS is doing something questionable. */
7733b49b 14793 intel_fbc_disable(dev_priv);
fa9fa083 14794
6e9f798d 14795 drm_modeset_lock_all(dev);
043e9bda 14796 intel_modeset_setup_hw_state(dev);
6e9f798d 14797 drm_modeset_unlock_all(dev);
46f297fb 14798
d3fcc808 14799 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14800 struct intel_initial_plane_config plane_config = {};
14801
46f297fb
JB		 14802 if (!crtc->active)
14803 continue;
14804
46f297fb 14805 /*
46f297fb
JB		 14806 * Note that reserving the BIOS fb up front prevents us
14807 * from stuffing other stolen allocations like the ring
14808 * on top. This prevents some ugliness at boot time, and
14809 * can even allow for smooth boot transitions if the BIOS
14810 * fb is large enough for the active pipe configuration.
14811 */
eeebeac5
ML		 14812 dev_priv->display.get_initial_plane_config(crtc,
14813 &plane_config);
14814
14815 /*
14816 * If the fb is shared between multiple heads, we'll
14817 * just get the first one.
14818 */
14819 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14820 }
2c7111db
CW		 14821}
14822
7fad798e
DV		 14823static void intel_enable_pipe_a(struct drm_device *dev)
14824{
14825 struct intel_connector *connector;
14826 struct drm_connector *crt = NULL;
14827 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14828 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14829
14830 /* We can't just switch on the pipe A, we need to set things up with a
14831 * proper mode and output configuration. As a gross hack, enable pipe A
14832 * by enabling the load detect pipe once. */
3a3371ff 14833 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14834 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14835 crt = &connector->base;
14836 break;
14837 }
14838 }
14839
14840 if (!crt)
14841 return;
14842
208bf9fd 14843 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14844 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14845}
14846
fa555837
DV		 14847static bool
14848intel_check_plane_mapping(struct intel_crtc *crtc)
14849{
7eb552ae
BW		 14850 struct drm_device *dev = crtc->base.dev;
14851 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14852 u32 reg, val;
14853
7eb552ae 14854 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14855 return true;
14856
14857 reg = DSPCNTR(!crtc->plane);
14858 val = I915_READ(reg);
14859
14860 if ((val & DISPLAY_PLANE_ENABLE) &&
14861 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14862 return false;
14863
14864 return true;
14865}
14866
24929352
DV		 14867static void intel_sanitize_crtc(struct intel_crtc *crtc)
14868{
14869 struct drm_device *dev = crtc->base.dev;
14870 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 14871 struct intel_encoder *encoder;
fa555837 14872 u32 reg;
b17d48e2 14873 bool enable;
24929352 14874
24929352 14875 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14876 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14877 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14878
d3eaf884 14879 /* restore vblank interrupts to correct state */
9625604c 14880 drm_crtc_vblank_reset(&crtc->base);
d297e103 14881 if (crtc->active) {
3a03dfb0 14882 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14883 update_scanline_offset(crtc);
9625604c
DV		 14884 drm_crtc_vblank_on(&crtc->base);
14885 }
d3eaf884 14886
24929352 14887 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14888 * disable the crtc (and hence change the state) if it is wrong. Note
14889 * that gen4+ has a fixed plane -> pipe mapping. */
14890 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14891 bool plane;
14892
24929352
DV		 14893 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14894 crtc->base.base.id);
14895
14896 /* Pipe has the wrong plane attached and the plane is active.
14897 * Temporarily change the plane mapping and disable everything
14898 * ... */
14899 plane = crtc->plane;
b70709a6 14900 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14901 crtc->plane = !plane;
b17d48e2 14902 intel_crtc_disable_noatomic(&crtc->base);
24929352 14903 crtc->plane = plane;
24929352 14904 }
24929352 14905
7fad798e
DV		 14906 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14907 crtc->pipe == PIPE_A && !crtc->active) {
14908 /* BIOS forgot to enable pipe A, this mostly happens after
14909 * resume. Force-enable the pipe to fix this, the update_dpms
14910 * call below we restore the pipe to the right state, but leave
14911 * the required bits on. */
14912 intel_enable_pipe_a(dev);
14913 }
14914
24929352
DV		 14915 /* Adjust the state of the output pipe according to whether we
14916 * have active connectors/encoders. */
b17d48e2 14917 enable = false;
873ffe69
ML		 14918 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14919 enable = true;
14920 break;
14921 }
24929352 14922
b17d48e2
ML		 14923 if (!enable)
14924 intel_crtc_disable_noatomic(&crtc->base);
24929352 14925
53d9f4e9 14926 if (crtc->active != crtc->base.state->active) {
24929352
DV		 14927
14928 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14929 * functions or because of calls to intel_crtc_disable_noatomic,
14930 * or because the pipe is force-enabled due to the
24929352
DV		 14931 * pipe A quirk. */
14932 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14933 crtc->base.base.id,
83d65738 14934 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14935 crtc->active ? "enabled" : "disabled");
14936
4be40c98 14937 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14938 crtc->base.state->active = crtc->active;
24929352
DV		 14939 crtc->base.enabled = crtc->active;
14940
14941 /* Because we only establish the connector -> encoder ->
14942 * crtc links if something is active, this means the
14943 * crtc is now deactivated. Break the links. connector
14944 * -> encoder links are only establish when things are
14945 * actually up, hence no need to break them. */
14946 WARN_ON(crtc->active);
14947
2d406bb0 14948 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14949 encoder->base.crtc = NULL;
24929352 14950 }
c5ab3bc0 14951
a3ed6aad 14952 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14953 /*
14954 * We start out with underrun reporting disabled to avoid races.
14955 * For correct bookkeeping mark this on active crtcs.
14956 *
c5ab3bc0
DV		 14957 * Also on gmch platforms we dont have any hardware bits to
14958 * disable the underrun reporting. Which means we need to start
14959 * out with underrun reporting disabled also on inactive pipes,
14960 * since otherwise we'll complain about the garbage we read when
14961 * e.g. coming up after runtime pm.
14962 *
4cc31489
DV		 14963 * No protection against concurrent access is required - at
14964 * worst a fifo underrun happens which also sets this to false.
14965 */
14966 crtc->cpu_fifo_underrun_disabled = true;
14967 crtc->pch_fifo_underrun_disabled = true;
14968 }
24929352
DV		 14969}
14970
14971static void intel_sanitize_encoder(struct intel_encoder *encoder)
14972{
14973 struct intel_connector *connector;
14974 struct drm_device *dev = encoder->base.dev;
873ffe69 14975 bool active = false;
24929352
DV		 14976
14977 /* We need to check both for a crtc link (meaning that the
14978 * encoder is active and trying to read from a pipe) and the
14979 * pipe itself being active. */
14980 bool has_active_crtc = encoder->base.crtc &&
14981 to_intel_crtc(encoder->base.crtc)->active;
14982
873ffe69
ML		 14983 for_each_intel_connector(dev, connector) {
14984 if (connector->base.encoder != &encoder->base)
14985 continue;
14986
14987 active = true;
14988 break;
14989 }
14990
14991 if (active && !has_active_crtc) {
24929352
DV		 14992 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14993 encoder->base.base.id,
8e329a03 14994 encoder->base.name);
24929352
DV		 14995
14996 /* Connector is active, but has no active pipe. This is
14997 * fallout from our resume register restoring. Disable
14998 * the encoder manually again. */
14999 if (encoder->base.crtc) {
15000 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15001 encoder->base.base.id,
8e329a03 15002 encoder->base.name);
24929352 15003 encoder->disable(encoder);
a62d1497
VS		 15004 if (encoder->post_disable)
15005 encoder->post_disable(encoder);
24929352 15006 }
7f1950fb 15007 encoder->base.crtc = NULL;
24929352
DV		 15008
15009 /* Inconsistent output/port/pipe state happens presumably due to
15010 * a bug in one of the get_hw_state functions. Or someplace else
15011 * in our code, like the register restore mess on resume. Clamp
15012 * things to off as a safer default. */
3a3371ff 15013 for_each_intel_connector(dev, connector) {
24929352
DV		 15014 if (connector->encoder != encoder)
15015 continue;
7f1950fb
EE		 15016 connector->base.dpms = DRM_MODE_DPMS_OFF;
15017 connector->base.encoder = NULL;
24929352
DV		 15018 }
15019 }
15020 /* Enabled encoders without active connectors will be fixed in
15021 * the crtc fixup. */
15022}
15023
04098753 15024void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15025{
15026 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15027 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15028
04098753
ID		 15029 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15030 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15031 i915_disable_vga(dev);
15032 }
15033}
15034
15035void i915_redisable_vga(struct drm_device *dev)
15036{
15037 struct drm_i915_private *dev_priv = dev->dev_private;
15038
8dc8a27c
PZ		 15039 /* This function can be called both from intel_modeset_setup_hw_state or
15040 * at a very early point in our resume sequence, where the power well
15041 * structures are not yet restored. Since this function is at a very
15042 * paranoid "someone might have enabled VGA while we were not looking"
15043 * level, just check if the power well is enabled instead of trying to
15044 * follow the "don't touch the power well if we don't need it" policy
15045 * the rest of the driver uses. */
f458ebbc 15046 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15047 return;
15048
04098753 15049 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15050}
15051
98ec7739
VS		 15052static bool primary_get_hw_state(struct intel_crtc *crtc)
15053{
15054 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15055
d032ffa0
ML		 15056 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15057}
15058
15059static void readout_plane_state(struct intel_crtc *crtc,
15060 struct intel_crtc_state *crtc_state)
15061{
15062 struct intel_plane *p;
4cf0ebbd 15063 struct intel_plane_state *plane_state;
d032ffa0
ML		 15064 bool active = crtc_state->base.active;
15065
d032ffa0 15066 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15067 if (crtc->pipe != p->pipe)
15068 continue;
15069
4cf0ebbd 15070 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15071
4cf0ebbd
ML		 15072 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15073 plane_state->visible = primary_get_hw_state(crtc);
15074 else {
15075 if (active)
15076 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15077
4cf0ebbd 15078 plane_state->visible = false;
d032ffa0
ML		 15079 }
15080 }
98ec7739
VS		 15081}
15082
30e984df 15083static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15084{
15085 struct drm_i915_private *dev_priv = dev->dev_private;
15086 enum pipe pipe;
24929352
DV		 15087 struct intel_crtc *crtc;
15088 struct intel_encoder *encoder;
15089 struct intel_connector *connector;
5358901f 15090 int i;
24929352 15091
d3fcc808 15092 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15093 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15094 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15095 crtc->config->base.crtc = &crtc->base;
3b117c8f 15096
0e8ffe1b 15097 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15098 crtc->config);
24929352 15099
49d6fa21 15100 crtc->base.state->active = crtc->active;
24929352 15101 crtc->base.enabled = crtc->active;
b70709a6 15102
5c1e3426
ML		 15103 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15104 if (crtc->base.state->active) {
15105 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15106 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15107 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15108
15109 /*
15110 * The initial mode needs to be set in order to keep
15111 * the atomic core happy. It wants a valid mode if the
15112 * crtc's enabled, so we do the above call.
15113 *
15114 * At this point some state updated by the connectors
15115 * in their ->detect() callback has not run yet, so
15116 * no recalculation can be done yet.
15117 *
15118 * Even if we could do a recalculation and modeset
15119 * right now it would cause a double modeset if
15120 * fbdev or userspace chooses a different initial mode.
15121 *
5c1e3426
ML		 15122 * If that happens, someone indicated they wanted a
15123 * mode change, which means it's safe to do a full
15124 * recalculation.
15125 */
1ed51de9 15126 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15127 }
15128
15129 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15130 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15131
15132 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15133 crtc->base.base.id,
15134 crtc->active ? "enabled" : "disabled");
15135 }
15136
5358901f
DV		 15137 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15138 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15139
3e369b76
ACO		 15140 pll->on = pll->get_hw_state(dev_priv, pll,
15141 &pll->config.hw_state);
5358901f 15142 pll->active = 0;
3e369b76 15143 pll->config.crtc_mask = 0;
d3fcc808 15144 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15145 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15146 pll->active++;
3e369b76 15147 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15148 }
5358901f 15149 }
5358901f 15150
1e6f2ddc 15151 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15152 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15153
3e369b76 15154 if (pll->config.crtc_mask)
bd2bb1b9 15155 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15156 }
15157
b2784e15 15158 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15159 pipe = 0;
15160
15161 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15162 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15163 encoder->base.crtc = &crtc->base;
6e3c9717 15164 encoder->get_config(encoder, crtc->config);
24929352
DV		 15165 } else {
15166 encoder->base.crtc = NULL;
15167 }
15168
6f2bcceb 15169 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15170 encoder->base.base.id,
8e329a03 15171 encoder->base.name,
24929352 15172 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15173 pipe_name(pipe));
24929352
DV		 15174 }
15175
3a3371ff 15176 for_each_intel_connector(dev, connector) {
24929352
DV		 15177 if (connector->get_hw_state(connector)) {
15178 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15179 connector->base.encoder = &connector->encoder->base;
15180 } else {
15181 connector->base.dpms = DRM_MODE_DPMS_OFF;
15182 connector->base.encoder = NULL;
15183 }
15184 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15185 connector->base.base.id,
c23cc417 15186 connector->base.name,
24929352
DV		 15187 connector->base.encoder ? "enabled" : "disabled");
15188 }
30e984df
DV		 15189}
15190
043e9bda
ML		 15191/* Scan out the current hw modeset state,
15192 * and sanitizes it to the current state
15193 */
15194static void
15195intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15196{
15197 struct drm_i915_private *dev_priv = dev->dev_private;
15198 enum pipe pipe;
30e984df
DV		 15199 struct intel_crtc *crtc;
15200 struct intel_encoder *encoder;
35c95375 15201 int i;
30e984df
DV		 15202
15203 intel_modeset_readout_hw_state(dev);
24929352
DV		 15204
15205 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15206 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15207 intel_sanitize_encoder(encoder);
15208 }
15209
055e393f 15210 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15211 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15212 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15213 intel_dump_pipe_config(crtc, crtc->config,
15214 "[setup_hw_state]");
24929352 15215 }
9a935856 15216
d29b2f9d
ACO		 15217 intel_modeset_update_connector_atomic_state(dev);
15218
35c95375
DV		 15219 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15220 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15221
15222 if (!pll->on || pll->active)
15223 continue;
15224
15225 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15226
15227 pll->disable(dev_priv, pll);
15228 pll->on = false;
15229 }
15230
26e1fe4f 15231 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15232 vlv_wm_get_hw_state(dev);
15233 else if (IS_GEN9(dev))
3078999f
PB		 15234 skl_wm_get_hw_state(dev);
15235 else if (HAS_PCH_SPLIT(dev))
243e6a44 15236 ilk_wm_get_hw_state(dev);
292b990e
ML		 15237
15238 for_each_intel_crtc(dev, crtc) {
15239 unsigned long put_domains;
15240
15241 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15242 if (WARN_ON(put_domains))
15243 modeset_put_power_domains(dev_priv, put_domains);
15244 }
15245 intel_display_set_init_power(dev_priv, false);
043e9bda 15246}
7d0bc1ea 15247
043e9bda
ML		 15248void intel_display_resume(struct drm_device *dev)
15249{
15250 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15251 struct intel_connector *conn;
15252 struct intel_plane *plane;
15253 struct drm_crtc *crtc;
15254 int ret;
f30da187 15255
043e9bda
ML		 15256 if (!state)
15257 return;
15258
15259 state->acquire_ctx = dev->mode_config.acquire_ctx;
15260
15261 /* preserve complete old state, including dpll */
15262 intel_atomic_get_shared_dpll_state(state);
15263
15264 for_each_crtc(dev, crtc) {
15265 struct drm_crtc_state *crtc_state =
15266 drm_atomic_get_crtc_state(state, crtc);
15267
15268 ret = PTR_ERR_OR_ZERO(crtc_state);
15269 if (ret)
15270 goto err;
15271
15272 /* force a restore */
15273 crtc_state->mode_changed = true;
45e2b5f6 15274 }
8af6cf88 15275
043e9bda
ML		 15276 for_each_intel_plane(dev, plane) {
15277 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15278 if (ret)
15279 goto err;
15280 }
15281
15282 for_each_intel_connector(dev, conn) {
15283 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15284 if (ret)
15285 goto err;
15286 }
15287
15288 intel_modeset_setup_hw_state(dev);
15289
15290 i915_redisable_vga(dev);
74c090b1 15291 ret = drm_atomic_commit(state);
043e9bda
ML		 15292 if (!ret)
15293 return;
15294
15295err:
15296 DRM_ERROR("Restoring old state failed with %i\n", ret);
15297 drm_atomic_state_free(state);
2c7111db
CW		 15298}
15299
15300void intel_modeset_gem_init(struct drm_device *dev)
15301{
92122789 15302 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15303 struct drm_crtc *c;
2ff8fde1 15304 struct drm_i915_gem_object *obj;
e0d6149b 15305 int ret;
484b41dd 15306
ae48434c
ID		 15307 mutex_lock(&dev->struct_mutex);
15308 intel_init_gt_powersave(dev);
15309 mutex_unlock(&dev->struct_mutex);
15310
92122789
JB		 15311 /*
15312 * There may be no VBT; and if the BIOS enabled SSC we can
15313 * just keep using it to avoid unnecessary flicker. Whereas if the
15314 * BIOS isn't using it, don't assume it will work even if the VBT
15315 * indicates as much.
15316 */
15317 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15318 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15319 DREF_SSC1_ENABLE);
15320
1833b134 15321 intel_modeset_init_hw(dev);
02e792fb
DV		 15322
15323 intel_setup_overlay(dev);
484b41dd
JB		 15324
15325 /*
15326 * Make sure any fbs we allocated at startup are properly
15327 * pinned & fenced. When we do the allocation it's too early
15328 * for this.
15329 */
70e1e0ec 15330 for_each_crtc(dev, c) {
2ff8fde1
MR		 15331 obj = intel_fb_obj(c->primary->fb);
15332 if (obj == NULL)
484b41dd
JB		 15333 continue;
15334
e0d6149b
TU		 15335 mutex_lock(&dev->struct_mutex);
15336 ret = intel_pin_and_fence_fb_obj(c->primary,
15337 c->primary->fb,
15338 c->primary->state,
91af127f 15339 NULL, NULL);
e0d6149b
TU		 15340 mutex_unlock(&dev->struct_mutex);
15341 if (ret) {
484b41dd
JB		 15342 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15343 to_intel_crtc(c)->pipe);
66e514c1
DA		 15344 drm_framebuffer_unreference(c->primary->fb);
15345 c->primary->fb = NULL;
36750f28 15346 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15347 update_state_fb(c->primary);
36750f28 15348 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15349 }
15350 }
0962c3c9
VS		 15351
15352 intel_backlight_register(dev);
79e53945
JB		 15353}
15354
4932e2c3
ID		 15355void intel_connector_unregister(struct intel_connector *intel_connector)
15356{
15357 struct drm_connector *connector = &intel_connector->base;
15358
15359 intel_panel_destroy_backlight(connector);
34ea3d38 15360 drm_connector_unregister(connector);
4932e2c3
ID		 15361}
15362
79e53945
JB		 15363void intel_modeset_cleanup(struct drm_device *dev)
15364{
652c393a 15365 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15366 struct drm_connector *connector;
652c393a 15367
2eb5252e
ID		 15368 intel_disable_gt_powersave(dev);
15369
0962c3c9
VS		 15370 intel_backlight_unregister(dev);
15371
fd0c0642
DV		 15372 /*
15373 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15374 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15375 * experience fancy races otherwise.
15376 */
2aeb7d3a 15377 intel_irq_uninstall(dev_priv);
eb21b92b 15378
fd0c0642
DV		 15379 /*
15380 * Due to the hpd irq storm handling the hotplug work can re-arm the
15381 * poll handlers. Hence disable polling after hpd handling is shut down.
15382 */
f87ea761 15383 drm_kms_helper_poll_fini(dev);
fd0c0642 15384
723bfd70
JB		 15385 intel_unregister_dsm_handler();
15386
7733b49b 15387 intel_fbc_disable(dev_priv);
69341a5e 15388
1630fe75
CW		 15389 /* flush any delayed tasks or pending work */
15390 flush_scheduled_work();
15391
db31af1d
JN		 15392 /* destroy the backlight and sysfs files before encoders/connectors */
15393 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15394 struct intel_connector *intel_connector;
15395
15396 intel_connector = to_intel_connector(connector);
15397 intel_connector->unregister(intel_connector);
db31af1d 15398 }
d9255d57 15399
79e53945 15400 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15401
15402 intel_cleanup_overlay(dev);
ae48434c
ID		 15403
15404 mutex_lock(&dev->struct_mutex);
15405 intel_cleanup_gt_powersave(dev);
15406 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15407}
15408
f1c79df3
ZW		 15409/*
15410 * Return which encoder is currently attached for connector.
15411 */
df0e9248 15412struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15413{
df0e9248
CW		 15414 return &intel_attached_encoder(connector)->base;
15415}
f1c79df3 15416
df0e9248
CW		 15417void intel_connector_attach_encoder(struct intel_connector *connector,
15418 struct intel_encoder *encoder)
15419{
15420 connector->encoder = encoder;
15421 drm_mode_connector_attach_encoder(&connector->base,
15422 &encoder->base);
79e53945 15423}
28d52043
DA		 15424
15425/*
15426 * set vga decode state - true == enable VGA decode
15427 */
15428int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15429{
15430 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15431 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15432 u16 gmch_ctrl;
15433
75fa041d
CW		 15434 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15435 DRM_ERROR("failed to read control word\n");
15436 return -EIO;
15437 }
15438
c0cc8a55
CW		 15439 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15440 return 0;
15441
28d52043
DA		 15442 if (state)
15443 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15444 else
15445 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15446
15447 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15448 DRM_ERROR("failed to write control word\n");
15449 return -EIO;
15450 }
15451
28d52043
DA		 15452 return 0;
15453}
c4a1d9e4 15454
c4a1d9e4 15455struct intel_display_error_state {
ff57f1b0
PZ		 15456
15457 u32 power_well_driver;
15458
63b66e5b
CW		 15459 int num_transcoders;
15460
c4a1d9e4
CW		 15461 struct intel_cursor_error_state {
15462 u32 control;
15463 u32 position;
15464 u32 base;
15465 u32 size;
52331309 15466 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15467
15468 struct intel_pipe_error_state {
ddf9c536 15469 bool power_domain_on;
c4a1d9e4 15470 u32 source;
f301b1e1 15471 u32 stat;
52331309 15472 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15473
15474 struct intel_plane_error_state {
15475 u32 control;
15476 u32 stride;
15477 u32 size;
15478 u32 pos;
15479 u32 addr;
15480 u32 surface;
15481 u32 tile_offset;
52331309 15482 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15483
15484 struct intel_transcoder_error_state {
ddf9c536 15485 bool power_domain_on;
63b66e5b
CW		 15486 enum transcoder cpu_transcoder;
15487
15488 u32 conf;
15489
15490 u32 htotal;
15491 u32 hblank;
15492 u32 hsync;
15493 u32 vtotal;
15494 u32 vblank;
15495 u32 vsync;
15496 } transcoder[4];
c4a1d9e4
CW		 15497};
15498
15499struct intel_display_error_state *
15500intel_display_capture_error_state(struct drm_device *dev)
15501{
fbee40df 15502 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15503 struct intel_display_error_state *error;
63b66e5b
CW		 15504 int transcoders[] = {
15505 TRANSCODER_A,
15506 TRANSCODER_B,
15507 TRANSCODER_C,
15508 TRANSCODER_EDP,
15509 };
c4a1d9e4
CW		 15510 int i;
15511
63b66e5b
CW		 15512 if (INTEL_INFO(dev)->num_pipes == 0)
15513 return NULL;
15514
9d1cb914 15515 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15516 if (error == NULL)
15517 return NULL;
15518
190be112 15519 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15520 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15521
055e393f 15522 for_each_pipe(dev_priv, i) {
ddf9c536 15523 error->pipe[i].power_domain_on =
f458ebbc
DV		 15524 __intel_display_power_is_enabled(dev_priv,
15525 POWER_DOMAIN_PIPE(i));
ddf9c536 15526 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15527 continue;
15528
5efb3e28
VS		 15529 error->cursor[i].control = I915_READ(CURCNTR(i));
15530 error->cursor[i].position = I915_READ(CURPOS(i));
15531 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15532
15533 error->plane[i].control = I915_READ(DSPCNTR(i));
15534 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15535 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15536 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15537 error->plane[i].pos = I915_READ(DSPPOS(i));
15538 }
ca291363
PZ		 15539 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15540 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15541 if (INTEL_INFO(dev)->gen >= 4) {
15542 error->plane[i].surface = I915_READ(DSPSURF(i));
15543 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15544 }
15545
c4a1d9e4 15546 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15547
3abfce77 15548 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15549 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15550 }
15551
15552 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15553 if (HAS_DDI(dev_priv->dev))
15554 error->num_transcoders++; /* Account for eDP. */
15555
15556 for (i = 0; i < error->num_transcoders; i++) {
15557 enum transcoder cpu_transcoder = transcoders[i];
15558
ddf9c536 15559 error->transcoder[i].power_domain_on =
f458ebbc 15560 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15561 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15562 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15563 continue;
15564
63b66e5b
CW		 15565 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15566
15567 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15568 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15569 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15570 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15571 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15572 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15573 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15574 }
15575
15576 return error;
15577}
15578
edc3d884
MK		 15579#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15580
c4a1d9e4 15581void
edc3d884 15582intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15583 struct drm_device *dev,
15584 struct intel_display_error_state *error)
15585{
055e393f 15586 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15587 int i;
15588
63b66e5b
CW		 15589 if (!error)
15590 return;
15591
edc3d884 15592 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15593 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15594 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15595 error->power_well_driver);
055e393f 15596 for_each_pipe(dev_priv, i) {
edc3d884 15597 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15598 err_printf(m, " Power: %s\n",
15599 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15600 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15601 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15602
15603 err_printf(m, "Plane [%d]:\n", i);
15604 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15605 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15606 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15607 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15608 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15609 }
4b71a570 15610 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15611 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15612 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15613 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15614 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15615 }
15616
edc3d884
MK		 15617 err_printf(m, "Cursor [%d]:\n", i);
15618 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15619 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15620 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15621 }
63b66e5b
CW		 15622
15623 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15624 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15625 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15626 err_printf(m, " Power: %s\n",
15627 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15628 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15629 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15630 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15631 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15632 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15633 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15634 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15635 }
c4a1d9e4 15636}
e2fcdaa9
VS		 15637
15638void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15639{
15640 struct intel_crtc *crtc;
15641
15642 for_each_intel_crtc(dev, crtc) {
15643 struct intel_unpin_work *work;
e2fcdaa9 15644
5e2d7afc 15645 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15646
15647 work = crtc->unpin_work;
15648
15649 if (work && work->event &&
15650 work->event->base.file_priv == file) {
15651 kfree(work->event);
15652 work->event = NULL;
15653 }
15654
5e2d7afc 15655 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15656 }
15657}
Linux kernel - Deliverables
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