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drm/i915: Change SRM, LRM instructions to use correct length
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB		 89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV		 93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
5ab7b0b7
ID		 401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
e6292556 404 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
cdba954e
ACO		 413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
fc596660 416 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 417}
418
e0638cdf
PZ		 419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
4093561b 422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 423{
409ee761 424 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 425 struct intel_encoder *encoder;
426
409ee761 427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
d0737e1d
ACO		 434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
a93e255f
ACO		 440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
d0737e1d 442{
a93e255f 443 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 444 struct drm_connector *connector;
a93e255f 445 struct drm_connector_state *connector_state;
d0737e1d 446 struct intel_encoder *encoder;
a93e255f
ACO		 447 int i, num_connectors = 0;
448
da3ced29 449 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
d0737e1d 454
a93e255f
ACO		 455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
d0737e1d 457 return true;
a93e255f
ACO		 458 }
459
460 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 461
462 return false;
463}
464
a93e255f
ACO		 465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 467{
a93e255f 468 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 469 const intel_limit_t *limit;
b91ad0ec 470
a93e255f 471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 472 if (intel_is_dual_link_lvds(dev)) {
1b894b59 473 if (refclk == 100000)
b91ad0ec
ZW		 474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
c6bb3538 483 } else
b91ad0ec 484 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 485
486 return limit;
487}
488
a93e255f
ACO		 489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 491{
a93e255f 492 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 493 const intel_limit_t *limit;
494
a93e255f 495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 496 if (intel_is_dual_link_lvds(dev))
e4b36699 497 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 498 else
e4b36699 499 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 502 limit = &intel_limits_g4x_hdmi;
a93e255f 503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 504 limit = &intel_limits_g4x_sdvo;
044c7c41 505 } else /* The option is for other outputs */
e4b36699 506 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 507
508 return limit;
509}
510
a93e255f
ACO		 511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 513{
a93e255f 514 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 515 const intel_limit_t *limit;
516
5ab7b0b7
ID		 517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
a93e255f 520 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 521 else if (IS_G4X(dev)) {
a93e255f 522 limit = intel_g4x_limit(crtc_state);
f2b115e6 523 } else if (IS_PINEVIEW(dev)) {
a93e255f 524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 525 limit = &intel_limits_pineview_lvds;
2177832f 526 else
f2b115e6 527 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
a0c4da24 530 } else if (IS_VALLEYVIEW(dev)) {
dc730512 531 limit = &intel_limits_vlv;
a6c45cf0 532 } else if (!IS_GEN2(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
79e53945 537 } else {
a93e255f 538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 539 limit = &intel_limits_i8xx_lvds;
a93e255f 540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 541 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 542 else
543 limit = &intel_limits_i8xx_dac;
79e53945
JB		 544 }
545 return limit;
546}
547
dccbea3b
ID		 548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
f2b115e6 556/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 558{
2177832f
SL		 559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
ed5ca77e 561 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 562 return 0;
fb03ac01
VS		 563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 565
566 return clock->dot;
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
dccbea3b 574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 579 return 0;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 582
583 return clock->dot;
79e53945
JB		 584}
585
dccbea3b 586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 591 return 0;
589eca67
ID		 592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 594
595 return clock->dot / 5;
589eca67
ID		 596}
597
dccbea3b 598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 603 return 0;
ef9348c8
CML		 604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 607
608 return clock->dot / 5;
ef9348c8
CML		 609}
610
7c04d1d9 611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
1b894b59
CW		 617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
79e53945 620{
f01b7962
VS		 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 624 INTELPllInvalid("p1 out of range\n");
79e53945 625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 626 INTELPllInvalid("m2 out of range\n");
79e53945 627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 628 INTELPllInvalid("m1 out of range\n");
f01b7962 629
5ab7b0b7 630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
5ab7b0b7 634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
79e53945 641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 642 INTELPllInvalid("vco out of range\n");
79e53945
JB		 643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 647 INTELPllInvalid("dot out of range\n");
79e53945
JB		 648
649 return true;
650}
651
3b1429d9
VS		 652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
79e53945 656{
3b1429d9 657 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 658
a93e255f 659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 660 /*
a210b028
DV		 661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
79e53945 664 */
1974cad0 665 if (intel_is_dual_link_lvds(dev))
3b1429d9 666 return limit->p2.p2_fast;
79e53945 667 else
3b1429d9 668 return limit->p2.p2_slow;
79e53945
JB		 669 } else {
670 if (target < limit->p2.dot_limit)
3b1429d9 671 return limit->p2.p2_slow;
79e53945 672 else
3b1429d9 673 return limit->p2.p2_fast;
79e53945 674 }
3b1429d9
VS		 675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
79e53945 686
0206e353 687 memset(best_clock, 0, sizeof(*best_clock));
79e53945 688
3b1429d9
VS		 689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 695 if (clock.m2 >= clock.m1)
42158660
ZY		 696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 701 int this_err;
702
dccbea3b 703 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
a93e255f
ACO		 725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
79e53945 729{
3b1429d9 730 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 731 intel_clock_t clock;
79e53945
JB		 732 int err = target;
733
0206e353 734 memset(best_clock, 0, sizeof(*best_clock));
79e53945 735
3b1429d9
VS		 736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
42158660
ZY		 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 746 int this_err;
747
dccbea3b 748 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
79e53945 751 continue;
cec2f356
SP		 752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
79e53945
JB		 755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
d4906093 769static bool
a93e255f
ACO		 770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
d4906093 774{
3b1429d9 775 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 776 intel_clock_t clock;
777 int max_n;
3b1429d9 778 bool found = false;
6ba770dc
AJ		 779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 781
782 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
d4906093 786 max_n = limit->n.max;
f77f13e2 787 /* based on hardware requirement, prefer smaller n to precision */
d4906093 788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 789 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
dccbea3b 798 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
d4906093 801 continue;
1b894b59
CW		 802
803 this_err = abs(clock.dot - target);
d4906093
ML		 804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
2c07245f
ZW		 814 return found;
815}
816
d5dd62bd
ID		 817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
9ca3ba01
ID		 827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
24be4e46
ID		 837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
d5dd62bd
ID		 840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
a0c4da24 857static bool
a93e255f
ACO		 858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
a0c4da24 862{
a93e255f 863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 864 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 865 intel_clock_t clock;
69e4f900 866 unsigned int bestppm = 1000000;
27e639bf
VS		 867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 869 bool found = false;
a0c4da24 870
6b4bf1c4
VS		 871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 874
875 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 880 clock.p = clock.p1 * clock.p2;
a0c4da24 881 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 883 unsigned int ppm;
69e4f900 884
6b4bf1c4
VS		 885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
dccbea3b 888 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 889
f01b7962
VS		 890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
43b0ac53
VS		 892 continue;
893
d5dd62bd
ID		 894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
6b4bf1c4 899
d5dd62bd
ID		 900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
a0c4da24
JB		 903 }
904 }
905 }
906 }
a0c4da24 907
49e497ef 908 return found;
a0c4da24 909}
a4fc5ed6 910
ef9348c8 911static bool
a93e255f
ACO		 912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
a93e255f 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 918 struct drm_device *dev = crtc->base.dev;
9ca3ba01 919 unsigned int best_error_ppm;
ef9348c8
CML		 920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 925 best_error_ppm = 1000000;
ef9348c8
CML		 926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 939 unsigned int error_ppm;
ef9348c8
CML		 940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
dccbea3b 951 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
9ca3ba01
ID		 956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
ef9348c8
CML		 963 }
964 }
965
966 return found;
967}
968
5ab7b0b7
ID		 969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
20ddf665
VS		 978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
241bfc38 985 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 986 * as Haswell has gained clock readout/fastboot support.
987 *
66e514c1 988 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 989 * properly reconstruct framebuffers.
c3d1f436
MR		 990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
20ddf665 994 */
c3d1f436 995 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 996 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 997}
998
a5c961d1
PZ		 999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
6e3c9717 1005 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1006}
1007
fbf49ea2
VS		 1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1021 msleep(5);
fbf49ea2
VS		 1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
ab7ad7f6
KP		 1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1029 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
ab7ad7f6
KP		 1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
58e10eb9 1041 *
9d0498a2 1042 */
575f7ab7 1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1044{
575f7ab7 1045 struct drm_device *dev = crtc->base.dev;
9d0498a2 1046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1048 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1051 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1052
1053 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
284637d9 1056 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1057 } else {
ab7ad7f6 1058 /* Wait for the display line to settle */
fbf49ea2 1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 }
79e53945
JB		 1062}
1063
b0ea7d37
DL		 1064/*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073{
1074 u32 bit;
1075
c36346e3 1076 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1077 switch (port->port) {
c36346e3
DL		 1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
eba905b2 1091 switch (port->port) {
c36346e3
DL		 1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 default:
1102 return true;
1103 }
b0ea7d37
DL		 1104 }
1105
1106 return I915_READ(SDEISR) & bit;
1107}
1108
b24e7179
JB		 1109static const char *state_string(bool enabled)
1110{
1111 return enabled ? "on" : "off";
1112}
1113
1114/* Only for pre-ILK configs */
55607e8a
DV		 1115void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
b24e7179
JB		 1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121
1122 reg = DPLL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1125 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1128}
b24e7179 1129
23538ef1
JN		 1130/* XXX: the dsi pll is shared between MIPI DSI ports */
1131static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132{
1133 u32 val;
1134 bool cur_state;
1135
a580516d 1136 mutex_lock(&dev_priv->sb_lock);
23538ef1 1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1138 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1139
1140 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1141 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1144}
1145#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
55607e8a 1148struct intel_shared_dpll *
e2b78267
DV		 1149intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150{
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
6e3c9717 1153 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1154 return NULL;
1155
6e3c9717 1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1157}
1158
040484af 1159/* For ILK+ */
55607e8a
DV		 1160void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1162 bool state)
040484af 1163{
040484af 1164 bool cur_state;
5358901f 1165 struct intel_dpll_hw_state hw_state;
040484af 1166
92b27b08 1167 if (WARN (!pll,
46edb027 1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1169 return;
ee7b9f93 1170
5358901f 1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1172 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
040484af 1175}
040484af
JB		 1176
1177static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179{
1180 int reg;
1181 u32 val;
1182 bool cur_state;
ad80a810
PZ		 1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184 pipe);
040484af 1185
affa9354
PZ		 1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
ad80a810 1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1189 val = I915_READ(reg);
ad80a810 1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1191 } else {
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1195 }
e2c719b7 1196 I915_STATE_WARN(cur_state != state,
040484af
JB		 1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1199}
1200#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205{
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209
d63fa0dc
PZ		 1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1213 I915_STATE_WARN(cur_state != state,
040484af
JB		 1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1216}
1217#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe)
1222{
1223 int reg;
1224 u32 val;
1225
1226 /* ILK FDI PLL is always enabled */
3d13ef2e 1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1228 return;
1229
bf507ef7 1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1231 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1232 return;
1233
040484af
JB		 1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
e2c719b7 1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1237}
1238
55607e8a
DV		 1239void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
040484af
JB		 1241{
1242 int reg;
1243 u32 val;
55607e8a 1244 bool cur_state;
040484af
JB		 1245
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
55607e8a 1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1249 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
040484af
JB		 1252}
1253
b680c37a
DV		 1254void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
ea0760cf 1256{
bedd4dba
JN		 1257 struct drm_device *dev = dev_priv->dev;
1258 int pp_reg;
ea0760cf
JB		 1259 u32 val;
1260 enum pipe panel_pipe = PIPE_A;
0de3b485 1261 bool locked = true;
ea0760cf 1262
bedd4dba
JN		 1263 if (WARN_ON(HAS_DDI(dev)))
1264 return;
1265
1266 if (HAS_PCH_SPLIT(dev)) {
1267 u32 port_sel;
1268
ea0760cf 1269 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279 panel_pipe = pipe;
ea0760cf
JB		 1280 } else {
1281 pp_reg = PP_CONTROL;
bedd4dba
JN		 1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
ea0760cf
JB		 1284 }
1285
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1289 locked = false;
1290
e2c719b7 1291 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1292 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1293 pipe_name(pipe));
ea0760cf
JB		 1294}
1295
93ce0ba6
JN		 1296static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1298{
1299 struct drm_device *dev = dev_priv->dev;
1300 bool cur_state;
1301
d9d82081 1302 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1304 else
5efb3e28 1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1306
e2c719b7 1307 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1310}
1311#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
b840d907
JB		 1314void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
b24e7179
JB		 1316{
1317 int reg;
1318 u32 val;
63d7bbe9 1319 bool cur_state;
702e7a56
PZ		 1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321 pipe);
b24e7179 1322
b6b5d049
VS		 1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1326 state = true;
1327
f458ebbc 1328 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1330 cur_state = false;
1331 } else {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1335 }
1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
63d7bbe9 1338 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1339 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1340}
1341
931872fc
CW		 1342static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
b24e7179
JB		 1344{
1345 int reg;
1346 u32 val;
931872fc 1347 bool cur_state;
b24e7179
JB		 1348
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
931872fc 1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1352 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1355}
1356
931872fc
CW		 1357#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
b24e7179
JB		 1360static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362{
653e1026 1363 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1364 int reg, i;
1365 u32 val;
1366 int cur_pipe;
1367
653e1026
VS		 1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
e2c719b7 1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1373 "plane %c assertion failure, should be disabled but not\n",
1374 plane_name(pipe));
19ec1358 1375 return;
28c05794 1376 }
19ec1358 1377
b24e7179 1378 /* Need to check both planes against the pipe */
055e393f 1379 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1380 reg = DSPCNTR(i);
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1387 }
1388}
1389
19332d7a
JB		 1390static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392{
20674eef 1393 struct drm_device *dev = dev_priv->dev;
1fe47785 1394 int reg, sprite;
19332d7a
JB		 1395 u32 val;
1396
7feb8b88 1397 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1398 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1399 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1403 }
1404 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1406 reg = SPCNTR(pipe, sprite);
20674eef 1407 val = I915_READ(reg);
e2c719b7 1408 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1410 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1411 }
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1413 reg = SPRCTL(pipe);
19332d7a 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
19332d7a 1420 val = I915_READ(reg);
e2c719b7 1421 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1423 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1424 }
1425}
1426
08c71e5e
VS		 1427static void assert_vblank_disabled(struct drm_crtc *crtc)
1428{
e2c719b7 1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1430 drm_crtc_vblank_put(crtc);
1431}
1432
89eff4be 1433static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1434{
1435 u32 val;
1436 bool enabled;
1437
e2c719b7 1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1439
92f2584a
JB		 1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1444}
1445
ab9412ba
DV		 1446static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe)
92f2584a
JB		 1448{
1449 int reg;
1450 u32 val;
1451 bool enabled;
1452
ab9412ba 1453 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1456 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458 pipe_name(pipe));
92f2584a
JB		 1459}
1460
4e634389
KP		 1461static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1463{
1464 if ((val & DP_PORT_EN) == 0)
1465 return false;
1466
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471 return false;
44f37d1f
CML		 1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474 return false;
f0575e92
KP		 1475 } else {
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 return false;
1478 }
1479 return true;
1480}
1481
1519b995
KP		 1482static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1484{
dc0fa718 1485 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1486 return false;
1487
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1490 return false;
44f37d1f
CML		 1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493 return false;
1519b995 1494 } else {
dc0fa718 1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1496 return false;
1497 }
1498 return true;
1499}
1500
1501static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1503{
1504 if ((val & LVDS_PORT_EN) == 0)
1505 return false;
1506
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509 return false;
1510 } else {
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 return false;
1513 }
1514 return true;
1515}
1516
1517static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519{
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1521 return false;
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
291906f1 1532static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1533 enum pipe pipe, int reg, u32 port_sel)
291906f1 1534{
47a05eca 1535 u32 val = I915_READ(reg);
e2c719b7 1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1538 reg, pipe_name(pipe));
de9a35ab 1539
e2c719b7 1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1541 && (val & DP_PIPEB_SELECT),
de9a35ab 1542 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1543}
1544
1545static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1547{
47a05eca 1548 u32 val = I915_READ(reg);
e2c719b7 1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1551 reg, pipe_name(pipe));
de9a35ab 1552
e2c719b7 1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1554 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1555 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1556}
1557
1558static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe)
1560{
1561 int reg;
1562 u32 val;
291906f1 1563
f0575e92
KP		 1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1567
1568 reg = PCH_ADPA;
1569 val = I915_READ(reg);
e2c719b7 1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1572 pipe_name(pipe));
291906f1
JB		 1573
1574 reg = PCH_LVDS;
1575 val = I915_READ(reg);
e2c719b7 1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1578 pipe_name(pipe));
291906f1 1579
e2debe91
PZ		 1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1583}
1584
40e9cf64
JB		 1585static void intel_init_dpio(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 if (!IS_VALLEYVIEW(dev))
1590 return;
1591
a09caddd
CML		 1592 /*
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596 */
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600 } else {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602 }
5382f5f3
JB		 1603}
1604
d288f65f 1605static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1606 const struct intel_crtc_state *pipe_config)
87442f73 1607{
426115cf
DV		 1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
d288f65f 1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1612
426115cf 1613 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1614
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1619 if (IS_MOBILE(dev_priv->dev))
426115cf 1620 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1621
426115cf
DV		 1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150);
1625
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
d288f65f 1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1630 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1631
1632 /* We do this three times for luck */
426115cf 1633 I915_WRITE(reg, dpll);
87442f73
DV		 1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642}
1643
d288f65f 1644static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1645 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1646{
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1651 u32 tmp;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
a580516d 1657 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1658
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
54433e91
VS		 1664 mutex_unlock(&dev_priv->sb_lock);
1665
9d556c99
CML		 1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
d288f65f 1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1673
1674 /* Check PLL is locked */
a11b0703 1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
a11b0703 1678 /* not sure when this should be written */
d288f65f 1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1680 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1681}
1682
1c4e0274
VS		 1683static int intel_num_dvo_pipes(struct drm_device *dev)
1684{
1685 struct intel_crtc *crtc;
1686 int count = 0;
1687
1688 for_each_intel_crtc(dev, crtc)
3538b9df 1689 count += crtc->base.state->active &&
409ee761 1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1691
1692 return count;
1693}
1694
66e3d5c0 1695static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1696{
66e3d5c0
DV		 1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
6e3c9717 1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1701
66e3d5c0 1702 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1703
63d7bbe9 1704 /* No really, not for ILK+ */
3d13ef2e 1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1706
1707 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1710
1c4e0274
VS		 1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713 /*
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1718 */
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722 }
66e3d5c0
DV		 1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1730 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
63d7bbe9
JB		 1739
1740 /* We do this three times for luck */
66e3d5c0 1741 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750}
1751
1752/**
50b44a44 1753 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1c4e0274 1761static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1762{
1c4e0274
VS		 1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
409ee761 1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1770 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
b6b5d049
VS		 1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
b8afb911 1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1786 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1787}
1788
f6071166
JB		 1789static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790{
b8afb911 1791 u32 val;
f6071166
JB		 1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
e5cbfbfb
ID		 1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
b8afb911 1800 val = DPLL_VGA_MODE_DIS;
f6071166 1801 if (pipe == PIPE_B)
60bfe44f 1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1805
1806}
1807
1808static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809{
d752048d 1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1811 u32 val;
1812
a11b0703
VS		 1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1815
a11b0703 1816 /* Set PLL en = 0 */
60bfe44f
VS		 1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
d752048d 1823
a580516d 1824 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
61407f6d
VS		 1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
a580516d 1842 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1843}
1844
e4607fcf 1845void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
89b667f8
JB		 1848{
1849 u32 port_mask;
00fc31b7 1850 int dpll_reg;
89b667f8 1851
e4607fcf
CML		 1852 switch (dport->port) {
1853 case PORT_B:
89b667f8 1854 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1855 dpll_reg = DPLL(0);
e4607fcf
CML		 1856 break;
1857 case PORT_C:
89b667f8 1858 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1859 dpll_reg = DPLL(0);
9b6de0a1 1860 expected_mask <<= 4;
00fc31b7
CML		 1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1865 break;
1866 default:
1867 BUG();
1868 }
89b667f8 1869
9b6de0a1
VS		 1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1873}
1874
b14b1055
DV		 1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
be19f0ff
CW		 1881 if (WARN_ON(pll == NULL))
1882 return;
1883
3e369b76 1884 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
92f2584a 1894/**
85b3894f 1895 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
85b3894f 1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1903{
3d13ef2e
DL		 1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1907
87a875bb 1908 if (WARN_ON(pll == NULL))
48da64a8
CW		 1909 return;
1910
3e369b76 1911 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1912 return;
ee7b9f93 1913
74dd6928 1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1915 pll->name, pll->active, pll->on,
e2b78267 1916 crtc->base.base.id);
92f2584a 1917
cdbd2316
DV		 1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
e9d6944e 1920 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1921 return;
1922 }
f4a091c7 1923 WARN_ON(pll->on);
ee7b9f93 1924
bd2bb1b9
PZ		 1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
46edb027 1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1928 pll->enable(dev_priv, pll);
ee7b9f93 1929 pll->on = true;
92f2584a
JB		 1930}
1931
f6daaec2 1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1933{
3d13ef2e
DL		 1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1937
92f2584a 1938 /* PCH only available on ILK+ */
80aa9312
JB		 1939 if (INTEL_INFO(dev)->gen < 5)
1940 return;
1941
eddfcbcd
ML		 1942 if (pll == NULL)
1943 return;
92f2584a 1944
eddfcbcd 1945 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1946 return;
7a419866 1947
46edb027
DV		 1948 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1949 pll->name, pll->active, pll->on,
e2b78267 1950 crtc->base.base.id);
7a419866 1951
48da64a8 1952 if (WARN_ON(pll->active == 0)) {
e9d6944e 1953 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1954 return;
1955 }
1956
e9d6944e 1957 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1958 WARN_ON(!pll->on);
cdbd2316 1959 if (--pll->active)
7a419866 1960 return;
ee7b9f93 1961
46edb027 1962 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1963 pll->disable(dev_priv, pll);
ee7b9f93 1964 pll->on = false;
bd2bb1b9
PZ		 1965
1966 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1967}
1968
b8a4f404
PZ		 1969static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1970 enum pipe pipe)
040484af 1971{
23670b32 1972 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1973 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1975 uint32_t reg, val, pipeconf_val;
040484af
JB		 1976
1977 /* PCH only available on ILK+ */
55522f37 1978 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1979
1980 /* Make sure PCH DPLL is enabled */
e72f9fbf 1981 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1982 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1983
1984 /* FDI must be feeding us bits for PCH ports */
1985 assert_fdi_tx_enabled(dev_priv, pipe);
1986 assert_fdi_rx_enabled(dev_priv, pipe);
1987
23670b32
DV		 1988 if (HAS_PCH_CPT(dev)) {
1989 /* Workaround: Set the timing override bit before enabling the
1990 * pch transcoder. */
1991 reg = TRANS_CHICKEN2(pipe);
1992 val = I915_READ(reg);
1993 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1994 I915_WRITE(reg, val);
59c859d6 1995 }
23670b32 1996
ab9412ba 1997 reg = PCH_TRANSCONF(pipe);
040484af 1998 val = I915_READ(reg);
5f7f726d 1999 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2000
2001 if (HAS_PCH_IBX(dev_priv->dev)) {
2002 /*
c5de7c6f
VS		 2003 * Make the BPC in transcoder be consistent with
2004 * that in pipeconf reg. For HDMI we must use 8bpc
2005 * here for both 8bpc and 12bpc.
e9bcff5c 2006 */
dfd07d72 2007 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2008 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2009 val |= PIPECONF_8BPC;
2010 else
2011 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2012 }
5f7f726d
PZ		 2013
2014 val &= ~TRANS_INTERLACE_MASK;
2015 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2016 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2017 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2018 val |= TRANS_LEGACY_INTERLACED_ILK;
2019 else
2020 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2021 else
2022 val |= TRANS_PROGRESSIVE;
2023
040484af
JB		 2024 I915_WRITE(reg, val | TRANS_ENABLE);
2025 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2026 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2027}
2028
8fb033d7 2029static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2030 enum transcoder cpu_transcoder)
040484af 2031{
8fb033d7 2032 u32 val, pipeconf_val;
8fb033d7
PZ		 2033
2034 /* PCH only available on ILK+ */
55522f37 2035 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2036
8fb033d7 2037 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2038 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2039 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2040
223a6fdf
PZ		 2041 /* Workaround: set timing override bit. */
2042 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2043 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2044 I915_WRITE(_TRANSA_CHICKEN2, val);
2045
25f3ef11 2046 val = TRANS_ENABLE;
937bb610 2047 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2048
9a76b1c6
PZ		 2049 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2050 PIPECONF_INTERLACED_ILK)
a35f2679 2051 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2052 else
2053 val |= TRANS_PROGRESSIVE;
2054
ab9412ba
DV		 2055 I915_WRITE(LPT_TRANSCONF, val);
2056 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2057 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2058}
2059
b8a4f404
PZ		 2060static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2061 enum pipe pipe)
040484af 2062{
23670b32
DV		 2063 struct drm_device *dev = dev_priv->dev;
2064 uint32_t reg, val;
040484af
JB		 2065
2066 /* FDI relies on the transcoder */
2067 assert_fdi_tx_disabled(dev_priv, pipe);
2068 assert_fdi_rx_disabled(dev_priv, pipe);
2069
291906f1
JB		 2070 /* Ports must be off as well */
2071 assert_pch_ports_disabled(dev_priv, pipe);
2072
ab9412ba 2073 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2074 val = I915_READ(reg);
2075 val &= ~TRANS_ENABLE;
2076 I915_WRITE(reg, val);
2077 /* wait for PCH transcoder off, transcoder state */
2078 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2079 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2080
2081 if (!HAS_PCH_IBX(dev)) {
2082 /* Workaround: Clear the timing override chicken bit again. */
2083 reg = TRANS_CHICKEN2(pipe);
2084 val = I915_READ(reg);
2085 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2086 I915_WRITE(reg, val);
2087 }
040484af
JB		 2088}
2089
ab4d966c 2090static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2091{
8fb033d7
PZ		 2092 u32 val;
2093
ab9412ba 2094 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2095 val &= ~TRANS_ENABLE;
ab9412ba 2096 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2097 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2098 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2099 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2100
2101 /* Workaround: clear timing override bit. */
2102 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2103 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2104 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2105}
2106
b24e7179 2107/**
309cfea8 2108 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2109 * @crtc: crtc responsible for the pipe
b24e7179 2110 *
0372264a 2111 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2112 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2113 */
e1fdc473 2114static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2115{
0372264a
PZ		 2116 struct drm_device *dev = crtc->base.dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
2118 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2119 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2120 pipe);
1a240d4d 2121 enum pipe pch_transcoder;
b24e7179
JB		 2122 int reg;
2123 u32 val;
2124
9e2ee2dd
VS		 2125 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2126
58c6eaa2 2127 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2128 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2129 assert_sprites_disabled(dev_priv, pipe);
2130
681e5811 2131 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2132 pch_transcoder = TRANSCODER_A;
2133 else
2134 pch_transcoder = pipe;
2135
b24e7179
JB		 2136 /*
2137 * A pipe without a PLL won't actually be able to drive bits from
2138 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2139 * need the check.
2140 */
50360403 2141 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2143 assert_dsi_pll_enabled(dev_priv);
2144 else
2145 assert_pll_enabled(dev_priv, pipe);
040484af 2146 else {
6e3c9717 2147 if (crtc->config->has_pch_encoder) {
040484af 2148 /* if driving the PCH, we need FDI enabled */
cc391bbb 2149 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2150 assert_fdi_tx_pll_enabled(dev_priv,
2151 (enum pipe) cpu_transcoder);
040484af
JB		 2152 }
2153 /* FIXME: assert CPU port conditions for SNB+ */
2154 }
b24e7179 2155
702e7a56 2156 reg = PIPECONF(cpu_transcoder);
b24e7179 2157 val = I915_READ(reg);
7ad25d48 2158 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2159 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2160 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2161 return;
7ad25d48 2162 }
00d70b15
CW		 2163
2164 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2165 POSTING_READ(reg);
b24e7179
JB		 2166}
2167
2168/**
309cfea8 2169 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2170 * @crtc: crtc whose pipes is to be disabled
b24e7179 2171 *
575f7ab7
VS		 2172 * Disable the pipe of @crtc, making sure that various hardware
2173 * specific requirements are met, if applicable, e.g. plane
2174 * disabled, panel fitter off, etc.
b24e7179
JB		 2175 *
2176 * Will wait until the pipe has shut down before returning.
2177 */
575f7ab7 2178static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2179{
575f7ab7 2180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2181 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2182 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2183 int reg;
2184 u32 val;
2185
9e2ee2dd
VS		 2186 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2187
b24e7179
JB		 2188 /*
2189 * Make sure planes won't keep trying to pump pixels to us,
2190 * or we might hang the display.
2191 */
2192 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2193 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2194 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2195
702e7a56 2196 reg = PIPECONF(cpu_transcoder);
b24e7179 2197 val = I915_READ(reg);
00d70b15
CW		 2198 if ((val & PIPECONF_ENABLE) == 0)
2199 return;
2200
67adc644
VS		 2201 /*
2202 * Double wide has implications for planes
2203 * so best keep it disabled when not needed.
2204 */
6e3c9717 2205 if (crtc->config->double_wide)
67adc644
VS		 2206 val &= ~PIPECONF_DOUBLE_WIDE;
2207
2208 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2209 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2210 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2211 val &= ~PIPECONF_ENABLE;
2212
2213 I915_WRITE(reg, val);
2214 if ((val & PIPECONF_ENABLE) == 0)
2215 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2216}
2217
693db184
CW		 2218static bool need_vtd_wa(struct drm_device *dev)
2219{
2220#ifdef CONFIG_INTEL_IOMMU
2221 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2222 return true;
2223#endif
2224 return false;
2225}
2226
50470bb0 2227unsigned int
6761dd31
TU		 2228intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2229 uint64_t fb_format_modifier)
a57ce0b2 2230{
6761dd31
TU		 2231 unsigned int tile_height;
2232 uint32_t pixel_bytes;
a57ce0b2 2233
b5d0e9bf
DL		 2234 switch (fb_format_modifier) {
2235 case DRM_FORMAT_MOD_NONE:
2236 tile_height = 1;
2237 break;
2238 case I915_FORMAT_MOD_X_TILED:
2239 tile_height = IS_GEN2(dev) ? 16 : 8;
2240 break;
2241 case I915_FORMAT_MOD_Y_TILED:
2242 tile_height = 32;
2243 break;
2244 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2245 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2246 switch (pixel_bytes) {
b5d0e9bf 2247 default:
6761dd31 2248 case 1:
b5d0e9bf
DL		 2249 tile_height = 64;
2250 break;
6761dd31
TU		 2251 case 2:
2252 case 4:
b5d0e9bf
DL		 2253 tile_height = 32;
2254 break;
6761dd31 2255 case 8:
b5d0e9bf
DL		 2256 tile_height = 16;
2257 break;
6761dd31 2258 case 16:
b5d0e9bf
DL		 2259 WARN_ONCE(1,
2260 "128-bit pixels are not supported for display!");
2261 tile_height = 16;
2262 break;
2263 }
2264 break;
2265 default:
2266 MISSING_CASE(fb_format_modifier);
2267 tile_height = 1;
2268 break;
2269 }
091df6cb 2270
6761dd31
TU		 2271 return tile_height;
2272}
2273
2274unsigned int
2275intel_fb_align_height(struct drm_device *dev, unsigned int height,
2276 uint32_t pixel_format, uint64_t fb_format_modifier)
2277{
2278 return ALIGN(height, intel_tile_height(dev, pixel_format,
2279 fb_format_modifier));
a57ce0b2
JB		 2280}
2281
f64b98cd
TU		 2282static int
2283intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285{
50470bb0 2286 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2287 unsigned int tile_height, tile_pitch;
50470bb0 2288
f64b98cd
TU		 2289 *view = i915_ggtt_view_normal;
2290
50470bb0
TU		 2291 if (!plane_state)
2292 return 0;
2293
121920fa 2294 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2295 return 0;
2296
9abc4648 2297 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2298
2299 info->height = fb->height;
2300 info->pixel_format = fb->pixel_format;
2301 info->pitch = fb->pitches[0];
2302 info->fb_modifier = fb->modifier[0];
2303
84fe03f7
TU		 2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0]);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2309 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2310
f64b98cd
TU		 2311 return 0;
2312}
2313
4e9a86b6
VS		 2314static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2315{
2316 if (INTEL_INFO(dev_priv)->gen >= 9)
2317 return 256 * 1024;
985b8bb4
VS		 2318 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2319 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2320 return 128 * 1024;
2321 else if (INTEL_INFO(dev_priv)->gen >= 4)
2322 return 4 * 1024;
2323 else
44c5905e 2324 return 0;
4e9a86b6
VS		 2325}
2326
127bd2ac 2327int
850c4cdc
TU		 2328intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2329 struct drm_framebuffer *fb,
82bc3b2d 2330 const struct drm_plane_state *plane_state,
91af127f
JH		 2331 struct intel_engine_cs *pipelined,
2332 struct drm_i915_gem_request **pipelined_request)
6b95a207 2333{
850c4cdc 2334 struct drm_device *dev = fb->dev;
ce453d81 2335 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2337 struct i915_ggtt_view view;
6b95a207
KH		 2338 u32 alignment;
2339 int ret;
2340
ebcdd39e
MR		 2341 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2342
7b911adc
TU		 2343 switch (fb->modifier[0]) {
2344 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2345 alignment = intel_linear_alignment(dev_priv);
6b95a207 2346 break;
7b911adc 2347 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2348 if (INTEL_INFO(dev)->gen >= 9)
2349 alignment = 256 * 1024;
2350 else {
2351 /* pin() will align the object as required by fence */
2352 alignment = 0;
2353 }
6b95a207 2354 break;
7b911adc 2355 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2356 case I915_FORMAT_MOD_Yf_TILED:
2357 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2358 "Y tiling bo slipped through, driver bug!\n"))
2359 return -EINVAL;
2360 alignment = 1 * 1024 * 1024;
2361 break;
6b95a207 2362 default:
7b911adc
TU		 2363 MISSING_CASE(fb->modifier[0]);
2364 return -EINVAL;
6b95a207
KH		 2365 }
2366
f64b98cd
TU		 2367 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2368 if (ret)
2369 return ret;
2370
693db184
CW		 2371 /* Note that the w/a also requires 64 PTE of padding following the
2372 * bo. We currently fill all unused PTE with the shadow page and so
2373 * we should always have valid PTE following the scanout preventing
2374 * the VT-d warning.
2375 */
2376 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2377 alignment = 256 * 1024;
2378
d6dd6843
PZ		 2379 /*
2380 * Global gtt pte registers are special registers which actually forward
2381 * writes to a chunk of system memory. Which means that there is no risk
2382 * that the register values disappear as soon as we call
2383 * intel_runtime_pm_put(), so it is correct to wrap only the
2384 * pin/unpin/fence and not more.
2385 */
2386 intel_runtime_pm_get(dev_priv);
2387
ce453d81 2388 dev_priv->mm.interruptible = false;
e6617330 2389 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2390 pipelined_request, &view);
48b956c5 2391 if (ret)
ce453d81 2392 goto err_interruptible;
6b95a207
KH		 2393
2394 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2395 * fence, whereas 965+ only requires a fence if using
2396 * framebuffer compression. For simplicity, we always install
2397 * a fence as the cost is not that onerous.
2398 */
06d98131 2399 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2400 if (ret == -EDEADLK) {
2401 /*
2402 * -EDEADLK means there are no free fences
2403 * no pending flips.
2404 *
2405 * This is propagated to atomic, but it uses
2406 * -EDEADLK to force a locking recovery, so
2407 * change the returned error to -EBUSY.
2408 */
2409 ret = -EBUSY;
2410 goto err_unpin;
2411 } else if (ret)
9a5a53b3 2412 goto err_unpin;
1690e1eb 2413
9a5a53b3 2414 i915_gem_object_pin_fence(obj);
6b95a207 2415
ce453d81 2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
6b95a207 2418 return 0;
48b956c5
CW		 2419
2420err_unpin:
f64b98cd 2421 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2422err_interruptible:
2423 dev_priv->mm.interruptible = true;
d6dd6843 2424 intel_runtime_pm_put(dev_priv);
48b956c5 2425 return ret;
6b95a207
KH		 2426}
2427
82bc3b2d
TU		 2428static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
1690e1eb 2430{
82bc3b2d 2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2432 struct i915_ggtt_view view;
2433 int ret;
82bc3b2d 2434
ebcdd39e
MR		 2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
f64b98cd
TU		 2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
1690e1eb 2440 i915_gem_object_unpin_fence(obj);
f64b98cd 2441 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2442}
2443
c2c75131
DV		 2444/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2446unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2447 int *x, int *y,
bc752862
CW		 2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
c2c75131 2451{
bc752862
CW		 2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
c2c75131 2454
bc752862
CW		 2455 tile_rows = *y / 8;
2456 *y %= 8;
c2c75131 2457
bc752862
CW		 2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
4e9a86b6 2463 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2464 unsigned int offset;
2465
2466 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2467 *y = (offset & alignment) / pitch;
2468 *x = ((offset & alignment) - *y * pitch) / cpp;
2469 return offset & ~alignment;
bc752862 2470 }
c2c75131
DV		 2471}
2472
b35d63fa 2473static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2474{
2475 switch (format) {
2476 case DISPPLANE_8BPP:
2477 return DRM_FORMAT_C8;
2478 case DISPPLANE_BGRX555:
2479 return DRM_FORMAT_XRGB1555;
2480 case DISPPLANE_BGRX565:
2481 return DRM_FORMAT_RGB565;
2482 default:
2483 case DISPPLANE_BGRX888:
2484 return DRM_FORMAT_XRGB8888;
2485 case DISPPLANE_RGBX888:
2486 return DRM_FORMAT_XBGR8888;
2487 case DISPPLANE_BGRX101010:
2488 return DRM_FORMAT_XRGB2101010;
2489 case DISPPLANE_RGBX101010:
2490 return DRM_FORMAT_XBGR2101010;
2491 }
2492}
2493
bc8d7dff
DL		 2494static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2495{
2496 switch (format) {
2497 case PLANE_CTL_FORMAT_RGB_565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case PLANE_CTL_FORMAT_XRGB_8888:
2501 if (rgb_order) {
2502 if (alpha)
2503 return DRM_FORMAT_ABGR8888;
2504 else
2505 return DRM_FORMAT_XBGR8888;
2506 } else {
2507 if (alpha)
2508 return DRM_FORMAT_ARGB8888;
2509 else
2510 return DRM_FORMAT_XRGB8888;
2511 }
2512 case PLANE_CTL_FORMAT_XRGB_2101010:
2513 if (rgb_order)
2514 return DRM_FORMAT_XBGR2101010;
2515 else
2516 return DRM_FORMAT_XRGB2101010;
2517 }
2518}
2519
5724dbd1 2520static bool
f6936e29
DV		 2521intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2522 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2523{
2524 struct drm_device *dev = crtc->base.dev;
2525 struct drm_i915_gem_object *obj = NULL;
2526 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2527 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2528 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2529 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2530 PAGE_SIZE);
2531
2532 size_aligned -= base_aligned;
46f297fb 2533
ff2652ea
CW		 2534 if (plane_config->size == 0)
2535 return false;
2536
f37b5c2b
DV		 2537 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2538 base_aligned,
2539 base_aligned,
2540 size_aligned);
46f297fb 2541 if (!obj)
484b41dd 2542 return false;
46f297fb 2543
49af449b
DL		 2544 obj->tiling_mode = plane_config->tiling;
2545 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2546 obj->stride = fb->pitches[0];
46f297fb 2547
6bf129df
DL		 2548 mode_cmd.pixel_format = fb->pixel_format;
2549 mode_cmd.width = fb->width;
2550 mode_cmd.height = fb->height;
2551 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2552 mode_cmd.modifier[0] = fb->modifier[0];
2553 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2554
2555 mutex_lock(&dev->struct_mutex);
6bf129df 2556 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2557 &mode_cmd, obj)) {
46f297fb
JB		 2558 DRM_DEBUG_KMS("intel fb init failed\n");
2559 goto out_unref_obj;
2560 }
46f297fb 2561 mutex_unlock(&dev->struct_mutex);
484b41dd 2562
f6936e29 2563 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2564 return true;
46f297fb
JB		 2565
2566out_unref_obj:
2567 drm_gem_object_unreference(&obj->base);
2568 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2569 return false;
2570}
2571
afd65eb4
MR		 2572/* Update plane->state->fb to match plane->fb after driver-internal updates */
2573static void
2574update_state_fb(struct drm_plane *plane)
2575{
2576 if (plane->fb == plane->state->fb)
2577 return;
2578
2579 if (plane->state->fb)
2580 drm_framebuffer_unreference(plane->state->fb);
2581 plane->state->fb = plane->fb;
2582 if (plane->state->fb)
2583 drm_framebuffer_reference(plane->state->fb);
2584}
2585
5724dbd1 2586static void
f6936e29
DV		 2587intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2588 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2589{
2590 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2591 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2592 struct drm_crtc *c;
2593 struct intel_crtc *i;
2ff8fde1 2594 struct drm_i915_gem_object *obj;
88595ac9 2595 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2596 struct drm_plane_state *plane_state = primary->state;
88595ac9 2597 struct drm_framebuffer *fb;
484b41dd 2598
2d14030b 2599 if (!plane_config->fb)
484b41dd
JB		 2600 return;
2601
f6936e29 2602 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2603 fb = &plane_config->fb->base;
2604 goto valid_fb;
f55548b5 2605 }
484b41dd 2606
2d14030b 2607 kfree(plane_config->fb);
484b41dd
JB		 2608
2609 /*
2610 * Failed to alloc the obj, check to see if we should share
2611 * an fb with another CRTC instead
2612 */
70e1e0ec 2613 for_each_crtc(dev, c) {
484b41dd
JB		 2614 i = to_intel_crtc(c);
2615
2616 if (c == &intel_crtc->base)
2617 continue;
2618
2ff8fde1
MR		 2619 if (!i->active)
2620 continue;
2621
88595ac9
DV		 2622 fb = c->primary->fb;
2623 if (!fb)
484b41dd
JB		 2624 continue;
2625
88595ac9 2626 obj = intel_fb_obj(fb);
2ff8fde1 2627 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2628 drm_framebuffer_reference(fb);
2629 goto valid_fb;
484b41dd
JB		 2630 }
2631 }
88595ac9
DV		 2632
2633 return;
2634
2635valid_fb:
be5651f2
ML		 2636 plane_state->src_x = plane_state->src_y = 0;
2637 plane_state->src_w = fb->width << 16;
2638 plane_state->src_h = fb->height << 16;
2639
2640 plane_state->crtc_x = plane_state->src_y = 0;
2641 plane_state->crtc_w = fb->width;
2642 plane_state->crtc_h = fb->height;
2643
88595ac9
DV		 2644 obj = intel_fb_obj(fb);
2645 if (obj->tiling_mode != I915_TILING_NONE)
2646 dev_priv->preserve_bios_swizzle = true;
2647
be5651f2
ML		 2648 drm_framebuffer_reference(fb);
2649 primary->fb = primary->state->fb = fb;
36750f28 2650 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2651 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2652 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2653}
2654
29b9bde6
DV		 2655static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2656 struct drm_framebuffer *fb,
2657 int x, int y)
81255565
JB		 2658{
2659 struct drm_device *dev = crtc->dev;
2660 struct drm_i915_private *dev_priv = dev->dev_private;
2661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2662 struct drm_plane *primary = crtc->primary;
2663 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2664 struct drm_i915_gem_object *obj;
81255565 2665 int plane = intel_crtc->plane;
e506a0c6 2666 unsigned long linear_offset;
81255565 2667 u32 dspcntr;
f45651ba 2668 u32 reg = DSPCNTR(plane);
48404c1e 2669 int pixel_size;
f45651ba 2670
b70709a6 2671 if (!visible || !fb) {
fdd508a6
VS		 2672 I915_WRITE(reg, 0);
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2675 else
2676 I915_WRITE(DSPADDR(plane), 0);
2677 POSTING_READ(reg);
2678 return;
2679 }
2680
c9ba6fad
VS		 2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2683 return;
2684
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
f45651ba
VS		 2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
fdd508a6 2689 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2690
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2697 */
2698 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2701 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2708 }
81255565 2709
57779d06
VS		 2710 switch (fb->pixel_format) {
2711 case DRM_FORMAT_C8:
81255565
JB		 2712 dspcntr |= DISPPLANE_8BPP;
2713 break;
57779d06 2714 case DRM_FORMAT_XRGB1555:
57779d06 2715 dspcntr |= DISPPLANE_BGRX555;
81255565 2716 break;
57779d06
VS		 2717 case DRM_FORMAT_RGB565:
2718 dspcntr |= DISPPLANE_BGRX565;
2719 break;
2720 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX888;
2722 break;
2723 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2724 dspcntr |= DISPPLANE_RGBX888;
2725 break;
2726 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2727 dspcntr |= DISPPLANE_BGRX101010;
2728 break;
2729 case DRM_FORMAT_XBGR2101010:
57779d06 2730 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2731 break;
2732 default:
baba133a 2733 BUG();
81255565 2734 }
57779d06 2735
f45651ba
VS		 2736 if (INTEL_INFO(dev)->gen >= 4 &&
2737 obj->tiling_mode != I915_TILING_NONE)
2738 dspcntr |= DISPPLANE_TILED;
81255565 2739
de1aa629
VS		 2740 if (IS_G4X(dev))
2741 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2742
b9897127 2743 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2744
c2c75131
DV		 2745 if (INTEL_INFO(dev)->gen >= 4) {
2746 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2747 intel_gen4_compute_page_offset(dev_priv,
2748 &x, &y, obj->tiling_mode,
b9897127 2749 pixel_size,
bc752862 2750 fb->pitches[0]);
c2c75131
DV		 2751 linear_offset -= intel_crtc->dspaddr_offset;
2752 } else {
e506a0c6 2753 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2754 }
e506a0c6 2755
8e7d688b 2756 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2757 dspcntr |= DISPPLANE_ROTATE_180;
2758
6e3c9717
ACO		 2759 x += (intel_crtc->config->pipe_src_w - 1);
2760 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2761
2762 /* Finding the last pixel of the last line of the display
2763 data and adding to linear_offset*/
2764 linear_offset +=
6e3c9717
ACO		 2765 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2766 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2767 }
2768
2769 I915_WRITE(reg, dspcntr);
2770
01f2c773 2771 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2772 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2773 I915_WRITE(DSPSURF(plane),
2774 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2776 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2777 } else
f343c5f6 2778 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2779 POSTING_READ(reg);
17638cd6
JB		 2780}
2781
29b9bde6
DV		 2782static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783 struct drm_framebuffer *fb,
2784 int x, int y)
17638cd6
JB		 2785{
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2789 struct drm_plane *primary = crtc->primary;
2790 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2791 struct drm_i915_gem_object *obj;
17638cd6 2792 int plane = intel_crtc->plane;
e506a0c6 2793 unsigned long linear_offset;
17638cd6 2794 u32 dspcntr;
f45651ba 2795 u32 reg = DSPCNTR(plane);
48404c1e 2796 int pixel_size;
f45651ba 2797
b70709a6 2798 if (!visible || !fb) {
fdd508a6
VS		 2799 I915_WRITE(reg, 0);
2800 I915_WRITE(DSPSURF(plane), 0);
2801 POSTING_READ(reg);
2802 return;
2803 }
2804
c9ba6fad
VS		 2805 obj = intel_fb_obj(fb);
2806 if (WARN_ON(obj == NULL))
2807 return;
2808
2809 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
f45651ba
VS		 2811 dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
fdd508a6 2813 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2814
2815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2817
57779d06
VS		 2818 switch (fb->pixel_format) {
2819 case DRM_FORMAT_C8:
17638cd6
JB		 2820 dspcntr |= DISPPLANE_8BPP;
2821 break;
57779d06
VS		 2822 case DRM_FORMAT_RGB565:
2823 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2824 break;
57779d06 2825 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_BGRX888;
2827 break;
2828 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2829 dspcntr |= DISPPLANE_RGBX888;
2830 break;
2831 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2832 dspcntr |= DISPPLANE_BGRX101010;
2833 break;
2834 case DRM_FORMAT_XBGR2101010:
57779d06 2835 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2836 break;
2837 default:
baba133a 2838 BUG();
17638cd6
JB		 2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
17638cd6 2843
f45651ba 2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2846
b9897127 2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2848 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2849 intel_gen4_compute_page_offset(dev_priv,
2850 &x, &y, obj->tiling_mode,
b9897127 2851 pixel_size,
bc752862 2852 fb->pitches[0]);
c2c75131 2853 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2854 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2855 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2858 x += (intel_crtc->config->pipe_src_w - 1);
2859 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2860
2861 /* Finding the last pixel of the last line of the display
2862 data and adding to linear_offset*/
2863 linear_offset +=
6e3c9717
ACO		 2864 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2866 }
2867 }
2868
2869 I915_WRITE(reg, dspcntr);
17638cd6 2870
01f2c773 2871 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2872 I915_WRITE(DSPSURF(plane),
2873 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2874 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2875 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2876 } else {
2877 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2878 I915_WRITE(DSPLINOFF(plane), linear_offset);
2879 }
17638cd6 2880 POSTING_READ(reg);
17638cd6
JB		 2881}
2882
b321803d
DL		 2883u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2884 uint32_t pixel_format)
2885{
2886 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2887
2888 /*
2889 * The stride is either expressed as a multiple of 64 bytes
2890 * chunks for linear buffers or in number of tiles for tiled
2891 * buffers.
2892 */
2893 switch (fb_modifier) {
2894 case DRM_FORMAT_MOD_NONE:
2895 return 64;
2896 case I915_FORMAT_MOD_X_TILED:
2897 if (INTEL_INFO(dev)->gen == 2)
2898 return 128;
2899 return 512;
2900 case I915_FORMAT_MOD_Y_TILED:
2901 /* No need to check for old gens and Y tiling since this is
2902 * about the display engine and those will be blocked before
2903 * we get here.
2904 */
2905 return 128;
2906 case I915_FORMAT_MOD_Yf_TILED:
2907 if (bits_per_pixel == 8)
2908 return 64;
2909 else
2910 return 128;
2911 default:
2912 MISSING_CASE(fb_modifier);
2913 return 64;
2914 }
2915}
2916
121920fa
TU		 2917unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2918 struct drm_i915_gem_object *obj)
2919{
9abc4648 2920 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2921
2922 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2923 view = &i915_ggtt_view_rotated;
121920fa
TU		 2924
2925 return i915_gem_obj_ggtt_offset_view(obj, view);
2926}
2927
e435d6e5
ML		 2928static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2929{
2930 struct drm_device *dev = intel_crtc->base.dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2934 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2935 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2936}
2937
a1b2278e
CK		 2938/*
2939 * This function detaches (aka. unbinds) unused scalers in hardware
2940 */
0583236e 2941static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2942{
a1b2278e
CK		 2943 struct intel_crtc_scaler_state *scaler_state;
2944 int i;
2945
a1b2278e
CK		 2946 scaler_state = &intel_crtc->config->scaler_state;
2947
2948 /* loop through and disable scalers that aren't in use */
2949 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2950 if (!scaler_state->scalers[i].in_use)
2951 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2952 }
2953}
2954
6156a456 2955u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2956{
6156a456 2957 switch (pixel_format) {
d161cf7a 2958 case DRM_FORMAT_C8:
c34ce3d1 2959 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2960 case DRM_FORMAT_RGB565:
c34ce3d1 2961 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2962 case DRM_FORMAT_XBGR8888:
c34ce3d1 2963 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2964 case DRM_FORMAT_XRGB8888:
c34ce3d1 2965 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2966 /*
2967 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2968 * to be already pre-multiplied. We need to add a knob (or a different
2969 * DRM_FORMAT) for user-space to configure that.
2970 */
f75fb42a 2971 case DRM_FORMAT_ABGR8888:
c34ce3d1 2972 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2974 case DRM_FORMAT_ARGB8888:
c34ce3d1 2975 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2976 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2977 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2978 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2979 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2980 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2981 case DRM_FORMAT_YUYV:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2983 case DRM_FORMAT_YVYU:
c34ce3d1 2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2985 case DRM_FORMAT_UYVY:
c34ce3d1 2986 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2987 case DRM_FORMAT_VYUY:
c34ce3d1 2988 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2989 default:
4249eeef 2990 MISSING_CASE(pixel_format);
70d21f0e 2991 }
8cfcba41 2992
c34ce3d1 2993 return 0;
6156a456 2994}
70d21f0e 2995
6156a456
CK		 2996u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2997{
6156a456 2998 switch (fb_modifier) {
30af77c4 2999 case DRM_FORMAT_MOD_NONE:
70d21f0e 3000 break;
30af77c4 3001 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3002 return PLANE_CTL_TILED_X;
b321803d 3003 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3004 return PLANE_CTL_TILED_Y;
b321803d 3005 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3006 return PLANE_CTL_TILED_YF;
70d21f0e 3007 default:
6156a456 3008 MISSING_CASE(fb_modifier);
70d21f0e 3009 }
8cfcba41 3010
c34ce3d1 3011 return 0;
6156a456 3012}
70d21f0e 3013
6156a456
CK		 3014u32 skl_plane_ctl_rotation(unsigned int rotation)
3015{
3b7a5119 3016 switch (rotation) {
6156a456
CK		 3017 case BIT(DRM_ROTATE_0):
3018 break;
1e8df167
SJ		 3019 /*
3020 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3021 * while i915 HW rotation is clockwise, thats why this swapping.
3022 */
3b7a5119 3023 case BIT(DRM_ROTATE_90):
1e8df167 3024 return PLANE_CTL_ROTATE_270;
3b7a5119 3025 case BIT(DRM_ROTATE_180):
c34ce3d1 3026 return PLANE_CTL_ROTATE_180;
3b7a5119 3027 case BIT(DRM_ROTATE_270):
1e8df167 3028 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3029 default:
3030 MISSING_CASE(rotation);
3031 }
3032
c34ce3d1 3033 return 0;
6156a456
CK		 3034}
3035
3036static void skylake_update_primary_plane(struct drm_crtc *crtc,
3037 struct drm_framebuffer *fb,
3038 int x, int y)
3039{
3040 struct drm_device *dev = crtc->dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3043 struct drm_plane *plane = crtc->primary;
3044 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3045 struct drm_i915_gem_object *obj;
3046 int pipe = intel_crtc->pipe;
3047 u32 plane_ctl, stride_div, stride;
3048 u32 tile_height, plane_offset, plane_size;
3049 unsigned int rotation;
3050 int x_offset, y_offset;
3051 unsigned long surf_addr;
6156a456
CK		 3052 struct intel_crtc_state *crtc_state = intel_crtc->config;
3053 struct intel_plane_state *plane_state;
3054 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3055 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3056 int scaler_id = -1;
3057
6156a456
CK		 3058 plane_state = to_intel_plane_state(plane->state);
3059
b70709a6 3060 if (!visible || !fb) {
6156a456
CK		 3061 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3062 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3063 POSTING_READ(PLANE_CTL(pipe, 0));
3064 return;
3b7a5119 3065 }
70d21f0e 3066
6156a456
CK		 3067 plane_ctl = PLANE_CTL_ENABLE |
3068 PLANE_CTL_PIPE_GAMMA_ENABLE |
3069 PLANE_CTL_PIPE_CSC_ENABLE;
3070
3071 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3072 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3073 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3074
3075 rotation = plane->state->rotation;
3076 plane_ctl |= skl_plane_ctl_rotation(rotation);
3077
b321803d
DL		 3078 obj = intel_fb_obj(fb);
3079 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3080 fb->pixel_format);
3b7a5119
SJ		 3081 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3082
6156a456
CK		 3083 /*
3084 * FIXME: intel_plane_state->src, dst aren't set when transitional
3085 * update_plane helpers are called from legacy paths.
3086 * Once full atomic crtc is available, below check can be avoided.
3087 */
3088 if (drm_rect_width(&plane_state->src)) {
3089 scaler_id = plane_state->scaler_id;
3090 src_x = plane_state->src.x1 >> 16;
3091 src_y = plane_state->src.y1 >> 16;
3092 src_w = drm_rect_width(&plane_state->src) >> 16;
3093 src_h = drm_rect_height(&plane_state->src) >> 16;
3094 dst_x = plane_state->dst.x1;
3095 dst_y = plane_state->dst.y1;
3096 dst_w = drm_rect_width(&plane_state->dst);
3097 dst_h = drm_rect_height(&plane_state->dst);
3098
3099 WARN_ON(x != src_x || y != src_y);
3100 } else {
3101 src_w = intel_crtc->config->pipe_src_w;
3102 src_h = intel_crtc->config->pipe_src_h;
3103 }
3104
3b7a5119
SJ		 3105 if (intel_rotation_90_or_270(rotation)) {
3106 /* stride = Surface height in tiles */
2614f17d 3107 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3108 fb->modifier[0]);
3109 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3110 x_offset = stride * tile_height - y - src_h;
3b7a5119 3111 y_offset = x;
6156a456 3112 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3113 } else {
3114 stride = fb->pitches[0] / stride_div;
3115 x_offset = x;
3116 y_offset = y;
6156a456 3117 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3118 }
3119 plane_offset = y_offset << 16 | x_offset;
b321803d 3120
70d21f0e 3121 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3122 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3123 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3124 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3125
3126 if (scaler_id >= 0) {
3127 uint32_t ps_ctrl = 0;
3128
3129 WARN_ON(!dst_w || !dst_h);
3130 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3131 crtc_state->scaler_state.scalers[scaler_id].mode;
3132 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3133 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3134 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3135 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3136 I915_WRITE(PLANE_POS(pipe, 0), 0);
3137 } else {
3138 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3139 }
3140
121920fa 3141 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3142
3143 POSTING_READ(PLANE_SURF(pipe, 0));
3144}
3145
17638cd6
JB		 3146/* Assume fb object is pinned & idle & fenced and just update base pointers */
3147static int
3148intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3149 int x, int y, enum mode_set_atomic state)
3150{
3151 struct drm_device *dev = crtc->dev;
3152 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3153
ff2a3117 3154 if (dev_priv->fbc.disable_fbc)
7733b49b 3155 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3156
29b9bde6
DV		 3157 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3158
3159 return 0;
81255565
JB		 3160}
3161
7514747d 3162static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3163{
96a02917
VS		 3164 struct drm_crtc *crtc;
3165
70e1e0ec 3166 for_each_crtc(dev, crtc) {
96a02917
VS		 3167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168 enum plane plane = intel_crtc->plane;
3169
3170 intel_prepare_page_flip(dev, plane);
3171 intel_finish_page_flip_plane(dev, plane);
3172 }
7514747d
VS		 3173}
3174
3175static void intel_update_primary_planes(struct drm_device *dev)
3176{
3177 struct drm_i915_private *dev_priv = dev->dev_private;
3178 struct drm_crtc *crtc;
96a02917 3179
70e1e0ec 3180 for_each_crtc(dev, crtc) {
96a02917
VS		 3181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3182
51fd371b 3183 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3184 /*
3185 * FIXME: Once we have proper support for primary planes (and
3186 * disabling them without disabling the entire crtc) allow again
66e514c1 3187 * a NULL crtc->primary->fb.
947fdaad 3188 */
f4510a27 3189 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3190 dev_priv->display.update_primary_plane(crtc,
66e514c1 3191 crtc->primary->fb,
262ca2b0
MR		 3192 crtc->x,
3193 crtc->y);
51fd371b 3194 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3195 }
3196}
3197
7514747d
VS		 3198void intel_prepare_reset(struct drm_device *dev)
3199{
3200 /* no reset support for gen2 */
3201 if (IS_GEN2(dev))
3202 return;
3203
3204 /* reset doesn't touch the display */
3205 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3206 return;
3207
3208 drm_modeset_lock_all(dev);
f98ce92f
VS		 3209 /*
3210 * Disabling the crtcs gracefully seems nicer. Also the
3211 * g33 docs say we should at least disable all the planes.
3212 */
6b72d486 3213 intel_display_suspend(dev);
7514747d
VS		 3214}
3215
3216void intel_finish_reset(struct drm_device *dev)
3217{
3218 struct drm_i915_private *dev_priv = to_i915(dev);
3219
3220 /*
3221 * Flips in the rings will be nuked by the reset,
3222 * so complete all pending flips so that user space
3223 * will get its events and not get stuck.
3224 */
3225 intel_complete_page_flips(dev);
3226
3227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3233 /*
3234 * Flips in the rings have been nuked by the reset,
3235 * so update the base address of all primary
3236 * planes to the the last fb to make sure we're
3237 * showing the correct fb after a reset.
3238 */
3239 intel_update_primary_planes(dev);
3240 return;
3241 }
3242
3243 /*
3244 * The display has been reset as well,
3245 * so need a full re-initialization.
3246 */
3247 intel_runtime_pm_disable_interrupts(dev_priv);
3248 intel_runtime_pm_enable_interrupts(dev_priv);
3249
3250 intel_modeset_init_hw(dev);
3251
3252 spin_lock_irq(&dev_priv->irq_lock);
3253 if (dev_priv->display.hpd_irq_setup)
3254 dev_priv->display.hpd_irq_setup(dev);
3255 spin_unlock_irq(&dev_priv->irq_lock);
3256
043e9bda 3257 intel_display_resume(dev);
7514747d
VS		 3258
3259 intel_hpd_init(dev_priv);
3260
3261 drm_modeset_unlock_all(dev);
3262}
3263
2e2f351d 3264static void
14667a4b
CW		 3265intel_finish_fb(struct drm_framebuffer *old_fb)
3266{
2ff8fde1 3267 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3268 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3269 bool was_interruptible = dev_priv->mm.interruptible;
3270 int ret;
3271
14667a4b
CW		 3272 /* Big Hammer, we also need to ensure that any pending
3273 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3274 * current scanout is retired before unpinning the old
2e2f351d
CW		 3275 * framebuffer. Note that we rely on userspace rendering
3276 * into the buffer attached to the pipe they are waiting
3277 * on. If not, userspace generates a GPU hang with IPEHR
3278 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3279 *
3280 * This should only fail upon a hung GPU, in which case we
3281 * can safely continue.
3282 */
3283 dev_priv->mm.interruptible = false;
2e2f351d 3284 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3285 dev_priv->mm.interruptible = was_interruptible;
3286
2e2f351d 3287 WARN_ON(ret);
14667a4b
CW		 3288}
3289
7d5e3799
CW		 3290static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3291{
3292 struct drm_device *dev = crtc->dev;
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3295 bool pending;
3296
3297 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3298 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3299 return false;
3300
5e2d7afc 3301 spin_lock_irq(&dev->event_lock);
7d5e3799 3302 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3303 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3304
3305 return pending;
3306}
3307
e30e8f75
GP		 3308static void intel_update_pipe_size(struct intel_crtc *crtc)
3309{
3310 struct drm_device *dev = crtc->base.dev;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 const struct drm_display_mode *adjusted_mode;
3313
3314 if (!i915.fastboot)
3315 return;
3316
3317 /*
3318 * Update pipe size and adjust fitter if needed: the reason for this is
3319 * that in compute_mode_changes we check the native mode (not the pfit
3320 * mode) to see if we can flip rather than do a full mode set. In the
3321 * fastboot case, we'll flip, but if we don't update the pipesrc and
3322 * pfit state, we'll end up with a big fb scanned out into the wrong
3323 * sized surface.
3324 *
3325 * To fix this properly, we need to hoist the checks up into
3326 * compute_mode_changes (or above), check the actual pfit state and
3327 * whether the platform allows pfit disable with pipe active, and only
3328 * then update the pipesrc and pfit state, even on the flip path.
3329 */
3330
6e3c9717 3331 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3332
3333 I915_WRITE(PIPESRC(crtc->pipe),
3334 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3335 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3336 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3337 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3338 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3339 I915_WRITE(PF_CTL(crtc->pipe), 0);
3340 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3341 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3342 }
6e3c9717
ACO		 3343 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3344 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3345}
3346
5e84e1a4
ZW		 3347static void intel_fdi_normal_train(struct drm_crtc *crtc)
3348{
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352 int pipe = intel_crtc->pipe;
3353 u32 reg, temp;
3354
3355 /* enable normal train */
3356 reg = FDI_TX_CTL(pipe);
3357 temp = I915_READ(reg);
61e499bf 3358 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3359 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3360 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3364 }
5e84e1a4
ZW		 3365 I915_WRITE(reg, temp);
3366
3367 reg = FDI_RX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 if (HAS_PCH_CPT(dev)) {
3370 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3371 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3372 } else {
3373 temp &= ~FDI_LINK_TRAIN_NONE;
3374 temp |= FDI_LINK_TRAIN_NONE;
3375 }
3376 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3377
3378 /* wait one idle pattern time */
3379 POSTING_READ(reg);
3380 udelay(1000);
357555c0
JB		 3381
3382 /* IVB wants error correction enabled */
3383 if (IS_IVYBRIDGE(dev))
3384 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3385 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3386}
3387
8db9d77b
ZW		 3388/* The FDI link training functions for ILK/Ibexpeak. */
3389static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3390{
3391 struct drm_device *dev = crtc->dev;
3392 struct drm_i915_private *dev_priv = dev->dev_private;
3393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3394 int pipe = intel_crtc->pipe;
5eddb70b 3395 u32 reg, temp, tries;
8db9d77b 3396
1c8562f6 3397 /* FDI needs bits from pipe first */
0fc932b8 3398 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3399
e1a44743
AJ		 3400 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3401 for train result */
5eddb70b
CW		 3402 reg = FDI_RX_IMR(pipe);
3403 temp = I915_READ(reg);
e1a44743
AJ		 3404 temp &= ~FDI_RX_SYMBOL_LOCK;
3405 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3406 I915_WRITE(reg, temp);
3407 I915_READ(reg);
e1a44743
AJ		 3408 udelay(150);
3409
8db9d77b 3410 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
627eb5a3 3413 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3414 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3415 temp &= ~FDI_LINK_TRAIN_NONE;
3416 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3418
5eddb70b
CW		 3419 reg = FDI_RX_CTL(pipe);
3420 temp = I915_READ(reg);
8db9d77b
ZW		 3421 temp &= ~FDI_LINK_TRAIN_NONE;
3422 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3423 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3424
3425 POSTING_READ(reg);
8db9d77b
ZW		 3426 udelay(150);
3427
5b2adf89 3428 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3431 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3432
5eddb70b 3433 reg = FDI_RX_IIR(pipe);
e1a44743 3434 for (tries = 0; tries < 5; tries++) {
5eddb70b 3435 temp = I915_READ(reg);
8db9d77b
ZW		 3436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3437
3438 if ((temp & FDI_RX_BIT_LOCK)) {
3439 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3441 break;
3442 }
8db9d77b 3443 }
e1a44743 3444 if (tries == 5)
5eddb70b 3445 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3446
3447 /* Train 2 */
5eddb70b
CW		 3448 reg = FDI_TX_CTL(pipe);
3449 temp = I915_READ(reg);
8db9d77b
ZW		 3450 temp &= ~FDI_LINK_TRAIN_NONE;
3451 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3452 I915_WRITE(reg, temp);
8db9d77b 3453
5eddb70b
CW		 3454 reg = FDI_RX_CTL(pipe);
3455 temp = I915_READ(reg);
8db9d77b
ZW		 3456 temp &= ~FDI_LINK_TRAIN_NONE;
3457 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3458 I915_WRITE(reg, temp);
8db9d77b 3459
5eddb70b
CW		 3460 POSTING_READ(reg);
3461 udelay(150);
8db9d77b 3462
5eddb70b 3463 reg = FDI_RX_IIR(pipe);
e1a44743 3464 for (tries = 0; tries < 5; tries++) {
5eddb70b 3465 temp = I915_READ(reg);
8db9d77b
ZW		 3466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3469 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3470 DRM_DEBUG_KMS("FDI train 2 done.\n");
3471 break;
3472 }
8db9d77b 3473 }
e1a44743 3474 if (tries == 5)
5eddb70b 3475 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3476
3477 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3478
8db9d77b
ZW		 3479}
3480
0206e353 3481static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3482 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3483 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3484 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3485 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3486};
3487
3488/* The FDI link training functions for SNB/Cougarpoint. */
3489static void gen6_fdi_link_train(struct drm_crtc *crtc)
3490{
3491 struct drm_device *dev = crtc->dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3494 int pipe = intel_crtc->pipe;
fa37d39e 3495 u32 reg, temp, i, retry;
8db9d77b 3496
e1a44743
AJ		 3497 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3498 for train result */
5eddb70b
CW		 3499 reg = FDI_RX_IMR(pipe);
3500 temp = I915_READ(reg);
e1a44743
AJ		 3501 temp &= ~FDI_RX_SYMBOL_LOCK;
3502 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3503 I915_WRITE(reg, temp);
3504
3505 POSTING_READ(reg);
e1a44743
AJ		 3506 udelay(150);
3507
8db9d77b 3508 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3509 reg = FDI_TX_CTL(pipe);
3510 temp = I915_READ(reg);
627eb5a3 3511 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3512 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3513 temp &= ~FDI_LINK_TRAIN_NONE;
3514 temp |= FDI_LINK_TRAIN_PATTERN_1;
3515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3516 /* SNB-B */
3517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3518 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3519
d74cf324
DV		 3520 I915_WRITE(FDI_RX_MISC(pipe),
3521 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3522
5eddb70b
CW		 3523 reg = FDI_RX_CTL(pipe);
3524 temp = I915_READ(reg);
8db9d77b
ZW		 3525 if (HAS_PCH_CPT(dev)) {
3526 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3527 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3528 } else {
3529 temp &= ~FDI_LINK_TRAIN_NONE;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1;
3531 }
5eddb70b
CW		 3532 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3533
3534 POSTING_READ(reg);
8db9d77b
ZW		 3535 udelay(150);
3536
0206e353 3537 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3538 reg = FDI_TX_CTL(pipe);
3539 temp = I915_READ(reg);
8db9d77b
ZW		 3540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3541 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3542 I915_WRITE(reg, temp);
3543
3544 POSTING_READ(reg);
8db9d77b
ZW		 3545 udelay(500);
3546
fa37d39e
SP		 3547 for (retry = 0; retry < 5; retry++) {
3548 reg = FDI_RX_IIR(pipe);
3549 temp = I915_READ(reg);
3550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3551 if (temp & FDI_RX_BIT_LOCK) {
3552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3553 DRM_DEBUG_KMS("FDI train 1 done.\n");
3554 break;
3555 }
3556 udelay(50);
8db9d77b 3557 }
fa37d39e
SP		 3558 if (retry < 5)
3559 break;
8db9d77b
ZW		 3560 }
3561 if (i == 4)
5eddb70b 3562 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3563
3564 /* Train 2 */
5eddb70b
CW		 3565 reg = FDI_TX_CTL(pipe);
3566 temp = I915_READ(reg);
8db9d77b
ZW		 3567 temp &= ~FDI_LINK_TRAIN_NONE;
3568 temp |= FDI_LINK_TRAIN_PATTERN_2;
3569 if (IS_GEN6(dev)) {
3570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571 /* SNB-B */
3572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3573 }
5eddb70b 3574 I915_WRITE(reg, temp);
8db9d77b 3575
5eddb70b
CW		 3576 reg = FDI_RX_CTL(pipe);
3577 temp = I915_READ(reg);
8db9d77b
ZW		 3578 if (HAS_PCH_CPT(dev)) {
3579 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3580 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3581 } else {
3582 temp &= ~FDI_LINK_TRAIN_NONE;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2;
3584 }
5eddb70b
CW		 3585 I915_WRITE(reg, temp);
3586
3587 POSTING_READ(reg);
8db9d77b
ZW		 3588 udelay(150);
3589
0206e353 3590 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3591 reg = FDI_TX_CTL(pipe);
3592 temp = I915_READ(reg);
8db9d77b
ZW		 3593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3594 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3595 I915_WRITE(reg, temp);
3596
3597 POSTING_READ(reg);
8db9d77b
ZW		 3598 udelay(500);
3599
fa37d39e
SP		 3600 for (retry = 0; retry < 5; retry++) {
3601 reg = FDI_RX_IIR(pipe);
3602 temp = I915_READ(reg);
3603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3604 if (temp & FDI_RX_SYMBOL_LOCK) {
3605 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3606 DRM_DEBUG_KMS("FDI train 2 done.\n");
3607 break;
3608 }
3609 udelay(50);
8db9d77b 3610 }
fa37d39e
SP		 3611 if (retry < 5)
3612 break;
8db9d77b
ZW		 3613 }
3614 if (i == 4)
5eddb70b 3615 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3616
3617 DRM_DEBUG_KMS("FDI train done.\n");
3618}
3619
357555c0
JB		 3620/* Manual link training for Ivy Bridge A0 parts */
3621static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3622{
3623 struct drm_device *dev = crtc->dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 int pipe = intel_crtc->pipe;
139ccd3f 3627 u32 reg, temp, i, j;
357555c0
JB		 3628
3629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3630 for train result */
3631 reg = FDI_RX_IMR(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_RX_SYMBOL_LOCK;
3634 temp &= ~FDI_RX_BIT_LOCK;
3635 I915_WRITE(reg, temp);
3636
3637 POSTING_READ(reg);
3638 udelay(150);
3639
01a415fd
DV		 3640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3641 I915_READ(FDI_RX_IIR(pipe)));
3642
139ccd3f
JB		 3643 /* Try each vswing and preemphasis setting twice before moving on */
3644 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3645 /* disable first in case we need to retry */
3646 reg = FDI_TX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3649 temp &= ~FDI_TX_ENABLE;
3650 I915_WRITE(reg, temp);
357555c0 3651
139ccd3f
JB		 3652 reg = FDI_RX_CTL(pipe);
3653 temp = I915_READ(reg);
3654 temp &= ~FDI_LINK_TRAIN_AUTO;
3655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3656 temp &= ~FDI_RX_ENABLE;
3657 I915_WRITE(reg, temp);
357555c0 3658
139ccd3f 3659 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3660 reg = FDI_TX_CTL(pipe);
3661 temp = I915_READ(reg);
139ccd3f 3662 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3666 temp |= snb_b_fdi_train_param[j/2];
3667 temp |= FDI_COMPOSITE_SYNC;
3668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3669
139ccd3f
JB		 3670 I915_WRITE(FDI_RX_MISC(pipe),
3671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3672
139ccd3f 3673 reg = FDI_RX_CTL(pipe);
357555c0 3674 temp = I915_READ(reg);
139ccd3f
JB		 3675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3676 temp |= FDI_COMPOSITE_SYNC;
3677 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3678
139ccd3f
JB		 3679 POSTING_READ(reg);
3680 udelay(1); /* should be 0.5us */
357555c0 3681
139ccd3f
JB		 3682 for (i = 0; i < 4; i++) {
3683 reg = FDI_RX_IIR(pipe);
3684 temp = I915_READ(reg);
3685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3686
139ccd3f
JB		 3687 if (temp & FDI_RX_BIT_LOCK ||
3688 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3689 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3691 i);
3692 break;
3693 }
3694 udelay(1); /* should be 0.5us */
3695 }
3696 if (i == 4) {
3697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3698 continue;
3699 }
357555c0 3700
139ccd3f 3701 /* Train 2 */
357555c0
JB		 3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
139ccd3f
JB		 3704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3706 I915_WRITE(reg, temp);
3707
3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
3710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3712 I915_WRITE(reg, temp);
3713
3714 POSTING_READ(reg);
139ccd3f 3715 udelay(2); /* should be 1.5us */
357555c0 3716
139ccd3f
JB		 3717 for (i = 0; i < 4; i++) {
3718 reg = FDI_RX_IIR(pipe);
3719 temp = I915_READ(reg);
3720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3721
139ccd3f
JB		 3722 if (temp & FDI_RX_SYMBOL_LOCK ||
3723 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3726 i);
3727 goto train_done;
3728 }
3729 udelay(2); /* should be 1.5us */
357555c0 3730 }
139ccd3f
JB		 3731 if (i == 4)
3732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3733 }
357555c0 3734
139ccd3f 3735train_done:
357555c0
JB		 3736 DRM_DEBUG_KMS("FDI train done.\n");
3737}
3738
88cefb6c 3739static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3740{
88cefb6c 3741 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3742 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3743 int pipe = intel_crtc->pipe;
5eddb70b 3744 u32 reg, temp;
79e53945 3745
c64e311e 3746
c98e9dcf 3747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3748 reg = FDI_RX_CTL(pipe);
3749 temp = I915_READ(reg);
627eb5a3 3750 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3751 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3754
3755 POSTING_READ(reg);
c98e9dcf
JB		 3756 udelay(200);
3757
3758 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3759 temp = I915_READ(reg);
3760 I915_WRITE(reg, temp | FDI_PCDCLK);
3761
3762 POSTING_READ(reg);
c98e9dcf
JB		 3763 udelay(200);
3764
20749730
PZ		 3765 /* Enable CPU FDI TX PLL, always on for Ironlake */
3766 reg = FDI_TX_CTL(pipe);
3767 temp = I915_READ(reg);
3768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3770
20749730
PZ		 3771 POSTING_READ(reg);
3772 udelay(100);
6be4a607 3773 }
0e23b99d
JB		 3774}
3775
88cefb6c
DV		 3776static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3777{
3778 struct drm_device *dev = intel_crtc->base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 int pipe = intel_crtc->pipe;
3781 u32 reg, temp;
3782
3783 /* Switch from PCDclk to Rawclk */
3784 reg = FDI_RX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3787
3788 /* Disable CPU FDI TX PLL */
3789 reg = FDI_TX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3792
3793 POSTING_READ(reg);
3794 udelay(100);
3795
3796 reg = FDI_RX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3799
3800 /* Wait for the clocks to turn off. */
3801 POSTING_READ(reg);
3802 udelay(100);
3803}
3804
0fc932b8
JB		 3805static void ironlake_fdi_disable(struct drm_crtc *crtc)
3806{
3807 struct drm_device *dev = crtc->dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3810 int pipe = intel_crtc->pipe;
3811 u32 reg, temp;
3812
3813 /* disable CPU FDI tx and PCH FDI rx */
3814 reg = FDI_TX_CTL(pipe);
3815 temp = I915_READ(reg);
3816 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3817 POSTING_READ(reg);
3818
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 temp &= ~(0x7 << 16);
dfd07d72 3822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3823 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3824
3825 POSTING_READ(reg);
3826 udelay(100);
3827
3828 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3829 if (HAS_PCH_IBX(dev))
6f06ce18 3830 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3831
3832 /* still set train pattern 1 */
3833 reg = FDI_TX_CTL(pipe);
3834 temp = I915_READ(reg);
3835 temp &= ~FDI_LINK_TRAIN_NONE;
3836 temp |= FDI_LINK_TRAIN_PATTERN_1;
3837 I915_WRITE(reg, temp);
3838
3839 reg = FDI_RX_CTL(pipe);
3840 temp = I915_READ(reg);
3841 if (HAS_PCH_CPT(dev)) {
3842 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3843 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3844 } else {
3845 temp &= ~FDI_LINK_TRAIN_NONE;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1;
3847 }
3848 /* BPC in FDI rx is consistent with that in PIPECONF */
3849 temp &= ~(0x07 << 16);
dfd07d72 3850 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3851 I915_WRITE(reg, temp);
3852
3853 POSTING_READ(reg);
3854 udelay(100);
3855}
3856
5dce5b93
CW		 3857bool intel_has_pending_fb_unpin(struct drm_device *dev)
3858{
3859 struct intel_crtc *crtc;
3860
3861 /* Note that we don't need to be called with mode_config.lock here
3862 * as our list of CRTC objects is static for the lifetime of the
3863 * device and so cannot disappear as we iterate. Similarly, we can
3864 * happily treat the predicates as racy, atomic checks as userspace
3865 * cannot claim and pin a new fb without at least acquring the
3866 * struct_mutex and so serialising with us.
3867 */
d3fcc808 3868 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3869 if (atomic_read(&crtc->unpin_work_count) == 0)
3870 continue;
3871
3872 if (crtc->unpin_work)
3873 intel_wait_for_vblank(dev, crtc->pipe);
3874
3875 return true;
3876 }
3877
3878 return false;
3879}
3880
d6bbafa1
CW		 3881static void page_flip_completed(struct intel_crtc *intel_crtc)
3882{
3883 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3884 struct intel_unpin_work *work = intel_crtc->unpin_work;
3885
3886 /* ensure that the unpin work is consistent wrt ->pending. */
3887 smp_rmb();
3888 intel_crtc->unpin_work = NULL;
3889
3890 if (work->event)
3891 drm_send_vblank_event(intel_crtc->base.dev,
3892 intel_crtc->pipe,
3893 work->event);
3894
3895 drm_crtc_vblank_put(&intel_crtc->base);
3896
3897 wake_up_all(&dev_priv->pending_flip_queue);
3898 queue_work(dev_priv->wq, &work->work);
3899
3900 trace_i915_flip_complete(intel_crtc->plane,
3901 work->pending_flip_obj);
3902}
3903
46a55d30 3904void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3905{
0f91128d 3906 struct drm_device *dev = crtc->dev;
5bb61643 3907 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3908
2c10d571 3909 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3910 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3911 !intel_crtc_has_pending_flip(crtc),
3912 60*HZ) == 0)) {
3913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3914
5e2d7afc 3915 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3916 if (intel_crtc->unpin_work) {
3917 WARN_ONCE(1, "Removing stuck page flip\n");
3918 page_flip_completed(intel_crtc);
3919 }
5e2d7afc 3920 spin_unlock_irq(&dev->event_lock);
9c787942 3921 }
5bb61643 3922
975d568a
CW		 3923 if (crtc->primary->fb) {
3924 mutex_lock(&dev->struct_mutex);
3925 intel_finish_fb(crtc->primary->fb);
3926 mutex_unlock(&dev->struct_mutex);
3927 }
e6c3a2a6
CW		 3928}
3929
e615efe4
ED		 3930/* Program iCLKIP clock to the desired frequency */
3931static void lpt_program_iclkip(struct drm_crtc *crtc)
3932{
3933 struct drm_device *dev = crtc->dev;
3934 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3935 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3936 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3937 u32 temp;
3938
a580516d 3939 mutex_lock(&dev_priv->sb_lock);
09153000 3940
e615efe4
ED		 3941 /* It is necessary to ungate the pixclk gate prior to programming
3942 * the divisors, and gate it back when it is done.
3943 */
3944 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3945
3946 /* Disable SSCCTL */
3947 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3948 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3949 SBI_SSCCTL_DISABLE,
3950 SBI_ICLK);
e615efe4
ED		 3951
3952 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3953 if (clock == 20000) {
e615efe4
ED		 3954 auxdiv = 1;
3955 divsel = 0x41;
3956 phaseinc = 0x20;
3957 } else {
3958 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3959 * but the adjusted_mode->crtc_clock in in KHz. To get the
3960 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3961 * convert the virtual clock precision to KHz here for higher
3962 * precision.
3963 */
3964 u32 iclk_virtual_root_freq = 172800 * 1000;
3965 u32 iclk_pi_range = 64;
3966 u32 desired_divisor, msb_divisor_value, pi_value;
3967
12d7ceed 3968 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3969 msb_divisor_value = desired_divisor / iclk_pi_range;
3970 pi_value = desired_divisor % iclk_pi_range;
3971
3972 auxdiv = 0;
3973 divsel = msb_divisor_value - 2;
3974 phaseinc = pi_value;
3975 }
3976
3977 /* This should not happen with any sane values */
3978 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3979 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3980 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3981 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3982
3983 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3984 clock,
e615efe4
ED		 3985 auxdiv,
3986 divsel,
3987 phasedir,
3988 phaseinc);
3989
3990 /* Program SSCDIVINTPHASE6 */
988d6ee8 3991 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3992 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3993 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3994 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3995 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3996 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3997 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3998 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3999
4000 /* Program SSCAUXDIV */
988d6ee8 4001 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4002 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4003 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4004 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4005
4006 /* Enable modulator and associated divider */
988d6ee8 4007 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4008 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4009 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4010
4011 /* Wait for initialization time */
4012 udelay(24);
4013
4014 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4015
a580516d 4016 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4017}
4018
275f01b2
DV		 4019static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4020 enum pipe pch_transcoder)
4021{
4022 struct drm_device *dev = crtc->base.dev;
4023 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4024 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4025
4026 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4027 I915_READ(HTOTAL(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4029 I915_READ(HBLANK(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4031 I915_READ(HSYNC(cpu_transcoder)));
4032
4033 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4034 I915_READ(VTOTAL(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4036 I915_READ(VBLANK(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4038 I915_READ(VSYNC(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4040 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4041}
4042
003632d9 4043static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4044{
4045 struct drm_i915_private *dev_priv = dev->dev_private;
4046 uint32_t temp;
4047
4048 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4049 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4050 return;
4051
4052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4053 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4054
003632d9
ACO		 4055 temp &= ~FDI_BC_BIFURCATION_SELECT;
4056 if (enable)
4057 temp |= FDI_BC_BIFURCATION_SELECT;
4058
4059 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4060 I915_WRITE(SOUTH_CHICKEN1, temp);
4061 POSTING_READ(SOUTH_CHICKEN1);
4062}
4063
4064static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4065{
4066 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4067
4068 switch (intel_crtc->pipe) {
4069 case PIPE_A:
4070 break;
4071 case PIPE_B:
6e3c9717 4072 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4073 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4074 else
003632d9 4075 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4076
4077 break;
4078 case PIPE_C:
003632d9 4079 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4080
4081 break;
4082 default:
4083 BUG();
4084 }
4085}
4086
f67a559d
JB		 4087/*
4088 * Enable PCH resources required for PCH ports:
4089 * - PCH PLLs
4090 * - FDI training & RX/TX
4091 * - update transcoder timings
4092 * - DP transcoding bits
4093 * - transcoder
4094 */
4095static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4096{
4097 struct drm_device *dev = crtc->dev;
4098 struct drm_i915_private *dev_priv = dev->dev_private;
4099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4100 int pipe = intel_crtc->pipe;
ee7b9f93 4101 u32 reg, temp;
2c07245f 4102
ab9412ba 4103 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4104
1fbc0d78
DV		 4105 if (IS_IVYBRIDGE(dev))
4106 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4107
cd986abb
DV		 4108 /* Write the TU size bits before fdi link training, so that error
4109 * detection works. */
4110 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4111 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4112
c98e9dcf 4113 /* For PCH output, training FDI link */
674cf967 4114 dev_priv->display.fdi_link_train(crtc);
2c07245f 4115
3ad8a208
DV		 4116 /* We need to program the right clock selection before writing the pixel
4117 * mutliplier into the DPLL. */
303b81e0 4118 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4119 u32 sel;
4b645f14 4120
c98e9dcf 4121 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4122 temp |= TRANS_DPLL_ENABLE(pipe);
4123 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4124 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4125 temp |= sel;
4126 else
4127 temp &= ~sel;
c98e9dcf 4128 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4129 }
5eddb70b 4130
3ad8a208
DV		 4131 /* XXX: pch pll's can be enabled any time before we enable the PCH
4132 * transcoder, and we actually should do this to not upset any PCH
4133 * transcoder that already use the clock when we share it.
4134 *
4135 * Note that enable_shared_dpll tries to do the right thing, but
4136 * get_shared_dpll unconditionally resets the pll - we need that to have
4137 * the right LVDS enable sequence. */
85b3894f 4138 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4139
d9b6cb56
JB		 4140 /* set transcoder timing, panel must allow it */
4141 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4142 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4143
303b81e0 4144 intel_fdi_normal_train(crtc);
5e84e1a4 4145
c98e9dcf 4146 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4147 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4148 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4149 reg = TRANS_DP_CTL(pipe);
4150 temp = I915_READ(reg);
4151 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4152 TRANS_DP_SYNC_MASK |
4153 TRANS_DP_BPC_MASK);
e3ef4479 4154 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4155 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4156
4157 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4158 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4159 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4160 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4161
4162 switch (intel_trans_dp_port_sel(crtc)) {
4163 case PCH_DP_B:
5eddb70b 4164 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4165 break;
4166 case PCH_DP_C:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_D:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4171 break;
4172 default:
e95d41e1 4173 BUG();
32f9d658 4174 }
2c07245f 4175
5eddb70b 4176 I915_WRITE(reg, temp);
6be4a607 4177 }
b52eb4dc 4178
b8a4f404 4179 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4180}
4181
1507e5bd
PZ		 4182static void lpt_pch_enable(struct drm_crtc *crtc)
4183{
4184 struct drm_device *dev = crtc->dev;
4185 struct drm_i915_private *dev_priv = dev->dev_private;
4186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4187 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4188
ab9412ba 4189 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4190
8c52b5e8 4191 lpt_program_iclkip(crtc);
1507e5bd 4192
0540e488 4193 /* Set transcoder timing. */
275f01b2 4194 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4195
937bb610 4196 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4197}
4198
190f68c5
ACO		 4199struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4200 struct intel_crtc_state *crtc_state)
ee7b9f93 4201{
e2b78267 4202 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4203 struct intel_shared_dpll *pll;
de419ab6 4204 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4205 enum intel_dpll_id i;
ee7b9f93 4206
de419ab6
ML		 4207 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4208
98b6bd99
DV		 4209 if (HAS_PCH_IBX(dev_priv->dev)) {
4210 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4211 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4212 pll = &dev_priv->shared_dplls[i];
98b6bd99 4213
46edb027
DV		 4214 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4215 crtc->base.base.id, pll->name);
98b6bd99 4216
de419ab6 4217 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4218
98b6bd99
DV		 4219 goto found;
4220 }
4221
bcddf610
S		 4222 if (IS_BROXTON(dev_priv->dev)) {
4223 /* PLL is attached to port in bxt */
4224 struct intel_encoder *encoder;
4225 struct intel_digital_port *intel_dig_port;
4226
4227 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4228 if (WARN_ON(!encoder))
4229 return NULL;
4230
4231 intel_dig_port = enc_to_dig_port(&encoder->base);
4232 /* 1:1 mapping between ports and PLLs */
4233 i = (enum intel_dpll_id)intel_dig_port->port;
4234 pll = &dev_priv->shared_dplls[i];
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
de419ab6 4237 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4238
4239 goto found;
4240 }
4241
e72f9fbf
DV		 4242 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4243 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4244
4245 /* Only want to check enabled timings first */
de419ab6 4246 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4247 continue;
4248
190f68c5 4249 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4250 &shared_dpll[i].hw_state,
4251 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4252 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4253 crtc->base.base.id, pll->name,
de419ab6 4254 shared_dpll[i].crtc_mask,
8bd31e67 4255 pll->active);
ee7b9f93
JB		 4256 goto found;
4257 }
4258 }
4259
4260 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4261 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4262 pll = &dev_priv->shared_dplls[i];
de419ab6 4263 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4264 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4265 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4266 goto found;
4267 }
4268 }
4269
4270 return NULL;
4271
4272found:
de419ab6
ML		 4273 if (shared_dpll[i].crtc_mask == 0)
4274 shared_dpll[i].hw_state =
4275 crtc_state->dpll_hw_state;
f2a69f44 4276
190f68c5 4277 crtc_state->shared_dpll = i;
46edb027
DV		 4278 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4279 pipe_name(crtc->pipe));
ee7b9f93 4280
de419ab6 4281 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4282
ee7b9f93
JB		 4283 return pll;
4284}
4285
de419ab6 4286static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4287{
de419ab6
ML		 4288 struct drm_i915_private *dev_priv = to_i915(state->dev);
4289 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4290 struct intel_shared_dpll *pll;
4291 enum intel_dpll_id i;
4292
de419ab6
ML		 4293 if (!to_intel_atomic_state(state)->dpll_set)
4294 return;
8bd31e67 4295
de419ab6 4296 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
de419ab6 4299 pll->config = shared_dpll[i];
8bd31e67
ACO		 4300 }
4301}
4302
a1520318 4303static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4304{
4305 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4306 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4307 u32 temp;
4308
4309 temp = I915_READ(dslreg);
4310 udelay(500);
4311 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4312 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4313 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4314 }
4315}
4316
86adf9d7
ML		 4317static int
4318skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4319 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4320 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4321{
86adf9d7
ML		 4322 struct intel_crtc_scaler_state *scaler_state =
4323 &crtc_state->scaler_state;
4324 struct intel_crtc *intel_crtc =
4325 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4326 int need_scaling;
6156a456
CK		 4327
4328 need_scaling = intel_rotation_90_or_270(rotation) ?
4329 (src_h != dst_w || src_w != dst_h):
4330 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4331
4332 /*
4333 * if plane is being disabled or scaler is no more required or force detach
4334 * - free scaler binded to this plane/crtc
4335 * - in order to do this, update crtc->scaler_usage
4336 *
4337 * Here scaler state in crtc_state is set free so that
4338 * scaler can be assigned to other user. Actual register
4339 * update to free the scaler is done in plane/panel-fit programming.
4340 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4341 */
86adf9d7 4342 if (force_detach || !need_scaling) {
a1b2278e 4343 if (*scaler_id >= 0) {
86adf9d7 4344 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4345 scaler_state->scalers[*scaler_id].in_use = 0;
4346
86adf9d7
ML		 4347 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4348 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4349 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4350 scaler_state->scaler_users);
4351 *scaler_id = -1;
4352 }
4353 return 0;
4354 }
4355
4356 /* range checks */
4357 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4358 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4359
4360 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4361 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4362 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4363 "size is out of scaler range\n",
86adf9d7 4364 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4365 return -EINVAL;
4366 }
4367
86adf9d7
ML		 4368 /* mark this plane as a scaler user in crtc_state */
4369 scaler_state->scaler_users |= (1 << scaler_user);
4370 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4371 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4372 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4373 scaler_state->scaler_users);
4374
4375 return 0;
4376}
4377
4378/**
4379 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4380 *
4381 * @state: crtc's scaler state
86adf9d7
ML		 4382 *
4383 * Return
4384 * 0 - scaler_usage updated successfully
4385 * error - requested scaling cannot be supported or other error condition
4386 */
e435d6e5 4387int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4388{
4389 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4390 struct drm_display_mode *adjusted_mode =
4391 &state->base.adjusted_mode;
4392
4393 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4394 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4395
e435d6e5 4396 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4397 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4398 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4399 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4400}
4401
4402/**
4403 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4404 *
4405 * @state: crtc's scaler state
86adf9d7
ML		 4406 * @plane_state: atomic plane state to update
4407 *
4408 * Return
4409 * 0 - scaler_usage updated successfully
4410 * error - requested scaling cannot be supported or other error condition
4411 */
da20eabd
ML		 4412static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4413 struct intel_plane_state *plane_state)
86adf9d7
ML		 4414{
4415
4416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4417 struct intel_plane *intel_plane =
4418 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4419 struct drm_framebuffer *fb = plane_state->base.fb;
4420 int ret;
4421
4422 bool force_detach = !fb || !plane_state->visible;
4423
4424 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4425 intel_plane->base.base.id, intel_crtc->pipe,
4426 drm_plane_index(&intel_plane->base));
4427
4428 ret = skl_update_scaler(crtc_state, force_detach,
4429 drm_plane_index(&intel_plane->base),
4430 &plane_state->scaler_id,
4431 plane_state->base.rotation,
4432 drm_rect_width(&plane_state->src) >> 16,
4433 drm_rect_height(&plane_state->src) >> 16,
4434 drm_rect_width(&plane_state->dst),
4435 drm_rect_height(&plane_state->dst));
4436
4437 if (ret || plane_state->scaler_id < 0)
4438 return ret;
4439
a1b2278e 4440 /* check colorkey */
818ed961 4441 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4442 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4443 intel_plane->base.base.id);
a1b2278e
CK		 4444 return -EINVAL;
4445 }
4446
4447 /* Check src format */
86adf9d7
ML		 4448 switch (fb->pixel_format) {
4449 case DRM_FORMAT_RGB565:
4450 case DRM_FORMAT_XBGR8888:
4451 case DRM_FORMAT_XRGB8888:
4452 case DRM_FORMAT_ABGR8888:
4453 case DRM_FORMAT_ARGB8888:
4454 case DRM_FORMAT_XRGB2101010:
4455 case DRM_FORMAT_XBGR2101010:
4456 case DRM_FORMAT_YUYV:
4457 case DRM_FORMAT_YVYU:
4458 case DRM_FORMAT_UYVY:
4459 case DRM_FORMAT_VYUY:
4460 break;
4461 default:
4462 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4463 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4464 return -EINVAL;
a1b2278e
CK		 4465 }
4466
a1b2278e
CK		 4467 return 0;
4468}
4469
e435d6e5
ML		 4470static void skylake_scaler_disable(struct intel_crtc *crtc)
4471{
4472 int i;
4473
4474 for (i = 0; i < crtc->num_scalers; i++)
4475 skl_detach_scaler(crtc, i);
4476}
4477
4478static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4479{
4480 struct drm_device *dev = crtc->base.dev;
4481 struct drm_i915_private *dev_priv = dev->dev_private;
4482 int pipe = crtc->pipe;
a1b2278e
CK		 4483 struct intel_crtc_scaler_state *scaler_state =
4484 &crtc->config->scaler_state;
4485
4486 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4487
6e3c9717 4488 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4489 int id;
4490
4491 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4492 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4493 return;
4494 }
4495
4496 id = scaler_state->scaler_id;
4497 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4498 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4499 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4500 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4501
4502 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4503 }
4504}
4505
b074cec8
JB		 4506static void ironlake_pfit_enable(struct intel_crtc *crtc)
4507{
4508 struct drm_device *dev = crtc->base.dev;
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 int pipe = crtc->pipe;
4511
6e3c9717 4512 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4513 /* Force use of hard-coded filter coefficients
4514 * as some pre-programmed values are broken,
4515 * e.g. x201.
4516 */
4517 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4518 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4519 PF_PIPE_SEL_IVB(pipe));
4520 else
4521 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4522 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4523 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4524 }
4525}
4526
20bc8673 4527void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4528{
cea165c3
VS		 4529 struct drm_device *dev = crtc->base.dev;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4531
6e3c9717 4532 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4533 return;
4534
cea165c3
VS		 4535 /* We can only enable IPS after we enable a plane and wait for a vblank */
4536 intel_wait_for_vblank(dev, crtc->pipe);
4537
d77e4531 4538 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4539 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4540 mutex_lock(&dev_priv->rps.hw_lock);
4541 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4542 mutex_unlock(&dev_priv->rps.hw_lock);
4543 /* Quoting Art Runyan: "its not safe to expect any particular
4544 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4545 * mailbox." Moreover, the mailbox may return a bogus state,
4546 * so we need to just enable it and continue on.
2a114cc1
BW		 4547 */
4548 } else {
4549 I915_WRITE(IPS_CTL, IPS_ENABLE);
4550 /* The bit only becomes 1 in the next vblank, so this wait here
4551 * is essentially intel_wait_for_vblank. If we don't have this
4552 * and don't wait for vblanks until the end of crtc_enable, then
4553 * the HW state readout code will complain that the expected
4554 * IPS_CTL value is not the one we read. */
4555 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4556 DRM_ERROR("Timed out waiting for IPS enable\n");
4557 }
d77e4531
PZ		 4558}
4559
20bc8673 4560void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4561{
4562 struct drm_device *dev = crtc->base.dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564
6e3c9717 4565 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4566 return;
4567
4568 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4569 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4570 mutex_lock(&dev_priv->rps.hw_lock);
4571 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4572 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4573 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4574 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4575 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4576 } else {
2a114cc1 4577 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4578 POSTING_READ(IPS_CTL);
4579 }
d77e4531
PZ		 4580
4581 /* We need to wait for a vblank before we can disable the plane. */
4582 intel_wait_for_vblank(dev, crtc->pipe);
4583}
4584
4585/** Loads the palette/gamma unit for the CRTC with the prepared values */
4586static void intel_crtc_load_lut(struct drm_crtc *crtc)
4587{
4588 struct drm_device *dev = crtc->dev;
4589 struct drm_i915_private *dev_priv = dev->dev_private;
4590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4591 enum pipe pipe = intel_crtc->pipe;
4592 int palreg = PALETTE(pipe);
4593 int i;
4594 bool reenable_ips = false;
4595
4596 /* The clocks have to be on to load the palette. */
53d9f4e9 4597 if (!crtc->state->active)
d77e4531
PZ		 4598 return;
4599
50360403 4600 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4601 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4602 assert_dsi_pll_enabled(dev_priv);
4603 else
4604 assert_pll_enabled(dev_priv, pipe);
4605 }
4606
4607 /* use legacy palette for Ironlake */
7a1db49a 4608 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4609 palreg = LGC_PALETTE(pipe);
4610
4611 /* Workaround : Do not read or write the pipe palette/gamma data while
4612 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4613 */
6e3c9717 4614 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4615 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4616 GAMMA_MODE_MODE_SPLIT)) {
4617 hsw_disable_ips(intel_crtc);
4618 reenable_ips = true;
4619 }
4620
4621 for (i = 0; i < 256; i++) {
4622 I915_WRITE(palreg + 4 * i,
4623 (intel_crtc->lut_r[i] << 16) |
4624 (intel_crtc->lut_g[i] << 8) |
4625 intel_crtc->lut_b[i]);
4626 }
4627
4628 if (reenable_ips)
4629 hsw_enable_ips(intel_crtc);
4630}
4631
7cac945f 4632static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4633{
7cac945f 4634 if (intel_crtc->overlay) {
d3eedb1a
VS		 4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
4638 mutex_lock(&dev->struct_mutex);
4639 dev_priv->mm.interruptible = false;
4640 (void) intel_overlay_switch_off(intel_crtc->overlay);
4641 dev_priv->mm.interruptible = true;
4642 mutex_unlock(&dev->struct_mutex);
4643 }
4644
4645 /* Let userspace switch the overlay on again. In most cases userspace
4646 * has to recompute where to put it anyway.
4647 */
4648}
4649
87d4300a
ML		 4650/**
4651 * intel_post_enable_primary - Perform operations after enabling primary plane
4652 * @crtc: the CRTC whose primary plane was just enabled
4653 *
4654 * Performs potentially sleeping operations that must be done after the primary
4655 * plane is enabled, such as updating FBC and IPS. Note that this may be
4656 * called due to an explicit primary plane update, or due to an implicit
4657 * re-enable that is caused when a sprite plane is updated to no longer
4658 * completely hide the primary plane.
4659 */
4660static void
4661intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4662{
4663 struct drm_device *dev = crtc->dev;
87d4300a 4664 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4666 int pipe = intel_crtc->pipe;
a5c4d7bc 4667
87d4300a
ML		 4668 /*
4669 * BDW signals flip done immediately if the plane
4670 * is disabled, even if the plane enable is already
4671 * armed to occur at the next vblank :(
4672 */
4673 if (IS_BROADWELL(dev))
4674 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4675
87d4300a
ML		 4676 /*
4677 * FIXME IPS should be fine as long as one plane is
4678 * enabled, but in practice it seems to have problems
4679 * when going from primary only to sprite only and vice
4680 * versa.
4681 */
a5c4d7bc
VS		 4682 hsw_enable_ips(intel_crtc);
4683
f99d7069 4684 /*
87d4300a
ML		 4685 * Gen2 reports pipe underruns whenever all planes are disabled.
4686 * So don't enable underrun reporting before at least some planes
4687 * are enabled.
4688 * FIXME: Need to fix the logic to work when we turn off all planes
4689 * but leave the pipe running.
f99d7069 4690 */
87d4300a
ML		 4691 if (IS_GEN2(dev))
4692 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4693
4694 /* Underruns don't raise interrupts, so check manually. */
4695 if (HAS_GMCH_DISPLAY(dev))
4696 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4697}
4698
87d4300a
ML		 4699/**
4700 * intel_pre_disable_primary - Perform operations before disabling primary plane
4701 * @crtc: the CRTC whose primary plane is to be disabled
4702 *
4703 * Performs potentially sleeping operations that must be done before the
4704 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4705 * be called due to an explicit primary plane update, or due to an implicit
4706 * disable that is caused when a sprite plane completely hides the primary
4707 * plane.
4708 */
4709static void
4710intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4711{
4712 struct drm_device *dev = crtc->dev;
4713 struct drm_i915_private *dev_priv = dev->dev_private;
4714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4715 int pipe = intel_crtc->pipe;
a5c4d7bc 4716
87d4300a
ML		 4717 /*
4718 * Gen2 reports pipe underruns whenever all planes are disabled.
4719 * So diasble underrun reporting before all the planes get disabled.
4720 * FIXME: Need to fix the logic to work when we turn off all planes
4721 * but leave the pipe running.
4722 */
4723 if (IS_GEN2(dev))
4724 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4725
87d4300a
ML		 4726 /*
4727 * Vblank time updates from the shadow to live plane control register
4728 * are blocked if the memory self-refresh mode is active at that
4729 * moment. So to make sure the plane gets truly disabled, disable
4730 * first the self-refresh mode. The self-refresh enable bit in turn
4731 * will be checked/applied by the HW only at the next frame start
4732 * event which is after the vblank start event, so we need to have a
4733 * wait-for-vblank between disabling the plane and the pipe.
4734 */
262cd2e1 4735 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4736 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4737 dev_priv->wm.vlv.cxsr = false;
4738 intel_wait_for_vblank(dev, pipe);
4739 }
87d4300a 4740
87d4300a
ML		 4741 /*
4742 * FIXME IPS should be fine as long as one plane is
4743 * enabled, but in practice it seems to have problems
4744 * when going from primary only to sprite only and vice
4745 * versa.
4746 */
a5c4d7bc 4747 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4748}
4749
ac21b225
ML		 4750static void intel_post_plane_update(struct intel_crtc *crtc)
4751{
4752 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4753 struct drm_device *dev = crtc->base.dev;
7733b49b 4754 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4755 struct drm_plane *plane;
4756
4757 if (atomic->wait_vblank)
4758 intel_wait_for_vblank(dev, crtc->pipe);
4759
4760 intel_frontbuffer_flip(dev, atomic->fb_bits);
4761
852eb00d
VS		 4762 if (atomic->disable_cxsr)
4763 crtc->wm.cxsr_allowed = true;
4764
f015c551
VS		 4765 if (crtc->atomic.update_wm_post)
4766 intel_update_watermarks(&crtc->base);
4767
c80ac854 4768 if (atomic->update_fbc)
7733b49b 4769 intel_fbc_update(dev_priv);
ac21b225
ML		 4770
4771 if (atomic->post_enable_primary)
4772 intel_post_enable_primary(&crtc->base);
4773
4774 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4775 intel_update_sprite_watermarks(plane, &crtc->base,
4776 0, 0, 0, false, false);
4777
4778 memset(atomic, 0, sizeof(*atomic));
4779}
4780
4781static void intel_pre_plane_update(struct intel_crtc *crtc)
4782{
4783 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4784 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4785 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4786 struct drm_plane *p;
4787
4788 /* Track fb's for any planes being disabled */
ac21b225
ML		 4789 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4790 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4791
4792 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4793 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4794 plane->frontbuffer_bit);
ac21b225
ML		 4795 mutex_unlock(&dev->struct_mutex);
4796 }
4797
4798 if (atomic->wait_for_flips)
4799 intel_crtc_wait_for_pending_flips(&crtc->base);
4800
c80ac854 4801 if (atomic->disable_fbc)
25ad93fd 4802 intel_fbc_disable_crtc(crtc);
ac21b225 4803
066cf55b
RV		 4804 if (crtc->atomic.disable_ips)
4805 hsw_disable_ips(crtc);
4806
ac21b225
ML		 4807 if (atomic->pre_disable_primary)
4808 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4809
4810 if (atomic->disable_cxsr) {
4811 crtc->wm.cxsr_allowed = false;
4812 intel_set_memory_cxsr(dev_priv, false);
4813 }
ac21b225
ML		 4814}
4815
d032ffa0 4816static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4817{
4818 struct drm_device *dev = crtc->dev;
4819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4820 struct drm_plane *p;
87d4300a
ML		 4821 int pipe = intel_crtc->pipe;
4822
7cac945f 4823 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4824
d032ffa0
ML		 4825 drm_for_each_plane_mask(p, dev, plane_mask)
4826 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4827
f99d7069
DV		 4828 /*
4829 * FIXME: Once we grow proper nuclear flip support out of this we need
4830 * to compute the mask of flip planes precisely. For the time being
4831 * consider this a flip to a NULL plane.
4832 */
4833 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4834}
4835
f67a559d
JB		 4836static void ironlake_crtc_enable(struct drm_crtc *crtc)
4837{
4838 struct drm_device *dev = crtc->dev;
4839 struct drm_i915_private *dev_priv = dev->dev_private;
4840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4841 struct intel_encoder *encoder;
f67a559d 4842 int pipe = intel_crtc->pipe;
f67a559d 4843
53d9f4e9 4844 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4845 return;
4846
6e3c9717 4847 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4848 intel_prepare_shared_dpll(intel_crtc);
4849
6e3c9717 4850 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4851 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4852
4853 intel_set_pipe_timings(intel_crtc);
4854
6e3c9717 4855 if (intel_crtc->config->has_pch_encoder) {
29407aab 4856 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4857 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4858 }
4859
4860 ironlake_set_pipeconf(crtc);
4861
f67a559d 4862 intel_crtc->active = true;
8664281b 4863
a72e4c9f
DV		 4864 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4865 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4866
f6736a1a 4867 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4868 if (encoder->pre_enable)
4869 encoder->pre_enable(encoder);
f67a559d 4870
6e3c9717 4871 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4872 /* Note: FDI PLL enabling _must_ be done before we enable the
4873 * cpu pipes, hence this is separate from all the other fdi/pch
4874 * enabling. */
88cefb6c 4875 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4876 } else {
4877 assert_fdi_tx_disabled(dev_priv, pipe);
4878 assert_fdi_rx_disabled(dev_priv, pipe);
4879 }
f67a559d 4880
b074cec8 4881 ironlake_pfit_enable(intel_crtc);
f67a559d 4882
9c54c0dd
JB		 4883 /*
4884 * On ILK+ LUT must be loaded before the pipe is running but with
4885 * clocks enabled
4886 */
4887 intel_crtc_load_lut(crtc);
4888
f37fcc2a 4889 intel_update_watermarks(crtc);
e1fdc473 4890 intel_enable_pipe(intel_crtc);
f67a559d 4891
6e3c9717 4892 if (intel_crtc->config->has_pch_encoder)
f67a559d 4893 ironlake_pch_enable(crtc);
c98e9dcf 4894
f9b61ff6
DV		 4895 assert_vblank_disabled(crtc);
4896 drm_crtc_vblank_on(crtc);
4897
fa5c73b1
DV		 4898 for_each_encoder_on_crtc(dev, crtc, encoder)
4899 encoder->enable(encoder);
61b77ddd
DV		 4900
4901 if (HAS_PCH_CPT(dev))
a1520318 4902 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4903}
4904
42db64ef
PZ		 4905/* IPS only exists on ULT machines and is tied to pipe A. */
4906static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4907{
f5adf94e 4908 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4909}
4910
4f771f10
PZ		 4911static void haswell_crtc_enable(struct drm_crtc *crtc)
4912{
4913 struct drm_device *dev = crtc->dev;
4914 struct drm_i915_private *dev_priv = dev->dev_private;
4915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4916 struct intel_encoder *encoder;
99d736a2
ML		 4917 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4918 struct intel_crtc_state *pipe_config =
4919 to_intel_crtc_state(crtc->state);
4f771f10 4920
53d9f4e9 4921 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4922 return;
4923
df8ad70c
DV		 4924 if (intel_crtc_to_shared_dpll(intel_crtc))
4925 intel_enable_shared_dpll(intel_crtc);
4926
6e3c9717 4927 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4928 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4929
4930 intel_set_pipe_timings(intel_crtc);
4931
6e3c9717
ACO		 4932 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4933 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4934 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4935 }
4936
6e3c9717 4937 if (intel_crtc->config->has_pch_encoder) {
229fca97 4938 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4939 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4940 }
4941
4942 haswell_set_pipeconf(crtc);
4943
4944 intel_set_pipe_csc(crtc);
4945
4f771f10 4946 intel_crtc->active = true;
8664281b 4947
a72e4c9f 4948 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4949 for_each_encoder_on_crtc(dev, crtc, encoder)
4950 if (encoder->pre_enable)
4951 encoder->pre_enable(encoder);
4952
6e3c9717 4953 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4954 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4955 true);
4fe9467d
ID		 4956 dev_priv->display.fdi_link_train(crtc);
4957 }
4958
1f544388 4959 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4960
ff6d9f55 4961 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4962 skylake_pfit_enable(intel_crtc);
ff6d9f55 4963 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4964 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4965 else
4966 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4967
4968 /*
4969 * On ILK+ LUT must be loaded before the pipe is running but with
4970 * clocks enabled
4971 */
4972 intel_crtc_load_lut(crtc);
4973
1f544388 4974 intel_ddi_set_pipe_settings(crtc);
8228c251 4975 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4976
f37fcc2a 4977 intel_update_watermarks(crtc);
e1fdc473 4978 intel_enable_pipe(intel_crtc);
42db64ef 4979
6e3c9717 4980 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4981 lpt_pch_enable(crtc);
4f771f10 4982
6e3c9717 4983 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4984 intel_ddi_set_vc_payload_alloc(crtc, true);
4985
f9b61ff6
DV		 4986 assert_vblank_disabled(crtc);
4987 drm_crtc_vblank_on(crtc);
4988
8807e55b 4989 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4990 encoder->enable(encoder);
8807e55b
JN		 4991 intel_opregion_notify_encoder(encoder, true);
4992 }
4f771f10 4993
e4916946
PZ		 4994 /* If we change the relative order between pipe/planes enabling, we need
4995 * to change the workaround. */
99d736a2
ML		 4996 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4997 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4998 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4999 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5000 }
4f771f10
PZ		 5001}
5002
3f8dce3a
DV		 5003static void ironlake_pfit_disable(struct intel_crtc *crtc)
5004{
5005 struct drm_device *dev = crtc->base.dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 int pipe = crtc->pipe;
5008
5009 /* To avoid upsetting the power well on haswell only disable the pfit if
5010 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5011 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5012 I915_WRITE(PF_CTL(pipe), 0);
5013 I915_WRITE(PF_WIN_POS(pipe), 0);
5014 I915_WRITE(PF_WIN_SZ(pipe), 0);
5015 }
5016}
5017
6be4a607
JB		 5018static void ironlake_crtc_disable(struct drm_crtc *crtc)
5019{
5020 struct drm_device *dev = crtc->dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5023 struct intel_encoder *encoder;
6be4a607 5024 int pipe = intel_crtc->pipe;
5eddb70b 5025 u32 reg, temp;
b52eb4dc 5026
ea9d758d
DV		 5027 for_each_encoder_on_crtc(dev, crtc, encoder)
5028 encoder->disable(encoder);
5029
f9b61ff6
DV		 5030 drm_crtc_vblank_off(crtc);
5031 assert_vblank_disabled(crtc);
5032
6e3c9717 5033 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5034 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5035
575f7ab7 5036 intel_disable_pipe(intel_crtc);
32f9d658 5037
3f8dce3a 5038 ironlake_pfit_disable(intel_crtc);
2c07245f 5039
5a74f70a
VS		 5040 if (intel_crtc->config->has_pch_encoder)
5041 ironlake_fdi_disable(crtc);
5042
bf49ec8c
DV		 5043 for_each_encoder_on_crtc(dev, crtc, encoder)
5044 if (encoder->post_disable)
5045 encoder->post_disable(encoder);
2c07245f 5046
6e3c9717 5047 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5048 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5049
d925c59a
DV		 5050 if (HAS_PCH_CPT(dev)) {
5051 /* disable TRANS_DP_CTL */
5052 reg = TRANS_DP_CTL(pipe);
5053 temp = I915_READ(reg);
5054 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5055 TRANS_DP_PORT_SEL_MASK);
5056 temp |= TRANS_DP_PORT_SEL_NONE;
5057 I915_WRITE(reg, temp);
5058
5059 /* disable DPLL_SEL */
5060 temp = I915_READ(PCH_DPLL_SEL);
11887397 5061 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5062 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5063 }
e3421a18 5064
d925c59a
DV		 5065 ironlake_fdi_pll_disable(intel_crtc);
5066 }
e4ca0612
PJ		 5067
5068 intel_crtc->active = false;
5069 intel_update_watermarks(crtc);
6be4a607 5070}
1b3c7a47 5071
4f771f10 5072static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5073{
4f771f10
PZ		 5074 struct drm_device *dev = crtc->dev;
5075 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5077 struct intel_encoder *encoder;
6e3c9717 5078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5079
8807e55b
JN		 5080 for_each_encoder_on_crtc(dev, crtc, encoder) {
5081 intel_opregion_notify_encoder(encoder, false);
4f771f10 5082 encoder->disable(encoder);
8807e55b 5083 }
4f771f10 5084
f9b61ff6
DV		 5085 drm_crtc_vblank_off(crtc);
5086 assert_vblank_disabled(crtc);
5087
6e3c9717 5088 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5089 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5090 false);
575f7ab7 5091 intel_disable_pipe(intel_crtc);
4f771f10 5092
6e3c9717 5093 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5094 intel_ddi_set_vc_payload_alloc(crtc, false);
5095
ad80a810 5096 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5097
ff6d9f55 5098 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5099 skylake_scaler_disable(intel_crtc);
ff6d9f55 5100 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5101 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5102 else
5103 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5104
1f544388 5105 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5106
6e3c9717 5107 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5108 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5109 intel_ddi_fdi_disable(crtc);
83616634 5110 }
4f771f10 5111
97b040aa
ID		 5112 for_each_encoder_on_crtc(dev, crtc, encoder)
5113 if (encoder->post_disable)
5114 encoder->post_disable(encoder);
e4ca0612
PJ		 5115
5116 intel_crtc->active = false;
5117 intel_update_watermarks(crtc);
4f771f10
PZ		 5118}
5119
2dd24552
JB		 5120static void i9xx_pfit_enable(struct intel_crtc *crtc)
5121{
5122 struct drm_device *dev = crtc->base.dev;
5123 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5124 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5125
681a8504 5126 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5127 return;
5128
2dd24552 5129 /*
c0b03411
DV		 5130 * The panel fitter should only be adjusted whilst the pipe is disabled,
5131 * according to register description and PRM.
2dd24552 5132 */
c0b03411
DV		 5133 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5134 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5135
b074cec8
JB		 5136 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5137 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5138
5139 /* Border color in case we don't scale up to the full screen. Black by
5140 * default, change to something else for debugging. */
5141 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5142}
5143
d05410f9
DA		 5144static enum intel_display_power_domain port_to_power_domain(enum port port)
5145{
5146 switch (port) {
5147 case PORT_A:
a513e3d7 5148 case PORT_E:
d05410f9
DA		 5149 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5150 case PORT_B:
5151 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5152 case PORT_C:
5153 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5154 case PORT_D:
5155 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5156 default:
5157 WARN_ON_ONCE(1);
5158 return POWER_DOMAIN_PORT_OTHER;
5159 }
5160}
5161
77d22dca
ID		 5162#define for_each_power_domain(domain, mask) \
5163 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5164 if ((1 << (domain)) & (mask))
5165
319be8ae
ID		 5166enum intel_display_power_domain
5167intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5168{
5169 struct drm_device *dev = intel_encoder->base.dev;
5170 struct intel_digital_port *intel_dig_port;
5171
5172 switch (intel_encoder->type) {
5173 case INTEL_OUTPUT_UNKNOWN:
5174 /* Only DDI platforms should ever use this output type */
5175 WARN_ON_ONCE(!HAS_DDI(dev));
5176 case INTEL_OUTPUT_DISPLAYPORT:
5177 case INTEL_OUTPUT_HDMI:
5178 case INTEL_OUTPUT_EDP:
5179 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5180 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5181 case INTEL_OUTPUT_DP_MST:
5182 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5183 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5184 case INTEL_OUTPUT_ANALOG:
5185 return POWER_DOMAIN_PORT_CRT;
5186 case INTEL_OUTPUT_DSI:
5187 return POWER_DOMAIN_PORT_DSI;
5188 default:
5189 return POWER_DOMAIN_PORT_OTHER;
5190 }
5191}
5192
5193static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5194{
319be8ae
ID		 5195 struct drm_device *dev = crtc->dev;
5196 struct intel_encoder *intel_encoder;
5197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5198 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5199 unsigned long mask;
5200 enum transcoder transcoder;
5201
292b990e
ML		 5202 if (!crtc->state->active)
5203 return 0;
5204
77d22dca
ID		 5205 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5206
5207 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5208 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5209 if (intel_crtc->config->pch_pfit.enabled ||
5210 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5211 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5212
319be8ae
ID		 5213 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5214 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5215
77d22dca
ID		 5216 return mask;
5217}
5218
292b990e 5219static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5220{
292b990e
ML		 5221 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 enum intel_display_power_domain domain;
5224 unsigned long domains, new_domains, old_domains;
77d22dca 5225
292b990e
ML		 5226 old_domains = intel_crtc->enabled_power_domains;
5227 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5228
292b990e
ML		 5229 domains = new_domains & ~old_domains;
5230
5231 for_each_power_domain(domain, domains)
5232 intel_display_power_get(dev_priv, domain);
5233
5234 return old_domains & ~new_domains;
5235}
5236
5237static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5238 unsigned long domains)
5239{
5240 enum intel_display_power_domain domain;
5241
5242 for_each_power_domain(domain, domains)
5243 intel_display_power_put(dev_priv, domain);
5244}
77d22dca 5245
292b990e
ML		 5246static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5247{
5248 struct drm_device *dev = state->dev;
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250 unsigned long put_domains[I915_MAX_PIPES] = {};
5251 struct drm_crtc_state *crtc_state;
5252 struct drm_crtc *crtc;
5253 int i;
77d22dca 5254
292b990e
ML		 5255 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5256 if (needs_modeset(crtc->state))
5257 put_domains[to_intel_crtc(crtc)->pipe] =
5258 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5259 }
5260
27c329ed
ML		 5261 if (dev_priv->display.modeset_commit_cdclk) {
5262 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5263
5264 if (cdclk != dev_priv->cdclk_freq &&
5265 !WARN_ON(!state->allow_modeset))
5266 dev_priv->display.modeset_commit_cdclk(state);
5267 }
50f6e502 5268
292b990e
ML		 5269 for (i = 0; i < I915_MAX_PIPES; i++)
5270 if (put_domains[i])
5271 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5272}
5273
560a7ae4
DL		 5274static void intel_update_max_cdclk(struct drm_device *dev)
5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277
5278 if (IS_SKYLAKE(dev)) {
5279 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5280
5281 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5282 dev_priv->max_cdclk_freq = 675000;
5283 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5284 dev_priv->max_cdclk_freq = 540000;
5285 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5286 dev_priv->max_cdclk_freq = 450000;
5287 else
5288 dev_priv->max_cdclk_freq = 337500;
5289 } else if (IS_BROADWELL(dev)) {
5290 /*
5291 * FIXME with extra cooling we can allow
5292 * 540 MHz for ULX and 675 Mhz for ULT.
5293 * How can we know if extra cooling is
5294 * available? PCI ID, VTB, something else?
5295 */
5296 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5297 dev_priv->max_cdclk_freq = 450000;
5298 else if (IS_BDW_ULX(dev))
5299 dev_priv->max_cdclk_freq = 450000;
5300 else if (IS_BDW_ULT(dev))
5301 dev_priv->max_cdclk_freq = 540000;
5302 else
5303 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5304 } else if (IS_CHERRYVIEW(dev)) {
5305 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5306 } else if (IS_VALLEYVIEW(dev)) {
5307 dev_priv->max_cdclk_freq = 400000;
5308 } else {
5309 /* otherwise assume cdclk is fixed */
5310 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5311 }
5312
5313 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5314 dev_priv->max_cdclk_freq);
5315}
5316
5317static void intel_update_cdclk(struct drm_device *dev)
5318{
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320
5321 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5322 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5323 dev_priv->cdclk_freq);
5324
5325 /*
5326 * Program the gmbus_freq based on the cdclk frequency.
5327 * BSpec erroneously claims we should aim for 4MHz, but
5328 * in fact 1MHz is the correct frequency.
5329 */
5330 if (IS_VALLEYVIEW(dev)) {
5331 /*
5332 * Program the gmbus_freq based on the cdclk frequency.
5333 * BSpec erroneously claims we should aim for 4MHz, but
5334 * in fact 1MHz is the correct frequency.
5335 */
5336 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5337 }
5338
5339 if (dev_priv->max_cdclk_freq == 0)
5340 intel_update_max_cdclk(dev);
5341}
5342
70d0c574 5343static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5344{
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346 uint32_t divider;
5347 uint32_t ratio;
5348 uint32_t current_freq;
5349 int ret;
5350
5351 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5352 switch (frequency) {
5353 case 144000:
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5355 ratio = BXT_DE_PLL_RATIO(60);
5356 break;
5357 case 288000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5359 ratio = BXT_DE_PLL_RATIO(60);
5360 break;
5361 case 384000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 576000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 624000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5371 ratio = BXT_DE_PLL_RATIO(65);
5372 break;
5373 case 19200:
5374 /*
5375 * Bypass frequency with DE PLL disabled. Init ratio, divider
5376 * to suppress GCC warning.
5377 */
5378 ratio = 0;
5379 divider = 0;
5380 break;
5381 default:
5382 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5383
5384 return;
5385 }
5386
5387 mutex_lock(&dev_priv->rps.hw_lock);
5388 /* Inform power controller of upcoming frequency change */
5389 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5390 0x80000000);
5391 mutex_unlock(&dev_priv->rps.hw_lock);
5392
5393 if (ret) {
5394 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5395 ret, frequency);
5396 return;
5397 }
5398
5399 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5400 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5401 current_freq = current_freq * 500 + 1000;
5402
5403 /*
5404 * DE PLL has to be disabled when
5405 * - setting to 19.2MHz (bypass, PLL isn't used)
5406 * - before setting to 624MHz (PLL needs toggling)
5407 * - before setting to any frequency from 624MHz (PLL needs toggling)
5408 */
5409 if (frequency == 19200 || frequency == 624000 ||
5410 current_freq == 624000) {
5411 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5412 /* Timeout 200us */
5413 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5414 1))
5415 DRM_ERROR("timout waiting for DE PLL unlock\n");
5416 }
5417
5418 if (frequency != 19200) {
5419 uint32_t val;
5420
5421 val = I915_READ(BXT_DE_PLL_CTL);
5422 val &= ~BXT_DE_PLL_RATIO_MASK;
5423 val |= ratio;
5424 I915_WRITE(BXT_DE_PLL_CTL, val);
5425
5426 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5427 /* Timeout 200us */
5428 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5429 DRM_ERROR("timeout waiting for DE PLL lock\n");
5430
5431 val = I915_READ(CDCLK_CTL);
5432 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5433 val |= divider;
5434 /*
5435 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5436 * enable otherwise.
5437 */
5438 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5439 if (frequency >= 500000)
5440 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5441
5442 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5443 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5444 val |= (frequency - 1000) / 500;
5445 I915_WRITE(CDCLK_CTL, val);
5446 }
5447
5448 mutex_lock(&dev_priv->rps.hw_lock);
5449 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5450 DIV_ROUND_UP(frequency, 25000));
5451 mutex_unlock(&dev_priv->rps.hw_lock);
5452
5453 if (ret) {
5454 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5455 ret, frequency);
5456 return;
5457 }
5458
a47871bd 5459 intel_update_cdclk(dev);
f8437dd1
VK		 5460}
5461
5462void broxton_init_cdclk(struct drm_device *dev)
5463{
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 uint32_t val;
5466
5467 /*
5468 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5469 * or else the reset will hang because there is no PCH to respond.
5470 * Move the handshake programming to initialization sequence.
5471 * Previously was left up to BIOS.
5472 */
5473 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5474 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5475 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5476
5477 /* Enable PG1 for cdclk */
5478 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5479
5480 /* check if cd clock is enabled */
5481 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5482 DRM_DEBUG_KMS("Display already initialized\n");
5483 return;
5484 }
5485
5486 /*
5487 * FIXME:
5488 * - The initial CDCLK needs to be read from VBT.
5489 * Need to make this change after VBT has changes for BXT.
5490 * - check if setting the max (or any) cdclk freq is really necessary
5491 * here, it belongs to modeset time
5492 */
5493 broxton_set_cdclk(dev, 624000);
5494
5495 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5496 POSTING_READ(DBUF_CTL);
5497
f8437dd1
VK		 5498 udelay(10);
5499
5500 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5501 DRM_ERROR("DBuf power enable timeout!\n");
5502}
5503
5504void broxton_uninit_cdclk(struct drm_device *dev)
5505{
5506 struct drm_i915_private *dev_priv = dev->dev_private;
5507
5508 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5509 POSTING_READ(DBUF_CTL);
5510
f8437dd1
VK		 5511 udelay(10);
5512
5513 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5514 DRM_ERROR("DBuf power disable timeout!\n");
5515
5516 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5517 broxton_set_cdclk(dev, 19200);
5518
5519 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5520}
5521
5d96d8af
DL		 5522static const struct skl_cdclk_entry {
5523 unsigned int freq;
5524 unsigned int vco;
5525} skl_cdclk_frequencies[] = {
5526 { .freq = 308570, .vco = 8640 },
5527 { .freq = 337500, .vco = 8100 },
5528 { .freq = 432000, .vco = 8640 },
5529 { .freq = 450000, .vco = 8100 },
5530 { .freq = 540000, .vco = 8100 },
5531 { .freq = 617140, .vco = 8640 },
5532 { .freq = 675000, .vco = 8100 },
5533};
5534
5535static unsigned int skl_cdclk_decimal(unsigned int freq)
5536{
5537 return (freq - 1000) / 500;
5538}
5539
5540static unsigned int skl_cdclk_get_vco(unsigned int freq)
5541{
5542 unsigned int i;
5543
5544 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5545 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5546
5547 if (e->freq == freq)
5548 return e->vco;
5549 }
5550
5551 return 8100;
5552}
5553
5554static void
5555skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5556{
5557 unsigned int min_freq;
5558 u32 val;
5559
5560 /* select the minimum CDCLK before enabling DPLL 0 */
5561 val = I915_READ(CDCLK_CTL);
5562 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5563 val |= CDCLK_FREQ_337_308;
5564
5565 if (required_vco == 8640)
5566 min_freq = 308570;
5567 else
5568 min_freq = 337500;
5569
5570 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5571
5572 I915_WRITE(CDCLK_CTL, val);
5573 POSTING_READ(CDCLK_CTL);
5574
5575 /*
5576 * We always enable DPLL0 with the lowest link rate possible, but still
5577 * taking into account the VCO required to operate the eDP panel at the
5578 * desired frequency. The usual DP link rates operate with a VCO of
5579 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5580 * The modeset code is responsible for the selection of the exact link
5581 * rate later on, with the constraint of choosing a frequency that
5582 * works with required_vco.
5583 */
5584 val = I915_READ(DPLL_CTRL1);
5585
5586 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5587 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5588 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5589 if (required_vco == 8640)
5590 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5591 SKL_DPLL0);
5592 else
5593 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5594 SKL_DPLL0);
5595
5596 I915_WRITE(DPLL_CTRL1, val);
5597 POSTING_READ(DPLL_CTRL1);
5598
5599 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5600
5601 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5602 DRM_ERROR("DPLL0 not locked\n");
5603}
5604
5605static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5606{
5607 int ret;
5608 u32 val;
5609
5610 /* inform PCU we want to change CDCLK */
5611 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5612 mutex_lock(&dev_priv->rps.hw_lock);
5613 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5614 mutex_unlock(&dev_priv->rps.hw_lock);
5615
5616 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5617}
5618
5619static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5620{
5621 unsigned int i;
5622
5623 for (i = 0; i < 15; i++) {
5624 if (skl_cdclk_pcu_ready(dev_priv))
5625 return true;
5626 udelay(10);
5627 }
5628
5629 return false;
5630}
5631
5632static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5633{
560a7ae4 5634 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5635 u32 freq_select, pcu_ack;
5636
5637 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5638
5639 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5640 DRM_ERROR("failed to inform PCU about cdclk change\n");
5641 return;
5642 }
5643
5644 /* set CDCLK_CTL */
5645 switch(freq) {
5646 case 450000:
5647 case 432000:
5648 freq_select = CDCLK_FREQ_450_432;
5649 pcu_ack = 1;
5650 break;
5651 case 540000:
5652 freq_select = CDCLK_FREQ_540;
5653 pcu_ack = 2;
5654 break;
5655 case 308570:
5656 case 337500:
5657 default:
5658 freq_select = CDCLK_FREQ_337_308;
5659 pcu_ack = 0;
5660 break;
5661 case 617140:
5662 case 675000:
5663 freq_select = CDCLK_FREQ_675_617;
5664 pcu_ack = 3;
5665 break;
5666 }
5667
5668 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5669 POSTING_READ(CDCLK_CTL);
5670
5671 /* inform PCU of the change */
5672 mutex_lock(&dev_priv->rps.hw_lock);
5673 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5674 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5675
5676 intel_update_cdclk(dev);
5d96d8af
DL		 5677}
5678
5679void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5680{
5681 /* disable DBUF power */
5682 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5683 POSTING_READ(DBUF_CTL);
5684
5685 udelay(10);
5686
5687 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5688 DRM_ERROR("DBuf power disable timeout\n");
5689
5690 /* disable DPLL0 */
5691 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5692 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5693 DRM_ERROR("Couldn't disable DPLL0\n");
5694
5695 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5696}
5697
5698void skl_init_cdclk(struct drm_i915_private *dev_priv)
5699{
5700 u32 val;
5701 unsigned int required_vco;
5702
5703 /* enable PCH reset handshake */
5704 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5705 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5706
5707 /* enable PG1 and Misc I/O */
5708 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5709
5710 /* DPLL0 already enabed !? */
5711 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5712 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5713 return;
5714 }
5715
5716 /* enable DPLL0 */
5717 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5718 skl_dpll0_enable(dev_priv, required_vco);
5719
5720 /* set CDCLK to the frequency the BIOS chose */
5721 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5722
5723 /* enable DBUF power */
5724 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5725 POSTING_READ(DBUF_CTL);
5726
5727 udelay(10);
5728
5729 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5730 DRM_ERROR("DBuf power enable timeout\n");
5731}
5732
dfcab17e 5733/* returns HPLL frequency in kHz */
f8bf63fd 5734static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5735{
586f49dc 5736 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5737
586f49dc 5738 /* Obtain SKU information */
a580516d 5739 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5740 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5741 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5742 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5743
dfcab17e 5744 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5745}
5746
5747/* Adjust CDclk dividers to allow high res or save power if possible */
5748static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5749{
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751 u32 val, cmd;
5752
164dfd28
VK		 5753 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5754 != dev_priv->cdclk_freq);
d60c4473 5755
dfcab17e 5756 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5757 cmd = 2;
dfcab17e 5758 else if (cdclk == 266667)
30a970c6
JB		 5759 cmd = 1;
5760 else
5761 cmd = 0;
5762
5763 mutex_lock(&dev_priv->rps.hw_lock);
5764 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5765 val &= ~DSPFREQGUAR_MASK;
5766 val |= (cmd << DSPFREQGUAR_SHIFT);
5767 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5768 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5769 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5770 50)) {
5771 DRM_ERROR("timed out waiting for CDclk change\n");
5772 }
5773 mutex_unlock(&dev_priv->rps.hw_lock);
5774
54433e91
VS		 5775 mutex_lock(&dev_priv->sb_lock);
5776
dfcab17e 5777 if (cdclk == 400000) {
6bcda4f0 5778 u32 divider;
30a970c6 5779
6bcda4f0 5780 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5781
30a970c6
JB		 5782 /* adjust cdclk divider */
5783 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5784 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5785 val |= divider;
5786 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5787
5788 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5789 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5790 50))
5791 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5792 }
5793
30a970c6
JB		 5794 /* adjust self-refresh exit latency value */
5795 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5796 val &= ~0x7f;
5797
5798 /*
5799 * For high bandwidth configs, we set a higher latency in the bunit
5800 * so that the core display fetch happens in time to avoid underruns.
5801 */
dfcab17e 5802 if (cdclk == 400000)
30a970c6
JB		 5803 val |= 4500 / 250; /* 4.5 usec */
5804 else
5805 val |= 3000 / 250; /* 3.0 usec */
5806 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5807
a580516d 5808 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5809
b6283055 5810 intel_update_cdclk(dev);
30a970c6
JB		 5811}
5812
383c5a6a
VS		 5813static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5814{
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 u32 val, cmd;
5817
164dfd28
VK		 5818 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5819 != dev_priv->cdclk_freq);
383c5a6a
VS		 5820
5821 switch (cdclk) {
383c5a6a
VS		 5822 case 333333:
5823 case 320000:
383c5a6a 5824 case 266667:
383c5a6a 5825 case 200000:
383c5a6a
VS		 5826 break;
5827 default:
5f77eeb0 5828 MISSING_CASE(cdclk);
383c5a6a
VS		 5829 return;
5830 }
5831
9d0d3fda
VS		 5832 /*
5833 * Specs are full of misinformation, but testing on actual
5834 * hardware has shown that we just need to write the desired
5835 * CCK divider into the Punit register.
5836 */
5837 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5838
383c5a6a
VS		 5839 mutex_lock(&dev_priv->rps.hw_lock);
5840 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5841 val &= ~DSPFREQGUAR_MASK_CHV;
5842 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5843 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5844 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5845 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5846 50)) {
5847 DRM_ERROR("timed out waiting for CDclk change\n");
5848 }
5849 mutex_unlock(&dev_priv->rps.hw_lock);
5850
b6283055 5851 intel_update_cdclk(dev);
383c5a6a
VS		 5852}
5853
30a970c6
JB		 5854static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5855 int max_pixclk)
5856{
6bcda4f0 5857 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5858 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5859
30a970c6
JB		 5860 /*
5861 * Really only a few cases to deal with, as only 4 CDclks are supported:
5862 * 200MHz
5863 * 267MHz
29dc7ef3 5864 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5865 * 400MHz (VLV only)
5866 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5867 * of the lower bin and adjust if needed.
e37c67a1
VS		 5868 *
5869 * We seem to get an unstable or solid color picture at 200MHz.
5870 * Not sure what's wrong. For now use 200MHz only when all pipes
5871 * are off.
30a970c6 5872 */
6cca3195
VS		 5873 if (!IS_CHERRYVIEW(dev_priv) &&
5874 max_pixclk > freq_320*limit/100)
dfcab17e 5875 return 400000;
6cca3195 5876 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5877 return freq_320;
e37c67a1 5878 else if (max_pixclk > 0)
dfcab17e 5879 return 266667;
e37c67a1
VS		 5880 else
5881 return 200000;
30a970c6
JB		 5882}
5883
f8437dd1
VK		 5884static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5885 int max_pixclk)
5886{
5887 /*
5888 * FIXME:
5889 * - remove the guardband, it's not needed on BXT
5890 * - set 19.2MHz bypass frequency if there are no active pipes
5891 */
5892 if (max_pixclk > 576000*9/10)
5893 return 624000;
5894 else if (max_pixclk > 384000*9/10)
5895 return 576000;
5896 else if (max_pixclk > 288000*9/10)
5897 return 384000;
5898 else if (max_pixclk > 144000*9/10)
5899 return 288000;
5900 else
5901 return 144000;
5902}
5903
a821fc46
ACO		 5904/* Compute the max pixel clock for new configuration. Uses atomic state if
5905 * that's non-NULL, look at current state otherwise. */
5906static int intel_mode_max_pixclk(struct drm_device *dev,
5907 struct drm_atomic_state *state)
30a970c6 5908{
30a970c6 5909 struct intel_crtc *intel_crtc;
304603f4 5910 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5911 int max_pixclk = 0;
5912
d3fcc808 5913 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5914 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5915 if (IS_ERR(crtc_state))
5916 return PTR_ERR(crtc_state);
5917
5918 if (!crtc_state->base.enable)
5919 continue;
5920
5921 max_pixclk = max(max_pixclk,
5922 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5923 }
5924
5925 return max_pixclk;
5926}
5927
27c329ed 5928static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5929{
27c329ed
ML		 5930 struct drm_device *dev = state->dev;
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5933
304603f4
ACO		 5934 if (max_pixclk < 0)
5935 return max_pixclk;
30a970c6 5936
27c329ed
ML		 5937 to_intel_atomic_state(state)->cdclk =
5938 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5939
27c329ed
ML		 5940 return 0;
5941}
304603f4 5942
27c329ed
ML		 5943static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5944{
5945 struct drm_device *dev = state->dev;
5946 struct drm_i915_private *dev_priv = dev->dev_private;
5947 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5948
27c329ed
ML		 5949 if (max_pixclk < 0)
5950 return max_pixclk;
85a96e7a 5951
27c329ed
ML		 5952 to_intel_atomic_state(state)->cdclk =
5953 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5954
27c329ed 5955 return 0;
30a970c6
JB		 5956}
5957
1e69cd74
VS		 5958static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5959{
5960 unsigned int credits, default_credits;
5961
5962 if (IS_CHERRYVIEW(dev_priv))
5963 default_credits = PFI_CREDIT(12);
5964 else
5965 default_credits = PFI_CREDIT(8);
5966
164dfd28 5967 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5968 /* CHV suggested value is 31 or 63 */
5969 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5970 credits = PFI_CREDIT_63;
1e69cd74
VS		 5971 else
5972 credits = PFI_CREDIT(15);
5973 } else {
5974 credits = default_credits;
5975 }
5976
5977 /*
5978 * WA - write default credits before re-programming
5979 * FIXME: should we also set the resend bit here?
5980 */
5981 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5982 default_credits);
5983
5984 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985 credits | PFI_CREDIT_RESEND);
5986
5987 /*
5988 * FIXME is this guaranteed to clear
5989 * immediately or should we poll for it?
5990 */
5991 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5992}
5993
27c329ed 5994static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5995{
a821fc46 5996 struct drm_device *dev = old_state->dev;
27c329ed 5997 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5998 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5999
27c329ed
ML		 6000 /*
6001 * FIXME: We can end up here with all power domains off, yet
6002 * with a CDCLK frequency other than the minimum. To account
6003 * for this take the PIPE-A power domain, which covers the HW
6004 * blocks needed for the following programming. This can be
6005 * removed once it's guaranteed that we get here either with
6006 * the minimum CDCLK set, or the required power domains
6007 * enabled.
6008 */
6009 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6010
27c329ed
ML		 6011 if (IS_CHERRYVIEW(dev))
6012 cherryview_set_cdclk(dev, req_cdclk);
6013 else
6014 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6015
27c329ed 6016 vlv_program_pfi_credits(dev_priv);
1e69cd74 6017
27c329ed 6018 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6019}
6020
89b667f8
JB		 6021static void valleyview_crtc_enable(struct drm_crtc *crtc)
6022{
6023 struct drm_device *dev = crtc->dev;
a72e4c9f 6024 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6026 struct intel_encoder *encoder;
6027 int pipe = intel_crtc->pipe;
23538ef1 6028 bool is_dsi;
89b667f8 6029
53d9f4e9 6030 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6031 return;
6032
409ee761 6033 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6034
1ae0d137
VS		 6035 if (!is_dsi) {
6036 if (IS_CHERRYVIEW(dev))
6e3c9717 6037 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6038 else
6e3c9717 6039 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6040 }
5b18e57c 6041
6e3c9717 6042 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6043 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6044
6045 intel_set_pipe_timings(intel_crtc);
6046
c14b0485
VS		 6047 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049
6050 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6051 I915_WRITE(CHV_CANVAS(pipe), 0);
6052 }
6053
5b18e57c
DV		 6054 i9xx_set_pipeconf(intel_crtc);
6055
89b667f8 6056 intel_crtc->active = true;
89b667f8 6057
a72e4c9f 6058 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6059
89b667f8
JB		 6060 for_each_encoder_on_crtc(dev, crtc, encoder)
6061 if (encoder->pre_pll_enable)
6062 encoder->pre_pll_enable(encoder);
6063
9d556c99
CML		 6064 if (!is_dsi) {
6065 if (IS_CHERRYVIEW(dev))
6e3c9717 6066 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6067 else
6e3c9717 6068 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6069 }
89b667f8
JB		 6070
6071 for_each_encoder_on_crtc(dev, crtc, encoder)
6072 if (encoder->pre_enable)
6073 encoder->pre_enable(encoder);
6074
2dd24552
JB		 6075 i9xx_pfit_enable(intel_crtc);
6076
63cbb074
VS		 6077 intel_crtc_load_lut(crtc);
6078
e1fdc473 6079 intel_enable_pipe(intel_crtc);
be6a6f8e 6080
4b3a9526
VS		 6081 assert_vblank_disabled(crtc);
6082 drm_crtc_vblank_on(crtc);
6083
f9b61ff6
DV		 6084 for_each_encoder_on_crtc(dev, crtc, encoder)
6085 encoder->enable(encoder);
89b667f8
JB		 6086}
6087
f13c2ef3
DV		 6088static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6089{
6090 struct drm_device *dev = crtc->base.dev;
6091 struct drm_i915_private *dev_priv = dev->dev_private;
6092
6e3c9717
ACO		 6093 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6094 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6095}
6096
0b8765c6 6097static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6098{
6099 struct drm_device *dev = crtc->dev;
a72e4c9f 6100 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6102 struct intel_encoder *encoder;
79e53945 6103 int pipe = intel_crtc->pipe;
79e53945 6104
53d9f4e9 6105 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6106 return;
6107
f13c2ef3
DV		 6108 i9xx_set_pll_dividers(intel_crtc);
6109
6e3c9717 6110 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6111 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6112
6113 intel_set_pipe_timings(intel_crtc);
6114
5b18e57c
DV		 6115 i9xx_set_pipeconf(intel_crtc);
6116
f7abfe8b 6117 intel_crtc->active = true;
6b383a7f 6118
4a3436e8 6119 if (!IS_GEN2(dev))
a72e4c9f 6120 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6121
9d6d9f19
MK		 6122 for_each_encoder_on_crtc(dev, crtc, encoder)
6123 if (encoder->pre_enable)
6124 encoder->pre_enable(encoder);
6125
f6736a1a
DV		 6126 i9xx_enable_pll(intel_crtc);
6127
2dd24552
JB		 6128 i9xx_pfit_enable(intel_crtc);
6129
63cbb074
VS		 6130 intel_crtc_load_lut(crtc);
6131
f37fcc2a 6132 intel_update_watermarks(crtc);
e1fdc473 6133 intel_enable_pipe(intel_crtc);
be6a6f8e 6134
4b3a9526
VS		 6135 assert_vblank_disabled(crtc);
6136 drm_crtc_vblank_on(crtc);
6137
f9b61ff6
DV		 6138 for_each_encoder_on_crtc(dev, crtc, encoder)
6139 encoder->enable(encoder);
0b8765c6 6140}
79e53945 6141
87476d63
DV		 6142static void i9xx_pfit_disable(struct intel_crtc *crtc)
6143{
6144 struct drm_device *dev = crtc->base.dev;
6145 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6146
6e3c9717 6147 if (!crtc->config->gmch_pfit.control)
328d8e82 6148 return;
87476d63 6149
328d8e82 6150 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6151
328d8e82
DV		 6152 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6153 I915_READ(PFIT_CONTROL));
6154 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6155}
6156
0b8765c6
JB		 6157static void i9xx_crtc_disable(struct drm_crtc *crtc)
6158{
6159 struct drm_device *dev = crtc->dev;
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6162 struct intel_encoder *encoder;
0b8765c6 6163 int pipe = intel_crtc->pipe;
ef9c3aee 6164
6304cd91
VS		 6165 /*
6166 * On gen2 planes are double buffered but the pipe isn't, so we must
6167 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6168 * We also need to wait on all gmch platforms because of the
6169 * self-refresh mode constraint explained above.
6304cd91 6170 */
564ed191 6171 intel_wait_for_vblank(dev, pipe);
6304cd91 6172
4b3a9526
VS		 6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 encoder->disable(encoder);
6175
f9b61ff6
DV		 6176 drm_crtc_vblank_off(crtc);
6177 assert_vblank_disabled(crtc);
6178
575f7ab7 6179 intel_disable_pipe(intel_crtc);
24a1f16d 6180
87476d63 6181 i9xx_pfit_disable(intel_crtc);
24a1f16d 6182
89b667f8
JB		 6183 for_each_encoder_on_crtc(dev, crtc, encoder)
6184 if (encoder->post_disable)
6185 encoder->post_disable(encoder);
6186
409ee761 6187 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6188 if (IS_CHERRYVIEW(dev))
6189 chv_disable_pll(dev_priv, pipe);
6190 else if (IS_VALLEYVIEW(dev))
6191 vlv_disable_pll(dev_priv, pipe);
6192 else
1c4e0274 6193 i9xx_disable_pll(intel_crtc);
076ed3b2 6194 }
0b8765c6 6195
4a3436e8 6196 if (!IS_GEN2(dev))
a72e4c9f 6197 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6198
6199 intel_crtc->active = false;
6200 intel_update_watermarks(crtc);
0b8765c6
JB		 6201}
6202
b17d48e2
ML		 6203static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6204{
6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6206 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6207 enum intel_display_power_domain domain;
6208 unsigned long domains;
6209
6210 if (!intel_crtc->active)
6211 return;
6212
a539205a
ML		 6213 if (to_intel_plane_state(crtc->primary->state)->visible) {
6214 intel_crtc_wait_for_pending_flips(crtc);
6215 intel_pre_disable_primary(crtc);
6216 }
6217
d032ffa0 6218 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6219 dev_priv->display.crtc_disable(crtc);
1f7457b1 6220 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6221
6222 domains = intel_crtc->enabled_power_domains;
6223 for_each_power_domain(domain, domains)
6224 intel_display_power_put(dev_priv, domain);
6225 intel_crtc->enabled_power_domains = 0;
6226}
6227
6b72d486
ML		 6228/*
6229 * turn all crtc's off, but do not adjust state
6230 * This has to be paired with a call to intel_modeset_setup_hw_state.
6231 */
70e0bd74 6232int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6233{
70e0bd74
ML		 6234 struct drm_mode_config *config = &dev->mode_config;
6235 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6236 struct drm_atomic_state *state;
6b72d486 6237 struct drm_crtc *crtc;
70e0bd74
ML		 6238 unsigned crtc_mask = 0;
6239 int ret = 0;
6240
6241 if (WARN_ON(!ctx))
6242 return 0;
6243
6244 lockdep_assert_held(&ctx->ww_ctx);
6245 state = drm_atomic_state_alloc(dev);
6246 if (WARN_ON(!state))
6247 return -ENOMEM;
6248
6249 state->acquire_ctx = ctx;
6250 state->allow_modeset = true;
6251
6252 for_each_crtc(dev, crtc) {
6253 struct drm_crtc_state *crtc_state =
6254 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6255
70e0bd74
ML		 6256 ret = PTR_ERR_OR_ZERO(crtc_state);
6257 if (ret)
6258 goto free;
6259
6260 if (!crtc_state->active)
6261 continue;
6262
6263 crtc_state->active = false;
6264 crtc_mask |= 1 << drm_crtc_index(crtc);
6265 }
6266
6267 if (crtc_mask) {
74c090b1 6268 ret = drm_atomic_commit(state);
70e0bd74
ML		 6269
6270 if (!ret) {
6271 for_each_crtc(dev, crtc)
6272 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6273 crtc->state->active = true;
6274
6275 return ret;
6276 }
6277 }
6278
6279free:
6280 if (ret)
6281 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6282 drm_atomic_state_free(state);
6283 return ret;
ee7b9f93
JB		 6284}
6285
ea5b213a 6286void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6287{
4ef69c7a 6288 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6289
ea5b213a
CW		 6290 drm_encoder_cleanup(encoder);
6291 kfree(intel_encoder);
7e7d76c3
JB		 6292}
6293
0a91ca29
DV		 6294/* Cross check the actual hw state with our own modeset state tracking (and it's
6295 * internal consistency). */
b980514c 6296static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6297{
35dd3c64
ML		 6298 struct drm_crtc *crtc = connector->base.state->crtc;
6299
6300 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6301 connector->base.base.id,
6302 connector->base.name);
6303
0a91ca29 6304 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6305 struct drm_encoder *encoder = &connector->encoder->base;
6306 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6307
35dd3c64
ML		 6308 I915_STATE_WARN(!crtc,
6309 "connector enabled without attached crtc\n");
0a91ca29 6310
35dd3c64
ML		 6311 if (!crtc)
6312 return;
6313
6314 I915_STATE_WARN(!crtc->state->active,
6315 "connector is active, but attached crtc isn't\n");
6316
6317 if (!encoder)
6318 return;
6319
6320 I915_STATE_WARN(conn_state->best_encoder != encoder,
6321 "atomic encoder doesn't match attached encoder\n");
6322
6323 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6324 "attached encoder crtc differs from connector crtc\n");
6325 } else {
4d688a2a
ML		 6326 I915_STATE_WARN(crtc && crtc->state->active,
6327 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6328 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6329 "best encoder set without crtc!\n");
0a91ca29 6330 }
79e53945
JB		 6331}
6332
08d9bc92
ACO		 6333int intel_connector_init(struct intel_connector *connector)
6334{
6335 struct drm_connector_state *connector_state;
6336
6337 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6338 if (!connector_state)
6339 return -ENOMEM;
6340
6341 connector->base.state = connector_state;
6342 return 0;
6343}
6344
6345struct intel_connector *intel_connector_alloc(void)
6346{
6347 struct intel_connector *connector;
6348
6349 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6350 if (!connector)
6351 return NULL;
6352
6353 if (intel_connector_init(connector) < 0) {
6354 kfree(connector);
6355 return NULL;
6356 }
6357
6358 return connector;
6359}
6360
f0947c37
DV		 6361/* Simple connector->get_hw_state implementation for encoders that support only
6362 * one connector and no cloning and hence the encoder state determines the state
6363 * of the connector. */
6364bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6365{
24929352 6366 enum pipe pipe = 0;
f0947c37 6367 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6368
f0947c37 6369 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6370}
6371
6d293983 6372static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6373{
6d293983
ACO		 6374 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6375 return crtc_state->fdi_lanes;
d272ddfa
VS		 6376
6377 return 0;
6378}
6379
6d293983 6380static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6381 struct intel_crtc_state *pipe_config)
1857e1da 6382{
6d293983
ACO		 6383 struct drm_atomic_state *state = pipe_config->base.state;
6384 struct intel_crtc *other_crtc;
6385 struct intel_crtc_state *other_crtc_state;
6386
1857e1da
DV		 6387 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6388 pipe_name(pipe), pipe_config->fdi_lanes);
6389 if (pipe_config->fdi_lanes > 4) {
6390 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6391 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6392 return -EINVAL;
1857e1da
DV		 6393 }
6394
bafb6553 6395 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6396 if (pipe_config->fdi_lanes > 2) {
6397 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6398 pipe_config->fdi_lanes);
6d293983 6399 return -EINVAL;
1857e1da 6400 } else {
6d293983 6401 return 0;
1857e1da
DV		 6402 }
6403 }
6404
6405 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6406 return 0;
1857e1da
DV		 6407
6408 /* Ivybridge 3 pipe is really complicated */
6409 switch (pipe) {
6410 case PIPE_A:
6d293983 6411 return 0;
1857e1da 6412 case PIPE_B:
6d293983
ACO		 6413 if (pipe_config->fdi_lanes <= 2)
6414 return 0;
6415
6416 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6417 other_crtc_state =
6418 intel_atomic_get_crtc_state(state, other_crtc);
6419 if (IS_ERR(other_crtc_state))
6420 return PTR_ERR(other_crtc_state);
6421
6422 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6423 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6424 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6425 return -EINVAL;
1857e1da 6426 }
6d293983 6427 return 0;
1857e1da 6428 case PIPE_C:
251cc67c
VS		 6429 if (pipe_config->fdi_lanes > 2) {
6430 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6431 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6432 return -EINVAL;
251cc67c 6433 }
6d293983
ACO		 6434
6435 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6436 other_crtc_state =
6437 intel_atomic_get_crtc_state(state, other_crtc);
6438 if (IS_ERR(other_crtc_state))
6439 return PTR_ERR(other_crtc_state);
6440
6441 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6442 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6443 return -EINVAL;
1857e1da 6444 }
6d293983 6445 return 0;
1857e1da
DV		 6446 default:
6447 BUG();
6448 }
6449}
6450
e29c22c0
DV		 6451#define RETRY 1
6452static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6453 struct intel_crtc_state *pipe_config)
877d48d5 6454{
1857e1da 6455 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6456 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6457 int lane, link_bw, fdi_dotclock, ret;
6458 bool needs_recompute = false;
877d48d5 6459
e29c22c0 6460retry:
877d48d5
DV		 6461 /* FDI is a binary signal running at ~2.7GHz, encoding
6462 * each output octet as 10 bits. The actual frequency
6463 * is stored as a divider into a 100MHz clock, and the
6464 * mode pixel clock is stored in units of 1KHz.
6465 * Hence the bw of each lane in terms of the mode signal
6466 * is:
6467 */
6468 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6469
241bfc38 6470 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6471
2bd89a07 6472 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6473 pipe_config->pipe_bpp);
6474
6475 pipe_config->fdi_lanes = lane;
6476
2bd89a07 6477 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6478 link_bw, &pipe_config->fdi_m_n);
1857e1da 6479
6d293983
ACO		 6480 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6481 intel_crtc->pipe, pipe_config);
6482 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6483 pipe_config->pipe_bpp -= 2*3;
6484 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6485 pipe_config->pipe_bpp);
6486 needs_recompute = true;
6487 pipe_config->bw_constrained = true;
6488
6489 goto retry;
6490 }
6491
6492 if (needs_recompute)
6493 return RETRY;
6494
6d293983 6495 return ret;
877d48d5
DV		 6496}
6497
8cfb3407
VS		 6498static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6499 struct intel_crtc_state *pipe_config)
6500{
6501 if (pipe_config->pipe_bpp > 24)
6502 return false;
6503
6504 /* HSW can handle pixel rate up to cdclk? */
6505 if (IS_HASWELL(dev_priv->dev))
6506 return true;
6507
6508 /*
b432e5cf
VS		 6509 * We compare against max which means we must take
6510 * the increased cdclk requirement into account when
6511 * calculating the new cdclk.
6512 *
6513 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6514 */
6515 return ilk_pipe_pixel_rate(pipe_config) <=
6516 dev_priv->max_cdclk_freq * 95 / 100;
6517}
6518
42db64ef 6519static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6520 struct intel_crtc_state *pipe_config)
42db64ef 6521{
8cfb3407
VS		 6522 struct drm_device *dev = crtc->base.dev;
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524
d330a953 6525 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6526 hsw_crtc_supports_ips(crtc) &&
6527 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6528}
6529
a43f6e0f 6530static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6531 struct intel_crtc_state *pipe_config)
79e53945 6532{
a43f6e0f 6533 struct drm_device *dev = crtc->base.dev;
8bd31e67 6534 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6535 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6536
ad3a4479 6537 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6538 if (INTEL_INFO(dev)->gen < 4) {
44913155 6539 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6540
6541 /*
6542 * Enable pixel doubling when the dot clock
6543 * is > 90% of the (display) core speed.
6544 *
b397c96b
VS		 6545 * GDG double wide on either pipe,
6546 * otherwise pipe A only.
cf532bb2 6547 */
b397c96b 6548 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6549 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6550 clock_limit *= 2;
cf532bb2 6551 pipe_config->double_wide = true;
ad3a4479
VS		 6552 }
6553
241bfc38 6554 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6555 return -EINVAL;
2c07245f 6556 }
89749350 6557
1d1d0e27
VS		 6558 /*
6559 * Pipe horizontal size must be even in:
6560 * - DVO ganged mode
6561 * - LVDS dual channel mode
6562 * - Double wide pipe
6563 */
a93e255f 6564 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6565 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6566 pipe_config->pipe_src_w &= ~1;
6567
8693a824
DL		 6568 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6569 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6570 */
6571 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6572 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6573 return -EINVAL;
44f46b42 6574
f5adf94e 6575 if (HAS_IPS(dev))
a43f6e0f
DV		 6576 hsw_compute_ips_config(crtc, pipe_config);
6577
877d48d5 6578 if (pipe_config->has_pch_encoder)
a43f6e0f 6579 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6580
cf5a15be 6581 return 0;
79e53945
JB		 6582}
6583
1652d19e
VS		 6584static int skylake_get_display_clock_speed(struct drm_device *dev)
6585{
6586 struct drm_i915_private *dev_priv = to_i915(dev);
6587 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6588 uint32_t cdctl = I915_READ(CDCLK_CTL);
6589 uint32_t linkrate;
6590
414355a7 6591 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6592 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6593
6594 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6595 return 540000;
6596
6597 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6598 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6599
71cd8423
DL		 6600 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6601 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6602 /* vco 8640 */
6603 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6604 case CDCLK_FREQ_450_432:
6605 return 432000;
6606 case CDCLK_FREQ_337_308:
6607 return 308570;
6608 case CDCLK_FREQ_675_617:
6609 return 617140;
6610 default:
6611 WARN(1, "Unknown cd freq selection\n");
6612 }
6613 } else {
6614 /* vco 8100 */
6615 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6616 case CDCLK_FREQ_450_432:
6617 return 450000;
6618 case CDCLK_FREQ_337_308:
6619 return 337500;
6620 case CDCLK_FREQ_675_617:
6621 return 675000;
6622 default:
6623 WARN(1, "Unknown cd freq selection\n");
6624 }
6625 }
6626
6627 /* error case, do as if DPLL0 isn't enabled */
6628 return 24000;
6629}
6630
acd3f3d3
BP		 6631static int broxton_get_display_clock_speed(struct drm_device *dev)
6632{
6633 struct drm_i915_private *dev_priv = to_i915(dev);
6634 uint32_t cdctl = I915_READ(CDCLK_CTL);
6635 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6636 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6637 int cdclk;
6638
6639 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6640 return 19200;
6641
6642 cdclk = 19200 * pll_ratio / 2;
6643
6644 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6645 case BXT_CDCLK_CD2X_DIV_SEL_1:
6646 return cdclk; /* 576MHz or 624MHz */
6647 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6648 return cdclk * 2 / 3; /* 384MHz */
6649 case BXT_CDCLK_CD2X_DIV_SEL_2:
6650 return cdclk / 2; /* 288MHz */
6651 case BXT_CDCLK_CD2X_DIV_SEL_4:
6652 return cdclk / 4; /* 144MHz */
6653 }
6654
6655 /* error case, do as if DE PLL isn't enabled */
6656 return 19200;
6657}
6658
1652d19e
VS		 6659static int broadwell_get_display_clock_speed(struct drm_device *dev)
6660{
6661 struct drm_i915_private *dev_priv = dev->dev_private;
6662 uint32_t lcpll = I915_READ(LCPLL_CTL);
6663 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6664
6665 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6666 return 800000;
6667 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6668 return 450000;
6669 else if (freq == LCPLL_CLK_FREQ_450)
6670 return 450000;
6671 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6672 return 540000;
6673 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6674 return 337500;
6675 else
6676 return 675000;
6677}
6678
6679static int haswell_get_display_clock_speed(struct drm_device *dev)
6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 uint32_t lcpll = I915_READ(LCPLL_CTL);
6683 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6684
6685 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6686 return 800000;
6687 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6688 return 450000;
6689 else if (freq == LCPLL_CLK_FREQ_450)
6690 return 450000;
6691 else if (IS_HSW_ULT(dev))
6692 return 337500;
6693 else
6694 return 540000;
79e53945
JB		 6695}
6696
25eb05fc
JB		 6697static int valleyview_get_display_clock_speed(struct drm_device *dev)
6698{
d197b7d3 6699 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6700 u32 val;
6701 int divider;
6702
6bcda4f0
VS		 6703 if (dev_priv->hpll_freq == 0)
6704 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6705
a580516d 6706 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6707 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6708 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6709
6710 divider = val & DISPLAY_FREQUENCY_VALUES;
6711
7d007f40
VS		 6712 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6713 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6714 "cdclk change in progress\n");
6715
6bcda4f0 6716 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6717}
6718
b37a6434
VS		 6719static int ilk_get_display_clock_speed(struct drm_device *dev)
6720{
6721 return 450000;
6722}
6723
e70236a8
JB		 6724static int i945_get_display_clock_speed(struct drm_device *dev)
6725{
6726 return 400000;
6727}
79e53945 6728
e70236a8 6729static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6730{
e907f170 6731 return 333333;
e70236a8 6732}
79e53945 6733
e70236a8
JB		 6734static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6735{
6736 return 200000;
6737}
79e53945 6738
257a7ffc
DV		 6739static int pnv_get_display_clock_speed(struct drm_device *dev)
6740{
6741 u16 gcfgc = 0;
6742
6743 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6744
6745 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6746 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6747 return 266667;
257a7ffc 6748 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6749 return 333333;
257a7ffc 6750 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6751 return 444444;
257a7ffc
DV		 6752 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6753 return 200000;
6754 default:
6755 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6756 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6757 return 133333;
257a7ffc 6758 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6759 return 166667;
257a7ffc
DV		 6760 }
6761}
6762
e70236a8
JB		 6763static int i915gm_get_display_clock_speed(struct drm_device *dev)
6764{
6765 u16 gcfgc = 0;
79e53945 6766
e70236a8
JB		 6767 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6768
6769 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6770 return 133333;
e70236a8
JB		 6771 else {
6772 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6773 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6774 return 333333;
e70236a8
JB		 6775 default:
6776 case GC_DISPLAY_CLOCK_190_200_MHZ:
6777 return 190000;
79e53945 6778 }
e70236a8
JB		 6779 }
6780}
6781
6782static int i865_get_display_clock_speed(struct drm_device *dev)
6783{
e907f170 6784 return 266667;
e70236a8
JB		 6785}
6786
1b1d2716 6787static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6788{
6789 u16 hpllcc = 0;
1b1d2716 6790
65cd2b3f
VS		 6791 /*
6792 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6793 * encoding is different :(
6794 * FIXME is this the right way to detect 852GM/852GMV?
6795 */
6796 if (dev->pdev->revision == 0x1)
6797 return 133333;
6798
1b1d2716
VS		 6799 pci_bus_read_config_word(dev->pdev->bus,
6800 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6801
e70236a8
JB		 6802 /* Assume that the hardware is in the high speed state. This
6803 * should be the default.
6804 */
6805 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6806 case GC_CLOCK_133_200:
1b1d2716 6807 case GC_CLOCK_133_200_2:
e70236a8
JB		 6808 case GC_CLOCK_100_200:
6809 return 200000;
6810 case GC_CLOCK_166_250:
6811 return 250000;
6812 case GC_CLOCK_100_133:
e907f170 6813 return 133333;
1b1d2716
VS		 6814 case GC_CLOCK_133_266:
6815 case GC_CLOCK_133_266_2:
6816 case GC_CLOCK_166_266:
6817 return 266667;
e70236a8 6818 }
79e53945 6819
e70236a8
JB		 6820 /* Shouldn't happen */
6821 return 0;
6822}
79e53945 6823
e70236a8
JB		 6824static int i830_get_display_clock_speed(struct drm_device *dev)
6825{
e907f170 6826 return 133333;
79e53945
JB		 6827}
6828
34edce2f
VS		 6829static unsigned int intel_hpll_vco(struct drm_device *dev)
6830{
6831 struct drm_i915_private *dev_priv = dev->dev_private;
6832 static const unsigned int blb_vco[8] = {
6833 [0] = 3200000,
6834 [1] = 4000000,
6835 [2] = 5333333,
6836 [3] = 4800000,
6837 [4] = 6400000,
6838 };
6839 static const unsigned int pnv_vco[8] = {
6840 [0] = 3200000,
6841 [1] = 4000000,
6842 [2] = 5333333,
6843 [3] = 4800000,
6844 [4] = 2666667,
6845 };
6846 static const unsigned int cl_vco[8] = {
6847 [0] = 3200000,
6848 [1] = 4000000,
6849 [2] = 5333333,
6850 [3] = 6400000,
6851 [4] = 3333333,
6852 [5] = 3566667,
6853 [6] = 4266667,
6854 };
6855 static const unsigned int elk_vco[8] = {
6856 [0] = 3200000,
6857 [1] = 4000000,
6858 [2] = 5333333,
6859 [3] = 4800000,
6860 };
6861 static const unsigned int ctg_vco[8] = {
6862 [0] = 3200000,
6863 [1] = 4000000,
6864 [2] = 5333333,
6865 [3] = 6400000,
6866 [4] = 2666667,
6867 [5] = 4266667,
6868 };
6869 const unsigned int *vco_table;
6870 unsigned int vco;
6871 uint8_t tmp = 0;
6872
6873 /* FIXME other chipsets? */
6874 if (IS_GM45(dev))
6875 vco_table = ctg_vco;
6876 else if (IS_G4X(dev))
6877 vco_table = elk_vco;
6878 else if (IS_CRESTLINE(dev))
6879 vco_table = cl_vco;
6880 else if (IS_PINEVIEW(dev))
6881 vco_table = pnv_vco;
6882 else if (IS_G33(dev))
6883 vco_table = blb_vco;
6884 else
6885 return 0;
6886
6887 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6888
6889 vco = vco_table[tmp & 0x7];
6890 if (vco == 0)
6891 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6892 else
6893 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6894
6895 return vco;
6896}
6897
6898static int gm45_get_display_clock_speed(struct drm_device *dev)
6899{
6900 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6901 uint16_t tmp = 0;
6902
6903 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6904
6905 cdclk_sel = (tmp >> 12) & 0x1;
6906
6907 switch (vco) {
6908 case 2666667:
6909 case 4000000:
6910 case 5333333:
6911 return cdclk_sel ? 333333 : 222222;
6912 case 3200000:
6913 return cdclk_sel ? 320000 : 228571;
6914 default:
6915 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6916 return 222222;
6917 }
6918}
6919
6920static int i965gm_get_display_clock_speed(struct drm_device *dev)
6921{
6922 static const uint8_t div_3200[] = { 16, 10, 8 };
6923 static const uint8_t div_4000[] = { 20, 12, 10 };
6924 static const uint8_t div_5333[] = { 24, 16, 14 };
6925 const uint8_t *div_table;
6926 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6927 uint16_t tmp = 0;
6928
6929 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6930
6931 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6932
6933 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6934 goto fail;
6935
6936 switch (vco) {
6937 case 3200000:
6938 div_table = div_3200;
6939 break;
6940 case 4000000:
6941 div_table = div_4000;
6942 break;
6943 case 5333333:
6944 div_table = div_5333;
6945 break;
6946 default:
6947 goto fail;
6948 }
6949
6950 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6951
caf4e252 6952fail:
34edce2f
VS		 6953 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6954 return 200000;
6955}
6956
6957static int g33_get_display_clock_speed(struct drm_device *dev)
6958{
6959 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6960 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6961 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6962 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6963 const uint8_t *div_table;
6964 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965 uint16_t tmp = 0;
6966
6967 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969 cdclk_sel = (tmp >> 4) & 0x7;
6970
6971 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6972 goto fail;
6973
6974 switch (vco) {
6975 case 3200000:
6976 div_table = div_3200;
6977 break;
6978 case 4000000:
6979 div_table = div_4000;
6980 break;
6981 case 4800000:
6982 div_table = div_4800;
6983 break;
6984 case 5333333:
6985 div_table = div_5333;
6986 break;
6987 default:
6988 goto fail;
6989 }
6990
6991 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6992
caf4e252 6993fail:
34edce2f
VS		 6994 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6995 return 190476;
6996}
6997
2c07245f 6998static void
a65851af 6999intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7000{
a65851af
VS		 7001 while (*num > DATA_LINK_M_N_MASK ||
7002 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7003 *num >>= 1;
7004 *den >>= 1;
7005 }
7006}
7007
a65851af
VS		 7008static void compute_m_n(unsigned int m, unsigned int n,
7009 uint32_t *ret_m, uint32_t *ret_n)
7010{
7011 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7012 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7013 intel_reduce_m_n_ratio(ret_m, ret_n);
7014}
7015
e69d0bc1
DV		 7016void
7017intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7018 int pixel_clock, int link_clock,
7019 struct intel_link_m_n *m_n)
2c07245f 7020{
e69d0bc1 7021 m_n->tu = 64;
a65851af
VS		 7022
7023 compute_m_n(bits_per_pixel * pixel_clock,
7024 link_clock * nlanes * 8,
7025 &m_n->gmch_m, &m_n->gmch_n);
7026
7027 compute_m_n(pixel_clock, link_clock,
7028 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7029}
7030
a7615030
CW		 7031static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7032{
d330a953
JN		 7033 if (i915.panel_use_ssc >= 0)
7034 return i915.panel_use_ssc != 0;
41aa3448 7035 return dev_priv->vbt.lvds_use_ssc
435793df 7036 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7037}
7038
a93e255f
ACO		 7039static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7040 int num_connectors)
c65d77d8 7041{
a93e255f 7042 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7043 struct drm_i915_private *dev_priv = dev->dev_private;
7044 int refclk;
7045
a93e255f
ACO		 7046 WARN_ON(!crtc_state->base.state);
7047
5ab7b0b7 7048 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7049 refclk = 100000;
a93e255f 7050 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7051 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7052 refclk = dev_priv->vbt.lvds_ssc_freq;
7053 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7054 } else if (!IS_GEN2(dev)) {
7055 refclk = 96000;
7056 } else {
7057 refclk = 48000;
7058 }
7059
7060 return refclk;
7061}
7062
7429e9d4 7063static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7064{
7df00d7a 7065 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7066}
f47709a9 7067
7429e9d4
DV		 7068static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7069{
7070 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7071}
7072
f47709a9 7073static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7074 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7075 intel_clock_t *reduced_clock)
7076{
f47709a9 7077 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7078 u32 fp, fp2 = 0;
7079
7080 if (IS_PINEVIEW(dev)) {
190f68c5 7081 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7082 if (reduced_clock)
7429e9d4 7083 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7084 } else {
190f68c5 7085 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7086 if (reduced_clock)
7429e9d4 7087 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7088 }
7089
190f68c5 7090 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7091
f47709a9 7092 crtc->lowfreq_avail = false;
a93e255f 7093 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7094 reduced_clock) {
190f68c5 7095 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7096 crtc->lowfreq_avail = true;
a7516a05 7097 } else {
190f68c5 7098 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7099 }
7100}
7101
5e69f97f
CML		 7102static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7103 pipe)
89b667f8
JB		 7104{
7105 u32 reg_val;
7106
7107 /*
7108 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7109 * and set it to a reasonable value instead.
7110 */
ab3c759a 7111 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7112 reg_val &= 0xffffff00;
7113 reg_val |= 0x00000030;
ab3c759a 7114 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7115
ab3c759a 7116 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7117 reg_val &= 0x8cffffff;
7118 reg_val = 0x8c000000;
ab3c759a 7119 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7120
ab3c759a 7121 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7122 reg_val &= 0xffffff00;
ab3c759a 7123 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7124
ab3c759a 7125 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7126 reg_val &= 0x00ffffff;
7127 reg_val |= 0xb0000000;
ab3c759a 7128 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7129}
7130
b551842d
DV		 7131static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7132 struct intel_link_m_n *m_n)
7133{
7134 struct drm_device *dev = crtc->base.dev;
7135 struct drm_i915_private *dev_priv = dev->dev_private;
7136 int pipe = crtc->pipe;
7137
e3b95f1e
DV		 7138 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7139 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7140 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7141 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7142}
7143
7144static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7145 struct intel_link_m_n *m_n,
7146 struct intel_link_m_n *m2_n2)
b551842d
DV		 7147{
7148 struct drm_device *dev = crtc->base.dev;
7149 struct drm_i915_private *dev_priv = dev->dev_private;
7150 int pipe = crtc->pipe;
6e3c9717 7151 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7152
7153 if (INTEL_INFO(dev)->gen >= 5) {
7154 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7155 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7156 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7157 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7158 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7159 * for gen < 8) and if DRRS is supported (to make sure the
7160 * registers are not unnecessarily accessed).
7161 */
44395bfe 7162 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7163 crtc->config->has_drrs) {
f769cd24
VK		 7164 I915_WRITE(PIPE_DATA_M2(transcoder),
7165 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7166 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7167 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7168 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7169 }
b551842d 7170 } else {
e3b95f1e
DV		 7171 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7173 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7174 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7175 }
7176}
7177
fe3cd48d 7178void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7179{
fe3cd48d
R		 7180 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7181
7182 if (m_n == M1_N1) {
7183 dp_m_n = &crtc->config->dp_m_n;
7184 dp_m2_n2 = &crtc->config->dp_m2_n2;
7185 } else if (m_n == M2_N2) {
7186
7187 /*
7188 * M2_N2 registers are not supported. Hence m2_n2 divider value
7189 * needs to be programmed into M1_N1.
7190 */
7191 dp_m_n = &crtc->config->dp_m2_n2;
7192 } else {
7193 DRM_ERROR("Unsupported divider value\n");
7194 return;
7195 }
7196
6e3c9717
ACO		 7197 if (crtc->config->has_pch_encoder)
7198 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7199 else
fe3cd48d 7200 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7201}
7202
251ac862
DV		 7203static void vlv_compute_dpll(struct intel_crtc *crtc,
7204 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7205{
7206 u32 dpll, dpll_md;
7207
7208 /*
7209 * Enable DPIO clock input. We should never disable the reference
7210 * clock for pipe B, since VGA hotplug / manual detection depends
7211 * on it.
7212 */
60bfe44f
VS		 7213 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7214 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7215 /* We should never disable this, set it here for state tracking */
7216 if (crtc->pipe == PIPE_B)
7217 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7218 dpll |= DPLL_VCO_ENABLE;
d288f65f 7219 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7220
d288f65f 7221 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7222 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7223 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7224}
7225
d288f65f 7226static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7227 const struct intel_crtc_state *pipe_config)
a0c4da24 7228{
f47709a9 7229 struct drm_device *dev = crtc->base.dev;
a0c4da24 7230 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7231 int pipe = crtc->pipe;
bdd4b6a6 7232 u32 mdiv;
a0c4da24 7233 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7234 u32 coreclk, reg_val;
a0c4da24 7235
a580516d 7236 mutex_lock(&dev_priv->sb_lock);
09153000 7237
d288f65f
VS		 7238 bestn = pipe_config->dpll.n;
7239 bestm1 = pipe_config->dpll.m1;
7240 bestm2 = pipe_config->dpll.m2;
7241 bestp1 = pipe_config->dpll.p1;
7242 bestp2 = pipe_config->dpll.p2;
a0c4da24 7243
89b667f8
JB		 7244 /* See eDP HDMI DPIO driver vbios notes doc */
7245
7246 /* PLL B needs special handling */
bdd4b6a6 7247 if (pipe == PIPE_B)
5e69f97f 7248 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7249
7250 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7251 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7252
7253 /* Disable target IRef on PLL */
ab3c759a 7254 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7255 reg_val &= 0x00ffffff;
ab3c759a 7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7257
7258 /* Disable fast lock */
ab3c759a 7259 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7260
7261 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7262 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7263 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7264 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7265 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7266
7267 /*
7268 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7269 * but we don't support that).
7270 * Note: don't use the DAC post divider as it seems unstable.
7271 */
7272 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7274
a0c4da24 7275 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7277
89b667f8 7278 /* Set HBR and RBR LPF coefficients */
d288f65f 7279 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7280 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7283 0x009f0003);
89b667f8 7284 else
ab3c759a 7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7286 0x00d0000f);
7287
681a8504 7288 if (pipe_config->has_dp_encoder) {
89b667f8 7289 /* Use SSC source */
bdd4b6a6 7290 if (pipe == PIPE_A)
ab3c759a 7291 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7292 0x0df40000);
7293 else
ab3c759a 7294 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7295 0x0df70000);
7296 } else { /* HDMI or VGA */
7297 /* Use bend source */
bdd4b6a6 7298 if (pipe == PIPE_A)
ab3c759a 7299 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7300 0x0df70000);
7301 else
ab3c759a 7302 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7303 0x0df40000);
7304 }
a0c4da24 7305
ab3c759a 7306 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7307 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7308 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7309 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7310 coreclk |= 0x01000000;
ab3c759a 7311 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7312
ab3c759a 7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7314 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7315}
7316
251ac862
DV		 7317static void chv_compute_dpll(struct intel_crtc *crtc,
7318 struct intel_crtc_state *pipe_config)
1ae0d137 7319{
60bfe44f
VS		 7320 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7321 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7322 DPLL_VCO_ENABLE;
7323 if (crtc->pipe != PIPE_A)
d288f65f 7324 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7325
d288f65f
VS		 7326 pipe_config->dpll_hw_state.dpll_md =
7327 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7328}
7329
d288f65f 7330static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7331 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7332{
7333 struct drm_device *dev = crtc->base.dev;
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 int pipe = crtc->pipe;
7336 int dpll_reg = DPLL(crtc->pipe);
7337 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7338 u32 loopfilter, tribuf_calcntr;
9d556c99 7339 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7340 u32 dpio_val;
9cbe40c1 7341 int vco;
9d556c99 7342
d288f65f
VS		 7343 bestn = pipe_config->dpll.n;
7344 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7345 bestm1 = pipe_config->dpll.m1;
7346 bestm2 = pipe_config->dpll.m2 >> 22;
7347 bestp1 = pipe_config->dpll.p1;
7348 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7349 vco = pipe_config->dpll.vco;
a945ce7e 7350 dpio_val = 0;
9cbe40c1 7351 loopfilter = 0;
9d556c99
CML		 7352
7353 /*
7354 * Enable Refclk and SSC
7355 */
a11b0703 7356 I915_WRITE(dpll_reg,
d288f65f 7357 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7358
a580516d 7359 mutex_lock(&dev_priv->sb_lock);
9d556c99 7360
9d556c99
CML		 7361 /* p1 and p2 divider */
7362 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7363 5 << DPIO_CHV_S1_DIV_SHIFT |
7364 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7365 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7366 1 << DPIO_CHV_K_DIV_SHIFT);
7367
7368 /* Feedback post-divider - m2 */
7369 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7370
7371 /* Feedback refclk divider - n and m1 */
7372 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7373 DPIO_CHV_M1_DIV_BY_2 |
7374 1 << DPIO_CHV_N_DIV_SHIFT);
7375
7376 /* M2 fraction division */
a945ce7e
VP		 7377 if (bestm2_frac)
7378 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7379
7380 /* M2 fraction division enable */
a945ce7e
VP		 7381 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7382 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7383 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7384 if (bestm2_frac)
7385 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7387
de3a0fde
VP		 7388 /* Program digital lock detect threshold */
7389 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7390 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7391 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7392 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7393 if (!bestm2_frac)
7394 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7396
9d556c99 7397 /* Loop filter */
9cbe40c1
VP		 7398 if (vco == 5400000) {
7399 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7400 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7401 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7402 tribuf_calcntr = 0x9;
7403 } else if (vco <= 6200000) {
7404 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7405 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7406 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7407 tribuf_calcntr = 0x9;
7408 } else if (vco <= 6480000) {
7409 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7410 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7411 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7412 tribuf_calcntr = 0x8;
7413 } else {
7414 /* Not supported. Apply the same limits as in the max case */
7415 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7416 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7417 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7418 tribuf_calcntr = 0;
7419 }
9d556c99
CML		 7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7421
968040b2 7422 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7423 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7424 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7425 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7426
9d556c99
CML		 7427 /* AFC Recal */
7428 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7429 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7430 DPIO_AFC_RECAL);
7431
a580516d 7432 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7433}
7434
d288f65f
VS		 7435/**
7436 * vlv_force_pll_on - forcibly enable just the PLL
7437 * @dev_priv: i915 private structure
7438 * @pipe: pipe PLL to enable
7439 * @dpll: PLL configuration
7440 *
7441 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7442 * in cases where we need the PLL enabled even when @pipe is not going to
7443 * be enabled.
7444 */
7445void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7446 const struct dpll *dpll)
7447{
7448 struct intel_crtc *crtc =
7449 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7450 struct intel_crtc_state pipe_config = {
a93e255f 7451 .base.crtc = &crtc->base,
d288f65f
VS		 7452 .pixel_multiplier = 1,
7453 .dpll = *dpll,
7454 };
7455
7456 if (IS_CHERRYVIEW(dev)) {
251ac862 7457 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7458 chv_prepare_pll(crtc, &pipe_config);
7459 chv_enable_pll(crtc, &pipe_config);
7460 } else {
251ac862 7461 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7462 vlv_prepare_pll(crtc, &pipe_config);
7463 vlv_enable_pll(crtc, &pipe_config);
7464 }
7465}
7466
7467/**
7468 * vlv_force_pll_off - forcibly disable just the PLL
7469 * @dev_priv: i915 private structure
7470 * @pipe: pipe PLL to disable
7471 *
7472 * Disable the PLL for @pipe. To be used in cases where we need
7473 * the PLL enabled even when @pipe is not going to be enabled.
7474 */
7475void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7476{
7477 if (IS_CHERRYVIEW(dev))
7478 chv_disable_pll(to_i915(dev), pipe);
7479 else
7480 vlv_disable_pll(to_i915(dev), pipe);
7481}
7482
251ac862
DV		 7483static void i9xx_compute_dpll(struct intel_crtc *crtc,
7484 struct intel_crtc_state *crtc_state,
7485 intel_clock_t *reduced_clock,
7486 int num_connectors)
eb1cbe48 7487{
f47709a9 7488 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7489 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7490 u32 dpll;
7491 bool is_sdvo;
190f68c5 7492 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7493
190f68c5 7494 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7495
a93e255f
ACO		 7496 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7497 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7498
7499 dpll = DPLL_VGA_MODE_DIS;
7500
a93e255f 7501 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7502 dpll |= DPLLB_MODE_LVDS;
7503 else
7504 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7505
ef1b460d 7506 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7507 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7508 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7509 }
198a037f
DV		 7510
7511 if (is_sdvo)
4a33e48d 7512 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7513
190f68c5 7514 if (crtc_state->has_dp_encoder)
4a33e48d 7515 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7516
7517 /* compute bitmask from p1 value */
7518 if (IS_PINEVIEW(dev))
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7520 else {
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7522 if (IS_G4X(dev) && reduced_clock)
7523 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7524 }
7525 switch (clock->p2) {
7526 case 5:
7527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7528 break;
7529 case 7:
7530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7531 break;
7532 case 10:
7533 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7534 break;
7535 case 14:
7536 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7537 break;
7538 }
7539 if (INTEL_INFO(dev)->gen >= 4)
7540 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7541
190f68c5 7542 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7543 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7544 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7545 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7546 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7547 else
7548 dpll |= PLL_REF_INPUT_DREFCLK;
7549
7550 dpll |= DPLL_VCO_ENABLE;
190f68c5 7551 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7552
eb1cbe48 7553 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7554 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7555 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7556 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7557 }
7558}
7559
251ac862
DV		 7560static void i8xx_compute_dpll(struct intel_crtc *crtc,
7561 struct intel_crtc_state *crtc_state,
7562 intel_clock_t *reduced_clock,
7563 int num_connectors)
eb1cbe48 7564{
f47709a9 7565 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7566 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7567 u32 dpll;
190f68c5 7568 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7569
190f68c5 7570 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7571
eb1cbe48
DV		 7572 dpll = DPLL_VGA_MODE_DIS;
7573
a93e255f 7574 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7575 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7576 } else {
7577 if (clock->p1 == 2)
7578 dpll |= PLL_P1_DIVIDE_BY_TWO;
7579 else
7580 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7581 if (clock->p2 == 4)
7582 dpll |= PLL_P2_DIVIDE_BY_4;
7583 }
7584
a93e255f 7585 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7586 dpll |= DPLL_DVO_2X_MODE;
7587
a93e255f 7588 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7591 else
7592 dpll |= PLL_REF_INPUT_DREFCLK;
7593
7594 dpll |= DPLL_VCO_ENABLE;
190f68c5 7595 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7596}
7597
8a654f3b 7598static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7599{
7600 struct drm_device *dev = intel_crtc->base.dev;
7601 struct drm_i915_private *dev_priv = dev->dev_private;
7602 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7603 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7604 struct drm_display_mode *adjusted_mode =
6e3c9717 7605 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7606 uint32_t crtc_vtotal, crtc_vblank_end;
7607 int vsyncshift = 0;
4d8a62ea
DV		 7608
7609 /* We need to be careful not to changed the adjusted mode, for otherwise
7610 * the hw state checker will get angry at the mismatch. */
7611 crtc_vtotal = adjusted_mode->crtc_vtotal;
7612 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7613
609aeaca 7614 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7615 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7616 crtc_vtotal -= 1;
7617 crtc_vblank_end -= 1;
609aeaca 7618
409ee761 7619 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7620 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7621 else
7622 vsyncshift = adjusted_mode->crtc_hsync_start -
7623 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7624 if (vsyncshift < 0)
7625 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7626 }
7627
7628 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7629 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7630
fe2b8f9d 7631 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7632 (adjusted_mode->crtc_hdisplay - 1) |
7633 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7634 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7635 (adjusted_mode->crtc_hblank_start - 1) |
7636 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7637 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7638 (adjusted_mode->crtc_hsync_start - 1) |
7639 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7640
fe2b8f9d 7641 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7642 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7643 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7644 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7645 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7646 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7647 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7648 (adjusted_mode->crtc_vsync_start - 1) |
7649 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7650
b5e508d4
PZ		 7651 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7652 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7653 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7654 * bits. */
7655 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7656 (pipe == PIPE_B || pipe == PIPE_C))
7657 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7658
b0e77b9c
PZ		 7659 /* pipesrc controls the size that is scaled from, which should
7660 * always be the user's requested size.
7661 */
7662 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7663 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7664 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7665}
7666
1bd1bd80 7667static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7668 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7669{
7670 struct drm_device *dev = crtc->base.dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
7672 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7673 uint32_t tmp;
7674
7675 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7676 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7677 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7678 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7679 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7681 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7682 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7684
7685 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7686 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7687 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7688 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7689 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7690 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7691 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7692 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7693 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7694
7695 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7696 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7697 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7698 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7699 }
7700
7701 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7702 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7703 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7704
2d112de7
ACO		 7705 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7706 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7707}
7708
f6a83288 7709void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7710 struct intel_crtc_state *pipe_config)
babea61d 7711{
2d112de7
ACO		 7712 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7713 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7714 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7715 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7716
2d112de7
ACO		 7717 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7718 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7719 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7720 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7721
2d112de7 7722 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7723 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7724
2d112de7
ACO		 7725 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7726 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7727
7728 mode->hsync = drm_mode_hsync(mode);
7729 mode->vrefresh = drm_mode_vrefresh(mode);
7730 drm_mode_set_name(mode);
babea61d
JB		 7731}
7732
84b046f3
DV		 7733static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7734{
7735 struct drm_device *dev = intel_crtc->base.dev;
7736 struct drm_i915_private *dev_priv = dev->dev_private;
7737 uint32_t pipeconf;
7738
9f11a9e4 7739 pipeconf = 0;
84b046f3 7740
b6b5d049
VS		 7741 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7742 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7743 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7744
6e3c9717 7745 if (intel_crtc->config->double_wide)
cf532bb2 7746 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7747
ff9ce46e
DV		 7748 /* only g4x and later have fancy bpc/dither controls */
7749 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7750 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7751 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7752 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7753 PIPECONF_DITHER_TYPE_SP;
84b046f3 7754
6e3c9717 7755 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7756 case 18:
7757 pipeconf |= PIPECONF_6BPC;
7758 break;
7759 case 24:
7760 pipeconf |= PIPECONF_8BPC;
7761 break;
7762 case 30:
7763 pipeconf |= PIPECONF_10BPC;
7764 break;
7765 default:
7766 /* Case prevented by intel_choose_pipe_bpp_dither. */
7767 BUG();
84b046f3
DV		 7768 }
7769 }
7770
7771 if (HAS_PIPE_CXSR(dev)) {
7772 if (intel_crtc->lowfreq_avail) {
7773 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7774 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7775 } else {
7776 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7777 }
7778 }
7779
6e3c9717 7780 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7781 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7782 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7783 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7784 else
7785 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7786 } else
84b046f3
DV		 7787 pipeconf |= PIPECONF_PROGRESSIVE;
7788
6e3c9717 7789 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7790 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7791
84b046f3
DV		 7792 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7793 POSTING_READ(PIPECONF(intel_crtc->pipe));
7794}
7795
190f68c5
ACO		 7796static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7797 struct intel_crtc_state *crtc_state)
79e53945 7798{
c7653199 7799 struct drm_device *dev = crtc->base.dev;
79e53945 7800 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7801 int refclk, num_connectors = 0;
c329a4ec
DV		 7802 intel_clock_t clock;
7803 bool ok;
7804 bool is_dsi = false;
5eddb70b 7805 struct intel_encoder *encoder;
d4906093 7806 const intel_limit_t *limit;
55bb9992 7807 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7808 struct drm_connector *connector;
55bb9992
ACO		 7809 struct drm_connector_state *connector_state;
7810 int i;
79e53945 7811
dd3cd74a
ACO		 7812 memset(&crtc_state->dpll_hw_state, 0,
7813 sizeof(crtc_state->dpll_hw_state));
7814
da3ced29 7815 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7816 if (connector_state->crtc != &crtc->base)
7817 continue;
7818
7819 encoder = to_intel_encoder(connector_state->best_encoder);
7820
5eddb70b 7821 switch (encoder->type) {
e9fd1c02
JN		 7822 case INTEL_OUTPUT_DSI:
7823 is_dsi = true;
7824 break;
6847d71b
PZ		 7825 default:
7826 break;
79e53945 7827 }
43565a06 7828
c751ce4f 7829 num_connectors++;
79e53945
JB		 7830 }
7831
f2335330 7832 if (is_dsi)
5b18e57c 7833 return 0;
f2335330 7834
190f68c5 7835 if (!crtc_state->clock_set) {
a93e255f 7836 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7837
e9fd1c02
JN		 7838 /*
7839 * Returns a set of divisors for the desired target clock with
7840 * the given refclk, or FALSE. The returned values represent
7841 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7842 * 2) / p1 / p2.
7843 */
a93e255f
ACO		 7844 limit = intel_limit(crtc_state, refclk);
7845 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7846 crtc_state->port_clock,
e9fd1c02 7847 refclk, NULL, &clock);
f2335330 7848 if (!ok) {
e9fd1c02
JN		 7849 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7850 return -EINVAL;
7851 }
79e53945 7852
f2335330 7853 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7854 crtc_state->dpll.n = clock.n;
7855 crtc_state->dpll.m1 = clock.m1;
7856 crtc_state->dpll.m2 = clock.m2;
7857 crtc_state->dpll.p1 = clock.p1;
7858 crtc_state->dpll.p2 = clock.p2;
f47709a9 7859 }
7026d4ac 7860
e9fd1c02 7861 if (IS_GEN2(dev)) {
c329a4ec 7862 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7863 num_connectors);
9d556c99 7864 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7865 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7866 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7867 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7868 } else {
c329a4ec 7869 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7870 num_connectors);
e9fd1c02 7871 }
79e53945 7872
c8f7a0db 7873 return 0;
f564048e
EA		 7874}
7875
2fa2fe9a 7876static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7877 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7878{
7879 struct drm_device *dev = crtc->base.dev;
7880 struct drm_i915_private *dev_priv = dev->dev_private;
7881 uint32_t tmp;
7882
dc9e7dec
VS		 7883 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7884 return;
7885
2fa2fe9a 7886 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7887 if (!(tmp & PFIT_ENABLE))
7888 return;
2fa2fe9a 7889
06922821 7890 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7891 if (INTEL_INFO(dev)->gen < 4) {
7892 if (crtc->pipe != PIPE_B)
7893 return;
2fa2fe9a
DV		 7894 } else {
7895 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7896 return;
7897 }
7898
06922821 7899 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7900 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7901 if (INTEL_INFO(dev)->gen < 5)
7902 pipe_config->gmch_pfit.lvds_border_bits =
7903 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7904}
7905
acbec814 7906static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7907 struct intel_crtc_state *pipe_config)
acbec814
JB		 7908{
7909 struct drm_device *dev = crtc->base.dev;
7910 struct drm_i915_private *dev_priv = dev->dev_private;
7911 int pipe = pipe_config->cpu_transcoder;
7912 intel_clock_t clock;
7913 u32 mdiv;
662c6ecb 7914 int refclk = 100000;
acbec814 7915
f573de5a
SK		 7916 /* In case of MIPI DPLL will not even be used */
7917 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7918 return;
7919
a580516d 7920 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7921 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7922 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7923
7924 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7925 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7926 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7927 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7928 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7929
dccbea3b 7930 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7931}
7932
5724dbd1
DL		 7933static void
7934i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7935 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7936{
7937 struct drm_device *dev = crtc->base.dev;
7938 struct drm_i915_private *dev_priv = dev->dev_private;
7939 u32 val, base, offset;
7940 int pipe = crtc->pipe, plane = crtc->plane;
7941 int fourcc, pixel_format;
6761dd31 7942 unsigned int aligned_height;
b113d5ee 7943 struct drm_framebuffer *fb;
1b842c89 7944 struct intel_framebuffer *intel_fb;
1ad292b5 7945
42a7b088
DL		 7946 val = I915_READ(DSPCNTR(plane));
7947 if (!(val & DISPLAY_PLANE_ENABLE))
7948 return;
7949
d9806c9f 7950 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7951 if (!intel_fb) {
1ad292b5
JB		 7952 DRM_DEBUG_KMS("failed to alloc fb\n");
7953 return;
7954 }
7955
1b842c89
DL		 7956 fb = &intel_fb->base;
7957
18c5247e
DV		 7958 if (INTEL_INFO(dev)->gen >= 4) {
7959 if (val & DISPPLANE_TILED) {
49af449b 7960 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7961 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7962 }
7963 }
1ad292b5
JB		 7964
7965 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7966 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7967 fb->pixel_format = fourcc;
7968 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7969
7970 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7971 if (plane_config->tiling)
1ad292b5
JB		 7972 offset = I915_READ(DSPTILEOFF(plane));
7973 else
7974 offset = I915_READ(DSPLINOFF(plane));
7975 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7976 } else {
7977 base = I915_READ(DSPADDR(plane));
7978 }
7979 plane_config->base = base;
7980
7981 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7982 fb->width = ((val >> 16) & 0xfff) + 1;
7983 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7984
7985 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7986 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7987
b113d5ee 7988 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7989 fb->pixel_format,
7990 fb->modifier[0]);
1ad292b5 7991
f37b5c2b 7992 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7993
2844a921
DL		 7994 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7995 pipe_name(pipe), plane, fb->width, fb->height,
7996 fb->bits_per_pixel, base, fb->pitches[0],
7997 plane_config->size);
1ad292b5 7998
2d14030b 7999 plane_config->fb = intel_fb;
1ad292b5
JB		 8000}
8001
70b23a98 8002static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8003 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8004{
8005 struct drm_device *dev = crtc->base.dev;
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007 int pipe = pipe_config->cpu_transcoder;
8008 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8009 intel_clock_t clock;
0d7b6b11 8010 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8011 int refclk = 100000;
8012
a580516d 8013 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8014 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8015 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8016 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8017 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8018 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8019 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8020
8021 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8022 clock.m2 = (pll_dw0 & 0xff) << 22;
8023 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8024 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8025 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8026 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8027 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8028
dccbea3b 8029 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8030}
8031
0e8ffe1b 8032static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8033 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8034{
8035 struct drm_device *dev = crtc->base.dev;
8036 struct drm_i915_private *dev_priv = dev->dev_private;
8037 uint32_t tmp;
8038
f458ebbc
DV		 8039 if (!intel_display_power_is_enabled(dev_priv,
8040 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8041 return false;
8042
e143a21c 8043 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8044 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8045
0e8ffe1b
DV		 8046 tmp = I915_READ(PIPECONF(crtc->pipe));
8047 if (!(tmp & PIPECONF_ENABLE))
8048 return false;
8049
42571aef
VS		 8050 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8051 switch (tmp & PIPECONF_BPC_MASK) {
8052 case PIPECONF_6BPC:
8053 pipe_config->pipe_bpp = 18;
8054 break;
8055 case PIPECONF_8BPC:
8056 pipe_config->pipe_bpp = 24;
8057 break;
8058 case PIPECONF_10BPC:
8059 pipe_config->pipe_bpp = 30;
8060 break;
8061 default:
8062 break;
8063 }
8064 }
8065
b5a9fa09
DV		 8066 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8067 pipe_config->limited_color_range = true;
8068
282740f7
VS		 8069 if (INTEL_INFO(dev)->gen < 4)
8070 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8071
1bd1bd80
DV		 8072 intel_get_pipe_timings(crtc, pipe_config);
8073
2fa2fe9a
DV		 8074 i9xx_get_pfit_config(crtc, pipe_config);
8075
6c49f241
DV		 8076 if (INTEL_INFO(dev)->gen >= 4) {
8077 tmp = I915_READ(DPLL_MD(crtc->pipe));
8078 pipe_config->pixel_multiplier =
8079 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8080 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8081 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8082 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8083 tmp = I915_READ(DPLL(crtc->pipe));
8084 pipe_config->pixel_multiplier =
8085 ((tmp & SDVO_MULTIPLIER_MASK)
8086 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8087 } else {
8088 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8089 * port and will be fixed up in the encoder->get_config
8090 * function. */
8091 pipe_config->pixel_multiplier = 1;
8092 }
8bcc2795
DV		 8093 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8094 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8095 /*
8096 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8097 * on 830. Filter it out here so that we don't
8098 * report errors due to that.
8099 */
8100 if (IS_I830(dev))
8101 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8102
8bcc2795
DV		 8103 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8104 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8105 } else {
8106 /* Mask out read-only status bits. */
8107 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8108 DPLL_PORTC_READY_MASK |
8109 DPLL_PORTB_READY_MASK);
8bcc2795 8110 }
6c49f241 8111
70b23a98
VS		 8112 if (IS_CHERRYVIEW(dev))
8113 chv_crtc_clock_get(crtc, pipe_config);
8114 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8115 vlv_crtc_clock_get(crtc, pipe_config);
8116 else
8117 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8118
0e8ffe1b
DV		 8119 return true;
8120}
8121
dde86e2d 8122static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8123{
8124 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8125 struct intel_encoder *encoder;
74cfd7ac 8126 u32 val, final;
13d83a67 8127 bool has_lvds = false;
199e5d79 8128 bool has_cpu_edp = false;
199e5d79 8129 bool has_panel = false;
99eb6a01
KP		 8130 bool has_ck505 = false;
8131 bool can_ssc = false;
13d83a67
JB		 8132
8133 /* We need to take the global config into account */
b2784e15 8134 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8135 switch (encoder->type) {
8136 case INTEL_OUTPUT_LVDS:
8137 has_panel = true;
8138 has_lvds = true;
8139 break;
8140 case INTEL_OUTPUT_EDP:
8141 has_panel = true;
2de6905f 8142 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8143 has_cpu_edp = true;
8144 break;
6847d71b
PZ		 8145 default:
8146 break;
13d83a67
JB		 8147 }
8148 }
8149
99eb6a01 8150 if (HAS_PCH_IBX(dev)) {
41aa3448 8151 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8152 can_ssc = has_ck505;
8153 } else {
8154 has_ck505 = false;
8155 can_ssc = true;
8156 }
8157
2de6905f
ID		 8158 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8159 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8160
8161 /* Ironlake: try to setup display ref clock before DPLL
8162 * enabling. This is only under driver's control after
8163 * PCH B stepping, previous chipset stepping should be
8164 * ignoring this setting.
8165 */
74cfd7ac
CW		 8166 val = I915_READ(PCH_DREF_CONTROL);
8167
8168 /* As we must carefully and slowly disable/enable each source in turn,
8169 * compute the final state we want first and check if we need to
8170 * make any changes at all.
8171 */
8172 final = val;
8173 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8174 if (has_ck505)
8175 final |= DREF_NONSPREAD_CK505_ENABLE;
8176 else
8177 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8178
8179 final &= ~DREF_SSC_SOURCE_MASK;
8180 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8181 final &= ~DREF_SSC1_ENABLE;
8182
8183 if (has_panel) {
8184 final |= DREF_SSC_SOURCE_ENABLE;
8185
8186 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8187 final |= DREF_SSC1_ENABLE;
8188
8189 if (has_cpu_edp) {
8190 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8191 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8192 else
8193 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8194 } else
8195 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8196 } else {
8197 final |= DREF_SSC_SOURCE_DISABLE;
8198 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8199 }
8200
8201 if (final == val)
8202 return;
8203
13d83a67 8204 /* Always enable nonspread source */
74cfd7ac 8205 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8206
99eb6a01 8207 if (has_ck505)
74cfd7ac 8208 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8209 else
74cfd7ac 8210 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8211
199e5d79 8212 if (has_panel) {
74cfd7ac
CW		 8213 val &= ~DREF_SSC_SOURCE_MASK;
8214 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8215
199e5d79 8216 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8217 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8218 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8219 val |= DREF_SSC1_ENABLE;
e77166b5 8220 } else
74cfd7ac 8221 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8222
8223 /* Get SSC going before enabling the outputs */
74cfd7ac 8224 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8225 POSTING_READ(PCH_DREF_CONTROL);
8226 udelay(200);
8227
74cfd7ac 8228 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8229
8230 /* Enable CPU source on CPU attached eDP */
199e5d79 8231 if (has_cpu_edp) {
99eb6a01 8232 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8233 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8234 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8235 } else
74cfd7ac 8236 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8237 } else
74cfd7ac 8238 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8239
74cfd7ac 8240 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8241 POSTING_READ(PCH_DREF_CONTROL);
8242 udelay(200);
8243 } else {
8244 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8245
74cfd7ac 8246 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8247
8248 /* Turn off CPU output */
74cfd7ac 8249 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8250
74cfd7ac 8251 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8252 POSTING_READ(PCH_DREF_CONTROL);
8253 udelay(200);
8254
8255 /* Turn off the SSC source */
74cfd7ac
CW		 8256 val &= ~DREF_SSC_SOURCE_MASK;
8257 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8258
8259 /* Turn off SSC1 */
74cfd7ac 8260 val &= ~DREF_SSC1_ENABLE;
199e5d79 8261
74cfd7ac 8262 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8263 POSTING_READ(PCH_DREF_CONTROL);
8264 udelay(200);
8265 }
74cfd7ac
CW		 8266
8267 BUG_ON(val != final);
13d83a67
JB		 8268}
8269
f31f2d55 8270static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8271{
f31f2d55 8272 uint32_t tmp;
dde86e2d 8273
0ff066a9
PZ		 8274 tmp = I915_READ(SOUTH_CHICKEN2);
8275 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8276 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8277
0ff066a9
PZ		 8278 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8279 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8280 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8281
0ff066a9
PZ		 8282 tmp = I915_READ(SOUTH_CHICKEN2);
8283 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8284 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8285
0ff066a9
PZ		 8286 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8287 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8288 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8289}
8290
8291/* WaMPhyProgramming:hsw */
8292static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8293{
8294 uint32_t tmp;
dde86e2d
PZ		 8295
8296 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8297 tmp &= ~(0xFF << 24);
8298 tmp |= (0x12 << 24);
8299 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8300
dde86e2d
PZ		 8301 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8302 tmp |= (1 << 11);
8303 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8304
8305 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8306 tmp |= (1 << 11);
8307 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8308
dde86e2d
PZ		 8309 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8310 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8311 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8312
8313 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8314 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8315 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8316
0ff066a9
PZ		 8317 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8318 tmp &= ~(7 << 13);
8319 tmp |= (5 << 13);
8320 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8321
0ff066a9
PZ		 8322 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8323 tmp &= ~(7 << 13);
8324 tmp |= (5 << 13);
8325 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8326
8327 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8328 tmp &= ~0xFF;
8329 tmp |= 0x1C;
8330 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8331
8332 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8333 tmp &= ~0xFF;
8334 tmp |= 0x1C;
8335 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8336
8337 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8338 tmp &= ~(0xFF << 16);
8339 tmp |= (0x1C << 16);
8340 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8343 tmp &= ~(0xFF << 16);
8344 tmp |= (0x1C << 16);
8345 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8346
0ff066a9
PZ		 8347 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8348 tmp |= (1 << 27);
8349 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8350
0ff066a9
PZ		 8351 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8352 tmp |= (1 << 27);
8353 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8354
0ff066a9
PZ		 8355 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8356 tmp &= ~(0xF << 28);
8357 tmp |= (4 << 28);
8358 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8359
0ff066a9
PZ		 8360 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8361 tmp &= ~(0xF << 28);
8362 tmp |= (4 << 28);
8363 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8364}
8365
2fa86a1f
PZ		 8366/* Implements 3 different sequences from BSpec chapter "Display iCLK
8367 * Programming" based on the parameters passed:
8368 * - Sequence to enable CLKOUT_DP
8369 * - Sequence to enable CLKOUT_DP without spread
8370 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8371 */
8372static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8373 bool with_fdi)
f31f2d55
PZ		 8374{
8375 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8376 uint32_t reg, tmp;
8377
8378 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8379 with_spread = true;
8380 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8381 with_fdi, "LP PCH doesn't have FDI\n"))
8382 with_fdi = false;
f31f2d55 8383
a580516d 8384 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8385
8386 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8387 tmp &= ~SBI_SSCCTL_DISABLE;
8388 tmp |= SBI_SSCCTL_PATHALT;
8389 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8390
8391 udelay(24);
8392
2fa86a1f
PZ		 8393 if (with_spread) {
8394 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8395 tmp &= ~SBI_SSCCTL_PATHALT;
8396 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8397
2fa86a1f
PZ		 8398 if (with_fdi) {
8399 lpt_reset_fdi_mphy(dev_priv);
8400 lpt_program_fdi_mphy(dev_priv);
8401 }
8402 }
dde86e2d 8403
2fa86a1f
PZ		 8404 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8405 SBI_GEN0 : SBI_DBUFF0;
8406 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8407 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8408 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8409
a580516d 8410 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8411}
8412
47701c3b
PZ		 8413/* Sequence to disable CLKOUT_DP */
8414static void lpt_disable_clkout_dp(struct drm_device *dev)
8415{
8416 struct drm_i915_private *dev_priv = dev->dev_private;
8417 uint32_t reg, tmp;
8418
a580516d 8419 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8420
8421 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8422 SBI_GEN0 : SBI_DBUFF0;
8423 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8424 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8425 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8426
8427 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8428 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8429 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8430 tmp |= SBI_SSCCTL_PATHALT;
8431 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8432 udelay(32);
8433 }
8434 tmp |= SBI_SSCCTL_DISABLE;
8435 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8436 }
8437
a580516d 8438 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8439}
8440
bf8fa3d3
PZ		 8441static void lpt_init_pch_refclk(struct drm_device *dev)
8442{
bf8fa3d3
PZ		 8443 struct intel_encoder *encoder;
8444 bool has_vga = false;
8445
b2784e15 8446 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8447 switch (encoder->type) {
8448 case INTEL_OUTPUT_ANALOG:
8449 has_vga = true;
8450 break;
6847d71b
PZ		 8451 default:
8452 break;
bf8fa3d3
PZ		 8453 }
8454 }
8455
47701c3b
PZ		 8456 if (has_vga)
8457 lpt_enable_clkout_dp(dev, true, true);
8458 else
8459 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8460}
8461
dde86e2d
PZ		 8462/*
8463 * Initialize reference clocks when the driver loads
8464 */
8465void intel_init_pch_refclk(struct drm_device *dev)
8466{
8467 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8468 ironlake_init_pch_refclk(dev);
8469 else if (HAS_PCH_LPT(dev))
8470 lpt_init_pch_refclk(dev);
8471}
8472
55bb9992 8473static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8474{
55bb9992 8475 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8476 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8477 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8478 struct drm_connector *connector;
55bb9992 8479 struct drm_connector_state *connector_state;
d9d444cb 8480 struct intel_encoder *encoder;
55bb9992 8481 int num_connectors = 0, i;
d9d444cb
JB		 8482 bool is_lvds = false;
8483
da3ced29 8484 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8485 if (connector_state->crtc != crtc_state->base.crtc)
8486 continue;
8487
8488 encoder = to_intel_encoder(connector_state->best_encoder);
8489
d9d444cb
JB		 8490 switch (encoder->type) {
8491 case INTEL_OUTPUT_LVDS:
8492 is_lvds = true;
8493 break;
6847d71b
PZ		 8494 default:
8495 break;
d9d444cb
JB		 8496 }
8497 num_connectors++;
8498 }
8499
8500 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8501 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8502 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8503 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8504 }
8505
8506 return 120000;
8507}
8508
6ff93609 8509static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8510{
c8203565 8511 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8513 int pipe = intel_crtc->pipe;
c8203565
PZ		 8514 uint32_t val;
8515
78114071 8516 val = 0;
c8203565 8517
6e3c9717 8518 switch (intel_crtc->config->pipe_bpp) {
c8203565 8519 case 18:
dfd07d72 8520 val |= PIPECONF_6BPC;
c8203565
PZ		 8521 break;
8522 case 24:
dfd07d72 8523 val |= PIPECONF_8BPC;
c8203565
PZ		 8524 break;
8525 case 30:
dfd07d72 8526 val |= PIPECONF_10BPC;
c8203565
PZ		 8527 break;
8528 case 36:
dfd07d72 8529 val |= PIPECONF_12BPC;
c8203565
PZ		 8530 break;
8531 default:
cc769b62
PZ		 8532 /* Case prevented by intel_choose_pipe_bpp_dither. */
8533 BUG();
c8203565
PZ		 8534 }
8535
6e3c9717 8536 if (intel_crtc->config->dither)
c8203565
PZ		 8537 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8538
6e3c9717 8539 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8540 val |= PIPECONF_INTERLACED_ILK;
8541 else
8542 val |= PIPECONF_PROGRESSIVE;
8543
6e3c9717 8544 if (intel_crtc->config->limited_color_range)
3685a8f3 8545 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8546
c8203565
PZ		 8547 I915_WRITE(PIPECONF(pipe), val);
8548 POSTING_READ(PIPECONF(pipe));
8549}
8550
86d3efce
VS		 8551/*
8552 * Set up the pipe CSC unit.
8553 *
8554 * Currently only full range RGB to limited range RGB conversion
8555 * is supported, but eventually this should handle various
8556 * RGB<->YCbCr scenarios as well.
8557 */
50f3b016 8558static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8559{
8560 struct drm_device *dev = crtc->dev;
8561 struct drm_i915_private *dev_priv = dev->dev_private;
8562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8563 int pipe = intel_crtc->pipe;
8564 uint16_t coeff = 0x7800; /* 1.0 */
8565
8566 /*
8567 * TODO: Check what kind of values actually come out of the pipe
8568 * with these coeff/postoff values and adjust to get the best
8569 * accuracy. Perhaps we even need to take the bpc value into
8570 * consideration.
8571 */
8572
6e3c9717 8573 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8574 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8575
8576 /*
8577 * GY/GU and RY/RU should be the other way around according
8578 * to BSpec, but reality doesn't agree. Just set them up in
8579 * a way that results in the correct picture.
8580 */
8581 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8582 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8583
8584 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8585 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8586
8587 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8588 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8589
8590 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8591 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8592 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8593
8594 if (INTEL_INFO(dev)->gen > 6) {
8595 uint16_t postoff = 0;
8596
6e3c9717 8597 if (intel_crtc->config->limited_color_range)
32cf0cb0 8598 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8599
8600 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8601 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8602 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8603
8604 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8605 } else {
8606 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8607
6e3c9717 8608 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8609 mode |= CSC_BLACK_SCREEN_OFFSET;
8610
8611 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8612 }
8613}
8614
6ff93609 8615static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8616{
756f85cf
PZ		 8617 struct drm_device *dev = crtc->dev;
8618 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8620 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8621 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8622 uint32_t val;
8623
3eff4faa 8624 val = 0;
ee2b0b38 8625
6e3c9717 8626 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8627 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8628
6e3c9717 8629 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8630 val |= PIPECONF_INTERLACED_ILK;
8631 else
8632 val |= PIPECONF_PROGRESSIVE;
8633
702e7a56
PZ		 8634 I915_WRITE(PIPECONF(cpu_transcoder), val);
8635 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8636
8637 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8638 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8639
3cdf122c 8640 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8641 val = 0;
8642
6e3c9717 8643 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8644 case 18:
8645 val |= PIPEMISC_DITHER_6_BPC;
8646 break;
8647 case 24:
8648 val |= PIPEMISC_DITHER_8_BPC;
8649 break;
8650 case 30:
8651 val |= PIPEMISC_DITHER_10_BPC;
8652 break;
8653 case 36:
8654 val |= PIPEMISC_DITHER_12_BPC;
8655 break;
8656 default:
8657 /* Case prevented by pipe_config_set_bpp. */
8658 BUG();
8659 }
8660
6e3c9717 8661 if (intel_crtc->config->dither)
756f85cf
PZ		 8662 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8663
8664 I915_WRITE(PIPEMISC(pipe), val);
8665 }
ee2b0b38
PZ		 8666}
8667
6591c6e4 8668static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8669 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8670 intel_clock_t *clock,
8671 bool *has_reduced_clock,
8672 intel_clock_t *reduced_clock)
8673{
8674 struct drm_device *dev = crtc->dev;
8675 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8676 int refclk;
d4906093 8677 const intel_limit_t *limit;
c329a4ec 8678 bool ret;
79e53945 8679
55bb9992 8680 refclk = ironlake_get_refclk(crtc_state);
79e53945 8681
d4906093
ML		 8682 /*
8683 * Returns a set of divisors for the desired target clock with the given
8684 * refclk, or FALSE. The returned values represent the clock equation:
8685 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8686 */
a93e255f
ACO		 8687 limit = intel_limit(crtc_state, refclk);
8688 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8689 crtc_state->port_clock,
ee9300bb 8690 refclk, NULL, clock);
6591c6e4
PZ		 8691 if (!ret)
8692 return false;
cda4b7d3 8693
6591c6e4
PZ		 8694 return true;
8695}
8696
d4b1931c
PZ		 8697int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8698{
8699 /*
8700 * Account for spread spectrum to avoid
8701 * oversubscribing the link. Max center spread
8702 * is 2.5%; use 5% for safety's sake.
8703 */
8704 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8705 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8706}
8707
7429e9d4 8708static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8709{
7429e9d4 8710 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8711}
8712
de13a2e3 8713static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8714 struct intel_crtc_state *crtc_state,
7429e9d4 8715 u32 *fp,
9a7c7890 8716 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8717{
de13a2e3 8718 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8719 struct drm_device *dev = crtc->dev;
8720 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8721 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8722 struct drm_connector *connector;
55bb9992
ACO		 8723 struct drm_connector_state *connector_state;
8724 struct intel_encoder *encoder;
de13a2e3 8725 uint32_t dpll;
55bb9992 8726 int factor, num_connectors = 0, i;
09ede541 8727 bool is_lvds = false, is_sdvo = false;
79e53945 8728
da3ced29 8729 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8730 if (connector_state->crtc != crtc_state->base.crtc)
8731 continue;
8732
8733 encoder = to_intel_encoder(connector_state->best_encoder);
8734
8735 switch (encoder->type) {
79e53945
JB		 8736 case INTEL_OUTPUT_LVDS:
8737 is_lvds = true;
8738 break;
8739 case INTEL_OUTPUT_SDVO:
7d57382e 8740 case INTEL_OUTPUT_HDMI:
79e53945 8741 is_sdvo = true;
79e53945 8742 break;
6847d71b
PZ		 8743 default:
8744 break;
79e53945 8745 }
43565a06 8746
c751ce4f 8747 num_connectors++;
79e53945 8748 }
79e53945 8749
c1858123 8750 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8751 factor = 21;
8752 if (is_lvds) {
8753 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8754 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8755 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8756 factor = 25;
190f68c5 8757 } else if (crtc_state->sdvo_tv_clock)
8febb297 8758 factor = 20;
c1858123 8759
190f68c5 8760 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8761 *fp |= FP_CB_TUNE;
2c07245f 8762
9a7c7890
DV		 8763 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8764 *fp2 |= FP_CB_TUNE;
8765
5eddb70b 8766 dpll = 0;
2c07245f 8767
a07d6787
EA		 8768 if (is_lvds)
8769 dpll |= DPLLB_MODE_LVDS;
8770 else
8771 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8772
190f68c5 8773 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8774 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8775
8776 if (is_sdvo)
4a33e48d 8777 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8778 if (crtc_state->has_dp_encoder)
4a33e48d 8779 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8780
a07d6787 8781 /* compute bitmask from p1 value */
190f68c5 8782 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8783 /* also FPA1 */
190f68c5 8784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8785
190f68c5 8786 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8787 case 5:
8788 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8789 break;
8790 case 7:
8791 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8792 break;
8793 case 10:
8794 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8795 break;
8796 case 14:
8797 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8798 break;
79e53945
JB		 8799 }
8800
b4c09f3b 8801 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8802 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8803 else
8804 dpll |= PLL_REF_INPUT_DREFCLK;
8805
959e16d6 8806 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8807}
8808
190f68c5
ACO		 8809static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8810 struct intel_crtc_state *crtc_state)
de13a2e3 8811{
c7653199 8812 struct drm_device *dev = crtc->base.dev;
de13a2e3 8813 intel_clock_t clock, reduced_clock;
cbbab5bd 8814 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8815 bool ok, has_reduced_clock = false;
8b47047b 8816 bool is_lvds = false;
e2b78267 8817 struct intel_shared_dpll *pll;
de13a2e3 8818
dd3cd74a
ACO		 8819 memset(&crtc_state->dpll_hw_state, 0,
8820 sizeof(crtc_state->dpll_hw_state));
8821
409ee761 8822 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8823
5dc5298b
PZ		 8824 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8825 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8826
190f68c5 8827 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8828 &has_reduced_clock, &reduced_clock);
190f68c5 8829 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8830 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8831 return -EINVAL;
79e53945 8832 }
f47709a9 8833 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8834 if (!crtc_state->clock_set) {
8835 crtc_state->dpll.n = clock.n;
8836 crtc_state->dpll.m1 = clock.m1;
8837 crtc_state->dpll.m2 = clock.m2;
8838 crtc_state->dpll.p1 = clock.p1;
8839 crtc_state->dpll.p2 = clock.p2;
f47709a9 8840 }
79e53945 8841
5dc5298b 8842 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8843 if (crtc_state->has_pch_encoder) {
8844 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8845 if (has_reduced_clock)
7429e9d4 8846 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8847
190f68c5 8848 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8849 &fp, &reduced_clock,
8850 has_reduced_clock ? &fp2 : NULL);
8851
190f68c5
ACO		 8852 crtc_state->dpll_hw_state.dpll = dpll;
8853 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8854 if (has_reduced_clock)
190f68c5 8855 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8856 else
190f68c5 8857 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8858
190f68c5 8859 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8860 if (pll == NULL) {
84f44ce7 8861 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8862 pipe_name(crtc->pipe));
4b645f14
JB		 8863 return -EINVAL;
8864 }
3fb37703 8865 }
79e53945 8866
ab585dea 8867 if (is_lvds && has_reduced_clock)
c7653199 8868 crtc->lowfreq_avail = true;
bcd644e0 8869 else
c7653199 8870 crtc->lowfreq_avail = false;
e2b78267 8871
c8f7a0db 8872 return 0;
79e53945
JB		 8873}
8874
eb14cb74
VS		 8875static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8876 struct intel_link_m_n *m_n)
8877{
8878 struct drm_device *dev = crtc->base.dev;
8879 struct drm_i915_private *dev_priv = dev->dev_private;
8880 enum pipe pipe = crtc->pipe;
8881
8882 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8883 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8884 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8885 & ~TU_SIZE_MASK;
8886 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8887 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8888 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8889}
8890
8891static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8892 enum transcoder transcoder,
b95af8be
VK		 8893 struct intel_link_m_n *m_n,
8894 struct intel_link_m_n *m2_n2)
72419203
DV		 8895{
8896 struct drm_device *dev = crtc->base.dev;
8897 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8898 enum pipe pipe = crtc->pipe;
72419203 8899
eb14cb74
VS		 8900 if (INTEL_INFO(dev)->gen >= 5) {
8901 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8902 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8903 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8904 & ~TU_SIZE_MASK;
8905 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8906 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8907 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8908 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8909 * gen < 8) and if DRRS is supported (to make sure the
8910 * registers are not unnecessarily read).
8911 */
8912 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8913 crtc->config->has_drrs) {
b95af8be
VK		 8914 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8915 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8916 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8917 & ~TU_SIZE_MASK;
8918 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8919 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8920 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8921 }
eb14cb74
VS		 8922 } else {
8923 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8924 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8925 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8926 & ~TU_SIZE_MASK;
8927 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8928 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8929 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8930 }
8931}
8932
8933void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8934 struct intel_crtc_state *pipe_config)
eb14cb74 8935{
681a8504 8936 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8937 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8938 else
8939 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8940 &pipe_config->dp_m_n,
8941 &pipe_config->dp_m2_n2);
eb14cb74 8942}
72419203 8943
eb14cb74 8944static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8945 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8946{
8947 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8948 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8949}
8950
bd2e244f 8951static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8952 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8953{
8954 struct drm_device *dev = crtc->base.dev;
8955 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8956 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8957 uint32_t ps_ctrl = 0;
8958 int id = -1;
8959 int i;
bd2e244f 8960
a1b2278e
CK		 8961 /* find scaler attached to this pipe */
8962 for (i = 0; i < crtc->num_scalers; i++) {
8963 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8964 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8965 id = i;
8966 pipe_config->pch_pfit.enabled = true;
8967 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8968 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8969 break;
8970 }
8971 }
bd2e244f 8972
a1b2278e
CK		 8973 scaler_state->scaler_id = id;
8974 if (id >= 0) {
8975 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8976 } else {
8977 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8978 }
8979}
8980
5724dbd1
DL		 8981static void
8982skylake_get_initial_plane_config(struct intel_crtc *crtc,
8983 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8984{
8985 struct drm_device *dev = crtc->base.dev;
8986 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8987 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8988 int pipe = crtc->pipe;
8989 int fourcc, pixel_format;
6761dd31 8990 unsigned int aligned_height;
bc8d7dff 8991 struct drm_framebuffer *fb;
1b842c89 8992 struct intel_framebuffer *intel_fb;
bc8d7dff 8993
d9806c9f 8994 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8995 if (!intel_fb) {
bc8d7dff
DL		 8996 DRM_DEBUG_KMS("failed to alloc fb\n");
8997 return;
8998 }
8999
1b842c89
DL		 9000 fb = &intel_fb->base;
9001
bc8d7dff 9002 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9003 if (!(val & PLANE_CTL_ENABLE))
9004 goto error;
9005
bc8d7dff
DL		 9006 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9007 fourcc = skl_format_to_fourcc(pixel_format,
9008 val & PLANE_CTL_ORDER_RGBX,
9009 val & PLANE_CTL_ALPHA_MASK);
9010 fb->pixel_format = fourcc;
9011 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9012
40f46283
DL		 9013 tiling = val & PLANE_CTL_TILED_MASK;
9014 switch (tiling) {
9015 case PLANE_CTL_TILED_LINEAR:
9016 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9017 break;
9018 case PLANE_CTL_TILED_X:
9019 plane_config->tiling = I915_TILING_X;
9020 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9021 break;
9022 case PLANE_CTL_TILED_Y:
9023 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9024 break;
9025 case PLANE_CTL_TILED_YF:
9026 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9027 break;
9028 default:
9029 MISSING_CASE(tiling);
9030 goto error;
9031 }
9032
bc8d7dff
DL		 9033 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9034 plane_config->base = base;
9035
9036 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9037
9038 val = I915_READ(PLANE_SIZE(pipe, 0));
9039 fb->height = ((val >> 16) & 0xfff) + 1;
9040 fb->width = ((val >> 0) & 0x1fff) + 1;
9041
9042 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9043 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9044 fb->pixel_format);
bc8d7dff
DL		 9045 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9046
9047 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9048 fb->pixel_format,
9049 fb->modifier[0]);
bc8d7dff 9050
f37b5c2b 9051 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9052
9053 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9054 pipe_name(pipe), fb->width, fb->height,
9055 fb->bits_per_pixel, base, fb->pitches[0],
9056 plane_config->size);
9057
2d14030b 9058 plane_config->fb = intel_fb;
bc8d7dff
DL		 9059 return;
9060
9061error:
9062 kfree(fb);
9063}
9064
2fa2fe9a 9065static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9066 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9067{
9068 struct drm_device *dev = crtc->base.dev;
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070 uint32_t tmp;
9071
9072 tmp = I915_READ(PF_CTL(crtc->pipe));
9073
9074 if (tmp & PF_ENABLE) {
fd4daa9c 9075 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9076 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9077 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9078
9079 /* We currently do not free assignements of panel fitters on
9080 * ivb/hsw (since we don't use the higher upscaling modes which
9081 * differentiates them) so just WARN about this case for now. */
9082 if (IS_GEN7(dev)) {
9083 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9084 PF_PIPE_SEL_IVB(crtc->pipe));
9085 }
2fa2fe9a 9086 }
79e53945
JB		 9087}
9088
5724dbd1
DL		 9089static void
9090ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9091 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9092{
9093 struct drm_device *dev = crtc->base.dev;
9094 struct drm_i915_private *dev_priv = dev->dev_private;
9095 u32 val, base, offset;
aeee5a49 9096 int pipe = crtc->pipe;
4c6baa59 9097 int fourcc, pixel_format;
6761dd31 9098 unsigned int aligned_height;
b113d5ee 9099 struct drm_framebuffer *fb;
1b842c89 9100 struct intel_framebuffer *intel_fb;
4c6baa59 9101
42a7b088
DL		 9102 val = I915_READ(DSPCNTR(pipe));
9103 if (!(val & DISPLAY_PLANE_ENABLE))
9104 return;
9105
d9806c9f 9106 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9107 if (!intel_fb) {
4c6baa59
JB		 9108 DRM_DEBUG_KMS("failed to alloc fb\n");
9109 return;
9110 }
9111
1b842c89
DL		 9112 fb = &intel_fb->base;
9113
18c5247e
DV		 9114 if (INTEL_INFO(dev)->gen >= 4) {
9115 if (val & DISPPLANE_TILED) {
49af449b 9116 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9117 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9118 }
9119 }
4c6baa59
JB		 9120
9121 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9122 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9123 fb->pixel_format = fourcc;
9124 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9125
aeee5a49 9126 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9127 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9128 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9129 } else {
49af449b 9130 if (plane_config->tiling)
aeee5a49 9131 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9132 else
aeee5a49 9133 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9134 }
9135 plane_config->base = base;
9136
9137 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9138 fb->width = ((val >> 16) & 0xfff) + 1;
9139 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9140
9141 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9142 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9143
b113d5ee 9144 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9145 fb->pixel_format,
9146 fb->modifier[0]);
4c6baa59 9147
f37b5c2b 9148 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9149
2844a921
DL		 9150 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9151 pipe_name(pipe), fb->width, fb->height,
9152 fb->bits_per_pixel, base, fb->pitches[0],
9153 plane_config->size);
b113d5ee 9154
2d14030b 9155 plane_config->fb = intel_fb;
4c6baa59
JB		 9156}
9157
0e8ffe1b 9158static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9159 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9160{
9161 struct drm_device *dev = crtc->base.dev;
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163 uint32_t tmp;
9164
f458ebbc
DV		 9165 if (!intel_display_power_is_enabled(dev_priv,
9166 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9167 return false;
9168
e143a21c 9169 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9170 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9171
0e8ffe1b
DV		 9172 tmp = I915_READ(PIPECONF(crtc->pipe));
9173 if (!(tmp & PIPECONF_ENABLE))
9174 return false;
9175
42571aef
VS		 9176 switch (tmp & PIPECONF_BPC_MASK) {
9177 case PIPECONF_6BPC:
9178 pipe_config->pipe_bpp = 18;
9179 break;
9180 case PIPECONF_8BPC:
9181 pipe_config->pipe_bpp = 24;
9182 break;
9183 case PIPECONF_10BPC:
9184 pipe_config->pipe_bpp = 30;
9185 break;
9186 case PIPECONF_12BPC:
9187 pipe_config->pipe_bpp = 36;
9188 break;
9189 default:
9190 break;
9191 }
9192
b5a9fa09
DV		 9193 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9194 pipe_config->limited_color_range = true;
9195
ab9412ba 9196 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9197 struct intel_shared_dpll *pll;
9198
88adfff1
DV		 9199 pipe_config->has_pch_encoder = true;
9200
627eb5a3
DV		 9201 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9202 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9203 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9204
9205 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9206
c0d43d62 9207 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9208 pipe_config->shared_dpll =
9209 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9210 } else {
9211 tmp = I915_READ(PCH_DPLL_SEL);
9212 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9213 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9214 else
9215 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9216 }
66e985c0
DV		 9217
9218 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9219
9220 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9221 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9222
9223 tmp = pipe_config->dpll_hw_state.dpll;
9224 pipe_config->pixel_multiplier =
9225 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9226 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9227
9228 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9229 } else {
9230 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9231 }
9232
1bd1bd80
DV		 9233 intel_get_pipe_timings(crtc, pipe_config);
9234
2fa2fe9a
DV		 9235 ironlake_get_pfit_config(crtc, pipe_config);
9236
0e8ffe1b
DV		 9237 return true;
9238}
9239
be256dc7
PZ		 9240static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9241{
9242 struct drm_device *dev = dev_priv->dev;
be256dc7 9243 struct intel_crtc *crtc;
be256dc7 9244
d3fcc808 9245 for_each_intel_crtc(dev, crtc)
e2c719b7 9246 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9247 pipe_name(crtc->pipe));
9248
e2c719b7
RC		 9249 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9250 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9251 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9252 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9253 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9254 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9255 "CPU PWM1 enabled\n");
c5107b87 9256 if (IS_HASWELL(dev))
e2c719b7 9257 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9258 "CPU PWM2 enabled\n");
e2c719b7 9259 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9260 "PCH PWM1 enabled\n");
e2c719b7 9261 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9262 "Utility pin enabled\n");
e2c719b7 9263 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9264
9926ada1
PZ		 9265 /*
9266 * In theory we can still leave IRQs enabled, as long as only the HPD
9267 * interrupts remain enabled. We used to check for that, but since it's
9268 * gen-specific and since we only disable LCPLL after we fully disable
9269 * the interrupts, the check below should be enough.
9270 */
e2c719b7 9271 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9272}
9273
9ccd5aeb
PZ		 9274static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9275{
9276 struct drm_device *dev = dev_priv->dev;
9277
9278 if (IS_HASWELL(dev))
9279 return I915_READ(D_COMP_HSW);
9280 else
9281 return I915_READ(D_COMP_BDW);
9282}
9283
3c4c9b81
PZ		 9284static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9285{
9286 struct drm_device *dev = dev_priv->dev;
9287
9288 if (IS_HASWELL(dev)) {
9289 mutex_lock(&dev_priv->rps.hw_lock);
9290 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9291 val))
f475dadf 9292 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9293 mutex_unlock(&dev_priv->rps.hw_lock);
9294 } else {
9ccd5aeb
PZ		 9295 I915_WRITE(D_COMP_BDW, val);
9296 POSTING_READ(D_COMP_BDW);
3c4c9b81 9297 }
be256dc7
PZ		 9298}
9299
9300/*
9301 * This function implements pieces of two sequences from BSpec:
9302 * - Sequence for display software to disable LCPLL
9303 * - Sequence for display software to allow package C8+
9304 * The steps implemented here are just the steps that actually touch the LCPLL
9305 * register. Callers should take care of disabling all the display engine
9306 * functions, doing the mode unset, fixing interrupts, etc.
9307 */
6ff58d53
PZ		 9308static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9309 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9310{
9311 uint32_t val;
9312
9313 assert_can_disable_lcpll(dev_priv);
9314
9315 val = I915_READ(LCPLL_CTL);
9316
9317 if (switch_to_fclk) {
9318 val |= LCPLL_CD_SOURCE_FCLK;
9319 I915_WRITE(LCPLL_CTL, val);
9320
9321 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9322 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9323 DRM_ERROR("Switching to FCLK failed\n");
9324
9325 val = I915_READ(LCPLL_CTL);
9326 }
9327
9328 val |= LCPLL_PLL_DISABLE;
9329 I915_WRITE(LCPLL_CTL, val);
9330 POSTING_READ(LCPLL_CTL);
9331
9332 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9333 DRM_ERROR("LCPLL still locked\n");
9334
9ccd5aeb 9335 val = hsw_read_dcomp(dev_priv);
be256dc7 9336 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9337 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9338 ndelay(100);
9339
9ccd5aeb
PZ		 9340 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9341 1))
be256dc7
PZ		 9342 DRM_ERROR("D_COMP RCOMP still in progress\n");
9343
9344 if (allow_power_down) {
9345 val = I915_READ(LCPLL_CTL);
9346 val |= LCPLL_POWER_DOWN_ALLOW;
9347 I915_WRITE(LCPLL_CTL, val);
9348 POSTING_READ(LCPLL_CTL);
9349 }
9350}
9351
9352/*
9353 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9354 * source.
9355 */
6ff58d53 9356static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9357{
9358 uint32_t val;
9359
9360 val = I915_READ(LCPLL_CTL);
9361
9362 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9363 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9364 return;
9365
a8a8bd54
PZ		 9366 /*
9367 * Make sure we're not on PC8 state before disabling PC8, otherwise
9368 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9369 */
59bad947 9370 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9371
be256dc7
PZ		 9372 if (val & LCPLL_POWER_DOWN_ALLOW) {
9373 val &= ~LCPLL_POWER_DOWN_ALLOW;
9374 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9375 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9376 }
9377
9ccd5aeb 9378 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9379 val |= D_COMP_COMP_FORCE;
9380 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9381 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9382
9383 val = I915_READ(LCPLL_CTL);
9384 val &= ~LCPLL_PLL_DISABLE;
9385 I915_WRITE(LCPLL_CTL, val);
9386
9387 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9388 DRM_ERROR("LCPLL not locked yet\n");
9389
9390 if (val & LCPLL_CD_SOURCE_FCLK) {
9391 val = I915_READ(LCPLL_CTL);
9392 val &= ~LCPLL_CD_SOURCE_FCLK;
9393 I915_WRITE(LCPLL_CTL, val);
9394
9395 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9396 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9397 DRM_ERROR("Switching back to LCPLL failed\n");
9398 }
215733fa 9399
59bad947 9400 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9401 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9402}
9403
765dab67
PZ		 9404/*
9405 * Package states C8 and deeper are really deep PC states that can only be
9406 * reached when all the devices on the system allow it, so even if the graphics
9407 * device allows PC8+, it doesn't mean the system will actually get to these
9408 * states. Our driver only allows PC8+ when going into runtime PM.
9409 *
9410 * The requirements for PC8+ are that all the outputs are disabled, the power
9411 * well is disabled and most interrupts are disabled, and these are also
9412 * requirements for runtime PM. When these conditions are met, we manually do
9413 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9414 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9415 * hang the machine.
9416 *
9417 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9418 * the state of some registers, so when we come back from PC8+ we need to
9419 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9420 * need to take care of the registers kept by RC6. Notice that this happens even
9421 * if we don't put the device in PCI D3 state (which is what currently happens
9422 * because of the runtime PM support).
9423 *
9424 * For more, read "Display Sequences for Package C8" on the hardware
9425 * documentation.
9426 */
a14cb6fc 9427void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9428{
c67a470b
PZ		 9429 struct drm_device *dev = dev_priv->dev;
9430 uint32_t val;
9431
c67a470b
PZ		 9432 DRM_DEBUG_KMS("Enabling package C8+\n");
9433
c67a470b
PZ		 9434 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9435 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9436 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9437 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9438 }
9439
9440 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9441 hsw_disable_lcpll(dev_priv, true, true);
9442}
9443
a14cb6fc 9444void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9445{
9446 struct drm_device *dev = dev_priv->dev;
9447 uint32_t val;
9448
c67a470b
PZ		 9449 DRM_DEBUG_KMS("Disabling package C8+\n");
9450
9451 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9452 lpt_init_pch_refclk(dev);
9453
9454 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9455 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9456 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9457 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9458 }
9459
9460 intel_prepare_ddi(dev);
c67a470b
PZ		 9461}
9462
27c329ed 9463static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9464{
a821fc46 9465 struct drm_device *dev = old_state->dev;
27c329ed 9466 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9467
27c329ed 9468 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9469}
9470
b432e5cf 9471/* compute the max rate for new configuration */
27c329ed 9472static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9473{
b432e5cf 9474 struct intel_crtc *intel_crtc;
27c329ed 9475 struct intel_crtc_state *crtc_state;
b432e5cf 9476 int max_pixel_rate = 0;
b432e5cf 9477
27c329ed
ML		 9478 for_each_intel_crtc(state->dev, intel_crtc) {
9479 int pixel_rate;
9480
9481 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9482 if (IS_ERR(crtc_state))
9483 return PTR_ERR(crtc_state);
9484
9485 if (!crtc_state->base.enable)
b432e5cf
VS		 9486 continue;
9487
27c329ed 9488 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9489
9490 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9491 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9492 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9493
9494 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9495 }
9496
9497 return max_pixel_rate;
9498}
9499
9500static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9501{
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503 uint32_t val, data;
9504 int ret;
9505
9506 if (WARN((I915_READ(LCPLL_CTL) &
9507 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9508 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9509 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9510 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9511 "trying to change cdclk frequency with cdclk not enabled\n"))
9512 return;
9513
9514 mutex_lock(&dev_priv->rps.hw_lock);
9515 ret = sandybridge_pcode_write(dev_priv,
9516 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9517 mutex_unlock(&dev_priv->rps.hw_lock);
9518 if (ret) {
9519 DRM_ERROR("failed to inform pcode about cdclk change\n");
9520 return;
9521 }
9522
9523 val = I915_READ(LCPLL_CTL);
9524 val |= LCPLL_CD_SOURCE_FCLK;
9525 I915_WRITE(LCPLL_CTL, val);
9526
9527 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9528 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9529 DRM_ERROR("Switching to FCLK failed\n");
9530
9531 val = I915_READ(LCPLL_CTL);
9532 val &= ~LCPLL_CLK_FREQ_MASK;
9533
9534 switch (cdclk) {
9535 case 450000:
9536 val |= LCPLL_CLK_FREQ_450;
9537 data = 0;
9538 break;
9539 case 540000:
9540 val |= LCPLL_CLK_FREQ_54O_BDW;
9541 data = 1;
9542 break;
9543 case 337500:
9544 val |= LCPLL_CLK_FREQ_337_5_BDW;
9545 data = 2;
9546 break;
9547 case 675000:
9548 val |= LCPLL_CLK_FREQ_675_BDW;
9549 data = 3;
9550 break;
9551 default:
9552 WARN(1, "invalid cdclk frequency\n");
9553 return;
9554 }
9555
9556 I915_WRITE(LCPLL_CTL, val);
9557
9558 val = I915_READ(LCPLL_CTL);
9559 val &= ~LCPLL_CD_SOURCE_FCLK;
9560 I915_WRITE(LCPLL_CTL, val);
9561
9562 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9563 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9564 DRM_ERROR("Switching back to LCPLL failed\n");
9565
9566 mutex_lock(&dev_priv->rps.hw_lock);
9567 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9568 mutex_unlock(&dev_priv->rps.hw_lock);
9569
9570 intel_update_cdclk(dev);
9571
9572 WARN(cdclk != dev_priv->cdclk_freq,
9573 "cdclk requested %d kHz but got %d kHz\n",
9574 cdclk, dev_priv->cdclk_freq);
9575}
9576
27c329ed 9577static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9578{
27c329ed
ML		 9579 struct drm_i915_private *dev_priv = to_i915(state->dev);
9580 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9581 int cdclk;
9582
9583 /*
9584 * FIXME should also account for plane ratio
9585 * once 64bpp pixel formats are supported.
9586 */
27c329ed 9587 if (max_pixclk > 540000)
b432e5cf 9588 cdclk = 675000;
27c329ed 9589 else if (max_pixclk > 450000)
b432e5cf 9590 cdclk = 540000;
27c329ed 9591 else if (max_pixclk > 337500)
b432e5cf
VS		 9592 cdclk = 450000;
9593 else
9594 cdclk = 337500;
9595
9596 /*
9597 * FIXME move the cdclk caclulation to
9598 * compute_config() so we can fail gracegully.
9599 */
9600 if (cdclk > dev_priv->max_cdclk_freq) {
9601 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9602 cdclk, dev_priv->max_cdclk_freq);
9603 cdclk = dev_priv->max_cdclk_freq;
9604 }
9605
27c329ed 9606 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9607
9608 return 0;
9609}
9610
27c329ed 9611static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9612{
27c329ed
ML		 9613 struct drm_device *dev = old_state->dev;
9614 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9615
27c329ed 9616 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9617}
9618
190f68c5
ACO		 9619static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9620 struct intel_crtc_state *crtc_state)
09b4ddf9 9621{
190f68c5 9622 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9623 return -EINVAL;
716c2e55 9624
c7653199 9625 crtc->lowfreq_avail = false;
644cef34 9626
c8f7a0db 9627 return 0;
79e53945
JB		 9628}
9629
3760b59c
S		 9630static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9631 enum port port,
9632 struct intel_crtc_state *pipe_config)
9633{
9634 switch (port) {
9635 case PORT_A:
9636 pipe_config->ddi_pll_sel = SKL_DPLL0;
9637 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9638 break;
9639 case PORT_B:
9640 pipe_config->ddi_pll_sel = SKL_DPLL1;
9641 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9642 break;
9643 case PORT_C:
9644 pipe_config->ddi_pll_sel = SKL_DPLL2;
9645 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9646 break;
9647 default:
9648 DRM_ERROR("Incorrect port type\n");
9649 }
9650}
9651
96b7dfb7
S		 9652static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9653 enum port port,
5cec258b 9654 struct intel_crtc_state *pipe_config)
96b7dfb7 9655{
3148ade7 9656 u32 temp, dpll_ctl1;
96b7dfb7
S		 9657
9658 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9659 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9660
9661 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9662 case SKL_DPLL0:
9663 /*
9664 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9665 * of the shared DPLL framework and thus needs to be read out
9666 * separately
9667 */
9668 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9669 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9670 break;
96b7dfb7
S		 9671 case SKL_DPLL1:
9672 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9673 break;
9674 case SKL_DPLL2:
9675 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9676 break;
9677 case SKL_DPLL3:
9678 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9679 break;
96b7dfb7
S		 9680 }
9681}
9682
7d2c8175
DL		 9683static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9684 enum port port,
5cec258b 9685 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9686{
9687 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9688
9689 switch (pipe_config->ddi_pll_sel) {
9690 case PORT_CLK_SEL_WRPLL1:
9691 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9692 break;
9693 case PORT_CLK_SEL_WRPLL2:
9694 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9695 break;
9696 }
9697}
9698
26804afd 9699static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9700 struct intel_crtc_state *pipe_config)
26804afd
DV		 9701{
9702 struct drm_device *dev = crtc->base.dev;
9703 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9704 struct intel_shared_dpll *pll;
26804afd
DV		 9705 enum port port;
9706 uint32_t tmp;
9707
9708 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9709
9710 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9711
96b7dfb7
S		 9712 if (IS_SKYLAKE(dev))
9713 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9714 else if (IS_BROXTON(dev))
9715 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9716 else
9717 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9718
d452c5b6
DV		 9719 if (pipe_config->shared_dpll >= 0) {
9720 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9721
9722 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9723 &pipe_config->dpll_hw_state));
9724 }
9725
26804afd
DV		 9726 /*
9727 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9728 * DDI E. So just check whether this pipe is wired to DDI E and whether
9729 * the PCH transcoder is on.
9730 */
ca370455
DL		 9731 if (INTEL_INFO(dev)->gen < 9 &&
9732 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9733 pipe_config->has_pch_encoder = true;
9734
9735 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9736 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9737 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9738
9739 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9740 }
9741}
9742
0e8ffe1b 9743static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9744 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9745{
9746 struct drm_device *dev = crtc->base.dev;
9747 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9748 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9749 uint32_t tmp;
9750
f458ebbc 9751 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9752 POWER_DOMAIN_PIPE(crtc->pipe)))
9753 return false;
9754
e143a21c 9755 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9756 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9757
eccb140b
DV		 9758 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9759 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9760 enum pipe trans_edp_pipe;
9761 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9762 default:
9763 WARN(1, "unknown pipe linked to edp transcoder\n");
9764 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9765 case TRANS_DDI_EDP_INPUT_A_ON:
9766 trans_edp_pipe = PIPE_A;
9767 break;
9768 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9769 trans_edp_pipe = PIPE_B;
9770 break;
9771 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9772 trans_edp_pipe = PIPE_C;
9773 break;
9774 }
9775
9776 if (trans_edp_pipe == crtc->pipe)
9777 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9778 }
9779
f458ebbc 9780 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9781 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9782 return false;
9783
eccb140b 9784 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9785 if (!(tmp & PIPECONF_ENABLE))
9786 return false;
9787
26804afd 9788 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9789
1bd1bd80
DV		 9790 intel_get_pipe_timings(crtc, pipe_config);
9791
a1b2278e
CK		 9792 if (INTEL_INFO(dev)->gen >= 9) {
9793 skl_init_scalers(dev, crtc, pipe_config);
9794 }
9795
2fa2fe9a 9796 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9797
9798 if (INTEL_INFO(dev)->gen >= 9) {
9799 pipe_config->scaler_state.scaler_id = -1;
9800 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9801 }
9802
bd2e244f 9803 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9804 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9805 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9806 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9807 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9808 else
9809 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9810 }
88adfff1 9811
e59150dc
JB		 9812 if (IS_HASWELL(dev))
9813 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9814 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9815
ebb69c95
CT		 9816 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9817 pipe_config->pixel_multiplier =
9818 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9819 } else {
9820 pipe_config->pixel_multiplier = 1;
9821 }
6c49f241 9822
0e8ffe1b
DV		 9823 return true;
9824}
9825
560b85bb
CW		 9826static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9827{
9828 struct drm_device *dev = crtc->dev;
9829 struct drm_i915_private *dev_priv = dev->dev_private;
9830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9831 uint32_t cntl = 0, size = 0;
560b85bb 9832
dc41c154 9833 if (base) {
3dd512fb
MR		 9834 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9835 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9836 unsigned int stride = roundup_pow_of_two(width) * 4;
9837
9838 switch (stride) {
9839 default:
9840 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9841 width, stride);
9842 stride = 256;
9843 /* fallthrough */
9844 case 256:
9845 case 512:
9846 case 1024:
9847 case 2048:
9848 break;
4b0e333e
CW		 9849 }
9850
dc41c154
VS		 9851 cntl |= CURSOR_ENABLE |
9852 CURSOR_GAMMA_ENABLE |
9853 CURSOR_FORMAT_ARGB |
9854 CURSOR_STRIDE(stride);
9855
9856 size = (height << 12) | width;
4b0e333e 9857 }
560b85bb 9858
dc41c154
VS		 9859 if (intel_crtc->cursor_cntl != 0 &&
9860 (intel_crtc->cursor_base != base ||
9861 intel_crtc->cursor_size != size ||
9862 intel_crtc->cursor_cntl != cntl)) {
9863 /* On these chipsets we can only modify the base/size/stride
9864 * whilst the cursor is disabled.
9865 */
9866 I915_WRITE(_CURACNTR, 0);
4b0e333e 9867 POSTING_READ(_CURACNTR);
dc41c154 9868 intel_crtc->cursor_cntl = 0;
4b0e333e 9869 }
560b85bb 9870
99d1f387 9871 if (intel_crtc->cursor_base != base) {
9db4a9c7 9872 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9873 intel_crtc->cursor_base = base;
9874 }
4726e0b0 9875
dc41c154
VS		 9876 if (intel_crtc->cursor_size != size) {
9877 I915_WRITE(CURSIZE, size);
9878 intel_crtc->cursor_size = size;
4b0e333e 9879 }
560b85bb 9880
4b0e333e 9881 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9882 I915_WRITE(_CURACNTR, cntl);
9883 POSTING_READ(_CURACNTR);
4b0e333e 9884 intel_crtc->cursor_cntl = cntl;
560b85bb 9885 }
560b85bb
CW		 9886}
9887
560b85bb 9888static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9889{
9890 struct drm_device *dev = crtc->dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9893 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9894 uint32_t cntl;
9895
9896 cntl = 0;
9897 if (base) {
9898 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9899 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9900 case 64:
9901 cntl |= CURSOR_MODE_64_ARGB_AX;
9902 break;
9903 case 128:
9904 cntl |= CURSOR_MODE_128_ARGB_AX;
9905 break;
9906 case 256:
9907 cntl |= CURSOR_MODE_256_ARGB_AX;
9908 break;
9909 default:
3dd512fb 9910 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9911 return;
65a21cd6 9912 }
4b0e333e 9913 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9914
9915 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9916 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9917 }
65a21cd6 9918
8e7d688b 9919 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9920 cntl |= CURSOR_ROTATE_180;
9921
4b0e333e
CW		 9922 if (intel_crtc->cursor_cntl != cntl) {
9923 I915_WRITE(CURCNTR(pipe), cntl);
9924 POSTING_READ(CURCNTR(pipe));
9925 intel_crtc->cursor_cntl = cntl;
65a21cd6 9926 }
4b0e333e 9927
65a21cd6 9928 /* and commit changes on next vblank */
5efb3e28
VS		 9929 I915_WRITE(CURBASE(pipe), base);
9930 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9931
9932 intel_crtc->cursor_base = base;
65a21cd6
JB		 9933}
9934
cda4b7d3 9935/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9936static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9937 bool on)
cda4b7d3
CW		 9938{
9939 struct drm_device *dev = crtc->dev;
9940 struct drm_i915_private *dev_priv = dev->dev_private;
9941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9942 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9943 int x = crtc->cursor_x;
9944 int y = crtc->cursor_y;
d6e4db15 9945 u32 base = 0, pos = 0;
cda4b7d3 9946
d6e4db15 9947 if (on)
cda4b7d3 9948 base = intel_crtc->cursor_addr;
cda4b7d3 9949
6e3c9717 9950 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9951 base = 0;
9952
6e3c9717 9953 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9954 base = 0;
9955
9956 if (x < 0) {
3dd512fb 9957 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9958 base = 0;
9959
9960 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9961 x = -x;
9962 }
9963 pos |= x << CURSOR_X_SHIFT;
9964
9965 if (y < 0) {
3dd512fb 9966 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9967 base = 0;
9968
9969 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9970 y = -y;
9971 }
9972 pos |= y << CURSOR_Y_SHIFT;
9973
4b0e333e 9974 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9975 return;
9976
5efb3e28
VS		 9977 I915_WRITE(CURPOS(pipe), pos);
9978
4398ad45
VS		 9979 /* ILK+ do this automagically */
9980 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9981 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9982 base += (intel_crtc->base.cursor->state->crtc_h *
9983 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9984 }
9985
8ac54669 9986 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9987 i845_update_cursor(crtc, base);
9988 else
9989 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9990}
9991
dc41c154
VS		 9992static bool cursor_size_ok(struct drm_device *dev,
9993 uint32_t width, uint32_t height)
9994{
9995 if (width == 0 || height == 0)
9996 return false;
9997
9998 /*
9999 * 845g/865g are special in that they are only limited by
10000 * the width of their cursors, the height is arbitrary up to
10001 * the precision of the register. Everything else requires
10002 * square cursors, limited to a few power-of-two sizes.
10003 */
10004 if (IS_845G(dev) || IS_I865G(dev)) {
10005 if ((width & 63) != 0)
10006 return false;
10007
10008 if (width > (IS_845G(dev) ? 64 : 512))
10009 return false;
10010
10011 if (height > 1023)
10012 return false;
10013 } else {
10014 switch (width | height) {
10015 case 256:
10016 case 128:
10017 if (IS_GEN2(dev))
10018 return false;
10019 case 64:
10020 break;
10021 default:
10022 return false;
10023 }
10024 }
10025
10026 return true;
10027}
10028
79e53945 10029static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10030 u16 *blue, uint32_t start, uint32_t size)
79e53945 10031{
7203425a 10032 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10034
7203425a 10035 for (i = start; i < end; i++) {
79e53945
JB		 10036 intel_crtc->lut_r[i] = red[i] >> 8;
10037 intel_crtc->lut_g[i] = green[i] >> 8;
10038 intel_crtc->lut_b[i] = blue[i] >> 8;
10039 }
10040
10041 intel_crtc_load_lut(crtc);
10042}
10043
79e53945
JB		 10044/* VESA 640x480x72Hz mode to set on the pipe */
10045static struct drm_display_mode load_detect_mode = {
10046 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10047 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10048};
10049
a8bb6818
DV		 10050struct drm_framebuffer *
10051__intel_framebuffer_create(struct drm_device *dev,
10052 struct drm_mode_fb_cmd2 *mode_cmd,
10053 struct drm_i915_gem_object *obj)
d2dff872
CW		 10054{
10055 struct intel_framebuffer *intel_fb;
10056 int ret;
10057
10058 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10059 if (!intel_fb) {
6ccb81f2 10060 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10061 return ERR_PTR(-ENOMEM);
10062 }
10063
10064 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10065 if (ret)
10066 goto err;
d2dff872
CW		 10067
10068 return &intel_fb->base;
dd4916c5 10069err:
6ccb81f2 10070 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10071 kfree(intel_fb);
10072
10073 return ERR_PTR(ret);
d2dff872
CW		 10074}
10075
b5ea642a 10076static struct drm_framebuffer *
a8bb6818
DV		 10077intel_framebuffer_create(struct drm_device *dev,
10078 struct drm_mode_fb_cmd2 *mode_cmd,
10079 struct drm_i915_gem_object *obj)
10080{
10081 struct drm_framebuffer *fb;
10082 int ret;
10083
10084 ret = i915_mutex_lock_interruptible(dev);
10085 if (ret)
10086 return ERR_PTR(ret);
10087 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10088 mutex_unlock(&dev->struct_mutex);
10089
10090 return fb;
10091}
10092
d2dff872
CW		 10093static u32
10094intel_framebuffer_pitch_for_width(int width, int bpp)
10095{
10096 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10097 return ALIGN(pitch, 64);
10098}
10099
10100static u32
10101intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10102{
10103 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10104 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10105}
10106
10107static struct drm_framebuffer *
10108intel_framebuffer_create_for_mode(struct drm_device *dev,
10109 struct drm_display_mode *mode,
10110 int depth, int bpp)
10111{
10112 struct drm_i915_gem_object *obj;
0fed39bd 10113 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10114
10115 obj = i915_gem_alloc_object(dev,
10116 intel_framebuffer_size_for_mode(mode, bpp));
10117 if (obj == NULL)
10118 return ERR_PTR(-ENOMEM);
10119
10120 mode_cmd.width = mode->hdisplay;
10121 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10122 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10123 bpp);
5ca0c34a 10124 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10125
10126 return intel_framebuffer_create(dev, &mode_cmd, obj);
10127}
10128
10129static struct drm_framebuffer *
10130mode_fits_in_fbdev(struct drm_device *dev,
10131 struct drm_display_mode *mode)
10132{
4520f53a 10133#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10134 struct drm_i915_private *dev_priv = dev->dev_private;
10135 struct drm_i915_gem_object *obj;
10136 struct drm_framebuffer *fb;
10137
4c0e5528 10138 if (!dev_priv->fbdev)
d2dff872
CW		 10139 return NULL;
10140
4c0e5528 10141 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10142 return NULL;
10143
4c0e5528
DV		 10144 obj = dev_priv->fbdev->fb->obj;
10145 BUG_ON(!obj);
10146
8bcd4553 10147 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10148 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10149 fb->bits_per_pixel))
d2dff872
CW		 10150 return NULL;
10151
01f2c773 10152 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10153 return NULL;
10154
10155 return fb;
4520f53a
DV		 10156#else
10157 return NULL;
10158#endif
d2dff872
CW		 10159}
10160
d3a40d1b
ACO		 10161static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10162 struct drm_crtc *crtc,
10163 struct drm_display_mode *mode,
10164 struct drm_framebuffer *fb,
10165 int x, int y)
10166{
10167 struct drm_plane_state *plane_state;
10168 int hdisplay, vdisplay;
10169 int ret;
10170
10171 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10172 if (IS_ERR(plane_state))
10173 return PTR_ERR(plane_state);
10174
10175 if (mode)
10176 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10177 else
10178 hdisplay = vdisplay = 0;
10179
10180 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10181 if (ret)
10182 return ret;
10183 drm_atomic_set_fb_for_plane(plane_state, fb);
10184 plane_state->crtc_x = 0;
10185 plane_state->crtc_y = 0;
10186 plane_state->crtc_w = hdisplay;
10187 plane_state->crtc_h = vdisplay;
10188 plane_state->src_x = x << 16;
10189 plane_state->src_y = y << 16;
10190 plane_state->src_w = hdisplay << 16;
10191 plane_state->src_h = vdisplay << 16;
10192
10193 return 0;
10194}
10195
d2434ab7 10196bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10197 struct drm_display_mode *mode,
51fd371b
RC		 10198 struct intel_load_detect_pipe *old,
10199 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10200{
10201 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10202 struct intel_encoder *intel_encoder =
10203 intel_attached_encoder(connector);
79e53945 10204 struct drm_crtc *possible_crtc;
4ef69c7a 10205 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10206 struct drm_crtc *crtc = NULL;
10207 struct drm_device *dev = encoder->dev;
94352cf9 10208 struct drm_framebuffer *fb;
51fd371b 10209 struct drm_mode_config *config = &dev->mode_config;
83a57153 10210 struct drm_atomic_state *state = NULL;
944b0c76 10211 struct drm_connector_state *connector_state;
4be07317 10212 struct intel_crtc_state *crtc_state;
51fd371b 10213 int ret, i = -1;
79e53945 10214
d2dff872 10215 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10216 connector->base.id, connector->name,
8e329a03 10217 encoder->base.id, encoder->name);
d2dff872 10218
51fd371b
RC		 10219retry:
10220 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10221 if (ret)
ad3c558f 10222 goto fail;
6e9f798d 10223
79e53945
JB		 10224 /*
10225 * Algorithm gets a little messy:
7a5e4805 10226 *
79e53945
JB		 10227 * - if the connector already has an assigned crtc, use it (but make
10228 * sure it's on first)
7a5e4805 10229 *
79e53945
JB		 10230 * - try to find the first unused crtc that can drive this connector,
10231 * and use that if we find one
79e53945
JB		 10232 */
10233
10234 /* See if we already have a CRTC for this connector */
10235 if (encoder->crtc) {
10236 crtc = encoder->crtc;
8261b191 10237
51fd371b 10238 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10239 if (ret)
ad3c558f 10240 goto fail;
4d02e2de 10241 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10242 if (ret)
ad3c558f 10243 goto fail;
7b24056b 10244
24218aac 10245 old->dpms_mode = connector->dpms;
8261b191
CW		 10246 old->load_detect_temp = false;
10247
10248 /* Make sure the crtc and connector are running */
24218aac
DV		 10249 if (connector->dpms != DRM_MODE_DPMS_ON)
10250 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10251
7173188d 10252 return true;
79e53945
JB		 10253 }
10254
10255 /* Find an unused one (if possible) */
70e1e0ec 10256 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10257 i++;
10258 if (!(encoder->possible_crtcs & (1 << i)))
10259 continue;
83d65738 10260 if (possible_crtc->state->enable)
a459249c 10261 continue;
a459249c
VS		 10262
10263 crtc = possible_crtc;
10264 break;
79e53945
JB		 10265 }
10266
10267 /*
10268 * If we didn't find an unused CRTC, don't use any.
10269 */
10270 if (!crtc) {
7173188d 10271 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10272 goto fail;
79e53945
JB		 10273 }
10274
51fd371b
RC		 10275 ret = drm_modeset_lock(&crtc->mutex, ctx);
10276 if (ret)
ad3c558f 10277 goto fail;
4d02e2de
DV		 10278 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10279 if (ret)
ad3c558f 10280 goto fail;
79e53945
JB		 10281
10282 intel_crtc = to_intel_crtc(crtc);
24218aac 10283 old->dpms_mode = connector->dpms;
8261b191 10284 old->load_detect_temp = true;
d2dff872 10285 old->release_fb = NULL;
79e53945 10286
83a57153
ACO		 10287 state = drm_atomic_state_alloc(dev);
10288 if (!state)
10289 return false;
10290
10291 state->acquire_ctx = ctx;
10292
944b0c76
ACO		 10293 connector_state = drm_atomic_get_connector_state(state, connector);
10294 if (IS_ERR(connector_state)) {
10295 ret = PTR_ERR(connector_state);
10296 goto fail;
10297 }
10298
10299 connector_state->crtc = crtc;
10300 connector_state->best_encoder = &intel_encoder->base;
10301
4be07317
ACO		 10302 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10303 if (IS_ERR(crtc_state)) {
10304 ret = PTR_ERR(crtc_state);
10305 goto fail;
10306 }
10307
49d6fa21 10308 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10309
6492711d
CW		 10310 if (!mode)
10311 mode = &load_detect_mode;
79e53945 10312
d2dff872
CW		 10313 /* We need a framebuffer large enough to accommodate all accesses
10314 * that the plane may generate whilst we perform load detection.
10315 * We can not rely on the fbcon either being present (we get called
10316 * during its initialisation to detect all boot displays, or it may
10317 * not even exist) or that it is large enough to satisfy the
10318 * requested mode.
10319 */
94352cf9
DV		 10320 fb = mode_fits_in_fbdev(dev, mode);
10321 if (fb == NULL) {
d2dff872 10322 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10323 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10324 old->release_fb = fb;
d2dff872
CW		 10325 } else
10326 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10327 if (IS_ERR(fb)) {
d2dff872 10328 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10329 goto fail;
79e53945 10330 }
79e53945 10331
d3a40d1b
ACO		 10332 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10333 if (ret)
10334 goto fail;
10335
8c7b5ccb
ACO		 10336 drm_mode_copy(&crtc_state->base.mode, mode);
10337
74c090b1 10338 if (drm_atomic_commit(state)) {
6492711d 10339 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10340 if (old->release_fb)
10341 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10342 goto fail;
79e53945 10343 }
9128b040 10344 crtc->primary->crtc = crtc;
7173188d 10345
79e53945 10346 /* let the connector get through one full cycle before testing */
9d0498a2 10347 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10348 return true;
412b61d8 10349
ad3c558f 10350fail:
e5d958ef
ACO		 10351 drm_atomic_state_free(state);
10352 state = NULL;
83a57153 10353
51fd371b
RC		 10354 if (ret == -EDEADLK) {
10355 drm_modeset_backoff(ctx);
10356 goto retry;
10357 }
10358
412b61d8 10359 return false;
79e53945
JB		 10360}
10361
d2434ab7 10362void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10363 struct intel_load_detect_pipe *old,
10364 struct drm_modeset_acquire_ctx *ctx)
79e53945 10365{
83a57153 10366 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10367 struct intel_encoder *intel_encoder =
10368 intel_attached_encoder(connector);
4ef69c7a 10369 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10370 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10372 struct drm_atomic_state *state;
944b0c76 10373 struct drm_connector_state *connector_state;
4be07317 10374 struct intel_crtc_state *crtc_state;
d3a40d1b 10375 int ret;
79e53945 10376
d2dff872 10377 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10378 connector->base.id, connector->name,
8e329a03 10379 encoder->base.id, encoder->name);
d2dff872 10380
8261b191 10381 if (old->load_detect_temp) {
83a57153 10382 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10383 if (!state)
10384 goto fail;
83a57153
ACO		 10385
10386 state->acquire_ctx = ctx;
10387
944b0c76
ACO		 10388 connector_state = drm_atomic_get_connector_state(state, connector);
10389 if (IS_ERR(connector_state))
10390 goto fail;
10391
4be07317
ACO		 10392 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10393 if (IS_ERR(crtc_state))
10394 goto fail;
10395
944b0c76
ACO		 10396 connector_state->best_encoder = NULL;
10397 connector_state->crtc = NULL;
10398
49d6fa21 10399 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10400
d3a40d1b
ACO		 10401 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10402 0, 0);
10403 if (ret)
10404 goto fail;
10405
74c090b1 10406 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10407 if (ret)
10408 goto fail;
d2dff872 10409
36206361
DV		 10410 if (old->release_fb) {
10411 drm_framebuffer_unregister_private(old->release_fb);
10412 drm_framebuffer_unreference(old->release_fb);
10413 }
d2dff872 10414
0622a53c 10415 return;
79e53945
JB		 10416 }
10417
c751ce4f 10418 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10419 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10420 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10421
10422 return;
10423fail:
10424 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10425 drm_atomic_state_free(state);
79e53945
JB		 10426}
10427
da4a1efa 10428static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10429 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10430{
10431 struct drm_i915_private *dev_priv = dev->dev_private;
10432 u32 dpll = pipe_config->dpll_hw_state.dpll;
10433
10434 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10435 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10436 else if (HAS_PCH_SPLIT(dev))
10437 return 120000;
10438 else if (!IS_GEN2(dev))
10439 return 96000;
10440 else
10441 return 48000;
10442}
10443
79e53945 10444/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10445static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10446 struct intel_crtc_state *pipe_config)
79e53945 10447{
f1f644dc 10448 struct drm_device *dev = crtc->base.dev;
79e53945 10449 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10450 int pipe = pipe_config->cpu_transcoder;
293623f7 10451 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10452 u32 fp;
10453 intel_clock_t clock;
dccbea3b 10454 int port_clock;
da4a1efa 10455 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10456
10457 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10458 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10459 else
293623f7 10460 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10461
10462 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10463 if (IS_PINEVIEW(dev)) {
10464 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10465 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10466 } else {
10467 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10468 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10469 }
10470
a6c45cf0 10471 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10472 if (IS_PINEVIEW(dev))
10473 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10474 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10475 else
10476 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10477 DPLL_FPA01_P1_POST_DIV_SHIFT);
10478
10479 switch (dpll & DPLL_MODE_MASK) {
10480 case DPLLB_MODE_DAC_SERIAL:
10481 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10482 5 : 10;
10483 break;
10484 case DPLLB_MODE_LVDS:
10485 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10486 7 : 14;
10487 break;
10488 default:
28c97730 10489 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10490 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10491 return;
79e53945
JB		 10492 }
10493
ac58c3f0 10494 if (IS_PINEVIEW(dev))
dccbea3b 10495 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10496 else
dccbea3b 10497 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10498 } else {
0fb58223 10499 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10500 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10501
10502 if (is_lvds) {
10503 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10504 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10505
10506 if (lvds & LVDS_CLKB_POWER_UP)
10507 clock.p2 = 7;
10508 else
10509 clock.p2 = 14;
79e53945
JB		 10510 } else {
10511 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10512 clock.p1 = 2;
10513 else {
10514 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10515 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10516 }
10517 if (dpll & PLL_P2_DIVIDE_BY_4)
10518 clock.p2 = 4;
10519 else
10520 clock.p2 = 2;
79e53945 10521 }
da4a1efa 10522
dccbea3b 10523 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10524 }
10525
18442d08
VS		 10526 /*
10527 * This value includes pixel_multiplier. We will use
241bfc38 10528 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10529 * encoder's get_config() function.
10530 */
dccbea3b 10531 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10532}
10533
6878da05
VS		 10534int intel_dotclock_calculate(int link_freq,
10535 const struct intel_link_m_n *m_n)
f1f644dc 10536{
f1f644dc
JB		 10537 /*
10538 * The calculation for the data clock is:
1041a02f 10539 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10540 * But we want to avoid losing precison if possible, so:
1041a02f 10541 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10542 *
10543 * and the link clock is simpler:
1041a02f 10544 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10545 */
10546
6878da05
VS		 10547 if (!m_n->link_n)
10548 return 0;
f1f644dc 10549
6878da05
VS		 10550 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10551}
f1f644dc 10552
18442d08 10553static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10554 struct intel_crtc_state *pipe_config)
6878da05
VS		 10555{
10556 struct drm_device *dev = crtc->base.dev;
79e53945 10557
18442d08
VS		 10558 /* read out port_clock from the DPLL */
10559 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10560
f1f644dc 10561 /*
18442d08 10562 * This value does not include pixel_multiplier.
241bfc38 10563 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10564 * agree once we know their relationship in the encoder's
10565 * get_config() function.
79e53945 10566 */
2d112de7 10567 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10568 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10569 &pipe_config->fdi_m_n);
79e53945
JB		 10570}
10571
10572/** Returns the currently programmed mode of the given pipe. */
10573struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10574 struct drm_crtc *crtc)
10575{
548f245b 10576 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10578 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10579 struct drm_display_mode *mode;
5cec258b 10580 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10581 int htot = I915_READ(HTOTAL(cpu_transcoder));
10582 int hsync = I915_READ(HSYNC(cpu_transcoder));
10583 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10584 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10585 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10586
10587 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10588 if (!mode)
10589 return NULL;
10590
f1f644dc
JB		 10591 /*
10592 * Construct a pipe_config sufficient for getting the clock info
10593 * back out of crtc_clock_get.
10594 *
10595 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10596 * to use a real value here instead.
10597 */
293623f7 10598 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10599 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10600 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10601 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10602 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10603 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10604
773ae034 10605 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10606 mode->hdisplay = (htot & 0xffff) + 1;
10607 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10608 mode->hsync_start = (hsync & 0xffff) + 1;
10609 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10610 mode->vdisplay = (vtot & 0xffff) + 1;
10611 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10612 mode->vsync_start = (vsync & 0xffff) + 1;
10613 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10614
10615 drm_mode_set_name(mode);
79e53945
JB		 10616
10617 return mode;
10618}
10619
f047e395
CW		 10620void intel_mark_busy(struct drm_device *dev)
10621{
c67a470b
PZ		 10622 struct drm_i915_private *dev_priv = dev->dev_private;
10623
f62a0076
CW		 10624 if (dev_priv->mm.busy)
10625 return;
10626
43694d69 10627 intel_runtime_pm_get(dev_priv);
c67a470b 10628 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10629 if (INTEL_INFO(dev)->gen >= 6)
10630 gen6_rps_busy(dev_priv);
f62a0076 10631 dev_priv->mm.busy = true;
f047e395
CW		 10632}
10633
10634void intel_mark_idle(struct drm_device *dev)
652c393a 10635{
c67a470b 10636 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10637
f62a0076
CW		 10638 if (!dev_priv->mm.busy)
10639 return;
10640
10641 dev_priv->mm.busy = false;
10642
3d13ef2e 10643 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10644 gen6_rps_idle(dev->dev_private);
bb4cdd53 10645
43694d69 10646 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10647}
10648
79e53945
JB		 10649static void intel_crtc_destroy(struct drm_crtc *crtc)
10650{
10651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10652 struct drm_device *dev = crtc->dev;
10653 struct intel_unpin_work *work;
67e77c5a 10654
5e2d7afc 10655 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10656 work = intel_crtc->unpin_work;
10657 intel_crtc->unpin_work = NULL;
5e2d7afc 10658 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10659
10660 if (work) {
10661 cancel_work_sync(&work->work);
10662 kfree(work);
10663 }
79e53945
JB		 10664
10665 drm_crtc_cleanup(crtc);
67e77c5a 10666
79e53945
JB		 10667 kfree(intel_crtc);
10668}
10669
6b95a207
KH		 10670static void intel_unpin_work_fn(struct work_struct *__work)
10671{
10672 struct intel_unpin_work *work =
10673 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10674 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10675 struct drm_device *dev = crtc->base.dev;
10676 struct drm_plane *primary = crtc->base.primary;
6b95a207 10677
b4a98e57 10678 mutex_lock(&dev->struct_mutex);
a9ff8714 10679 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10680 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10681
f06cc1b9 10682 if (work->flip_queued_req)
146d84f0 10683 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10684 mutex_unlock(&dev->struct_mutex);
10685
a9ff8714 10686 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10687 drm_framebuffer_unreference(work->old_fb);
f99d7069 10688
a9ff8714
VS		 10689 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10690 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10691
6b95a207
KH		 10692 kfree(work);
10693}
10694
1afe3e9d 10695static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10696 struct drm_crtc *crtc)
6b95a207 10697{
6b95a207
KH		 10698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10699 struct intel_unpin_work *work;
6b95a207
KH		 10700 unsigned long flags;
10701
10702 /* Ignore early vblank irqs */
10703 if (intel_crtc == NULL)
10704 return;
10705
f326038a
DV		 10706 /*
10707 * This is called both by irq handlers and the reset code (to complete
10708 * lost pageflips) so needs the full irqsave spinlocks.
10709 */
6b95a207
KH		 10710 spin_lock_irqsave(&dev->event_lock, flags);
10711 work = intel_crtc->unpin_work;
e7d841ca
CW		 10712
10713 /* Ensure we don't miss a work->pending update ... */
10714 smp_rmb();
10715
10716 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10717 spin_unlock_irqrestore(&dev->event_lock, flags);
10718 return;
10719 }
10720
d6bbafa1 10721 page_flip_completed(intel_crtc);
0af7e4df 10722
6b95a207 10723 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10724}
10725
1afe3e9d
JB		 10726void intel_finish_page_flip(struct drm_device *dev, int pipe)
10727{
fbee40df 10728 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10729 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10730
49b14a5c 10731 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10732}
10733
10734void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10735{
fbee40df 10736 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10737 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10738
49b14a5c 10739 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10740}
10741
75f7f3ec
VS		 10742/* Is 'a' after or equal to 'b'? */
10743static bool g4x_flip_count_after_eq(u32 a, u32 b)
10744{
10745 return !((a - b) & 0x80000000);
10746}
10747
10748static bool page_flip_finished(struct intel_crtc *crtc)
10749{
10750 struct drm_device *dev = crtc->base.dev;
10751 struct drm_i915_private *dev_priv = dev->dev_private;
10752
bdfa7542
VS		 10753 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10754 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10755 return true;
10756
75f7f3ec
VS		 10757 /*
10758 * The relevant registers doen't exist on pre-ctg.
10759 * As the flip done interrupt doesn't trigger for mmio
10760 * flips on gmch platforms, a flip count check isn't
10761 * really needed there. But since ctg has the registers,
10762 * include it in the check anyway.
10763 */
10764 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10765 return true;
10766
10767 /*
10768 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10769 * used the same base address. In that case the mmio flip might
10770 * have completed, but the CS hasn't even executed the flip yet.
10771 *
10772 * A flip count check isn't enough as the CS might have updated
10773 * the base address just after start of vblank, but before we
10774 * managed to process the interrupt. This means we'd complete the
10775 * CS flip too soon.
10776 *
10777 * Combining both checks should get us a good enough result. It may
10778 * still happen that the CS flip has been executed, but has not
10779 * yet actually completed. But in case the base address is the same
10780 * anyway, we don't really care.
10781 */
10782 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10783 crtc->unpin_work->gtt_offset &&
10784 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10785 crtc->unpin_work->flip_count);
10786}
10787
6b95a207
KH		 10788void intel_prepare_page_flip(struct drm_device *dev, int plane)
10789{
fbee40df 10790 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10791 struct intel_crtc *intel_crtc =
10792 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10793 unsigned long flags;
10794
f326038a
DV		 10795
10796 /*
10797 * This is called both by irq handlers and the reset code (to complete
10798 * lost pageflips) so needs the full irqsave spinlocks.
10799 *
10800 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10801 * generate a page-flip completion irq, i.e. every modeset
10802 * is also accompanied by a spurious intel_prepare_page_flip().
10803 */
6b95a207 10804 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10805 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10806 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10807 spin_unlock_irqrestore(&dev->event_lock, flags);
10808}
10809
eba905b2 10810static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10811{
10812 /* Ensure that the work item is consistent when activating it ... */
10813 smp_wmb();
10814 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10815 /* and that it is marked active as soon as the irq could fire. */
10816 smp_wmb();
10817}
10818
8c9f3aaf
JB		 10819static int intel_gen2_queue_flip(struct drm_device *dev,
10820 struct drm_crtc *crtc,
10821 struct drm_framebuffer *fb,
ed8d1975 10822 struct drm_i915_gem_object *obj,
6258fbe2 10823 struct drm_i915_gem_request *req,
ed8d1975 10824 uint32_t flags)
8c9f3aaf 10825{
6258fbe2 10826 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10828 u32 flip_mask;
10829 int ret;
10830
5fb9de1a 10831 ret = intel_ring_begin(req, 6);
8c9f3aaf 10832 if (ret)
4fa62c89 10833 return ret;
8c9f3aaf
JB		 10834
10835 /* Can't queue multiple flips, so wait for the previous
10836 * one to finish before executing the next.
10837 */
10838 if (intel_crtc->plane)
10839 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10840 else
10841 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10842 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10843 intel_ring_emit(ring, MI_NOOP);
10844 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10845 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10846 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10847 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10848 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10849
10850 intel_mark_page_flip_active(intel_crtc);
83d4092b 10851 return 0;
8c9f3aaf
JB		 10852}
10853
10854static int intel_gen3_queue_flip(struct drm_device *dev,
10855 struct drm_crtc *crtc,
10856 struct drm_framebuffer *fb,
ed8d1975 10857 struct drm_i915_gem_object *obj,
6258fbe2 10858 struct drm_i915_gem_request *req,
ed8d1975 10859 uint32_t flags)
8c9f3aaf 10860{
6258fbe2 10861 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10863 u32 flip_mask;
10864 int ret;
10865
5fb9de1a 10866 ret = intel_ring_begin(req, 6);
8c9f3aaf 10867 if (ret)
4fa62c89 10868 return ret;
8c9f3aaf
JB		 10869
10870 if (intel_crtc->plane)
10871 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10872 else
10873 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10874 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10875 intel_ring_emit(ring, MI_NOOP);
10876 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10877 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10878 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10879 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10880 intel_ring_emit(ring, MI_NOOP);
10881
e7d841ca 10882 intel_mark_page_flip_active(intel_crtc);
83d4092b 10883 return 0;
8c9f3aaf
JB		 10884}
10885
10886static int intel_gen4_queue_flip(struct drm_device *dev,
10887 struct drm_crtc *crtc,
10888 struct drm_framebuffer *fb,
ed8d1975 10889 struct drm_i915_gem_object *obj,
6258fbe2 10890 struct drm_i915_gem_request *req,
ed8d1975 10891 uint32_t flags)
8c9f3aaf 10892{
6258fbe2 10893 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10894 struct drm_i915_private *dev_priv = dev->dev_private;
10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10896 uint32_t pf, pipesrc;
10897 int ret;
10898
5fb9de1a 10899 ret = intel_ring_begin(req, 4);
8c9f3aaf 10900 if (ret)
4fa62c89 10901 return ret;
8c9f3aaf
JB		 10902
10903 /* i965+ uses the linear or tiled offsets from the
10904 * Display Registers (which do not change across a page-flip)
10905 * so we need only reprogram the base address.
10906 */
6d90c952
DV		 10907 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10908 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10909 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10910 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10911 obj->tiling_mode);
8c9f3aaf
JB		 10912
10913 /* XXX Enabling the panel-fitter across page-flip is so far
10914 * untested on non-native modes, so ignore it for now.
10915 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10916 */
10917 pf = 0;
10918 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10919 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10920
10921 intel_mark_page_flip_active(intel_crtc);
83d4092b 10922 return 0;
8c9f3aaf
JB		 10923}
10924
10925static int intel_gen6_queue_flip(struct drm_device *dev,
10926 struct drm_crtc *crtc,
10927 struct drm_framebuffer *fb,
ed8d1975 10928 struct drm_i915_gem_object *obj,
6258fbe2 10929 struct drm_i915_gem_request *req,
ed8d1975 10930 uint32_t flags)
8c9f3aaf 10931{
6258fbe2 10932 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10933 struct drm_i915_private *dev_priv = dev->dev_private;
10934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10935 uint32_t pf, pipesrc;
10936 int ret;
10937
5fb9de1a 10938 ret = intel_ring_begin(req, 4);
8c9f3aaf 10939 if (ret)
4fa62c89 10940 return ret;
8c9f3aaf 10941
6d90c952
DV		 10942 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10943 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10944 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10945 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10946
dc257cf1
DV		 10947 /* Contrary to the suggestions in the documentation,
10948 * "Enable Panel Fitter" does not seem to be required when page
10949 * flipping with a non-native mode, and worse causes a normal
10950 * modeset to fail.
10951 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10952 */
10953 pf = 0;
8c9f3aaf 10954 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10955 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10956
10957 intel_mark_page_flip_active(intel_crtc);
83d4092b 10958 return 0;
8c9f3aaf
JB		 10959}
10960
7c9017e5
JB		 10961static int intel_gen7_queue_flip(struct drm_device *dev,
10962 struct drm_crtc *crtc,
10963 struct drm_framebuffer *fb,
ed8d1975 10964 struct drm_i915_gem_object *obj,
6258fbe2 10965 struct drm_i915_gem_request *req,
ed8d1975 10966 uint32_t flags)
7c9017e5 10967{
6258fbe2 10968 struct intel_engine_cs *ring = req->ring;
7c9017e5 10969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10970 uint32_t plane_bit = 0;
ffe74d75
CW		 10971 int len, ret;
10972
eba905b2 10973 switch (intel_crtc->plane) {
cb05d8de
DV		 10974 case PLANE_A:
10975 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10976 break;
10977 case PLANE_B:
10978 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10979 break;
10980 case PLANE_C:
10981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10982 break;
10983 default:
10984 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10985 return -ENODEV;
cb05d8de
DV		 10986 }
10987
ffe74d75 10988 len = 4;
f476828a 10989 if (ring->id == RCS) {
ffe74d75 10990 len += 6;
f476828a
DL		 10991 /*
10992 * On Gen 8, SRM is now taking an extra dword to accommodate
10993 * 48bits addresses, and we need a NOOP for the batch size to
10994 * stay even.
10995 */
10996 if (IS_GEN8(dev))
10997 len += 2;
10998 }
ffe74d75 10999
f66fab8e
VS		 11000 /*
11001 * BSpec MI_DISPLAY_FLIP for IVB:
11002 * "The full packet must be contained within the same cache line."
11003 *
11004 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11005 * cacheline, if we ever start emitting more commands before
11006 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11007 * then do the cacheline alignment, and finally emit the
11008 * MI_DISPLAY_FLIP.
11009 */
bba09b12 11010 ret = intel_ring_cacheline_align(req);
f66fab8e 11011 if (ret)
4fa62c89 11012 return ret;
f66fab8e 11013
5fb9de1a 11014 ret = intel_ring_begin(req, len);
7c9017e5 11015 if (ret)
4fa62c89 11016 return ret;
7c9017e5 11017
ffe74d75
CW		 11018 /* Unmask the flip-done completion message. Note that the bspec says that
11019 * we should do this for both the BCS and RCS, and that we must not unmask
11020 * more than one flip event at any time (or ensure that one flip message
11021 * can be sent by waiting for flip-done prior to queueing new flips).
11022 * Experimentation says that BCS works despite DERRMR masking all
11023 * flip-done completion events and that unmasking all planes at once
11024 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11025 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11026 */
11027 if (ring->id == RCS) {
11028 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11029 intel_ring_emit(ring, DERRMR);
11030 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11031 DERRMR_PIPEB_PRI_FLIP_DONE |
11032 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11033 if (IS_GEN8(dev))
f1afe24f 11034 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11035 MI_SRM_LRM_GLOBAL_GTT);
11036 else
f1afe24f 11037 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11038 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11039 intel_ring_emit(ring, DERRMR);
11040 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11041 if (IS_GEN8(dev)) {
11042 intel_ring_emit(ring, 0);
11043 intel_ring_emit(ring, MI_NOOP);
11044 }
ffe74d75
CW		 11045 }
11046
cb05d8de 11047 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11048 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11049 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11050 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11051
11052 intel_mark_page_flip_active(intel_crtc);
83d4092b 11053 return 0;
7c9017e5
JB		 11054}
11055
84c33a64
SG		 11056static bool use_mmio_flip(struct intel_engine_cs *ring,
11057 struct drm_i915_gem_object *obj)
11058{
11059 /*
11060 * This is not being used for older platforms, because
11061 * non-availability of flip done interrupt forces us to use
11062 * CS flips. Older platforms derive flip done using some clever
11063 * tricks involving the flip_pending status bits and vblank irqs.
11064 * So using MMIO flips there would disrupt this mechanism.
11065 */
11066
8e09bf83
CW		 11067 if (ring == NULL)
11068 return true;
11069
84c33a64
SG		 11070 if (INTEL_INFO(ring->dev)->gen < 5)
11071 return false;
11072
11073 if (i915.use_mmio_flip < 0)
11074 return false;
11075 else if (i915.use_mmio_flip > 0)
11076 return true;
14bf993e
OM		 11077 else if (i915.enable_execlists)
11078 return true;
84c33a64 11079 else
b4716185 11080 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11081}
11082
ff944564
DL		 11083static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11084{
11085 struct drm_device *dev = intel_crtc->base.dev;
11086 struct drm_i915_private *dev_priv = dev->dev_private;
11087 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11088 const enum pipe pipe = intel_crtc->pipe;
11089 u32 ctl, stride;
11090
11091 ctl = I915_READ(PLANE_CTL(pipe, 0));
11092 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11093 switch (fb->modifier[0]) {
11094 case DRM_FORMAT_MOD_NONE:
11095 break;
11096 case I915_FORMAT_MOD_X_TILED:
ff944564 11097 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11098 break;
11099 case I915_FORMAT_MOD_Y_TILED:
11100 ctl |= PLANE_CTL_TILED_Y;
11101 break;
11102 case I915_FORMAT_MOD_Yf_TILED:
11103 ctl |= PLANE_CTL_TILED_YF;
11104 break;
11105 default:
11106 MISSING_CASE(fb->modifier[0]);
11107 }
ff944564
DL		 11108
11109 /*
11110 * The stride is either expressed as a multiple of 64 bytes chunks for
11111 * linear buffers or in number of tiles for tiled buffers.
11112 */
2ebef630
TU		 11113 stride = fb->pitches[0] /
11114 intel_fb_stride_alignment(dev, fb->modifier[0],
11115 fb->pixel_format);
ff944564
DL		 11116
11117 /*
11118 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11119 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11120 */
11121 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11122 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11123
11124 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11125 POSTING_READ(PLANE_SURF(pipe, 0));
11126}
11127
11128static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11129{
11130 struct drm_device *dev = intel_crtc->base.dev;
11131 struct drm_i915_private *dev_priv = dev->dev_private;
11132 struct intel_framebuffer *intel_fb =
11133 to_intel_framebuffer(intel_crtc->base.primary->fb);
11134 struct drm_i915_gem_object *obj = intel_fb->obj;
11135 u32 dspcntr;
11136 u32 reg;
11137
84c33a64
SG		 11138 reg = DSPCNTR(intel_crtc->plane);
11139 dspcntr = I915_READ(reg);
11140
c5d97472
DL		 11141 if (obj->tiling_mode != I915_TILING_NONE)
11142 dspcntr |= DISPPLANE_TILED;
11143 else
11144 dspcntr &= ~DISPPLANE_TILED;
11145
84c33a64
SG		 11146 I915_WRITE(reg, dspcntr);
11147
11148 I915_WRITE(DSPSURF(intel_crtc->plane),
11149 intel_crtc->unpin_work->gtt_offset);
11150 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11151
ff944564
DL		 11152}
11153
11154/*
11155 * XXX: This is the temporary way to update the plane registers until we get
11156 * around to using the usual plane update functions for MMIO flips
11157 */
11158static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11159{
11160 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11161 u32 start_vbl_count;
11162
11163 intel_mark_page_flip_active(intel_crtc);
11164
8f539a83 11165 intel_pipe_update_start(intel_crtc, &start_vbl_count);
ff944564
DL		 11166
11167 if (INTEL_INFO(dev)->gen >= 9)
11168 skl_do_mmio_flip(intel_crtc);
11169 else
11170 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11171 ilk_do_mmio_flip(intel_crtc);
11172
8f539a83 11173 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11174}
11175
9362c7c5 11176static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11177{
b2cfe0ab
CW		 11178 struct intel_mmio_flip *mmio_flip =
11179 container_of(work, struct intel_mmio_flip, work);
84c33a64 11180
eed29a5b
DV		 11181 if (mmio_flip->req)
11182 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11183 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11184 false, NULL,
11185 &mmio_flip->i915->rps.mmioflips));
84c33a64 11186
b2cfe0ab
CW		 11187 intel_do_mmio_flip(mmio_flip->crtc);
11188
eed29a5b 11189 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11190 kfree(mmio_flip);
84c33a64
SG		 11191}
11192
11193static int intel_queue_mmio_flip(struct drm_device *dev,
11194 struct drm_crtc *crtc,
11195 struct drm_framebuffer *fb,
11196 struct drm_i915_gem_object *obj,
11197 struct intel_engine_cs *ring,
11198 uint32_t flags)
11199{
b2cfe0ab
CW		 11200 struct intel_mmio_flip *mmio_flip;
11201
11202 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11203 if (mmio_flip == NULL)
11204 return -ENOMEM;
84c33a64 11205
bcafc4e3 11206 mmio_flip->i915 = to_i915(dev);
eed29a5b 11207 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11208 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11209
b2cfe0ab
CW		 11210 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11211 schedule_work(&mmio_flip->work);
84c33a64 11212
84c33a64
SG		 11213 return 0;
11214}
11215
8c9f3aaf
JB		 11216static int intel_default_queue_flip(struct drm_device *dev,
11217 struct drm_crtc *crtc,
11218 struct drm_framebuffer *fb,
ed8d1975 11219 struct drm_i915_gem_object *obj,
6258fbe2 11220 struct drm_i915_gem_request *req,
ed8d1975 11221 uint32_t flags)
8c9f3aaf
JB		 11222{
11223 return -ENODEV;
11224}
11225
d6bbafa1
CW		 11226static bool __intel_pageflip_stall_check(struct drm_device *dev,
11227 struct drm_crtc *crtc)
11228{
11229 struct drm_i915_private *dev_priv = dev->dev_private;
11230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11231 struct intel_unpin_work *work = intel_crtc->unpin_work;
11232 u32 addr;
11233
11234 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11235 return true;
11236
908565c2
CW		 11237 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11238 return false;
11239
d6bbafa1
CW		 11240 if (!work->enable_stall_check)
11241 return false;
11242
11243 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11244 if (work->flip_queued_req &&
11245 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11246 return false;
11247
1e3feefd 11248 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11249 }
11250
1e3feefd 11251 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11252 return false;
11253
11254 /* Potential stall - if we see that the flip has happened,
11255 * assume a missed interrupt. */
11256 if (INTEL_INFO(dev)->gen >= 4)
11257 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11258 else
11259 addr = I915_READ(DSPADDR(intel_crtc->plane));
11260
11261 /* There is a potential issue here with a false positive after a flip
11262 * to the same address. We could address this by checking for a
11263 * non-incrementing frame counter.
11264 */
11265 return addr == work->gtt_offset;
11266}
11267
11268void intel_check_page_flip(struct drm_device *dev, int pipe)
11269{
11270 struct drm_i915_private *dev_priv = dev->dev_private;
11271 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11273 struct intel_unpin_work *work;
f326038a 11274
6c51d46f 11275 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11276
11277 if (crtc == NULL)
11278 return;
11279
f326038a 11280 spin_lock(&dev->event_lock);
6ad790c0
CW		 11281 work = intel_crtc->unpin_work;
11282 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11283 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11284 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11285 page_flip_completed(intel_crtc);
6ad790c0 11286 work = NULL;
d6bbafa1 11287 }
6ad790c0
CW		 11288 if (work != NULL &&
11289 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11290 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11291 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11292}
11293
6b95a207
KH		 11294static int intel_crtc_page_flip(struct drm_crtc *crtc,
11295 struct drm_framebuffer *fb,
ed8d1975
KP		 11296 struct drm_pending_vblank_event *event,
11297 uint32_t page_flip_flags)
6b95a207
KH		 11298{
11299 struct drm_device *dev = crtc->dev;
11300 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11301 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11302 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11304 struct drm_plane *primary = crtc->primary;
a071fa00 11305 enum pipe pipe = intel_crtc->pipe;
6b95a207 11306 struct intel_unpin_work *work;
a4872ba6 11307 struct intel_engine_cs *ring;
cf5d8a46 11308 bool mmio_flip;
91af127f 11309 struct drm_i915_gem_request *request = NULL;
52e68630 11310 int ret;
6b95a207 11311
2ff8fde1
MR		 11312 /*
11313 * drm_mode_page_flip_ioctl() should already catch this, but double
11314 * check to be safe. In the future we may enable pageflipping from
11315 * a disabled primary plane.
11316 */
11317 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11318 return -EBUSY;
11319
e6a595d2 11320 /* Can't change pixel format via MI display flips. */
f4510a27 11321 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11322 return -EINVAL;
11323
11324 /*
11325 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11326 * Note that pitch changes could also affect these register.
11327 */
11328 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11329 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11330 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11331 return -EINVAL;
11332
f900db47
CW		 11333 if (i915_terminally_wedged(&dev_priv->gpu_error))
11334 goto out_hang;
11335
b14c5679 11336 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11337 if (work == NULL)
11338 return -ENOMEM;
11339
6b95a207 11340 work->event = event;
b4a98e57 11341 work->crtc = crtc;
ab8d6675 11342 work->old_fb = old_fb;
6b95a207
KH		 11343 INIT_WORK(&work->work, intel_unpin_work_fn);
11344
87b6b101 11345 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11346 if (ret)
11347 goto free_work;
11348
6b95a207 11349 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11350 spin_lock_irq(&dev->event_lock);
6b95a207 11351 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11352 /* Before declaring the flip queue wedged, check if
11353 * the hardware completed the operation behind our backs.
11354 */
11355 if (__intel_pageflip_stall_check(dev, crtc)) {
11356 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11357 page_flip_completed(intel_crtc);
11358 } else {
11359 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11360 spin_unlock_irq(&dev->event_lock);
468f0b44 11361
d6bbafa1
CW		 11362 drm_crtc_vblank_put(crtc);
11363 kfree(work);
11364 return -EBUSY;
11365 }
6b95a207
KH		 11366 }
11367 intel_crtc->unpin_work = work;
5e2d7afc 11368 spin_unlock_irq(&dev->event_lock);
6b95a207 11369
b4a98e57
CW		 11370 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11371 flush_workqueue(dev_priv->wq);
11372
75dfca80 11373 /* Reference the objects for the scheduled work. */
ab8d6675 11374 drm_framebuffer_reference(work->old_fb);
05394f39 11375 drm_gem_object_reference(&obj->base);
6b95a207 11376
f4510a27 11377 crtc->primary->fb = fb;
afd65eb4 11378 update_state_fb(crtc->primary);
1ed1f968 11379
e1f99ce6 11380 work->pending_flip_obj = obj;
e1f99ce6 11381
89ed88ba
CW		 11382 ret = i915_mutex_lock_interruptible(dev);
11383 if (ret)
11384 goto cleanup;
11385
b4a98e57 11386 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11387 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11388
75f7f3ec 11389 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11390 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11391
4fa62c89
VS		 11392 if (IS_VALLEYVIEW(dev)) {
11393 ring = &dev_priv->ring[BCS];
ab8d6675 11394 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11395 /* vlv: DISPLAY_FLIP fails to change tiling */
11396 ring = NULL;
48bf5b2d 11397 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11398 ring = &dev_priv->ring[BCS];
4fa62c89 11399 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11400 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11401 if (ring == NULL || ring->id != RCS)
11402 ring = &dev_priv->ring[BCS];
11403 } else {
11404 ring = &dev_priv->ring[RCS];
11405 }
11406
cf5d8a46
CW		 11407 mmio_flip = use_mmio_flip(ring, obj);
11408
11409 /* When using CS flips, we want to emit semaphores between rings.
11410 * However, when using mmio flips we will create a task to do the
11411 * synchronisation, so all we want here is to pin the framebuffer
11412 * into the display plane and skip any waits.
11413 */
82bc3b2d 11414 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11415 crtc->primary->state,
91af127f 11416 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11417 if (ret)
11418 goto cleanup_pending;
6b95a207 11419
121920fa
TU		 11420 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11421 + intel_crtc->dspaddr_offset;
4fa62c89 11422
cf5d8a46 11423 if (mmio_flip) {
84c33a64
SG		 11424 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11425 page_flip_flags);
d6bbafa1
CW		 11426 if (ret)
11427 goto cleanup_unpin;
11428
f06cc1b9
JH		 11429 i915_gem_request_assign(&work->flip_queued_req,
11430 obj->last_write_req);
d6bbafa1 11431 } else {
6258fbe2
JH		 11432 if (!request) {
11433 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11434 if (ret)
11435 goto cleanup_unpin;
11436 }
11437
11438 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11439 page_flip_flags);
11440 if (ret)
11441 goto cleanup_unpin;
11442
6258fbe2 11443 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11444 }
11445
91af127f 11446 if (request)
75289874 11447 i915_add_request_no_flush(request);
91af127f 11448
1e3feefd 11449 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11450 work->enable_stall_check = true;
4fa62c89 11451
ab8d6675 11452 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11453 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11454 mutex_unlock(&dev->struct_mutex);
a071fa00 11455
4e1e26f1 11456 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11457 intel_frontbuffer_flip_prepare(dev,
11458 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11459
e5510fac
JB		 11460 trace_i915_flip_request(intel_crtc->plane, obj);
11461
6b95a207 11462 return 0;
96b099fd 11463
4fa62c89 11464cleanup_unpin:
82bc3b2d 11465 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11466cleanup_pending:
91af127f
JH		 11467 if (request)
11468 i915_gem_request_cancel(request);
b4a98e57 11469 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11470 mutex_unlock(&dev->struct_mutex);
11471cleanup:
f4510a27 11472 crtc->primary->fb = old_fb;
afd65eb4 11473 update_state_fb(crtc->primary);
89ed88ba
CW		 11474
11475 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11476 drm_framebuffer_unreference(work->old_fb);
96b099fd 11477
5e2d7afc 11478 spin_lock_irq(&dev->event_lock);
96b099fd 11479 intel_crtc->unpin_work = NULL;
5e2d7afc 11480 spin_unlock_irq(&dev->event_lock);
96b099fd 11481
87b6b101 11482 drm_crtc_vblank_put(crtc);
7317c75e 11483free_work:
96b099fd
CW		 11484 kfree(work);
11485
f900db47 11486 if (ret == -EIO) {
02e0efb5
ML		 11487 struct drm_atomic_state *state;
11488 struct drm_plane_state *plane_state;
11489
f900db47 11490out_hang:
02e0efb5
ML		 11491 state = drm_atomic_state_alloc(dev);
11492 if (!state)
11493 return -ENOMEM;
11494 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11495
11496retry:
11497 plane_state = drm_atomic_get_plane_state(state, primary);
11498 ret = PTR_ERR_OR_ZERO(plane_state);
11499 if (!ret) {
11500 drm_atomic_set_fb_for_plane(plane_state, fb);
11501
11502 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11503 if (!ret)
11504 ret = drm_atomic_commit(state);
11505 }
11506
11507 if (ret == -EDEADLK) {
11508 drm_modeset_backoff(state->acquire_ctx);
11509 drm_atomic_state_clear(state);
11510 goto retry;
11511 }
11512
11513 if (ret)
11514 drm_atomic_state_free(state);
11515
f0d3dad3 11516 if (ret == 0 && event) {
5e2d7afc 11517 spin_lock_irq(&dev->event_lock);
a071fa00 11518 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11519 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11520 }
f900db47 11521 }
96b099fd 11522 return ret;
6b95a207
KH		 11523}
11524
da20eabd
ML		 11525
11526/**
11527 * intel_wm_need_update - Check whether watermarks need updating
11528 * @plane: drm plane
11529 * @state: new plane state
11530 *
11531 * Check current plane state versus the new one to determine whether
11532 * watermarks need to be recalculated.
11533 *
11534 * Returns true or false.
11535 */
11536static bool intel_wm_need_update(struct drm_plane *plane,
11537 struct drm_plane_state *state)
11538{
11539 /* Update watermarks on tiling changes. */
11540 if (!plane->state->fb || !state->fb ||
11541 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11542 plane->state->rotation != state->rotation)
11543 return true;
11544
11545 if (plane->state->crtc_w != state->crtc_w)
11546 return true;
11547
11548 return false;
11549}
11550
11551int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11552 struct drm_plane_state *plane_state)
11553{
11554 struct drm_crtc *crtc = crtc_state->crtc;
11555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11556 struct drm_plane *plane = plane_state->plane;
11557 struct drm_device *dev = crtc->dev;
11558 struct drm_i915_private *dev_priv = dev->dev_private;
11559 struct intel_plane_state *old_plane_state =
11560 to_intel_plane_state(plane->state);
11561 int idx = intel_crtc->base.base.id, ret;
11562 int i = drm_plane_index(plane);
11563 bool mode_changed = needs_modeset(crtc_state);
11564 bool was_crtc_enabled = crtc->state->active;
11565 bool is_crtc_enabled = crtc_state->active;
11566
11567 bool turn_off, turn_on, visible, was_visible;
11568 struct drm_framebuffer *fb = plane_state->fb;
11569
11570 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11571 plane->type != DRM_PLANE_TYPE_CURSOR) {
11572 ret = skl_update_scaler_plane(
11573 to_intel_crtc_state(crtc_state),
11574 to_intel_plane_state(plane_state));
11575 if (ret)
11576 return ret;
11577 }
11578
11579 /*
11580 * Disabling a plane is always okay; we just need to update
11581 * fb tracking in a special way since cleanup_fb() won't
11582 * get called by the plane helpers.
11583 */
11584 if (old_plane_state->base.fb && !fb)
11585 intel_crtc->atomic.disabled_planes |= 1 << i;
11586
da20eabd
ML		 11587 was_visible = old_plane_state->visible;
11588 visible = to_intel_plane_state(plane_state)->visible;
11589
11590 if (!was_crtc_enabled && WARN_ON(was_visible))
11591 was_visible = false;
11592
11593 if (!is_crtc_enabled && WARN_ON(visible))
11594 visible = false;
11595
11596 if (!was_visible && !visible)
11597 return 0;
11598
11599 turn_off = was_visible && (!visible || mode_changed);
11600 turn_on = visible && (!was_visible || mode_changed);
11601
11602 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11603 plane->base.id, fb ? fb->base.id : -1);
11604
11605 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11606 plane->base.id, was_visible, visible,
11607 turn_off, turn_on, mode_changed);
11608
852eb00d 11609 if (turn_on) {
f015c551 11610 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11611 /* must disable cxsr around plane enable/disable */
11612 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11613 intel_crtc->atomic.disable_cxsr = true;
11614 /* to potentially re-enable cxsr */
11615 intel_crtc->atomic.wait_vblank = true;
11616 intel_crtc->atomic.update_wm_post = true;
11617 }
11618 } else if (turn_off) {
f015c551 11619 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11620 /* must disable cxsr around plane enable/disable */
11621 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11622 if (is_crtc_enabled)
11623 intel_crtc->atomic.wait_vblank = true;
11624 intel_crtc->atomic.disable_cxsr = true;
11625 }
11626 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11627 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11628 }
da20eabd 11629
a9ff8714
VS		 11630 if (visible)
11631 intel_crtc->atomic.fb_bits |=
11632 to_intel_plane(plane)->frontbuffer_bit;
11633
da20eabd
ML		 11634 switch (plane->type) {
11635 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11636 intel_crtc->atomic.wait_for_flips = true;
11637 intel_crtc->atomic.pre_disable_primary = turn_off;
11638 intel_crtc->atomic.post_enable_primary = turn_on;
11639
066cf55b
RV		 11640 if (turn_off) {
11641 /*
11642 * FIXME: Actually if we will still have any other
11643 * plane enabled on the pipe we could let IPS enabled
11644 * still, but for now lets consider that when we make
11645 * primary invisible by setting DSPCNTR to 0 on
11646 * update_primary_plane function IPS needs to be
11647 * disable.
11648 */
11649 intel_crtc->atomic.disable_ips = true;
11650
da20eabd 11651 intel_crtc->atomic.disable_fbc = true;
066cf55b 11652 }
da20eabd
ML		 11653
11654 /*
11655 * FBC does not work on some platforms for rotated
11656 * planes, so disable it when rotation is not 0 and
11657 * update it when rotation is set back to 0.
11658 *
11659 * FIXME: This is redundant with the fbc update done in
11660 * the primary plane enable function except that that
11661 * one is done too late. We eventually need to unify
11662 * this.
11663 */
11664
11665 if (visible &&
11666 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11667 dev_priv->fbc.crtc == intel_crtc &&
11668 plane_state->rotation != BIT(DRM_ROTATE_0))
11669 intel_crtc->atomic.disable_fbc = true;
11670
11671 /*
11672 * BDW signals flip done immediately if the plane
11673 * is disabled, even if the plane enable is already
11674 * armed to occur at the next vblank :(
11675 */
11676 if (turn_on && IS_BROADWELL(dev))
11677 intel_crtc->atomic.wait_vblank = true;
11678
11679 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11680 break;
11681 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11682 break;
11683 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11684 if (turn_off && !mode_changed) {
da20eabd
ML		 11685 intel_crtc->atomic.wait_vblank = true;
11686 intel_crtc->atomic.update_sprite_watermarks |=
11687 1 << i;
11688 }
da20eabd
ML		 11689 }
11690 return 0;
11691}
11692
6d3a1ce7
ML		 11693static bool encoders_cloneable(const struct intel_encoder *a,
11694 const struct intel_encoder *b)
11695{
11696 /* masks could be asymmetric, so check both ways */
11697 return a == b || (a->cloneable & (1 << b->type) &&
11698 b->cloneable & (1 << a->type));
11699}
11700
11701static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11702 struct intel_crtc *crtc,
11703 struct intel_encoder *encoder)
11704{
11705 struct intel_encoder *source_encoder;
11706 struct drm_connector *connector;
11707 struct drm_connector_state *connector_state;
11708 int i;
11709
11710 for_each_connector_in_state(state, connector, connector_state, i) {
11711 if (connector_state->crtc != &crtc->base)
11712 continue;
11713
11714 source_encoder =
11715 to_intel_encoder(connector_state->best_encoder);
11716 if (!encoders_cloneable(encoder, source_encoder))
11717 return false;
11718 }
11719
11720 return true;
11721}
11722
11723static bool check_encoder_cloning(struct drm_atomic_state *state,
11724 struct intel_crtc *crtc)
11725{
11726 struct intel_encoder *encoder;
11727 struct drm_connector *connector;
11728 struct drm_connector_state *connector_state;
11729 int i;
11730
11731 for_each_connector_in_state(state, connector, connector_state, i) {
11732 if (connector_state->crtc != &crtc->base)
11733 continue;
11734
11735 encoder = to_intel_encoder(connector_state->best_encoder);
11736 if (!check_single_encoder_cloning(state, crtc, encoder))
11737 return false;
11738 }
11739
11740 return true;
11741}
11742
11743static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11744 struct drm_crtc_state *crtc_state)
11745{
cf5a15be 11746 struct drm_device *dev = crtc->dev;
ad421372 11747 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11749 struct intel_crtc_state *pipe_config =
11750 to_intel_crtc_state(crtc_state);
6d3a1ce7 11751 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11752 int ret;
6d3a1ce7
ML		 11753 bool mode_changed = needs_modeset(crtc_state);
11754
11755 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11756 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11757 return -EINVAL;
11758 }
11759
852eb00d
VS		 11760 if (mode_changed && !crtc_state->active)
11761 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11762
ad421372
ML		 11763 if (mode_changed && crtc_state->enable &&
11764 dev_priv->display.crtc_compute_clock &&
11765 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11766 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11767 pipe_config);
11768 if (ret)
11769 return ret;
11770 }
11771
e435d6e5
ML		 11772 ret = 0;
11773 if (INTEL_INFO(dev)->gen >= 9) {
11774 if (mode_changed)
11775 ret = skl_update_scaler_crtc(pipe_config);
11776
11777 if (!ret)
11778 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11779 pipe_config);
11780 }
11781
11782 return ret;
6d3a1ce7
ML		 11783}
11784
65b38e0d 11785static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11786 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11787 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11788 .atomic_begin = intel_begin_crtc_commit,
11789 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11790 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11791};
11792
d29b2f9d
ACO		 11793static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11794{
11795 struct intel_connector *connector;
11796
11797 for_each_intel_connector(dev, connector) {
11798 if (connector->base.encoder) {
11799 connector->base.state->best_encoder =
11800 connector->base.encoder;
11801 connector->base.state->crtc =
11802 connector->base.encoder->crtc;
11803 } else {
11804 connector->base.state->best_encoder = NULL;
11805 connector->base.state->crtc = NULL;
11806 }
11807 }
11808}
11809
050f7aeb 11810static void
eba905b2 11811connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11812 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11813{
11814 int bpp = pipe_config->pipe_bpp;
11815
11816 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11817 connector->base.base.id,
c23cc417 11818 connector->base.name);
050f7aeb
DV		 11819
11820 /* Don't use an invalid EDID bpc value */
11821 if (connector->base.display_info.bpc &&
11822 connector->base.display_info.bpc * 3 < bpp) {
11823 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11824 bpp, connector->base.display_info.bpc*3);
11825 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11826 }
11827
11828 /* Clamp bpp to 8 on screens without EDID 1.4 */
11829 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11830 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11831 bpp);
11832 pipe_config->pipe_bpp = 24;
11833 }
11834}
11835
4e53c2e0 11836static int
050f7aeb 11837compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11838 struct intel_crtc_state *pipe_config)
4e53c2e0 11839{
050f7aeb 11840 struct drm_device *dev = crtc->base.dev;
1486017f 11841 struct drm_atomic_state *state;
da3ced29
ACO		 11842 struct drm_connector *connector;
11843 struct drm_connector_state *connector_state;
1486017f 11844 int bpp, i;
4e53c2e0 11845
d328c9d7 11846 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11847 bpp = 10*3;
d328c9d7
DV		 11848 else if (INTEL_INFO(dev)->gen >= 5)
11849 bpp = 12*3;
11850 else
11851 bpp = 8*3;
11852
4e53c2e0 11853
4e53c2e0
DV		 11854 pipe_config->pipe_bpp = bpp;
11855
1486017f
ACO		 11856 state = pipe_config->base.state;
11857
4e53c2e0 11858 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11859 for_each_connector_in_state(state, connector, connector_state, i) {
11860 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11861 continue;
11862
da3ced29
ACO		 11863 connected_sink_compute_bpp(to_intel_connector(connector),
11864 pipe_config);
4e53c2e0
DV		 11865 }
11866
11867 return bpp;
11868}
11869
644db711
DV		 11870static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11871{
11872 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11873 "type: 0x%x flags: 0x%x\n",
1342830c 11874 mode->crtc_clock,
644db711
DV		 11875 mode->crtc_hdisplay, mode->crtc_hsync_start,
11876 mode->crtc_hsync_end, mode->crtc_htotal,
11877 mode->crtc_vdisplay, mode->crtc_vsync_start,
11878 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11879}
11880
c0b03411 11881static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11882 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11883 const char *context)
11884{
6a60cd87
CK		 11885 struct drm_device *dev = crtc->base.dev;
11886 struct drm_plane *plane;
11887 struct intel_plane *intel_plane;
11888 struct intel_plane_state *state;
11889 struct drm_framebuffer *fb;
11890
11891 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11892 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11893
11894 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11895 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11896 pipe_config->pipe_bpp, pipe_config->dither);
11897 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11898 pipe_config->has_pch_encoder,
11899 pipe_config->fdi_lanes,
11900 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11901 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11902 pipe_config->fdi_m_n.tu);
90a6b7b0 11903 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11904 pipe_config->has_dp_encoder,
90a6b7b0 11905 pipe_config->lane_count,
eb14cb74
VS		 11906 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11907 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11908 pipe_config->dp_m_n.tu);
b95af8be 11909
90a6b7b0 11910 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11911 pipe_config->has_dp_encoder,
90a6b7b0 11912 pipe_config->lane_count,
b95af8be
VK		 11913 pipe_config->dp_m2_n2.gmch_m,
11914 pipe_config->dp_m2_n2.gmch_n,
11915 pipe_config->dp_m2_n2.link_m,
11916 pipe_config->dp_m2_n2.link_n,
11917 pipe_config->dp_m2_n2.tu);
11918
55072d19
DV		 11919 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11920 pipe_config->has_audio,
11921 pipe_config->has_infoframe);
11922
c0b03411 11923 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11924 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11925 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11926 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11927 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11928 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11929 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11930 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11931 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11932 crtc->num_scalers,
11933 pipe_config->scaler_state.scaler_users,
11934 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11935 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11936 pipe_config->gmch_pfit.control,
11937 pipe_config->gmch_pfit.pgm_ratios,
11938 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11939 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11940 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11941 pipe_config->pch_pfit.size,
11942 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11943 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11944 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11945
415ff0f6 11946 if (IS_BROXTON(dev)) {
05712c15 11947 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11948 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11949 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11950 pipe_config->ddi_pll_sel,
11951 pipe_config->dpll_hw_state.ebb0,
05712c15 11952 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11953 pipe_config->dpll_hw_state.pll0,
11954 pipe_config->dpll_hw_state.pll1,
11955 pipe_config->dpll_hw_state.pll2,
11956 pipe_config->dpll_hw_state.pll3,
11957 pipe_config->dpll_hw_state.pll6,
11958 pipe_config->dpll_hw_state.pll8,
05712c15 11959 pipe_config->dpll_hw_state.pll9,
c8453338 11960 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11961 pipe_config->dpll_hw_state.pcsdw12);
11962 } else if (IS_SKYLAKE(dev)) {
11963 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11964 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11965 pipe_config->ddi_pll_sel,
11966 pipe_config->dpll_hw_state.ctrl1,
11967 pipe_config->dpll_hw_state.cfgcr1,
11968 pipe_config->dpll_hw_state.cfgcr2);
11969 } else if (HAS_DDI(dev)) {
11970 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11971 pipe_config->ddi_pll_sel,
11972 pipe_config->dpll_hw_state.wrpll);
11973 } else {
11974 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11975 "fp0: 0x%x, fp1: 0x%x\n",
11976 pipe_config->dpll_hw_state.dpll,
11977 pipe_config->dpll_hw_state.dpll_md,
11978 pipe_config->dpll_hw_state.fp0,
11979 pipe_config->dpll_hw_state.fp1);
11980 }
11981
6a60cd87
CK		 11982 DRM_DEBUG_KMS("planes on this crtc\n");
11983 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11984 intel_plane = to_intel_plane(plane);
11985 if (intel_plane->pipe != crtc->pipe)
11986 continue;
11987
11988 state = to_intel_plane_state(plane->state);
11989 fb = state->base.fb;
11990 if (!fb) {
11991 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11992 "disabled, scaler_id = %d\n",
11993 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11994 plane->base.id, intel_plane->pipe,
11995 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11996 drm_plane_index(plane), state->scaler_id);
11997 continue;
11998 }
11999
12000 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12001 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12002 plane->base.id, intel_plane->pipe,
12003 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12004 drm_plane_index(plane));
12005 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12006 fb->base.id, fb->width, fb->height, fb->pixel_format);
12007 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12008 state->scaler_id,
12009 state->src.x1 >> 16, state->src.y1 >> 16,
12010 drm_rect_width(&state->src) >> 16,
12011 drm_rect_height(&state->src) >> 16,
12012 state->dst.x1, state->dst.y1,
12013 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12014 }
c0b03411
DV		 12015}
12016
5448a00d 12017static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12018{
5448a00d
ACO		 12019 struct drm_device *dev = state->dev;
12020 struct intel_encoder *encoder;
da3ced29 12021 struct drm_connector *connector;
5448a00d 12022 struct drm_connector_state *connector_state;
00f0b378 12023 unsigned int used_ports = 0;
5448a00d 12024 int i;
00f0b378
VS		 12025
12026 /*
12027 * Walk the connector list instead of the encoder
12028 * list to detect the problem on ddi platforms
12029 * where there's just one encoder per digital port.
12030 */
da3ced29 12031 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12032 if (!connector_state->best_encoder)
00f0b378
VS		 12033 continue;
12034
5448a00d
ACO		 12035 encoder = to_intel_encoder(connector_state->best_encoder);
12036
12037 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12038
12039 switch (encoder->type) {
12040 unsigned int port_mask;
12041 case INTEL_OUTPUT_UNKNOWN:
12042 if (WARN_ON(!HAS_DDI(dev)))
12043 break;
12044 case INTEL_OUTPUT_DISPLAYPORT:
12045 case INTEL_OUTPUT_HDMI:
12046 case INTEL_OUTPUT_EDP:
12047 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12048
12049 /* the same port mustn't appear more than once */
12050 if (used_ports & port_mask)
12051 return false;
12052
12053 used_ports |= port_mask;
12054 default:
12055 break;
12056 }
12057 }
12058
12059 return true;
12060}
12061
83a57153
ACO		 12062static void
12063clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12064{
12065 struct drm_crtc_state tmp_state;
663a3640 12066 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12067 struct intel_dpll_hw_state dpll_hw_state;
12068 enum intel_dpll_id shared_dpll;
8504c74c 12069 uint32_t ddi_pll_sel;
c4e2d043 12070 bool force_thru;
83a57153 12071
7546a384
ACO		 12072 /* FIXME: before the switch to atomic started, a new pipe_config was
12073 * kzalloc'd. Code that depends on any field being zero should be
12074 * fixed, so that the crtc_state can be safely duplicated. For now,
12075 * only fields that are know to not cause problems are preserved. */
12076
83a57153 12077 tmp_state = crtc_state->base;
663a3640 12078 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12079 shared_dpll = crtc_state->shared_dpll;
12080 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12081 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12082 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12083
83a57153 12084 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12085
83a57153 12086 crtc_state->base = tmp_state;
663a3640 12087 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12088 crtc_state->shared_dpll = shared_dpll;
12089 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12090 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12091 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12092}
12093
548ee15b 12094static int
b8cecdf5 12095intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12096 struct intel_crtc_state *pipe_config)
ee7b9f93 12097{
b359283a 12098 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12099 struct intel_encoder *encoder;
da3ced29 12100 struct drm_connector *connector;
0b901879 12101 struct drm_connector_state *connector_state;
d328c9d7 12102 int base_bpp, ret = -EINVAL;
0b901879 12103 int i;
e29c22c0 12104 bool retry = true;
ee7b9f93 12105
83a57153 12106 clear_intel_crtc_state(pipe_config);
7758a113 12107
e143a21c
DV		 12108 pipe_config->cpu_transcoder =
12109 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12110
2960bc9c
ID		 12111 /*
12112 * Sanitize sync polarity flags based on requested ones. If neither
12113 * positive or negative polarity is requested, treat this as meaning
12114 * negative polarity.
12115 */
2d112de7 12116 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12117 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12118 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12119
2d112de7 12120 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12121 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12122 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12123
050f7aeb
DV		 12124 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12125 * plane pixel format and any sink constraints into account. Returns the
12126 * source plane bpp so that dithering can be selected on mismatches
12127 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12128 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12129 pipe_config);
12130 if (base_bpp < 0)
4e53c2e0
DV		 12131 goto fail;
12132
e41a56be
VS		 12133 /*
12134 * Determine the real pipe dimensions. Note that stereo modes can
12135 * increase the actual pipe size due to the frame doubling and
12136 * insertion of additional space for blanks between the frame. This
12137 * is stored in the crtc timings. We use the requested mode to do this
12138 * computation to clearly distinguish it from the adjusted mode, which
12139 * can be changed by the connectors in the below retry loop.
12140 */
2d112de7 12141 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12142 &pipe_config->pipe_src_w,
12143 &pipe_config->pipe_src_h);
e41a56be 12144
e29c22c0 12145encoder_retry:
ef1b460d 12146 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12147 pipe_config->port_clock = 0;
ef1b460d 12148 pipe_config->pixel_multiplier = 1;
ff9a6750 12149
135c81b8 12150 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12151 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12152 CRTC_STEREO_DOUBLE);
135c81b8 12153
7758a113
DV		 12154 /* Pass our mode to the connectors and the CRTC to give them a chance to
12155 * adjust it according to limitations or connector properties, and also
12156 * a chance to reject the mode entirely.
47f1c6c9 12157 */
da3ced29 12158 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12159 if (connector_state->crtc != crtc)
7758a113 12160 continue;
7ae89233 12161
0b901879
ACO		 12162 encoder = to_intel_encoder(connector_state->best_encoder);
12163
efea6e8e
DV		 12164 if (!(encoder->compute_config(encoder, pipe_config))) {
12165 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12166 goto fail;
12167 }
ee7b9f93 12168 }
47f1c6c9 12169
ff9a6750
DV		 12170 /* Set default port clock if not overwritten by the encoder. Needs to be
12171 * done afterwards in case the encoder adjusts the mode. */
12172 if (!pipe_config->port_clock)
2d112de7 12173 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12174 * pipe_config->pixel_multiplier;
ff9a6750 12175
a43f6e0f 12176 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12177 if (ret < 0) {
7758a113
DV		 12178 DRM_DEBUG_KMS("CRTC fixup failed\n");
12179 goto fail;
ee7b9f93 12180 }
e29c22c0
DV		 12181
12182 if (ret == RETRY) {
12183 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12184 ret = -EINVAL;
12185 goto fail;
12186 }
12187
12188 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12189 retry = false;
12190 goto encoder_retry;
12191 }
12192
e8fa4270
DV		 12193 /* Dithering seems to not pass-through bits correctly when it should, so
12194 * only enable it on 6bpc panels. */
12195 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
4e53c2e0 12196 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12197 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12198
7758a113 12199fail:
548ee15b 12200 return ret;
ee7b9f93 12201}
47f1c6c9 12202
ea9d758d 12203static void
4740b0f2 12204intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12205{
0a9ab303
ACO		 12206 struct drm_crtc *crtc;
12207 struct drm_crtc_state *crtc_state;
8a75d157 12208 int i;
ea9d758d 12209
7668851f 12210 /* Double check state. */
8a75d157 12211 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12212 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12213
12214 /* Update hwmode for vblank functions */
12215 if (crtc->state->active)
12216 crtc->hwmode = crtc->state->adjusted_mode;
12217 else
12218 crtc->hwmode.crtc_clock = 0;
ea9d758d 12219 }
ea9d758d
DV		 12220}
12221
3bd26263 12222static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12223{
3bd26263 12224 int diff;
f1f644dc
JB		 12225
12226 if (clock1 == clock2)
12227 return true;
12228
12229 if (!clock1 || !clock2)
12230 return false;
12231
12232 diff = abs(clock1 - clock2);
12233
12234 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12235 return true;
12236
12237 return false;
12238}
12239
25c5b266
DV		 12240#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12241 list_for_each_entry((intel_crtc), \
12242 &(dev)->mode_config.crtc_list, \
12243 base.head) \
0973f18f 12244 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12245
cfb23ed6
ML		 12246
12247static bool
12248intel_compare_m_n(unsigned int m, unsigned int n,
12249 unsigned int m2, unsigned int n2,
12250 bool exact)
12251{
12252 if (m == m2 && n == n2)
12253 return true;
12254
12255 if (exact || !m || !n || !m2 || !n2)
12256 return false;
12257
12258 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12259
12260 if (m > m2) {
12261 while (m > m2) {
12262 m2 <<= 1;
12263 n2 <<= 1;
12264 }
12265 } else if (m < m2) {
12266 while (m < m2) {
12267 m <<= 1;
12268 n <<= 1;
12269 }
12270 }
12271
12272 return m == m2 && n == n2;
12273}
12274
12275static bool
12276intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12277 struct intel_link_m_n *m2_n2,
12278 bool adjust)
12279{
12280 if (m_n->tu == m2_n2->tu &&
12281 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12282 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12283 intel_compare_m_n(m_n->link_m, m_n->link_n,
12284 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12285 if (adjust)
12286 *m2_n2 = *m_n;
12287
12288 return true;
12289 }
12290
12291 return false;
12292}
12293
0e8ffe1b 12294static bool
2fa2fe9a 12295intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12296 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12297 struct intel_crtc_state *pipe_config,
12298 bool adjust)
0e8ffe1b 12299{
cfb23ed6
ML		 12300 bool ret = true;
12301
12302#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12303 do { \
12304 if (!adjust) \
12305 DRM_ERROR(fmt, ##__VA_ARGS__); \
12306 else \
12307 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12308 } while (0)
12309
66e985c0
DV		 12310#define PIPE_CONF_CHECK_X(name) \
12311 if (current_config->name != pipe_config->name) { \
cfb23ed6 12312 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12313 "(expected 0x%08x, found 0x%08x)\n", \
12314 current_config->name, \
12315 pipe_config->name); \
cfb23ed6 12316 ret = false; \
66e985c0
DV		 12317 }
12318
08a24034
DV		 12319#define PIPE_CONF_CHECK_I(name) \
12320 if (current_config->name != pipe_config->name) { \
cfb23ed6 12321 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12322 "(expected %i, found %i)\n", \
12323 current_config->name, \
12324 pipe_config->name); \
cfb23ed6
ML		 12325 ret = false; \
12326 }
12327
12328#define PIPE_CONF_CHECK_M_N(name) \
12329 if (!intel_compare_link_m_n(&current_config->name, \
12330 &pipe_config->name,\
12331 adjust)) { \
12332 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12333 "(expected tu %i gmch %i/%i link %i/%i, " \
12334 "found tu %i, gmch %i/%i link %i/%i)\n", \
12335 current_config->name.tu, \
12336 current_config->name.gmch_m, \
12337 current_config->name.gmch_n, \
12338 current_config->name.link_m, \
12339 current_config->name.link_n, \
12340 pipe_config->name.tu, \
12341 pipe_config->name.gmch_m, \
12342 pipe_config->name.gmch_n, \
12343 pipe_config->name.link_m, \
12344 pipe_config->name.link_n); \
12345 ret = false; \
12346 }
12347
12348#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12349 if (!intel_compare_link_m_n(&current_config->name, \
12350 &pipe_config->name, adjust) && \
12351 !intel_compare_link_m_n(&current_config->alt_name, \
12352 &pipe_config->name, adjust)) { \
12353 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12354 "(expected tu %i gmch %i/%i link %i/%i, " \
12355 "or tu %i gmch %i/%i link %i/%i, " \
12356 "found tu %i, gmch %i/%i link %i/%i)\n", \
12357 current_config->name.tu, \
12358 current_config->name.gmch_m, \
12359 current_config->name.gmch_n, \
12360 current_config->name.link_m, \
12361 current_config->name.link_n, \
12362 current_config->alt_name.tu, \
12363 current_config->alt_name.gmch_m, \
12364 current_config->alt_name.gmch_n, \
12365 current_config->alt_name.link_m, \
12366 current_config->alt_name.link_n, \
12367 pipe_config->name.tu, \
12368 pipe_config->name.gmch_m, \
12369 pipe_config->name.gmch_n, \
12370 pipe_config->name.link_m, \
12371 pipe_config->name.link_n); \
12372 ret = false; \
88adfff1
DV		 12373 }
12374
b95af8be
VK		 12375/* This is required for BDW+ where there is only one set of registers for
12376 * switching between high and low RR.
12377 * This macro can be used whenever a comparison has to be made between one
12378 * hw state and multiple sw state variables.
12379 */
12380#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12381 if ((current_config->name != pipe_config->name) && \
12382 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12383 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12384 "(expected %i or %i, found %i)\n", \
12385 current_config->name, \
12386 current_config->alt_name, \
12387 pipe_config->name); \
cfb23ed6 12388 ret = false; \
b95af8be
VK		 12389 }
12390
1bd1bd80
DV		 12391#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12392 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12393 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12394 "(expected %i, found %i)\n", \
12395 current_config->name & (mask), \
12396 pipe_config->name & (mask)); \
cfb23ed6 12397 ret = false; \
1bd1bd80
DV		 12398 }
12399
5e550656
VS		 12400#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12401 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12402 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12403 "(expected %i, found %i)\n", \
12404 current_config->name, \
12405 pipe_config->name); \
cfb23ed6 12406 ret = false; \
5e550656
VS		 12407 }
12408
bb760063
DV		 12409#define PIPE_CONF_QUIRK(quirk) \
12410 ((current_config->quirks | pipe_config->quirks) & (quirk))
12411
eccb140b
DV		 12412 PIPE_CONF_CHECK_I(cpu_transcoder);
12413
08a24034
DV		 12414 PIPE_CONF_CHECK_I(has_pch_encoder);
12415 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12416 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12417
eb14cb74 12418 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12419 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12420
12421 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12422 PIPE_CONF_CHECK_M_N(dp_m_n);
12423
12424 PIPE_CONF_CHECK_I(has_drrs);
12425 if (current_config->has_drrs)
12426 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12427 } else
12428 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12429
2d112de7
ACO		 12430 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12431 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12432 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12433 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12434 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12435 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12436
2d112de7
ACO		 12437 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12438 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12439 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12440 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12441 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12442 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12443
c93f54cf 12444 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12445 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12446 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12447 IS_VALLEYVIEW(dev))
12448 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12449 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12450
9ed109a7
DV		 12451 PIPE_CONF_CHECK_I(has_audio);
12452
2d112de7 12453 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12454 DRM_MODE_FLAG_INTERLACE);
12455
bb760063 12456 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12457 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12458 DRM_MODE_FLAG_PHSYNC);
2d112de7 12459 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12460 DRM_MODE_FLAG_NHSYNC);
2d112de7 12461 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12462 DRM_MODE_FLAG_PVSYNC);
2d112de7 12463 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12464 DRM_MODE_FLAG_NVSYNC);
12465 }
045ac3b5 12466
37327abd
VS		 12467 PIPE_CONF_CHECK_I(pipe_src_w);
12468 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12469
e2ff2d4a
DV		 12470 PIPE_CONF_CHECK_I(gmch_pfit.control);
12471 /* pfit ratios are autocomputed by the hw on gen4+ */
12472 if (INTEL_INFO(dev)->gen < 4)
12473 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12474 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9953599b 12475
fd4daa9c
CW		 12476 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12477 if (current_config->pch_pfit.enabled) {
12478 PIPE_CONF_CHECK_I(pch_pfit.pos);
12479 PIPE_CONF_CHECK_I(pch_pfit.size);
12480 }
2fa2fe9a 12481
a1b2278e
CK		 12482 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12483
e59150dc
JB		 12484 /* BDW+ don't expose a synchronous way to read the state */
12485 if (IS_HASWELL(dev))
12486 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12487
282740f7
VS		 12488 PIPE_CONF_CHECK_I(double_wide);
12489
26804afd
DV		 12490 PIPE_CONF_CHECK_X(ddi_pll_sel);
12491
c0d43d62 12492 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12493 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12494 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12495 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12496 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12497 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12498 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12499 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12500 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12501
42571aef
VS		 12502 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12503 PIPE_CONF_CHECK_I(pipe_bpp);
12504
2d112de7 12505 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12506 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12507
66e985c0 12508#undef PIPE_CONF_CHECK_X
08a24034 12509#undef PIPE_CONF_CHECK_I
b95af8be 12510#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12511#undef PIPE_CONF_CHECK_FLAGS
5e550656 12512#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12513#undef PIPE_CONF_QUIRK
cfb23ed6 12514#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12515
cfb23ed6 12516 return ret;
0e8ffe1b
DV		 12517}
12518
08db6652
DL		 12519static void check_wm_state(struct drm_device *dev)
12520{
12521 struct drm_i915_private *dev_priv = dev->dev_private;
12522 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12523 struct intel_crtc *intel_crtc;
12524 int plane;
12525
12526 if (INTEL_INFO(dev)->gen < 9)
12527 return;
12528
12529 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12530 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12531
12532 for_each_intel_crtc(dev, intel_crtc) {
12533 struct skl_ddb_entry *hw_entry, *sw_entry;
12534 const enum pipe pipe = intel_crtc->pipe;
12535
12536 if (!intel_crtc->active)
12537 continue;
12538
12539 /* planes */
dd740780 12540 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12541 hw_entry = &hw_ddb.plane[pipe][plane];
12542 sw_entry = &sw_ddb->plane[pipe][plane];
12543
12544 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12545 continue;
12546
12547 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12548 "(expected (%u,%u), found (%u,%u))\n",
12549 pipe_name(pipe), plane + 1,
12550 sw_entry->start, sw_entry->end,
12551 hw_entry->start, hw_entry->end);
12552 }
12553
12554 /* cursor */
12555 hw_entry = &hw_ddb.cursor[pipe];
12556 sw_entry = &sw_ddb->cursor[pipe];
12557
12558 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12559 continue;
12560
12561 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12562 "(expected (%u,%u), found (%u,%u))\n",
12563 pipe_name(pipe),
12564 sw_entry->start, sw_entry->end,
12565 hw_entry->start, hw_entry->end);
12566 }
12567}
12568
91d1b4bd 12569static void
35dd3c64
ML		 12570check_connector_state(struct drm_device *dev,
12571 struct drm_atomic_state *old_state)
8af6cf88 12572{
35dd3c64
ML		 12573 struct drm_connector_state *old_conn_state;
12574 struct drm_connector *connector;
12575 int i;
8af6cf88 12576
35dd3c64
ML		 12577 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12578 struct drm_encoder *encoder = connector->encoder;
12579 struct drm_connector_state *state = connector->state;
ad3c558f 12580
8af6cf88
DV		 12581 /* This also checks the encoder/connector hw state with the
12582 * ->get_hw_state callbacks. */
35dd3c64 12583 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12584
ad3c558f 12585 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12586 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12587 }
91d1b4bd
DV		 12588}
12589
12590static void
12591check_encoder_state(struct drm_device *dev)
12592{
12593 struct intel_encoder *encoder;
12594 struct intel_connector *connector;
8af6cf88 12595
b2784e15 12596 for_each_intel_encoder(dev, encoder) {
8af6cf88 12597 bool enabled = false;
4d20cd86 12598 enum pipe pipe;
8af6cf88
DV		 12599
12600 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12601 encoder->base.base.id,
8e329a03 12602 encoder->base.name);
8af6cf88 12603
3a3371ff 12604 for_each_intel_connector(dev, connector) {
4d20cd86 12605 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12606 continue;
12607 enabled = true;
ad3c558f
ML		 12608
12609 I915_STATE_WARN(connector->base.state->crtc !=
12610 encoder->base.crtc,
12611 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12612 }
0e32b39c 12613
e2c719b7 12614 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12615 "encoder's enabled state mismatch "
12616 "(expected %i, found %i)\n",
12617 !!encoder->base.crtc, enabled);
7c60d198
ML		 12618
12619 if (!encoder->base.crtc) {
4d20cd86 12620 bool active;
7c60d198 12621
4d20cd86
ML		 12622 active = encoder->get_hw_state(encoder, &pipe);
12623 I915_STATE_WARN(active,
12624 "encoder detached but still enabled on pipe %c.\n",
12625 pipe_name(pipe));
7c60d198 12626 }
8af6cf88 12627 }
91d1b4bd
DV		 12628}
12629
12630static void
4d20cd86 12631check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12632{
fbee40df 12633 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12634 struct intel_encoder *encoder;
4d20cd86
ML		 12635 struct drm_crtc_state *old_crtc_state;
12636 struct drm_crtc *crtc;
12637 int i;
8af6cf88 12638
4d20cd86
ML		 12639 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12641 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12642 bool active;
8af6cf88 12643
4d20cd86
ML		 12644 if (!needs_modeset(crtc->state))
12645 continue;
045ac3b5 12646
4d20cd86
ML		 12647 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12648 pipe_config = to_intel_crtc_state(old_crtc_state);
12649 memset(pipe_config, 0, sizeof(*pipe_config));
12650 pipe_config->base.crtc = crtc;
12651 pipe_config->base.state = old_state;
8af6cf88 12652
4d20cd86
ML		 12653 DRM_DEBUG_KMS("[CRTC:%d]\n",
12654 crtc->base.id);
8af6cf88 12655
4d20cd86
ML		 12656 active = dev_priv->display.get_pipe_config(intel_crtc,
12657 pipe_config);
d62cf62a 12658
b6b5d049 12659 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12660 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12661 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12662 active = crtc->state->active;
6c49f241 12663
4d20cd86 12664 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12665 "crtc active state doesn't match with hw state "
4d20cd86 12666 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12667
4d20cd86 12668 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12669 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12670 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12671
12672 for_each_encoder_on_crtc(dev, crtc, encoder) {
12673 enum pipe pipe;
12674
12675 active = encoder->get_hw_state(encoder, &pipe);
12676 I915_STATE_WARN(active != crtc->state->active,
12677 "[ENCODER:%i] active %i with crtc active %i\n",
12678 encoder->base.base.id, active, crtc->state->active);
12679
12680 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12681 "Encoder connected to wrong pipe %c\n",
12682 pipe_name(pipe));
12683
12684 if (active)
12685 encoder->get_config(encoder, pipe_config);
12686 }
53d9f4e9 12687
4d20cd86 12688 if (!crtc->state->active)
cfb23ed6
ML		 12689 continue;
12690
4d20cd86
ML		 12691 sw_config = to_intel_crtc_state(crtc->state);
12692 if (!intel_pipe_config_compare(dev, sw_config,
12693 pipe_config, false)) {
e2c719b7 12694 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12695 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12696 "[hw state]");
4d20cd86 12697 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12698 "[sw state]");
12699 }
8af6cf88
DV		 12700 }
12701}
12702
91d1b4bd
DV		 12703static void
12704check_shared_dpll_state(struct drm_device *dev)
12705{
fbee40df 12706 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12707 struct intel_crtc *crtc;
12708 struct intel_dpll_hw_state dpll_hw_state;
12709 int i;
5358901f
DV		 12710
12711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12712 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12713 int enabled_crtcs = 0, active_crtcs = 0;
12714 bool active;
12715
12716 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12717
12718 DRM_DEBUG_KMS("%s\n", pll->name);
12719
12720 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12721
e2c719b7 12722 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12723 "more active pll users than references: %i vs %i\n",
3e369b76 12724 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12725 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12726 "pll in active use but not on in sw tracking\n");
e2c719b7 12727 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12728 "pll in on but not on in use in sw tracking\n");
e2c719b7 12729 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12730 "pll on state mismatch (expected %i, found %i)\n",
12731 pll->on, active);
12732
d3fcc808 12733 for_each_intel_crtc(dev, crtc) {
83d65738 12734 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12735 enabled_crtcs++;
12736 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12737 active_crtcs++;
12738 }
e2c719b7 12739 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12740 "pll active crtcs mismatch (expected %i, found %i)\n",
12741 pll->active, active_crtcs);
e2c719b7 12742 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12743 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12744 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12745
e2c719b7 12746 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12747 sizeof(dpll_hw_state)),
12748 "pll hw state mismatch\n");
5358901f 12749 }
8af6cf88
DV		 12750}
12751
ee165b1a
ML		 12752static void
12753intel_modeset_check_state(struct drm_device *dev,
12754 struct drm_atomic_state *old_state)
91d1b4bd 12755{
08db6652 12756 check_wm_state(dev);
35dd3c64 12757 check_connector_state(dev, old_state);
91d1b4bd 12758 check_encoder_state(dev);
4d20cd86 12759 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12760 check_shared_dpll_state(dev);
12761}
12762
5cec258b 12763void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12764 int dotclock)
12765{
12766 /*
12767 * FDI already provided one idea for the dotclock.
12768 * Yell if the encoder disagrees.
12769 */
2d112de7 12770 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12771 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12772 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12773}
12774
80715b2f
VS		 12775static void update_scanline_offset(struct intel_crtc *crtc)
12776{
12777 struct drm_device *dev = crtc->base.dev;
12778
12779 /*
12780 * The scanline counter increments at the leading edge of hsync.
12781 *
12782 * On most platforms it starts counting from vtotal-1 on the
12783 * first active line. That means the scanline counter value is
12784 * always one less than what we would expect. Ie. just after
12785 * start of vblank, which also occurs at start of hsync (on the
12786 * last active line), the scanline counter will read vblank_start-1.
12787 *
12788 * On gen2 the scanline counter starts counting from 1 instead
12789 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12790 * to keep the value positive), instead of adding one.
12791 *
12792 * On HSW+ the behaviour of the scanline counter depends on the output
12793 * type. For DP ports it behaves like most other platforms, but on HDMI
12794 * there's an extra 1 line difference. So we need to add two instead of
12795 * one to the value.
12796 */
12797 if (IS_GEN2(dev)) {
6e3c9717 12798 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12799 int vtotal;
12800
12801 vtotal = mode->crtc_vtotal;
12802 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12803 vtotal /= 2;
12804
12805 crtc->scanline_offset = vtotal - 1;
12806 } else if (HAS_DDI(dev) &&
409ee761 12807 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12808 crtc->scanline_offset = 2;
12809 } else
12810 crtc->scanline_offset = 1;
12811}
12812
ad421372 12813static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12814{
225da59b 12815 struct drm_device *dev = state->dev;
ed6739ef 12816 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12817 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12818 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12819 struct intel_crtc_state *intel_crtc_state;
12820 struct drm_crtc *crtc;
12821 struct drm_crtc_state *crtc_state;
0a9ab303 12822 int i;
ed6739ef
ACO		 12823
12824 if (!dev_priv->display.crtc_compute_clock)
ad421372 12825 return;
ed6739ef 12826
0a9ab303 12827 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12828 int dpll;
12829
0a9ab303 12830 intel_crtc = to_intel_crtc(crtc);
4978cc93 12831 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12832 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12833
ad421372 12834 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12835 continue;
12836
ad421372 12837 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12838
ad421372
ML		 12839 if (!shared_dpll)
12840 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12841
ad421372
ML		 12842 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12843 }
ed6739ef
ACO		 12844}
12845
99d736a2
ML		 12846/*
12847 * This implements the workaround described in the "notes" section of the mode
12848 * set sequence documentation. When going from no pipes or single pipe to
12849 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12850 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12851 */
12852static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12853{
12854 struct drm_crtc_state *crtc_state;
12855 struct intel_crtc *intel_crtc;
12856 struct drm_crtc *crtc;
12857 struct intel_crtc_state *first_crtc_state = NULL;
12858 struct intel_crtc_state *other_crtc_state = NULL;
12859 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12860 int i;
12861
12862 /* look at all crtc's that are going to be enabled in during modeset */
12863 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12864 intel_crtc = to_intel_crtc(crtc);
12865
12866 if (!crtc_state->active || !needs_modeset(crtc_state))
12867 continue;
12868
12869 if (first_crtc_state) {
12870 other_crtc_state = to_intel_crtc_state(crtc_state);
12871 break;
12872 } else {
12873 first_crtc_state = to_intel_crtc_state(crtc_state);
12874 first_pipe = intel_crtc->pipe;
12875 }
12876 }
12877
12878 /* No workaround needed? */
12879 if (!first_crtc_state)
12880 return 0;
12881
12882 /* w/a possibly needed, check how many crtc's are already enabled. */
12883 for_each_intel_crtc(state->dev, intel_crtc) {
12884 struct intel_crtc_state *pipe_config;
12885
12886 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12887 if (IS_ERR(pipe_config))
12888 return PTR_ERR(pipe_config);
12889
12890 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12891
12892 if (!pipe_config->base.active ||
12893 needs_modeset(&pipe_config->base))
12894 continue;
12895
12896 /* 2 or more enabled crtcs means no need for w/a */
12897 if (enabled_pipe != INVALID_PIPE)
12898 return 0;
12899
12900 enabled_pipe = intel_crtc->pipe;
12901 }
12902
12903 if (enabled_pipe != INVALID_PIPE)
12904 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12905 else if (other_crtc_state)
12906 other_crtc_state->hsw_workaround_pipe = first_pipe;
12907
12908 return 0;
12909}
12910
27c329ed
ML		 12911static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12912{
12913 struct drm_crtc *crtc;
12914 struct drm_crtc_state *crtc_state;
12915 int ret = 0;
12916
12917 /* add all active pipes to the state */
12918 for_each_crtc(state->dev, crtc) {
12919 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12920 if (IS_ERR(crtc_state))
12921 return PTR_ERR(crtc_state);
12922
12923 if (!crtc_state->active || needs_modeset(crtc_state))
12924 continue;
12925
12926 crtc_state->mode_changed = true;
12927
12928 ret = drm_atomic_add_affected_connectors(state, crtc);
12929 if (ret)
12930 break;
12931
12932 ret = drm_atomic_add_affected_planes(state, crtc);
12933 if (ret)
12934 break;
12935 }
12936
12937 return ret;
12938}
12939
12940
c347a676 12941static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12942{
12943 struct drm_device *dev = state->dev;
27c329ed 12944 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12945 int ret;
12946
b359283a
ML		 12947 if (!check_digital_port_conflicts(state)) {
12948 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12949 return -EINVAL;
12950 }
12951
054518dd
ACO		 12952 /*
12953 * See if the config requires any additional preparation, e.g.
12954 * to adjust global state with pipes off. We need to do this
12955 * here so we can get the modeset_pipe updated config for the new
12956 * mode set on this crtc. For other crtcs we need to use the
12957 * adjusted_mode bits in the crtc directly.
12958 */
27c329ed
ML		 12959 if (dev_priv->display.modeset_calc_cdclk) {
12960 unsigned int cdclk;
b432e5cf 12961
27c329ed
ML		 12962 ret = dev_priv->display.modeset_calc_cdclk(state);
12963
12964 cdclk = to_intel_atomic_state(state)->cdclk;
12965 if (!ret && cdclk != dev_priv->cdclk_freq)
12966 ret = intel_modeset_all_pipes(state);
12967
12968 if (ret < 0)
054518dd 12969 return ret;
27c329ed
ML		 12970 } else
12971 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12972
ad421372 12973 intel_modeset_clear_plls(state);
054518dd 12974
99d736a2 12975 if (IS_HASWELL(dev))
ad421372 12976 return haswell_mode_set_planes_workaround(state);
99d736a2 12977
ad421372 12978 return 0;
c347a676
ACO		 12979}
12980
74c090b1
ML		 12981/**
12982 * intel_atomic_check - validate state object
12983 * @dev: drm device
12984 * @state: state to validate
12985 */
12986static int intel_atomic_check(struct drm_device *dev,
12987 struct drm_atomic_state *state)
c347a676
ACO		 12988{
12989 struct drm_crtc *crtc;
12990 struct drm_crtc_state *crtc_state;
12991 int ret, i;
61333b60 12992 bool any_ms = false;
c347a676 12993
74c090b1 12994 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12995 if (ret)
12996 return ret;
12997
c347a676 12998 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12999 struct intel_crtc_state *pipe_config =
13000 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13001
13002 /* Catch I915_MODE_FLAG_INHERITED */
13003 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13004 crtc_state->mode_changed = true;
cfb23ed6 13005
61333b60
ML		 13006 if (!crtc_state->enable) {
13007 if (needs_modeset(crtc_state))
13008 any_ms = true;
c347a676 13009 continue;
61333b60 13010 }
c347a676 13011
26495481 13012 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13013 continue;
13014
26495481
DV		 13015 /* FIXME: For only active_changed we shouldn't need to do any
13016 * state recomputation at all. */
13017
1ed51de9
DV		 13018 ret = drm_atomic_add_affected_connectors(state, crtc);
13019 if (ret)
13020 return ret;
b359283a 13021
cfb23ed6 13022 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13023 if (ret)
13024 return ret;
13025
26495481
DV		 13026 if (i915.fastboot &&
13027 intel_pipe_config_compare(state->dev,
cfb23ed6 13028 to_intel_crtc_state(crtc->state),
1ed51de9 13029 pipe_config, true)) {
26495481
DV		 13030 crtc_state->mode_changed = false;
13031 }
13032
13033 if (needs_modeset(crtc_state)) {
13034 any_ms = true;
cfb23ed6
ML		 13035
13036 ret = drm_atomic_add_affected_planes(state, crtc);
13037 if (ret)
13038 return ret;
13039 }
61333b60 13040
26495481
DV		 13041 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13042 needs_modeset(crtc_state) ?
13043 "[modeset]" : "[fastset]");
c347a676
ACO		 13044 }
13045
61333b60
ML		 13046 if (any_ms) {
13047 ret = intel_modeset_checks(state);
13048
13049 if (ret)
13050 return ret;
27c329ed
ML		 13051 } else
13052 to_intel_atomic_state(state)->cdclk =
13053 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13054
13055 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13056}
13057
74c090b1
ML		 13058/**
13059 * intel_atomic_commit - commit validated state object
13060 * @dev: DRM device
13061 * @state: the top-level driver state object
13062 * @async: asynchronous commit
13063 *
13064 * This function commits a top-level state object that has been validated
13065 * with drm_atomic_helper_check().
13066 *
13067 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13068 * we can only handle plane-related operations and do not yet support
13069 * asynchronous commit.
13070 *
13071 * RETURNS
13072 * Zero for success or -errno.
13073 */
13074static int intel_atomic_commit(struct drm_device *dev,
13075 struct drm_atomic_state *state,
13076 bool async)
a6778b3c 13077{
fbee40df 13078 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13079 struct drm_crtc *crtc;
13080 struct drm_crtc_state *crtc_state;
c0c36b94 13081 int ret = 0;
0a9ab303 13082 int i;
61333b60 13083 bool any_ms = false;
a6778b3c 13084
74c090b1
ML		 13085 if (async) {
13086 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13087 return -EINVAL;
13088 }
13089
d4afb8cc
ACO		 13090 ret = drm_atomic_helper_prepare_planes(dev, state);
13091 if (ret)
13092 return ret;
13093
1c5e19f8
ML		 13094 drm_atomic_helper_swap_state(dev, state);
13095
0a9ab303 13096 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13098
61333b60
ML		 13099 if (!needs_modeset(crtc->state))
13100 continue;
13101
13102 any_ms = true;
a539205a 13103 intel_pre_plane_update(intel_crtc);
460da916 13104
a539205a
ML		 13105 if (crtc_state->active) {
13106 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13107 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13108 intel_crtc->active = false;
13109 intel_disable_shared_dpll(intel_crtc);
a539205a 13110 }
b8cecdf5 13111 }
7758a113 13112
ea9d758d
DV		 13113 /* Only after disabling all output pipelines that will be changed can we
13114 * update the the output configuration. */
4740b0f2 13115 intel_modeset_update_crtc_state(state);
f6e5b160 13116
4740b0f2
ML		 13117 if (any_ms) {
13118 intel_shared_dpll_commit(state);
13119
13120 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13121 modeset_update_crtc_power_domains(state);
4740b0f2 13122 }
47fab737 13123
a6778b3c 13124 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13125 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13127 bool modeset = needs_modeset(crtc->state);
13128
13129 if (modeset && crtc->state->active) {
a539205a
ML		 13130 update_scanline_offset(to_intel_crtc(crtc));
13131 dev_priv->display.crtc_enable(crtc);
13132 }
80715b2f 13133
f6ac4b2a
ML		 13134 if (!modeset)
13135 intel_pre_plane_update(intel_crtc);
13136
a539205a 13137 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13138 intel_post_plane_update(intel_crtc);
80715b2f 13139 }
a6778b3c 13140
a6778b3c 13141 /* FIXME: add subpixel order */
83a57153 13142
74c090b1 13143 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13144 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13145
74c090b1 13146 if (any_ms)
ee165b1a
ML		 13147 intel_modeset_check_state(dev, state);
13148
13149 drm_atomic_state_free(state);
f30da187 13150
74c090b1 13151 return 0;
7f27126e
JB		 13152}
13153
c0c36b94
CW		 13154void intel_crtc_restore_mode(struct drm_crtc *crtc)
13155{
83a57153
ACO		 13156 struct drm_device *dev = crtc->dev;
13157 struct drm_atomic_state *state;
e694eb02 13158 struct drm_crtc_state *crtc_state;
2bfb4627 13159 int ret;
83a57153
ACO		 13160
13161 state = drm_atomic_state_alloc(dev);
13162 if (!state) {
e694eb02 13163 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13164 crtc->base.id);
13165 return;
13166 }
13167
e694eb02 13168 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13169
e694eb02
ML		 13170retry:
13171 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13172 ret = PTR_ERR_OR_ZERO(crtc_state);
13173 if (!ret) {
13174 if (!crtc_state->active)
13175 goto out;
83a57153 13176
e694eb02 13177 crtc_state->mode_changed = true;
74c090b1 13178 ret = drm_atomic_commit(state);
83a57153
ACO		 13179 }
13180
e694eb02
ML		 13181 if (ret == -EDEADLK) {
13182 drm_atomic_state_clear(state);
13183 drm_modeset_backoff(state->acquire_ctx);
13184 goto retry;
4ed9fb37 13185 }
4be07317 13186
2bfb4627 13187 if (ret)
e694eb02 13188out:
2bfb4627 13189 drm_atomic_state_free(state);
c0c36b94
CW		 13190}
13191
25c5b266
DV		 13192#undef for_each_intel_crtc_masked
13193
f6e5b160 13194static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13195 .gamma_set = intel_crtc_gamma_set,
74c090b1 13196 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13197 .destroy = intel_crtc_destroy,
13198 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13199 .atomic_duplicate_state = intel_crtc_duplicate_state,
13200 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13201};
13202
5358901f
DV		 13203static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13204 struct intel_shared_dpll *pll,
13205 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13206{
5358901f 13207 uint32_t val;
ee7b9f93 13208
f458ebbc 13209 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13210 return false;
13211
5358901f 13212 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13213 hw_state->dpll = val;
13214 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13215 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13216
13217 return val & DPLL_VCO_ENABLE;
13218}
13219
15bdd4cf
DV		 13220static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13221 struct intel_shared_dpll *pll)
13222{
3e369b76
ACO		 13223 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13224 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13225}
13226
e7b903d2
DV		 13227static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13228 struct intel_shared_dpll *pll)
13229{
e7b903d2 13230 /* PCH refclock must be enabled first */
89eff4be 13231 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13232
3e369b76 13233 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13234
13235 /* Wait for the clocks to stabilize. */
13236 POSTING_READ(PCH_DPLL(pll->id));
13237 udelay(150);
13238
13239 /* The pixel multiplier can only be updated once the
13240 * DPLL is enabled and the clocks are stable.
13241 *
13242 * So write it again.
13243 */
3e369b76 13244 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13245 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13246 udelay(200);
13247}
13248
13249static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13250 struct intel_shared_dpll *pll)
13251{
13252 struct drm_device *dev = dev_priv->dev;
13253 struct intel_crtc *crtc;
e7b903d2
DV		 13254
13255 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13256 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13257 if (intel_crtc_to_shared_dpll(crtc) == pll)
13258 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13259 }
13260
15bdd4cf
DV		 13261 I915_WRITE(PCH_DPLL(pll->id), 0);
13262 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13263 udelay(200);
13264}
13265
46edb027
DV		 13266static char *ibx_pch_dpll_names[] = {
13267 "PCH DPLL A",
13268 "PCH DPLL B",
13269};
13270
7c74ade1 13271static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13272{
e7b903d2 13273 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13274 int i;
13275
7c74ade1 13276 dev_priv->num_shared_dpll = 2;
ee7b9f93 13277
e72f9fbf 13278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13279 dev_priv->shared_dplls[i].id = i;
13280 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13281 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13282 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13283 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13284 dev_priv->shared_dplls[i].get_hw_state =
13285 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13286 }
13287}
13288
7c74ade1
DV		 13289static void intel_shared_dpll_init(struct drm_device *dev)
13290{
e7b903d2 13291 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13292
b6283055
VS		 13293 intel_update_cdclk(dev);
13294
9cd86933
DV		 13295 if (HAS_DDI(dev))
13296 intel_ddi_pll_init(dev);
13297 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13298 ibx_pch_dpll_init(dev);
13299 else
13300 dev_priv->num_shared_dpll = 0;
13301
13302 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13303}
13304
6beb8c23
MR		 13305/**
13306 * intel_prepare_plane_fb - Prepare fb for usage on plane
13307 * @plane: drm plane to prepare for
13308 * @fb: framebuffer to prepare for presentation
13309 *
13310 * Prepares a framebuffer for usage on a display plane. Generally this
13311 * involves pinning the underlying object and updating the frontbuffer tracking
13312 * bits. Some older platforms need special physical address handling for
13313 * cursor planes.
13314 *
13315 * Returns 0 on success, negative error code on failure.
13316 */
13317int
13318intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13319 struct drm_framebuffer *fb,
13320 const struct drm_plane_state *new_state)
465c120c
MR		 13321{
13322 struct drm_device *dev = plane->dev;
6beb8c23 13323 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13324 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13325 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13326 int ret = 0;
465c120c 13327
ea2c67bb 13328 if (!obj)
465c120c
MR		 13329 return 0;
13330
6beb8c23 13331 mutex_lock(&dev->struct_mutex);
465c120c 13332
6beb8c23
MR		 13333 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13334 INTEL_INFO(dev)->cursor_needs_physical) {
13335 int align = IS_I830(dev) ? 16 * 1024 : 256;
13336 ret = i915_gem_object_attach_phys(obj, align);
13337 if (ret)
13338 DRM_DEBUG_KMS("failed to attach phys object\n");
13339 } else {
91af127f 13340 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13341 }
465c120c 13342
6beb8c23 13343 if (ret == 0)
a9ff8714 13344 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13345
4c34574f 13346 mutex_unlock(&dev->struct_mutex);
465c120c 13347
6beb8c23
MR		 13348 return ret;
13349}
13350
38f3ce3a
MR		 13351/**
13352 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13353 * @plane: drm plane to clean up for
13354 * @fb: old framebuffer that was on plane
13355 *
13356 * Cleans up a framebuffer that has just been removed from a plane.
13357 */
13358void
13359intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13360 struct drm_framebuffer *fb,
13361 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13362{
13363 struct drm_device *dev = plane->dev;
13364 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13365
13366 if (WARN_ON(!obj))
13367 return;
13368
13369 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13370 !INTEL_INFO(dev)->cursor_needs_physical) {
13371 mutex_lock(&dev->struct_mutex);
82bc3b2d 13372 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13373 mutex_unlock(&dev->struct_mutex);
13374 }
465c120c
MR		 13375}
13376
6156a456
CK		 13377int
13378skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13379{
13380 int max_scale;
13381 struct drm_device *dev;
13382 struct drm_i915_private *dev_priv;
13383 int crtc_clock, cdclk;
13384
13385 if (!intel_crtc || !crtc_state)
13386 return DRM_PLANE_HELPER_NO_SCALING;
13387
13388 dev = intel_crtc->base.dev;
13389 dev_priv = dev->dev_private;
13390 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13391 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13392
13393 if (!crtc_clock || !cdclk)
13394 return DRM_PLANE_HELPER_NO_SCALING;
13395
13396 /*
13397 * skl max scale is lower of:
13398 * close to 3 but not 3, -1 is for that purpose
13399 * or
13400 * cdclk/crtc_clock
13401 */
13402 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13403
13404 return max_scale;
13405}
13406
465c120c 13407static int
3c692a41 13408intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13409 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13410 struct intel_plane_state *state)
13411{
2b875c22
MR		 13412 struct drm_crtc *crtc = state->base.crtc;
13413 struct drm_framebuffer *fb = state->base.fb;
6156a456 13414 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13415 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13416 bool can_position = false;
465c120c 13417
061e4b8d
ML		 13418 /* use scaler when colorkey is not required */
13419 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13420 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13421 min_scale = 1;
13422 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13423 can_position = true;
6156a456 13424 }
d8106366 13425
061e4b8d
ML		 13426 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13427 &state->dst, &state->clip,
da20eabd
ML		 13428 min_scale, max_scale,
13429 can_position, true,
13430 &state->visible);
14af293f
GP		 13431}
13432
13433static void
13434intel_commit_primary_plane(struct drm_plane *plane,
13435 struct intel_plane_state *state)
13436{
2b875c22
MR		 13437 struct drm_crtc *crtc = state->base.crtc;
13438 struct drm_framebuffer *fb = state->base.fb;
13439 struct drm_device *dev = plane->dev;
14af293f 13440 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13441 struct intel_crtc *intel_crtc;
14af293f
GP		 13442 struct drm_rect *src = &state->src;
13443
ea2c67bb
MR		 13444 crtc = crtc ? crtc : plane->crtc;
13445 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13446
13447 plane->fb = fb;
9dc806fc
MR		 13448 crtc->x = src->x1 >> 16;
13449 crtc->y = src->y1 >> 16;
ccc759dc 13450
a539205a 13451 if (!crtc->state->active)
302d19ac 13452 return;
465c120c 13453
302d19ac
ML		 13454 if (state->visible)
13455 /* FIXME: kill this fastboot hack */
13456 intel_update_pipe_size(intel_crtc);
13457
13458 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13459}
13460
a8ad0d8e
ML		 13461static void
13462intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13463 struct drm_crtc *crtc)
a8ad0d8e
ML		 13464{
13465 struct drm_device *dev = plane->dev;
13466 struct drm_i915_private *dev_priv = dev->dev_private;
13467
a8ad0d8e
ML		 13468 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13469}
13470
613d2b27
ML		 13471static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13472 struct drm_crtc_state *old_crtc_state)
3c692a41 13473{
32b7eeec 13474 struct drm_device *dev = crtc->dev;
3c692a41 13475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13476
f015c551 13477 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13478 intel_update_watermarks(crtc);
3c692a41 13479
c34c9ee4 13480 /* Perform vblank evasion around commit operation */
a539205a 13481 if (crtc->state->active)
8f539a83 13482 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
0583236e
ML		 13483
13484 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13485 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13486}
13487
613d2b27
ML		 13488static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13489 struct drm_crtc_state *old_crtc_state)
32b7eeec 13490{
32b7eeec 13491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13492
8f539a83
ML		 13493 if (crtc->state->active)
13494 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
3c692a41
GP		 13495}
13496
cf4c7c12 13497/**
4a3b8769
MR		 13498 * intel_plane_destroy - destroy a plane
13499 * @plane: plane to destroy
cf4c7c12 13500 *
4a3b8769
MR		 13501 * Common destruction function for all types of planes (primary, cursor,
13502 * sprite).
cf4c7c12 13503 */
4a3b8769 13504void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13505{
13506 struct intel_plane *intel_plane = to_intel_plane(plane);
13507 drm_plane_cleanup(plane);
13508 kfree(intel_plane);
13509}
13510
65a3fea0 13511const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13512 .update_plane = drm_atomic_helper_update_plane,
13513 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13514 .destroy = intel_plane_destroy,
c196e1d6 13515 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13516 .atomic_get_property = intel_plane_atomic_get_property,
13517 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13518 .atomic_duplicate_state = intel_plane_duplicate_state,
13519 .atomic_destroy_state = intel_plane_destroy_state,
13520
465c120c
MR		 13521};
13522
13523static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13524 int pipe)
13525{
13526 struct intel_plane *primary;
8e7d688b 13527 struct intel_plane_state *state;
465c120c
MR		 13528 const uint32_t *intel_primary_formats;
13529 int num_formats;
13530
13531 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13532 if (primary == NULL)
13533 return NULL;
13534
8e7d688b
MR		 13535 state = intel_create_plane_state(&primary->base);
13536 if (!state) {
ea2c67bb
MR		 13537 kfree(primary);
13538 return NULL;
13539 }
8e7d688b 13540 primary->base.state = &state->base;
ea2c67bb 13541
465c120c
MR		 13542 primary->can_scale = false;
13543 primary->max_downscale = 1;
6156a456
CK		 13544 if (INTEL_INFO(dev)->gen >= 9) {
13545 primary->can_scale = true;
af99ceda 13546 state->scaler_id = -1;
6156a456 13547 }
465c120c
MR		 13548 primary->pipe = pipe;
13549 primary->plane = pipe;
a9ff8714 13550 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13551 primary->check_plane = intel_check_primary_plane;
13552 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13553 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13554 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13555 primary->plane = !pipe;
13556
6c0fd451
DL		 13557 if (INTEL_INFO(dev)->gen >= 9) {
13558 intel_primary_formats = skl_primary_formats;
13559 num_formats = ARRAY_SIZE(skl_primary_formats);
13560 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13561 intel_primary_formats = i965_primary_formats;
13562 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13563 } else {
13564 intel_primary_formats = i8xx_primary_formats;
13565 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13566 }
13567
13568 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13569 &intel_plane_funcs,
465c120c
MR		 13570 intel_primary_formats, num_formats,
13571 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13572
3b7a5119
SJ		 13573 if (INTEL_INFO(dev)->gen >= 4)
13574 intel_create_rotation_property(dev, primary);
48404c1e 13575
ea2c67bb
MR		 13576 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13577
465c120c
MR		 13578 return &primary->base;
13579}
13580
3b7a5119
SJ		 13581void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13582{
13583 if (!dev->mode_config.rotation_property) {
13584 unsigned long flags = BIT(DRM_ROTATE_0) |
13585 BIT(DRM_ROTATE_180);
13586
13587 if (INTEL_INFO(dev)->gen >= 9)
13588 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13589
13590 dev->mode_config.rotation_property =
13591 drm_mode_create_rotation_property(dev, flags);
13592 }
13593 if (dev->mode_config.rotation_property)
13594 drm_object_attach_property(&plane->base.base,
13595 dev->mode_config.rotation_property,
13596 plane->base.state->rotation);
13597}
13598
3d7d6510 13599static int
852e787c 13600intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13601 struct intel_crtc_state *crtc_state,
852e787c 13602 struct intel_plane_state *state)
3d7d6510 13603{
061e4b8d 13604 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13605 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13606 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13607 unsigned stride;
13608 int ret;
3d7d6510 13609
061e4b8d
ML		 13610 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13611 &state->dst, &state->clip,
3d7d6510
MR		 13612 DRM_PLANE_HELPER_NO_SCALING,
13613 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13614 true, true, &state->visible);
757f9a3e
GP		 13615 if (ret)
13616 return ret;
13617
757f9a3e
GP		 13618 /* if we want to turn off the cursor ignore width and height */
13619 if (!obj)
da20eabd 13620 return 0;
757f9a3e 13621
757f9a3e 13622 /* Check for which cursor types we support */
061e4b8d 13623 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13624 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13625 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13626 return -EINVAL;
13627 }
13628
ea2c67bb
MR		 13629 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13630 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13631 DRM_DEBUG_KMS("buffer is too small\n");
13632 return -ENOMEM;
13633 }
13634
3a656b54 13635 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13636 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13637 return -EINVAL;
32b7eeec
MR		 13638 }
13639
da20eabd 13640 return 0;
852e787c 13641}
3d7d6510 13642
a8ad0d8e
ML		 13643static void
13644intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13645 struct drm_crtc *crtc)
a8ad0d8e 13646{
a8ad0d8e
ML		 13647 intel_crtc_update_cursor(crtc, false);
13648}
13649
f4a2cf29 13650static void
852e787c
GP		 13651intel_commit_cursor_plane(struct drm_plane *plane,
13652 struct intel_plane_state *state)
13653{
2b875c22 13654 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13655 struct drm_device *dev = plane->dev;
13656 struct intel_crtc *intel_crtc;
2b875c22 13657 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13658 uint32_t addr;
852e787c 13659
ea2c67bb
MR		 13660 crtc = crtc ? crtc : plane->crtc;
13661 intel_crtc = to_intel_crtc(crtc);
13662
2b875c22 13663 plane->fb = state->base.fb;
ea2c67bb
MR		 13664 crtc->cursor_x = state->base.crtc_x;
13665 crtc->cursor_y = state->base.crtc_y;
13666
a912f12f
GP		 13667 if (intel_crtc->cursor_bo == obj)
13668 goto update;
4ed91096 13669
f4a2cf29 13670 if (!obj)
a912f12f 13671 addr = 0;
f4a2cf29 13672 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13673 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13674 else
a912f12f 13675 addr = obj->phys_handle->busaddr;
852e787c 13676
a912f12f
GP		 13677 intel_crtc->cursor_addr = addr;
13678 intel_crtc->cursor_bo = obj;
852e787c 13679
302d19ac 13680update:
a539205a 13681 if (crtc->state->active)
a912f12f 13682 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13683}
13684
3d7d6510
MR		 13685static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13686 int pipe)
13687{
13688 struct intel_plane *cursor;
8e7d688b 13689 struct intel_plane_state *state;
3d7d6510
MR		 13690
13691 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13692 if (cursor == NULL)
13693 return NULL;
13694
8e7d688b
MR		 13695 state = intel_create_plane_state(&cursor->base);
13696 if (!state) {
ea2c67bb
MR		 13697 kfree(cursor);
13698 return NULL;
13699 }
8e7d688b 13700 cursor->base.state = &state->base;
ea2c67bb 13701
3d7d6510
MR		 13702 cursor->can_scale = false;
13703 cursor->max_downscale = 1;
13704 cursor->pipe = pipe;
13705 cursor->plane = pipe;
a9ff8714 13706 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13707 cursor->check_plane = intel_check_cursor_plane;
13708 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13709 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13710
13711 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13712 &intel_plane_funcs,
3d7d6510
MR		 13713 intel_cursor_formats,
13714 ARRAY_SIZE(intel_cursor_formats),
13715 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13716
13717 if (INTEL_INFO(dev)->gen >= 4) {
13718 if (!dev->mode_config.rotation_property)
13719 dev->mode_config.rotation_property =
13720 drm_mode_create_rotation_property(dev,
13721 BIT(DRM_ROTATE_0) |
13722 BIT(DRM_ROTATE_180));
13723 if (dev->mode_config.rotation_property)
13724 drm_object_attach_property(&cursor->base.base,
13725 dev->mode_config.rotation_property,
8e7d688b 13726 state->base.rotation);
4398ad45
VS		 13727 }
13728
af99ceda
CK		 13729 if (INTEL_INFO(dev)->gen >=9)
13730 state->scaler_id = -1;
13731
ea2c67bb
MR		 13732 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13733
3d7d6510
MR		 13734 return &cursor->base;
13735}
13736
549e2bfb
CK		 13737static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13738 struct intel_crtc_state *crtc_state)
13739{
13740 int i;
13741 struct intel_scaler *intel_scaler;
13742 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13743
13744 for (i = 0; i < intel_crtc->num_scalers; i++) {
13745 intel_scaler = &scaler_state->scalers[i];
13746 intel_scaler->in_use = 0;
549e2bfb
CK		 13747 intel_scaler->mode = PS_SCALER_MODE_DYN;
13748 }
13749
13750 scaler_state->scaler_id = -1;
13751}
13752
b358d0a6 13753static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13754{
fbee40df 13755 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13756 struct intel_crtc *intel_crtc;
f5de6e07 13757 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13758 struct drm_plane *primary = NULL;
13759 struct drm_plane *cursor = NULL;
465c120c 13760 int i, ret;
79e53945 13761
955382f3 13762 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13763 if (intel_crtc == NULL)
13764 return;
13765
f5de6e07
ACO		 13766 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13767 if (!crtc_state)
13768 goto fail;
550acefd
ACO		 13769 intel_crtc->config = crtc_state;
13770 intel_crtc->base.state = &crtc_state->base;
07878248 13771 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13772
549e2bfb
CK		 13773 /* initialize shared scalers */
13774 if (INTEL_INFO(dev)->gen >= 9) {
13775 if (pipe == PIPE_C)
13776 intel_crtc->num_scalers = 1;
13777 else
13778 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13779
13780 skl_init_scalers(dev, intel_crtc, crtc_state);
13781 }
13782
465c120c 13783 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13784 if (!primary)
13785 goto fail;
13786
13787 cursor = intel_cursor_plane_create(dev, pipe);
13788 if (!cursor)
13789 goto fail;
13790
465c120c 13791 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13792 cursor, &intel_crtc_funcs);
13793 if (ret)
13794 goto fail;
79e53945
JB		 13795
13796 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13797 for (i = 0; i < 256; i++) {
13798 intel_crtc->lut_r[i] = i;
13799 intel_crtc->lut_g[i] = i;
13800 intel_crtc->lut_b[i] = i;
13801 }
13802
1f1c2e24
VS		 13803 /*
13804 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13805 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13806 */
80824003
JB		 13807 intel_crtc->pipe = pipe;
13808 intel_crtc->plane = pipe;
3a77c4c4 13809 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13810 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13811 intel_crtc->plane = !pipe;
80824003
JB		 13812 }
13813
4b0e333e
CW		 13814 intel_crtc->cursor_base = ~0;
13815 intel_crtc->cursor_cntl = ~0;
dc41c154 13816 intel_crtc->cursor_size = ~0;
8d7849db 13817
852eb00d
VS		 13818 intel_crtc->wm.cxsr_allowed = true;
13819
22fd0fab
JB		 13820 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13821 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13822 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13823 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13824
79e53945 13825 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13826
13827 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13828 return;
13829
13830fail:
13831 if (primary)
13832 drm_plane_cleanup(primary);
13833 if (cursor)
13834 drm_plane_cleanup(cursor);
f5de6e07 13835 kfree(crtc_state);
3d7d6510 13836 kfree(intel_crtc);
79e53945
JB		 13837}
13838
752aa88a
JB		 13839enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13840{
13841 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13842 struct drm_device *dev = connector->base.dev;
752aa88a 13843
51fd371b 13844 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13845
d3babd3f 13846 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13847 return INVALID_PIPE;
13848
13849 return to_intel_crtc(encoder->crtc)->pipe;
13850}
13851
08d7b3d1 13852int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13853 struct drm_file *file)
08d7b3d1 13854{
08d7b3d1 13855 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13856 struct drm_crtc *drmmode_crtc;
c05422d5 13857 struct intel_crtc *crtc;
08d7b3d1 13858
7707e653 13859 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13860
7707e653 13861 if (!drmmode_crtc) {
08d7b3d1 13862 DRM_ERROR("no such CRTC id\n");
3f2c2057 13863 return -ENOENT;
08d7b3d1
CW		 13864 }
13865
7707e653 13866 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13867 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13868
c05422d5 13869 return 0;
08d7b3d1
CW		 13870}
13871
66a9278e 13872static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13873{
66a9278e
DV		 13874 struct drm_device *dev = encoder->base.dev;
13875 struct intel_encoder *source_encoder;
79e53945 13876 int index_mask = 0;
79e53945
JB		 13877 int entry = 0;
13878
b2784e15 13879 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13880 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13881 index_mask |= (1 << entry);
13882
79e53945
JB		 13883 entry++;
13884 }
4ef69c7a 13885
79e53945
JB		 13886 return index_mask;
13887}
13888
4d302442
CW		 13889static bool has_edp_a(struct drm_device *dev)
13890{
13891 struct drm_i915_private *dev_priv = dev->dev_private;
13892
13893 if (!IS_MOBILE(dev))
13894 return false;
13895
13896 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13897 return false;
13898
e3589908 13899 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13900 return false;
13901
13902 return true;
13903}
13904
84b4e042
JB		 13905static bool intel_crt_present(struct drm_device *dev)
13906{
13907 struct drm_i915_private *dev_priv = dev->dev_private;
13908
884497ed
DL		 13909 if (INTEL_INFO(dev)->gen >= 9)
13910 return false;
13911
cf404ce4 13912 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13913 return false;
13914
13915 if (IS_CHERRYVIEW(dev))
13916 return false;
13917
13918 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13919 return false;
13920
13921 return true;
13922}
13923
79e53945
JB		 13924static void intel_setup_outputs(struct drm_device *dev)
13925{
725e30ad 13926 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13927 struct intel_encoder *encoder;
cb0953d7 13928 bool dpd_is_edp = false;
79e53945 13929
c9093354 13930 intel_lvds_init(dev);
79e53945 13931
84b4e042 13932 if (intel_crt_present(dev))
79935fca 13933 intel_crt_init(dev);
cb0953d7 13934
c776eb2e
VK		 13935 if (IS_BROXTON(dev)) {
13936 /*
13937 * FIXME: Broxton doesn't support port detection via the
13938 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13939 * detect the ports.
13940 */
13941 intel_ddi_init(dev, PORT_A);
13942 intel_ddi_init(dev, PORT_B);
13943 intel_ddi_init(dev, PORT_C);
13944 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13945 int found;
13946
de31facd
JB		 13947 /*
13948 * Haswell uses DDI functions to detect digital outputs.
13949 * On SKL pre-D0 the strap isn't connected, so we assume
13950 * it's there.
13951 */
0e72a5b5 13952 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13953 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13954 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13955 intel_ddi_init(dev, PORT_A);
13956
13957 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13958 * register */
13959 found = I915_READ(SFUSE_STRAP);
13960
13961 if (found & SFUSE_STRAP_DDIB_DETECTED)
13962 intel_ddi_init(dev, PORT_B);
13963 if (found & SFUSE_STRAP_DDIC_DETECTED)
13964 intel_ddi_init(dev, PORT_C);
13965 if (found & SFUSE_STRAP_DDID_DETECTED)
13966 intel_ddi_init(dev, PORT_D);
13967 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13968 int found;
5d8a7752 13969 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13970
13971 if (has_edp_a(dev))
13972 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13973
dc0fa718 13974 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13975 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13976 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13977 if (!found)
e2debe91 13978 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13979 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13980 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13981 }
13982
dc0fa718 13983 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13984 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13985
dc0fa718 13986 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13987 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13988
5eb08b69 13989 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13990 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13991
270b3042 13992 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13993 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13994 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13995 /*
13996 * The DP_DETECTED bit is the latched state of the DDC
13997 * SDA pin at boot. However since eDP doesn't require DDC
13998 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13999 * eDP ports may have been muxed to an alternate function.
14000 * Thus we can't rely on the DP_DETECTED bit alone to detect
14001 * eDP ports. Consult the VBT as well as DP_DETECTED to
14002 * detect eDP ports.
14003 */
d2182a66
VS		 14004 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14005 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14006 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14007 PORT_B);
e17ac6db
VS		 14008 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14009 intel_dp_is_edp(dev, PORT_B))
14010 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14011
d2182a66
VS		 14012 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14013 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14014 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14015 PORT_C);
e17ac6db
VS		 14016 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14017 intel_dp_is_edp(dev, PORT_C))
14018 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14019
9418c1f1 14020 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14021 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14022 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14023 PORT_D);
e17ac6db
VS		 14024 /* eDP not supported on port D, so don't check VBT */
14025 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14026 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14027 }
14028
3cfca973 14029 intel_dsi_init(dev);
09da55dc 14030 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14031 bool found = false;
7d57382e 14032
e2debe91 14033 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14034 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14035 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14036 if (!found && IS_G4X(dev)) {
b01f2c3a 14037 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14038 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14039 }
27185ae1 14040
3fec3d2f 14041 if (!found && IS_G4X(dev))
ab9d7c30 14042 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14043 }
13520b05
KH		 14044
14045 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14046
e2debe91 14047 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14048 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14049 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14050 }
27185ae1 14051
e2debe91 14052 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14053
3fec3d2f 14054 if (IS_G4X(dev)) {
b01f2c3a 14055 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14056 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14057 }
3fec3d2f 14058 if (IS_G4X(dev))
ab9d7c30 14059 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14060 }
27185ae1 14061
3fec3d2f 14062 if (IS_G4X(dev) &&
e7281eab 14063 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14064 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14065 } else if (IS_GEN2(dev))
79e53945
JB		 14066 intel_dvo_init(dev);
14067
103a196f 14068 if (SUPPORTS_TV(dev))
79e53945
JB		 14069 intel_tv_init(dev);
14070
0bc12bcb 14071 intel_psr_init(dev);
7c8f8a70 14072
b2784e15 14073 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14074 encoder->base.possible_crtcs = encoder->crtc_mask;
14075 encoder->base.possible_clones =
66a9278e 14076 intel_encoder_clones(encoder);
79e53945 14077 }
47356eb6 14078
dde86e2d 14079 intel_init_pch_refclk(dev);
270b3042
DV		 14080
14081 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14082}
14083
14084static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14085{
60a5ca01 14086 struct drm_device *dev = fb->dev;
79e53945 14087 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14088
ef2d633e 14089 drm_framebuffer_cleanup(fb);
60a5ca01 14090 mutex_lock(&dev->struct_mutex);
ef2d633e 14091 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14092 drm_gem_object_unreference(&intel_fb->obj->base);
14093 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14094 kfree(intel_fb);
14095}
14096
14097static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14098 struct drm_file *file,
79e53945
JB		 14099 unsigned int *handle)
14100{
14101 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14102 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14103
05394f39 14104 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14105}
14106
86c98588
RV		 14107static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14108 struct drm_file *file,
14109 unsigned flags, unsigned color,
14110 struct drm_clip_rect *clips,
14111 unsigned num_clips)
14112{
14113 struct drm_device *dev = fb->dev;
14114 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14115 struct drm_i915_gem_object *obj = intel_fb->obj;
14116
14117 mutex_lock(&dev->struct_mutex);
74b4ea1e 14118 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14119 mutex_unlock(&dev->struct_mutex);
14120
14121 return 0;
14122}
14123
79e53945
JB		 14124static const struct drm_framebuffer_funcs intel_fb_funcs = {
14125 .destroy = intel_user_framebuffer_destroy,
14126 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14127 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14128};
14129
b321803d
DL		 14130static
14131u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14132 uint32_t pixel_format)
14133{
14134 u32 gen = INTEL_INFO(dev)->gen;
14135
14136 if (gen >= 9) {
14137 /* "The stride in bytes must not exceed the of the size of 8K
14138 * pixels and 32K bytes."
14139 */
14140 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14141 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14142 return 32*1024;
14143 } else if (gen >= 4) {
14144 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14145 return 16*1024;
14146 else
14147 return 32*1024;
14148 } else if (gen >= 3) {
14149 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14150 return 8*1024;
14151 else
14152 return 16*1024;
14153 } else {
14154 /* XXX DSPC is limited to 4k tiled */
14155 return 8*1024;
14156 }
14157}
14158
b5ea642a
DV		 14159static int intel_framebuffer_init(struct drm_device *dev,
14160 struct intel_framebuffer *intel_fb,
14161 struct drm_mode_fb_cmd2 *mode_cmd,
14162 struct drm_i915_gem_object *obj)
79e53945 14163{
6761dd31 14164 unsigned int aligned_height;
79e53945 14165 int ret;
b321803d 14166 u32 pitch_limit, stride_alignment;
79e53945 14167
dd4916c5
DV		 14168 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14169
2a80eada
DV		 14170 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14171 /* Enforce that fb modifier and tiling mode match, but only for
14172 * X-tiled. This is needed for FBC. */
14173 if (!!(obj->tiling_mode == I915_TILING_X) !=
14174 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14175 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14176 return -EINVAL;
14177 }
14178 } else {
14179 if (obj->tiling_mode == I915_TILING_X)
14180 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14181 else if (obj->tiling_mode == I915_TILING_Y) {
14182 DRM_DEBUG("No Y tiling for legacy addfb\n");
14183 return -EINVAL;
14184 }
14185 }
14186
9a8f0a12
TU		 14187 /* Passed in modifier sanity checking. */
14188 switch (mode_cmd->modifier[0]) {
14189 case I915_FORMAT_MOD_Y_TILED:
14190 case I915_FORMAT_MOD_Yf_TILED:
14191 if (INTEL_INFO(dev)->gen < 9) {
14192 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14193 mode_cmd->modifier[0]);
14194 return -EINVAL;
14195 }
14196 case DRM_FORMAT_MOD_NONE:
14197 case I915_FORMAT_MOD_X_TILED:
14198 break;
14199 default:
c0f40428
JB		 14200 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14201 mode_cmd->modifier[0]);
57cd6508 14202 return -EINVAL;
c16ed4be 14203 }
57cd6508 14204
b321803d
DL		 14205 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14206 mode_cmd->pixel_format);
14207 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14208 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14209 mode_cmd->pitches[0], stride_alignment);
57cd6508 14210 return -EINVAL;
c16ed4be 14211 }
57cd6508 14212
b321803d
DL		 14213 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14214 mode_cmd->pixel_format);
a35cdaa0 14215 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14216 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14217 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14218 "tiled" : "linear",
a35cdaa0 14219 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14220 return -EINVAL;
c16ed4be 14221 }
5d7bd705 14222
2a80eada 14223 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14224 mode_cmd->pitches[0] != obj->stride) {
14225 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14226 mode_cmd->pitches[0], obj->stride);
5d7bd705 14227 return -EINVAL;
c16ed4be 14228 }
5d7bd705 14229
57779d06 14230 /* Reject formats not supported by any plane early. */
308e5bcb 14231 switch (mode_cmd->pixel_format) {
57779d06 14232 case DRM_FORMAT_C8:
04b3924d
VS		 14233 case DRM_FORMAT_RGB565:
14234 case DRM_FORMAT_XRGB8888:
14235 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14236 break;
14237 case DRM_FORMAT_XRGB1555:
c16ed4be 14238 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14239 DRM_DEBUG("unsupported pixel format: %s\n",
14240 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14241 return -EINVAL;
c16ed4be 14242 }
57779d06 14243 break;
57779d06 14244 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14245 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14246 DRM_DEBUG("unsupported pixel format: %s\n",
14247 drm_get_format_name(mode_cmd->pixel_format));
14248 return -EINVAL;
14249 }
14250 break;
14251 case DRM_FORMAT_XBGR8888:
04b3924d 14252 case DRM_FORMAT_XRGB2101010:
57779d06 14253 case DRM_FORMAT_XBGR2101010:
c16ed4be 14254 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14255 DRM_DEBUG("unsupported pixel format: %s\n",
14256 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14257 return -EINVAL;
c16ed4be 14258 }
b5626747 14259 break;
7531208b
DL		 14260 case DRM_FORMAT_ABGR2101010:
14261 if (!IS_VALLEYVIEW(dev)) {
14262 DRM_DEBUG("unsupported pixel format: %s\n",
14263 drm_get_format_name(mode_cmd->pixel_format));
14264 return -EINVAL;
14265 }
14266 break;
04b3924d
VS		 14267 case DRM_FORMAT_YUYV:
14268 case DRM_FORMAT_UYVY:
14269 case DRM_FORMAT_YVYU:
14270 case DRM_FORMAT_VYUY:
c16ed4be 14271 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14272 DRM_DEBUG("unsupported pixel format: %s\n",
14273 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14274 return -EINVAL;
c16ed4be 14275 }
57cd6508
CW		 14276 break;
14277 default:
4ee62c76
VS		 14278 DRM_DEBUG("unsupported pixel format: %s\n",
14279 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14280 return -EINVAL;
14281 }
14282
90f9a336
VS		 14283 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14284 if (mode_cmd->offsets[0] != 0)
14285 return -EINVAL;
14286
ec2c981e 14287 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14288 mode_cmd->pixel_format,
14289 mode_cmd->modifier[0]);
53155c0a
DV		 14290 /* FIXME drm helper for size checks (especially planar formats)? */
14291 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14292 return -EINVAL;
14293
c7d73f6a
DV		 14294 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14295 intel_fb->obj = obj;
80075d49 14296 intel_fb->obj->framebuffer_references++;
c7d73f6a 14297
79e53945
JB		 14298 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14299 if (ret) {
14300 DRM_ERROR("framebuffer init failed %d\n", ret);
14301 return ret;
14302 }
14303
79e53945
JB		 14304 return 0;
14305}
14306
79e53945
JB		 14307static struct drm_framebuffer *
14308intel_user_framebuffer_create(struct drm_device *dev,
14309 struct drm_file *filp,
308e5bcb 14310 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14311{
05394f39 14312 struct drm_i915_gem_object *obj;
79e53945 14313
308e5bcb
JB		 14314 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14315 mode_cmd->handles[0]));
c8725226 14316 if (&obj->base == NULL)
cce13ff7 14317 return ERR_PTR(-ENOENT);
79e53945 14318
d2dff872 14319 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14320}
14321
4520f53a 14322#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14323static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14324{
14325}
14326#endif
14327
79e53945 14328static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14329 .fb_create = intel_user_framebuffer_create,
0632fef6 14330 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14331 .atomic_check = intel_atomic_check,
14332 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14333 .atomic_state_alloc = intel_atomic_state_alloc,
14334 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14335};
14336
e70236a8
JB		 14337/* Set up chip specific display functions */
14338static void intel_init_display(struct drm_device *dev)
14339{
14340 struct drm_i915_private *dev_priv = dev->dev_private;
14341
ee9300bb
DV		 14342 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14343 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14344 else if (IS_CHERRYVIEW(dev))
14345 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14346 else if (IS_VALLEYVIEW(dev))
14347 dev_priv->display.find_dpll = vlv_find_best_dpll;
14348 else if (IS_PINEVIEW(dev))
14349 dev_priv->display.find_dpll = pnv_find_best_dpll;
14350 else
14351 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14352
bc8d7dff
DL		 14353 if (INTEL_INFO(dev)->gen >= 9) {
14354 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14355 dev_priv->display.get_initial_plane_config =
14356 skylake_get_initial_plane_config;
bc8d7dff
DL		 14357 dev_priv->display.crtc_compute_clock =
14358 haswell_crtc_compute_clock;
14359 dev_priv->display.crtc_enable = haswell_crtc_enable;
14360 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14361 dev_priv->display.update_primary_plane =
14362 skylake_update_primary_plane;
14363 } else if (HAS_DDI(dev)) {
0e8ffe1b 14364 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14365 dev_priv->display.get_initial_plane_config =
14366 ironlake_get_initial_plane_config;
797d0259
ACO		 14367 dev_priv->display.crtc_compute_clock =
14368 haswell_crtc_compute_clock;
4f771f10
PZ		 14369 dev_priv->display.crtc_enable = haswell_crtc_enable;
14370 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14371 dev_priv->display.update_primary_plane =
14372 ironlake_update_primary_plane;
09b4ddf9 14373 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14374 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14375 dev_priv->display.get_initial_plane_config =
14376 ironlake_get_initial_plane_config;
3fb37703
ACO		 14377 dev_priv->display.crtc_compute_clock =
14378 ironlake_crtc_compute_clock;
76e5a89c
DV		 14379 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14380 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14381 dev_priv->display.update_primary_plane =
14382 ironlake_update_primary_plane;
89b667f8
JB		 14383 } else if (IS_VALLEYVIEW(dev)) {
14384 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14385 dev_priv->display.get_initial_plane_config =
14386 i9xx_get_initial_plane_config;
d6dfee7a 14387 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14388 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14389 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14390 dev_priv->display.update_primary_plane =
14391 i9xx_update_primary_plane;
f564048e 14392 } else {
0e8ffe1b 14393 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14394 dev_priv->display.get_initial_plane_config =
14395 i9xx_get_initial_plane_config;
d6dfee7a 14396 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14397 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14398 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14399 dev_priv->display.update_primary_plane =
14400 i9xx_update_primary_plane;
f564048e 14401 }
e70236a8 14402
e70236a8 14403 /* Returns the core display clock speed */
1652d19e
VS		 14404 if (IS_SKYLAKE(dev))
14405 dev_priv->display.get_display_clock_speed =
14406 skylake_get_display_clock_speed;
acd3f3d3
BP		 14407 else if (IS_BROXTON(dev))
14408 dev_priv->display.get_display_clock_speed =
14409 broxton_get_display_clock_speed;
1652d19e
VS		 14410 else if (IS_BROADWELL(dev))
14411 dev_priv->display.get_display_clock_speed =
14412 broadwell_get_display_clock_speed;
14413 else if (IS_HASWELL(dev))
14414 dev_priv->display.get_display_clock_speed =
14415 haswell_get_display_clock_speed;
14416 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14417 dev_priv->display.get_display_clock_speed =
14418 valleyview_get_display_clock_speed;
b37a6434
VS		 14419 else if (IS_GEN5(dev))
14420 dev_priv->display.get_display_clock_speed =
14421 ilk_get_display_clock_speed;
a7c66cd8 14422 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14423 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14424 dev_priv->display.get_display_clock_speed =
14425 i945_get_display_clock_speed;
34edce2f
VS		 14426 else if (IS_GM45(dev))
14427 dev_priv->display.get_display_clock_speed =
14428 gm45_get_display_clock_speed;
14429 else if (IS_CRESTLINE(dev))
14430 dev_priv->display.get_display_clock_speed =
14431 i965gm_get_display_clock_speed;
14432 else if (IS_PINEVIEW(dev))
14433 dev_priv->display.get_display_clock_speed =
14434 pnv_get_display_clock_speed;
14435 else if (IS_G33(dev) || IS_G4X(dev))
14436 dev_priv->display.get_display_clock_speed =
14437 g33_get_display_clock_speed;
e70236a8
JB		 14438 else if (IS_I915G(dev))
14439 dev_priv->display.get_display_clock_speed =
14440 i915_get_display_clock_speed;
257a7ffc 14441 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14442 dev_priv->display.get_display_clock_speed =
14443 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14444 else if (IS_PINEVIEW(dev))
14445 dev_priv->display.get_display_clock_speed =
14446 pnv_get_display_clock_speed;
e70236a8
JB		 14447 else if (IS_I915GM(dev))
14448 dev_priv->display.get_display_clock_speed =
14449 i915gm_get_display_clock_speed;
14450 else if (IS_I865G(dev))
14451 dev_priv->display.get_display_clock_speed =
14452 i865_get_display_clock_speed;
f0f8a9ce 14453 else if (IS_I85X(dev))
e70236a8 14454 dev_priv->display.get_display_clock_speed =
1b1d2716 14455 i85x_get_display_clock_speed;
623e01e5
VS		 14456 else { /* 830 */
14457 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14458 dev_priv->display.get_display_clock_speed =
14459 i830_get_display_clock_speed;
623e01e5 14460 }
e70236a8 14461
7c10a2b5 14462 if (IS_GEN5(dev)) {
3bb11b53 14463 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14464 } else if (IS_GEN6(dev)) {
14465 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14466 } else if (IS_IVYBRIDGE(dev)) {
14467 /* FIXME: detect B0+ stepping and use auto training */
14468 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14469 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14470 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14471 if (IS_BROADWELL(dev)) {
14472 dev_priv->display.modeset_commit_cdclk =
14473 broadwell_modeset_commit_cdclk;
14474 dev_priv->display.modeset_calc_cdclk =
14475 broadwell_modeset_calc_cdclk;
14476 }
30a970c6 14477 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14478 dev_priv->display.modeset_commit_cdclk =
14479 valleyview_modeset_commit_cdclk;
14480 dev_priv->display.modeset_calc_cdclk =
14481 valleyview_modeset_calc_cdclk;
f8437dd1 14482 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14483 dev_priv->display.modeset_commit_cdclk =
14484 broxton_modeset_commit_cdclk;
14485 dev_priv->display.modeset_calc_cdclk =
14486 broxton_modeset_calc_cdclk;
e70236a8 14487 }
8c9f3aaf 14488
8c9f3aaf
JB		 14489 switch (INTEL_INFO(dev)->gen) {
14490 case 2:
14491 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14492 break;
14493
14494 case 3:
14495 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14496 break;
14497
14498 case 4:
14499 case 5:
14500 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14501 break;
14502
14503 case 6:
14504 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14505 break;
7c9017e5 14506 case 7:
4e0bbc31 14507 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14508 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14509 break;
830c81db 14510 case 9:
ba343e02
TU		 14511 /* Drop through - unsupported since execlist only. */
14512 default:
14513 /* Default just returns -ENODEV to indicate unsupported */
14514 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14515 }
7bd688cd
JN		 14516
14517 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14518
14519 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14520}
14521
b690e96c
JB		 14522/*
14523 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14524 * resume, or other times. This quirk makes sure that's the case for
14525 * affected systems.
14526 */
0206e353 14527static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14528{
14529 struct drm_i915_private *dev_priv = dev->dev_private;
14530
14531 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14532 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14533}
14534
b6b5d049
VS		 14535static void quirk_pipeb_force(struct drm_device *dev)
14536{
14537 struct drm_i915_private *dev_priv = dev->dev_private;
14538
14539 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14540 DRM_INFO("applying pipe b force quirk\n");
14541}
14542
435793df
KP		 14543/*
14544 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14545 */
14546static void quirk_ssc_force_disable(struct drm_device *dev)
14547{
14548 struct drm_i915_private *dev_priv = dev->dev_private;
14549 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14550 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14551}
14552
4dca20ef 14553/*
5a15ab5b
CE		 14554 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14555 * brightness value
4dca20ef
CE		 14556 */
14557static void quirk_invert_brightness(struct drm_device *dev)
14558{
14559 struct drm_i915_private *dev_priv = dev->dev_private;
14560 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14561 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14562}
14563
9c72cc6f
SD		 14564/* Some VBT's incorrectly indicate no backlight is present */
14565static void quirk_backlight_present(struct drm_device *dev)
14566{
14567 struct drm_i915_private *dev_priv = dev->dev_private;
14568 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14569 DRM_INFO("applying backlight present quirk\n");
14570}
14571
b690e96c
JB		 14572struct intel_quirk {
14573 int device;
14574 int subsystem_vendor;
14575 int subsystem_device;
14576 void (*hook)(struct drm_device *dev);
14577};
14578
5f85f176
EE		 14579/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14580struct intel_dmi_quirk {
14581 void (*hook)(struct drm_device *dev);
14582 const struct dmi_system_id (*dmi_id_list)[];
14583};
14584
14585static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14586{
14587 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14588 return 1;
14589}
14590
14591static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14592 {
14593 .dmi_id_list = &(const struct dmi_system_id[]) {
14594 {
14595 .callback = intel_dmi_reverse_brightness,
14596 .ident = "NCR Corporation",
14597 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14598 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14599 },
14600 },
14601 { } /* terminating entry */
14602 },
14603 .hook = quirk_invert_brightness,
14604 },
14605};
14606
c43b5634 14607static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14608 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14609 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14610
b690e96c
JB		 14611 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14612 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14613
5f080c0f
VS		 14614 /* 830 needs to leave pipe A & dpll A up */
14615 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14616
b6b5d049
VS		 14617 /* 830 needs to leave pipe B & dpll B up */
14618 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14619
435793df
KP		 14620 /* Lenovo U160 cannot use SSC on LVDS */
14621 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14622
14623 /* Sony Vaio Y cannot use SSC on LVDS */
14624 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14625
be505f64
AH		 14626 /* Acer Aspire 5734Z must invert backlight brightness */
14627 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14628
14629 /* Acer/eMachines G725 */
14630 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14631
14632 /* Acer/eMachines e725 */
14633 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14634
14635 /* Acer/Packard Bell NCL20 */
14636 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14637
14638 /* Acer Aspire 4736Z */
14639 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14640
14641 /* Acer Aspire 5336 */
14642 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14643
14644 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14645 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14646
dfb3d47b
SD		 14647 /* Acer C720 Chromebook (Core i3 4005U) */
14648 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14649
b2a9601c 14650 /* Apple Macbook 2,1 (Core 2 T7400) */
14651 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14652
d4967d8c
SD		 14653 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14654 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14655
14656 /* HP Chromebook 14 (Celeron 2955U) */
14657 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14658
14659 /* Dell Chromebook 11 */
14660 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14661};
14662
14663static void intel_init_quirks(struct drm_device *dev)
14664{
14665 struct pci_dev *d = dev->pdev;
14666 int i;
14667
14668 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14669 struct intel_quirk *q = &intel_quirks[i];
14670
14671 if (d->device == q->device &&
14672 (d->subsystem_vendor == q->subsystem_vendor ||
14673 q->subsystem_vendor == PCI_ANY_ID) &&
14674 (d->subsystem_device == q->subsystem_device ||
14675 q->subsystem_device == PCI_ANY_ID))
14676 q->hook(dev);
14677 }
5f85f176
EE		 14678 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14679 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14680 intel_dmi_quirks[i].hook(dev);
14681 }
b690e96c
JB		 14682}
14683
9cce37f4
JB		 14684/* Disable the VGA plane that we never use */
14685static void i915_disable_vga(struct drm_device *dev)
14686{
14687 struct drm_i915_private *dev_priv = dev->dev_private;
14688 u8 sr1;
766aa1c4 14689 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14690
2b37c616 14691 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14692 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14693 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14694 sr1 = inb(VGA_SR_DATA);
14695 outb(sr1 | 1<<5, VGA_SR_DATA);
14696 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14697 udelay(300);
14698
01f5a626 14699 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14700 POSTING_READ(vga_reg);
14701}
14702
f817586c
DV		 14703void intel_modeset_init_hw(struct drm_device *dev)
14704{
b6283055 14705 intel_update_cdclk(dev);
a8f78b58 14706 intel_prepare_ddi(dev);
f817586c 14707 intel_init_clock_gating(dev);
8090c6b9 14708 intel_enable_gt_powersave(dev);
f817586c
DV		 14709}
14710
79e53945
JB		 14711void intel_modeset_init(struct drm_device *dev)
14712{
652c393a 14713 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14714 int sprite, ret;
8cc87b75 14715 enum pipe pipe;
46f297fb 14716 struct intel_crtc *crtc;
79e53945
JB		 14717
14718 drm_mode_config_init(dev);
14719
14720 dev->mode_config.min_width = 0;
14721 dev->mode_config.min_height = 0;
14722
019d96cb
DA		 14723 dev->mode_config.preferred_depth = 24;
14724 dev->mode_config.prefer_shadow = 1;
14725
25bab385
TU		 14726 dev->mode_config.allow_fb_modifiers = true;
14727
e6ecefaa 14728 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14729
b690e96c
JB		 14730 intel_init_quirks(dev);
14731
1fa61106
ED		 14732 intel_init_pm(dev);
14733
e3c74757
BW		 14734 if (INTEL_INFO(dev)->num_pipes == 0)
14735 return;
14736
e70236a8 14737 intel_init_display(dev);
7c10a2b5 14738 intel_init_audio(dev);
e70236a8 14739
a6c45cf0
CW		 14740 if (IS_GEN2(dev)) {
14741 dev->mode_config.max_width = 2048;
14742 dev->mode_config.max_height = 2048;
14743 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14744 dev->mode_config.max_width = 4096;
14745 dev->mode_config.max_height = 4096;
79e53945 14746 } else {
a6c45cf0
CW		 14747 dev->mode_config.max_width = 8192;
14748 dev->mode_config.max_height = 8192;
79e53945 14749 }
068be561 14750
dc41c154
VS		 14751 if (IS_845G(dev) || IS_I865G(dev)) {
14752 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14753 dev->mode_config.cursor_height = 1023;
14754 } else if (IS_GEN2(dev)) {
068be561
DL		 14755 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14756 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14757 } else {
14758 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14759 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14760 }
14761
5d4545ae 14762 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14763
28c97730 14764 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14765 INTEL_INFO(dev)->num_pipes,
14766 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14767
055e393f 14768 for_each_pipe(dev_priv, pipe) {
8cc87b75 14769 intel_crtc_init(dev, pipe);
3bdcfc0c 14770 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14771 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14772 if (ret)
06da8da2 14773 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14774 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14775 }
79e53945
JB		 14776 }
14777
f42bb70d
JB		 14778 intel_init_dpio(dev);
14779
e72f9fbf 14780 intel_shared_dpll_init(dev);
ee7b9f93 14781
9cce37f4
JB		 14782 /* Just disable it once at startup */
14783 i915_disable_vga(dev);
79e53945 14784 intel_setup_outputs(dev);
11be49eb
CW		 14785
14786 /* Just in case the BIOS is doing something questionable. */
7733b49b 14787 intel_fbc_disable(dev_priv);
fa9fa083 14788
6e9f798d 14789 drm_modeset_lock_all(dev);
043e9bda 14790 intel_modeset_setup_hw_state(dev);
6e9f798d 14791 drm_modeset_unlock_all(dev);
46f297fb 14792
d3fcc808 14793 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14794 struct intel_initial_plane_config plane_config = {};
14795
46f297fb
JB		 14796 if (!crtc->active)
14797 continue;
14798
46f297fb 14799 /*
46f297fb
JB		 14800 * Note that reserving the BIOS fb up front prevents us
14801 * from stuffing other stolen allocations like the ring
14802 * on top. This prevents some ugliness at boot time, and
14803 * can even allow for smooth boot transitions if the BIOS
14804 * fb is large enough for the active pipe configuration.
14805 */
eeebeac5
ML		 14806 dev_priv->display.get_initial_plane_config(crtc,
14807 &plane_config);
14808
14809 /*
14810 * If the fb is shared between multiple heads, we'll
14811 * just get the first one.
14812 */
14813 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14814 }
2c7111db
CW		 14815}
14816
7fad798e
DV		 14817static void intel_enable_pipe_a(struct drm_device *dev)
14818{
14819 struct intel_connector *connector;
14820 struct drm_connector *crt = NULL;
14821 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14822 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14823
14824 /* We can't just switch on the pipe A, we need to set things up with a
14825 * proper mode and output configuration. As a gross hack, enable pipe A
14826 * by enabling the load detect pipe once. */
3a3371ff 14827 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14828 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14829 crt = &connector->base;
14830 break;
14831 }
14832 }
14833
14834 if (!crt)
14835 return;
14836
208bf9fd 14837 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14838 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14839}
14840
fa555837
DV		 14841static bool
14842intel_check_plane_mapping(struct intel_crtc *crtc)
14843{
7eb552ae
BW		 14844 struct drm_device *dev = crtc->base.dev;
14845 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14846 u32 reg, val;
14847
7eb552ae 14848 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14849 return true;
14850
14851 reg = DSPCNTR(!crtc->plane);
14852 val = I915_READ(reg);
14853
14854 if ((val & DISPLAY_PLANE_ENABLE) &&
14855 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14856 return false;
14857
14858 return true;
14859}
14860
24929352
DV		 14861static void intel_sanitize_crtc(struct intel_crtc *crtc)
14862{
14863 struct drm_device *dev = crtc->base.dev;
14864 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 14865 struct intel_encoder *encoder;
fa555837 14866 u32 reg;
b17d48e2 14867 bool enable;
24929352 14868
24929352 14869 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14870 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14871 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14872
d3eaf884 14873 /* restore vblank interrupts to correct state */
9625604c 14874 drm_crtc_vblank_reset(&crtc->base);
d297e103 14875 if (crtc->active) {
3a03dfb0 14876 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14877 update_scanline_offset(crtc);
9625604c
DV		 14878 drm_crtc_vblank_on(&crtc->base);
14879 }
d3eaf884 14880
24929352 14881 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14882 * disable the crtc (and hence change the state) if it is wrong. Note
14883 * that gen4+ has a fixed plane -> pipe mapping. */
14884 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14885 bool plane;
14886
24929352
DV		 14887 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14888 crtc->base.base.id);
14889
14890 /* Pipe has the wrong plane attached and the plane is active.
14891 * Temporarily change the plane mapping and disable everything
14892 * ... */
14893 plane = crtc->plane;
b70709a6 14894 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14895 crtc->plane = !plane;
b17d48e2 14896 intel_crtc_disable_noatomic(&crtc->base);
24929352 14897 crtc->plane = plane;
24929352 14898 }
24929352 14899
7fad798e
DV		 14900 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14901 crtc->pipe == PIPE_A && !crtc->active) {
14902 /* BIOS forgot to enable pipe A, this mostly happens after
14903 * resume. Force-enable the pipe to fix this, the update_dpms
14904 * call below we restore the pipe to the right state, but leave
14905 * the required bits on. */
14906 intel_enable_pipe_a(dev);
14907 }
14908
24929352
DV		 14909 /* Adjust the state of the output pipe according to whether we
14910 * have active connectors/encoders. */
b17d48e2 14911 enable = false;
873ffe69
ML		 14912 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14913 enable = true;
14914 break;
14915 }
24929352 14916
b17d48e2
ML		 14917 if (!enable)
14918 intel_crtc_disable_noatomic(&crtc->base);
24929352 14919
53d9f4e9 14920 if (crtc->active != crtc->base.state->active) {
24929352
DV		 14921
14922 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14923 * functions or because of calls to intel_crtc_disable_noatomic,
14924 * or because the pipe is force-enabled due to the
24929352
DV		 14925 * pipe A quirk. */
14926 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14927 crtc->base.base.id,
83d65738 14928 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14929 crtc->active ? "enabled" : "disabled");
14930
4be40c98 14931 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14932 crtc->base.state->active = crtc->active;
24929352
DV		 14933 crtc->base.enabled = crtc->active;
14934
14935 /* Because we only establish the connector -> encoder ->
14936 * crtc links if something is active, this means the
14937 * crtc is now deactivated. Break the links. connector
14938 * -> encoder links are only establish when things are
14939 * actually up, hence no need to break them. */
14940 WARN_ON(crtc->active);
14941
2d406bb0 14942 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14943 encoder->base.crtc = NULL;
24929352 14944 }
c5ab3bc0 14945
a3ed6aad 14946 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14947 /*
14948 * We start out with underrun reporting disabled to avoid races.
14949 * For correct bookkeeping mark this on active crtcs.
14950 *
c5ab3bc0
DV		 14951 * Also on gmch platforms we dont have any hardware bits to
14952 * disable the underrun reporting. Which means we need to start
14953 * out with underrun reporting disabled also on inactive pipes,
14954 * since otherwise we'll complain about the garbage we read when
14955 * e.g. coming up after runtime pm.
14956 *
4cc31489
DV		 14957 * No protection against concurrent access is required - at
14958 * worst a fifo underrun happens which also sets this to false.
14959 */
14960 crtc->cpu_fifo_underrun_disabled = true;
14961 crtc->pch_fifo_underrun_disabled = true;
14962 }
24929352
DV		 14963}
14964
14965static void intel_sanitize_encoder(struct intel_encoder *encoder)
14966{
14967 struct intel_connector *connector;
14968 struct drm_device *dev = encoder->base.dev;
873ffe69 14969 bool active = false;
24929352
DV		 14970
14971 /* We need to check both for a crtc link (meaning that the
14972 * encoder is active and trying to read from a pipe) and the
14973 * pipe itself being active. */
14974 bool has_active_crtc = encoder->base.crtc &&
14975 to_intel_crtc(encoder->base.crtc)->active;
14976
873ffe69
ML		 14977 for_each_intel_connector(dev, connector) {
14978 if (connector->base.encoder != &encoder->base)
14979 continue;
14980
14981 active = true;
14982 break;
14983 }
14984
14985 if (active && !has_active_crtc) {
24929352
DV		 14986 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14987 encoder->base.base.id,
8e329a03 14988 encoder->base.name);
24929352
DV		 14989
14990 /* Connector is active, but has no active pipe. This is
14991 * fallout from our resume register restoring. Disable
14992 * the encoder manually again. */
14993 if (encoder->base.crtc) {
14994 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14995 encoder->base.base.id,
8e329a03 14996 encoder->base.name);
24929352 14997 encoder->disable(encoder);
a62d1497
VS		 14998 if (encoder->post_disable)
14999 encoder->post_disable(encoder);
24929352 15000 }
7f1950fb 15001 encoder->base.crtc = NULL;
24929352
DV		 15002
15003 /* Inconsistent output/port/pipe state happens presumably due to
15004 * a bug in one of the get_hw_state functions. Or someplace else
15005 * in our code, like the register restore mess on resume. Clamp
15006 * things to off as a safer default. */
3a3371ff 15007 for_each_intel_connector(dev, connector) {
24929352
DV		 15008 if (connector->encoder != encoder)
15009 continue;
7f1950fb
EE		 15010 connector->base.dpms = DRM_MODE_DPMS_OFF;
15011 connector->base.encoder = NULL;
24929352
DV		 15012 }
15013 }
15014 /* Enabled encoders without active connectors will be fixed in
15015 * the crtc fixup. */
15016}
15017
04098753 15018void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15019{
15020 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15021 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15022
04098753
ID		 15023 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15024 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15025 i915_disable_vga(dev);
15026 }
15027}
15028
15029void i915_redisable_vga(struct drm_device *dev)
15030{
15031 struct drm_i915_private *dev_priv = dev->dev_private;
15032
8dc8a27c
PZ		 15033 /* This function can be called both from intel_modeset_setup_hw_state or
15034 * at a very early point in our resume sequence, where the power well
15035 * structures are not yet restored. Since this function is at a very
15036 * paranoid "someone might have enabled VGA while we were not looking"
15037 * level, just check if the power well is enabled instead of trying to
15038 * follow the "don't touch the power well if we don't need it" policy
15039 * the rest of the driver uses. */
f458ebbc 15040 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15041 return;
15042
04098753 15043 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15044}
15045
98ec7739
VS		 15046static bool primary_get_hw_state(struct intel_crtc *crtc)
15047{
15048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15049
d032ffa0
ML		 15050 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15051}
15052
15053static void readout_plane_state(struct intel_crtc *crtc,
15054 struct intel_crtc_state *crtc_state)
15055{
15056 struct intel_plane *p;
4cf0ebbd 15057 struct intel_plane_state *plane_state;
d032ffa0
ML		 15058 bool active = crtc_state->base.active;
15059
d032ffa0 15060 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15061 if (crtc->pipe != p->pipe)
15062 continue;
15063
4cf0ebbd 15064 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15065
4cf0ebbd
ML		 15066 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15067 plane_state->visible = primary_get_hw_state(crtc);
15068 else {
15069 if (active)
15070 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15071
4cf0ebbd 15072 plane_state->visible = false;
d032ffa0
ML		 15073 }
15074 }
98ec7739
VS		 15075}
15076
30e984df 15077static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15078{
15079 struct drm_i915_private *dev_priv = dev->dev_private;
15080 enum pipe pipe;
24929352
DV		 15081 struct intel_crtc *crtc;
15082 struct intel_encoder *encoder;
15083 struct intel_connector *connector;
5358901f 15084 int i;
24929352 15085
d3fcc808 15086 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15087 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15088 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15089 crtc->config->base.crtc = &crtc->base;
3b117c8f 15090
0e8ffe1b 15091 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15092 crtc->config);
24929352 15093
49d6fa21 15094 crtc->base.state->active = crtc->active;
24929352 15095 crtc->base.enabled = crtc->active;
b70709a6 15096
5c1e3426
ML		 15097 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15098 if (crtc->base.state->active) {
15099 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15100 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15101 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15102
15103 /*
15104 * The initial mode needs to be set in order to keep
15105 * the atomic core happy. It wants a valid mode if the
15106 * crtc's enabled, so we do the above call.
15107 *
15108 * At this point some state updated by the connectors
15109 * in their ->detect() callback has not run yet, so
15110 * no recalculation can be done yet.
15111 *
15112 * Even if we could do a recalculation and modeset
15113 * right now it would cause a double modeset if
15114 * fbdev or userspace chooses a different initial mode.
15115 *
5c1e3426
ML		 15116 * If that happens, someone indicated they wanted a
15117 * mode change, which means it's safe to do a full
15118 * recalculation.
15119 */
1ed51de9 15120 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15121 }
15122
15123 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15124 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15125
15126 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15127 crtc->base.base.id,
15128 crtc->active ? "enabled" : "disabled");
15129 }
15130
5358901f
DV		 15131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15132 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15133
3e369b76
ACO		 15134 pll->on = pll->get_hw_state(dev_priv, pll,
15135 &pll->config.hw_state);
5358901f 15136 pll->active = 0;
3e369b76 15137 pll->config.crtc_mask = 0;
d3fcc808 15138 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15139 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15140 pll->active++;
3e369b76 15141 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15142 }
5358901f 15143 }
5358901f 15144
1e6f2ddc 15145 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15146 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15147
3e369b76 15148 if (pll->config.crtc_mask)
bd2bb1b9 15149 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15150 }
15151
b2784e15 15152 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15153 pipe = 0;
15154
15155 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15156 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15157 encoder->base.crtc = &crtc->base;
6e3c9717 15158 encoder->get_config(encoder, crtc->config);
24929352
DV		 15159 } else {
15160 encoder->base.crtc = NULL;
15161 }
15162
6f2bcceb 15163 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15164 encoder->base.base.id,
8e329a03 15165 encoder->base.name,
24929352 15166 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15167 pipe_name(pipe));
24929352
DV		 15168 }
15169
3a3371ff 15170 for_each_intel_connector(dev, connector) {
24929352
DV		 15171 if (connector->get_hw_state(connector)) {
15172 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15173 connector->base.encoder = &connector->encoder->base;
15174 } else {
15175 connector->base.dpms = DRM_MODE_DPMS_OFF;
15176 connector->base.encoder = NULL;
15177 }
15178 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15179 connector->base.base.id,
c23cc417 15180 connector->base.name,
24929352
DV		 15181 connector->base.encoder ? "enabled" : "disabled");
15182 }
30e984df
DV		 15183}
15184
043e9bda
ML		 15185/* Scan out the current hw modeset state,
15186 * and sanitizes it to the current state
15187 */
15188static void
15189intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15190{
15191 struct drm_i915_private *dev_priv = dev->dev_private;
15192 enum pipe pipe;
30e984df
DV		 15193 struct intel_crtc *crtc;
15194 struct intel_encoder *encoder;
35c95375 15195 int i;
30e984df
DV		 15196
15197 intel_modeset_readout_hw_state(dev);
24929352
DV		 15198
15199 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15200 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15201 intel_sanitize_encoder(encoder);
15202 }
15203
055e393f 15204 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15205 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15206 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15207 intel_dump_pipe_config(crtc, crtc->config,
15208 "[setup_hw_state]");
24929352 15209 }
9a935856 15210
d29b2f9d
ACO		 15211 intel_modeset_update_connector_atomic_state(dev);
15212
35c95375
DV		 15213 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15214 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15215
15216 if (!pll->on || pll->active)
15217 continue;
15218
15219 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15220
15221 pll->disable(dev_priv, pll);
15222 pll->on = false;
15223 }
15224
26e1fe4f 15225 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15226 vlv_wm_get_hw_state(dev);
15227 else if (IS_GEN9(dev))
3078999f
PB		 15228 skl_wm_get_hw_state(dev);
15229 else if (HAS_PCH_SPLIT(dev))
243e6a44 15230 ilk_wm_get_hw_state(dev);
292b990e
ML		 15231
15232 for_each_intel_crtc(dev, crtc) {
15233 unsigned long put_domains;
15234
15235 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15236 if (WARN_ON(put_domains))
15237 modeset_put_power_domains(dev_priv, put_domains);
15238 }
15239 intel_display_set_init_power(dev_priv, false);
043e9bda 15240}
7d0bc1ea 15241
043e9bda
ML		 15242void intel_display_resume(struct drm_device *dev)
15243{
15244 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15245 struct intel_connector *conn;
15246 struct intel_plane *plane;
15247 struct drm_crtc *crtc;
15248 int ret;
f30da187 15249
043e9bda
ML		 15250 if (!state)
15251 return;
15252
15253 state->acquire_ctx = dev->mode_config.acquire_ctx;
15254
15255 /* preserve complete old state, including dpll */
15256 intel_atomic_get_shared_dpll_state(state);
15257
15258 for_each_crtc(dev, crtc) {
15259 struct drm_crtc_state *crtc_state =
15260 drm_atomic_get_crtc_state(state, crtc);
15261
15262 ret = PTR_ERR_OR_ZERO(crtc_state);
15263 if (ret)
15264 goto err;
15265
15266 /* force a restore */
15267 crtc_state->mode_changed = true;
45e2b5f6 15268 }
8af6cf88 15269
043e9bda
ML		 15270 for_each_intel_plane(dev, plane) {
15271 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15272 if (ret)
15273 goto err;
15274 }
15275
15276 for_each_intel_connector(dev, conn) {
15277 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15278 if (ret)
15279 goto err;
15280 }
15281
15282 intel_modeset_setup_hw_state(dev);
15283
15284 i915_redisable_vga(dev);
74c090b1 15285 ret = drm_atomic_commit(state);
043e9bda
ML		 15286 if (!ret)
15287 return;
15288
15289err:
15290 DRM_ERROR("Restoring old state failed with %i\n", ret);
15291 drm_atomic_state_free(state);
2c7111db
CW		 15292}
15293
15294void intel_modeset_gem_init(struct drm_device *dev)
15295{
92122789 15296 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15297 struct drm_crtc *c;
2ff8fde1 15298 struct drm_i915_gem_object *obj;
e0d6149b 15299 int ret;
484b41dd 15300
ae48434c
ID		 15301 mutex_lock(&dev->struct_mutex);
15302 intel_init_gt_powersave(dev);
15303 mutex_unlock(&dev->struct_mutex);
15304
92122789
JB		 15305 /*
15306 * There may be no VBT; and if the BIOS enabled SSC we can
15307 * just keep using it to avoid unnecessary flicker. Whereas if the
15308 * BIOS isn't using it, don't assume it will work even if the VBT
15309 * indicates as much.
15310 */
15311 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15312 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15313 DREF_SSC1_ENABLE);
15314
1833b134 15315 intel_modeset_init_hw(dev);
02e792fb
DV		 15316
15317 intel_setup_overlay(dev);
484b41dd
JB		 15318
15319 /*
15320 * Make sure any fbs we allocated at startup are properly
15321 * pinned & fenced. When we do the allocation it's too early
15322 * for this.
15323 */
70e1e0ec 15324 for_each_crtc(dev, c) {
2ff8fde1
MR		 15325 obj = intel_fb_obj(c->primary->fb);
15326 if (obj == NULL)
484b41dd
JB		 15327 continue;
15328
e0d6149b
TU		 15329 mutex_lock(&dev->struct_mutex);
15330 ret = intel_pin_and_fence_fb_obj(c->primary,
15331 c->primary->fb,
15332 c->primary->state,
91af127f 15333 NULL, NULL);
e0d6149b
TU		 15334 mutex_unlock(&dev->struct_mutex);
15335 if (ret) {
484b41dd
JB		 15336 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15337 to_intel_crtc(c)->pipe);
66e514c1
DA		 15338 drm_framebuffer_unreference(c->primary->fb);
15339 c->primary->fb = NULL;
36750f28 15340 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15341 update_state_fb(c->primary);
36750f28 15342 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15343 }
15344 }
0962c3c9
VS		 15345
15346 intel_backlight_register(dev);
79e53945
JB		 15347}
15348
4932e2c3
ID		 15349void intel_connector_unregister(struct intel_connector *intel_connector)
15350{
15351 struct drm_connector *connector = &intel_connector->base;
15352
15353 intel_panel_destroy_backlight(connector);
34ea3d38 15354 drm_connector_unregister(connector);
4932e2c3
ID		 15355}
15356
79e53945
JB		 15357void intel_modeset_cleanup(struct drm_device *dev)
15358{
652c393a 15359 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15360 struct drm_connector *connector;
652c393a 15361
2eb5252e
ID		 15362 intel_disable_gt_powersave(dev);
15363
0962c3c9
VS		 15364 intel_backlight_unregister(dev);
15365
fd0c0642
DV		 15366 /*
15367 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15368 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15369 * experience fancy races otherwise.
15370 */
2aeb7d3a 15371 intel_irq_uninstall(dev_priv);
eb21b92b 15372
fd0c0642
DV		 15373 /*
15374 * Due to the hpd irq storm handling the hotplug work can re-arm the
15375 * poll handlers. Hence disable polling after hpd handling is shut down.
15376 */
f87ea761 15377 drm_kms_helper_poll_fini(dev);
fd0c0642 15378
723bfd70
JB		 15379 intel_unregister_dsm_handler();
15380
7733b49b 15381 intel_fbc_disable(dev_priv);
69341a5e 15382
1630fe75
CW		 15383 /* flush any delayed tasks or pending work */
15384 flush_scheduled_work();
15385
db31af1d
JN		 15386 /* destroy the backlight and sysfs files before encoders/connectors */
15387 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15388 struct intel_connector *intel_connector;
15389
15390 intel_connector = to_intel_connector(connector);
15391 intel_connector->unregister(intel_connector);
db31af1d 15392 }
d9255d57 15393
79e53945 15394 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15395
15396 intel_cleanup_overlay(dev);
ae48434c
ID		 15397
15398 mutex_lock(&dev->struct_mutex);
15399 intel_cleanup_gt_powersave(dev);
15400 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15401}
15402
f1c79df3
ZW		 15403/*
15404 * Return which encoder is currently attached for connector.
15405 */
df0e9248 15406struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15407{
df0e9248
CW		 15408 return &intel_attached_encoder(connector)->base;
15409}
f1c79df3 15410
df0e9248
CW		 15411void intel_connector_attach_encoder(struct intel_connector *connector,
15412 struct intel_encoder *encoder)
15413{
15414 connector->encoder = encoder;
15415 drm_mode_connector_attach_encoder(&connector->base,
15416 &encoder->base);
79e53945 15417}
28d52043
DA		 15418
15419/*
15420 * set vga decode state - true == enable VGA decode
15421 */
15422int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15423{
15424 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15425 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15426 u16 gmch_ctrl;
15427
75fa041d
CW		 15428 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15429 DRM_ERROR("failed to read control word\n");
15430 return -EIO;
15431 }
15432
c0cc8a55
CW		 15433 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15434 return 0;
15435
28d52043
DA		 15436 if (state)
15437 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15438 else
15439 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15440
15441 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15442 DRM_ERROR("failed to write control word\n");
15443 return -EIO;
15444 }
15445
28d52043
DA		 15446 return 0;
15447}
c4a1d9e4 15448
c4a1d9e4 15449struct intel_display_error_state {
ff57f1b0
PZ		 15450
15451 u32 power_well_driver;
15452
63b66e5b
CW		 15453 int num_transcoders;
15454
c4a1d9e4
CW		 15455 struct intel_cursor_error_state {
15456 u32 control;
15457 u32 position;
15458 u32 base;
15459 u32 size;
52331309 15460 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15461
15462 struct intel_pipe_error_state {
ddf9c536 15463 bool power_domain_on;
c4a1d9e4 15464 u32 source;
f301b1e1 15465 u32 stat;
52331309 15466 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15467
15468 struct intel_plane_error_state {
15469 u32 control;
15470 u32 stride;
15471 u32 size;
15472 u32 pos;
15473 u32 addr;
15474 u32 surface;
15475 u32 tile_offset;
52331309 15476 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15477
15478 struct intel_transcoder_error_state {
ddf9c536 15479 bool power_domain_on;
63b66e5b
CW		 15480 enum transcoder cpu_transcoder;
15481
15482 u32 conf;
15483
15484 u32 htotal;
15485 u32 hblank;
15486 u32 hsync;
15487 u32 vtotal;
15488 u32 vblank;
15489 u32 vsync;
15490 } transcoder[4];
c4a1d9e4
CW		 15491};
15492
15493struct intel_display_error_state *
15494intel_display_capture_error_state(struct drm_device *dev)
15495{
fbee40df 15496 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15497 struct intel_display_error_state *error;
63b66e5b
CW		 15498 int transcoders[] = {
15499 TRANSCODER_A,
15500 TRANSCODER_B,
15501 TRANSCODER_C,
15502 TRANSCODER_EDP,
15503 };
c4a1d9e4
CW		 15504 int i;
15505
63b66e5b
CW		 15506 if (INTEL_INFO(dev)->num_pipes == 0)
15507 return NULL;
15508
9d1cb914 15509 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15510 if (error == NULL)
15511 return NULL;
15512
190be112 15513 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15514 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15515
055e393f 15516 for_each_pipe(dev_priv, i) {
ddf9c536 15517 error->pipe[i].power_domain_on =
f458ebbc
DV		 15518 __intel_display_power_is_enabled(dev_priv,
15519 POWER_DOMAIN_PIPE(i));
ddf9c536 15520 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15521 continue;
15522
5efb3e28
VS		 15523 error->cursor[i].control = I915_READ(CURCNTR(i));
15524 error->cursor[i].position = I915_READ(CURPOS(i));
15525 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15526
15527 error->plane[i].control = I915_READ(DSPCNTR(i));
15528 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15529 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15530 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15531 error->plane[i].pos = I915_READ(DSPPOS(i));
15532 }
ca291363
PZ		 15533 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15534 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15535 if (INTEL_INFO(dev)->gen >= 4) {
15536 error->plane[i].surface = I915_READ(DSPSURF(i));
15537 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15538 }
15539
c4a1d9e4 15540 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15541
3abfce77 15542 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15543 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15544 }
15545
15546 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15547 if (HAS_DDI(dev_priv->dev))
15548 error->num_transcoders++; /* Account for eDP. */
15549
15550 for (i = 0; i < error->num_transcoders; i++) {
15551 enum transcoder cpu_transcoder = transcoders[i];
15552
ddf9c536 15553 error->transcoder[i].power_domain_on =
f458ebbc 15554 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15555 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15556 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15557 continue;
15558
63b66e5b
CW		 15559 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15560
15561 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15562 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15563 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15564 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15565 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15566 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15567 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15568 }
15569
15570 return error;
15571}
15572
edc3d884
MK		 15573#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15574
c4a1d9e4 15575void
edc3d884 15576intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15577 struct drm_device *dev,
15578 struct intel_display_error_state *error)
15579{
055e393f 15580 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15581 int i;
15582
63b66e5b
CW		 15583 if (!error)
15584 return;
15585
edc3d884 15586 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15587 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15588 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15589 error->power_well_driver);
055e393f 15590 for_each_pipe(dev_priv, i) {
edc3d884 15591 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15592 err_printf(m, " Power: %s\n",
15593 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15594 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15595 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15596
15597 err_printf(m, "Plane [%d]:\n", i);
15598 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15599 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15600 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15601 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15602 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15603 }
4b71a570 15604 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15605 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15606 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15607 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15608 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15609 }
15610
edc3d884
MK		 15611 err_printf(m, "Cursor [%d]:\n", i);
15612 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15613 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15614 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15615 }
63b66e5b
CW		 15616
15617 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15618 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15619 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15620 err_printf(m, " Power: %s\n",
15621 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15622 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15623 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15624 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15625 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15626 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15627 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15628 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15629 }
c4a1d9e4 15630}
e2fcdaa9
VS		 15631
15632void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15633{
15634 struct intel_crtc *crtc;
15635
15636 for_each_intel_crtc(dev, crtc) {
15637 struct intel_unpin_work *work;
e2fcdaa9 15638
5e2d7afc 15639 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15640
15641 work = crtc->unpin_work;
15642
15643 if (work && work->event &&
15644 work->event->base.file_priv == file) {
15645 kfree(work->event);
15646 work->event = NULL;
15647 }
15648
5e2d7afc 15649 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15650 }
15651}
Linux kernel - Deliverables
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