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drm/i915: rename INSTDONE1 to GEN4_INSTDONE1
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179
JB		 1159{
1160 int reg;
1161 u32 val;
1162 bool cur_state;
1163
1164 reg = DPLL(pipe);
1165 val = I915_READ(reg);
1166 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1167 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1168 "PLL state assertion failure (expected %s, current %s)\n",
1169 state_string(state), state_string(cur_state));
1170}
b24e7179 1171
23538ef1
JN		 1172/* XXX: the dsi pll is shared between MIPI DSI ports */
1173static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174{
1175 u32 val;
1176 bool cur_state;
1177
a580516d 1178 mutex_lock(&dev_priv->sb_lock);
23538ef1 1179 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1180 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1181
1182 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1183 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1184 "DSI PLL state assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186}
1187#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
55607e8a 1190struct intel_shared_dpll *
e2b78267
DV		 1191intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192{
1193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
6e3c9717 1195 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1196 return NULL;
1197
6e3c9717 1198 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1199}
1200
040484af 1201/* For ILK+ */
55607e8a
DV		 1202void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203 struct intel_shared_dpll *pll,
1204 bool state)
040484af 1205{
040484af 1206 bool cur_state;
5358901f 1207 struct intel_dpll_hw_state hw_state;
040484af 1208
92b27b08 1209 if (WARN (!pll,
46edb027 1210 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1211 return;
ee7b9f93 1212
5358901f 1213 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1214 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1215 "%s assertion failure (expected %s, current %s)\n",
1216 pll->name, state_string(state), state_string(cur_state));
040484af 1217}
040484af
JB		 1218
1219static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221{
1222 int reg;
1223 u32 val;
1224 bool cur_state;
ad80a810
PZ		 1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
040484af 1227
affa9354
PZ		 1228 if (HAS_DDI(dev_priv->dev)) {
1229 /* DDI does not have a specific FDI_TX register */
ad80a810 1230 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1231 val = I915_READ(reg);
ad80a810 1232 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1233 } else {
1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & FDI_TX_ENABLE);
1237 }
e2c719b7 1238 I915_STATE_WARN(cur_state != state,
040484af
JB		 1239 "FDI TX state assertion failure (expected %s, current %s)\n",
1240 state_string(state), state_string(cur_state));
1241}
1242#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1243#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1244
1245static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247{
1248 int reg;
1249 u32 val;
1250 bool cur_state;
1251
d63fa0dc
PZ		 1252 reg = FDI_RX_CTL(pipe);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1255 I915_STATE_WARN(cur_state != state,
040484af
JB		 1256 "FDI RX state assertion failure (expected %s, current %s)\n",
1257 state_string(state), state_string(cur_state));
1258}
1259#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1260#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1261
1262static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg;
1266 u32 val;
1267
1268 /* ILK FDI PLL is always enabled */
3d13ef2e 1269 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1270 return;
1271
bf507ef7 1272 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1273 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1274 return;
1275
040484af
JB		 1276 reg = FDI_TX_CTL(pipe);
1277 val = I915_READ(reg);
e2c719b7 1278 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1279}
1280
55607e8a
DV		 1281void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1282 enum pipe pipe, bool state)
040484af
JB		 1283{
1284 int reg;
1285 u32 val;
55607e8a 1286 bool cur_state;
040484af
JB		 1287
1288 reg = FDI_RX_CTL(pipe);
1289 val = I915_READ(reg);
55607e8a 1290 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1291 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1292 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1293 state_string(state), state_string(cur_state));
040484af
JB		 1294}
1295
b680c37a
DV		 1296void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1297 enum pipe pipe)
ea0760cf 1298{
bedd4dba
JN		 1299 struct drm_device *dev = dev_priv->dev;
1300 int pp_reg;
ea0760cf
JB		 1301 u32 val;
1302 enum pipe panel_pipe = PIPE_A;
0de3b485 1303 bool locked = true;
ea0760cf 1304
bedd4dba
JN		 1305 if (WARN_ON(HAS_DDI(dev)))
1306 return;
1307
1308 if (HAS_PCH_SPLIT(dev)) {
1309 u32 port_sel;
1310
ea0760cf 1311 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1312 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1313
1314 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1315 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1316 panel_pipe = PIPE_B;
1317 /* XXX: else fix for eDP */
1318 } else if (IS_VALLEYVIEW(dev)) {
1319 /* presumably write lock depends on pipe, not port select */
1320 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1321 panel_pipe = pipe;
ea0760cf
JB		 1322 } else {
1323 pp_reg = PP_CONTROL;
bedd4dba
JN		 1324 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1325 panel_pipe = PIPE_B;
ea0760cf
JB		 1326 }
1327
1328 val = I915_READ(pp_reg);
1329 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1330 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1331 locked = false;
1332
e2c719b7 1333 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1334 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1335 pipe_name(pipe));
ea0760cf
JB		 1336}
1337
93ce0ba6
JN		 1338static void assert_cursor(struct drm_i915_private *dev_priv,
1339 enum pipe pipe, bool state)
1340{
1341 struct drm_device *dev = dev_priv->dev;
1342 bool cur_state;
1343
d9d82081 1344 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1345 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1346 else
5efb3e28 1347 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1348
e2c719b7 1349 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1350 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1351 pipe_name(pipe), state_string(state), state_string(cur_state));
1352}
1353#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1354#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1355
b840d907
JB		 1356void assert_pipe(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, bool state)
b24e7179
JB		 1358{
1359 int reg;
1360 u32 val;
63d7bbe9 1361 bool cur_state;
702e7a56
PZ		 1362 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1363 pipe);
b24e7179 1364
b6b5d049
VS		 1365 /* if we need the pipe quirk it must be always on */
1366 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1367 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1368 state = true;
1369
f458ebbc 1370 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1371 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1372 cur_state = false;
1373 } else {
1374 reg = PIPECONF(cpu_transcoder);
1375 val = I915_READ(reg);
1376 cur_state = !!(val & PIPECONF_ENABLE);
1377 }
1378
e2c719b7 1379 I915_STATE_WARN(cur_state != state,
63d7bbe9 1380 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1381 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1382}
1383
931872fc
CW		 1384static void assert_plane(struct drm_i915_private *dev_priv,
1385 enum plane plane, bool state)
b24e7179
JB		 1386{
1387 int reg;
1388 u32 val;
931872fc 1389 bool cur_state;
b24e7179
JB		 1390
1391 reg = DSPCNTR(plane);
1392 val = I915_READ(reg);
931872fc 1393 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1394 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1395 "plane %c assertion failure (expected %s, current %s)\n",
1396 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1397}
1398
931872fc
CW		 1399#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1400#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1401
b24e7179
JB		 1402static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404{
653e1026 1405 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1406 int reg, i;
1407 u32 val;
1408 int cur_pipe;
1409
653e1026
VS		 1410 /* Primary planes are fixed to pipes on gen4+ */
1411 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1412 reg = DSPCNTR(pipe);
1413 val = I915_READ(reg);
e2c719b7 1414 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1415 "plane %c assertion failure, should be disabled but not\n",
1416 plane_name(pipe));
19ec1358 1417 return;
28c05794 1418 }
19ec1358 1419
b24e7179 1420 /* Need to check both planes against the pipe */
055e393f 1421 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1422 reg = DSPCNTR(i);
1423 val = I915_READ(reg);
1424 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1425 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1426 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1427 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1428 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1429 }
1430}
1431
19332d7a
JB		 1432static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
20674eef 1435 struct drm_device *dev = dev_priv->dev;
1fe47785 1436 int reg, sprite;
19332d7a
JB		 1437 u32 val;
1438
7feb8b88 1439 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1440 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1441 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1442 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1443 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1444 sprite, pipe_name(pipe));
1445 }
1446 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1447 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1448 reg = SPCNTR(pipe, sprite);
20674eef 1449 val = I915_READ(reg);
e2c719b7 1450 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1451 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1452 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1453 }
1454 } else if (INTEL_INFO(dev)->gen >= 7) {
1455 reg = SPRCTL(pipe);
19332d7a 1456 val = I915_READ(reg);
e2c719b7 1457 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1458 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1459 plane_name(pipe), pipe_name(pipe));
1460 } else if (INTEL_INFO(dev)->gen >= 5) {
1461 reg = DVSCNTR(pipe);
19332d7a 1462 val = I915_READ(reg);
e2c719b7 1463 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1464 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1465 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1466 }
1467}
1468
08c71e5e
VS		 1469static void assert_vblank_disabled(struct drm_crtc *crtc)
1470{
e2c719b7 1471 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1472 drm_crtc_vblank_put(crtc);
1473}
1474
89eff4be 1475static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1476{
1477 u32 val;
1478 bool enabled;
1479
e2c719b7 1480 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1481
92f2584a
JB		 1482 val = I915_READ(PCH_DREF_CONTROL);
1483 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1484 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1485 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1486}
1487
ab9412ba
DV		 1488static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1489 enum pipe pipe)
92f2584a
JB		 1490{
1491 int reg;
1492 u32 val;
1493 bool enabled;
1494
ab9412ba 1495 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1496 val = I915_READ(reg);
1497 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1498 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1499 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1500 pipe_name(pipe));
92f2584a
JB		 1501}
1502
4e634389
KP		 1503static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1504 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1505{
1506 if ((val & DP_PORT_EN) == 0)
1507 return false;
1508
1509 if (HAS_PCH_CPT(dev_priv->dev)) {
1510 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1511 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1512 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1513 return false;
44f37d1f
CML		 1514 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1515 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1516 return false;
f0575e92
KP		 1517 } else {
1518 if ((val & DP_PIPE_MASK) != (pipe << 30))
1519 return false;
1520 }
1521 return true;
1522}
1523
1519b995
KP		 1524static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
dc0fa718 1527 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1528 return false;
1529
1530 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1531 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1532 return false;
44f37d1f
CML		 1533 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1534 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1535 return false;
1519b995 1536 } else {
dc0fa718 1537 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1538 return false;
1539 }
1540 return true;
1541}
1542
1543static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1544 enum pipe pipe, u32 val)
1545{
1546 if ((val & LVDS_PORT_EN) == 0)
1547 return false;
1548
1549 if (HAS_PCH_CPT(dev_priv->dev)) {
1550 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1551 return false;
1552 } else {
1553 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1554 return false;
1555 }
1556 return true;
1557}
1558
1559static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1560 enum pipe pipe, u32 val)
1561{
1562 if ((val & ADPA_DAC_ENABLE) == 0)
1563 return false;
1564 if (HAS_PCH_CPT(dev_priv->dev)) {
1565 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1566 return false;
1567 } else {
1568 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1569 return false;
1570 }
1571 return true;
1572}
1573
291906f1 1574static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1575 enum pipe pipe, int reg, u32 port_sel)
291906f1 1576{
47a05eca 1577 u32 val = I915_READ(reg);
e2c719b7 1578 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1579 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1580 reg, pipe_name(pipe));
de9a35ab 1581
e2c719b7 1582 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1583 && (val & DP_PIPEB_SELECT),
de9a35ab 1584 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1585}
1586
1587static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1588 enum pipe pipe, int reg)
1589{
47a05eca 1590 u32 val = I915_READ(reg);
e2c719b7 1591 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1592 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1593 reg, pipe_name(pipe));
de9a35ab 1594
e2c719b7 1595 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1596 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1597 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1598}
1599
1600static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1601 enum pipe pipe)
1602{
1603 int reg;
1604 u32 val;
291906f1 1605
f0575e92
KP		 1606 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1607 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1608 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1609
1610 reg = PCH_ADPA;
1611 val = I915_READ(reg);
e2c719b7 1612 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1613 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1614 pipe_name(pipe));
291906f1
JB		 1615
1616 reg = PCH_LVDS;
1617 val = I915_READ(reg);
e2c719b7 1618 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1619 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1620 pipe_name(pipe));
291906f1 1621
e2debe91
PZ		 1622 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1623 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1624 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1625}
1626
d288f65f 1627static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1628 const struct intel_crtc_state *pipe_config)
87442f73 1629{
426115cf
DV		 1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 int reg = DPLL(crtc->pipe);
d288f65f 1633 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1634
426115cf 1635 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1636
1637 /* No really, not for ILK+ */
1638 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1639
1640 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1641 if (IS_MOBILE(dev_priv->dev))
426115cf 1642 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1643
426115cf
DV		 1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150);
1647
1648 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1649 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1650
d288f65f 1651 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1652 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1653
1654 /* We do this three times for luck */
426115cf 1655 I915_WRITE(reg, dpll);
87442f73
DV		 1656 POSTING_READ(reg);
1657 udelay(150); /* wait for warmup */
426115cf 1658 I915_WRITE(reg, dpll);
87442f73
DV		 1659 POSTING_READ(reg);
1660 udelay(150); /* wait for warmup */
426115cf 1661 I915_WRITE(reg, dpll);
87442f73
DV		 1662 POSTING_READ(reg);
1663 udelay(150); /* wait for warmup */
1664}
1665
d288f65f 1666static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1667 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1668{
1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int pipe = crtc->pipe;
1672 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1673 u32 tmp;
1674
1675 assert_pipe_disabled(dev_priv, crtc->pipe);
1676
1677 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1678
a580516d 1679 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1680
1681 /* Enable back the 10bit clock to display controller */
1682 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1683 tmp |= DPIO_DCLKP_EN;
1684 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1685
54433e91
VS		 1686 mutex_unlock(&dev_priv->sb_lock);
1687
9d556c99
CML		 1688 /*
1689 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1690 */
1691 udelay(1);
1692
1693 /* Enable PLL */
d288f65f 1694 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1695
1696 /* Check PLL is locked */
a11b0703 1697 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1698 DRM_ERROR("PLL %d failed to lock\n", pipe);
1699
a11b0703 1700 /* not sure when this should be written */
d288f65f 1701 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1702 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1703}
1704
1c4e0274
VS		 1705static int intel_num_dvo_pipes(struct drm_device *dev)
1706{
1707 struct intel_crtc *crtc;
1708 int count = 0;
1709
1710 for_each_intel_crtc(dev, crtc)
3538b9df 1711 count += crtc->base.state->active &&
409ee761 1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1713
1714 return count;
1715}
1716
66e3d5c0 1717static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1718{
66e3d5c0
DV		 1719 struct drm_device *dev = crtc->base.dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1721 int reg = DPLL(crtc->pipe);
6e3c9717 1722 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1723
66e3d5c0 1724 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1725
63d7bbe9 1726 /* No really, not for ILK+ */
3d13ef2e 1727 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1728
1729 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1730 if (IS_MOBILE(dev) && !IS_I830(dev))
1731 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1732
1c4e0274
VS		 1733 /* Enable DVO 2x clock on both PLLs if necessary */
1734 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1735 /*
1736 * It appears to be important that we don't enable this
1737 * for the current pipe before otherwise configuring the
1738 * PLL. No idea how this should be handled if multiple
1739 * DVO outputs are enabled simultaneosly.
1740 */
1741 dpll |= DPLL_DVO_2X_MODE;
1742 I915_WRITE(DPLL(!crtc->pipe),
1743 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1744 }
66e3d5c0
DV		 1745
1746 /* Wait for the clocks to stabilize. */
1747 POSTING_READ(reg);
1748 udelay(150);
1749
1750 if (INTEL_INFO(dev)->gen >= 4) {
1751 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1752 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1753 } else {
1754 /* The pixel multiplier can only be updated once the
1755 * DPLL is enabled and the clocks are stable.
1756 *
1757 * So write it again.
1758 */
1759 I915_WRITE(reg, dpll);
1760 }
63d7bbe9
JB		 1761
1762 /* We do this three times for luck */
66e3d5c0 1763 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1764 POSTING_READ(reg);
1765 udelay(150); /* wait for warmup */
66e3d5c0 1766 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1767 POSTING_READ(reg);
1768 udelay(150); /* wait for warmup */
66e3d5c0 1769 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1770 POSTING_READ(reg);
1771 udelay(150); /* wait for warmup */
1772}
1773
1774/**
50b44a44 1775 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1776 * @dev_priv: i915 private structure
1777 * @pipe: pipe PLL to disable
1778 *
1779 * Disable the PLL for @pipe, making sure the pipe is off first.
1780 *
1781 * Note! This is for pre-ILK only.
1782 */
1c4e0274 1783static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1784{
1c4e0274
VS		 1785 struct drm_device *dev = crtc->base.dev;
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787 enum pipe pipe = crtc->pipe;
1788
1789 /* Disable DVO 2x clock on both PLLs if necessary */
1790 if (IS_I830(dev) &&
409ee761 1791 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1792 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1793 I915_WRITE(DPLL(PIPE_B),
1794 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1795 I915_WRITE(DPLL(PIPE_A),
1796 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1797 }
1798
b6b5d049
VS		 1799 /* Don't disable pipe or pipe PLLs if needed */
1800 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1801 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1802 return;
1803
1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
1806
b8afb911 1807 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1808 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1809}
1810
f6071166
JB		 1811static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812{
b8afb911 1813 u32 val;
f6071166
JB		 1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
e5cbfbfb
ID		 1818 /*
1819 * Leave integrated clock source and reference clock enabled for pipe B.
1820 * The latter is needed for VGA hotplug / manual detection.
1821 */
b8afb911 1822 val = DPLL_VGA_MODE_DIS;
f6071166 1823 if (pipe == PIPE_B)
60bfe44f 1824 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1825 I915_WRITE(DPLL(pipe), val);
1826 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1827
1828}
1829
1830static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1831{
d752048d 1832 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1833 u32 val;
1834
a11b0703
VS		 1835 /* Make sure the pipe isn't still relying on us */
1836 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1837
a11b0703 1838 /* Set PLL en = 0 */
60bfe44f
VS		 1839 val = DPLL_SSC_REF_CLK_CHV |
1840 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1841 if (pipe != PIPE_A)
1842 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1843 I915_WRITE(DPLL(pipe), val);
1844 POSTING_READ(DPLL(pipe));
d752048d 1845
a580516d 1846 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1847
1848 /* Disable 10bit clock to display controller */
1849 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1850 val &= ~DPIO_DCLKP_EN;
1851 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1852
a580516d 1853 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1854}
1855
e4607fcf 1856void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1857 struct intel_digital_port *dport,
1858 unsigned int expected_mask)
89b667f8
JB		 1859{
1860 u32 port_mask;
00fc31b7 1861 int dpll_reg;
89b667f8 1862
e4607fcf
CML		 1863 switch (dport->port) {
1864 case PORT_B:
89b667f8 1865 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1866 dpll_reg = DPLL(0);
e4607fcf
CML		 1867 break;
1868 case PORT_C:
89b667f8 1869 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1870 dpll_reg = DPLL(0);
9b6de0a1 1871 expected_mask <<= 4;
00fc31b7
CML		 1872 break;
1873 case PORT_D:
1874 port_mask = DPLL_PORTD_READY_MASK;
1875 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1876 break;
1877 default:
1878 BUG();
1879 }
89b667f8 1880
9b6de0a1
VS		 1881 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1882 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1883 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1884}
1885
b14b1055
DV		 1886static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1887{
1888 struct drm_device *dev = crtc->base.dev;
1889 struct drm_i915_private *dev_priv = dev->dev_private;
1890 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1891
be19f0ff
CW		 1892 if (WARN_ON(pll == NULL))
1893 return;
1894
3e369b76 1895 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1896 if (pll->active == 0) {
1897 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1898 WARN_ON(pll->on);
1899 assert_shared_dpll_disabled(dev_priv, pll);
1900
1901 pll->mode_set(dev_priv, pll);
1902 }
1903}
1904
92f2584a 1905/**
85b3894f 1906 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1907 * @dev_priv: i915 private structure
1908 * @pipe: pipe PLL to enable
1909 *
1910 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1911 * drives the transcoder clock.
1912 */
85b3894f 1913static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1918
87a875bb 1919 if (WARN_ON(pll == NULL))
48da64a8
CW		 1920 return;
1921
3e369b76 1922 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1923 return;
ee7b9f93 1924
74dd6928 1925 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1926 pll->name, pll->active, pll->on,
e2b78267 1927 crtc->base.base.id);
92f2584a 1928
cdbd2316
DV		 1929 if (pll->active++) {
1930 WARN_ON(!pll->on);
e9d6944e 1931 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1932 return;
1933 }
f4a091c7 1934 WARN_ON(pll->on);
ee7b9f93 1935
bd2bb1b9
PZ		 1936 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1937
46edb027 1938 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1939 pll->enable(dev_priv, pll);
ee7b9f93 1940 pll->on = true;
92f2584a
JB		 1941}
1942
f6daaec2 1943static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1944{
3d13ef2e
DL		 1945 struct drm_device *dev = crtc->base.dev;
1946 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1947 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1948
92f2584a 1949 /* PCH only available on ILK+ */
80aa9312
JB		 1950 if (INTEL_INFO(dev)->gen < 5)
1951 return;
1952
eddfcbcd
ML		 1953 if (pll == NULL)
1954 return;
92f2584a 1955
eddfcbcd 1956 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1957 return;
7a419866 1958
46edb027
DV		 1959 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1960 pll->name, pll->active, pll->on,
e2b78267 1961 crtc->base.base.id);
7a419866 1962
48da64a8 1963 if (WARN_ON(pll->active == 0)) {
e9d6944e 1964 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1965 return;
1966 }
1967
e9d6944e 1968 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1969 WARN_ON(!pll->on);
cdbd2316 1970 if (--pll->active)
7a419866 1971 return;
ee7b9f93 1972
46edb027 1973 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1974 pll->disable(dev_priv, pll);
ee7b9f93 1975 pll->on = false;
bd2bb1b9
PZ		 1976
1977 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1978}
1979
b8a4f404
PZ		 1980static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1981 enum pipe pipe)
040484af 1982{
23670b32 1983 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1984 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1986 uint32_t reg, val, pipeconf_val;
040484af
JB		 1987
1988 /* PCH only available on ILK+ */
55522f37 1989 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1990
1991 /* Make sure PCH DPLL is enabled */
e72f9fbf 1992 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1993 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1994
1995 /* FDI must be feeding us bits for PCH ports */
1996 assert_fdi_tx_enabled(dev_priv, pipe);
1997 assert_fdi_rx_enabled(dev_priv, pipe);
1998
23670b32
DV		 1999 if (HAS_PCH_CPT(dev)) {
2000 /* Workaround: Set the timing override bit before enabling the
2001 * pch transcoder. */
2002 reg = TRANS_CHICKEN2(pipe);
2003 val = I915_READ(reg);
2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2005 I915_WRITE(reg, val);
59c859d6 2006 }
23670b32 2007
ab9412ba 2008 reg = PCH_TRANSCONF(pipe);
040484af 2009 val = I915_READ(reg);
5f7f726d 2010 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2011
2012 if (HAS_PCH_IBX(dev_priv->dev)) {
2013 /*
c5de7c6f
VS		 2014 * Make the BPC in transcoder be consistent with
2015 * that in pipeconf reg. For HDMI we must use 8bpc
2016 * here for both 8bpc and 12bpc.
e9bcff5c 2017 */
dfd07d72 2018 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2019 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2020 val |= PIPECONF_8BPC;
2021 else
2022 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2023 }
5f7f726d
PZ		 2024
2025 val &= ~TRANS_INTERLACE_MASK;
2026 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2027 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2028 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2029 val |= TRANS_LEGACY_INTERLACED_ILK;
2030 else
2031 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2032 else
2033 val |= TRANS_PROGRESSIVE;
2034
040484af
JB		 2035 I915_WRITE(reg, val | TRANS_ENABLE);
2036 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2037 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2038}
2039
8fb033d7 2040static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2041 enum transcoder cpu_transcoder)
040484af 2042{
8fb033d7 2043 u32 val, pipeconf_val;
8fb033d7
PZ		 2044
2045 /* PCH only available on ILK+ */
55522f37 2046 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2047
8fb033d7 2048 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2049 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2050 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2051
223a6fdf 2052 /* Workaround: set timing override bit. */
36c0d0cf 2053 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2054 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2055 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2056
25f3ef11 2057 val = TRANS_ENABLE;
937bb610 2058 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2059
9a76b1c6
PZ		 2060 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2061 PIPECONF_INTERLACED_ILK)
a35f2679 2062 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2063 else
2064 val |= TRANS_PROGRESSIVE;
2065
ab9412ba
DV		 2066 I915_WRITE(LPT_TRANSCONF, val);
2067 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2068 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2069}
2070
b8a4f404
PZ		 2071static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2072 enum pipe pipe)
040484af 2073{
23670b32
DV		 2074 struct drm_device *dev = dev_priv->dev;
2075 uint32_t reg, val;
040484af
JB		 2076
2077 /* FDI relies on the transcoder */
2078 assert_fdi_tx_disabled(dev_priv, pipe);
2079 assert_fdi_rx_disabled(dev_priv, pipe);
2080
291906f1
JB		 2081 /* Ports must be off as well */
2082 assert_pch_ports_disabled(dev_priv, pipe);
2083
ab9412ba 2084 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2085 val = I915_READ(reg);
2086 val &= ~TRANS_ENABLE;
2087 I915_WRITE(reg, val);
2088 /* wait for PCH transcoder off, transcoder state */
2089 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2090 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2091
2092 if (!HAS_PCH_IBX(dev)) {
2093 /* Workaround: Clear the timing override chicken bit again. */
2094 reg = TRANS_CHICKEN2(pipe);
2095 val = I915_READ(reg);
2096 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2097 I915_WRITE(reg, val);
2098 }
040484af
JB		 2099}
2100
ab4d966c 2101static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2102{
8fb033d7
PZ		 2103 u32 val;
2104
ab9412ba 2105 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2106 val &= ~TRANS_ENABLE;
ab9412ba 2107 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2108 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2109 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2110 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2111
2112 /* Workaround: clear timing override bit. */
36c0d0cf 2113 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2114 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2115 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2116}
2117
b24e7179 2118/**
309cfea8 2119 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2120 * @crtc: crtc responsible for the pipe
b24e7179 2121 *
0372264a 2122 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2123 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2124 */
e1fdc473 2125static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2126{
0372264a
PZ		 2127 struct drm_device *dev = crtc->base.dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2130 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2131 pipe);
1a240d4d 2132 enum pipe pch_transcoder;
b24e7179
JB		 2133 int reg;
2134 u32 val;
2135
9e2ee2dd
VS		 2136 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2137
58c6eaa2 2138 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2139 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2140 assert_sprites_disabled(dev_priv, pipe);
2141
681e5811 2142 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2143 pch_transcoder = TRANSCODER_A;
2144 else
2145 pch_transcoder = pipe;
2146
b24e7179
JB		 2147 /*
2148 * A pipe without a PLL won't actually be able to drive bits from
2149 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2150 * need the check.
2151 */
50360403 2152 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2154 assert_dsi_pll_enabled(dev_priv);
2155 else
2156 assert_pll_enabled(dev_priv, pipe);
040484af 2157 else {
6e3c9717 2158 if (crtc->config->has_pch_encoder) {
040484af 2159 /* if driving the PCH, we need FDI enabled */
cc391bbb 2160 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2161 assert_fdi_tx_pll_enabled(dev_priv,
2162 (enum pipe) cpu_transcoder);
040484af
JB		 2163 }
2164 /* FIXME: assert CPU port conditions for SNB+ */
2165 }
b24e7179 2166
702e7a56 2167 reg = PIPECONF(cpu_transcoder);
b24e7179 2168 val = I915_READ(reg);
7ad25d48 2169 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2170 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2171 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2172 return;
7ad25d48 2173 }
00d70b15
CW		 2174
2175 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2176 POSTING_READ(reg);
b24e7179
JB		 2177}
2178
2179/**
309cfea8 2180 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2181 * @crtc: crtc whose pipes is to be disabled
b24e7179 2182 *
575f7ab7
VS		 2183 * Disable the pipe of @crtc, making sure that various hardware
2184 * specific requirements are met, if applicable, e.g. plane
2185 * disabled, panel fitter off, etc.
b24e7179
JB		 2186 *
2187 * Will wait until the pipe has shut down before returning.
2188 */
575f7ab7 2189static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2190{
575f7ab7 2191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2192 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2193 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2194 int reg;
2195 u32 val;
2196
9e2ee2dd
VS		 2197 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2198
b24e7179
JB		 2199 /*
2200 * Make sure planes won't keep trying to pump pixels to us,
2201 * or we might hang the display.
2202 */
2203 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2204 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2205 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2206
702e7a56 2207 reg = PIPECONF(cpu_transcoder);
b24e7179 2208 val = I915_READ(reg);
00d70b15
CW		 2209 if ((val & PIPECONF_ENABLE) == 0)
2210 return;
2211
67adc644
VS		 2212 /*
2213 * Double wide has implications for planes
2214 * so best keep it disabled when not needed.
2215 */
6e3c9717 2216 if (crtc->config->double_wide)
67adc644
VS		 2217 val &= ~PIPECONF_DOUBLE_WIDE;
2218
2219 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2220 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2221 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2222 val &= ~PIPECONF_ENABLE;
2223
2224 I915_WRITE(reg, val);
2225 if ((val & PIPECONF_ENABLE) == 0)
2226 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2227}
2228
693db184
CW		 2229static bool need_vtd_wa(struct drm_device *dev)
2230{
2231#ifdef CONFIG_INTEL_IOMMU
2232 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2233 return true;
2234#endif
2235 return false;
2236}
2237
50470bb0 2238unsigned int
6761dd31 2239intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2240 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2241{
6761dd31
TU		 2242 unsigned int tile_height;
2243 uint32_t pixel_bytes;
a57ce0b2 2244
b5d0e9bf
DL		 2245 switch (fb_format_modifier) {
2246 case DRM_FORMAT_MOD_NONE:
2247 tile_height = 1;
2248 break;
2249 case I915_FORMAT_MOD_X_TILED:
2250 tile_height = IS_GEN2(dev) ? 16 : 8;
2251 break;
2252 case I915_FORMAT_MOD_Y_TILED:
2253 tile_height = 32;
2254 break;
2255 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2256 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2257 switch (pixel_bytes) {
b5d0e9bf 2258 default:
6761dd31 2259 case 1:
b5d0e9bf
DL		 2260 tile_height = 64;
2261 break;
6761dd31
TU		 2262 case 2:
2263 case 4:
b5d0e9bf
DL		 2264 tile_height = 32;
2265 break;
6761dd31 2266 case 8:
b5d0e9bf
DL		 2267 tile_height = 16;
2268 break;
6761dd31 2269 case 16:
b5d0e9bf
DL		 2270 WARN_ONCE(1,
2271 "128-bit pixels are not supported for display!");
2272 tile_height = 16;
2273 break;
2274 }
2275 break;
2276 default:
2277 MISSING_CASE(fb_format_modifier);
2278 tile_height = 1;
2279 break;
2280 }
091df6cb 2281
6761dd31
TU		 2282 return tile_height;
2283}
2284
2285unsigned int
2286intel_fb_align_height(struct drm_device *dev, unsigned int height,
2287 uint32_t pixel_format, uint64_t fb_format_modifier)
2288{
2289 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2290 fb_format_modifier, 0));
a57ce0b2
JB		 2291}
2292
f64b98cd
TU		 2293static int
2294intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2295 const struct drm_plane_state *plane_state)
2296{
50470bb0 2297 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2298 unsigned int tile_height, tile_pitch;
50470bb0 2299
f64b98cd
TU		 2300 *view = i915_ggtt_view_normal;
2301
50470bb0
TU		 2302 if (!plane_state)
2303 return 0;
2304
121920fa 2305 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2306 return 0;
2307
9abc4648 2308 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2309
2310 info->height = fb->height;
2311 info->pixel_format = fb->pixel_format;
2312 info->pitch = fb->pitches[0];
89e3e142 2313 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2314 info->fb_modifier = fb->modifier[0];
2315
84fe03f7 2316 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2317 fb->modifier[0], 0);
84fe03f7
TU		 2318 tile_pitch = PAGE_SIZE / tile_height;
2319 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2320 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2321 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2322
89e3e142
TU		 2323 if (info->pixel_format == DRM_FORMAT_NV12) {
2324 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2325 fb->modifier[0], 1);
2326 tile_pitch = PAGE_SIZE / tile_height;
2327 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2328 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2329 tile_height);
2330 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2331 PAGE_SIZE;
2332 }
2333
f64b98cd
TU		 2334 return 0;
2335}
2336
4e9a86b6
VS		 2337static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2338{
2339 if (INTEL_INFO(dev_priv)->gen >= 9)
2340 return 256 * 1024;
985b8bb4
VS		 2341 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2342 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2343 return 128 * 1024;
2344 else if (INTEL_INFO(dev_priv)->gen >= 4)
2345 return 4 * 1024;
2346 else
44c5905e 2347 return 0;
4e9a86b6
VS		 2348}
2349
127bd2ac 2350int
850c4cdc
TU		 2351intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2352 struct drm_framebuffer *fb,
82bc3b2d 2353 const struct drm_plane_state *plane_state,
91af127f
JH		 2354 struct intel_engine_cs *pipelined,
2355 struct drm_i915_gem_request **pipelined_request)
6b95a207 2356{
850c4cdc 2357 struct drm_device *dev = fb->dev;
ce453d81 2358 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2360 struct i915_ggtt_view view;
6b95a207
KH		 2361 u32 alignment;
2362 int ret;
2363
ebcdd39e
MR		 2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
7b911adc
TU		 2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2368 alignment = intel_linear_alignment(dev_priv);
6b95a207 2369 break;
7b911adc 2370 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2371 if (INTEL_INFO(dev)->gen >= 9)
2372 alignment = 256 * 1024;
2373 else {
2374 /* pin() will align the object as required by fence */
2375 alignment = 0;
2376 }
6b95a207 2377 break;
7b911adc 2378 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2379 case I915_FORMAT_MOD_Yf_TILED:
2380 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2381 "Y tiling bo slipped through, driver bug!\n"))
2382 return -EINVAL;
2383 alignment = 1 * 1024 * 1024;
2384 break;
6b95a207 2385 default:
7b911adc
TU		 2386 MISSING_CASE(fb->modifier[0]);
2387 return -EINVAL;
6b95a207
KH		 2388 }
2389
f64b98cd
TU		 2390 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2391 if (ret)
2392 return ret;
2393
693db184
CW		 2394 /* Note that the w/a also requires 64 PTE of padding following the
2395 * bo. We currently fill all unused PTE with the shadow page and so
2396 * we should always have valid PTE following the scanout preventing
2397 * the VT-d warning.
2398 */
2399 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2400 alignment = 256 * 1024;
2401
d6dd6843
PZ		 2402 /*
2403 * Global gtt pte registers are special registers which actually forward
2404 * writes to a chunk of system memory. Which means that there is no risk
2405 * that the register values disappear as soon as we call
2406 * intel_runtime_pm_put(), so it is correct to wrap only the
2407 * pin/unpin/fence and not more.
2408 */
2409 intel_runtime_pm_get(dev_priv);
2410
ce453d81 2411 dev_priv->mm.interruptible = false;
e6617330 2412 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2413 pipelined_request, &view);
48b956c5 2414 if (ret)
ce453d81 2415 goto err_interruptible;
6b95a207
KH		 2416
2417 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418 * fence, whereas 965+ only requires a fence if using
2419 * framebuffer compression. For simplicity, we always install
2420 * a fence as the cost is not that onerous.
2421 */
06d98131 2422 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2423 if (ret == -EDEADLK) {
2424 /*
2425 * -EDEADLK means there are no free fences
2426 * no pending flips.
2427 *
2428 * This is propagated to atomic, but it uses
2429 * -EDEADLK to force a locking recovery, so
2430 * change the returned error to -EBUSY.
2431 */
2432 ret = -EBUSY;
2433 goto err_unpin;
2434 } else if (ret)
9a5a53b3 2435 goto err_unpin;
1690e1eb 2436
9a5a53b3 2437 i915_gem_object_pin_fence(obj);
6b95a207 2438
ce453d81 2439 dev_priv->mm.interruptible = true;
d6dd6843 2440 intel_runtime_pm_put(dev_priv);
6b95a207 2441 return 0;
48b956c5
CW		 2442
2443err_unpin:
f64b98cd 2444 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2445err_interruptible:
2446 dev_priv->mm.interruptible = true;
d6dd6843 2447 intel_runtime_pm_put(dev_priv);
48b956c5 2448 return ret;
6b95a207
KH		 2449}
2450
82bc3b2d
TU		 2451static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2452 const struct drm_plane_state *plane_state)
1690e1eb 2453{
82bc3b2d 2454 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2455 struct i915_ggtt_view view;
2456 int ret;
82bc3b2d 2457
ebcdd39e
MR		 2458 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2459
f64b98cd
TU		 2460 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2461 WARN_ONCE(ret, "Couldn't get view from plane state!");
2462
1690e1eb 2463 i915_gem_object_unpin_fence(obj);
f64b98cd 2464 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2465}
2466
c2c75131
DV		 2467/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2468 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2469unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2470 int *x, int *y,
bc752862
CW		 2471 unsigned int tiling_mode,
2472 unsigned int cpp,
2473 unsigned int pitch)
c2c75131 2474{
bc752862
CW		 2475 if (tiling_mode != I915_TILING_NONE) {
2476 unsigned int tile_rows, tiles;
c2c75131 2477
bc752862
CW		 2478 tile_rows = *y / 8;
2479 *y %= 8;
c2c75131 2480
bc752862
CW		 2481 tiles = *x / (512/cpp);
2482 *x %= 512/cpp;
2483
2484 return tile_rows * pitch * 8 + tiles * 4096;
2485 } else {
4e9a86b6 2486 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2487 unsigned int offset;
2488
2489 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2490 *y = (offset & alignment) / pitch;
2491 *x = ((offset & alignment) - *y * pitch) / cpp;
2492 return offset & ~alignment;
bc752862 2493 }
c2c75131
DV		 2494}
2495
b35d63fa 2496static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2497{
2498 switch (format) {
2499 case DISPPLANE_8BPP:
2500 return DRM_FORMAT_C8;
2501 case DISPPLANE_BGRX555:
2502 return DRM_FORMAT_XRGB1555;
2503 case DISPPLANE_BGRX565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case DISPPLANE_BGRX888:
2507 return DRM_FORMAT_XRGB8888;
2508 case DISPPLANE_RGBX888:
2509 return DRM_FORMAT_XBGR8888;
2510 case DISPPLANE_BGRX101010:
2511 return DRM_FORMAT_XRGB2101010;
2512 case DISPPLANE_RGBX101010:
2513 return DRM_FORMAT_XBGR2101010;
2514 }
2515}
2516
bc8d7dff
DL		 2517static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2518{
2519 switch (format) {
2520 case PLANE_CTL_FORMAT_RGB_565:
2521 return DRM_FORMAT_RGB565;
2522 default:
2523 case PLANE_CTL_FORMAT_XRGB_8888:
2524 if (rgb_order) {
2525 if (alpha)
2526 return DRM_FORMAT_ABGR8888;
2527 else
2528 return DRM_FORMAT_XBGR8888;
2529 } else {
2530 if (alpha)
2531 return DRM_FORMAT_ARGB8888;
2532 else
2533 return DRM_FORMAT_XRGB8888;
2534 }
2535 case PLANE_CTL_FORMAT_XRGB_2101010:
2536 if (rgb_order)
2537 return DRM_FORMAT_XBGR2101010;
2538 else
2539 return DRM_FORMAT_XRGB2101010;
2540 }
2541}
2542
5724dbd1 2543static bool
f6936e29
DV		 2544intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2545 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2546{
2547 struct drm_device *dev = crtc->base.dev;
2548 struct drm_i915_gem_object *obj = NULL;
2549 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2550 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2551 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2552 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2553 PAGE_SIZE);
2554
2555 size_aligned -= base_aligned;
46f297fb 2556
ff2652ea
CW		 2557 if (plane_config->size == 0)
2558 return false;
2559
f37b5c2b
DV		 2560 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2561 base_aligned,
2562 base_aligned,
2563 size_aligned);
46f297fb 2564 if (!obj)
484b41dd 2565 return false;
46f297fb 2566
49af449b
DL		 2567 obj->tiling_mode = plane_config->tiling;
2568 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2569 obj->stride = fb->pitches[0];
46f297fb 2570
6bf129df
DL		 2571 mode_cmd.pixel_format = fb->pixel_format;
2572 mode_cmd.width = fb->width;
2573 mode_cmd.height = fb->height;
2574 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2575 mode_cmd.modifier[0] = fb->modifier[0];
2576 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2577
2578 mutex_lock(&dev->struct_mutex);
6bf129df 2579 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2580 &mode_cmd, obj)) {
46f297fb
JB		 2581 DRM_DEBUG_KMS("intel fb init failed\n");
2582 goto out_unref_obj;
2583 }
46f297fb 2584 mutex_unlock(&dev->struct_mutex);
484b41dd 2585
f6936e29 2586 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2587 return true;
46f297fb
JB		 2588
2589out_unref_obj:
2590 drm_gem_object_unreference(&obj->base);
2591 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2592 return false;
2593}
2594
afd65eb4
MR		 2595/* Update plane->state->fb to match plane->fb after driver-internal updates */
2596static void
2597update_state_fb(struct drm_plane *plane)
2598{
2599 if (plane->fb == plane->state->fb)
2600 return;
2601
2602 if (plane->state->fb)
2603 drm_framebuffer_unreference(plane->state->fb);
2604 plane->state->fb = plane->fb;
2605 if (plane->state->fb)
2606 drm_framebuffer_reference(plane->state->fb);
2607}
2608
5724dbd1 2609static void
f6936e29
DV		 2610intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2611 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2612{
2613 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2614 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2615 struct drm_crtc *c;
2616 struct intel_crtc *i;
2ff8fde1 2617 struct drm_i915_gem_object *obj;
88595ac9 2618 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2619 struct drm_plane_state *plane_state = primary->state;
88595ac9 2620 struct drm_framebuffer *fb;
484b41dd 2621
2d14030b 2622 if (!plane_config->fb)
484b41dd
JB		 2623 return;
2624
f6936e29 2625 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2626 fb = &plane_config->fb->base;
2627 goto valid_fb;
f55548b5 2628 }
484b41dd 2629
2d14030b 2630 kfree(plane_config->fb);
484b41dd
JB		 2631
2632 /*
2633 * Failed to alloc the obj, check to see if we should share
2634 * an fb with another CRTC instead
2635 */
70e1e0ec 2636 for_each_crtc(dev, c) {
484b41dd
JB		 2637 i = to_intel_crtc(c);
2638
2639 if (c == &intel_crtc->base)
2640 continue;
2641
2ff8fde1
MR		 2642 if (!i->active)
2643 continue;
2644
88595ac9
DV		 2645 fb = c->primary->fb;
2646 if (!fb)
484b41dd
JB		 2647 continue;
2648
88595ac9 2649 obj = intel_fb_obj(fb);
2ff8fde1 2650 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2651 drm_framebuffer_reference(fb);
2652 goto valid_fb;
484b41dd
JB		 2653 }
2654 }
88595ac9
DV		 2655
2656 return;
2657
2658valid_fb:
be5651f2
ML		 2659 plane_state->src_x = plane_state->src_y = 0;
2660 plane_state->src_w = fb->width << 16;
2661 plane_state->src_h = fb->height << 16;
2662
2663 plane_state->crtc_x = plane_state->src_y = 0;
2664 plane_state->crtc_w = fb->width;
2665 plane_state->crtc_h = fb->height;
2666
88595ac9
DV		 2667 obj = intel_fb_obj(fb);
2668 if (obj->tiling_mode != I915_TILING_NONE)
2669 dev_priv->preserve_bios_swizzle = true;
2670
be5651f2
ML		 2671 drm_framebuffer_reference(fb);
2672 primary->fb = primary->state->fb = fb;
36750f28 2673 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2674 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2675 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2676}
2677
29b9bde6
DV		 2678static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2679 struct drm_framebuffer *fb,
2680 int x, int y)
81255565
JB		 2681{
2682 struct drm_device *dev = crtc->dev;
2683 struct drm_i915_private *dev_priv = dev->dev_private;
2684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2685 struct drm_plane *primary = crtc->primary;
2686 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2687 struct drm_i915_gem_object *obj;
81255565 2688 int plane = intel_crtc->plane;
e506a0c6 2689 unsigned long linear_offset;
81255565 2690 u32 dspcntr;
f45651ba 2691 u32 reg = DSPCNTR(plane);
48404c1e 2692 int pixel_size;
f45651ba 2693
b70709a6 2694 if (!visible || !fb) {
fdd508a6
VS		 2695 I915_WRITE(reg, 0);
2696 if (INTEL_INFO(dev)->gen >= 4)
2697 I915_WRITE(DSPSURF(plane), 0);
2698 else
2699 I915_WRITE(DSPADDR(plane), 0);
2700 POSTING_READ(reg);
2701 return;
2702 }
2703
c9ba6fad
VS		 2704 obj = intel_fb_obj(fb);
2705 if (WARN_ON(obj == NULL))
2706 return;
2707
2708 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2709
f45651ba
VS		 2710 dspcntr = DISPPLANE_GAMMA_ENABLE;
2711
fdd508a6 2712 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2713
2714 if (INTEL_INFO(dev)->gen < 4) {
2715 if (intel_crtc->pipe == PIPE_B)
2716 dspcntr |= DISPPLANE_SEL_PIPE_B;
2717
2718 /* pipesrc and dspsize control the size that is scaled from,
2719 * which should always be the user's requested size.
2720 */
2721 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2722 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2723 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2724 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2725 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2726 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2727 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2728 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2729 I915_WRITE(PRIMPOS(plane), 0);
2730 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2731 }
81255565 2732
57779d06
VS		 2733 switch (fb->pixel_format) {
2734 case DRM_FORMAT_C8:
81255565
JB		 2735 dspcntr |= DISPPLANE_8BPP;
2736 break;
57779d06 2737 case DRM_FORMAT_XRGB1555:
57779d06 2738 dspcntr |= DISPPLANE_BGRX555;
81255565 2739 break;
57779d06
VS		 2740 case DRM_FORMAT_RGB565:
2741 dspcntr |= DISPPLANE_BGRX565;
2742 break;
2743 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2744 dspcntr |= DISPPLANE_BGRX888;
2745 break;
2746 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2747 dspcntr |= DISPPLANE_RGBX888;
2748 break;
2749 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2750 dspcntr |= DISPPLANE_BGRX101010;
2751 break;
2752 case DRM_FORMAT_XBGR2101010:
57779d06 2753 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2754 break;
2755 default:
baba133a 2756 BUG();
81255565 2757 }
57779d06 2758
f45651ba
VS		 2759 if (INTEL_INFO(dev)->gen >= 4 &&
2760 obj->tiling_mode != I915_TILING_NONE)
2761 dspcntr |= DISPPLANE_TILED;
81255565 2762
de1aa629
VS		 2763 if (IS_G4X(dev))
2764 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2765
b9897127 2766 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2767
c2c75131
DV		 2768 if (INTEL_INFO(dev)->gen >= 4) {
2769 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2770 intel_gen4_compute_page_offset(dev_priv,
2771 &x, &y, obj->tiling_mode,
b9897127 2772 pixel_size,
bc752862 2773 fb->pitches[0]);
c2c75131
DV		 2774 linear_offset -= intel_crtc->dspaddr_offset;
2775 } else {
e506a0c6 2776 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2777 }
e506a0c6 2778
8e7d688b 2779 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2780 dspcntr |= DISPPLANE_ROTATE_180;
2781
6e3c9717
ACO		 2782 x += (intel_crtc->config->pipe_src_w - 1);
2783 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2784
2785 /* Finding the last pixel of the last line of the display
2786 data and adding to linear_offset*/
2787 linear_offset +=
6e3c9717
ACO		 2788 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2790 }
2791
2db3366b
PZ		 2792 intel_crtc->adjusted_x = x;
2793 intel_crtc->adjusted_y = y;
2794
48404c1e
SJ		 2795 I915_WRITE(reg, dspcntr);
2796
01f2c773 2797 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2798 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2799 I915_WRITE(DSPSURF(plane),
2800 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2801 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2802 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2803 } else
f343c5f6 2804 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2805 POSTING_READ(reg);
17638cd6
JB		 2806}
2807
29b9bde6
DV		 2808static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2810 int x, int y)
17638cd6
JB		 2811{
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2815 struct drm_plane *primary = crtc->primary;
2816 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2817 struct drm_i915_gem_object *obj;
17638cd6 2818 int plane = intel_crtc->plane;
e506a0c6 2819 unsigned long linear_offset;
17638cd6 2820 u32 dspcntr;
f45651ba 2821 u32 reg = DSPCNTR(plane);
48404c1e 2822 int pixel_size;
f45651ba 2823
b70709a6 2824 if (!visible || !fb) {
fdd508a6
VS		 2825 I915_WRITE(reg, 0);
2826 I915_WRITE(DSPSURF(plane), 0);
2827 POSTING_READ(reg);
2828 return;
2829 }
2830
c9ba6fad
VS		 2831 obj = intel_fb_obj(fb);
2832 if (WARN_ON(obj == NULL))
2833 return;
2834
2835 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2836
f45651ba
VS		 2837 dspcntr = DISPPLANE_GAMMA_ENABLE;
2838
fdd508a6 2839 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2840
2841 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2842 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2843
57779d06
VS		 2844 switch (fb->pixel_format) {
2845 case DRM_FORMAT_C8:
17638cd6
JB		 2846 dspcntr |= DISPPLANE_8BPP;
2847 break;
57779d06
VS		 2848 case DRM_FORMAT_RGB565:
2849 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2850 break;
57779d06 2851 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2852 dspcntr |= DISPPLANE_BGRX888;
2853 break;
2854 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2855 dspcntr |= DISPPLANE_RGBX888;
2856 break;
2857 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2858 dspcntr |= DISPPLANE_BGRX101010;
2859 break;
2860 case DRM_FORMAT_XBGR2101010:
57779d06 2861 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2862 break;
2863 default:
baba133a 2864 BUG();
17638cd6
JB		 2865 }
2866
2867 if (obj->tiling_mode != I915_TILING_NONE)
2868 dspcntr |= DISPPLANE_TILED;
17638cd6 2869
f45651ba 2870 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2871 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2872
b9897127 2873 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2874 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2875 intel_gen4_compute_page_offset(dev_priv,
2876 &x, &y, obj->tiling_mode,
b9897127 2877 pixel_size,
bc752862 2878 fb->pitches[0]);
c2c75131 2879 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2881 dspcntr |= DISPPLANE_ROTATE_180;
2882
2883 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2884 x += (intel_crtc->config->pipe_src_w - 1);
2885 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2886
2887 /* Finding the last pixel of the last line of the display
2888 data and adding to linear_offset*/
2889 linear_offset +=
6e3c9717
ACO		 2890 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2891 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2892 }
2893 }
2894
2db3366b
PZ		 2895 intel_crtc->adjusted_x = x;
2896 intel_crtc->adjusted_y = y;
2897
48404c1e 2898 I915_WRITE(reg, dspcntr);
17638cd6 2899
01f2c773 2900 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2901 I915_WRITE(DSPSURF(plane),
2902 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2903 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2904 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2905 } else {
2906 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2907 I915_WRITE(DSPLINOFF(plane), linear_offset);
2908 }
17638cd6 2909 POSTING_READ(reg);
17638cd6
JB		 2910}
2911
b321803d
DL		 2912u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2913 uint32_t pixel_format)
2914{
2915 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2916
2917 /*
2918 * The stride is either expressed as a multiple of 64 bytes
2919 * chunks for linear buffers or in number of tiles for tiled
2920 * buffers.
2921 */
2922 switch (fb_modifier) {
2923 case DRM_FORMAT_MOD_NONE:
2924 return 64;
2925 case I915_FORMAT_MOD_X_TILED:
2926 if (INTEL_INFO(dev)->gen == 2)
2927 return 128;
2928 return 512;
2929 case I915_FORMAT_MOD_Y_TILED:
2930 /* No need to check for old gens and Y tiling since this is
2931 * about the display engine and those will be blocked before
2932 * we get here.
2933 */
2934 return 128;
2935 case I915_FORMAT_MOD_Yf_TILED:
2936 if (bits_per_pixel == 8)
2937 return 64;
2938 else
2939 return 128;
2940 default:
2941 MISSING_CASE(fb_modifier);
2942 return 64;
2943 }
2944}
2945
121920fa 2946unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
dedf278c
TU		 2947 struct drm_i915_gem_object *obj,
2948 unsigned int plane)
121920fa 2949{
9abc4648 2950 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c
TU		 2951 struct i915_vma *vma;
2952 unsigned char *offset;
121920fa
TU		 2953
2954 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2955 view = &i915_ggtt_view_rotated;
121920fa 2956
dedf278c
TU		 2957 vma = i915_gem_obj_to_ggtt_view(obj, view);
2958 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2959 view->type))
2960 return -1;
2961
2962 offset = (unsigned char *)vma->node.start;
2963
2964 if (plane == 1) {
2965 offset += vma->ggtt_view.rotation_info.uv_start_page *
2966 PAGE_SIZE;
2967 }
2968
2969 return (unsigned long)offset;
121920fa
TU		 2970}
2971
e435d6e5
ML		 2972static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2973{
2974 struct drm_device *dev = intel_crtc->base.dev;
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976
2977 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2978 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2979 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2980}
2981
a1b2278e
CK		 2982/*
2983 * This function detaches (aka. unbinds) unused scalers in hardware
2984 */
0583236e 2985static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2986{
a1b2278e
CK		 2987 struct intel_crtc_scaler_state *scaler_state;
2988 int i;
2989
a1b2278e
CK		 2990 scaler_state = &intel_crtc->config->scaler_state;
2991
2992 /* loop through and disable scalers that aren't in use */
2993 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2994 if (!scaler_state->scalers[i].in_use)
2995 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2996 }
2997}
2998
6156a456 2999u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 3000{
6156a456 3001 switch (pixel_format) {
d161cf7a 3002 case DRM_FORMAT_C8:
c34ce3d1 3003 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 3004 case DRM_FORMAT_RGB565:
c34ce3d1 3005 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 3006 case DRM_FORMAT_XBGR8888:
c34ce3d1 3007 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 3008 case DRM_FORMAT_XRGB8888:
c34ce3d1 3009 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 3010 /*
3011 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3012 * to be already pre-multiplied. We need to add a knob (or a different
3013 * DRM_FORMAT) for user-space to configure that.
3014 */
f75fb42a 3015 case DRM_FORMAT_ABGR8888:
c34ce3d1 3016 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 3017 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 3018 case DRM_FORMAT_ARGB8888:
c34ce3d1 3019 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 3020 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 3021 case DRM_FORMAT_XRGB2101010:
c34ce3d1 3022 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 3023 case DRM_FORMAT_XBGR2101010:
c34ce3d1 3024 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 3025 case DRM_FORMAT_YUYV:
c34ce3d1 3026 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3027 case DRM_FORMAT_YVYU:
c34ce3d1 3028 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3029 case DRM_FORMAT_UYVY:
c34ce3d1 3030 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3031 case DRM_FORMAT_VYUY:
c34ce3d1 3032 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3033 default:
4249eeef 3034 MISSING_CASE(pixel_format);
70d21f0e 3035 }
8cfcba41 3036
c34ce3d1 3037 return 0;
6156a456 3038}
70d21f0e 3039
6156a456
CK		 3040u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3041{
6156a456 3042 switch (fb_modifier) {
30af77c4 3043 case DRM_FORMAT_MOD_NONE:
70d21f0e 3044 break;
30af77c4 3045 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3046 return PLANE_CTL_TILED_X;
b321803d 3047 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3048 return PLANE_CTL_TILED_Y;
b321803d 3049 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3050 return PLANE_CTL_TILED_YF;
70d21f0e 3051 default:
6156a456 3052 MISSING_CASE(fb_modifier);
70d21f0e 3053 }
8cfcba41 3054
c34ce3d1 3055 return 0;
6156a456 3056}
70d21f0e 3057
6156a456
CK		 3058u32 skl_plane_ctl_rotation(unsigned int rotation)
3059{
3b7a5119 3060 switch (rotation) {
6156a456
CK		 3061 case BIT(DRM_ROTATE_0):
3062 break;
1e8df167
SJ		 3063 /*
3064 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3065 * while i915 HW rotation is clockwise, thats why this swapping.
3066 */
3b7a5119 3067 case BIT(DRM_ROTATE_90):
1e8df167 3068 return PLANE_CTL_ROTATE_270;
3b7a5119 3069 case BIT(DRM_ROTATE_180):
c34ce3d1 3070 return PLANE_CTL_ROTATE_180;
3b7a5119 3071 case BIT(DRM_ROTATE_270):
1e8df167 3072 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3073 default:
3074 MISSING_CASE(rotation);
3075 }
3076
c34ce3d1 3077 return 0;
6156a456
CK		 3078}
3079
3080static void skylake_update_primary_plane(struct drm_crtc *crtc,
3081 struct drm_framebuffer *fb,
3082 int x, int y)
3083{
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3087 struct drm_plane *plane = crtc->primary;
3088 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3089 struct drm_i915_gem_object *obj;
3090 int pipe = intel_crtc->pipe;
3091 u32 plane_ctl, stride_div, stride;
3092 u32 tile_height, plane_offset, plane_size;
3093 unsigned int rotation;
3094 int x_offset, y_offset;
3095 unsigned long surf_addr;
6156a456
CK		 3096 struct intel_crtc_state *crtc_state = intel_crtc->config;
3097 struct intel_plane_state *plane_state;
3098 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3099 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3100 int scaler_id = -1;
3101
6156a456
CK		 3102 plane_state = to_intel_plane_state(plane->state);
3103
b70709a6 3104 if (!visible || !fb) {
6156a456
CK		 3105 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3106 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3107 POSTING_READ(PLANE_CTL(pipe, 0));
3108 return;
3b7a5119 3109 }
70d21f0e 3110
6156a456
CK		 3111 plane_ctl = PLANE_CTL_ENABLE |
3112 PLANE_CTL_PIPE_GAMMA_ENABLE |
3113 PLANE_CTL_PIPE_CSC_ENABLE;
3114
3115 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3116 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3117 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3118
3119 rotation = plane->state->rotation;
3120 plane_ctl |= skl_plane_ctl_rotation(rotation);
3121
b321803d
DL		 3122 obj = intel_fb_obj(fb);
3123 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3124 fb->pixel_format);
dedf278c 3125 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3126
6156a456
CK		 3127 /*
3128 * FIXME: intel_plane_state->src, dst aren't set when transitional
3129 * update_plane helpers are called from legacy paths.
3130 * Once full atomic crtc is available, below check can be avoided.
3131 */
3132 if (drm_rect_width(&plane_state->src)) {
3133 scaler_id = plane_state->scaler_id;
3134 src_x = plane_state->src.x1 >> 16;
3135 src_y = plane_state->src.y1 >> 16;
3136 src_w = drm_rect_width(&plane_state->src) >> 16;
3137 src_h = drm_rect_height(&plane_state->src) >> 16;
3138 dst_x = plane_state->dst.x1;
3139 dst_y = plane_state->dst.y1;
3140 dst_w = drm_rect_width(&plane_state->dst);
3141 dst_h = drm_rect_height(&plane_state->dst);
3142
3143 WARN_ON(x != src_x || y != src_y);
3144 } else {
3145 src_w = intel_crtc->config->pipe_src_w;
3146 src_h = intel_crtc->config->pipe_src_h;
3147 }
3148
3b7a5119
SJ		 3149 if (intel_rotation_90_or_270(rotation)) {
3150 /* stride = Surface height in tiles */
2614f17d 3151 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3152 fb->modifier[0], 0);
3b7a5119 3153 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3154 x_offset = stride * tile_height - y - src_h;
3b7a5119 3155 y_offset = x;
6156a456 3156 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3157 } else {
3158 stride = fb->pitches[0] / stride_div;
3159 x_offset = x;
3160 y_offset = y;
6156a456 3161 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3162 }
3163 plane_offset = y_offset << 16 | x_offset;
b321803d 3164
2db3366b
PZ		 3165 intel_crtc->adjusted_x = x_offset;
3166 intel_crtc->adjusted_y = y_offset;
3167
70d21f0e 3168 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3169 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3170 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3171 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3172
3173 if (scaler_id >= 0) {
3174 uint32_t ps_ctrl = 0;
3175
3176 WARN_ON(!dst_w || !dst_h);
3177 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3178 crtc_state->scaler_state.scalers[scaler_id].mode;
3179 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3180 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3181 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3182 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3183 I915_WRITE(PLANE_POS(pipe, 0), 0);
3184 } else {
3185 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3186 }
3187
121920fa 3188 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3189
3190 POSTING_READ(PLANE_SURF(pipe, 0));
3191}
3192
17638cd6
JB		 3193/* Assume fb object is pinned & idle & fenced and just update base pointers */
3194static int
3195intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3196 int x, int y, enum mode_set_atomic state)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3200
ff2a3117 3201 if (dev_priv->fbc.disable_fbc)
7733b49b 3202 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3203
29b9bde6
DV		 3204 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3205
3206 return 0;
81255565
JB		 3207}
3208
7514747d 3209static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3210{
96a02917
VS		 3211 struct drm_crtc *crtc;
3212
70e1e0ec 3213 for_each_crtc(dev, crtc) {
96a02917
VS		 3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 enum plane plane = intel_crtc->plane;
3216
3217 intel_prepare_page_flip(dev, plane);
3218 intel_finish_page_flip_plane(dev, plane);
3219 }
7514747d
VS		 3220}
3221
3222static void intel_update_primary_planes(struct drm_device *dev)
3223{
7514747d 3224 struct drm_crtc *crtc;
96a02917 3225
70e1e0ec 3226 for_each_crtc(dev, crtc) {
11c22da6
ML		 3227 struct intel_plane *plane = to_intel_plane(crtc->primary);
3228 struct intel_plane_state *plane_state;
96a02917 3229
11c22da6
ML		 3230 drm_modeset_lock_crtc(crtc, &plane->base);
3231
3232 plane_state = to_intel_plane_state(plane->base.state);
3233
3234 if (plane_state->base.fb)
3235 plane->commit_plane(&plane->base, plane_state);
3236
3237 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3238 }
3239}
3240
7514747d
VS		 3241void intel_prepare_reset(struct drm_device *dev)
3242{
3243 /* no reset support for gen2 */
3244 if (IS_GEN2(dev))
3245 return;
3246
3247 /* reset doesn't touch the display */
3248 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3249 return;
3250
3251 drm_modeset_lock_all(dev);
f98ce92f
VS		 3252 /*
3253 * Disabling the crtcs gracefully seems nicer. Also the
3254 * g33 docs say we should at least disable all the planes.
3255 */
6b72d486 3256 intel_display_suspend(dev);
7514747d
VS		 3257}
3258
3259void intel_finish_reset(struct drm_device *dev)
3260{
3261 struct drm_i915_private *dev_priv = to_i915(dev);
3262
3263 /*
3264 * Flips in the rings will be nuked by the reset,
3265 * so complete all pending flips so that user space
3266 * will get its events and not get stuck.
3267 */
3268 intel_complete_page_flips(dev);
3269
3270 /* no reset support for gen2 */
3271 if (IS_GEN2(dev))
3272 return;
3273
3274 /* reset doesn't touch the display */
3275 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3276 /*
3277 * Flips in the rings have been nuked by the reset,
3278 * so update the base address of all primary
3279 * planes to the the last fb to make sure we're
3280 * showing the correct fb after a reset.
11c22da6
ML		 3281 *
3282 * FIXME: Atomic will make this obsolete since we won't schedule
3283 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3284 */
3285 intel_update_primary_planes(dev);
3286 return;
3287 }
3288
3289 /*
3290 * The display has been reset as well,
3291 * so need a full re-initialization.
3292 */
3293 intel_runtime_pm_disable_interrupts(dev_priv);
3294 intel_runtime_pm_enable_interrupts(dev_priv);
3295
3296 intel_modeset_init_hw(dev);
3297
3298 spin_lock_irq(&dev_priv->irq_lock);
3299 if (dev_priv->display.hpd_irq_setup)
3300 dev_priv->display.hpd_irq_setup(dev);
3301 spin_unlock_irq(&dev_priv->irq_lock);
3302
043e9bda 3303 intel_display_resume(dev);
7514747d
VS		 3304
3305 intel_hpd_init(dev_priv);
3306
3307 drm_modeset_unlock_all(dev);
3308}
3309
2e2f351d 3310static void
14667a4b
CW		 3311intel_finish_fb(struct drm_framebuffer *old_fb)
3312{
2ff8fde1 3313 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3314 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3315 bool was_interruptible = dev_priv->mm.interruptible;
3316 int ret;
3317
14667a4b
CW		 3318 /* Big Hammer, we also need to ensure that any pending
3319 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3320 * current scanout is retired before unpinning the old
2e2f351d
CW		 3321 * framebuffer. Note that we rely on userspace rendering
3322 * into the buffer attached to the pipe they are waiting
3323 * on. If not, userspace generates a GPU hang with IPEHR
3324 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3325 *
3326 * This should only fail upon a hung GPU, in which case we
3327 * can safely continue.
3328 */
3329 dev_priv->mm.interruptible = false;
2e2f351d 3330 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3331 dev_priv->mm.interruptible = was_interruptible;
3332
2e2f351d 3333 WARN_ON(ret);
14667a4b
CW		 3334}
3335
7d5e3799
CW		 3336static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3341 bool pending;
3342
3343 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3344 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3345 return false;
3346
5e2d7afc 3347 spin_lock_irq(&dev->event_lock);
7d5e3799 3348 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3349 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3350
3351 return pending;
3352}
3353
bfd16b2a
ML		 3354static void intel_update_pipe_config(struct intel_crtc *crtc,
3355 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3356{
3357 struct drm_device *dev = crtc->base.dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3359 struct intel_crtc_state *pipe_config =
3360 to_intel_crtc_state(crtc->base.state);
e30e8f75 3361
bfd16b2a
ML		 3362 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3363 crtc->base.mode = crtc->base.state->mode;
3364
3365 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3366 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3367 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3368
44522d85
ML		 3369 if (HAS_DDI(dev))
3370 intel_set_pipe_csc(&crtc->base);
3371
e30e8f75
GP		 3372 /*
3373 * Update pipe size and adjust fitter if needed: the reason for this is
3374 * that in compute_mode_changes we check the native mode (not the pfit
3375 * mode) to see if we can flip rather than do a full mode set. In the
3376 * fastboot case, we'll flip, but if we don't update the pipesrc and
3377 * pfit state, we'll end up with a big fb scanned out into the wrong
3378 * sized surface.
e30e8f75
GP		 3379 */
3380
e30e8f75 3381 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3382 ((pipe_config->pipe_src_w - 1) << 16) |
3383 (pipe_config->pipe_src_h - 1));
3384
3385 /* on skylake this is done by detaching scalers */
3386 if (INTEL_INFO(dev)->gen >= 9) {
3387 skl_detach_scalers(crtc);
3388
3389 if (pipe_config->pch_pfit.enabled)
3390 skylake_pfit_enable(crtc);
3391 } else if (HAS_PCH_SPLIT(dev)) {
3392 if (pipe_config->pch_pfit.enabled)
3393 ironlake_pfit_enable(crtc);
3394 else if (old_crtc_state->pch_pfit.enabled)
3395 ironlake_pfit_disable(crtc, true);
e30e8f75 3396 }
e30e8f75
GP		 3397}
3398
5e84e1a4
ZW		 3399static void intel_fdi_normal_train(struct drm_crtc *crtc)
3400{
3401 struct drm_device *dev = crtc->dev;
3402 struct drm_i915_private *dev_priv = dev->dev_private;
3403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3404 int pipe = intel_crtc->pipe;
3405 u32 reg, temp;
3406
3407 /* enable normal train */
3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
61e499bf 3410 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3413 } else {
3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3416 }
5e84e1a4
ZW		 3417 I915_WRITE(reg, temp);
3418
3419 reg = FDI_RX_CTL(pipe);
3420 temp = I915_READ(reg);
3421 if (HAS_PCH_CPT(dev)) {
3422 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3423 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3424 } else {
3425 temp &= ~FDI_LINK_TRAIN_NONE;
3426 temp |= FDI_LINK_TRAIN_NONE;
3427 }
3428 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3429
3430 /* wait one idle pattern time */
3431 POSTING_READ(reg);
3432 udelay(1000);
357555c0
JB		 3433
3434 /* IVB wants error correction enabled */
3435 if (IS_IVYBRIDGE(dev))
3436 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3437 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3438}
3439
8db9d77b
ZW		 3440/* The FDI link training functions for ILK/Ibexpeak. */
3441static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3442{
3443 struct drm_device *dev = crtc->dev;
3444 struct drm_i915_private *dev_priv = dev->dev_private;
3445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3446 int pipe = intel_crtc->pipe;
5eddb70b 3447 u32 reg, temp, tries;
8db9d77b 3448
1c8562f6 3449 /* FDI needs bits from pipe first */
0fc932b8 3450 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3451
e1a44743
AJ		 3452 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3453 for train result */
5eddb70b
CW		 3454 reg = FDI_RX_IMR(pipe);
3455 temp = I915_READ(reg);
e1a44743
AJ		 3456 temp &= ~FDI_RX_SYMBOL_LOCK;
3457 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3458 I915_WRITE(reg, temp);
3459 I915_READ(reg);
e1a44743
AJ		 3460 udelay(150);
3461
8db9d77b 3462 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3463 reg = FDI_TX_CTL(pipe);
3464 temp = I915_READ(reg);
627eb5a3 3465 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3466 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3475 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3476
3477 POSTING_READ(reg);
8db9d77b
ZW		 3478 udelay(150);
3479
5b2adf89 3480 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3481 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3482 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3483 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3484
5eddb70b 3485 reg = FDI_RX_IIR(pipe);
e1a44743 3486 for (tries = 0; tries < 5; tries++) {
5eddb70b 3487 temp = I915_READ(reg);
8db9d77b
ZW		 3488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3489
3490 if ((temp & FDI_RX_BIT_LOCK)) {
3491 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3492 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3493 break;
3494 }
8db9d77b 3495 }
e1a44743 3496 if (tries == 5)
5eddb70b 3497 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3498
3499 /* Train 2 */
5eddb70b
CW		 3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
8db9d77b
ZW		 3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3504 I915_WRITE(reg, temp);
8db9d77b 3505
5eddb70b
CW		 3506 reg = FDI_RX_CTL(pipe);
3507 temp = I915_READ(reg);
8db9d77b
ZW		 3508 temp &= ~FDI_LINK_TRAIN_NONE;
3509 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3510 I915_WRITE(reg, temp);
8db9d77b 3511
5eddb70b
CW		 3512 POSTING_READ(reg);
3513 udelay(150);
8db9d77b 3514
5eddb70b 3515 reg = FDI_RX_IIR(pipe);
e1a44743 3516 for (tries = 0; tries < 5; tries++) {
5eddb70b 3517 temp = I915_READ(reg);
8db9d77b
ZW		 3518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3519
3520 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3521 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3522 DRM_DEBUG_KMS("FDI train 2 done.\n");
3523 break;
3524 }
8db9d77b 3525 }
e1a44743 3526 if (tries == 5)
5eddb70b 3527 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3528
3529 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3530
8db9d77b
ZW		 3531}
3532
0206e353 3533static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3534 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3535 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3536 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3537 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3538};
3539
3540/* The FDI link training functions for SNB/Cougarpoint. */
3541static void gen6_fdi_link_train(struct drm_crtc *crtc)
3542{
3543 struct drm_device *dev = crtc->dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 int pipe = intel_crtc->pipe;
fa37d39e 3547 u32 reg, temp, i, retry;
8db9d77b 3548
e1a44743
AJ		 3549 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3550 for train result */
5eddb70b
CW		 3551 reg = FDI_RX_IMR(pipe);
3552 temp = I915_READ(reg);
e1a44743
AJ		 3553 temp &= ~FDI_RX_SYMBOL_LOCK;
3554 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3555 I915_WRITE(reg, temp);
3556
3557 POSTING_READ(reg);
e1a44743
AJ		 3558 udelay(150);
3559
8db9d77b 3560 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
627eb5a3 3563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_1;
3567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3568 /* SNB-B */
3569 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3571
d74cf324
DV		 3572 I915_WRITE(FDI_RX_MISC(pipe),
3573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3574
5eddb70b
CW		 3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
8db9d77b
ZW		 3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3580 } else {
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_1;
3583 }
5eddb70b
CW		 3584 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(150);
3588
0206e353 3589 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
8db9d77b
ZW		 3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
8db9d77b
ZW		 3597 udelay(500);
3598
fa37d39e
SP		 3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_BIT_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done.\n");
3606 break;
3607 }
3608 udelay(50);
8db9d77b 3609 }
fa37d39e
SP		 3610 if (retry < 5)
3611 break;
8db9d77b
ZW		 3612 }
3613 if (i == 4)
5eddb70b 3614 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3615
3616 /* Train 2 */
5eddb70b
CW		 3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
8db9d77b
ZW		 3619 temp &= ~FDI_LINK_TRAIN_NONE;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2;
3621 if (IS_GEN6(dev)) {
3622 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3623 /* SNB-B */
3624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3625 }
5eddb70b 3626 I915_WRITE(reg, temp);
8db9d77b 3627
5eddb70b
CW		 3628 reg = FDI_RX_CTL(pipe);
3629 temp = I915_READ(reg);
8db9d77b
ZW		 3630 if (HAS_PCH_CPT(dev)) {
3631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3632 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3633 } else {
3634 temp &= ~FDI_LINK_TRAIN_NONE;
3635 temp |= FDI_LINK_TRAIN_PATTERN_2;
3636 }
5eddb70b
CW		 3637 I915_WRITE(reg, temp);
3638
3639 POSTING_READ(reg);
8db9d77b
ZW		 3640 udelay(150);
3641
0206e353 3642 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3643 reg = FDI_TX_CTL(pipe);
3644 temp = I915_READ(reg);
8db9d77b
ZW		 3645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3646 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3647 I915_WRITE(reg, temp);
3648
3649 POSTING_READ(reg);
8db9d77b
ZW		 3650 udelay(500);
3651
fa37d39e
SP		 3652 for (retry = 0; retry < 5; retry++) {
3653 reg = FDI_RX_IIR(pipe);
3654 temp = I915_READ(reg);
3655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3656 if (temp & FDI_RX_SYMBOL_LOCK) {
3657 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3658 DRM_DEBUG_KMS("FDI train 2 done.\n");
3659 break;
3660 }
3661 udelay(50);
8db9d77b 3662 }
fa37d39e
SP		 3663 if (retry < 5)
3664 break;
8db9d77b
ZW		 3665 }
3666 if (i == 4)
5eddb70b 3667 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3668
3669 DRM_DEBUG_KMS("FDI train done.\n");
3670}
3671
357555c0
JB		 3672/* Manual link training for Ivy Bridge A0 parts */
3673static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3674{
3675 struct drm_device *dev = crtc->dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
3677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3678 int pipe = intel_crtc->pipe;
139ccd3f 3679 u32 reg, temp, i, j;
357555c0
JB		 3680
3681 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3682 for train result */
3683 reg = FDI_RX_IMR(pipe);
3684 temp = I915_READ(reg);
3685 temp &= ~FDI_RX_SYMBOL_LOCK;
3686 temp &= ~FDI_RX_BIT_LOCK;
3687 I915_WRITE(reg, temp);
3688
3689 POSTING_READ(reg);
3690 udelay(150);
3691
01a415fd
DV		 3692 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3693 I915_READ(FDI_RX_IIR(pipe)));
3694
139ccd3f
JB		 3695 /* Try each vswing and preemphasis setting twice before moving on */
3696 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3697 /* disable first in case we need to retry */
3698 reg = FDI_TX_CTL(pipe);
3699 temp = I915_READ(reg);
3700 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3701 temp &= ~FDI_TX_ENABLE;
3702 I915_WRITE(reg, temp);
357555c0 3703
139ccd3f
JB		 3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp &= ~FDI_LINK_TRAIN_AUTO;
3707 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3708 temp &= ~FDI_RX_ENABLE;
3709 I915_WRITE(reg, temp);
357555c0 3710
139ccd3f 3711 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3712 reg = FDI_TX_CTL(pipe);
3713 temp = I915_READ(reg);
139ccd3f 3714 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3715 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3716 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3717 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3718 temp |= snb_b_fdi_train_param[j/2];
3719 temp |= FDI_COMPOSITE_SYNC;
3720 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3721
139ccd3f
JB		 3722 I915_WRITE(FDI_RX_MISC(pipe),
3723 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3724
139ccd3f 3725 reg = FDI_RX_CTL(pipe);
357555c0 3726 temp = I915_READ(reg);
139ccd3f
JB		 3727 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728 temp |= FDI_COMPOSITE_SYNC;
3729 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3730
139ccd3f
JB		 3731 POSTING_READ(reg);
3732 udelay(1); /* should be 0.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_BIT_LOCK ||
3740 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3742 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3743 i);
3744 break;
3745 }
3746 udelay(1); /* should be 0.5us */
3747 }
3748 if (i == 4) {
3749 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3750 continue;
3751 }
357555c0 3752
139ccd3f 3753 /* Train 2 */
357555c0
JB		 3754 reg = FDI_TX_CTL(pipe);
3755 temp = I915_READ(reg);
139ccd3f
JB		 3756 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3757 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3758 I915_WRITE(reg, temp);
3759
3760 reg = FDI_RX_CTL(pipe);
3761 temp = I915_READ(reg);
3762 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3763 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3764 I915_WRITE(reg, temp);
3765
3766 POSTING_READ(reg);
139ccd3f 3767 udelay(2); /* should be 1.5us */
357555c0 3768
139ccd3f
JB		 3769 for (i = 0; i < 4; i++) {
3770 reg = FDI_RX_IIR(pipe);
3771 temp = I915_READ(reg);
3772 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3773
139ccd3f
JB		 3774 if (temp & FDI_RX_SYMBOL_LOCK ||
3775 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3776 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3777 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3778 i);
3779 goto train_done;
3780 }
3781 udelay(2); /* should be 1.5us */
357555c0 3782 }
139ccd3f
JB		 3783 if (i == 4)
3784 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3785 }
357555c0 3786
139ccd3f 3787train_done:
357555c0
JB		 3788 DRM_DEBUG_KMS("FDI train done.\n");
3789}
3790
88cefb6c 3791static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3792{
88cefb6c 3793 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3794 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3795 int pipe = intel_crtc->pipe;
5eddb70b 3796 u32 reg, temp;
79e53945 3797
c64e311e 3798
c98e9dcf 3799 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3800 reg = FDI_RX_CTL(pipe);
3801 temp = I915_READ(reg);
627eb5a3 3802 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3803 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3804 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3805 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3806
3807 POSTING_READ(reg);
c98e9dcf
JB		 3808 udelay(200);
3809
3810 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3811 temp = I915_READ(reg);
3812 I915_WRITE(reg, temp | FDI_PCDCLK);
3813
3814 POSTING_READ(reg);
c98e9dcf
JB		 3815 udelay(200);
3816
20749730
PZ		 3817 /* Enable CPU FDI TX PLL, always on for Ironlake */
3818 reg = FDI_TX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3821 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3822
20749730
PZ		 3823 POSTING_READ(reg);
3824 udelay(100);
6be4a607 3825 }
0e23b99d
JB		 3826}
3827
88cefb6c
DV		 3828static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3829{
3830 struct drm_device *dev = intel_crtc->base.dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 int pipe = intel_crtc->pipe;
3833 u32 reg, temp;
3834
3835 /* Switch from PCDclk to Rawclk */
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3839
3840 /* Disable CPU FDI TX PLL */
3841 reg = FDI_TX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3844
3845 POSTING_READ(reg);
3846 udelay(100);
3847
3848 reg = FDI_RX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3851
3852 /* Wait for the clocks to turn off. */
3853 POSTING_READ(reg);
3854 udelay(100);
3855}
3856
0fc932b8
JB		 3857static void ironlake_fdi_disable(struct drm_crtc *crtc)
3858{
3859 struct drm_device *dev = crtc->dev;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3862 int pipe = intel_crtc->pipe;
3863 u32 reg, temp;
3864
3865 /* disable CPU FDI tx and PCH FDI rx */
3866 reg = FDI_TX_CTL(pipe);
3867 temp = I915_READ(reg);
3868 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3869 POSTING_READ(reg);
3870
3871 reg = FDI_RX_CTL(pipe);
3872 temp = I915_READ(reg);
3873 temp &= ~(0x7 << 16);
dfd07d72 3874 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3875 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3876
3877 POSTING_READ(reg);
3878 udelay(100);
3879
3880 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3881 if (HAS_PCH_IBX(dev))
6f06ce18 3882 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3883
3884 /* still set train pattern 1 */
3885 reg = FDI_TX_CTL(pipe);
3886 temp = I915_READ(reg);
3887 temp &= ~FDI_LINK_TRAIN_NONE;
3888 temp |= FDI_LINK_TRAIN_PATTERN_1;
3889 I915_WRITE(reg, temp);
3890
3891 reg = FDI_RX_CTL(pipe);
3892 temp = I915_READ(reg);
3893 if (HAS_PCH_CPT(dev)) {
3894 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3895 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3896 } else {
3897 temp &= ~FDI_LINK_TRAIN_NONE;
3898 temp |= FDI_LINK_TRAIN_PATTERN_1;
3899 }
3900 /* BPC in FDI rx is consistent with that in PIPECONF */
3901 temp &= ~(0x07 << 16);
dfd07d72 3902 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3903 I915_WRITE(reg, temp);
3904
3905 POSTING_READ(reg);
3906 udelay(100);
3907}
3908
5dce5b93
CW		 3909bool intel_has_pending_fb_unpin(struct drm_device *dev)
3910{
3911 struct intel_crtc *crtc;
3912
3913 /* Note that we don't need to be called with mode_config.lock here
3914 * as our list of CRTC objects is static for the lifetime of the
3915 * device and so cannot disappear as we iterate. Similarly, we can
3916 * happily treat the predicates as racy, atomic checks as userspace
3917 * cannot claim and pin a new fb without at least acquring the
3918 * struct_mutex and so serialising with us.
3919 */
d3fcc808 3920 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3921 if (atomic_read(&crtc->unpin_work_count) == 0)
3922 continue;
3923
3924 if (crtc->unpin_work)
3925 intel_wait_for_vblank(dev, crtc->pipe);
3926
3927 return true;
3928 }
3929
3930 return false;
3931}
3932
d6bbafa1
CW		 3933static void page_flip_completed(struct intel_crtc *intel_crtc)
3934{
3935 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3936 struct intel_unpin_work *work = intel_crtc->unpin_work;
3937
3938 /* ensure that the unpin work is consistent wrt ->pending. */
3939 smp_rmb();
3940 intel_crtc->unpin_work = NULL;
3941
3942 if (work->event)
3943 drm_send_vblank_event(intel_crtc->base.dev,
3944 intel_crtc->pipe,
3945 work->event);
3946
3947 drm_crtc_vblank_put(&intel_crtc->base);
3948
3949 wake_up_all(&dev_priv->pending_flip_queue);
3950 queue_work(dev_priv->wq, &work->work);
3951
3952 trace_i915_flip_complete(intel_crtc->plane,
3953 work->pending_flip_obj);
3954}
3955
46a55d30 3956void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3957{
0f91128d 3958 struct drm_device *dev = crtc->dev;
5bb61643 3959 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3960
2c10d571 3961 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3962 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3963 !intel_crtc_has_pending_flip(crtc),
3964 60*HZ) == 0)) {
3965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3966
5e2d7afc 3967 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3968 if (intel_crtc->unpin_work) {
3969 WARN_ONCE(1, "Removing stuck page flip\n");
3970 page_flip_completed(intel_crtc);
3971 }
5e2d7afc 3972 spin_unlock_irq(&dev->event_lock);
9c787942 3973 }
5bb61643 3974
975d568a
CW		 3975 if (crtc->primary->fb) {
3976 mutex_lock(&dev->struct_mutex);
3977 intel_finish_fb(crtc->primary->fb);
3978 mutex_unlock(&dev->struct_mutex);
3979 }
e6c3a2a6
CW		 3980}
3981
e615efe4
ED		 3982/* Program iCLKIP clock to the desired frequency */
3983static void lpt_program_iclkip(struct drm_crtc *crtc)
3984{
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3987 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3988 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3989 u32 temp;
3990
a580516d 3991 mutex_lock(&dev_priv->sb_lock);
09153000 3992
e615efe4
ED		 3993 /* It is necessary to ungate the pixclk gate prior to programming
3994 * the divisors, and gate it back when it is done.
3995 */
3996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3997
3998 /* Disable SSCCTL */
3999 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 4000 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
4001 SBI_SSCCTL_DISABLE,
4002 SBI_ICLK);
e615efe4
ED		 4003
4004 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 4005 if (clock == 20000) {
e615efe4
ED		 4006 auxdiv = 1;
4007 divsel = 0x41;
4008 phaseinc = 0x20;
4009 } else {
4010 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 4011 * but the adjusted_mode->crtc_clock in in KHz. To get the
4012 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 4013 * convert the virtual clock precision to KHz here for higher
4014 * precision.
4015 */
4016 u32 iclk_virtual_root_freq = 172800 * 1000;
4017 u32 iclk_pi_range = 64;
4018 u32 desired_divisor, msb_divisor_value, pi_value;
4019
12d7ceed 4020 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 4021 msb_divisor_value = desired_divisor / iclk_pi_range;
4022 pi_value = desired_divisor % iclk_pi_range;
4023
4024 auxdiv = 0;
4025 divsel = msb_divisor_value - 2;
4026 phaseinc = pi_value;
4027 }
4028
4029 /* This should not happen with any sane values */
4030 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4031 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4032 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4033 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4034
4035 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4036 clock,
e615efe4
ED		 4037 auxdiv,
4038 divsel,
4039 phasedir,
4040 phaseinc);
4041
4042 /* Program SSCDIVINTPHASE6 */
988d6ee8 4043 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4044 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4045 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4046 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4047 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4048 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4049 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4050 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4051
4052 /* Program SSCAUXDIV */
988d6ee8 4053 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4054 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4055 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4056 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4057
4058 /* Enable modulator and associated divider */
988d6ee8 4059 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4060 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4061 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4062
4063 /* Wait for initialization time */
4064 udelay(24);
4065
4066 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4067
a580516d 4068 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4069}
4070
275f01b2
DV		 4071static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4072 enum pipe pch_transcoder)
4073{
4074 struct drm_device *dev = crtc->base.dev;
4075 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4076 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4077
4078 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4079 I915_READ(HTOTAL(cpu_transcoder)));
4080 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4081 I915_READ(HBLANK(cpu_transcoder)));
4082 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4083 I915_READ(HSYNC(cpu_transcoder)));
4084
4085 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4086 I915_READ(VTOTAL(cpu_transcoder)));
4087 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4088 I915_READ(VBLANK(cpu_transcoder)));
4089 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4090 I915_READ(VSYNC(cpu_transcoder)));
4091 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4092 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4093}
4094
003632d9 4095static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4096{
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098 uint32_t temp;
4099
4100 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4101 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4102 return;
4103
4104 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4105 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4106
003632d9
ACO		 4107 temp &= ~FDI_BC_BIFURCATION_SELECT;
4108 if (enable)
4109 temp |= FDI_BC_BIFURCATION_SELECT;
4110
4111 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4112 I915_WRITE(SOUTH_CHICKEN1, temp);
4113 POSTING_READ(SOUTH_CHICKEN1);
4114}
4115
4116static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4117{
4118 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4119
4120 switch (intel_crtc->pipe) {
4121 case PIPE_A:
4122 break;
4123 case PIPE_B:
6e3c9717 4124 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4125 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4126 else
003632d9 4127 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4128
4129 break;
4130 case PIPE_C:
003632d9 4131 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4132
4133 break;
4134 default:
4135 BUG();
4136 }
4137}
4138
f67a559d
JB		 4139/*
4140 * Enable PCH resources required for PCH ports:
4141 * - PCH PLLs
4142 * - FDI training & RX/TX
4143 * - update transcoder timings
4144 * - DP transcoding bits
4145 * - transcoder
4146 */
4147static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4148{
4149 struct drm_device *dev = crtc->dev;
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4152 int pipe = intel_crtc->pipe;
ee7b9f93 4153 u32 reg, temp;
2c07245f 4154
ab9412ba 4155 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4156
1fbc0d78
DV		 4157 if (IS_IVYBRIDGE(dev))
4158 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4159
cd986abb
DV		 4160 /* Write the TU size bits before fdi link training, so that error
4161 * detection works. */
4162 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4163 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4164
c98e9dcf 4165 /* For PCH output, training FDI link */
674cf967 4166 dev_priv->display.fdi_link_train(crtc);
2c07245f 4167
3ad8a208
DV		 4168 /* We need to program the right clock selection before writing the pixel
4169 * mutliplier into the DPLL. */
303b81e0 4170 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4171 u32 sel;
4b645f14 4172
c98e9dcf 4173 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4174 temp |= TRANS_DPLL_ENABLE(pipe);
4175 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4176 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4177 temp |= sel;
4178 else
4179 temp &= ~sel;
c98e9dcf 4180 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4181 }
5eddb70b 4182
3ad8a208
DV		 4183 /* XXX: pch pll's can be enabled any time before we enable the PCH
4184 * transcoder, and we actually should do this to not upset any PCH
4185 * transcoder that already use the clock when we share it.
4186 *
4187 * Note that enable_shared_dpll tries to do the right thing, but
4188 * get_shared_dpll unconditionally resets the pll - we need that to have
4189 * the right LVDS enable sequence. */
85b3894f 4190 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4191
d9b6cb56
JB		 4192 /* set transcoder timing, panel must allow it */
4193 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4194 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4195
303b81e0 4196 intel_fdi_normal_train(crtc);
5e84e1a4 4197
c98e9dcf 4198 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4199 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4200 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4201 reg = TRANS_DP_CTL(pipe);
4202 temp = I915_READ(reg);
4203 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4204 TRANS_DP_SYNC_MASK |
4205 TRANS_DP_BPC_MASK);
e3ef4479 4206 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4207 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4208
4209 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4210 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4211 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4212 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4213
4214 switch (intel_trans_dp_port_sel(crtc)) {
4215 case PCH_DP_B:
5eddb70b 4216 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4217 break;
4218 case PCH_DP_C:
5eddb70b 4219 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4220 break;
4221 case PCH_DP_D:
5eddb70b 4222 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4223 break;
4224 default:
e95d41e1 4225 BUG();
32f9d658 4226 }
2c07245f 4227
5eddb70b 4228 I915_WRITE(reg, temp);
6be4a607 4229 }
b52eb4dc 4230
b8a4f404 4231 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4232}
4233
1507e5bd
PZ		 4234static void lpt_pch_enable(struct drm_crtc *crtc)
4235{
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4239 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4240
ab9412ba 4241 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4242
8c52b5e8 4243 lpt_program_iclkip(crtc);
1507e5bd 4244
0540e488 4245 /* Set transcoder timing. */
275f01b2 4246 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4247
937bb610 4248 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4249}
4250
190f68c5
ACO		 4251struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252 struct intel_crtc_state *crtc_state)
ee7b9f93 4253{
e2b78267 4254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4255 struct intel_shared_dpll *pll;
de419ab6 4256 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4257 enum intel_dpll_id i;
ee7b9f93 4258
de419ab6
ML		 4259 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4260
98b6bd99
DV		 4261 if (HAS_PCH_IBX(dev_priv->dev)) {
4262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4263 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4264 pll = &dev_priv->shared_dplls[i];
98b6bd99 4265
46edb027
DV		 4266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4267 crtc->base.base.id, pll->name);
98b6bd99 4268
de419ab6 4269 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4270
98b6bd99
DV		 4271 goto found;
4272 }
4273
bcddf610
S		 4274 if (IS_BROXTON(dev_priv->dev)) {
4275 /* PLL is attached to port in bxt */
4276 struct intel_encoder *encoder;
4277 struct intel_digital_port *intel_dig_port;
4278
4279 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4280 if (WARN_ON(!encoder))
4281 return NULL;
4282
4283 intel_dig_port = enc_to_dig_port(&encoder->base);
4284 /* 1:1 mapping between ports and PLLs */
4285 i = (enum intel_dpll_id)intel_dig_port->port;
4286 pll = &dev_priv->shared_dplls[i];
4287 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288 crtc->base.base.id, pll->name);
de419ab6 4289 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4290
4291 goto found;
4292 }
4293
e72f9fbf
DV		 4294 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4295 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4296
4297 /* Only want to check enabled timings first */
de419ab6 4298 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4299 continue;
4300
190f68c5 4301 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4302 &shared_dpll[i].hw_state,
4303 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4304 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4305 crtc->base.base.id, pll->name,
de419ab6 4306 shared_dpll[i].crtc_mask,
8bd31e67 4307 pll->active);
ee7b9f93
JB		 4308 goto found;
4309 }
4310 }
4311
4312 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4313 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4314 pll = &dev_priv->shared_dplls[i];
de419ab6 4315 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4316 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4317 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4318 goto found;
4319 }
4320 }
4321
4322 return NULL;
4323
4324found:
de419ab6
ML		 4325 if (shared_dpll[i].crtc_mask == 0)
4326 shared_dpll[i].hw_state =
4327 crtc_state->dpll_hw_state;
f2a69f44 4328
190f68c5 4329 crtc_state->shared_dpll = i;
46edb027
DV		 4330 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4331 pipe_name(crtc->pipe));
ee7b9f93 4332
de419ab6 4333 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4334
ee7b9f93
JB		 4335 return pll;
4336}
4337
de419ab6 4338static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4339{
de419ab6
ML		 4340 struct drm_i915_private *dev_priv = to_i915(state->dev);
4341 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4342 struct intel_shared_dpll *pll;
4343 enum intel_dpll_id i;
4344
de419ab6
ML		 4345 if (!to_intel_atomic_state(state)->dpll_set)
4346 return;
8bd31e67 4347
de419ab6 4348 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
de419ab6 4351 pll->config = shared_dpll[i];
8bd31e67
ACO		 4352 }
4353}
4354
a1520318 4355static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4356{
4357 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4358 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4359 u32 temp;
4360
4361 temp = I915_READ(dslreg);
4362 udelay(500);
4363 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4364 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4365 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4366 }
4367}
4368
86adf9d7
ML		 4369static int
4370skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4371 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4372 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4373{
86adf9d7
ML		 4374 struct intel_crtc_scaler_state *scaler_state =
4375 &crtc_state->scaler_state;
4376 struct intel_crtc *intel_crtc =
4377 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4378 int need_scaling;
6156a456
CK		 4379
4380 need_scaling = intel_rotation_90_or_270(rotation) ?
4381 (src_h != dst_w || src_w != dst_h):
4382 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4383
4384 /*
4385 * if plane is being disabled or scaler is no more required or force detach
4386 * - free scaler binded to this plane/crtc
4387 * - in order to do this, update crtc->scaler_usage
4388 *
4389 * Here scaler state in crtc_state is set free so that
4390 * scaler can be assigned to other user. Actual register
4391 * update to free the scaler is done in plane/panel-fit programming.
4392 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4393 */
86adf9d7 4394 if (force_detach || !need_scaling) {
a1b2278e 4395 if (*scaler_id >= 0) {
86adf9d7 4396 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4397 scaler_state->scalers[*scaler_id].in_use = 0;
4398
86adf9d7
ML		 4399 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4400 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4401 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4402 scaler_state->scaler_users);
4403 *scaler_id = -1;
4404 }
4405 return 0;
4406 }
4407
4408 /* range checks */
4409 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4410 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4411
4412 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4413 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4414 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4415 "size is out of scaler range\n",
86adf9d7 4416 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4417 return -EINVAL;
4418 }
4419
86adf9d7
ML		 4420 /* mark this plane as a scaler user in crtc_state */
4421 scaler_state->scaler_users |= (1 << scaler_user);
4422 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4424 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4425 scaler_state->scaler_users);
4426
4427 return 0;
4428}
4429
4430/**
4431 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4432 *
4433 * @state: crtc's scaler state
86adf9d7
ML		 4434 *
4435 * Return
4436 * 0 - scaler_usage updated successfully
4437 * error - requested scaling cannot be supported or other error condition
4438 */
e435d6e5 4439int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4440{
4441 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4442 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4443
4444 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4445 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4446
e435d6e5 4447 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4448 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4449 state->pipe_src_w, state->pipe_src_h,
aad941d5 4450 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4451}
4452
4453/**
4454 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4455 *
4456 * @state: crtc's scaler state
86adf9d7
ML		 4457 * @plane_state: atomic plane state to update
4458 *
4459 * Return
4460 * 0 - scaler_usage updated successfully
4461 * error - requested scaling cannot be supported or other error condition
4462 */
da20eabd
ML		 4463static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4464 struct intel_plane_state *plane_state)
86adf9d7
ML		 4465{
4466
4467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4468 struct intel_plane *intel_plane =
4469 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4470 struct drm_framebuffer *fb = plane_state->base.fb;
4471 int ret;
4472
4473 bool force_detach = !fb || !plane_state->visible;
4474
4475 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4476 intel_plane->base.base.id, intel_crtc->pipe,
4477 drm_plane_index(&intel_plane->base));
4478
4479 ret = skl_update_scaler(crtc_state, force_detach,
4480 drm_plane_index(&intel_plane->base),
4481 &plane_state->scaler_id,
4482 plane_state->base.rotation,
4483 drm_rect_width(&plane_state->src) >> 16,
4484 drm_rect_height(&plane_state->src) >> 16,
4485 drm_rect_width(&plane_state->dst),
4486 drm_rect_height(&plane_state->dst));
4487
4488 if (ret || plane_state->scaler_id < 0)
4489 return ret;
4490
a1b2278e 4491 /* check colorkey */
818ed961 4492 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4493 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4494 intel_plane->base.base.id);
a1b2278e
CK		 4495 return -EINVAL;
4496 }
4497
4498 /* Check src format */
86adf9d7
ML		 4499 switch (fb->pixel_format) {
4500 case DRM_FORMAT_RGB565:
4501 case DRM_FORMAT_XBGR8888:
4502 case DRM_FORMAT_XRGB8888:
4503 case DRM_FORMAT_ABGR8888:
4504 case DRM_FORMAT_ARGB8888:
4505 case DRM_FORMAT_XRGB2101010:
4506 case DRM_FORMAT_XBGR2101010:
4507 case DRM_FORMAT_YUYV:
4508 case DRM_FORMAT_YVYU:
4509 case DRM_FORMAT_UYVY:
4510 case DRM_FORMAT_VYUY:
4511 break;
4512 default:
4513 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4514 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4515 return -EINVAL;
a1b2278e
CK		 4516 }
4517
a1b2278e
CK		 4518 return 0;
4519}
4520
e435d6e5
ML		 4521static void skylake_scaler_disable(struct intel_crtc *crtc)
4522{
4523 int i;
4524
4525 for (i = 0; i < crtc->num_scalers; i++)
4526 skl_detach_scaler(crtc, i);
4527}
4528
4529static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4530{
4531 struct drm_device *dev = crtc->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 int pipe = crtc->pipe;
a1b2278e
CK		 4534 struct intel_crtc_scaler_state *scaler_state =
4535 &crtc->config->scaler_state;
4536
4537 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4538
6e3c9717 4539 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4540 int id;
4541
4542 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4543 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4544 return;
4545 }
4546
4547 id = scaler_state->scaler_id;
4548 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4549 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4550 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4551 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4552
4553 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4554 }
4555}
4556
b074cec8
JB		 4557static void ironlake_pfit_enable(struct intel_crtc *crtc)
4558{
4559 struct drm_device *dev = crtc->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 int pipe = crtc->pipe;
4562
6e3c9717 4563 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4564 /* Force use of hard-coded filter coefficients
4565 * as some pre-programmed values are broken,
4566 * e.g. x201.
4567 */
4568 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4569 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4570 PF_PIPE_SEL_IVB(pipe));
4571 else
4572 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4573 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4574 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4575 }
4576}
4577
20bc8673 4578void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4579{
cea165c3
VS		 4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4582
6e3c9717 4583 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4584 return;
4585
cea165c3
VS		 4586 /* We can only enable IPS after we enable a plane and wait for a vblank */
4587 intel_wait_for_vblank(dev, crtc->pipe);
4588
d77e4531 4589 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4590 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4591 mutex_lock(&dev_priv->rps.hw_lock);
4592 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4593 mutex_unlock(&dev_priv->rps.hw_lock);
4594 /* Quoting Art Runyan: "its not safe to expect any particular
4595 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4596 * mailbox." Moreover, the mailbox may return a bogus state,
4597 * so we need to just enable it and continue on.
2a114cc1
BW		 4598 */
4599 } else {
4600 I915_WRITE(IPS_CTL, IPS_ENABLE);
4601 /* The bit only becomes 1 in the next vblank, so this wait here
4602 * is essentially intel_wait_for_vblank. If we don't have this
4603 * and don't wait for vblanks until the end of crtc_enable, then
4604 * the HW state readout code will complain that the expected
4605 * IPS_CTL value is not the one we read. */
4606 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4607 DRM_ERROR("Timed out waiting for IPS enable\n");
4608 }
d77e4531
PZ		 4609}
4610
20bc8673 4611void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4612{
4613 struct drm_device *dev = crtc->base.dev;
4614 struct drm_i915_private *dev_priv = dev->dev_private;
4615
6e3c9717 4616 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4617 return;
4618
4619 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4620 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4621 mutex_lock(&dev_priv->rps.hw_lock);
4622 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4623 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4624 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4625 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4626 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4627 } else {
2a114cc1 4628 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4629 POSTING_READ(IPS_CTL);
4630 }
d77e4531
PZ		 4631
4632 /* We need to wait for a vblank before we can disable the plane. */
4633 intel_wait_for_vblank(dev, crtc->pipe);
4634}
4635
4636/** Loads the palette/gamma unit for the CRTC with the prepared values */
4637static void intel_crtc_load_lut(struct drm_crtc *crtc)
4638{
4639 struct drm_device *dev = crtc->dev;
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4642 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4643 int i;
4644 bool reenable_ips = false;
4645
4646 /* The clocks have to be on to load the palette. */
53d9f4e9 4647 if (!crtc->state->active)
d77e4531
PZ		 4648 return;
4649
50360403 4650 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4651 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4652 assert_dsi_pll_enabled(dev_priv);
4653 else
4654 assert_pll_enabled(dev_priv, pipe);
4655 }
4656
d77e4531
PZ		 4657 /* Workaround : Do not read or write the pipe palette/gamma data while
4658 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4659 */
6e3c9717 4660 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4661 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4662 GAMMA_MODE_MODE_SPLIT)) {
4663 hsw_disable_ips(intel_crtc);
4664 reenable_ips = true;
4665 }
4666
4667 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4668 u32 palreg;
4669
4670 if (HAS_GMCH_DISPLAY(dev))
4671 palreg = PALETTE(pipe, i);
4672 else
4673 palreg = LGC_PALETTE(pipe, i);
4674
4675 I915_WRITE(palreg,
d77e4531
PZ		 4676 (intel_crtc->lut_r[i] << 16) |
4677 (intel_crtc->lut_g[i] << 8) |
4678 intel_crtc->lut_b[i]);
4679 }
4680
4681 if (reenable_ips)
4682 hsw_enable_ips(intel_crtc);
4683}
4684
7cac945f 4685static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4686{
7cac945f 4687 if (intel_crtc->overlay) {
d3eedb1a
VS		 4688 struct drm_device *dev = intel_crtc->base.dev;
4689 struct drm_i915_private *dev_priv = dev->dev_private;
4690
4691 mutex_lock(&dev->struct_mutex);
4692 dev_priv->mm.interruptible = false;
4693 (void) intel_overlay_switch_off(intel_crtc->overlay);
4694 dev_priv->mm.interruptible = true;
4695 mutex_unlock(&dev->struct_mutex);
4696 }
4697
4698 /* Let userspace switch the overlay on again. In most cases userspace
4699 * has to recompute where to put it anyway.
4700 */
4701}
4702
87d4300a
ML		 4703/**
4704 * intel_post_enable_primary - Perform operations after enabling primary plane
4705 * @crtc: the CRTC whose primary plane was just enabled
4706 *
4707 * Performs potentially sleeping operations that must be done after the primary
4708 * plane is enabled, such as updating FBC and IPS. Note that this may be
4709 * called due to an explicit primary plane update, or due to an implicit
4710 * re-enable that is caused when a sprite plane is updated to no longer
4711 * completely hide the primary plane.
4712 */
4713static void
4714intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4715{
4716 struct drm_device *dev = crtc->dev;
87d4300a 4717 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 int pipe = intel_crtc->pipe;
a5c4d7bc 4720
87d4300a
ML		 4721 /*
4722 * BDW signals flip done immediately if the plane
4723 * is disabled, even if the plane enable is already
4724 * armed to occur at the next vblank :(
4725 */
4726 if (IS_BROADWELL(dev))
4727 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4728
87d4300a
ML		 4729 /*
4730 * FIXME IPS should be fine as long as one plane is
4731 * enabled, but in practice it seems to have problems
4732 * when going from primary only to sprite only and vice
4733 * versa.
4734 */
a5c4d7bc
VS		 4735 hsw_enable_ips(intel_crtc);
4736
f99d7069 4737 /*
87d4300a
ML		 4738 * Gen2 reports pipe underruns whenever all planes are disabled.
4739 * So don't enable underrun reporting before at least some planes
4740 * are enabled.
4741 * FIXME: Need to fix the logic to work when we turn off all planes
4742 * but leave the pipe running.
f99d7069 4743 */
87d4300a
ML		 4744 if (IS_GEN2(dev))
4745 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4746
4747 /* Underruns don't raise interrupts, so check manually. */
4748 if (HAS_GMCH_DISPLAY(dev))
4749 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4750}
4751
87d4300a
ML		 4752/**
4753 * intel_pre_disable_primary - Perform operations before disabling primary plane
4754 * @crtc: the CRTC whose primary plane is to be disabled
4755 *
4756 * Performs potentially sleeping operations that must be done before the
4757 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4758 * be called due to an explicit primary plane update, or due to an implicit
4759 * disable that is caused when a sprite plane completely hides the primary
4760 * plane.
4761 */
4762static void
4763intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4764{
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
a5c4d7bc 4769
87d4300a
ML		 4770 /*
4771 * Gen2 reports pipe underruns whenever all planes are disabled.
4772 * So diasble underrun reporting before all the planes get disabled.
4773 * FIXME: Need to fix the logic to work when we turn off all planes
4774 * but leave the pipe running.
4775 */
4776 if (IS_GEN2(dev))
4777 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4778
87d4300a
ML		 4779 /*
4780 * Vblank time updates from the shadow to live plane control register
4781 * are blocked if the memory self-refresh mode is active at that
4782 * moment. So to make sure the plane gets truly disabled, disable
4783 * first the self-refresh mode. The self-refresh enable bit in turn
4784 * will be checked/applied by the HW only at the next frame start
4785 * event which is after the vblank start event, so we need to have a
4786 * wait-for-vblank between disabling the plane and the pipe.
4787 */
262cd2e1 4788 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4789 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4790 dev_priv->wm.vlv.cxsr = false;
4791 intel_wait_for_vblank(dev, pipe);
4792 }
87d4300a 4793
87d4300a
ML		 4794 /*
4795 * FIXME IPS should be fine as long as one plane is
4796 * enabled, but in practice it seems to have problems
4797 * when going from primary only to sprite only and vice
4798 * versa.
4799 */
a5c4d7bc 4800 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4801}
4802
ac21b225
ML		 4803static void intel_post_plane_update(struct intel_crtc *crtc)
4804{
4805 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4806 struct drm_device *dev = crtc->base.dev;
7733b49b 4807 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4808
4809 if (atomic->wait_vblank)
4810 intel_wait_for_vblank(dev, crtc->pipe);
4811
4812 intel_frontbuffer_flip(dev, atomic->fb_bits);
4813
852eb00d
VS		 4814 if (atomic->disable_cxsr)
4815 crtc->wm.cxsr_allowed = true;
4816
f015c551
VS		 4817 if (crtc->atomic.update_wm_post)
4818 intel_update_watermarks(&crtc->base);
4819
c80ac854 4820 if (atomic->update_fbc)
7733b49b 4821 intel_fbc_update(dev_priv);
ac21b225
ML		 4822
4823 if (atomic->post_enable_primary)
4824 intel_post_enable_primary(&crtc->base);
4825
ac21b225
ML		 4826 memset(atomic, 0, sizeof(*atomic));
4827}
4828
4829static void intel_pre_plane_update(struct intel_crtc *crtc)
4830{
4831 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4832 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4833 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4834 struct drm_plane *p;
4835
4836 /* Track fb's for any planes being disabled */
ac21b225
ML		 4837 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4838 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4839
4840 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4841 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4842 plane->frontbuffer_bit);
ac21b225
ML		 4843 mutex_unlock(&dev->struct_mutex);
4844 }
4845
4846 if (atomic->wait_for_flips)
4847 intel_crtc_wait_for_pending_flips(&crtc->base);
4848
c80ac854 4849 if (atomic->disable_fbc)
25ad93fd 4850 intel_fbc_disable_crtc(crtc);
ac21b225 4851
066cf55b
RV		 4852 if (crtc->atomic.disable_ips)
4853 hsw_disable_ips(crtc);
4854
ac21b225
ML		 4855 if (atomic->pre_disable_primary)
4856 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4857
4858 if (atomic->disable_cxsr) {
4859 crtc->wm.cxsr_allowed = false;
4860 intel_set_memory_cxsr(dev_priv, false);
4861 }
ac21b225
ML		 4862}
4863
d032ffa0 4864static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4865{
4866 struct drm_device *dev = crtc->dev;
4867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4868 struct drm_plane *p;
87d4300a
ML		 4869 int pipe = intel_crtc->pipe;
4870
7cac945f 4871 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4872
d032ffa0
ML		 4873 drm_for_each_plane_mask(p, dev, plane_mask)
4874 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4875
f99d7069
DV		 4876 /*
4877 * FIXME: Once we grow proper nuclear flip support out of this we need
4878 * to compute the mask of flip planes precisely. For the time being
4879 * consider this a flip to a NULL plane.
4880 */
4881 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4882}
4883
f67a559d
JB		 4884static void ironlake_crtc_enable(struct drm_crtc *crtc)
4885{
4886 struct drm_device *dev = crtc->dev;
4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4889 struct intel_encoder *encoder;
f67a559d 4890 int pipe = intel_crtc->pipe;
f67a559d 4891
53d9f4e9 4892 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4893 return;
4894
6e3c9717 4895 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4896 intel_prepare_shared_dpll(intel_crtc);
4897
6e3c9717 4898 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4899 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4900
4901 intel_set_pipe_timings(intel_crtc);
4902
6e3c9717 4903 if (intel_crtc->config->has_pch_encoder) {
29407aab 4904 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4905 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4906 }
4907
4908 ironlake_set_pipeconf(crtc);
4909
f67a559d 4910 intel_crtc->active = true;
8664281b 4911
a72e4c9f
DV		 4912 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4913 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4914
f6736a1a 4915 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4916 if (encoder->pre_enable)
4917 encoder->pre_enable(encoder);
f67a559d 4918
6e3c9717 4919 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4920 /* Note: FDI PLL enabling _must_ be done before we enable the
4921 * cpu pipes, hence this is separate from all the other fdi/pch
4922 * enabling. */
88cefb6c 4923 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4924 } else {
4925 assert_fdi_tx_disabled(dev_priv, pipe);
4926 assert_fdi_rx_disabled(dev_priv, pipe);
4927 }
f67a559d 4928
b074cec8 4929 ironlake_pfit_enable(intel_crtc);
f67a559d 4930
9c54c0dd
JB		 4931 /*
4932 * On ILK+ LUT must be loaded before the pipe is running but with
4933 * clocks enabled
4934 */
4935 intel_crtc_load_lut(crtc);
4936
f37fcc2a 4937 intel_update_watermarks(crtc);
e1fdc473 4938 intel_enable_pipe(intel_crtc);
f67a559d 4939
6e3c9717 4940 if (intel_crtc->config->has_pch_encoder)
f67a559d 4941 ironlake_pch_enable(crtc);
c98e9dcf 4942
f9b61ff6
DV		 4943 assert_vblank_disabled(crtc);
4944 drm_crtc_vblank_on(crtc);
4945
fa5c73b1
DV		 4946 for_each_encoder_on_crtc(dev, crtc, encoder)
4947 encoder->enable(encoder);
61b77ddd
DV		 4948
4949 if (HAS_PCH_CPT(dev))
a1520318 4950 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4951}
4952
42db64ef
PZ		 4953/* IPS only exists on ULT machines and is tied to pipe A. */
4954static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4955{
f5adf94e 4956 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4957}
4958
4f771f10
PZ		 4959static void haswell_crtc_enable(struct drm_crtc *crtc)
4960{
4961 struct drm_device *dev = crtc->dev;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4964 struct intel_encoder *encoder;
99d736a2
ML		 4965 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4966 struct intel_crtc_state *pipe_config =
4967 to_intel_crtc_state(crtc->state);
4f771f10 4968
53d9f4e9 4969 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4970 return;
4971
df8ad70c
DV		 4972 if (intel_crtc_to_shared_dpll(intel_crtc))
4973 intel_enable_shared_dpll(intel_crtc);
4974
6e3c9717 4975 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4976 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4977
4978 intel_set_pipe_timings(intel_crtc);
4979
6e3c9717
ACO		 4980 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4981 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4982 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4983 }
4984
6e3c9717 4985 if (intel_crtc->config->has_pch_encoder) {
229fca97 4986 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4987 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4988 }
4989
4990 haswell_set_pipeconf(crtc);
4991
4992 intel_set_pipe_csc(crtc);
4993
4f771f10 4994 intel_crtc->active = true;
8664281b 4995
a72e4c9f 4996 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4997 for_each_encoder_on_crtc(dev, crtc, encoder)
4998 if (encoder->pre_enable)
4999 encoder->pre_enable(encoder);
5000
6e3c9717 5001 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5002 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5003 true);
4fe9467d
ID		 5004 dev_priv->display.fdi_link_train(crtc);
5005 }
5006
1f544388 5007 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5008
1c132b44 5009 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5010 skylake_pfit_enable(intel_crtc);
ff6d9f55 5011 else
1c132b44 5012 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 5013
5014 /*
5015 * On ILK+ LUT must be loaded before the pipe is running but with
5016 * clocks enabled
5017 */
5018 intel_crtc_load_lut(crtc);
5019
1f544388 5020 intel_ddi_set_pipe_settings(crtc);
8228c251 5021 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5022
f37fcc2a 5023 intel_update_watermarks(crtc);
e1fdc473 5024 intel_enable_pipe(intel_crtc);
42db64ef 5025
6e3c9717 5026 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5027 lpt_pch_enable(crtc);
4f771f10 5028
6e3c9717 5029 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5030 intel_ddi_set_vc_payload_alloc(crtc, true);
5031
f9b61ff6
DV		 5032 assert_vblank_disabled(crtc);
5033 drm_crtc_vblank_on(crtc);
5034
8807e55b 5035 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5036 encoder->enable(encoder);
8807e55b
JN		 5037 intel_opregion_notify_encoder(encoder, true);
5038 }
4f771f10 5039
e4916946
PZ		 5040 /* If we change the relative order between pipe/planes enabling, we need
5041 * to change the workaround. */
99d736a2
ML		 5042 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5043 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5044 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5045 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5046 }
4f771f10
PZ		 5047}
5048
bfd16b2a 5049static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 5050{
5051 struct drm_device *dev = crtc->base.dev;
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053 int pipe = crtc->pipe;
5054
5055 /* To avoid upsetting the power well on haswell only disable the pfit if
5056 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 5057 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5058 I915_WRITE(PF_CTL(pipe), 0);
5059 I915_WRITE(PF_WIN_POS(pipe), 0);
5060 I915_WRITE(PF_WIN_SZ(pipe), 0);
5061 }
5062}
5063
6be4a607
JB		 5064static void ironlake_crtc_disable(struct drm_crtc *crtc)
5065{
5066 struct drm_device *dev = crtc->dev;
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5069 struct intel_encoder *encoder;
6be4a607 5070 int pipe = intel_crtc->pipe;
5eddb70b 5071 u32 reg, temp;
b52eb4dc 5072
ea9d758d
DV		 5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 encoder->disable(encoder);
5075
f9b61ff6
DV		 5076 drm_crtc_vblank_off(crtc);
5077 assert_vblank_disabled(crtc);
5078
6e3c9717 5079 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5080 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5081
575f7ab7 5082 intel_disable_pipe(intel_crtc);
32f9d658 5083
bfd16b2a 5084 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5085
5a74f70a
VS		 5086 if (intel_crtc->config->has_pch_encoder)
5087 ironlake_fdi_disable(crtc);
5088
bf49ec8c
DV		 5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 if (encoder->post_disable)
5091 encoder->post_disable(encoder);
2c07245f 5092
6e3c9717 5093 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5094 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5095
d925c59a
DV		 5096 if (HAS_PCH_CPT(dev)) {
5097 /* disable TRANS_DP_CTL */
5098 reg = TRANS_DP_CTL(pipe);
5099 temp = I915_READ(reg);
5100 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5101 TRANS_DP_PORT_SEL_MASK);
5102 temp |= TRANS_DP_PORT_SEL_NONE;
5103 I915_WRITE(reg, temp);
5104
5105 /* disable DPLL_SEL */
5106 temp = I915_READ(PCH_DPLL_SEL);
11887397 5107 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5108 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5109 }
e3421a18 5110
d925c59a
DV		 5111 ironlake_fdi_pll_disable(intel_crtc);
5112 }
6be4a607 5113}
1b3c7a47 5114
4f771f10 5115static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5116{
4f771f10
PZ		 5117 struct drm_device *dev = crtc->dev;
5118 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5120 struct intel_encoder *encoder;
6e3c9717 5121 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5122
8807e55b
JN		 5123 for_each_encoder_on_crtc(dev, crtc, encoder) {
5124 intel_opregion_notify_encoder(encoder, false);
4f771f10 5125 encoder->disable(encoder);
8807e55b 5126 }
4f771f10 5127
f9b61ff6
DV		 5128 drm_crtc_vblank_off(crtc);
5129 assert_vblank_disabled(crtc);
5130
6e3c9717 5131 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5132 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5133 false);
575f7ab7 5134 intel_disable_pipe(intel_crtc);
4f771f10 5135
6e3c9717 5136 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5137 intel_ddi_set_vc_payload_alloc(crtc, false);
5138
ad80a810 5139 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5140
1c132b44 5141 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5142 skylake_scaler_disable(intel_crtc);
ff6d9f55 5143 else
bfd16b2a 5144 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5145
1f544388 5146 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5147
6e3c9717 5148 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5149 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5150 intel_ddi_fdi_disable(crtc);
83616634 5151 }
4f771f10 5152
97b040aa
ID		 5153 for_each_encoder_on_crtc(dev, crtc, encoder)
5154 if (encoder->post_disable)
5155 encoder->post_disable(encoder);
4f771f10
PZ		 5156}
5157
2dd24552
JB		 5158static void i9xx_pfit_enable(struct intel_crtc *crtc)
5159{
5160 struct drm_device *dev = crtc->base.dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5162 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5163
681a8504 5164 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5165 return;
5166
2dd24552 5167 /*
c0b03411
DV		 5168 * The panel fitter should only be adjusted whilst the pipe is disabled,
5169 * according to register description and PRM.
2dd24552 5170 */
c0b03411
DV		 5171 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5172 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5173
b074cec8
JB		 5174 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5175 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5176
5177 /* Border color in case we don't scale up to the full screen. Black by
5178 * default, change to something else for debugging. */
5179 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5180}
5181
d05410f9
DA		 5182static enum intel_display_power_domain port_to_power_domain(enum port port)
5183{
5184 switch (port) {
5185 case PORT_A:
5186 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5187 case PORT_B:
5188 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5189 case PORT_C:
5190 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5191 case PORT_D:
5192 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5193 case PORT_E:
5194 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5195 default:
5196 WARN_ON_ONCE(1);
5197 return POWER_DOMAIN_PORT_OTHER;
5198 }
5199}
5200
77d22dca
ID		 5201#define for_each_power_domain(domain, mask) \
5202 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5203 if ((1 << (domain)) & (mask))
5204
319be8ae
ID		 5205enum intel_display_power_domain
5206intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5207{
5208 struct drm_device *dev = intel_encoder->base.dev;
5209 struct intel_digital_port *intel_dig_port;
5210
5211 switch (intel_encoder->type) {
5212 case INTEL_OUTPUT_UNKNOWN:
5213 /* Only DDI platforms should ever use this output type */
5214 WARN_ON_ONCE(!HAS_DDI(dev));
5215 case INTEL_OUTPUT_DISPLAYPORT:
5216 case INTEL_OUTPUT_HDMI:
5217 case INTEL_OUTPUT_EDP:
5218 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5219 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5220 case INTEL_OUTPUT_DP_MST:
5221 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5222 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5223 case INTEL_OUTPUT_ANALOG:
5224 return POWER_DOMAIN_PORT_CRT;
5225 case INTEL_OUTPUT_DSI:
5226 return POWER_DOMAIN_PORT_DSI;
5227 default:
5228 return POWER_DOMAIN_PORT_OTHER;
5229 }
5230}
5231
5232static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5233{
319be8ae
ID		 5234 struct drm_device *dev = crtc->dev;
5235 struct intel_encoder *intel_encoder;
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5238 unsigned long mask;
5239 enum transcoder transcoder;
5240
292b990e
ML		 5241 if (!crtc->state->active)
5242 return 0;
5243
77d22dca
ID		 5244 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5245
5246 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5247 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5248 if (intel_crtc->config->pch_pfit.enabled ||
5249 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5250 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5251
319be8ae
ID		 5252 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5253 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5254
77d22dca
ID		 5255 return mask;
5256}
5257
292b990e 5258static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5259{
292b990e
ML		 5260 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5262 enum intel_display_power_domain domain;
5263 unsigned long domains, new_domains, old_domains;
77d22dca 5264
292b990e
ML		 5265 old_domains = intel_crtc->enabled_power_domains;
5266 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5267
292b990e
ML		 5268 domains = new_domains & ~old_domains;
5269
5270 for_each_power_domain(domain, domains)
5271 intel_display_power_get(dev_priv, domain);
5272
5273 return old_domains & ~new_domains;
5274}
5275
5276static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5277 unsigned long domains)
5278{
5279 enum intel_display_power_domain domain;
5280
5281 for_each_power_domain(domain, domains)
5282 intel_display_power_put(dev_priv, domain);
5283}
77d22dca 5284
292b990e
ML		 5285static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5286{
5287 struct drm_device *dev = state->dev;
5288 struct drm_i915_private *dev_priv = dev->dev_private;
5289 unsigned long put_domains[I915_MAX_PIPES] = {};
5290 struct drm_crtc_state *crtc_state;
5291 struct drm_crtc *crtc;
5292 int i;
77d22dca 5293
292b990e
ML		 5294 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5295 if (needs_modeset(crtc->state))
5296 put_domains[to_intel_crtc(crtc)->pipe] =
5297 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5298 }
5299
27c329ed
ML		 5300 if (dev_priv->display.modeset_commit_cdclk) {
5301 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5302
5303 if (cdclk != dev_priv->cdclk_freq &&
5304 !WARN_ON(!state->allow_modeset))
5305 dev_priv->display.modeset_commit_cdclk(state);
5306 }
50f6e502 5307
292b990e
ML		 5308 for (i = 0; i < I915_MAX_PIPES; i++)
5309 if (put_domains[i])
5310 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5311}
5312
adafdc6f
MK		 5313static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5314{
5315 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5316
5317 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5318 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5319 return max_cdclk_freq;
5320 else if (IS_CHERRYVIEW(dev_priv))
5321 return max_cdclk_freq*95/100;
5322 else if (INTEL_INFO(dev_priv)->gen < 4)
5323 return 2*max_cdclk_freq*90/100;
5324 else
5325 return max_cdclk_freq*90/100;
5326}
5327
560a7ae4
DL		 5328static void intel_update_max_cdclk(struct drm_device *dev)
5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331
5332 if (IS_SKYLAKE(dev)) {
5333 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5334
5335 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5336 dev_priv->max_cdclk_freq = 675000;
5337 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5338 dev_priv->max_cdclk_freq = 540000;
5339 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5340 dev_priv->max_cdclk_freq = 450000;
5341 else
5342 dev_priv->max_cdclk_freq = 337500;
5343 } else if (IS_BROADWELL(dev)) {
5344 /*
5345 * FIXME with extra cooling we can allow
5346 * 540 MHz for ULX and 675 Mhz for ULT.
5347 * How can we know if extra cooling is
5348 * available? PCI ID, VTB, something else?
5349 */
5350 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5351 dev_priv->max_cdclk_freq = 450000;
5352 else if (IS_BDW_ULX(dev))
5353 dev_priv->max_cdclk_freq = 450000;
5354 else if (IS_BDW_ULT(dev))
5355 dev_priv->max_cdclk_freq = 540000;
5356 else
5357 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5358 } else if (IS_CHERRYVIEW(dev)) {
5359 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5360 } else if (IS_VALLEYVIEW(dev)) {
5361 dev_priv->max_cdclk_freq = 400000;
5362 } else {
5363 /* otherwise assume cdclk is fixed */
5364 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5365 }
5366
adafdc6f
MK		 5367 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5368
560a7ae4
DL		 5369 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5370 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5371
5372 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5373 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5374}
5375
5376static void intel_update_cdclk(struct drm_device *dev)
5377{
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379
5380 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5381 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5382 dev_priv->cdclk_freq);
5383
5384 /*
5385 * Program the gmbus_freq based on the cdclk frequency.
5386 * BSpec erroneously claims we should aim for 4MHz, but
5387 * in fact 1MHz is the correct frequency.
5388 */
5389 if (IS_VALLEYVIEW(dev)) {
5390 /*
5391 * Program the gmbus_freq based on the cdclk frequency.
5392 * BSpec erroneously claims we should aim for 4MHz, but
5393 * in fact 1MHz is the correct frequency.
5394 */
5395 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5396 }
5397
5398 if (dev_priv->max_cdclk_freq == 0)
5399 intel_update_max_cdclk(dev);
5400}
5401
70d0c574 5402static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5403{
5404 struct drm_i915_private *dev_priv = dev->dev_private;
5405 uint32_t divider;
5406 uint32_t ratio;
5407 uint32_t current_freq;
5408 int ret;
5409
5410 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5411 switch (frequency) {
5412 case 144000:
5413 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5414 ratio = BXT_DE_PLL_RATIO(60);
5415 break;
5416 case 288000:
5417 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5418 ratio = BXT_DE_PLL_RATIO(60);
5419 break;
5420 case 384000:
5421 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5422 ratio = BXT_DE_PLL_RATIO(60);
5423 break;
5424 case 576000:
5425 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5426 ratio = BXT_DE_PLL_RATIO(60);
5427 break;
5428 case 624000:
5429 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5430 ratio = BXT_DE_PLL_RATIO(65);
5431 break;
5432 case 19200:
5433 /*
5434 * Bypass frequency with DE PLL disabled. Init ratio, divider
5435 * to suppress GCC warning.
5436 */
5437 ratio = 0;
5438 divider = 0;
5439 break;
5440 default:
5441 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5442
5443 return;
5444 }
5445
5446 mutex_lock(&dev_priv->rps.hw_lock);
5447 /* Inform power controller of upcoming frequency change */
5448 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5449 0x80000000);
5450 mutex_unlock(&dev_priv->rps.hw_lock);
5451
5452 if (ret) {
5453 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5454 ret, frequency);
5455 return;
5456 }
5457
5458 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5459 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5460 current_freq = current_freq * 500 + 1000;
5461
5462 /*
5463 * DE PLL has to be disabled when
5464 * - setting to 19.2MHz (bypass, PLL isn't used)
5465 * - before setting to 624MHz (PLL needs toggling)
5466 * - before setting to any frequency from 624MHz (PLL needs toggling)
5467 */
5468 if (frequency == 19200 || frequency == 624000 ||
5469 current_freq == 624000) {
5470 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5471 /* Timeout 200us */
5472 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5473 1))
5474 DRM_ERROR("timout waiting for DE PLL unlock\n");
5475 }
5476
5477 if (frequency != 19200) {
5478 uint32_t val;
5479
5480 val = I915_READ(BXT_DE_PLL_CTL);
5481 val &= ~BXT_DE_PLL_RATIO_MASK;
5482 val |= ratio;
5483 I915_WRITE(BXT_DE_PLL_CTL, val);
5484
5485 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5486 /* Timeout 200us */
5487 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5488 DRM_ERROR("timeout waiting for DE PLL lock\n");
5489
5490 val = I915_READ(CDCLK_CTL);
5491 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5492 val |= divider;
5493 /*
5494 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5495 * enable otherwise.
5496 */
5497 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5498 if (frequency >= 500000)
5499 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5500
5501 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5502 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5503 val |= (frequency - 1000) / 500;
5504 I915_WRITE(CDCLK_CTL, val);
5505 }
5506
5507 mutex_lock(&dev_priv->rps.hw_lock);
5508 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5509 DIV_ROUND_UP(frequency, 25000));
5510 mutex_unlock(&dev_priv->rps.hw_lock);
5511
5512 if (ret) {
5513 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5514 ret, frequency);
5515 return;
5516 }
5517
a47871bd 5518 intel_update_cdclk(dev);
f8437dd1
VK		 5519}
5520
5521void broxton_init_cdclk(struct drm_device *dev)
5522{
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524 uint32_t val;
5525
5526 /*
5527 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5528 * or else the reset will hang because there is no PCH to respond.
5529 * Move the handshake programming to initialization sequence.
5530 * Previously was left up to BIOS.
5531 */
5532 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5533 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5534 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5535
5536 /* Enable PG1 for cdclk */
5537 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5538
5539 /* check if cd clock is enabled */
5540 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5541 DRM_DEBUG_KMS("Display already initialized\n");
5542 return;
5543 }
5544
5545 /*
5546 * FIXME:
5547 * - The initial CDCLK needs to be read from VBT.
5548 * Need to make this change after VBT has changes for BXT.
5549 * - check if setting the max (or any) cdclk freq is really necessary
5550 * here, it belongs to modeset time
5551 */
5552 broxton_set_cdclk(dev, 624000);
5553
5554 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5555 POSTING_READ(DBUF_CTL);
5556
f8437dd1
VK		 5557 udelay(10);
5558
5559 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5560 DRM_ERROR("DBuf power enable timeout!\n");
5561}
5562
5563void broxton_uninit_cdclk(struct drm_device *dev)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566
5567 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5568 POSTING_READ(DBUF_CTL);
5569
f8437dd1
VK		 5570 udelay(10);
5571
5572 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5573 DRM_ERROR("DBuf power disable timeout!\n");
5574
5575 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5576 broxton_set_cdclk(dev, 19200);
5577
5578 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5579}
5580
5d96d8af
DL		 5581static const struct skl_cdclk_entry {
5582 unsigned int freq;
5583 unsigned int vco;
5584} skl_cdclk_frequencies[] = {
5585 { .freq = 308570, .vco = 8640 },
5586 { .freq = 337500, .vco = 8100 },
5587 { .freq = 432000, .vco = 8640 },
5588 { .freq = 450000, .vco = 8100 },
5589 { .freq = 540000, .vco = 8100 },
5590 { .freq = 617140, .vco = 8640 },
5591 { .freq = 675000, .vco = 8100 },
5592};
5593
5594static unsigned int skl_cdclk_decimal(unsigned int freq)
5595{
5596 return (freq - 1000) / 500;
5597}
5598
5599static unsigned int skl_cdclk_get_vco(unsigned int freq)
5600{
5601 unsigned int i;
5602
5603 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5604 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5605
5606 if (e->freq == freq)
5607 return e->vco;
5608 }
5609
5610 return 8100;
5611}
5612
5613static void
5614skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5615{
5616 unsigned int min_freq;
5617 u32 val;
5618
5619 /* select the minimum CDCLK before enabling DPLL 0 */
5620 val = I915_READ(CDCLK_CTL);
5621 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5622 val |= CDCLK_FREQ_337_308;
5623
5624 if (required_vco == 8640)
5625 min_freq = 308570;
5626 else
5627 min_freq = 337500;
5628
5629 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5630
5631 I915_WRITE(CDCLK_CTL, val);
5632 POSTING_READ(CDCLK_CTL);
5633
5634 /*
5635 * We always enable DPLL0 with the lowest link rate possible, but still
5636 * taking into account the VCO required to operate the eDP panel at the
5637 * desired frequency. The usual DP link rates operate with a VCO of
5638 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5639 * The modeset code is responsible for the selection of the exact link
5640 * rate later on, with the constraint of choosing a frequency that
5641 * works with required_vco.
5642 */
5643 val = I915_READ(DPLL_CTRL1);
5644
5645 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5646 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5647 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5648 if (required_vco == 8640)
5649 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5650 SKL_DPLL0);
5651 else
5652 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5653 SKL_DPLL0);
5654
5655 I915_WRITE(DPLL_CTRL1, val);
5656 POSTING_READ(DPLL_CTRL1);
5657
5658 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5659
5660 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5661 DRM_ERROR("DPLL0 not locked\n");
5662}
5663
5664static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5665{
5666 int ret;
5667 u32 val;
5668
5669 /* inform PCU we want to change CDCLK */
5670 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5671 mutex_lock(&dev_priv->rps.hw_lock);
5672 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5673 mutex_unlock(&dev_priv->rps.hw_lock);
5674
5675 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5676}
5677
5678static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5679{
5680 unsigned int i;
5681
5682 for (i = 0; i < 15; i++) {
5683 if (skl_cdclk_pcu_ready(dev_priv))
5684 return true;
5685 udelay(10);
5686 }
5687
5688 return false;
5689}
5690
5691static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5692{
560a7ae4 5693 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5694 u32 freq_select, pcu_ack;
5695
5696 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5697
5698 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5699 DRM_ERROR("failed to inform PCU about cdclk change\n");
5700 return;
5701 }
5702
5703 /* set CDCLK_CTL */
5704 switch(freq) {
5705 case 450000:
5706 case 432000:
5707 freq_select = CDCLK_FREQ_450_432;
5708 pcu_ack = 1;
5709 break;
5710 case 540000:
5711 freq_select = CDCLK_FREQ_540;
5712 pcu_ack = 2;
5713 break;
5714 case 308570:
5715 case 337500:
5716 default:
5717 freq_select = CDCLK_FREQ_337_308;
5718 pcu_ack = 0;
5719 break;
5720 case 617140:
5721 case 675000:
5722 freq_select = CDCLK_FREQ_675_617;
5723 pcu_ack = 3;
5724 break;
5725 }
5726
5727 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5728 POSTING_READ(CDCLK_CTL);
5729
5730 /* inform PCU of the change */
5731 mutex_lock(&dev_priv->rps.hw_lock);
5732 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5733 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5734
5735 intel_update_cdclk(dev);
5d96d8af
DL		 5736}
5737
5738void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5739{
5740 /* disable DBUF power */
5741 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5742 POSTING_READ(DBUF_CTL);
5743
5744 udelay(10);
5745
5746 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5747 DRM_ERROR("DBuf power disable timeout\n");
5748
4e961e42
AM		 5749 /*
5750 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5751 */
5752 if (dev_priv->csr.dmc_payload) {
5753 /* disable DPLL0 */
5754 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5755 ~LCPLL_PLL_ENABLE);
5756 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5757 DRM_ERROR("Couldn't disable DPLL0\n");
5758 }
5d96d8af
DL		 5759
5760 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5761}
5762
5763void skl_init_cdclk(struct drm_i915_private *dev_priv)
5764{
5765 u32 val;
5766 unsigned int required_vco;
5767
5768 /* enable PCH reset handshake */
5769 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5770 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5771
5772 /* enable PG1 and Misc I/O */
5773 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5774
39d9b85a
GW		 5775 /* DPLL0 not enabled (happens on early BIOS versions) */
5776 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5777 /* enable DPLL0 */
5778 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5779 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5780 }
5781
5d96d8af
DL		 5782 /* set CDCLK to the frequency the BIOS chose */
5783 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5784
5785 /* enable DBUF power */
5786 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5787 POSTING_READ(DBUF_CTL);
5788
5789 udelay(10);
5790
5791 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5792 DRM_ERROR("DBuf power enable timeout\n");
5793}
5794
30a970c6
JB		 5795/* Adjust CDclk dividers to allow high res or save power if possible */
5796static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5797{
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 u32 val, cmd;
5800
164dfd28
VK		 5801 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5802 != dev_priv->cdclk_freq);
d60c4473 5803
dfcab17e 5804 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5805 cmd = 2;
dfcab17e 5806 else if (cdclk == 266667)
30a970c6
JB		 5807 cmd = 1;
5808 else
5809 cmd = 0;
5810
5811 mutex_lock(&dev_priv->rps.hw_lock);
5812 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5813 val &= ~DSPFREQGUAR_MASK;
5814 val |= (cmd << DSPFREQGUAR_SHIFT);
5815 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5816 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5817 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5818 50)) {
5819 DRM_ERROR("timed out waiting for CDclk change\n");
5820 }
5821 mutex_unlock(&dev_priv->rps.hw_lock);
5822
54433e91
VS		 5823 mutex_lock(&dev_priv->sb_lock);
5824
dfcab17e 5825 if (cdclk == 400000) {
6bcda4f0 5826 u32 divider;
30a970c6 5827
6bcda4f0 5828 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5829
30a970c6
JB		 5830 /* adjust cdclk divider */
5831 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5832 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5833 val |= divider;
5834 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5835
5836 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5837 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5838 50))
5839 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5840 }
5841
30a970c6
JB		 5842 /* adjust self-refresh exit latency value */
5843 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5844 val &= ~0x7f;
5845
5846 /*
5847 * For high bandwidth configs, we set a higher latency in the bunit
5848 * so that the core display fetch happens in time to avoid underruns.
5849 */
dfcab17e 5850 if (cdclk == 400000)
30a970c6
JB		 5851 val |= 4500 / 250; /* 4.5 usec */
5852 else
5853 val |= 3000 / 250; /* 3.0 usec */
5854 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5855
a580516d 5856 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5857
b6283055 5858 intel_update_cdclk(dev);
30a970c6
JB		 5859}
5860
383c5a6a
VS		 5861static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5862{
5863 struct drm_i915_private *dev_priv = dev->dev_private;
5864 u32 val, cmd;
5865
164dfd28
VK		 5866 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5867 != dev_priv->cdclk_freq);
383c5a6a
VS		 5868
5869 switch (cdclk) {
383c5a6a
VS		 5870 case 333333:
5871 case 320000:
383c5a6a 5872 case 266667:
383c5a6a 5873 case 200000:
383c5a6a
VS		 5874 break;
5875 default:
5f77eeb0 5876 MISSING_CASE(cdclk);
383c5a6a
VS		 5877 return;
5878 }
5879
9d0d3fda
VS		 5880 /*
5881 * Specs are full of misinformation, but testing on actual
5882 * hardware has shown that we just need to write the desired
5883 * CCK divider into the Punit register.
5884 */
5885 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5886
383c5a6a
VS		 5887 mutex_lock(&dev_priv->rps.hw_lock);
5888 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5889 val &= ~DSPFREQGUAR_MASK_CHV;
5890 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5891 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5892 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5893 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5894 50)) {
5895 DRM_ERROR("timed out waiting for CDclk change\n");
5896 }
5897 mutex_unlock(&dev_priv->rps.hw_lock);
5898
b6283055 5899 intel_update_cdclk(dev);
383c5a6a
VS		 5900}
5901
30a970c6
JB		 5902static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5903 int max_pixclk)
5904{
6bcda4f0 5905 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5906 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5907
30a970c6
JB		 5908 /*
5909 * Really only a few cases to deal with, as only 4 CDclks are supported:
5910 * 200MHz
5911 * 267MHz
29dc7ef3 5912 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5913 * 400MHz (VLV only)
5914 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5915 * of the lower bin and adjust if needed.
e37c67a1
VS		 5916 *
5917 * We seem to get an unstable or solid color picture at 200MHz.
5918 * Not sure what's wrong. For now use 200MHz only when all pipes
5919 * are off.
30a970c6 5920 */
6cca3195
VS		 5921 if (!IS_CHERRYVIEW(dev_priv) &&
5922 max_pixclk > freq_320*limit/100)
dfcab17e 5923 return 400000;
6cca3195 5924 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5925 return freq_320;
e37c67a1 5926 else if (max_pixclk > 0)
dfcab17e 5927 return 266667;
e37c67a1
VS		 5928 else
5929 return 200000;
30a970c6
JB		 5930}
5931
f8437dd1
VK		 5932static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5933 int max_pixclk)
5934{
5935 /*
5936 * FIXME:
5937 * - remove the guardband, it's not needed on BXT
5938 * - set 19.2MHz bypass frequency if there are no active pipes
5939 */
5940 if (max_pixclk > 576000*9/10)
5941 return 624000;
5942 else if (max_pixclk > 384000*9/10)
5943 return 576000;
5944 else if (max_pixclk > 288000*9/10)
5945 return 384000;
5946 else if (max_pixclk > 144000*9/10)
5947 return 288000;
5948 else
5949 return 144000;
5950}
5951
a821fc46
ACO		 5952/* Compute the max pixel clock for new configuration. Uses atomic state if
5953 * that's non-NULL, look at current state otherwise. */
5954static int intel_mode_max_pixclk(struct drm_device *dev,
5955 struct drm_atomic_state *state)
30a970c6 5956{
30a970c6 5957 struct intel_crtc *intel_crtc;
304603f4 5958 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5959 int max_pixclk = 0;
5960
d3fcc808 5961 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5962 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5963 if (IS_ERR(crtc_state))
5964 return PTR_ERR(crtc_state);
5965
5966 if (!crtc_state->base.enable)
5967 continue;
5968
5969 max_pixclk = max(max_pixclk,
5970 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5971 }
5972
5973 return max_pixclk;
5974}
5975
27c329ed 5976static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5977{
27c329ed
ML		 5978 struct drm_device *dev = state->dev;
5979 struct drm_i915_private *dev_priv = dev->dev_private;
5980 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5981
304603f4
ACO		 5982 if (max_pixclk < 0)
5983 return max_pixclk;
30a970c6 5984
27c329ed
ML		 5985 to_intel_atomic_state(state)->cdclk =
5986 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5987
27c329ed
ML		 5988 return 0;
5989}
304603f4 5990
27c329ed
ML		 5991static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5992{
5993 struct drm_device *dev = state->dev;
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5996
27c329ed
ML		 5997 if (max_pixclk < 0)
5998 return max_pixclk;
85a96e7a 5999
27c329ed
ML		 6000 to_intel_atomic_state(state)->cdclk =
6001 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 6002
27c329ed 6003 return 0;
30a970c6
JB		 6004}
6005
1e69cd74
VS		 6006static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6007{
6008 unsigned int credits, default_credits;
6009
6010 if (IS_CHERRYVIEW(dev_priv))
6011 default_credits = PFI_CREDIT(12);
6012 else
6013 default_credits = PFI_CREDIT(8);
6014
bfa7df01 6015 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 6016 /* CHV suggested value is 31 or 63 */
6017 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 6018 credits = PFI_CREDIT_63;
1e69cd74
VS		 6019 else
6020 credits = PFI_CREDIT(15);
6021 } else {
6022 credits = default_credits;
6023 }
6024
6025 /*
6026 * WA - write default credits before re-programming
6027 * FIXME: should we also set the resend bit here?
6028 */
6029 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6030 default_credits);
6031
6032 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6033 credits | PFI_CREDIT_RESEND);
6034
6035 /*
6036 * FIXME is this guaranteed to clear
6037 * immediately or should we poll for it?
6038 */
6039 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6040}
6041
27c329ed 6042static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6043{
a821fc46 6044 struct drm_device *dev = old_state->dev;
27c329ed 6045 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6046 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6047
27c329ed
ML		 6048 /*
6049 * FIXME: We can end up here with all power domains off, yet
6050 * with a CDCLK frequency other than the minimum. To account
6051 * for this take the PIPE-A power domain, which covers the HW
6052 * blocks needed for the following programming. This can be
6053 * removed once it's guaranteed that we get here either with
6054 * the minimum CDCLK set, or the required power domains
6055 * enabled.
6056 */
6057 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6058
27c329ed
ML		 6059 if (IS_CHERRYVIEW(dev))
6060 cherryview_set_cdclk(dev, req_cdclk);
6061 else
6062 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6063
27c329ed 6064 vlv_program_pfi_credits(dev_priv);
1e69cd74 6065
27c329ed 6066 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6067}
6068
89b667f8
JB		 6069static void valleyview_crtc_enable(struct drm_crtc *crtc)
6070{
6071 struct drm_device *dev = crtc->dev;
a72e4c9f 6072 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074 struct intel_encoder *encoder;
6075 int pipe = intel_crtc->pipe;
23538ef1 6076 bool is_dsi;
89b667f8 6077
53d9f4e9 6078 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6079 return;
6080
409ee761 6081 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6082
6e3c9717 6083 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6084 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6085
6086 intel_set_pipe_timings(intel_crtc);
6087
c14b0485
VS		 6088 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6089 struct drm_i915_private *dev_priv = dev->dev_private;
6090
6091 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6092 I915_WRITE(CHV_CANVAS(pipe), 0);
6093 }
6094
5b18e57c
DV		 6095 i9xx_set_pipeconf(intel_crtc);
6096
89b667f8 6097 intel_crtc->active = true;
89b667f8 6098
a72e4c9f 6099 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6100
89b667f8
JB		 6101 for_each_encoder_on_crtc(dev, crtc, encoder)
6102 if (encoder->pre_pll_enable)
6103 encoder->pre_pll_enable(encoder);
6104
9d556c99 6105 if (!is_dsi) {
c0b4c660
VS		 6106 if (IS_CHERRYVIEW(dev)) {
6107 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6108 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6109 } else {
6110 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6111 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6112 }
9d556c99 6113 }
89b667f8
JB		 6114
6115 for_each_encoder_on_crtc(dev, crtc, encoder)
6116 if (encoder->pre_enable)
6117 encoder->pre_enable(encoder);
6118
2dd24552
JB		 6119 i9xx_pfit_enable(intel_crtc);
6120
63cbb074
VS		 6121 intel_crtc_load_lut(crtc);
6122
e1fdc473 6123 intel_enable_pipe(intel_crtc);
be6a6f8e 6124
4b3a9526
VS		 6125 assert_vblank_disabled(crtc);
6126 drm_crtc_vblank_on(crtc);
6127
f9b61ff6
DV		 6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 encoder->enable(encoder);
89b667f8
JB		 6130}
6131
f13c2ef3
DV		 6132static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6133{
6134 struct drm_device *dev = crtc->base.dev;
6135 struct drm_i915_private *dev_priv = dev->dev_private;
6136
6e3c9717
ACO		 6137 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6138 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6139}
6140
0b8765c6 6141static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6142{
6143 struct drm_device *dev = crtc->dev;
a72e4c9f 6144 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6146 struct intel_encoder *encoder;
79e53945 6147 int pipe = intel_crtc->pipe;
79e53945 6148
53d9f4e9 6149 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6150 return;
6151
f13c2ef3
DV		 6152 i9xx_set_pll_dividers(intel_crtc);
6153
6e3c9717 6154 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6155 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6156
6157 intel_set_pipe_timings(intel_crtc);
6158
5b18e57c
DV		 6159 i9xx_set_pipeconf(intel_crtc);
6160
f7abfe8b 6161 intel_crtc->active = true;
6b383a7f 6162
4a3436e8 6163 if (!IS_GEN2(dev))
a72e4c9f 6164 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6165
9d6d9f19
MK		 6166 for_each_encoder_on_crtc(dev, crtc, encoder)
6167 if (encoder->pre_enable)
6168 encoder->pre_enable(encoder);
6169
f6736a1a
DV		 6170 i9xx_enable_pll(intel_crtc);
6171
2dd24552
JB		 6172 i9xx_pfit_enable(intel_crtc);
6173
63cbb074
VS		 6174 intel_crtc_load_lut(crtc);
6175
f37fcc2a 6176 intel_update_watermarks(crtc);
e1fdc473 6177 intel_enable_pipe(intel_crtc);
be6a6f8e 6178
4b3a9526
VS		 6179 assert_vblank_disabled(crtc);
6180 drm_crtc_vblank_on(crtc);
6181
f9b61ff6
DV		 6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 encoder->enable(encoder);
0b8765c6 6184}
79e53945 6185
87476d63
DV		 6186static void i9xx_pfit_disable(struct intel_crtc *crtc)
6187{
6188 struct drm_device *dev = crtc->base.dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6190
6e3c9717 6191 if (!crtc->config->gmch_pfit.control)
328d8e82 6192 return;
87476d63 6193
328d8e82 6194 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6195
328d8e82
DV		 6196 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6197 I915_READ(PFIT_CONTROL));
6198 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6199}
6200
0b8765c6
JB		 6201static void i9xx_crtc_disable(struct drm_crtc *crtc)
6202{
6203 struct drm_device *dev = crtc->dev;
6204 struct drm_i915_private *dev_priv = dev->dev_private;
6205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6206 struct intel_encoder *encoder;
0b8765c6 6207 int pipe = intel_crtc->pipe;
ef9c3aee 6208
6304cd91
VS		 6209 /*
6210 * On gen2 planes are double buffered but the pipe isn't, so we must
6211 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6212 * We also need to wait on all gmch platforms because of the
6213 * self-refresh mode constraint explained above.
6304cd91 6214 */
564ed191 6215 intel_wait_for_vblank(dev, pipe);
6304cd91 6216
4b3a9526
VS		 6217 for_each_encoder_on_crtc(dev, crtc, encoder)
6218 encoder->disable(encoder);
6219
f9b61ff6
DV		 6220 drm_crtc_vblank_off(crtc);
6221 assert_vblank_disabled(crtc);
6222
575f7ab7 6223 intel_disable_pipe(intel_crtc);
24a1f16d 6224
87476d63 6225 i9xx_pfit_disable(intel_crtc);
24a1f16d 6226
89b667f8
JB		 6227 for_each_encoder_on_crtc(dev, crtc, encoder)
6228 if (encoder->post_disable)
6229 encoder->post_disable(encoder);
6230
409ee761 6231 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6232 if (IS_CHERRYVIEW(dev))
6233 chv_disable_pll(dev_priv, pipe);
6234 else if (IS_VALLEYVIEW(dev))
6235 vlv_disable_pll(dev_priv, pipe);
6236 else
1c4e0274 6237 i9xx_disable_pll(intel_crtc);
076ed3b2 6238 }
0b8765c6 6239
d6db995f
VS		 6240 for_each_encoder_on_crtc(dev, crtc, encoder)
6241 if (encoder->post_pll_disable)
6242 encoder->post_pll_disable(encoder);
6243
4a3436e8 6244 if (!IS_GEN2(dev))
a72e4c9f 6245 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6246}
6247
b17d48e2
ML		 6248static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6249{
6250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6252 enum intel_display_power_domain domain;
6253 unsigned long domains;
6254
6255 if (!intel_crtc->active)
6256 return;
6257
a539205a
ML		 6258 if (to_intel_plane_state(crtc->primary->state)->visible) {
6259 intel_crtc_wait_for_pending_flips(crtc);
6260 intel_pre_disable_primary(crtc);
6261 }
6262
d032ffa0 6263 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6264 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6265 intel_crtc->active = false;
6266 intel_update_watermarks(crtc);
1f7457b1 6267 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6268
6269 domains = intel_crtc->enabled_power_domains;
6270 for_each_power_domain(domain, domains)
6271 intel_display_power_put(dev_priv, domain);
6272 intel_crtc->enabled_power_domains = 0;
6273}
6274
6b72d486
ML		 6275/*
6276 * turn all crtc's off, but do not adjust state
6277 * This has to be paired with a call to intel_modeset_setup_hw_state.
6278 */
70e0bd74 6279int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6280{
70e0bd74
ML		 6281 struct drm_mode_config *config = &dev->mode_config;
6282 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6283 struct drm_atomic_state *state;
6b72d486 6284 struct drm_crtc *crtc;
70e0bd74
ML		 6285 unsigned crtc_mask = 0;
6286 int ret = 0;
6287
6288 if (WARN_ON(!ctx))
6289 return 0;
6290
6291 lockdep_assert_held(&ctx->ww_ctx);
6292 state = drm_atomic_state_alloc(dev);
6293 if (WARN_ON(!state))
6294 return -ENOMEM;
6295
6296 state->acquire_ctx = ctx;
6297 state->allow_modeset = true;
6298
6299 for_each_crtc(dev, crtc) {
6300 struct drm_crtc_state *crtc_state =
6301 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6302
70e0bd74
ML		 6303 ret = PTR_ERR_OR_ZERO(crtc_state);
6304 if (ret)
6305 goto free;
6306
6307 if (!crtc_state->active)
6308 continue;
6309
6310 crtc_state->active = false;
6311 crtc_mask |= 1 << drm_crtc_index(crtc);
6312 }
6313
6314 if (crtc_mask) {
74c090b1 6315 ret = drm_atomic_commit(state);
70e0bd74
ML		 6316
6317 if (!ret) {
6318 for_each_crtc(dev, crtc)
6319 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6320 crtc->state->active = true;
6321
6322 return ret;
6323 }
6324 }
6325
6326free:
6327 if (ret)
6328 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6329 drm_atomic_state_free(state);
6330 return ret;
ee7b9f93
JB		 6331}
6332
ea5b213a 6333void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6334{
4ef69c7a 6335 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6336
ea5b213a
CW		 6337 drm_encoder_cleanup(encoder);
6338 kfree(intel_encoder);
7e7d76c3
JB		 6339}
6340
0a91ca29
DV		 6341/* Cross check the actual hw state with our own modeset state tracking (and it's
6342 * internal consistency). */
b980514c 6343static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6344{
35dd3c64
ML		 6345 struct drm_crtc *crtc = connector->base.state->crtc;
6346
6347 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6348 connector->base.base.id,
6349 connector->base.name);
6350
0a91ca29 6351 if (connector->get_hw_state(connector)) {
e85376cb 6352 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6353 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6354
35dd3c64
ML		 6355 I915_STATE_WARN(!crtc,
6356 "connector enabled without attached crtc\n");
0a91ca29 6357
35dd3c64
ML		 6358 if (!crtc)
6359 return;
6360
6361 I915_STATE_WARN(!crtc->state->active,
6362 "connector is active, but attached crtc isn't\n");
6363
e85376cb 6364 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6365 return;
6366
e85376cb 6367 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6368 "atomic encoder doesn't match attached encoder\n");
6369
e85376cb 6370 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6371 "attached encoder crtc differs from connector crtc\n");
6372 } else {
4d688a2a
ML		 6373 I915_STATE_WARN(crtc && crtc->state->active,
6374 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6375 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6376 "best encoder set without crtc!\n");
0a91ca29 6377 }
79e53945
JB		 6378}
6379
08d9bc92
ACO		 6380int intel_connector_init(struct intel_connector *connector)
6381{
6382 struct drm_connector_state *connector_state;
6383
6384 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6385 if (!connector_state)
6386 return -ENOMEM;
6387
6388 connector->base.state = connector_state;
6389 return 0;
6390}
6391
6392struct intel_connector *intel_connector_alloc(void)
6393{
6394 struct intel_connector *connector;
6395
6396 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6397 if (!connector)
6398 return NULL;
6399
6400 if (intel_connector_init(connector) < 0) {
6401 kfree(connector);
6402 return NULL;
6403 }
6404
6405 return connector;
6406}
6407
f0947c37
DV		 6408/* Simple connector->get_hw_state implementation for encoders that support only
6409 * one connector and no cloning and hence the encoder state determines the state
6410 * of the connector. */
6411bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6412{
24929352 6413 enum pipe pipe = 0;
f0947c37 6414 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6415
f0947c37 6416 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6417}
6418
6d293983 6419static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6420{
6d293983
ACO		 6421 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6422 return crtc_state->fdi_lanes;
d272ddfa
VS		 6423
6424 return 0;
6425}
6426
6d293983 6427static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6428 struct intel_crtc_state *pipe_config)
1857e1da 6429{
6d293983
ACO		 6430 struct drm_atomic_state *state = pipe_config->base.state;
6431 struct intel_crtc *other_crtc;
6432 struct intel_crtc_state *other_crtc_state;
6433
1857e1da
DV		 6434 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6435 pipe_name(pipe), pipe_config->fdi_lanes);
6436 if (pipe_config->fdi_lanes > 4) {
6437 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6438 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6439 return -EINVAL;
1857e1da
DV		 6440 }
6441
bafb6553 6442 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6443 if (pipe_config->fdi_lanes > 2) {
6444 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6445 pipe_config->fdi_lanes);
6d293983 6446 return -EINVAL;
1857e1da 6447 } else {
6d293983 6448 return 0;
1857e1da
DV		 6449 }
6450 }
6451
6452 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6453 return 0;
1857e1da
DV		 6454
6455 /* Ivybridge 3 pipe is really complicated */
6456 switch (pipe) {
6457 case PIPE_A:
6d293983 6458 return 0;
1857e1da 6459 case PIPE_B:
6d293983
ACO		 6460 if (pipe_config->fdi_lanes <= 2)
6461 return 0;
6462
6463 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6464 other_crtc_state =
6465 intel_atomic_get_crtc_state(state, other_crtc);
6466 if (IS_ERR(other_crtc_state))
6467 return PTR_ERR(other_crtc_state);
6468
6469 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6470 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6471 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6472 return -EINVAL;
1857e1da 6473 }
6d293983 6474 return 0;
1857e1da 6475 case PIPE_C:
251cc67c
VS		 6476 if (pipe_config->fdi_lanes > 2) {
6477 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6478 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6479 return -EINVAL;
251cc67c 6480 }
6d293983
ACO		 6481
6482 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6483 other_crtc_state =
6484 intel_atomic_get_crtc_state(state, other_crtc);
6485 if (IS_ERR(other_crtc_state))
6486 return PTR_ERR(other_crtc_state);
6487
6488 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6489 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6490 return -EINVAL;
1857e1da 6491 }
6d293983 6492 return 0;
1857e1da
DV		 6493 default:
6494 BUG();
6495 }
6496}
6497
e29c22c0
DV		 6498#define RETRY 1
6499static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6500 struct intel_crtc_state *pipe_config)
877d48d5 6501{
1857e1da 6502 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6503 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6504 int lane, link_bw, fdi_dotclock, ret;
6505 bool needs_recompute = false;
877d48d5 6506
e29c22c0 6507retry:
877d48d5
DV		 6508 /* FDI is a binary signal running at ~2.7GHz, encoding
6509 * each output octet as 10 bits. The actual frequency
6510 * is stored as a divider into a 100MHz clock, and the
6511 * mode pixel clock is stored in units of 1KHz.
6512 * Hence the bw of each lane in terms of the mode signal
6513 * is:
6514 */
6515 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6516
241bfc38 6517 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6518
2bd89a07 6519 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6520 pipe_config->pipe_bpp);
6521
6522 pipe_config->fdi_lanes = lane;
6523
2bd89a07 6524 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6525 link_bw, &pipe_config->fdi_m_n);
1857e1da 6526
6d293983
ACO		 6527 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6528 intel_crtc->pipe, pipe_config);
6529 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6530 pipe_config->pipe_bpp -= 2*3;
6531 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6532 pipe_config->pipe_bpp);
6533 needs_recompute = true;
6534 pipe_config->bw_constrained = true;
6535
6536 goto retry;
6537 }
6538
6539 if (needs_recompute)
6540 return RETRY;
6541
6d293983 6542 return ret;
877d48d5
DV		 6543}
6544
8cfb3407
VS		 6545static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6546 struct intel_crtc_state *pipe_config)
6547{
6548 if (pipe_config->pipe_bpp > 24)
6549 return false;
6550
6551 /* HSW can handle pixel rate up to cdclk? */
6552 if (IS_HASWELL(dev_priv->dev))
6553 return true;
6554
6555 /*
b432e5cf
VS		 6556 * We compare against max which means we must take
6557 * the increased cdclk requirement into account when
6558 * calculating the new cdclk.
6559 *
6560 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6561 */
6562 return ilk_pipe_pixel_rate(pipe_config) <=
6563 dev_priv->max_cdclk_freq * 95 / 100;
6564}
6565
42db64ef 6566static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6567 struct intel_crtc_state *pipe_config)
42db64ef 6568{
8cfb3407
VS		 6569 struct drm_device *dev = crtc->base.dev;
6570 struct drm_i915_private *dev_priv = dev->dev_private;
6571
d330a953 6572 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6573 hsw_crtc_supports_ips(crtc) &&
6574 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6575}
6576
a43f6e0f 6577static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6578 struct intel_crtc_state *pipe_config)
79e53945 6579{
a43f6e0f 6580 struct drm_device *dev = crtc->base.dev;
8bd31e67 6581 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6582 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6583
ad3a4479 6584 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6585 if (INTEL_INFO(dev)->gen < 4) {
44913155 6586 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6587
6588 /*
6589 * Enable pixel doubling when the dot clock
6590 * is > 90% of the (display) core speed.
6591 *
b397c96b
VS		 6592 * GDG double wide on either pipe,
6593 * otherwise pipe A only.
cf532bb2 6594 */
b397c96b 6595 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6596 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6597 clock_limit *= 2;
cf532bb2 6598 pipe_config->double_wide = true;
ad3a4479
VS		 6599 }
6600
241bfc38 6601 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6602 return -EINVAL;
2c07245f 6603 }
89749350 6604
1d1d0e27
VS		 6605 /*
6606 * Pipe horizontal size must be even in:
6607 * - DVO ganged mode
6608 * - LVDS dual channel mode
6609 * - Double wide pipe
6610 */
a93e255f 6611 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6612 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6613 pipe_config->pipe_src_w &= ~1;
6614
8693a824
DL		 6615 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6616 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6617 */
6618 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6619 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6620 return -EINVAL;
44f46b42 6621
f5adf94e 6622 if (HAS_IPS(dev))
a43f6e0f
DV		 6623 hsw_compute_ips_config(crtc, pipe_config);
6624
877d48d5 6625 if (pipe_config->has_pch_encoder)
a43f6e0f 6626 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6627
cf5a15be 6628 return 0;
79e53945
JB		 6629}
6630
1652d19e
VS		 6631static int skylake_get_display_clock_speed(struct drm_device *dev)
6632{
6633 struct drm_i915_private *dev_priv = to_i915(dev);
6634 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6635 uint32_t cdctl = I915_READ(CDCLK_CTL);
6636 uint32_t linkrate;
6637
414355a7 6638 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6639 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6640
6641 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6642 return 540000;
6643
6644 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6645 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6646
71cd8423
DL		 6647 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6648 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6649 /* vco 8640 */
6650 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6651 case CDCLK_FREQ_450_432:
6652 return 432000;
6653 case CDCLK_FREQ_337_308:
6654 return 308570;
6655 case CDCLK_FREQ_675_617:
6656 return 617140;
6657 default:
6658 WARN(1, "Unknown cd freq selection\n");
6659 }
6660 } else {
6661 /* vco 8100 */
6662 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6663 case CDCLK_FREQ_450_432:
6664 return 450000;
6665 case CDCLK_FREQ_337_308:
6666 return 337500;
6667 case CDCLK_FREQ_675_617:
6668 return 675000;
6669 default:
6670 WARN(1, "Unknown cd freq selection\n");
6671 }
6672 }
6673
6674 /* error case, do as if DPLL0 isn't enabled */
6675 return 24000;
6676}
6677
acd3f3d3
BP		 6678static int broxton_get_display_clock_speed(struct drm_device *dev)
6679{
6680 struct drm_i915_private *dev_priv = to_i915(dev);
6681 uint32_t cdctl = I915_READ(CDCLK_CTL);
6682 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6683 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6684 int cdclk;
6685
6686 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6687 return 19200;
6688
6689 cdclk = 19200 * pll_ratio / 2;
6690
6691 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6692 case BXT_CDCLK_CD2X_DIV_SEL_1:
6693 return cdclk; /* 576MHz or 624MHz */
6694 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6695 return cdclk * 2 / 3; /* 384MHz */
6696 case BXT_CDCLK_CD2X_DIV_SEL_2:
6697 return cdclk / 2; /* 288MHz */
6698 case BXT_CDCLK_CD2X_DIV_SEL_4:
6699 return cdclk / 4; /* 144MHz */
6700 }
6701
6702 /* error case, do as if DE PLL isn't enabled */
6703 return 19200;
6704}
6705
1652d19e
VS		 6706static int broadwell_get_display_clock_speed(struct drm_device *dev)
6707{
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 uint32_t lcpll = I915_READ(LCPLL_CTL);
6710 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6711
6712 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6713 return 800000;
6714 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6715 return 450000;
6716 else if (freq == LCPLL_CLK_FREQ_450)
6717 return 450000;
6718 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6719 return 540000;
6720 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6721 return 337500;
6722 else
6723 return 675000;
6724}
6725
6726static int haswell_get_display_clock_speed(struct drm_device *dev)
6727{
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 uint32_t lcpll = I915_READ(LCPLL_CTL);
6730 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6731
6732 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6733 return 800000;
6734 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6735 return 450000;
6736 else if (freq == LCPLL_CLK_FREQ_450)
6737 return 450000;
6738 else if (IS_HSW_ULT(dev))
6739 return 337500;
6740 else
6741 return 540000;
79e53945
JB		 6742}
6743
25eb05fc
JB		 6744static int valleyview_get_display_clock_speed(struct drm_device *dev)
6745{
bfa7df01
VS		 6746 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6747 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6748}
6749
b37a6434
VS		 6750static int ilk_get_display_clock_speed(struct drm_device *dev)
6751{
6752 return 450000;
6753}
6754
e70236a8
JB		 6755static int i945_get_display_clock_speed(struct drm_device *dev)
6756{
6757 return 400000;
6758}
79e53945 6759
e70236a8 6760static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6761{
e907f170 6762 return 333333;
e70236a8 6763}
79e53945 6764
e70236a8
JB		 6765static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6766{
6767 return 200000;
6768}
79e53945 6769
257a7ffc
DV		 6770static int pnv_get_display_clock_speed(struct drm_device *dev)
6771{
6772 u16 gcfgc = 0;
6773
6774 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6775
6776 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6777 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6778 return 266667;
257a7ffc 6779 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6780 return 333333;
257a7ffc 6781 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6782 return 444444;
257a7ffc
DV		 6783 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6784 return 200000;
6785 default:
6786 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6787 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6788 return 133333;
257a7ffc 6789 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6790 return 166667;
257a7ffc
DV		 6791 }
6792}
6793
e70236a8
JB		 6794static int i915gm_get_display_clock_speed(struct drm_device *dev)
6795{
6796 u16 gcfgc = 0;
79e53945 6797
e70236a8
JB		 6798 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6799
6800 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6801 return 133333;
e70236a8
JB		 6802 else {
6803 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6804 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6805 return 333333;
e70236a8
JB		 6806 default:
6807 case GC_DISPLAY_CLOCK_190_200_MHZ:
6808 return 190000;
79e53945 6809 }
e70236a8
JB		 6810 }
6811}
6812
6813static int i865_get_display_clock_speed(struct drm_device *dev)
6814{
e907f170 6815 return 266667;
e70236a8
JB		 6816}
6817
1b1d2716 6818static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6819{
6820 u16 hpllcc = 0;
1b1d2716 6821
65cd2b3f
VS		 6822 /*
6823 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6824 * encoding is different :(
6825 * FIXME is this the right way to detect 852GM/852GMV?
6826 */
6827 if (dev->pdev->revision == 0x1)
6828 return 133333;
6829
1b1d2716
VS		 6830 pci_bus_read_config_word(dev->pdev->bus,
6831 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6832
e70236a8
JB		 6833 /* Assume that the hardware is in the high speed state. This
6834 * should be the default.
6835 */
6836 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6837 case GC_CLOCK_133_200:
1b1d2716 6838 case GC_CLOCK_133_200_2:
e70236a8
JB		 6839 case GC_CLOCK_100_200:
6840 return 200000;
6841 case GC_CLOCK_166_250:
6842 return 250000;
6843 case GC_CLOCK_100_133:
e907f170 6844 return 133333;
1b1d2716
VS		 6845 case GC_CLOCK_133_266:
6846 case GC_CLOCK_133_266_2:
6847 case GC_CLOCK_166_266:
6848 return 266667;
e70236a8 6849 }
79e53945 6850
e70236a8
JB		 6851 /* Shouldn't happen */
6852 return 0;
6853}
79e53945 6854
e70236a8
JB		 6855static int i830_get_display_clock_speed(struct drm_device *dev)
6856{
e907f170 6857 return 133333;
79e53945
JB		 6858}
6859
34edce2f
VS		 6860static unsigned int intel_hpll_vco(struct drm_device *dev)
6861{
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 static const unsigned int blb_vco[8] = {
6864 [0] = 3200000,
6865 [1] = 4000000,
6866 [2] = 5333333,
6867 [3] = 4800000,
6868 [4] = 6400000,
6869 };
6870 static const unsigned int pnv_vco[8] = {
6871 [0] = 3200000,
6872 [1] = 4000000,
6873 [2] = 5333333,
6874 [3] = 4800000,
6875 [4] = 2666667,
6876 };
6877 static const unsigned int cl_vco[8] = {
6878 [0] = 3200000,
6879 [1] = 4000000,
6880 [2] = 5333333,
6881 [3] = 6400000,
6882 [4] = 3333333,
6883 [5] = 3566667,
6884 [6] = 4266667,
6885 };
6886 static const unsigned int elk_vco[8] = {
6887 [0] = 3200000,
6888 [1] = 4000000,
6889 [2] = 5333333,
6890 [3] = 4800000,
6891 };
6892 static const unsigned int ctg_vco[8] = {
6893 [0] = 3200000,
6894 [1] = 4000000,
6895 [2] = 5333333,
6896 [3] = 6400000,
6897 [4] = 2666667,
6898 [5] = 4266667,
6899 };
6900 const unsigned int *vco_table;
6901 unsigned int vco;
6902 uint8_t tmp = 0;
6903
6904 /* FIXME other chipsets? */
6905 if (IS_GM45(dev))
6906 vco_table = ctg_vco;
6907 else if (IS_G4X(dev))
6908 vco_table = elk_vco;
6909 else if (IS_CRESTLINE(dev))
6910 vco_table = cl_vco;
6911 else if (IS_PINEVIEW(dev))
6912 vco_table = pnv_vco;
6913 else if (IS_G33(dev))
6914 vco_table = blb_vco;
6915 else
6916 return 0;
6917
6918 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6919
6920 vco = vco_table[tmp & 0x7];
6921 if (vco == 0)
6922 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6923 else
6924 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6925
6926 return vco;
6927}
6928
6929static int gm45_get_display_clock_speed(struct drm_device *dev)
6930{
6931 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6932 uint16_t tmp = 0;
6933
6934 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6935
6936 cdclk_sel = (tmp >> 12) & 0x1;
6937
6938 switch (vco) {
6939 case 2666667:
6940 case 4000000:
6941 case 5333333:
6942 return cdclk_sel ? 333333 : 222222;
6943 case 3200000:
6944 return cdclk_sel ? 320000 : 228571;
6945 default:
6946 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6947 return 222222;
6948 }
6949}
6950
6951static int i965gm_get_display_clock_speed(struct drm_device *dev)
6952{
6953 static const uint8_t div_3200[] = { 16, 10, 8 };
6954 static const uint8_t div_4000[] = { 20, 12, 10 };
6955 static const uint8_t div_5333[] = { 24, 16, 14 };
6956 const uint8_t *div_table;
6957 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6958 uint16_t tmp = 0;
6959
6960 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6961
6962 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6963
6964 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6965 goto fail;
6966
6967 switch (vco) {
6968 case 3200000:
6969 div_table = div_3200;
6970 break;
6971 case 4000000:
6972 div_table = div_4000;
6973 break;
6974 case 5333333:
6975 div_table = div_5333;
6976 break;
6977 default:
6978 goto fail;
6979 }
6980
6981 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6982
caf4e252 6983fail:
34edce2f
VS		 6984 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6985 return 200000;
6986}
6987
6988static int g33_get_display_clock_speed(struct drm_device *dev)
6989{
6990 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6991 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6992 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6993 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6994 const uint8_t *div_table;
6995 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6996 uint16_t tmp = 0;
6997
6998 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6999
7000 cdclk_sel = (tmp >> 4) & 0x7;
7001
7002 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7003 goto fail;
7004
7005 switch (vco) {
7006 case 3200000:
7007 div_table = div_3200;
7008 break;
7009 case 4000000:
7010 div_table = div_4000;
7011 break;
7012 case 4800000:
7013 div_table = div_4800;
7014 break;
7015 case 5333333:
7016 div_table = div_5333;
7017 break;
7018 default:
7019 goto fail;
7020 }
7021
7022 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7023
caf4e252 7024fail:
34edce2f
VS		 7025 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7026 return 190476;
7027}
7028
2c07245f 7029static void
a65851af 7030intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7031{
a65851af
VS		 7032 while (*num > DATA_LINK_M_N_MASK ||
7033 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7034 *num >>= 1;
7035 *den >>= 1;
7036 }
7037}
7038
a65851af
VS		 7039static void compute_m_n(unsigned int m, unsigned int n,
7040 uint32_t *ret_m, uint32_t *ret_n)
7041{
7042 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7043 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7044 intel_reduce_m_n_ratio(ret_m, ret_n);
7045}
7046
e69d0bc1
DV		 7047void
7048intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7049 int pixel_clock, int link_clock,
7050 struct intel_link_m_n *m_n)
2c07245f 7051{
e69d0bc1 7052 m_n->tu = 64;
a65851af
VS		 7053
7054 compute_m_n(bits_per_pixel * pixel_clock,
7055 link_clock * nlanes * 8,
7056 &m_n->gmch_m, &m_n->gmch_n);
7057
7058 compute_m_n(pixel_clock, link_clock,
7059 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7060}
7061
a7615030
CW		 7062static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7063{
d330a953
JN		 7064 if (i915.panel_use_ssc >= 0)
7065 return i915.panel_use_ssc != 0;
41aa3448 7066 return dev_priv->vbt.lvds_use_ssc
435793df 7067 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7068}
7069
a93e255f
ACO		 7070static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7071 int num_connectors)
c65d77d8 7072{
a93e255f 7073 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 int refclk;
7076
a93e255f
ACO		 7077 WARN_ON(!crtc_state->base.state);
7078
5ab7b0b7 7079 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7080 refclk = 100000;
a93e255f 7081 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7082 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7083 refclk = dev_priv->vbt.lvds_ssc_freq;
7084 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7085 } else if (!IS_GEN2(dev)) {
7086 refclk = 96000;
7087 } else {
7088 refclk = 48000;
7089 }
7090
7091 return refclk;
7092}
7093
7429e9d4 7094static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7095{
7df00d7a 7096 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7097}
f47709a9 7098
7429e9d4
DV		 7099static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7100{
7101 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7102}
7103
f47709a9 7104static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7105 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7106 intel_clock_t *reduced_clock)
7107{
f47709a9 7108 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7109 u32 fp, fp2 = 0;
7110
7111 if (IS_PINEVIEW(dev)) {
190f68c5 7112 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7113 if (reduced_clock)
7429e9d4 7114 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7115 } else {
190f68c5 7116 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7117 if (reduced_clock)
7429e9d4 7118 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7119 }
7120
190f68c5 7121 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7122
f47709a9 7123 crtc->lowfreq_avail = false;
a93e255f 7124 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7125 reduced_clock) {
190f68c5 7126 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7127 crtc->lowfreq_avail = true;
a7516a05 7128 } else {
190f68c5 7129 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7130 }
7131}
7132
5e69f97f
CML		 7133static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7134 pipe)
89b667f8
JB		 7135{
7136 u32 reg_val;
7137
7138 /*
7139 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7140 * and set it to a reasonable value instead.
7141 */
ab3c759a 7142 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7143 reg_val &= 0xffffff00;
7144 reg_val |= 0x00000030;
ab3c759a 7145 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7146
ab3c759a 7147 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7148 reg_val &= 0x8cffffff;
7149 reg_val = 0x8c000000;
ab3c759a 7150 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7151
ab3c759a 7152 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7153 reg_val &= 0xffffff00;
ab3c759a 7154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7155
ab3c759a 7156 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7157 reg_val &= 0x00ffffff;
7158 reg_val |= 0xb0000000;
ab3c759a 7159 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7160}
7161
b551842d
DV		 7162static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7163 struct intel_link_m_n *m_n)
7164{
7165 struct drm_device *dev = crtc->base.dev;
7166 struct drm_i915_private *dev_priv = dev->dev_private;
7167 int pipe = crtc->pipe;
7168
e3b95f1e
DV		 7169 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7170 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7171 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7172 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7173}
7174
7175static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7176 struct intel_link_m_n *m_n,
7177 struct intel_link_m_n *m2_n2)
b551842d
DV		 7178{
7179 struct drm_device *dev = crtc->base.dev;
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 int pipe = crtc->pipe;
6e3c9717 7182 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7183
7184 if (INTEL_INFO(dev)->gen >= 5) {
7185 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7186 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7187 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7188 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7189 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7190 * for gen < 8) and if DRRS is supported (to make sure the
7191 * registers are not unnecessarily accessed).
7192 */
44395bfe 7193 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7194 crtc->config->has_drrs) {
f769cd24
VK		 7195 I915_WRITE(PIPE_DATA_M2(transcoder),
7196 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7197 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7198 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7199 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7200 }
b551842d 7201 } else {
e3b95f1e
DV		 7202 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7203 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7204 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7205 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7206 }
7207}
7208
fe3cd48d 7209void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7210{
fe3cd48d
R		 7211 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7212
7213 if (m_n == M1_N1) {
7214 dp_m_n = &crtc->config->dp_m_n;
7215 dp_m2_n2 = &crtc->config->dp_m2_n2;
7216 } else if (m_n == M2_N2) {
7217
7218 /*
7219 * M2_N2 registers are not supported. Hence m2_n2 divider value
7220 * needs to be programmed into M1_N1.
7221 */
7222 dp_m_n = &crtc->config->dp_m2_n2;
7223 } else {
7224 DRM_ERROR("Unsupported divider value\n");
7225 return;
7226 }
7227
6e3c9717
ACO		 7228 if (crtc->config->has_pch_encoder)
7229 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7230 else
fe3cd48d 7231 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7232}
7233
251ac862
DV		 7234static void vlv_compute_dpll(struct intel_crtc *crtc,
7235 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7236{
7237 u32 dpll, dpll_md;
7238
7239 /*
7240 * Enable DPIO clock input. We should never disable the reference
7241 * clock for pipe B, since VGA hotplug / manual detection depends
7242 * on it.
7243 */
60bfe44f
VS		 7244 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7245 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7246 /* We should never disable this, set it here for state tracking */
7247 if (crtc->pipe == PIPE_B)
7248 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7249 dpll |= DPLL_VCO_ENABLE;
d288f65f 7250 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7251
d288f65f 7252 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7253 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7254 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7255}
7256
d288f65f 7257static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7258 const struct intel_crtc_state *pipe_config)
a0c4da24 7259{
f47709a9 7260 struct drm_device *dev = crtc->base.dev;
a0c4da24 7261 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7262 int pipe = crtc->pipe;
bdd4b6a6 7263 u32 mdiv;
a0c4da24 7264 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7265 u32 coreclk, reg_val;
a0c4da24 7266
a580516d 7267 mutex_lock(&dev_priv->sb_lock);
09153000 7268
d288f65f
VS		 7269 bestn = pipe_config->dpll.n;
7270 bestm1 = pipe_config->dpll.m1;
7271 bestm2 = pipe_config->dpll.m2;
7272 bestp1 = pipe_config->dpll.p1;
7273 bestp2 = pipe_config->dpll.p2;
a0c4da24 7274
89b667f8
JB		 7275 /* See eDP HDMI DPIO driver vbios notes doc */
7276
7277 /* PLL B needs special handling */
bdd4b6a6 7278 if (pipe == PIPE_B)
5e69f97f 7279 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7280
7281 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7282 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7283
7284 /* Disable target IRef on PLL */
ab3c759a 7285 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7286 reg_val &= 0x00ffffff;
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7288
7289 /* Disable fast lock */
ab3c759a 7290 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7291
7292 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7293 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7294 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7295 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7296 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7297
7298 /*
7299 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7300 * but we don't support that).
7301 * Note: don't use the DAC post divider as it seems unstable.
7302 */
7303 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7305
a0c4da24 7306 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7307 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7308
89b667f8 7309 /* Set HBR and RBR LPF coefficients */
d288f65f 7310 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7311 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7312 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7313 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7314 0x009f0003);
89b667f8 7315 else
ab3c759a 7316 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7317 0x00d0000f);
7318
681a8504 7319 if (pipe_config->has_dp_encoder) {
89b667f8 7320 /* Use SSC source */
bdd4b6a6 7321 if (pipe == PIPE_A)
ab3c759a 7322 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7323 0x0df40000);
7324 else
ab3c759a 7325 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7326 0x0df70000);
7327 } else { /* HDMI or VGA */
7328 /* Use bend source */
bdd4b6a6 7329 if (pipe == PIPE_A)
ab3c759a 7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7331 0x0df70000);
7332 else
ab3c759a 7333 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7334 0x0df40000);
7335 }
a0c4da24 7336
ab3c759a 7337 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7338 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7339 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7340 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7341 coreclk |= 0x01000000;
ab3c759a 7342 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7343
ab3c759a 7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7345 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7346}
7347
251ac862
DV		 7348static void chv_compute_dpll(struct intel_crtc *crtc,
7349 struct intel_crtc_state *pipe_config)
1ae0d137 7350{
60bfe44f
VS		 7351 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7352 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7353 DPLL_VCO_ENABLE;
7354 if (crtc->pipe != PIPE_A)
d288f65f 7355 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7356
d288f65f
VS		 7357 pipe_config->dpll_hw_state.dpll_md =
7358 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7359}
7360
d288f65f 7361static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7362 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7363{
7364 struct drm_device *dev = crtc->base.dev;
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 int pipe = crtc->pipe;
7367 int dpll_reg = DPLL(crtc->pipe);
7368 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7369 u32 loopfilter, tribuf_calcntr;
9d556c99 7370 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7371 u32 dpio_val;
9cbe40c1 7372 int vco;
9d556c99 7373
d288f65f
VS		 7374 bestn = pipe_config->dpll.n;
7375 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7376 bestm1 = pipe_config->dpll.m1;
7377 bestm2 = pipe_config->dpll.m2 >> 22;
7378 bestp1 = pipe_config->dpll.p1;
7379 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7380 vco = pipe_config->dpll.vco;
a945ce7e 7381 dpio_val = 0;
9cbe40c1 7382 loopfilter = 0;
9d556c99
CML		 7383
7384 /*
7385 * Enable Refclk and SSC
7386 */
a11b0703 7387 I915_WRITE(dpll_reg,
d288f65f 7388 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7389
a580516d 7390 mutex_lock(&dev_priv->sb_lock);
9d556c99 7391
9d556c99
CML		 7392 /* p1 and p2 divider */
7393 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7394 5 << DPIO_CHV_S1_DIV_SHIFT |
7395 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7396 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7397 1 << DPIO_CHV_K_DIV_SHIFT);
7398
7399 /* Feedback post-divider - m2 */
7400 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7401
7402 /* Feedback refclk divider - n and m1 */
7403 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7404 DPIO_CHV_M1_DIV_BY_2 |
7405 1 << DPIO_CHV_N_DIV_SHIFT);
7406
7407 /* M2 fraction division */
25a25dfc 7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7409
7410 /* M2 fraction division enable */
a945ce7e
VP		 7411 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7412 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7413 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7414 if (bestm2_frac)
7415 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7416 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7417
de3a0fde
VP		 7418 /* Program digital lock detect threshold */
7419 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7420 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7421 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7422 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7423 if (!bestm2_frac)
7424 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7425 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7426
9d556c99 7427 /* Loop filter */
9cbe40c1
VP		 7428 if (vco == 5400000) {
7429 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7430 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7431 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7432 tribuf_calcntr = 0x9;
7433 } else if (vco <= 6200000) {
7434 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7435 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7436 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7437 tribuf_calcntr = 0x9;
7438 } else if (vco <= 6480000) {
7439 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7440 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7441 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7442 tribuf_calcntr = 0x8;
7443 } else {
7444 /* Not supported. Apply the same limits as in the max case */
7445 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7446 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7447 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7448 tribuf_calcntr = 0;
7449 }
9d556c99
CML		 7450 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7451
968040b2 7452 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7453 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7454 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7455 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7456
9d556c99
CML		 7457 /* AFC Recal */
7458 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7459 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7460 DPIO_AFC_RECAL);
7461
a580516d 7462 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7463}
7464
d288f65f
VS		 7465/**
7466 * vlv_force_pll_on - forcibly enable just the PLL
7467 * @dev_priv: i915 private structure
7468 * @pipe: pipe PLL to enable
7469 * @dpll: PLL configuration
7470 *
7471 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7472 * in cases where we need the PLL enabled even when @pipe is not going to
7473 * be enabled.
7474 */
7475void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7476 const struct dpll *dpll)
7477{
7478 struct intel_crtc *crtc =
7479 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7480 struct intel_crtc_state pipe_config = {
a93e255f 7481 .base.crtc = &crtc->base,
d288f65f
VS		 7482 .pixel_multiplier = 1,
7483 .dpll = *dpll,
7484 };
7485
7486 if (IS_CHERRYVIEW(dev)) {
251ac862 7487 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7488 chv_prepare_pll(crtc, &pipe_config);
7489 chv_enable_pll(crtc, &pipe_config);
7490 } else {
251ac862 7491 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7492 vlv_prepare_pll(crtc, &pipe_config);
7493 vlv_enable_pll(crtc, &pipe_config);
7494 }
7495}
7496
7497/**
7498 * vlv_force_pll_off - forcibly disable just the PLL
7499 * @dev_priv: i915 private structure
7500 * @pipe: pipe PLL to disable
7501 *
7502 * Disable the PLL for @pipe. To be used in cases where we need
7503 * the PLL enabled even when @pipe is not going to be enabled.
7504 */
7505void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7506{
7507 if (IS_CHERRYVIEW(dev))
7508 chv_disable_pll(to_i915(dev), pipe);
7509 else
7510 vlv_disable_pll(to_i915(dev), pipe);
7511}
7512
251ac862
DV		 7513static void i9xx_compute_dpll(struct intel_crtc *crtc,
7514 struct intel_crtc_state *crtc_state,
7515 intel_clock_t *reduced_clock,
7516 int num_connectors)
eb1cbe48 7517{
f47709a9 7518 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7519 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7520 u32 dpll;
7521 bool is_sdvo;
190f68c5 7522 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7523
190f68c5 7524 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7525
a93e255f
ACO		 7526 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7527 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7528
7529 dpll = DPLL_VGA_MODE_DIS;
7530
a93e255f 7531 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7532 dpll |= DPLLB_MODE_LVDS;
7533 else
7534 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7535
ef1b460d 7536 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7537 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7538 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7539 }
198a037f
DV		 7540
7541 if (is_sdvo)
4a33e48d 7542 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7543
190f68c5 7544 if (crtc_state->has_dp_encoder)
4a33e48d 7545 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7546
7547 /* compute bitmask from p1 value */
7548 if (IS_PINEVIEW(dev))
7549 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7550 else {
7551 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7552 if (IS_G4X(dev) && reduced_clock)
7553 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7554 }
7555 switch (clock->p2) {
7556 case 5:
7557 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7558 break;
7559 case 7:
7560 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7561 break;
7562 case 10:
7563 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7564 break;
7565 case 14:
7566 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7567 break;
7568 }
7569 if (INTEL_INFO(dev)->gen >= 4)
7570 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7571
190f68c5 7572 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7573 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7574 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7575 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7576 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7577 else
7578 dpll |= PLL_REF_INPUT_DREFCLK;
7579
7580 dpll |= DPLL_VCO_ENABLE;
190f68c5 7581 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7582
eb1cbe48 7583 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7584 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7585 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7586 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7587 }
7588}
7589
251ac862
DV		 7590static void i8xx_compute_dpll(struct intel_crtc *crtc,
7591 struct intel_crtc_state *crtc_state,
7592 intel_clock_t *reduced_clock,
7593 int num_connectors)
eb1cbe48 7594{
f47709a9 7595 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7596 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7597 u32 dpll;
190f68c5 7598 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7599
190f68c5 7600 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7601
eb1cbe48
DV		 7602 dpll = DPLL_VGA_MODE_DIS;
7603
a93e255f 7604 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7605 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7606 } else {
7607 if (clock->p1 == 2)
7608 dpll |= PLL_P1_DIVIDE_BY_TWO;
7609 else
7610 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611 if (clock->p2 == 4)
7612 dpll |= PLL_P2_DIVIDE_BY_4;
7613 }
7614
a93e255f 7615 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7616 dpll |= DPLL_DVO_2X_MODE;
7617
a93e255f 7618 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7619 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7620 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7621 else
7622 dpll |= PLL_REF_INPUT_DREFCLK;
7623
7624 dpll |= DPLL_VCO_ENABLE;
190f68c5 7625 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7626}
7627
8a654f3b 7628static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7629{
7630 struct drm_device *dev = intel_crtc->base.dev;
7631 struct drm_i915_private *dev_priv = dev->dev_private;
7632 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7633 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7634 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7635 uint32_t crtc_vtotal, crtc_vblank_end;
7636 int vsyncshift = 0;
4d8a62ea
DV		 7637
7638 /* We need to be careful not to changed the adjusted mode, for otherwise
7639 * the hw state checker will get angry at the mismatch. */
7640 crtc_vtotal = adjusted_mode->crtc_vtotal;
7641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7642
609aeaca 7643 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7644 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7645 crtc_vtotal -= 1;
7646 crtc_vblank_end -= 1;
609aeaca 7647
409ee761 7648 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7649 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7650 else
7651 vsyncshift = adjusted_mode->crtc_hsync_start -
7652 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7653 if (vsyncshift < 0)
7654 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7655 }
7656
7657 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7658 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7659
fe2b8f9d 7660 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7661 (adjusted_mode->crtc_hdisplay - 1) |
7662 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7663 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7664 (adjusted_mode->crtc_hblank_start - 1) |
7665 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7666 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7667 (adjusted_mode->crtc_hsync_start - 1) |
7668 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7669
fe2b8f9d 7670 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7671 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7672 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7673 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7674 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7675 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7676 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7677 (adjusted_mode->crtc_vsync_start - 1) |
7678 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7679
b5e508d4
PZ		 7680 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7681 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7682 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7683 * bits. */
7684 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7685 (pipe == PIPE_B || pipe == PIPE_C))
7686 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7687
b0e77b9c
PZ		 7688 /* pipesrc controls the size that is scaled from, which should
7689 * always be the user's requested size.
7690 */
7691 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7692 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7693 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7694}
7695
1bd1bd80 7696static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7697 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7698{
7699 struct drm_device *dev = crtc->base.dev;
7700 struct drm_i915_private *dev_priv = dev->dev_private;
7701 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7702 uint32_t tmp;
7703
7704 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7705 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7706 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7707 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7708 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7709 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7710 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7711 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7712 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7713
7714 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7715 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7716 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7717 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7718 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7719 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7720 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7721 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7722 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7723
7724 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7725 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7726 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7727 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7728 }
7729
7730 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7731 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7732 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7733
2d112de7
ACO		 7734 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7735 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7736}
7737
f6a83288 7738void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7739 struct intel_crtc_state *pipe_config)
babea61d 7740{
2d112de7
ACO		 7741 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7742 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7743 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7744 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7745
2d112de7
ACO		 7746 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7747 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7748 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7749 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7750
2d112de7 7751 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7752 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7753
2d112de7
ACO		 7754 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7755 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7756
7757 mode->hsync = drm_mode_hsync(mode);
7758 mode->vrefresh = drm_mode_vrefresh(mode);
7759 drm_mode_set_name(mode);
babea61d
JB		 7760}
7761
84b046f3
DV		 7762static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7763{
7764 struct drm_device *dev = intel_crtc->base.dev;
7765 struct drm_i915_private *dev_priv = dev->dev_private;
7766 uint32_t pipeconf;
7767
9f11a9e4 7768 pipeconf = 0;
84b046f3 7769
b6b5d049
VS		 7770 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7771 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7772 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7773
6e3c9717 7774 if (intel_crtc->config->double_wide)
cf532bb2 7775 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7776
ff9ce46e
DV		 7777 /* only g4x and later have fancy bpc/dither controls */
7778 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7779 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7780 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7781 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7782 PIPECONF_DITHER_TYPE_SP;
84b046f3 7783
6e3c9717 7784 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7785 case 18:
7786 pipeconf |= PIPECONF_6BPC;
7787 break;
7788 case 24:
7789 pipeconf |= PIPECONF_8BPC;
7790 break;
7791 case 30:
7792 pipeconf |= PIPECONF_10BPC;
7793 break;
7794 default:
7795 /* Case prevented by intel_choose_pipe_bpp_dither. */
7796 BUG();
84b046f3
DV		 7797 }
7798 }
7799
7800 if (HAS_PIPE_CXSR(dev)) {
7801 if (intel_crtc->lowfreq_avail) {
7802 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7803 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7804 } else {
7805 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7806 }
7807 }
7808
6e3c9717 7809 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7810 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7811 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7812 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7813 else
7814 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7815 } else
84b046f3
DV		 7816 pipeconf |= PIPECONF_PROGRESSIVE;
7817
6e3c9717 7818 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7819 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7820
84b046f3
DV		 7821 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7822 POSTING_READ(PIPECONF(intel_crtc->pipe));
7823}
7824
190f68c5
ACO		 7825static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7826 struct intel_crtc_state *crtc_state)
79e53945 7827{
c7653199 7828 struct drm_device *dev = crtc->base.dev;
79e53945 7829 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7830 int refclk, num_connectors = 0;
c329a4ec
DV		 7831 intel_clock_t clock;
7832 bool ok;
7833 bool is_dsi = false;
5eddb70b 7834 struct intel_encoder *encoder;
d4906093 7835 const intel_limit_t *limit;
55bb9992 7836 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7837 struct drm_connector *connector;
55bb9992
ACO		 7838 struct drm_connector_state *connector_state;
7839 int i;
79e53945 7840
dd3cd74a
ACO		 7841 memset(&crtc_state->dpll_hw_state, 0,
7842 sizeof(crtc_state->dpll_hw_state));
7843
da3ced29 7844 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7845 if (connector_state->crtc != &crtc->base)
7846 continue;
7847
7848 encoder = to_intel_encoder(connector_state->best_encoder);
7849
5eddb70b 7850 switch (encoder->type) {
e9fd1c02
JN		 7851 case INTEL_OUTPUT_DSI:
7852 is_dsi = true;
7853 break;
6847d71b
PZ		 7854 default:
7855 break;
79e53945 7856 }
43565a06 7857
c751ce4f 7858 num_connectors++;
79e53945
JB		 7859 }
7860
f2335330 7861 if (is_dsi)
5b18e57c 7862 return 0;
f2335330 7863
190f68c5 7864 if (!crtc_state->clock_set) {
a93e255f 7865 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7866
e9fd1c02
JN		 7867 /*
7868 * Returns a set of divisors for the desired target clock with
7869 * the given refclk, or FALSE. The returned values represent
7870 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7871 * 2) / p1 / p2.
7872 */
a93e255f
ACO		 7873 limit = intel_limit(crtc_state, refclk);
7874 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7875 crtc_state->port_clock,
e9fd1c02 7876 refclk, NULL, &clock);
f2335330 7877 if (!ok) {
e9fd1c02
JN		 7878 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7879 return -EINVAL;
7880 }
79e53945 7881
f2335330 7882 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7883 crtc_state->dpll.n = clock.n;
7884 crtc_state->dpll.m1 = clock.m1;
7885 crtc_state->dpll.m2 = clock.m2;
7886 crtc_state->dpll.p1 = clock.p1;
7887 crtc_state->dpll.p2 = clock.p2;
f47709a9 7888 }
7026d4ac 7889
e9fd1c02 7890 if (IS_GEN2(dev)) {
c329a4ec 7891 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7892 num_connectors);
9d556c99 7893 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7894 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7895 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7896 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7897 } else {
c329a4ec 7898 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7899 num_connectors);
e9fd1c02 7900 }
79e53945 7901
c8f7a0db 7902 return 0;
f564048e
EA		 7903}
7904
2fa2fe9a 7905static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7906 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7907{
7908 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 uint32_t tmp;
7911
dc9e7dec
VS		 7912 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7913 return;
7914
2fa2fe9a 7915 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7916 if (!(tmp & PFIT_ENABLE))
7917 return;
2fa2fe9a 7918
06922821 7919 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7920 if (INTEL_INFO(dev)->gen < 4) {
7921 if (crtc->pipe != PIPE_B)
7922 return;
2fa2fe9a
DV		 7923 } else {
7924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7925 return;
7926 }
7927
06922821 7928 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7929 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7930 if (INTEL_INFO(dev)->gen < 5)
7931 pipe_config->gmch_pfit.lvds_border_bits =
7932 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7933}
7934
acbec814 7935static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7936 struct intel_crtc_state *pipe_config)
acbec814
JB		 7937{
7938 struct drm_device *dev = crtc->base.dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 int pipe = pipe_config->cpu_transcoder;
7941 intel_clock_t clock;
7942 u32 mdiv;
662c6ecb 7943 int refclk = 100000;
acbec814 7944
f573de5a
SK		 7945 /* In case of MIPI DPLL will not even be used */
7946 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7947 return;
7948
a580516d 7949 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7950 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7951 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7952
7953 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7954 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7955 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7956 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7957 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7958
dccbea3b 7959 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7960}
7961
5724dbd1
DL		 7962static void
7963i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7964 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7965{
7966 struct drm_device *dev = crtc->base.dev;
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7968 u32 val, base, offset;
7969 int pipe = crtc->pipe, plane = crtc->plane;
7970 int fourcc, pixel_format;
6761dd31 7971 unsigned int aligned_height;
b113d5ee 7972 struct drm_framebuffer *fb;
1b842c89 7973 struct intel_framebuffer *intel_fb;
1ad292b5 7974
42a7b088
DL		 7975 val = I915_READ(DSPCNTR(plane));
7976 if (!(val & DISPLAY_PLANE_ENABLE))
7977 return;
7978
d9806c9f 7979 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7980 if (!intel_fb) {
1ad292b5
JB		 7981 DRM_DEBUG_KMS("failed to alloc fb\n");
7982 return;
7983 }
7984
1b842c89
DL		 7985 fb = &intel_fb->base;
7986
18c5247e
DV		 7987 if (INTEL_INFO(dev)->gen >= 4) {
7988 if (val & DISPPLANE_TILED) {
49af449b 7989 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7990 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7991 }
7992 }
1ad292b5
JB		 7993
7994 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7995 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7996 fb->pixel_format = fourcc;
7997 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7998
7999 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8000 if (plane_config->tiling)
1ad292b5
JB		 8001 offset = I915_READ(DSPTILEOFF(plane));
8002 else
8003 offset = I915_READ(DSPLINOFF(plane));
8004 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8005 } else {
8006 base = I915_READ(DSPADDR(plane));
8007 }
8008 plane_config->base = base;
8009
8010 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8011 fb->width = ((val >> 16) & 0xfff) + 1;
8012 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8013
8014 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8015 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8016
b113d5ee 8017 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8018 fb->pixel_format,
8019 fb->modifier[0]);
1ad292b5 8020
f37b5c2b 8021 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8022
2844a921
DL		 8023 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8024 pipe_name(pipe), plane, fb->width, fb->height,
8025 fb->bits_per_pixel, base, fb->pitches[0],
8026 plane_config->size);
1ad292b5 8027
2d14030b 8028 plane_config->fb = intel_fb;
1ad292b5
JB		 8029}
8030
70b23a98 8031static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8032 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8033{
8034 struct drm_device *dev = crtc->base.dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 int pipe = pipe_config->cpu_transcoder;
8037 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8038 intel_clock_t clock;
0d7b6b11 8039 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8040 int refclk = 100000;
8041
a580516d 8042 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8043 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8044 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8045 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8046 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8047 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8048 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8049
8050 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8051 clock.m2 = (pll_dw0 & 0xff) << 22;
8052 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8053 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8054 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8055 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8056 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8057
dccbea3b 8058 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8059}
8060
0e8ffe1b 8061static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8062 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8063{
8064 struct drm_device *dev = crtc->base.dev;
8065 struct drm_i915_private *dev_priv = dev->dev_private;
8066 uint32_t tmp;
8067
f458ebbc
DV		 8068 if (!intel_display_power_is_enabled(dev_priv,
8069 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8070 return false;
8071
e143a21c 8072 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8073 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8074
0e8ffe1b
DV		 8075 tmp = I915_READ(PIPECONF(crtc->pipe));
8076 if (!(tmp & PIPECONF_ENABLE))
8077 return false;
8078
42571aef
VS		 8079 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8080 switch (tmp & PIPECONF_BPC_MASK) {
8081 case PIPECONF_6BPC:
8082 pipe_config->pipe_bpp = 18;
8083 break;
8084 case PIPECONF_8BPC:
8085 pipe_config->pipe_bpp = 24;
8086 break;
8087 case PIPECONF_10BPC:
8088 pipe_config->pipe_bpp = 30;
8089 break;
8090 default:
8091 break;
8092 }
8093 }
8094
b5a9fa09
DV		 8095 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8096 pipe_config->limited_color_range = true;
8097
282740f7
VS		 8098 if (INTEL_INFO(dev)->gen < 4)
8099 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8100
1bd1bd80
DV		 8101 intel_get_pipe_timings(crtc, pipe_config);
8102
2fa2fe9a
DV		 8103 i9xx_get_pfit_config(crtc, pipe_config);
8104
6c49f241
DV		 8105 if (INTEL_INFO(dev)->gen >= 4) {
8106 tmp = I915_READ(DPLL_MD(crtc->pipe));
8107 pipe_config->pixel_multiplier =
8108 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8109 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8110 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8111 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8112 tmp = I915_READ(DPLL(crtc->pipe));
8113 pipe_config->pixel_multiplier =
8114 ((tmp & SDVO_MULTIPLIER_MASK)
8115 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8116 } else {
8117 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8118 * port and will be fixed up in the encoder->get_config
8119 * function. */
8120 pipe_config->pixel_multiplier = 1;
8121 }
8bcc2795
DV		 8122 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8123 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8124 /*
8125 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8126 * on 830. Filter it out here so that we don't
8127 * report errors due to that.
8128 */
8129 if (IS_I830(dev))
8130 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8131
8bcc2795
DV		 8132 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8133 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8134 } else {
8135 /* Mask out read-only status bits. */
8136 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8137 DPLL_PORTC_READY_MASK |
8138 DPLL_PORTB_READY_MASK);
8bcc2795 8139 }
6c49f241 8140
70b23a98
VS		 8141 if (IS_CHERRYVIEW(dev))
8142 chv_crtc_clock_get(crtc, pipe_config);
8143 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8144 vlv_crtc_clock_get(crtc, pipe_config);
8145 else
8146 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8147
0f64614d
VS		 8148 /*
8149 * Normally the dotclock is filled in by the encoder .get_config()
8150 * but in case the pipe is enabled w/o any ports we need a sane
8151 * default.
8152 */
8153 pipe_config->base.adjusted_mode.crtc_clock =
8154 pipe_config->port_clock / pipe_config->pixel_multiplier;
8155
0e8ffe1b
DV		 8156 return true;
8157}
8158
dde86e2d 8159static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8160{
8161 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8162 struct intel_encoder *encoder;
74cfd7ac 8163 u32 val, final;
13d83a67 8164 bool has_lvds = false;
199e5d79 8165 bool has_cpu_edp = false;
199e5d79 8166 bool has_panel = false;
99eb6a01
KP		 8167 bool has_ck505 = false;
8168 bool can_ssc = false;
13d83a67
JB		 8169
8170 /* We need to take the global config into account */
b2784e15 8171 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8172 switch (encoder->type) {
8173 case INTEL_OUTPUT_LVDS:
8174 has_panel = true;
8175 has_lvds = true;
8176 break;
8177 case INTEL_OUTPUT_EDP:
8178 has_panel = true;
2de6905f 8179 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8180 has_cpu_edp = true;
8181 break;
6847d71b
PZ		 8182 default:
8183 break;
13d83a67
JB		 8184 }
8185 }
8186
99eb6a01 8187 if (HAS_PCH_IBX(dev)) {
41aa3448 8188 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8189 can_ssc = has_ck505;
8190 } else {
8191 has_ck505 = false;
8192 can_ssc = true;
8193 }
8194
2de6905f
ID		 8195 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8196 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8197
8198 /* Ironlake: try to setup display ref clock before DPLL
8199 * enabling. This is only under driver's control after
8200 * PCH B stepping, previous chipset stepping should be
8201 * ignoring this setting.
8202 */
74cfd7ac
CW		 8203 val = I915_READ(PCH_DREF_CONTROL);
8204
8205 /* As we must carefully and slowly disable/enable each source in turn,
8206 * compute the final state we want first and check if we need to
8207 * make any changes at all.
8208 */
8209 final = val;
8210 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8211 if (has_ck505)
8212 final |= DREF_NONSPREAD_CK505_ENABLE;
8213 else
8214 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8215
8216 final &= ~DREF_SSC_SOURCE_MASK;
8217 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8218 final &= ~DREF_SSC1_ENABLE;
8219
8220 if (has_panel) {
8221 final |= DREF_SSC_SOURCE_ENABLE;
8222
8223 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8224 final |= DREF_SSC1_ENABLE;
8225
8226 if (has_cpu_edp) {
8227 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8228 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8229 else
8230 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8231 } else
8232 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8233 } else {
8234 final |= DREF_SSC_SOURCE_DISABLE;
8235 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8236 }
8237
8238 if (final == val)
8239 return;
8240
13d83a67 8241 /* Always enable nonspread source */
74cfd7ac 8242 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8243
99eb6a01 8244 if (has_ck505)
74cfd7ac 8245 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8246 else
74cfd7ac 8247 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8248
199e5d79 8249 if (has_panel) {
74cfd7ac
CW		 8250 val &= ~DREF_SSC_SOURCE_MASK;
8251 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8252
199e5d79 8253 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8254 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8255 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8256 val |= DREF_SSC1_ENABLE;
e77166b5 8257 } else
74cfd7ac 8258 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8259
8260 /* Get SSC going before enabling the outputs */
74cfd7ac 8261 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8262 POSTING_READ(PCH_DREF_CONTROL);
8263 udelay(200);
8264
74cfd7ac 8265 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8266
8267 /* Enable CPU source on CPU attached eDP */
199e5d79 8268 if (has_cpu_edp) {
99eb6a01 8269 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8270 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8271 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8272 } else
74cfd7ac 8273 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8274 } else
74cfd7ac 8275 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8276
74cfd7ac 8277 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8278 POSTING_READ(PCH_DREF_CONTROL);
8279 udelay(200);
8280 } else {
8281 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8282
74cfd7ac 8283 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8284
8285 /* Turn off CPU output */
74cfd7ac 8286 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8287
74cfd7ac 8288 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8289 POSTING_READ(PCH_DREF_CONTROL);
8290 udelay(200);
8291
8292 /* Turn off the SSC source */
74cfd7ac
CW		 8293 val &= ~DREF_SSC_SOURCE_MASK;
8294 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8295
8296 /* Turn off SSC1 */
74cfd7ac 8297 val &= ~DREF_SSC1_ENABLE;
199e5d79 8298
74cfd7ac 8299 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8300 POSTING_READ(PCH_DREF_CONTROL);
8301 udelay(200);
8302 }
74cfd7ac
CW		 8303
8304 BUG_ON(val != final);
13d83a67
JB		 8305}
8306
f31f2d55 8307static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8308{
f31f2d55 8309 uint32_t tmp;
dde86e2d 8310
0ff066a9
PZ		 8311 tmp = I915_READ(SOUTH_CHICKEN2);
8312 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8313 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8314
0ff066a9
PZ		 8315 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8316 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8317 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8318
0ff066a9
PZ		 8319 tmp = I915_READ(SOUTH_CHICKEN2);
8320 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8321 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8322
0ff066a9
PZ		 8323 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8324 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8325 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8326}
8327
8328/* WaMPhyProgramming:hsw */
8329static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8330{
8331 uint32_t tmp;
dde86e2d
PZ		 8332
8333 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8334 tmp &= ~(0xFF << 24);
8335 tmp |= (0x12 << 24);
8336 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8337
dde86e2d
PZ		 8338 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8339 tmp |= (1 << 11);
8340 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8343 tmp |= (1 << 11);
8344 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8345
dde86e2d
PZ		 8346 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8347 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8348 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8351 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8352 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8353
0ff066a9
PZ		 8354 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8355 tmp &= ~(7 << 13);
8356 tmp |= (5 << 13);
8357 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8358
0ff066a9
PZ		 8359 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8360 tmp &= ~(7 << 13);
8361 tmp |= (5 << 13);
8362 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8363
8364 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8365 tmp &= ~0xFF;
8366 tmp |= 0x1C;
8367 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8368
8369 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8370 tmp &= ~0xFF;
8371 tmp |= 0x1C;
8372 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8373
8374 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8375 tmp &= ~(0xFF << 16);
8376 tmp |= (0x1C << 16);
8377 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8378
8379 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8380 tmp &= ~(0xFF << 16);
8381 tmp |= (0x1C << 16);
8382 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8383
0ff066a9
PZ		 8384 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8385 tmp |= (1 << 27);
8386 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8387
0ff066a9
PZ		 8388 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8389 tmp |= (1 << 27);
8390 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8391
0ff066a9
PZ		 8392 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8393 tmp &= ~(0xF << 28);
8394 tmp |= (4 << 28);
8395 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8396
0ff066a9
PZ		 8397 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8398 tmp &= ~(0xF << 28);
8399 tmp |= (4 << 28);
8400 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8401}
8402
2fa86a1f
PZ		 8403/* Implements 3 different sequences from BSpec chapter "Display iCLK
8404 * Programming" based on the parameters passed:
8405 * - Sequence to enable CLKOUT_DP
8406 * - Sequence to enable CLKOUT_DP without spread
8407 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8408 */
8409static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8410 bool with_fdi)
f31f2d55
PZ		 8411{
8412 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8413 uint32_t reg, tmp;
8414
8415 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8416 with_spread = true;
c2699524 8417 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8418 with_fdi = false;
f31f2d55 8419
a580516d 8420 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8421
8422 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8423 tmp &= ~SBI_SSCCTL_DISABLE;
8424 tmp |= SBI_SSCCTL_PATHALT;
8425 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8426
8427 udelay(24);
8428
2fa86a1f
PZ		 8429 if (with_spread) {
8430 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8431 tmp &= ~SBI_SSCCTL_PATHALT;
8432 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8433
2fa86a1f
PZ		 8434 if (with_fdi) {
8435 lpt_reset_fdi_mphy(dev_priv);
8436 lpt_program_fdi_mphy(dev_priv);
8437 }
8438 }
dde86e2d 8439
c2699524 8440 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8441 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8442 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8443 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8444
a580516d 8445 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8446}
8447
47701c3b
PZ		 8448/* Sequence to disable CLKOUT_DP */
8449static void lpt_disable_clkout_dp(struct drm_device *dev)
8450{
8451 struct drm_i915_private *dev_priv = dev->dev_private;
8452 uint32_t reg, tmp;
8453
a580516d 8454 mutex_lock(&dev_priv->sb_lock);
47701c3b 8455
c2699524 8456 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8457 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8458 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8459 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8460
8461 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8462 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8463 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8464 tmp |= SBI_SSCCTL_PATHALT;
8465 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8466 udelay(32);
8467 }
8468 tmp |= SBI_SSCCTL_DISABLE;
8469 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8470 }
8471
a580516d 8472 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8473}
8474
bf8fa3d3
PZ		 8475static void lpt_init_pch_refclk(struct drm_device *dev)
8476{
bf8fa3d3
PZ		 8477 struct intel_encoder *encoder;
8478 bool has_vga = false;
8479
b2784e15 8480 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8481 switch (encoder->type) {
8482 case INTEL_OUTPUT_ANALOG:
8483 has_vga = true;
8484 break;
6847d71b
PZ		 8485 default:
8486 break;
bf8fa3d3
PZ		 8487 }
8488 }
8489
47701c3b
PZ		 8490 if (has_vga)
8491 lpt_enable_clkout_dp(dev, true, true);
8492 else
8493 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8494}
8495
dde86e2d
PZ		 8496/*
8497 * Initialize reference clocks when the driver loads
8498 */
8499void intel_init_pch_refclk(struct drm_device *dev)
8500{
8501 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8502 ironlake_init_pch_refclk(dev);
8503 else if (HAS_PCH_LPT(dev))
8504 lpt_init_pch_refclk(dev);
8505}
8506
55bb9992 8507static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8508{
55bb9992 8509 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8510 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8511 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8512 struct drm_connector *connector;
55bb9992 8513 struct drm_connector_state *connector_state;
d9d444cb 8514 struct intel_encoder *encoder;
55bb9992 8515 int num_connectors = 0, i;
d9d444cb
JB		 8516 bool is_lvds = false;
8517
da3ced29 8518 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8519 if (connector_state->crtc != crtc_state->base.crtc)
8520 continue;
8521
8522 encoder = to_intel_encoder(connector_state->best_encoder);
8523
d9d444cb
JB		 8524 switch (encoder->type) {
8525 case INTEL_OUTPUT_LVDS:
8526 is_lvds = true;
8527 break;
6847d71b
PZ		 8528 default:
8529 break;
d9d444cb
JB		 8530 }
8531 num_connectors++;
8532 }
8533
8534 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8535 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8536 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8537 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8538 }
8539
8540 return 120000;
8541}
8542
6ff93609 8543static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8544{
c8203565 8545 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8547 int pipe = intel_crtc->pipe;
c8203565
PZ		 8548 uint32_t val;
8549
78114071 8550 val = 0;
c8203565 8551
6e3c9717 8552 switch (intel_crtc->config->pipe_bpp) {
c8203565 8553 case 18:
dfd07d72 8554 val |= PIPECONF_6BPC;
c8203565
PZ		 8555 break;
8556 case 24:
dfd07d72 8557 val |= PIPECONF_8BPC;
c8203565
PZ		 8558 break;
8559 case 30:
dfd07d72 8560 val |= PIPECONF_10BPC;
c8203565
PZ		 8561 break;
8562 case 36:
dfd07d72 8563 val |= PIPECONF_12BPC;
c8203565
PZ		 8564 break;
8565 default:
cc769b62
PZ		 8566 /* Case prevented by intel_choose_pipe_bpp_dither. */
8567 BUG();
c8203565
PZ		 8568 }
8569
6e3c9717 8570 if (intel_crtc->config->dither)
c8203565
PZ		 8571 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8572
6e3c9717 8573 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8574 val |= PIPECONF_INTERLACED_ILK;
8575 else
8576 val |= PIPECONF_PROGRESSIVE;
8577
6e3c9717 8578 if (intel_crtc->config->limited_color_range)
3685a8f3 8579 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8580
c8203565
PZ		 8581 I915_WRITE(PIPECONF(pipe), val);
8582 POSTING_READ(PIPECONF(pipe));
8583}
8584
86d3efce
VS		 8585/*
8586 * Set up the pipe CSC unit.
8587 *
8588 * Currently only full range RGB to limited range RGB conversion
8589 * is supported, but eventually this should handle various
8590 * RGB<->YCbCr scenarios as well.
8591 */
50f3b016 8592static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8593{
8594 struct drm_device *dev = crtc->dev;
8595 struct drm_i915_private *dev_priv = dev->dev_private;
8596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8597 int pipe = intel_crtc->pipe;
8598 uint16_t coeff = 0x7800; /* 1.0 */
8599
8600 /*
8601 * TODO: Check what kind of values actually come out of the pipe
8602 * with these coeff/postoff values and adjust to get the best
8603 * accuracy. Perhaps we even need to take the bpc value into
8604 * consideration.
8605 */
8606
6e3c9717 8607 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8608 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8609
8610 /*
8611 * GY/GU and RY/RU should be the other way around according
8612 * to BSpec, but reality doesn't agree. Just set them up in
8613 * a way that results in the correct picture.
8614 */
8615 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8616 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8617
8618 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8619 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8620
8621 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8622 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8623
8624 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8625 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8626 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8627
8628 if (INTEL_INFO(dev)->gen > 6) {
8629 uint16_t postoff = 0;
8630
6e3c9717 8631 if (intel_crtc->config->limited_color_range)
32cf0cb0 8632 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8633
8634 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8635 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8636 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8637
8638 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8639 } else {
8640 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8641
6e3c9717 8642 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8643 mode |= CSC_BLACK_SCREEN_OFFSET;
8644
8645 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8646 }
8647}
8648
6ff93609 8649static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8650{
756f85cf
PZ		 8651 struct drm_device *dev = crtc->dev;
8652 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8654 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8655 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8656 uint32_t val;
8657
3eff4faa 8658 val = 0;
ee2b0b38 8659
6e3c9717 8660 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8661 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8662
6e3c9717 8663 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8664 val |= PIPECONF_INTERLACED_ILK;
8665 else
8666 val |= PIPECONF_PROGRESSIVE;
8667
702e7a56
PZ		 8668 I915_WRITE(PIPECONF(cpu_transcoder), val);
8669 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8670
8671 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8672 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8673
3cdf122c 8674 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8675 val = 0;
8676
6e3c9717 8677 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8678 case 18:
8679 val |= PIPEMISC_DITHER_6_BPC;
8680 break;
8681 case 24:
8682 val |= PIPEMISC_DITHER_8_BPC;
8683 break;
8684 case 30:
8685 val |= PIPEMISC_DITHER_10_BPC;
8686 break;
8687 case 36:
8688 val |= PIPEMISC_DITHER_12_BPC;
8689 break;
8690 default:
8691 /* Case prevented by pipe_config_set_bpp. */
8692 BUG();
8693 }
8694
6e3c9717 8695 if (intel_crtc->config->dither)
756f85cf
PZ		 8696 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8697
8698 I915_WRITE(PIPEMISC(pipe), val);
8699 }
ee2b0b38
PZ		 8700}
8701
6591c6e4 8702static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8703 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8704 intel_clock_t *clock,
8705 bool *has_reduced_clock,
8706 intel_clock_t *reduced_clock)
8707{
8708 struct drm_device *dev = crtc->dev;
8709 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8710 int refclk;
d4906093 8711 const intel_limit_t *limit;
c329a4ec 8712 bool ret;
79e53945 8713
55bb9992 8714 refclk = ironlake_get_refclk(crtc_state);
79e53945 8715
d4906093
ML		 8716 /*
8717 * Returns a set of divisors for the desired target clock with the given
8718 * refclk, or FALSE. The returned values represent the clock equation:
8719 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8720 */
a93e255f
ACO		 8721 limit = intel_limit(crtc_state, refclk);
8722 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8723 crtc_state->port_clock,
ee9300bb 8724 refclk, NULL, clock);
6591c6e4
PZ		 8725 if (!ret)
8726 return false;
cda4b7d3 8727
6591c6e4
PZ		 8728 return true;
8729}
8730
d4b1931c
PZ		 8731int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8732{
8733 /*
8734 * Account for spread spectrum to avoid
8735 * oversubscribing the link. Max center spread
8736 * is 2.5%; use 5% for safety's sake.
8737 */
8738 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8739 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8740}
8741
7429e9d4 8742static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8743{
7429e9d4 8744 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8745}
8746
de13a2e3 8747static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8748 struct intel_crtc_state *crtc_state,
7429e9d4 8749 u32 *fp,
9a7c7890 8750 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8751{
de13a2e3 8752 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8753 struct drm_device *dev = crtc->dev;
8754 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8755 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8756 struct drm_connector *connector;
55bb9992
ACO		 8757 struct drm_connector_state *connector_state;
8758 struct intel_encoder *encoder;
de13a2e3 8759 uint32_t dpll;
55bb9992 8760 int factor, num_connectors = 0, i;
09ede541 8761 bool is_lvds = false, is_sdvo = false;
79e53945 8762
da3ced29 8763 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8764 if (connector_state->crtc != crtc_state->base.crtc)
8765 continue;
8766
8767 encoder = to_intel_encoder(connector_state->best_encoder);
8768
8769 switch (encoder->type) {
79e53945
JB		 8770 case INTEL_OUTPUT_LVDS:
8771 is_lvds = true;
8772 break;
8773 case INTEL_OUTPUT_SDVO:
7d57382e 8774 case INTEL_OUTPUT_HDMI:
79e53945 8775 is_sdvo = true;
79e53945 8776 break;
6847d71b
PZ		 8777 default:
8778 break;
79e53945 8779 }
43565a06 8780
c751ce4f 8781 num_connectors++;
79e53945 8782 }
79e53945 8783
c1858123 8784 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8785 factor = 21;
8786 if (is_lvds) {
8787 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8788 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8789 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8790 factor = 25;
190f68c5 8791 } else if (crtc_state->sdvo_tv_clock)
8febb297 8792 factor = 20;
c1858123 8793
190f68c5 8794 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8795 *fp |= FP_CB_TUNE;
2c07245f 8796
9a7c7890
DV		 8797 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8798 *fp2 |= FP_CB_TUNE;
8799
5eddb70b 8800 dpll = 0;
2c07245f 8801
a07d6787
EA		 8802 if (is_lvds)
8803 dpll |= DPLLB_MODE_LVDS;
8804 else
8805 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8806
190f68c5 8807 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8808 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8809
8810 if (is_sdvo)
4a33e48d 8811 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8812 if (crtc_state->has_dp_encoder)
4a33e48d 8813 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8814
a07d6787 8815 /* compute bitmask from p1 value */
190f68c5 8816 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8817 /* also FPA1 */
190f68c5 8818 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8819
190f68c5 8820 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8821 case 5:
8822 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8823 break;
8824 case 7:
8825 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8826 break;
8827 case 10:
8828 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8829 break;
8830 case 14:
8831 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8832 break;
79e53945
JB		 8833 }
8834
b4c09f3b 8835 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8836 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8837 else
8838 dpll |= PLL_REF_INPUT_DREFCLK;
8839
959e16d6 8840 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8841}
8842
190f68c5
ACO		 8843static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8844 struct intel_crtc_state *crtc_state)
de13a2e3 8845{
c7653199 8846 struct drm_device *dev = crtc->base.dev;
de13a2e3 8847 intel_clock_t clock, reduced_clock;
cbbab5bd 8848 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8849 bool ok, has_reduced_clock = false;
8b47047b 8850 bool is_lvds = false;
e2b78267 8851 struct intel_shared_dpll *pll;
de13a2e3 8852
dd3cd74a
ACO		 8853 memset(&crtc_state->dpll_hw_state, 0,
8854 sizeof(crtc_state->dpll_hw_state));
8855
409ee761 8856 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8857
5dc5298b
PZ		 8858 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8859 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8860
190f68c5 8861 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8862 &has_reduced_clock, &reduced_clock);
190f68c5 8863 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8864 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8865 return -EINVAL;
79e53945 8866 }
f47709a9 8867 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8868 if (!crtc_state->clock_set) {
8869 crtc_state->dpll.n = clock.n;
8870 crtc_state->dpll.m1 = clock.m1;
8871 crtc_state->dpll.m2 = clock.m2;
8872 crtc_state->dpll.p1 = clock.p1;
8873 crtc_state->dpll.p2 = clock.p2;
f47709a9 8874 }
79e53945 8875
5dc5298b 8876 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8877 if (crtc_state->has_pch_encoder) {
8878 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8879 if (has_reduced_clock)
7429e9d4 8880 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8881
190f68c5 8882 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8883 &fp, &reduced_clock,
8884 has_reduced_clock ? &fp2 : NULL);
8885
190f68c5
ACO		 8886 crtc_state->dpll_hw_state.dpll = dpll;
8887 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8888 if (has_reduced_clock)
190f68c5 8889 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8890 else
190f68c5 8891 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8892
190f68c5 8893 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8894 if (pll == NULL) {
84f44ce7 8895 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8896 pipe_name(crtc->pipe));
4b645f14
JB		 8897 return -EINVAL;
8898 }
3fb37703 8899 }
79e53945 8900
ab585dea 8901 if (is_lvds && has_reduced_clock)
c7653199 8902 crtc->lowfreq_avail = true;
bcd644e0 8903 else
c7653199 8904 crtc->lowfreq_avail = false;
e2b78267 8905
c8f7a0db 8906 return 0;
79e53945
JB		 8907}
8908
eb14cb74
VS		 8909static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8910 struct intel_link_m_n *m_n)
8911{
8912 struct drm_device *dev = crtc->base.dev;
8913 struct drm_i915_private *dev_priv = dev->dev_private;
8914 enum pipe pipe = crtc->pipe;
8915
8916 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8917 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8918 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8919 & ~TU_SIZE_MASK;
8920 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8921 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8922 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8923}
8924
8925static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8926 enum transcoder transcoder,
b95af8be
VK		 8927 struct intel_link_m_n *m_n,
8928 struct intel_link_m_n *m2_n2)
72419203
DV		 8929{
8930 struct drm_device *dev = crtc->base.dev;
8931 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8932 enum pipe pipe = crtc->pipe;
72419203 8933
eb14cb74
VS		 8934 if (INTEL_INFO(dev)->gen >= 5) {
8935 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8936 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8937 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8938 & ~TU_SIZE_MASK;
8939 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8940 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8941 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8942 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8943 * gen < 8) and if DRRS is supported (to make sure the
8944 * registers are not unnecessarily read).
8945 */
8946 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8947 crtc->config->has_drrs) {
b95af8be
VK		 8948 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8949 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8950 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8951 & ~TU_SIZE_MASK;
8952 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8953 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8954 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8955 }
eb14cb74
VS		 8956 } else {
8957 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8958 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8959 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8960 & ~TU_SIZE_MASK;
8961 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8962 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8963 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8964 }
8965}
8966
8967void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8968 struct intel_crtc_state *pipe_config)
eb14cb74 8969{
681a8504 8970 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8971 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8972 else
8973 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8974 &pipe_config->dp_m_n,
8975 &pipe_config->dp_m2_n2);
eb14cb74 8976}
72419203 8977
eb14cb74 8978static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8979 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8980{
8981 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8982 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8983}
8984
bd2e244f 8985static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8986 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8987{
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8990 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8991 uint32_t ps_ctrl = 0;
8992 int id = -1;
8993 int i;
bd2e244f 8994
a1b2278e
CK		 8995 /* find scaler attached to this pipe */
8996 for (i = 0; i < crtc->num_scalers; i++) {
8997 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8998 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8999 id = i;
9000 pipe_config->pch_pfit.enabled = true;
9001 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9002 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9003 break;
9004 }
9005 }
bd2e244f 9006
a1b2278e
CK		 9007 scaler_state->scaler_id = id;
9008 if (id >= 0) {
9009 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9010 } else {
9011 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9012 }
9013}
9014
5724dbd1
DL		 9015static void
9016skylake_get_initial_plane_config(struct intel_crtc *crtc,
9017 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9018{
9019 struct drm_device *dev = crtc->base.dev;
9020 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9021 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9022 int pipe = crtc->pipe;
9023 int fourcc, pixel_format;
6761dd31 9024 unsigned int aligned_height;
bc8d7dff 9025 struct drm_framebuffer *fb;
1b842c89 9026 struct intel_framebuffer *intel_fb;
bc8d7dff 9027
d9806c9f 9028 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9029 if (!intel_fb) {
bc8d7dff
DL		 9030 DRM_DEBUG_KMS("failed to alloc fb\n");
9031 return;
9032 }
9033
1b842c89
DL		 9034 fb = &intel_fb->base;
9035
bc8d7dff 9036 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9037 if (!(val & PLANE_CTL_ENABLE))
9038 goto error;
9039
bc8d7dff
DL		 9040 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9041 fourcc = skl_format_to_fourcc(pixel_format,
9042 val & PLANE_CTL_ORDER_RGBX,
9043 val & PLANE_CTL_ALPHA_MASK);
9044 fb->pixel_format = fourcc;
9045 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9046
40f46283
DL		 9047 tiling = val & PLANE_CTL_TILED_MASK;
9048 switch (tiling) {
9049 case PLANE_CTL_TILED_LINEAR:
9050 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9051 break;
9052 case PLANE_CTL_TILED_X:
9053 plane_config->tiling = I915_TILING_X;
9054 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9055 break;
9056 case PLANE_CTL_TILED_Y:
9057 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9058 break;
9059 case PLANE_CTL_TILED_YF:
9060 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9061 break;
9062 default:
9063 MISSING_CASE(tiling);
9064 goto error;
9065 }
9066
bc8d7dff
DL		 9067 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9068 plane_config->base = base;
9069
9070 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9071
9072 val = I915_READ(PLANE_SIZE(pipe, 0));
9073 fb->height = ((val >> 16) & 0xfff) + 1;
9074 fb->width = ((val >> 0) & 0x1fff) + 1;
9075
9076 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9077 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9078 fb->pixel_format);
bc8d7dff
DL		 9079 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9080
9081 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9082 fb->pixel_format,
9083 fb->modifier[0]);
bc8d7dff 9084
f37b5c2b 9085 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9086
9087 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9088 pipe_name(pipe), fb->width, fb->height,
9089 fb->bits_per_pixel, base, fb->pitches[0],
9090 plane_config->size);
9091
2d14030b 9092 plane_config->fb = intel_fb;
bc8d7dff
DL		 9093 return;
9094
9095error:
9096 kfree(fb);
9097}
9098
2fa2fe9a 9099static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9100 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9101{
9102 struct drm_device *dev = crtc->base.dev;
9103 struct drm_i915_private *dev_priv = dev->dev_private;
9104 uint32_t tmp;
9105
9106 tmp = I915_READ(PF_CTL(crtc->pipe));
9107
9108 if (tmp & PF_ENABLE) {
fd4daa9c 9109 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9110 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9111 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9112
9113 /* We currently do not free assignements of panel fitters on
9114 * ivb/hsw (since we don't use the higher upscaling modes which
9115 * differentiates them) so just WARN about this case for now. */
9116 if (IS_GEN7(dev)) {
9117 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9118 PF_PIPE_SEL_IVB(crtc->pipe));
9119 }
2fa2fe9a 9120 }
79e53945
JB		 9121}
9122
5724dbd1
DL		 9123static void
9124ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9125 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9126{
9127 struct drm_device *dev = crtc->base.dev;
9128 struct drm_i915_private *dev_priv = dev->dev_private;
9129 u32 val, base, offset;
aeee5a49 9130 int pipe = crtc->pipe;
4c6baa59 9131 int fourcc, pixel_format;
6761dd31 9132 unsigned int aligned_height;
b113d5ee 9133 struct drm_framebuffer *fb;
1b842c89 9134 struct intel_framebuffer *intel_fb;
4c6baa59 9135
42a7b088
DL		 9136 val = I915_READ(DSPCNTR(pipe));
9137 if (!(val & DISPLAY_PLANE_ENABLE))
9138 return;
9139
d9806c9f 9140 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9141 if (!intel_fb) {
4c6baa59
JB		 9142 DRM_DEBUG_KMS("failed to alloc fb\n");
9143 return;
9144 }
9145
1b842c89
DL		 9146 fb = &intel_fb->base;
9147
18c5247e
DV		 9148 if (INTEL_INFO(dev)->gen >= 4) {
9149 if (val & DISPPLANE_TILED) {
49af449b 9150 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9151 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9152 }
9153 }
4c6baa59
JB		 9154
9155 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9156 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9157 fb->pixel_format = fourcc;
9158 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9159
aeee5a49 9160 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9161 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9162 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9163 } else {
49af449b 9164 if (plane_config->tiling)
aeee5a49 9165 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9166 else
aeee5a49 9167 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9168 }
9169 plane_config->base = base;
9170
9171 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9172 fb->width = ((val >> 16) & 0xfff) + 1;
9173 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9174
9175 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9176 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9177
b113d5ee 9178 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9179 fb->pixel_format,
9180 fb->modifier[0]);
4c6baa59 9181
f37b5c2b 9182 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9183
2844a921
DL		 9184 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9185 pipe_name(pipe), fb->width, fb->height,
9186 fb->bits_per_pixel, base, fb->pitches[0],
9187 plane_config->size);
b113d5ee 9188
2d14030b 9189 plane_config->fb = intel_fb;
4c6baa59
JB		 9190}
9191
0e8ffe1b 9192static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9193 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9194{
9195 struct drm_device *dev = crtc->base.dev;
9196 struct drm_i915_private *dev_priv = dev->dev_private;
9197 uint32_t tmp;
9198
f458ebbc
DV		 9199 if (!intel_display_power_is_enabled(dev_priv,
9200 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9201 return false;
9202
e143a21c 9203 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9204 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9205
0e8ffe1b
DV		 9206 tmp = I915_READ(PIPECONF(crtc->pipe));
9207 if (!(tmp & PIPECONF_ENABLE))
9208 return false;
9209
42571aef
VS		 9210 switch (tmp & PIPECONF_BPC_MASK) {
9211 case PIPECONF_6BPC:
9212 pipe_config->pipe_bpp = 18;
9213 break;
9214 case PIPECONF_8BPC:
9215 pipe_config->pipe_bpp = 24;
9216 break;
9217 case PIPECONF_10BPC:
9218 pipe_config->pipe_bpp = 30;
9219 break;
9220 case PIPECONF_12BPC:
9221 pipe_config->pipe_bpp = 36;
9222 break;
9223 default:
9224 break;
9225 }
9226
b5a9fa09
DV		 9227 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9228 pipe_config->limited_color_range = true;
9229
ab9412ba 9230 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9231 struct intel_shared_dpll *pll;
9232
88adfff1
DV		 9233 pipe_config->has_pch_encoder = true;
9234
627eb5a3
DV		 9235 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9236 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9237 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9238
9239 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9240
c0d43d62 9241 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9242 pipe_config->shared_dpll =
9243 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9244 } else {
9245 tmp = I915_READ(PCH_DPLL_SEL);
9246 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9247 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9248 else
9249 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9250 }
66e985c0
DV		 9251
9252 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9253
9254 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9255 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9256
9257 tmp = pipe_config->dpll_hw_state.dpll;
9258 pipe_config->pixel_multiplier =
9259 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9260 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9261
9262 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9263 } else {
9264 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9265 }
9266
1bd1bd80
DV		 9267 intel_get_pipe_timings(crtc, pipe_config);
9268
2fa2fe9a
DV		 9269 ironlake_get_pfit_config(crtc, pipe_config);
9270
0e8ffe1b
DV		 9271 return true;
9272}
9273
be256dc7
PZ		 9274static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9275{
9276 struct drm_device *dev = dev_priv->dev;
be256dc7 9277 struct intel_crtc *crtc;
be256dc7 9278
d3fcc808 9279 for_each_intel_crtc(dev, crtc)
e2c719b7 9280 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9281 pipe_name(crtc->pipe));
9282
e2c719b7
RC		 9283 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9284 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9285 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9286 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9287 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9288 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9289 "CPU PWM1 enabled\n");
c5107b87 9290 if (IS_HASWELL(dev))
e2c719b7 9291 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9292 "CPU PWM2 enabled\n");
e2c719b7 9293 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9294 "PCH PWM1 enabled\n");
e2c719b7 9295 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9296 "Utility pin enabled\n");
e2c719b7 9297 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9298
9926ada1
PZ		 9299 /*
9300 * In theory we can still leave IRQs enabled, as long as only the HPD
9301 * interrupts remain enabled. We used to check for that, but since it's
9302 * gen-specific and since we only disable LCPLL after we fully disable
9303 * the interrupts, the check below should be enough.
9304 */
e2c719b7 9305 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9306}
9307
9ccd5aeb
PZ		 9308static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9309{
9310 struct drm_device *dev = dev_priv->dev;
9311
9312 if (IS_HASWELL(dev))
9313 return I915_READ(D_COMP_HSW);
9314 else
9315 return I915_READ(D_COMP_BDW);
9316}
9317
3c4c9b81
PZ		 9318static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9319{
9320 struct drm_device *dev = dev_priv->dev;
9321
9322 if (IS_HASWELL(dev)) {
9323 mutex_lock(&dev_priv->rps.hw_lock);
9324 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9325 val))
f475dadf 9326 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9327 mutex_unlock(&dev_priv->rps.hw_lock);
9328 } else {
9ccd5aeb
PZ		 9329 I915_WRITE(D_COMP_BDW, val);
9330 POSTING_READ(D_COMP_BDW);
3c4c9b81 9331 }
be256dc7
PZ		 9332}
9333
9334/*
9335 * This function implements pieces of two sequences from BSpec:
9336 * - Sequence for display software to disable LCPLL
9337 * - Sequence for display software to allow package C8+
9338 * The steps implemented here are just the steps that actually touch the LCPLL
9339 * register. Callers should take care of disabling all the display engine
9340 * functions, doing the mode unset, fixing interrupts, etc.
9341 */
6ff58d53
PZ		 9342static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9343 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9344{
9345 uint32_t val;
9346
9347 assert_can_disable_lcpll(dev_priv);
9348
9349 val = I915_READ(LCPLL_CTL);
9350
9351 if (switch_to_fclk) {
9352 val |= LCPLL_CD_SOURCE_FCLK;
9353 I915_WRITE(LCPLL_CTL, val);
9354
9355 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9356 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9357 DRM_ERROR("Switching to FCLK failed\n");
9358
9359 val = I915_READ(LCPLL_CTL);
9360 }
9361
9362 val |= LCPLL_PLL_DISABLE;
9363 I915_WRITE(LCPLL_CTL, val);
9364 POSTING_READ(LCPLL_CTL);
9365
9366 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9367 DRM_ERROR("LCPLL still locked\n");
9368
9ccd5aeb 9369 val = hsw_read_dcomp(dev_priv);
be256dc7 9370 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9371 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9372 ndelay(100);
9373
9ccd5aeb
PZ		 9374 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9375 1))
be256dc7
PZ		 9376 DRM_ERROR("D_COMP RCOMP still in progress\n");
9377
9378 if (allow_power_down) {
9379 val = I915_READ(LCPLL_CTL);
9380 val |= LCPLL_POWER_DOWN_ALLOW;
9381 I915_WRITE(LCPLL_CTL, val);
9382 POSTING_READ(LCPLL_CTL);
9383 }
9384}
9385
9386/*
9387 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9388 * source.
9389 */
6ff58d53 9390static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9391{
9392 uint32_t val;
9393
9394 val = I915_READ(LCPLL_CTL);
9395
9396 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9397 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9398 return;
9399
a8a8bd54
PZ		 9400 /*
9401 * Make sure we're not on PC8 state before disabling PC8, otherwise
9402 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9403 */
59bad947 9404 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9405
be256dc7
PZ		 9406 if (val & LCPLL_POWER_DOWN_ALLOW) {
9407 val &= ~LCPLL_POWER_DOWN_ALLOW;
9408 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9409 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9410 }
9411
9ccd5aeb 9412 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9413 val |= D_COMP_COMP_FORCE;
9414 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9415 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9416
9417 val = I915_READ(LCPLL_CTL);
9418 val &= ~LCPLL_PLL_DISABLE;
9419 I915_WRITE(LCPLL_CTL, val);
9420
9421 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9422 DRM_ERROR("LCPLL not locked yet\n");
9423
9424 if (val & LCPLL_CD_SOURCE_FCLK) {
9425 val = I915_READ(LCPLL_CTL);
9426 val &= ~LCPLL_CD_SOURCE_FCLK;
9427 I915_WRITE(LCPLL_CTL, val);
9428
9429 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9430 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9431 DRM_ERROR("Switching back to LCPLL failed\n");
9432 }
215733fa 9433
59bad947 9434 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9435 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9436}
9437
765dab67
PZ		 9438/*
9439 * Package states C8 and deeper are really deep PC states that can only be
9440 * reached when all the devices on the system allow it, so even if the graphics
9441 * device allows PC8+, it doesn't mean the system will actually get to these
9442 * states. Our driver only allows PC8+ when going into runtime PM.
9443 *
9444 * The requirements for PC8+ are that all the outputs are disabled, the power
9445 * well is disabled and most interrupts are disabled, and these are also
9446 * requirements for runtime PM. When these conditions are met, we manually do
9447 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9448 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9449 * hang the machine.
9450 *
9451 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9452 * the state of some registers, so when we come back from PC8+ we need to
9453 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9454 * need to take care of the registers kept by RC6. Notice that this happens even
9455 * if we don't put the device in PCI D3 state (which is what currently happens
9456 * because of the runtime PM support).
9457 *
9458 * For more, read "Display Sequences for Package C8" on the hardware
9459 * documentation.
9460 */
a14cb6fc 9461void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9462{
c67a470b
PZ		 9463 struct drm_device *dev = dev_priv->dev;
9464 uint32_t val;
9465
c67a470b
PZ		 9466 DRM_DEBUG_KMS("Enabling package C8+\n");
9467
c2699524 9468 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9469 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9470 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9471 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9472 }
9473
9474 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9475 hsw_disable_lcpll(dev_priv, true, true);
9476}
9477
a14cb6fc 9478void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9479{
9480 struct drm_device *dev = dev_priv->dev;
9481 uint32_t val;
9482
c67a470b
PZ		 9483 DRM_DEBUG_KMS("Disabling package C8+\n");
9484
9485 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9486 lpt_init_pch_refclk(dev);
9487
c2699524 9488 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9489 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9490 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9491 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9492 }
9493
9494 intel_prepare_ddi(dev);
c67a470b
PZ		 9495}
9496
27c329ed 9497static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9498{
a821fc46 9499 struct drm_device *dev = old_state->dev;
27c329ed 9500 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9501
27c329ed 9502 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9503}
9504
b432e5cf 9505/* compute the max rate for new configuration */
27c329ed 9506static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9507{
b432e5cf 9508 struct intel_crtc *intel_crtc;
27c329ed 9509 struct intel_crtc_state *crtc_state;
b432e5cf 9510 int max_pixel_rate = 0;
b432e5cf 9511
27c329ed
ML		 9512 for_each_intel_crtc(state->dev, intel_crtc) {
9513 int pixel_rate;
9514
9515 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9516 if (IS_ERR(crtc_state))
9517 return PTR_ERR(crtc_state);
9518
9519 if (!crtc_state->base.enable)
b432e5cf
VS		 9520 continue;
9521
27c329ed 9522 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9523
9524 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9525 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9526 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9527
9528 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9529 }
9530
9531 return max_pixel_rate;
9532}
9533
9534static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9535{
9536 struct drm_i915_private *dev_priv = dev->dev_private;
9537 uint32_t val, data;
9538 int ret;
9539
9540 if (WARN((I915_READ(LCPLL_CTL) &
9541 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9542 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9543 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9544 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9545 "trying to change cdclk frequency with cdclk not enabled\n"))
9546 return;
9547
9548 mutex_lock(&dev_priv->rps.hw_lock);
9549 ret = sandybridge_pcode_write(dev_priv,
9550 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9551 mutex_unlock(&dev_priv->rps.hw_lock);
9552 if (ret) {
9553 DRM_ERROR("failed to inform pcode about cdclk change\n");
9554 return;
9555 }
9556
9557 val = I915_READ(LCPLL_CTL);
9558 val |= LCPLL_CD_SOURCE_FCLK;
9559 I915_WRITE(LCPLL_CTL, val);
9560
9561 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9562 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9563 DRM_ERROR("Switching to FCLK failed\n");
9564
9565 val = I915_READ(LCPLL_CTL);
9566 val &= ~LCPLL_CLK_FREQ_MASK;
9567
9568 switch (cdclk) {
9569 case 450000:
9570 val |= LCPLL_CLK_FREQ_450;
9571 data = 0;
9572 break;
9573 case 540000:
9574 val |= LCPLL_CLK_FREQ_54O_BDW;
9575 data = 1;
9576 break;
9577 case 337500:
9578 val |= LCPLL_CLK_FREQ_337_5_BDW;
9579 data = 2;
9580 break;
9581 case 675000:
9582 val |= LCPLL_CLK_FREQ_675_BDW;
9583 data = 3;
9584 break;
9585 default:
9586 WARN(1, "invalid cdclk frequency\n");
9587 return;
9588 }
9589
9590 I915_WRITE(LCPLL_CTL, val);
9591
9592 val = I915_READ(LCPLL_CTL);
9593 val &= ~LCPLL_CD_SOURCE_FCLK;
9594 I915_WRITE(LCPLL_CTL, val);
9595
9596 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9597 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9598 DRM_ERROR("Switching back to LCPLL failed\n");
9599
9600 mutex_lock(&dev_priv->rps.hw_lock);
9601 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9602 mutex_unlock(&dev_priv->rps.hw_lock);
9603
9604 intel_update_cdclk(dev);
9605
9606 WARN(cdclk != dev_priv->cdclk_freq,
9607 "cdclk requested %d kHz but got %d kHz\n",
9608 cdclk, dev_priv->cdclk_freq);
9609}
9610
27c329ed 9611static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9612{
27c329ed
ML		 9613 struct drm_i915_private *dev_priv = to_i915(state->dev);
9614 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9615 int cdclk;
9616
9617 /*
9618 * FIXME should also account for plane ratio
9619 * once 64bpp pixel formats are supported.
9620 */
27c329ed 9621 if (max_pixclk > 540000)
b432e5cf 9622 cdclk = 675000;
27c329ed 9623 else if (max_pixclk > 450000)
b432e5cf 9624 cdclk = 540000;
27c329ed 9625 else if (max_pixclk > 337500)
b432e5cf
VS		 9626 cdclk = 450000;
9627 else
9628 cdclk = 337500;
9629
9630 /*
9631 * FIXME move the cdclk caclulation to
9632 * compute_config() so we can fail gracegully.
9633 */
9634 if (cdclk > dev_priv->max_cdclk_freq) {
9635 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9636 cdclk, dev_priv->max_cdclk_freq);
9637 cdclk = dev_priv->max_cdclk_freq;
9638 }
9639
27c329ed 9640 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9641
9642 return 0;
9643}
9644
27c329ed 9645static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9646{
27c329ed
ML		 9647 struct drm_device *dev = old_state->dev;
9648 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9649
27c329ed 9650 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9651}
9652
190f68c5
ACO		 9653static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9654 struct intel_crtc_state *crtc_state)
09b4ddf9 9655{
190f68c5 9656 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9657 return -EINVAL;
716c2e55 9658
c7653199 9659 crtc->lowfreq_avail = false;
644cef34 9660
c8f7a0db 9661 return 0;
79e53945
JB		 9662}
9663
3760b59c
S		 9664static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9665 enum port port,
9666 struct intel_crtc_state *pipe_config)
9667{
9668 switch (port) {
9669 case PORT_A:
9670 pipe_config->ddi_pll_sel = SKL_DPLL0;
9671 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9672 break;
9673 case PORT_B:
9674 pipe_config->ddi_pll_sel = SKL_DPLL1;
9675 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9676 break;
9677 case PORT_C:
9678 pipe_config->ddi_pll_sel = SKL_DPLL2;
9679 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9680 break;
9681 default:
9682 DRM_ERROR("Incorrect port type\n");
9683 }
9684}
9685
96b7dfb7
S		 9686static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9687 enum port port,
5cec258b 9688 struct intel_crtc_state *pipe_config)
96b7dfb7 9689{
3148ade7 9690 u32 temp, dpll_ctl1;
96b7dfb7
S		 9691
9692 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9693 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9694
9695 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9696 case SKL_DPLL0:
9697 /*
9698 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9699 * of the shared DPLL framework and thus needs to be read out
9700 * separately
9701 */
9702 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9703 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9704 break;
96b7dfb7
S		 9705 case SKL_DPLL1:
9706 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9707 break;
9708 case SKL_DPLL2:
9709 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9710 break;
9711 case SKL_DPLL3:
9712 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9713 break;
96b7dfb7
S		 9714 }
9715}
9716
7d2c8175
DL		 9717static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9718 enum port port,
5cec258b 9719 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9720{
9721 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9722
9723 switch (pipe_config->ddi_pll_sel) {
9724 case PORT_CLK_SEL_WRPLL1:
9725 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9726 break;
9727 case PORT_CLK_SEL_WRPLL2:
9728 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9729 break;
9730 }
9731}
9732
26804afd 9733static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9734 struct intel_crtc_state *pipe_config)
26804afd
DV		 9735{
9736 struct drm_device *dev = crtc->base.dev;
9737 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9738 struct intel_shared_dpll *pll;
26804afd
DV		 9739 enum port port;
9740 uint32_t tmp;
9741
9742 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9743
9744 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9745
96b7dfb7
S		 9746 if (IS_SKYLAKE(dev))
9747 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9748 else if (IS_BROXTON(dev))
9749 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9750 else
9751 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9752
d452c5b6
DV		 9753 if (pipe_config->shared_dpll >= 0) {
9754 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9755
9756 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9757 &pipe_config->dpll_hw_state));
9758 }
9759
26804afd
DV		 9760 /*
9761 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9762 * DDI E. So just check whether this pipe is wired to DDI E and whether
9763 * the PCH transcoder is on.
9764 */
ca370455
DL		 9765 if (INTEL_INFO(dev)->gen < 9 &&
9766 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9767 pipe_config->has_pch_encoder = true;
9768
9769 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9770 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9771 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9772
9773 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9774 }
9775}
9776
0e8ffe1b 9777static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9778 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9779{
9780 struct drm_device *dev = crtc->base.dev;
9781 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9782 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9783 uint32_t tmp;
9784
f458ebbc 9785 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9786 POWER_DOMAIN_PIPE(crtc->pipe)))
9787 return false;
9788
e143a21c 9789 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9790 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9791
eccb140b
DV		 9792 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9793 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9794 enum pipe trans_edp_pipe;
9795 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9796 default:
9797 WARN(1, "unknown pipe linked to edp transcoder\n");
9798 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9799 case TRANS_DDI_EDP_INPUT_A_ON:
9800 trans_edp_pipe = PIPE_A;
9801 break;
9802 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9803 trans_edp_pipe = PIPE_B;
9804 break;
9805 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9806 trans_edp_pipe = PIPE_C;
9807 break;
9808 }
9809
9810 if (trans_edp_pipe == crtc->pipe)
9811 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9812 }
9813
f458ebbc 9814 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9815 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9816 return false;
9817
eccb140b 9818 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9819 if (!(tmp & PIPECONF_ENABLE))
9820 return false;
9821
26804afd 9822 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9823
1bd1bd80
DV		 9824 intel_get_pipe_timings(crtc, pipe_config);
9825
a1b2278e
CK		 9826 if (INTEL_INFO(dev)->gen >= 9) {
9827 skl_init_scalers(dev, crtc, pipe_config);
9828 }
9829
2fa2fe9a 9830 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9831
9832 if (INTEL_INFO(dev)->gen >= 9) {
9833 pipe_config->scaler_state.scaler_id = -1;
9834 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9835 }
9836
bd2e244f 9837 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9838 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9839 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9840 else
1c132b44 9841 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9842 }
88adfff1 9843
e59150dc
JB		 9844 if (IS_HASWELL(dev))
9845 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9846 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9847
ebb69c95
CT		 9848 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9849 pipe_config->pixel_multiplier =
9850 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9851 } else {
9852 pipe_config->pixel_multiplier = 1;
9853 }
6c49f241 9854
0e8ffe1b
DV		 9855 return true;
9856}
9857
560b85bb
CW		 9858static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9859{
9860 struct drm_device *dev = crtc->dev;
9861 struct drm_i915_private *dev_priv = dev->dev_private;
9862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9863 uint32_t cntl = 0, size = 0;
560b85bb 9864
dc41c154 9865 if (base) {
3dd512fb
MR		 9866 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9867 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9868 unsigned int stride = roundup_pow_of_two(width) * 4;
9869
9870 switch (stride) {
9871 default:
9872 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9873 width, stride);
9874 stride = 256;
9875 /* fallthrough */
9876 case 256:
9877 case 512:
9878 case 1024:
9879 case 2048:
9880 break;
4b0e333e
CW		 9881 }
9882
dc41c154
VS		 9883 cntl |= CURSOR_ENABLE |
9884 CURSOR_GAMMA_ENABLE |
9885 CURSOR_FORMAT_ARGB |
9886 CURSOR_STRIDE(stride);
9887
9888 size = (height << 12) | width;
4b0e333e 9889 }
560b85bb 9890
dc41c154
VS		 9891 if (intel_crtc->cursor_cntl != 0 &&
9892 (intel_crtc->cursor_base != base ||
9893 intel_crtc->cursor_size != size ||
9894 intel_crtc->cursor_cntl != cntl)) {
9895 /* On these chipsets we can only modify the base/size/stride
9896 * whilst the cursor is disabled.
9897 */
0b87c24e
VS		 9898 I915_WRITE(CURCNTR(PIPE_A), 0);
9899 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9900 intel_crtc->cursor_cntl = 0;
4b0e333e 9901 }
560b85bb 9902
99d1f387 9903 if (intel_crtc->cursor_base != base) {
0b87c24e 9904 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9905 intel_crtc->cursor_base = base;
9906 }
4726e0b0 9907
dc41c154
VS		 9908 if (intel_crtc->cursor_size != size) {
9909 I915_WRITE(CURSIZE, size);
9910 intel_crtc->cursor_size = size;
4b0e333e 9911 }
560b85bb 9912
4b0e333e 9913 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9914 I915_WRITE(CURCNTR(PIPE_A), cntl);
9915 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9916 intel_crtc->cursor_cntl = cntl;
560b85bb 9917 }
560b85bb
CW		 9918}
9919
560b85bb 9920static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9921{
9922 struct drm_device *dev = crtc->dev;
9923 struct drm_i915_private *dev_priv = dev->dev_private;
9924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9925 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9926 uint32_t cntl;
9927
9928 cntl = 0;
9929 if (base) {
9930 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9931 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9932 case 64:
9933 cntl |= CURSOR_MODE_64_ARGB_AX;
9934 break;
9935 case 128:
9936 cntl |= CURSOR_MODE_128_ARGB_AX;
9937 break;
9938 case 256:
9939 cntl |= CURSOR_MODE_256_ARGB_AX;
9940 break;
9941 default:
3dd512fb 9942 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9943 return;
65a21cd6 9944 }
4b0e333e 9945 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9946
9947 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9948 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9949 }
65a21cd6 9950
8e7d688b 9951 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9952 cntl |= CURSOR_ROTATE_180;
9953
4b0e333e
CW		 9954 if (intel_crtc->cursor_cntl != cntl) {
9955 I915_WRITE(CURCNTR(pipe), cntl);
9956 POSTING_READ(CURCNTR(pipe));
9957 intel_crtc->cursor_cntl = cntl;
65a21cd6 9958 }
4b0e333e 9959
65a21cd6 9960 /* and commit changes on next vblank */
5efb3e28
VS		 9961 I915_WRITE(CURBASE(pipe), base);
9962 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9963
9964 intel_crtc->cursor_base = base;
65a21cd6
JB		 9965}
9966
cda4b7d3 9967/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9968static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9969 bool on)
cda4b7d3
CW		 9970{
9971 struct drm_device *dev = crtc->dev;
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9974 int pipe = intel_crtc->pipe;
9b4101be
ML		 9975 struct drm_plane_state *cursor_state = crtc->cursor->state;
9976 int x = cursor_state->crtc_x;
9977 int y = cursor_state->crtc_y;
d6e4db15 9978 u32 base = 0, pos = 0;
cda4b7d3 9979
d6e4db15 9980 if (on)
cda4b7d3 9981 base = intel_crtc->cursor_addr;
cda4b7d3 9982
6e3c9717 9983 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9984 base = 0;
9985
6e3c9717 9986 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9987 base = 0;
9988
9989 if (x < 0) {
9b4101be 9990 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9991 base = 0;
9992
9993 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9994 x = -x;
9995 }
9996 pos |= x << CURSOR_X_SHIFT;
9997
9998 if (y < 0) {
9b4101be 9999 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 10000 base = 0;
10001
10002 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10003 y = -y;
10004 }
10005 pos |= y << CURSOR_Y_SHIFT;
10006
4b0e333e 10007 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10008 return;
10009
5efb3e28
VS		 10010 I915_WRITE(CURPOS(pipe), pos);
10011
4398ad45
VS		 10012 /* ILK+ do this automagically */
10013 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10014 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 10015 base += (cursor_state->crtc_h *
10016 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 10017 }
10018
8ac54669 10019 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10020 i845_update_cursor(crtc, base);
10021 else
10022 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10023}
10024
dc41c154
VS		 10025static bool cursor_size_ok(struct drm_device *dev,
10026 uint32_t width, uint32_t height)
10027{
10028 if (width == 0 || height == 0)
10029 return false;
10030
10031 /*
10032 * 845g/865g are special in that they are only limited by
10033 * the width of their cursors, the height is arbitrary up to
10034 * the precision of the register. Everything else requires
10035 * square cursors, limited to a few power-of-two sizes.
10036 */
10037 if (IS_845G(dev) || IS_I865G(dev)) {
10038 if ((width & 63) != 0)
10039 return false;
10040
10041 if (width > (IS_845G(dev) ? 64 : 512))
10042 return false;
10043
10044 if (height > 1023)
10045 return false;
10046 } else {
10047 switch (width | height) {
10048 case 256:
10049 case 128:
10050 if (IS_GEN2(dev))
10051 return false;
10052 case 64:
10053 break;
10054 default:
10055 return false;
10056 }
10057 }
10058
10059 return true;
10060}
10061
79e53945 10062static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10063 u16 *blue, uint32_t start, uint32_t size)
79e53945 10064{
7203425a 10065 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10067
7203425a 10068 for (i = start; i < end; i++) {
79e53945
JB		 10069 intel_crtc->lut_r[i] = red[i] >> 8;
10070 intel_crtc->lut_g[i] = green[i] >> 8;
10071 intel_crtc->lut_b[i] = blue[i] >> 8;
10072 }
10073
10074 intel_crtc_load_lut(crtc);
10075}
10076
79e53945
JB		 10077/* VESA 640x480x72Hz mode to set on the pipe */
10078static struct drm_display_mode load_detect_mode = {
10079 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10080 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10081};
10082
a8bb6818
DV		 10083struct drm_framebuffer *
10084__intel_framebuffer_create(struct drm_device *dev,
10085 struct drm_mode_fb_cmd2 *mode_cmd,
10086 struct drm_i915_gem_object *obj)
d2dff872
CW		 10087{
10088 struct intel_framebuffer *intel_fb;
10089 int ret;
10090
10091 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10092 if (!intel_fb) {
6ccb81f2 10093 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10094 return ERR_PTR(-ENOMEM);
10095 }
10096
10097 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10098 if (ret)
10099 goto err;
d2dff872
CW		 10100
10101 return &intel_fb->base;
dd4916c5 10102err:
6ccb81f2 10103 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10104 kfree(intel_fb);
10105
10106 return ERR_PTR(ret);
d2dff872
CW		 10107}
10108
b5ea642a 10109static struct drm_framebuffer *
a8bb6818
DV		 10110intel_framebuffer_create(struct drm_device *dev,
10111 struct drm_mode_fb_cmd2 *mode_cmd,
10112 struct drm_i915_gem_object *obj)
10113{
10114 struct drm_framebuffer *fb;
10115 int ret;
10116
10117 ret = i915_mutex_lock_interruptible(dev);
10118 if (ret)
10119 return ERR_PTR(ret);
10120 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10121 mutex_unlock(&dev->struct_mutex);
10122
10123 return fb;
10124}
10125
d2dff872
CW		 10126static u32
10127intel_framebuffer_pitch_for_width(int width, int bpp)
10128{
10129 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10130 return ALIGN(pitch, 64);
10131}
10132
10133static u32
10134intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10135{
10136 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10137 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10138}
10139
10140static struct drm_framebuffer *
10141intel_framebuffer_create_for_mode(struct drm_device *dev,
10142 struct drm_display_mode *mode,
10143 int depth, int bpp)
10144{
10145 struct drm_i915_gem_object *obj;
0fed39bd 10146 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10147
10148 obj = i915_gem_alloc_object(dev,
10149 intel_framebuffer_size_for_mode(mode, bpp));
10150 if (obj == NULL)
10151 return ERR_PTR(-ENOMEM);
10152
10153 mode_cmd.width = mode->hdisplay;
10154 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10155 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10156 bpp);
5ca0c34a 10157 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10158
10159 return intel_framebuffer_create(dev, &mode_cmd, obj);
10160}
10161
10162static struct drm_framebuffer *
10163mode_fits_in_fbdev(struct drm_device *dev,
10164 struct drm_display_mode *mode)
10165{
0695726e 10166#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10167 struct drm_i915_private *dev_priv = dev->dev_private;
10168 struct drm_i915_gem_object *obj;
10169 struct drm_framebuffer *fb;
10170
4c0e5528 10171 if (!dev_priv->fbdev)
d2dff872
CW		 10172 return NULL;
10173
4c0e5528 10174 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10175 return NULL;
10176
4c0e5528
DV		 10177 obj = dev_priv->fbdev->fb->obj;
10178 BUG_ON(!obj);
10179
8bcd4553 10180 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10181 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10182 fb->bits_per_pixel))
d2dff872
CW		 10183 return NULL;
10184
01f2c773 10185 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10186 return NULL;
10187
10188 return fb;
4520f53a
DV		 10189#else
10190 return NULL;
10191#endif
d2dff872
CW		 10192}
10193
d3a40d1b
ACO		 10194static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10195 struct drm_crtc *crtc,
10196 struct drm_display_mode *mode,
10197 struct drm_framebuffer *fb,
10198 int x, int y)
10199{
10200 struct drm_plane_state *plane_state;
10201 int hdisplay, vdisplay;
10202 int ret;
10203
10204 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10205 if (IS_ERR(plane_state))
10206 return PTR_ERR(plane_state);
10207
10208 if (mode)
10209 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10210 else
10211 hdisplay = vdisplay = 0;
10212
10213 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10214 if (ret)
10215 return ret;
10216 drm_atomic_set_fb_for_plane(plane_state, fb);
10217 plane_state->crtc_x = 0;
10218 plane_state->crtc_y = 0;
10219 plane_state->crtc_w = hdisplay;
10220 plane_state->crtc_h = vdisplay;
10221 plane_state->src_x = x << 16;
10222 plane_state->src_y = y << 16;
10223 plane_state->src_w = hdisplay << 16;
10224 plane_state->src_h = vdisplay << 16;
10225
10226 return 0;
10227}
10228
d2434ab7 10229bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10230 struct drm_display_mode *mode,
51fd371b
RC		 10231 struct intel_load_detect_pipe *old,
10232 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10233{
10234 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10235 struct intel_encoder *intel_encoder =
10236 intel_attached_encoder(connector);
79e53945 10237 struct drm_crtc *possible_crtc;
4ef69c7a 10238 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10239 struct drm_crtc *crtc = NULL;
10240 struct drm_device *dev = encoder->dev;
94352cf9 10241 struct drm_framebuffer *fb;
51fd371b 10242 struct drm_mode_config *config = &dev->mode_config;
83a57153 10243 struct drm_atomic_state *state = NULL;
944b0c76 10244 struct drm_connector_state *connector_state;
4be07317 10245 struct intel_crtc_state *crtc_state;
51fd371b 10246 int ret, i = -1;
79e53945 10247
d2dff872 10248 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10249 connector->base.id, connector->name,
8e329a03 10250 encoder->base.id, encoder->name);
d2dff872 10251
51fd371b
RC		 10252retry:
10253 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10254 if (ret)
ad3c558f 10255 goto fail;
6e9f798d 10256
79e53945
JB		 10257 /*
10258 * Algorithm gets a little messy:
7a5e4805 10259 *
79e53945
JB		 10260 * - if the connector already has an assigned crtc, use it (but make
10261 * sure it's on first)
7a5e4805 10262 *
79e53945
JB		 10263 * - try to find the first unused crtc that can drive this connector,
10264 * and use that if we find one
79e53945
JB		 10265 */
10266
10267 /* See if we already have a CRTC for this connector */
10268 if (encoder->crtc) {
10269 crtc = encoder->crtc;
8261b191 10270
51fd371b 10271 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10272 if (ret)
ad3c558f 10273 goto fail;
4d02e2de 10274 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10275 if (ret)
ad3c558f 10276 goto fail;
7b24056b 10277
24218aac 10278 old->dpms_mode = connector->dpms;
8261b191
CW		 10279 old->load_detect_temp = false;
10280
10281 /* Make sure the crtc and connector are running */
24218aac
DV		 10282 if (connector->dpms != DRM_MODE_DPMS_ON)
10283 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10284
7173188d 10285 return true;
79e53945
JB		 10286 }
10287
10288 /* Find an unused one (if possible) */
70e1e0ec 10289 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10290 i++;
10291 if (!(encoder->possible_crtcs & (1 << i)))
10292 continue;
83d65738 10293 if (possible_crtc->state->enable)
a459249c 10294 continue;
a459249c
VS		 10295
10296 crtc = possible_crtc;
10297 break;
79e53945
JB		 10298 }
10299
10300 /*
10301 * If we didn't find an unused CRTC, don't use any.
10302 */
10303 if (!crtc) {
7173188d 10304 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10305 goto fail;
79e53945
JB		 10306 }
10307
51fd371b
RC		 10308 ret = drm_modeset_lock(&crtc->mutex, ctx);
10309 if (ret)
ad3c558f 10310 goto fail;
4d02e2de
DV		 10311 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10312 if (ret)
ad3c558f 10313 goto fail;
79e53945
JB		 10314
10315 intel_crtc = to_intel_crtc(crtc);
24218aac 10316 old->dpms_mode = connector->dpms;
8261b191 10317 old->load_detect_temp = true;
d2dff872 10318 old->release_fb = NULL;
79e53945 10319
83a57153
ACO		 10320 state = drm_atomic_state_alloc(dev);
10321 if (!state)
10322 return false;
10323
10324 state->acquire_ctx = ctx;
10325
944b0c76
ACO		 10326 connector_state = drm_atomic_get_connector_state(state, connector);
10327 if (IS_ERR(connector_state)) {
10328 ret = PTR_ERR(connector_state);
10329 goto fail;
10330 }
10331
10332 connector_state->crtc = crtc;
10333 connector_state->best_encoder = &intel_encoder->base;
10334
4be07317
ACO		 10335 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10336 if (IS_ERR(crtc_state)) {
10337 ret = PTR_ERR(crtc_state);
10338 goto fail;
10339 }
10340
49d6fa21 10341 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10342
6492711d
CW		 10343 if (!mode)
10344 mode = &load_detect_mode;
79e53945 10345
d2dff872
CW		 10346 /* We need a framebuffer large enough to accommodate all accesses
10347 * that the plane may generate whilst we perform load detection.
10348 * We can not rely on the fbcon either being present (we get called
10349 * during its initialisation to detect all boot displays, or it may
10350 * not even exist) or that it is large enough to satisfy the
10351 * requested mode.
10352 */
94352cf9
DV		 10353 fb = mode_fits_in_fbdev(dev, mode);
10354 if (fb == NULL) {
d2dff872 10355 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10356 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10357 old->release_fb = fb;
d2dff872
CW		 10358 } else
10359 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10360 if (IS_ERR(fb)) {
d2dff872 10361 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10362 goto fail;
79e53945 10363 }
79e53945 10364
d3a40d1b
ACO		 10365 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10366 if (ret)
10367 goto fail;
10368
8c7b5ccb
ACO		 10369 drm_mode_copy(&crtc_state->base.mode, mode);
10370
74c090b1 10371 if (drm_atomic_commit(state)) {
6492711d 10372 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10373 if (old->release_fb)
10374 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10375 goto fail;
79e53945 10376 }
9128b040 10377 crtc->primary->crtc = crtc;
7173188d 10378
79e53945 10379 /* let the connector get through one full cycle before testing */
9d0498a2 10380 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10381 return true;
412b61d8 10382
ad3c558f 10383fail:
e5d958ef
ACO		 10384 drm_atomic_state_free(state);
10385 state = NULL;
83a57153 10386
51fd371b
RC		 10387 if (ret == -EDEADLK) {
10388 drm_modeset_backoff(ctx);
10389 goto retry;
10390 }
10391
412b61d8 10392 return false;
79e53945
JB		 10393}
10394
d2434ab7 10395void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10396 struct intel_load_detect_pipe *old,
10397 struct drm_modeset_acquire_ctx *ctx)
79e53945 10398{
83a57153 10399 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10400 struct intel_encoder *intel_encoder =
10401 intel_attached_encoder(connector);
4ef69c7a 10402 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10403 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10405 struct drm_atomic_state *state;
944b0c76 10406 struct drm_connector_state *connector_state;
4be07317 10407 struct intel_crtc_state *crtc_state;
d3a40d1b 10408 int ret;
79e53945 10409
d2dff872 10410 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10411 connector->base.id, connector->name,
8e329a03 10412 encoder->base.id, encoder->name);
d2dff872 10413
8261b191 10414 if (old->load_detect_temp) {
83a57153 10415 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10416 if (!state)
10417 goto fail;
83a57153
ACO		 10418
10419 state->acquire_ctx = ctx;
10420
944b0c76
ACO		 10421 connector_state = drm_atomic_get_connector_state(state, connector);
10422 if (IS_ERR(connector_state))
10423 goto fail;
10424
4be07317
ACO		 10425 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10426 if (IS_ERR(crtc_state))
10427 goto fail;
10428
944b0c76
ACO		 10429 connector_state->best_encoder = NULL;
10430 connector_state->crtc = NULL;
10431
49d6fa21 10432 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10433
d3a40d1b
ACO		 10434 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10435 0, 0);
10436 if (ret)
10437 goto fail;
10438
74c090b1 10439 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10440 if (ret)
10441 goto fail;
d2dff872 10442
36206361
DV		 10443 if (old->release_fb) {
10444 drm_framebuffer_unregister_private(old->release_fb);
10445 drm_framebuffer_unreference(old->release_fb);
10446 }
d2dff872 10447
0622a53c 10448 return;
79e53945
JB		 10449 }
10450
c751ce4f 10451 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10452 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10453 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10454
10455 return;
10456fail:
10457 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10458 drm_atomic_state_free(state);
79e53945
JB		 10459}
10460
da4a1efa 10461static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10462 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10463{
10464 struct drm_i915_private *dev_priv = dev->dev_private;
10465 u32 dpll = pipe_config->dpll_hw_state.dpll;
10466
10467 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10468 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10469 else if (HAS_PCH_SPLIT(dev))
10470 return 120000;
10471 else if (!IS_GEN2(dev))
10472 return 96000;
10473 else
10474 return 48000;
10475}
10476
79e53945 10477/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10478static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10479 struct intel_crtc_state *pipe_config)
79e53945 10480{
f1f644dc 10481 struct drm_device *dev = crtc->base.dev;
79e53945 10482 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10483 int pipe = pipe_config->cpu_transcoder;
293623f7 10484 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10485 u32 fp;
10486 intel_clock_t clock;
dccbea3b 10487 int port_clock;
da4a1efa 10488 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10489
10490 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10491 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10492 else
293623f7 10493 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10494
10495 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10496 if (IS_PINEVIEW(dev)) {
10497 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10498 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10499 } else {
10500 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10501 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10502 }
10503
a6c45cf0 10504 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10505 if (IS_PINEVIEW(dev))
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10508 else
10509 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10510 DPLL_FPA01_P1_POST_DIV_SHIFT);
10511
10512 switch (dpll & DPLL_MODE_MASK) {
10513 case DPLLB_MODE_DAC_SERIAL:
10514 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10515 5 : 10;
10516 break;
10517 case DPLLB_MODE_LVDS:
10518 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10519 7 : 14;
10520 break;
10521 default:
28c97730 10522 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10523 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10524 return;
79e53945
JB		 10525 }
10526
ac58c3f0 10527 if (IS_PINEVIEW(dev))
dccbea3b 10528 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10529 else
dccbea3b 10530 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10531 } else {
0fb58223 10532 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10533 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10534
10535 if (is_lvds) {
10536 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10537 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10538
10539 if (lvds & LVDS_CLKB_POWER_UP)
10540 clock.p2 = 7;
10541 else
10542 clock.p2 = 14;
79e53945
JB		 10543 } else {
10544 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10545 clock.p1 = 2;
10546 else {
10547 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10548 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10549 }
10550 if (dpll & PLL_P2_DIVIDE_BY_4)
10551 clock.p2 = 4;
10552 else
10553 clock.p2 = 2;
79e53945 10554 }
da4a1efa 10555
dccbea3b 10556 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10557 }
10558
18442d08
VS		 10559 /*
10560 * This value includes pixel_multiplier. We will use
241bfc38 10561 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10562 * encoder's get_config() function.
10563 */
dccbea3b 10564 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10565}
10566
6878da05
VS		 10567int intel_dotclock_calculate(int link_freq,
10568 const struct intel_link_m_n *m_n)
f1f644dc 10569{
f1f644dc
JB		 10570 /*
10571 * The calculation for the data clock is:
1041a02f 10572 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10573 * But we want to avoid losing precison if possible, so:
1041a02f 10574 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10575 *
10576 * and the link clock is simpler:
1041a02f 10577 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10578 */
10579
6878da05
VS		 10580 if (!m_n->link_n)
10581 return 0;
f1f644dc 10582
6878da05
VS		 10583 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10584}
f1f644dc 10585
18442d08 10586static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10587 struct intel_crtc_state *pipe_config)
6878da05
VS		 10588{
10589 struct drm_device *dev = crtc->base.dev;
79e53945 10590
18442d08
VS		 10591 /* read out port_clock from the DPLL */
10592 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10593
f1f644dc 10594 /*
18442d08 10595 * This value does not include pixel_multiplier.
241bfc38 10596 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10597 * agree once we know their relationship in the encoder's
10598 * get_config() function.
79e53945 10599 */
2d112de7 10600 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10601 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10602 &pipe_config->fdi_m_n);
79e53945
JB		 10603}
10604
10605/** Returns the currently programmed mode of the given pipe. */
10606struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10607 struct drm_crtc *crtc)
10608{
548f245b 10609 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10611 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10612 struct drm_display_mode *mode;
5cec258b 10613 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10614 int htot = I915_READ(HTOTAL(cpu_transcoder));
10615 int hsync = I915_READ(HSYNC(cpu_transcoder));
10616 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10617 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10618 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10619
10620 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10621 if (!mode)
10622 return NULL;
10623
f1f644dc
JB		 10624 /*
10625 * Construct a pipe_config sufficient for getting the clock info
10626 * back out of crtc_clock_get.
10627 *
10628 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10629 * to use a real value here instead.
10630 */
293623f7 10631 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10632 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10633 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10634 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10635 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10636 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10637
773ae034 10638 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10639 mode->hdisplay = (htot & 0xffff) + 1;
10640 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10641 mode->hsync_start = (hsync & 0xffff) + 1;
10642 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10643 mode->vdisplay = (vtot & 0xffff) + 1;
10644 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10645 mode->vsync_start = (vsync & 0xffff) + 1;
10646 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10647
10648 drm_mode_set_name(mode);
79e53945
JB		 10649
10650 return mode;
10651}
10652
f047e395
CW		 10653void intel_mark_busy(struct drm_device *dev)
10654{
c67a470b
PZ		 10655 struct drm_i915_private *dev_priv = dev->dev_private;
10656
f62a0076
CW		 10657 if (dev_priv->mm.busy)
10658 return;
10659
43694d69 10660 intel_runtime_pm_get(dev_priv);
c67a470b 10661 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10662 if (INTEL_INFO(dev)->gen >= 6)
10663 gen6_rps_busy(dev_priv);
f62a0076 10664 dev_priv->mm.busy = true;
f047e395
CW		 10665}
10666
10667void intel_mark_idle(struct drm_device *dev)
652c393a 10668{
c67a470b 10669 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10670
f62a0076
CW		 10671 if (!dev_priv->mm.busy)
10672 return;
10673
10674 dev_priv->mm.busy = false;
10675
3d13ef2e 10676 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10677 gen6_rps_idle(dev->dev_private);
bb4cdd53 10678
43694d69 10679 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10680}
10681
79e53945
JB		 10682static void intel_crtc_destroy(struct drm_crtc *crtc)
10683{
10684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10685 struct drm_device *dev = crtc->dev;
10686 struct intel_unpin_work *work;
67e77c5a 10687
5e2d7afc 10688 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10689 work = intel_crtc->unpin_work;
10690 intel_crtc->unpin_work = NULL;
5e2d7afc 10691 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10692
10693 if (work) {
10694 cancel_work_sync(&work->work);
10695 kfree(work);
10696 }
79e53945
JB		 10697
10698 drm_crtc_cleanup(crtc);
67e77c5a 10699
79e53945
JB		 10700 kfree(intel_crtc);
10701}
10702
6b95a207
KH		 10703static void intel_unpin_work_fn(struct work_struct *__work)
10704{
10705 struct intel_unpin_work *work =
10706 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10707 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10708 struct drm_device *dev = crtc->base.dev;
10709 struct drm_plane *primary = crtc->base.primary;
6b95a207 10710
b4a98e57 10711 mutex_lock(&dev->struct_mutex);
a9ff8714 10712 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10713 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10714
f06cc1b9 10715 if (work->flip_queued_req)
146d84f0 10716 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10717 mutex_unlock(&dev->struct_mutex);
10718
a9ff8714 10719 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10720 drm_framebuffer_unreference(work->old_fb);
f99d7069 10721
a9ff8714
VS		 10722 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10723 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10724
6b95a207
KH		 10725 kfree(work);
10726}
10727
1afe3e9d 10728static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10729 struct drm_crtc *crtc)
6b95a207 10730{
6b95a207
KH		 10731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10732 struct intel_unpin_work *work;
6b95a207
KH		 10733 unsigned long flags;
10734
10735 /* Ignore early vblank irqs */
10736 if (intel_crtc == NULL)
10737 return;
10738
f326038a
DV		 10739 /*
10740 * This is called both by irq handlers and the reset code (to complete
10741 * lost pageflips) so needs the full irqsave spinlocks.
10742 */
6b95a207
KH		 10743 spin_lock_irqsave(&dev->event_lock, flags);
10744 work = intel_crtc->unpin_work;
e7d841ca
CW		 10745
10746 /* Ensure we don't miss a work->pending update ... */
10747 smp_rmb();
10748
10749 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10750 spin_unlock_irqrestore(&dev->event_lock, flags);
10751 return;
10752 }
10753
d6bbafa1 10754 page_flip_completed(intel_crtc);
0af7e4df 10755
6b95a207 10756 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10757}
10758
1afe3e9d
JB		 10759void intel_finish_page_flip(struct drm_device *dev, int pipe)
10760{
fbee40df 10761 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10762 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10763
49b14a5c 10764 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10765}
10766
10767void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10768{
fbee40df 10769 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10770 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10771
49b14a5c 10772 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10773}
10774
75f7f3ec
VS		 10775/* Is 'a' after or equal to 'b'? */
10776static bool g4x_flip_count_after_eq(u32 a, u32 b)
10777{
10778 return !((a - b) & 0x80000000);
10779}
10780
10781static bool page_flip_finished(struct intel_crtc *crtc)
10782{
10783 struct drm_device *dev = crtc->base.dev;
10784 struct drm_i915_private *dev_priv = dev->dev_private;
10785
bdfa7542
VS		 10786 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10787 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10788 return true;
10789
75f7f3ec
VS		 10790 /*
10791 * The relevant registers doen't exist on pre-ctg.
10792 * As the flip done interrupt doesn't trigger for mmio
10793 * flips on gmch platforms, a flip count check isn't
10794 * really needed there. But since ctg has the registers,
10795 * include it in the check anyway.
10796 */
10797 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10798 return true;
10799
10800 /*
10801 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10802 * used the same base address. In that case the mmio flip might
10803 * have completed, but the CS hasn't even executed the flip yet.
10804 *
10805 * A flip count check isn't enough as the CS might have updated
10806 * the base address just after start of vblank, but before we
10807 * managed to process the interrupt. This means we'd complete the
10808 * CS flip too soon.
10809 *
10810 * Combining both checks should get us a good enough result. It may
10811 * still happen that the CS flip has been executed, but has not
10812 * yet actually completed. But in case the base address is the same
10813 * anyway, we don't really care.
10814 */
10815 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10816 crtc->unpin_work->gtt_offset &&
10817 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10818 crtc->unpin_work->flip_count);
10819}
10820
6b95a207
KH		 10821void intel_prepare_page_flip(struct drm_device *dev, int plane)
10822{
fbee40df 10823 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10824 struct intel_crtc *intel_crtc =
10825 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10826 unsigned long flags;
10827
f326038a
DV		 10828
10829 /*
10830 * This is called both by irq handlers and the reset code (to complete
10831 * lost pageflips) so needs the full irqsave spinlocks.
10832 *
10833 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10834 * generate a page-flip completion irq, i.e. every modeset
10835 * is also accompanied by a spurious intel_prepare_page_flip().
10836 */
6b95a207 10837 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10838 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10839 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10840 spin_unlock_irqrestore(&dev->event_lock, flags);
10841}
10842
eba905b2 10843static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10844{
10845 /* Ensure that the work item is consistent when activating it ... */
10846 smp_wmb();
10847 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10848 /* and that it is marked active as soon as the irq could fire. */
10849 smp_wmb();
10850}
10851
8c9f3aaf
JB		 10852static int intel_gen2_queue_flip(struct drm_device *dev,
10853 struct drm_crtc *crtc,
10854 struct drm_framebuffer *fb,
ed8d1975 10855 struct drm_i915_gem_object *obj,
6258fbe2 10856 struct drm_i915_gem_request *req,
ed8d1975 10857 uint32_t flags)
8c9f3aaf 10858{
6258fbe2 10859 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10861 u32 flip_mask;
10862 int ret;
10863
5fb9de1a 10864 ret = intel_ring_begin(req, 6);
8c9f3aaf 10865 if (ret)
4fa62c89 10866 return ret;
8c9f3aaf
JB		 10867
10868 /* Can't queue multiple flips, so wait for the previous
10869 * one to finish before executing the next.
10870 */
10871 if (intel_crtc->plane)
10872 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10873 else
10874 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10875 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10876 intel_ring_emit(ring, MI_NOOP);
10877 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10878 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10879 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10880 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10881 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10882
10883 intel_mark_page_flip_active(intel_crtc);
83d4092b 10884 return 0;
8c9f3aaf
JB		 10885}
10886
10887static int intel_gen3_queue_flip(struct drm_device *dev,
10888 struct drm_crtc *crtc,
10889 struct drm_framebuffer *fb,
ed8d1975 10890 struct drm_i915_gem_object *obj,
6258fbe2 10891 struct drm_i915_gem_request *req,
ed8d1975 10892 uint32_t flags)
8c9f3aaf 10893{
6258fbe2 10894 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10896 u32 flip_mask;
10897 int ret;
10898
5fb9de1a 10899 ret = intel_ring_begin(req, 6);
8c9f3aaf 10900 if (ret)
4fa62c89 10901 return ret;
8c9f3aaf
JB		 10902
10903 if (intel_crtc->plane)
10904 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10905 else
10906 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10907 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10908 intel_ring_emit(ring, MI_NOOP);
10909 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10910 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10911 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10912 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10913 intel_ring_emit(ring, MI_NOOP);
10914
e7d841ca 10915 intel_mark_page_flip_active(intel_crtc);
83d4092b 10916 return 0;
8c9f3aaf
JB		 10917}
10918
10919static int intel_gen4_queue_flip(struct drm_device *dev,
10920 struct drm_crtc *crtc,
10921 struct drm_framebuffer *fb,
ed8d1975 10922 struct drm_i915_gem_object *obj,
6258fbe2 10923 struct drm_i915_gem_request *req,
ed8d1975 10924 uint32_t flags)
8c9f3aaf 10925{
6258fbe2 10926 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10929 uint32_t pf, pipesrc;
10930 int ret;
10931
5fb9de1a 10932 ret = intel_ring_begin(req, 4);
8c9f3aaf 10933 if (ret)
4fa62c89 10934 return ret;
8c9f3aaf
JB		 10935
10936 /* i965+ uses the linear or tiled offsets from the
10937 * Display Registers (which do not change across a page-flip)
10938 * so we need only reprogram the base address.
10939 */
6d90c952
DV		 10940 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10941 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10942 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10943 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10944 obj->tiling_mode);
8c9f3aaf
JB		 10945
10946 /* XXX Enabling the panel-fitter across page-flip is so far
10947 * untested on non-native modes, so ignore it for now.
10948 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10949 */
10950 pf = 0;
10951 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10952 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10953
10954 intel_mark_page_flip_active(intel_crtc);
83d4092b 10955 return 0;
8c9f3aaf
JB		 10956}
10957
10958static int intel_gen6_queue_flip(struct drm_device *dev,
10959 struct drm_crtc *crtc,
10960 struct drm_framebuffer *fb,
ed8d1975 10961 struct drm_i915_gem_object *obj,
6258fbe2 10962 struct drm_i915_gem_request *req,
ed8d1975 10963 uint32_t flags)
8c9f3aaf 10964{
6258fbe2 10965 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10966 struct drm_i915_private *dev_priv = dev->dev_private;
10967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10968 uint32_t pf, pipesrc;
10969 int ret;
10970
5fb9de1a 10971 ret = intel_ring_begin(req, 4);
8c9f3aaf 10972 if (ret)
4fa62c89 10973 return ret;
8c9f3aaf 10974
6d90c952
DV		 10975 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10976 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10977 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10978 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10979
dc257cf1
DV		 10980 /* Contrary to the suggestions in the documentation,
10981 * "Enable Panel Fitter" does not seem to be required when page
10982 * flipping with a non-native mode, and worse causes a normal
10983 * modeset to fail.
10984 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10985 */
10986 pf = 0;
8c9f3aaf 10987 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10988 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10989
10990 intel_mark_page_flip_active(intel_crtc);
83d4092b 10991 return 0;
8c9f3aaf
JB		 10992}
10993
7c9017e5
JB		 10994static int intel_gen7_queue_flip(struct drm_device *dev,
10995 struct drm_crtc *crtc,
10996 struct drm_framebuffer *fb,
ed8d1975 10997 struct drm_i915_gem_object *obj,
6258fbe2 10998 struct drm_i915_gem_request *req,
ed8d1975 10999 uint32_t flags)
7c9017e5 11000{
6258fbe2 11001 struct intel_engine_cs *ring = req->ring;
7c9017e5 11002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11003 uint32_t plane_bit = 0;
ffe74d75
CW		 11004 int len, ret;
11005
eba905b2 11006 switch (intel_crtc->plane) {
cb05d8de
DV		 11007 case PLANE_A:
11008 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11009 break;
11010 case PLANE_B:
11011 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11012 break;
11013 case PLANE_C:
11014 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11015 break;
11016 default:
11017 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11018 return -ENODEV;
cb05d8de
DV		 11019 }
11020
ffe74d75 11021 len = 4;
f476828a 11022 if (ring->id == RCS) {
ffe74d75 11023 len += 6;
f476828a
DL		 11024 /*
11025 * On Gen 8, SRM is now taking an extra dword to accommodate
11026 * 48bits addresses, and we need a NOOP for the batch size to
11027 * stay even.
11028 */
11029 if (IS_GEN8(dev))
11030 len += 2;
11031 }
ffe74d75 11032
f66fab8e
VS		 11033 /*
11034 * BSpec MI_DISPLAY_FLIP for IVB:
11035 * "The full packet must be contained within the same cache line."
11036 *
11037 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11038 * cacheline, if we ever start emitting more commands before
11039 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11040 * then do the cacheline alignment, and finally emit the
11041 * MI_DISPLAY_FLIP.
11042 */
bba09b12 11043 ret = intel_ring_cacheline_align(req);
f66fab8e 11044 if (ret)
4fa62c89 11045 return ret;
f66fab8e 11046
5fb9de1a 11047 ret = intel_ring_begin(req, len);
7c9017e5 11048 if (ret)
4fa62c89 11049 return ret;
7c9017e5 11050
ffe74d75
CW		 11051 /* Unmask the flip-done completion message. Note that the bspec says that
11052 * we should do this for both the BCS and RCS, and that we must not unmask
11053 * more than one flip event at any time (or ensure that one flip message
11054 * can be sent by waiting for flip-done prior to queueing new flips).
11055 * Experimentation says that BCS works despite DERRMR masking all
11056 * flip-done completion events and that unmasking all planes at once
11057 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11058 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11059 */
11060 if (ring->id == RCS) {
11061 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11062 intel_ring_emit(ring, DERRMR);
11063 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11064 DERRMR_PIPEB_PRI_FLIP_DONE |
11065 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11066 if (IS_GEN8(dev))
f1afe24f 11067 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11068 MI_SRM_LRM_GLOBAL_GTT);
11069 else
f1afe24f 11070 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11071 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11072 intel_ring_emit(ring, DERRMR);
11073 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11074 if (IS_GEN8(dev)) {
11075 intel_ring_emit(ring, 0);
11076 intel_ring_emit(ring, MI_NOOP);
11077 }
ffe74d75
CW		 11078 }
11079
cb05d8de 11080 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11081 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11082 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11083 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11084
11085 intel_mark_page_flip_active(intel_crtc);
83d4092b 11086 return 0;
7c9017e5
JB		 11087}
11088
84c33a64
SG		 11089static bool use_mmio_flip(struct intel_engine_cs *ring,
11090 struct drm_i915_gem_object *obj)
11091{
11092 /*
11093 * This is not being used for older platforms, because
11094 * non-availability of flip done interrupt forces us to use
11095 * CS flips. Older platforms derive flip done using some clever
11096 * tricks involving the flip_pending status bits and vblank irqs.
11097 * So using MMIO flips there would disrupt this mechanism.
11098 */
11099
8e09bf83
CW		 11100 if (ring == NULL)
11101 return true;
11102
84c33a64
SG		 11103 if (INTEL_INFO(ring->dev)->gen < 5)
11104 return false;
11105
11106 if (i915.use_mmio_flip < 0)
11107 return false;
11108 else if (i915.use_mmio_flip > 0)
11109 return true;
14bf993e
OM		 11110 else if (i915.enable_execlists)
11111 return true;
84c33a64 11112 else
b4716185 11113 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11114}
11115
ff944564
DL		 11116static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11117{
11118 struct drm_device *dev = intel_crtc->base.dev;
11119 struct drm_i915_private *dev_priv = dev->dev_private;
11120 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11121 const enum pipe pipe = intel_crtc->pipe;
11122 u32 ctl, stride;
11123
11124 ctl = I915_READ(PLANE_CTL(pipe, 0));
11125 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11126 switch (fb->modifier[0]) {
11127 case DRM_FORMAT_MOD_NONE:
11128 break;
11129 case I915_FORMAT_MOD_X_TILED:
ff944564 11130 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11131 break;
11132 case I915_FORMAT_MOD_Y_TILED:
11133 ctl |= PLANE_CTL_TILED_Y;
11134 break;
11135 case I915_FORMAT_MOD_Yf_TILED:
11136 ctl |= PLANE_CTL_TILED_YF;
11137 break;
11138 default:
11139 MISSING_CASE(fb->modifier[0]);
11140 }
ff944564
DL		 11141
11142 /*
11143 * The stride is either expressed as a multiple of 64 bytes chunks for
11144 * linear buffers or in number of tiles for tiled buffers.
11145 */
2ebef630
TU		 11146 stride = fb->pitches[0] /
11147 intel_fb_stride_alignment(dev, fb->modifier[0],
11148 fb->pixel_format);
ff944564
DL		 11149
11150 /*
11151 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11152 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11153 */
11154 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11155 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11156
11157 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11158 POSTING_READ(PLANE_SURF(pipe, 0));
11159}
11160
11161static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11162{
11163 struct drm_device *dev = intel_crtc->base.dev;
11164 struct drm_i915_private *dev_priv = dev->dev_private;
11165 struct intel_framebuffer *intel_fb =
11166 to_intel_framebuffer(intel_crtc->base.primary->fb);
11167 struct drm_i915_gem_object *obj = intel_fb->obj;
11168 u32 dspcntr;
11169 u32 reg;
11170
84c33a64
SG		 11171 reg = DSPCNTR(intel_crtc->plane);
11172 dspcntr = I915_READ(reg);
11173
c5d97472
DL		 11174 if (obj->tiling_mode != I915_TILING_NONE)
11175 dspcntr |= DISPPLANE_TILED;
11176 else
11177 dspcntr &= ~DISPPLANE_TILED;
11178
84c33a64
SG		 11179 I915_WRITE(reg, dspcntr);
11180
11181 I915_WRITE(DSPSURF(intel_crtc->plane),
11182 intel_crtc->unpin_work->gtt_offset);
11183 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11184
ff944564
DL		 11185}
11186
11187/*
11188 * XXX: This is the temporary way to update the plane registers until we get
11189 * around to using the usual plane update functions for MMIO flips
11190 */
11191static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11192{
11193 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11194
11195 intel_mark_page_flip_active(intel_crtc);
11196
34e0adbb 11197 intel_pipe_update_start(intel_crtc);
ff944564
DL		 11198
11199 if (INTEL_INFO(dev)->gen >= 9)
11200 skl_do_mmio_flip(intel_crtc);
11201 else
11202 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11203 ilk_do_mmio_flip(intel_crtc);
11204
34e0adbb 11205 intel_pipe_update_end(intel_crtc);
84c33a64
SG		 11206}
11207
9362c7c5 11208static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11209{
b2cfe0ab
CW		 11210 struct intel_mmio_flip *mmio_flip =
11211 container_of(work, struct intel_mmio_flip, work);
84c33a64 11212
eed29a5b
DV		 11213 if (mmio_flip->req)
11214 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11215 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11216 false, NULL,
11217 &mmio_flip->i915->rps.mmioflips));
84c33a64 11218
b2cfe0ab
CW		 11219 intel_do_mmio_flip(mmio_flip->crtc);
11220
eed29a5b 11221 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11222 kfree(mmio_flip);
84c33a64
SG		 11223}
11224
11225static int intel_queue_mmio_flip(struct drm_device *dev,
11226 struct drm_crtc *crtc,
11227 struct drm_framebuffer *fb,
11228 struct drm_i915_gem_object *obj,
11229 struct intel_engine_cs *ring,
11230 uint32_t flags)
11231{
b2cfe0ab
CW		 11232 struct intel_mmio_flip *mmio_flip;
11233
11234 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11235 if (mmio_flip == NULL)
11236 return -ENOMEM;
84c33a64 11237
bcafc4e3 11238 mmio_flip->i915 = to_i915(dev);
eed29a5b 11239 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11240 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11241
b2cfe0ab
CW		 11242 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11243 schedule_work(&mmio_flip->work);
84c33a64 11244
84c33a64
SG		 11245 return 0;
11246}
11247
8c9f3aaf
JB		 11248static int intel_default_queue_flip(struct drm_device *dev,
11249 struct drm_crtc *crtc,
11250 struct drm_framebuffer *fb,
ed8d1975 11251 struct drm_i915_gem_object *obj,
6258fbe2 11252 struct drm_i915_gem_request *req,
ed8d1975 11253 uint32_t flags)
8c9f3aaf
JB		 11254{
11255 return -ENODEV;
11256}
11257
d6bbafa1
CW		 11258static bool __intel_pageflip_stall_check(struct drm_device *dev,
11259 struct drm_crtc *crtc)
11260{
11261 struct drm_i915_private *dev_priv = dev->dev_private;
11262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11263 struct intel_unpin_work *work = intel_crtc->unpin_work;
11264 u32 addr;
11265
11266 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11267 return true;
11268
908565c2
CW		 11269 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11270 return false;
11271
d6bbafa1
CW		 11272 if (!work->enable_stall_check)
11273 return false;
11274
11275 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11276 if (work->flip_queued_req &&
11277 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11278 return false;
11279
1e3feefd 11280 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11281 }
11282
1e3feefd 11283 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11284 return false;
11285
11286 /* Potential stall - if we see that the flip has happened,
11287 * assume a missed interrupt. */
11288 if (INTEL_INFO(dev)->gen >= 4)
11289 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11290 else
11291 addr = I915_READ(DSPADDR(intel_crtc->plane));
11292
11293 /* There is a potential issue here with a false positive after a flip
11294 * to the same address. We could address this by checking for a
11295 * non-incrementing frame counter.
11296 */
11297 return addr == work->gtt_offset;
11298}
11299
11300void intel_check_page_flip(struct drm_device *dev, int pipe)
11301{
11302 struct drm_i915_private *dev_priv = dev->dev_private;
11303 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11305 struct intel_unpin_work *work;
f326038a 11306
6c51d46f 11307 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11308
11309 if (crtc == NULL)
11310 return;
11311
f326038a 11312 spin_lock(&dev->event_lock);
6ad790c0
CW		 11313 work = intel_crtc->unpin_work;
11314 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11315 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11316 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11317 page_flip_completed(intel_crtc);
6ad790c0 11318 work = NULL;
d6bbafa1 11319 }
6ad790c0
CW		 11320 if (work != NULL &&
11321 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11322 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11323 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11324}
11325
6b95a207
KH		 11326static int intel_crtc_page_flip(struct drm_crtc *crtc,
11327 struct drm_framebuffer *fb,
ed8d1975
KP		 11328 struct drm_pending_vblank_event *event,
11329 uint32_t page_flip_flags)
6b95a207
KH		 11330{
11331 struct drm_device *dev = crtc->dev;
11332 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11333 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11336 struct drm_plane *primary = crtc->primary;
a071fa00 11337 enum pipe pipe = intel_crtc->pipe;
6b95a207 11338 struct intel_unpin_work *work;
a4872ba6 11339 struct intel_engine_cs *ring;
cf5d8a46 11340 bool mmio_flip;
91af127f 11341 struct drm_i915_gem_request *request = NULL;
52e68630 11342 int ret;
6b95a207 11343
2ff8fde1
MR		 11344 /*
11345 * drm_mode_page_flip_ioctl() should already catch this, but double
11346 * check to be safe. In the future we may enable pageflipping from
11347 * a disabled primary plane.
11348 */
11349 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11350 return -EBUSY;
11351
e6a595d2 11352 /* Can't change pixel format via MI display flips. */
f4510a27 11353 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11354 return -EINVAL;
11355
11356 /*
11357 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11358 * Note that pitch changes could also affect these register.
11359 */
11360 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11361 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11362 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11363 return -EINVAL;
11364
f900db47
CW		 11365 if (i915_terminally_wedged(&dev_priv->gpu_error))
11366 goto out_hang;
11367
b14c5679 11368 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11369 if (work == NULL)
11370 return -ENOMEM;
11371
6b95a207 11372 work->event = event;
b4a98e57 11373 work->crtc = crtc;
ab8d6675 11374 work->old_fb = old_fb;
6b95a207
KH		 11375 INIT_WORK(&work->work, intel_unpin_work_fn);
11376
87b6b101 11377 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11378 if (ret)
11379 goto free_work;
11380
6b95a207 11381 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11382 spin_lock_irq(&dev->event_lock);
6b95a207 11383 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11384 /* Before declaring the flip queue wedged, check if
11385 * the hardware completed the operation behind our backs.
11386 */
11387 if (__intel_pageflip_stall_check(dev, crtc)) {
11388 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11389 page_flip_completed(intel_crtc);
11390 } else {
11391 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11392 spin_unlock_irq(&dev->event_lock);
468f0b44 11393
d6bbafa1
CW		 11394 drm_crtc_vblank_put(crtc);
11395 kfree(work);
11396 return -EBUSY;
11397 }
6b95a207
KH		 11398 }
11399 intel_crtc->unpin_work = work;
5e2d7afc 11400 spin_unlock_irq(&dev->event_lock);
6b95a207 11401
b4a98e57
CW		 11402 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11403 flush_workqueue(dev_priv->wq);
11404
75dfca80 11405 /* Reference the objects for the scheduled work. */
ab8d6675 11406 drm_framebuffer_reference(work->old_fb);
05394f39 11407 drm_gem_object_reference(&obj->base);
6b95a207 11408
f4510a27 11409 crtc->primary->fb = fb;
afd65eb4 11410 update_state_fb(crtc->primary);
1ed1f968 11411
e1f99ce6 11412 work->pending_flip_obj = obj;
e1f99ce6 11413
89ed88ba
CW		 11414 ret = i915_mutex_lock_interruptible(dev);
11415 if (ret)
11416 goto cleanup;
11417
b4a98e57 11418 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11419 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11420
75f7f3ec 11421 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11422 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11423
4fa62c89
VS		 11424 if (IS_VALLEYVIEW(dev)) {
11425 ring = &dev_priv->ring[BCS];
ab8d6675 11426 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11427 /* vlv: DISPLAY_FLIP fails to change tiling */
11428 ring = NULL;
48bf5b2d 11429 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11430 ring = &dev_priv->ring[BCS];
4fa62c89 11431 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11432 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11433 if (ring == NULL || ring->id != RCS)
11434 ring = &dev_priv->ring[BCS];
11435 } else {
11436 ring = &dev_priv->ring[RCS];
11437 }
11438
cf5d8a46
CW		 11439 mmio_flip = use_mmio_flip(ring, obj);
11440
11441 /* When using CS flips, we want to emit semaphores between rings.
11442 * However, when using mmio flips we will create a task to do the
11443 * synchronisation, so all we want here is to pin the framebuffer
11444 * into the display plane and skip any waits.
11445 */
82bc3b2d 11446 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11447 crtc->primary->state,
91af127f 11448 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11449 if (ret)
11450 goto cleanup_pending;
6b95a207 11451
dedf278c
TU		 11452 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11453 obj, 0);
11454 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11455
cf5d8a46 11456 if (mmio_flip) {
84c33a64
SG		 11457 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11458 page_flip_flags);
d6bbafa1
CW		 11459 if (ret)
11460 goto cleanup_unpin;
11461
f06cc1b9
JH		 11462 i915_gem_request_assign(&work->flip_queued_req,
11463 obj->last_write_req);
d6bbafa1 11464 } else {
6258fbe2
JH		 11465 if (!request) {
11466 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11467 if (ret)
11468 goto cleanup_unpin;
11469 }
11470
11471 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11472 page_flip_flags);
11473 if (ret)
11474 goto cleanup_unpin;
11475
6258fbe2 11476 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11477 }
11478
91af127f 11479 if (request)
75289874 11480 i915_add_request_no_flush(request);
91af127f 11481
1e3feefd 11482 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11483 work->enable_stall_check = true;
4fa62c89 11484
ab8d6675 11485 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11486 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11487 mutex_unlock(&dev->struct_mutex);
a071fa00 11488
4e1e26f1 11489 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11490 intel_frontbuffer_flip_prepare(dev,
11491 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11492
e5510fac
JB		 11493 trace_i915_flip_request(intel_crtc->plane, obj);
11494
6b95a207 11495 return 0;
96b099fd 11496
4fa62c89 11497cleanup_unpin:
82bc3b2d 11498 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11499cleanup_pending:
91af127f
JH		 11500 if (request)
11501 i915_gem_request_cancel(request);
b4a98e57 11502 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11503 mutex_unlock(&dev->struct_mutex);
11504cleanup:
f4510a27 11505 crtc->primary->fb = old_fb;
afd65eb4 11506 update_state_fb(crtc->primary);
89ed88ba
CW		 11507
11508 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11509 drm_framebuffer_unreference(work->old_fb);
96b099fd 11510
5e2d7afc 11511 spin_lock_irq(&dev->event_lock);
96b099fd 11512 intel_crtc->unpin_work = NULL;
5e2d7afc 11513 spin_unlock_irq(&dev->event_lock);
96b099fd 11514
87b6b101 11515 drm_crtc_vblank_put(crtc);
7317c75e 11516free_work:
96b099fd
CW		 11517 kfree(work);
11518
f900db47 11519 if (ret == -EIO) {
02e0efb5
ML		 11520 struct drm_atomic_state *state;
11521 struct drm_plane_state *plane_state;
11522
f900db47 11523out_hang:
02e0efb5
ML		 11524 state = drm_atomic_state_alloc(dev);
11525 if (!state)
11526 return -ENOMEM;
11527 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11528
11529retry:
11530 plane_state = drm_atomic_get_plane_state(state, primary);
11531 ret = PTR_ERR_OR_ZERO(plane_state);
11532 if (!ret) {
11533 drm_atomic_set_fb_for_plane(plane_state, fb);
11534
11535 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11536 if (!ret)
11537 ret = drm_atomic_commit(state);
11538 }
11539
11540 if (ret == -EDEADLK) {
11541 drm_modeset_backoff(state->acquire_ctx);
11542 drm_atomic_state_clear(state);
11543 goto retry;
11544 }
11545
11546 if (ret)
11547 drm_atomic_state_free(state);
11548
f0d3dad3 11549 if (ret == 0 && event) {
5e2d7afc 11550 spin_lock_irq(&dev->event_lock);
a071fa00 11551 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11552 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11553 }
f900db47 11554 }
96b099fd 11555 return ret;
6b95a207
KH		 11556}
11557
da20eabd
ML		 11558
11559/**
11560 * intel_wm_need_update - Check whether watermarks need updating
11561 * @plane: drm plane
11562 * @state: new plane state
11563 *
11564 * Check current plane state versus the new one to determine whether
11565 * watermarks need to be recalculated.
11566 *
11567 * Returns true or false.
11568 */
11569static bool intel_wm_need_update(struct drm_plane *plane,
11570 struct drm_plane_state *state)
11571{
7809e5ae
MR		 11572 struct intel_plane_state *new = to_intel_plane_state(state);
11573 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11574
11575 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11576 if (!plane->state->fb || !state->fb ||
11577 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
7809e5ae
MR		 11578 plane->state->rotation != state->rotation ||
11579 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11580 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11581 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11582 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
da20eabd
ML		 11583 return true;
11584
11585 return false;
11586}
11587
7809e5ae
MR		 11588static bool needs_scaling(struct intel_plane_state *state)
11589{
11590 int src_w = drm_rect_width(&state->src) >> 16;
11591 int src_h = drm_rect_height(&state->src) >> 16;
11592 int dst_w = drm_rect_width(&state->dst);
11593 int dst_h = drm_rect_height(&state->dst);
11594
11595 return (src_w != dst_w || src_h != dst_h);
11596}
11597
da20eabd
ML		 11598int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11599 struct drm_plane_state *plane_state)
11600{
11601 struct drm_crtc *crtc = crtc_state->crtc;
11602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11603 struct drm_plane *plane = plane_state->plane;
11604 struct drm_device *dev = crtc->dev;
11605 struct drm_i915_private *dev_priv = dev->dev_private;
11606 struct intel_plane_state *old_plane_state =
11607 to_intel_plane_state(plane->state);
11608 int idx = intel_crtc->base.base.id, ret;
11609 int i = drm_plane_index(plane);
11610 bool mode_changed = needs_modeset(crtc_state);
11611 bool was_crtc_enabled = crtc->state->active;
11612 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11613 bool turn_off, turn_on, visible, was_visible;
11614 struct drm_framebuffer *fb = plane_state->fb;
11615
11616 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11617 plane->type != DRM_PLANE_TYPE_CURSOR) {
11618 ret = skl_update_scaler_plane(
11619 to_intel_crtc_state(crtc_state),
11620 to_intel_plane_state(plane_state));
11621 if (ret)
11622 return ret;
11623 }
11624
11625 /*
11626 * Disabling a plane is always okay; we just need to update
11627 * fb tracking in a special way since cleanup_fb() won't
11628 * get called by the plane helpers.
11629 */
11630 if (old_plane_state->base.fb && !fb)
11631 intel_crtc->atomic.disabled_planes |= 1 << i;
11632
da20eabd
ML		 11633 was_visible = old_plane_state->visible;
11634 visible = to_intel_plane_state(plane_state)->visible;
11635
11636 if (!was_crtc_enabled && WARN_ON(was_visible))
11637 was_visible = false;
11638
11639 if (!is_crtc_enabled && WARN_ON(visible))
11640 visible = false;
11641
11642 if (!was_visible && !visible)
11643 return 0;
11644
11645 turn_off = was_visible && (!visible || mode_changed);
11646 turn_on = visible && (!was_visible || mode_changed);
11647
11648 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11649 plane->base.id, fb ? fb->base.id : -1);
11650
11651 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11652 plane->base.id, was_visible, visible,
11653 turn_off, turn_on, mode_changed);
11654
852eb00d 11655 if (turn_on) {
f015c551 11656 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11657 /* must disable cxsr around plane enable/disable */
11658 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11659 intel_crtc->atomic.disable_cxsr = true;
11660 /* to potentially re-enable cxsr */
11661 intel_crtc->atomic.wait_vblank = true;
11662 intel_crtc->atomic.update_wm_post = true;
11663 }
11664 } else if (turn_off) {
f015c551 11665 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11666 /* must disable cxsr around plane enable/disable */
11667 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11668 if (is_crtc_enabled)
11669 intel_crtc->atomic.wait_vblank = true;
11670 intel_crtc->atomic.disable_cxsr = true;
11671 }
11672 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11673 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11674 }
da20eabd 11675
8be6ca85 11676 if (visible || was_visible)
a9ff8714
VS		 11677 intel_crtc->atomic.fb_bits |=
11678 to_intel_plane(plane)->frontbuffer_bit;
11679
da20eabd
ML		 11680 switch (plane->type) {
11681 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11682 intel_crtc->atomic.wait_for_flips = true;
11683 intel_crtc->atomic.pre_disable_primary = turn_off;
11684 intel_crtc->atomic.post_enable_primary = turn_on;
11685
066cf55b
RV		 11686 if (turn_off) {
11687 /*
11688 * FIXME: Actually if we will still have any other
11689 * plane enabled on the pipe we could let IPS enabled
11690 * still, but for now lets consider that when we make
11691 * primary invisible by setting DSPCNTR to 0 on
11692 * update_primary_plane function IPS needs to be
11693 * disable.
11694 */
11695 intel_crtc->atomic.disable_ips = true;
11696
da20eabd 11697 intel_crtc->atomic.disable_fbc = true;
066cf55b 11698 }
da20eabd
ML		 11699
11700 /*
11701 * FBC does not work on some platforms for rotated
11702 * planes, so disable it when rotation is not 0 and
11703 * update it when rotation is set back to 0.
11704 *
11705 * FIXME: This is redundant with the fbc update done in
11706 * the primary plane enable function except that that
11707 * one is done too late. We eventually need to unify
11708 * this.
11709 */
11710
11711 if (visible &&
11712 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11713 dev_priv->fbc.crtc == intel_crtc &&
11714 plane_state->rotation != BIT(DRM_ROTATE_0))
11715 intel_crtc->atomic.disable_fbc = true;
11716
11717 /*
11718 * BDW signals flip done immediately if the plane
11719 * is disabled, even if the plane enable is already
11720 * armed to occur at the next vblank :(
11721 */
11722 if (turn_on && IS_BROADWELL(dev))
11723 intel_crtc->atomic.wait_vblank = true;
11724
11725 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11726 break;
11727 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11728 break;
11729 case DRM_PLANE_TYPE_OVERLAY:
7809e5ae
MR		 11730 /*
11731 * WaCxSRDisabledForSpriteScaling:ivb
11732 *
11733 * cstate->update_wm was already set above, so this flag will
11734 * take effect when we commit and program watermarks.
11735 */
11736 if (IS_IVYBRIDGE(dev) &&
11737 needs_scaling(to_intel_plane_state(plane_state)) &&
11738 !needs_scaling(old_plane_state)) {
11739 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11740 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11741 intel_crtc->atomic.wait_vblank = true;
11742 intel_crtc->atomic.update_sprite_watermarks |=
11743 1 << i;
11744 }
7809e5ae
MR		 11745
11746 break;
da20eabd
ML		 11747 }
11748 return 0;
11749}
11750
6d3a1ce7
ML		 11751static bool encoders_cloneable(const struct intel_encoder *a,
11752 const struct intel_encoder *b)
11753{
11754 /* masks could be asymmetric, so check both ways */
11755 return a == b || (a->cloneable & (1 << b->type) &&
11756 b->cloneable & (1 << a->type));
11757}
11758
11759static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11760 struct intel_crtc *crtc,
11761 struct intel_encoder *encoder)
11762{
11763 struct intel_encoder *source_encoder;
11764 struct drm_connector *connector;
11765 struct drm_connector_state *connector_state;
11766 int i;
11767
11768 for_each_connector_in_state(state, connector, connector_state, i) {
11769 if (connector_state->crtc != &crtc->base)
11770 continue;
11771
11772 source_encoder =
11773 to_intel_encoder(connector_state->best_encoder);
11774 if (!encoders_cloneable(encoder, source_encoder))
11775 return false;
11776 }
11777
11778 return true;
11779}
11780
11781static bool check_encoder_cloning(struct drm_atomic_state *state,
11782 struct intel_crtc *crtc)
11783{
11784 struct intel_encoder *encoder;
11785 struct drm_connector *connector;
11786 struct drm_connector_state *connector_state;
11787 int i;
11788
11789 for_each_connector_in_state(state, connector, connector_state, i) {
11790 if (connector_state->crtc != &crtc->base)
11791 continue;
11792
11793 encoder = to_intel_encoder(connector_state->best_encoder);
11794 if (!check_single_encoder_cloning(state, crtc, encoder))
11795 return false;
11796 }
11797
11798 return true;
11799}
11800
11801static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11802 struct drm_crtc_state *crtc_state)
11803{
cf5a15be 11804 struct drm_device *dev = crtc->dev;
ad421372 11805 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11807 struct intel_crtc_state *pipe_config =
11808 to_intel_crtc_state(crtc_state);
6d3a1ce7 11809 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11810 int ret;
6d3a1ce7
ML		 11811 bool mode_changed = needs_modeset(crtc_state);
11812
11813 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11814 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11815 return -EINVAL;
11816 }
11817
852eb00d
VS		 11818 if (mode_changed && !crtc_state->active)
11819 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11820
ad421372
ML		 11821 if (mode_changed && crtc_state->enable &&
11822 dev_priv->display.crtc_compute_clock &&
11823 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11824 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11825 pipe_config);
11826 if (ret)
11827 return ret;
11828 }
11829
e435d6e5 11830 ret = 0;
a28170f3
MR		 11831 if (dev_priv->display.compute_pipe_wm) {
11832 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11833 if (ret)
11834 return ret;
11835 }
11836
e435d6e5
ML		 11837 if (INTEL_INFO(dev)->gen >= 9) {
11838 if (mode_changed)
11839 ret = skl_update_scaler_crtc(pipe_config);
11840
11841 if (!ret)
11842 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11843 pipe_config);
11844 }
11845
11846 return ret;
6d3a1ce7
ML		 11847}
11848
65b38e0d 11849static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11850 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11851 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11852 .atomic_begin = intel_begin_crtc_commit,
11853 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11854 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11855};
11856
d29b2f9d
ACO		 11857static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11858{
11859 struct intel_connector *connector;
11860
11861 for_each_intel_connector(dev, connector) {
11862 if (connector->base.encoder) {
11863 connector->base.state->best_encoder =
11864 connector->base.encoder;
11865 connector->base.state->crtc =
11866 connector->base.encoder->crtc;
11867 } else {
11868 connector->base.state->best_encoder = NULL;
11869 connector->base.state->crtc = NULL;
11870 }
11871 }
11872}
11873
050f7aeb 11874static void
eba905b2 11875connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11876 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11877{
11878 int bpp = pipe_config->pipe_bpp;
11879
11880 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11881 connector->base.base.id,
c23cc417 11882 connector->base.name);
050f7aeb
DV		 11883
11884 /* Don't use an invalid EDID bpc value */
11885 if (connector->base.display_info.bpc &&
11886 connector->base.display_info.bpc * 3 < bpp) {
11887 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11888 bpp, connector->base.display_info.bpc*3);
11889 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11890 }
11891
11892 /* Clamp bpp to 8 on screens without EDID 1.4 */
11893 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11894 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11895 bpp);
11896 pipe_config->pipe_bpp = 24;
11897 }
11898}
11899
4e53c2e0 11900static int
050f7aeb 11901compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11902 struct intel_crtc_state *pipe_config)
4e53c2e0 11903{
050f7aeb 11904 struct drm_device *dev = crtc->base.dev;
1486017f 11905 struct drm_atomic_state *state;
da3ced29
ACO		 11906 struct drm_connector *connector;
11907 struct drm_connector_state *connector_state;
1486017f 11908 int bpp, i;
4e53c2e0 11909
d328c9d7 11910 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11911 bpp = 10*3;
d328c9d7
DV		 11912 else if (INTEL_INFO(dev)->gen >= 5)
11913 bpp = 12*3;
11914 else
11915 bpp = 8*3;
11916
4e53c2e0 11917
4e53c2e0
DV		 11918 pipe_config->pipe_bpp = bpp;
11919
1486017f
ACO		 11920 state = pipe_config->base.state;
11921
4e53c2e0 11922 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11923 for_each_connector_in_state(state, connector, connector_state, i) {
11924 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11925 continue;
11926
da3ced29
ACO		 11927 connected_sink_compute_bpp(to_intel_connector(connector),
11928 pipe_config);
4e53c2e0
DV		 11929 }
11930
11931 return bpp;
11932}
11933
644db711
DV		 11934static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11935{
11936 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11937 "type: 0x%x flags: 0x%x\n",
1342830c 11938 mode->crtc_clock,
644db711
DV		 11939 mode->crtc_hdisplay, mode->crtc_hsync_start,
11940 mode->crtc_hsync_end, mode->crtc_htotal,
11941 mode->crtc_vdisplay, mode->crtc_vsync_start,
11942 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11943}
11944
c0b03411 11945static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11946 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11947 const char *context)
11948{
6a60cd87
CK		 11949 struct drm_device *dev = crtc->base.dev;
11950 struct drm_plane *plane;
11951 struct intel_plane *intel_plane;
11952 struct intel_plane_state *state;
11953 struct drm_framebuffer *fb;
11954
11955 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11956 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11957
11958 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11959 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11960 pipe_config->pipe_bpp, pipe_config->dither);
11961 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11962 pipe_config->has_pch_encoder,
11963 pipe_config->fdi_lanes,
11964 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11965 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11966 pipe_config->fdi_m_n.tu);
90a6b7b0 11967 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11968 pipe_config->has_dp_encoder,
90a6b7b0 11969 pipe_config->lane_count,
eb14cb74
VS		 11970 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11971 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11972 pipe_config->dp_m_n.tu);
b95af8be 11973
90a6b7b0 11974 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11975 pipe_config->has_dp_encoder,
90a6b7b0 11976 pipe_config->lane_count,
b95af8be
VK		 11977 pipe_config->dp_m2_n2.gmch_m,
11978 pipe_config->dp_m2_n2.gmch_n,
11979 pipe_config->dp_m2_n2.link_m,
11980 pipe_config->dp_m2_n2.link_n,
11981 pipe_config->dp_m2_n2.tu);
11982
55072d19
DV		 11983 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11984 pipe_config->has_audio,
11985 pipe_config->has_infoframe);
11986
c0b03411 11987 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11988 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11989 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11990 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11991 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11992 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11993 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11994 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11995 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11996 crtc->num_scalers,
11997 pipe_config->scaler_state.scaler_users,
11998 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11999 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12000 pipe_config->gmch_pfit.control,
12001 pipe_config->gmch_pfit.pgm_ratios,
12002 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12003 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12004 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12005 pipe_config->pch_pfit.size,
12006 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12007 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12008 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12009
415ff0f6 12010 if (IS_BROXTON(dev)) {
05712c15 12011 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12012 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12013 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12014 pipe_config->ddi_pll_sel,
12015 pipe_config->dpll_hw_state.ebb0,
05712c15 12016 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12017 pipe_config->dpll_hw_state.pll0,
12018 pipe_config->dpll_hw_state.pll1,
12019 pipe_config->dpll_hw_state.pll2,
12020 pipe_config->dpll_hw_state.pll3,
12021 pipe_config->dpll_hw_state.pll6,
12022 pipe_config->dpll_hw_state.pll8,
05712c15 12023 pipe_config->dpll_hw_state.pll9,
c8453338 12024 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12025 pipe_config->dpll_hw_state.pcsdw12);
12026 } else if (IS_SKYLAKE(dev)) {
12027 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12028 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12029 pipe_config->ddi_pll_sel,
12030 pipe_config->dpll_hw_state.ctrl1,
12031 pipe_config->dpll_hw_state.cfgcr1,
12032 pipe_config->dpll_hw_state.cfgcr2);
12033 } else if (HAS_DDI(dev)) {
12034 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12035 pipe_config->ddi_pll_sel,
12036 pipe_config->dpll_hw_state.wrpll);
12037 } else {
12038 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12039 "fp0: 0x%x, fp1: 0x%x\n",
12040 pipe_config->dpll_hw_state.dpll,
12041 pipe_config->dpll_hw_state.dpll_md,
12042 pipe_config->dpll_hw_state.fp0,
12043 pipe_config->dpll_hw_state.fp1);
12044 }
12045
6a60cd87
CK		 12046 DRM_DEBUG_KMS("planes on this crtc\n");
12047 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12048 intel_plane = to_intel_plane(plane);
12049 if (intel_plane->pipe != crtc->pipe)
12050 continue;
12051
12052 state = to_intel_plane_state(plane->state);
12053 fb = state->base.fb;
12054 if (!fb) {
12055 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12056 "disabled, scaler_id = %d\n",
12057 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12058 plane->base.id, intel_plane->pipe,
12059 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12060 drm_plane_index(plane), state->scaler_id);
12061 continue;
12062 }
12063
12064 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12065 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12066 plane->base.id, intel_plane->pipe,
12067 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12068 drm_plane_index(plane));
12069 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12070 fb->base.id, fb->width, fb->height, fb->pixel_format);
12071 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12072 state->scaler_id,
12073 state->src.x1 >> 16, state->src.y1 >> 16,
12074 drm_rect_width(&state->src) >> 16,
12075 drm_rect_height(&state->src) >> 16,
12076 state->dst.x1, state->dst.y1,
12077 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12078 }
c0b03411
DV		 12079}
12080
5448a00d 12081static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12082{
5448a00d
ACO		 12083 struct drm_device *dev = state->dev;
12084 struct intel_encoder *encoder;
da3ced29 12085 struct drm_connector *connector;
5448a00d 12086 struct drm_connector_state *connector_state;
00f0b378 12087 unsigned int used_ports = 0;
5448a00d 12088 int i;
00f0b378
VS		 12089
12090 /*
12091 * Walk the connector list instead of the encoder
12092 * list to detect the problem on ddi platforms
12093 * where there's just one encoder per digital port.
12094 */
da3ced29 12095 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12096 if (!connector_state->best_encoder)
00f0b378
VS		 12097 continue;
12098
5448a00d
ACO		 12099 encoder = to_intel_encoder(connector_state->best_encoder);
12100
12101 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12102
12103 switch (encoder->type) {
12104 unsigned int port_mask;
12105 case INTEL_OUTPUT_UNKNOWN:
12106 if (WARN_ON(!HAS_DDI(dev)))
12107 break;
12108 case INTEL_OUTPUT_DISPLAYPORT:
12109 case INTEL_OUTPUT_HDMI:
12110 case INTEL_OUTPUT_EDP:
12111 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12112
12113 /* the same port mustn't appear more than once */
12114 if (used_ports & port_mask)
12115 return false;
12116
12117 used_ports |= port_mask;
12118 default:
12119 break;
12120 }
12121 }
12122
12123 return true;
12124}
12125
83a57153
ACO		 12126static void
12127clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12128{
12129 struct drm_crtc_state tmp_state;
663a3640 12130 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12131 struct intel_dpll_hw_state dpll_hw_state;
12132 enum intel_dpll_id shared_dpll;
8504c74c 12133 uint32_t ddi_pll_sel;
c4e2d043 12134 bool force_thru;
83a57153 12135
7546a384
ACO		 12136 /* FIXME: before the switch to atomic started, a new pipe_config was
12137 * kzalloc'd. Code that depends on any field being zero should be
12138 * fixed, so that the crtc_state can be safely duplicated. For now,
12139 * only fields that are know to not cause problems are preserved. */
12140
83a57153 12141 tmp_state = crtc_state->base;
663a3640 12142 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12143 shared_dpll = crtc_state->shared_dpll;
12144 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12145 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12146 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12147
83a57153 12148 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12149
83a57153 12150 crtc_state->base = tmp_state;
663a3640 12151 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12152 crtc_state->shared_dpll = shared_dpll;
12153 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12154 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12155 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12156}
12157
548ee15b 12158static int
b8cecdf5 12159intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12160 struct intel_crtc_state *pipe_config)
ee7b9f93 12161{
b359283a 12162 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12163 struct intel_encoder *encoder;
da3ced29 12164 struct drm_connector *connector;
0b901879 12165 struct drm_connector_state *connector_state;
d328c9d7 12166 int base_bpp, ret = -EINVAL;
0b901879 12167 int i;
e29c22c0 12168 bool retry = true;
ee7b9f93 12169
83a57153 12170 clear_intel_crtc_state(pipe_config);
7758a113 12171
e143a21c
DV		 12172 pipe_config->cpu_transcoder =
12173 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12174
2960bc9c
ID		 12175 /*
12176 * Sanitize sync polarity flags based on requested ones. If neither
12177 * positive or negative polarity is requested, treat this as meaning
12178 * negative polarity.
12179 */
2d112de7 12180 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12181 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12182 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12183
2d112de7 12184 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12185 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12186 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12187
d328c9d7
DV		 12188 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12189 pipe_config);
12190 if (base_bpp < 0)
4e53c2e0
DV		 12191 goto fail;
12192
e41a56be
VS		 12193 /*
12194 * Determine the real pipe dimensions. Note that stereo modes can
12195 * increase the actual pipe size due to the frame doubling and
12196 * insertion of additional space for blanks between the frame. This
12197 * is stored in the crtc timings. We use the requested mode to do this
12198 * computation to clearly distinguish it from the adjusted mode, which
12199 * can be changed by the connectors in the below retry loop.
12200 */
2d112de7 12201 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12202 &pipe_config->pipe_src_w,
12203 &pipe_config->pipe_src_h);
e41a56be 12204
e29c22c0 12205encoder_retry:
ef1b460d 12206 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12207 pipe_config->port_clock = 0;
ef1b460d 12208 pipe_config->pixel_multiplier = 1;
ff9a6750 12209
135c81b8 12210 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12211 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12212 CRTC_STEREO_DOUBLE);
135c81b8 12213
7758a113
DV		 12214 /* Pass our mode to the connectors and the CRTC to give them a chance to
12215 * adjust it according to limitations or connector properties, and also
12216 * a chance to reject the mode entirely.
47f1c6c9 12217 */
da3ced29 12218 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12219 if (connector_state->crtc != crtc)
7758a113 12220 continue;
7ae89233 12221
0b901879
ACO		 12222 encoder = to_intel_encoder(connector_state->best_encoder);
12223
efea6e8e
DV		 12224 if (!(encoder->compute_config(encoder, pipe_config))) {
12225 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12226 goto fail;
12227 }
ee7b9f93 12228 }
47f1c6c9 12229
ff9a6750
DV		 12230 /* Set default port clock if not overwritten by the encoder. Needs to be
12231 * done afterwards in case the encoder adjusts the mode. */
12232 if (!pipe_config->port_clock)
2d112de7 12233 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12234 * pipe_config->pixel_multiplier;
ff9a6750 12235
a43f6e0f 12236 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12237 if (ret < 0) {
7758a113
DV		 12238 DRM_DEBUG_KMS("CRTC fixup failed\n");
12239 goto fail;
ee7b9f93 12240 }
e29c22c0
DV		 12241
12242 if (ret == RETRY) {
12243 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12244 ret = -EINVAL;
12245 goto fail;
12246 }
12247
12248 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12249 retry = false;
12250 goto encoder_retry;
12251 }
12252
e8fa4270
DV		 12253 /* Dithering seems to not pass-through bits correctly when it should, so
12254 * only enable it on 6bpc panels. */
12255 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12256 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12257 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12258
7758a113 12259fail:
548ee15b 12260 return ret;
ee7b9f93 12261}
47f1c6c9 12262
ea9d758d 12263static void
4740b0f2 12264intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12265{
0a9ab303
ACO		 12266 struct drm_crtc *crtc;
12267 struct drm_crtc_state *crtc_state;
8a75d157 12268 int i;
ea9d758d 12269
7668851f 12270 /* Double check state. */
8a75d157 12271 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12272 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12273
12274 /* Update hwmode for vblank functions */
12275 if (crtc->state->active)
12276 crtc->hwmode = crtc->state->adjusted_mode;
12277 else
12278 crtc->hwmode.crtc_clock = 0;
ea9d758d 12279 }
ea9d758d
DV		 12280}
12281
3bd26263 12282static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12283{
3bd26263 12284 int diff;
f1f644dc
JB		 12285
12286 if (clock1 == clock2)
12287 return true;
12288
12289 if (!clock1 || !clock2)
12290 return false;
12291
12292 diff = abs(clock1 - clock2);
12293
12294 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12295 return true;
12296
12297 return false;
12298}
12299
25c5b266
DV		 12300#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12301 list_for_each_entry((intel_crtc), \
12302 &(dev)->mode_config.crtc_list, \
12303 base.head) \
0973f18f 12304 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12305
cfb23ed6
ML		 12306static bool
12307intel_compare_m_n(unsigned int m, unsigned int n,
12308 unsigned int m2, unsigned int n2,
12309 bool exact)
12310{
12311 if (m == m2 && n == n2)
12312 return true;
12313
12314 if (exact || !m || !n || !m2 || !n2)
12315 return false;
12316
12317 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12318
12319 if (m > m2) {
12320 while (m > m2) {
12321 m2 <<= 1;
12322 n2 <<= 1;
12323 }
12324 } else if (m < m2) {
12325 while (m < m2) {
12326 m <<= 1;
12327 n <<= 1;
12328 }
12329 }
12330
12331 return m == m2 && n == n2;
12332}
12333
12334static bool
12335intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12336 struct intel_link_m_n *m2_n2,
12337 bool adjust)
12338{
12339 if (m_n->tu == m2_n2->tu &&
12340 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12341 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12342 intel_compare_m_n(m_n->link_m, m_n->link_n,
12343 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12344 if (adjust)
12345 *m2_n2 = *m_n;
12346
12347 return true;
12348 }
12349
12350 return false;
12351}
12352
0e8ffe1b 12353static bool
2fa2fe9a 12354intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12355 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12356 struct intel_crtc_state *pipe_config,
12357 bool adjust)
0e8ffe1b 12358{
cfb23ed6
ML		 12359 bool ret = true;
12360
12361#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12362 do { \
12363 if (!adjust) \
12364 DRM_ERROR(fmt, ##__VA_ARGS__); \
12365 else \
12366 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12367 } while (0)
12368
66e985c0
DV		 12369#define PIPE_CONF_CHECK_X(name) \
12370 if (current_config->name != pipe_config->name) { \
cfb23ed6 12371 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12372 "(expected 0x%08x, found 0x%08x)\n", \
12373 current_config->name, \
12374 pipe_config->name); \
cfb23ed6 12375 ret = false; \
66e985c0
DV		 12376 }
12377
08a24034
DV		 12378#define PIPE_CONF_CHECK_I(name) \
12379 if (current_config->name != pipe_config->name) { \
cfb23ed6 12380 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12381 "(expected %i, found %i)\n", \
12382 current_config->name, \
12383 pipe_config->name); \
cfb23ed6
ML		 12384 ret = false; \
12385 }
12386
12387#define PIPE_CONF_CHECK_M_N(name) \
12388 if (!intel_compare_link_m_n(&current_config->name, \
12389 &pipe_config->name,\
12390 adjust)) { \
12391 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12392 "(expected tu %i gmch %i/%i link %i/%i, " \
12393 "found tu %i, gmch %i/%i link %i/%i)\n", \
12394 current_config->name.tu, \
12395 current_config->name.gmch_m, \
12396 current_config->name.gmch_n, \
12397 current_config->name.link_m, \
12398 current_config->name.link_n, \
12399 pipe_config->name.tu, \
12400 pipe_config->name.gmch_m, \
12401 pipe_config->name.gmch_n, \
12402 pipe_config->name.link_m, \
12403 pipe_config->name.link_n); \
12404 ret = false; \
12405 }
12406
12407#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12408 if (!intel_compare_link_m_n(&current_config->name, \
12409 &pipe_config->name, adjust) && \
12410 !intel_compare_link_m_n(&current_config->alt_name, \
12411 &pipe_config->name, adjust)) { \
12412 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12413 "(expected tu %i gmch %i/%i link %i/%i, " \
12414 "or tu %i gmch %i/%i link %i/%i, " \
12415 "found tu %i, gmch %i/%i link %i/%i)\n", \
12416 current_config->name.tu, \
12417 current_config->name.gmch_m, \
12418 current_config->name.gmch_n, \
12419 current_config->name.link_m, \
12420 current_config->name.link_n, \
12421 current_config->alt_name.tu, \
12422 current_config->alt_name.gmch_m, \
12423 current_config->alt_name.gmch_n, \
12424 current_config->alt_name.link_m, \
12425 current_config->alt_name.link_n, \
12426 pipe_config->name.tu, \
12427 pipe_config->name.gmch_m, \
12428 pipe_config->name.gmch_n, \
12429 pipe_config->name.link_m, \
12430 pipe_config->name.link_n); \
12431 ret = false; \
88adfff1
DV		 12432 }
12433
b95af8be
VK		 12434/* This is required for BDW+ where there is only one set of registers for
12435 * switching between high and low RR.
12436 * This macro can be used whenever a comparison has to be made between one
12437 * hw state and multiple sw state variables.
12438 */
12439#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12440 if ((current_config->name != pipe_config->name) && \
12441 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12442 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12443 "(expected %i or %i, found %i)\n", \
12444 current_config->name, \
12445 current_config->alt_name, \
12446 pipe_config->name); \
cfb23ed6 12447 ret = false; \
b95af8be
VK		 12448 }
12449
1bd1bd80
DV		 12450#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12451 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12452 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12453 "(expected %i, found %i)\n", \
12454 current_config->name & (mask), \
12455 pipe_config->name & (mask)); \
cfb23ed6 12456 ret = false; \
1bd1bd80
DV		 12457 }
12458
5e550656
VS		 12459#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12460 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12461 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12462 "(expected %i, found %i)\n", \
12463 current_config->name, \
12464 pipe_config->name); \
cfb23ed6 12465 ret = false; \
5e550656
VS		 12466 }
12467
bb760063
DV		 12468#define PIPE_CONF_QUIRK(quirk) \
12469 ((current_config->quirks | pipe_config->quirks) & (quirk))
12470
eccb140b
DV		 12471 PIPE_CONF_CHECK_I(cpu_transcoder);
12472
08a24034
DV		 12473 PIPE_CONF_CHECK_I(has_pch_encoder);
12474 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12475 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12476
eb14cb74 12477 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12478 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12479
12480 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12481 PIPE_CONF_CHECK_M_N(dp_m_n);
12482
12483 PIPE_CONF_CHECK_I(has_drrs);
12484 if (current_config->has_drrs)
12485 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12486 } else
12487 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12488
2d112de7
ACO		 12489 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12495
2d112de7
ACO		 12496 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12497 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12498 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12499 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12500 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12501 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12502
c93f54cf 12503 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12504 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12505 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12506 IS_VALLEYVIEW(dev))
12507 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12508 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12509
9ed109a7
DV		 12510 PIPE_CONF_CHECK_I(has_audio);
12511
2d112de7 12512 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12513 DRM_MODE_FLAG_INTERLACE);
12514
bb760063 12515 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12517 DRM_MODE_FLAG_PHSYNC);
2d112de7 12518 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12519 DRM_MODE_FLAG_NHSYNC);
2d112de7 12520 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12521 DRM_MODE_FLAG_PVSYNC);
2d112de7 12522 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12523 DRM_MODE_FLAG_NVSYNC);
12524 }
045ac3b5 12525
333b8ca8 12526 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12527 /* pfit ratios are autocomputed by the hw on gen4+ */
12528 if (INTEL_INFO(dev)->gen < 4)
12529 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12530 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12531
bfd16b2a
ML		 12532 if (!adjust) {
12533 PIPE_CONF_CHECK_I(pipe_src_w);
12534 PIPE_CONF_CHECK_I(pipe_src_h);
12535
12536 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12537 if (current_config->pch_pfit.enabled) {
12538 PIPE_CONF_CHECK_X(pch_pfit.pos);
12539 PIPE_CONF_CHECK_X(pch_pfit.size);
12540 }
2fa2fe9a 12541
7aefe2b5
ML		 12542 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12543 }
a1b2278e 12544
e59150dc
JB		 12545 /* BDW+ don't expose a synchronous way to read the state */
12546 if (IS_HASWELL(dev))
12547 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12548
282740f7
VS		 12549 PIPE_CONF_CHECK_I(double_wide);
12550
26804afd
DV		 12551 PIPE_CONF_CHECK_X(ddi_pll_sel);
12552
c0d43d62 12553 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12554 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12555 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12556 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12557 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12558 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12559 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12560 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12561 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12562
42571aef
VS		 12563 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12564 PIPE_CONF_CHECK_I(pipe_bpp);
12565
2d112de7 12566 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12567 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12568
66e985c0 12569#undef PIPE_CONF_CHECK_X
08a24034 12570#undef PIPE_CONF_CHECK_I
b95af8be 12571#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12572#undef PIPE_CONF_CHECK_FLAGS
5e550656 12573#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12574#undef PIPE_CONF_QUIRK
cfb23ed6 12575#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12576
cfb23ed6 12577 return ret;
0e8ffe1b
DV		 12578}
12579
08db6652
DL		 12580static void check_wm_state(struct drm_device *dev)
12581{
12582 struct drm_i915_private *dev_priv = dev->dev_private;
12583 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12584 struct intel_crtc *intel_crtc;
12585 int plane;
12586
12587 if (INTEL_INFO(dev)->gen < 9)
12588 return;
12589
12590 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12591 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12592
12593 for_each_intel_crtc(dev, intel_crtc) {
12594 struct skl_ddb_entry *hw_entry, *sw_entry;
12595 const enum pipe pipe = intel_crtc->pipe;
12596
12597 if (!intel_crtc->active)
12598 continue;
12599
12600 /* planes */
dd740780 12601 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12602 hw_entry = &hw_ddb.plane[pipe][plane];
12603 sw_entry = &sw_ddb->plane[pipe][plane];
12604
12605 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12606 continue;
12607
12608 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12609 "(expected (%u,%u), found (%u,%u))\n",
12610 pipe_name(pipe), plane + 1,
12611 sw_entry->start, sw_entry->end,
12612 hw_entry->start, hw_entry->end);
12613 }
12614
12615 /* cursor */
4969d33e
MR		 12616 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12617 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12618
12619 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12620 continue;
12621
12622 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12623 "(expected (%u,%u), found (%u,%u))\n",
12624 pipe_name(pipe),
12625 sw_entry->start, sw_entry->end,
12626 hw_entry->start, hw_entry->end);
12627 }
12628}
12629
91d1b4bd 12630static void
35dd3c64
ML		 12631check_connector_state(struct drm_device *dev,
12632 struct drm_atomic_state *old_state)
8af6cf88 12633{
35dd3c64
ML		 12634 struct drm_connector_state *old_conn_state;
12635 struct drm_connector *connector;
12636 int i;
8af6cf88 12637
35dd3c64
ML		 12638 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12639 struct drm_encoder *encoder = connector->encoder;
12640 struct drm_connector_state *state = connector->state;
ad3c558f 12641
8af6cf88
DV		 12642 /* This also checks the encoder/connector hw state with the
12643 * ->get_hw_state callbacks. */
35dd3c64 12644 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12645
ad3c558f 12646 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12647 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12648 }
91d1b4bd
DV		 12649}
12650
12651static void
12652check_encoder_state(struct drm_device *dev)
12653{
12654 struct intel_encoder *encoder;
12655 struct intel_connector *connector;
8af6cf88 12656
b2784e15 12657 for_each_intel_encoder(dev, encoder) {
8af6cf88 12658 bool enabled = false;
4d20cd86 12659 enum pipe pipe;
8af6cf88
DV		 12660
12661 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12662 encoder->base.base.id,
8e329a03 12663 encoder->base.name);
8af6cf88 12664
3a3371ff 12665 for_each_intel_connector(dev, connector) {
4d20cd86 12666 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12667 continue;
12668 enabled = true;
ad3c558f
ML		 12669
12670 I915_STATE_WARN(connector->base.state->crtc !=
12671 encoder->base.crtc,
12672 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12673 }
0e32b39c 12674
e2c719b7 12675 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12676 "encoder's enabled state mismatch "
12677 "(expected %i, found %i)\n",
12678 !!encoder->base.crtc, enabled);
7c60d198
ML		 12679
12680 if (!encoder->base.crtc) {
4d20cd86 12681 bool active;
7c60d198 12682
4d20cd86
ML		 12683 active = encoder->get_hw_state(encoder, &pipe);
12684 I915_STATE_WARN(active,
12685 "encoder detached but still enabled on pipe %c.\n",
12686 pipe_name(pipe));
7c60d198 12687 }
8af6cf88 12688 }
91d1b4bd
DV		 12689}
12690
12691static void
4d20cd86 12692check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12693{
fbee40df 12694 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12695 struct intel_encoder *encoder;
4d20cd86
ML		 12696 struct drm_crtc_state *old_crtc_state;
12697 struct drm_crtc *crtc;
12698 int i;
8af6cf88 12699
4d20cd86
ML		 12700 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12702 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12703 bool active;
8af6cf88 12704
bfd16b2a
ML		 12705 if (!needs_modeset(crtc->state) &&
12706 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12707 continue;
045ac3b5 12708
4d20cd86
ML		 12709 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12710 pipe_config = to_intel_crtc_state(old_crtc_state);
12711 memset(pipe_config, 0, sizeof(*pipe_config));
12712 pipe_config->base.crtc = crtc;
12713 pipe_config->base.state = old_state;
8af6cf88 12714
4d20cd86
ML		 12715 DRM_DEBUG_KMS("[CRTC:%d]\n",
12716 crtc->base.id);
8af6cf88 12717
4d20cd86
ML		 12718 active = dev_priv->display.get_pipe_config(intel_crtc,
12719 pipe_config);
d62cf62a 12720
b6b5d049 12721 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12722 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12723 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12724 active = crtc->state->active;
6c49f241 12725
4d20cd86 12726 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12727 "crtc active state doesn't match with hw state "
4d20cd86 12728 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12729
4d20cd86 12730 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12731 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12732 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12733
12734 for_each_encoder_on_crtc(dev, crtc, encoder) {
12735 enum pipe pipe;
12736
12737 active = encoder->get_hw_state(encoder, &pipe);
12738 I915_STATE_WARN(active != crtc->state->active,
12739 "[ENCODER:%i] active %i with crtc active %i\n",
12740 encoder->base.base.id, active, crtc->state->active);
12741
12742 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12743 "Encoder connected to wrong pipe %c\n",
12744 pipe_name(pipe));
12745
12746 if (active)
12747 encoder->get_config(encoder, pipe_config);
12748 }
53d9f4e9 12749
4d20cd86 12750 if (!crtc->state->active)
cfb23ed6
ML		 12751 continue;
12752
4d20cd86
ML		 12753 sw_config = to_intel_crtc_state(crtc->state);
12754 if (!intel_pipe_config_compare(dev, sw_config,
12755 pipe_config, false)) {
e2c719b7 12756 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12757 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12758 "[hw state]");
4d20cd86 12759 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12760 "[sw state]");
12761 }
8af6cf88
DV		 12762 }
12763}
12764
91d1b4bd
DV		 12765static void
12766check_shared_dpll_state(struct drm_device *dev)
12767{
fbee40df 12768 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12769 struct intel_crtc *crtc;
12770 struct intel_dpll_hw_state dpll_hw_state;
12771 int i;
5358901f
DV		 12772
12773 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12774 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12775 int enabled_crtcs = 0, active_crtcs = 0;
12776 bool active;
12777
12778 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12779
12780 DRM_DEBUG_KMS("%s\n", pll->name);
12781
12782 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12783
e2c719b7 12784 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12785 "more active pll users than references: %i vs %i\n",
3e369b76 12786 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12787 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12788 "pll in active use but not on in sw tracking\n");
e2c719b7 12789 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12790 "pll in on but not on in use in sw tracking\n");
e2c719b7 12791 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12792 "pll on state mismatch (expected %i, found %i)\n",
12793 pll->on, active);
12794
d3fcc808 12795 for_each_intel_crtc(dev, crtc) {
83d65738 12796 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12797 enabled_crtcs++;
12798 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12799 active_crtcs++;
12800 }
e2c719b7 12801 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12802 "pll active crtcs mismatch (expected %i, found %i)\n",
12803 pll->active, active_crtcs);
e2c719b7 12804 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12805 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12806 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12807
e2c719b7 12808 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12809 sizeof(dpll_hw_state)),
12810 "pll hw state mismatch\n");
5358901f 12811 }
8af6cf88
DV		 12812}
12813
ee165b1a
ML		 12814static void
12815intel_modeset_check_state(struct drm_device *dev,
12816 struct drm_atomic_state *old_state)
91d1b4bd 12817{
08db6652 12818 check_wm_state(dev);
35dd3c64 12819 check_connector_state(dev, old_state);
91d1b4bd 12820 check_encoder_state(dev);
4d20cd86 12821 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12822 check_shared_dpll_state(dev);
12823}
12824
5cec258b 12825void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12826 int dotclock)
12827{
12828 /*
12829 * FDI already provided one idea for the dotclock.
12830 * Yell if the encoder disagrees.
12831 */
2d112de7 12832 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12833 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12834 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12835}
12836
80715b2f
VS		 12837static void update_scanline_offset(struct intel_crtc *crtc)
12838{
12839 struct drm_device *dev = crtc->base.dev;
12840
12841 /*
12842 * The scanline counter increments at the leading edge of hsync.
12843 *
12844 * On most platforms it starts counting from vtotal-1 on the
12845 * first active line. That means the scanline counter value is
12846 * always one less than what we would expect. Ie. just after
12847 * start of vblank, which also occurs at start of hsync (on the
12848 * last active line), the scanline counter will read vblank_start-1.
12849 *
12850 * On gen2 the scanline counter starts counting from 1 instead
12851 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12852 * to keep the value positive), instead of adding one.
12853 *
12854 * On HSW+ the behaviour of the scanline counter depends on the output
12855 * type. For DP ports it behaves like most other platforms, but on HDMI
12856 * there's an extra 1 line difference. So we need to add two instead of
12857 * one to the value.
12858 */
12859 if (IS_GEN2(dev)) {
124abe07 12860 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12861 int vtotal;
12862
124abe07
VS		 12863 vtotal = adjusted_mode->crtc_vtotal;
12864 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12865 vtotal /= 2;
12866
12867 crtc->scanline_offset = vtotal - 1;
12868 } else if (HAS_DDI(dev) &&
409ee761 12869 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12870 crtc->scanline_offset = 2;
12871 } else
12872 crtc->scanline_offset = 1;
12873}
12874
ad421372 12875static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12876{
225da59b 12877 struct drm_device *dev = state->dev;
ed6739ef 12878 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12879 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12880 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12881 struct intel_crtc_state *intel_crtc_state;
12882 struct drm_crtc *crtc;
12883 struct drm_crtc_state *crtc_state;
0a9ab303 12884 int i;
ed6739ef
ACO		 12885
12886 if (!dev_priv->display.crtc_compute_clock)
ad421372 12887 return;
ed6739ef 12888
0a9ab303 12889 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12890 int dpll;
12891
0a9ab303 12892 intel_crtc = to_intel_crtc(crtc);
4978cc93 12893 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12894 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12895
ad421372 12896 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12897 continue;
12898
ad421372 12899 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12900
ad421372
ML		 12901 if (!shared_dpll)
12902 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12903
ad421372
ML		 12904 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12905 }
ed6739ef
ACO		 12906}
12907
99d736a2
ML		 12908/*
12909 * This implements the workaround described in the "notes" section of the mode
12910 * set sequence documentation. When going from no pipes or single pipe to
12911 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12912 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12913 */
12914static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12915{
12916 struct drm_crtc_state *crtc_state;
12917 struct intel_crtc *intel_crtc;
12918 struct drm_crtc *crtc;
12919 struct intel_crtc_state *first_crtc_state = NULL;
12920 struct intel_crtc_state *other_crtc_state = NULL;
12921 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12922 int i;
12923
12924 /* look at all crtc's that are going to be enabled in during modeset */
12925 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12926 intel_crtc = to_intel_crtc(crtc);
12927
12928 if (!crtc_state->active || !needs_modeset(crtc_state))
12929 continue;
12930
12931 if (first_crtc_state) {
12932 other_crtc_state = to_intel_crtc_state(crtc_state);
12933 break;
12934 } else {
12935 first_crtc_state = to_intel_crtc_state(crtc_state);
12936 first_pipe = intel_crtc->pipe;
12937 }
12938 }
12939
12940 /* No workaround needed? */
12941 if (!first_crtc_state)
12942 return 0;
12943
12944 /* w/a possibly needed, check how many crtc's are already enabled. */
12945 for_each_intel_crtc(state->dev, intel_crtc) {
12946 struct intel_crtc_state *pipe_config;
12947
12948 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12949 if (IS_ERR(pipe_config))
12950 return PTR_ERR(pipe_config);
12951
12952 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12953
12954 if (!pipe_config->base.active ||
12955 needs_modeset(&pipe_config->base))
12956 continue;
12957
12958 /* 2 or more enabled crtcs means no need for w/a */
12959 if (enabled_pipe != INVALID_PIPE)
12960 return 0;
12961
12962 enabled_pipe = intel_crtc->pipe;
12963 }
12964
12965 if (enabled_pipe != INVALID_PIPE)
12966 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12967 else if (other_crtc_state)
12968 other_crtc_state->hsw_workaround_pipe = first_pipe;
12969
12970 return 0;
12971}
12972
27c329ed
ML		 12973static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12974{
12975 struct drm_crtc *crtc;
12976 struct drm_crtc_state *crtc_state;
12977 int ret = 0;
12978
12979 /* add all active pipes to the state */
12980 for_each_crtc(state->dev, crtc) {
12981 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12982 if (IS_ERR(crtc_state))
12983 return PTR_ERR(crtc_state);
12984
12985 if (!crtc_state->active || needs_modeset(crtc_state))
12986 continue;
12987
12988 crtc_state->mode_changed = true;
12989
12990 ret = drm_atomic_add_affected_connectors(state, crtc);
12991 if (ret)
12992 break;
12993
12994 ret = drm_atomic_add_affected_planes(state, crtc);
12995 if (ret)
12996 break;
12997 }
12998
12999 return ret;
13000}
13001
c347a676 13002static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13003{
13004 struct drm_device *dev = state->dev;
27c329ed 13005 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13006 int ret;
13007
b359283a
ML		 13008 if (!check_digital_port_conflicts(state)) {
13009 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13010 return -EINVAL;
13011 }
13012
054518dd
ACO		 13013 /*
13014 * See if the config requires any additional preparation, e.g.
13015 * to adjust global state with pipes off. We need to do this
13016 * here so we can get the modeset_pipe updated config for the new
13017 * mode set on this crtc. For other crtcs we need to use the
13018 * adjusted_mode bits in the crtc directly.
13019 */
27c329ed
ML		 13020 if (dev_priv->display.modeset_calc_cdclk) {
13021 unsigned int cdclk;
b432e5cf 13022
27c329ed
ML		 13023 ret = dev_priv->display.modeset_calc_cdclk(state);
13024
13025 cdclk = to_intel_atomic_state(state)->cdclk;
13026 if (!ret && cdclk != dev_priv->cdclk_freq)
13027 ret = intel_modeset_all_pipes(state);
13028
13029 if (ret < 0)
054518dd 13030 return ret;
27c329ed
ML		 13031 } else
13032 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13033
ad421372 13034 intel_modeset_clear_plls(state);
054518dd 13035
99d736a2 13036 if (IS_HASWELL(dev))
ad421372 13037 return haswell_mode_set_planes_workaround(state);
99d736a2 13038
ad421372 13039 return 0;
c347a676
ACO		 13040}
13041
76305b1a
MR		 13042/*
13043 * Handle calculation of various watermark data at the end of the atomic check
13044 * phase. The code here should be run after the per-crtc and per-plane 'check'
13045 * handlers to ensure that all derived state has been updated.
13046 */
13047static void calc_watermark_data(struct drm_atomic_state *state)
13048{
13049 struct drm_device *dev = state->dev;
13050 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13051 struct drm_crtc *crtc;
13052 struct drm_crtc_state *cstate;
13053 struct drm_plane *plane;
13054 struct drm_plane_state *pstate;
13055
13056 /*
13057 * Calculate watermark configuration details now that derived
13058 * plane/crtc state is all properly updated.
13059 */
13060 drm_for_each_crtc(crtc, dev) {
13061 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13062 crtc->state;
13063
13064 if (cstate->active)
13065 intel_state->wm_config.num_pipes_active++;
13066 }
13067 drm_for_each_legacy_plane(plane, dev) {
13068 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13069 plane->state;
13070
13071 if (!to_intel_plane_state(pstate)->visible)
13072 continue;
13073
13074 intel_state->wm_config.sprites_enabled = true;
13075 if (pstate->crtc_w != pstate->src_w >> 16 ||
13076 pstate->crtc_h != pstate->src_h >> 16)
13077 intel_state->wm_config.sprites_scaled = true;
13078 }
13079}
13080
74c090b1
ML		 13081/**
13082 * intel_atomic_check - validate state object
13083 * @dev: drm device
13084 * @state: state to validate
13085 */
13086static int intel_atomic_check(struct drm_device *dev,
13087 struct drm_atomic_state *state)
c347a676 13088{
76305b1a 13089 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13090 struct drm_crtc *crtc;
13091 struct drm_crtc_state *crtc_state;
13092 int ret, i;
61333b60 13093 bool any_ms = false;
c347a676 13094
74c090b1 13095 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13096 if (ret)
13097 return ret;
13098
c347a676 13099 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13100 struct intel_crtc_state *pipe_config =
13101 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13102
13103 /* Catch I915_MODE_FLAG_INHERITED */
13104 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13105 crtc_state->mode_changed = true;
cfb23ed6 13106
61333b60
ML		 13107 if (!crtc_state->enable) {
13108 if (needs_modeset(crtc_state))
13109 any_ms = true;
c347a676 13110 continue;
61333b60 13111 }
c347a676 13112
26495481 13113 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13114 continue;
13115
26495481
DV		 13116 /* FIXME: For only active_changed we shouldn't need to do any
13117 * state recomputation at all. */
13118
1ed51de9
DV		 13119 ret = drm_atomic_add_affected_connectors(state, crtc);
13120 if (ret)
13121 return ret;
b359283a 13122
cfb23ed6 13123 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13124 if (ret)
13125 return ret;
13126
6764e9f8 13127 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13128 to_intel_crtc_state(crtc->state),
1ed51de9 13129 pipe_config, true)) {
26495481 13130 crtc_state->mode_changed = false;
bfd16b2a 13131 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13132 }
13133
13134 if (needs_modeset(crtc_state)) {
13135 any_ms = true;
cfb23ed6
ML		 13136
13137 ret = drm_atomic_add_affected_planes(state, crtc);
13138 if (ret)
13139 return ret;
13140 }
61333b60 13141
26495481
DV		 13142 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13143 needs_modeset(crtc_state) ?
13144 "[modeset]" : "[fastset]");
c347a676
ACO		 13145 }
13146
61333b60
ML		 13147 if (any_ms) {
13148 ret = intel_modeset_checks(state);
13149
13150 if (ret)
13151 return ret;
27c329ed 13152 } else
76305b1a 13153 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
c347a676 13154
76305b1a
MR		 13155 ret = drm_atomic_helper_check_planes(state->dev, state);
13156 if (ret)
13157 return ret;
13158
13159 calc_watermark_data(state);
13160
13161 return 0;
054518dd
ACO		 13162}
13163
74c090b1
ML		 13164/**
13165 * intel_atomic_commit - commit validated state object
13166 * @dev: DRM device
13167 * @state: the top-level driver state object
13168 * @async: asynchronous commit
13169 *
13170 * This function commits a top-level state object that has been validated
13171 * with drm_atomic_helper_check().
13172 *
13173 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13174 * we can only handle plane-related operations and do not yet support
13175 * asynchronous commit.
13176 *
13177 * RETURNS
13178 * Zero for success or -errno.
13179 */
13180static int intel_atomic_commit(struct drm_device *dev,
13181 struct drm_atomic_state *state,
13182 bool async)
a6778b3c 13183{
fbee40df 13184 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13185 struct drm_crtc *crtc;
13186 struct drm_crtc_state *crtc_state;
c0c36b94 13187 int ret = 0;
0a9ab303 13188 int i;
61333b60 13189 bool any_ms = false;
a6778b3c 13190
74c090b1
ML		 13191 if (async) {
13192 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13193 return -EINVAL;
13194 }
13195
d4afb8cc
ACO		 13196 ret = drm_atomic_helper_prepare_planes(dev, state);
13197 if (ret)
13198 return ret;
13199
1c5e19f8 13200 drm_atomic_helper_swap_state(dev, state);
76305b1a 13201 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13202
0a9ab303 13203 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13205
61333b60
ML		 13206 if (!needs_modeset(crtc->state))
13207 continue;
13208
13209 any_ms = true;
a539205a 13210 intel_pre_plane_update(intel_crtc);
460da916 13211
a539205a
ML		 13212 if (crtc_state->active) {
13213 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13214 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13215 intel_crtc->active = false;
13216 intel_disable_shared_dpll(intel_crtc);
a539205a 13217 }
b8cecdf5 13218 }
7758a113 13219
ea9d758d
DV		 13220 /* Only after disabling all output pipelines that will be changed can we
13221 * update the the output configuration. */
4740b0f2 13222 intel_modeset_update_crtc_state(state);
f6e5b160 13223
4740b0f2
ML		 13224 if (any_ms) {
13225 intel_shared_dpll_commit(state);
13226
13227 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13228 modeset_update_crtc_power_domains(state);
4740b0f2 13229 }
47fab737 13230
a6778b3c 13231 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13232 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13234 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13235 bool update_pipe = !modeset &&
13236 to_intel_crtc_state(crtc->state)->update_pipe;
13237 unsigned long put_domains = 0;
f6ac4b2a
ML		 13238
13239 if (modeset && crtc->state->active) {
a539205a
ML		 13240 update_scanline_offset(to_intel_crtc(crtc));
13241 dev_priv->display.crtc_enable(crtc);
13242 }
80715b2f 13243
bfd16b2a
ML		 13244 if (update_pipe) {
13245 put_domains = modeset_get_crtc_power_domains(crtc);
13246
13247 /* make sure intel_modeset_check_state runs */
13248 any_ms = true;
13249 }
13250
f6ac4b2a
ML		 13251 if (!modeset)
13252 intel_pre_plane_update(intel_crtc);
13253
a539205a 13254 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13255
13256 if (put_domains)
13257 modeset_put_power_domains(dev_priv, put_domains);
13258
f6ac4b2a 13259 intel_post_plane_update(intel_crtc);
80715b2f 13260 }
a6778b3c 13261
a6778b3c 13262 /* FIXME: add subpixel order */
83a57153 13263
74c090b1 13264 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13265 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13266
74c090b1 13267 if (any_ms)
ee165b1a
ML		 13268 intel_modeset_check_state(dev, state);
13269
13270 drm_atomic_state_free(state);
f30da187 13271
74c090b1 13272 return 0;
7f27126e
JB		 13273}
13274
c0c36b94
CW		 13275void intel_crtc_restore_mode(struct drm_crtc *crtc)
13276{
83a57153
ACO		 13277 struct drm_device *dev = crtc->dev;
13278 struct drm_atomic_state *state;
e694eb02 13279 struct drm_crtc_state *crtc_state;
2bfb4627 13280 int ret;
83a57153
ACO		 13281
13282 state = drm_atomic_state_alloc(dev);
13283 if (!state) {
e694eb02 13284 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13285 crtc->base.id);
13286 return;
13287 }
13288
e694eb02 13289 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13290
e694eb02
ML		 13291retry:
13292 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13293 ret = PTR_ERR_OR_ZERO(crtc_state);
13294 if (!ret) {
13295 if (!crtc_state->active)
13296 goto out;
83a57153 13297
e694eb02 13298 crtc_state->mode_changed = true;
74c090b1 13299 ret = drm_atomic_commit(state);
83a57153
ACO		 13300 }
13301
e694eb02
ML		 13302 if (ret == -EDEADLK) {
13303 drm_atomic_state_clear(state);
13304 drm_modeset_backoff(state->acquire_ctx);
13305 goto retry;
4ed9fb37 13306 }
4be07317 13307
2bfb4627 13308 if (ret)
e694eb02 13309out:
2bfb4627 13310 drm_atomic_state_free(state);
c0c36b94
CW		 13311}
13312
25c5b266
DV		 13313#undef for_each_intel_crtc_masked
13314
f6e5b160 13315static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13316 .gamma_set = intel_crtc_gamma_set,
74c090b1 13317 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13318 .destroy = intel_crtc_destroy,
13319 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13320 .atomic_duplicate_state = intel_crtc_duplicate_state,
13321 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13322};
13323
5358901f
DV		 13324static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13325 struct intel_shared_dpll *pll,
13326 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13327{
5358901f 13328 uint32_t val;
ee7b9f93 13329
f458ebbc 13330 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13331 return false;
13332
5358901f 13333 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13334 hw_state->dpll = val;
13335 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13336 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13337
13338 return val & DPLL_VCO_ENABLE;
13339}
13340
15bdd4cf
DV		 13341static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13342 struct intel_shared_dpll *pll)
13343{
3e369b76
ACO		 13344 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13345 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13346}
13347
e7b903d2
DV		 13348static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13349 struct intel_shared_dpll *pll)
13350{
e7b903d2 13351 /* PCH refclock must be enabled first */
89eff4be 13352 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13353
3e369b76 13354 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13355
13356 /* Wait for the clocks to stabilize. */
13357 POSTING_READ(PCH_DPLL(pll->id));
13358 udelay(150);
13359
13360 /* The pixel multiplier can only be updated once the
13361 * DPLL is enabled and the clocks are stable.
13362 *
13363 * So write it again.
13364 */
3e369b76 13365 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13366 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13367 udelay(200);
13368}
13369
13370static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13371 struct intel_shared_dpll *pll)
13372{
13373 struct drm_device *dev = dev_priv->dev;
13374 struct intel_crtc *crtc;
e7b903d2
DV		 13375
13376 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13377 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13378 if (intel_crtc_to_shared_dpll(crtc) == pll)
13379 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13380 }
13381
15bdd4cf
DV		 13382 I915_WRITE(PCH_DPLL(pll->id), 0);
13383 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13384 udelay(200);
13385}
13386
46edb027
DV		 13387static char *ibx_pch_dpll_names[] = {
13388 "PCH DPLL A",
13389 "PCH DPLL B",
13390};
13391
7c74ade1 13392static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13393{
e7b903d2 13394 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13395 int i;
13396
7c74ade1 13397 dev_priv->num_shared_dpll = 2;
ee7b9f93 13398
e72f9fbf 13399 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13400 dev_priv->shared_dplls[i].id = i;
13401 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13402 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13403 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13404 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13405 dev_priv->shared_dplls[i].get_hw_state =
13406 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13407 }
13408}
13409
7c74ade1
DV		 13410static void intel_shared_dpll_init(struct drm_device *dev)
13411{
e7b903d2 13412 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13413
9cd86933
DV		 13414 if (HAS_DDI(dev))
13415 intel_ddi_pll_init(dev);
13416 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13417 ibx_pch_dpll_init(dev);
13418 else
13419 dev_priv->num_shared_dpll = 0;
13420
13421 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13422}
13423
6beb8c23
MR		 13424/**
13425 * intel_prepare_plane_fb - Prepare fb for usage on plane
13426 * @plane: drm plane to prepare for
13427 * @fb: framebuffer to prepare for presentation
13428 *
13429 * Prepares a framebuffer for usage on a display plane. Generally this
13430 * involves pinning the underlying object and updating the frontbuffer tracking
13431 * bits. Some older platforms need special physical address handling for
13432 * cursor planes.
13433 *
13434 * Returns 0 on success, negative error code on failure.
13435 */
13436int
13437intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13438 const struct drm_plane_state *new_state)
465c120c
MR		 13439{
13440 struct drm_device *dev = plane->dev;
844f9111 13441 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13442 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13443 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13444 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13445 int ret = 0;
465c120c 13446
ea2c67bb 13447 if (!obj)
465c120c
MR		 13448 return 0;
13449
6beb8c23 13450 mutex_lock(&dev->struct_mutex);
465c120c 13451
6beb8c23
MR		 13452 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13453 INTEL_INFO(dev)->cursor_needs_physical) {
13454 int align = IS_I830(dev) ? 16 * 1024 : 256;
13455 ret = i915_gem_object_attach_phys(obj, align);
13456 if (ret)
13457 DRM_DEBUG_KMS("failed to attach phys object\n");
13458 } else {
91af127f 13459 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13460 }
465c120c 13461
6beb8c23 13462 if (ret == 0)
a9ff8714 13463 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13464
4c34574f 13465 mutex_unlock(&dev->struct_mutex);
465c120c 13466
6beb8c23
MR		 13467 return ret;
13468}
13469
38f3ce3a
MR		 13470/**
13471 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13472 * @plane: drm plane to clean up for
13473 * @fb: old framebuffer that was on plane
13474 *
13475 * Cleans up a framebuffer that has just been removed from a plane.
13476 */
13477void
13478intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13479 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13480{
13481 struct drm_device *dev = plane->dev;
844f9111 13482 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
38f3ce3a 13483
844f9111 13484 if (!obj)
38f3ce3a
MR		 13485 return;
13486
13487 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13488 !INTEL_INFO(dev)->cursor_needs_physical) {
13489 mutex_lock(&dev->struct_mutex);
844f9111 13490 intel_unpin_fb_obj(old_state->fb, old_state);
38f3ce3a
MR		 13491 mutex_unlock(&dev->struct_mutex);
13492 }
465c120c
MR		 13493}
13494
6156a456
CK		 13495int
13496skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13497{
13498 int max_scale;
13499 struct drm_device *dev;
13500 struct drm_i915_private *dev_priv;
13501 int crtc_clock, cdclk;
13502
13503 if (!intel_crtc || !crtc_state)
13504 return DRM_PLANE_HELPER_NO_SCALING;
13505
13506 dev = intel_crtc->base.dev;
13507 dev_priv = dev->dev_private;
13508 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13509 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13510
13511 if (!crtc_clock || !cdclk)
13512 return DRM_PLANE_HELPER_NO_SCALING;
13513
13514 /*
13515 * skl max scale is lower of:
13516 * close to 3 but not 3, -1 is for that purpose
13517 * or
13518 * cdclk/crtc_clock
13519 */
13520 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13521
13522 return max_scale;
13523}
13524
465c120c 13525static int
3c692a41 13526intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13527 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13528 struct intel_plane_state *state)
13529{
2b875c22
MR		 13530 struct drm_crtc *crtc = state->base.crtc;
13531 struct drm_framebuffer *fb = state->base.fb;
6156a456 13532 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13533 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13534 bool can_position = false;
465c120c 13535
061e4b8d
ML		 13536 /* use scaler when colorkey is not required */
13537 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13538 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13539 min_scale = 1;
13540 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13541 can_position = true;
6156a456 13542 }
d8106366 13543
061e4b8d
ML		 13544 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13545 &state->dst, &state->clip,
da20eabd
ML		 13546 min_scale, max_scale,
13547 can_position, true,
13548 &state->visible);
14af293f
GP		 13549}
13550
13551static void
13552intel_commit_primary_plane(struct drm_plane *plane,
13553 struct intel_plane_state *state)
13554{
2b875c22
MR		 13555 struct drm_crtc *crtc = state->base.crtc;
13556 struct drm_framebuffer *fb = state->base.fb;
13557 struct drm_device *dev = plane->dev;
14af293f 13558 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13559 struct intel_crtc *intel_crtc;
14af293f
GP		 13560 struct drm_rect *src = &state->src;
13561
ea2c67bb
MR		 13562 crtc = crtc ? crtc : plane->crtc;
13563 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13564
13565 plane->fb = fb;
9dc806fc
MR		 13566 crtc->x = src->x1 >> 16;
13567 crtc->y = src->y1 >> 16;
ccc759dc 13568
a539205a 13569 if (!crtc->state->active)
302d19ac 13570 return;
465c120c 13571
d4b08630
ML		 13572 dev_priv->display.update_primary_plane(crtc, fb,
13573 state->src.x1 >> 16,
13574 state->src.y1 >> 16);
465c120c
MR		 13575}
13576
a8ad0d8e
ML		 13577static void
13578intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13579 struct drm_crtc *crtc)
a8ad0d8e
ML		 13580{
13581 struct drm_device *dev = plane->dev;
13582 struct drm_i915_private *dev_priv = dev->dev_private;
13583
a8ad0d8e
ML		 13584 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13585}
13586
613d2b27
ML		 13587static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13588 struct drm_crtc_state *old_crtc_state)
3c692a41 13589{
32b7eeec 13590 struct drm_device *dev = crtc->dev;
3c692a41 13591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13592 struct intel_crtc_state *old_intel_state =
13593 to_intel_crtc_state(old_crtc_state);
13594 bool modeset = needs_modeset(crtc->state);
3c692a41 13595
f015c551 13596 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13597 intel_update_watermarks(crtc);
3c692a41 13598
c34c9ee4 13599 /* Perform vblank evasion around commit operation */
a539205a 13600 if (crtc->state->active)
34e0adbb 13601 intel_pipe_update_start(intel_crtc);
0583236e 13602
bfd16b2a
ML		 13603 if (modeset)
13604 return;
13605
13606 if (to_intel_crtc_state(crtc->state)->update_pipe)
13607 intel_update_pipe_config(intel_crtc, old_intel_state);
13608 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13609 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13610}
13611
613d2b27
ML		 13612static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13613 struct drm_crtc_state *old_crtc_state)
32b7eeec 13614{
32b7eeec 13615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13616
8f539a83 13617 if (crtc->state->active)
34e0adbb 13618 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13619}
13620
cf4c7c12 13621/**
4a3b8769
MR		 13622 * intel_plane_destroy - destroy a plane
13623 * @plane: plane to destroy
cf4c7c12 13624 *
4a3b8769
MR		 13625 * Common destruction function for all types of planes (primary, cursor,
13626 * sprite).
cf4c7c12 13627 */
4a3b8769 13628void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13629{
13630 struct intel_plane *intel_plane = to_intel_plane(plane);
13631 drm_plane_cleanup(plane);
13632 kfree(intel_plane);
13633}
13634
65a3fea0 13635const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13636 .update_plane = drm_atomic_helper_update_plane,
13637 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13638 .destroy = intel_plane_destroy,
c196e1d6 13639 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13640 .atomic_get_property = intel_plane_atomic_get_property,
13641 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13642 .atomic_duplicate_state = intel_plane_duplicate_state,
13643 .atomic_destroy_state = intel_plane_destroy_state,
13644
465c120c
MR		 13645};
13646
13647static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13648 int pipe)
13649{
13650 struct intel_plane *primary;
8e7d688b 13651 struct intel_plane_state *state;
465c120c 13652 const uint32_t *intel_primary_formats;
45e3743a 13653 unsigned int num_formats;
465c120c
MR		 13654
13655 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13656 if (primary == NULL)
13657 return NULL;
13658
8e7d688b
MR		 13659 state = intel_create_plane_state(&primary->base);
13660 if (!state) {
ea2c67bb
MR		 13661 kfree(primary);
13662 return NULL;
13663 }
8e7d688b 13664 primary->base.state = &state->base;
ea2c67bb 13665
465c120c
MR		 13666 primary->can_scale = false;
13667 primary->max_downscale = 1;
6156a456
CK		 13668 if (INTEL_INFO(dev)->gen >= 9) {
13669 primary->can_scale = true;
af99ceda 13670 state->scaler_id = -1;
6156a456 13671 }
465c120c
MR		 13672 primary->pipe = pipe;
13673 primary->plane = pipe;
a9ff8714 13674 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13675 primary->check_plane = intel_check_primary_plane;
13676 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13677 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13678 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13679 primary->plane = !pipe;
13680
6c0fd451
DL		 13681 if (INTEL_INFO(dev)->gen >= 9) {
13682 intel_primary_formats = skl_primary_formats;
13683 num_formats = ARRAY_SIZE(skl_primary_formats);
13684 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13685 intel_primary_formats = i965_primary_formats;
13686 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13687 } else {
13688 intel_primary_formats = i8xx_primary_formats;
13689 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13690 }
13691
13692 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13693 &intel_plane_funcs,
465c120c
MR		 13694 intel_primary_formats, num_formats,
13695 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13696
3b7a5119
SJ		 13697 if (INTEL_INFO(dev)->gen >= 4)
13698 intel_create_rotation_property(dev, primary);
48404c1e 13699
ea2c67bb
MR		 13700 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13701
465c120c
MR		 13702 return &primary->base;
13703}
13704
3b7a5119
SJ		 13705void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13706{
13707 if (!dev->mode_config.rotation_property) {
13708 unsigned long flags = BIT(DRM_ROTATE_0) |
13709 BIT(DRM_ROTATE_180);
13710
13711 if (INTEL_INFO(dev)->gen >= 9)
13712 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13713
13714 dev->mode_config.rotation_property =
13715 drm_mode_create_rotation_property(dev, flags);
13716 }
13717 if (dev->mode_config.rotation_property)
13718 drm_object_attach_property(&plane->base.base,
13719 dev->mode_config.rotation_property,
13720 plane->base.state->rotation);
13721}
13722
3d7d6510 13723static int
852e787c 13724intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13725 struct intel_crtc_state *crtc_state,
852e787c 13726 struct intel_plane_state *state)
3d7d6510 13727{
061e4b8d 13728 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13729 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13730 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13731 unsigned stride;
13732 int ret;
3d7d6510 13733
061e4b8d
ML		 13734 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13735 &state->dst, &state->clip,
3d7d6510
MR		 13736 DRM_PLANE_HELPER_NO_SCALING,
13737 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13738 true, true, &state->visible);
757f9a3e
GP		 13739 if (ret)
13740 return ret;
13741
757f9a3e
GP		 13742 /* if we want to turn off the cursor ignore width and height */
13743 if (!obj)
da20eabd 13744 return 0;
757f9a3e 13745
757f9a3e 13746 /* Check for which cursor types we support */
061e4b8d 13747 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13748 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13749 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13750 return -EINVAL;
13751 }
13752
ea2c67bb
MR		 13753 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13754 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13755 DRM_DEBUG_KMS("buffer is too small\n");
13756 return -ENOMEM;
13757 }
13758
3a656b54 13759 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13760 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13761 return -EINVAL;
32b7eeec
MR		 13762 }
13763
da20eabd 13764 return 0;
852e787c 13765}
3d7d6510 13766
a8ad0d8e
ML		 13767static void
13768intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13769 struct drm_crtc *crtc)
a8ad0d8e 13770{
a8ad0d8e
ML		 13771 intel_crtc_update_cursor(crtc, false);
13772}
13773
f4a2cf29 13774static void
852e787c
GP		 13775intel_commit_cursor_plane(struct drm_plane *plane,
13776 struct intel_plane_state *state)
13777{
2b875c22 13778 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13779 struct drm_device *dev = plane->dev;
13780 struct intel_crtc *intel_crtc;
2b875c22 13781 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13782 uint32_t addr;
852e787c 13783
ea2c67bb
MR		 13784 crtc = crtc ? crtc : plane->crtc;
13785 intel_crtc = to_intel_crtc(crtc);
13786
a912f12f
GP		 13787 if (intel_crtc->cursor_bo == obj)
13788 goto update;
4ed91096 13789
f4a2cf29 13790 if (!obj)
a912f12f 13791 addr = 0;
f4a2cf29 13792 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13793 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13794 else
a912f12f 13795 addr = obj->phys_handle->busaddr;
852e787c 13796
a912f12f
GP		 13797 intel_crtc->cursor_addr = addr;
13798 intel_crtc->cursor_bo = obj;
852e787c 13799
302d19ac 13800update:
a539205a 13801 if (crtc->state->active)
a912f12f 13802 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13803}
13804
3d7d6510
MR		 13805static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13806 int pipe)
13807{
13808 struct intel_plane *cursor;
8e7d688b 13809 struct intel_plane_state *state;
3d7d6510
MR		 13810
13811 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13812 if (cursor == NULL)
13813 return NULL;
13814
8e7d688b
MR		 13815 state = intel_create_plane_state(&cursor->base);
13816 if (!state) {
ea2c67bb
MR		 13817 kfree(cursor);
13818 return NULL;
13819 }
8e7d688b 13820 cursor->base.state = &state->base;
ea2c67bb 13821
3d7d6510
MR		 13822 cursor->can_scale = false;
13823 cursor->max_downscale = 1;
13824 cursor->pipe = pipe;
13825 cursor->plane = pipe;
a9ff8714 13826 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13827 cursor->check_plane = intel_check_cursor_plane;
13828 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13829 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13830
13831 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13832 &intel_plane_funcs,
3d7d6510
MR		 13833 intel_cursor_formats,
13834 ARRAY_SIZE(intel_cursor_formats),
13835 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13836
13837 if (INTEL_INFO(dev)->gen >= 4) {
13838 if (!dev->mode_config.rotation_property)
13839 dev->mode_config.rotation_property =
13840 drm_mode_create_rotation_property(dev,
13841 BIT(DRM_ROTATE_0) |
13842 BIT(DRM_ROTATE_180));
13843 if (dev->mode_config.rotation_property)
13844 drm_object_attach_property(&cursor->base.base,
13845 dev->mode_config.rotation_property,
8e7d688b 13846 state->base.rotation);
4398ad45
VS		 13847 }
13848
af99ceda
CK		 13849 if (INTEL_INFO(dev)->gen >=9)
13850 state->scaler_id = -1;
13851
ea2c67bb
MR		 13852 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13853
3d7d6510
MR		 13854 return &cursor->base;
13855}
13856
549e2bfb
CK		 13857static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13858 struct intel_crtc_state *crtc_state)
13859{
13860 int i;
13861 struct intel_scaler *intel_scaler;
13862 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13863
13864 for (i = 0; i < intel_crtc->num_scalers; i++) {
13865 intel_scaler = &scaler_state->scalers[i];
13866 intel_scaler->in_use = 0;
549e2bfb
CK		 13867 intel_scaler->mode = PS_SCALER_MODE_DYN;
13868 }
13869
13870 scaler_state->scaler_id = -1;
13871}
13872
b358d0a6 13873static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13874{
fbee40df 13875 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13876 struct intel_crtc *intel_crtc;
f5de6e07 13877 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13878 struct drm_plane *primary = NULL;
13879 struct drm_plane *cursor = NULL;
465c120c 13880 int i, ret;
79e53945 13881
955382f3 13882 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13883 if (intel_crtc == NULL)
13884 return;
13885
f5de6e07
ACO		 13886 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13887 if (!crtc_state)
13888 goto fail;
550acefd
ACO		 13889 intel_crtc->config = crtc_state;
13890 intel_crtc->base.state = &crtc_state->base;
07878248 13891 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13892
549e2bfb
CK		 13893 /* initialize shared scalers */
13894 if (INTEL_INFO(dev)->gen >= 9) {
13895 if (pipe == PIPE_C)
13896 intel_crtc->num_scalers = 1;
13897 else
13898 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13899
13900 skl_init_scalers(dev, intel_crtc, crtc_state);
13901 }
13902
465c120c 13903 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13904 if (!primary)
13905 goto fail;
13906
13907 cursor = intel_cursor_plane_create(dev, pipe);
13908 if (!cursor)
13909 goto fail;
13910
465c120c 13911 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13912 cursor, &intel_crtc_funcs);
13913 if (ret)
13914 goto fail;
79e53945
JB		 13915
13916 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13917 for (i = 0; i < 256; i++) {
13918 intel_crtc->lut_r[i] = i;
13919 intel_crtc->lut_g[i] = i;
13920 intel_crtc->lut_b[i] = i;
13921 }
13922
1f1c2e24
VS		 13923 /*
13924 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13925 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13926 */
80824003
JB		 13927 intel_crtc->pipe = pipe;
13928 intel_crtc->plane = pipe;
3a77c4c4 13929 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13930 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13931 intel_crtc->plane = !pipe;
80824003
JB		 13932 }
13933
4b0e333e
CW		 13934 intel_crtc->cursor_base = ~0;
13935 intel_crtc->cursor_cntl = ~0;
dc41c154 13936 intel_crtc->cursor_size = ~0;
8d7849db 13937
852eb00d
VS		 13938 intel_crtc->wm.cxsr_allowed = true;
13939
22fd0fab
JB		 13940 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13941 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13942 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13943 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13944
79e53945 13945 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13946
13947 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13948 return;
13949
13950fail:
13951 if (primary)
13952 drm_plane_cleanup(primary);
13953 if (cursor)
13954 drm_plane_cleanup(cursor);
f5de6e07 13955 kfree(crtc_state);
3d7d6510 13956 kfree(intel_crtc);
79e53945
JB		 13957}
13958
752aa88a
JB		 13959enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13960{
13961 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13962 struct drm_device *dev = connector->base.dev;
752aa88a 13963
51fd371b 13964 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13965
d3babd3f 13966 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13967 return INVALID_PIPE;
13968
13969 return to_intel_crtc(encoder->crtc)->pipe;
13970}
13971
08d7b3d1 13972int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13973 struct drm_file *file)
08d7b3d1 13974{
08d7b3d1 13975 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13976 struct drm_crtc *drmmode_crtc;
c05422d5 13977 struct intel_crtc *crtc;
08d7b3d1 13978
7707e653 13979 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13980
7707e653 13981 if (!drmmode_crtc) {
08d7b3d1 13982 DRM_ERROR("no such CRTC id\n");
3f2c2057 13983 return -ENOENT;
08d7b3d1
CW		 13984 }
13985
7707e653 13986 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13987 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13988
c05422d5 13989 return 0;
08d7b3d1
CW		 13990}
13991
66a9278e 13992static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13993{
66a9278e
DV		 13994 struct drm_device *dev = encoder->base.dev;
13995 struct intel_encoder *source_encoder;
79e53945 13996 int index_mask = 0;
79e53945
JB		 13997 int entry = 0;
13998
b2784e15 13999 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14000 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14001 index_mask |= (1 << entry);
14002
79e53945
JB		 14003 entry++;
14004 }
4ef69c7a 14005
79e53945
JB		 14006 return index_mask;
14007}
14008
4d302442
CW		 14009static bool has_edp_a(struct drm_device *dev)
14010{
14011 struct drm_i915_private *dev_priv = dev->dev_private;
14012
14013 if (!IS_MOBILE(dev))
14014 return false;
14015
14016 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14017 return false;
14018
e3589908 14019 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14020 return false;
14021
14022 return true;
14023}
14024
84b4e042
JB		 14025static bool intel_crt_present(struct drm_device *dev)
14026{
14027 struct drm_i915_private *dev_priv = dev->dev_private;
14028
884497ed
DL		 14029 if (INTEL_INFO(dev)->gen >= 9)
14030 return false;
14031
cf404ce4 14032 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14033 return false;
14034
14035 if (IS_CHERRYVIEW(dev))
14036 return false;
14037
14038 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14039 return false;
14040
14041 return true;
14042}
14043
79e53945
JB		 14044static void intel_setup_outputs(struct drm_device *dev)
14045{
725e30ad 14046 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14047 struct intel_encoder *encoder;
cb0953d7 14048 bool dpd_is_edp = false;
79e53945 14049
c9093354 14050 intel_lvds_init(dev);
79e53945 14051
84b4e042 14052 if (intel_crt_present(dev))
79935fca 14053 intel_crt_init(dev);
cb0953d7 14054
c776eb2e
VK		 14055 if (IS_BROXTON(dev)) {
14056 /*
14057 * FIXME: Broxton doesn't support port detection via the
14058 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14059 * detect the ports.
14060 */
14061 intel_ddi_init(dev, PORT_A);
14062 intel_ddi_init(dev, PORT_B);
14063 intel_ddi_init(dev, PORT_C);
14064 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14065 int found;
14066
de31facd
JB		 14067 /*
14068 * Haswell uses DDI functions to detect digital outputs.
14069 * On SKL pre-D0 the strap isn't connected, so we assume
14070 * it's there.
14071 */
77179400 14072 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14073 /* WaIgnoreDDIAStrap: skl */
5a2376d1 14074 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 14075 intel_ddi_init(dev, PORT_A);
14076
14077 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14078 * register */
14079 found = I915_READ(SFUSE_STRAP);
14080
14081 if (found & SFUSE_STRAP_DDIB_DETECTED)
14082 intel_ddi_init(dev, PORT_B);
14083 if (found & SFUSE_STRAP_DDIC_DETECTED)
14084 intel_ddi_init(dev, PORT_C);
14085 if (found & SFUSE_STRAP_DDID_DETECTED)
14086 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14087 /*
14088 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14089 */
14090 if (IS_SKYLAKE(dev) &&
14091 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14092 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14093 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14094 intel_ddi_init(dev, PORT_E);
14095
0e72a5b5 14096 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14097 int found;
5d8a7752 14098 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14099
14100 if (has_edp_a(dev))
14101 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14102
dc0fa718 14103 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14104 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14105 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14106 if (!found)
e2debe91 14107 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14108 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14109 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14110 }
14111
dc0fa718 14112 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14113 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14114
dc0fa718 14115 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14116 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14117
5eb08b69 14118 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14119 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14120
270b3042 14121 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14122 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14123 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14124 /*
14125 * The DP_DETECTED bit is the latched state of the DDC
14126 * SDA pin at boot. However since eDP doesn't require DDC
14127 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14128 * eDP ports may have been muxed to an alternate function.
14129 * Thus we can't rely on the DP_DETECTED bit alone to detect
14130 * eDP ports. Consult the VBT as well as DP_DETECTED to
14131 * detect eDP ports.
14132 */
e66eb81d 14133 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14134 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14135 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14136 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14137 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14138 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14139
e66eb81d 14140 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14141 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14142 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14143 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14144 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14145 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14146
9418c1f1 14147 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14148 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14149 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14150 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14151 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14152 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14153 }
14154
3cfca973 14155 intel_dsi_init(dev);
09da55dc 14156 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14157 bool found = false;
7d57382e 14158
e2debe91 14159 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14160 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14161 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14162 if (!found && IS_G4X(dev)) {
b01f2c3a 14163 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14164 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14165 }
27185ae1 14166
3fec3d2f 14167 if (!found && IS_G4X(dev))
ab9d7c30 14168 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14169 }
13520b05
KH		 14170
14171 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14172
e2debe91 14173 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14174 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14175 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14176 }
27185ae1 14177
e2debe91 14178 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14179
3fec3d2f 14180 if (IS_G4X(dev)) {
b01f2c3a 14181 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14182 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14183 }
3fec3d2f 14184 if (IS_G4X(dev))
ab9d7c30 14185 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14186 }
27185ae1 14187
3fec3d2f 14188 if (IS_G4X(dev) &&
e7281eab 14189 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14190 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14191 } else if (IS_GEN2(dev))
79e53945
JB		 14192 intel_dvo_init(dev);
14193
103a196f 14194 if (SUPPORTS_TV(dev))
79e53945
JB		 14195 intel_tv_init(dev);
14196
0bc12bcb 14197 intel_psr_init(dev);
7c8f8a70 14198
b2784e15 14199 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14200 encoder->base.possible_crtcs = encoder->crtc_mask;
14201 encoder->base.possible_clones =
66a9278e 14202 intel_encoder_clones(encoder);
79e53945 14203 }
47356eb6 14204
dde86e2d 14205 intel_init_pch_refclk(dev);
270b3042
DV		 14206
14207 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14208}
14209
14210static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14211{
60a5ca01 14212 struct drm_device *dev = fb->dev;
79e53945 14213 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14214
ef2d633e 14215 drm_framebuffer_cleanup(fb);
60a5ca01 14216 mutex_lock(&dev->struct_mutex);
ef2d633e 14217 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14218 drm_gem_object_unreference(&intel_fb->obj->base);
14219 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14220 kfree(intel_fb);
14221}
14222
14223static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14224 struct drm_file *file,
79e53945
JB		 14225 unsigned int *handle)
14226{
14227 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14228 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14229
05394f39 14230 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14231}
14232
86c98588
RV		 14233static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14234 struct drm_file *file,
14235 unsigned flags, unsigned color,
14236 struct drm_clip_rect *clips,
14237 unsigned num_clips)
14238{
14239 struct drm_device *dev = fb->dev;
14240 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14241 struct drm_i915_gem_object *obj = intel_fb->obj;
14242
14243 mutex_lock(&dev->struct_mutex);
74b4ea1e 14244 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14245 mutex_unlock(&dev->struct_mutex);
14246
14247 return 0;
14248}
14249
79e53945
JB		 14250static const struct drm_framebuffer_funcs intel_fb_funcs = {
14251 .destroy = intel_user_framebuffer_destroy,
14252 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14253 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14254};
14255
b321803d
DL		 14256static
14257u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14258 uint32_t pixel_format)
14259{
14260 u32 gen = INTEL_INFO(dev)->gen;
14261
14262 if (gen >= 9) {
14263 /* "The stride in bytes must not exceed the of the size of 8K
14264 * pixels and 32K bytes."
14265 */
14266 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14267 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14268 return 32*1024;
14269 } else if (gen >= 4) {
14270 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14271 return 16*1024;
14272 else
14273 return 32*1024;
14274 } else if (gen >= 3) {
14275 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14276 return 8*1024;
14277 else
14278 return 16*1024;
14279 } else {
14280 /* XXX DSPC is limited to 4k tiled */
14281 return 8*1024;
14282 }
14283}
14284
b5ea642a
DV		 14285static int intel_framebuffer_init(struct drm_device *dev,
14286 struct intel_framebuffer *intel_fb,
14287 struct drm_mode_fb_cmd2 *mode_cmd,
14288 struct drm_i915_gem_object *obj)
79e53945 14289{
6761dd31 14290 unsigned int aligned_height;
79e53945 14291 int ret;
b321803d 14292 u32 pitch_limit, stride_alignment;
79e53945 14293
dd4916c5
DV		 14294 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14295
2a80eada
DV		 14296 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14297 /* Enforce that fb modifier and tiling mode match, but only for
14298 * X-tiled. This is needed for FBC. */
14299 if (!!(obj->tiling_mode == I915_TILING_X) !=
14300 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14301 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14302 return -EINVAL;
14303 }
14304 } else {
14305 if (obj->tiling_mode == I915_TILING_X)
14306 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14307 else if (obj->tiling_mode == I915_TILING_Y) {
14308 DRM_DEBUG("No Y tiling for legacy addfb\n");
14309 return -EINVAL;
14310 }
14311 }
14312
9a8f0a12
TU		 14313 /* Passed in modifier sanity checking. */
14314 switch (mode_cmd->modifier[0]) {
14315 case I915_FORMAT_MOD_Y_TILED:
14316 case I915_FORMAT_MOD_Yf_TILED:
14317 if (INTEL_INFO(dev)->gen < 9) {
14318 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14319 mode_cmd->modifier[0]);
14320 return -EINVAL;
14321 }
14322 case DRM_FORMAT_MOD_NONE:
14323 case I915_FORMAT_MOD_X_TILED:
14324 break;
14325 default:
c0f40428
JB		 14326 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14327 mode_cmd->modifier[0]);
57cd6508 14328 return -EINVAL;
c16ed4be 14329 }
57cd6508 14330
b321803d
DL		 14331 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14332 mode_cmd->pixel_format);
14333 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14334 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14335 mode_cmd->pitches[0], stride_alignment);
57cd6508 14336 return -EINVAL;
c16ed4be 14337 }
57cd6508 14338
b321803d
DL		 14339 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14340 mode_cmd->pixel_format);
a35cdaa0 14341 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14342 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14343 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14344 "tiled" : "linear",
a35cdaa0 14345 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14346 return -EINVAL;
c16ed4be 14347 }
5d7bd705 14348
2a80eada 14349 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14350 mode_cmd->pitches[0] != obj->stride) {
14351 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14352 mode_cmd->pitches[0], obj->stride);
5d7bd705 14353 return -EINVAL;
c16ed4be 14354 }
5d7bd705 14355
57779d06 14356 /* Reject formats not supported by any plane early. */
308e5bcb 14357 switch (mode_cmd->pixel_format) {
57779d06 14358 case DRM_FORMAT_C8:
04b3924d
VS		 14359 case DRM_FORMAT_RGB565:
14360 case DRM_FORMAT_XRGB8888:
14361 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14362 break;
14363 case DRM_FORMAT_XRGB1555:
c16ed4be 14364 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14365 DRM_DEBUG("unsupported pixel format: %s\n",
14366 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14367 return -EINVAL;
c16ed4be 14368 }
57779d06 14369 break;
57779d06 14370 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14371 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14372 DRM_DEBUG("unsupported pixel format: %s\n",
14373 drm_get_format_name(mode_cmd->pixel_format));
14374 return -EINVAL;
14375 }
14376 break;
14377 case DRM_FORMAT_XBGR8888:
04b3924d 14378 case DRM_FORMAT_XRGB2101010:
57779d06 14379 case DRM_FORMAT_XBGR2101010:
c16ed4be 14380 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14381 DRM_DEBUG("unsupported pixel format: %s\n",
14382 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14383 return -EINVAL;
c16ed4be 14384 }
b5626747 14385 break;
7531208b
DL		 14386 case DRM_FORMAT_ABGR2101010:
14387 if (!IS_VALLEYVIEW(dev)) {
14388 DRM_DEBUG("unsupported pixel format: %s\n",
14389 drm_get_format_name(mode_cmd->pixel_format));
14390 return -EINVAL;
14391 }
14392 break;
04b3924d
VS		 14393 case DRM_FORMAT_YUYV:
14394 case DRM_FORMAT_UYVY:
14395 case DRM_FORMAT_YVYU:
14396 case DRM_FORMAT_VYUY:
c16ed4be 14397 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14398 DRM_DEBUG("unsupported pixel format: %s\n",
14399 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14400 return -EINVAL;
c16ed4be 14401 }
57cd6508
CW		 14402 break;
14403 default:
4ee62c76
VS		 14404 DRM_DEBUG("unsupported pixel format: %s\n",
14405 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14406 return -EINVAL;
14407 }
14408
90f9a336
VS		 14409 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14410 if (mode_cmd->offsets[0] != 0)
14411 return -EINVAL;
14412
ec2c981e 14413 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14414 mode_cmd->pixel_format,
14415 mode_cmd->modifier[0]);
53155c0a
DV		 14416 /* FIXME drm helper for size checks (especially planar formats)? */
14417 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14418 return -EINVAL;
14419
c7d73f6a
DV		 14420 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14421 intel_fb->obj = obj;
80075d49 14422 intel_fb->obj->framebuffer_references++;
c7d73f6a 14423
79e53945
JB		 14424 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14425 if (ret) {
14426 DRM_ERROR("framebuffer init failed %d\n", ret);
14427 return ret;
14428 }
14429
79e53945
JB		 14430 return 0;
14431}
14432
79e53945
JB		 14433static struct drm_framebuffer *
14434intel_user_framebuffer_create(struct drm_device *dev,
14435 struct drm_file *filp,
308e5bcb 14436 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14437{
05394f39 14438 struct drm_i915_gem_object *obj;
79e53945 14439
308e5bcb
JB		 14440 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14441 mode_cmd->handles[0]));
c8725226 14442 if (&obj->base == NULL)
cce13ff7 14443 return ERR_PTR(-ENOENT);
79e53945 14444
d2dff872 14445 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14446}
14447
0695726e 14448#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14449static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14450{
14451}
14452#endif
14453
79e53945 14454static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14455 .fb_create = intel_user_framebuffer_create,
0632fef6 14456 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14457 .atomic_check = intel_atomic_check,
14458 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14459 .atomic_state_alloc = intel_atomic_state_alloc,
14460 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14461};
14462
e70236a8
JB		 14463/* Set up chip specific display functions */
14464static void intel_init_display(struct drm_device *dev)
14465{
14466 struct drm_i915_private *dev_priv = dev->dev_private;
14467
ee9300bb
DV		 14468 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14469 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14470 else if (IS_CHERRYVIEW(dev))
14471 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14472 else if (IS_VALLEYVIEW(dev))
14473 dev_priv->display.find_dpll = vlv_find_best_dpll;
14474 else if (IS_PINEVIEW(dev))
14475 dev_priv->display.find_dpll = pnv_find_best_dpll;
14476 else
14477 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14478
bc8d7dff
DL		 14479 if (INTEL_INFO(dev)->gen >= 9) {
14480 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14481 dev_priv->display.get_initial_plane_config =
14482 skylake_get_initial_plane_config;
bc8d7dff
DL		 14483 dev_priv->display.crtc_compute_clock =
14484 haswell_crtc_compute_clock;
14485 dev_priv->display.crtc_enable = haswell_crtc_enable;
14486 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14487 dev_priv->display.update_primary_plane =
14488 skylake_update_primary_plane;
14489 } else if (HAS_DDI(dev)) {
0e8ffe1b 14490 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14491 dev_priv->display.get_initial_plane_config =
14492 ironlake_get_initial_plane_config;
797d0259
ACO		 14493 dev_priv->display.crtc_compute_clock =
14494 haswell_crtc_compute_clock;
4f771f10
PZ		 14495 dev_priv->display.crtc_enable = haswell_crtc_enable;
14496 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14497 dev_priv->display.update_primary_plane =
14498 ironlake_update_primary_plane;
09b4ddf9 14499 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14500 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14501 dev_priv->display.get_initial_plane_config =
14502 ironlake_get_initial_plane_config;
3fb37703
ACO		 14503 dev_priv->display.crtc_compute_clock =
14504 ironlake_crtc_compute_clock;
76e5a89c
DV		 14505 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14506 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14507 dev_priv->display.update_primary_plane =
14508 ironlake_update_primary_plane;
89b667f8
JB		 14509 } else if (IS_VALLEYVIEW(dev)) {
14510 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14511 dev_priv->display.get_initial_plane_config =
14512 i9xx_get_initial_plane_config;
d6dfee7a 14513 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14514 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14515 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14516 dev_priv->display.update_primary_plane =
14517 i9xx_update_primary_plane;
f564048e 14518 } else {
0e8ffe1b 14519 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14520 dev_priv->display.get_initial_plane_config =
14521 i9xx_get_initial_plane_config;
d6dfee7a 14522 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14523 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14524 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14525 dev_priv->display.update_primary_plane =
14526 i9xx_update_primary_plane;
f564048e 14527 }
e70236a8 14528
e70236a8 14529 /* Returns the core display clock speed */
1652d19e
VS		 14530 if (IS_SKYLAKE(dev))
14531 dev_priv->display.get_display_clock_speed =
14532 skylake_get_display_clock_speed;
acd3f3d3
BP		 14533 else if (IS_BROXTON(dev))
14534 dev_priv->display.get_display_clock_speed =
14535 broxton_get_display_clock_speed;
1652d19e
VS		 14536 else if (IS_BROADWELL(dev))
14537 dev_priv->display.get_display_clock_speed =
14538 broadwell_get_display_clock_speed;
14539 else if (IS_HASWELL(dev))
14540 dev_priv->display.get_display_clock_speed =
14541 haswell_get_display_clock_speed;
14542 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14543 dev_priv->display.get_display_clock_speed =
14544 valleyview_get_display_clock_speed;
b37a6434
VS		 14545 else if (IS_GEN5(dev))
14546 dev_priv->display.get_display_clock_speed =
14547 ilk_get_display_clock_speed;
a7c66cd8 14548 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14549 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14550 dev_priv->display.get_display_clock_speed =
14551 i945_get_display_clock_speed;
34edce2f
VS		 14552 else if (IS_GM45(dev))
14553 dev_priv->display.get_display_clock_speed =
14554 gm45_get_display_clock_speed;
14555 else if (IS_CRESTLINE(dev))
14556 dev_priv->display.get_display_clock_speed =
14557 i965gm_get_display_clock_speed;
14558 else if (IS_PINEVIEW(dev))
14559 dev_priv->display.get_display_clock_speed =
14560 pnv_get_display_clock_speed;
14561 else if (IS_G33(dev) || IS_G4X(dev))
14562 dev_priv->display.get_display_clock_speed =
14563 g33_get_display_clock_speed;
e70236a8
JB		 14564 else if (IS_I915G(dev))
14565 dev_priv->display.get_display_clock_speed =
14566 i915_get_display_clock_speed;
257a7ffc 14567 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14568 dev_priv->display.get_display_clock_speed =
14569 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14570 else if (IS_PINEVIEW(dev))
14571 dev_priv->display.get_display_clock_speed =
14572 pnv_get_display_clock_speed;
e70236a8
JB		 14573 else if (IS_I915GM(dev))
14574 dev_priv->display.get_display_clock_speed =
14575 i915gm_get_display_clock_speed;
14576 else if (IS_I865G(dev))
14577 dev_priv->display.get_display_clock_speed =
14578 i865_get_display_clock_speed;
f0f8a9ce 14579 else if (IS_I85X(dev))
e70236a8 14580 dev_priv->display.get_display_clock_speed =
1b1d2716 14581 i85x_get_display_clock_speed;
623e01e5
VS		 14582 else { /* 830 */
14583 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14584 dev_priv->display.get_display_clock_speed =
14585 i830_get_display_clock_speed;
623e01e5 14586 }
e70236a8 14587
7c10a2b5 14588 if (IS_GEN5(dev)) {
3bb11b53 14589 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14590 } else if (IS_GEN6(dev)) {
14591 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14592 } else if (IS_IVYBRIDGE(dev)) {
14593 /* FIXME: detect B0+ stepping and use auto training */
14594 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14595 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14596 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14597 if (IS_BROADWELL(dev)) {
14598 dev_priv->display.modeset_commit_cdclk =
14599 broadwell_modeset_commit_cdclk;
14600 dev_priv->display.modeset_calc_cdclk =
14601 broadwell_modeset_calc_cdclk;
14602 }
30a970c6 14603 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14604 dev_priv->display.modeset_commit_cdclk =
14605 valleyview_modeset_commit_cdclk;
14606 dev_priv->display.modeset_calc_cdclk =
14607 valleyview_modeset_calc_cdclk;
f8437dd1 14608 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14609 dev_priv->display.modeset_commit_cdclk =
14610 broxton_modeset_commit_cdclk;
14611 dev_priv->display.modeset_calc_cdclk =
14612 broxton_modeset_calc_cdclk;
e70236a8 14613 }
8c9f3aaf 14614
8c9f3aaf
JB		 14615 switch (INTEL_INFO(dev)->gen) {
14616 case 2:
14617 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14618 break;
14619
14620 case 3:
14621 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14622 break;
14623
14624 case 4:
14625 case 5:
14626 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14627 break;
14628
14629 case 6:
14630 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14631 break;
7c9017e5 14632 case 7:
4e0bbc31 14633 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14634 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14635 break;
830c81db 14636 case 9:
ba343e02
TU		 14637 /* Drop through - unsupported since execlist only. */
14638 default:
14639 /* Default just returns -ENODEV to indicate unsupported */
14640 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14641 }
7bd688cd 14642
e39b999a 14643 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14644}
14645
b690e96c
JB		 14646/*
14647 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14648 * resume, or other times. This quirk makes sure that's the case for
14649 * affected systems.
14650 */
0206e353 14651static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14652{
14653 struct drm_i915_private *dev_priv = dev->dev_private;
14654
14655 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14656 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14657}
14658
b6b5d049
VS		 14659static void quirk_pipeb_force(struct drm_device *dev)
14660{
14661 struct drm_i915_private *dev_priv = dev->dev_private;
14662
14663 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14664 DRM_INFO("applying pipe b force quirk\n");
14665}
14666
435793df
KP		 14667/*
14668 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14669 */
14670static void quirk_ssc_force_disable(struct drm_device *dev)
14671{
14672 struct drm_i915_private *dev_priv = dev->dev_private;
14673 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14674 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14675}
14676
4dca20ef 14677/*
5a15ab5b
CE		 14678 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14679 * brightness value
4dca20ef
CE		 14680 */
14681static void quirk_invert_brightness(struct drm_device *dev)
14682{
14683 struct drm_i915_private *dev_priv = dev->dev_private;
14684 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14685 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14686}
14687
9c72cc6f
SD		 14688/* Some VBT's incorrectly indicate no backlight is present */
14689static void quirk_backlight_present(struct drm_device *dev)
14690{
14691 struct drm_i915_private *dev_priv = dev->dev_private;
14692 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14693 DRM_INFO("applying backlight present quirk\n");
14694}
14695
b690e96c
JB		 14696struct intel_quirk {
14697 int device;
14698 int subsystem_vendor;
14699 int subsystem_device;
14700 void (*hook)(struct drm_device *dev);
14701};
14702
5f85f176
EE		 14703/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14704struct intel_dmi_quirk {
14705 void (*hook)(struct drm_device *dev);
14706 const struct dmi_system_id (*dmi_id_list)[];
14707};
14708
14709static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14710{
14711 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14712 return 1;
14713}
14714
14715static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14716 {
14717 .dmi_id_list = &(const struct dmi_system_id[]) {
14718 {
14719 .callback = intel_dmi_reverse_brightness,
14720 .ident = "NCR Corporation",
14721 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14722 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14723 },
14724 },
14725 { } /* terminating entry */
14726 },
14727 .hook = quirk_invert_brightness,
14728 },
14729};
14730
c43b5634 14731static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14732 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14733 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14734
b690e96c
JB		 14735 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14736 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14737
5f080c0f
VS		 14738 /* 830 needs to leave pipe A & dpll A up */
14739 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14740
b6b5d049
VS		 14741 /* 830 needs to leave pipe B & dpll B up */
14742 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14743
435793df
KP		 14744 /* Lenovo U160 cannot use SSC on LVDS */
14745 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14746
14747 /* Sony Vaio Y cannot use SSC on LVDS */
14748 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14749
be505f64
AH		 14750 /* Acer Aspire 5734Z must invert backlight brightness */
14751 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14752
14753 /* Acer/eMachines G725 */
14754 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14755
14756 /* Acer/eMachines e725 */
14757 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14758
14759 /* Acer/Packard Bell NCL20 */
14760 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14761
14762 /* Acer Aspire 4736Z */
14763 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14764
14765 /* Acer Aspire 5336 */
14766 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14767
14768 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14769 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14770
dfb3d47b
SD		 14771 /* Acer C720 Chromebook (Core i3 4005U) */
14772 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14773
b2a9601c 14774 /* Apple Macbook 2,1 (Core 2 T7400) */
14775 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14776
d4967d8c
SD		 14777 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14778 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14779
14780 /* HP Chromebook 14 (Celeron 2955U) */
14781 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14782
14783 /* Dell Chromebook 11 */
14784 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14785};
14786
14787static void intel_init_quirks(struct drm_device *dev)
14788{
14789 struct pci_dev *d = dev->pdev;
14790 int i;
14791
14792 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14793 struct intel_quirk *q = &intel_quirks[i];
14794
14795 if (d->device == q->device &&
14796 (d->subsystem_vendor == q->subsystem_vendor ||
14797 q->subsystem_vendor == PCI_ANY_ID) &&
14798 (d->subsystem_device == q->subsystem_device ||
14799 q->subsystem_device == PCI_ANY_ID))
14800 q->hook(dev);
14801 }
5f85f176
EE		 14802 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14803 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14804 intel_dmi_quirks[i].hook(dev);
14805 }
b690e96c
JB		 14806}
14807
9cce37f4
JB		 14808/* Disable the VGA plane that we never use */
14809static void i915_disable_vga(struct drm_device *dev)
14810{
14811 struct drm_i915_private *dev_priv = dev->dev_private;
14812 u8 sr1;
766aa1c4 14813 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14814
2b37c616 14815 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14816 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14817 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14818 sr1 = inb(VGA_SR_DATA);
14819 outb(sr1 | 1<<5, VGA_SR_DATA);
14820 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14821 udelay(300);
14822
01f5a626 14823 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14824 POSTING_READ(vga_reg);
14825}
14826
f817586c
DV		 14827void intel_modeset_init_hw(struct drm_device *dev)
14828{
b6283055 14829 intel_update_cdclk(dev);
a8f78b58 14830 intel_prepare_ddi(dev);
f817586c 14831 intel_init_clock_gating(dev);
8090c6b9 14832 intel_enable_gt_powersave(dev);
f817586c
DV		 14833}
14834
79e53945
JB		 14835void intel_modeset_init(struct drm_device *dev)
14836{
652c393a 14837 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14838 int sprite, ret;
8cc87b75 14839 enum pipe pipe;
46f297fb 14840 struct intel_crtc *crtc;
79e53945
JB		 14841
14842 drm_mode_config_init(dev);
14843
14844 dev->mode_config.min_width = 0;
14845 dev->mode_config.min_height = 0;
14846
019d96cb
DA		 14847 dev->mode_config.preferred_depth = 24;
14848 dev->mode_config.prefer_shadow = 1;
14849
25bab385
TU		 14850 dev->mode_config.allow_fb_modifiers = true;
14851
e6ecefaa 14852 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14853
b690e96c
JB		 14854 intel_init_quirks(dev);
14855
1fa61106
ED		 14856 intel_init_pm(dev);
14857
e3c74757
BW		 14858 if (INTEL_INFO(dev)->num_pipes == 0)
14859 return;
14860
69f92f67
LW		 14861 /*
14862 * There may be no VBT; and if the BIOS enabled SSC we can
14863 * just keep using it to avoid unnecessary flicker. Whereas if the
14864 * BIOS isn't using it, don't assume it will work even if the VBT
14865 * indicates as much.
14866 */
14867 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14868 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14869 DREF_SSC1_ENABLE);
14870
14871 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14872 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14873 bios_lvds_use_ssc ? "en" : "dis",
14874 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14875 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14876 }
14877 }
14878
e70236a8 14879 intel_init_display(dev);
7c10a2b5 14880 intel_init_audio(dev);
e70236a8 14881
a6c45cf0
CW		 14882 if (IS_GEN2(dev)) {
14883 dev->mode_config.max_width = 2048;
14884 dev->mode_config.max_height = 2048;
14885 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14886 dev->mode_config.max_width = 4096;
14887 dev->mode_config.max_height = 4096;
79e53945 14888 } else {
a6c45cf0
CW		 14889 dev->mode_config.max_width = 8192;
14890 dev->mode_config.max_height = 8192;
79e53945 14891 }
068be561 14892
dc41c154
VS		 14893 if (IS_845G(dev) || IS_I865G(dev)) {
14894 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14895 dev->mode_config.cursor_height = 1023;
14896 } else if (IS_GEN2(dev)) {
068be561
DL		 14897 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14898 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14899 } else {
14900 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14901 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14902 }
14903
5d4545ae 14904 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14905
28c97730 14906 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14907 INTEL_INFO(dev)->num_pipes,
14908 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14909
055e393f 14910 for_each_pipe(dev_priv, pipe) {
8cc87b75 14911 intel_crtc_init(dev, pipe);
3bdcfc0c 14912 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14913 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14914 if (ret)
06da8da2 14915 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14916 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14917 }
79e53945
JB		 14918 }
14919
bfa7df01
VS		 14920 intel_update_czclk(dev_priv);
14921 intel_update_cdclk(dev);
14922
e72f9fbf 14923 intel_shared_dpll_init(dev);
ee7b9f93 14924
9cce37f4
JB		 14925 /* Just disable it once at startup */
14926 i915_disable_vga(dev);
79e53945 14927 intel_setup_outputs(dev);
11be49eb
CW		 14928
14929 /* Just in case the BIOS is doing something questionable. */
7733b49b 14930 intel_fbc_disable(dev_priv);
fa9fa083 14931
6e9f798d 14932 drm_modeset_lock_all(dev);
043e9bda 14933 intel_modeset_setup_hw_state(dev);
6e9f798d 14934 drm_modeset_unlock_all(dev);
46f297fb 14935
d3fcc808 14936 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14937 struct intel_initial_plane_config plane_config = {};
14938
46f297fb
JB		 14939 if (!crtc->active)
14940 continue;
14941
46f297fb 14942 /*
46f297fb
JB		 14943 * Note that reserving the BIOS fb up front prevents us
14944 * from stuffing other stolen allocations like the ring
14945 * on top. This prevents some ugliness at boot time, and
14946 * can even allow for smooth boot transitions if the BIOS
14947 * fb is large enough for the active pipe configuration.
14948 */
eeebeac5
ML		 14949 dev_priv->display.get_initial_plane_config(crtc,
14950 &plane_config);
14951
14952 /*
14953 * If the fb is shared between multiple heads, we'll
14954 * just get the first one.
14955 */
14956 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14957 }
2c7111db
CW		 14958}
14959
7fad798e
DV		 14960static void intel_enable_pipe_a(struct drm_device *dev)
14961{
14962 struct intel_connector *connector;
14963 struct drm_connector *crt = NULL;
14964 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14965 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14966
14967 /* We can't just switch on the pipe A, we need to set things up with a
14968 * proper mode and output configuration. As a gross hack, enable pipe A
14969 * by enabling the load detect pipe once. */
3a3371ff 14970 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14971 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14972 crt = &connector->base;
14973 break;
14974 }
14975 }
14976
14977 if (!crt)
14978 return;
14979
208bf9fd 14980 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14981 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14982}
14983
fa555837
DV		 14984static bool
14985intel_check_plane_mapping(struct intel_crtc *crtc)
14986{
7eb552ae
BW		 14987 struct drm_device *dev = crtc->base.dev;
14988 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14989 u32 reg, val;
14990
7eb552ae 14991 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14992 return true;
14993
14994 reg = DSPCNTR(!crtc->plane);
14995 val = I915_READ(reg);
14996
14997 if ((val & DISPLAY_PLANE_ENABLE) &&
14998 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14999 return false;
15000
15001 return true;
15002}
15003
02e93c35
VS		 15004static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15005{
15006 struct drm_device *dev = crtc->base.dev;
15007 struct intel_encoder *encoder;
15008
15009 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15010 return true;
15011
15012 return false;
15013}
15014
24929352
DV		 15015static void intel_sanitize_crtc(struct intel_crtc *crtc)
15016{
15017 struct drm_device *dev = crtc->base.dev;
15018 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15019 u32 reg;
24929352 15020
24929352 15021 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15022 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15023 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15024
d3eaf884 15025 /* restore vblank interrupts to correct state */
9625604c 15026 drm_crtc_vblank_reset(&crtc->base);
d297e103 15027 if (crtc->active) {
f9cd7b88
VS		 15028 struct intel_plane *plane;
15029
9625604c 15030 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15031
15032 /* Disable everything but the primary plane */
15033 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15034 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15035 continue;
15036
15037 plane->disable_plane(&plane->base, &crtc->base);
15038 }
9625604c 15039 }
d3eaf884 15040
24929352 15041 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15042 * disable the crtc (and hence change the state) if it is wrong. Note
15043 * that gen4+ has a fixed plane -> pipe mapping. */
15044 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15045 bool plane;
15046
24929352
DV		 15047 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15048 crtc->base.base.id);
15049
15050 /* Pipe has the wrong plane attached and the plane is active.
15051 * Temporarily change the plane mapping and disable everything
15052 * ... */
15053 plane = crtc->plane;
b70709a6 15054 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15055 crtc->plane = !plane;
b17d48e2 15056 intel_crtc_disable_noatomic(&crtc->base);
24929352 15057 crtc->plane = plane;
24929352 15058 }
24929352 15059
7fad798e
DV		 15060 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15061 crtc->pipe == PIPE_A && !crtc->active) {
15062 /* BIOS forgot to enable pipe A, this mostly happens after
15063 * resume. Force-enable the pipe to fix this, the update_dpms
15064 * call below we restore the pipe to the right state, but leave
15065 * the required bits on. */
15066 intel_enable_pipe_a(dev);
15067 }
15068
24929352
DV		 15069 /* Adjust the state of the output pipe according to whether we
15070 * have active connectors/encoders. */
02e93c35 15071 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15072 intel_crtc_disable_noatomic(&crtc->base);
24929352 15073
53d9f4e9 15074 if (crtc->active != crtc->base.state->active) {
02e93c35 15075 struct intel_encoder *encoder;
24929352
DV		 15076
15077 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15078 * functions or because of calls to intel_crtc_disable_noatomic,
15079 * or because the pipe is force-enabled due to the
24929352
DV		 15080 * pipe A quirk. */
15081 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15082 crtc->base.base.id,
83d65738 15083 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15084 crtc->active ? "enabled" : "disabled");
15085
4be40c98 15086 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15087 crtc->base.state->active = crtc->active;
24929352
DV		 15088 crtc->base.enabled = crtc->active;
15089
15090 /* Because we only establish the connector -> encoder ->
15091 * crtc links if something is active, this means the
15092 * crtc is now deactivated. Break the links. connector
15093 * -> encoder links are only establish when things are
15094 * actually up, hence no need to break them. */
15095 WARN_ON(crtc->active);
15096
2d406bb0 15097 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15098 encoder->base.crtc = NULL;
24929352 15099 }
c5ab3bc0 15100
a3ed6aad 15101 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15102 /*
15103 * We start out with underrun reporting disabled to avoid races.
15104 * For correct bookkeeping mark this on active crtcs.
15105 *
c5ab3bc0
DV		 15106 * Also on gmch platforms we dont have any hardware bits to
15107 * disable the underrun reporting. Which means we need to start
15108 * out with underrun reporting disabled also on inactive pipes,
15109 * since otherwise we'll complain about the garbage we read when
15110 * e.g. coming up after runtime pm.
15111 *
4cc31489
DV		 15112 * No protection against concurrent access is required - at
15113 * worst a fifo underrun happens which also sets this to false.
15114 */
15115 crtc->cpu_fifo_underrun_disabled = true;
15116 crtc->pch_fifo_underrun_disabled = true;
15117 }
24929352
DV		 15118}
15119
15120static void intel_sanitize_encoder(struct intel_encoder *encoder)
15121{
15122 struct intel_connector *connector;
15123 struct drm_device *dev = encoder->base.dev;
873ffe69 15124 bool active = false;
24929352
DV		 15125
15126 /* We need to check both for a crtc link (meaning that the
15127 * encoder is active and trying to read from a pipe) and the
15128 * pipe itself being active. */
15129 bool has_active_crtc = encoder->base.crtc &&
15130 to_intel_crtc(encoder->base.crtc)->active;
15131
873ffe69
ML		 15132 for_each_intel_connector(dev, connector) {
15133 if (connector->base.encoder != &encoder->base)
15134 continue;
15135
15136 active = true;
15137 break;
15138 }
15139
15140 if (active && !has_active_crtc) {
24929352
DV		 15141 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15142 encoder->base.base.id,
8e329a03 15143 encoder->base.name);
24929352
DV		 15144
15145 /* Connector is active, but has no active pipe. This is
15146 * fallout from our resume register restoring. Disable
15147 * the encoder manually again. */
15148 if (encoder->base.crtc) {
15149 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15150 encoder->base.base.id,
8e329a03 15151 encoder->base.name);
24929352 15152 encoder->disable(encoder);
a62d1497
VS		 15153 if (encoder->post_disable)
15154 encoder->post_disable(encoder);
24929352 15155 }
7f1950fb 15156 encoder->base.crtc = NULL;
24929352
DV		 15157
15158 /* Inconsistent output/port/pipe state happens presumably due to
15159 * a bug in one of the get_hw_state functions. Or someplace else
15160 * in our code, like the register restore mess on resume. Clamp
15161 * things to off as a safer default. */
3a3371ff 15162 for_each_intel_connector(dev, connector) {
24929352
DV		 15163 if (connector->encoder != encoder)
15164 continue;
7f1950fb
EE		 15165 connector->base.dpms = DRM_MODE_DPMS_OFF;
15166 connector->base.encoder = NULL;
24929352
DV		 15167 }
15168 }
15169 /* Enabled encoders without active connectors will be fixed in
15170 * the crtc fixup. */
15171}
15172
04098753 15173void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15174{
15175 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15176 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15177
04098753
ID		 15178 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15179 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15180 i915_disable_vga(dev);
15181 }
15182}
15183
15184void i915_redisable_vga(struct drm_device *dev)
15185{
15186 struct drm_i915_private *dev_priv = dev->dev_private;
15187
8dc8a27c
PZ		 15188 /* This function can be called both from intel_modeset_setup_hw_state or
15189 * at a very early point in our resume sequence, where the power well
15190 * structures are not yet restored. Since this function is at a very
15191 * paranoid "someone might have enabled VGA while we were not looking"
15192 * level, just check if the power well is enabled instead of trying to
15193 * follow the "don't touch the power well if we don't need it" policy
15194 * the rest of the driver uses. */
f458ebbc 15195 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15196 return;
15197
04098753 15198 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15199}
15200
f9cd7b88 15201static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15202{
f9cd7b88 15203 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15204
f9cd7b88 15205 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15206}
15207
f9cd7b88
VS		 15208/* FIXME read out full plane state for all planes */
15209static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15210{
b26d3ea3 15211 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15212 struct intel_plane_state *plane_state =
b26d3ea3 15213 to_intel_plane_state(primary->state);
d032ffa0 15214
a4611e44 15215 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15216 primary_get_hw_state(to_intel_plane(primary));
15217
15218 if (plane_state->visible)
15219 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15220}
15221
30e984df 15222static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15223{
15224 struct drm_i915_private *dev_priv = dev->dev_private;
15225 enum pipe pipe;
24929352
DV		 15226 struct intel_crtc *crtc;
15227 struct intel_encoder *encoder;
15228 struct intel_connector *connector;
5358901f 15229 int i;
24929352 15230
d3fcc808 15231 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15232 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15233 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15234 crtc->config->base.crtc = &crtc->base;
3b117c8f 15235
0e8ffe1b 15236 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15237 crtc->config);
24929352 15238
49d6fa21 15239 crtc->base.state->active = crtc->active;
24929352 15240 crtc->base.enabled = crtc->active;
b70709a6 15241
f9cd7b88 15242 readout_plane_state(crtc);
24929352
DV		 15243
15244 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15245 crtc->base.base.id,
15246 crtc->active ? "enabled" : "disabled");
15247 }
15248
5358901f
DV		 15249 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15250 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15251
3e369b76
ACO		 15252 pll->on = pll->get_hw_state(dev_priv, pll,
15253 &pll->config.hw_state);
5358901f 15254 pll->active = 0;
3e369b76 15255 pll->config.crtc_mask = 0;
d3fcc808 15256 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15257 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15258 pll->active++;
3e369b76 15259 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15260 }
5358901f 15261 }
5358901f 15262
1e6f2ddc 15263 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15264 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15265
3e369b76 15266 if (pll->config.crtc_mask)
bd2bb1b9 15267 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15268 }
15269
b2784e15 15270 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15271 pipe = 0;
15272
15273 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15275 encoder->base.crtc = &crtc->base;
6e3c9717 15276 encoder->get_config(encoder, crtc->config);
24929352
DV		 15277 } else {
15278 encoder->base.crtc = NULL;
15279 }
15280
6f2bcceb 15281 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15282 encoder->base.base.id,
8e329a03 15283 encoder->base.name,
24929352 15284 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15285 pipe_name(pipe));
24929352
DV		 15286 }
15287
3a3371ff 15288 for_each_intel_connector(dev, connector) {
24929352
DV		 15289 if (connector->get_hw_state(connector)) {
15290 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15291 connector->base.encoder = &connector->encoder->base;
15292 } else {
15293 connector->base.dpms = DRM_MODE_DPMS_OFF;
15294 connector->base.encoder = NULL;
15295 }
15296 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15297 connector->base.base.id,
c23cc417 15298 connector->base.name,
24929352
DV		 15299 connector->base.encoder ? "enabled" : "disabled");
15300 }
7f4c6284
VS		 15301
15302 for_each_intel_crtc(dev, crtc) {
15303 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15304
15305 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15306 if (crtc->base.state->active) {
15307 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15308 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15309 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15310
15311 /*
15312 * The initial mode needs to be set in order to keep
15313 * the atomic core happy. It wants a valid mode if the
15314 * crtc's enabled, so we do the above call.
15315 *
15316 * At this point some state updated by the connectors
15317 * in their ->detect() callback has not run yet, so
15318 * no recalculation can be done yet.
15319 *
15320 * Even if we could do a recalculation and modeset
15321 * right now it would cause a double modeset if
15322 * fbdev or userspace chooses a different initial mode.
15323 *
15324 * If that happens, someone indicated they wanted a
15325 * mode change, which means it's safe to do a full
15326 * recalculation.
15327 */
15328 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15329
15330 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15331 update_scanline_offset(crtc);
7f4c6284
VS		 15332 }
15333 }
30e984df
DV		 15334}
15335
043e9bda
ML		 15336/* Scan out the current hw modeset state,
15337 * and sanitizes it to the current state
15338 */
15339static void
15340intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15341{
15342 struct drm_i915_private *dev_priv = dev->dev_private;
15343 enum pipe pipe;
30e984df
DV		 15344 struct intel_crtc *crtc;
15345 struct intel_encoder *encoder;
35c95375 15346 int i;
30e984df
DV		 15347
15348 intel_modeset_readout_hw_state(dev);
24929352
DV		 15349
15350 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15351 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15352 intel_sanitize_encoder(encoder);
15353 }
15354
055e393f 15355 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15356 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15357 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15358 intel_dump_pipe_config(crtc, crtc->config,
15359 "[setup_hw_state]");
24929352 15360 }
9a935856 15361
d29b2f9d
ACO		 15362 intel_modeset_update_connector_atomic_state(dev);
15363
35c95375
DV		 15364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15365 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15366
15367 if (!pll->on || pll->active)
15368 continue;
15369
15370 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15371
15372 pll->disable(dev_priv, pll);
15373 pll->on = false;
15374 }
15375
26e1fe4f 15376 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15377 vlv_wm_get_hw_state(dev);
15378 else if (IS_GEN9(dev))
3078999f
PB		 15379 skl_wm_get_hw_state(dev);
15380 else if (HAS_PCH_SPLIT(dev))
243e6a44 15381 ilk_wm_get_hw_state(dev);
292b990e
ML		 15382
15383 for_each_intel_crtc(dev, crtc) {
15384 unsigned long put_domains;
15385
15386 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15387 if (WARN_ON(put_domains))
15388 modeset_put_power_domains(dev_priv, put_domains);
15389 }
15390 intel_display_set_init_power(dev_priv, false);
043e9bda 15391}
7d0bc1ea 15392
043e9bda
ML		 15393void intel_display_resume(struct drm_device *dev)
15394{
15395 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15396 struct intel_connector *conn;
15397 struct intel_plane *plane;
15398 struct drm_crtc *crtc;
15399 int ret;
f30da187 15400
043e9bda
ML		 15401 if (!state)
15402 return;
15403
15404 state->acquire_ctx = dev->mode_config.acquire_ctx;
15405
15406 /* preserve complete old state, including dpll */
15407 intel_atomic_get_shared_dpll_state(state);
15408
15409 for_each_crtc(dev, crtc) {
15410 struct drm_crtc_state *crtc_state =
15411 drm_atomic_get_crtc_state(state, crtc);
15412
15413 ret = PTR_ERR_OR_ZERO(crtc_state);
15414 if (ret)
15415 goto err;
15416
15417 /* force a restore */
15418 crtc_state->mode_changed = true;
45e2b5f6 15419 }
8af6cf88 15420
043e9bda
ML		 15421 for_each_intel_plane(dev, plane) {
15422 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15423 if (ret)
15424 goto err;
15425 }
15426
15427 for_each_intel_connector(dev, conn) {
15428 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15429 if (ret)
15430 goto err;
15431 }
15432
15433 intel_modeset_setup_hw_state(dev);
15434
15435 i915_redisable_vga(dev);
74c090b1 15436 ret = drm_atomic_commit(state);
043e9bda
ML		 15437 if (!ret)
15438 return;
15439
15440err:
15441 DRM_ERROR("Restoring old state failed with %i\n", ret);
15442 drm_atomic_state_free(state);
2c7111db
CW		 15443}
15444
15445void intel_modeset_gem_init(struct drm_device *dev)
15446{
484b41dd 15447 struct drm_crtc *c;
2ff8fde1 15448 struct drm_i915_gem_object *obj;
e0d6149b 15449 int ret;
484b41dd 15450
ae48434c
ID		 15451 mutex_lock(&dev->struct_mutex);
15452 intel_init_gt_powersave(dev);
15453 mutex_unlock(&dev->struct_mutex);
15454
1833b134 15455 intel_modeset_init_hw(dev);
02e792fb
DV		 15456
15457 intel_setup_overlay(dev);
484b41dd
JB		 15458
15459 /*
15460 * Make sure any fbs we allocated at startup are properly
15461 * pinned & fenced. When we do the allocation it's too early
15462 * for this.
15463 */
70e1e0ec 15464 for_each_crtc(dev, c) {
2ff8fde1
MR		 15465 obj = intel_fb_obj(c->primary->fb);
15466 if (obj == NULL)
484b41dd
JB		 15467 continue;
15468
e0d6149b
TU		 15469 mutex_lock(&dev->struct_mutex);
15470 ret = intel_pin_and_fence_fb_obj(c->primary,
15471 c->primary->fb,
15472 c->primary->state,
91af127f 15473 NULL, NULL);
e0d6149b
TU		 15474 mutex_unlock(&dev->struct_mutex);
15475 if (ret) {
484b41dd
JB		 15476 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15477 to_intel_crtc(c)->pipe);
66e514c1
DA		 15478 drm_framebuffer_unreference(c->primary->fb);
15479 c->primary->fb = NULL;
36750f28 15480 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15481 update_state_fb(c->primary);
36750f28 15482 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15483 }
15484 }
0962c3c9
VS		 15485
15486 intel_backlight_register(dev);
79e53945
JB		 15487}
15488
4932e2c3
ID		 15489void intel_connector_unregister(struct intel_connector *intel_connector)
15490{
15491 struct drm_connector *connector = &intel_connector->base;
15492
15493 intel_panel_destroy_backlight(connector);
34ea3d38 15494 drm_connector_unregister(connector);
4932e2c3
ID		 15495}
15496
79e53945
JB		 15497void intel_modeset_cleanup(struct drm_device *dev)
15498{
652c393a 15499 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15500 struct drm_connector *connector;
652c393a 15501
2eb5252e
ID		 15502 intel_disable_gt_powersave(dev);
15503
0962c3c9
VS		 15504 intel_backlight_unregister(dev);
15505
fd0c0642
DV		 15506 /*
15507 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15508 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15509 * experience fancy races otherwise.
15510 */
2aeb7d3a 15511 intel_irq_uninstall(dev_priv);
eb21b92b 15512
fd0c0642
DV		 15513 /*
15514 * Due to the hpd irq storm handling the hotplug work can re-arm the
15515 * poll handlers. Hence disable polling after hpd handling is shut down.
15516 */
f87ea761 15517 drm_kms_helper_poll_fini(dev);
fd0c0642 15518
723bfd70
JB		 15519 intel_unregister_dsm_handler();
15520
7733b49b 15521 intel_fbc_disable(dev_priv);
69341a5e 15522
1630fe75
CW		 15523 /* flush any delayed tasks or pending work */
15524 flush_scheduled_work();
15525
db31af1d
JN		 15526 /* destroy the backlight and sysfs files before encoders/connectors */
15527 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15528 struct intel_connector *intel_connector;
15529
15530 intel_connector = to_intel_connector(connector);
15531 intel_connector->unregister(intel_connector);
db31af1d 15532 }
d9255d57 15533
79e53945 15534 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15535
15536 intel_cleanup_overlay(dev);
ae48434c
ID		 15537
15538 mutex_lock(&dev->struct_mutex);
15539 intel_cleanup_gt_powersave(dev);
15540 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15541}
15542
f1c79df3
ZW		 15543/*
15544 * Return which encoder is currently attached for connector.
15545 */
df0e9248 15546struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15547{
df0e9248
CW		 15548 return &intel_attached_encoder(connector)->base;
15549}
f1c79df3 15550
df0e9248
CW		 15551void intel_connector_attach_encoder(struct intel_connector *connector,
15552 struct intel_encoder *encoder)
15553{
15554 connector->encoder = encoder;
15555 drm_mode_connector_attach_encoder(&connector->base,
15556 &encoder->base);
79e53945 15557}
28d52043
DA		 15558
15559/*
15560 * set vga decode state - true == enable VGA decode
15561 */
15562int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15563{
15564 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15565 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15566 u16 gmch_ctrl;
15567
75fa041d
CW		 15568 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15569 DRM_ERROR("failed to read control word\n");
15570 return -EIO;
15571 }
15572
c0cc8a55
CW		 15573 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15574 return 0;
15575
28d52043
DA		 15576 if (state)
15577 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15578 else
15579 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15580
15581 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15582 DRM_ERROR("failed to write control word\n");
15583 return -EIO;
15584 }
15585
28d52043
DA		 15586 return 0;
15587}
c4a1d9e4 15588
c4a1d9e4 15589struct intel_display_error_state {
ff57f1b0
PZ		 15590
15591 u32 power_well_driver;
15592
63b66e5b
CW		 15593 int num_transcoders;
15594
c4a1d9e4
CW		 15595 struct intel_cursor_error_state {
15596 u32 control;
15597 u32 position;
15598 u32 base;
15599 u32 size;
52331309 15600 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15601
15602 struct intel_pipe_error_state {
ddf9c536 15603 bool power_domain_on;
c4a1d9e4 15604 u32 source;
f301b1e1 15605 u32 stat;
52331309 15606 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15607
15608 struct intel_plane_error_state {
15609 u32 control;
15610 u32 stride;
15611 u32 size;
15612 u32 pos;
15613 u32 addr;
15614 u32 surface;
15615 u32 tile_offset;
52331309 15616 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15617
15618 struct intel_transcoder_error_state {
ddf9c536 15619 bool power_domain_on;
63b66e5b
CW		 15620 enum transcoder cpu_transcoder;
15621
15622 u32 conf;
15623
15624 u32 htotal;
15625 u32 hblank;
15626 u32 hsync;
15627 u32 vtotal;
15628 u32 vblank;
15629 u32 vsync;
15630 } transcoder[4];
c4a1d9e4
CW		 15631};
15632
15633struct intel_display_error_state *
15634intel_display_capture_error_state(struct drm_device *dev)
15635{
fbee40df 15636 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15637 struct intel_display_error_state *error;
63b66e5b
CW		 15638 int transcoders[] = {
15639 TRANSCODER_A,
15640 TRANSCODER_B,
15641 TRANSCODER_C,
15642 TRANSCODER_EDP,
15643 };
c4a1d9e4
CW		 15644 int i;
15645
63b66e5b
CW		 15646 if (INTEL_INFO(dev)->num_pipes == 0)
15647 return NULL;
15648
9d1cb914 15649 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15650 if (error == NULL)
15651 return NULL;
15652
190be112 15653 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15654 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15655
055e393f 15656 for_each_pipe(dev_priv, i) {
ddf9c536 15657 error->pipe[i].power_domain_on =
f458ebbc
DV		 15658 __intel_display_power_is_enabled(dev_priv,
15659 POWER_DOMAIN_PIPE(i));
ddf9c536 15660 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15661 continue;
15662
5efb3e28
VS		 15663 error->cursor[i].control = I915_READ(CURCNTR(i));
15664 error->cursor[i].position = I915_READ(CURPOS(i));
15665 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15666
15667 error->plane[i].control = I915_READ(DSPCNTR(i));
15668 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15669 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15670 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15671 error->plane[i].pos = I915_READ(DSPPOS(i));
15672 }
ca291363
PZ		 15673 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15674 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15675 if (INTEL_INFO(dev)->gen >= 4) {
15676 error->plane[i].surface = I915_READ(DSPSURF(i));
15677 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15678 }
15679
c4a1d9e4 15680 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15681
3abfce77 15682 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15683 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15684 }
15685
15686 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15687 if (HAS_DDI(dev_priv->dev))
15688 error->num_transcoders++; /* Account for eDP. */
15689
15690 for (i = 0; i < error->num_transcoders; i++) {
15691 enum transcoder cpu_transcoder = transcoders[i];
15692
ddf9c536 15693 error->transcoder[i].power_domain_on =
f458ebbc 15694 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15695 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15696 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15697 continue;
15698
63b66e5b
CW		 15699 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15700
15701 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15702 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15703 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15704 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15705 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15706 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15707 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15708 }
15709
15710 return error;
15711}
15712
edc3d884
MK		 15713#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15714
c4a1d9e4 15715void
edc3d884 15716intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15717 struct drm_device *dev,
15718 struct intel_display_error_state *error)
15719{
055e393f 15720 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15721 int i;
15722
63b66e5b
CW		 15723 if (!error)
15724 return;
15725
edc3d884 15726 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15727 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15728 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15729 error->power_well_driver);
055e393f 15730 for_each_pipe(dev_priv, i) {
edc3d884 15731 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15732 err_printf(m, " Power: %s\n",
15733 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15734 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15735 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15736
15737 err_printf(m, "Plane [%d]:\n", i);
15738 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15739 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15740 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15741 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15742 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15743 }
4b71a570 15744 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15745 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15746 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15747 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15748 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15749 }
15750
edc3d884
MK		 15751 err_printf(m, "Cursor [%d]:\n", i);
15752 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15753 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15754 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15755 }
63b66e5b
CW		 15756
15757 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15758 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15759 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15760 err_printf(m, " Power: %s\n",
15761 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15762 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15763 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15764 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15765 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15766 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15767 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15768 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15769 }
c4a1d9e4 15770}
e2fcdaa9
VS		 15771
15772void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15773{
15774 struct intel_crtc *crtc;
15775
15776 for_each_intel_crtc(dev, crtc) {
15777 struct intel_unpin_work *work;
e2fcdaa9 15778
5e2d7afc 15779 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15780
15781 work = crtc->unpin_work;
15782
15783 if (work && work->event &&
15784 work->event->base.file_priv == file) {
15785 kfree(work->event);
15786 work->event = NULL;
15787 }
15788
5e2d7afc 15789 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15790 }
15791}
Linux kernel - Deliverables
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