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drm/i915: Change locking for struct_mutex, v3.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
bfd16b2a
ML		 115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
bfa7df01
VS		 135/* returns HPLL frequency in kHz */
136static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137{
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147}
148
149static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151{
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169}
170
d2acd215
DV		 171int
172intel_pch_rawclk(struct drm_device *dev)
173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179}
180
79e50a4f
JN		 181/* hrawclock is 1/4 the FSB frequency */
182int intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
bfa7df01
VS		 214static void intel_update_czclk(struct drm_i915_private *dev_priv)
215{
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223}
224
021357ac
CW		 225static inline u32 /* units of 100MHz */
226intel_fdi_link_freq(struct drm_device *dev)
227{
8b99e68c
CW		 228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
021357ac
CW		 233}
234
5d536e28 235static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 236 .dot = { .min = 25000, .max = 350000 },
9c333719 237 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 238 .n = { .min = 2, .max = 16 },
0206e353
AJ		 239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 246};
247
5d536e28
DV		 248static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
9c333719 250 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 251 .n = { .min = 2, .max = 16 },
5d536e28
DV		 252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259};
260
e4b36699 261static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 262 .dot = { .min = 25000, .max = 350000 },
9c333719 263 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 264 .n = { .min = 2, .max = 16 },
0206e353
AJ		 265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
e4b36699 272};
273e27ca 273
e4b36699 274static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
287static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 298};
299
273e27ca 300
e4b36699 301static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
044c7c41 313 },
e4b36699
KP		 314};
315
316static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 327};
328
329static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
044c7c41 340 },
e4b36699
KP		 341};
342
343static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
044c7c41 354 },
e4b36699
KP		 355};
356
f2b115e6 357static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 360 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
273e27ca 363 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 370};
371
f2b115e6 372static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 383};
384
273e27ca
EA		 385/* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
b91ad0ec 390static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 401};
402
b91ad0ec 403static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 414};
415
416static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 427};
428
273e27ca 429/* LVDS 100mhz refclk limits. */
b91ad0ec 430static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
0206e353 438 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 441};
442
443static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
0206e353 451 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 454};
455
dc730512 456static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 464 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 465 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
b99ab663 468 .p1 = { .min = 2, .max = 3 },
5fdc9c49 469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 470};
471
ef9348c8
CML		 472static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 480 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486};
487
5ab7b0b7
ID		 488static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
e6292556 491 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498};
499
cdba954e
ACO		 500static bool
501needs_modeset(struct drm_crtc_state *state)
502{
fc596660 503 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 504}
505
e0638cdf
PZ		 506/**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
4093561b 509bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 510{
409ee761 511 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 512 struct intel_encoder *encoder;
513
409ee761 514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 515 if (encoder->type == type)
516 return true;
517
518 return false;
519}
520
d0737e1d
ACO		 521/**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
a93e255f
ACO		 527static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
d0737e1d 529{
a93e255f 530 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 531 struct drm_connector *connector;
a93e255f 532 struct drm_connector_state *connector_state;
d0737e1d 533 struct intel_encoder *encoder;
a93e255f
ACO		 534 int i, num_connectors = 0;
535
da3ced29 536 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
d0737e1d 541
a93e255f
ACO		 542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
d0737e1d 544 return true;
a93e255f
ACO		 545 }
546
547 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 548
549 return false;
550}
551
a93e255f
ACO		 552static const intel_limit_t *
553intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 554{
a93e255f 555 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 556 const intel_limit_t *limit;
b91ad0ec 557
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 559 if (intel_is_dual_link_lvds(dev)) {
1b894b59 560 if (refclk == 100000)
b91ad0ec
ZW		 561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
1b894b59 565 if (refclk == 100000)
b91ad0ec
ZW		 566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
c6bb3538 570 } else
b91ad0ec 571 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 572
573 return limit;
574}
575
a93e255f
ACO		 576static const intel_limit_t *
577intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 578{
a93e255f 579 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 580 const intel_limit_t *limit;
581
a93e255f 582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 583 if (intel_is_dual_link_lvds(dev))
e4b36699 584 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 585 else
e4b36699 586 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 589 limit = &intel_limits_g4x_hdmi;
a93e255f 590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 591 limit = &intel_limits_g4x_sdvo;
044c7c41 592 } else /* The option is for other outputs */
e4b36699 593 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 594
595 return limit;
596}
597
a93e255f
ACO		 598static const intel_limit_t *
599intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 600{
a93e255f 601 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 602 const intel_limit_t *limit;
603
5ab7b0b7
ID		 604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
a93e255f 607 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 608 else if (IS_G4X(dev)) {
a93e255f 609 limit = intel_g4x_limit(crtc_state);
f2b115e6 610 } else if (IS_PINEVIEW(dev)) {
a93e255f 611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 612 limit = &intel_limits_pineview_lvds;
2177832f 613 else
f2b115e6 614 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
a0c4da24 617 } else if (IS_VALLEYVIEW(dev)) {
dc730512 618 limit = &intel_limits_vlv;
a6c45cf0 619 } else if (!IS_GEN2(dev)) {
a93e255f 620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
79e53945 624 } else {
a93e255f 625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 626 limit = &intel_limits_i8xx_lvds;
a93e255f 627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 628 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 629 else
630 limit = &intel_limits_i8xx_dac;
79e53945
JB		 631 }
632 return limit;
633}
634
dccbea3b
ID		 635/*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
f2b115e6 643/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 644static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 645{
2177832f
SL		 646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
ed5ca77e 648 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 649 return 0;
fb03ac01
VS		 650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 652
653 return clock->dot;
2177832f
SL		 654}
655
7429e9d4
DV		 656static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657{
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659}
660
dccbea3b 661static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 662{
7429e9d4 663 clock->m = i9xx_dpll_compute_m(clock);
79e53945 664 clock->p = clock->p1 * clock->p2;
ed5ca77e 665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 666 return 0;
fb03ac01
VS		 667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 669
670 return clock->dot;
79e53945
JB		 671}
672
dccbea3b 673static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 674{
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 678 return 0;
589eca67
ID		 679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 681
682 return clock->dot / 5;
589eca67
ID		 683}
684
dccbea3b 685int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 686{
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 690 return 0;
ef9348c8
CML		 691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 694
695 return clock->dot / 5;
ef9348c8
CML		 696}
697
7c04d1d9 698#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 699/**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
1b894b59
CW		 704static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
79e53945 707{
f01b7962
VS		 708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
79e53945 710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 711 INTELPllInvalid("p1 out of range\n");
79e53945 712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 713 INTELPllInvalid("m2 out of range\n");
79e53945 714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 715 INTELPllInvalid("m1 out of range\n");
f01b7962 716
5ab7b0b7 717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
5ab7b0b7 721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
79e53945 728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 729 INTELPllInvalid("vco out of range\n");
79e53945
JB		 730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 734 INTELPllInvalid("dot out of range\n");
79e53945
JB		 735
736 return true;
737}
738
3b1429d9
VS		 739static int
740i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
79e53945 743{
3b1429d9 744 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 745
a93e255f 746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 747 /*
a210b028
DV		 748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
79e53945 751 */
1974cad0 752 if (intel_is_dual_link_lvds(dev))
3b1429d9 753 return limit->p2.p2_fast;
79e53945 754 else
3b1429d9 755 return limit->p2.p2_slow;
79e53945
JB		 756 } else {
757 if (target < limit->p2.dot_limit)
3b1429d9 758 return limit->p2.p2_slow;
79e53945 759 else
3b1429d9 760 return limit->p2.p2_fast;
79e53945 761 }
3b1429d9
VS		 762}
763
764static bool
765i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769{
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
79e53945 773
0206e353 774 memset(best_clock, 0, sizeof(*best_clock));
79e53945 775
3b1429d9
VS		 776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
42158660
ZY		 778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 782 if (clock.m2 >= clock.m1)
42158660
ZY		 783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 788 int this_err;
789
dccbea3b 790 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809}
810
811static bool
a93e255f
ACO		 812pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
79e53945 816{
3b1429d9 817 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 818 intel_clock_t clock;
79e53945
JB		 819 int err = target;
820
0206e353 821 memset(best_clock, 0, sizeof(*best_clock));
79e53945 822
3b1429d9
VS		 823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
42158660
ZY		 825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 833 int this_err;
834
dccbea3b 835 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
79e53945 838 continue;
cec2f356
SP		 839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
79e53945
JB		 842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854}
855
d4906093 856static bool
a93e255f
ACO		 857g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
d4906093 861{
3b1429d9 862 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 863 intel_clock_t clock;
864 int max_n;
3b1429d9 865 bool found = false;
6ba770dc
AJ		 866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 868
869 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
d4906093 873 max_n = limit->n.max;
f77f13e2 874 /* based on hardware requirement, prefer smaller n to precision */
d4906093 875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 876 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
dccbea3b 885 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
d4906093 888 continue;
1b894b59
CW		 889
890 this_err = abs(clock.dot - target);
d4906093
ML		 891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
2c07245f
ZW		 901 return found;
902}
903
d5dd62bd
ID		 904/*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913{
9ca3ba01
ID		 914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
24be4e46
ID		 924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
d5dd62bd
ID		 927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942}
943
a0c4da24 944static bool
a93e255f
ACO		 945vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
a0c4da24 949{
a93e255f 950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 951 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 952 intel_clock_t clock;
69e4f900 953 unsigned int bestppm = 1000000;
27e639bf
VS		 954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 956 bool found = false;
a0c4da24 957
6b4bf1c4
VS		 958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 961
962 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 967 clock.p = clock.p1 * clock.p2;
a0c4da24 968 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 970 unsigned int ppm;
69e4f900 971
6b4bf1c4
VS		 972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
dccbea3b 975 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 976
f01b7962
VS		 977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
43b0ac53
VS		 979 continue;
980
d5dd62bd
ID		 981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
6b4bf1c4 986
d5dd62bd
ID		 987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
a0c4da24
JB		 990 }
991 }
992 }
993 }
a0c4da24 994
49e497ef 995 return found;
a0c4da24 996}
a4fc5ed6 997
ef9348c8 998static bool
a93e255f
ACO		 999chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003{
a93e255f 1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 1005 struct drm_device *dev = crtc->base.dev;
9ca3ba01 1006 unsigned int best_error_ppm;
ef9348c8
CML		 1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 1012 best_error_ppm = 1000000;
ef9348c8
CML		 1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 1026 unsigned int error_ppm;
ef9348c8
CML		 1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
dccbea3b 1038 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
9ca3ba01
ID		 1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
ef9348c8
CML		 1050 }
1051 }
1052
1053 return found;
1054}
1055
5ab7b0b7
ID		 1056bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058{
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063}
1064
20ddf665
VS		 1065bool intel_crtc_active(struct drm_crtc *crtc)
1066{
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
241bfc38 1072 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1073 * as Haswell has gained clock readout/fastboot support.
1074 *
66e514c1 1075 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1076 * properly reconstruct framebuffers.
c3d1f436
MR		 1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
20ddf665 1081 */
c3d1f436 1082 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1084}
1085
a5c961d1
PZ		 1086enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088{
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
6e3c9717 1092 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1093}
1094
fbf49ea2
VS		 1095static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096{
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1108 msleep(5);
fbf49ea2
VS		 1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112}
1113
ab7ad7f6
KP		 1114/*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1116 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
ab7ad7f6
KP		 1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
58e10eb9 1128 *
9d0498a2 1129 */
575f7ab7 1130static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1131{
575f7ab7 1132 struct drm_device *dev = crtc->base.dev;
9d0498a2 1133 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1135 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1138 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1139
1140 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
284637d9 1143 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1144 } else {
ab7ad7f6 1145 /* Wait for the display line to settle */
fbf49ea2 1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1147 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1148 }
79e53945
JB		 1149}
1150
b24e7179
JB		 1151static const char *state_string(bool enabled)
1152{
1153 return enabled ? "on" : "off";
1154}
1155
1156/* Only for pre-ILK configs */
55607e8a
DV		 1157void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
b24e7179 1159{
b24e7179
JB		 1160 u32 val;
1161 bool cur_state;
1162
649636ef 1163 val = I915_READ(DPLL(pipe));
b24e7179 1164 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1165 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168}
b24e7179 1169
23538ef1
JN		 1170/* XXX: the dsi pll is shared between MIPI DSI ports */
1171static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172{
1173 u32 val;
1174 bool cur_state;
1175
a580516d 1176 mutex_lock(&dev_priv->sb_lock);
23538ef1 1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1178 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1179
1180 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184}
1185#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
55607e8a 1188struct intel_shared_dpll *
e2b78267
DV		 1189intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190{
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
6e3c9717 1193 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1194 return NULL;
1195
6e3c9717 1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1197}
1198
040484af 1199/* For ILK+ */
55607e8a
DV		 1200void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
040484af 1203{
040484af 1204 bool cur_state;
5358901f 1205 struct intel_dpll_hw_state hw_state;
040484af 1206
92b27b08 1207 if (WARN (!pll,
46edb027 1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1209 return;
ee7b9f93 1210
5358901f 1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1212 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
040484af 1215}
040484af
JB		 1216
1217static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219{
040484af 1220 bool cur_state;
ad80a810
PZ		 1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
040484af 1223
affa9354
PZ		 1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
649636ef 1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1228 } else {
649636ef 1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED		 1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
e2c719b7 1232 I915_STATE_WARN(cur_state != state,
040484af
JB		 1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235}
1236#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241{
040484af
JB		 1242 u32 val;
1243 bool cur_state;
1244
649636ef 1245 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1246 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1247 I915_STATE_WARN(cur_state != state,
040484af
JB		 1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250}
1251#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
040484af
JB		 1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
3d13ef2e 1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1261 return;
1262
bf507ef7 1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1264 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1265 return;
1266
649636ef 1267 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1269}
1270
55607e8a
DV		 1271void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
040484af 1273{
040484af 1274 u32 val;
55607e8a 1275 bool cur_state;
040484af 1276
649636ef 1277 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1279 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
040484af
JB		 1282}
1283
b680c37a
DV		 1284void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
ea0760cf 1286{
bedd4dba
JN		 1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
ea0760cf
JB		 1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
0de3b485 1291 bool locked = true;
ea0760cf 1292
bedd4dba
JN		 1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
ea0760cf 1299 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
ea0760cf
JB		 1310 } else {
1311 pp_reg = PP_CONTROL;
bedd4dba
JN		 1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
ea0760cf
JB		 1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1319 locked = false;
1320
e2c719b7 1321 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1322 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1323 pipe_name(pipe));
ea0760cf
JB		 1324}
1325
93ce0ba6
JN		 1326static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328{
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
d9d82081 1332 if (IS_845G(dev) || IS_I865G(dev))
0b87c24e 1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1334 else
5efb3e28 1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340}
1341#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
b840d907
JB		 1344void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
b24e7179 1346{
63d7bbe9 1347 bool cur_state;
702e7a56
PZ		 1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
b24e7179 1350
b6b5d049
VS		 1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1354 state = true;
1355
f458ebbc 1356 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1358 cur_state = false;
1359 } else {
649636ef 1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161
PZ		 1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
63d7bbe9 1365 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1366 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
b24e7179 1371{
b24e7179 1372 u32 val;
931872fc 1373 bool cur_state;
b24e7179 1374
649636ef 1375 val = I915_READ(DSPCNTR(plane));
931872fc 1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1377 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1380}
1381
931872fc
CW		 1382#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
b24e7179
JB		 1385static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387{
653e1026 1388 struct drm_device *dev = dev_priv->dev;
649636ef 1389 int i;
b24e7179 1390
653e1026
VS		 1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
649636ef 1393 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
19ec1358 1397 return;
28c05794 1398 }
19ec1358 1399
b24e7179 1400 /* Need to check both planes against the pipe */
055e393f 1401 for_each_pipe(dev_priv, i) {
649636ef
VS		 1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1404 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1408 }
1409}
1410
19332d7a
JB		 1411static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413{
20674eef 1414 struct drm_device *dev = dev_priv->dev;
649636ef 1415 int sprite;
19332d7a 1416
7feb8b88 1417 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1418 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1425 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
e2c719b7 1427 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1429 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
649636ef 1432 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1433 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
649636ef 1437 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1438 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1440 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1441 }
1442}
1443
08c71e5e
VS		 1444static void assert_vblank_disabled(struct drm_crtc *crtc)
1445{
e2c719b7 1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1447 drm_crtc_vblank_put(crtc);
1448}
1449
89eff4be 1450static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1451{
1452 u32 val;
1453 bool enabled;
1454
e2c719b7 1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1456
92f2584a
JB		 1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1461}
1462
ab9412ba
DV		 1463static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
92f2584a 1465{
92f2584a
JB		 1466 u32 val;
1467 bool enabled;
1468
649636ef 1469 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1470 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1471 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
92f2584a
JB		 1474}
1475
4e634389
KP		 1476static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1478{
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
44f37d1f
CML		 1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
f0575e92
KP		 1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495}
1496
1519b995
KP		 1497static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499{
dc0fa718 1500 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1505 return false;
44f37d1f
CML		 1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1519b995 1509 } else {
dc0fa718 1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1511 return false;
1512 }
1513 return true;
1514}
1515
1516static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518{
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
1532static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534{
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545}
1546
291906f1 1547static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1548 enum pipe pipe, int reg, u32 port_sel)
291906f1 1549{
47a05eca 1550 u32 val = I915_READ(reg);
e2c719b7 1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1553 reg, pipe_name(pipe));
de9a35ab 1554
e2c719b7 1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1556 && (val & DP_PIPEB_SELECT),
de9a35ab 1557 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1558}
1559
1560static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562{
47a05eca 1563 u32 val = I915_READ(reg);
e2c719b7 1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1566 reg, pipe_name(pipe));
de9a35ab 1567
e2c719b7 1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1569 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1570 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1571}
1572
1573static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575{
291906f1 1576 u32 val;
291906f1 1577
f0575e92
KP		 1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1581
649636ef 1582 val = I915_READ(PCH_ADPA);
e2c719b7 1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
649636ef 1587 val = I915_READ(PCH_LVDS);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
b8afb911 1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
b8afb911 1783 u32 val;
f6071166
JB		 1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
b8afb911 1792 val = DPLL_VGA_MODE_DIS;
f6071166 1793 if (pipe == PIPE_B)
60bfe44f 1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1797
1798}
1799
1800static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801{
d752048d 1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1803 u32 val;
1804
a11b0703
VS		 1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1807
a11b0703 1808 /* Set PLL en = 0 */
60bfe44f
VS		 1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
d752048d 1815
a580516d 1816 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
a580516d 1823 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1824}
1825
e4607fcf 1826void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
89b667f8
JB		 1829{
1830 u32 port_mask;
00fc31b7 1831 int dpll_reg;
89b667f8 1832
e4607fcf
CML		 1833 switch (dport->port) {
1834 case PORT_B:
89b667f8 1835 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1836 dpll_reg = DPLL(0);
e4607fcf
CML		 1837 break;
1838 case PORT_C:
89b667f8 1839 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1840 dpll_reg = DPLL(0);
9b6de0a1 1841 expected_mask <<= 4;
00fc31b7
CML		 1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1846 break;
1847 default:
1848 BUG();
1849 }
89b667f8 1850
9b6de0a1
VS		 1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1854}
1855
b14b1055
DV		 1856static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857{
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
be19f0ff
CW		 1862 if (WARN_ON(pll == NULL))
1863 return;
1864
3e369b76 1865 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873}
1874
92f2584a 1875/**
85b3894f 1876 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
85b3894f 1883static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1884{
3d13ef2e
DL		 1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1888
87a875bb 1889 if (WARN_ON(pll == NULL))
48da64a8
CW		 1890 return;
1891
3e369b76 1892 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1893 return;
ee7b9f93 1894
74dd6928 1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1896 pll->name, pll->active, pll->on,
e2b78267 1897 crtc->base.base.id);
92f2584a 1898
cdbd2316
DV		 1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
e9d6944e 1901 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1902 return;
1903 }
f4a091c7 1904 WARN_ON(pll->on);
ee7b9f93 1905
bd2bb1b9
PZ		 1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
46edb027 1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1909 pll->enable(dev_priv, pll);
ee7b9f93 1910 pll->on = true;
92f2584a
JB		 1911}
1912
f6daaec2 1913static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1914{
3d13ef2e
DL		 1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1918
92f2584a 1919 /* PCH only available on ILK+ */
80aa9312
JB		 1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
eddfcbcd
ML		 1923 if (pll == NULL)
1924 return;
92f2584a 1925
eddfcbcd 1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1927 return;
7a419866 1928
46edb027
DV		 1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
e2b78267 1931 crtc->base.base.id);
7a419866 1932
48da64a8 1933 if (WARN_ON(pll->active == 0)) {
e9d6944e 1934 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1935 return;
1936 }
1937
e9d6944e 1938 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1939 WARN_ON(!pll->on);
cdbd2316 1940 if (--pll->active)
7a419866 1941 return;
ee7b9f93 1942
46edb027 1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1944 pll->disable(dev_priv, pll);
ee7b9f93 1945 pll->on = false;
bd2bb1b9
PZ		 1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1948}
1949
b8a4f404
PZ		 1950static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
040484af 1952{
23670b32 1953 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1956 uint32_t reg, val, pipeconf_val;
040484af
JB		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1960
1961 /* Make sure PCH DPLL is enabled */
e72f9fbf 1962 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1963 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1964
1965 /* FDI must be feeding us bits for PCH ports */
1966 assert_fdi_tx_enabled(dev_priv, pipe);
1967 assert_fdi_rx_enabled(dev_priv, pipe);
1968
23670b32
DV		 1969 if (HAS_PCH_CPT(dev)) {
1970 /* Workaround: Set the timing override bit before enabling the
1971 * pch transcoder. */
1972 reg = TRANS_CHICKEN2(pipe);
1973 val = I915_READ(reg);
1974 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1975 I915_WRITE(reg, val);
59c859d6 1976 }
23670b32 1977
ab9412ba 1978 reg = PCH_TRANSCONF(pipe);
040484af 1979 val = I915_READ(reg);
5f7f726d 1980 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1981
1982 if (HAS_PCH_IBX(dev_priv->dev)) {
1983 /*
c5de7c6f
VS		 1984 * Make the BPC in transcoder be consistent with
1985 * that in pipeconf reg. For HDMI we must use 8bpc
1986 * here for both 8bpc and 12bpc.
e9bcff5c 1987 */
dfd07d72 1988 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1989 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1990 val |= PIPECONF_8BPC;
1991 else
1992 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1993 }
5f7f726d
PZ		 1994
1995 val &= ~TRANS_INTERLACE_MASK;
1996 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1997 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1998 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1999 val |= TRANS_LEGACY_INTERLACED_ILK;
2000 else
2001 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2002 else
2003 val |= TRANS_PROGRESSIVE;
2004
040484af
JB		 2005 I915_WRITE(reg, val | TRANS_ENABLE);
2006 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2007 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2008}
2009
8fb033d7 2010static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2011 enum transcoder cpu_transcoder)
040484af 2012{
8fb033d7 2013 u32 val, pipeconf_val;
8fb033d7
PZ		 2014
2015 /* PCH only available on ILK+ */
55522f37 2016 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2017
8fb033d7 2018 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2019 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2020 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2021
223a6fdf 2022 /* Workaround: set timing override bit. */
36c0d0cf 2023 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2024 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2025 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 2026
25f3ef11 2027 val = TRANS_ENABLE;
937bb610 2028 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2029
9a76b1c6
PZ		 2030 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2031 PIPECONF_INTERLACED_ILK)
a35f2679 2032 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2033 else
2034 val |= TRANS_PROGRESSIVE;
2035
ab9412ba
DV		 2036 I915_WRITE(LPT_TRANSCONF, val);
2037 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2038 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2039}
2040
b8a4f404
PZ		 2041static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2042 enum pipe pipe)
040484af 2043{
23670b32
DV		 2044 struct drm_device *dev = dev_priv->dev;
2045 uint32_t reg, val;
040484af
JB		 2046
2047 /* FDI relies on the transcoder */
2048 assert_fdi_tx_disabled(dev_priv, pipe);
2049 assert_fdi_rx_disabled(dev_priv, pipe);
2050
291906f1
JB		 2051 /* Ports must be off as well */
2052 assert_pch_ports_disabled(dev_priv, pipe);
2053
ab9412ba 2054 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2055 val = I915_READ(reg);
2056 val &= ~TRANS_ENABLE;
2057 I915_WRITE(reg, val);
2058 /* wait for PCH transcoder off, transcoder state */
2059 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2060 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2061
2062 if (!HAS_PCH_IBX(dev)) {
2063 /* Workaround: Clear the timing override chicken bit again. */
2064 reg = TRANS_CHICKEN2(pipe);
2065 val = I915_READ(reg);
2066 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2067 I915_WRITE(reg, val);
2068 }
040484af
JB		 2069}
2070
ab4d966c 2071static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2072{
8fb033d7
PZ		 2073 u32 val;
2074
ab9412ba 2075 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2076 val &= ~TRANS_ENABLE;
ab9412ba 2077 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2078 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2079 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2080 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2081
2082 /* Workaround: clear timing override bit. */
36c0d0cf 2083 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 2085 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB		 2086}
2087
b24e7179 2088/**
309cfea8 2089 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2090 * @crtc: crtc responsible for the pipe
b24e7179 2091 *
0372264a 2092 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2093 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2094 */
e1fdc473 2095static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2096{
0372264a
PZ		 2097 struct drm_device *dev = crtc->base.dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2101 pipe);
1a240d4d 2102 enum pipe pch_transcoder;
b24e7179
JB		 2103 int reg;
2104 u32 val;
2105
9e2ee2dd
VS		 2106 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2107
58c6eaa2 2108 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2109 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2110 assert_sprites_disabled(dev_priv, pipe);
2111
681e5811 2112 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2113 pch_transcoder = TRANSCODER_A;
2114 else
2115 pch_transcoder = pipe;
2116
b24e7179
JB		 2117 /*
2118 * A pipe without a PLL won't actually be able to drive bits from
2119 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2120 * need the check.
2121 */
50360403 2122 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2124 assert_dsi_pll_enabled(dev_priv);
2125 else
2126 assert_pll_enabled(dev_priv, pipe);
040484af 2127 else {
6e3c9717 2128 if (crtc->config->has_pch_encoder) {
040484af 2129 /* if driving the PCH, we need FDI enabled */
cc391bbb 2130 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2131 assert_fdi_tx_pll_enabled(dev_priv,
2132 (enum pipe) cpu_transcoder);
040484af
JB		 2133 }
2134 /* FIXME: assert CPU port conditions for SNB+ */
2135 }
b24e7179 2136
702e7a56 2137 reg = PIPECONF(cpu_transcoder);
b24e7179 2138 val = I915_READ(reg);
7ad25d48 2139 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2140 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2141 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2142 return;
7ad25d48 2143 }
00d70b15
CW		 2144
2145 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2146 POSTING_READ(reg);
b24e7179
JB		 2147}
2148
2149/**
309cfea8 2150 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2151 * @crtc: crtc whose pipes is to be disabled
b24e7179 2152 *
575f7ab7
VS		 2153 * Disable the pipe of @crtc, making sure that various hardware
2154 * specific requirements are met, if applicable, e.g. plane
2155 * disabled, panel fitter off, etc.
b24e7179
JB		 2156 *
2157 * Will wait until the pipe has shut down before returning.
2158 */
575f7ab7 2159static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2160{
575f7ab7 2161 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2162 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2163 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2164 int reg;
2165 u32 val;
2166
9e2ee2dd
VS		 2167 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2168
b24e7179
JB		 2169 /*
2170 * Make sure planes won't keep trying to pump pixels to us,
2171 * or we might hang the display.
2172 */
2173 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2174 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2175 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2176
702e7a56 2177 reg = PIPECONF(cpu_transcoder);
b24e7179 2178 val = I915_READ(reg);
00d70b15
CW		 2179 if ((val & PIPECONF_ENABLE) == 0)
2180 return;
2181
67adc644
VS		 2182 /*
2183 * Double wide has implications for planes
2184 * so best keep it disabled when not needed.
2185 */
6e3c9717 2186 if (crtc->config->double_wide)
67adc644
VS		 2187 val &= ~PIPECONF_DOUBLE_WIDE;
2188
2189 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2190 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2191 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2192 val &= ~PIPECONF_ENABLE;
2193
2194 I915_WRITE(reg, val);
2195 if ((val & PIPECONF_ENABLE) == 0)
2196 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2197}
2198
693db184
CW		 2199static bool need_vtd_wa(struct drm_device *dev)
2200{
2201#ifdef CONFIG_INTEL_IOMMU
2202 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2203 return true;
2204#endif
2205 return false;
2206}
2207
50470bb0 2208unsigned int
6761dd31 2209intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
fe47ea0c 2210 uint64_t fb_format_modifier, unsigned int plane)
a57ce0b2 2211{
6761dd31
TU		 2212 unsigned int tile_height;
2213 uint32_t pixel_bytes;
a57ce0b2 2214
b5d0e9bf
DL		 2215 switch (fb_format_modifier) {
2216 case DRM_FORMAT_MOD_NONE:
2217 tile_height = 1;
2218 break;
2219 case I915_FORMAT_MOD_X_TILED:
2220 tile_height = IS_GEN2(dev) ? 16 : 8;
2221 break;
2222 case I915_FORMAT_MOD_Y_TILED:
2223 tile_height = 32;
2224 break;
2225 case I915_FORMAT_MOD_Yf_TILED:
fe47ea0c 2226 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
6761dd31 2227 switch (pixel_bytes) {
b5d0e9bf 2228 default:
6761dd31 2229 case 1:
b5d0e9bf
DL		 2230 tile_height = 64;
2231 break;
6761dd31
TU		 2232 case 2:
2233 case 4:
b5d0e9bf
DL		 2234 tile_height = 32;
2235 break;
6761dd31 2236 case 8:
b5d0e9bf
DL		 2237 tile_height = 16;
2238 break;
6761dd31 2239 case 16:
b5d0e9bf
DL		 2240 WARN_ONCE(1,
2241 "128-bit pixels are not supported for display!");
2242 tile_height = 16;
2243 break;
2244 }
2245 break;
2246 default:
2247 MISSING_CASE(fb_format_modifier);
2248 tile_height = 1;
2249 break;
2250 }
091df6cb 2251
6761dd31
TU		 2252 return tile_height;
2253}
2254
2255unsigned int
2256intel_fb_align_height(struct drm_device *dev, unsigned int height,
2257 uint32_t pixel_format, uint64_t fb_format_modifier)
2258{
2259 return ALIGN(height, intel_tile_height(dev, pixel_format,
fe47ea0c 2260 fb_format_modifier, 0));
a57ce0b2
JB		 2261}
2262
f64b98cd
TU		 2263static int
2264intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2265 const struct drm_plane_state *plane_state)
2266{
50470bb0 2267 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2268 unsigned int tile_height, tile_pitch;
50470bb0 2269
f64b98cd
TU		 2270 *view = i915_ggtt_view_normal;
2271
50470bb0
TU		 2272 if (!plane_state)
2273 return 0;
2274
121920fa 2275 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2276 return 0;
2277
9abc4648 2278 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2279
2280 info->height = fb->height;
2281 info->pixel_format = fb->pixel_format;
2282 info->pitch = fb->pitches[0];
89e3e142 2283 info->uv_offset = fb->offsets[1];
50470bb0
TU		 2284 info->fb_modifier = fb->modifier[0];
2285
84fe03f7 2286 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
fe47ea0c 2287 fb->modifier[0], 0);
84fe03f7
TU		 2288 tile_pitch = PAGE_SIZE / tile_height;
2289 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2290 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2291 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2292
89e3e142
TU		 2293 if (info->pixel_format == DRM_FORMAT_NV12) {
2294 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2295 fb->modifier[0], 1);
2296 tile_pitch = PAGE_SIZE / tile_height;
2297 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2298 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2299 tile_height);
2300 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2301 PAGE_SIZE;
2302 }
2303
f64b98cd
TU		 2304 return 0;
2305}
2306
4e9a86b6
VS		 2307static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2308{
2309 if (INTEL_INFO(dev_priv)->gen >= 9)
2310 return 256 * 1024;
985b8bb4
VS		 2311 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2312 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2313 return 128 * 1024;
2314 else if (INTEL_INFO(dev_priv)->gen >= 4)
2315 return 4 * 1024;
2316 else
44c5905e 2317 return 0;
4e9a86b6
VS		 2318}
2319
127bd2ac 2320int
850c4cdc
TU		 2321intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2322 struct drm_framebuffer *fb,
82bc3b2d 2323 const struct drm_plane_state *plane_state,
91af127f
JH		 2324 struct intel_engine_cs *pipelined,
2325 struct drm_i915_gem_request **pipelined_request)
6b95a207 2326{
850c4cdc 2327 struct drm_device *dev = fb->dev;
ce453d81 2328 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2329 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2330 struct i915_ggtt_view view;
6b95a207
KH		 2331 u32 alignment;
2332 int ret;
2333
ebcdd39e
MR		 2334 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2335
7b911adc
TU		 2336 switch (fb->modifier[0]) {
2337 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2338 alignment = intel_linear_alignment(dev_priv);
6b95a207 2339 break;
7b911adc 2340 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else {
2344 /* pin() will align the object as required by fence */
2345 alignment = 0;
2346 }
6b95a207 2347 break;
7b911adc 2348 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2349 case I915_FORMAT_MOD_Yf_TILED:
2350 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2351 "Y tiling bo slipped through, driver bug!\n"))
2352 return -EINVAL;
2353 alignment = 1 * 1024 * 1024;
2354 break;
6b95a207 2355 default:
7b911adc
TU		 2356 MISSING_CASE(fb->modifier[0]);
2357 return -EINVAL;
6b95a207
KH		 2358 }
2359
f64b98cd
TU		 2360 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2361 if (ret)
2362 return ret;
2363
693db184
CW		 2364 /* Note that the w/a also requires 64 PTE of padding following the
2365 * bo. We currently fill all unused PTE with the shadow page and so
2366 * we should always have valid PTE following the scanout preventing
2367 * the VT-d warning.
2368 */
2369 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2370 alignment = 256 * 1024;
2371
d6dd6843
PZ		 2372 /*
2373 * Global gtt pte registers are special registers which actually forward
2374 * writes to a chunk of system memory. Which means that there is no risk
2375 * that the register values disappear as soon as we call
2376 * intel_runtime_pm_put(), so it is correct to wrap only the
2377 * pin/unpin/fence and not more.
2378 */
2379 intel_runtime_pm_get(dev_priv);
2380
e6617330 2381 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2382 pipelined_request, &view);
48b956c5 2383 if (ret)
b26a6b35 2384 goto err_pm;
6b95a207
KH		 2385
2386 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2387 * fence, whereas 965+ only requires a fence if using
2388 * framebuffer compression. For simplicity, we always install
2389 * a fence as the cost is not that onerous.
2390 */
06d98131 2391 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2392 if (ret == -EDEADLK) {
2393 /*
2394 * -EDEADLK means there are no free fences
2395 * no pending flips.
2396 *
2397 * This is propagated to atomic, but it uses
2398 * -EDEADLK to force a locking recovery, so
2399 * change the returned error to -EBUSY.
2400 */
2401 ret = -EBUSY;
2402 goto err_unpin;
2403 } else if (ret)
9a5a53b3 2404 goto err_unpin;
1690e1eb 2405
9a5a53b3 2406 i915_gem_object_pin_fence(obj);
6b95a207 2407
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
b26a6b35 2413err_pm:
d6dd6843 2414 intel_runtime_pm_put(dev_priv);
48b956c5 2415 return ret;
6b95a207
KH		 2416}
2417
82bc3b2d
TU		 2418static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2419 const struct drm_plane_state *plane_state)
1690e1eb 2420{
82bc3b2d 2421 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2422 struct i915_ggtt_view view;
2423 int ret;
82bc3b2d 2424
ebcdd39e
MR		 2425 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2426
f64b98cd
TU		 2427 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2428 WARN_ONCE(ret, "Couldn't get view from plane state!");
2429
1690e1eb 2430 i915_gem_object_unpin_fence(obj);
f64b98cd 2431 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2432}
2433
c2c75131
DV		 2434/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2435 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2436unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2437 int *x, int *y,
bc752862
CW		 2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
4e9a86b6 2453 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2454 unsigned int offset;
2455
2456 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2457 *y = (offset & alignment) / pitch;
2458 *x = ((offset & alignment) - *y * pitch) / cpp;
2459 return offset & ~alignment;
bc752862 2460 }
c2c75131
DV		 2461}
2462
b35d63fa 2463static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2464{
2465 switch (format) {
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2481 }
2482}
2483
bc8d7dff
DL		 2484static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485{
2486 switch (format) {
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2489 default:
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2491 if (rgb_order) {
2492 if (alpha)
2493 return DRM_FORMAT_ABGR8888;
2494 else
2495 return DRM_FORMAT_XBGR8888;
2496 } else {
2497 if (alpha)
2498 return DRM_FORMAT_ARGB8888;
2499 else
2500 return DRM_FORMAT_XRGB8888;
2501 }
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2503 if (rgb_order)
2504 return DRM_FORMAT_XBGR2101010;
2505 else
2506 return DRM_FORMAT_XRGB2101010;
2507 }
2508}
2509
5724dbd1 2510static bool
f6936e29
DV		 2511intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2513{
2514 struct drm_device *dev = crtc->base.dev;
3badb49f 2515 struct drm_i915_private *dev_priv = to_i915(dev);
46f297fb
JB		 2516 struct drm_i915_gem_object *obj = NULL;
2517 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2518 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2519 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2520 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2521 PAGE_SIZE);
2522
2523 size_aligned -= base_aligned;
46f297fb 2524
ff2652ea
CW		 2525 if (plane_config->size == 0)
2526 return false;
2527
3badb49f
PZ		 2528 /* If the FB is too big, just don't use it since fbdev is not very
2529 * important and we should probably use that space with FBC or other
2530 * features. */
2531 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2532 return false;
2533
f37b5c2b
DV		 2534 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2535 base_aligned,
2536 base_aligned,
2537 size_aligned);
46f297fb 2538 if (!obj)
484b41dd 2539 return false;
46f297fb 2540
49af449b
DL		 2541 obj->tiling_mode = plane_config->tiling;
2542 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2543 obj->stride = fb->pitches[0];
46f297fb 2544
6bf129df
DL		 2545 mode_cmd.pixel_format = fb->pixel_format;
2546 mode_cmd.width = fb->width;
2547 mode_cmd.height = fb->height;
2548 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2549 mode_cmd.modifier[0] = fb->modifier[0];
2550 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2551
2552 mutex_lock(&dev->struct_mutex);
6bf129df 2553 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2554 &mode_cmd, obj)) {
46f297fb
JB		 2555 DRM_DEBUG_KMS("intel fb init failed\n");
2556 goto out_unref_obj;
2557 }
46f297fb 2558 mutex_unlock(&dev->struct_mutex);
484b41dd 2559
f6936e29 2560 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2561 return true;
46f297fb
JB		 2562
2563out_unref_obj:
2564 drm_gem_object_unreference(&obj->base);
2565 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2566 return false;
2567}
2568
afd65eb4
MR		 2569/* Update plane->state->fb to match plane->fb after driver-internal updates */
2570static void
2571update_state_fb(struct drm_plane *plane)
2572{
2573 if (plane->fb == plane->state->fb)
2574 return;
2575
2576 if (plane->state->fb)
2577 drm_framebuffer_unreference(plane->state->fb);
2578 plane->state->fb = plane->fb;
2579 if (plane->state->fb)
2580 drm_framebuffer_reference(plane->state->fb);
2581}
2582
5724dbd1 2583static void
f6936e29
DV		 2584intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2585 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2586{
2587 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2588 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2589 struct drm_crtc *c;
2590 struct intel_crtc *i;
2ff8fde1 2591 struct drm_i915_gem_object *obj;
88595ac9 2592 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2593 struct drm_plane_state *plane_state = primary->state;
88595ac9 2594 struct drm_framebuffer *fb;
484b41dd 2595
2d14030b 2596 if (!plane_config->fb)
484b41dd
JB		 2597 return;
2598
f6936e29 2599 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2600 fb = &plane_config->fb->base;
2601 goto valid_fb;
f55548b5 2602 }
484b41dd 2603
2d14030b 2604 kfree(plane_config->fb);
484b41dd
JB		 2605
2606 /*
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2609 */
70e1e0ec 2610 for_each_crtc(dev, c) {
484b41dd
JB		 2611 i = to_intel_crtc(c);
2612
2613 if (c == &intel_crtc->base)
2614 continue;
2615
2ff8fde1
MR		 2616 if (!i->active)
2617 continue;
2618
88595ac9
DV		 2619 fb = c->primary->fb;
2620 if (!fb)
484b41dd
JB		 2621 continue;
2622
88595ac9 2623 obj = intel_fb_obj(fb);
2ff8fde1 2624 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2625 drm_framebuffer_reference(fb);
2626 goto valid_fb;
484b41dd
JB		 2627 }
2628 }
88595ac9
DV		 2629
2630 return;
2631
2632valid_fb:
be5651f2
ML		 2633 plane_state->src_x = plane_state->src_y = 0;
2634 plane_state->src_w = fb->width << 16;
2635 plane_state->src_h = fb->height << 16;
2636
2637 plane_state->crtc_x = plane_state->src_y = 0;
2638 plane_state->crtc_w = fb->width;
2639 plane_state->crtc_h = fb->height;
2640
88595ac9
DV		 2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
be5651f2
ML		 2645 drm_framebuffer_reference(fb);
2646 primary->fb = primary->state->fb = fb;
36750f28 2647 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2649 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2650}
2651
29b9bde6
DV		 2652static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
81255565
JB		 2655{
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2661 struct drm_i915_gem_object *obj;
81255565 2662 int plane = intel_crtc->plane;
e506a0c6 2663 unsigned long linear_offset;
81255565 2664 u32 dspcntr;
f45651ba 2665 u32 reg = DSPCNTR(plane);
48404c1e 2666 int pixel_size;
f45651ba 2667
b70709a6 2668 if (!visible || !fb) {
fdd508a6
VS		 2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
c9ba6fad
VS		 2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
f45651ba
VS		 2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
fdd508a6 2686 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2698 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2705 }
81255565 2706
57779d06
VS		 2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
81255565
JB		 2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
57779d06 2711 case DRM_FORMAT_XRGB1555:
57779d06 2712 dspcntr |= DISPPLANE_BGRX555;
81255565 2713 break;
57779d06
VS		 2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
57779d06 2727 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2728 break;
2729 default:
baba133a 2730 BUG();
81255565 2731 }
57779d06 2732
f45651ba
VS		 2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
81255565 2736
de1aa629
VS		 2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
b9897127 2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2741
c2c75131
DV		 2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
b9897127 2746 pixel_size,
bc752862 2747 fb->pitches[0]);
c2c75131
DV		 2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
e506a0c6 2750 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2751 }
e506a0c6 2752
8e7d688b 2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
6e3c9717
ACO		 2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
6e3c9717
ACO		 2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2764 }
2765
2db3366b
PZ		 2766 intel_crtc->adjusted_x = x;
2767 intel_crtc->adjusted_y = y;
2768
48404c1e
SJ		 2769 I915_WRITE(reg, dspcntr);
2770
01f2c773 2771 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2772 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2773 I915_WRITE(DSPSURF(plane),
2774 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2775 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2776 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2777 } else
f343c5f6 2778 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2779 POSTING_READ(reg);
17638cd6
JB		 2780}
2781
29b9bde6
DV		 2782static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2783 struct drm_framebuffer *fb,
2784 int x, int y)
17638cd6
JB		 2785{
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2789 struct drm_plane *primary = crtc->primary;
2790 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2791 struct drm_i915_gem_object *obj;
17638cd6 2792 int plane = intel_crtc->plane;
e506a0c6 2793 unsigned long linear_offset;
17638cd6 2794 u32 dspcntr;
f45651ba 2795 u32 reg = DSPCNTR(plane);
48404c1e 2796 int pixel_size;
f45651ba 2797
b70709a6 2798 if (!visible || !fb) {
fdd508a6
VS		 2799 I915_WRITE(reg, 0);
2800 I915_WRITE(DSPSURF(plane), 0);
2801 POSTING_READ(reg);
2802 return;
2803 }
2804
c9ba6fad
VS		 2805 obj = intel_fb_obj(fb);
2806 if (WARN_ON(obj == NULL))
2807 return;
2808
2809 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2810
f45651ba
VS		 2811 dspcntr = DISPPLANE_GAMMA_ENABLE;
2812
fdd508a6 2813 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2814
2815 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2816 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2817
57779d06
VS		 2818 switch (fb->pixel_format) {
2819 case DRM_FORMAT_C8:
17638cd6
JB		 2820 dspcntr |= DISPPLANE_8BPP;
2821 break;
57779d06
VS		 2822 case DRM_FORMAT_RGB565:
2823 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2824 break;
57779d06 2825 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_BGRX888;
2827 break;
2828 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2829 dspcntr |= DISPPLANE_RGBX888;
2830 break;
2831 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2832 dspcntr |= DISPPLANE_BGRX101010;
2833 break;
2834 case DRM_FORMAT_XBGR2101010:
57779d06 2835 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2836 break;
2837 default:
baba133a 2838 BUG();
17638cd6
JB		 2839 }
2840
2841 if (obj->tiling_mode != I915_TILING_NONE)
2842 dspcntr |= DISPPLANE_TILED;
17638cd6 2843
f45651ba 2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2845 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2846
b9897127 2847 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2848 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2849 intel_gen4_compute_page_offset(dev_priv,
2850 &x, &y, obj->tiling_mode,
b9897127 2851 pixel_size,
bc752862 2852 fb->pitches[0]);
c2c75131 2853 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2854 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2855 dspcntr |= DISPPLANE_ROTATE_180;
2856
2857 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2858 x += (intel_crtc->config->pipe_src_w - 1);
2859 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2860
2861 /* Finding the last pixel of the last line of the display
2862 data and adding to linear_offset*/
2863 linear_offset +=
6e3c9717
ACO		 2864 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2865 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2866 }
2867 }
2868
2db3366b
PZ		 2869 intel_crtc->adjusted_x = x;
2870 intel_crtc->adjusted_y = y;
2871
48404c1e 2872 I915_WRITE(reg, dspcntr);
17638cd6 2873
01f2c773 2874 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2875 I915_WRITE(DSPSURF(plane),
2876 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2877 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2878 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2879 } else {
2880 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2881 I915_WRITE(DSPLINOFF(plane), linear_offset);
2882 }
17638cd6 2883 POSTING_READ(reg);
17638cd6
JB		 2884}
2885
b321803d
DL		 2886u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2887 uint32_t pixel_format)
2888{
2889 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2890
2891 /*
2892 * The stride is either expressed as a multiple of 64 bytes
2893 * chunks for linear buffers or in number of tiles for tiled
2894 * buffers.
2895 */
2896 switch (fb_modifier) {
2897 case DRM_FORMAT_MOD_NONE:
2898 return 64;
2899 case I915_FORMAT_MOD_X_TILED:
2900 if (INTEL_INFO(dev)->gen == 2)
2901 return 128;
2902 return 512;
2903 case I915_FORMAT_MOD_Y_TILED:
2904 /* No need to check for old gens and Y tiling since this is
2905 * about the display engine and those will be blocked before
2906 * we get here.
2907 */
2908 return 128;
2909 case I915_FORMAT_MOD_Yf_TILED:
2910 if (bits_per_pixel == 8)
2911 return 64;
2912 else
2913 return 128;
2914 default:
2915 MISSING_CASE(fb_modifier);
2916 return 64;
2917 }
2918}
2919
121920fa 2920unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
dedf278c
TU		 2921 struct drm_i915_gem_object *obj,
2922 unsigned int plane)
121920fa 2923{
9abc4648 2924 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
dedf278c
TU		 2925 struct i915_vma *vma;
2926 unsigned char *offset;
121920fa
TU		 2927
2928 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2929 view = &i915_ggtt_view_rotated;
121920fa 2930
dedf278c
TU		 2931 vma = i915_gem_obj_to_ggtt_view(obj, view);
2932 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2933 view->type))
2934 return -1;
2935
2936 offset = (unsigned char *)vma->node.start;
2937
2938 if (plane == 1) {
2939 offset += vma->ggtt_view.rotation_info.uv_start_page *
2940 PAGE_SIZE;
2941 }
2942
2943 return (unsigned long)offset;
121920fa
TU		 2944}
2945
e435d6e5
ML		 2946static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2947{
2948 struct drm_device *dev = intel_crtc->base.dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2952 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2953 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2954}
2955
a1b2278e
CK		 2956/*
2957 * This function detaches (aka. unbinds) unused scalers in hardware
2958 */
0583236e 2959static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2960{
a1b2278e
CK		 2961 struct intel_crtc_scaler_state *scaler_state;
2962 int i;
2963
a1b2278e
CK		 2964 scaler_state = &intel_crtc->config->scaler_state;
2965
2966 /* loop through and disable scalers that aren't in use */
2967 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2968 if (!scaler_state->scalers[i].in_use)
2969 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2970 }
2971}
2972
6156a456 2973u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2974{
6156a456 2975 switch (pixel_format) {
d161cf7a 2976 case DRM_FORMAT_C8:
c34ce3d1 2977 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2978 case DRM_FORMAT_RGB565:
c34ce3d1 2979 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2980 case DRM_FORMAT_XBGR8888:
c34ce3d1 2981 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2982 case DRM_FORMAT_XRGB8888:
c34ce3d1 2983 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2984 /*
2985 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2986 * to be already pre-multiplied. We need to add a knob (or a different
2987 * DRM_FORMAT) for user-space to configure that.
2988 */
f75fb42a 2989 case DRM_FORMAT_ABGR8888:
c34ce3d1 2990 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2991 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2992 case DRM_FORMAT_ARGB8888:
c34ce3d1 2993 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2994 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2995 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2996 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2997 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2998 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2999 case DRM_FORMAT_YUYV:
c34ce3d1 3000 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3001 case DRM_FORMAT_YVYU:
c34ce3d1 3002 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3003 case DRM_FORMAT_UYVY:
c34ce3d1 3004 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3005 case DRM_FORMAT_VYUY:
c34ce3d1 3006 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3007 default:
4249eeef 3008 MISSING_CASE(pixel_format);
70d21f0e 3009 }
8cfcba41 3010
c34ce3d1 3011 return 0;
6156a456 3012}
70d21f0e 3013
6156a456
CK		 3014u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3015{
6156a456 3016 switch (fb_modifier) {
30af77c4 3017 case DRM_FORMAT_MOD_NONE:
70d21f0e 3018 break;
30af77c4 3019 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3020 return PLANE_CTL_TILED_X;
b321803d 3021 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3022 return PLANE_CTL_TILED_Y;
b321803d 3023 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3024 return PLANE_CTL_TILED_YF;
70d21f0e 3025 default:
6156a456 3026 MISSING_CASE(fb_modifier);
70d21f0e 3027 }
8cfcba41 3028
c34ce3d1 3029 return 0;
6156a456 3030}
70d21f0e 3031
6156a456
CK		 3032u32 skl_plane_ctl_rotation(unsigned int rotation)
3033{
3b7a5119 3034 switch (rotation) {
6156a456
CK		 3035 case BIT(DRM_ROTATE_0):
3036 break;
1e8df167
SJ		 3037 /*
3038 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3039 * while i915 HW rotation is clockwise, thats why this swapping.
3040 */
3b7a5119 3041 case BIT(DRM_ROTATE_90):
1e8df167 3042 return PLANE_CTL_ROTATE_270;
3b7a5119 3043 case BIT(DRM_ROTATE_180):
c34ce3d1 3044 return PLANE_CTL_ROTATE_180;
3b7a5119 3045 case BIT(DRM_ROTATE_270):
1e8df167 3046 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3047 default:
3048 MISSING_CASE(rotation);
3049 }
3050
c34ce3d1 3051 return 0;
6156a456
CK		 3052}
3053
3054static void skylake_update_primary_plane(struct drm_crtc *crtc,
3055 struct drm_framebuffer *fb,
3056 int x, int y)
3057{
3058 struct drm_device *dev = crtc->dev;
3059 struct drm_i915_private *dev_priv = dev->dev_private;
3060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3061 struct drm_plane *plane = crtc->primary;
3062 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3063 struct drm_i915_gem_object *obj;
3064 int pipe = intel_crtc->pipe;
3065 u32 plane_ctl, stride_div, stride;
3066 u32 tile_height, plane_offset, plane_size;
3067 unsigned int rotation;
3068 int x_offset, y_offset;
3069 unsigned long surf_addr;
6156a456
CK		 3070 struct intel_crtc_state *crtc_state = intel_crtc->config;
3071 struct intel_plane_state *plane_state;
3072 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3073 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3074 int scaler_id = -1;
3075
6156a456
CK		 3076 plane_state = to_intel_plane_state(plane->state);
3077
b70709a6 3078 if (!visible || !fb) {
6156a456
CK		 3079 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3080 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3081 POSTING_READ(PLANE_CTL(pipe, 0));
3082 return;
3b7a5119 3083 }
70d21f0e 3084
6156a456
CK		 3085 plane_ctl = PLANE_CTL_ENABLE |
3086 PLANE_CTL_PIPE_GAMMA_ENABLE |
3087 PLANE_CTL_PIPE_CSC_ENABLE;
3088
3089 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3090 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3091 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3092
3093 rotation = plane->state->rotation;
3094 plane_ctl |= skl_plane_ctl_rotation(rotation);
3095
b321803d
DL		 3096 obj = intel_fb_obj(fb);
3097 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3098 fb->pixel_format);
dedf278c 3099 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3b7a5119 3100
a42e5a23
PZ		 3101 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3102
3103 scaler_id = plane_state->scaler_id;
3104 src_x = plane_state->src.x1 >> 16;
3105 src_y = plane_state->src.y1 >> 16;
3106 src_w = drm_rect_width(&plane_state->src) >> 16;
3107 src_h = drm_rect_height(&plane_state->src) >> 16;
3108 dst_x = plane_state->dst.x1;
3109 dst_y = plane_state->dst.y1;
3110 dst_w = drm_rect_width(&plane_state->dst);
3111 dst_h = drm_rect_height(&plane_state->dst);
3112
3113 WARN_ON(x != src_x || y != src_y);
6156a456 3114
3b7a5119
SJ		 3115 if (intel_rotation_90_or_270(rotation)) {
3116 /* stride = Surface height in tiles */
2614f17d 3117 tile_height = intel_tile_height(dev, fb->pixel_format,
fe47ea0c 3118 fb->modifier[0], 0);
3b7a5119 3119 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3120 x_offset = stride * tile_height - y - src_h;
3b7a5119 3121 y_offset = x;
6156a456 3122 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3123 } else {
3124 stride = fb->pitches[0] / stride_div;
3125 x_offset = x;
3126 y_offset = y;
6156a456 3127 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3128 }
3129 plane_offset = y_offset << 16 | x_offset;
b321803d 3130
2db3366b
PZ		 3131 intel_crtc->adjusted_x = x_offset;
3132 intel_crtc->adjusted_y = y_offset;
3133
70d21f0e 3134 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3135 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3136 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3137 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3138
3139 if (scaler_id >= 0) {
3140 uint32_t ps_ctrl = 0;
3141
3142 WARN_ON(!dst_w || !dst_h);
3143 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3144 crtc_state->scaler_state.scalers[scaler_id].mode;
3145 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3146 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3147 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3148 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3149 I915_WRITE(PLANE_POS(pipe, 0), 0);
3150 } else {
3151 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3152 }
3153
121920fa 3154 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3155
3156 POSTING_READ(PLANE_SURF(pipe, 0));
3157}
3158
17638cd6
JB		 3159/* Assume fb object is pinned & idle & fenced and just update base pointers */
3160static int
3161intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3162 int x, int y, enum mode_set_atomic state)
3163{
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3166
ff2a3117 3167 if (dev_priv->fbc.disable_fbc)
7733b49b 3168 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3169
29b9bde6
DV		 3170 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3171
3172 return 0;
81255565
JB		 3173}
3174
7514747d 3175static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3176{
96a02917
VS		 3177 struct drm_crtc *crtc;
3178
70e1e0ec 3179 for_each_crtc(dev, crtc) {
96a02917
VS		 3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181 enum plane plane = intel_crtc->plane;
3182
3183 intel_prepare_page_flip(dev, plane);
3184 intel_finish_page_flip_plane(dev, plane);
3185 }
7514747d
VS		 3186}
3187
3188static void intel_update_primary_planes(struct drm_device *dev)
3189{
7514747d 3190 struct drm_crtc *crtc;
96a02917 3191
70e1e0ec 3192 for_each_crtc(dev, crtc) {
11c22da6
ML		 3193 struct intel_plane *plane = to_intel_plane(crtc->primary);
3194 struct intel_plane_state *plane_state;
96a02917 3195
11c22da6 3196 drm_modeset_lock_crtc(crtc, &plane->base);
11c22da6
ML		 3197 plane_state = to_intel_plane_state(plane->base.state);
3198
f029ee82 3199 if (crtc->state->active && plane_state->base.fb)
11c22da6
ML		 3200 plane->commit_plane(&plane->base, plane_state);
3201
3202 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3203 }
3204}
3205
7514747d
VS		 3206void intel_prepare_reset(struct drm_device *dev)
3207{
3208 /* no reset support for gen2 */
3209 if (IS_GEN2(dev))
3210 return;
3211
3212 /* reset doesn't touch the display */
3213 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3214 return;
3215
3216 drm_modeset_lock_all(dev);
f98ce92f
VS		 3217 /*
3218 * Disabling the crtcs gracefully seems nicer. Also the
3219 * g33 docs say we should at least disable all the planes.
3220 */
6b72d486 3221 intel_display_suspend(dev);
7514747d
VS		 3222}
3223
3224void intel_finish_reset(struct drm_device *dev)
3225{
3226 struct drm_i915_private *dev_priv = to_i915(dev);
3227
3228 /*
3229 * Flips in the rings will be nuked by the reset,
3230 * so complete all pending flips so that user space
3231 * will get its events and not get stuck.
3232 */
3233 intel_complete_page_flips(dev);
3234
3235 /* no reset support for gen2 */
3236 if (IS_GEN2(dev))
3237 return;
3238
3239 /* reset doesn't touch the display */
3240 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3241 /*
3242 * Flips in the rings have been nuked by the reset,
3243 * so update the base address of all primary
3244 * planes to the the last fb to make sure we're
3245 * showing the correct fb after a reset.
11c22da6
ML		 3246 *
3247 * FIXME: Atomic will make this obsolete since we won't schedule
3248 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3249 */
3250 intel_update_primary_planes(dev);
3251 return;
3252 }
3253
3254 /*
3255 * The display has been reset as well,
3256 * so need a full re-initialization.
3257 */
3258 intel_runtime_pm_disable_interrupts(dev_priv);
3259 intel_runtime_pm_enable_interrupts(dev_priv);
3260
3261 intel_modeset_init_hw(dev);
3262
3263 spin_lock_irq(&dev_priv->irq_lock);
3264 if (dev_priv->display.hpd_irq_setup)
3265 dev_priv->display.hpd_irq_setup(dev);
3266 spin_unlock_irq(&dev_priv->irq_lock);
3267
043e9bda 3268 intel_display_resume(dev);
7514747d
VS		 3269
3270 intel_hpd_init(dev_priv);
3271
3272 drm_modeset_unlock_all(dev);
3273}
3274
7d5e3799
CW		 3275static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3280 bool pending;
3281
3282 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3283 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3284 return false;
3285
5e2d7afc 3286 spin_lock_irq(&dev->event_lock);
7d5e3799 3287 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3288 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3289
3290 return pending;
3291}
3292
bfd16b2a
ML		 3293static void intel_update_pipe_config(struct intel_crtc *crtc,
3294 struct intel_crtc_state *old_crtc_state)
e30e8f75
GP		 3295{
3296 struct drm_device *dev = crtc->base.dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
bfd16b2a
ML		 3298 struct intel_crtc_state *pipe_config =
3299 to_intel_crtc_state(crtc->base.state);
e30e8f75 3300
bfd16b2a
ML		 3301 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3302 crtc->base.mode = crtc->base.state->mode;
3303
3304 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3305 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3306 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
e30e8f75 3307
44522d85
ML		 3308 if (HAS_DDI(dev))
3309 intel_set_pipe_csc(&crtc->base);
3310
e30e8f75
GP		 3311 /*
3312 * Update pipe size and adjust fitter if needed: the reason for this is
3313 * that in compute_mode_changes we check the native mode (not the pfit
3314 * mode) to see if we can flip rather than do a full mode set. In the
3315 * fastboot case, we'll flip, but if we don't update the pipesrc and
3316 * pfit state, we'll end up with a big fb scanned out into the wrong
3317 * sized surface.
e30e8f75
GP		 3318 */
3319
e30e8f75 3320 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML		 3321 ((pipe_config->pipe_src_w - 1) << 16) |
3322 (pipe_config->pipe_src_h - 1));
3323
3324 /* on skylake this is done by detaching scalers */
3325 if (INTEL_INFO(dev)->gen >= 9) {
3326 skl_detach_scalers(crtc);
3327
3328 if (pipe_config->pch_pfit.enabled)
3329 skylake_pfit_enable(crtc);
3330 } else if (HAS_PCH_SPLIT(dev)) {
3331 if (pipe_config->pch_pfit.enabled)
3332 ironlake_pfit_enable(crtc);
3333 else if (old_crtc_state->pch_pfit.enabled)
3334 ironlake_pfit_disable(crtc, true);
e30e8f75 3335 }
e30e8f75
GP		 3336}
3337
5e84e1a4
ZW		 3338static void intel_fdi_normal_train(struct drm_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 int pipe = intel_crtc->pipe;
3344 u32 reg, temp;
3345
3346 /* enable normal train */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
61e499bf 3349 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3350 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3351 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3352 } else {
3353 temp &= ~FDI_LINK_TRAIN_NONE;
3354 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3355 }
5e84e1a4
ZW		 3356 I915_WRITE(reg, temp);
3357
3358 reg = FDI_RX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (HAS_PCH_CPT(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3362 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE;
3366 }
3367 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3368
3369 /* wait one idle pattern time */
3370 POSTING_READ(reg);
3371 udelay(1000);
357555c0
JB		 3372
3373 /* IVB wants error correction enabled */
3374 if (IS_IVYBRIDGE(dev))
3375 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3376 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3377}
3378
8db9d77b
ZW		 3379/* The FDI link training functions for ILK/Ibexpeak. */
3380static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3381{
3382 struct drm_device *dev = crtc->dev;
3383 struct drm_i915_private *dev_priv = dev->dev_private;
3384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3385 int pipe = intel_crtc->pipe;
5eddb70b 3386 u32 reg, temp, tries;
8db9d77b 3387
1c8562f6 3388 /* FDI needs bits from pipe first */
0fc932b8 3389 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3390
e1a44743
AJ		 3391 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3392 for train result */
5eddb70b
CW		 3393 reg = FDI_RX_IMR(pipe);
3394 temp = I915_READ(reg);
e1a44743
AJ		 3395 temp &= ~FDI_RX_SYMBOL_LOCK;
3396 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3397 I915_WRITE(reg, temp);
3398 I915_READ(reg);
e1a44743
AJ		 3399 udelay(150);
3400
8db9d77b 3401 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3402 reg = FDI_TX_CTL(pipe);
3403 temp = I915_READ(reg);
627eb5a3 3404 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3405 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3406 temp &= ~FDI_LINK_TRAIN_NONE;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3408 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3409
5eddb70b
CW		 3410 reg = FDI_RX_CTL(pipe);
3411 temp = I915_READ(reg);
8db9d77b
ZW		 3412 temp &= ~FDI_LINK_TRAIN_NONE;
3413 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3414 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3415
3416 POSTING_READ(reg);
8db9d77b
ZW		 3417 udelay(150);
3418
5b2adf89 3419 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3421 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3422 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3423
5eddb70b 3424 reg = FDI_RX_IIR(pipe);
e1a44743 3425 for (tries = 0; tries < 5; tries++) {
5eddb70b 3426 temp = I915_READ(reg);
8db9d77b
ZW		 3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429 if ((temp & FDI_RX_BIT_LOCK)) {
3430 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3431 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3432 break;
3433 }
8db9d77b 3434 }
e1a44743 3435 if (tries == 5)
5eddb70b 3436 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3437
3438 /* Train 2 */
5eddb70b
CW		 3439 reg = FDI_TX_CTL(pipe);
3440 temp = I915_READ(reg);
8db9d77b
ZW		 3441 temp &= ~FDI_LINK_TRAIN_NONE;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3443 I915_WRITE(reg, temp);
8db9d77b 3444
5eddb70b
CW		 3445 reg = FDI_RX_CTL(pipe);
3446 temp = I915_READ(reg);
8db9d77b
ZW		 3447 temp &= ~FDI_LINK_TRAIN_NONE;
3448 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3449 I915_WRITE(reg, temp);
8db9d77b 3450
5eddb70b
CW		 3451 POSTING_READ(reg);
3452 udelay(150);
8db9d77b 3453
5eddb70b 3454 reg = FDI_RX_IIR(pipe);
e1a44743 3455 for (tries = 0; tries < 5; tries++) {
5eddb70b 3456 temp = I915_READ(reg);
8db9d77b
ZW		 3457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3458
3459 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3460 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3461 DRM_DEBUG_KMS("FDI train 2 done.\n");
3462 break;
3463 }
8db9d77b 3464 }
e1a44743 3465 if (tries == 5)
5eddb70b 3466 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3467
3468 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3469
8db9d77b
ZW		 3470}
3471
0206e353 3472static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3473 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3474 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3475 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3476 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3477};
3478
3479/* The FDI link training functions for SNB/Cougarpoint. */
3480static void gen6_fdi_link_train(struct drm_crtc *crtc)
3481{
3482 struct drm_device *dev = crtc->dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485 int pipe = intel_crtc->pipe;
fa37d39e 3486 u32 reg, temp, i, retry;
8db9d77b 3487
e1a44743
AJ		 3488 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3489 for train result */
5eddb70b
CW		 3490 reg = FDI_RX_IMR(pipe);
3491 temp = I915_READ(reg);
e1a44743
AJ		 3492 temp &= ~FDI_RX_SYMBOL_LOCK;
3493 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3494 I915_WRITE(reg, temp);
3495
3496 POSTING_READ(reg);
e1a44743
AJ		 3497 udelay(150);
3498
8db9d77b 3499 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3500 reg = FDI_TX_CTL(pipe);
3501 temp = I915_READ(reg);
627eb5a3 3502 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3503 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3504 temp &= ~FDI_LINK_TRAIN_NONE;
3505 temp |= FDI_LINK_TRAIN_PATTERN_1;
3506 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3507 /* SNB-B */
3508 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3509 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3510
d74cf324
DV		 3511 I915_WRITE(FDI_RX_MISC(pipe),
3512 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3513
5eddb70b
CW		 3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
8db9d77b
ZW		 3516 if (HAS_PCH_CPT(dev)) {
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3519 } else {
3520 temp &= ~FDI_LINK_TRAIN_NONE;
3521 temp |= FDI_LINK_TRAIN_PATTERN_1;
3522 }
5eddb70b
CW		 3523 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3524
3525 POSTING_READ(reg);
8db9d77b
ZW		 3526 udelay(150);
3527
0206e353 3528 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3529 reg = FDI_TX_CTL(pipe);
3530 temp = I915_READ(reg);
8db9d77b
ZW		 3531 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3532 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3533 I915_WRITE(reg, temp);
3534
3535 POSTING_READ(reg);
8db9d77b
ZW		 3536 udelay(500);
3537
fa37d39e
SP		 3538 for (retry = 0; retry < 5; retry++) {
3539 reg = FDI_RX_IIR(pipe);
3540 temp = I915_READ(reg);
3541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3542 if (temp & FDI_RX_BIT_LOCK) {
3543 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3544 DRM_DEBUG_KMS("FDI train 1 done.\n");
3545 break;
3546 }
3547 udelay(50);
8db9d77b 3548 }
fa37d39e
SP		 3549 if (retry < 5)
3550 break;
8db9d77b
ZW		 3551 }
3552 if (i == 4)
5eddb70b 3553 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3554
3555 /* Train 2 */
5eddb70b
CW		 3556 reg = FDI_TX_CTL(pipe);
3557 temp = I915_READ(reg);
8db9d77b
ZW		 3558 temp &= ~FDI_LINK_TRAIN_NONE;
3559 temp |= FDI_LINK_TRAIN_PATTERN_2;
3560 if (IS_GEN6(dev)) {
3561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3562 /* SNB-B */
3563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3564 }
5eddb70b 3565 I915_WRITE(reg, temp);
8db9d77b 3566
5eddb70b
CW		 3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
8db9d77b
ZW		 3569 if (HAS_PCH_CPT(dev)) {
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3572 } else {
3573 temp &= ~FDI_LINK_TRAIN_NONE;
3574 temp |= FDI_LINK_TRAIN_PATTERN_2;
3575 }
5eddb70b
CW		 3576 I915_WRITE(reg, temp);
3577
3578 POSTING_READ(reg);
8db9d77b
ZW		 3579 udelay(150);
3580
0206e353 3581 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
8db9d77b
ZW		 3584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3585 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3586 I915_WRITE(reg, temp);
3587
3588 POSTING_READ(reg);
8db9d77b
ZW		 3589 udelay(500);
3590
fa37d39e
SP		 3591 for (retry = 0; retry < 5; retry++) {
3592 reg = FDI_RX_IIR(pipe);
3593 temp = I915_READ(reg);
3594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3595 if (temp & FDI_RX_SYMBOL_LOCK) {
3596 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3597 DRM_DEBUG_KMS("FDI train 2 done.\n");
3598 break;
3599 }
3600 udelay(50);
8db9d77b 3601 }
fa37d39e
SP		 3602 if (retry < 5)
3603 break;
8db9d77b
ZW		 3604 }
3605 if (i == 4)
5eddb70b 3606 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3607
3608 DRM_DEBUG_KMS("FDI train done.\n");
3609}
3610
357555c0
JB		 3611/* Manual link training for Ivy Bridge A0 parts */
3612static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3613{
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 int pipe = intel_crtc->pipe;
139ccd3f 3618 u32 reg, temp, i, j;
357555c0
JB		 3619
3620 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3621 for train result */
3622 reg = FDI_RX_IMR(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~FDI_RX_SYMBOL_LOCK;
3625 temp &= ~FDI_RX_BIT_LOCK;
3626 I915_WRITE(reg, temp);
3627
3628 POSTING_READ(reg);
3629 udelay(150);
3630
01a415fd
DV		 3631 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3632 I915_READ(FDI_RX_IIR(pipe)));
3633
139ccd3f
JB		 3634 /* Try each vswing and preemphasis setting twice before moving on */
3635 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3636 /* disable first in case we need to retry */
3637 reg = FDI_TX_CTL(pipe);
3638 temp = I915_READ(reg);
3639 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3640 temp &= ~FDI_TX_ENABLE;
3641 I915_WRITE(reg, temp);
357555c0 3642
139ccd3f
JB		 3643 reg = FDI_RX_CTL(pipe);
3644 temp = I915_READ(reg);
3645 temp &= ~FDI_LINK_TRAIN_AUTO;
3646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3647 temp &= ~FDI_RX_ENABLE;
3648 I915_WRITE(reg, temp);
357555c0 3649
139ccd3f 3650 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
139ccd3f 3653 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3654 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3655 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3657 temp |= snb_b_fdi_train_param[j/2];
3658 temp |= FDI_COMPOSITE_SYNC;
3659 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3660
139ccd3f
JB		 3661 I915_WRITE(FDI_RX_MISC(pipe),
3662 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3663
139ccd3f 3664 reg = FDI_RX_CTL(pipe);
357555c0 3665 temp = I915_READ(reg);
139ccd3f
JB		 3666 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3667 temp |= FDI_COMPOSITE_SYNC;
3668 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3669
139ccd3f
JB		 3670 POSTING_READ(reg);
3671 udelay(1); /* should be 0.5us */
357555c0 3672
139ccd3f
JB		 3673 for (i = 0; i < 4; i++) {
3674 reg = FDI_RX_IIR(pipe);
3675 temp = I915_READ(reg);
3676 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3677
139ccd3f
JB		 3678 if (temp & FDI_RX_BIT_LOCK ||
3679 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3680 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3681 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3682 i);
3683 break;
3684 }
3685 udelay(1); /* should be 0.5us */
3686 }
3687 if (i == 4) {
3688 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3689 continue;
3690 }
357555c0 3691
139ccd3f 3692 /* Train 2 */
357555c0
JB		 3693 reg = FDI_TX_CTL(pipe);
3694 temp = I915_READ(reg);
139ccd3f
JB		 3695 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3696 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3697 I915_WRITE(reg, temp);
3698
3699 reg = FDI_RX_CTL(pipe);
3700 temp = I915_READ(reg);
3701 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3702 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3703 I915_WRITE(reg, temp);
3704
3705 POSTING_READ(reg);
139ccd3f 3706 udelay(2); /* should be 1.5us */
357555c0 3707
139ccd3f
JB		 3708 for (i = 0; i < 4; i++) {
3709 reg = FDI_RX_IIR(pipe);
3710 temp = I915_READ(reg);
3711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3712
139ccd3f
JB		 3713 if (temp & FDI_RX_SYMBOL_LOCK ||
3714 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3715 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3716 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3717 i);
3718 goto train_done;
3719 }
3720 udelay(2); /* should be 1.5us */
357555c0 3721 }
139ccd3f
JB		 3722 if (i == 4)
3723 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3724 }
357555c0 3725
139ccd3f 3726train_done:
357555c0
JB		 3727 DRM_DEBUG_KMS("FDI train done.\n");
3728}
3729
88cefb6c 3730static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3731{
88cefb6c 3732 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3733 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3734 int pipe = intel_crtc->pipe;
5eddb70b 3735 u32 reg, temp;
79e53945 3736
c64e311e 3737
c98e9dcf 3738 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
627eb5a3 3741 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3742 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3743 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3744 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3745
3746 POSTING_READ(reg);
c98e9dcf
JB		 3747 udelay(200);
3748
3749 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3750 temp = I915_READ(reg);
3751 I915_WRITE(reg, temp | FDI_PCDCLK);
3752
3753 POSTING_READ(reg);
c98e9dcf
JB		 3754 udelay(200);
3755
20749730
PZ		 3756 /* Enable CPU FDI TX PLL, always on for Ironlake */
3757 reg = FDI_TX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3760 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3761
20749730
PZ		 3762 POSTING_READ(reg);
3763 udelay(100);
6be4a607 3764 }
0e23b99d
JB		 3765}
3766
88cefb6c
DV		 3767static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3768{
3769 struct drm_device *dev = intel_crtc->base.dev;
3770 struct drm_i915_private *dev_priv = dev->dev_private;
3771 int pipe = intel_crtc->pipe;
3772 u32 reg, temp;
3773
3774 /* Switch from PCDclk to Rawclk */
3775 reg = FDI_RX_CTL(pipe);
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3778
3779 /* Disable CPU FDI TX PLL */
3780 reg = FDI_TX_CTL(pipe);
3781 temp = I915_READ(reg);
3782 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3783
3784 POSTING_READ(reg);
3785 udelay(100);
3786
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3790
3791 /* Wait for the clocks to turn off. */
3792 POSTING_READ(reg);
3793 udelay(100);
3794}
3795
0fc932b8
JB		 3796static void ironlake_fdi_disable(struct drm_crtc *crtc)
3797{
3798 struct drm_device *dev = crtc->dev;
3799 struct drm_i915_private *dev_priv = dev->dev_private;
3800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3801 int pipe = intel_crtc->pipe;
3802 u32 reg, temp;
3803
3804 /* disable CPU FDI tx and PCH FDI rx */
3805 reg = FDI_TX_CTL(pipe);
3806 temp = I915_READ(reg);
3807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3808 POSTING_READ(reg);
3809
3810 reg = FDI_RX_CTL(pipe);
3811 temp = I915_READ(reg);
3812 temp &= ~(0x7 << 16);
dfd07d72 3813 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818
3819 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3820 if (HAS_PCH_IBX(dev))
6f06ce18 3821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3822
3823 /* still set train pattern 1 */
3824 reg = FDI_TX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 temp &= ~FDI_LINK_TRAIN_NONE;
3827 temp |= FDI_LINK_TRAIN_PATTERN_1;
3828 I915_WRITE(reg, temp);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 if (HAS_PCH_CPT(dev)) {
3833 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3835 } else {
3836 temp &= ~FDI_LINK_TRAIN_NONE;
3837 temp |= FDI_LINK_TRAIN_PATTERN_1;
3838 }
3839 /* BPC in FDI rx is consistent with that in PIPECONF */
3840 temp &= ~(0x07 << 16);
dfd07d72 3841 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3842 I915_WRITE(reg, temp);
3843
3844 POSTING_READ(reg);
3845 udelay(100);
3846}
3847
5dce5b93
CW		 3848bool intel_has_pending_fb_unpin(struct drm_device *dev)
3849{
3850 struct intel_crtc *crtc;
3851
3852 /* Note that we don't need to be called with mode_config.lock here
3853 * as our list of CRTC objects is static for the lifetime of the
3854 * device and so cannot disappear as we iterate. Similarly, we can
3855 * happily treat the predicates as racy, atomic checks as userspace
3856 * cannot claim and pin a new fb without at least acquring the
3857 * struct_mutex and so serialising with us.
3858 */
d3fcc808 3859 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3860 if (atomic_read(&crtc->unpin_work_count) == 0)
3861 continue;
3862
3863 if (crtc->unpin_work)
3864 intel_wait_for_vblank(dev, crtc->pipe);
3865
3866 return true;
3867 }
3868
3869 return false;
3870}
3871
d6bbafa1
CW		 3872static void page_flip_completed(struct intel_crtc *intel_crtc)
3873{
3874 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3875 struct intel_unpin_work *work = intel_crtc->unpin_work;
3876
3877 /* ensure that the unpin work is consistent wrt ->pending. */
3878 smp_rmb();
3879 intel_crtc->unpin_work = NULL;
3880
3881 if (work->event)
3882 drm_send_vblank_event(intel_crtc->base.dev,
3883 intel_crtc->pipe,
3884 work->event);
3885
3886 drm_crtc_vblank_put(&intel_crtc->base);
3887
3888 wake_up_all(&dev_priv->pending_flip_queue);
3889 queue_work(dev_priv->wq, &work->work);
3890
3891 trace_i915_flip_complete(intel_crtc->plane,
3892 work->pending_flip_obj);
3893}
3894
5008e874 3895static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3896{
0f91128d 3897 struct drm_device *dev = crtc->dev;
5bb61643 3898 struct drm_i915_private *dev_priv = dev->dev_private;
5008e874 3899 long ret;
e6c3a2a6 3900
2c10d571 3901 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML		 3902
3903 ret = wait_event_interruptible_timeout(
3904 dev_priv->pending_flip_queue,
3905 !intel_crtc_has_pending_flip(crtc),
3906 60*HZ);
3907
3908 if (ret < 0)
3909 return ret;
3910
3911 if (ret == 0) {
9c787942 3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3913
5e2d7afc 3914 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3915 if (intel_crtc->unpin_work) {
3916 WARN_ONCE(1, "Removing stuck page flip\n");
3917 page_flip_completed(intel_crtc);
3918 }
5e2d7afc 3919 spin_unlock_irq(&dev->event_lock);
9c787942 3920 }
5bb61643 3921
5008e874 3922 return 0;
e6c3a2a6
CW		 3923}
3924
e615efe4
ED		 3925/* Program iCLKIP clock to the desired frequency */
3926static void lpt_program_iclkip(struct drm_crtc *crtc)
3927{
3928 struct drm_device *dev = crtc->dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3930 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3931 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3932 u32 temp;
3933
a580516d 3934 mutex_lock(&dev_priv->sb_lock);
09153000 3935
e615efe4
ED		 3936 /* It is necessary to ungate the pixclk gate prior to programming
3937 * the divisors, and gate it back when it is done.
3938 */
3939 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3940
3941 /* Disable SSCCTL */
3942 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3943 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3944 SBI_SSCCTL_DISABLE,
3945 SBI_ICLK);
e615efe4
ED		 3946
3947 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3948 if (clock == 20000) {
e615efe4
ED		 3949 auxdiv = 1;
3950 divsel = 0x41;
3951 phaseinc = 0x20;
3952 } else {
3953 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3954 * but the adjusted_mode->crtc_clock in in KHz. To get the
3955 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3956 * convert the virtual clock precision to KHz here for higher
3957 * precision.
3958 */
3959 u32 iclk_virtual_root_freq = 172800 * 1000;
3960 u32 iclk_pi_range = 64;
3961 u32 desired_divisor, msb_divisor_value, pi_value;
3962
12d7ceed 3963 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3964 msb_divisor_value = desired_divisor / iclk_pi_range;
3965 pi_value = desired_divisor % iclk_pi_range;
3966
3967 auxdiv = 0;
3968 divsel = msb_divisor_value - 2;
3969 phaseinc = pi_value;
3970 }
3971
3972 /* This should not happen with any sane values */
3973 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3974 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3975 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3976 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3977
3978 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3979 clock,
e615efe4
ED		 3980 auxdiv,
3981 divsel,
3982 phasedir,
3983 phaseinc);
3984
3985 /* Program SSCDIVINTPHASE6 */
988d6ee8 3986 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3987 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3988 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3989 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3990 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3991 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3992 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3993 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3994
3995 /* Program SSCAUXDIV */
988d6ee8 3996 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3997 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3998 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3999 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4000
4001 /* Enable modulator and associated divider */
988d6ee8 4002 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4003 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4004 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4005
4006 /* Wait for initialization time */
4007 udelay(24);
4008
4009 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4010
a580516d 4011 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4012}
4013
275f01b2
DV		 4014static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4015 enum pipe pch_transcoder)
4016{
4017 struct drm_device *dev = crtc->base.dev;
4018 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4019 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4020
4021 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4022 I915_READ(HTOTAL(cpu_transcoder)));
4023 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4024 I915_READ(HBLANK(cpu_transcoder)));
4025 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4026 I915_READ(HSYNC(cpu_transcoder)));
4027
4028 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4029 I915_READ(VTOTAL(cpu_transcoder)));
4030 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4031 I915_READ(VBLANK(cpu_transcoder)));
4032 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4033 I915_READ(VSYNC(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4035 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4036}
4037
003632d9 4038static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4039{
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 uint32_t temp;
4042
4043 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4044 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4045 return;
4046
4047 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4048 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4049
003632d9
ACO		 4050 temp &= ~FDI_BC_BIFURCATION_SELECT;
4051 if (enable)
4052 temp |= FDI_BC_BIFURCATION_SELECT;
4053
4054 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4055 I915_WRITE(SOUTH_CHICKEN1, temp);
4056 POSTING_READ(SOUTH_CHICKEN1);
4057}
4058
4059static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4060{
4061 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4062
4063 switch (intel_crtc->pipe) {
4064 case PIPE_A:
4065 break;
4066 case PIPE_B:
6e3c9717 4067 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4068 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4069 else
003632d9 4070 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4071
4072 break;
4073 case PIPE_C:
003632d9 4074 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4075
4076 break;
4077 default:
4078 BUG();
4079 }
4080}
4081
f67a559d
JB		 4082/*
4083 * Enable PCH resources required for PCH ports:
4084 * - PCH PLLs
4085 * - FDI training & RX/TX
4086 * - update transcoder timings
4087 * - DP transcoding bits
4088 * - transcoder
4089 */
4090static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4091{
4092 struct drm_device *dev = crtc->dev;
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4095 int pipe = intel_crtc->pipe;
ee7b9f93 4096 u32 reg, temp;
2c07245f 4097
ab9412ba 4098 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4099
1fbc0d78
DV		 4100 if (IS_IVYBRIDGE(dev))
4101 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4102
cd986abb
DV		 4103 /* Write the TU size bits before fdi link training, so that error
4104 * detection works. */
4105 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4106 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4107
c98e9dcf 4108 /* For PCH output, training FDI link */
674cf967 4109 dev_priv->display.fdi_link_train(crtc);
2c07245f 4110
3ad8a208
DV		 4111 /* We need to program the right clock selection before writing the pixel
4112 * mutliplier into the DPLL. */
303b81e0 4113 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4114 u32 sel;
4b645f14 4115
c98e9dcf 4116 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4117 temp |= TRANS_DPLL_ENABLE(pipe);
4118 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4119 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4120 temp |= sel;
4121 else
4122 temp &= ~sel;
c98e9dcf 4123 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4124 }
5eddb70b 4125
3ad8a208
DV		 4126 /* XXX: pch pll's can be enabled any time before we enable the PCH
4127 * transcoder, and we actually should do this to not upset any PCH
4128 * transcoder that already use the clock when we share it.
4129 *
4130 * Note that enable_shared_dpll tries to do the right thing, but
4131 * get_shared_dpll unconditionally resets the pll - we need that to have
4132 * the right LVDS enable sequence. */
85b3894f 4133 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4134
d9b6cb56
JB		 4135 /* set transcoder timing, panel must allow it */
4136 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4137 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4138
303b81e0 4139 intel_fdi_normal_train(crtc);
5e84e1a4 4140
c98e9dcf 4141 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4142 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4143 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4144 reg = TRANS_DP_CTL(pipe);
4145 temp = I915_READ(reg);
4146 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4147 TRANS_DP_SYNC_MASK |
4148 TRANS_DP_BPC_MASK);
e3ef4479 4149 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4150 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4151
4152 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4153 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4154 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4155 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4156
4157 switch (intel_trans_dp_port_sel(crtc)) {
4158 case PCH_DP_B:
5eddb70b 4159 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4160 break;
4161 case PCH_DP_C:
5eddb70b 4162 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4163 break;
4164 case PCH_DP_D:
5eddb70b 4165 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4166 break;
4167 default:
e95d41e1 4168 BUG();
32f9d658 4169 }
2c07245f 4170
5eddb70b 4171 I915_WRITE(reg, temp);
6be4a607 4172 }
b52eb4dc 4173
b8a4f404 4174 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4175}
4176
1507e5bd
PZ		 4177static void lpt_pch_enable(struct drm_crtc *crtc)
4178{
4179 struct drm_device *dev = crtc->dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4182 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4183
ab9412ba 4184 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4185
8c52b5e8 4186 lpt_program_iclkip(crtc);
1507e5bd 4187
0540e488 4188 /* Set transcoder timing. */
275f01b2 4189 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4190
937bb610 4191 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4192}
4193
190f68c5
ACO		 4194struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4195 struct intel_crtc_state *crtc_state)
ee7b9f93 4196{
e2b78267 4197 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4198 struct intel_shared_dpll *pll;
de419ab6 4199 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4200 enum intel_dpll_id i;
ee7b9f93 4201
de419ab6
ML		 4202 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4203
98b6bd99
DV		 4204 if (HAS_PCH_IBX(dev_priv->dev)) {
4205 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4206 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4207 pll = &dev_priv->shared_dplls[i];
98b6bd99 4208
46edb027
DV		 4209 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4210 crtc->base.base.id, pll->name);
98b6bd99 4211
de419ab6 4212 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4213
98b6bd99
DV		 4214 goto found;
4215 }
4216
bcddf610
S		 4217 if (IS_BROXTON(dev_priv->dev)) {
4218 /* PLL is attached to port in bxt */
4219 struct intel_encoder *encoder;
4220 struct intel_digital_port *intel_dig_port;
4221
4222 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4223 if (WARN_ON(!encoder))
4224 return NULL;
4225
4226 intel_dig_port = enc_to_dig_port(&encoder->base);
4227 /* 1:1 mapping between ports and PLLs */
4228 i = (enum intel_dpll_id)intel_dig_port->port;
4229 pll = &dev_priv->shared_dplls[i];
4230 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4231 crtc->base.base.id, pll->name);
de419ab6 4232 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4233
4234 goto found;
4235 }
4236
e72f9fbf
DV		 4237 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4238 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4239
4240 /* Only want to check enabled timings first */
de419ab6 4241 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4242 continue;
4243
190f68c5 4244 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4245 &shared_dpll[i].hw_state,
4246 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4247 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4248 crtc->base.base.id, pll->name,
de419ab6 4249 shared_dpll[i].crtc_mask,
8bd31e67 4250 pll->active);
ee7b9f93
JB		 4251 goto found;
4252 }
4253 }
4254
4255 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4256 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4257 pll = &dev_priv->shared_dplls[i];
de419ab6 4258 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4259 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4260 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4261 goto found;
4262 }
4263 }
4264
4265 return NULL;
4266
4267found:
de419ab6
ML		 4268 if (shared_dpll[i].crtc_mask == 0)
4269 shared_dpll[i].hw_state =
4270 crtc_state->dpll_hw_state;
f2a69f44 4271
190f68c5 4272 crtc_state->shared_dpll = i;
46edb027
DV		 4273 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4274 pipe_name(crtc->pipe));
ee7b9f93 4275
de419ab6 4276 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4277
ee7b9f93
JB		 4278 return pll;
4279}
4280
de419ab6 4281static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4282{
de419ab6
ML		 4283 struct drm_i915_private *dev_priv = to_i915(state->dev);
4284 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4285 struct intel_shared_dpll *pll;
4286 enum intel_dpll_id i;
4287
de419ab6
ML		 4288 if (!to_intel_atomic_state(state)->dpll_set)
4289 return;
8bd31e67 4290
de419ab6 4291 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4292 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4293 pll = &dev_priv->shared_dplls[i];
de419ab6 4294 pll->config = shared_dpll[i];
8bd31e67
ACO		 4295 }
4296}
4297
a1520318 4298static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4299{
4300 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4301 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4302 u32 temp;
4303
4304 temp = I915_READ(dslreg);
4305 udelay(500);
4306 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4307 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4308 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4309 }
4310}
4311
86adf9d7
ML		 4312static int
4313skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4314 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4315 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4316{
86adf9d7
ML		 4317 struct intel_crtc_scaler_state *scaler_state =
4318 &crtc_state->scaler_state;
4319 struct intel_crtc *intel_crtc =
4320 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4321 int need_scaling;
6156a456
CK		 4322
4323 need_scaling = intel_rotation_90_or_270(rotation) ?
4324 (src_h != dst_w || src_w != dst_h):
4325 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4326
4327 /*
4328 * if plane is being disabled or scaler is no more required or force detach
4329 * - free scaler binded to this plane/crtc
4330 * - in order to do this, update crtc->scaler_usage
4331 *
4332 * Here scaler state in crtc_state is set free so that
4333 * scaler can be assigned to other user. Actual register
4334 * update to free the scaler is done in plane/panel-fit programming.
4335 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4336 */
86adf9d7 4337 if (force_detach || !need_scaling) {
a1b2278e 4338 if (*scaler_id >= 0) {
86adf9d7 4339 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4340 scaler_state->scalers[*scaler_id].in_use = 0;
4341
86adf9d7
ML		 4342 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4343 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4344 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4345 scaler_state->scaler_users);
4346 *scaler_id = -1;
4347 }
4348 return 0;
4349 }
4350
4351 /* range checks */
4352 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4353 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4354
4355 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4356 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4357 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4358 "size is out of scaler range\n",
86adf9d7 4359 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4360 return -EINVAL;
4361 }
4362
86adf9d7
ML		 4363 /* mark this plane as a scaler user in crtc_state */
4364 scaler_state->scaler_users |= (1 << scaler_user);
4365 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4366 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4367 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4368 scaler_state->scaler_users);
4369
4370 return 0;
4371}
4372
4373/**
4374 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4375 *
4376 * @state: crtc's scaler state
86adf9d7
ML		 4377 *
4378 * Return
4379 * 0 - scaler_usage updated successfully
4380 * error - requested scaling cannot be supported or other error condition
4381 */
e435d6e5 4382int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4383{
4384 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
7c5f93b0 4385 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7
ML		 4386
4387 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4388 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4389
e435d6e5 4390 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4391 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4392 state->pipe_src_w, state->pipe_src_h,
aad941d5 4393 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML		 4394}
4395
4396/**
4397 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4398 *
4399 * @state: crtc's scaler state
86adf9d7
ML		 4400 * @plane_state: atomic plane state to update
4401 *
4402 * Return
4403 * 0 - scaler_usage updated successfully
4404 * error - requested scaling cannot be supported or other error condition
4405 */
da20eabd
ML		 4406static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4407 struct intel_plane_state *plane_state)
86adf9d7
ML		 4408{
4409
4410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4411 struct intel_plane *intel_plane =
4412 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4413 struct drm_framebuffer *fb = plane_state->base.fb;
4414 int ret;
4415
4416 bool force_detach = !fb || !plane_state->visible;
4417
4418 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4419 intel_plane->base.base.id, intel_crtc->pipe,
4420 drm_plane_index(&intel_plane->base));
4421
4422 ret = skl_update_scaler(crtc_state, force_detach,
4423 drm_plane_index(&intel_plane->base),
4424 &plane_state->scaler_id,
4425 plane_state->base.rotation,
4426 drm_rect_width(&plane_state->src) >> 16,
4427 drm_rect_height(&plane_state->src) >> 16,
4428 drm_rect_width(&plane_state->dst),
4429 drm_rect_height(&plane_state->dst));
4430
4431 if (ret || plane_state->scaler_id < 0)
4432 return ret;
4433
a1b2278e 4434 /* check colorkey */
818ed961 4435 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4436 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4437 intel_plane->base.base.id);
a1b2278e
CK		 4438 return -EINVAL;
4439 }
4440
4441 /* Check src format */
86adf9d7
ML		 4442 switch (fb->pixel_format) {
4443 case DRM_FORMAT_RGB565:
4444 case DRM_FORMAT_XBGR8888:
4445 case DRM_FORMAT_XRGB8888:
4446 case DRM_FORMAT_ABGR8888:
4447 case DRM_FORMAT_ARGB8888:
4448 case DRM_FORMAT_XRGB2101010:
4449 case DRM_FORMAT_XBGR2101010:
4450 case DRM_FORMAT_YUYV:
4451 case DRM_FORMAT_YVYU:
4452 case DRM_FORMAT_UYVY:
4453 case DRM_FORMAT_VYUY:
4454 break;
4455 default:
4456 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4457 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4458 return -EINVAL;
a1b2278e
CK		 4459 }
4460
a1b2278e
CK		 4461 return 0;
4462}
4463
e435d6e5
ML		 4464static void skylake_scaler_disable(struct intel_crtc *crtc)
4465{
4466 int i;
4467
4468 for (i = 0; i < crtc->num_scalers; i++)
4469 skl_detach_scaler(crtc, i);
4470}
4471
4472static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4473{
4474 struct drm_device *dev = crtc->base.dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 int pipe = crtc->pipe;
a1b2278e
CK		 4477 struct intel_crtc_scaler_state *scaler_state =
4478 &crtc->config->scaler_state;
4479
4480 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4481
6e3c9717 4482 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4483 int id;
4484
4485 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4486 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4487 return;
4488 }
4489
4490 id = scaler_state->scaler_id;
4491 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4492 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4493 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4494 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4495
4496 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4497 }
4498}
4499
b074cec8
JB		 4500static void ironlake_pfit_enable(struct intel_crtc *crtc)
4501{
4502 struct drm_device *dev = crtc->base.dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 int pipe = crtc->pipe;
4505
6e3c9717 4506 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4507 /* Force use of hard-coded filter coefficients
4508 * as some pre-programmed values are broken,
4509 * e.g. x201.
4510 */
4511 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4512 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4513 PF_PIPE_SEL_IVB(pipe));
4514 else
4515 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4516 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4517 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4518 }
4519}
4520
20bc8673 4521void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4522{
cea165c3
VS		 4523 struct drm_device *dev = crtc->base.dev;
4524 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4525
6e3c9717 4526 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4527 return;
4528
cea165c3
VS		 4529 /* We can only enable IPS after we enable a plane and wait for a vblank */
4530 intel_wait_for_vblank(dev, crtc->pipe);
4531
d77e4531 4532 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4533 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4534 mutex_lock(&dev_priv->rps.hw_lock);
4535 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4536 mutex_unlock(&dev_priv->rps.hw_lock);
4537 /* Quoting Art Runyan: "its not safe to expect any particular
4538 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4539 * mailbox." Moreover, the mailbox may return a bogus state,
4540 * so we need to just enable it and continue on.
2a114cc1
BW		 4541 */
4542 } else {
4543 I915_WRITE(IPS_CTL, IPS_ENABLE);
4544 /* The bit only becomes 1 in the next vblank, so this wait here
4545 * is essentially intel_wait_for_vblank. If we don't have this
4546 * and don't wait for vblanks until the end of crtc_enable, then
4547 * the HW state readout code will complain that the expected
4548 * IPS_CTL value is not the one we read. */
4549 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4550 DRM_ERROR("Timed out waiting for IPS enable\n");
4551 }
d77e4531
PZ		 4552}
4553
20bc8673 4554void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4555{
4556 struct drm_device *dev = crtc->base.dev;
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558
6e3c9717 4559 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4560 return;
4561
4562 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4563 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4564 mutex_lock(&dev_priv->rps.hw_lock);
4565 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4566 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4567 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4568 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4569 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4570 } else {
2a114cc1 4571 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4572 POSTING_READ(IPS_CTL);
4573 }
d77e4531
PZ		 4574
4575 /* We need to wait for a vblank before we can disable the plane. */
4576 intel_wait_for_vblank(dev, crtc->pipe);
4577}
4578
4579/** Loads the palette/gamma unit for the CRTC with the prepared values */
4580static void intel_crtc_load_lut(struct drm_crtc *crtc)
4581{
4582 struct drm_device *dev = crtc->dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4585 enum pipe pipe = intel_crtc->pipe;
d77e4531
PZ		 4586 int i;
4587 bool reenable_ips = false;
4588
4589 /* The clocks have to be on to load the palette. */
53d9f4e9 4590 if (!crtc->state->active)
d77e4531
PZ		 4591 return;
4592
50360403 4593 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4594 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4595 assert_dsi_pll_enabled(dev_priv);
4596 else
4597 assert_pll_enabled(dev_priv, pipe);
4598 }
4599
d77e4531
PZ		 4600 /* Workaround : Do not read or write the pipe palette/gamma data while
4601 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4602 */
6e3c9717 4603 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4604 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4605 GAMMA_MODE_MODE_SPLIT)) {
4606 hsw_disable_ips(intel_crtc);
4607 reenable_ips = true;
4608 }
4609
4610 for (i = 0; i < 256; i++) {
f65a9c5b
VS		 4611 u32 palreg;
4612
4613 if (HAS_GMCH_DISPLAY(dev))
4614 palreg = PALETTE(pipe, i);
4615 else
4616 palreg = LGC_PALETTE(pipe, i);
4617
4618 I915_WRITE(palreg,
d77e4531
PZ		 4619 (intel_crtc->lut_r[i] << 16) |
4620 (intel_crtc->lut_g[i] << 8) |
4621 intel_crtc->lut_b[i]);
4622 }
4623
4624 if (reenable_ips)
4625 hsw_enable_ips(intel_crtc);
4626}
4627
7cac945f 4628static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4629{
7cac945f 4630 if (intel_crtc->overlay) {
d3eedb1a
VS		 4631 struct drm_device *dev = intel_crtc->base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633
4634 mutex_lock(&dev->struct_mutex);
4635 dev_priv->mm.interruptible = false;
4636 (void) intel_overlay_switch_off(intel_crtc->overlay);
4637 dev_priv->mm.interruptible = true;
4638 mutex_unlock(&dev->struct_mutex);
4639 }
4640
4641 /* Let userspace switch the overlay on again. In most cases userspace
4642 * has to recompute where to put it anyway.
4643 */
4644}
4645
87d4300a
ML		 4646/**
4647 * intel_post_enable_primary - Perform operations after enabling primary plane
4648 * @crtc: the CRTC whose primary plane was just enabled
4649 *
4650 * Performs potentially sleeping operations that must be done after the primary
4651 * plane is enabled, such as updating FBC and IPS. Note that this may be
4652 * called due to an explicit primary plane update, or due to an implicit
4653 * re-enable that is caused when a sprite plane is updated to no longer
4654 * completely hide the primary plane.
4655 */
4656static void
4657intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4658{
4659 struct drm_device *dev = crtc->dev;
87d4300a 4660 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4662 int pipe = intel_crtc->pipe;
a5c4d7bc 4663
87d4300a
ML		 4664 /*
4665 * BDW signals flip done immediately if the plane
4666 * is disabled, even if the plane enable is already
4667 * armed to occur at the next vblank :(
4668 */
4669 if (IS_BROADWELL(dev))
4670 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4671
87d4300a
ML		 4672 /*
4673 * FIXME IPS should be fine as long as one plane is
4674 * enabled, but in practice it seems to have problems
4675 * when going from primary only to sprite only and vice
4676 * versa.
4677 */
a5c4d7bc
VS		 4678 hsw_enable_ips(intel_crtc);
4679
f99d7069 4680 /*
87d4300a
ML		 4681 * Gen2 reports pipe underruns whenever all planes are disabled.
4682 * So don't enable underrun reporting before at least some planes
4683 * are enabled.
4684 * FIXME: Need to fix the logic to work when we turn off all planes
4685 * but leave the pipe running.
f99d7069 4686 */
87d4300a
ML		 4687 if (IS_GEN2(dev))
4688 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4689
4690 /* Underruns don't raise interrupts, so check manually. */
4691 if (HAS_GMCH_DISPLAY(dev))
4692 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4693}
4694
87d4300a
ML		 4695/**
4696 * intel_pre_disable_primary - Perform operations before disabling primary plane
4697 * @crtc: the CRTC whose primary plane is to be disabled
4698 *
4699 * Performs potentially sleeping operations that must be done before the
4700 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4701 * be called due to an explicit primary plane update, or due to an implicit
4702 * disable that is caused when a sprite plane completely hides the primary
4703 * plane.
4704 */
4705static void
4706intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4707{
4708 struct drm_device *dev = crtc->dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4711 int pipe = intel_crtc->pipe;
a5c4d7bc 4712
87d4300a
ML		 4713 /*
4714 * Gen2 reports pipe underruns whenever all planes are disabled.
4715 * So diasble underrun reporting before all the planes get disabled.
4716 * FIXME: Need to fix the logic to work when we turn off all planes
4717 * but leave the pipe running.
4718 */
4719 if (IS_GEN2(dev))
4720 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4721
87d4300a
ML		 4722 /*
4723 * Vblank time updates from the shadow to live plane control register
4724 * are blocked if the memory self-refresh mode is active at that
4725 * moment. So to make sure the plane gets truly disabled, disable
4726 * first the self-refresh mode. The self-refresh enable bit in turn
4727 * will be checked/applied by the HW only at the next frame start
4728 * event which is after the vblank start event, so we need to have a
4729 * wait-for-vblank between disabling the plane and the pipe.
4730 */
262cd2e1 4731 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4732 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4733 dev_priv->wm.vlv.cxsr = false;
4734 intel_wait_for_vblank(dev, pipe);
4735 }
87d4300a 4736
87d4300a
ML		 4737 /*
4738 * FIXME IPS should be fine as long as one plane is
4739 * enabled, but in practice it seems to have problems
4740 * when going from primary only to sprite only and vice
4741 * versa.
4742 */
a5c4d7bc 4743 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4744}
4745
ac21b225
ML		 4746static void intel_post_plane_update(struct intel_crtc *crtc)
4747{
4748 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4749 struct drm_device *dev = crtc->base.dev;
7733b49b 4750 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4751
4752 if (atomic->wait_vblank)
4753 intel_wait_for_vblank(dev, crtc->pipe);
4754
4755 intel_frontbuffer_flip(dev, atomic->fb_bits);
4756
852eb00d
VS		 4757 if (atomic->disable_cxsr)
4758 crtc->wm.cxsr_allowed = true;
4759
f015c551
VS		 4760 if (crtc->atomic.update_wm_post)
4761 intel_update_watermarks(&crtc->base);
4762
c80ac854 4763 if (atomic->update_fbc)
7733b49b 4764 intel_fbc_update(dev_priv);
ac21b225
ML		 4765
4766 if (atomic->post_enable_primary)
4767 intel_post_enable_primary(&crtc->base);
4768
ac21b225
ML		 4769 memset(atomic, 0, sizeof(*atomic));
4770}
4771
4772static void intel_pre_plane_update(struct intel_crtc *crtc)
4773{
4774 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4775 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225 4776 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
ac21b225 4777
c80ac854 4778 if (atomic->disable_fbc)
25ad93fd 4779 intel_fbc_disable_crtc(crtc);
ac21b225 4780
066cf55b
RV		 4781 if (crtc->atomic.disable_ips)
4782 hsw_disable_ips(crtc);
4783
ac21b225
ML		 4784 if (atomic->pre_disable_primary)
4785 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4786
4787 if (atomic->disable_cxsr) {
4788 crtc->wm.cxsr_allowed = false;
4789 intel_set_memory_cxsr(dev_priv, false);
4790 }
ac21b225
ML		 4791}
4792
d032ffa0 4793static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4794{
4795 struct drm_device *dev = crtc->dev;
4796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4797 struct drm_plane *p;
87d4300a
ML		 4798 int pipe = intel_crtc->pipe;
4799
7cac945f 4800 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4801
d032ffa0
ML		 4802 drm_for_each_plane_mask(p, dev, plane_mask)
4803 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4804
f99d7069
DV		 4805 /*
4806 * FIXME: Once we grow proper nuclear flip support out of this we need
4807 * to compute the mask of flip planes precisely. For the time being
4808 * consider this a flip to a NULL plane.
4809 */
4810 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4811}
4812
f67a559d
JB		 4813static void ironlake_crtc_enable(struct drm_crtc *crtc)
4814{
4815 struct drm_device *dev = crtc->dev;
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4818 struct intel_encoder *encoder;
f67a559d 4819 int pipe = intel_crtc->pipe;
f67a559d 4820
53d9f4e9 4821 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4822 return;
4823
6e3c9717 4824 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4825 intel_prepare_shared_dpll(intel_crtc);
4826
6e3c9717 4827 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4828 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4829
4830 intel_set_pipe_timings(intel_crtc);
4831
6e3c9717 4832 if (intel_crtc->config->has_pch_encoder) {
29407aab 4833 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4834 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4835 }
4836
4837 ironlake_set_pipeconf(crtc);
4838
f67a559d 4839 intel_crtc->active = true;
8664281b 4840
a72e4c9f
DV		 4841 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4842 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4843
f6736a1a 4844 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4845 if (encoder->pre_enable)
4846 encoder->pre_enable(encoder);
f67a559d 4847
6e3c9717 4848 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4849 /* Note: FDI PLL enabling _must_ be done before we enable the
4850 * cpu pipes, hence this is separate from all the other fdi/pch
4851 * enabling. */
88cefb6c 4852 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4853 } else {
4854 assert_fdi_tx_disabled(dev_priv, pipe);
4855 assert_fdi_rx_disabled(dev_priv, pipe);
4856 }
f67a559d 4857
b074cec8 4858 ironlake_pfit_enable(intel_crtc);
f67a559d 4859
9c54c0dd
JB		 4860 /*
4861 * On ILK+ LUT must be loaded before the pipe is running but with
4862 * clocks enabled
4863 */
4864 intel_crtc_load_lut(crtc);
4865
f37fcc2a 4866 intel_update_watermarks(crtc);
e1fdc473 4867 intel_enable_pipe(intel_crtc);
f67a559d 4868
6e3c9717 4869 if (intel_crtc->config->has_pch_encoder)
f67a559d 4870 ironlake_pch_enable(crtc);
c98e9dcf 4871
f9b61ff6
DV		 4872 assert_vblank_disabled(crtc);
4873 drm_crtc_vblank_on(crtc);
4874
fa5c73b1
DV		 4875 for_each_encoder_on_crtc(dev, crtc, encoder)
4876 encoder->enable(encoder);
61b77ddd
DV		 4877
4878 if (HAS_PCH_CPT(dev))
a1520318 4879 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4880}
4881
42db64ef
PZ		 4882/* IPS only exists on ULT machines and is tied to pipe A. */
4883static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4884{
f5adf94e 4885 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4886}
4887
4f771f10
PZ		 4888static void haswell_crtc_enable(struct drm_crtc *crtc)
4889{
4890 struct drm_device *dev = crtc->dev;
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4893 struct intel_encoder *encoder;
99d736a2
ML		 4894 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4895 struct intel_crtc_state *pipe_config =
4896 to_intel_crtc_state(crtc->state);
7d4aefd0 4897 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4f771f10 4898
53d9f4e9 4899 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4900 return;
4901
df8ad70c
DV		 4902 if (intel_crtc_to_shared_dpll(intel_crtc))
4903 intel_enable_shared_dpll(intel_crtc);
4904
6e3c9717 4905 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4906 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4907
4908 intel_set_pipe_timings(intel_crtc);
4909
6e3c9717
ACO		 4910 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4911 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4912 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4913 }
4914
6e3c9717 4915 if (intel_crtc->config->has_pch_encoder) {
229fca97 4916 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4917 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4918 }
4919
4920 haswell_set_pipeconf(crtc);
4921
4922 intel_set_pipe_csc(crtc);
4923
4f771f10 4924 intel_crtc->active = true;
8664281b 4925
a72e4c9f 4926 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
7d4aefd0
SS		 4927 for_each_encoder_on_crtc(dev, crtc, encoder) {
4928 if (encoder->pre_pll_enable)
4929 encoder->pre_pll_enable(encoder);
4f771f10
PZ		 4930 if (encoder->pre_enable)
4931 encoder->pre_enable(encoder);
7d4aefd0 4932 }
4f771f10 4933
6e3c9717 4934 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4935 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4936 true);
4fe9467d
ID		 4937 dev_priv->display.fdi_link_train(crtc);
4938 }
4939
7d4aefd0
SS		 4940 if (!is_dsi)
4941 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4942
1c132b44 4943 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4944 skylake_pfit_enable(intel_crtc);
ff6d9f55 4945 else
1c132b44 4946 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4947
4948 /*
4949 * On ILK+ LUT must be loaded before the pipe is running but with
4950 * clocks enabled
4951 */
4952 intel_crtc_load_lut(crtc);
4953
1f544388 4954 intel_ddi_set_pipe_settings(crtc);
7d4aefd0
SS		 4955 if (!is_dsi)
4956 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4957
f37fcc2a 4958 intel_update_watermarks(crtc);
e1fdc473 4959 intel_enable_pipe(intel_crtc);
42db64ef 4960
6e3c9717 4961 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4962 lpt_pch_enable(crtc);
4f771f10 4963
7d4aefd0 4964 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
0e32b39c
DA		 4965 intel_ddi_set_vc_payload_alloc(crtc, true);
4966
f9b61ff6
DV		 4967 assert_vblank_disabled(crtc);
4968 drm_crtc_vblank_on(crtc);
4969
8807e55b 4970 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4971 encoder->enable(encoder);
8807e55b
JN		 4972 intel_opregion_notify_encoder(encoder, true);
4973 }
4f771f10 4974
e4916946
PZ		 4975 /* If we change the relative order between pipe/planes enabling, we need
4976 * to change the workaround. */
99d736a2
ML		 4977 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4978 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4979 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4980 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4981 }
4f771f10
PZ		 4982}
4983
bfd16b2a 4984static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV		 4985{
4986 struct drm_device *dev = crtc->base.dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 int pipe = crtc->pipe;
4989
4990 /* To avoid upsetting the power well on haswell only disable the pfit if
4991 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 4992 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4993 I915_WRITE(PF_CTL(pipe), 0);
4994 I915_WRITE(PF_WIN_POS(pipe), 0);
4995 I915_WRITE(PF_WIN_SZ(pipe), 0);
4996 }
4997}
4998
6be4a607
JB		 4999static void ironlake_crtc_disable(struct drm_crtc *crtc)
5000{
5001 struct drm_device *dev = crtc->dev;
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5004 struct intel_encoder *encoder;
6be4a607 5005 int pipe = intel_crtc->pipe;
5eddb70b 5006 u32 reg, temp;
b52eb4dc 5007
ea9d758d
DV		 5008 for_each_encoder_on_crtc(dev, crtc, encoder)
5009 encoder->disable(encoder);
5010
f9b61ff6
DV		 5011 drm_crtc_vblank_off(crtc);
5012 assert_vblank_disabled(crtc);
5013
6e3c9717 5014 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5015 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5016
575f7ab7 5017 intel_disable_pipe(intel_crtc);
32f9d658 5018
bfd16b2a 5019 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5020
5a74f70a
VS		 5021 if (intel_crtc->config->has_pch_encoder)
5022 ironlake_fdi_disable(crtc);
5023
bf49ec8c
DV		 5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 if (encoder->post_disable)
5026 encoder->post_disable(encoder);
2c07245f 5027
6e3c9717 5028 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5029 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5030
d925c59a
DV		 5031 if (HAS_PCH_CPT(dev)) {
5032 /* disable TRANS_DP_CTL */
5033 reg = TRANS_DP_CTL(pipe);
5034 temp = I915_READ(reg);
5035 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5036 TRANS_DP_PORT_SEL_MASK);
5037 temp |= TRANS_DP_PORT_SEL_NONE;
5038 I915_WRITE(reg, temp);
5039
5040 /* disable DPLL_SEL */
5041 temp = I915_READ(PCH_DPLL_SEL);
11887397 5042 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5043 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5044 }
e3421a18 5045
d925c59a
DV		 5046 ironlake_fdi_pll_disable(intel_crtc);
5047 }
6be4a607 5048}
1b3c7a47 5049
4f771f10 5050static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5051{
4f771f10
PZ		 5052 struct drm_device *dev = crtc->dev;
5053 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5055 struct intel_encoder *encoder;
6e3c9717 5056 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7d4aefd0 5057 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
ee7b9f93 5058
8807e55b
JN		 5059 for_each_encoder_on_crtc(dev, crtc, encoder) {
5060 intel_opregion_notify_encoder(encoder, false);
4f771f10 5061 encoder->disable(encoder);
8807e55b 5062 }
4f771f10 5063
f9b61ff6
DV		 5064 drm_crtc_vblank_off(crtc);
5065 assert_vblank_disabled(crtc);
5066
6e3c9717 5067 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5068 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5069 false);
575f7ab7 5070 intel_disable_pipe(intel_crtc);
4f771f10 5071
6e3c9717 5072 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5073 intel_ddi_set_vc_payload_alloc(crtc, false);
5074
7d4aefd0
SS		 5075 if (!is_dsi)
5076 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5077
1c132b44 5078 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5079 skylake_scaler_disable(intel_crtc);
ff6d9f55 5080 else
bfd16b2a 5081 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5082
7d4aefd0
SS		 5083 if (!is_dsi)
5084 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5085
6e3c9717 5086 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5087 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5088 intel_ddi_fdi_disable(crtc);
83616634 5089 }
4f771f10 5090
97b040aa
ID		 5091 for_each_encoder_on_crtc(dev, crtc, encoder)
5092 if (encoder->post_disable)
5093 encoder->post_disable(encoder);
4f771f10
PZ		 5094}
5095
2dd24552
JB		 5096static void i9xx_pfit_enable(struct intel_crtc *crtc)
5097{
5098 struct drm_device *dev = crtc->base.dev;
5099 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5100 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5101
681a8504 5102 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5103 return;
5104
2dd24552 5105 /*
c0b03411
DV		 5106 * The panel fitter should only be adjusted whilst the pipe is disabled,
5107 * according to register description and PRM.
2dd24552 5108 */
c0b03411
DV		 5109 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5110 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5111
b074cec8
JB		 5112 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5113 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5114
5115 /* Border color in case we don't scale up to the full screen. Black by
5116 * default, change to something else for debugging. */
5117 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5118}
5119
d05410f9
DA		 5120static enum intel_display_power_domain port_to_power_domain(enum port port)
5121{
5122 switch (port) {
5123 case PORT_A:
5124 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5125 case PORT_B:
5126 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5127 case PORT_C:
5128 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5129 case PORT_D:
5130 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5131 case PORT_E:
5132 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5133 default:
5134 WARN_ON_ONCE(1);
5135 return POWER_DOMAIN_PORT_OTHER;
5136 }
5137}
5138
77d22dca
ID		 5139#define for_each_power_domain(domain, mask) \
5140 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5141 if ((1 << (domain)) & (mask))
5142
319be8ae
ID		 5143enum intel_display_power_domain
5144intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5145{
5146 struct drm_device *dev = intel_encoder->base.dev;
5147 struct intel_digital_port *intel_dig_port;
5148
5149 switch (intel_encoder->type) {
5150 case INTEL_OUTPUT_UNKNOWN:
5151 /* Only DDI platforms should ever use this output type */
5152 WARN_ON_ONCE(!HAS_DDI(dev));
5153 case INTEL_OUTPUT_DISPLAYPORT:
5154 case INTEL_OUTPUT_HDMI:
5155 case INTEL_OUTPUT_EDP:
5156 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5157 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5158 case INTEL_OUTPUT_DP_MST:
5159 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5160 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5161 case INTEL_OUTPUT_ANALOG:
5162 return POWER_DOMAIN_PORT_CRT;
5163 case INTEL_OUTPUT_DSI:
5164 return POWER_DOMAIN_PORT_DSI;
5165 default:
5166 return POWER_DOMAIN_PORT_OTHER;
5167 }
5168}
5169
5170static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5171{
319be8ae
ID		 5172 struct drm_device *dev = crtc->dev;
5173 struct intel_encoder *intel_encoder;
5174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5175 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5176 unsigned long mask;
5177 enum transcoder transcoder;
5178
292b990e
ML		 5179 if (!crtc->state->active)
5180 return 0;
5181
77d22dca
ID		 5182 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5183
5184 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5185 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5186 if (intel_crtc->config->pch_pfit.enabled ||
5187 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5188 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5189
319be8ae
ID		 5190 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5191 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5192
77d22dca
ID		 5193 return mask;
5194}
5195
292b990e 5196static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5197{
292b990e
ML		 5198 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 enum intel_display_power_domain domain;
5201 unsigned long domains, new_domains, old_domains;
77d22dca 5202
292b990e
ML		 5203 old_domains = intel_crtc->enabled_power_domains;
5204 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5205
292b990e
ML		 5206 domains = new_domains & ~old_domains;
5207
5208 for_each_power_domain(domain, domains)
5209 intel_display_power_get(dev_priv, domain);
5210
5211 return old_domains & ~new_domains;
5212}
5213
5214static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5215 unsigned long domains)
5216{
5217 enum intel_display_power_domain domain;
5218
5219 for_each_power_domain(domain, domains)
5220 intel_display_power_put(dev_priv, domain);
5221}
77d22dca 5222
292b990e
ML		 5223static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5224{
5225 struct drm_device *dev = state->dev;
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227 unsigned long put_domains[I915_MAX_PIPES] = {};
5228 struct drm_crtc_state *crtc_state;
5229 struct drm_crtc *crtc;
5230 int i;
77d22dca 5231
292b990e
ML		 5232 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5233 if (needs_modeset(crtc->state))
5234 put_domains[to_intel_crtc(crtc)->pipe] =
5235 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5236 }
5237
27c329ed
ML		 5238 if (dev_priv->display.modeset_commit_cdclk) {
5239 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5240
5241 if (cdclk != dev_priv->cdclk_freq &&
5242 !WARN_ON(!state->allow_modeset))
5243 dev_priv->display.modeset_commit_cdclk(state);
5244 }
50f6e502 5245
292b990e
ML		 5246 for (i = 0; i < I915_MAX_PIPES; i++)
5247 if (put_domains[i])
5248 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5249}
5250
adafdc6f
MK		 5251static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5252{
5253 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5254
5255 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5256 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5257 return max_cdclk_freq;
5258 else if (IS_CHERRYVIEW(dev_priv))
5259 return max_cdclk_freq*95/100;
5260 else if (INTEL_INFO(dev_priv)->gen < 4)
5261 return 2*max_cdclk_freq*90/100;
5262 else
5263 return max_cdclk_freq*90/100;
5264}
5265
560a7ae4
DL		 5266static void intel_update_max_cdclk(struct drm_device *dev)
5267{
5268 struct drm_i915_private *dev_priv = dev->dev_private;
5269
ef11bdb3 5270 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
560a7ae4
DL		 5271 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5272
5273 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5274 dev_priv->max_cdclk_freq = 675000;
5275 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5276 dev_priv->max_cdclk_freq = 540000;
5277 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5278 dev_priv->max_cdclk_freq = 450000;
5279 else
5280 dev_priv->max_cdclk_freq = 337500;
5281 } else if (IS_BROADWELL(dev)) {
5282 /*
5283 * FIXME with extra cooling we can allow
5284 * 540 MHz for ULX and 675 Mhz for ULT.
5285 * How can we know if extra cooling is
5286 * available? PCI ID, VTB, something else?
5287 */
5288 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5289 dev_priv->max_cdclk_freq = 450000;
5290 else if (IS_BDW_ULX(dev))
5291 dev_priv->max_cdclk_freq = 450000;
5292 else if (IS_BDW_ULT(dev))
5293 dev_priv->max_cdclk_freq = 540000;
5294 else
5295 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5296 } else if (IS_CHERRYVIEW(dev)) {
5297 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5298 } else if (IS_VALLEYVIEW(dev)) {
5299 dev_priv->max_cdclk_freq = 400000;
5300 } else {
5301 /* otherwise assume cdclk is fixed */
5302 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5303 }
5304
adafdc6f
MK		 5305 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5306
560a7ae4
DL		 5307 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5308 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5309
5310 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5311 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5312}
5313
5314static void intel_update_cdclk(struct drm_device *dev)
5315{
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317
5318 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5319 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5320 dev_priv->cdclk_freq);
5321
5322 /*
5323 * Program the gmbus_freq based on the cdclk frequency.
5324 * BSpec erroneously claims we should aim for 4MHz, but
5325 * in fact 1MHz is the correct frequency.
5326 */
5327 if (IS_VALLEYVIEW(dev)) {
5328 /*
5329 * Program the gmbus_freq based on the cdclk frequency.
5330 * BSpec erroneously claims we should aim for 4MHz, but
5331 * in fact 1MHz is the correct frequency.
5332 */
5333 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5334 }
5335
5336 if (dev_priv->max_cdclk_freq == 0)
5337 intel_update_max_cdclk(dev);
5338}
5339
70d0c574 5340static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5341{
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 uint32_t divider;
5344 uint32_t ratio;
5345 uint32_t current_freq;
5346 int ret;
5347
5348 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5349 switch (frequency) {
5350 case 144000:
5351 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5352 ratio = BXT_DE_PLL_RATIO(60);
5353 break;
5354 case 288000:
5355 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5356 ratio = BXT_DE_PLL_RATIO(60);
5357 break;
5358 case 384000:
5359 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5360 ratio = BXT_DE_PLL_RATIO(60);
5361 break;
5362 case 576000:
5363 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5364 ratio = BXT_DE_PLL_RATIO(60);
5365 break;
5366 case 624000:
5367 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5368 ratio = BXT_DE_PLL_RATIO(65);
5369 break;
5370 case 19200:
5371 /*
5372 * Bypass frequency with DE PLL disabled. Init ratio, divider
5373 * to suppress GCC warning.
5374 */
5375 ratio = 0;
5376 divider = 0;
5377 break;
5378 default:
5379 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5380
5381 return;
5382 }
5383
5384 mutex_lock(&dev_priv->rps.hw_lock);
5385 /* Inform power controller of upcoming frequency change */
5386 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5387 0x80000000);
5388 mutex_unlock(&dev_priv->rps.hw_lock);
5389
5390 if (ret) {
5391 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5392 ret, frequency);
5393 return;
5394 }
5395
5396 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5397 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5398 current_freq = current_freq * 500 + 1000;
5399
5400 /*
5401 * DE PLL has to be disabled when
5402 * - setting to 19.2MHz (bypass, PLL isn't used)
5403 * - before setting to 624MHz (PLL needs toggling)
5404 * - before setting to any frequency from 624MHz (PLL needs toggling)
5405 */
5406 if (frequency == 19200 || frequency == 624000 ||
5407 current_freq == 624000) {
5408 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5409 /* Timeout 200us */
5410 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5411 1))
5412 DRM_ERROR("timout waiting for DE PLL unlock\n");
5413 }
5414
5415 if (frequency != 19200) {
5416 uint32_t val;
5417
5418 val = I915_READ(BXT_DE_PLL_CTL);
5419 val &= ~BXT_DE_PLL_RATIO_MASK;
5420 val |= ratio;
5421 I915_WRITE(BXT_DE_PLL_CTL, val);
5422
5423 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5424 /* Timeout 200us */
5425 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5426 DRM_ERROR("timeout waiting for DE PLL lock\n");
5427
5428 val = I915_READ(CDCLK_CTL);
5429 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5430 val |= divider;
5431 /*
5432 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5433 * enable otherwise.
5434 */
5435 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5436 if (frequency >= 500000)
5437 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5438
5439 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5440 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5441 val |= (frequency - 1000) / 500;
5442 I915_WRITE(CDCLK_CTL, val);
5443 }
5444
5445 mutex_lock(&dev_priv->rps.hw_lock);
5446 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5447 DIV_ROUND_UP(frequency, 25000));
5448 mutex_unlock(&dev_priv->rps.hw_lock);
5449
5450 if (ret) {
5451 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5452 ret, frequency);
5453 return;
5454 }
5455
a47871bd 5456 intel_update_cdclk(dev);
f8437dd1
VK		 5457}
5458
5459void broxton_init_cdclk(struct drm_device *dev)
5460{
5461 struct drm_i915_private *dev_priv = dev->dev_private;
5462 uint32_t val;
5463
5464 /*
5465 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5466 * or else the reset will hang because there is no PCH to respond.
5467 * Move the handshake programming to initialization sequence.
5468 * Previously was left up to BIOS.
5469 */
5470 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5471 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5472 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5473
5474 /* Enable PG1 for cdclk */
5475 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5476
5477 /* check if cd clock is enabled */
5478 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5479 DRM_DEBUG_KMS("Display already initialized\n");
5480 return;
5481 }
5482
5483 /*
5484 * FIXME:
5485 * - The initial CDCLK needs to be read from VBT.
5486 * Need to make this change after VBT has changes for BXT.
5487 * - check if setting the max (or any) cdclk freq is really necessary
5488 * here, it belongs to modeset time
5489 */
5490 broxton_set_cdclk(dev, 624000);
5491
5492 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5493 POSTING_READ(DBUF_CTL);
5494
f8437dd1
VK		 5495 udelay(10);
5496
5497 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5498 DRM_ERROR("DBuf power enable timeout!\n");
5499}
5500
5501void broxton_uninit_cdclk(struct drm_device *dev)
5502{
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504
5505 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5506 POSTING_READ(DBUF_CTL);
5507
f8437dd1
VK		 5508 udelay(10);
5509
5510 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5511 DRM_ERROR("DBuf power disable timeout!\n");
5512
5513 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5514 broxton_set_cdclk(dev, 19200);
5515
5516 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5517}
5518
5d96d8af
DL		 5519static const struct skl_cdclk_entry {
5520 unsigned int freq;
5521 unsigned int vco;
5522} skl_cdclk_frequencies[] = {
5523 { .freq = 308570, .vco = 8640 },
5524 { .freq = 337500, .vco = 8100 },
5525 { .freq = 432000, .vco = 8640 },
5526 { .freq = 450000, .vco = 8100 },
5527 { .freq = 540000, .vco = 8100 },
5528 { .freq = 617140, .vco = 8640 },
5529 { .freq = 675000, .vco = 8100 },
5530};
5531
5532static unsigned int skl_cdclk_decimal(unsigned int freq)
5533{
5534 return (freq - 1000) / 500;
5535}
5536
5537static unsigned int skl_cdclk_get_vco(unsigned int freq)
5538{
5539 unsigned int i;
5540
5541 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5542 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5543
5544 if (e->freq == freq)
5545 return e->vco;
5546 }
5547
5548 return 8100;
5549}
5550
5551static void
5552skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5553{
5554 unsigned int min_freq;
5555 u32 val;
5556
5557 /* select the minimum CDCLK before enabling DPLL 0 */
5558 val = I915_READ(CDCLK_CTL);
5559 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5560 val |= CDCLK_FREQ_337_308;
5561
5562 if (required_vco == 8640)
5563 min_freq = 308570;
5564 else
5565 min_freq = 337500;
5566
5567 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5568
5569 I915_WRITE(CDCLK_CTL, val);
5570 POSTING_READ(CDCLK_CTL);
5571
5572 /*
5573 * We always enable DPLL0 with the lowest link rate possible, but still
5574 * taking into account the VCO required to operate the eDP panel at the
5575 * desired frequency. The usual DP link rates operate with a VCO of
5576 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5577 * The modeset code is responsible for the selection of the exact link
5578 * rate later on, with the constraint of choosing a frequency that
5579 * works with required_vco.
5580 */
5581 val = I915_READ(DPLL_CTRL1);
5582
5583 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5584 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5585 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5586 if (required_vco == 8640)
5587 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5588 SKL_DPLL0);
5589 else
5590 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5591 SKL_DPLL0);
5592
5593 I915_WRITE(DPLL_CTRL1, val);
5594 POSTING_READ(DPLL_CTRL1);
5595
5596 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5597
5598 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5599 DRM_ERROR("DPLL0 not locked\n");
5600}
5601
5602static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5603{
5604 int ret;
5605 u32 val;
5606
5607 /* inform PCU we want to change CDCLK */
5608 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5609 mutex_lock(&dev_priv->rps.hw_lock);
5610 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5611 mutex_unlock(&dev_priv->rps.hw_lock);
5612
5613 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5614}
5615
5616static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5617{
5618 unsigned int i;
5619
5620 for (i = 0; i < 15; i++) {
5621 if (skl_cdclk_pcu_ready(dev_priv))
5622 return true;
5623 udelay(10);
5624 }
5625
5626 return false;
5627}
5628
5629static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5630{
560a7ae4 5631 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5632 u32 freq_select, pcu_ack;
5633
5634 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5635
5636 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5637 DRM_ERROR("failed to inform PCU about cdclk change\n");
5638 return;
5639 }
5640
5641 /* set CDCLK_CTL */
5642 switch(freq) {
5643 case 450000:
5644 case 432000:
5645 freq_select = CDCLK_FREQ_450_432;
5646 pcu_ack = 1;
5647 break;
5648 case 540000:
5649 freq_select = CDCLK_FREQ_540;
5650 pcu_ack = 2;
5651 break;
5652 case 308570:
5653 case 337500:
5654 default:
5655 freq_select = CDCLK_FREQ_337_308;
5656 pcu_ack = 0;
5657 break;
5658 case 617140:
5659 case 675000:
5660 freq_select = CDCLK_FREQ_675_617;
5661 pcu_ack = 3;
5662 break;
5663 }
5664
5665 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5666 POSTING_READ(CDCLK_CTL);
5667
5668 /* inform PCU of the change */
5669 mutex_lock(&dev_priv->rps.hw_lock);
5670 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5671 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5672
5673 intel_update_cdclk(dev);
5d96d8af
DL		 5674}
5675
5676void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5677{
5678 /* disable DBUF power */
5679 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5680 POSTING_READ(DBUF_CTL);
5681
5682 udelay(10);
5683
5684 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5685 DRM_ERROR("DBuf power disable timeout\n");
5686
4e961e42
AM		 5687 /*
5688 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5689 */
5690 if (dev_priv->csr.dmc_payload) {
5691 /* disable DPLL0 */
5692 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5693 ~LCPLL_PLL_ENABLE);
5694 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5695 DRM_ERROR("Couldn't disable DPLL0\n");
5696 }
5d96d8af
DL		 5697
5698 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5699}
5700
5701void skl_init_cdclk(struct drm_i915_private *dev_priv)
5702{
5703 u32 val;
5704 unsigned int required_vco;
5705
5706 /* enable PCH reset handshake */
5707 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5708 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5709
5710 /* enable PG1 and Misc I/O */
5711 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5712
39d9b85a
GW		 5713 /* DPLL0 not enabled (happens on early BIOS versions) */
5714 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5715 /* enable DPLL0 */
5716 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5717 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5718 }
5719
5d96d8af
DL		 5720 /* set CDCLK to the frequency the BIOS chose */
5721 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5722
5723 /* enable DBUF power */
5724 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5725 POSTING_READ(DBUF_CTL);
5726
5727 udelay(10);
5728
5729 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5730 DRM_ERROR("DBuf power enable timeout\n");
5731}
5732
c73666f3
SK		 5733int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5734{
5735 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5736 uint32_t cdctl = I915_READ(CDCLK_CTL);
5737 int freq = dev_priv->skl_boot_cdclk;
5738
5739 /* Is PLL enabled and locked ? */
5740 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5741 goto sanitize;
5742
5743 /* DPLL okay; verify the cdclock
5744 *
5745 * Noticed in some instances that the freq selection is correct but
5746 * decimal part is programmed wrong from BIOS where pre-os does not
5747 * enable display. Verify the same as well.
5748 */
5749 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5750 /* All well; nothing to sanitize */
5751 return false;
5752sanitize:
5753 /*
5754 * As of now initialize with max cdclk till
5755 * we get dynamic cdclk support
5756 * */
5757 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5758 skl_init_cdclk(dev_priv);
5759
5760 /* we did have to sanitize */
5761 return true;
5762}
5763
30a970c6
JB		 5764/* Adjust CDclk dividers to allow high res or save power if possible */
5765static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5766{
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768 u32 val, cmd;
5769
164dfd28
VK		 5770 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5771 != dev_priv->cdclk_freq);
d60c4473 5772
dfcab17e 5773 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5774 cmd = 2;
dfcab17e 5775 else if (cdclk == 266667)
30a970c6
JB		 5776 cmd = 1;
5777 else
5778 cmd = 0;
5779
5780 mutex_lock(&dev_priv->rps.hw_lock);
5781 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5782 val &= ~DSPFREQGUAR_MASK;
5783 val |= (cmd << DSPFREQGUAR_SHIFT);
5784 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5785 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5786 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5787 50)) {
5788 DRM_ERROR("timed out waiting for CDclk change\n");
5789 }
5790 mutex_unlock(&dev_priv->rps.hw_lock);
5791
54433e91
VS		 5792 mutex_lock(&dev_priv->sb_lock);
5793
dfcab17e 5794 if (cdclk == 400000) {
6bcda4f0 5795 u32 divider;
30a970c6 5796
6bcda4f0 5797 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5798
30a970c6
JB		 5799 /* adjust cdclk divider */
5800 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
87d5d259 5801 val &= ~CCK_FREQUENCY_VALUES;
30a970c6
JB		 5802 val |= divider;
5803 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5804
5805 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
87d5d259 5806 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
a877e801
VS		 5807 50))
5808 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5809 }
5810
30a970c6
JB		 5811 /* adjust self-refresh exit latency value */
5812 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5813 val &= ~0x7f;
5814
5815 /*
5816 * For high bandwidth configs, we set a higher latency in the bunit
5817 * so that the core display fetch happens in time to avoid underruns.
5818 */
dfcab17e 5819 if (cdclk == 400000)
30a970c6
JB		 5820 val |= 4500 / 250; /* 4.5 usec */
5821 else
5822 val |= 3000 / 250; /* 3.0 usec */
5823 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5824
a580516d 5825 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5826
b6283055 5827 intel_update_cdclk(dev);
30a970c6
JB		 5828}
5829
383c5a6a
VS		 5830static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5831{
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833 u32 val, cmd;
5834
164dfd28
VK		 5835 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5836 != dev_priv->cdclk_freq);
383c5a6a
VS		 5837
5838 switch (cdclk) {
383c5a6a
VS		 5839 case 333333:
5840 case 320000:
383c5a6a 5841 case 266667:
383c5a6a 5842 case 200000:
383c5a6a
VS		 5843 break;
5844 default:
5f77eeb0 5845 MISSING_CASE(cdclk);
383c5a6a
VS		 5846 return;
5847 }
5848
9d0d3fda
VS		 5849 /*
5850 * Specs are full of misinformation, but testing on actual
5851 * hardware has shown that we just need to write the desired
5852 * CCK divider into the Punit register.
5853 */
5854 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5855
383c5a6a
VS		 5856 mutex_lock(&dev_priv->rps.hw_lock);
5857 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5858 val &= ~DSPFREQGUAR_MASK_CHV;
5859 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5860 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5861 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5862 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5863 50)) {
5864 DRM_ERROR("timed out waiting for CDclk change\n");
5865 }
5866 mutex_unlock(&dev_priv->rps.hw_lock);
5867
b6283055 5868 intel_update_cdclk(dev);
383c5a6a
VS		 5869}
5870
30a970c6
JB		 5871static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5872 int max_pixclk)
5873{
6bcda4f0 5874 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5875 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5876
30a970c6
JB		 5877 /*
5878 * Really only a few cases to deal with, as only 4 CDclks are supported:
5879 * 200MHz
5880 * 267MHz
29dc7ef3 5881 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5882 * 400MHz (VLV only)
5883 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5884 * of the lower bin and adjust if needed.
e37c67a1
VS		 5885 *
5886 * We seem to get an unstable or solid color picture at 200MHz.
5887 * Not sure what's wrong. For now use 200MHz only when all pipes
5888 * are off.
30a970c6 5889 */
6cca3195
VS		 5890 if (!IS_CHERRYVIEW(dev_priv) &&
5891 max_pixclk > freq_320*limit/100)
dfcab17e 5892 return 400000;
6cca3195 5893 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5894 return freq_320;
e37c67a1 5895 else if (max_pixclk > 0)
dfcab17e 5896 return 266667;
e37c67a1
VS		 5897 else
5898 return 200000;
30a970c6
JB		 5899}
5900
f8437dd1
VK		 5901static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5902 int max_pixclk)
5903{
5904 /*
5905 * FIXME:
5906 * - remove the guardband, it's not needed on BXT
5907 * - set 19.2MHz bypass frequency if there are no active pipes
5908 */
5909 if (max_pixclk > 576000*9/10)
5910 return 624000;
5911 else if (max_pixclk > 384000*9/10)
5912 return 576000;
5913 else if (max_pixclk > 288000*9/10)
5914 return 384000;
5915 else if (max_pixclk > 144000*9/10)
5916 return 288000;
5917 else
5918 return 144000;
5919}
5920
a821fc46
ACO		 5921/* Compute the max pixel clock for new configuration. Uses atomic state if
5922 * that's non-NULL, look at current state otherwise. */
5923static int intel_mode_max_pixclk(struct drm_device *dev,
5924 struct drm_atomic_state *state)
30a970c6 5925{
30a970c6 5926 struct intel_crtc *intel_crtc;
304603f4 5927 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5928 int max_pixclk = 0;
5929
d3fcc808 5930 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5931 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5932 if (IS_ERR(crtc_state))
5933 return PTR_ERR(crtc_state);
5934
5935 if (!crtc_state->base.enable)
5936 continue;
5937
5938 max_pixclk = max(max_pixclk,
5939 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5940 }
5941
5942 return max_pixclk;
5943}
5944
27c329ed 5945static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5946{
27c329ed
ML		 5947 struct drm_device *dev = state->dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5950
304603f4
ACO		 5951 if (max_pixclk < 0)
5952 return max_pixclk;
30a970c6 5953
27c329ed
ML		 5954 to_intel_atomic_state(state)->cdclk =
5955 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5956
27c329ed
ML		 5957 return 0;
5958}
304603f4 5959
27c329ed
ML		 5960static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5961{
5962 struct drm_device *dev = state->dev;
5963 struct drm_i915_private *dev_priv = dev->dev_private;
5964 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5965
27c329ed
ML		 5966 if (max_pixclk < 0)
5967 return max_pixclk;
85a96e7a 5968
27c329ed
ML		 5969 to_intel_atomic_state(state)->cdclk =
5970 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5971
27c329ed 5972 return 0;
30a970c6
JB		 5973}
5974
1e69cd74
VS		 5975static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5976{
5977 unsigned int credits, default_credits;
5978
5979 if (IS_CHERRYVIEW(dev_priv))
5980 default_credits = PFI_CREDIT(12);
5981 else
5982 default_credits = PFI_CREDIT(8);
5983
bfa7df01 5984 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
1e69cd74
VS		 5985 /* CHV suggested value is 31 or 63 */
5986 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5987 credits = PFI_CREDIT_63;
1e69cd74
VS		 5988 else
5989 credits = PFI_CREDIT(15);
5990 } else {
5991 credits = default_credits;
5992 }
5993
5994 /*
5995 * WA - write default credits before re-programming
5996 * FIXME: should we also set the resend bit here?
5997 */
5998 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5999 default_credits);
6000
6001 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6002 credits | PFI_CREDIT_RESEND);
6003
6004 /*
6005 * FIXME is this guaranteed to clear
6006 * immediately or should we poll for it?
6007 */
6008 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6009}
6010
27c329ed 6011static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 6012{
a821fc46 6013 struct drm_device *dev = old_state->dev;
27c329ed 6014 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 6015 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 6016
27c329ed
ML		 6017 /*
6018 * FIXME: We can end up here with all power domains off, yet
6019 * with a CDCLK frequency other than the minimum. To account
6020 * for this take the PIPE-A power domain, which covers the HW
6021 * blocks needed for the following programming. This can be
6022 * removed once it's guaranteed that we get here either with
6023 * the minimum CDCLK set, or the required power domains
6024 * enabled.
6025 */
6026 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 6027
27c329ed
ML		 6028 if (IS_CHERRYVIEW(dev))
6029 cherryview_set_cdclk(dev, req_cdclk);
6030 else
6031 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6032
27c329ed 6033 vlv_program_pfi_credits(dev_priv);
1e69cd74 6034
27c329ed 6035 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6036}
6037
89b667f8
JB		 6038static void valleyview_crtc_enable(struct drm_crtc *crtc)
6039{
6040 struct drm_device *dev = crtc->dev;
a72e4c9f 6041 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6043 struct intel_encoder *encoder;
6044 int pipe = intel_crtc->pipe;
23538ef1 6045 bool is_dsi;
89b667f8 6046
53d9f4e9 6047 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6048 return;
6049
409ee761 6050 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6051
6e3c9717 6052 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6053 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6054
6055 intel_set_pipe_timings(intel_crtc);
6056
c14b0485
VS		 6057 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6058 struct drm_i915_private *dev_priv = dev->dev_private;
6059
6060 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6061 I915_WRITE(CHV_CANVAS(pipe), 0);
6062 }
6063
5b18e57c
DV		 6064 i9xx_set_pipeconf(intel_crtc);
6065
89b667f8 6066 intel_crtc->active = true;
89b667f8 6067
a72e4c9f 6068 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6069
89b667f8
JB		 6070 for_each_encoder_on_crtc(dev, crtc, encoder)
6071 if (encoder->pre_pll_enable)
6072 encoder->pre_pll_enable(encoder);
6073
9d556c99 6074 if (!is_dsi) {
c0b4c660
VS		 6075 if (IS_CHERRYVIEW(dev)) {
6076 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6077 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6078 } else {
6079 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6080 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6081 }
9d556c99 6082 }
89b667f8
JB		 6083
6084 for_each_encoder_on_crtc(dev, crtc, encoder)
6085 if (encoder->pre_enable)
6086 encoder->pre_enable(encoder);
6087
2dd24552
JB		 6088 i9xx_pfit_enable(intel_crtc);
6089
63cbb074
VS		 6090 intel_crtc_load_lut(crtc);
6091
e1fdc473 6092 intel_enable_pipe(intel_crtc);
be6a6f8e 6093
4b3a9526
VS		 6094 assert_vblank_disabled(crtc);
6095 drm_crtc_vblank_on(crtc);
6096
f9b61ff6
DV		 6097 for_each_encoder_on_crtc(dev, crtc, encoder)
6098 encoder->enable(encoder);
89b667f8
JB		 6099}
6100
f13c2ef3
DV		 6101static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6102{
6103 struct drm_device *dev = crtc->base.dev;
6104 struct drm_i915_private *dev_priv = dev->dev_private;
6105
6e3c9717
ACO		 6106 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6107 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6108}
6109
0b8765c6 6110static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6111{
6112 struct drm_device *dev = crtc->dev;
a72e4c9f 6113 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6115 struct intel_encoder *encoder;
79e53945 6116 int pipe = intel_crtc->pipe;
79e53945 6117
53d9f4e9 6118 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6119 return;
6120
f13c2ef3
DV		 6121 i9xx_set_pll_dividers(intel_crtc);
6122
6e3c9717 6123 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6124 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6125
6126 intel_set_pipe_timings(intel_crtc);
6127
5b18e57c
DV		 6128 i9xx_set_pipeconf(intel_crtc);
6129
f7abfe8b 6130 intel_crtc->active = true;
6b383a7f 6131
4a3436e8 6132 if (!IS_GEN2(dev))
a72e4c9f 6133 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6134
9d6d9f19
MK		 6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 if (encoder->pre_enable)
6137 encoder->pre_enable(encoder);
6138
f6736a1a
DV		 6139 i9xx_enable_pll(intel_crtc);
6140
2dd24552
JB		 6141 i9xx_pfit_enable(intel_crtc);
6142
63cbb074
VS		 6143 intel_crtc_load_lut(crtc);
6144
f37fcc2a 6145 intel_update_watermarks(crtc);
e1fdc473 6146 intel_enable_pipe(intel_crtc);
be6a6f8e 6147
4b3a9526
VS		 6148 assert_vblank_disabled(crtc);
6149 drm_crtc_vblank_on(crtc);
6150
f9b61ff6
DV		 6151 for_each_encoder_on_crtc(dev, crtc, encoder)
6152 encoder->enable(encoder);
0b8765c6 6153}
79e53945 6154
87476d63
DV		 6155static void i9xx_pfit_disable(struct intel_crtc *crtc)
6156{
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6159
6e3c9717 6160 if (!crtc->config->gmch_pfit.control)
328d8e82 6161 return;
87476d63 6162
328d8e82 6163 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6164
328d8e82
DV		 6165 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6166 I915_READ(PFIT_CONTROL));
6167 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6168}
6169
0b8765c6
JB		 6170static void i9xx_crtc_disable(struct drm_crtc *crtc)
6171{
6172 struct drm_device *dev = crtc->dev;
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6175 struct intel_encoder *encoder;
0b8765c6 6176 int pipe = intel_crtc->pipe;
ef9c3aee 6177
6304cd91
VS		 6178 /*
6179 * On gen2 planes are double buffered but the pipe isn't, so we must
6180 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6181 * We also need to wait on all gmch platforms because of the
6182 * self-refresh mode constraint explained above.
6304cd91 6183 */
564ed191 6184 intel_wait_for_vblank(dev, pipe);
6304cd91 6185
4b3a9526
VS		 6186 for_each_encoder_on_crtc(dev, crtc, encoder)
6187 encoder->disable(encoder);
6188
f9b61ff6
DV		 6189 drm_crtc_vblank_off(crtc);
6190 assert_vblank_disabled(crtc);
6191
575f7ab7 6192 intel_disable_pipe(intel_crtc);
24a1f16d 6193
87476d63 6194 i9xx_pfit_disable(intel_crtc);
24a1f16d 6195
89b667f8
JB		 6196 for_each_encoder_on_crtc(dev, crtc, encoder)
6197 if (encoder->post_disable)
6198 encoder->post_disable(encoder);
6199
409ee761 6200 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6201 if (IS_CHERRYVIEW(dev))
6202 chv_disable_pll(dev_priv, pipe);
6203 else if (IS_VALLEYVIEW(dev))
6204 vlv_disable_pll(dev_priv, pipe);
6205 else
1c4e0274 6206 i9xx_disable_pll(intel_crtc);
076ed3b2 6207 }
0b8765c6 6208
d6db995f
VS		 6209 for_each_encoder_on_crtc(dev, crtc, encoder)
6210 if (encoder->post_pll_disable)
6211 encoder->post_pll_disable(encoder);
6212
4a3436e8 6213 if (!IS_GEN2(dev))
a72e4c9f 6214 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6215}
6216
b17d48e2
ML		 6217static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6218{
6219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6220 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6221 enum intel_display_power_domain domain;
6222 unsigned long domains;
6223
6224 if (!intel_crtc->active)
6225 return;
6226
a539205a 6227 if (to_intel_plane_state(crtc->primary->state)->visible) {
fc32b1fd
ML		 6228 WARN_ON(intel_crtc->unpin_work);
6229
a539205a
ML		 6230 intel_pre_disable_primary(crtc);
6231 }
6232
d032ffa0 6233 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6234 dev_priv->display.crtc_disable(crtc);
37d9078b
MR		 6235 intel_crtc->active = false;
6236 intel_update_watermarks(crtc);
1f7457b1 6237 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6238
6239 domains = intel_crtc->enabled_power_domains;
6240 for_each_power_domain(domain, domains)
6241 intel_display_power_put(dev_priv, domain);
6242 intel_crtc->enabled_power_domains = 0;
6243}
6244
6b72d486
ML		 6245/*
6246 * turn all crtc's off, but do not adjust state
6247 * This has to be paired with a call to intel_modeset_setup_hw_state.
6248 */
70e0bd74 6249int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6250{
70e0bd74
ML		 6251 struct drm_mode_config *config = &dev->mode_config;
6252 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6253 struct drm_atomic_state *state;
6b72d486 6254 struct drm_crtc *crtc;
70e0bd74
ML		 6255 unsigned crtc_mask = 0;
6256 int ret = 0;
6257
6258 if (WARN_ON(!ctx))
6259 return 0;
6260
6261 lockdep_assert_held(&ctx->ww_ctx);
6262 state = drm_atomic_state_alloc(dev);
6263 if (WARN_ON(!state))
6264 return -ENOMEM;
6265
6266 state->acquire_ctx = ctx;
6267 state->allow_modeset = true;
6268
6269 for_each_crtc(dev, crtc) {
6270 struct drm_crtc_state *crtc_state =
6271 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6272
70e0bd74
ML		 6273 ret = PTR_ERR_OR_ZERO(crtc_state);
6274 if (ret)
6275 goto free;
6276
6277 if (!crtc_state->active)
6278 continue;
6279
6280 crtc_state->active = false;
6281 crtc_mask |= 1 << drm_crtc_index(crtc);
6282 }
6283
6284 if (crtc_mask) {
74c090b1 6285 ret = drm_atomic_commit(state);
70e0bd74
ML		 6286
6287 if (!ret) {
6288 for_each_crtc(dev, crtc)
6289 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6290 crtc->state->active = true;
6291
6292 return ret;
6293 }
6294 }
6295
6296free:
6297 if (ret)
6298 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6299 drm_atomic_state_free(state);
6300 return ret;
ee7b9f93
JB		 6301}
6302
ea5b213a 6303void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6304{
4ef69c7a 6305 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6306
ea5b213a
CW		 6307 drm_encoder_cleanup(encoder);
6308 kfree(intel_encoder);
7e7d76c3
JB		 6309}
6310
0a91ca29
DV		 6311/* Cross check the actual hw state with our own modeset state tracking (and it's
6312 * internal consistency). */
b980514c 6313static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6314{
35dd3c64
ML		 6315 struct drm_crtc *crtc = connector->base.state->crtc;
6316
6317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6318 connector->base.base.id,
6319 connector->base.name);
6320
0a91ca29 6321 if (connector->get_hw_state(connector)) {
e85376cb 6322 struct intel_encoder *encoder = connector->encoder;
35dd3c64 6323 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6324
35dd3c64
ML		 6325 I915_STATE_WARN(!crtc,
6326 "connector enabled without attached crtc\n");
0a91ca29 6327
35dd3c64
ML		 6328 if (!crtc)
6329 return;
6330
6331 I915_STATE_WARN(!crtc->state->active,
6332 "connector is active, but attached crtc isn't\n");
6333
e85376cb 6334 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML		 6335 return;
6336
e85376cb 6337 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML		 6338 "atomic encoder doesn't match attached encoder\n");
6339
e85376cb 6340 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML		 6341 "attached encoder crtc differs from connector crtc\n");
6342 } else {
4d688a2a
ML		 6343 I915_STATE_WARN(crtc && crtc->state->active,
6344 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6345 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6346 "best encoder set without crtc!\n");
0a91ca29 6347 }
79e53945
JB		 6348}
6349
08d9bc92
ACO		 6350int intel_connector_init(struct intel_connector *connector)
6351{
6352 struct drm_connector_state *connector_state;
6353
6354 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6355 if (!connector_state)
6356 return -ENOMEM;
6357
6358 connector->base.state = connector_state;
6359 return 0;
6360}
6361
6362struct intel_connector *intel_connector_alloc(void)
6363{
6364 struct intel_connector *connector;
6365
6366 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6367 if (!connector)
6368 return NULL;
6369
6370 if (intel_connector_init(connector) < 0) {
6371 kfree(connector);
6372 return NULL;
6373 }
6374
6375 return connector;
6376}
6377
f0947c37
DV		 6378/* Simple connector->get_hw_state implementation for encoders that support only
6379 * one connector and no cloning and hence the encoder state determines the state
6380 * of the connector. */
6381bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6382{
24929352 6383 enum pipe pipe = 0;
f0947c37 6384 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6385
f0947c37 6386 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6387}
6388
6d293983 6389static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6390{
6d293983
ACO		 6391 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6392 return crtc_state->fdi_lanes;
d272ddfa
VS		 6393
6394 return 0;
6395}
6396
6d293983 6397static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6398 struct intel_crtc_state *pipe_config)
1857e1da 6399{
6d293983
ACO		 6400 struct drm_atomic_state *state = pipe_config->base.state;
6401 struct intel_crtc *other_crtc;
6402 struct intel_crtc_state *other_crtc_state;
6403
1857e1da
DV		 6404 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6405 pipe_name(pipe), pipe_config->fdi_lanes);
6406 if (pipe_config->fdi_lanes > 4) {
6407 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6408 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6409 return -EINVAL;
1857e1da
DV		 6410 }
6411
bafb6553 6412 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6413 if (pipe_config->fdi_lanes > 2) {
6414 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6415 pipe_config->fdi_lanes);
6d293983 6416 return -EINVAL;
1857e1da 6417 } else {
6d293983 6418 return 0;
1857e1da
DV		 6419 }
6420 }
6421
6422 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6423 return 0;
1857e1da
DV		 6424
6425 /* Ivybridge 3 pipe is really complicated */
6426 switch (pipe) {
6427 case PIPE_A:
6d293983 6428 return 0;
1857e1da 6429 case PIPE_B:
6d293983
ACO		 6430 if (pipe_config->fdi_lanes <= 2)
6431 return 0;
6432
6433 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6434 other_crtc_state =
6435 intel_atomic_get_crtc_state(state, other_crtc);
6436 if (IS_ERR(other_crtc_state))
6437 return PTR_ERR(other_crtc_state);
6438
6439 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6440 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6441 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6442 return -EINVAL;
1857e1da 6443 }
6d293983 6444 return 0;
1857e1da 6445 case PIPE_C:
251cc67c
VS		 6446 if (pipe_config->fdi_lanes > 2) {
6447 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6448 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6449 return -EINVAL;
251cc67c 6450 }
6d293983
ACO		 6451
6452 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6453 other_crtc_state =
6454 intel_atomic_get_crtc_state(state, other_crtc);
6455 if (IS_ERR(other_crtc_state))
6456 return PTR_ERR(other_crtc_state);
6457
6458 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6459 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6460 return -EINVAL;
1857e1da 6461 }
6d293983 6462 return 0;
1857e1da
DV		 6463 default:
6464 BUG();
6465 }
6466}
6467
e29c22c0
DV		 6468#define RETRY 1
6469static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6470 struct intel_crtc_state *pipe_config)
877d48d5 6471{
1857e1da 6472 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6473 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6474 int lane, link_bw, fdi_dotclock, ret;
6475 bool needs_recompute = false;
877d48d5 6476
e29c22c0 6477retry:
877d48d5
DV		 6478 /* FDI is a binary signal running at ~2.7GHz, encoding
6479 * each output octet as 10 bits. The actual frequency
6480 * is stored as a divider into a 100MHz clock, and the
6481 * mode pixel clock is stored in units of 1KHz.
6482 * Hence the bw of each lane in terms of the mode signal
6483 * is:
6484 */
6485 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6486
241bfc38 6487 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6488
2bd89a07 6489 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6490 pipe_config->pipe_bpp);
6491
6492 pipe_config->fdi_lanes = lane;
6493
2bd89a07 6494 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6495 link_bw, &pipe_config->fdi_m_n);
1857e1da 6496
6d293983
ACO		 6497 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6498 intel_crtc->pipe, pipe_config);
6499 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6500 pipe_config->pipe_bpp -= 2*3;
6501 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6502 pipe_config->pipe_bpp);
6503 needs_recompute = true;
6504 pipe_config->bw_constrained = true;
6505
6506 goto retry;
6507 }
6508
6509 if (needs_recompute)
6510 return RETRY;
6511
6d293983 6512 return ret;
877d48d5
DV		 6513}
6514
8cfb3407
VS		 6515static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6516 struct intel_crtc_state *pipe_config)
6517{
6518 if (pipe_config->pipe_bpp > 24)
6519 return false;
6520
6521 /* HSW can handle pixel rate up to cdclk? */
6522 if (IS_HASWELL(dev_priv->dev))
6523 return true;
6524
6525 /*
b432e5cf
VS		 6526 * We compare against max which means we must take
6527 * the increased cdclk requirement into account when
6528 * calculating the new cdclk.
6529 *
6530 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6531 */
6532 return ilk_pipe_pixel_rate(pipe_config) <=
6533 dev_priv->max_cdclk_freq * 95 / 100;
6534}
6535
42db64ef 6536static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6537 struct intel_crtc_state *pipe_config)
42db64ef 6538{
8cfb3407
VS		 6539 struct drm_device *dev = crtc->base.dev;
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541
d330a953 6542 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6543 hsw_crtc_supports_ips(crtc) &&
6544 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6545}
6546
a43f6e0f 6547static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6548 struct intel_crtc_state *pipe_config)
79e53945 6549{
a43f6e0f 6550 struct drm_device *dev = crtc->base.dev;
8bd31e67 6551 struct drm_i915_private *dev_priv = dev->dev_private;
7c5f93b0 6552 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6553
ad3a4479 6554 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6555 if (INTEL_INFO(dev)->gen < 4) {
44913155 6556 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6557
6558 /*
6559 * Enable pixel doubling when the dot clock
6560 * is > 90% of the (display) core speed.
6561 *
b397c96b
VS		 6562 * GDG double wide on either pipe,
6563 * otherwise pipe A only.
cf532bb2 6564 */
b397c96b 6565 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6566 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6567 clock_limit *= 2;
cf532bb2 6568 pipe_config->double_wide = true;
ad3a4479
VS		 6569 }
6570
241bfc38 6571 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6572 return -EINVAL;
2c07245f 6573 }
89749350 6574
1d1d0e27
VS		 6575 /*
6576 * Pipe horizontal size must be even in:
6577 * - DVO ganged mode
6578 * - LVDS dual channel mode
6579 * - Double wide pipe
6580 */
a93e255f 6581 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6582 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6583 pipe_config->pipe_src_w &= ~1;
6584
8693a824
DL		 6585 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6586 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6587 */
6588 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
aad941d5 6589 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
e29c22c0 6590 return -EINVAL;
44f46b42 6591
f5adf94e 6592 if (HAS_IPS(dev))
a43f6e0f
DV		 6593 hsw_compute_ips_config(crtc, pipe_config);
6594
877d48d5 6595 if (pipe_config->has_pch_encoder)
a43f6e0f 6596 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6597
cf5a15be 6598 return 0;
79e53945
JB		 6599}
6600
1652d19e
VS		 6601static int skylake_get_display_clock_speed(struct drm_device *dev)
6602{
6603 struct drm_i915_private *dev_priv = to_i915(dev);
6604 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6605 uint32_t cdctl = I915_READ(CDCLK_CTL);
6606 uint32_t linkrate;
6607
414355a7 6608 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6609 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6610
6611 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6612 return 540000;
6613
6614 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6615 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6616
71cd8423
DL		 6617 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6618 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6619 /* vco 8640 */
6620 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6621 case CDCLK_FREQ_450_432:
6622 return 432000;
6623 case CDCLK_FREQ_337_308:
6624 return 308570;
6625 case CDCLK_FREQ_675_617:
6626 return 617140;
6627 default:
6628 WARN(1, "Unknown cd freq selection\n");
6629 }
6630 } else {
6631 /* vco 8100 */
6632 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6633 case CDCLK_FREQ_450_432:
6634 return 450000;
6635 case CDCLK_FREQ_337_308:
6636 return 337500;
6637 case CDCLK_FREQ_675_617:
6638 return 675000;
6639 default:
6640 WARN(1, "Unknown cd freq selection\n");
6641 }
6642 }
6643
6644 /* error case, do as if DPLL0 isn't enabled */
6645 return 24000;
6646}
6647
acd3f3d3
BP		 6648static int broxton_get_display_clock_speed(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = to_i915(dev);
6651 uint32_t cdctl = I915_READ(CDCLK_CTL);
6652 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6653 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6654 int cdclk;
6655
6656 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6657 return 19200;
6658
6659 cdclk = 19200 * pll_ratio / 2;
6660
6661 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6662 case BXT_CDCLK_CD2X_DIV_SEL_1:
6663 return cdclk; /* 576MHz or 624MHz */
6664 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6665 return cdclk * 2 / 3; /* 384MHz */
6666 case BXT_CDCLK_CD2X_DIV_SEL_2:
6667 return cdclk / 2; /* 288MHz */
6668 case BXT_CDCLK_CD2X_DIV_SEL_4:
6669 return cdclk / 4; /* 144MHz */
6670 }
6671
6672 /* error case, do as if DE PLL isn't enabled */
6673 return 19200;
6674}
6675
1652d19e
VS		 6676static int broadwell_get_display_clock_speed(struct drm_device *dev)
6677{
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679 uint32_t lcpll = I915_READ(LCPLL_CTL);
6680 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6681
6682 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6683 return 800000;
6684 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6685 return 450000;
6686 else if (freq == LCPLL_CLK_FREQ_450)
6687 return 450000;
6688 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6689 return 540000;
6690 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6691 return 337500;
6692 else
6693 return 675000;
6694}
6695
6696static int haswell_get_display_clock_speed(struct drm_device *dev)
6697{
6698 struct drm_i915_private *dev_priv = dev->dev_private;
6699 uint32_t lcpll = I915_READ(LCPLL_CTL);
6700 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6701
6702 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6703 return 800000;
6704 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6705 return 450000;
6706 else if (freq == LCPLL_CLK_FREQ_450)
6707 return 450000;
6708 else if (IS_HSW_ULT(dev))
6709 return 337500;
6710 else
6711 return 540000;
79e53945
JB		 6712}
6713
25eb05fc
JB		 6714static int valleyview_get_display_clock_speed(struct drm_device *dev)
6715{
bfa7df01
VS		 6716 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6717 CCK_DISPLAY_CLOCK_CONTROL);
25eb05fc
JB		 6718}
6719
b37a6434
VS		 6720static int ilk_get_display_clock_speed(struct drm_device *dev)
6721{
6722 return 450000;
6723}
6724
e70236a8
JB		 6725static int i945_get_display_clock_speed(struct drm_device *dev)
6726{
6727 return 400000;
6728}
79e53945 6729
e70236a8 6730static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6731{
e907f170 6732 return 333333;
e70236a8 6733}
79e53945 6734
e70236a8
JB		 6735static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6736{
6737 return 200000;
6738}
79e53945 6739
257a7ffc
DV		 6740static int pnv_get_display_clock_speed(struct drm_device *dev)
6741{
6742 u16 gcfgc = 0;
6743
6744 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6745
6746 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6747 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6748 return 266667;
257a7ffc 6749 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6750 return 333333;
257a7ffc 6751 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6752 return 444444;
257a7ffc
DV		 6753 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6754 return 200000;
6755 default:
6756 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6757 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6758 return 133333;
257a7ffc 6759 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6760 return 166667;
257a7ffc
DV		 6761 }
6762}
6763
e70236a8
JB		 6764static int i915gm_get_display_clock_speed(struct drm_device *dev)
6765{
6766 u16 gcfgc = 0;
79e53945 6767
e70236a8
JB		 6768 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6769
6770 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6771 return 133333;
e70236a8
JB		 6772 else {
6773 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6774 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6775 return 333333;
e70236a8
JB		 6776 default:
6777 case GC_DISPLAY_CLOCK_190_200_MHZ:
6778 return 190000;
79e53945 6779 }
e70236a8
JB		 6780 }
6781}
6782
6783static int i865_get_display_clock_speed(struct drm_device *dev)
6784{
e907f170 6785 return 266667;
e70236a8
JB		 6786}
6787
1b1d2716 6788static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6789{
6790 u16 hpllcc = 0;
1b1d2716 6791
65cd2b3f
VS		 6792 /*
6793 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6794 * encoding is different :(
6795 * FIXME is this the right way to detect 852GM/852GMV?
6796 */
6797 if (dev->pdev->revision == 0x1)
6798 return 133333;
6799
1b1d2716
VS		 6800 pci_bus_read_config_word(dev->pdev->bus,
6801 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6802
e70236a8
JB		 6803 /* Assume that the hardware is in the high speed state. This
6804 * should be the default.
6805 */
6806 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6807 case GC_CLOCK_133_200:
1b1d2716 6808 case GC_CLOCK_133_200_2:
e70236a8
JB		 6809 case GC_CLOCK_100_200:
6810 return 200000;
6811 case GC_CLOCK_166_250:
6812 return 250000;
6813 case GC_CLOCK_100_133:
e907f170 6814 return 133333;
1b1d2716
VS		 6815 case GC_CLOCK_133_266:
6816 case GC_CLOCK_133_266_2:
6817 case GC_CLOCK_166_266:
6818 return 266667;
e70236a8 6819 }
79e53945 6820
e70236a8
JB		 6821 /* Shouldn't happen */
6822 return 0;
6823}
79e53945 6824
e70236a8
JB		 6825static int i830_get_display_clock_speed(struct drm_device *dev)
6826{
e907f170 6827 return 133333;
79e53945
JB		 6828}
6829
34edce2f
VS		 6830static unsigned int intel_hpll_vco(struct drm_device *dev)
6831{
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 static const unsigned int blb_vco[8] = {
6834 [0] = 3200000,
6835 [1] = 4000000,
6836 [2] = 5333333,
6837 [3] = 4800000,
6838 [4] = 6400000,
6839 };
6840 static const unsigned int pnv_vco[8] = {
6841 [0] = 3200000,
6842 [1] = 4000000,
6843 [2] = 5333333,
6844 [3] = 4800000,
6845 [4] = 2666667,
6846 };
6847 static const unsigned int cl_vco[8] = {
6848 [0] = 3200000,
6849 [1] = 4000000,
6850 [2] = 5333333,
6851 [3] = 6400000,
6852 [4] = 3333333,
6853 [5] = 3566667,
6854 [6] = 4266667,
6855 };
6856 static const unsigned int elk_vco[8] = {
6857 [0] = 3200000,
6858 [1] = 4000000,
6859 [2] = 5333333,
6860 [3] = 4800000,
6861 };
6862 static const unsigned int ctg_vco[8] = {
6863 [0] = 3200000,
6864 [1] = 4000000,
6865 [2] = 5333333,
6866 [3] = 6400000,
6867 [4] = 2666667,
6868 [5] = 4266667,
6869 };
6870 const unsigned int *vco_table;
6871 unsigned int vco;
6872 uint8_t tmp = 0;
6873
6874 /* FIXME other chipsets? */
6875 if (IS_GM45(dev))
6876 vco_table = ctg_vco;
6877 else if (IS_G4X(dev))
6878 vco_table = elk_vco;
6879 else if (IS_CRESTLINE(dev))
6880 vco_table = cl_vco;
6881 else if (IS_PINEVIEW(dev))
6882 vco_table = pnv_vco;
6883 else if (IS_G33(dev))
6884 vco_table = blb_vco;
6885 else
6886 return 0;
6887
6888 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6889
6890 vco = vco_table[tmp & 0x7];
6891 if (vco == 0)
6892 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6893 else
6894 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6895
6896 return vco;
6897}
6898
6899static int gm45_get_display_clock_speed(struct drm_device *dev)
6900{
6901 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6902 uint16_t tmp = 0;
6903
6904 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6905
6906 cdclk_sel = (tmp >> 12) & 0x1;
6907
6908 switch (vco) {
6909 case 2666667:
6910 case 4000000:
6911 case 5333333:
6912 return cdclk_sel ? 333333 : 222222;
6913 case 3200000:
6914 return cdclk_sel ? 320000 : 228571;
6915 default:
6916 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6917 return 222222;
6918 }
6919}
6920
6921static int i965gm_get_display_clock_speed(struct drm_device *dev)
6922{
6923 static const uint8_t div_3200[] = { 16, 10, 8 };
6924 static const uint8_t div_4000[] = { 20, 12, 10 };
6925 static const uint8_t div_5333[] = { 24, 16, 14 };
6926 const uint8_t *div_table;
6927 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6928 uint16_t tmp = 0;
6929
6930 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6931
6932 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6933
6934 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6935 goto fail;
6936
6937 switch (vco) {
6938 case 3200000:
6939 div_table = div_3200;
6940 break;
6941 case 4000000:
6942 div_table = div_4000;
6943 break;
6944 case 5333333:
6945 div_table = div_5333;
6946 break;
6947 default:
6948 goto fail;
6949 }
6950
6951 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6952
caf4e252 6953fail:
34edce2f
VS		 6954 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6955 return 200000;
6956}
6957
6958static int g33_get_display_clock_speed(struct drm_device *dev)
6959{
6960 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6961 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6962 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6963 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6964 const uint8_t *div_table;
6965 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6966 uint16_t tmp = 0;
6967
6968 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6969
6970 cdclk_sel = (tmp >> 4) & 0x7;
6971
6972 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6973 goto fail;
6974
6975 switch (vco) {
6976 case 3200000:
6977 div_table = div_3200;
6978 break;
6979 case 4000000:
6980 div_table = div_4000;
6981 break;
6982 case 4800000:
6983 div_table = div_4800;
6984 break;
6985 case 5333333:
6986 div_table = div_5333;
6987 break;
6988 default:
6989 goto fail;
6990 }
6991
6992 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6993
caf4e252 6994fail:
34edce2f
VS		 6995 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6996 return 190476;
6997}
6998
2c07245f 6999static void
a65851af 7000intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7001{
a65851af
VS		 7002 while (*num > DATA_LINK_M_N_MASK ||
7003 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7004 *num >>= 1;
7005 *den >>= 1;
7006 }
7007}
7008
a65851af
VS		 7009static void compute_m_n(unsigned int m, unsigned int n,
7010 uint32_t *ret_m, uint32_t *ret_n)
7011{
7012 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7013 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7014 intel_reduce_m_n_ratio(ret_m, ret_n);
7015}
7016
e69d0bc1
DV		 7017void
7018intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7019 int pixel_clock, int link_clock,
7020 struct intel_link_m_n *m_n)
2c07245f 7021{
e69d0bc1 7022 m_n->tu = 64;
a65851af
VS		 7023
7024 compute_m_n(bits_per_pixel * pixel_clock,
7025 link_clock * nlanes * 8,
7026 &m_n->gmch_m, &m_n->gmch_n);
7027
7028 compute_m_n(pixel_clock, link_clock,
7029 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7030}
7031
a7615030
CW		 7032static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7033{
d330a953
JN		 7034 if (i915.panel_use_ssc >= 0)
7035 return i915.panel_use_ssc != 0;
41aa3448 7036 return dev_priv->vbt.lvds_use_ssc
435793df 7037 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7038}
7039
a93e255f
ACO		 7040static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7041 int num_connectors)
c65d77d8 7042{
a93e255f 7043 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7044 struct drm_i915_private *dev_priv = dev->dev_private;
7045 int refclk;
7046
a93e255f
ACO		 7047 WARN_ON(!crtc_state->base.state);
7048
5ab7b0b7 7049 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7050 refclk = 100000;
a93e255f 7051 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7052 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7053 refclk = dev_priv->vbt.lvds_ssc_freq;
7054 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7055 } else if (!IS_GEN2(dev)) {
7056 refclk = 96000;
7057 } else {
7058 refclk = 48000;
7059 }
7060
7061 return refclk;
7062}
7063
7429e9d4 7064static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7065{
7df00d7a 7066 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7067}
f47709a9 7068
7429e9d4
DV		 7069static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7070{
7071 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7072}
7073
f47709a9 7074static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7075 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7076 intel_clock_t *reduced_clock)
7077{
f47709a9 7078 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7079 u32 fp, fp2 = 0;
7080
7081 if (IS_PINEVIEW(dev)) {
190f68c5 7082 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7083 if (reduced_clock)
7429e9d4 7084 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7085 } else {
190f68c5 7086 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7087 if (reduced_clock)
7429e9d4 7088 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7089 }
7090
190f68c5 7091 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7092
f47709a9 7093 crtc->lowfreq_avail = false;
a93e255f 7094 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7095 reduced_clock) {
190f68c5 7096 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7097 crtc->lowfreq_avail = true;
a7516a05 7098 } else {
190f68c5 7099 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7100 }
7101}
7102
5e69f97f
CML		 7103static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7104 pipe)
89b667f8
JB		 7105{
7106 u32 reg_val;
7107
7108 /*
7109 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7110 * and set it to a reasonable value instead.
7111 */
ab3c759a 7112 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7113 reg_val &= 0xffffff00;
7114 reg_val |= 0x00000030;
ab3c759a 7115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7116
ab3c759a 7117 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7118 reg_val &= 0x8cffffff;
7119 reg_val = 0x8c000000;
ab3c759a 7120 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7121
ab3c759a 7122 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7123 reg_val &= 0xffffff00;
ab3c759a 7124 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7125
ab3c759a 7126 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7127 reg_val &= 0x00ffffff;
7128 reg_val |= 0xb0000000;
ab3c759a 7129 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7130}
7131
b551842d
DV		 7132static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7133 struct intel_link_m_n *m_n)
7134{
7135 struct drm_device *dev = crtc->base.dev;
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137 int pipe = crtc->pipe;
7138
e3b95f1e
DV		 7139 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7140 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7141 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7142 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7143}
7144
7145static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7146 struct intel_link_m_n *m_n,
7147 struct intel_link_m_n *m2_n2)
b551842d
DV		 7148{
7149 struct drm_device *dev = crtc->base.dev;
7150 struct drm_i915_private *dev_priv = dev->dev_private;
7151 int pipe = crtc->pipe;
6e3c9717 7152 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7153
7154 if (INTEL_INFO(dev)->gen >= 5) {
7155 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7156 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7157 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7158 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7159 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7160 * for gen < 8) and if DRRS is supported (to make sure the
7161 * registers are not unnecessarily accessed).
7162 */
44395bfe 7163 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7164 crtc->config->has_drrs) {
f769cd24
VK		 7165 I915_WRITE(PIPE_DATA_M2(transcoder),
7166 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7167 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7168 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7169 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7170 }
b551842d 7171 } else {
e3b95f1e
DV		 7172 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7173 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7174 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7175 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7176 }
7177}
7178
fe3cd48d 7179void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7180{
fe3cd48d
R		 7181 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7182
7183 if (m_n == M1_N1) {
7184 dp_m_n = &crtc->config->dp_m_n;
7185 dp_m2_n2 = &crtc->config->dp_m2_n2;
7186 } else if (m_n == M2_N2) {
7187
7188 /*
7189 * M2_N2 registers are not supported. Hence m2_n2 divider value
7190 * needs to be programmed into M1_N1.
7191 */
7192 dp_m_n = &crtc->config->dp_m2_n2;
7193 } else {
7194 DRM_ERROR("Unsupported divider value\n");
7195 return;
7196 }
7197
6e3c9717
ACO		 7198 if (crtc->config->has_pch_encoder)
7199 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7200 else
fe3cd48d 7201 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7202}
7203
251ac862
DV		 7204static void vlv_compute_dpll(struct intel_crtc *crtc,
7205 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7206{
7207 u32 dpll, dpll_md;
7208
7209 /*
7210 * Enable DPIO clock input. We should never disable the reference
7211 * clock for pipe B, since VGA hotplug / manual detection depends
7212 * on it.
7213 */
60bfe44f
VS		 7214 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7215 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7216 /* We should never disable this, set it here for state tracking */
7217 if (crtc->pipe == PIPE_B)
7218 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7219 dpll |= DPLL_VCO_ENABLE;
d288f65f 7220 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7221
d288f65f 7222 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7224 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7225}
7226
d288f65f 7227static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7228 const struct intel_crtc_state *pipe_config)
a0c4da24 7229{
f47709a9 7230 struct drm_device *dev = crtc->base.dev;
a0c4da24 7231 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7232 int pipe = crtc->pipe;
bdd4b6a6 7233 u32 mdiv;
a0c4da24 7234 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7235 u32 coreclk, reg_val;
a0c4da24 7236
a580516d 7237 mutex_lock(&dev_priv->sb_lock);
09153000 7238
d288f65f
VS		 7239 bestn = pipe_config->dpll.n;
7240 bestm1 = pipe_config->dpll.m1;
7241 bestm2 = pipe_config->dpll.m2;
7242 bestp1 = pipe_config->dpll.p1;
7243 bestp2 = pipe_config->dpll.p2;
a0c4da24 7244
89b667f8
JB		 7245 /* See eDP HDMI DPIO driver vbios notes doc */
7246
7247 /* PLL B needs special handling */
bdd4b6a6 7248 if (pipe == PIPE_B)
5e69f97f 7249 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7250
7251 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7253
7254 /* Disable target IRef on PLL */
ab3c759a 7255 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7256 reg_val &= 0x00ffffff;
ab3c759a 7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7258
7259 /* Disable fast lock */
ab3c759a 7260 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7261
7262 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7263 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7264 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7265 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7266 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7267
7268 /*
7269 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7270 * but we don't support that).
7271 * Note: don't use the DAC post divider as it seems unstable.
7272 */
7273 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7274 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7275
a0c4da24 7276 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7278
89b667f8 7279 /* Set HBR and RBR LPF coefficients */
d288f65f 7280 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7281 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7282 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7284 0x009f0003);
89b667f8 7285 else
ab3c759a 7286 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7287 0x00d0000f);
7288
681a8504 7289 if (pipe_config->has_dp_encoder) {
89b667f8 7290 /* Use SSC source */
bdd4b6a6 7291 if (pipe == PIPE_A)
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7293 0x0df40000);
7294 else
ab3c759a 7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7296 0x0df70000);
7297 } else { /* HDMI or VGA */
7298 /* Use bend source */
bdd4b6a6 7299 if (pipe == PIPE_A)
ab3c759a 7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7301 0x0df70000);
7302 else
ab3c759a 7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7304 0x0df40000);
7305 }
a0c4da24 7306
ab3c759a 7307 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7308 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7309 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7311 coreclk |= 0x01000000;
ab3c759a 7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7313
ab3c759a 7314 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7315 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7316}
7317
251ac862
DV		 7318static void chv_compute_dpll(struct intel_crtc *crtc,
7319 struct intel_crtc_state *pipe_config)
1ae0d137 7320{
60bfe44f
VS		 7321 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7322 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7323 DPLL_VCO_ENABLE;
7324 if (crtc->pipe != PIPE_A)
d288f65f 7325 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7326
d288f65f
VS		 7327 pipe_config->dpll_hw_state.dpll_md =
7328 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7329}
7330
d288f65f 7331static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7332 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7333{
7334 struct drm_device *dev = crtc->base.dev;
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 int pipe = crtc->pipe;
7337 int dpll_reg = DPLL(crtc->pipe);
7338 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7339 u32 loopfilter, tribuf_calcntr;
9d556c99 7340 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7341 u32 dpio_val;
9cbe40c1 7342 int vco;
9d556c99 7343
d288f65f
VS		 7344 bestn = pipe_config->dpll.n;
7345 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7346 bestm1 = pipe_config->dpll.m1;
7347 bestm2 = pipe_config->dpll.m2 >> 22;
7348 bestp1 = pipe_config->dpll.p1;
7349 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7350 vco = pipe_config->dpll.vco;
a945ce7e 7351 dpio_val = 0;
9cbe40c1 7352 loopfilter = 0;
9d556c99
CML		 7353
7354 /*
7355 * Enable Refclk and SSC
7356 */
a11b0703 7357 I915_WRITE(dpll_reg,
d288f65f 7358 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7359
a580516d 7360 mutex_lock(&dev_priv->sb_lock);
9d556c99 7361
9d556c99
CML		 7362 /* p1 and p2 divider */
7363 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7364 5 << DPIO_CHV_S1_DIV_SHIFT |
7365 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7366 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7367 1 << DPIO_CHV_K_DIV_SHIFT);
7368
7369 /* Feedback post-divider - m2 */
7370 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7371
7372 /* Feedback refclk divider - n and m1 */
7373 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7374 DPIO_CHV_M1_DIV_BY_2 |
7375 1 << DPIO_CHV_N_DIV_SHIFT);
7376
7377 /* M2 fraction division */
25a25dfc 7378 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7379
7380 /* M2 fraction division enable */
a945ce7e
VP		 7381 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7382 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7383 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7384 if (bestm2_frac)
7385 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7386 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7387
de3a0fde
VP		 7388 /* Program digital lock detect threshold */
7389 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7390 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7391 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7392 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7393 if (!bestm2_frac)
7394 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7395 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7396
9d556c99 7397 /* Loop filter */
9cbe40c1
VP		 7398 if (vco == 5400000) {
7399 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7400 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7401 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7402 tribuf_calcntr = 0x9;
7403 } else if (vco <= 6200000) {
7404 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7405 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7406 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7407 tribuf_calcntr = 0x9;
7408 } else if (vco <= 6480000) {
7409 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7410 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7411 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7412 tribuf_calcntr = 0x8;
7413 } else {
7414 /* Not supported. Apply the same limits as in the max case */
7415 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7416 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7417 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7418 tribuf_calcntr = 0;
7419 }
9d556c99
CML		 7420 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7421
968040b2 7422 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7423 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7424 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7425 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7426
9d556c99
CML		 7427 /* AFC Recal */
7428 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7429 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7430 DPIO_AFC_RECAL);
7431
a580516d 7432 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7433}
7434
d288f65f
VS		 7435/**
7436 * vlv_force_pll_on - forcibly enable just the PLL
7437 * @dev_priv: i915 private structure
7438 * @pipe: pipe PLL to enable
7439 * @dpll: PLL configuration
7440 *
7441 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7442 * in cases where we need the PLL enabled even when @pipe is not going to
7443 * be enabled.
7444 */
7445void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7446 const struct dpll *dpll)
7447{
7448 struct intel_crtc *crtc =
7449 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7450 struct intel_crtc_state pipe_config = {
a93e255f 7451 .base.crtc = &crtc->base,
d288f65f
VS		 7452 .pixel_multiplier = 1,
7453 .dpll = *dpll,
7454 };
7455
7456 if (IS_CHERRYVIEW(dev)) {
251ac862 7457 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7458 chv_prepare_pll(crtc, &pipe_config);
7459 chv_enable_pll(crtc, &pipe_config);
7460 } else {
251ac862 7461 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7462 vlv_prepare_pll(crtc, &pipe_config);
7463 vlv_enable_pll(crtc, &pipe_config);
7464 }
7465}
7466
7467/**
7468 * vlv_force_pll_off - forcibly disable just the PLL
7469 * @dev_priv: i915 private structure
7470 * @pipe: pipe PLL to disable
7471 *
7472 * Disable the PLL for @pipe. To be used in cases where we need
7473 * the PLL enabled even when @pipe is not going to be enabled.
7474 */
7475void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7476{
7477 if (IS_CHERRYVIEW(dev))
7478 chv_disable_pll(to_i915(dev), pipe);
7479 else
7480 vlv_disable_pll(to_i915(dev), pipe);
7481}
7482
251ac862
DV		 7483static void i9xx_compute_dpll(struct intel_crtc *crtc,
7484 struct intel_crtc_state *crtc_state,
7485 intel_clock_t *reduced_clock,
7486 int num_connectors)
eb1cbe48 7487{
f47709a9 7488 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7489 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7490 u32 dpll;
7491 bool is_sdvo;
190f68c5 7492 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7493
190f68c5 7494 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7495
a93e255f
ACO		 7496 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7497 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7498
7499 dpll = DPLL_VGA_MODE_DIS;
7500
a93e255f 7501 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7502 dpll |= DPLLB_MODE_LVDS;
7503 else
7504 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7505
ef1b460d 7506 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7507 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7508 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7509 }
198a037f
DV		 7510
7511 if (is_sdvo)
4a33e48d 7512 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7513
190f68c5 7514 if (crtc_state->has_dp_encoder)
4a33e48d 7515 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7516
7517 /* compute bitmask from p1 value */
7518 if (IS_PINEVIEW(dev))
7519 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7520 else {
7521 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7522 if (IS_G4X(dev) && reduced_clock)
7523 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7524 }
7525 switch (clock->p2) {
7526 case 5:
7527 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7528 break;
7529 case 7:
7530 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7531 break;
7532 case 10:
7533 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7534 break;
7535 case 14:
7536 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7537 break;
7538 }
7539 if (INTEL_INFO(dev)->gen >= 4)
7540 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7541
190f68c5 7542 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7543 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7544 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7545 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7546 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7547 else
7548 dpll |= PLL_REF_INPUT_DREFCLK;
7549
7550 dpll |= DPLL_VCO_ENABLE;
190f68c5 7551 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7552
eb1cbe48 7553 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7554 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7555 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7556 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7557 }
7558}
7559
251ac862
DV		 7560static void i8xx_compute_dpll(struct intel_crtc *crtc,
7561 struct intel_crtc_state *crtc_state,
7562 intel_clock_t *reduced_clock,
7563 int num_connectors)
eb1cbe48 7564{
f47709a9 7565 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7566 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7567 u32 dpll;
190f68c5 7568 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7569
190f68c5 7570 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7571
eb1cbe48
DV		 7572 dpll = DPLL_VGA_MODE_DIS;
7573
a93e255f 7574 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7575 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7576 } else {
7577 if (clock->p1 == 2)
7578 dpll |= PLL_P1_DIVIDE_BY_TWO;
7579 else
7580 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7581 if (clock->p2 == 4)
7582 dpll |= PLL_P2_DIVIDE_BY_4;
7583 }
7584
a93e255f 7585 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7586 dpll |= DPLL_DVO_2X_MODE;
7587
a93e255f 7588 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7591 else
7592 dpll |= PLL_REF_INPUT_DREFCLK;
7593
7594 dpll |= DPLL_VCO_ENABLE;
190f68c5 7595 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7596}
7597
8a654f3b 7598static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7599{
7600 struct drm_device *dev = intel_crtc->base.dev;
7601 struct drm_i915_private *dev_priv = dev->dev_private;
7602 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7603 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 7604 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7605 uint32_t crtc_vtotal, crtc_vblank_end;
7606 int vsyncshift = 0;
4d8a62ea
DV		 7607
7608 /* We need to be careful not to changed the adjusted mode, for otherwise
7609 * the hw state checker will get angry at the mismatch. */
7610 crtc_vtotal = adjusted_mode->crtc_vtotal;
7611 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7612
609aeaca 7613 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7614 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7615 crtc_vtotal -= 1;
7616 crtc_vblank_end -= 1;
609aeaca 7617
409ee761 7618 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7619 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7620 else
7621 vsyncshift = adjusted_mode->crtc_hsync_start -
7622 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7623 if (vsyncshift < 0)
7624 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7625 }
7626
7627 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7628 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7629
fe2b8f9d 7630 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7631 (adjusted_mode->crtc_hdisplay - 1) |
7632 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7633 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7634 (adjusted_mode->crtc_hblank_start - 1) |
7635 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7636 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7637 (adjusted_mode->crtc_hsync_start - 1) |
7638 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7639
fe2b8f9d 7640 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7641 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7642 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7643 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7644 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7645 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7646 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7647 (adjusted_mode->crtc_vsync_start - 1) |
7648 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7649
b5e508d4
PZ		 7650 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7651 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7652 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7653 * bits. */
7654 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7655 (pipe == PIPE_B || pipe == PIPE_C))
7656 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7657
b0e77b9c
PZ		 7658 /* pipesrc controls the size that is scaled from, which should
7659 * always be the user's requested size.
7660 */
7661 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7662 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7663 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7664}
7665
1bd1bd80 7666static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7667 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7668{
7669 struct drm_device *dev = crtc->base.dev;
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7672 uint32_t tmp;
7673
7674 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7675 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7676 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7677 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7678 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7679 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7680 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7681 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7682 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7683
7684 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7685 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7686 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7687 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7688 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7689 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7690 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7691 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7692 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7693
7694 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7695 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7696 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7697 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7698 }
7699
7700 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7701 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7702 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7703
2d112de7
ACO		 7704 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7705 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7706}
7707
f6a83288 7708void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7709 struct intel_crtc_state *pipe_config)
babea61d 7710{
2d112de7
ACO		 7711 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7712 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7713 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7714 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7715
2d112de7
ACO		 7716 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7717 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7718 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7719 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7720
2d112de7 7721 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7722 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7723
2d112de7
ACO		 7724 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7725 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7726
7727 mode->hsync = drm_mode_hsync(mode);
7728 mode->vrefresh = drm_mode_vrefresh(mode);
7729 drm_mode_set_name(mode);
babea61d
JB		 7730}
7731
84b046f3
DV		 7732static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7733{
7734 struct drm_device *dev = intel_crtc->base.dev;
7735 struct drm_i915_private *dev_priv = dev->dev_private;
7736 uint32_t pipeconf;
7737
9f11a9e4 7738 pipeconf = 0;
84b046f3 7739
b6b5d049
VS		 7740 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7741 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7742 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7743
6e3c9717 7744 if (intel_crtc->config->double_wide)
cf532bb2 7745 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7746
ff9ce46e
DV		 7747 /* only g4x and later have fancy bpc/dither controls */
7748 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7749 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7750 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7751 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7752 PIPECONF_DITHER_TYPE_SP;
84b046f3 7753
6e3c9717 7754 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7755 case 18:
7756 pipeconf |= PIPECONF_6BPC;
7757 break;
7758 case 24:
7759 pipeconf |= PIPECONF_8BPC;
7760 break;
7761 case 30:
7762 pipeconf |= PIPECONF_10BPC;
7763 break;
7764 default:
7765 /* Case prevented by intel_choose_pipe_bpp_dither. */
7766 BUG();
84b046f3
DV		 7767 }
7768 }
7769
7770 if (HAS_PIPE_CXSR(dev)) {
7771 if (intel_crtc->lowfreq_avail) {
7772 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7773 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7774 } else {
7775 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7776 }
7777 }
7778
6e3c9717 7779 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7780 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7781 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7782 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7783 else
7784 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7785 } else
84b046f3
DV		 7786 pipeconf |= PIPECONF_PROGRESSIVE;
7787
6e3c9717 7788 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7790
84b046f3
DV		 7791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7792 POSTING_READ(PIPECONF(intel_crtc->pipe));
7793}
7794
190f68c5
ACO		 7795static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7796 struct intel_crtc_state *crtc_state)
79e53945 7797{
c7653199 7798 struct drm_device *dev = crtc->base.dev;
79e53945 7799 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7800 int refclk, num_connectors = 0;
c329a4ec
DV		 7801 intel_clock_t clock;
7802 bool ok;
7803 bool is_dsi = false;
5eddb70b 7804 struct intel_encoder *encoder;
d4906093 7805 const intel_limit_t *limit;
55bb9992 7806 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7807 struct drm_connector *connector;
55bb9992
ACO		 7808 struct drm_connector_state *connector_state;
7809 int i;
79e53945 7810
dd3cd74a
ACO		 7811 memset(&crtc_state->dpll_hw_state, 0,
7812 sizeof(crtc_state->dpll_hw_state));
7813
da3ced29 7814 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7815 if (connector_state->crtc != &crtc->base)
7816 continue;
7817
7818 encoder = to_intel_encoder(connector_state->best_encoder);
7819
5eddb70b 7820 switch (encoder->type) {
e9fd1c02
JN		 7821 case INTEL_OUTPUT_DSI:
7822 is_dsi = true;
7823 break;
6847d71b
PZ		 7824 default:
7825 break;
79e53945 7826 }
43565a06 7827
c751ce4f 7828 num_connectors++;
79e53945
JB		 7829 }
7830
f2335330 7831 if (is_dsi)
5b18e57c 7832 return 0;
f2335330 7833
190f68c5 7834 if (!crtc_state->clock_set) {
a93e255f 7835 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7836
e9fd1c02
JN		 7837 /*
7838 * Returns a set of divisors for the desired target clock with
7839 * the given refclk, or FALSE. The returned values represent
7840 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7841 * 2) / p1 / p2.
7842 */
a93e255f
ACO		 7843 limit = intel_limit(crtc_state, refclk);
7844 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7845 crtc_state->port_clock,
e9fd1c02 7846 refclk, NULL, &clock);
f2335330 7847 if (!ok) {
e9fd1c02
JN		 7848 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7849 return -EINVAL;
7850 }
79e53945 7851
f2335330 7852 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7853 crtc_state->dpll.n = clock.n;
7854 crtc_state->dpll.m1 = clock.m1;
7855 crtc_state->dpll.m2 = clock.m2;
7856 crtc_state->dpll.p1 = clock.p1;
7857 crtc_state->dpll.p2 = clock.p2;
f47709a9 7858 }
7026d4ac 7859
e9fd1c02 7860 if (IS_GEN2(dev)) {
c329a4ec 7861 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7862 num_connectors);
9d556c99 7863 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7864 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7865 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7866 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7867 } else {
c329a4ec 7868 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7869 num_connectors);
e9fd1c02 7870 }
79e53945 7871
c8f7a0db 7872 return 0;
f564048e
EA		 7873}
7874
2fa2fe9a 7875static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7876 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7877{
7878 struct drm_device *dev = crtc->base.dev;
7879 struct drm_i915_private *dev_priv = dev->dev_private;
7880 uint32_t tmp;
7881
dc9e7dec
VS		 7882 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7883 return;
7884
2fa2fe9a 7885 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7886 if (!(tmp & PFIT_ENABLE))
7887 return;
2fa2fe9a 7888
06922821 7889 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7890 if (INTEL_INFO(dev)->gen < 4) {
7891 if (crtc->pipe != PIPE_B)
7892 return;
2fa2fe9a
DV		 7893 } else {
7894 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7895 return;
7896 }
7897
06922821 7898 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7899 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7900 if (INTEL_INFO(dev)->gen < 5)
7901 pipe_config->gmch_pfit.lvds_border_bits =
7902 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7903}
7904
acbec814 7905static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7906 struct intel_crtc_state *pipe_config)
acbec814
JB		 7907{
7908 struct drm_device *dev = crtc->base.dev;
7909 struct drm_i915_private *dev_priv = dev->dev_private;
7910 int pipe = pipe_config->cpu_transcoder;
7911 intel_clock_t clock;
7912 u32 mdiv;
662c6ecb 7913 int refclk = 100000;
acbec814 7914
f573de5a
SK		 7915 /* In case of MIPI DPLL will not even be used */
7916 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7917 return;
7918
a580516d 7919 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7920 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7921 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7922
7923 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7924 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7925 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7926 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7927 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7928
dccbea3b 7929 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7930}
7931
5724dbd1
DL		 7932static void
7933i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7934 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7935{
7936 struct drm_device *dev = crtc->base.dev;
7937 struct drm_i915_private *dev_priv = dev->dev_private;
7938 u32 val, base, offset;
7939 int pipe = crtc->pipe, plane = crtc->plane;
7940 int fourcc, pixel_format;
6761dd31 7941 unsigned int aligned_height;
b113d5ee 7942 struct drm_framebuffer *fb;
1b842c89 7943 struct intel_framebuffer *intel_fb;
1ad292b5 7944
42a7b088
DL		 7945 val = I915_READ(DSPCNTR(plane));
7946 if (!(val & DISPLAY_PLANE_ENABLE))
7947 return;
7948
d9806c9f 7949 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7950 if (!intel_fb) {
1ad292b5
JB		 7951 DRM_DEBUG_KMS("failed to alloc fb\n");
7952 return;
7953 }
7954
1b842c89
DL		 7955 fb = &intel_fb->base;
7956
18c5247e
DV		 7957 if (INTEL_INFO(dev)->gen >= 4) {
7958 if (val & DISPPLANE_TILED) {
49af449b 7959 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7960 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7961 }
7962 }
1ad292b5
JB		 7963
7964 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7965 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7966 fb->pixel_format = fourcc;
7967 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7968
7969 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7970 if (plane_config->tiling)
1ad292b5
JB		 7971 offset = I915_READ(DSPTILEOFF(plane));
7972 else
7973 offset = I915_READ(DSPLINOFF(plane));
7974 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7975 } else {
7976 base = I915_READ(DSPADDR(plane));
7977 }
7978 plane_config->base = base;
7979
7980 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7981 fb->width = ((val >> 16) & 0xfff) + 1;
7982 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7983
7984 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7985 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7986
b113d5ee 7987 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7988 fb->pixel_format,
7989 fb->modifier[0]);
1ad292b5 7990
f37b5c2b 7991 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7992
2844a921
DL		 7993 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7994 pipe_name(pipe), plane, fb->width, fb->height,
7995 fb->bits_per_pixel, base, fb->pitches[0],
7996 plane_config->size);
1ad292b5 7997
2d14030b 7998 plane_config->fb = intel_fb;
1ad292b5
JB		 7999}
8000
70b23a98 8001static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8002 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8003{
8004 struct drm_device *dev = crtc->base.dev;
8005 struct drm_i915_private *dev_priv = dev->dev_private;
8006 int pipe = pipe_config->cpu_transcoder;
8007 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8008 intel_clock_t clock;
0d7b6b11 8009 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 8010 int refclk = 100000;
8011
a580516d 8012 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8013 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8014 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8015 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8016 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 8017 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 8018 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8019
8020 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 8021 clock.m2 = (pll_dw0 & 0xff) << 22;
8022 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8023 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 8024 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8025 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8026 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8027
dccbea3b 8028 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8029}
8030
0e8ffe1b 8031static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8032 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8033{
8034 struct drm_device *dev = crtc->base.dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 uint32_t tmp;
8037
f458ebbc
DV		 8038 if (!intel_display_power_is_enabled(dev_priv,
8039 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8040 return false;
8041
e143a21c 8042 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8043 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8044
0e8ffe1b
DV		 8045 tmp = I915_READ(PIPECONF(crtc->pipe));
8046 if (!(tmp & PIPECONF_ENABLE))
8047 return false;
8048
42571aef
VS		 8049 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8050 switch (tmp & PIPECONF_BPC_MASK) {
8051 case PIPECONF_6BPC:
8052 pipe_config->pipe_bpp = 18;
8053 break;
8054 case PIPECONF_8BPC:
8055 pipe_config->pipe_bpp = 24;
8056 break;
8057 case PIPECONF_10BPC:
8058 pipe_config->pipe_bpp = 30;
8059 break;
8060 default:
8061 break;
8062 }
8063 }
8064
b5a9fa09
DV		 8065 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8066 pipe_config->limited_color_range = true;
8067
282740f7
VS		 8068 if (INTEL_INFO(dev)->gen < 4)
8069 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8070
1bd1bd80
DV		 8071 intel_get_pipe_timings(crtc, pipe_config);
8072
2fa2fe9a
DV		 8073 i9xx_get_pfit_config(crtc, pipe_config);
8074
6c49f241
DV		 8075 if (INTEL_INFO(dev)->gen >= 4) {
8076 tmp = I915_READ(DPLL_MD(crtc->pipe));
8077 pipe_config->pixel_multiplier =
8078 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8079 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8080 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8081 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8082 tmp = I915_READ(DPLL(crtc->pipe));
8083 pipe_config->pixel_multiplier =
8084 ((tmp & SDVO_MULTIPLIER_MASK)
8085 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8086 } else {
8087 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8088 * port and will be fixed up in the encoder->get_config
8089 * function. */
8090 pipe_config->pixel_multiplier = 1;
8091 }
8bcc2795
DV		 8092 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8093 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8094 /*
8095 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8096 * on 830. Filter it out here so that we don't
8097 * report errors due to that.
8098 */
8099 if (IS_I830(dev))
8100 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8101
8bcc2795
DV		 8102 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8103 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8104 } else {
8105 /* Mask out read-only status bits. */
8106 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8107 DPLL_PORTC_READY_MASK |
8108 DPLL_PORTB_READY_MASK);
8bcc2795 8109 }
6c49f241 8110
70b23a98
VS		 8111 if (IS_CHERRYVIEW(dev))
8112 chv_crtc_clock_get(crtc, pipe_config);
8113 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8114 vlv_crtc_clock_get(crtc, pipe_config);
8115 else
8116 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8117
0f64614d
VS		 8118 /*
8119 * Normally the dotclock is filled in by the encoder .get_config()
8120 * but in case the pipe is enabled w/o any ports we need a sane
8121 * default.
8122 */
8123 pipe_config->base.adjusted_mode.crtc_clock =
8124 pipe_config->port_clock / pipe_config->pixel_multiplier;
8125
0e8ffe1b
DV		 8126 return true;
8127}
8128
dde86e2d 8129static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8130{
8131 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8132 struct intel_encoder *encoder;
74cfd7ac 8133 u32 val, final;
13d83a67 8134 bool has_lvds = false;
199e5d79 8135 bool has_cpu_edp = false;
199e5d79 8136 bool has_panel = false;
99eb6a01
KP		 8137 bool has_ck505 = false;
8138 bool can_ssc = false;
13d83a67
JB		 8139
8140 /* We need to take the global config into account */
b2784e15 8141 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8142 switch (encoder->type) {
8143 case INTEL_OUTPUT_LVDS:
8144 has_panel = true;
8145 has_lvds = true;
8146 break;
8147 case INTEL_OUTPUT_EDP:
8148 has_panel = true;
2de6905f 8149 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8150 has_cpu_edp = true;
8151 break;
6847d71b
PZ		 8152 default:
8153 break;
13d83a67
JB		 8154 }
8155 }
8156
99eb6a01 8157 if (HAS_PCH_IBX(dev)) {
41aa3448 8158 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8159 can_ssc = has_ck505;
8160 } else {
8161 has_ck505 = false;
8162 can_ssc = true;
8163 }
8164
2de6905f
ID		 8165 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8166 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8167
8168 /* Ironlake: try to setup display ref clock before DPLL
8169 * enabling. This is only under driver's control after
8170 * PCH B stepping, previous chipset stepping should be
8171 * ignoring this setting.
8172 */
74cfd7ac
CW		 8173 val = I915_READ(PCH_DREF_CONTROL);
8174
8175 /* As we must carefully and slowly disable/enable each source in turn,
8176 * compute the final state we want first and check if we need to
8177 * make any changes at all.
8178 */
8179 final = val;
8180 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8181 if (has_ck505)
8182 final |= DREF_NONSPREAD_CK505_ENABLE;
8183 else
8184 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8185
8186 final &= ~DREF_SSC_SOURCE_MASK;
8187 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8188 final &= ~DREF_SSC1_ENABLE;
8189
8190 if (has_panel) {
8191 final |= DREF_SSC_SOURCE_ENABLE;
8192
8193 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8194 final |= DREF_SSC1_ENABLE;
8195
8196 if (has_cpu_edp) {
8197 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8198 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8199 else
8200 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8201 } else
8202 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8203 } else {
8204 final |= DREF_SSC_SOURCE_DISABLE;
8205 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8206 }
8207
8208 if (final == val)
8209 return;
8210
13d83a67 8211 /* Always enable nonspread source */
74cfd7ac 8212 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8213
99eb6a01 8214 if (has_ck505)
74cfd7ac 8215 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8216 else
74cfd7ac 8217 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8218
199e5d79 8219 if (has_panel) {
74cfd7ac
CW		 8220 val &= ~DREF_SSC_SOURCE_MASK;
8221 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8222
199e5d79 8223 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8224 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8225 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8226 val |= DREF_SSC1_ENABLE;
e77166b5 8227 } else
74cfd7ac 8228 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8229
8230 /* Get SSC going before enabling the outputs */
74cfd7ac 8231 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8232 POSTING_READ(PCH_DREF_CONTROL);
8233 udelay(200);
8234
74cfd7ac 8235 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8236
8237 /* Enable CPU source on CPU attached eDP */
199e5d79 8238 if (has_cpu_edp) {
99eb6a01 8239 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8240 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8241 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8242 } else
74cfd7ac 8243 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8244 } else
74cfd7ac 8245 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8246
74cfd7ac 8247 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8248 POSTING_READ(PCH_DREF_CONTROL);
8249 udelay(200);
8250 } else {
8251 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8252
74cfd7ac 8253 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8254
8255 /* Turn off CPU output */
74cfd7ac 8256 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8257
74cfd7ac 8258 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8259 POSTING_READ(PCH_DREF_CONTROL);
8260 udelay(200);
8261
8262 /* Turn off the SSC source */
74cfd7ac
CW		 8263 val &= ~DREF_SSC_SOURCE_MASK;
8264 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8265
8266 /* Turn off SSC1 */
74cfd7ac 8267 val &= ~DREF_SSC1_ENABLE;
199e5d79 8268
74cfd7ac 8269 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8270 POSTING_READ(PCH_DREF_CONTROL);
8271 udelay(200);
8272 }
74cfd7ac
CW		 8273
8274 BUG_ON(val != final);
13d83a67
JB		 8275}
8276
f31f2d55 8277static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8278{
f31f2d55 8279 uint32_t tmp;
dde86e2d 8280
0ff066a9
PZ		 8281 tmp = I915_READ(SOUTH_CHICKEN2);
8282 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8283 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8284
0ff066a9
PZ		 8285 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8286 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8287 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8288
0ff066a9
PZ		 8289 tmp = I915_READ(SOUTH_CHICKEN2);
8290 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8291 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8292
0ff066a9
PZ		 8293 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8294 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8295 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8296}
8297
8298/* WaMPhyProgramming:hsw */
8299static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8300{
8301 uint32_t tmp;
dde86e2d
PZ		 8302
8303 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8304 tmp &= ~(0xFF << 24);
8305 tmp |= (0x12 << 24);
8306 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8307
dde86e2d
PZ		 8308 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8309 tmp |= (1 << 11);
8310 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8311
8312 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8313 tmp |= (1 << 11);
8314 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8315
dde86e2d
PZ		 8316 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8317 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8318 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8319
8320 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8321 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8322 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8323
0ff066a9
PZ		 8324 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8325 tmp &= ~(7 << 13);
8326 tmp |= (5 << 13);
8327 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8328
0ff066a9
PZ		 8329 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8330 tmp &= ~(7 << 13);
8331 tmp |= (5 << 13);
8332 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8333
8334 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8335 tmp &= ~0xFF;
8336 tmp |= 0x1C;
8337 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8338
8339 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8340 tmp &= ~0xFF;
8341 tmp |= 0x1C;
8342 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8343
8344 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8345 tmp &= ~(0xFF << 16);
8346 tmp |= (0x1C << 16);
8347 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8348
8349 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8350 tmp &= ~(0xFF << 16);
8351 tmp |= (0x1C << 16);
8352 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8353
0ff066a9
PZ		 8354 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8355 tmp |= (1 << 27);
8356 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8357
0ff066a9
PZ		 8358 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8359 tmp |= (1 << 27);
8360 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8361
0ff066a9
PZ		 8362 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8363 tmp &= ~(0xF << 28);
8364 tmp |= (4 << 28);
8365 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8366
0ff066a9
PZ		 8367 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8368 tmp &= ~(0xF << 28);
8369 tmp |= (4 << 28);
8370 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8371}
8372
2fa86a1f
PZ		 8373/* Implements 3 different sequences from BSpec chapter "Display iCLK
8374 * Programming" based on the parameters passed:
8375 * - Sequence to enable CLKOUT_DP
8376 * - Sequence to enable CLKOUT_DP without spread
8377 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8378 */
8379static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8380 bool with_fdi)
f31f2d55
PZ		 8381{
8382 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8383 uint32_t reg, tmp;
8384
8385 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8386 with_spread = true;
c2699524 8387 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8388 with_fdi = false;
f31f2d55 8389
a580516d 8390 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8391
8392 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8393 tmp &= ~SBI_SSCCTL_DISABLE;
8394 tmp |= SBI_SSCCTL_PATHALT;
8395 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8396
8397 udelay(24);
8398
2fa86a1f
PZ		 8399 if (with_spread) {
8400 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8401 tmp &= ~SBI_SSCCTL_PATHALT;
8402 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8403
2fa86a1f
PZ		 8404 if (with_fdi) {
8405 lpt_reset_fdi_mphy(dev_priv);
8406 lpt_program_fdi_mphy(dev_priv);
8407 }
8408 }
dde86e2d 8409
c2699524 8410 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8411 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8412 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8413 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8414
a580516d 8415 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8416}
8417
47701c3b
PZ		 8418/* Sequence to disable CLKOUT_DP */
8419static void lpt_disable_clkout_dp(struct drm_device *dev)
8420{
8421 struct drm_i915_private *dev_priv = dev->dev_private;
8422 uint32_t reg, tmp;
8423
a580516d 8424 mutex_lock(&dev_priv->sb_lock);
47701c3b 8425
c2699524 8426 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8427 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8428 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8429 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8430
8431 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8432 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8433 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8434 tmp |= SBI_SSCCTL_PATHALT;
8435 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8436 udelay(32);
8437 }
8438 tmp |= SBI_SSCCTL_DISABLE;
8439 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8440 }
8441
a580516d 8442 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8443}
8444
bf8fa3d3
PZ		 8445static void lpt_init_pch_refclk(struct drm_device *dev)
8446{
bf8fa3d3
PZ		 8447 struct intel_encoder *encoder;
8448 bool has_vga = false;
8449
b2784e15 8450 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8451 switch (encoder->type) {
8452 case INTEL_OUTPUT_ANALOG:
8453 has_vga = true;
8454 break;
6847d71b
PZ		 8455 default:
8456 break;
bf8fa3d3
PZ		 8457 }
8458 }
8459
47701c3b
PZ		 8460 if (has_vga)
8461 lpt_enable_clkout_dp(dev, true, true);
8462 else
8463 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8464}
8465
dde86e2d
PZ		 8466/*
8467 * Initialize reference clocks when the driver loads
8468 */
8469void intel_init_pch_refclk(struct drm_device *dev)
8470{
8471 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8472 ironlake_init_pch_refclk(dev);
8473 else if (HAS_PCH_LPT(dev))
8474 lpt_init_pch_refclk(dev);
8475}
8476
55bb9992 8477static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8478{
55bb9992 8479 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8480 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8481 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8482 struct drm_connector *connector;
55bb9992 8483 struct drm_connector_state *connector_state;
d9d444cb 8484 struct intel_encoder *encoder;
55bb9992 8485 int num_connectors = 0, i;
d9d444cb
JB		 8486 bool is_lvds = false;
8487
da3ced29 8488 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8489 if (connector_state->crtc != crtc_state->base.crtc)
8490 continue;
8491
8492 encoder = to_intel_encoder(connector_state->best_encoder);
8493
d9d444cb
JB		 8494 switch (encoder->type) {
8495 case INTEL_OUTPUT_LVDS:
8496 is_lvds = true;
8497 break;
6847d71b
PZ		 8498 default:
8499 break;
d9d444cb
JB		 8500 }
8501 num_connectors++;
8502 }
8503
8504 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8505 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8506 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8507 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8508 }
8509
8510 return 120000;
8511}
8512
6ff93609 8513static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8514{
c8203565 8515 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8517 int pipe = intel_crtc->pipe;
c8203565
PZ		 8518 uint32_t val;
8519
78114071 8520 val = 0;
c8203565 8521
6e3c9717 8522 switch (intel_crtc->config->pipe_bpp) {
c8203565 8523 case 18:
dfd07d72 8524 val |= PIPECONF_6BPC;
c8203565
PZ		 8525 break;
8526 case 24:
dfd07d72 8527 val |= PIPECONF_8BPC;
c8203565
PZ		 8528 break;
8529 case 30:
dfd07d72 8530 val |= PIPECONF_10BPC;
c8203565
PZ		 8531 break;
8532 case 36:
dfd07d72 8533 val |= PIPECONF_12BPC;
c8203565
PZ		 8534 break;
8535 default:
cc769b62
PZ		 8536 /* Case prevented by intel_choose_pipe_bpp_dither. */
8537 BUG();
c8203565
PZ		 8538 }
8539
6e3c9717 8540 if (intel_crtc->config->dither)
c8203565
PZ		 8541 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8542
6e3c9717 8543 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8544 val |= PIPECONF_INTERLACED_ILK;
8545 else
8546 val |= PIPECONF_PROGRESSIVE;
8547
6e3c9717 8548 if (intel_crtc->config->limited_color_range)
3685a8f3 8549 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8550
c8203565
PZ		 8551 I915_WRITE(PIPECONF(pipe), val);
8552 POSTING_READ(PIPECONF(pipe));
8553}
8554
86d3efce
VS		 8555/*
8556 * Set up the pipe CSC unit.
8557 *
8558 * Currently only full range RGB to limited range RGB conversion
8559 * is supported, but eventually this should handle various
8560 * RGB<->YCbCr scenarios as well.
8561 */
50f3b016 8562static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8563{
8564 struct drm_device *dev = crtc->dev;
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8567 int pipe = intel_crtc->pipe;
8568 uint16_t coeff = 0x7800; /* 1.0 */
8569
8570 /*
8571 * TODO: Check what kind of values actually come out of the pipe
8572 * with these coeff/postoff values and adjust to get the best
8573 * accuracy. Perhaps we even need to take the bpc value into
8574 * consideration.
8575 */
8576
6e3c9717 8577 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8578 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8579
8580 /*
8581 * GY/GU and RY/RU should be the other way around according
8582 * to BSpec, but reality doesn't agree. Just set them up in
8583 * a way that results in the correct picture.
8584 */
8585 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8586 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8587
8588 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8589 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8590
8591 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8592 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8593
8594 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8595 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8596 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8597
8598 if (INTEL_INFO(dev)->gen > 6) {
8599 uint16_t postoff = 0;
8600
6e3c9717 8601 if (intel_crtc->config->limited_color_range)
32cf0cb0 8602 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8603
8604 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8605 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8606 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8607
8608 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8609 } else {
8610 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8611
6e3c9717 8612 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8613 mode |= CSC_BLACK_SCREEN_OFFSET;
8614
8615 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8616 }
8617}
8618
6ff93609 8619static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8620{
756f85cf
PZ		 8621 struct drm_device *dev = crtc->dev;
8622 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8624 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8625 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8626 uint32_t val;
8627
3eff4faa 8628 val = 0;
ee2b0b38 8629
6e3c9717 8630 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8631 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8632
6e3c9717 8633 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8634 val |= PIPECONF_INTERLACED_ILK;
8635 else
8636 val |= PIPECONF_PROGRESSIVE;
8637
702e7a56
PZ		 8638 I915_WRITE(PIPECONF(cpu_transcoder), val);
8639 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8640
8641 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8642 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8643
3cdf122c 8644 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8645 val = 0;
8646
6e3c9717 8647 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8648 case 18:
8649 val |= PIPEMISC_DITHER_6_BPC;
8650 break;
8651 case 24:
8652 val |= PIPEMISC_DITHER_8_BPC;
8653 break;
8654 case 30:
8655 val |= PIPEMISC_DITHER_10_BPC;
8656 break;
8657 case 36:
8658 val |= PIPEMISC_DITHER_12_BPC;
8659 break;
8660 default:
8661 /* Case prevented by pipe_config_set_bpp. */
8662 BUG();
8663 }
8664
6e3c9717 8665 if (intel_crtc->config->dither)
756f85cf
PZ		 8666 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8667
8668 I915_WRITE(PIPEMISC(pipe), val);
8669 }
ee2b0b38
PZ		 8670}
8671
6591c6e4 8672static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8673 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8674 intel_clock_t *clock,
8675 bool *has_reduced_clock,
8676 intel_clock_t *reduced_clock)
8677{
8678 struct drm_device *dev = crtc->dev;
8679 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8680 int refclk;
d4906093 8681 const intel_limit_t *limit;
c329a4ec 8682 bool ret;
79e53945 8683
55bb9992 8684 refclk = ironlake_get_refclk(crtc_state);
79e53945 8685
d4906093
ML		 8686 /*
8687 * Returns a set of divisors for the desired target clock with the given
8688 * refclk, or FALSE. The returned values represent the clock equation:
8689 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8690 */
a93e255f
ACO		 8691 limit = intel_limit(crtc_state, refclk);
8692 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8693 crtc_state->port_clock,
ee9300bb 8694 refclk, NULL, clock);
6591c6e4
PZ		 8695 if (!ret)
8696 return false;
cda4b7d3 8697
6591c6e4
PZ		 8698 return true;
8699}
8700
d4b1931c
PZ		 8701int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8702{
8703 /*
8704 * Account for spread spectrum to avoid
8705 * oversubscribing the link. Max center spread
8706 * is 2.5%; use 5% for safety's sake.
8707 */
8708 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8709 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8710}
8711
7429e9d4 8712static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8713{
7429e9d4 8714 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8715}
8716
de13a2e3 8717static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8718 struct intel_crtc_state *crtc_state,
7429e9d4 8719 u32 *fp,
9a7c7890 8720 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8721{
de13a2e3 8722 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8723 struct drm_device *dev = crtc->dev;
8724 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8725 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8726 struct drm_connector *connector;
55bb9992
ACO		 8727 struct drm_connector_state *connector_state;
8728 struct intel_encoder *encoder;
de13a2e3 8729 uint32_t dpll;
55bb9992 8730 int factor, num_connectors = 0, i;
09ede541 8731 bool is_lvds = false, is_sdvo = false;
79e53945 8732
da3ced29 8733 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8734 if (connector_state->crtc != crtc_state->base.crtc)
8735 continue;
8736
8737 encoder = to_intel_encoder(connector_state->best_encoder);
8738
8739 switch (encoder->type) {
79e53945
JB		 8740 case INTEL_OUTPUT_LVDS:
8741 is_lvds = true;
8742 break;
8743 case INTEL_OUTPUT_SDVO:
7d57382e 8744 case INTEL_OUTPUT_HDMI:
79e53945 8745 is_sdvo = true;
79e53945 8746 break;
6847d71b
PZ		 8747 default:
8748 break;
79e53945 8749 }
43565a06 8750
c751ce4f 8751 num_connectors++;
79e53945 8752 }
79e53945 8753
c1858123 8754 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8755 factor = 21;
8756 if (is_lvds) {
8757 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8758 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8759 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8760 factor = 25;
190f68c5 8761 } else if (crtc_state->sdvo_tv_clock)
8febb297 8762 factor = 20;
c1858123 8763
190f68c5 8764 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8765 *fp |= FP_CB_TUNE;
2c07245f 8766
9a7c7890
DV		 8767 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8768 *fp2 |= FP_CB_TUNE;
8769
5eddb70b 8770 dpll = 0;
2c07245f 8771
a07d6787
EA		 8772 if (is_lvds)
8773 dpll |= DPLLB_MODE_LVDS;
8774 else
8775 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8776
190f68c5 8777 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8778 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8779
8780 if (is_sdvo)
4a33e48d 8781 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8782 if (crtc_state->has_dp_encoder)
4a33e48d 8783 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8784
a07d6787 8785 /* compute bitmask from p1 value */
190f68c5 8786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8787 /* also FPA1 */
190f68c5 8788 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8789
190f68c5 8790 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8791 case 5:
8792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8793 break;
8794 case 7:
8795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8796 break;
8797 case 10:
8798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8799 break;
8800 case 14:
8801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8802 break;
79e53945
JB		 8803 }
8804
b4c09f3b 8805 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8806 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8807 else
8808 dpll |= PLL_REF_INPUT_DREFCLK;
8809
959e16d6 8810 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8811}
8812
190f68c5
ACO		 8813static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8814 struct intel_crtc_state *crtc_state)
de13a2e3 8815{
c7653199 8816 struct drm_device *dev = crtc->base.dev;
de13a2e3 8817 intel_clock_t clock, reduced_clock;
cbbab5bd 8818 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8819 bool ok, has_reduced_clock = false;
8b47047b 8820 bool is_lvds = false;
e2b78267 8821 struct intel_shared_dpll *pll;
de13a2e3 8822
dd3cd74a
ACO		 8823 memset(&crtc_state->dpll_hw_state, 0,
8824 sizeof(crtc_state->dpll_hw_state));
8825
409ee761 8826 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8827
5dc5298b
PZ		 8828 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8829 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8830
190f68c5 8831 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8832 &has_reduced_clock, &reduced_clock);
190f68c5 8833 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8834 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8835 return -EINVAL;
79e53945 8836 }
f47709a9 8837 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8838 if (!crtc_state->clock_set) {
8839 crtc_state->dpll.n = clock.n;
8840 crtc_state->dpll.m1 = clock.m1;
8841 crtc_state->dpll.m2 = clock.m2;
8842 crtc_state->dpll.p1 = clock.p1;
8843 crtc_state->dpll.p2 = clock.p2;
f47709a9 8844 }
79e53945 8845
5dc5298b 8846 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8847 if (crtc_state->has_pch_encoder) {
8848 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8849 if (has_reduced_clock)
7429e9d4 8850 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8851
190f68c5 8852 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8853 &fp, &reduced_clock,
8854 has_reduced_clock ? &fp2 : NULL);
8855
190f68c5
ACO		 8856 crtc_state->dpll_hw_state.dpll = dpll;
8857 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8858 if (has_reduced_clock)
190f68c5 8859 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8860 else
190f68c5 8861 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8862
190f68c5 8863 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8864 if (pll == NULL) {
84f44ce7 8865 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8866 pipe_name(crtc->pipe));
4b645f14
JB		 8867 return -EINVAL;
8868 }
3fb37703 8869 }
79e53945 8870
ab585dea 8871 if (is_lvds && has_reduced_clock)
c7653199 8872 crtc->lowfreq_avail = true;
bcd644e0 8873 else
c7653199 8874 crtc->lowfreq_avail = false;
e2b78267 8875
c8f7a0db 8876 return 0;
79e53945
JB		 8877}
8878
eb14cb74
VS		 8879static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8880 struct intel_link_m_n *m_n)
8881{
8882 struct drm_device *dev = crtc->base.dev;
8883 struct drm_i915_private *dev_priv = dev->dev_private;
8884 enum pipe pipe = crtc->pipe;
8885
8886 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8887 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8888 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8889 & ~TU_SIZE_MASK;
8890 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8891 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8892 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8893}
8894
8895static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8896 enum transcoder transcoder,
b95af8be
VK		 8897 struct intel_link_m_n *m_n,
8898 struct intel_link_m_n *m2_n2)
72419203
DV		 8899{
8900 struct drm_device *dev = crtc->base.dev;
8901 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8902 enum pipe pipe = crtc->pipe;
72419203 8903
eb14cb74
VS		 8904 if (INTEL_INFO(dev)->gen >= 5) {
8905 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8906 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8907 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8908 & ~TU_SIZE_MASK;
8909 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8910 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8911 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8912 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8913 * gen < 8) and if DRRS is supported (to make sure the
8914 * registers are not unnecessarily read).
8915 */
8916 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8917 crtc->config->has_drrs) {
b95af8be
VK		 8918 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8919 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8920 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8921 & ~TU_SIZE_MASK;
8922 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8923 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8924 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8925 }
eb14cb74
VS		 8926 } else {
8927 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8928 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8929 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8930 & ~TU_SIZE_MASK;
8931 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8932 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8933 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8934 }
8935}
8936
8937void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8938 struct intel_crtc_state *pipe_config)
eb14cb74 8939{
681a8504 8940 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8941 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8942 else
8943 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8944 &pipe_config->dp_m_n,
8945 &pipe_config->dp_m2_n2);
eb14cb74 8946}
72419203 8947
eb14cb74 8948static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8949 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8950{
8951 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8952 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8953}
8954
bd2e244f 8955static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8956 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8957{
8958 struct drm_device *dev = crtc->base.dev;
8959 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8960 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8961 uint32_t ps_ctrl = 0;
8962 int id = -1;
8963 int i;
bd2e244f 8964
a1b2278e
CK		 8965 /* find scaler attached to this pipe */
8966 for (i = 0; i < crtc->num_scalers; i++) {
8967 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8968 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8969 id = i;
8970 pipe_config->pch_pfit.enabled = true;
8971 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8972 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8973 break;
8974 }
8975 }
bd2e244f 8976
a1b2278e
CK		 8977 scaler_state->scaler_id = id;
8978 if (id >= 0) {
8979 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8980 } else {
8981 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8982 }
8983}
8984
5724dbd1
DL		 8985static void
8986skylake_get_initial_plane_config(struct intel_crtc *crtc,
8987 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8988{
8989 struct drm_device *dev = crtc->base.dev;
8990 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8991 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8992 int pipe = crtc->pipe;
8993 int fourcc, pixel_format;
6761dd31 8994 unsigned int aligned_height;
bc8d7dff 8995 struct drm_framebuffer *fb;
1b842c89 8996 struct intel_framebuffer *intel_fb;
bc8d7dff 8997
d9806c9f 8998 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8999 if (!intel_fb) {
bc8d7dff
DL		 9000 DRM_DEBUG_KMS("failed to alloc fb\n");
9001 return;
9002 }
9003
1b842c89
DL		 9004 fb = &intel_fb->base;
9005
bc8d7dff 9006 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9007 if (!(val & PLANE_CTL_ENABLE))
9008 goto error;
9009
bc8d7dff
DL		 9010 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9011 fourcc = skl_format_to_fourcc(pixel_format,
9012 val & PLANE_CTL_ORDER_RGBX,
9013 val & PLANE_CTL_ALPHA_MASK);
9014 fb->pixel_format = fourcc;
9015 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9016
40f46283
DL		 9017 tiling = val & PLANE_CTL_TILED_MASK;
9018 switch (tiling) {
9019 case PLANE_CTL_TILED_LINEAR:
9020 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9021 break;
9022 case PLANE_CTL_TILED_X:
9023 plane_config->tiling = I915_TILING_X;
9024 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9025 break;
9026 case PLANE_CTL_TILED_Y:
9027 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9028 break;
9029 case PLANE_CTL_TILED_YF:
9030 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9031 break;
9032 default:
9033 MISSING_CASE(tiling);
9034 goto error;
9035 }
9036
bc8d7dff
DL		 9037 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9038 plane_config->base = base;
9039
9040 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9041
9042 val = I915_READ(PLANE_SIZE(pipe, 0));
9043 fb->height = ((val >> 16) & 0xfff) + 1;
9044 fb->width = ((val >> 0) & 0x1fff) + 1;
9045
9046 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9047 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9048 fb->pixel_format);
bc8d7dff
DL		 9049 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9050
9051 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9052 fb->pixel_format,
9053 fb->modifier[0]);
bc8d7dff 9054
f37b5c2b 9055 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9056
9057 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9058 pipe_name(pipe), fb->width, fb->height,
9059 fb->bits_per_pixel, base, fb->pitches[0],
9060 plane_config->size);
9061
2d14030b 9062 plane_config->fb = intel_fb;
bc8d7dff
DL		 9063 return;
9064
9065error:
9066 kfree(fb);
9067}
9068
2fa2fe9a 9069static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9070 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9071{
9072 struct drm_device *dev = crtc->base.dev;
9073 struct drm_i915_private *dev_priv = dev->dev_private;
9074 uint32_t tmp;
9075
9076 tmp = I915_READ(PF_CTL(crtc->pipe));
9077
9078 if (tmp & PF_ENABLE) {
fd4daa9c 9079 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9080 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9081 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9082
9083 /* We currently do not free assignements of panel fitters on
9084 * ivb/hsw (since we don't use the higher upscaling modes which
9085 * differentiates them) so just WARN about this case for now. */
9086 if (IS_GEN7(dev)) {
9087 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9088 PF_PIPE_SEL_IVB(crtc->pipe));
9089 }
2fa2fe9a 9090 }
79e53945
JB		 9091}
9092
5724dbd1
DL		 9093static void
9094ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9095 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9096{
9097 struct drm_device *dev = crtc->base.dev;
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9099 u32 val, base, offset;
aeee5a49 9100 int pipe = crtc->pipe;
4c6baa59 9101 int fourcc, pixel_format;
6761dd31 9102 unsigned int aligned_height;
b113d5ee 9103 struct drm_framebuffer *fb;
1b842c89 9104 struct intel_framebuffer *intel_fb;
4c6baa59 9105
42a7b088
DL		 9106 val = I915_READ(DSPCNTR(pipe));
9107 if (!(val & DISPLAY_PLANE_ENABLE))
9108 return;
9109
d9806c9f 9110 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9111 if (!intel_fb) {
4c6baa59
JB		 9112 DRM_DEBUG_KMS("failed to alloc fb\n");
9113 return;
9114 }
9115
1b842c89
DL		 9116 fb = &intel_fb->base;
9117
18c5247e
DV		 9118 if (INTEL_INFO(dev)->gen >= 4) {
9119 if (val & DISPPLANE_TILED) {
49af449b 9120 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9121 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9122 }
9123 }
4c6baa59
JB		 9124
9125 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9126 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9127 fb->pixel_format = fourcc;
9128 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9129
aeee5a49 9130 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9131 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9132 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9133 } else {
49af449b 9134 if (plane_config->tiling)
aeee5a49 9135 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9136 else
aeee5a49 9137 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9138 }
9139 plane_config->base = base;
9140
9141 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9142 fb->width = ((val >> 16) & 0xfff) + 1;
9143 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9144
9145 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9146 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9147
b113d5ee 9148 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9149 fb->pixel_format,
9150 fb->modifier[0]);
4c6baa59 9151
f37b5c2b 9152 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9153
2844a921
DL		 9154 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9155 pipe_name(pipe), fb->width, fb->height,
9156 fb->bits_per_pixel, base, fb->pitches[0],
9157 plane_config->size);
b113d5ee 9158
2d14030b 9159 plane_config->fb = intel_fb;
4c6baa59
JB		 9160}
9161
0e8ffe1b 9162static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9163 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9164{
9165 struct drm_device *dev = crtc->base.dev;
9166 struct drm_i915_private *dev_priv = dev->dev_private;
9167 uint32_t tmp;
9168
f458ebbc
DV		 9169 if (!intel_display_power_is_enabled(dev_priv,
9170 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9171 return false;
9172
e143a21c 9173 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9174 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9175
0e8ffe1b
DV		 9176 tmp = I915_READ(PIPECONF(crtc->pipe));
9177 if (!(tmp & PIPECONF_ENABLE))
9178 return false;
9179
42571aef
VS		 9180 switch (tmp & PIPECONF_BPC_MASK) {
9181 case PIPECONF_6BPC:
9182 pipe_config->pipe_bpp = 18;
9183 break;
9184 case PIPECONF_8BPC:
9185 pipe_config->pipe_bpp = 24;
9186 break;
9187 case PIPECONF_10BPC:
9188 pipe_config->pipe_bpp = 30;
9189 break;
9190 case PIPECONF_12BPC:
9191 pipe_config->pipe_bpp = 36;
9192 break;
9193 default:
9194 break;
9195 }
9196
b5a9fa09
DV		 9197 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9198 pipe_config->limited_color_range = true;
9199
ab9412ba 9200 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9201 struct intel_shared_dpll *pll;
9202
88adfff1
DV		 9203 pipe_config->has_pch_encoder = true;
9204
627eb5a3
DV		 9205 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9206 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9207 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9208
9209 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9210
c0d43d62 9211 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9212 pipe_config->shared_dpll =
9213 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9214 } else {
9215 tmp = I915_READ(PCH_DPLL_SEL);
9216 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9217 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9218 else
9219 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9220 }
66e985c0
DV		 9221
9222 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9223
9224 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9225 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9226
9227 tmp = pipe_config->dpll_hw_state.dpll;
9228 pipe_config->pixel_multiplier =
9229 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9230 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9231
9232 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9233 } else {
9234 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9235 }
9236
1bd1bd80
DV		 9237 intel_get_pipe_timings(crtc, pipe_config);
9238
2fa2fe9a
DV		 9239 ironlake_get_pfit_config(crtc, pipe_config);
9240
0e8ffe1b
DV		 9241 return true;
9242}
9243
be256dc7
PZ		 9244static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9245{
9246 struct drm_device *dev = dev_priv->dev;
be256dc7 9247 struct intel_crtc *crtc;
be256dc7 9248
d3fcc808 9249 for_each_intel_crtc(dev, crtc)
e2c719b7 9250 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9251 pipe_name(crtc->pipe));
9252
e2c719b7
RC		 9253 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9254 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS		 9255 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9256 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
e2c719b7
RC		 9257 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9258 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9259 "CPU PWM1 enabled\n");
c5107b87 9260 if (IS_HASWELL(dev))
e2c719b7 9261 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9262 "CPU PWM2 enabled\n");
e2c719b7 9263 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9264 "PCH PWM1 enabled\n");
e2c719b7 9265 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9266 "Utility pin enabled\n");
e2c719b7 9267 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9268
9926ada1
PZ		 9269 /*
9270 * In theory we can still leave IRQs enabled, as long as only the HPD
9271 * interrupts remain enabled. We used to check for that, but since it's
9272 * gen-specific and since we only disable LCPLL after we fully disable
9273 * the interrupts, the check below should be enough.
9274 */
e2c719b7 9275 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9276}
9277
9ccd5aeb
PZ		 9278static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9279{
9280 struct drm_device *dev = dev_priv->dev;
9281
9282 if (IS_HASWELL(dev))
9283 return I915_READ(D_COMP_HSW);
9284 else
9285 return I915_READ(D_COMP_BDW);
9286}
9287
3c4c9b81
PZ		 9288static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9289{
9290 struct drm_device *dev = dev_priv->dev;
9291
9292 if (IS_HASWELL(dev)) {
9293 mutex_lock(&dev_priv->rps.hw_lock);
9294 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9295 val))
f475dadf 9296 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9297 mutex_unlock(&dev_priv->rps.hw_lock);
9298 } else {
9ccd5aeb
PZ		 9299 I915_WRITE(D_COMP_BDW, val);
9300 POSTING_READ(D_COMP_BDW);
3c4c9b81 9301 }
be256dc7
PZ		 9302}
9303
9304/*
9305 * This function implements pieces of two sequences from BSpec:
9306 * - Sequence for display software to disable LCPLL
9307 * - Sequence for display software to allow package C8+
9308 * The steps implemented here are just the steps that actually touch the LCPLL
9309 * register. Callers should take care of disabling all the display engine
9310 * functions, doing the mode unset, fixing interrupts, etc.
9311 */
6ff58d53
PZ		 9312static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9313 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9314{
9315 uint32_t val;
9316
9317 assert_can_disable_lcpll(dev_priv);
9318
9319 val = I915_READ(LCPLL_CTL);
9320
9321 if (switch_to_fclk) {
9322 val |= LCPLL_CD_SOURCE_FCLK;
9323 I915_WRITE(LCPLL_CTL, val);
9324
9325 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9326 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9327 DRM_ERROR("Switching to FCLK failed\n");
9328
9329 val = I915_READ(LCPLL_CTL);
9330 }
9331
9332 val |= LCPLL_PLL_DISABLE;
9333 I915_WRITE(LCPLL_CTL, val);
9334 POSTING_READ(LCPLL_CTL);
9335
9336 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9337 DRM_ERROR("LCPLL still locked\n");
9338
9ccd5aeb 9339 val = hsw_read_dcomp(dev_priv);
be256dc7 9340 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9341 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9342 ndelay(100);
9343
9ccd5aeb
PZ		 9344 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9345 1))
be256dc7
PZ		 9346 DRM_ERROR("D_COMP RCOMP still in progress\n");
9347
9348 if (allow_power_down) {
9349 val = I915_READ(LCPLL_CTL);
9350 val |= LCPLL_POWER_DOWN_ALLOW;
9351 I915_WRITE(LCPLL_CTL, val);
9352 POSTING_READ(LCPLL_CTL);
9353 }
9354}
9355
9356/*
9357 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9358 * source.
9359 */
6ff58d53 9360static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9361{
9362 uint32_t val;
9363
9364 val = I915_READ(LCPLL_CTL);
9365
9366 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9367 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9368 return;
9369
a8a8bd54
PZ		 9370 /*
9371 * Make sure we're not on PC8 state before disabling PC8, otherwise
9372 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9373 */
59bad947 9374 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9375
be256dc7
PZ		 9376 if (val & LCPLL_POWER_DOWN_ALLOW) {
9377 val &= ~LCPLL_POWER_DOWN_ALLOW;
9378 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9379 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9380 }
9381
9ccd5aeb 9382 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9383 val |= D_COMP_COMP_FORCE;
9384 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9385 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9386
9387 val = I915_READ(LCPLL_CTL);
9388 val &= ~LCPLL_PLL_DISABLE;
9389 I915_WRITE(LCPLL_CTL, val);
9390
9391 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9392 DRM_ERROR("LCPLL not locked yet\n");
9393
9394 if (val & LCPLL_CD_SOURCE_FCLK) {
9395 val = I915_READ(LCPLL_CTL);
9396 val &= ~LCPLL_CD_SOURCE_FCLK;
9397 I915_WRITE(LCPLL_CTL, val);
9398
9399 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9400 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9401 DRM_ERROR("Switching back to LCPLL failed\n");
9402 }
215733fa 9403
59bad947 9404 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9405 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9406}
9407
765dab67
PZ		 9408/*
9409 * Package states C8 and deeper are really deep PC states that can only be
9410 * reached when all the devices on the system allow it, so even if the graphics
9411 * device allows PC8+, it doesn't mean the system will actually get to these
9412 * states. Our driver only allows PC8+ when going into runtime PM.
9413 *
9414 * The requirements for PC8+ are that all the outputs are disabled, the power
9415 * well is disabled and most interrupts are disabled, and these are also
9416 * requirements for runtime PM. When these conditions are met, we manually do
9417 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9418 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9419 * hang the machine.
9420 *
9421 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9422 * the state of some registers, so when we come back from PC8+ we need to
9423 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9424 * need to take care of the registers kept by RC6. Notice that this happens even
9425 * if we don't put the device in PCI D3 state (which is what currently happens
9426 * because of the runtime PM support).
9427 *
9428 * For more, read "Display Sequences for Package C8" on the hardware
9429 * documentation.
9430 */
a14cb6fc 9431void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9432{
c67a470b
PZ		 9433 struct drm_device *dev = dev_priv->dev;
9434 uint32_t val;
9435
c67a470b
PZ		 9436 DRM_DEBUG_KMS("Enabling package C8+\n");
9437
c2699524 9438 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9439 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9440 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9441 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9442 }
9443
9444 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9445 hsw_disable_lcpll(dev_priv, true, true);
9446}
9447
a14cb6fc 9448void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9449{
9450 struct drm_device *dev = dev_priv->dev;
9451 uint32_t val;
9452
c67a470b
PZ		 9453 DRM_DEBUG_KMS("Disabling package C8+\n");
9454
9455 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9456 lpt_init_pch_refclk(dev);
9457
c2699524 9458 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9459 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9460 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9461 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9462 }
9463
9464 intel_prepare_ddi(dev);
c67a470b
PZ		 9465}
9466
27c329ed 9467static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9468{
a821fc46 9469 struct drm_device *dev = old_state->dev;
27c329ed 9470 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9471
27c329ed 9472 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9473}
9474
b432e5cf 9475/* compute the max rate for new configuration */
27c329ed 9476static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9477{
b432e5cf 9478 struct intel_crtc *intel_crtc;
27c329ed 9479 struct intel_crtc_state *crtc_state;
b432e5cf 9480 int max_pixel_rate = 0;
b432e5cf 9481
27c329ed
ML		 9482 for_each_intel_crtc(state->dev, intel_crtc) {
9483 int pixel_rate;
9484
9485 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9486 if (IS_ERR(crtc_state))
9487 return PTR_ERR(crtc_state);
9488
9489 if (!crtc_state->base.enable)
b432e5cf
VS		 9490 continue;
9491
27c329ed 9492 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9493
9494 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9495 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9496 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9497
9498 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9499 }
9500
9501 return max_pixel_rate;
9502}
9503
9504static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9505{
9506 struct drm_i915_private *dev_priv = dev->dev_private;
9507 uint32_t val, data;
9508 int ret;
9509
9510 if (WARN((I915_READ(LCPLL_CTL) &
9511 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9512 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9513 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9514 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9515 "trying to change cdclk frequency with cdclk not enabled\n"))
9516 return;
9517
9518 mutex_lock(&dev_priv->rps.hw_lock);
9519 ret = sandybridge_pcode_write(dev_priv,
9520 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9521 mutex_unlock(&dev_priv->rps.hw_lock);
9522 if (ret) {
9523 DRM_ERROR("failed to inform pcode about cdclk change\n");
9524 return;
9525 }
9526
9527 val = I915_READ(LCPLL_CTL);
9528 val |= LCPLL_CD_SOURCE_FCLK;
9529 I915_WRITE(LCPLL_CTL, val);
9530
9531 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9532 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9533 DRM_ERROR("Switching to FCLK failed\n");
9534
9535 val = I915_READ(LCPLL_CTL);
9536 val &= ~LCPLL_CLK_FREQ_MASK;
9537
9538 switch (cdclk) {
9539 case 450000:
9540 val |= LCPLL_CLK_FREQ_450;
9541 data = 0;
9542 break;
9543 case 540000:
9544 val |= LCPLL_CLK_FREQ_54O_BDW;
9545 data = 1;
9546 break;
9547 case 337500:
9548 val |= LCPLL_CLK_FREQ_337_5_BDW;
9549 data = 2;
9550 break;
9551 case 675000:
9552 val |= LCPLL_CLK_FREQ_675_BDW;
9553 data = 3;
9554 break;
9555 default:
9556 WARN(1, "invalid cdclk frequency\n");
9557 return;
9558 }
9559
9560 I915_WRITE(LCPLL_CTL, val);
9561
9562 val = I915_READ(LCPLL_CTL);
9563 val &= ~LCPLL_CD_SOURCE_FCLK;
9564 I915_WRITE(LCPLL_CTL, val);
9565
9566 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9567 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9568 DRM_ERROR("Switching back to LCPLL failed\n");
9569
9570 mutex_lock(&dev_priv->rps.hw_lock);
9571 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9572 mutex_unlock(&dev_priv->rps.hw_lock);
9573
9574 intel_update_cdclk(dev);
9575
9576 WARN(cdclk != dev_priv->cdclk_freq,
9577 "cdclk requested %d kHz but got %d kHz\n",
9578 cdclk, dev_priv->cdclk_freq);
9579}
9580
27c329ed 9581static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9582{
27c329ed
ML		 9583 struct drm_i915_private *dev_priv = to_i915(state->dev);
9584 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9585 int cdclk;
9586
9587 /*
9588 * FIXME should also account for plane ratio
9589 * once 64bpp pixel formats are supported.
9590 */
27c329ed 9591 if (max_pixclk > 540000)
b432e5cf 9592 cdclk = 675000;
27c329ed 9593 else if (max_pixclk > 450000)
b432e5cf 9594 cdclk = 540000;
27c329ed 9595 else if (max_pixclk > 337500)
b432e5cf
VS		 9596 cdclk = 450000;
9597 else
9598 cdclk = 337500;
9599
9600 /*
9601 * FIXME move the cdclk caclulation to
9602 * compute_config() so we can fail gracegully.
9603 */
9604 if (cdclk > dev_priv->max_cdclk_freq) {
9605 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9606 cdclk, dev_priv->max_cdclk_freq);
9607 cdclk = dev_priv->max_cdclk_freq;
9608 }
9609
27c329ed 9610 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9611
9612 return 0;
9613}
9614
27c329ed 9615static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9616{
27c329ed
ML		 9617 struct drm_device *dev = old_state->dev;
9618 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9619
27c329ed 9620 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9621}
9622
190f68c5
ACO		 9623static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9624 struct intel_crtc_state *crtc_state)
09b4ddf9 9625{
190f68c5 9626 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9627 return -EINVAL;
716c2e55 9628
c7653199 9629 crtc->lowfreq_avail = false;
644cef34 9630
c8f7a0db 9631 return 0;
79e53945
JB		 9632}
9633
3760b59c
S		 9634static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9635 enum port port,
9636 struct intel_crtc_state *pipe_config)
9637{
9638 switch (port) {
9639 case PORT_A:
9640 pipe_config->ddi_pll_sel = SKL_DPLL0;
9641 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9642 break;
9643 case PORT_B:
9644 pipe_config->ddi_pll_sel = SKL_DPLL1;
9645 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9646 break;
9647 case PORT_C:
9648 pipe_config->ddi_pll_sel = SKL_DPLL2;
9649 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9650 break;
9651 default:
9652 DRM_ERROR("Incorrect port type\n");
9653 }
9654}
9655
96b7dfb7
S		 9656static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9657 enum port port,
5cec258b 9658 struct intel_crtc_state *pipe_config)
96b7dfb7 9659{
3148ade7 9660 u32 temp, dpll_ctl1;
96b7dfb7
S		 9661
9662 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9663 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9664
9665 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9666 case SKL_DPLL0:
9667 /*
9668 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9669 * of the shared DPLL framework and thus needs to be read out
9670 * separately
9671 */
9672 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9673 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9674 break;
96b7dfb7
S		 9675 case SKL_DPLL1:
9676 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9677 break;
9678 case SKL_DPLL2:
9679 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9680 break;
9681 case SKL_DPLL3:
9682 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9683 break;
96b7dfb7
S		 9684 }
9685}
9686
7d2c8175
DL		 9687static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9688 enum port port,
5cec258b 9689 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9690{
9691 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9692
9693 switch (pipe_config->ddi_pll_sel) {
9694 case PORT_CLK_SEL_WRPLL1:
9695 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9696 break;
9697 case PORT_CLK_SEL_WRPLL2:
9698 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9699 break;
9700 }
9701}
9702
26804afd 9703static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9704 struct intel_crtc_state *pipe_config)
26804afd
DV		 9705{
9706 struct drm_device *dev = crtc->base.dev;
9707 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9708 struct intel_shared_dpll *pll;
26804afd
DV		 9709 enum port port;
9710 uint32_t tmp;
9711
9712 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9713
9714 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9715
ef11bdb3 9716 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
96b7dfb7 9717 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9718 else if (IS_BROXTON(dev))
9719 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9720 else
9721 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9722
d452c5b6
DV		 9723 if (pipe_config->shared_dpll >= 0) {
9724 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9725
9726 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9727 &pipe_config->dpll_hw_state));
9728 }
9729
26804afd
DV		 9730 /*
9731 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9732 * DDI E. So just check whether this pipe is wired to DDI E and whether
9733 * the PCH transcoder is on.
9734 */
ca370455
DL		 9735 if (INTEL_INFO(dev)->gen < 9 &&
9736 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9737 pipe_config->has_pch_encoder = true;
9738
9739 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9740 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9741 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9742
9743 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9744 }
9745}
9746
0e8ffe1b 9747static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9748 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9749{
9750 struct drm_device *dev = crtc->base.dev;
9751 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9752 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9753 uint32_t tmp;
9754
f458ebbc 9755 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9756 POWER_DOMAIN_PIPE(crtc->pipe)))
9757 return false;
9758
e143a21c 9759 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9760 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9761
eccb140b
DV		 9762 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9763 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9764 enum pipe trans_edp_pipe;
9765 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9766 default:
9767 WARN(1, "unknown pipe linked to edp transcoder\n");
9768 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9769 case TRANS_DDI_EDP_INPUT_A_ON:
9770 trans_edp_pipe = PIPE_A;
9771 break;
9772 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9773 trans_edp_pipe = PIPE_B;
9774 break;
9775 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9776 trans_edp_pipe = PIPE_C;
9777 break;
9778 }
9779
9780 if (trans_edp_pipe == crtc->pipe)
9781 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9782 }
9783
f458ebbc 9784 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9785 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9786 return false;
9787
eccb140b 9788 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9789 if (!(tmp & PIPECONF_ENABLE))
9790 return false;
9791
26804afd 9792 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9793
1bd1bd80
DV		 9794 intel_get_pipe_timings(crtc, pipe_config);
9795
a1b2278e
CK		 9796 if (INTEL_INFO(dev)->gen >= 9) {
9797 skl_init_scalers(dev, crtc, pipe_config);
9798 }
9799
2fa2fe9a 9800 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9801
9802 if (INTEL_INFO(dev)->gen >= 9) {
9803 pipe_config->scaler_state.scaler_id = -1;
9804 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9805 }
9806
bd2e244f 9807 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9808 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9809 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9810 else
1c132b44 9811 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9812 }
88adfff1 9813
e59150dc
JB		 9814 if (IS_HASWELL(dev))
9815 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9816 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9817
ebb69c95
CT		 9818 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9819 pipe_config->pixel_multiplier =
9820 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9821 } else {
9822 pipe_config->pixel_multiplier = 1;
9823 }
6c49f241 9824
0e8ffe1b
DV		 9825 return true;
9826}
9827
560b85bb
CW		 9828static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9829{
9830 struct drm_device *dev = crtc->dev;
9831 struct drm_i915_private *dev_priv = dev->dev_private;
9832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9833 uint32_t cntl = 0, size = 0;
560b85bb 9834
dc41c154 9835 if (base) {
3dd512fb
MR		 9836 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9837 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9838 unsigned int stride = roundup_pow_of_two(width) * 4;
9839
9840 switch (stride) {
9841 default:
9842 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9843 width, stride);
9844 stride = 256;
9845 /* fallthrough */
9846 case 256:
9847 case 512:
9848 case 1024:
9849 case 2048:
9850 break;
4b0e333e
CW		 9851 }
9852
dc41c154
VS		 9853 cntl |= CURSOR_ENABLE |
9854 CURSOR_GAMMA_ENABLE |
9855 CURSOR_FORMAT_ARGB |
9856 CURSOR_STRIDE(stride);
9857
9858 size = (height << 12) | width;
4b0e333e 9859 }
560b85bb 9860
dc41c154
VS		 9861 if (intel_crtc->cursor_cntl != 0 &&
9862 (intel_crtc->cursor_base != base ||
9863 intel_crtc->cursor_size != size ||
9864 intel_crtc->cursor_cntl != cntl)) {
9865 /* On these chipsets we can only modify the base/size/stride
9866 * whilst the cursor is disabled.
9867 */
0b87c24e
VS		 9868 I915_WRITE(CURCNTR(PIPE_A), 0);
9869 POSTING_READ(CURCNTR(PIPE_A));
dc41c154 9870 intel_crtc->cursor_cntl = 0;
4b0e333e 9871 }
560b85bb 9872
99d1f387 9873 if (intel_crtc->cursor_base != base) {
0b87c24e 9874 I915_WRITE(CURBASE(PIPE_A), base);
99d1f387
VS		 9875 intel_crtc->cursor_base = base;
9876 }
4726e0b0 9877
dc41c154
VS		 9878 if (intel_crtc->cursor_size != size) {
9879 I915_WRITE(CURSIZE, size);
9880 intel_crtc->cursor_size = size;
4b0e333e 9881 }
560b85bb 9882
4b0e333e 9883 if (intel_crtc->cursor_cntl != cntl) {
0b87c24e
VS		 9884 I915_WRITE(CURCNTR(PIPE_A), cntl);
9885 POSTING_READ(CURCNTR(PIPE_A));
4b0e333e 9886 intel_crtc->cursor_cntl = cntl;
560b85bb 9887 }
560b85bb
CW		 9888}
9889
560b85bb 9890static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9891{
9892 struct drm_device *dev = crtc->dev;
9893 struct drm_i915_private *dev_priv = dev->dev_private;
9894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9895 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9896 uint32_t cntl;
9897
9898 cntl = 0;
9899 if (base) {
9900 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9901 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9902 case 64:
9903 cntl |= CURSOR_MODE_64_ARGB_AX;
9904 break;
9905 case 128:
9906 cntl |= CURSOR_MODE_128_ARGB_AX;
9907 break;
9908 case 256:
9909 cntl |= CURSOR_MODE_256_ARGB_AX;
9910 break;
9911 default:
3dd512fb 9912 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9913 return;
65a21cd6 9914 }
4b0e333e 9915 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7 9916
fc6f93bc 9917 if (HAS_DDI(dev))
47bf17a7 9918 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9919 }
65a21cd6 9920
8e7d688b 9921 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9922 cntl |= CURSOR_ROTATE_180;
9923
4b0e333e
CW		 9924 if (intel_crtc->cursor_cntl != cntl) {
9925 I915_WRITE(CURCNTR(pipe), cntl);
9926 POSTING_READ(CURCNTR(pipe));
9927 intel_crtc->cursor_cntl = cntl;
65a21cd6 9928 }
4b0e333e 9929
65a21cd6 9930 /* and commit changes on next vblank */
5efb3e28
VS		 9931 I915_WRITE(CURBASE(pipe), base);
9932 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9933
9934 intel_crtc->cursor_base = base;
65a21cd6
JB		 9935}
9936
cda4b7d3 9937/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9938static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9939 bool on)
cda4b7d3
CW		 9940{
9941 struct drm_device *dev = crtc->dev;
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944 int pipe = intel_crtc->pipe;
9b4101be
ML		 9945 struct drm_plane_state *cursor_state = crtc->cursor->state;
9946 int x = cursor_state->crtc_x;
9947 int y = cursor_state->crtc_y;
d6e4db15 9948 u32 base = 0, pos = 0;
cda4b7d3 9949
d6e4db15 9950 if (on)
cda4b7d3 9951 base = intel_crtc->cursor_addr;
cda4b7d3 9952
6e3c9717 9953 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9954 base = 0;
9955
6e3c9717 9956 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9957 base = 0;
9958
9959 if (x < 0) {
9b4101be 9960 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9961 base = 0;
9962
9963 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9964 x = -x;
9965 }
9966 pos |= x << CURSOR_X_SHIFT;
9967
9968 if (y < 0) {
9b4101be 9969 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9970 base = 0;
9971
9972 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9973 y = -y;
9974 }
9975 pos |= y << CURSOR_Y_SHIFT;
9976
4b0e333e 9977 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9978 return;
9979
5efb3e28
VS		 9980 I915_WRITE(CURPOS(pipe), pos);
9981
4398ad45
VS		 9982 /* ILK+ do this automagically */
9983 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9984 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9985 base += (cursor_state->crtc_h *
9986 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9987 }
9988
8ac54669 9989 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9990 i845_update_cursor(crtc, base);
9991 else
9992 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9993}
9994
dc41c154
VS		 9995static bool cursor_size_ok(struct drm_device *dev,
9996 uint32_t width, uint32_t height)
9997{
9998 if (width == 0 || height == 0)
9999 return false;
10000
10001 /*
10002 * 845g/865g are special in that they are only limited by
10003 * the width of their cursors, the height is arbitrary up to
10004 * the precision of the register. Everything else requires
10005 * square cursors, limited to a few power-of-two sizes.
10006 */
10007 if (IS_845G(dev) || IS_I865G(dev)) {
10008 if ((width & 63) != 0)
10009 return false;
10010
10011 if (width > (IS_845G(dev) ? 64 : 512))
10012 return false;
10013
10014 if (height > 1023)
10015 return false;
10016 } else {
10017 switch (width | height) {
10018 case 256:
10019 case 128:
10020 if (IS_GEN2(dev))
10021 return false;
10022 case 64:
10023 break;
10024 default:
10025 return false;
10026 }
10027 }
10028
10029 return true;
10030}
10031
79e53945 10032static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10033 u16 *blue, uint32_t start, uint32_t size)
79e53945 10034{
7203425a 10035 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10037
7203425a 10038 for (i = start; i < end; i++) {
79e53945
JB		 10039 intel_crtc->lut_r[i] = red[i] >> 8;
10040 intel_crtc->lut_g[i] = green[i] >> 8;
10041 intel_crtc->lut_b[i] = blue[i] >> 8;
10042 }
10043
10044 intel_crtc_load_lut(crtc);
10045}
10046
79e53945
JB		 10047/* VESA 640x480x72Hz mode to set on the pipe */
10048static struct drm_display_mode load_detect_mode = {
10049 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10050 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10051};
10052
a8bb6818
DV		 10053struct drm_framebuffer *
10054__intel_framebuffer_create(struct drm_device *dev,
10055 struct drm_mode_fb_cmd2 *mode_cmd,
10056 struct drm_i915_gem_object *obj)
d2dff872
CW		 10057{
10058 struct intel_framebuffer *intel_fb;
10059 int ret;
10060
10061 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10062 if (!intel_fb) {
6ccb81f2 10063 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10064 return ERR_PTR(-ENOMEM);
10065 }
10066
10067 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10068 if (ret)
10069 goto err;
d2dff872
CW		 10070
10071 return &intel_fb->base;
dd4916c5 10072err:
6ccb81f2 10073 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10074 kfree(intel_fb);
10075
10076 return ERR_PTR(ret);
d2dff872
CW		 10077}
10078
b5ea642a 10079static struct drm_framebuffer *
a8bb6818
DV		 10080intel_framebuffer_create(struct drm_device *dev,
10081 struct drm_mode_fb_cmd2 *mode_cmd,
10082 struct drm_i915_gem_object *obj)
10083{
10084 struct drm_framebuffer *fb;
10085 int ret;
10086
10087 ret = i915_mutex_lock_interruptible(dev);
10088 if (ret)
10089 return ERR_PTR(ret);
10090 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10091 mutex_unlock(&dev->struct_mutex);
10092
10093 return fb;
10094}
10095
d2dff872
CW		 10096static u32
10097intel_framebuffer_pitch_for_width(int width, int bpp)
10098{
10099 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10100 return ALIGN(pitch, 64);
10101}
10102
10103static u32
10104intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10105{
10106 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10107 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10108}
10109
10110static struct drm_framebuffer *
10111intel_framebuffer_create_for_mode(struct drm_device *dev,
10112 struct drm_display_mode *mode,
10113 int depth, int bpp)
10114{
10115 struct drm_i915_gem_object *obj;
0fed39bd 10116 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10117
10118 obj = i915_gem_alloc_object(dev,
10119 intel_framebuffer_size_for_mode(mode, bpp));
10120 if (obj == NULL)
10121 return ERR_PTR(-ENOMEM);
10122
10123 mode_cmd.width = mode->hdisplay;
10124 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10125 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10126 bpp);
5ca0c34a 10127 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10128
10129 return intel_framebuffer_create(dev, &mode_cmd, obj);
10130}
10131
10132static struct drm_framebuffer *
10133mode_fits_in_fbdev(struct drm_device *dev,
10134 struct drm_display_mode *mode)
10135{
0695726e 10136#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10137 struct drm_i915_private *dev_priv = dev->dev_private;
10138 struct drm_i915_gem_object *obj;
10139 struct drm_framebuffer *fb;
10140
4c0e5528 10141 if (!dev_priv->fbdev)
d2dff872
CW		 10142 return NULL;
10143
4c0e5528 10144 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10145 return NULL;
10146
4c0e5528
DV		 10147 obj = dev_priv->fbdev->fb->obj;
10148 BUG_ON(!obj);
10149
8bcd4553 10150 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10151 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10152 fb->bits_per_pixel))
d2dff872
CW		 10153 return NULL;
10154
01f2c773 10155 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10156 return NULL;
10157
10158 return fb;
4520f53a
DV		 10159#else
10160 return NULL;
10161#endif
d2dff872
CW		 10162}
10163
d3a40d1b
ACO		 10164static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10165 struct drm_crtc *crtc,
10166 struct drm_display_mode *mode,
10167 struct drm_framebuffer *fb,
10168 int x, int y)
10169{
10170 struct drm_plane_state *plane_state;
10171 int hdisplay, vdisplay;
10172 int ret;
10173
10174 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10175 if (IS_ERR(plane_state))
10176 return PTR_ERR(plane_state);
10177
10178 if (mode)
10179 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10180 else
10181 hdisplay = vdisplay = 0;
10182
10183 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10184 if (ret)
10185 return ret;
10186 drm_atomic_set_fb_for_plane(plane_state, fb);
10187 plane_state->crtc_x = 0;
10188 plane_state->crtc_y = 0;
10189 plane_state->crtc_w = hdisplay;
10190 plane_state->crtc_h = vdisplay;
10191 plane_state->src_x = x << 16;
10192 plane_state->src_y = y << 16;
10193 plane_state->src_w = hdisplay << 16;
10194 plane_state->src_h = vdisplay << 16;
10195
10196 return 0;
10197}
10198
d2434ab7 10199bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10200 struct drm_display_mode *mode,
51fd371b
RC		 10201 struct intel_load_detect_pipe *old,
10202 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10203{
10204 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10205 struct intel_encoder *intel_encoder =
10206 intel_attached_encoder(connector);
79e53945 10207 struct drm_crtc *possible_crtc;
4ef69c7a 10208 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10209 struct drm_crtc *crtc = NULL;
10210 struct drm_device *dev = encoder->dev;
94352cf9 10211 struct drm_framebuffer *fb;
51fd371b 10212 struct drm_mode_config *config = &dev->mode_config;
83a57153 10213 struct drm_atomic_state *state = NULL;
944b0c76 10214 struct drm_connector_state *connector_state;
4be07317 10215 struct intel_crtc_state *crtc_state;
51fd371b 10216 int ret, i = -1;
79e53945 10217
d2dff872 10218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10219 connector->base.id, connector->name,
8e329a03 10220 encoder->base.id, encoder->name);
d2dff872 10221
51fd371b
RC		 10222retry:
10223 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10224 if (ret)
ad3c558f 10225 goto fail;
6e9f798d 10226
79e53945
JB		 10227 /*
10228 * Algorithm gets a little messy:
7a5e4805 10229 *
79e53945
JB		 10230 * - if the connector already has an assigned crtc, use it (but make
10231 * sure it's on first)
7a5e4805 10232 *
79e53945
JB		 10233 * - try to find the first unused crtc that can drive this connector,
10234 * and use that if we find one
79e53945
JB		 10235 */
10236
10237 /* See if we already have a CRTC for this connector */
10238 if (encoder->crtc) {
10239 crtc = encoder->crtc;
8261b191 10240
51fd371b 10241 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10242 if (ret)
ad3c558f 10243 goto fail;
4d02e2de 10244 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10245 if (ret)
ad3c558f 10246 goto fail;
7b24056b 10247
24218aac 10248 old->dpms_mode = connector->dpms;
8261b191
CW		 10249 old->load_detect_temp = false;
10250
10251 /* Make sure the crtc and connector are running */
24218aac
DV		 10252 if (connector->dpms != DRM_MODE_DPMS_ON)
10253 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10254
7173188d 10255 return true;
79e53945
JB		 10256 }
10257
10258 /* Find an unused one (if possible) */
70e1e0ec 10259 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10260 i++;
10261 if (!(encoder->possible_crtcs & (1 << i)))
10262 continue;
83d65738 10263 if (possible_crtc->state->enable)
a459249c 10264 continue;
a459249c
VS		 10265
10266 crtc = possible_crtc;
10267 break;
79e53945
JB		 10268 }
10269
10270 /*
10271 * If we didn't find an unused CRTC, don't use any.
10272 */
10273 if (!crtc) {
7173188d 10274 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10275 goto fail;
79e53945
JB		 10276 }
10277
51fd371b
RC		 10278 ret = drm_modeset_lock(&crtc->mutex, ctx);
10279 if (ret)
ad3c558f 10280 goto fail;
4d02e2de
DV		 10281 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10282 if (ret)
ad3c558f 10283 goto fail;
79e53945
JB		 10284
10285 intel_crtc = to_intel_crtc(crtc);
24218aac 10286 old->dpms_mode = connector->dpms;
8261b191 10287 old->load_detect_temp = true;
d2dff872 10288 old->release_fb = NULL;
79e53945 10289
83a57153
ACO		 10290 state = drm_atomic_state_alloc(dev);
10291 if (!state)
10292 return false;
10293
10294 state->acquire_ctx = ctx;
10295
944b0c76
ACO		 10296 connector_state = drm_atomic_get_connector_state(state, connector);
10297 if (IS_ERR(connector_state)) {
10298 ret = PTR_ERR(connector_state);
10299 goto fail;
10300 }
10301
10302 connector_state->crtc = crtc;
10303 connector_state->best_encoder = &intel_encoder->base;
10304
4be07317
ACO		 10305 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10306 if (IS_ERR(crtc_state)) {
10307 ret = PTR_ERR(crtc_state);
10308 goto fail;
10309 }
10310
49d6fa21 10311 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10312
6492711d
CW		 10313 if (!mode)
10314 mode = &load_detect_mode;
79e53945 10315
d2dff872
CW		 10316 /* We need a framebuffer large enough to accommodate all accesses
10317 * that the plane may generate whilst we perform load detection.
10318 * We can not rely on the fbcon either being present (we get called
10319 * during its initialisation to detect all boot displays, or it may
10320 * not even exist) or that it is large enough to satisfy the
10321 * requested mode.
10322 */
94352cf9
DV		 10323 fb = mode_fits_in_fbdev(dev, mode);
10324 if (fb == NULL) {
d2dff872 10325 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10326 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10327 old->release_fb = fb;
d2dff872
CW		 10328 } else
10329 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10330 if (IS_ERR(fb)) {
d2dff872 10331 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10332 goto fail;
79e53945 10333 }
79e53945 10334
d3a40d1b
ACO		 10335 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10336 if (ret)
10337 goto fail;
10338
8c7b5ccb
ACO		 10339 drm_mode_copy(&crtc_state->base.mode, mode);
10340
74c090b1 10341 if (drm_atomic_commit(state)) {
6492711d 10342 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10343 if (old->release_fb)
10344 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10345 goto fail;
79e53945 10346 }
9128b040 10347 crtc->primary->crtc = crtc;
7173188d 10348
79e53945 10349 /* let the connector get through one full cycle before testing */
9d0498a2 10350 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10351 return true;
412b61d8 10352
ad3c558f 10353fail:
e5d958ef
ACO		 10354 drm_atomic_state_free(state);
10355 state = NULL;
83a57153 10356
51fd371b
RC		 10357 if (ret == -EDEADLK) {
10358 drm_modeset_backoff(ctx);
10359 goto retry;
10360 }
10361
412b61d8 10362 return false;
79e53945
JB		 10363}
10364
d2434ab7 10365void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10366 struct intel_load_detect_pipe *old,
10367 struct drm_modeset_acquire_ctx *ctx)
79e53945 10368{
83a57153 10369 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10370 struct intel_encoder *intel_encoder =
10371 intel_attached_encoder(connector);
4ef69c7a 10372 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10373 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10375 struct drm_atomic_state *state;
944b0c76 10376 struct drm_connector_state *connector_state;
4be07317 10377 struct intel_crtc_state *crtc_state;
d3a40d1b 10378 int ret;
79e53945 10379
d2dff872 10380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10381 connector->base.id, connector->name,
8e329a03 10382 encoder->base.id, encoder->name);
d2dff872 10383
8261b191 10384 if (old->load_detect_temp) {
83a57153 10385 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10386 if (!state)
10387 goto fail;
83a57153
ACO		 10388
10389 state->acquire_ctx = ctx;
10390
944b0c76
ACO		 10391 connector_state = drm_atomic_get_connector_state(state, connector);
10392 if (IS_ERR(connector_state))
10393 goto fail;
10394
4be07317
ACO		 10395 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10396 if (IS_ERR(crtc_state))
10397 goto fail;
10398
944b0c76
ACO		 10399 connector_state->best_encoder = NULL;
10400 connector_state->crtc = NULL;
10401
49d6fa21 10402 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10403
d3a40d1b
ACO		 10404 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10405 0, 0);
10406 if (ret)
10407 goto fail;
10408
74c090b1 10409 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10410 if (ret)
10411 goto fail;
d2dff872 10412
36206361
DV		 10413 if (old->release_fb) {
10414 drm_framebuffer_unregister_private(old->release_fb);
10415 drm_framebuffer_unreference(old->release_fb);
10416 }
d2dff872 10417
0622a53c 10418 return;
79e53945
JB		 10419 }
10420
c751ce4f 10421 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10422 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10423 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10424
10425 return;
10426fail:
10427 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10428 drm_atomic_state_free(state);
79e53945
JB		 10429}
10430
da4a1efa 10431static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10432 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10433{
10434 struct drm_i915_private *dev_priv = dev->dev_private;
10435 u32 dpll = pipe_config->dpll_hw_state.dpll;
10436
10437 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10438 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10439 else if (HAS_PCH_SPLIT(dev))
10440 return 120000;
10441 else if (!IS_GEN2(dev))
10442 return 96000;
10443 else
10444 return 48000;
10445}
10446
79e53945 10447/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10448static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10449 struct intel_crtc_state *pipe_config)
79e53945 10450{
f1f644dc 10451 struct drm_device *dev = crtc->base.dev;
79e53945 10452 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10453 int pipe = pipe_config->cpu_transcoder;
293623f7 10454 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10455 u32 fp;
10456 intel_clock_t clock;
dccbea3b 10457 int port_clock;
da4a1efa 10458 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10459
10460 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10461 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10462 else
293623f7 10463 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10464
10465 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10466 if (IS_PINEVIEW(dev)) {
10467 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10468 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10469 } else {
10470 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10471 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10472 }
10473
a6c45cf0 10474 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10475 if (IS_PINEVIEW(dev))
10476 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10477 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10478 else
10479 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10480 DPLL_FPA01_P1_POST_DIV_SHIFT);
10481
10482 switch (dpll & DPLL_MODE_MASK) {
10483 case DPLLB_MODE_DAC_SERIAL:
10484 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10485 5 : 10;
10486 break;
10487 case DPLLB_MODE_LVDS:
10488 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10489 7 : 14;
10490 break;
10491 default:
28c97730 10492 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10493 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10494 return;
79e53945
JB		 10495 }
10496
ac58c3f0 10497 if (IS_PINEVIEW(dev))
dccbea3b 10498 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10499 else
dccbea3b 10500 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10501 } else {
0fb58223 10502 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10503 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10504
10505 if (is_lvds) {
10506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10507 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10508
10509 if (lvds & LVDS_CLKB_POWER_UP)
10510 clock.p2 = 7;
10511 else
10512 clock.p2 = 14;
79e53945
JB		 10513 } else {
10514 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10515 clock.p1 = 2;
10516 else {
10517 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10518 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10519 }
10520 if (dpll & PLL_P2_DIVIDE_BY_4)
10521 clock.p2 = 4;
10522 else
10523 clock.p2 = 2;
79e53945 10524 }
da4a1efa 10525
dccbea3b 10526 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10527 }
10528
18442d08
VS		 10529 /*
10530 * This value includes pixel_multiplier. We will use
241bfc38 10531 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10532 * encoder's get_config() function.
10533 */
dccbea3b 10534 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10535}
10536
6878da05
VS		 10537int intel_dotclock_calculate(int link_freq,
10538 const struct intel_link_m_n *m_n)
f1f644dc 10539{
f1f644dc
JB		 10540 /*
10541 * The calculation for the data clock is:
1041a02f 10542 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10543 * But we want to avoid losing precison if possible, so:
1041a02f 10544 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10545 *
10546 * and the link clock is simpler:
1041a02f 10547 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10548 */
10549
6878da05
VS		 10550 if (!m_n->link_n)
10551 return 0;
f1f644dc 10552
6878da05
VS		 10553 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10554}
f1f644dc 10555
18442d08 10556static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10557 struct intel_crtc_state *pipe_config)
6878da05
VS		 10558{
10559 struct drm_device *dev = crtc->base.dev;
79e53945 10560
18442d08
VS		 10561 /* read out port_clock from the DPLL */
10562 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10563
f1f644dc 10564 /*
18442d08 10565 * This value does not include pixel_multiplier.
241bfc38 10566 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10567 * agree once we know their relationship in the encoder's
10568 * get_config() function.
79e53945 10569 */
2d112de7 10570 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10571 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10572 &pipe_config->fdi_m_n);
79e53945
JB		 10573}
10574
10575/** Returns the currently programmed mode of the given pipe. */
10576struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10577 struct drm_crtc *crtc)
10578{
548f245b 10579 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10581 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10582 struct drm_display_mode *mode;
5cec258b 10583 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10584 int htot = I915_READ(HTOTAL(cpu_transcoder));
10585 int hsync = I915_READ(HSYNC(cpu_transcoder));
10586 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10587 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10588 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10589
10590 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10591 if (!mode)
10592 return NULL;
10593
f1f644dc
JB		 10594 /*
10595 * Construct a pipe_config sufficient for getting the clock info
10596 * back out of crtc_clock_get.
10597 *
10598 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10599 * to use a real value here instead.
10600 */
293623f7 10601 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10602 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10603 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10604 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10605 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10606 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10607
773ae034 10608 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10609 mode->hdisplay = (htot & 0xffff) + 1;
10610 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10611 mode->hsync_start = (hsync & 0xffff) + 1;
10612 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10613 mode->vdisplay = (vtot & 0xffff) + 1;
10614 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10615 mode->vsync_start = (vsync & 0xffff) + 1;
10616 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10617
10618 drm_mode_set_name(mode);
79e53945
JB		 10619
10620 return mode;
10621}
10622
f047e395
CW		 10623void intel_mark_busy(struct drm_device *dev)
10624{
c67a470b
PZ		 10625 struct drm_i915_private *dev_priv = dev->dev_private;
10626
f62a0076
CW		 10627 if (dev_priv->mm.busy)
10628 return;
10629
43694d69 10630 intel_runtime_pm_get(dev_priv);
c67a470b 10631 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10632 if (INTEL_INFO(dev)->gen >= 6)
10633 gen6_rps_busy(dev_priv);
f62a0076 10634 dev_priv->mm.busy = true;
f047e395
CW		 10635}
10636
10637void intel_mark_idle(struct drm_device *dev)
652c393a 10638{
c67a470b 10639 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10640
f62a0076
CW		 10641 if (!dev_priv->mm.busy)
10642 return;
10643
10644 dev_priv->mm.busy = false;
10645
3d13ef2e 10646 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10647 gen6_rps_idle(dev->dev_private);
bb4cdd53 10648
43694d69 10649 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10650}
10651
79e53945
JB		 10652static void intel_crtc_destroy(struct drm_crtc *crtc)
10653{
10654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10655 struct drm_device *dev = crtc->dev;
10656 struct intel_unpin_work *work;
67e77c5a 10657
5e2d7afc 10658 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10659 work = intel_crtc->unpin_work;
10660 intel_crtc->unpin_work = NULL;
5e2d7afc 10661 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10662
10663 if (work) {
10664 cancel_work_sync(&work->work);
10665 kfree(work);
10666 }
79e53945
JB		 10667
10668 drm_crtc_cleanup(crtc);
67e77c5a 10669
79e53945
JB		 10670 kfree(intel_crtc);
10671}
10672
6b95a207
KH		 10673static void intel_unpin_work_fn(struct work_struct *__work)
10674{
10675 struct intel_unpin_work *work =
10676 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10677 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10678 struct drm_device *dev = crtc->base.dev;
10679 struct drm_plane *primary = crtc->base.primary;
6b95a207 10680
b4a98e57 10681 mutex_lock(&dev->struct_mutex);
a9ff8714 10682 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10683 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10684
f06cc1b9 10685 if (work->flip_queued_req)
146d84f0 10686 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10687 mutex_unlock(&dev->struct_mutex);
10688
a9ff8714 10689 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10690 drm_framebuffer_unreference(work->old_fb);
f99d7069 10691
a9ff8714
VS		 10692 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10693 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10694
6b95a207
KH		 10695 kfree(work);
10696}
10697
1afe3e9d 10698static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10699 struct drm_crtc *crtc)
6b95a207 10700{
6b95a207
KH		 10701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10702 struct intel_unpin_work *work;
6b95a207
KH		 10703 unsigned long flags;
10704
10705 /* Ignore early vblank irqs */
10706 if (intel_crtc == NULL)
10707 return;
10708
f326038a
DV		 10709 /*
10710 * This is called both by irq handlers and the reset code (to complete
10711 * lost pageflips) so needs the full irqsave spinlocks.
10712 */
6b95a207
KH		 10713 spin_lock_irqsave(&dev->event_lock, flags);
10714 work = intel_crtc->unpin_work;
e7d841ca
CW		 10715
10716 /* Ensure we don't miss a work->pending update ... */
10717 smp_rmb();
10718
10719 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10720 spin_unlock_irqrestore(&dev->event_lock, flags);
10721 return;
10722 }
10723
d6bbafa1 10724 page_flip_completed(intel_crtc);
0af7e4df 10725
6b95a207 10726 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10727}
10728
1afe3e9d
JB		 10729void intel_finish_page_flip(struct drm_device *dev, int pipe)
10730{
fbee40df 10731 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10732 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10733
49b14a5c 10734 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10735}
10736
10737void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10738{
fbee40df 10739 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10740 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10741
49b14a5c 10742 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10743}
10744
75f7f3ec
VS		 10745/* Is 'a' after or equal to 'b'? */
10746static bool g4x_flip_count_after_eq(u32 a, u32 b)
10747{
10748 return !((a - b) & 0x80000000);
10749}
10750
10751static bool page_flip_finished(struct intel_crtc *crtc)
10752{
10753 struct drm_device *dev = crtc->base.dev;
10754 struct drm_i915_private *dev_priv = dev->dev_private;
10755
bdfa7542
VS		 10756 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10757 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10758 return true;
10759
75f7f3ec
VS		 10760 /*
10761 * The relevant registers doen't exist on pre-ctg.
10762 * As the flip done interrupt doesn't trigger for mmio
10763 * flips on gmch platforms, a flip count check isn't
10764 * really needed there. But since ctg has the registers,
10765 * include it in the check anyway.
10766 */
10767 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10768 return true;
10769
10770 /*
10771 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10772 * used the same base address. In that case the mmio flip might
10773 * have completed, but the CS hasn't even executed the flip yet.
10774 *
10775 * A flip count check isn't enough as the CS might have updated
10776 * the base address just after start of vblank, but before we
10777 * managed to process the interrupt. This means we'd complete the
10778 * CS flip too soon.
10779 *
10780 * Combining both checks should get us a good enough result. It may
10781 * still happen that the CS flip has been executed, but has not
10782 * yet actually completed. But in case the base address is the same
10783 * anyway, we don't really care.
10784 */
10785 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10786 crtc->unpin_work->gtt_offset &&
fd8f507c 10787 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
75f7f3ec
VS		 10788 crtc->unpin_work->flip_count);
10789}
10790
6b95a207
KH		 10791void intel_prepare_page_flip(struct drm_device *dev, int plane)
10792{
fbee40df 10793 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10794 struct intel_crtc *intel_crtc =
10795 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10796 unsigned long flags;
10797
f326038a
DV		 10798
10799 /*
10800 * This is called both by irq handlers and the reset code (to complete
10801 * lost pageflips) so needs the full irqsave spinlocks.
10802 *
10803 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10804 * generate a page-flip completion irq, i.e. every modeset
10805 * is also accompanied by a spurious intel_prepare_page_flip().
10806 */
6b95a207 10807 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10808 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10809 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10810 spin_unlock_irqrestore(&dev->event_lock, flags);
10811}
10812
6042639c 10813static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
e7d841ca
CW		 10814{
10815 /* Ensure that the work item is consistent when activating it ... */
10816 smp_wmb();
6042639c 10817 atomic_set(&work->pending, INTEL_FLIP_PENDING);
e7d841ca
CW		 10818 /* and that it is marked active as soon as the irq could fire. */
10819 smp_wmb();
10820}
10821
8c9f3aaf
JB		 10822static int intel_gen2_queue_flip(struct drm_device *dev,
10823 struct drm_crtc *crtc,
10824 struct drm_framebuffer *fb,
ed8d1975 10825 struct drm_i915_gem_object *obj,
6258fbe2 10826 struct drm_i915_gem_request *req,
ed8d1975 10827 uint32_t flags)
8c9f3aaf 10828{
6258fbe2 10829 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10831 u32 flip_mask;
10832 int ret;
10833
5fb9de1a 10834 ret = intel_ring_begin(req, 6);
8c9f3aaf 10835 if (ret)
4fa62c89 10836 return ret;
8c9f3aaf
JB		 10837
10838 /* Can't queue multiple flips, so wait for the previous
10839 * one to finish before executing the next.
10840 */
10841 if (intel_crtc->plane)
10842 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10843 else
10844 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10845 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10846 intel_ring_emit(ring, MI_NOOP);
10847 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10848 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10849 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10850 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10851 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca 10852
6042639c 10853 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10854 return 0;
8c9f3aaf
JB		 10855}
10856
10857static int intel_gen3_queue_flip(struct drm_device *dev,
10858 struct drm_crtc *crtc,
10859 struct drm_framebuffer *fb,
ed8d1975 10860 struct drm_i915_gem_object *obj,
6258fbe2 10861 struct drm_i915_gem_request *req,
ed8d1975 10862 uint32_t flags)
8c9f3aaf 10863{
6258fbe2 10864 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10866 u32 flip_mask;
10867 int ret;
10868
5fb9de1a 10869 ret = intel_ring_begin(req, 6);
8c9f3aaf 10870 if (ret)
4fa62c89 10871 return ret;
8c9f3aaf
JB		 10872
10873 if (intel_crtc->plane)
10874 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10875 else
10876 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10877 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10878 intel_ring_emit(ring, MI_NOOP);
10879 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10880 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10881 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10882 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10883 intel_ring_emit(ring, MI_NOOP);
10884
6042639c 10885 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10886 return 0;
8c9f3aaf
JB		 10887}
10888
10889static int intel_gen4_queue_flip(struct drm_device *dev,
10890 struct drm_crtc *crtc,
10891 struct drm_framebuffer *fb,
ed8d1975 10892 struct drm_i915_gem_object *obj,
6258fbe2 10893 struct drm_i915_gem_request *req,
ed8d1975 10894 uint32_t flags)
8c9f3aaf 10895{
6258fbe2 10896 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10897 struct drm_i915_private *dev_priv = dev->dev_private;
10898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10899 uint32_t pf, pipesrc;
10900 int ret;
10901
5fb9de1a 10902 ret = intel_ring_begin(req, 4);
8c9f3aaf 10903 if (ret)
4fa62c89 10904 return ret;
8c9f3aaf
JB		 10905
10906 /* i965+ uses the linear or tiled offsets from the
10907 * Display Registers (which do not change across a page-flip)
10908 * so we need only reprogram the base address.
10909 */
6d90c952
DV		 10910 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10911 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10912 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10913 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10914 obj->tiling_mode);
8c9f3aaf
JB		 10915
10916 /* XXX Enabling the panel-fitter across page-flip is so far
10917 * untested on non-native modes, so ignore it for now.
10918 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10919 */
10920 pf = 0;
10921 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10922 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10923
6042639c 10924 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10925 return 0;
8c9f3aaf
JB		 10926}
10927
10928static int intel_gen6_queue_flip(struct drm_device *dev,
10929 struct drm_crtc *crtc,
10930 struct drm_framebuffer *fb,
ed8d1975 10931 struct drm_i915_gem_object *obj,
6258fbe2 10932 struct drm_i915_gem_request *req,
ed8d1975 10933 uint32_t flags)
8c9f3aaf 10934{
6258fbe2 10935 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10936 struct drm_i915_private *dev_priv = dev->dev_private;
10937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10938 uint32_t pf, pipesrc;
10939 int ret;
10940
5fb9de1a 10941 ret = intel_ring_begin(req, 4);
8c9f3aaf 10942 if (ret)
4fa62c89 10943 return ret;
8c9f3aaf 10944
6d90c952
DV		 10945 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10946 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10947 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10948 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10949
dc257cf1
DV		 10950 /* Contrary to the suggestions in the documentation,
10951 * "Enable Panel Fitter" does not seem to be required when page
10952 * flipping with a non-native mode, and worse causes a normal
10953 * modeset to fail.
10954 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10955 */
10956 pf = 0;
8c9f3aaf 10957 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10958 intel_ring_emit(ring, pf | pipesrc);
e7d841ca 10959
6042639c 10960 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 10961 return 0;
8c9f3aaf
JB		 10962}
10963
7c9017e5
JB		 10964static int intel_gen7_queue_flip(struct drm_device *dev,
10965 struct drm_crtc *crtc,
10966 struct drm_framebuffer *fb,
ed8d1975 10967 struct drm_i915_gem_object *obj,
6258fbe2 10968 struct drm_i915_gem_request *req,
ed8d1975 10969 uint32_t flags)
7c9017e5 10970{
6258fbe2 10971 struct intel_engine_cs *ring = req->ring;
7c9017e5 10972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10973 uint32_t plane_bit = 0;
ffe74d75
CW		 10974 int len, ret;
10975
eba905b2 10976 switch (intel_crtc->plane) {
cb05d8de
DV		 10977 case PLANE_A:
10978 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10979 break;
10980 case PLANE_B:
10981 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10982 break;
10983 case PLANE_C:
10984 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10985 break;
10986 default:
10987 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10988 return -ENODEV;
cb05d8de
DV		 10989 }
10990
ffe74d75 10991 len = 4;
f476828a 10992 if (ring->id == RCS) {
ffe74d75 10993 len += 6;
f476828a
DL		 10994 /*
10995 * On Gen 8, SRM is now taking an extra dword to accommodate
10996 * 48bits addresses, and we need a NOOP for the batch size to
10997 * stay even.
10998 */
10999 if (IS_GEN8(dev))
11000 len += 2;
11001 }
ffe74d75 11002
f66fab8e
VS		 11003 /*
11004 * BSpec MI_DISPLAY_FLIP for IVB:
11005 * "The full packet must be contained within the same cache line."
11006 *
11007 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11008 * cacheline, if we ever start emitting more commands before
11009 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11010 * then do the cacheline alignment, and finally emit the
11011 * MI_DISPLAY_FLIP.
11012 */
bba09b12 11013 ret = intel_ring_cacheline_align(req);
f66fab8e 11014 if (ret)
4fa62c89 11015 return ret;
f66fab8e 11016
5fb9de1a 11017 ret = intel_ring_begin(req, len);
7c9017e5 11018 if (ret)
4fa62c89 11019 return ret;
7c9017e5 11020
ffe74d75
CW		 11021 /* Unmask the flip-done completion message. Note that the bspec says that
11022 * we should do this for both the BCS and RCS, and that we must not unmask
11023 * more than one flip event at any time (or ensure that one flip message
11024 * can be sent by waiting for flip-done prior to queueing new flips).
11025 * Experimentation says that BCS works despite DERRMR masking all
11026 * flip-done completion events and that unmasking all planes at once
11027 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11028 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11029 */
11030 if (ring->id == RCS) {
11031 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11032 intel_ring_emit(ring, DERRMR);
11033 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11034 DERRMR_PIPEB_PRI_FLIP_DONE |
11035 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11036 if (IS_GEN8(dev))
f1afe24f 11037 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11038 MI_SRM_LRM_GLOBAL_GTT);
11039 else
f1afe24f 11040 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11041 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11042 intel_ring_emit(ring, DERRMR);
11043 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11044 if (IS_GEN8(dev)) {
11045 intel_ring_emit(ring, 0);
11046 intel_ring_emit(ring, MI_NOOP);
11047 }
ffe74d75
CW		 11048 }
11049
cb05d8de 11050 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11051 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11052 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11053 intel_ring_emit(ring, (MI_NOOP));
e7d841ca 11054
6042639c 11055 intel_mark_page_flip_active(intel_crtc->unpin_work);
83d4092b 11056 return 0;
7c9017e5
JB		 11057}
11058
84c33a64
SG		 11059static bool use_mmio_flip(struct intel_engine_cs *ring,
11060 struct drm_i915_gem_object *obj)
11061{
11062 /*
11063 * This is not being used for older platforms, because
11064 * non-availability of flip done interrupt forces us to use
11065 * CS flips. Older platforms derive flip done using some clever
11066 * tricks involving the flip_pending status bits and vblank irqs.
11067 * So using MMIO flips there would disrupt this mechanism.
11068 */
11069
8e09bf83
CW		 11070 if (ring == NULL)
11071 return true;
11072
84c33a64
SG		 11073 if (INTEL_INFO(ring->dev)->gen < 5)
11074 return false;
11075
11076 if (i915.use_mmio_flip < 0)
11077 return false;
11078 else if (i915.use_mmio_flip > 0)
11079 return true;
14bf993e
OM		 11080 else if (i915.enable_execlists)
11081 return true;
84c33a64 11082 else
b4716185 11083 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11084}
11085
6042639c 11086static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
86efe24a 11087 unsigned int rotation,
6042639c 11088 struct intel_unpin_work *work)
ff944564
DL		 11089{
11090 struct drm_device *dev = intel_crtc->base.dev;
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564 11093 const enum pipe pipe = intel_crtc->pipe;
86efe24a 11094 u32 ctl, stride, tile_height;
ff944564
DL		 11095
11096 ctl = I915_READ(PLANE_CTL(pipe, 0));
11097 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11098 switch (fb->modifier[0]) {
11099 case DRM_FORMAT_MOD_NONE:
11100 break;
11101 case I915_FORMAT_MOD_X_TILED:
ff944564 11102 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11103 break;
11104 case I915_FORMAT_MOD_Y_TILED:
11105 ctl |= PLANE_CTL_TILED_Y;
11106 break;
11107 case I915_FORMAT_MOD_Yf_TILED:
11108 ctl |= PLANE_CTL_TILED_YF;
11109 break;
11110 default:
11111 MISSING_CASE(fb->modifier[0]);
11112 }
ff944564
DL		 11113
11114 /*
11115 * The stride is either expressed as a multiple of 64 bytes chunks for
11116 * linear buffers or in number of tiles for tiled buffers.
11117 */
86efe24a
TU		 11118 if (intel_rotation_90_or_270(rotation)) {
11119 /* stride = Surface height in tiles */
11120 tile_height = intel_tile_height(dev, fb->pixel_format,
11121 fb->modifier[0], 0);
11122 stride = DIV_ROUND_UP(fb->height, tile_height);
11123 } else {
11124 stride = fb->pitches[0] /
11125 intel_fb_stride_alignment(dev, fb->modifier[0],
11126 fb->pixel_format);
11127 }
ff944564
DL		 11128
11129 /*
11130 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11131 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11132 */
11133 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11134 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11135
6042639c 11136 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
ff944564
DL		 11137 POSTING_READ(PLANE_SURF(pipe, 0));
11138}
11139
6042639c
CW		 11140static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11141 struct intel_unpin_work *work)
84c33a64
SG		 11142{
11143 struct drm_device *dev = intel_crtc->base.dev;
11144 struct drm_i915_private *dev_priv = dev->dev_private;
11145 struct intel_framebuffer *intel_fb =
11146 to_intel_framebuffer(intel_crtc->base.primary->fb);
11147 struct drm_i915_gem_object *obj = intel_fb->obj;
11148 u32 dspcntr;
11149 u32 reg;
11150
84c33a64
SG		 11151 reg = DSPCNTR(intel_crtc->plane);
11152 dspcntr = I915_READ(reg);
11153
c5d97472
DL		 11154 if (obj->tiling_mode != I915_TILING_NONE)
11155 dspcntr |= DISPPLANE_TILED;
11156 else
11157 dspcntr &= ~DISPPLANE_TILED;
11158
84c33a64
SG		 11159 I915_WRITE(reg, dspcntr);
11160
6042639c 11161 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
84c33a64 11162 POSTING_READ(DSPSURF(intel_crtc->plane));
ff944564
DL		 11163}
11164
11165/*
11166 * XXX: This is the temporary way to update the plane registers until we get
11167 * around to using the usual plane update functions for MMIO flips
11168 */
6042639c 11169static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
ff944564 11170{
6042639c
CW		 11171 struct intel_crtc *crtc = mmio_flip->crtc;
11172 struct intel_unpin_work *work;
11173
11174 spin_lock_irq(&crtc->base.dev->event_lock);
11175 work = crtc->unpin_work;
11176 spin_unlock_irq(&crtc->base.dev->event_lock);
11177 if (work == NULL)
11178 return;
ff944564 11179
6042639c 11180 intel_mark_page_flip_active(work);
ff944564 11181
6042639c 11182 intel_pipe_update_start(crtc);
ff944564 11183
6042639c 11184 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
86efe24a 11185 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
ff944564
DL		 11186 else
11187 /* use_mmio_flip() retricts MMIO flips to ilk+ */
6042639c 11188 ilk_do_mmio_flip(crtc, work);
ff944564 11189
6042639c 11190 intel_pipe_update_end(crtc);
84c33a64
SG		 11191}
11192
9362c7c5 11193static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11194{
b2cfe0ab
CW		 11195 struct intel_mmio_flip *mmio_flip =
11196 container_of(work, struct intel_mmio_flip, work);
84c33a64 11197
6042639c 11198 if (mmio_flip->req) {
eed29a5b 11199 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11200 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11201 false, NULL,
11202 &mmio_flip->i915->rps.mmioflips));
6042639c
CW		 11203 i915_gem_request_unreference__unlocked(mmio_flip->req);
11204 }
84c33a64 11205
6042639c 11206 intel_do_mmio_flip(mmio_flip);
b2cfe0ab 11207 kfree(mmio_flip);
84c33a64
SG		 11208}
11209
11210static int intel_queue_mmio_flip(struct drm_device *dev,
11211 struct drm_crtc *crtc,
86efe24a 11212 struct drm_i915_gem_object *obj)
84c33a64 11213{
b2cfe0ab
CW		 11214 struct intel_mmio_flip *mmio_flip;
11215
11216 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11217 if (mmio_flip == NULL)
11218 return -ENOMEM;
84c33a64 11219
bcafc4e3 11220 mmio_flip->i915 = to_i915(dev);
eed29a5b 11221 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11222 mmio_flip->crtc = to_intel_crtc(crtc);
86efe24a 11223 mmio_flip->rotation = crtc->primary->state->rotation;
536f5b5e 11224
b2cfe0ab
CW		 11225 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11226 schedule_work(&mmio_flip->work);
84c33a64 11227
84c33a64
SG		 11228 return 0;
11229}
11230
8c9f3aaf
JB		 11231static int intel_default_queue_flip(struct drm_device *dev,
11232 struct drm_crtc *crtc,
11233 struct drm_framebuffer *fb,
ed8d1975 11234 struct drm_i915_gem_object *obj,
6258fbe2 11235 struct drm_i915_gem_request *req,
ed8d1975 11236 uint32_t flags)
8c9f3aaf
JB		 11237{
11238 return -ENODEV;
11239}
11240
d6bbafa1
CW		 11241static bool __intel_pageflip_stall_check(struct drm_device *dev,
11242 struct drm_crtc *crtc)
11243{
11244 struct drm_i915_private *dev_priv = dev->dev_private;
11245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11246 struct intel_unpin_work *work = intel_crtc->unpin_work;
11247 u32 addr;
11248
11249 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11250 return true;
11251
908565c2
CW		 11252 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11253 return false;
11254
d6bbafa1
CW		 11255 if (!work->enable_stall_check)
11256 return false;
11257
11258 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11259 if (work->flip_queued_req &&
11260 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11261 return false;
11262
1e3feefd 11263 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11264 }
11265
1e3feefd 11266 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11267 return false;
11268
11269 /* Potential stall - if we see that the flip has happened,
11270 * assume a missed interrupt. */
11271 if (INTEL_INFO(dev)->gen >= 4)
11272 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11273 else
11274 addr = I915_READ(DSPADDR(intel_crtc->plane));
11275
11276 /* There is a potential issue here with a false positive after a flip
11277 * to the same address. We could address this by checking for a
11278 * non-incrementing frame counter.
11279 */
11280 return addr == work->gtt_offset;
11281}
11282
11283void intel_check_page_flip(struct drm_device *dev, int pipe)
11284{
11285 struct drm_i915_private *dev_priv = dev->dev_private;
11286 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11288 struct intel_unpin_work *work;
f326038a 11289
6c51d46f 11290 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11291
11292 if (crtc == NULL)
11293 return;
11294
f326038a 11295 spin_lock(&dev->event_lock);
6ad790c0
CW		 11296 work = intel_crtc->unpin_work;
11297 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11298 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11299 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11300 page_flip_completed(intel_crtc);
6ad790c0 11301 work = NULL;
d6bbafa1 11302 }
6ad790c0
CW		 11303 if (work != NULL &&
11304 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11305 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11306 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11307}
11308
6b95a207
KH		 11309static int intel_crtc_page_flip(struct drm_crtc *crtc,
11310 struct drm_framebuffer *fb,
ed8d1975
KP		 11311 struct drm_pending_vblank_event *event,
11312 uint32_t page_flip_flags)
6b95a207
KH		 11313{
11314 struct drm_device *dev = crtc->dev;
11315 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11316 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11317 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11319 struct drm_plane *primary = crtc->primary;
a071fa00 11320 enum pipe pipe = intel_crtc->pipe;
6b95a207 11321 struct intel_unpin_work *work;
a4872ba6 11322 struct intel_engine_cs *ring;
cf5d8a46 11323 bool mmio_flip;
91af127f 11324 struct drm_i915_gem_request *request = NULL;
52e68630 11325 int ret;
6b95a207 11326
2ff8fde1
MR		 11327 /*
11328 * drm_mode_page_flip_ioctl() should already catch this, but double
11329 * check to be safe. In the future we may enable pageflipping from
11330 * a disabled primary plane.
11331 */
11332 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11333 return -EBUSY;
11334
e6a595d2 11335 /* Can't change pixel format via MI display flips. */
f4510a27 11336 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11337 return -EINVAL;
11338
11339 /*
11340 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11341 * Note that pitch changes could also affect these register.
11342 */
11343 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11344 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11345 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11346 return -EINVAL;
11347
f900db47
CW		 11348 if (i915_terminally_wedged(&dev_priv->gpu_error))
11349 goto out_hang;
11350
b14c5679 11351 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11352 if (work == NULL)
11353 return -ENOMEM;
11354
6b95a207 11355 work->event = event;
b4a98e57 11356 work->crtc = crtc;
ab8d6675 11357 work->old_fb = old_fb;
6b95a207
KH		 11358 INIT_WORK(&work->work, intel_unpin_work_fn);
11359
87b6b101 11360 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11361 if (ret)
11362 goto free_work;
11363
6b95a207 11364 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11365 spin_lock_irq(&dev->event_lock);
6b95a207 11366 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11367 /* Before declaring the flip queue wedged, check if
11368 * the hardware completed the operation behind our backs.
11369 */
11370 if (__intel_pageflip_stall_check(dev, crtc)) {
11371 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11372 page_flip_completed(intel_crtc);
11373 } else {
11374 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11375 spin_unlock_irq(&dev->event_lock);
468f0b44 11376
d6bbafa1
CW		 11377 drm_crtc_vblank_put(crtc);
11378 kfree(work);
11379 return -EBUSY;
11380 }
6b95a207
KH		 11381 }
11382 intel_crtc->unpin_work = work;
5e2d7afc 11383 spin_unlock_irq(&dev->event_lock);
6b95a207 11384
b4a98e57
CW		 11385 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11386 flush_workqueue(dev_priv->wq);
11387
75dfca80 11388 /* Reference the objects for the scheduled work. */
ab8d6675 11389 drm_framebuffer_reference(work->old_fb);
05394f39 11390 drm_gem_object_reference(&obj->base);
6b95a207 11391
f4510a27 11392 crtc->primary->fb = fb;
afd65eb4 11393 update_state_fb(crtc->primary);
1ed1f968 11394
e1f99ce6 11395 work->pending_flip_obj = obj;
e1f99ce6 11396
89ed88ba
CW		 11397 ret = i915_mutex_lock_interruptible(dev);
11398 if (ret)
11399 goto cleanup;
11400
b4a98e57 11401 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11402 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11403
75f7f3ec 11404 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
fd8f507c 11405 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
75f7f3ec 11406
4fa62c89
VS		 11407 if (IS_VALLEYVIEW(dev)) {
11408 ring = &dev_priv->ring[BCS];
ab8d6675 11409 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11410 /* vlv: DISPLAY_FLIP fails to change tiling */
11411 ring = NULL;
48bf5b2d 11412 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11413 ring = &dev_priv->ring[BCS];
4fa62c89 11414 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11415 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11416 if (ring == NULL || ring->id != RCS)
11417 ring = &dev_priv->ring[BCS];
11418 } else {
11419 ring = &dev_priv->ring[RCS];
11420 }
11421
cf5d8a46
CW		 11422 mmio_flip = use_mmio_flip(ring, obj);
11423
11424 /* When using CS flips, we want to emit semaphores between rings.
11425 * However, when using mmio flips we will create a task to do the
11426 * synchronisation, so all we want here is to pin the framebuffer
11427 * into the display plane and skip any waits.
11428 */
82bc3b2d 11429 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11430 crtc->primary->state,
91af127f 11431 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11432 if (ret)
11433 goto cleanup_pending;
6b95a207 11434
dedf278c
TU		 11435 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11436 obj, 0);
11437 work->gtt_offset += intel_crtc->dspaddr_offset;
4fa62c89 11438
cf5d8a46 11439 if (mmio_flip) {
86efe24a 11440 ret = intel_queue_mmio_flip(dev, crtc, obj);
d6bbafa1
CW		 11441 if (ret)
11442 goto cleanup_unpin;
11443
f06cc1b9
JH		 11444 i915_gem_request_assign(&work->flip_queued_req,
11445 obj->last_write_req);
d6bbafa1 11446 } else {
6258fbe2
JH		 11447 if (!request) {
11448 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11449 if (ret)
11450 goto cleanup_unpin;
11451 }
11452
11453 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11454 page_flip_flags);
11455 if (ret)
11456 goto cleanup_unpin;
11457
6258fbe2 11458 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11459 }
11460
91af127f 11461 if (request)
75289874 11462 i915_add_request_no_flush(request);
91af127f 11463
1e3feefd 11464 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11465 work->enable_stall_check = true;
4fa62c89 11466
ab8d6675 11467 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11468 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11469 mutex_unlock(&dev->struct_mutex);
a071fa00 11470
4e1e26f1 11471 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11472 intel_frontbuffer_flip_prepare(dev,
11473 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11474
e5510fac
JB		 11475 trace_i915_flip_request(intel_crtc->plane, obj);
11476
6b95a207 11477 return 0;
96b099fd 11478
4fa62c89 11479cleanup_unpin:
82bc3b2d 11480 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11481cleanup_pending:
91af127f
JH		 11482 if (request)
11483 i915_gem_request_cancel(request);
b4a98e57 11484 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11485 mutex_unlock(&dev->struct_mutex);
11486cleanup:
f4510a27 11487 crtc->primary->fb = old_fb;
afd65eb4 11488 update_state_fb(crtc->primary);
89ed88ba
CW		 11489
11490 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11491 drm_framebuffer_unreference(work->old_fb);
96b099fd 11492
5e2d7afc 11493 spin_lock_irq(&dev->event_lock);
96b099fd 11494 intel_crtc->unpin_work = NULL;
5e2d7afc 11495 spin_unlock_irq(&dev->event_lock);
96b099fd 11496
87b6b101 11497 drm_crtc_vblank_put(crtc);
7317c75e 11498free_work:
96b099fd
CW		 11499 kfree(work);
11500
f900db47 11501 if (ret == -EIO) {
02e0efb5
ML		 11502 struct drm_atomic_state *state;
11503 struct drm_plane_state *plane_state;
11504
f900db47 11505out_hang:
02e0efb5
ML		 11506 state = drm_atomic_state_alloc(dev);
11507 if (!state)
11508 return -ENOMEM;
11509 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11510
11511retry:
11512 plane_state = drm_atomic_get_plane_state(state, primary);
11513 ret = PTR_ERR_OR_ZERO(plane_state);
11514 if (!ret) {
11515 drm_atomic_set_fb_for_plane(plane_state, fb);
11516
11517 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11518 if (!ret)
11519 ret = drm_atomic_commit(state);
11520 }
11521
11522 if (ret == -EDEADLK) {
11523 drm_modeset_backoff(state->acquire_ctx);
11524 drm_atomic_state_clear(state);
11525 goto retry;
11526 }
11527
11528 if (ret)
11529 drm_atomic_state_free(state);
11530
f0d3dad3 11531 if (ret == 0 && event) {
5e2d7afc 11532 spin_lock_irq(&dev->event_lock);
a071fa00 11533 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11534 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11535 }
f900db47 11536 }
96b099fd 11537 return ret;
6b95a207
KH		 11538}
11539
da20eabd
ML		 11540
11541/**
11542 * intel_wm_need_update - Check whether watermarks need updating
11543 * @plane: drm plane
11544 * @state: new plane state
11545 *
11546 * Check current plane state versus the new one to determine whether
11547 * watermarks need to be recalculated.
11548 *
11549 * Returns true or false.
11550 */
11551static bool intel_wm_need_update(struct drm_plane *plane,
11552 struct drm_plane_state *state)
11553{
d21fbe87
MR		 11554 struct intel_plane_state *new = to_intel_plane_state(state);
11555 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11556
11557 /* Update watermarks on tiling or size changes. */
da20eabd
ML		 11558 if (!plane->state->fb || !state->fb ||
11559 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
d21fbe87
MR		 11560 plane->state->rotation != state->rotation ||
11561 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11562 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11563 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11564 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
2791a16c 11565 return true;
7809e5ae 11566
2791a16c 11567 return false;
7809e5ae
MR		 11568}
11569
d21fbe87
MR		 11570static bool needs_scaling(struct intel_plane_state *state)
11571{
11572 int src_w = drm_rect_width(&state->src) >> 16;
11573 int src_h = drm_rect_height(&state->src) >> 16;
11574 int dst_w = drm_rect_width(&state->dst);
11575 int dst_h = drm_rect_height(&state->dst);
11576
11577 return (src_w != dst_w || src_h != dst_h);
11578}
11579
da20eabd
ML		 11580int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11581 struct drm_plane_state *plane_state)
11582{
11583 struct drm_crtc *crtc = crtc_state->crtc;
11584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11585 struct drm_plane *plane = plane_state->plane;
11586 struct drm_device *dev = crtc->dev;
11587 struct drm_i915_private *dev_priv = dev->dev_private;
11588 struct intel_plane_state *old_plane_state =
11589 to_intel_plane_state(plane->state);
11590 int idx = intel_crtc->base.base.id, ret;
11591 int i = drm_plane_index(plane);
11592 bool mode_changed = needs_modeset(crtc_state);
11593 bool was_crtc_enabled = crtc->state->active;
11594 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML		 11595 bool turn_off, turn_on, visible, was_visible;
11596 struct drm_framebuffer *fb = plane_state->fb;
11597
11598 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11599 plane->type != DRM_PLANE_TYPE_CURSOR) {
11600 ret = skl_update_scaler_plane(
11601 to_intel_crtc_state(crtc_state),
11602 to_intel_plane_state(plane_state));
11603 if (ret)
11604 return ret;
11605 }
11606
da20eabd
ML		 11607 was_visible = old_plane_state->visible;
11608 visible = to_intel_plane_state(plane_state)->visible;
11609
11610 if (!was_crtc_enabled && WARN_ON(was_visible))
11611 was_visible = false;
11612
11613 if (!is_crtc_enabled && WARN_ON(visible))
11614 visible = false;
11615
11616 if (!was_visible && !visible)
11617 return 0;
11618
11619 turn_off = was_visible && (!visible || mode_changed);
11620 turn_on = visible && (!was_visible || mode_changed);
11621
11622 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11623 plane->base.id, fb ? fb->base.id : -1);
11624
11625 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11626 plane->base.id, was_visible, visible,
11627 turn_off, turn_on, mode_changed);
11628
852eb00d 11629 if (turn_on) {
f015c551 11630 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11631 /* must disable cxsr around plane enable/disable */
11632 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11633 intel_crtc->atomic.disable_cxsr = true;
11634 /* to potentially re-enable cxsr */
11635 intel_crtc->atomic.wait_vblank = true;
11636 intel_crtc->atomic.update_wm_post = true;
11637 }
11638 } else if (turn_off) {
f015c551 11639 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11640 /* must disable cxsr around plane enable/disable */
11641 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11642 if (is_crtc_enabled)
11643 intel_crtc->atomic.wait_vblank = true;
11644 intel_crtc->atomic.disable_cxsr = true;
11645 }
11646 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11647 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11648 }
da20eabd 11649
8be6ca85 11650 if (visible || was_visible)
a9ff8714
VS		 11651 intel_crtc->atomic.fb_bits |=
11652 to_intel_plane(plane)->frontbuffer_bit;
11653
da20eabd
ML		 11654 switch (plane->type) {
11655 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11656 intel_crtc->atomic.pre_disable_primary = turn_off;
11657 intel_crtc->atomic.post_enable_primary = turn_on;
11658
066cf55b
RV		 11659 if (turn_off) {
11660 /*
11661 * FIXME: Actually if we will still have any other
11662 * plane enabled on the pipe we could let IPS enabled
11663 * still, but for now lets consider that when we make
11664 * primary invisible by setting DSPCNTR to 0 on
11665 * update_primary_plane function IPS needs to be
11666 * disable.
11667 */
11668 intel_crtc->atomic.disable_ips = true;
11669
da20eabd 11670 intel_crtc->atomic.disable_fbc = true;
066cf55b 11671 }
da20eabd
ML		 11672
11673 /*
11674 * FBC does not work on some platforms for rotated
11675 * planes, so disable it when rotation is not 0 and
11676 * update it when rotation is set back to 0.
11677 *
11678 * FIXME: This is redundant with the fbc update done in
11679 * the primary plane enable function except that that
11680 * one is done too late. We eventually need to unify
11681 * this.
11682 */
11683
11684 if (visible &&
11685 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11686 dev_priv->fbc.crtc == intel_crtc &&
11687 plane_state->rotation != BIT(DRM_ROTATE_0))
11688 intel_crtc->atomic.disable_fbc = true;
11689
11690 /*
11691 * BDW signals flip done immediately if the plane
11692 * is disabled, even if the plane enable is already
11693 * armed to occur at the next vblank :(
11694 */
11695 if (turn_on && IS_BROADWELL(dev))
11696 intel_crtc->atomic.wait_vblank = true;
11697
11698 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11699 break;
11700 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11701 break;
11702 case DRM_PLANE_TYPE_OVERLAY:
d21fbe87
MR		 11703 /*
11704 * WaCxSRDisabledForSpriteScaling:ivb
11705 *
11706 * cstate->update_wm was already set above, so this flag will
11707 * take effect when we commit and program watermarks.
11708 */
11709 if (IS_IVYBRIDGE(dev) &&
11710 needs_scaling(to_intel_plane_state(plane_state)) &&
11711 !needs_scaling(old_plane_state)) {
11712 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11713 } else if (turn_off && !mode_changed) {
da20eabd
ML		 11714 intel_crtc->atomic.wait_vblank = true;
11715 intel_crtc->atomic.update_sprite_watermarks |=
11716 1 << i;
11717 }
d21fbe87
MR		 11718
11719 break;
da20eabd
ML		 11720 }
11721 return 0;
11722}
11723
6d3a1ce7
ML		 11724static bool encoders_cloneable(const struct intel_encoder *a,
11725 const struct intel_encoder *b)
11726{
11727 /* masks could be asymmetric, so check both ways */
11728 return a == b || (a->cloneable & (1 << b->type) &&
11729 b->cloneable & (1 << a->type));
11730}
11731
11732static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11733 struct intel_crtc *crtc,
11734 struct intel_encoder *encoder)
11735{
11736 struct intel_encoder *source_encoder;
11737 struct drm_connector *connector;
11738 struct drm_connector_state *connector_state;
11739 int i;
11740
11741 for_each_connector_in_state(state, connector, connector_state, i) {
11742 if (connector_state->crtc != &crtc->base)
11743 continue;
11744
11745 source_encoder =
11746 to_intel_encoder(connector_state->best_encoder);
11747 if (!encoders_cloneable(encoder, source_encoder))
11748 return false;
11749 }
11750
11751 return true;
11752}
11753
11754static bool check_encoder_cloning(struct drm_atomic_state *state,
11755 struct intel_crtc *crtc)
11756{
11757 struct intel_encoder *encoder;
11758 struct drm_connector *connector;
11759 struct drm_connector_state *connector_state;
11760 int i;
11761
11762 for_each_connector_in_state(state, connector, connector_state, i) {
11763 if (connector_state->crtc != &crtc->base)
11764 continue;
11765
11766 encoder = to_intel_encoder(connector_state->best_encoder);
11767 if (!check_single_encoder_cloning(state, crtc, encoder))
11768 return false;
11769 }
11770
11771 return true;
11772}
11773
11774static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11775 struct drm_crtc_state *crtc_state)
11776{
cf5a15be 11777 struct drm_device *dev = crtc->dev;
ad421372 11778 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11780 struct intel_crtc_state *pipe_config =
11781 to_intel_crtc_state(crtc_state);
6d3a1ce7 11782 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11783 int ret;
6d3a1ce7
ML		 11784 bool mode_changed = needs_modeset(crtc_state);
11785
11786 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11787 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11788 return -EINVAL;
11789 }
11790
852eb00d
VS		 11791 if (mode_changed && !crtc_state->active)
11792 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11793
ad421372
ML		 11794 if (mode_changed && crtc_state->enable &&
11795 dev_priv->display.crtc_compute_clock &&
11796 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11797 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11798 pipe_config);
11799 if (ret)
11800 return ret;
11801 }
11802
e435d6e5 11803 ret = 0;
86c8bbbe
MR		 11804 if (dev_priv->display.compute_pipe_wm) {
11805 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11806 if (ret)
11807 return ret;
11808 }
11809
e435d6e5
ML		 11810 if (INTEL_INFO(dev)->gen >= 9) {
11811 if (mode_changed)
11812 ret = skl_update_scaler_crtc(pipe_config);
11813
11814 if (!ret)
11815 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11816 pipe_config);
11817 }
11818
11819 return ret;
6d3a1ce7
ML		 11820}
11821
65b38e0d 11822static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11823 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11824 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11825 .atomic_begin = intel_begin_crtc_commit,
11826 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11827 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11828};
11829
d29b2f9d
ACO		 11830static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11831{
11832 struct intel_connector *connector;
11833
11834 for_each_intel_connector(dev, connector) {
11835 if (connector->base.encoder) {
11836 connector->base.state->best_encoder =
11837 connector->base.encoder;
11838 connector->base.state->crtc =
11839 connector->base.encoder->crtc;
11840 } else {
11841 connector->base.state->best_encoder = NULL;
11842 connector->base.state->crtc = NULL;
11843 }
11844 }
11845}
11846
050f7aeb 11847static void
eba905b2 11848connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11849 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11850{
11851 int bpp = pipe_config->pipe_bpp;
11852
11853 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11854 connector->base.base.id,
c23cc417 11855 connector->base.name);
050f7aeb
DV		 11856
11857 /* Don't use an invalid EDID bpc value */
11858 if (connector->base.display_info.bpc &&
11859 connector->base.display_info.bpc * 3 < bpp) {
11860 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11861 bpp, connector->base.display_info.bpc*3);
11862 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11863 }
11864
11865 /* Clamp bpp to 8 on screens without EDID 1.4 */
11866 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11867 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11868 bpp);
11869 pipe_config->pipe_bpp = 24;
11870 }
11871}
11872
4e53c2e0 11873static int
050f7aeb 11874compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11875 struct intel_crtc_state *pipe_config)
4e53c2e0 11876{
050f7aeb 11877 struct drm_device *dev = crtc->base.dev;
1486017f 11878 struct drm_atomic_state *state;
da3ced29
ACO		 11879 struct drm_connector *connector;
11880 struct drm_connector_state *connector_state;
1486017f 11881 int bpp, i;
4e53c2e0 11882
d328c9d7 11883 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11884 bpp = 10*3;
d328c9d7
DV		 11885 else if (INTEL_INFO(dev)->gen >= 5)
11886 bpp = 12*3;
11887 else
11888 bpp = 8*3;
11889
4e53c2e0 11890
4e53c2e0
DV		 11891 pipe_config->pipe_bpp = bpp;
11892
1486017f
ACO		 11893 state = pipe_config->base.state;
11894
4e53c2e0 11895 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11896 for_each_connector_in_state(state, connector, connector_state, i) {
11897 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11898 continue;
11899
da3ced29
ACO		 11900 connected_sink_compute_bpp(to_intel_connector(connector),
11901 pipe_config);
4e53c2e0
DV		 11902 }
11903
11904 return bpp;
11905}
11906
644db711
DV		 11907static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11908{
11909 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11910 "type: 0x%x flags: 0x%x\n",
1342830c 11911 mode->crtc_clock,
644db711
DV		 11912 mode->crtc_hdisplay, mode->crtc_hsync_start,
11913 mode->crtc_hsync_end, mode->crtc_htotal,
11914 mode->crtc_vdisplay, mode->crtc_vsync_start,
11915 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11916}
11917
c0b03411 11918static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11919 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11920 const char *context)
11921{
6a60cd87
CK		 11922 struct drm_device *dev = crtc->base.dev;
11923 struct drm_plane *plane;
11924 struct intel_plane *intel_plane;
11925 struct intel_plane_state *state;
11926 struct drm_framebuffer *fb;
11927
11928 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11929 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11930
11931 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11932 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11933 pipe_config->pipe_bpp, pipe_config->dither);
11934 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11935 pipe_config->has_pch_encoder,
11936 pipe_config->fdi_lanes,
11937 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11938 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11939 pipe_config->fdi_m_n.tu);
90a6b7b0 11940 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11941 pipe_config->has_dp_encoder,
90a6b7b0 11942 pipe_config->lane_count,
eb14cb74
VS		 11943 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11944 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11945 pipe_config->dp_m_n.tu);
b95af8be 11946
90a6b7b0 11947 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11948 pipe_config->has_dp_encoder,
90a6b7b0 11949 pipe_config->lane_count,
b95af8be
VK		 11950 pipe_config->dp_m2_n2.gmch_m,
11951 pipe_config->dp_m2_n2.gmch_n,
11952 pipe_config->dp_m2_n2.link_m,
11953 pipe_config->dp_m2_n2.link_n,
11954 pipe_config->dp_m2_n2.tu);
11955
55072d19
DV		 11956 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11957 pipe_config->has_audio,
11958 pipe_config->has_infoframe);
11959
c0b03411 11960 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11961 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11962 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11963 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11964 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11965 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11966 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11967 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11968 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11969 crtc->num_scalers,
11970 pipe_config->scaler_state.scaler_users,
11971 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11972 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11973 pipe_config->gmch_pfit.control,
11974 pipe_config->gmch_pfit.pgm_ratios,
11975 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11976 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11977 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11978 pipe_config->pch_pfit.size,
11979 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11980 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11981 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11982
415ff0f6 11983 if (IS_BROXTON(dev)) {
05712c15 11984 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11985 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11986 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11987 pipe_config->ddi_pll_sel,
11988 pipe_config->dpll_hw_state.ebb0,
05712c15 11989 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11990 pipe_config->dpll_hw_state.pll0,
11991 pipe_config->dpll_hw_state.pll1,
11992 pipe_config->dpll_hw_state.pll2,
11993 pipe_config->dpll_hw_state.pll3,
11994 pipe_config->dpll_hw_state.pll6,
11995 pipe_config->dpll_hw_state.pll8,
05712c15 11996 pipe_config->dpll_hw_state.pll9,
c8453338 11997 pipe_config->dpll_hw_state.pll10,
415ff0f6 11998 pipe_config->dpll_hw_state.pcsdw12);
ef11bdb3 11999 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
415ff0f6
TU		 12000 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12001 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12002 pipe_config->ddi_pll_sel,
12003 pipe_config->dpll_hw_state.ctrl1,
12004 pipe_config->dpll_hw_state.cfgcr1,
12005 pipe_config->dpll_hw_state.cfgcr2);
12006 } else if (HAS_DDI(dev)) {
12007 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12008 pipe_config->ddi_pll_sel,
12009 pipe_config->dpll_hw_state.wrpll);
12010 } else {
12011 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12012 "fp0: 0x%x, fp1: 0x%x\n",
12013 pipe_config->dpll_hw_state.dpll,
12014 pipe_config->dpll_hw_state.dpll_md,
12015 pipe_config->dpll_hw_state.fp0,
12016 pipe_config->dpll_hw_state.fp1);
12017 }
12018
6a60cd87
CK		 12019 DRM_DEBUG_KMS("planes on this crtc\n");
12020 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12021 intel_plane = to_intel_plane(plane);
12022 if (intel_plane->pipe != crtc->pipe)
12023 continue;
12024
12025 state = to_intel_plane_state(plane->state);
12026 fb = state->base.fb;
12027 if (!fb) {
12028 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12029 "disabled, scaler_id = %d\n",
12030 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12031 plane->base.id, intel_plane->pipe,
12032 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12033 drm_plane_index(plane), state->scaler_id);
12034 continue;
12035 }
12036
12037 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12038 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12039 plane->base.id, intel_plane->pipe,
12040 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12041 drm_plane_index(plane));
12042 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12043 fb->base.id, fb->width, fb->height, fb->pixel_format);
12044 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12045 state->scaler_id,
12046 state->src.x1 >> 16, state->src.y1 >> 16,
12047 drm_rect_width(&state->src) >> 16,
12048 drm_rect_height(&state->src) >> 16,
12049 state->dst.x1, state->dst.y1,
12050 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12051 }
c0b03411
DV		 12052}
12053
5448a00d 12054static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12055{
5448a00d
ACO		 12056 struct drm_device *dev = state->dev;
12057 struct intel_encoder *encoder;
da3ced29 12058 struct drm_connector *connector;
5448a00d 12059 struct drm_connector_state *connector_state;
00f0b378 12060 unsigned int used_ports = 0;
5448a00d 12061 int i;
00f0b378
VS		 12062
12063 /*
12064 * Walk the connector list instead of the encoder
12065 * list to detect the problem on ddi platforms
12066 * where there's just one encoder per digital port.
12067 */
da3ced29 12068 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12069 if (!connector_state->best_encoder)
00f0b378
VS		 12070 continue;
12071
5448a00d
ACO		 12072 encoder = to_intel_encoder(connector_state->best_encoder);
12073
12074 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12075
12076 switch (encoder->type) {
12077 unsigned int port_mask;
12078 case INTEL_OUTPUT_UNKNOWN:
12079 if (WARN_ON(!HAS_DDI(dev)))
12080 break;
12081 case INTEL_OUTPUT_DISPLAYPORT:
12082 case INTEL_OUTPUT_HDMI:
12083 case INTEL_OUTPUT_EDP:
12084 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12085
12086 /* the same port mustn't appear more than once */
12087 if (used_ports & port_mask)
12088 return false;
12089
12090 used_ports |= port_mask;
12091 default:
12092 break;
12093 }
12094 }
12095
12096 return true;
12097}
12098
83a57153
ACO		 12099static void
12100clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12101{
12102 struct drm_crtc_state tmp_state;
663a3640 12103 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12104 struct intel_dpll_hw_state dpll_hw_state;
12105 enum intel_dpll_id shared_dpll;
8504c74c 12106 uint32_t ddi_pll_sel;
c4e2d043 12107 bool force_thru;
83a57153 12108
7546a384
ACO		 12109 /* FIXME: before the switch to atomic started, a new pipe_config was
12110 * kzalloc'd. Code that depends on any field being zero should be
12111 * fixed, so that the crtc_state can be safely duplicated. For now,
12112 * only fields that are know to not cause problems are preserved. */
12113
83a57153 12114 tmp_state = crtc_state->base;
663a3640 12115 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12116 shared_dpll = crtc_state->shared_dpll;
12117 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12118 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12119 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12120
83a57153 12121 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12122
83a57153 12123 crtc_state->base = tmp_state;
663a3640 12124 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12125 crtc_state->shared_dpll = shared_dpll;
12126 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12127 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12128 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12129}
12130
548ee15b 12131static int
b8cecdf5 12132intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12133 struct intel_crtc_state *pipe_config)
ee7b9f93 12134{
b359283a 12135 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12136 struct intel_encoder *encoder;
da3ced29 12137 struct drm_connector *connector;
0b901879 12138 struct drm_connector_state *connector_state;
d328c9d7 12139 int base_bpp, ret = -EINVAL;
0b901879 12140 int i;
e29c22c0 12141 bool retry = true;
ee7b9f93 12142
83a57153 12143 clear_intel_crtc_state(pipe_config);
7758a113 12144
e143a21c
DV		 12145 pipe_config->cpu_transcoder =
12146 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12147
2960bc9c
ID		 12148 /*
12149 * Sanitize sync polarity flags based on requested ones. If neither
12150 * positive or negative polarity is requested, treat this as meaning
12151 * negative polarity.
12152 */
2d112de7 12153 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12154 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12155 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12156
2d112de7 12157 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12158 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12159 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12160
d328c9d7
DV		 12161 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12162 pipe_config);
12163 if (base_bpp < 0)
4e53c2e0
DV		 12164 goto fail;
12165
e41a56be
VS		 12166 /*
12167 * Determine the real pipe dimensions. Note that stereo modes can
12168 * increase the actual pipe size due to the frame doubling and
12169 * insertion of additional space for blanks between the frame. This
12170 * is stored in the crtc timings. We use the requested mode to do this
12171 * computation to clearly distinguish it from the adjusted mode, which
12172 * can be changed by the connectors in the below retry loop.
12173 */
2d112de7 12174 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12175 &pipe_config->pipe_src_w,
12176 &pipe_config->pipe_src_h);
e41a56be 12177
e29c22c0 12178encoder_retry:
ef1b460d 12179 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12180 pipe_config->port_clock = 0;
ef1b460d 12181 pipe_config->pixel_multiplier = 1;
ff9a6750 12182
135c81b8 12183 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12184 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12185 CRTC_STEREO_DOUBLE);
135c81b8 12186
7758a113
DV		 12187 /* Pass our mode to the connectors and the CRTC to give them a chance to
12188 * adjust it according to limitations or connector properties, and also
12189 * a chance to reject the mode entirely.
47f1c6c9 12190 */
da3ced29 12191 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12192 if (connector_state->crtc != crtc)
7758a113 12193 continue;
7ae89233 12194
0b901879
ACO		 12195 encoder = to_intel_encoder(connector_state->best_encoder);
12196
efea6e8e
DV		 12197 if (!(encoder->compute_config(encoder, pipe_config))) {
12198 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12199 goto fail;
12200 }
ee7b9f93 12201 }
47f1c6c9 12202
ff9a6750
DV		 12203 /* Set default port clock if not overwritten by the encoder. Needs to be
12204 * done afterwards in case the encoder adjusts the mode. */
12205 if (!pipe_config->port_clock)
2d112de7 12206 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12207 * pipe_config->pixel_multiplier;
ff9a6750 12208
a43f6e0f 12209 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12210 if (ret < 0) {
7758a113
DV		 12211 DRM_DEBUG_KMS("CRTC fixup failed\n");
12212 goto fail;
ee7b9f93 12213 }
e29c22c0
DV		 12214
12215 if (ret == RETRY) {
12216 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12217 ret = -EINVAL;
12218 goto fail;
12219 }
12220
12221 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12222 retry = false;
12223 goto encoder_retry;
12224 }
12225
e8fa4270
DV		 12226 /* Dithering seems to not pass-through bits correctly when it should, so
12227 * only enable it on 6bpc panels. */
12228 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12229 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12230 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12231
7758a113 12232fail:
548ee15b 12233 return ret;
ee7b9f93 12234}
47f1c6c9 12235
ea9d758d 12236static void
4740b0f2 12237intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12238{
0a9ab303
ACO		 12239 struct drm_crtc *crtc;
12240 struct drm_crtc_state *crtc_state;
8a75d157 12241 int i;
ea9d758d 12242
7668851f 12243 /* Double check state. */
8a75d157 12244 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12245 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12246
12247 /* Update hwmode for vblank functions */
12248 if (crtc->state->active)
12249 crtc->hwmode = crtc->state->adjusted_mode;
12250 else
12251 crtc->hwmode.crtc_clock = 0;
61067a5e
ML		 12252
12253 /*
12254 * Update legacy state to satisfy fbc code. This can
12255 * be removed when fbc uses the atomic state.
12256 */
12257 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12258 struct drm_plane_state *plane_state = crtc->primary->state;
12259
12260 crtc->primary->fb = plane_state->fb;
12261 crtc->x = plane_state->src_x >> 16;
12262 crtc->y = plane_state->src_y >> 16;
12263 }
ea9d758d 12264 }
ea9d758d
DV		 12265}
12266
3bd26263 12267static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12268{
3bd26263 12269 int diff;
f1f644dc
JB		 12270
12271 if (clock1 == clock2)
12272 return true;
12273
12274 if (!clock1 || !clock2)
12275 return false;
12276
12277 diff = abs(clock1 - clock2);
12278
12279 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12280 return true;
12281
12282 return false;
12283}
12284
25c5b266
DV		 12285#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12286 list_for_each_entry((intel_crtc), \
12287 &(dev)->mode_config.crtc_list, \
12288 base.head) \
0973f18f 12289 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12290
cfb23ed6
ML		 12291static bool
12292intel_compare_m_n(unsigned int m, unsigned int n,
12293 unsigned int m2, unsigned int n2,
12294 bool exact)
12295{
12296 if (m == m2 && n == n2)
12297 return true;
12298
12299 if (exact || !m || !n || !m2 || !n2)
12300 return false;
12301
12302 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12303
12304 if (m > m2) {
12305 while (m > m2) {
12306 m2 <<= 1;
12307 n2 <<= 1;
12308 }
12309 } else if (m < m2) {
12310 while (m < m2) {
12311 m <<= 1;
12312 n <<= 1;
12313 }
12314 }
12315
12316 return m == m2 && n == n2;
12317}
12318
12319static bool
12320intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12321 struct intel_link_m_n *m2_n2,
12322 bool adjust)
12323{
12324 if (m_n->tu == m2_n2->tu &&
12325 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12326 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12327 intel_compare_m_n(m_n->link_m, m_n->link_n,
12328 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12329 if (adjust)
12330 *m2_n2 = *m_n;
12331
12332 return true;
12333 }
12334
12335 return false;
12336}
12337
0e8ffe1b 12338static bool
2fa2fe9a 12339intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12340 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12341 struct intel_crtc_state *pipe_config,
12342 bool adjust)
0e8ffe1b 12343{
cfb23ed6
ML		 12344 bool ret = true;
12345
12346#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12347 do { \
12348 if (!adjust) \
12349 DRM_ERROR(fmt, ##__VA_ARGS__); \
12350 else \
12351 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12352 } while (0)
12353
66e985c0
DV		 12354#define PIPE_CONF_CHECK_X(name) \
12355 if (current_config->name != pipe_config->name) { \
cfb23ed6 12356 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12357 "(expected 0x%08x, found 0x%08x)\n", \
12358 current_config->name, \
12359 pipe_config->name); \
cfb23ed6 12360 ret = false; \
66e985c0
DV		 12361 }
12362
08a24034
DV		 12363#define PIPE_CONF_CHECK_I(name) \
12364 if (current_config->name != pipe_config->name) { \
cfb23ed6 12365 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12366 "(expected %i, found %i)\n", \
12367 current_config->name, \
12368 pipe_config->name); \
cfb23ed6
ML		 12369 ret = false; \
12370 }
12371
12372#define PIPE_CONF_CHECK_M_N(name) \
12373 if (!intel_compare_link_m_n(&current_config->name, \
12374 &pipe_config->name,\
12375 adjust)) { \
12376 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12377 "(expected tu %i gmch %i/%i link %i/%i, " \
12378 "found tu %i, gmch %i/%i link %i/%i)\n", \
12379 current_config->name.tu, \
12380 current_config->name.gmch_m, \
12381 current_config->name.gmch_n, \
12382 current_config->name.link_m, \
12383 current_config->name.link_n, \
12384 pipe_config->name.tu, \
12385 pipe_config->name.gmch_m, \
12386 pipe_config->name.gmch_n, \
12387 pipe_config->name.link_m, \
12388 pipe_config->name.link_n); \
12389 ret = false; \
12390 }
12391
12392#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12393 if (!intel_compare_link_m_n(&current_config->name, \
12394 &pipe_config->name, adjust) && \
12395 !intel_compare_link_m_n(&current_config->alt_name, \
12396 &pipe_config->name, adjust)) { \
12397 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12398 "(expected tu %i gmch %i/%i link %i/%i, " \
12399 "or tu %i gmch %i/%i link %i/%i, " \
12400 "found tu %i, gmch %i/%i link %i/%i)\n", \
12401 current_config->name.tu, \
12402 current_config->name.gmch_m, \
12403 current_config->name.gmch_n, \
12404 current_config->name.link_m, \
12405 current_config->name.link_n, \
12406 current_config->alt_name.tu, \
12407 current_config->alt_name.gmch_m, \
12408 current_config->alt_name.gmch_n, \
12409 current_config->alt_name.link_m, \
12410 current_config->alt_name.link_n, \
12411 pipe_config->name.tu, \
12412 pipe_config->name.gmch_m, \
12413 pipe_config->name.gmch_n, \
12414 pipe_config->name.link_m, \
12415 pipe_config->name.link_n); \
12416 ret = false; \
88adfff1
DV		 12417 }
12418
b95af8be
VK		 12419/* This is required for BDW+ where there is only one set of registers for
12420 * switching between high and low RR.
12421 * This macro can be used whenever a comparison has to be made between one
12422 * hw state and multiple sw state variables.
12423 */
12424#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12425 if ((current_config->name != pipe_config->name) && \
12426 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12427 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12428 "(expected %i or %i, found %i)\n", \
12429 current_config->name, \
12430 current_config->alt_name, \
12431 pipe_config->name); \
cfb23ed6 12432 ret = false; \
b95af8be
VK		 12433 }
12434
1bd1bd80
DV		 12435#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12436 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12437 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12438 "(expected %i, found %i)\n", \
12439 current_config->name & (mask), \
12440 pipe_config->name & (mask)); \
cfb23ed6 12441 ret = false; \
1bd1bd80
DV		 12442 }
12443
5e550656
VS		 12444#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12445 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12446 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12447 "(expected %i, found %i)\n", \
12448 current_config->name, \
12449 pipe_config->name); \
cfb23ed6 12450 ret = false; \
5e550656
VS		 12451 }
12452
bb760063
DV		 12453#define PIPE_CONF_QUIRK(quirk) \
12454 ((current_config->quirks | pipe_config->quirks) & (quirk))
12455
eccb140b
DV		 12456 PIPE_CONF_CHECK_I(cpu_transcoder);
12457
08a24034
DV		 12458 PIPE_CONF_CHECK_I(has_pch_encoder);
12459 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12460 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12461
eb14cb74 12462 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12463 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12464
12465 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12466 PIPE_CONF_CHECK_M_N(dp_m_n);
12467
12468 PIPE_CONF_CHECK_I(has_drrs);
12469 if (current_config->has_drrs)
12470 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12471 } else
12472 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12473
2d112de7
ACO		 12474 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12475 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12476 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12477 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12478 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12479 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12480
2d112de7
ACO		 12481 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12482 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12487
c93f54cf 12488 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12489 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12490 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12491 IS_VALLEYVIEW(dev))
12492 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12493 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12494
9ed109a7
DV		 12495 PIPE_CONF_CHECK_I(has_audio);
12496
2d112de7 12497 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12498 DRM_MODE_FLAG_INTERLACE);
12499
bb760063 12500 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12501 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12502 DRM_MODE_FLAG_PHSYNC);
2d112de7 12503 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12504 DRM_MODE_FLAG_NHSYNC);
2d112de7 12505 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12506 DRM_MODE_FLAG_PVSYNC);
2d112de7 12507 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12508 DRM_MODE_FLAG_NVSYNC);
12509 }
045ac3b5 12510
333b8ca8 12511 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12512 /* pfit ratios are autocomputed by the hw on gen4+ */
12513 if (INTEL_INFO(dev)->gen < 4)
12514 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12515 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12516
bfd16b2a
ML		 12517 if (!adjust) {
12518 PIPE_CONF_CHECK_I(pipe_src_w);
12519 PIPE_CONF_CHECK_I(pipe_src_h);
12520
12521 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12522 if (current_config->pch_pfit.enabled) {
12523 PIPE_CONF_CHECK_X(pch_pfit.pos);
12524 PIPE_CONF_CHECK_X(pch_pfit.size);
12525 }
2fa2fe9a 12526
7aefe2b5
ML		 12527 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12528 }
a1b2278e 12529
e59150dc
JB		 12530 /* BDW+ don't expose a synchronous way to read the state */
12531 if (IS_HASWELL(dev))
12532 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12533
282740f7
VS		 12534 PIPE_CONF_CHECK_I(double_wide);
12535
26804afd
DV		 12536 PIPE_CONF_CHECK_X(ddi_pll_sel);
12537
c0d43d62 12538 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12539 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12540 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12541 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12542 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12543 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12544 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12545 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12546 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12547
42571aef
VS		 12548 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12549 PIPE_CONF_CHECK_I(pipe_bpp);
12550
2d112de7 12551 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12552 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12553
66e985c0 12554#undef PIPE_CONF_CHECK_X
08a24034 12555#undef PIPE_CONF_CHECK_I
b95af8be 12556#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12557#undef PIPE_CONF_CHECK_FLAGS
5e550656 12558#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12559#undef PIPE_CONF_QUIRK
cfb23ed6 12560#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12561
cfb23ed6 12562 return ret;
0e8ffe1b
DV		 12563}
12564
08db6652
DL		 12565static void check_wm_state(struct drm_device *dev)
12566{
12567 struct drm_i915_private *dev_priv = dev->dev_private;
12568 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12569 struct intel_crtc *intel_crtc;
12570 int plane;
12571
12572 if (INTEL_INFO(dev)->gen < 9)
12573 return;
12574
12575 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12576 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12577
12578 for_each_intel_crtc(dev, intel_crtc) {
12579 struct skl_ddb_entry *hw_entry, *sw_entry;
12580 const enum pipe pipe = intel_crtc->pipe;
12581
12582 if (!intel_crtc->active)
12583 continue;
12584
12585 /* planes */
dd740780 12586 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12587 hw_entry = &hw_ddb.plane[pipe][plane];
12588 sw_entry = &sw_ddb->plane[pipe][plane];
12589
12590 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12591 continue;
12592
12593 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12594 "(expected (%u,%u), found (%u,%u))\n",
12595 pipe_name(pipe), plane + 1,
12596 sw_entry->start, sw_entry->end,
12597 hw_entry->start, hw_entry->end);
12598 }
12599
12600 /* cursor */
4969d33e
MR		 12601 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12602 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
08db6652
DL		 12603
12604 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12605 continue;
12606
12607 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12608 "(expected (%u,%u), found (%u,%u))\n",
12609 pipe_name(pipe),
12610 sw_entry->start, sw_entry->end,
12611 hw_entry->start, hw_entry->end);
12612 }
12613}
12614
91d1b4bd 12615static void
35dd3c64
ML		 12616check_connector_state(struct drm_device *dev,
12617 struct drm_atomic_state *old_state)
8af6cf88 12618{
35dd3c64
ML		 12619 struct drm_connector_state *old_conn_state;
12620 struct drm_connector *connector;
12621 int i;
8af6cf88 12622
35dd3c64
ML		 12623 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12624 struct drm_encoder *encoder = connector->encoder;
12625 struct drm_connector_state *state = connector->state;
ad3c558f 12626
8af6cf88
DV		 12627 /* This also checks the encoder/connector hw state with the
12628 * ->get_hw_state callbacks. */
35dd3c64 12629 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12630
ad3c558f 12631 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12632 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12633 }
91d1b4bd
DV		 12634}
12635
12636static void
12637check_encoder_state(struct drm_device *dev)
12638{
12639 struct intel_encoder *encoder;
12640 struct intel_connector *connector;
8af6cf88 12641
b2784e15 12642 for_each_intel_encoder(dev, encoder) {
8af6cf88 12643 bool enabled = false;
4d20cd86 12644 enum pipe pipe;
8af6cf88
DV		 12645
12646 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12647 encoder->base.base.id,
8e329a03 12648 encoder->base.name);
8af6cf88 12649
3a3371ff 12650 for_each_intel_connector(dev, connector) {
4d20cd86 12651 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12652 continue;
12653 enabled = true;
ad3c558f
ML		 12654
12655 I915_STATE_WARN(connector->base.state->crtc !=
12656 encoder->base.crtc,
12657 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12658 }
0e32b39c 12659
e2c719b7 12660 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12661 "encoder's enabled state mismatch "
12662 "(expected %i, found %i)\n",
12663 !!encoder->base.crtc, enabled);
7c60d198
ML		 12664
12665 if (!encoder->base.crtc) {
4d20cd86 12666 bool active;
7c60d198 12667
4d20cd86
ML		 12668 active = encoder->get_hw_state(encoder, &pipe);
12669 I915_STATE_WARN(active,
12670 "encoder detached but still enabled on pipe %c.\n",
12671 pipe_name(pipe));
7c60d198 12672 }
8af6cf88 12673 }
91d1b4bd
DV		 12674}
12675
12676static void
4d20cd86 12677check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12678{
fbee40df 12679 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12680 struct intel_encoder *encoder;
4d20cd86
ML		 12681 struct drm_crtc_state *old_crtc_state;
12682 struct drm_crtc *crtc;
12683 int i;
8af6cf88 12684
4d20cd86
ML		 12685 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12687 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12688 bool active;
8af6cf88 12689
bfd16b2a
ML		 12690 if (!needs_modeset(crtc->state) &&
12691 !to_intel_crtc_state(crtc->state)->update_pipe)
4d20cd86 12692 continue;
045ac3b5 12693
4d20cd86
ML		 12694 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12695 pipe_config = to_intel_crtc_state(old_crtc_state);
12696 memset(pipe_config, 0, sizeof(*pipe_config));
12697 pipe_config->base.crtc = crtc;
12698 pipe_config->base.state = old_state;
8af6cf88 12699
4d20cd86
ML		 12700 DRM_DEBUG_KMS("[CRTC:%d]\n",
12701 crtc->base.id);
8af6cf88 12702
4d20cd86
ML		 12703 active = dev_priv->display.get_pipe_config(intel_crtc,
12704 pipe_config);
d62cf62a 12705
b6b5d049 12706 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12707 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12708 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12709 active = crtc->state->active;
6c49f241 12710
4d20cd86 12711 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12712 "crtc active state doesn't match with hw state "
4d20cd86 12713 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12714
4d20cd86 12715 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12716 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12717 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12718
12719 for_each_encoder_on_crtc(dev, crtc, encoder) {
12720 enum pipe pipe;
12721
12722 active = encoder->get_hw_state(encoder, &pipe);
12723 I915_STATE_WARN(active != crtc->state->active,
12724 "[ENCODER:%i] active %i with crtc active %i\n",
12725 encoder->base.base.id, active, crtc->state->active);
12726
12727 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12728 "Encoder connected to wrong pipe %c\n",
12729 pipe_name(pipe));
12730
12731 if (active)
12732 encoder->get_config(encoder, pipe_config);
12733 }
53d9f4e9 12734
4d20cd86 12735 if (!crtc->state->active)
cfb23ed6
ML		 12736 continue;
12737
4d20cd86
ML		 12738 sw_config = to_intel_crtc_state(crtc->state);
12739 if (!intel_pipe_config_compare(dev, sw_config,
12740 pipe_config, false)) {
e2c719b7 12741 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12742 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12743 "[hw state]");
4d20cd86 12744 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12745 "[sw state]");
12746 }
8af6cf88
DV		 12747 }
12748}
12749
91d1b4bd
DV		 12750static void
12751check_shared_dpll_state(struct drm_device *dev)
12752{
fbee40df 12753 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12754 struct intel_crtc *crtc;
12755 struct intel_dpll_hw_state dpll_hw_state;
12756 int i;
5358901f
DV		 12757
12758 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12759 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12760 int enabled_crtcs = 0, active_crtcs = 0;
12761 bool active;
12762
12763 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12764
12765 DRM_DEBUG_KMS("%s\n", pll->name);
12766
12767 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12768
e2c719b7 12769 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12770 "more active pll users than references: %i vs %i\n",
3e369b76 12771 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12772 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12773 "pll in active use but not on in sw tracking\n");
e2c719b7 12774 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12775 "pll in on but not on in use in sw tracking\n");
e2c719b7 12776 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12777 "pll on state mismatch (expected %i, found %i)\n",
12778 pll->on, active);
12779
d3fcc808 12780 for_each_intel_crtc(dev, crtc) {
83d65738 12781 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12782 enabled_crtcs++;
12783 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12784 active_crtcs++;
12785 }
e2c719b7 12786 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12787 "pll active crtcs mismatch (expected %i, found %i)\n",
12788 pll->active, active_crtcs);
e2c719b7 12789 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12790 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12791 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12792
e2c719b7 12793 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12794 sizeof(dpll_hw_state)),
12795 "pll hw state mismatch\n");
5358901f 12796 }
8af6cf88
DV		 12797}
12798
ee165b1a
ML		 12799static void
12800intel_modeset_check_state(struct drm_device *dev,
12801 struct drm_atomic_state *old_state)
91d1b4bd 12802{
08db6652 12803 check_wm_state(dev);
35dd3c64 12804 check_connector_state(dev, old_state);
91d1b4bd 12805 check_encoder_state(dev);
4d20cd86 12806 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12807 check_shared_dpll_state(dev);
12808}
12809
5cec258b 12810void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12811 int dotclock)
12812{
12813 /*
12814 * FDI already provided one idea for the dotclock.
12815 * Yell if the encoder disagrees.
12816 */
2d112de7 12817 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12818 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12819 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12820}
12821
80715b2f
VS		 12822static void update_scanline_offset(struct intel_crtc *crtc)
12823{
12824 struct drm_device *dev = crtc->base.dev;
12825
12826 /*
12827 * The scanline counter increments at the leading edge of hsync.
12828 *
12829 * On most platforms it starts counting from vtotal-1 on the
12830 * first active line. That means the scanline counter value is
12831 * always one less than what we would expect. Ie. just after
12832 * start of vblank, which also occurs at start of hsync (on the
12833 * last active line), the scanline counter will read vblank_start-1.
12834 *
12835 * On gen2 the scanline counter starts counting from 1 instead
12836 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12837 * to keep the value positive), instead of adding one.
12838 *
12839 * On HSW+ the behaviour of the scanline counter depends on the output
12840 * type. For DP ports it behaves like most other platforms, but on HDMI
12841 * there's an extra 1 line difference. So we need to add two instead of
12842 * one to the value.
12843 */
12844 if (IS_GEN2(dev)) {
124abe07 12845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12846 int vtotal;
12847
124abe07
VS		 12848 vtotal = adjusted_mode->crtc_vtotal;
12849 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS		 12850 vtotal /= 2;
12851
12852 crtc->scanline_offset = vtotal - 1;
12853 } else if (HAS_DDI(dev) &&
409ee761 12854 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12855 crtc->scanline_offset = 2;
12856 } else
12857 crtc->scanline_offset = 1;
12858}
12859
ad421372 12860static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12861{
225da59b 12862 struct drm_device *dev = state->dev;
ed6739ef 12863 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12864 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12865 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12866 struct intel_crtc_state *intel_crtc_state;
12867 struct drm_crtc *crtc;
12868 struct drm_crtc_state *crtc_state;
0a9ab303 12869 int i;
ed6739ef
ACO		 12870
12871 if (!dev_priv->display.crtc_compute_clock)
ad421372 12872 return;
ed6739ef 12873
0a9ab303 12874 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12875 int dpll;
12876
0a9ab303 12877 intel_crtc = to_intel_crtc(crtc);
4978cc93 12878 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12879 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12880
ad421372 12881 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12882 continue;
12883
ad421372 12884 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12885
ad421372
ML		 12886 if (!shared_dpll)
12887 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12888
ad421372
ML		 12889 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12890 }
ed6739ef
ACO		 12891}
12892
99d736a2
ML		 12893/*
12894 * This implements the workaround described in the "notes" section of the mode
12895 * set sequence documentation. When going from no pipes or single pipe to
12896 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12897 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12898 */
12899static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12900{
12901 struct drm_crtc_state *crtc_state;
12902 struct intel_crtc *intel_crtc;
12903 struct drm_crtc *crtc;
12904 struct intel_crtc_state *first_crtc_state = NULL;
12905 struct intel_crtc_state *other_crtc_state = NULL;
12906 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12907 int i;
12908
12909 /* look at all crtc's that are going to be enabled in during modeset */
12910 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12911 intel_crtc = to_intel_crtc(crtc);
12912
12913 if (!crtc_state->active || !needs_modeset(crtc_state))
12914 continue;
12915
12916 if (first_crtc_state) {
12917 other_crtc_state = to_intel_crtc_state(crtc_state);
12918 break;
12919 } else {
12920 first_crtc_state = to_intel_crtc_state(crtc_state);
12921 first_pipe = intel_crtc->pipe;
12922 }
12923 }
12924
12925 /* No workaround needed? */
12926 if (!first_crtc_state)
12927 return 0;
12928
12929 /* w/a possibly needed, check how many crtc's are already enabled. */
12930 for_each_intel_crtc(state->dev, intel_crtc) {
12931 struct intel_crtc_state *pipe_config;
12932
12933 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12934 if (IS_ERR(pipe_config))
12935 return PTR_ERR(pipe_config);
12936
12937 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12938
12939 if (!pipe_config->base.active ||
12940 needs_modeset(&pipe_config->base))
12941 continue;
12942
12943 /* 2 or more enabled crtcs means no need for w/a */
12944 if (enabled_pipe != INVALID_PIPE)
12945 return 0;
12946
12947 enabled_pipe = intel_crtc->pipe;
12948 }
12949
12950 if (enabled_pipe != INVALID_PIPE)
12951 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12952 else if (other_crtc_state)
12953 other_crtc_state->hsw_workaround_pipe = first_pipe;
12954
12955 return 0;
12956}
12957
27c329ed
ML		 12958static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12959{
12960 struct drm_crtc *crtc;
12961 struct drm_crtc_state *crtc_state;
12962 int ret = 0;
12963
12964 /* add all active pipes to the state */
12965 for_each_crtc(state->dev, crtc) {
12966 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12967 if (IS_ERR(crtc_state))
12968 return PTR_ERR(crtc_state);
12969
12970 if (!crtc_state->active || needs_modeset(crtc_state))
12971 continue;
12972
12973 crtc_state->mode_changed = true;
12974
12975 ret = drm_atomic_add_affected_connectors(state, crtc);
12976 if (ret)
12977 break;
12978
12979 ret = drm_atomic_add_affected_planes(state, crtc);
12980 if (ret)
12981 break;
12982 }
12983
12984 return ret;
12985}
12986
c347a676 12987static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12988{
12989 struct drm_device *dev = state->dev;
27c329ed 12990 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12991 int ret;
12992
b359283a
ML		 12993 if (!check_digital_port_conflicts(state)) {
12994 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12995 return -EINVAL;
12996 }
12997
054518dd
ACO		 12998 /*
12999 * See if the config requires any additional preparation, e.g.
13000 * to adjust global state with pipes off. We need to do this
13001 * here so we can get the modeset_pipe updated config for the new
13002 * mode set on this crtc. For other crtcs we need to use the
13003 * adjusted_mode bits in the crtc directly.
13004 */
27c329ed
ML		 13005 if (dev_priv->display.modeset_calc_cdclk) {
13006 unsigned int cdclk;
b432e5cf 13007
27c329ed
ML		 13008 ret = dev_priv->display.modeset_calc_cdclk(state);
13009
13010 cdclk = to_intel_atomic_state(state)->cdclk;
13011 if (!ret && cdclk != dev_priv->cdclk_freq)
13012 ret = intel_modeset_all_pipes(state);
13013
13014 if (ret < 0)
054518dd 13015 return ret;
27c329ed
ML		 13016 } else
13017 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13018
ad421372 13019 intel_modeset_clear_plls(state);
054518dd 13020
99d736a2 13021 if (IS_HASWELL(dev))
ad421372 13022 return haswell_mode_set_planes_workaround(state);
99d736a2 13023
ad421372 13024 return 0;
c347a676
ACO		 13025}
13026
aa363136
MR		 13027/*
13028 * Handle calculation of various watermark data at the end of the atomic check
13029 * phase. The code here should be run after the per-crtc and per-plane 'check'
13030 * handlers to ensure that all derived state has been updated.
13031 */
13032static void calc_watermark_data(struct drm_atomic_state *state)
13033{
13034 struct drm_device *dev = state->dev;
13035 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13036 struct drm_crtc *crtc;
13037 struct drm_crtc_state *cstate;
13038 struct drm_plane *plane;
13039 struct drm_plane_state *pstate;
13040
13041 /*
13042 * Calculate watermark configuration details now that derived
13043 * plane/crtc state is all properly updated.
13044 */
13045 drm_for_each_crtc(crtc, dev) {
13046 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13047 crtc->state;
13048
13049 if (cstate->active)
13050 intel_state->wm_config.num_pipes_active++;
13051 }
13052 drm_for_each_legacy_plane(plane, dev) {
13053 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13054 plane->state;
13055
13056 if (!to_intel_plane_state(pstate)->visible)
13057 continue;
13058
13059 intel_state->wm_config.sprites_enabled = true;
13060 if (pstate->crtc_w != pstate->src_w >> 16 ||
13061 pstate->crtc_h != pstate->src_h >> 16)
13062 intel_state->wm_config.sprites_scaled = true;
13063 }
13064}
13065
74c090b1
ML		 13066/**
13067 * intel_atomic_check - validate state object
13068 * @dev: drm device
13069 * @state: state to validate
13070 */
13071static int intel_atomic_check(struct drm_device *dev,
13072 struct drm_atomic_state *state)
c347a676 13073{
aa363136 13074 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676
ACO		 13075 struct drm_crtc *crtc;
13076 struct drm_crtc_state *crtc_state;
13077 int ret, i;
61333b60 13078 bool any_ms = false;
c347a676 13079
74c090b1 13080 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13081 if (ret)
13082 return ret;
13083
c347a676 13084 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13085 struct intel_crtc_state *pipe_config =
13086 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 13087
13088 /* Catch I915_MODE_FLAG_INHERITED */
13089 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13090 crtc_state->mode_changed = true;
cfb23ed6 13091
61333b60
ML		 13092 if (!crtc_state->enable) {
13093 if (needs_modeset(crtc_state))
13094 any_ms = true;
c347a676 13095 continue;
61333b60 13096 }
c347a676 13097
26495481 13098 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 13099 continue;
13100
26495481
DV		 13101 /* FIXME: For only active_changed we shouldn't need to do any
13102 * state recomputation at all. */
13103
1ed51de9
DV		 13104 ret = drm_atomic_add_affected_connectors(state, crtc);
13105 if (ret)
13106 return ret;
b359283a 13107
cfb23ed6 13108 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13109 if (ret)
13110 return ret;
13111
6764e9f8 13112 if (intel_pipe_config_compare(state->dev,
cfb23ed6 13113 to_intel_crtc_state(crtc->state),
1ed51de9 13114 pipe_config, true)) {
26495481 13115 crtc_state->mode_changed = false;
bfd16b2a 13116 to_intel_crtc_state(crtc_state)->update_pipe = true;
26495481
DV		 13117 }
13118
13119 if (needs_modeset(crtc_state)) {
13120 any_ms = true;
cfb23ed6
ML		 13121
13122 ret = drm_atomic_add_affected_planes(state, crtc);
13123 if (ret)
13124 return ret;
13125 }
61333b60 13126
26495481
DV		 13127 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13128 needs_modeset(crtc_state) ?
13129 "[modeset]" : "[fastset]");
c347a676
ACO		 13130 }
13131
61333b60
ML		 13132 if (any_ms) {
13133 ret = intel_modeset_checks(state);
13134
13135 if (ret)
13136 return ret;
27c329ed 13137 } else
aa363136 13138 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
76305b1a 13139
aa363136
MR		 13140 ret = drm_atomic_helper_check_planes(state->dev, state);
13141 if (ret)
13142 return ret;
13143
13144 calc_watermark_data(state);
13145
13146 return 0;
054518dd
ACO		 13147}
13148
5008e874
ML		 13149static int intel_atomic_prepare_commit(struct drm_device *dev,
13150 struct drm_atomic_state *state,
13151 bool async)
13152{
13153 struct drm_crtc_state *crtc_state;
13154 struct drm_crtc *crtc;
13155 int i, ret;
13156
13157 if (async) {
13158 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13159 return -EINVAL;
13160 }
13161
13162 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13163 ret = intel_crtc_wait_for_pending_flips(crtc);
13164 if (ret)
13165 return ret;
13166 }
13167
f935675f
ML		 13168 ret = mutex_lock_interruptible(&dev->struct_mutex);
13169 if (ret)
13170 return ret;
13171
5008e874
ML		 13172 ret = drm_atomic_helper_prepare_planes(dev, state);
13173
f935675f 13174 mutex_unlock(&dev->struct_mutex);
5008e874
ML		 13175 return ret;
13176}
13177
74c090b1
ML		 13178/**
13179 * intel_atomic_commit - commit validated state object
13180 * @dev: DRM device
13181 * @state: the top-level driver state object
13182 * @async: asynchronous commit
13183 *
13184 * This function commits a top-level state object that has been validated
13185 * with drm_atomic_helper_check().
13186 *
13187 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13188 * we can only handle plane-related operations and do not yet support
13189 * asynchronous commit.
13190 *
13191 * RETURNS
13192 * Zero for success or -errno.
13193 */
13194static int intel_atomic_commit(struct drm_device *dev,
13195 struct drm_atomic_state *state,
13196 bool async)
a6778b3c 13197{
fbee40df 13198 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13199 struct drm_crtc *crtc;
13200 struct drm_crtc_state *crtc_state;
c0c36b94 13201 int ret = 0;
0a9ab303 13202 int i;
61333b60 13203 bool any_ms = false;
a6778b3c 13204
5008e874 13205 ret = intel_atomic_prepare_commit(dev, state, async);
d4afb8cc
ACO		 13206 if (ret)
13207 return ret;
13208
1c5e19f8 13209 drm_atomic_helper_swap_state(dev, state);
aa363136 13210 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
1c5e19f8 13211
0a9ab303 13212 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13214
61333b60
ML		 13215 if (!needs_modeset(crtc->state))
13216 continue;
13217
13218 any_ms = true;
a539205a 13219 intel_pre_plane_update(intel_crtc);
460da916 13220
a539205a
ML		 13221 if (crtc_state->active) {
13222 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13223 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13224 intel_crtc->active = false;
13225 intel_disable_shared_dpll(intel_crtc);
a539205a 13226 }
b8cecdf5 13227 }
7758a113 13228
ea9d758d
DV		 13229 /* Only after disabling all output pipelines that will be changed can we
13230 * update the the output configuration. */
4740b0f2 13231 intel_modeset_update_crtc_state(state);
f6e5b160 13232
4740b0f2
ML		 13233 if (any_ms) {
13234 intel_shared_dpll_commit(state);
13235
13236 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13237 modeset_update_crtc_power_domains(state);
4740b0f2 13238 }
47fab737 13239
a6778b3c 13240 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13241 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13243 bool modeset = needs_modeset(crtc->state);
bfd16b2a
ML		 13244 bool update_pipe = !modeset &&
13245 to_intel_crtc_state(crtc->state)->update_pipe;
13246 unsigned long put_domains = 0;
f6ac4b2a
ML		 13247
13248 if (modeset && crtc->state->active) {
a539205a
ML		 13249 update_scanline_offset(to_intel_crtc(crtc));
13250 dev_priv->display.crtc_enable(crtc);
13251 }
80715b2f 13252
bfd16b2a
ML		 13253 if (update_pipe) {
13254 put_domains = modeset_get_crtc_power_domains(crtc);
13255
13256 /* make sure intel_modeset_check_state runs */
13257 any_ms = true;
13258 }
13259
f6ac4b2a
ML		 13260 if (!modeset)
13261 intel_pre_plane_update(intel_crtc);
13262
6173ee28
ML		 13263 if (crtc->state->active &&
13264 (crtc->state->planes_changed || update_pipe))
62852622 13265 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
bfd16b2a
ML		 13266
13267 if (put_domains)
13268 modeset_put_power_domains(dev_priv, put_domains);
13269
f6ac4b2a 13270 intel_post_plane_update(intel_crtc);
80715b2f 13271 }
a6778b3c 13272
a6778b3c 13273 /* FIXME: add subpixel order */
83a57153 13274
74c090b1 13275 drm_atomic_helper_wait_for_vblanks(dev, state);
f935675f
ML		 13276
13277 mutex_lock(&dev->struct_mutex);
d4afb8cc 13278 drm_atomic_helper_cleanup_planes(dev, state);
f935675f 13279 mutex_unlock(&dev->struct_mutex);
2bfb4627 13280
74c090b1 13281 if (any_ms)
ee165b1a
ML		 13282 intel_modeset_check_state(dev, state);
13283
13284 drm_atomic_state_free(state);
f30da187 13285
74c090b1 13286 return 0;
7f27126e
JB		 13287}
13288
c0c36b94
CW		 13289void intel_crtc_restore_mode(struct drm_crtc *crtc)
13290{
83a57153
ACO		 13291 struct drm_device *dev = crtc->dev;
13292 struct drm_atomic_state *state;
e694eb02 13293 struct drm_crtc_state *crtc_state;
2bfb4627 13294 int ret;
83a57153
ACO		 13295
13296 state = drm_atomic_state_alloc(dev);
13297 if (!state) {
e694eb02 13298 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13299 crtc->base.id);
13300 return;
13301 }
13302
e694eb02 13303 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13304
e694eb02
ML		 13305retry:
13306 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13307 ret = PTR_ERR_OR_ZERO(crtc_state);
13308 if (!ret) {
13309 if (!crtc_state->active)
13310 goto out;
83a57153 13311
e694eb02 13312 crtc_state->mode_changed = true;
74c090b1 13313 ret = drm_atomic_commit(state);
83a57153
ACO		 13314 }
13315
e694eb02
ML		 13316 if (ret == -EDEADLK) {
13317 drm_atomic_state_clear(state);
13318 drm_modeset_backoff(state->acquire_ctx);
13319 goto retry;
4ed9fb37 13320 }
4be07317 13321
2bfb4627 13322 if (ret)
e694eb02 13323out:
2bfb4627 13324 drm_atomic_state_free(state);
c0c36b94
CW		 13325}
13326
25c5b266
DV		 13327#undef for_each_intel_crtc_masked
13328
f6e5b160 13329static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13330 .gamma_set = intel_crtc_gamma_set,
74c090b1 13331 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13332 .destroy = intel_crtc_destroy,
13333 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13334 .atomic_duplicate_state = intel_crtc_duplicate_state,
13335 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13336};
13337
5358901f
DV		 13338static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13339 struct intel_shared_dpll *pll,
13340 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13341{
5358901f 13342 uint32_t val;
ee7b9f93 13343
f458ebbc 13344 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13345 return false;
13346
5358901f 13347 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13348 hw_state->dpll = val;
13349 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13350 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13351
13352 return val & DPLL_VCO_ENABLE;
13353}
13354
15bdd4cf
DV		 13355static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13356 struct intel_shared_dpll *pll)
13357{
3e369b76
ACO		 13358 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13359 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13360}
13361
e7b903d2
DV		 13362static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13363 struct intel_shared_dpll *pll)
13364{
e7b903d2 13365 /* PCH refclock must be enabled first */
89eff4be 13366 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13367
3e369b76 13368 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13369
13370 /* Wait for the clocks to stabilize. */
13371 POSTING_READ(PCH_DPLL(pll->id));
13372 udelay(150);
13373
13374 /* The pixel multiplier can only be updated once the
13375 * DPLL is enabled and the clocks are stable.
13376 *
13377 * So write it again.
13378 */
3e369b76 13379 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13380 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13381 udelay(200);
13382}
13383
13384static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13385 struct intel_shared_dpll *pll)
13386{
13387 struct drm_device *dev = dev_priv->dev;
13388 struct intel_crtc *crtc;
e7b903d2
DV		 13389
13390 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13391 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13392 if (intel_crtc_to_shared_dpll(crtc) == pll)
13393 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13394 }
13395
15bdd4cf
DV		 13396 I915_WRITE(PCH_DPLL(pll->id), 0);
13397 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13398 udelay(200);
13399}
13400
46edb027
DV		 13401static char *ibx_pch_dpll_names[] = {
13402 "PCH DPLL A",
13403 "PCH DPLL B",
13404};
13405
7c74ade1 13406static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13407{
e7b903d2 13408 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13409 int i;
13410
7c74ade1 13411 dev_priv->num_shared_dpll = 2;
ee7b9f93 13412
e72f9fbf 13413 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13414 dev_priv->shared_dplls[i].id = i;
13415 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13416 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13417 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13418 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13419 dev_priv->shared_dplls[i].get_hw_state =
13420 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13421 }
13422}
13423
7c74ade1
DV		 13424static void intel_shared_dpll_init(struct drm_device *dev)
13425{
e7b903d2 13426 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13427
9cd86933
DV		 13428 if (HAS_DDI(dev))
13429 intel_ddi_pll_init(dev);
13430 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13431 ibx_pch_dpll_init(dev);
13432 else
13433 dev_priv->num_shared_dpll = 0;
13434
13435 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13436}
13437
6beb8c23
MR		 13438/**
13439 * intel_prepare_plane_fb - Prepare fb for usage on plane
13440 * @plane: drm plane to prepare for
13441 * @fb: framebuffer to prepare for presentation
13442 *
13443 * Prepares a framebuffer for usage on a display plane. Generally this
13444 * involves pinning the underlying object and updating the frontbuffer tracking
13445 * bits. Some older platforms need special physical address handling for
13446 * cursor planes.
13447 *
f935675f
ML		 13448 * Must be called with struct_mutex held.
13449 *
6beb8c23
MR		 13450 * Returns 0 on success, negative error code on failure.
13451 */
13452int
13453intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee 13454 const struct drm_plane_state *new_state)
465c120c
MR		 13455{
13456 struct drm_device *dev = plane->dev;
844f9111 13457 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13458 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23 13459 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13460 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
6beb8c23 13461 int ret = 0;
465c120c 13462
1ee49399 13463 if (!obj && !old_obj)
465c120c
MR		 13464 return 0;
13465
5008e874
ML		 13466 if (old_obj) {
13467 struct drm_crtc_state *crtc_state =
13468 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13469
13470 /* Big Hammer, we also need to ensure that any pending
13471 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13472 * current scanout is retired before unpinning the old
13473 * framebuffer. Note that we rely on userspace rendering
13474 * into the buffer attached to the pipe they are waiting
13475 * on. If not, userspace generates a GPU hang with IPEHR
13476 * point to the MI_WAIT_FOR_EVENT.
13477 *
13478 * This should only fail upon a hung GPU, in which case we
13479 * can safely continue.
13480 */
13481 if (needs_modeset(crtc_state))
13482 ret = i915_gem_object_wait_rendering(old_obj, true);
13483
13484 /* Swallow -EIO errors to allow updates during hw lockup. */
13485 if (ret && ret != -EIO)
f935675f 13486 return ret;
5008e874
ML		 13487 }
13488
1ee49399
ML		 13489 if (!obj) {
13490 ret = 0;
13491 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
6beb8c23
MR		 13492 INTEL_INFO(dev)->cursor_needs_physical) {
13493 int align = IS_I830(dev) ? 16 * 1024 : 256;
13494 ret = i915_gem_object_attach_phys(obj, align);
13495 if (ret)
13496 DRM_DEBUG_KMS("failed to attach phys object\n");
13497 } else {
91af127f 13498 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13499 }
465c120c 13500
6beb8c23 13501 if (ret == 0)
a9ff8714 13502 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13503
6beb8c23
MR		 13504 return ret;
13505}
13506
38f3ce3a
MR		 13507/**
13508 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13509 * @plane: drm plane to clean up for
13510 * @fb: old framebuffer that was on plane
13511 *
13512 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML		 13513 *
13514 * Must be called with struct_mutex held.
38f3ce3a
MR		 13515 */
13516void
13517intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee 13518 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13519{
13520 struct drm_device *dev = plane->dev;
1ee49399
ML		 13521 struct intel_plane *intel_plane = to_intel_plane(plane);
13522 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13523 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
38f3ce3a 13524
1ee49399 13525 if (!obj && !old_obj)
38f3ce3a
MR		 13526 return;
13527
1ee49399
ML		 13528 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13529 !INTEL_INFO(dev)->cursor_needs_physical))
844f9111 13530 intel_unpin_fb_obj(old_state->fb, old_state);
1ee49399
ML		 13531
13532 /* prepare_fb aborted? */
13533 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13534 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13535 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
465c120c
MR		 13536}
13537
6156a456
CK		 13538int
13539skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13540{
13541 int max_scale;
13542 struct drm_device *dev;
13543 struct drm_i915_private *dev_priv;
13544 int crtc_clock, cdclk;
13545
13546 if (!intel_crtc || !crtc_state)
13547 return DRM_PLANE_HELPER_NO_SCALING;
13548
13549 dev = intel_crtc->base.dev;
13550 dev_priv = dev->dev_private;
13551 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13552 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456 13553
54bf1ce6 13554 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
6156a456
CK		 13555 return DRM_PLANE_HELPER_NO_SCALING;
13556
13557 /*
13558 * skl max scale is lower of:
13559 * close to 3 but not 3, -1 is for that purpose
13560 * or
13561 * cdclk/crtc_clock
13562 */
13563 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13564
13565 return max_scale;
13566}
13567
465c120c 13568static int
3c692a41 13569intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13570 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13571 struct intel_plane_state *state)
13572{
2b875c22
MR		 13573 struct drm_crtc *crtc = state->base.crtc;
13574 struct drm_framebuffer *fb = state->base.fb;
6156a456 13575 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13576 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13577 bool can_position = false;
465c120c 13578
061e4b8d
ML		 13579 /* use scaler when colorkey is not required */
13580 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13581 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13582 min_scale = 1;
13583 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13584 can_position = true;
6156a456 13585 }
d8106366 13586
061e4b8d
ML		 13587 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13588 &state->dst, &state->clip,
da20eabd
ML		 13589 min_scale, max_scale,
13590 can_position, true,
13591 &state->visible);
14af293f
GP		 13592}
13593
13594static void
13595intel_commit_primary_plane(struct drm_plane *plane,
13596 struct intel_plane_state *state)
13597{
2b875c22
MR		 13598 struct drm_crtc *crtc = state->base.crtc;
13599 struct drm_framebuffer *fb = state->base.fb;
13600 struct drm_device *dev = plane->dev;
14af293f 13601 struct drm_i915_private *dev_priv = dev->dev_private;
14af293f 13602
ea2c67bb 13603 crtc = crtc ? crtc : plane->crtc;
ccc759dc 13604
d4b08630
ML		 13605 dev_priv->display.update_primary_plane(crtc, fb,
13606 state->src.x1 >> 16,
13607 state->src.y1 >> 16);
465c120c
MR		 13608}
13609
a8ad0d8e
ML		 13610static void
13611intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13612 struct drm_crtc *crtc)
a8ad0d8e
ML		 13613{
13614 struct drm_device *dev = plane->dev;
13615 struct drm_i915_private *dev_priv = dev->dev_private;
13616
a8ad0d8e
ML		 13617 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13618}
13619
613d2b27
ML		 13620static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13621 struct drm_crtc_state *old_crtc_state)
3c692a41 13622{
32b7eeec 13623 struct drm_device *dev = crtc->dev;
3c692a41 13624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bfd16b2a
ML		 13625 struct intel_crtc_state *old_intel_state =
13626 to_intel_crtc_state(old_crtc_state);
13627 bool modeset = needs_modeset(crtc->state);
3c692a41 13628
f015c551 13629 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13630 intel_update_watermarks(crtc);
3c692a41 13631
c34c9ee4 13632 /* Perform vblank evasion around commit operation */
62852622 13633 intel_pipe_update_start(intel_crtc);
0583236e 13634
bfd16b2a
ML		 13635 if (modeset)
13636 return;
13637
13638 if (to_intel_crtc_state(crtc->state)->update_pipe)
13639 intel_update_pipe_config(intel_crtc, old_intel_state);
13640 else if (INTEL_INFO(dev)->gen >= 9)
0583236e 13641 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13642}
13643
613d2b27
ML		 13644static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13645 struct drm_crtc_state *old_crtc_state)
32b7eeec 13646{
32b7eeec 13647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13648
62852622 13649 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13650}
13651
cf4c7c12 13652/**
4a3b8769
MR		 13653 * intel_plane_destroy - destroy a plane
13654 * @plane: plane to destroy
cf4c7c12 13655 *
4a3b8769
MR		 13656 * Common destruction function for all types of planes (primary, cursor,
13657 * sprite).
cf4c7c12 13658 */
4a3b8769 13659void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13660{
13661 struct intel_plane *intel_plane = to_intel_plane(plane);
13662 drm_plane_cleanup(plane);
13663 kfree(intel_plane);
13664}
13665
65a3fea0 13666const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13667 .update_plane = drm_atomic_helper_update_plane,
13668 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13669 .destroy = intel_plane_destroy,
c196e1d6 13670 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13671 .atomic_get_property = intel_plane_atomic_get_property,
13672 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13673 .atomic_duplicate_state = intel_plane_duplicate_state,
13674 .atomic_destroy_state = intel_plane_destroy_state,
13675
465c120c
MR		 13676};
13677
13678static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13679 int pipe)
13680{
13681 struct intel_plane *primary;
8e7d688b 13682 struct intel_plane_state *state;
465c120c 13683 const uint32_t *intel_primary_formats;
45e3743a 13684 unsigned int num_formats;
465c120c
MR		 13685
13686 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13687 if (primary == NULL)
13688 return NULL;
13689
8e7d688b
MR		 13690 state = intel_create_plane_state(&primary->base);
13691 if (!state) {
ea2c67bb
MR		 13692 kfree(primary);
13693 return NULL;
13694 }
8e7d688b 13695 primary->base.state = &state->base;
ea2c67bb 13696
465c120c
MR		 13697 primary->can_scale = false;
13698 primary->max_downscale = 1;
6156a456
CK		 13699 if (INTEL_INFO(dev)->gen >= 9) {
13700 primary->can_scale = true;
af99ceda 13701 state->scaler_id = -1;
6156a456 13702 }
465c120c
MR		 13703 primary->pipe = pipe;
13704 primary->plane = pipe;
a9ff8714 13705 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13706 primary->check_plane = intel_check_primary_plane;
13707 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13708 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13709 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13710 primary->plane = !pipe;
13711
6c0fd451
DL		 13712 if (INTEL_INFO(dev)->gen >= 9) {
13713 intel_primary_formats = skl_primary_formats;
13714 num_formats = ARRAY_SIZE(skl_primary_formats);
13715 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13716 intel_primary_formats = i965_primary_formats;
13717 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13718 } else {
13719 intel_primary_formats = i8xx_primary_formats;
13720 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13721 }
13722
13723 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13724 &intel_plane_funcs,
465c120c
MR		 13725 intel_primary_formats, num_formats,
13726 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13727
3b7a5119
SJ		 13728 if (INTEL_INFO(dev)->gen >= 4)
13729 intel_create_rotation_property(dev, primary);
48404c1e 13730
ea2c67bb
MR		 13731 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13732
465c120c
MR		 13733 return &primary->base;
13734}
13735
3b7a5119
SJ		 13736void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13737{
13738 if (!dev->mode_config.rotation_property) {
13739 unsigned long flags = BIT(DRM_ROTATE_0) |
13740 BIT(DRM_ROTATE_180);
13741
13742 if (INTEL_INFO(dev)->gen >= 9)
13743 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13744
13745 dev->mode_config.rotation_property =
13746 drm_mode_create_rotation_property(dev, flags);
13747 }
13748 if (dev->mode_config.rotation_property)
13749 drm_object_attach_property(&plane->base.base,
13750 dev->mode_config.rotation_property,
13751 plane->base.state->rotation);
13752}
13753
3d7d6510 13754static int
852e787c 13755intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13756 struct intel_crtc_state *crtc_state,
852e787c 13757 struct intel_plane_state *state)
3d7d6510 13758{
061e4b8d 13759 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13760 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13761 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13762 unsigned stride;
13763 int ret;
3d7d6510 13764
061e4b8d
ML		 13765 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13766 &state->dst, &state->clip,
3d7d6510
MR		 13767 DRM_PLANE_HELPER_NO_SCALING,
13768 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13769 true, true, &state->visible);
757f9a3e
GP		 13770 if (ret)
13771 return ret;
13772
757f9a3e
GP		 13773 /* if we want to turn off the cursor ignore width and height */
13774 if (!obj)
da20eabd 13775 return 0;
757f9a3e 13776
757f9a3e 13777 /* Check for which cursor types we support */
061e4b8d 13778 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13779 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13780 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13781 return -EINVAL;
13782 }
13783
ea2c67bb
MR		 13784 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13785 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13786 DRM_DEBUG_KMS("buffer is too small\n");
13787 return -ENOMEM;
13788 }
13789
3a656b54 13790 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13791 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13792 return -EINVAL;
32b7eeec
MR		 13793 }
13794
da20eabd 13795 return 0;
852e787c 13796}
3d7d6510 13797
a8ad0d8e
ML		 13798static void
13799intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13800 struct drm_crtc *crtc)
a8ad0d8e 13801{
a8ad0d8e
ML		 13802 intel_crtc_update_cursor(crtc, false);
13803}
13804
f4a2cf29 13805static void
852e787c
GP		 13806intel_commit_cursor_plane(struct drm_plane *plane,
13807 struct intel_plane_state *state)
13808{
2b875c22 13809 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13810 struct drm_device *dev = plane->dev;
13811 struct intel_crtc *intel_crtc;
2b875c22 13812 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13813 uint32_t addr;
852e787c 13814
ea2c67bb
MR		 13815 crtc = crtc ? crtc : plane->crtc;
13816 intel_crtc = to_intel_crtc(crtc);
13817
a912f12f
GP		 13818 if (intel_crtc->cursor_bo == obj)
13819 goto update;
4ed91096 13820
f4a2cf29 13821 if (!obj)
a912f12f 13822 addr = 0;
f4a2cf29 13823 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13824 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13825 else
a912f12f 13826 addr = obj->phys_handle->busaddr;
852e787c 13827
a912f12f
GP		 13828 intel_crtc->cursor_addr = addr;
13829 intel_crtc->cursor_bo = obj;
852e787c 13830
302d19ac 13831update:
62852622 13832 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13833}
13834
3d7d6510
MR		 13835static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13836 int pipe)
13837{
13838 struct intel_plane *cursor;
8e7d688b 13839 struct intel_plane_state *state;
3d7d6510
MR		 13840
13841 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13842 if (cursor == NULL)
13843 return NULL;
13844
8e7d688b
MR		 13845 state = intel_create_plane_state(&cursor->base);
13846 if (!state) {
ea2c67bb
MR		 13847 kfree(cursor);
13848 return NULL;
13849 }
8e7d688b 13850 cursor->base.state = &state->base;
ea2c67bb 13851
3d7d6510
MR		 13852 cursor->can_scale = false;
13853 cursor->max_downscale = 1;
13854 cursor->pipe = pipe;
13855 cursor->plane = pipe;
a9ff8714 13856 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13857 cursor->check_plane = intel_check_cursor_plane;
13858 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13859 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13860
13861 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13862 &intel_plane_funcs,
3d7d6510
MR		 13863 intel_cursor_formats,
13864 ARRAY_SIZE(intel_cursor_formats),
13865 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13866
13867 if (INTEL_INFO(dev)->gen >= 4) {
13868 if (!dev->mode_config.rotation_property)
13869 dev->mode_config.rotation_property =
13870 drm_mode_create_rotation_property(dev,
13871 BIT(DRM_ROTATE_0) |
13872 BIT(DRM_ROTATE_180));
13873 if (dev->mode_config.rotation_property)
13874 drm_object_attach_property(&cursor->base.base,
13875 dev->mode_config.rotation_property,
8e7d688b 13876 state->base.rotation);
4398ad45
VS		 13877 }
13878
af99ceda
CK		 13879 if (INTEL_INFO(dev)->gen >=9)
13880 state->scaler_id = -1;
13881
ea2c67bb
MR		 13882 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13883
3d7d6510
MR		 13884 return &cursor->base;
13885}
13886
549e2bfb
CK		 13887static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13888 struct intel_crtc_state *crtc_state)
13889{
13890 int i;
13891 struct intel_scaler *intel_scaler;
13892 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13893
13894 for (i = 0; i < intel_crtc->num_scalers; i++) {
13895 intel_scaler = &scaler_state->scalers[i];
13896 intel_scaler->in_use = 0;
549e2bfb
CK		 13897 intel_scaler->mode = PS_SCALER_MODE_DYN;
13898 }
13899
13900 scaler_state->scaler_id = -1;
13901}
13902
b358d0a6 13903static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13904{
fbee40df 13905 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13906 struct intel_crtc *intel_crtc;
f5de6e07 13907 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13908 struct drm_plane *primary = NULL;
13909 struct drm_plane *cursor = NULL;
465c120c 13910 int i, ret;
79e53945 13911
955382f3 13912 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13913 if (intel_crtc == NULL)
13914 return;
13915
f5de6e07
ACO		 13916 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13917 if (!crtc_state)
13918 goto fail;
550acefd
ACO		 13919 intel_crtc->config = crtc_state;
13920 intel_crtc->base.state = &crtc_state->base;
07878248 13921 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13922
549e2bfb
CK		 13923 /* initialize shared scalers */
13924 if (INTEL_INFO(dev)->gen >= 9) {
13925 if (pipe == PIPE_C)
13926 intel_crtc->num_scalers = 1;
13927 else
13928 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13929
13930 skl_init_scalers(dev, intel_crtc, crtc_state);
13931 }
13932
465c120c 13933 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13934 if (!primary)
13935 goto fail;
13936
13937 cursor = intel_cursor_plane_create(dev, pipe);
13938 if (!cursor)
13939 goto fail;
13940
465c120c 13941 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13942 cursor, &intel_crtc_funcs);
13943 if (ret)
13944 goto fail;
79e53945
JB		 13945
13946 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13947 for (i = 0; i < 256; i++) {
13948 intel_crtc->lut_r[i] = i;
13949 intel_crtc->lut_g[i] = i;
13950 intel_crtc->lut_b[i] = i;
13951 }
13952
1f1c2e24
VS		 13953 /*
13954 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13955 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13956 */
80824003
JB		 13957 intel_crtc->pipe = pipe;
13958 intel_crtc->plane = pipe;
3a77c4c4 13959 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13960 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13961 intel_crtc->plane = !pipe;
80824003
JB		 13962 }
13963
4b0e333e
CW		 13964 intel_crtc->cursor_base = ~0;
13965 intel_crtc->cursor_cntl = ~0;
dc41c154 13966 intel_crtc->cursor_size = ~0;
8d7849db 13967
852eb00d
VS		 13968 intel_crtc->wm.cxsr_allowed = true;
13969
22fd0fab
JB		 13970 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13971 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13972 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13973 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13974
79e53945 13975 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13976
13977 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13978 return;
13979
13980fail:
13981 if (primary)
13982 drm_plane_cleanup(primary);
13983 if (cursor)
13984 drm_plane_cleanup(cursor);
f5de6e07 13985 kfree(crtc_state);
3d7d6510 13986 kfree(intel_crtc);
79e53945
JB		 13987}
13988
752aa88a
JB		 13989enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13990{
13991 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13992 struct drm_device *dev = connector->base.dev;
752aa88a 13993
51fd371b 13994 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13995
d3babd3f 13996 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13997 return INVALID_PIPE;
13998
13999 return to_intel_crtc(encoder->crtc)->pipe;
14000}
14001
08d7b3d1 14002int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14003 struct drm_file *file)
08d7b3d1 14004{
08d7b3d1 14005 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14006 struct drm_crtc *drmmode_crtc;
c05422d5 14007 struct intel_crtc *crtc;
08d7b3d1 14008
7707e653 14009 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14010
7707e653 14011 if (!drmmode_crtc) {
08d7b3d1 14012 DRM_ERROR("no such CRTC id\n");
3f2c2057 14013 return -ENOENT;
08d7b3d1
CW		 14014 }
14015
7707e653 14016 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14017 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14018
c05422d5 14019 return 0;
08d7b3d1
CW		 14020}
14021
66a9278e 14022static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14023{
66a9278e
DV		 14024 struct drm_device *dev = encoder->base.dev;
14025 struct intel_encoder *source_encoder;
79e53945 14026 int index_mask = 0;
79e53945
JB		 14027 int entry = 0;
14028
b2784e15 14029 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14030 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14031 index_mask |= (1 << entry);
14032
79e53945
JB		 14033 entry++;
14034 }
4ef69c7a 14035
79e53945
JB		 14036 return index_mask;
14037}
14038
4d302442
CW		 14039static bool has_edp_a(struct drm_device *dev)
14040{
14041 struct drm_i915_private *dev_priv = dev->dev_private;
14042
14043 if (!IS_MOBILE(dev))
14044 return false;
14045
14046 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14047 return false;
14048
e3589908 14049 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14050 return false;
14051
14052 return true;
14053}
14054
84b4e042
JB		 14055static bool intel_crt_present(struct drm_device *dev)
14056{
14057 struct drm_i915_private *dev_priv = dev->dev_private;
14058
884497ed
DL		 14059 if (INTEL_INFO(dev)->gen >= 9)
14060 return false;
14061
cf404ce4 14062 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14063 return false;
14064
14065 if (IS_CHERRYVIEW(dev))
14066 return false;
14067
14068 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14069 return false;
14070
14071 return true;
14072}
14073
79e53945
JB		 14074static void intel_setup_outputs(struct drm_device *dev)
14075{
725e30ad 14076 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14077 struct intel_encoder *encoder;
cb0953d7 14078 bool dpd_is_edp = false;
79e53945 14079
c9093354 14080 intel_lvds_init(dev);
79e53945 14081
84b4e042 14082 if (intel_crt_present(dev))
79935fca 14083 intel_crt_init(dev);
cb0953d7 14084
c776eb2e
VK		 14085 if (IS_BROXTON(dev)) {
14086 /*
14087 * FIXME: Broxton doesn't support port detection via the
14088 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14089 * detect the ports.
14090 */
14091 intel_ddi_init(dev, PORT_A);
14092 intel_ddi_init(dev, PORT_B);
14093 intel_ddi_init(dev, PORT_C);
14094 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14095 int found;
14096
de31facd
JB		 14097 /*
14098 * Haswell uses DDI functions to detect digital outputs.
14099 * On SKL pre-D0 the strap isn't connected, so we assume
14100 * it's there.
14101 */
77179400 14102 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14103 /* WaIgnoreDDIAStrap: skl */
ef11bdb3 14104 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
0e72a5b5
ED		 14105 intel_ddi_init(dev, PORT_A);
14106
14107 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14108 * register */
14109 found = I915_READ(SFUSE_STRAP);
14110
14111 if (found & SFUSE_STRAP_DDIB_DETECTED)
14112 intel_ddi_init(dev, PORT_B);
14113 if (found & SFUSE_STRAP_DDIC_DETECTED)
14114 intel_ddi_init(dev, PORT_C);
14115 if (found & SFUSE_STRAP_DDID_DETECTED)
14116 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 14117 /*
14118 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14119 */
ef11bdb3 14120 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
2800e4c2
RV		 14121 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14122 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14123 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14124 intel_ddi_init(dev, PORT_E);
14125
0e72a5b5 14126 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14127 int found;
5d8a7752 14128 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14129
14130 if (has_edp_a(dev))
14131 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14132
dc0fa718 14133 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14134 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14135 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14136 if (!found)
e2debe91 14137 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14138 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14139 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14140 }
14141
dc0fa718 14142 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14143 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14144
dc0fa718 14145 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14146 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14147
5eb08b69 14148 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14149 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14150
270b3042 14151 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14152 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14153 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14154 /*
14155 * The DP_DETECTED bit is the latched state of the DDC
14156 * SDA pin at boot. However since eDP doesn't require DDC
14157 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14158 * eDP ports may have been muxed to an alternate function.
14159 * Thus we can't rely on the DP_DETECTED bit alone to detect
14160 * eDP ports. Consult the VBT as well as DP_DETECTED to
14161 * detect eDP ports.
14162 */
e66eb81d 14163 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
d2182a66 14164 !intel_dp_is_edp(dev, PORT_B))
e66eb81d
VS		 14165 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14166 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
e17ac6db 14167 intel_dp_is_edp(dev, PORT_B))
e66eb81d 14168 intel_dp_init(dev, VLV_DP_B, PORT_B);
585a94b8 14169
e66eb81d 14170 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
d2182a66 14171 !intel_dp_is_edp(dev, PORT_C))
e66eb81d
VS		 14172 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14173 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
e17ac6db 14174 intel_dp_is_edp(dev, PORT_C))
e66eb81d 14175 intel_dp_init(dev, VLV_DP_C, PORT_C);
19c03924 14176
9418c1f1 14177 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14178 /* eDP not supported on port D, so don't check VBT */
e66eb81d
VS		 14179 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14180 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14181 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14182 intel_dp_init(dev, CHV_DP_D, PORT_D);
9418c1f1
VS		 14183 }
14184
3cfca973 14185 intel_dsi_init(dev);
09da55dc 14186 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14187 bool found = false;
7d57382e 14188
e2debe91 14189 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14190 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14191 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14192 if (!found && IS_G4X(dev)) {
b01f2c3a 14193 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14194 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14195 }
27185ae1 14196
3fec3d2f 14197 if (!found && IS_G4X(dev))
ab9d7c30 14198 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14199 }
13520b05
KH		 14200
14201 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14202
e2debe91 14203 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14204 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14205 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14206 }
27185ae1 14207
e2debe91 14208 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14209
3fec3d2f 14210 if (IS_G4X(dev)) {
b01f2c3a 14211 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14212 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14213 }
3fec3d2f 14214 if (IS_G4X(dev))
ab9d7c30 14215 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14216 }
27185ae1 14217
3fec3d2f 14218 if (IS_G4X(dev) &&
e7281eab 14219 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14220 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14221 } else if (IS_GEN2(dev))
79e53945
JB		 14222 intel_dvo_init(dev);
14223
103a196f 14224 if (SUPPORTS_TV(dev))
79e53945
JB		 14225 intel_tv_init(dev);
14226
0bc12bcb 14227 intel_psr_init(dev);
7c8f8a70 14228
b2784e15 14229 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14230 encoder->base.possible_crtcs = encoder->crtc_mask;
14231 encoder->base.possible_clones =
66a9278e 14232 intel_encoder_clones(encoder);
79e53945 14233 }
47356eb6 14234
dde86e2d 14235 intel_init_pch_refclk(dev);
270b3042
DV		 14236
14237 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14238}
14239
14240static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14241{
60a5ca01 14242 struct drm_device *dev = fb->dev;
79e53945 14243 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14244
ef2d633e 14245 drm_framebuffer_cleanup(fb);
60a5ca01 14246 mutex_lock(&dev->struct_mutex);
ef2d633e 14247 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14248 drm_gem_object_unreference(&intel_fb->obj->base);
14249 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14250 kfree(intel_fb);
14251}
14252
14253static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14254 struct drm_file *file,
79e53945
JB		 14255 unsigned int *handle)
14256{
14257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14258 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14259
05394f39 14260 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14261}
14262
86c98588
RV		 14263static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14264 struct drm_file *file,
14265 unsigned flags, unsigned color,
14266 struct drm_clip_rect *clips,
14267 unsigned num_clips)
14268{
14269 struct drm_device *dev = fb->dev;
14270 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14271 struct drm_i915_gem_object *obj = intel_fb->obj;
14272
14273 mutex_lock(&dev->struct_mutex);
74b4ea1e 14274 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14275 mutex_unlock(&dev->struct_mutex);
14276
14277 return 0;
14278}
14279
79e53945
JB		 14280static const struct drm_framebuffer_funcs intel_fb_funcs = {
14281 .destroy = intel_user_framebuffer_destroy,
14282 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14283 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14284};
14285
b321803d
DL		 14286static
14287u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14288 uint32_t pixel_format)
14289{
14290 u32 gen = INTEL_INFO(dev)->gen;
14291
14292 if (gen >= 9) {
14293 /* "The stride in bytes must not exceed the of the size of 8K
14294 * pixels and 32K bytes."
14295 */
14296 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14297 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14298 return 32*1024;
14299 } else if (gen >= 4) {
14300 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14301 return 16*1024;
14302 else
14303 return 32*1024;
14304 } else if (gen >= 3) {
14305 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14306 return 8*1024;
14307 else
14308 return 16*1024;
14309 } else {
14310 /* XXX DSPC is limited to 4k tiled */
14311 return 8*1024;
14312 }
14313}
14314
b5ea642a
DV		 14315static int intel_framebuffer_init(struct drm_device *dev,
14316 struct intel_framebuffer *intel_fb,
14317 struct drm_mode_fb_cmd2 *mode_cmd,
14318 struct drm_i915_gem_object *obj)
79e53945 14319{
6761dd31 14320 unsigned int aligned_height;
79e53945 14321 int ret;
b321803d 14322 u32 pitch_limit, stride_alignment;
79e53945 14323
dd4916c5
DV		 14324 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14325
2a80eada
DV		 14326 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14327 /* Enforce that fb modifier and tiling mode match, but only for
14328 * X-tiled. This is needed for FBC. */
14329 if (!!(obj->tiling_mode == I915_TILING_X) !=
14330 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14331 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14332 return -EINVAL;
14333 }
14334 } else {
14335 if (obj->tiling_mode == I915_TILING_X)
14336 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14337 else if (obj->tiling_mode == I915_TILING_Y) {
14338 DRM_DEBUG("No Y tiling for legacy addfb\n");
14339 return -EINVAL;
14340 }
14341 }
14342
9a8f0a12
TU		 14343 /* Passed in modifier sanity checking. */
14344 switch (mode_cmd->modifier[0]) {
14345 case I915_FORMAT_MOD_Y_TILED:
14346 case I915_FORMAT_MOD_Yf_TILED:
14347 if (INTEL_INFO(dev)->gen < 9) {
14348 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14349 mode_cmd->modifier[0]);
14350 return -EINVAL;
14351 }
14352 case DRM_FORMAT_MOD_NONE:
14353 case I915_FORMAT_MOD_X_TILED:
14354 break;
14355 default:
c0f40428
JB		 14356 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14357 mode_cmd->modifier[0]);
57cd6508 14358 return -EINVAL;
c16ed4be 14359 }
57cd6508 14360
b321803d
DL		 14361 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14362 mode_cmd->pixel_format);
14363 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14364 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14365 mode_cmd->pitches[0], stride_alignment);
57cd6508 14366 return -EINVAL;
c16ed4be 14367 }
57cd6508 14368
b321803d
DL		 14369 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14370 mode_cmd->pixel_format);
a35cdaa0 14371 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14372 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14373 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14374 "tiled" : "linear",
a35cdaa0 14375 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14376 return -EINVAL;
c16ed4be 14377 }
5d7bd705 14378
2a80eada 14379 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14380 mode_cmd->pitches[0] != obj->stride) {
14381 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14382 mode_cmd->pitches[0], obj->stride);
5d7bd705 14383 return -EINVAL;
c16ed4be 14384 }
5d7bd705 14385
57779d06 14386 /* Reject formats not supported by any plane early. */
308e5bcb 14387 switch (mode_cmd->pixel_format) {
57779d06 14388 case DRM_FORMAT_C8:
04b3924d
VS		 14389 case DRM_FORMAT_RGB565:
14390 case DRM_FORMAT_XRGB8888:
14391 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14392 break;
14393 case DRM_FORMAT_XRGB1555:
c16ed4be 14394 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14395 DRM_DEBUG("unsupported pixel format: %s\n",
14396 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14397 return -EINVAL;
c16ed4be 14398 }
57779d06 14399 break;
57779d06 14400 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14401 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14402 DRM_DEBUG("unsupported pixel format: %s\n",
14403 drm_get_format_name(mode_cmd->pixel_format));
14404 return -EINVAL;
14405 }
14406 break;
14407 case DRM_FORMAT_XBGR8888:
04b3924d 14408 case DRM_FORMAT_XRGB2101010:
57779d06 14409 case DRM_FORMAT_XBGR2101010:
c16ed4be 14410 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14411 DRM_DEBUG("unsupported pixel format: %s\n",
14412 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14413 return -EINVAL;
c16ed4be 14414 }
b5626747 14415 break;
7531208b
DL		 14416 case DRM_FORMAT_ABGR2101010:
14417 if (!IS_VALLEYVIEW(dev)) {
14418 DRM_DEBUG("unsupported pixel format: %s\n",
14419 drm_get_format_name(mode_cmd->pixel_format));
14420 return -EINVAL;
14421 }
14422 break;
04b3924d
VS		 14423 case DRM_FORMAT_YUYV:
14424 case DRM_FORMAT_UYVY:
14425 case DRM_FORMAT_YVYU:
14426 case DRM_FORMAT_VYUY:
c16ed4be 14427 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14428 DRM_DEBUG("unsupported pixel format: %s\n",
14429 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14430 return -EINVAL;
c16ed4be 14431 }
57cd6508
CW		 14432 break;
14433 default:
4ee62c76
VS		 14434 DRM_DEBUG("unsupported pixel format: %s\n",
14435 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14436 return -EINVAL;
14437 }
14438
90f9a336
VS		 14439 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14440 if (mode_cmd->offsets[0] != 0)
14441 return -EINVAL;
14442
ec2c981e 14443 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14444 mode_cmd->pixel_format,
14445 mode_cmd->modifier[0]);
53155c0a
DV		 14446 /* FIXME drm helper for size checks (especially planar formats)? */
14447 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14448 return -EINVAL;
14449
c7d73f6a
DV		 14450 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14451 intel_fb->obj = obj;
80075d49 14452 intel_fb->obj->framebuffer_references++;
c7d73f6a 14453
79e53945
JB		 14454 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14455 if (ret) {
14456 DRM_ERROR("framebuffer init failed %d\n", ret);
14457 return ret;
14458 }
14459
79e53945
JB		 14460 return 0;
14461}
14462
79e53945
JB		 14463static struct drm_framebuffer *
14464intel_user_framebuffer_create(struct drm_device *dev,
14465 struct drm_file *filp,
308e5bcb 14466 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14467{
05394f39 14468 struct drm_i915_gem_object *obj;
79e53945 14469
308e5bcb
JB		 14470 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14471 mode_cmd->handles[0]));
c8725226 14472 if (&obj->base == NULL)
cce13ff7 14473 return ERR_PTR(-ENOENT);
79e53945 14474
d2dff872 14475 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14476}
14477
0695726e 14478#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14479static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14480{
14481}
14482#endif
14483
79e53945 14484static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14485 .fb_create = intel_user_framebuffer_create,
0632fef6 14486 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14487 .atomic_check = intel_atomic_check,
14488 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14489 .atomic_state_alloc = intel_atomic_state_alloc,
14490 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14491};
14492
e70236a8
JB		 14493/* Set up chip specific display functions */
14494static void intel_init_display(struct drm_device *dev)
14495{
14496 struct drm_i915_private *dev_priv = dev->dev_private;
14497
ee9300bb
DV		 14498 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14499 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14500 else if (IS_CHERRYVIEW(dev))
14501 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14502 else if (IS_VALLEYVIEW(dev))
14503 dev_priv->display.find_dpll = vlv_find_best_dpll;
14504 else if (IS_PINEVIEW(dev))
14505 dev_priv->display.find_dpll = pnv_find_best_dpll;
14506 else
14507 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14508
bc8d7dff
DL		 14509 if (INTEL_INFO(dev)->gen >= 9) {
14510 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14511 dev_priv->display.get_initial_plane_config =
14512 skylake_get_initial_plane_config;
bc8d7dff
DL		 14513 dev_priv->display.crtc_compute_clock =
14514 haswell_crtc_compute_clock;
14515 dev_priv->display.crtc_enable = haswell_crtc_enable;
14516 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14517 dev_priv->display.update_primary_plane =
14518 skylake_update_primary_plane;
14519 } else if (HAS_DDI(dev)) {
0e8ffe1b 14520 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14521 dev_priv->display.get_initial_plane_config =
14522 ironlake_get_initial_plane_config;
797d0259
ACO		 14523 dev_priv->display.crtc_compute_clock =
14524 haswell_crtc_compute_clock;
4f771f10
PZ		 14525 dev_priv->display.crtc_enable = haswell_crtc_enable;
14526 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14527 dev_priv->display.update_primary_plane =
14528 ironlake_update_primary_plane;
09b4ddf9 14529 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14530 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14531 dev_priv->display.get_initial_plane_config =
14532 ironlake_get_initial_plane_config;
3fb37703
ACO		 14533 dev_priv->display.crtc_compute_clock =
14534 ironlake_crtc_compute_clock;
76e5a89c
DV		 14535 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14536 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14537 dev_priv->display.update_primary_plane =
14538 ironlake_update_primary_plane;
89b667f8
JB		 14539 } else if (IS_VALLEYVIEW(dev)) {
14540 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14541 dev_priv->display.get_initial_plane_config =
14542 i9xx_get_initial_plane_config;
d6dfee7a 14543 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14544 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14545 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14546 dev_priv->display.update_primary_plane =
14547 i9xx_update_primary_plane;
f564048e 14548 } else {
0e8ffe1b 14549 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14550 dev_priv->display.get_initial_plane_config =
14551 i9xx_get_initial_plane_config;
d6dfee7a 14552 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14553 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14554 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14555 dev_priv->display.update_primary_plane =
14556 i9xx_update_primary_plane;
f564048e 14557 }
e70236a8 14558
e70236a8 14559 /* Returns the core display clock speed */
ef11bdb3 14560 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
1652d19e
VS		 14561 dev_priv->display.get_display_clock_speed =
14562 skylake_get_display_clock_speed;
acd3f3d3
BP		 14563 else if (IS_BROXTON(dev))
14564 dev_priv->display.get_display_clock_speed =
14565 broxton_get_display_clock_speed;
1652d19e
VS		 14566 else if (IS_BROADWELL(dev))
14567 dev_priv->display.get_display_clock_speed =
14568 broadwell_get_display_clock_speed;
14569 else if (IS_HASWELL(dev))
14570 dev_priv->display.get_display_clock_speed =
14571 haswell_get_display_clock_speed;
14572 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14573 dev_priv->display.get_display_clock_speed =
14574 valleyview_get_display_clock_speed;
b37a6434
VS		 14575 else if (IS_GEN5(dev))
14576 dev_priv->display.get_display_clock_speed =
14577 ilk_get_display_clock_speed;
a7c66cd8 14578 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14579 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14580 dev_priv->display.get_display_clock_speed =
14581 i945_get_display_clock_speed;
34edce2f
VS		 14582 else if (IS_GM45(dev))
14583 dev_priv->display.get_display_clock_speed =
14584 gm45_get_display_clock_speed;
14585 else if (IS_CRESTLINE(dev))
14586 dev_priv->display.get_display_clock_speed =
14587 i965gm_get_display_clock_speed;
14588 else if (IS_PINEVIEW(dev))
14589 dev_priv->display.get_display_clock_speed =
14590 pnv_get_display_clock_speed;
14591 else if (IS_G33(dev) || IS_G4X(dev))
14592 dev_priv->display.get_display_clock_speed =
14593 g33_get_display_clock_speed;
e70236a8
JB		 14594 else if (IS_I915G(dev))
14595 dev_priv->display.get_display_clock_speed =
14596 i915_get_display_clock_speed;
257a7ffc 14597 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14598 dev_priv->display.get_display_clock_speed =
14599 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14600 else if (IS_PINEVIEW(dev))
14601 dev_priv->display.get_display_clock_speed =
14602 pnv_get_display_clock_speed;
e70236a8
JB		 14603 else if (IS_I915GM(dev))
14604 dev_priv->display.get_display_clock_speed =
14605 i915gm_get_display_clock_speed;
14606 else if (IS_I865G(dev))
14607 dev_priv->display.get_display_clock_speed =
14608 i865_get_display_clock_speed;
f0f8a9ce 14609 else if (IS_I85X(dev))
e70236a8 14610 dev_priv->display.get_display_clock_speed =
1b1d2716 14611 i85x_get_display_clock_speed;
623e01e5
VS		 14612 else { /* 830 */
14613 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14614 dev_priv->display.get_display_clock_speed =
14615 i830_get_display_clock_speed;
623e01e5 14616 }
e70236a8 14617
7c10a2b5 14618 if (IS_GEN5(dev)) {
3bb11b53 14619 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14620 } else if (IS_GEN6(dev)) {
14621 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14622 } else if (IS_IVYBRIDGE(dev)) {
14623 /* FIXME: detect B0+ stepping and use auto training */
14624 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14625 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14626 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14627 if (IS_BROADWELL(dev)) {
14628 dev_priv->display.modeset_commit_cdclk =
14629 broadwell_modeset_commit_cdclk;
14630 dev_priv->display.modeset_calc_cdclk =
14631 broadwell_modeset_calc_cdclk;
14632 }
30a970c6 14633 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14634 dev_priv->display.modeset_commit_cdclk =
14635 valleyview_modeset_commit_cdclk;
14636 dev_priv->display.modeset_calc_cdclk =
14637 valleyview_modeset_calc_cdclk;
f8437dd1 14638 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14639 dev_priv->display.modeset_commit_cdclk =
14640 broxton_modeset_commit_cdclk;
14641 dev_priv->display.modeset_calc_cdclk =
14642 broxton_modeset_calc_cdclk;
e70236a8 14643 }
8c9f3aaf 14644
8c9f3aaf
JB		 14645 switch (INTEL_INFO(dev)->gen) {
14646 case 2:
14647 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14648 break;
14649
14650 case 3:
14651 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14652 break;
14653
14654 case 4:
14655 case 5:
14656 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14657 break;
14658
14659 case 6:
14660 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14661 break;
7c9017e5 14662 case 7:
4e0bbc31 14663 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14664 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14665 break;
830c81db 14666 case 9:
ba343e02
TU		 14667 /* Drop through - unsupported since execlist only. */
14668 default:
14669 /* Default just returns -ENODEV to indicate unsupported */
14670 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14671 }
7bd688cd 14672
e39b999a 14673 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14674}
14675
b690e96c
JB		 14676/*
14677 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14678 * resume, or other times. This quirk makes sure that's the case for
14679 * affected systems.
14680 */
0206e353 14681static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14682{
14683 struct drm_i915_private *dev_priv = dev->dev_private;
14684
14685 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14686 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14687}
14688
b6b5d049
VS		 14689static void quirk_pipeb_force(struct drm_device *dev)
14690{
14691 struct drm_i915_private *dev_priv = dev->dev_private;
14692
14693 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14694 DRM_INFO("applying pipe b force quirk\n");
14695}
14696
435793df
KP		 14697/*
14698 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14699 */
14700static void quirk_ssc_force_disable(struct drm_device *dev)
14701{
14702 struct drm_i915_private *dev_priv = dev->dev_private;
14703 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14704 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14705}
14706
4dca20ef 14707/*
5a15ab5b
CE		 14708 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14709 * brightness value
4dca20ef
CE		 14710 */
14711static void quirk_invert_brightness(struct drm_device *dev)
14712{
14713 struct drm_i915_private *dev_priv = dev->dev_private;
14714 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14715 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14716}
14717
9c72cc6f
SD		 14718/* Some VBT's incorrectly indicate no backlight is present */
14719static void quirk_backlight_present(struct drm_device *dev)
14720{
14721 struct drm_i915_private *dev_priv = dev->dev_private;
14722 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14723 DRM_INFO("applying backlight present quirk\n");
14724}
14725
b690e96c
JB		 14726struct intel_quirk {
14727 int device;
14728 int subsystem_vendor;
14729 int subsystem_device;
14730 void (*hook)(struct drm_device *dev);
14731};
14732
5f85f176
EE		 14733/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14734struct intel_dmi_quirk {
14735 void (*hook)(struct drm_device *dev);
14736 const struct dmi_system_id (*dmi_id_list)[];
14737};
14738
14739static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14740{
14741 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14742 return 1;
14743}
14744
14745static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14746 {
14747 .dmi_id_list = &(const struct dmi_system_id[]) {
14748 {
14749 .callback = intel_dmi_reverse_brightness,
14750 .ident = "NCR Corporation",
14751 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14752 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14753 },
14754 },
14755 { } /* terminating entry */
14756 },
14757 .hook = quirk_invert_brightness,
14758 },
14759};
14760
c43b5634 14761static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14762 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14763 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14764
b690e96c
JB		 14765 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14766 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14767
5f080c0f
VS		 14768 /* 830 needs to leave pipe A & dpll A up */
14769 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14770
b6b5d049
VS		 14771 /* 830 needs to leave pipe B & dpll B up */
14772 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14773
435793df
KP		 14774 /* Lenovo U160 cannot use SSC on LVDS */
14775 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14776
14777 /* Sony Vaio Y cannot use SSC on LVDS */
14778 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14779
be505f64
AH		 14780 /* Acer Aspire 5734Z must invert backlight brightness */
14781 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14782
14783 /* Acer/eMachines G725 */
14784 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14785
14786 /* Acer/eMachines e725 */
14787 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14788
14789 /* Acer/Packard Bell NCL20 */
14790 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14791
14792 /* Acer Aspire 4736Z */
14793 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14794
14795 /* Acer Aspire 5336 */
14796 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14797
14798 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14799 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14800
dfb3d47b
SD		 14801 /* Acer C720 Chromebook (Core i3 4005U) */
14802 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14803
b2a9601c 14804 /* Apple Macbook 2,1 (Core 2 T7400) */
14805 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14806
d4967d8c
SD		 14807 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14808 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14809
14810 /* HP Chromebook 14 (Celeron 2955U) */
14811 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14812
14813 /* Dell Chromebook 11 */
14814 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14815};
14816
14817static void intel_init_quirks(struct drm_device *dev)
14818{
14819 struct pci_dev *d = dev->pdev;
14820 int i;
14821
14822 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14823 struct intel_quirk *q = &intel_quirks[i];
14824
14825 if (d->device == q->device &&
14826 (d->subsystem_vendor == q->subsystem_vendor ||
14827 q->subsystem_vendor == PCI_ANY_ID) &&
14828 (d->subsystem_device == q->subsystem_device ||
14829 q->subsystem_device == PCI_ANY_ID))
14830 q->hook(dev);
14831 }
5f85f176
EE		 14832 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14833 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14834 intel_dmi_quirks[i].hook(dev);
14835 }
b690e96c
JB		 14836}
14837
9cce37f4
JB		 14838/* Disable the VGA plane that we never use */
14839static void i915_disable_vga(struct drm_device *dev)
14840{
14841 struct drm_i915_private *dev_priv = dev->dev_private;
14842 u8 sr1;
766aa1c4 14843 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14844
2b37c616 14845 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14846 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14847 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14848 sr1 = inb(VGA_SR_DATA);
14849 outb(sr1 | 1<<5, VGA_SR_DATA);
14850 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14851 udelay(300);
14852
01f5a626 14853 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14854 POSTING_READ(vga_reg);
14855}
14856
f817586c
DV		 14857void intel_modeset_init_hw(struct drm_device *dev)
14858{
b6283055 14859 intel_update_cdclk(dev);
a8f78b58 14860 intel_prepare_ddi(dev);
f817586c 14861 intel_init_clock_gating(dev);
8090c6b9 14862 intel_enable_gt_powersave(dev);
f817586c
DV		 14863}
14864
79e53945
JB		 14865void intel_modeset_init(struct drm_device *dev)
14866{
652c393a 14867 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14868 int sprite, ret;
8cc87b75 14869 enum pipe pipe;
46f297fb 14870 struct intel_crtc *crtc;
79e53945
JB		 14871
14872 drm_mode_config_init(dev);
14873
14874 dev->mode_config.min_width = 0;
14875 dev->mode_config.min_height = 0;
14876
019d96cb
DA		 14877 dev->mode_config.preferred_depth = 24;
14878 dev->mode_config.prefer_shadow = 1;
14879
25bab385
TU		 14880 dev->mode_config.allow_fb_modifiers = true;
14881
e6ecefaa 14882 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14883
b690e96c
JB		 14884 intel_init_quirks(dev);
14885
1fa61106
ED		 14886 intel_init_pm(dev);
14887
e3c74757
BW		 14888 if (INTEL_INFO(dev)->num_pipes == 0)
14889 return;
14890
69f92f67
LW		 14891 /*
14892 * There may be no VBT; and if the BIOS enabled SSC we can
14893 * just keep using it to avoid unnecessary flicker. Whereas if the
14894 * BIOS isn't using it, don't assume it will work even if the VBT
14895 * indicates as much.
14896 */
14897 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14898 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14899 DREF_SSC1_ENABLE);
14900
14901 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14902 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14903 bios_lvds_use_ssc ? "en" : "dis",
14904 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14905 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14906 }
14907 }
14908
e70236a8 14909 intel_init_display(dev);
7c10a2b5 14910 intel_init_audio(dev);
e70236a8 14911
a6c45cf0
CW		 14912 if (IS_GEN2(dev)) {
14913 dev->mode_config.max_width = 2048;
14914 dev->mode_config.max_height = 2048;
14915 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14916 dev->mode_config.max_width = 4096;
14917 dev->mode_config.max_height = 4096;
79e53945 14918 } else {
a6c45cf0
CW		 14919 dev->mode_config.max_width = 8192;
14920 dev->mode_config.max_height = 8192;
79e53945 14921 }
068be561 14922
dc41c154
VS		 14923 if (IS_845G(dev) || IS_I865G(dev)) {
14924 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14925 dev->mode_config.cursor_height = 1023;
14926 } else if (IS_GEN2(dev)) {
068be561
DL		 14927 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14928 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14929 } else {
14930 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14931 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14932 }
14933
5d4545ae 14934 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14935
28c97730 14936 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14937 INTEL_INFO(dev)->num_pipes,
14938 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14939
055e393f 14940 for_each_pipe(dev_priv, pipe) {
8cc87b75 14941 intel_crtc_init(dev, pipe);
3bdcfc0c 14942 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14943 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14944 if (ret)
06da8da2 14945 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14946 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14947 }
79e53945
JB		 14948 }
14949
bfa7df01
VS		 14950 intel_update_czclk(dev_priv);
14951 intel_update_cdclk(dev);
14952
e72f9fbf 14953 intel_shared_dpll_init(dev);
ee7b9f93 14954
9cce37f4
JB		 14955 /* Just disable it once at startup */
14956 i915_disable_vga(dev);
79e53945 14957 intel_setup_outputs(dev);
11be49eb
CW		 14958
14959 /* Just in case the BIOS is doing something questionable. */
7733b49b 14960 intel_fbc_disable(dev_priv);
fa9fa083 14961
6e9f798d 14962 drm_modeset_lock_all(dev);
043e9bda 14963 intel_modeset_setup_hw_state(dev);
6e9f798d 14964 drm_modeset_unlock_all(dev);
46f297fb 14965
d3fcc808 14966 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14967 struct intel_initial_plane_config plane_config = {};
14968
46f297fb
JB		 14969 if (!crtc->active)
14970 continue;
14971
46f297fb 14972 /*
46f297fb
JB		 14973 * Note that reserving the BIOS fb up front prevents us
14974 * from stuffing other stolen allocations like the ring
14975 * on top. This prevents some ugliness at boot time, and
14976 * can even allow for smooth boot transitions if the BIOS
14977 * fb is large enough for the active pipe configuration.
14978 */
eeebeac5
ML		 14979 dev_priv->display.get_initial_plane_config(crtc,
14980 &plane_config);
14981
14982 /*
14983 * If the fb is shared between multiple heads, we'll
14984 * just get the first one.
14985 */
14986 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14987 }
2c7111db
CW		 14988}
14989
7fad798e
DV		 14990static void intel_enable_pipe_a(struct drm_device *dev)
14991{
14992 struct intel_connector *connector;
14993 struct drm_connector *crt = NULL;
14994 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14995 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14996
14997 /* We can't just switch on the pipe A, we need to set things up with a
14998 * proper mode and output configuration. As a gross hack, enable pipe A
14999 * by enabling the load detect pipe once. */
3a3371ff 15000 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15001 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15002 crt = &connector->base;
15003 break;
15004 }
15005 }
15006
15007 if (!crt)
15008 return;
15009
208bf9fd 15010 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15011 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15012}
15013
fa555837
DV		 15014static bool
15015intel_check_plane_mapping(struct intel_crtc *crtc)
15016{
7eb552ae
BW		 15017 struct drm_device *dev = crtc->base.dev;
15018 struct drm_i915_private *dev_priv = dev->dev_private;
649636ef 15019 u32 val;
fa555837 15020
7eb552ae 15021 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15022 return true;
15023
649636ef 15024 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV		 15025
15026 if ((val & DISPLAY_PLANE_ENABLE) &&
15027 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15028 return false;
15029
15030 return true;
15031}
15032
02e93c35
VS		 15033static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15034{
15035 struct drm_device *dev = crtc->base.dev;
15036 struct intel_encoder *encoder;
15037
15038 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15039 return true;
15040
15041 return false;
15042}
15043
24929352
DV		 15044static void intel_sanitize_crtc(struct intel_crtc *crtc)
15045{
15046 struct drm_device *dev = crtc->base.dev;
15047 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15048 u32 reg;
24929352 15049
24929352 15050 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15051 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15052 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15053
d3eaf884 15054 /* restore vblank interrupts to correct state */
9625604c 15055 drm_crtc_vblank_reset(&crtc->base);
d297e103 15056 if (crtc->active) {
f9cd7b88
VS		 15057 struct intel_plane *plane;
15058
9625604c 15059 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS		 15060
15061 /* Disable everything but the primary plane */
15062 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15063 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15064 continue;
15065
15066 plane->disable_plane(&plane->base, &crtc->base);
15067 }
9625604c 15068 }
d3eaf884 15069
24929352 15070 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15071 * disable the crtc (and hence change the state) if it is wrong. Note
15072 * that gen4+ has a fixed plane -> pipe mapping. */
15073 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15074 bool plane;
15075
24929352
DV		 15076 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15077 crtc->base.base.id);
15078
15079 /* Pipe has the wrong plane attached and the plane is active.
15080 * Temporarily change the plane mapping and disable everything
15081 * ... */
15082 plane = crtc->plane;
b70709a6 15083 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15084 crtc->plane = !plane;
b17d48e2 15085 intel_crtc_disable_noatomic(&crtc->base);
24929352 15086 crtc->plane = plane;
24929352 15087 }
24929352 15088
7fad798e
DV		 15089 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15090 crtc->pipe == PIPE_A && !crtc->active) {
15091 /* BIOS forgot to enable pipe A, this mostly happens after
15092 * resume. Force-enable the pipe to fix this, the update_dpms
15093 * call below we restore the pipe to the right state, but leave
15094 * the required bits on. */
15095 intel_enable_pipe_a(dev);
15096 }
15097
24929352
DV		 15098 /* Adjust the state of the output pipe according to whether we
15099 * have active connectors/encoders. */
02e93c35 15100 if (!intel_crtc_has_encoders(crtc))
b17d48e2 15101 intel_crtc_disable_noatomic(&crtc->base);
24929352 15102
53d9f4e9 15103 if (crtc->active != crtc->base.state->active) {
02e93c35 15104 struct intel_encoder *encoder;
24929352
DV		 15105
15106 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15107 * functions or because of calls to intel_crtc_disable_noatomic,
15108 * or because the pipe is force-enabled due to the
24929352
DV		 15109 * pipe A quirk. */
15110 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15111 crtc->base.base.id,
83d65738 15112 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15113 crtc->active ? "enabled" : "disabled");
15114
4be40c98 15115 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15116 crtc->base.state->active = crtc->active;
24929352
DV		 15117 crtc->base.enabled = crtc->active;
15118
15119 /* Because we only establish the connector -> encoder ->
15120 * crtc links if something is active, this means the
15121 * crtc is now deactivated. Break the links. connector
15122 * -> encoder links are only establish when things are
15123 * actually up, hence no need to break them. */
15124 WARN_ON(crtc->active);
15125
2d406bb0 15126 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 15127 encoder->base.crtc = NULL;
24929352 15128 }
c5ab3bc0 15129
a3ed6aad 15130 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15131 /*
15132 * We start out with underrun reporting disabled to avoid races.
15133 * For correct bookkeeping mark this on active crtcs.
15134 *
c5ab3bc0
DV		 15135 * Also on gmch platforms we dont have any hardware bits to
15136 * disable the underrun reporting. Which means we need to start
15137 * out with underrun reporting disabled also on inactive pipes,
15138 * since otherwise we'll complain about the garbage we read when
15139 * e.g. coming up after runtime pm.
15140 *
4cc31489
DV		 15141 * No protection against concurrent access is required - at
15142 * worst a fifo underrun happens which also sets this to false.
15143 */
15144 crtc->cpu_fifo_underrun_disabled = true;
15145 crtc->pch_fifo_underrun_disabled = true;
15146 }
24929352
DV		 15147}
15148
15149static void intel_sanitize_encoder(struct intel_encoder *encoder)
15150{
15151 struct intel_connector *connector;
15152 struct drm_device *dev = encoder->base.dev;
873ffe69 15153 bool active = false;
24929352
DV		 15154
15155 /* We need to check both for a crtc link (meaning that the
15156 * encoder is active and trying to read from a pipe) and the
15157 * pipe itself being active. */
15158 bool has_active_crtc = encoder->base.crtc &&
15159 to_intel_crtc(encoder->base.crtc)->active;
15160
873ffe69
ML		 15161 for_each_intel_connector(dev, connector) {
15162 if (connector->base.encoder != &encoder->base)
15163 continue;
15164
15165 active = true;
15166 break;
15167 }
15168
15169 if (active && !has_active_crtc) {
24929352
DV		 15170 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15171 encoder->base.base.id,
8e329a03 15172 encoder->base.name);
24929352
DV		 15173
15174 /* Connector is active, but has no active pipe. This is
15175 * fallout from our resume register restoring. Disable
15176 * the encoder manually again. */
15177 if (encoder->base.crtc) {
15178 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15179 encoder->base.base.id,
8e329a03 15180 encoder->base.name);
24929352 15181 encoder->disable(encoder);
a62d1497
VS		 15182 if (encoder->post_disable)
15183 encoder->post_disable(encoder);
24929352 15184 }
7f1950fb 15185 encoder->base.crtc = NULL;
24929352
DV		 15186
15187 /* Inconsistent output/port/pipe state happens presumably due to
15188 * a bug in one of the get_hw_state functions. Or someplace else
15189 * in our code, like the register restore mess on resume. Clamp
15190 * things to off as a safer default. */
3a3371ff 15191 for_each_intel_connector(dev, connector) {
24929352
DV		 15192 if (connector->encoder != encoder)
15193 continue;
7f1950fb
EE		 15194 connector->base.dpms = DRM_MODE_DPMS_OFF;
15195 connector->base.encoder = NULL;
24929352
DV		 15196 }
15197 }
15198 /* Enabled encoders without active connectors will be fixed in
15199 * the crtc fixup. */
15200}
15201
04098753 15202void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15203{
15204 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15205 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15206
04098753
ID		 15207 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15208 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15209 i915_disable_vga(dev);
15210 }
15211}
15212
15213void i915_redisable_vga(struct drm_device *dev)
15214{
15215 struct drm_i915_private *dev_priv = dev->dev_private;
15216
8dc8a27c
PZ		 15217 /* This function can be called both from intel_modeset_setup_hw_state or
15218 * at a very early point in our resume sequence, where the power well
15219 * structures are not yet restored. Since this function is at a very
15220 * paranoid "someone might have enabled VGA while we were not looking"
15221 * level, just check if the power well is enabled instead of trying to
15222 * follow the "don't touch the power well if we don't need it" policy
15223 * the rest of the driver uses. */
f458ebbc 15224 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15225 return;
15226
04098753 15227 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15228}
15229
f9cd7b88 15230static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15231{
f9cd7b88 15232 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15233
f9cd7b88 15234 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML		 15235}
15236
f9cd7b88
VS		 15237/* FIXME read out full plane state for all planes */
15238static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15239{
b26d3ea3 15240 struct drm_plane *primary = crtc->base.primary;
f9cd7b88 15241 struct intel_plane_state *plane_state =
b26d3ea3 15242 to_intel_plane_state(primary->state);
d032ffa0 15243
19b8d387 15244 plane_state->visible = crtc->active &&
b26d3ea3
ML		 15245 primary_get_hw_state(to_intel_plane(primary));
15246
15247 if (plane_state->visible)
15248 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
98ec7739
VS		 15249}
15250
30e984df 15251static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15252{
15253 struct drm_i915_private *dev_priv = dev->dev_private;
15254 enum pipe pipe;
24929352
DV		 15255 struct intel_crtc *crtc;
15256 struct intel_encoder *encoder;
15257 struct intel_connector *connector;
5358901f 15258 int i;
24929352 15259
d3fcc808 15260 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15261 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15262 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15263 crtc->config->base.crtc = &crtc->base;
3b117c8f 15264
0e8ffe1b 15265 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15266 crtc->config);
24929352 15267
49d6fa21 15268 crtc->base.state->active = crtc->active;
24929352 15269 crtc->base.enabled = crtc->active;
b70709a6 15270
f9cd7b88 15271 readout_plane_state(crtc);
24929352
DV		 15272
15273 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15274 crtc->base.base.id,
15275 crtc->active ? "enabled" : "disabled");
15276 }
15277
5358901f
DV		 15278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15279 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15280
3e369b76
ACO		 15281 pll->on = pll->get_hw_state(dev_priv, pll,
15282 &pll->config.hw_state);
5358901f 15283 pll->active = 0;
3e369b76 15284 pll->config.crtc_mask = 0;
d3fcc808 15285 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15286 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15287 pll->active++;
3e369b76 15288 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15289 }
5358901f 15290 }
5358901f 15291
1e6f2ddc 15292 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15293 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15294
3e369b76 15295 if (pll->config.crtc_mask)
bd2bb1b9 15296 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15297 }
15298
b2784e15 15299 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15300 pipe = 0;
15301
15302 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15303 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15304 encoder->base.crtc = &crtc->base;
6e3c9717 15305 encoder->get_config(encoder, crtc->config);
24929352
DV		 15306 } else {
15307 encoder->base.crtc = NULL;
15308 }
15309
6f2bcceb 15310 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15311 encoder->base.base.id,
8e329a03 15312 encoder->base.name,
24929352 15313 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15314 pipe_name(pipe));
24929352
DV		 15315 }
15316
3a3371ff 15317 for_each_intel_connector(dev, connector) {
24929352
DV		 15318 if (connector->get_hw_state(connector)) {
15319 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15320 connector->base.encoder = &connector->encoder->base;
15321 } else {
15322 connector->base.dpms = DRM_MODE_DPMS_OFF;
15323 connector->base.encoder = NULL;
15324 }
15325 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15326 connector->base.base.id,
c23cc417 15327 connector->base.name,
24929352
DV		 15328 connector->base.encoder ? "enabled" : "disabled");
15329 }
7f4c6284
VS		 15330
15331 for_each_intel_crtc(dev, crtc) {
15332 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15333
15334 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15335 if (crtc->base.state->active) {
15336 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15337 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15338 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15339
15340 /*
15341 * The initial mode needs to be set in order to keep
15342 * the atomic core happy. It wants a valid mode if the
15343 * crtc's enabled, so we do the above call.
15344 *
15345 * At this point some state updated by the connectors
15346 * in their ->detect() callback has not run yet, so
15347 * no recalculation can be done yet.
15348 *
15349 * Even if we could do a recalculation and modeset
15350 * right now it would cause a double modeset if
15351 * fbdev or userspace chooses a different initial mode.
15352 *
15353 * If that happens, someone indicated they wanted a
15354 * mode change, which means it's safe to do a full
15355 * recalculation.
15356 */
15357 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832
VS		 15358
15359 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15360 update_scanline_offset(crtc);
7f4c6284
VS		 15361 }
15362 }
30e984df
DV		 15363}
15364
043e9bda
ML		 15365/* Scan out the current hw modeset state,
15366 * and sanitizes it to the current state
15367 */
15368static void
15369intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15370{
15371 struct drm_i915_private *dev_priv = dev->dev_private;
15372 enum pipe pipe;
30e984df
DV		 15373 struct intel_crtc *crtc;
15374 struct intel_encoder *encoder;
35c95375 15375 int i;
30e984df
DV		 15376
15377 intel_modeset_readout_hw_state(dev);
24929352
DV		 15378
15379 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15380 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15381 intel_sanitize_encoder(encoder);
15382 }
15383
055e393f 15384 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15385 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15386 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15387 intel_dump_pipe_config(crtc, crtc->config,
15388 "[setup_hw_state]");
24929352 15389 }
9a935856 15390
d29b2f9d
ACO		 15391 intel_modeset_update_connector_atomic_state(dev);
15392
35c95375
DV		 15393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15394 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15395
15396 if (!pll->on || pll->active)
15397 continue;
15398
15399 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15400
15401 pll->disable(dev_priv, pll);
15402 pll->on = false;
15403 }
15404
26e1fe4f 15405 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15406 vlv_wm_get_hw_state(dev);
15407 else if (IS_GEN9(dev))
3078999f
PB		 15408 skl_wm_get_hw_state(dev);
15409 else if (HAS_PCH_SPLIT(dev))
243e6a44 15410 ilk_wm_get_hw_state(dev);
292b990e
ML		 15411
15412 for_each_intel_crtc(dev, crtc) {
15413 unsigned long put_domains;
15414
15415 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15416 if (WARN_ON(put_domains))
15417 modeset_put_power_domains(dev_priv, put_domains);
15418 }
15419 intel_display_set_init_power(dev_priv, false);
043e9bda 15420}
7d0bc1ea 15421
043e9bda
ML		 15422void intel_display_resume(struct drm_device *dev)
15423{
15424 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15425 struct intel_connector *conn;
15426 struct intel_plane *plane;
15427 struct drm_crtc *crtc;
15428 int ret;
f30da187 15429
043e9bda
ML		 15430 if (!state)
15431 return;
15432
15433 state->acquire_ctx = dev->mode_config.acquire_ctx;
15434
15435 /* preserve complete old state, including dpll */
15436 intel_atomic_get_shared_dpll_state(state);
15437
15438 for_each_crtc(dev, crtc) {
15439 struct drm_crtc_state *crtc_state =
15440 drm_atomic_get_crtc_state(state, crtc);
15441
15442 ret = PTR_ERR_OR_ZERO(crtc_state);
15443 if (ret)
15444 goto err;
15445
15446 /* force a restore */
15447 crtc_state->mode_changed = true;
45e2b5f6 15448 }
8af6cf88 15449
043e9bda
ML		 15450 for_each_intel_plane(dev, plane) {
15451 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15452 if (ret)
15453 goto err;
15454 }
15455
15456 for_each_intel_connector(dev, conn) {
15457 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15458 if (ret)
15459 goto err;
15460 }
15461
15462 intel_modeset_setup_hw_state(dev);
15463
15464 i915_redisable_vga(dev);
74c090b1 15465 ret = drm_atomic_commit(state);
043e9bda
ML		 15466 if (!ret)
15467 return;
15468
15469err:
15470 DRM_ERROR("Restoring old state failed with %i\n", ret);
15471 drm_atomic_state_free(state);
2c7111db
CW		 15472}
15473
15474void intel_modeset_gem_init(struct drm_device *dev)
15475{
484b41dd 15476 struct drm_crtc *c;
2ff8fde1 15477 struct drm_i915_gem_object *obj;
e0d6149b 15478 int ret;
484b41dd 15479
ae48434c
ID		 15480 mutex_lock(&dev->struct_mutex);
15481 intel_init_gt_powersave(dev);
15482 mutex_unlock(&dev->struct_mutex);
15483
1833b134 15484 intel_modeset_init_hw(dev);
02e792fb
DV		 15485
15486 intel_setup_overlay(dev);
484b41dd
JB		 15487
15488 /*
15489 * Make sure any fbs we allocated at startup are properly
15490 * pinned & fenced. When we do the allocation it's too early
15491 * for this.
15492 */
70e1e0ec 15493 for_each_crtc(dev, c) {
2ff8fde1
MR		 15494 obj = intel_fb_obj(c->primary->fb);
15495 if (obj == NULL)
484b41dd
JB		 15496 continue;
15497
e0d6149b
TU		 15498 mutex_lock(&dev->struct_mutex);
15499 ret = intel_pin_and_fence_fb_obj(c->primary,
15500 c->primary->fb,
15501 c->primary->state,
91af127f 15502 NULL, NULL);
e0d6149b
TU		 15503 mutex_unlock(&dev->struct_mutex);
15504 if (ret) {
484b41dd
JB		 15505 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15506 to_intel_crtc(c)->pipe);
66e514c1
DA		 15507 drm_framebuffer_unreference(c->primary->fb);
15508 c->primary->fb = NULL;
36750f28 15509 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15510 update_state_fb(c->primary);
36750f28 15511 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15512 }
15513 }
0962c3c9
VS		 15514
15515 intel_backlight_register(dev);
79e53945
JB		 15516}
15517
4932e2c3
ID		 15518void intel_connector_unregister(struct intel_connector *intel_connector)
15519{
15520 struct drm_connector *connector = &intel_connector->base;
15521
15522 intel_panel_destroy_backlight(connector);
34ea3d38 15523 drm_connector_unregister(connector);
4932e2c3
ID		 15524}
15525
79e53945
JB		 15526void intel_modeset_cleanup(struct drm_device *dev)
15527{
652c393a 15528 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15529 struct drm_connector *connector;
652c393a 15530
2eb5252e
ID		 15531 intel_disable_gt_powersave(dev);
15532
0962c3c9
VS		 15533 intel_backlight_unregister(dev);
15534
fd0c0642
DV		 15535 /*
15536 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15537 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15538 * experience fancy races otherwise.
15539 */
2aeb7d3a 15540 intel_irq_uninstall(dev_priv);
eb21b92b 15541
fd0c0642
DV		 15542 /*
15543 * Due to the hpd irq storm handling the hotplug work can re-arm the
15544 * poll handlers. Hence disable polling after hpd handling is shut down.
15545 */
f87ea761 15546 drm_kms_helper_poll_fini(dev);
fd0c0642 15547
723bfd70
JB		 15548 intel_unregister_dsm_handler();
15549
7733b49b 15550 intel_fbc_disable(dev_priv);
69341a5e 15551
1630fe75
CW		 15552 /* flush any delayed tasks or pending work */
15553 flush_scheduled_work();
15554
db31af1d
JN		 15555 /* destroy the backlight and sysfs files before encoders/connectors */
15556 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15557 struct intel_connector *intel_connector;
15558
15559 intel_connector = to_intel_connector(connector);
15560 intel_connector->unregister(intel_connector);
db31af1d 15561 }
d9255d57 15562
79e53945 15563 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15564
15565 intel_cleanup_overlay(dev);
ae48434c
ID		 15566
15567 mutex_lock(&dev->struct_mutex);
15568 intel_cleanup_gt_powersave(dev);
15569 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15570}
15571
f1c79df3
ZW		 15572/*
15573 * Return which encoder is currently attached for connector.
15574 */
df0e9248 15575struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15576{
df0e9248
CW		 15577 return &intel_attached_encoder(connector)->base;
15578}
f1c79df3 15579
df0e9248
CW		 15580void intel_connector_attach_encoder(struct intel_connector *connector,
15581 struct intel_encoder *encoder)
15582{
15583 connector->encoder = encoder;
15584 drm_mode_connector_attach_encoder(&connector->base,
15585 &encoder->base);
79e53945 15586}
28d52043
DA		 15587
15588/*
15589 * set vga decode state - true == enable VGA decode
15590 */
15591int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15592{
15593 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15594 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15595 u16 gmch_ctrl;
15596
75fa041d
CW		 15597 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15598 DRM_ERROR("failed to read control word\n");
15599 return -EIO;
15600 }
15601
c0cc8a55
CW		 15602 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15603 return 0;
15604
28d52043
DA		 15605 if (state)
15606 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15607 else
15608 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15609
15610 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15611 DRM_ERROR("failed to write control word\n");
15612 return -EIO;
15613 }
15614
28d52043
DA		 15615 return 0;
15616}
c4a1d9e4 15617
c4a1d9e4 15618struct intel_display_error_state {
ff57f1b0
PZ		 15619
15620 u32 power_well_driver;
15621
63b66e5b
CW		 15622 int num_transcoders;
15623
c4a1d9e4
CW		 15624 struct intel_cursor_error_state {
15625 u32 control;
15626 u32 position;
15627 u32 base;
15628 u32 size;
52331309 15629 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15630
15631 struct intel_pipe_error_state {
ddf9c536 15632 bool power_domain_on;
c4a1d9e4 15633 u32 source;
f301b1e1 15634 u32 stat;
52331309 15635 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15636
15637 struct intel_plane_error_state {
15638 u32 control;
15639 u32 stride;
15640 u32 size;
15641 u32 pos;
15642 u32 addr;
15643 u32 surface;
15644 u32 tile_offset;
52331309 15645 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15646
15647 struct intel_transcoder_error_state {
ddf9c536 15648 bool power_domain_on;
63b66e5b
CW		 15649 enum transcoder cpu_transcoder;
15650
15651 u32 conf;
15652
15653 u32 htotal;
15654 u32 hblank;
15655 u32 hsync;
15656 u32 vtotal;
15657 u32 vblank;
15658 u32 vsync;
15659 } transcoder[4];
c4a1d9e4
CW		 15660};
15661
15662struct intel_display_error_state *
15663intel_display_capture_error_state(struct drm_device *dev)
15664{
fbee40df 15665 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15666 struct intel_display_error_state *error;
63b66e5b
CW		 15667 int transcoders[] = {
15668 TRANSCODER_A,
15669 TRANSCODER_B,
15670 TRANSCODER_C,
15671 TRANSCODER_EDP,
15672 };
c4a1d9e4
CW		 15673 int i;
15674
63b66e5b
CW		 15675 if (INTEL_INFO(dev)->num_pipes == 0)
15676 return NULL;
15677
9d1cb914 15678 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15679 if (error == NULL)
15680 return NULL;
15681
190be112 15682 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15683 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15684
055e393f 15685 for_each_pipe(dev_priv, i) {
ddf9c536 15686 error->pipe[i].power_domain_on =
f458ebbc
DV		 15687 __intel_display_power_is_enabled(dev_priv,
15688 POWER_DOMAIN_PIPE(i));
ddf9c536 15689 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15690 continue;
15691
5efb3e28
VS		 15692 error->cursor[i].control = I915_READ(CURCNTR(i));
15693 error->cursor[i].position = I915_READ(CURPOS(i));
15694 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15695
15696 error->plane[i].control = I915_READ(DSPCNTR(i));
15697 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15698 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15699 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15700 error->plane[i].pos = I915_READ(DSPPOS(i));
15701 }
ca291363
PZ		 15702 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15703 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15704 if (INTEL_INFO(dev)->gen >= 4) {
15705 error->plane[i].surface = I915_READ(DSPSURF(i));
15706 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15707 }
15708
c4a1d9e4 15709 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15710
3abfce77 15711 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15712 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15713 }
15714
15715 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15716 if (HAS_DDI(dev_priv->dev))
15717 error->num_transcoders++; /* Account for eDP. */
15718
15719 for (i = 0; i < error->num_transcoders; i++) {
15720 enum transcoder cpu_transcoder = transcoders[i];
15721
ddf9c536 15722 error->transcoder[i].power_domain_on =
f458ebbc 15723 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15724 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15725 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15726 continue;
15727
63b66e5b
CW		 15728 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15729
15730 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15731 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15732 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15733 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15734 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15735 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15736 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15737 }
15738
15739 return error;
15740}
15741
edc3d884
MK		 15742#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15743
c4a1d9e4 15744void
edc3d884 15745intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15746 struct drm_device *dev,
15747 struct intel_display_error_state *error)
15748{
055e393f 15749 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15750 int i;
15751
63b66e5b
CW		 15752 if (!error)
15753 return;
15754
edc3d884 15755 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15756 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15757 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15758 error->power_well_driver);
055e393f 15759 for_each_pipe(dev_priv, i) {
edc3d884 15760 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15761 err_printf(m, " Power: %s\n",
15762 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15763 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15764 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15765
15766 err_printf(m, "Plane [%d]:\n", i);
15767 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15768 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15769 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15770 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15771 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15772 }
4b71a570 15773 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15774 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15775 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15776 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15777 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15778 }
15779
edc3d884
MK		 15780 err_printf(m, "Cursor [%d]:\n", i);
15781 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15782 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15783 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15784 }
63b66e5b
CW		 15785
15786 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15787 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15788 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15789 err_printf(m, " Power: %s\n",
15790 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15791 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15792 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15793 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15794 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15795 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15796 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15797 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15798 }
c4a1d9e4 15799}
e2fcdaa9
VS		 15800
15801void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15802{
15803 struct intel_crtc *crtc;
15804
15805 for_each_intel_crtc(dev, crtc) {
15806 struct intel_unpin_work *work;
e2fcdaa9 15807
5e2d7afc 15808 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15809
15810 work = crtc->unpin_work;
15811
15812 if (work && work->event &&
15813 work->event->base.file_priv == file) {
15814 kfree(work->event);
15815 work->event = NULL;
15816 }
15817
5e2d7afc 15818 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15819 }
15820}
Linux kernel - Deliverables
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