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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
6b383a7f | 88 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 89 | |
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
eb1bfe80 JB |
95 | static int intel_framebuffer_init(struct drm_device *dev, |
96 | struct intel_framebuffer *ifb, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd, | |
98 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
99 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
100 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
106 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
115 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
116 | int num_connectors); | |
bfd16b2a ML |
117 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
118 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
119 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 120 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 121 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 122 | |
79e53945 | 123 | typedef struct { |
0206e353 | 124 | int min, max; |
79e53945 JB |
125 | } intel_range_t; |
126 | ||
127 | typedef struct { | |
0206e353 AJ |
128 | int dot_limit; |
129 | int p2_slow, p2_fast; | |
79e53945 JB |
130 | } intel_p2_t; |
131 | ||
d4906093 ML |
132 | typedef struct intel_limit intel_limit_t; |
133 | struct intel_limit { | |
0206e353 AJ |
134 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
135 | intel_p2_t p2; | |
d4906093 | 136 | }; |
79e53945 | 137 | |
bfa7df01 VS |
138 | /* returns HPLL frequency in kHz */ |
139 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
140 | { | |
141 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
142 | ||
143 | /* Obtain SKU information */ | |
144 | mutex_lock(&dev_priv->sb_lock); | |
145 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
146 | CCK_FUSE_HPLL_FREQ_MASK; | |
147 | mutex_unlock(&dev_priv->sb_lock); | |
148 | ||
149 | return vco_freq[hpll_freq] * 1000; | |
150 | } | |
151 | ||
152 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
153 | const char *name, u32 reg) | |
154 | { | |
155 | u32 val; | |
156 | int divider; | |
157 | ||
158 | if (dev_priv->hpll_freq == 0) | |
159 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
160 | ||
161 | mutex_lock(&dev_priv->sb_lock); | |
162 | val = vlv_cck_read(dev_priv, reg); | |
163 | mutex_unlock(&dev_priv->sb_lock); | |
164 | ||
165 | divider = val & CCK_FREQUENCY_VALUES; | |
166 | ||
167 | WARN((val & CCK_FREQUENCY_STATUS) != | |
168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
169 | "%s change in progress\n", name); | |
170 | ||
171 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
172 | } | |
173 | ||
d2acd215 DV |
174 | int |
175 | intel_pch_rawclk(struct drm_device *dev) | |
176 | { | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
178 | ||
179 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
180 | ||
181 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
182 | } | |
183 | ||
79e50a4f JN |
184 | /* hrawclock is 1/4 the FSB frequency */ |
185 | int intel_hrawclk(struct drm_device *dev) | |
186 | { | |
187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
188 | uint32_t clkcfg; | |
189 | ||
190 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 191 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
192 | return 200; |
193 | ||
194 | clkcfg = I915_READ(CLKCFG); | |
195 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
196 | case CLKCFG_FSB_400: | |
197 | return 100; | |
198 | case CLKCFG_FSB_533: | |
199 | return 133; | |
200 | case CLKCFG_FSB_667: | |
201 | return 166; | |
202 | case CLKCFG_FSB_800: | |
203 | return 200; | |
204 | case CLKCFG_FSB_1067: | |
205 | return 266; | |
206 | case CLKCFG_FSB_1333: | |
207 | return 333; | |
208 | /* these two are just a guess; one of them might be right */ | |
209 | case CLKCFG_FSB_1600: | |
210 | case CLKCFG_FSB_1600_ALT: | |
211 | return 400; | |
212 | default: | |
213 | return 133; | |
214 | } | |
215 | } | |
216 | ||
bfa7df01 VS |
217 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
218 | { | |
666a4537 | 219 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
220 | return; |
221 | ||
222 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
223 | CCK_CZ_CLOCK_CONTROL); | |
224 | ||
225 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
226 | } | |
227 | ||
021357ac CW |
228 | static inline u32 /* units of 100MHz */ |
229 | intel_fdi_link_freq(struct drm_device *dev) | |
230 | { | |
8b99e68c CW |
231 | if (IS_GEN5(dev)) { |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
234 | } else | |
235 | return 27; | |
021357ac CW |
236 | } |
237 | ||
5d536e28 | 238 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 239 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 240 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 241 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
242 | .m = { .min = 96, .max = 140 }, |
243 | .m1 = { .min = 18, .max = 26 }, | |
244 | .m2 = { .min = 6, .max = 16 }, | |
245 | .p = { .min = 4, .max = 128 }, | |
246 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 165000, |
248 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
249 | }; |
250 | ||
5d536e28 DV |
251 | static const intel_limit_t intel_limits_i8xx_dvo = { |
252 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
260 | .p2 = { .dot_limit = 165000, | |
261 | .p2_slow = 4, .p2_fast = 4 }, | |
262 | }; | |
263 | ||
e4b36699 | 264 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 275 | }; |
273e27ca | 276 | |
e4b36699 | 277 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
278 | .dot = { .min = 20000, .max = 400000 }, |
279 | .vco = { .min = 1400000, .max = 2800000 }, | |
280 | .n = { .min = 1, .max = 6 }, | |
281 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
282 | .m1 = { .min = 8, .max = 18 }, |
283 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
284 | .p = { .min = 5, .max = 80 }, |
285 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 200000, |
287 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
288 | }; |
289 | ||
290 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 7, .max = 98 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 112000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
301 | }; |
302 | ||
273e27ca | 303 | |
e4b36699 | 304 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 270000 }, |
306 | .vco = { .min = 1750000, .max = 3500000}, | |
307 | .n = { .min = 1, .max = 4 }, | |
308 | .m = { .min = 104, .max = 138 }, | |
309 | .m1 = { .min = 17, .max = 23 }, | |
310 | .m2 = { .min = 5, .max = 11 }, | |
311 | .p = { .min = 10, .max = 30 }, | |
312 | .p1 = { .min = 1, .max = 3}, | |
313 | .p2 = { .dot_limit = 270000, | |
314 | .p2_slow = 10, | |
315 | .p2_fast = 10 | |
044c7c41 | 316 | }, |
e4b36699 KP |
317 | }; |
318 | ||
319 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
320 | .dot = { .min = 22000, .max = 400000 }, |
321 | .vco = { .min = 1750000, .max = 3500000}, | |
322 | .n = { .min = 1, .max = 4 }, | |
323 | .m = { .min = 104, .max = 138 }, | |
324 | .m1 = { .min = 16, .max = 23 }, | |
325 | .m2 = { .min = 5, .max = 11 }, | |
326 | .p = { .min = 5, .max = 80 }, | |
327 | .p1 = { .min = 1, .max = 8}, | |
328 | .p2 = { .dot_limit = 165000, | |
329 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
333 | .dot = { .min = 20000, .max = 115000 }, |
334 | .vco = { .min = 1750000, .max = 3500000 }, | |
335 | .n = { .min = 1, .max = 3 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 17, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 28, .max = 112 }, | |
340 | .p1 = { .min = 2, .max = 8 }, | |
341 | .p2 = { .dot_limit = 0, | |
342 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 343 | }, |
e4b36699 KP |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
347 | .dot = { .min = 80000, .max = 224000 }, |
348 | .vco = { .min = 1750000, .max = 3500000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 104, .max = 138 }, | |
351 | .m1 = { .min = 17, .max = 23 }, | |
352 | .m2 = { .min = 5, .max = 11 }, | |
353 | .p = { .min = 14, .max = 42 }, | |
354 | .p1 = { .min = 2, .max = 6 }, | |
355 | .p2 = { .dot_limit = 0, | |
356 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 357 | }, |
e4b36699 KP |
358 | }; |
359 | ||
f2b115e6 | 360 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
361 | .dot = { .min = 20000, .max = 400000}, |
362 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 363 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
364 | .n = { .min = 3, .max = 6 }, |
365 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 366 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
367 | .m1 = { .min = 0, .max = 0 }, |
368 | .m2 = { .min = 0, .max = 254 }, | |
369 | .p = { .min = 5, .max = 80 }, | |
370 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
371 | .p2 = { .dot_limit = 200000, |
372 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
373 | }; |
374 | ||
f2b115e6 | 375 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
376 | .dot = { .min = 20000, .max = 400000 }, |
377 | .vco = { .min = 1700000, .max = 3500000 }, | |
378 | .n = { .min = 3, .max = 6 }, | |
379 | .m = { .min = 2, .max = 256 }, | |
380 | .m1 = { .min = 0, .max = 0 }, | |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 7, .max = 112 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 112000, |
385 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
386 | }; |
387 | ||
273e27ca EA |
388 | /* Ironlake / Sandybridge |
389 | * | |
390 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
391 | * the range value for them is (actual_value - 2). | |
392 | */ | |
b91ad0ec | 393 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
394 | .dot = { .min = 25000, .max = 350000 }, |
395 | .vco = { .min = 1760000, .max = 3510000 }, | |
396 | .n = { .min = 1, .max = 5 }, | |
397 | .m = { .min = 79, .max = 127 }, | |
398 | .m1 = { .min = 12, .max = 22 }, | |
399 | .m2 = { .min = 5, .max = 9 }, | |
400 | .p = { .min = 5, .max = 80 }, | |
401 | .p1 = { .min = 1, .max = 8 }, | |
402 | .p2 = { .dot_limit = 225000, | |
403 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
404 | }; |
405 | ||
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 3 }, | |
410 | .m = { .min = 79, .max = 118 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 28, .max = 112 }, | |
414 | .p1 = { .min = 2, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
417 | }; |
418 | ||
419 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 14, .max = 56 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
273e27ca | 432 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 433 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
434 | .dot = { .min = 25000, .max = 350000 }, |
435 | .vco = { .min = 1760000, .max = 3510000 }, | |
436 | .n = { .min = 1, .max = 2 }, | |
437 | .m = { .min = 79, .max = 126 }, | |
438 | .m1 = { .min = 12, .max = 22 }, | |
439 | .m2 = { .min = 5, .max = 9 }, | |
440 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 441 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
442 | .p2 = { .dot_limit = 225000, |
443 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
444 | }; |
445 | ||
446 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 3 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
457 | }; |
458 | ||
dc730512 | 459 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
460 | /* |
461 | * These are the data rate limits (measured in fast clocks) | |
462 | * since those are the strictest limits we have. The fast | |
463 | * clock and actual rate limits are more relaxed, so checking | |
464 | * them would make no difference. | |
465 | */ | |
466 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 467 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 468 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
469 | .m1 = { .min = 2, .max = 3 }, |
470 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 471 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 472 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
473 | }; |
474 | ||
ef9348c8 CML |
475 | static const intel_limit_t intel_limits_chv = { |
476 | /* | |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 483 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
484 | .n = { .min = 1, .max = 1 }, |
485 | .m1 = { .min = 2, .max = 2 }, | |
486 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
487 | .p1 = { .min = 2, .max = 4 }, | |
488 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
489 | }; | |
490 | ||
5ab7b0b7 ID |
491 | static const intel_limit_t intel_limits_bxt = { |
492 | /* FIXME: find real dot limits */ | |
493 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 494 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
495 | .n = { .min = 1, .max = 1 }, |
496 | .m1 = { .min = 2, .max = 2 }, | |
497 | /* FIXME: find real m2 limits */ | |
498 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
499 | .p1 = { .min = 2, .max = 4 }, | |
500 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
501 | }; | |
502 | ||
cdba954e ACO |
503 | static bool |
504 | needs_modeset(struct drm_crtc_state *state) | |
505 | { | |
fc596660 | 506 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
507 | } |
508 | ||
e0638cdf PZ |
509 | /** |
510 | * Returns whether any output on the specified pipe is of the specified type | |
511 | */ | |
4093561b | 512 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 513 | { |
409ee761 | 514 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
515 | struct intel_encoder *encoder; |
516 | ||
409ee761 | 517 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
518 | if (encoder->type == type) |
519 | return true; | |
520 | ||
521 | return false; | |
522 | } | |
523 | ||
d0737e1d ACO |
524 | /** |
525 | * Returns whether any output on the specified pipe will have the specified | |
526 | * type after a staged modeset is complete, i.e., the same as | |
527 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
528 | * encoder->crtc. | |
529 | */ | |
a93e255f ACO |
530 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
531 | int type) | |
d0737e1d | 532 | { |
a93e255f | 533 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 534 | struct drm_connector *connector; |
a93e255f | 535 | struct drm_connector_state *connector_state; |
d0737e1d | 536 | struct intel_encoder *encoder; |
a93e255f ACO |
537 | int i, num_connectors = 0; |
538 | ||
da3ced29 | 539 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
540 | if (connector_state->crtc != crtc_state->base.crtc) |
541 | continue; | |
542 | ||
543 | num_connectors++; | |
d0737e1d | 544 | |
a93e255f ACO |
545 | encoder = to_intel_encoder(connector_state->best_encoder); |
546 | if (encoder->type == type) | |
d0737e1d | 547 | return true; |
a93e255f ACO |
548 | } |
549 | ||
550 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
551 | |
552 | return false; | |
553 | } | |
554 | ||
a93e255f ACO |
555 | static const intel_limit_t * |
556 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 557 | { |
a93e255f | 558 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 559 | const intel_limit_t *limit; |
b91ad0ec | 560 | |
a93e255f | 561 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 562 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 563 | if (refclk == 100000) |
b91ad0ec ZW |
564 | limit = &intel_limits_ironlake_dual_lvds_100m; |
565 | else | |
566 | limit = &intel_limits_ironlake_dual_lvds; | |
567 | } else { | |
1b894b59 | 568 | if (refclk == 100000) |
b91ad0ec ZW |
569 | limit = &intel_limits_ironlake_single_lvds_100m; |
570 | else | |
571 | limit = &intel_limits_ironlake_single_lvds; | |
572 | } | |
c6bb3538 | 573 | } else |
b91ad0ec | 574 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
575 | |
576 | return limit; | |
577 | } | |
578 | ||
a93e255f ACO |
579 | static const intel_limit_t * |
580 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 581 | { |
a93e255f | 582 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
583 | const intel_limit_t *limit; |
584 | ||
a93e255f | 585 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 586 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 587 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 588 | else |
e4b36699 | 589 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
591 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 592 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 593 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 594 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 595 | } else /* The option is for other outputs */ |
e4b36699 | 596 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
597 | |
598 | return limit; | |
599 | } | |
600 | ||
a93e255f ACO |
601 | static const intel_limit_t * |
602 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 603 | { |
a93e255f | 604 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
605 | const intel_limit_t *limit; |
606 | ||
5ab7b0b7 ID |
607 | if (IS_BROXTON(dev)) |
608 | limit = &intel_limits_bxt; | |
609 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 610 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 611 | else if (IS_G4X(dev)) { |
a93e255f | 612 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 613 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 614 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 615 | limit = &intel_limits_pineview_lvds; |
2177832f | 616 | else |
f2b115e6 | 617 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
618 | } else if (IS_CHERRYVIEW(dev)) { |
619 | limit = &intel_limits_chv; | |
a0c4da24 | 620 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 621 | limit = &intel_limits_vlv; |
a6c45cf0 | 622 | } else if (!IS_GEN2(dev)) { |
a93e255f | 623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
624 | limit = &intel_limits_i9xx_lvds; |
625 | else | |
626 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 627 | } else { |
a93e255f | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 630 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 631 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
632 | else |
633 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
634 | } |
635 | return limit; | |
636 | } | |
637 | ||
dccbea3b ID |
638 | /* |
639 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
640 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
641 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
642 | * The helpers' return value is the rate of the clock that is fed to the | |
643 | * display engine's pipe which can be the above fast dot clock rate or a | |
644 | * divided-down version of it. | |
645 | */ | |
f2b115e6 | 646 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 647 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 648 | { |
2177832f SL |
649 | clock->m = clock->m2 + 2; |
650 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 651 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 652 | return 0; |
fb03ac01 VS |
653 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
654 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
655 | |
656 | return clock->dot; | |
2177832f SL |
657 | } |
658 | ||
7429e9d4 DV |
659 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
660 | { | |
661 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
662 | } | |
663 | ||
dccbea3b | 664 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 665 | { |
7429e9d4 | 666 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 667 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 668 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 669 | return 0; |
fb03ac01 VS |
670 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
671 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
672 | |
673 | return clock->dot; | |
79e53945 JB |
674 | } |
675 | ||
dccbea3b | 676 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
677 | { |
678 | clock->m = clock->m1 * clock->m2; | |
679 | clock->p = clock->p1 * clock->p2; | |
680 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 681 | return 0; |
589eca67 ID |
682 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
683 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
684 | |
685 | return clock->dot / 5; | |
589eca67 ID |
686 | } |
687 | ||
dccbea3b | 688 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
689 | { |
690 | clock->m = clock->m1 * clock->m2; | |
691 | clock->p = clock->p1 * clock->p2; | |
692 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 693 | return 0; |
ef9348c8 CML |
694 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
695 | clock->n << 22); | |
696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
697 | |
698 | return clock->dot / 5; | |
ef9348c8 CML |
699 | } |
700 | ||
7c04d1d9 | 701 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
702 | /** |
703 | * Returns whether the given set of divisors are valid for a given refclk with | |
704 | * the given connectors. | |
705 | */ | |
706 | ||
1b894b59 CW |
707 | static bool intel_PLL_is_valid(struct drm_device *dev, |
708 | const intel_limit_t *limit, | |
709 | const intel_clock_t *clock) | |
79e53945 | 710 | { |
f01b7962 VS |
711 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
712 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 713 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 714 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 716 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 718 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 719 | |
666a4537 WB |
720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
722 | if (clock->m1 <= clock->m2) |
723 | INTELPllInvalid("m1 <= m2\n"); | |
724 | ||
666a4537 | 725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
727 | INTELPllInvalid("p out of range\n"); | |
728 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
729 | INTELPllInvalid("m out of range\n"); | |
730 | } | |
731 | ||
79e53945 | 732 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 733 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
734 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
735 | * connector, etc., rather than just a single range. | |
736 | */ | |
737 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 738 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
739 | |
740 | return true; | |
741 | } | |
742 | ||
3b1429d9 VS |
743 | static int |
744 | i9xx_select_p2_div(const intel_limit_t *limit, | |
745 | const struct intel_crtc_state *crtc_state, | |
746 | int target) | |
79e53945 | 747 | { |
3b1429d9 | 748 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 749 | |
a93e255f | 750 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 751 | /* |
a210b028 DV |
752 | * For LVDS just rely on its current settings for dual-channel. |
753 | * We haven't figured out how to reliably set up different | |
754 | * single/dual channel state, if we even can. | |
79e53945 | 755 | */ |
1974cad0 | 756 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 757 | return limit->p2.p2_fast; |
79e53945 | 758 | else |
3b1429d9 | 759 | return limit->p2.p2_slow; |
79e53945 JB |
760 | } else { |
761 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 762 | return limit->p2.p2_slow; |
79e53945 | 763 | else |
3b1429d9 | 764 | return limit->p2.p2_fast; |
79e53945 | 765 | } |
3b1429d9 VS |
766 | } |
767 | ||
768 | static bool | |
769 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
770 | struct intel_crtc_state *crtc_state, | |
771 | int target, int refclk, intel_clock_t *match_clock, | |
772 | intel_clock_t *best_clock) | |
773 | { | |
774 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
775 | intel_clock_t clock; | |
776 | int err = target; | |
79e53945 | 777 | |
0206e353 | 778 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 779 | |
3b1429d9 VS |
780 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
781 | ||
42158660 ZY |
782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
783 | clock.m1++) { | |
784 | for (clock.m2 = limit->m2.min; | |
785 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 786 | if (clock.m2 >= clock.m1) |
42158660 ZY |
787 | break; |
788 | for (clock.n = limit->n.min; | |
789 | clock.n <= limit->n.max; clock.n++) { | |
790 | for (clock.p1 = limit->p1.min; | |
791 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
792 | int this_err; |
793 | ||
dccbea3b | 794 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
795 | if (!intel_PLL_is_valid(dev, limit, |
796 | &clock)) | |
797 | continue; | |
798 | if (match_clock && | |
799 | clock.p != match_clock->p) | |
800 | continue; | |
801 | ||
802 | this_err = abs(clock.dot - target); | |
803 | if (this_err < err) { | |
804 | *best_clock = clock; | |
805 | err = this_err; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | return (err != target); | |
813 | } | |
814 | ||
815 | static bool | |
a93e255f ACO |
816 | pnv_find_best_dpll(const intel_limit_t *limit, |
817 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
818 | int target, int refclk, intel_clock_t *match_clock, |
819 | intel_clock_t *best_clock) | |
79e53945 | 820 | { |
3b1429d9 | 821 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 822 | intel_clock_t clock; |
79e53945 JB |
823 | int err = target; |
824 | ||
0206e353 | 825 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 826 | |
3b1429d9 VS |
827 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
828 | ||
42158660 ZY |
829 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
830 | clock.m1++) { | |
831 | for (clock.m2 = limit->m2.min; | |
832 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
833 | for (clock.n = limit->n.min; |
834 | clock.n <= limit->n.max; clock.n++) { | |
835 | for (clock.p1 = limit->p1.min; | |
836 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
837 | int this_err; |
838 | ||
dccbea3b | 839 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
840 | if (!intel_PLL_is_valid(dev, limit, |
841 | &clock)) | |
79e53945 | 842 | continue; |
cec2f356 SP |
843 | if (match_clock && |
844 | clock.p != match_clock->p) | |
845 | continue; | |
79e53945 JB |
846 | |
847 | this_err = abs(clock.dot - target); | |
848 | if (this_err < err) { | |
849 | *best_clock = clock; | |
850 | err = this_err; | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return (err != target); | |
858 | } | |
859 | ||
d4906093 | 860 | static bool |
a93e255f ACO |
861 | g4x_find_best_dpll(const intel_limit_t *limit, |
862 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
863 | int target, int refclk, intel_clock_t *match_clock, |
864 | intel_clock_t *best_clock) | |
d4906093 | 865 | { |
3b1429d9 | 866 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
867 | intel_clock_t clock; |
868 | int max_n; | |
3b1429d9 | 869 | bool found = false; |
6ba770dc AJ |
870 | /* approximately equals target * 0.00585 */ |
871 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
872 | |
873 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
874 | |
875 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
876 | ||
d4906093 | 877 | max_n = limit->n.max; |
f77f13e2 | 878 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 880 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
881 | for (clock.m1 = limit->m1.max; |
882 | clock.m1 >= limit->m1.min; clock.m1--) { | |
883 | for (clock.m2 = limit->m2.max; | |
884 | clock.m2 >= limit->m2.min; clock.m2--) { | |
885 | for (clock.p1 = limit->p1.max; | |
886 | clock.p1 >= limit->p1.min; clock.p1--) { | |
887 | int this_err; | |
888 | ||
dccbea3b | 889 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
890 | if (!intel_PLL_is_valid(dev, limit, |
891 | &clock)) | |
d4906093 | 892 | continue; |
1b894b59 CW |
893 | |
894 | this_err = abs(clock.dot - target); | |
d4906093 ML |
895 | if (this_err < err_most) { |
896 | *best_clock = clock; | |
897 | err_most = this_err; | |
898 | max_n = clock.n; | |
899 | found = true; | |
900 | } | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
2c07245f ZW |
905 | return found; |
906 | } | |
907 | ||
d5dd62bd ID |
908 | /* |
909 | * Check if the calculated PLL configuration is more optimal compared to the | |
910 | * best configuration and error found so far. Return the calculated error. | |
911 | */ | |
912 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
913 | const intel_clock_t *calculated_clock, | |
914 | const intel_clock_t *best_clock, | |
915 | unsigned int best_error_ppm, | |
916 | unsigned int *error_ppm) | |
917 | { | |
9ca3ba01 ID |
918 | /* |
919 | * For CHV ignore the error and consider only the P value. | |
920 | * Prefer a bigger P value based on HW requirements. | |
921 | */ | |
922 | if (IS_CHERRYVIEW(dev)) { | |
923 | *error_ppm = 0; | |
924 | ||
925 | return calculated_clock->p > best_clock->p; | |
926 | } | |
927 | ||
24be4e46 ID |
928 | if (WARN_ON_ONCE(!target_freq)) |
929 | return false; | |
930 | ||
d5dd62bd ID |
931 | *error_ppm = div_u64(1000000ULL * |
932 | abs(target_freq - calculated_clock->dot), | |
933 | target_freq); | |
934 | /* | |
935 | * Prefer a better P value over a better (smaller) error if the error | |
936 | * is small. Ensure this preference for future configurations too by | |
937 | * setting the error to 0. | |
938 | */ | |
939 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
940 | *error_ppm = 0; | |
941 | ||
942 | return true; | |
943 | } | |
944 | ||
945 | return *error_ppm + 10 < best_error_ppm; | |
946 | } | |
947 | ||
a0c4da24 | 948 | static bool |
a93e255f ACO |
949 | vlv_find_best_dpll(const intel_limit_t *limit, |
950 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
951 | int target, int refclk, intel_clock_t *match_clock, |
952 | intel_clock_t *best_clock) | |
a0c4da24 | 953 | { |
a93e255f | 954 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 955 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 956 | intel_clock_t clock; |
69e4f900 | 957 | unsigned int bestppm = 1000000; |
27e639bf VS |
958 | /* min update 19.2 MHz */ |
959 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 960 | bool found = false; |
a0c4da24 | 961 | |
6b4bf1c4 VS |
962 | target *= 5; /* fast clock */ |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
965 | |
966 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 967 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 969 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 971 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 972 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 973 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 974 | unsigned int ppm; |
69e4f900 | 975 | |
6b4bf1c4 VS |
976 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
977 | refclk * clock.m1); | |
978 | ||
dccbea3b | 979 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 980 | |
f01b7962 VS |
981 | if (!intel_PLL_is_valid(dev, limit, |
982 | &clock)) | |
43b0ac53 VS |
983 | continue; |
984 | ||
d5dd62bd ID |
985 | if (!vlv_PLL_is_optimal(dev, target, |
986 | &clock, | |
987 | best_clock, | |
988 | bestppm, &ppm)) | |
989 | continue; | |
6b4bf1c4 | 990 | |
d5dd62bd ID |
991 | *best_clock = clock; |
992 | bestppm = ppm; | |
993 | found = true; | |
a0c4da24 JB |
994 | } |
995 | } | |
996 | } | |
997 | } | |
a0c4da24 | 998 | |
49e497ef | 999 | return found; |
a0c4da24 | 1000 | } |
a4fc5ed6 | 1001 | |
ef9348c8 | 1002 | static bool |
a93e255f ACO |
1003 | chv_find_best_dpll(const intel_limit_t *limit, |
1004 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1005 | int target, int refclk, intel_clock_t *match_clock, |
1006 | intel_clock_t *best_clock) | |
1007 | { | |
a93e255f | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1009 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1010 | unsigned int best_error_ppm; |
ef9348c8 CML |
1011 | intel_clock_t clock; |
1012 | uint64_t m2; | |
1013 | int found = false; | |
1014 | ||
1015 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1016 | best_error_ppm = 1000000; |
ef9348c8 CML |
1017 | |
1018 | /* | |
1019 | * Based on hardware doc, the n always set to 1, and m1 always | |
1020 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1021 | * revisit this because n may not 1 anymore. | |
1022 | */ | |
1023 | clock.n = 1, clock.m1 = 2; | |
1024 | target *= 5; /* fast clock */ | |
1025 | ||
1026 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1027 | for (clock.p2 = limit->p2.p2_fast; | |
1028 | clock.p2 >= limit->p2.p2_slow; | |
1029 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1030 | unsigned int error_ppm; |
ef9348c8 CML |
1031 | |
1032 | clock.p = clock.p1 * clock.p2; | |
1033 | ||
1034 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1035 | clock.n) << 22, refclk * clock.m1); | |
1036 | ||
1037 | if (m2 > INT_MAX/clock.m1) | |
1038 | continue; | |
1039 | ||
1040 | clock.m2 = m2; | |
1041 | ||
dccbea3b | 1042 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1043 | |
1044 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1045 | continue; | |
1046 | ||
9ca3ba01 ID |
1047 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1048 | best_error_ppm, &error_ppm)) | |
1049 | continue; | |
1050 | ||
1051 | *best_clock = clock; | |
1052 | best_error_ppm = error_ppm; | |
1053 | found = true; | |
ef9348c8 CML |
1054 | } |
1055 | } | |
1056 | ||
1057 | return found; | |
1058 | } | |
1059 | ||
5ab7b0b7 ID |
1060 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1061 | intel_clock_t *best_clock) | |
1062 | { | |
1063 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1064 | ||
1065 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1066 | target_clock, refclk, NULL, best_clock); | |
1067 | } | |
1068 | ||
20ddf665 VS |
1069 | bool intel_crtc_active(struct drm_crtc *crtc) |
1070 | { | |
1071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1072 | ||
1073 | /* Be paranoid as we can arrive here with only partial | |
1074 | * state retrieved from the hardware during setup. | |
1075 | * | |
241bfc38 | 1076 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1077 | * as Haswell has gained clock readout/fastboot support. |
1078 | * | |
66e514c1 | 1079 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1080 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1081 | * |
1082 | * FIXME: The intel_crtc->active here should be switched to | |
1083 | * crtc->state->active once we have proper CRTC states wired up | |
1084 | * for atomic. | |
20ddf665 | 1085 | */ |
c3d1f436 | 1086 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1087 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1088 | } |
1089 | ||
a5c961d1 PZ |
1090 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1091 | enum pipe pipe) | |
1092 | { | |
1093 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1095 | ||
6e3c9717 | 1096 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1097 | } |
1098 | ||
fbf49ea2 VS |
1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1102 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1103 | u32 line1, line2; |
1104 | u32 line_mask; | |
1105 | ||
1106 | if (IS_GEN2(dev)) | |
1107 | line_mask = DSL_LINEMASK_GEN2; | |
1108 | else | |
1109 | line_mask = DSL_LINEMASK_GEN3; | |
1110 | ||
1111 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1112 | msleep(5); |
fbf49ea2 VS |
1113 | line2 = I915_READ(reg) & line_mask; |
1114 | ||
1115 | return line1 == line2; | |
1116 | } | |
1117 | ||
ab7ad7f6 KP |
1118 | /* |
1119 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1120 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1121 | * |
1122 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1123 | * spinning on the vblank interrupt status bit, since we won't actually | |
1124 | * see an interrupt when the pipe is disabled. | |
1125 | * | |
ab7ad7f6 KP |
1126 | * On Gen4 and above: |
1127 | * wait for the pipe register state bit to turn off | |
1128 | * | |
1129 | * Otherwise: | |
1130 | * wait for the display line value to settle (it usually | |
1131 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1132 | * |
9d0498a2 | 1133 | */ |
575f7ab7 | 1134 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1135 | { |
575f7ab7 | 1136 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1139 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1140 | |
1141 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1143 | |
1144 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1146 | 100)) | |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } else { |
ab7ad7f6 | 1149 | /* Wait for the display line to settle */ |
fbf49ea2 | 1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1151 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1152 | } |
79e53945 JB |
1153 | } |
1154 | ||
b24e7179 JB |
1155 | static const char *state_string(bool enabled) |
1156 | { | |
1157 | return enabled ? "on" : "off"; | |
1158 | } | |
1159 | ||
1160 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1161 | void assert_pll(struct drm_i915_private *dev_priv, |
1162 | enum pipe pipe, bool state) | |
b24e7179 | 1163 | { |
b24e7179 JB |
1164 | u32 val; |
1165 | bool cur_state; | |
1166 | ||
649636ef | 1167 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1168 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1169 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1170 | "PLL state assertion failure (expected %s, current %s)\n", |
1171 | state_string(state), state_string(cur_state)); | |
1172 | } | |
b24e7179 | 1173 | |
23538ef1 JN |
1174 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1175 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1176 | { | |
1177 | u32 val; | |
1178 | bool cur_state; | |
1179 | ||
a580516d | 1180 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1181 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1182 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1183 | |
1184 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1186 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1187 | state_string(state), state_string(cur_state)); | |
1188 | } | |
1189 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1190 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1191 | ||
55607e8a | 1192 | struct intel_shared_dpll * |
e2b78267 DV |
1193 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1194 | { | |
1195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1196 | ||
6e3c9717 | 1197 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1198 | return NULL; |
1199 | ||
6e3c9717 | 1200 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1201 | } |
1202 | ||
040484af | 1203 | /* For ILK+ */ |
55607e8a DV |
1204 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1205 | struct intel_shared_dpll *pll, | |
1206 | bool state) | |
040484af | 1207 | { |
040484af | 1208 | bool cur_state; |
5358901f | 1209 | struct intel_dpll_hw_state hw_state; |
040484af | 1210 | |
92b27b08 | 1211 | if (WARN (!pll, |
46edb027 | 1212 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1213 | return; |
ee7b9f93 | 1214 | |
5358901f | 1215 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1216 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1217 | "%s assertion failure (expected %s, current %s)\n", |
1218 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1219 | } |
040484af JB |
1220 | |
1221 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1222 | enum pipe pipe, bool state) | |
1223 | { | |
040484af | 1224 | bool cur_state; |
ad80a810 PZ |
1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1226 | pipe); | |
040484af | 1227 | |
affa9354 PZ |
1228 | if (HAS_DDI(dev_priv->dev)) { |
1229 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1230 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1231 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1232 | } else { |
649636ef | 1233 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1234 | cur_state = !!(val & FDI_TX_ENABLE); |
1235 | } | |
e2c719b7 | 1236 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1237 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1238 | state_string(state), state_string(cur_state)); | |
1239 | } | |
1240 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1241 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1242 | ||
1243 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1244 | enum pipe pipe, bool state) | |
1245 | { | |
040484af JB |
1246 | u32 val; |
1247 | bool cur_state; | |
1248 | ||
649636ef | 1249 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1250 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1251 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1252 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1253 | state_string(state), state_string(cur_state)); | |
1254 | } | |
1255 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1256 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1257 | ||
1258 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1259 | enum pipe pipe) | |
1260 | { | |
040484af JB |
1261 | u32 val; |
1262 | ||
1263 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1264 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1265 | return; |
1266 | ||
bf507ef7 | 1267 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1268 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1269 | return; |
1270 | ||
649636ef | 1271 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1272 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1273 | } |
1274 | ||
55607e8a DV |
1275 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1276 | enum pipe pipe, bool state) | |
040484af | 1277 | { |
040484af | 1278 | u32 val; |
55607e8a | 1279 | bool cur_state; |
040484af | 1280 | |
649636ef | 1281 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1282 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1284 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1285 | state_string(state), state_string(cur_state)); | |
040484af JB |
1286 | } |
1287 | ||
b680c37a DV |
1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1289 | enum pipe pipe) | |
ea0760cf | 1290 | { |
bedd4dba | 1291 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1292 | i915_reg_t pp_reg; |
ea0760cf JB |
1293 | u32 val; |
1294 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1295 | bool locked = true; |
ea0760cf | 1296 | |
bedd4dba JN |
1297 | if (WARN_ON(HAS_DDI(dev))) |
1298 | return; | |
1299 | ||
1300 | if (HAS_PCH_SPLIT(dev)) { | |
1301 | u32 port_sel; | |
1302 | ||
ea0760cf | 1303 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1304 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1305 | ||
1306 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1307 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1308 | panel_pipe = PIPE_B; | |
1309 | /* XXX: else fix for eDP */ | |
666a4537 | 1310 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1311 | /* presumably write lock depends on pipe, not port select */ |
1312 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1313 | panel_pipe = pipe; | |
ea0760cf JB |
1314 | } else { |
1315 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1316 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1317 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1318 | } |
1319 | ||
1320 | val = I915_READ(pp_reg); | |
1321 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1322 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1323 | locked = false; |
1324 | ||
e2c719b7 | 1325 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1326 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1327 | pipe_name(pipe)); |
ea0760cf JB |
1328 | } |
1329 | ||
93ce0ba6 JN |
1330 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1331 | enum pipe pipe, bool state) | |
1332 | { | |
1333 | struct drm_device *dev = dev_priv->dev; | |
1334 | bool cur_state; | |
1335 | ||
d9d82081 | 1336 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1337 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1338 | else |
5efb3e28 | 1339 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1340 | |
e2c719b7 | 1341 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1342 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1344 | } | |
1345 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1346 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1347 | ||
b840d907 JB |
1348 | void assert_pipe(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe, bool state) | |
b24e7179 | 1350 | { |
63d7bbe9 | 1351 | bool cur_state; |
702e7a56 PZ |
1352 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1353 | pipe); | |
b24e7179 | 1354 | |
b6b5d049 VS |
1355 | /* if we need the pipe quirk it must be always on */ |
1356 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1357 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1358 | state = true; |
1359 | ||
f458ebbc | 1360 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1361 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1362 | cur_state = false; |
1363 | } else { | |
649636ef | 1364 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1365 | cur_state = !!(val & PIPECONF_ENABLE); |
1366 | } | |
1367 | ||
e2c719b7 | 1368 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1369 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1370 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1371 | } |
1372 | ||
931872fc CW |
1373 | static void assert_plane(struct drm_i915_private *dev_priv, |
1374 | enum plane plane, bool state) | |
b24e7179 | 1375 | { |
b24e7179 | 1376 | u32 val; |
931872fc | 1377 | bool cur_state; |
b24e7179 | 1378 | |
649636ef | 1379 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1380 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1381 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1382 | "plane %c assertion failure (expected %s, current %s)\n", |
1383 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1384 | } |
1385 | ||
931872fc CW |
1386 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1387 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1388 | ||
b24e7179 JB |
1389 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1390 | enum pipe pipe) | |
1391 | { | |
653e1026 | 1392 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1393 | int i; |
b24e7179 | 1394 | |
653e1026 VS |
1395 | /* Primary planes are fixed to pipes on gen4+ */ |
1396 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1397 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1398 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1399 | "plane %c assertion failure, should be disabled but not\n", |
1400 | plane_name(pipe)); | |
19ec1358 | 1401 | return; |
28c05794 | 1402 | } |
19ec1358 | 1403 | |
b24e7179 | 1404 | /* Need to check both planes against the pipe */ |
055e393f | 1405 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1406 | u32 val = I915_READ(DSPCNTR(i)); |
1407 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1408 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1409 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1410 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1411 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1412 | } |
1413 | } | |
1414 | ||
19332d7a JB |
1415 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1416 | enum pipe pipe) | |
1417 | { | |
20674eef | 1418 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1419 | int sprite; |
19332d7a | 1420 | |
7feb8b88 | 1421 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1422 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1423 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1424 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1425 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1426 | sprite, pipe_name(pipe)); | |
1427 | } | |
666a4537 | 1428 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1429 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1430 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1431 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1432 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1433 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1434 | } |
1435 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1436 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1437 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1439 | plane_name(pipe), pipe_name(pipe)); |
1440 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1441 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1442 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1443 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1444 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1445 | } |
1446 | } | |
1447 | ||
08c71e5e VS |
1448 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1449 | { | |
e2c719b7 | 1450 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1451 | drm_crtc_vblank_put(crtc); |
1452 | } | |
1453 | ||
89eff4be | 1454 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1455 | { |
1456 | u32 val; | |
1457 | bool enabled; | |
1458 | ||
e2c719b7 | 1459 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1460 | |
92f2584a JB |
1461 | val = I915_READ(PCH_DREF_CONTROL); |
1462 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1463 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1464 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1465 | } |
1466 | ||
ab9412ba DV |
1467 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1468 | enum pipe pipe) | |
92f2584a | 1469 | { |
92f2584a JB |
1470 | u32 val; |
1471 | bool enabled; | |
1472 | ||
649636ef | 1473 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1474 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1475 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1476 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1477 | pipe_name(pipe)); | |
92f2584a JB |
1478 | } |
1479 | ||
4e634389 KP |
1480 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1481 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1482 | { |
1483 | if ((val & DP_PORT_EN) == 0) | |
1484 | return false; | |
1485 | ||
1486 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1487 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1488 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1489 | return false; | |
44f37d1f CML |
1490 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1491 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1492 | return false; | |
f0575e92 KP |
1493 | } else { |
1494 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1495 | return false; | |
1496 | } | |
1497 | return true; | |
1498 | } | |
1499 | ||
1519b995 KP |
1500 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1501 | enum pipe pipe, u32 val) | |
1502 | { | |
dc0fa718 | 1503 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1504 | return false; |
1505 | ||
1506 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1507 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1508 | return false; |
44f37d1f CML |
1509 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1510 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1511 | return false; | |
1519b995 | 1512 | } else { |
dc0fa718 | 1513 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1514 | return false; |
1515 | } | |
1516 | return true; | |
1517 | } | |
1518 | ||
1519 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1520 | enum pipe pipe, u32 val) | |
1521 | { | |
1522 | if ((val & LVDS_PORT_EN) == 0) | |
1523 | return false; | |
1524 | ||
1525 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1526 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1527 | return false; | |
1528 | } else { | |
1529 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1530 | return false; | |
1531 | } | |
1532 | return true; | |
1533 | } | |
1534 | ||
1535 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1536 | enum pipe pipe, u32 val) | |
1537 | { | |
1538 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1539 | return false; | |
1540 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1541 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1542 | return false; | |
1543 | } else { | |
1544 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1545 | return false; | |
1546 | } | |
1547 | return true; | |
1548 | } | |
1549 | ||
291906f1 | 1550 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1551 | enum pipe pipe, i915_reg_t reg, |
1552 | u32 port_sel) | |
291906f1 | 1553 | { |
47a05eca | 1554 | u32 val = I915_READ(reg); |
e2c719b7 | 1555 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1556 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1557 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1558 | |
e2c719b7 | 1559 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1560 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1561 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1562 | } |
1563 | ||
1564 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1565 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1566 | { |
47a05eca | 1567 | u32 val = I915_READ(reg); |
e2c719b7 | 1568 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1569 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1570 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1571 | |
e2c719b7 | 1572 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1573 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1574 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1575 | } |
1576 | ||
1577 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1578 | enum pipe pipe) | |
1579 | { | |
291906f1 | 1580 | u32 val; |
291906f1 | 1581 | |
f0575e92 KP |
1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1583 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1584 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1585 | |
649636ef | 1586 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1587 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1588 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1589 | pipe_name(pipe)); |
291906f1 | 1590 | |
649636ef | 1591 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1592 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1593 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1594 | pipe_name(pipe)); |
291906f1 | 1595 | |
e2debe91 PZ |
1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1597 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1598 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1599 | } |
1600 | ||
d288f65f | 1601 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1602 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1603 | { |
426115cf DV |
1604 | struct drm_device *dev = crtc->base.dev; |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1606 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1607 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1608 | |
426115cf | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1610 | |
87442f73 | 1611 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1612 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1613 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1614 | |
426115cf DV |
1615 | I915_WRITE(reg, dpll); |
1616 | POSTING_READ(reg); | |
1617 | udelay(150); | |
1618 | ||
1619 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1620 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1621 | ||
d288f65f | 1622 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1623 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1624 | |
1625 | /* We do this three times for luck */ | |
426115cf | 1626 | I915_WRITE(reg, dpll); |
87442f73 DV |
1627 | POSTING_READ(reg); |
1628 | udelay(150); /* wait for warmup */ | |
426115cf | 1629 | I915_WRITE(reg, dpll); |
87442f73 DV |
1630 | POSTING_READ(reg); |
1631 | udelay(150); /* wait for warmup */ | |
426115cf | 1632 | I915_WRITE(reg, dpll); |
87442f73 DV |
1633 | POSTING_READ(reg); |
1634 | udelay(150); /* wait for warmup */ | |
1635 | } | |
1636 | ||
d288f65f | 1637 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1638 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1639 | { |
1640 | struct drm_device *dev = crtc->base.dev; | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | int pipe = crtc->pipe; | |
1643 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1644 | u32 tmp; |
1645 | ||
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1647 | ||
a580516d | 1648 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1649 | |
1650 | /* Enable back the 10bit clock to display controller */ | |
1651 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1652 | tmp |= DPIO_DCLKP_EN; | |
1653 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1654 | ||
54433e91 VS |
1655 | mutex_unlock(&dev_priv->sb_lock); |
1656 | ||
9d556c99 CML |
1657 | /* |
1658 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1659 | */ | |
1660 | udelay(1); | |
1661 | ||
1662 | /* Enable PLL */ | |
d288f65f | 1663 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1664 | |
1665 | /* Check PLL is locked */ | |
a11b0703 | 1666 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1667 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1668 | ||
a11b0703 | 1669 | /* not sure when this should be written */ |
d288f65f | 1670 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1671 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1672 | } |
1673 | ||
1c4e0274 VS |
1674 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1675 | { | |
1676 | struct intel_crtc *crtc; | |
1677 | int count = 0; | |
1678 | ||
1679 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1680 | count += crtc->base.state->active && |
409ee761 | 1681 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1682 | |
1683 | return count; | |
1684 | } | |
1685 | ||
66e3d5c0 | 1686 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1687 | { |
66e3d5c0 DV |
1688 | struct drm_device *dev = crtc->base.dev; |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1690 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1691 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1692 | |
66e3d5c0 | 1693 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1694 | |
63d7bbe9 | 1695 | /* No really, not for ILK+ */ |
3d13ef2e | 1696 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1697 | |
1698 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1699 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1700 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1701 | |
1c4e0274 VS |
1702 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1703 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1704 | /* | |
1705 | * It appears to be important that we don't enable this | |
1706 | * for the current pipe before otherwise configuring the | |
1707 | * PLL. No idea how this should be handled if multiple | |
1708 | * DVO outputs are enabled simultaneosly. | |
1709 | */ | |
1710 | dpll |= DPLL_DVO_2X_MODE; | |
1711 | I915_WRITE(DPLL(!crtc->pipe), | |
1712 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1713 | } | |
66e3d5c0 | 1714 | |
c2b63374 VS |
1715 | /* |
1716 | * Apparently we need to have VGA mode enabled prior to changing | |
1717 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1718 | * dividers, even though the register value does change. | |
1719 | */ | |
1720 | I915_WRITE(reg, 0); | |
1721 | ||
8e7a65aa VS |
1722 | I915_WRITE(reg, dpll); |
1723 | ||
66e3d5c0 DV |
1724 | /* Wait for the clocks to stabilize. */ |
1725 | POSTING_READ(reg); | |
1726 | udelay(150); | |
1727 | ||
1728 | if (INTEL_INFO(dev)->gen >= 4) { | |
1729 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1730 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1731 | } else { |
1732 | /* The pixel multiplier can only be updated once the | |
1733 | * DPLL is enabled and the clocks are stable. | |
1734 | * | |
1735 | * So write it again. | |
1736 | */ | |
1737 | I915_WRITE(reg, dpll); | |
1738 | } | |
63d7bbe9 JB |
1739 | |
1740 | /* We do this three times for luck */ | |
66e3d5c0 | 1741 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1742 | POSTING_READ(reg); |
1743 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1747 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1748 | POSTING_READ(reg); |
1749 | udelay(150); /* wait for warmup */ | |
1750 | } | |
1751 | ||
1752 | /** | |
50b44a44 | 1753 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1754 | * @dev_priv: i915 private structure |
1755 | * @pipe: pipe PLL to disable | |
1756 | * | |
1757 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1758 | * | |
1759 | * Note! This is for pre-ILK only. | |
1760 | */ | |
1c4e0274 | 1761 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1762 | { |
1c4e0274 VS |
1763 | struct drm_device *dev = crtc->base.dev; |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1765 | enum pipe pipe = crtc->pipe; | |
1766 | ||
1767 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1768 | if (IS_I830(dev) && | |
409ee761 | 1769 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1770 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1771 | I915_WRITE(DPLL(PIPE_B), |
1772 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1773 | I915_WRITE(DPLL(PIPE_A), | |
1774 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1775 | } | |
1776 | ||
b6b5d049 VS |
1777 | /* Don't disable pipe or pipe PLLs if needed */ |
1778 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1779 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1780 | return; |
1781 | ||
1782 | /* Make sure the pipe isn't still relying on us */ | |
1783 | assert_pipe_disabled(dev_priv, pipe); | |
1784 | ||
b8afb911 | 1785 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1786 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1787 | } |
1788 | ||
f6071166 JB |
1789 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1790 | { | |
b8afb911 | 1791 | u32 val; |
f6071166 JB |
1792 | |
1793 | /* Make sure the pipe isn't still relying on us */ | |
1794 | assert_pipe_disabled(dev_priv, pipe); | |
1795 | ||
e5cbfbfb ID |
1796 | /* |
1797 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1798 | * The latter is needed for VGA hotplug / manual detection. | |
1799 | */ | |
b8afb911 | 1800 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1801 | if (pipe == PIPE_B) |
60bfe44f | 1802 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1803 | I915_WRITE(DPLL(pipe), val); |
1804 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1805 | |
1806 | } | |
1807 | ||
1808 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1809 | { | |
d752048d | 1810 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1811 | u32 val; |
1812 | ||
a11b0703 VS |
1813 | /* Make sure the pipe isn't still relying on us */ |
1814 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1815 | |
a11b0703 | 1816 | /* Set PLL en = 0 */ |
60bfe44f VS |
1817 | val = DPLL_SSC_REF_CLK_CHV | |
1818 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1819 | if (pipe != PIPE_A) |
1820 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1821 | I915_WRITE(DPLL(pipe), val); | |
1822 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1823 | |
a580516d | 1824 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1825 | |
1826 | /* Disable 10bit clock to display controller */ | |
1827 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1828 | val &= ~DPIO_DCLKP_EN; | |
1829 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1830 | ||
a580516d | 1831 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1832 | } |
1833 | ||
e4607fcf | 1834 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1835 | struct intel_digital_port *dport, |
1836 | unsigned int expected_mask) | |
89b667f8 JB |
1837 | { |
1838 | u32 port_mask; | |
f0f59a00 | 1839 | i915_reg_t dpll_reg; |
89b667f8 | 1840 | |
e4607fcf CML |
1841 | switch (dport->port) { |
1842 | case PORT_B: | |
89b667f8 | 1843 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1844 | dpll_reg = DPLL(0); |
e4607fcf CML |
1845 | break; |
1846 | case PORT_C: | |
89b667f8 | 1847 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1848 | dpll_reg = DPLL(0); |
9b6de0a1 | 1849 | expected_mask <<= 4; |
00fc31b7 CML |
1850 | break; |
1851 | case PORT_D: | |
1852 | port_mask = DPLL_PORTD_READY_MASK; | |
1853 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1854 | break; |
1855 | default: | |
1856 | BUG(); | |
1857 | } | |
89b667f8 | 1858 | |
9b6de0a1 VS |
1859 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1860 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1861 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1862 | } |
1863 | ||
b14b1055 DV |
1864 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1865 | { | |
1866 | struct drm_device *dev = crtc->base.dev; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1869 | ||
be19f0ff CW |
1870 | if (WARN_ON(pll == NULL)) |
1871 | return; | |
1872 | ||
3e369b76 | 1873 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1874 | if (pll->active == 0) { |
1875 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1876 | WARN_ON(pll->on); | |
1877 | assert_shared_dpll_disabled(dev_priv, pll); | |
1878 | ||
1879 | pll->mode_set(dev_priv, pll); | |
1880 | } | |
1881 | } | |
1882 | ||
92f2584a | 1883 | /** |
85b3894f | 1884 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1885 | * @dev_priv: i915 private structure |
1886 | * @pipe: pipe PLL to enable | |
1887 | * | |
1888 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1889 | * drives the transcoder clock. | |
1890 | */ | |
85b3894f | 1891 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1892 | { |
3d13ef2e DL |
1893 | struct drm_device *dev = crtc->base.dev; |
1894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1895 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1896 | |
87a875bb | 1897 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1898 | return; |
1899 | ||
3e369b76 | 1900 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1901 | return; |
ee7b9f93 | 1902 | |
74dd6928 | 1903 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1904 | pll->name, pll->active, pll->on, |
e2b78267 | 1905 | crtc->base.base.id); |
92f2584a | 1906 | |
cdbd2316 DV |
1907 | if (pll->active++) { |
1908 | WARN_ON(!pll->on); | |
e9d6944e | 1909 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1910 | return; |
1911 | } | |
f4a091c7 | 1912 | WARN_ON(pll->on); |
ee7b9f93 | 1913 | |
bd2bb1b9 PZ |
1914 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1915 | ||
46edb027 | 1916 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1917 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1918 | pll->on = true; |
92f2584a JB |
1919 | } |
1920 | ||
f6daaec2 | 1921 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1922 | { |
3d13ef2e DL |
1923 | struct drm_device *dev = crtc->base.dev; |
1924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1925 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1926 | |
92f2584a | 1927 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1928 | if (INTEL_INFO(dev)->gen < 5) |
1929 | return; | |
1930 | ||
eddfcbcd ML |
1931 | if (pll == NULL) |
1932 | return; | |
92f2584a | 1933 | |
eddfcbcd | 1934 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1935 | return; |
7a419866 | 1936 | |
46edb027 DV |
1937 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1938 | pll->name, pll->active, pll->on, | |
e2b78267 | 1939 | crtc->base.base.id); |
7a419866 | 1940 | |
48da64a8 | 1941 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1942 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1943 | return; |
1944 | } | |
1945 | ||
e9d6944e | 1946 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1947 | WARN_ON(!pll->on); |
cdbd2316 | 1948 | if (--pll->active) |
7a419866 | 1949 | return; |
ee7b9f93 | 1950 | |
46edb027 | 1951 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1952 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1953 | pll->on = false; |
bd2bb1b9 PZ |
1954 | |
1955 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1956 | } |
1957 | ||
b8a4f404 PZ |
1958 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1959 | enum pipe pipe) | |
040484af | 1960 | { |
23670b32 | 1961 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1962 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1964 | i915_reg_t reg; |
1965 | uint32_t val, pipeconf_val; | |
040484af JB |
1966 | |
1967 | /* PCH only available on ILK+ */ | |
55522f37 | 1968 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1969 | |
1970 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1971 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1972 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1973 | |
1974 | /* FDI must be feeding us bits for PCH ports */ | |
1975 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1976 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1977 | ||
23670b32 DV |
1978 | if (HAS_PCH_CPT(dev)) { |
1979 | /* Workaround: Set the timing override bit before enabling the | |
1980 | * pch transcoder. */ | |
1981 | reg = TRANS_CHICKEN2(pipe); | |
1982 | val = I915_READ(reg); | |
1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1984 | I915_WRITE(reg, val); | |
59c859d6 | 1985 | } |
23670b32 | 1986 | |
ab9412ba | 1987 | reg = PCH_TRANSCONF(pipe); |
040484af | 1988 | val = I915_READ(reg); |
5f7f726d | 1989 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1990 | |
1991 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1992 | /* | |
c5de7c6f VS |
1993 | * Make the BPC in transcoder be consistent with |
1994 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1995 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1996 | */ |
dfd07d72 | 1997 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1998 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1999 | val |= PIPECONF_8BPC; | |
2000 | else | |
2001 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2002 | } |
5f7f726d PZ |
2003 | |
2004 | val &= ~TRANS_INTERLACE_MASK; | |
2005 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2006 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2007 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2008 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2009 | else | |
2010 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2011 | else |
2012 | val |= TRANS_PROGRESSIVE; | |
2013 | ||
040484af JB |
2014 | I915_WRITE(reg, val | TRANS_ENABLE); |
2015 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2016 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2017 | } |
2018 | ||
8fb033d7 | 2019 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2020 | enum transcoder cpu_transcoder) |
040484af | 2021 | { |
8fb033d7 | 2022 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2023 | |
2024 | /* PCH only available on ILK+ */ | |
55522f37 | 2025 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2026 | |
8fb033d7 | 2027 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2028 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2029 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2030 | |
223a6fdf | 2031 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2032 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2033 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2034 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2035 | |
25f3ef11 | 2036 | val = TRANS_ENABLE; |
937bb610 | 2037 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2038 | |
9a76b1c6 PZ |
2039 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2040 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2041 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2042 | else |
2043 | val |= TRANS_PROGRESSIVE; | |
2044 | ||
ab9412ba DV |
2045 | I915_WRITE(LPT_TRANSCONF, val); |
2046 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2047 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2048 | } |
2049 | ||
b8a4f404 PZ |
2050 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2051 | enum pipe pipe) | |
040484af | 2052 | { |
23670b32 | 2053 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2054 | i915_reg_t reg; |
2055 | uint32_t val; | |
040484af JB |
2056 | |
2057 | /* FDI relies on the transcoder */ | |
2058 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2059 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2060 | ||
291906f1 JB |
2061 | /* Ports must be off as well */ |
2062 | assert_pch_ports_disabled(dev_priv, pipe); | |
2063 | ||
ab9412ba | 2064 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2065 | val = I915_READ(reg); |
2066 | val &= ~TRANS_ENABLE; | |
2067 | I915_WRITE(reg, val); | |
2068 | /* wait for PCH transcoder off, transcoder state */ | |
2069 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2070 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2071 | |
c465613b | 2072 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2073 | /* Workaround: Clear the timing override chicken bit again. */ |
2074 | reg = TRANS_CHICKEN2(pipe); | |
2075 | val = I915_READ(reg); | |
2076 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2077 | I915_WRITE(reg, val); | |
2078 | } | |
040484af JB |
2079 | } |
2080 | ||
ab4d966c | 2081 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2082 | { |
8fb033d7 PZ |
2083 | u32 val; |
2084 | ||
ab9412ba | 2085 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2086 | val &= ~TRANS_ENABLE; |
ab9412ba | 2087 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2088 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2089 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2090 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2091 | |
2092 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2093 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2094 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2095 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2096 | } |
2097 | ||
b24e7179 | 2098 | /** |
309cfea8 | 2099 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2100 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2101 | * |
0372264a | 2102 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2103 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2104 | */ |
e1fdc473 | 2105 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2106 | { |
0372264a PZ |
2107 | struct drm_device *dev = crtc->base.dev; |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2110 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2111 | enum pipe pch_transcoder; |
f0f59a00 | 2112 | i915_reg_t reg; |
b24e7179 JB |
2113 | u32 val; |
2114 | ||
9e2ee2dd VS |
2115 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2116 | ||
58c6eaa2 | 2117 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2118 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2119 | assert_sprites_disabled(dev_priv, pipe); |
2120 | ||
681e5811 | 2121 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2122 | pch_transcoder = TRANSCODER_A; |
2123 | else | |
2124 | pch_transcoder = pipe; | |
2125 | ||
b24e7179 JB |
2126 | /* |
2127 | * A pipe without a PLL won't actually be able to drive bits from | |
2128 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2129 | * need the check. | |
2130 | */ | |
50360403 | 2131 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2132 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2133 | assert_dsi_pll_enabled(dev_priv); |
2134 | else | |
2135 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2136 | else { |
6e3c9717 | 2137 | if (crtc->config->has_pch_encoder) { |
040484af | 2138 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2139 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2140 | assert_fdi_tx_pll_enabled(dev_priv, |
2141 | (enum pipe) cpu_transcoder); | |
040484af JB |
2142 | } |
2143 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2144 | } | |
b24e7179 | 2145 | |
702e7a56 | 2146 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2147 | val = I915_READ(reg); |
7ad25d48 | 2148 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2149 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2150 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2151 | return; |
7ad25d48 | 2152 | } |
00d70b15 CW |
2153 | |
2154 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2155 | POSTING_READ(reg); |
b24e7179 JB |
2156 | } |
2157 | ||
2158 | /** | |
309cfea8 | 2159 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2160 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2161 | * |
575f7ab7 VS |
2162 | * Disable the pipe of @crtc, making sure that various hardware |
2163 | * specific requirements are met, if applicable, e.g. plane | |
2164 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2165 | * |
2166 | * Will wait until the pipe has shut down before returning. | |
2167 | */ | |
575f7ab7 | 2168 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2169 | { |
575f7ab7 | 2170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2171 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2172 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2173 | i915_reg_t reg; |
b24e7179 JB |
2174 | u32 val; |
2175 | ||
9e2ee2dd VS |
2176 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2177 | ||
b24e7179 JB |
2178 | /* |
2179 | * Make sure planes won't keep trying to pump pixels to us, | |
2180 | * or we might hang the display. | |
2181 | */ | |
2182 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2183 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2184 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2185 | |
702e7a56 | 2186 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2187 | val = I915_READ(reg); |
00d70b15 CW |
2188 | if ((val & PIPECONF_ENABLE) == 0) |
2189 | return; | |
2190 | ||
67adc644 VS |
2191 | /* |
2192 | * Double wide has implications for planes | |
2193 | * so best keep it disabled when not needed. | |
2194 | */ | |
6e3c9717 | 2195 | if (crtc->config->double_wide) |
67adc644 VS |
2196 | val &= ~PIPECONF_DOUBLE_WIDE; |
2197 | ||
2198 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2199 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2200 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2201 | val &= ~PIPECONF_ENABLE; |
2202 | ||
2203 | I915_WRITE(reg, val); | |
2204 | if ((val & PIPECONF_ENABLE) == 0) | |
2205 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2206 | } |
2207 | ||
693db184 CW |
2208 | static bool need_vtd_wa(struct drm_device *dev) |
2209 | { | |
2210 | #ifdef CONFIG_INTEL_IOMMU | |
2211 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2212 | return true; | |
2213 | #endif | |
2214 | return false; | |
2215 | } | |
2216 | ||
50470bb0 | 2217 | unsigned int |
6761dd31 | 2218 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2219 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2220 | { |
6761dd31 TU |
2221 | unsigned int tile_height; |
2222 | uint32_t pixel_bytes; | |
a57ce0b2 | 2223 | |
b5d0e9bf DL |
2224 | switch (fb_format_modifier) { |
2225 | case DRM_FORMAT_MOD_NONE: | |
2226 | tile_height = 1; | |
2227 | break; | |
2228 | case I915_FORMAT_MOD_X_TILED: | |
2229 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2230 | break; | |
2231 | case I915_FORMAT_MOD_Y_TILED: | |
2232 | tile_height = 32; | |
2233 | break; | |
2234 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2235 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2236 | switch (pixel_bytes) { |
b5d0e9bf | 2237 | default: |
6761dd31 | 2238 | case 1: |
b5d0e9bf DL |
2239 | tile_height = 64; |
2240 | break; | |
6761dd31 TU |
2241 | case 2: |
2242 | case 4: | |
b5d0e9bf DL |
2243 | tile_height = 32; |
2244 | break; | |
6761dd31 | 2245 | case 8: |
b5d0e9bf DL |
2246 | tile_height = 16; |
2247 | break; | |
6761dd31 | 2248 | case 16: |
b5d0e9bf DL |
2249 | WARN_ONCE(1, |
2250 | "128-bit pixels are not supported for display!"); | |
2251 | tile_height = 16; | |
2252 | break; | |
2253 | } | |
2254 | break; | |
2255 | default: | |
2256 | MISSING_CASE(fb_format_modifier); | |
2257 | tile_height = 1; | |
2258 | break; | |
2259 | } | |
091df6cb | 2260 | |
6761dd31 TU |
2261 | return tile_height; |
2262 | } | |
2263 | ||
2264 | unsigned int | |
2265 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2266 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2267 | { | |
2268 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2269 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2270 | } |
2271 | ||
75c82a53 | 2272 | static void |
f64b98cd TU |
2273 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2274 | const struct drm_plane_state *plane_state) | |
2275 | { | |
a6d09186 | 2276 | struct intel_rotation_info *info = &view->params.rotation_info; |
84fe03f7 | 2277 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2278 | |
f64b98cd TU |
2279 | *view = i915_ggtt_view_normal; |
2280 | ||
50470bb0 | 2281 | if (!plane_state) |
75c82a53 | 2282 | return; |
50470bb0 | 2283 | |
121920fa | 2284 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2285 | return; |
50470bb0 | 2286 | |
9abc4648 | 2287 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2288 | |
2289 | info->height = fb->height; | |
2290 | info->pixel_format = fb->pixel_format; | |
2291 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2292 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2293 | info->fb_modifier = fb->modifier[0]; |
2294 | ||
84fe03f7 | 2295 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2296 | fb->modifier[0], 0); |
84fe03f7 TU |
2297 | tile_pitch = PAGE_SIZE / tile_height; |
2298 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2299 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2300 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2301 | ||
89e3e142 TU |
2302 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2303 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2304 | fb->modifier[0], 1); | |
2305 | tile_pitch = PAGE_SIZE / tile_height; | |
2306 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2307 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2308 | tile_height); | |
2309 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2310 | PAGE_SIZE; | |
2311 | } | |
f64b98cd TU |
2312 | } |
2313 | ||
4e9a86b6 VS |
2314 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2315 | { | |
2316 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2317 | return 256 * 1024; | |
985b8bb4 | 2318 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2319 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2320 | return 128 * 1024; |
2321 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2322 | return 4 * 1024; | |
2323 | else | |
44c5905e | 2324 | return 0; |
4e9a86b6 VS |
2325 | } |
2326 | ||
127bd2ac | 2327 | int |
850c4cdc TU |
2328 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2329 | struct drm_framebuffer *fb, | |
7580d774 | 2330 | const struct drm_plane_state *plane_state) |
6b95a207 | 2331 | { |
850c4cdc | 2332 | struct drm_device *dev = fb->dev; |
ce453d81 | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2334 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2335 | struct i915_ggtt_view view; |
6b95a207 KH |
2336 | u32 alignment; |
2337 | int ret; | |
2338 | ||
ebcdd39e MR |
2339 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2340 | ||
7b911adc TU |
2341 | switch (fb->modifier[0]) { |
2342 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2343 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2344 | break; |
7b911adc | 2345 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2346 | if (INTEL_INFO(dev)->gen >= 9) |
2347 | alignment = 256 * 1024; | |
2348 | else { | |
2349 | /* pin() will align the object as required by fence */ | |
2350 | alignment = 0; | |
2351 | } | |
6b95a207 | 2352 | break; |
7b911adc | 2353 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2354 | case I915_FORMAT_MOD_Yf_TILED: |
2355 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2356 | "Y tiling bo slipped through, driver bug!\n")) | |
2357 | return -EINVAL; | |
2358 | alignment = 1 * 1024 * 1024; | |
2359 | break; | |
6b95a207 | 2360 | default: |
7b911adc TU |
2361 | MISSING_CASE(fb->modifier[0]); |
2362 | return -EINVAL; | |
6b95a207 KH |
2363 | } |
2364 | ||
75c82a53 | 2365 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2366 | |
693db184 CW |
2367 | /* Note that the w/a also requires 64 PTE of padding following the |
2368 | * bo. We currently fill all unused PTE with the shadow page and so | |
2369 | * we should always have valid PTE following the scanout preventing | |
2370 | * the VT-d warning. | |
2371 | */ | |
2372 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2373 | alignment = 256 * 1024; | |
2374 | ||
d6dd6843 PZ |
2375 | /* |
2376 | * Global gtt pte registers are special registers which actually forward | |
2377 | * writes to a chunk of system memory. Which means that there is no risk | |
2378 | * that the register values disappear as soon as we call | |
2379 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2380 | * pin/unpin/fence and not more. | |
2381 | */ | |
2382 | intel_runtime_pm_get(dev_priv); | |
2383 | ||
7580d774 ML |
2384 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2385 | &view); | |
48b956c5 | 2386 | if (ret) |
b26a6b35 | 2387 | goto err_pm; |
6b95a207 KH |
2388 | |
2389 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2390 | * fence, whereas 965+ only requires a fence if using | |
2391 | * framebuffer compression. For simplicity, we always install | |
2392 | * a fence as the cost is not that onerous. | |
2393 | */ | |
9807216f VK |
2394 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2395 | ret = i915_gem_object_get_fence(obj); | |
2396 | if (ret == -EDEADLK) { | |
2397 | /* | |
2398 | * -EDEADLK means there are no free fences | |
2399 | * no pending flips. | |
2400 | * | |
2401 | * This is propagated to atomic, but it uses | |
2402 | * -EDEADLK to force a locking recovery, so | |
2403 | * change the returned error to -EBUSY. | |
2404 | */ | |
2405 | ret = -EBUSY; | |
2406 | goto err_unpin; | |
2407 | } else if (ret) | |
2408 | goto err_unpin; | |
1690e1eb | 2409 | |
9807216f VK |
2410 | i915_gem_object_pin_fence(obj); |
2411 | } | |
6b95a207 | 2412 | |
d6dd6843 | 2413 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2414 | return 0; |
48b956c5 CW |
2415 | |
2416 | err_unpin: | |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2418 | err_pm: |
d6dd6843 | 2419 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2420 | return ret; |
6b95a207 KH |
2421 | } |
2422 | ||
82bc3b2d TU |
2423 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2424 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2425 | { |
82bc3b2d | 2426 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2427 | struct i915_ggtt_view view; |
82bc3b2d | 2428 | |
ebcdd39e MR |
2429 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2430 | ||
75c82a53 | 2431 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2432 | |
9807216f VK |
2433 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2434 | i915_gem_object_unpin_fence(obj); | |
2435 | ||
f64b98cd | 2436 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2437 | } |
2438 | ||
c2c75131 DV |
2439 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2440 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2441 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2442 | int *x, int *y, | |
bc752862 CW |
2443 | unsigned int tiling_mode, |
2444 | unsigned int cpp, | |
2445 | unsigned int pitch) | |
c2c75131 | 2446 | { |
bc752862 CW |
2447 | if (tiling_mode != I915_TILING_NONE) { |
2448 | unsigned int tile_rows, tiles; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tile_rows = *y / 8; |
2451 | *y %= 8; | |
c2c75131 | 2452 | |
bc752862 CW |
2453 | tiles = *x / (512/cpp); |
2454 | *x %= 512/cpp; | |
2455 | ||
2456 | return tile_rows * pitch * 8 + tiles * 4096; | |
2457 | } else { | |
4e9a86b6 | 2458 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2459 | unsigned int offset; |
2460 | ||
2461 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2462 | *y = (offset & alignment) / pitch; |
2463 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2464 | return offset & ~alignment; | |
bc752862 | 2465 | } |
c2c75131 DV |
2466 | } |
2467 | ||
b35d63fa | 2468 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2469 | { |
2470 | switch (format) { | |
2471 | case DISPPLANE_8BPP: | |
2472 | return DRM_FORMAT_C8; | |
2473 | case DISPPLANE_BGRX555: | |
2474 | return DRM_FORMAT_XRGB1555; | |
2475 | case DISPPLANE_BGRX565: | |
2476 | return DRM_FORMAT_RGB565; | |
2477 | default: | |
2478 | case DISPPLANE_BGRX888: | |
2479 | return DRM_FORMAT_XRGB8888; | |
2480 | case DISPPLANE_RGBX888: | |
2481 | return DRM_FORMAT_XBGR8888; | |
2482 | case DISPPLANE_BGRX101010: | |
2483 | return DRM_FORMAT_XRGB2101010; | |
2484 | case DISPPLANE_RGBX101010: | |
2485 | return DRM_FORMAT_XBGR2101010; | |
2486 | } | |
2487 | } | |
2488 | ||
bc8d7dff DL |
2489 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2490 | { | |
2491 | switch (format) { | |
2492 | case PLANE_CTL_FORMAT_RGB_565: | |
2493 | return DRM_FORMAT_RGB565; | |
2494 | default: | |
2495 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2496 | if (rgb_order) { | |
2497 | if (alpha) | |
2498 | return DRM_FORMAT_ABGR8888; | |
2499 | else | |
2500 | return DRM_FORMAT_XBGR8888; | |
2501 | } else { | |
2502 | if (alpha) | |
2503 | return DRM_FORMAT_ARGB8888; | |
2504 | else | |
2505 | return DRM_FORMAT_XRGB8888; | |
2506 | } | |
2507 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2508 | if (rgb_order) | |
2509 | return DRM_FORMAT_XBGR2101010; | |
2510 | else | |
2511 | return DRM_FORMAT_XRGB2101010; | |
2512 | } | |
2513 | } | |
2514 | ||
5724dbd1 | 2515 | static bool |
f6936e29 DV |
2516 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2517 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2518 | { |
2519 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2520 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2521 | struct drm_i915_gem_object *obj = NULL; |
2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2526 | PAGE_SIZE); | |
2527 | ||
2528 | size_aligned -= base_aligned; | |
46f297fb | 2529 | |
ff2652ea CW |
2530 | if (plane_config->size == 0) |
2531 | return false; | |
2532 | ||
3badb49f PZ |
2533 | /* If the FB is too big, just don't use it since fbdev is not very |
2534 | * important and we should probably use that space with FBC or other | |
2535 | * features. */ | |
2536 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2537 | return false; | |
2538 | ||
f37b5c2b DV |
2539 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2540 | base_aligned, | |
2541 | base_aligned, | |
2542 | size_aligned); | |
46f297fb | 2543 | if (!obj) |
484b41dd | 2544 | return false; |
46f297fb | 2545 | |
49af449b DL |
2546 | obj->tiling_mode = plane_config->tiling; |
2547 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2548 | obj->stride = fb->pitches[0]; |
46f297fb | 2549 | |
6bf129df DL |
2550 | mode_cmd.pixel_format = fb->pixel_format; |
2551 | mode_cmd.width = fb->width; | |
2552 | mode_cmd.height = fb->height; | |
2553 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2554 | mode_cmd.modifier[0] = fb->modifier[0]; |
2555 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2556 | |
2557 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2558 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2559 | &mode_cmd, obj)) { |
46f297fb JB |
2560 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2561 | goto out_unref_obj; | |
2562 | } | |
46f297fb | 2563 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2564 | |
f6936e29 | 2565 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2566 | return true; |
46f297fb JB |
2567 | |
2568 | out_unref_obj: | |
2569 | drm_gem_object_unreference(&obj->base); | |
2570 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2571 | return false; |
2572 | } | |
2573 | ||
afd65eb4 MR |
2574 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2575 | static void | |
2576 | update_state_fb(struct drm_plane *plane) | |
2577 | { | |
2578 | if (plane->fb == plane->state->fb) | |
2579 | return; | |
2580 | ||
2581 | if (plane->state->fb) | |
2582 | drm_framebuffer_unreference(plane->state->fb); | |
2583 | plane->state->fb = plane->fb; | |
2584 | if (plane->state->fb) | |
2585 | drm_framebuffer_reference(plane->state->fb); | |
2586 | } | |
2587 | ||
5724dbd1 | 2588 | static void |
f6936e29 DV |
2589 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2590 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2591 | { |
2592 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2593 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2594 | struct drm_crtc *c; |
2595 | struct intel_crtc *i; | |
2ff8fde1 | 2596 | struct drm_i915_gem_object *obj; |
88595ac9 | 2597 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2598 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2599 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2600 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
88595ac9 | 2601 | struct drm_framebuffer *fb; |
484b41dd | 2602 | |
2d14030b | 2603 | if (!plane_config->fb) |
484b41dd JB |
2604 | return; |
2605 | ||
f6936e29 | 2606 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2607 | fb = &plane_config->fb->base; |
2608 | goto valid_fb; | |
f55548b5 | 2609 | } |
484b41dd | 2610 | |
2d14030b | 2611 | kfree(plane_config->fb); |
484b41dd JB |
2612 | |
2613 | /* | |
2614 | * Failed to alloc the obj, check to see if we should share | |
2615 | * an fb with another CRTC instead | |
2616 | */ | |
70e1e0ec | 2617 | for_each_crtc(dev, c) { |
484b41dd JB |
2618 | i = to_intel_crtc(c); |
2619 | ||
2620 | if (c == &intel_crtc->base) | |
2621 | continue; | |
2622 | ||
2ff8fde1 MR |
2623 | if (!i->active) |
2624 | continue; | |
2625 | ||
88595ac9 DV |
2626 | fb = c->primary->fb; |
2627 | if (!fb) | |
484b41dd JB |
2628 | continue; |
2629 | ||
88595ac9 | 2630 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2631 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2632 | drm_framebuffer_reference(fb); |
2633 | goto valid_fb; | |
484b41dd JB |
2634 | } |
2635 | } | |
88595ac9 | 2636 | |
200757f5 MR |
2637 | /* |
2638 | * We've failed to reconstruct the BIOS FB. Current display state | |
2639 | * indicates that the primary plane is visible, but has a NULL FB, | |
2640 | * which will lead to problems later if we don't fix it up. The | |
2641 | * simplest solution is to just disable the primary plane now and | |
2642 | * pretend the BIOS never had it enabled. | |
2643 | */ | |
2644 | to_intel_plane_state(plane_state)->visible = false; | |
2645 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2646 | intel_pre_disable_primary(&intel_crtc->base); | |
2647 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2648 | ||
88595ac9 DV |
2649 | return; |
2650 | ||
2651 | valid_fb: | |
f44e2659 VS |
2652 | plane_state->src_x = 0; |
2653 | plane_state->src_y = 0; | |
be5651f2 ML |
2654 | plane_state->src_w = fb->width << 16; |
2655 | plane_state->src_h = fb->height << 16; | |
2656 | ||
f44e2659 VS |
2657 | plane_state->crtc_x = 0; |
2658 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2659 | plane_state->crtc_w = fb->width; |
2660 | plane_state->crtc_h = fb->height; | |
2661 | ||
88595ac9 DV |
2662 | obj = intel_fb_obj(fb); |
2663 | if (obj->tiling_mode != I915_TILING_NONE) | |
2664 | dev_priv->preserve_bios_swizzle = true; | |
2665 | ||
be5651f2 ML |
2666 | drm_framebuffer_reference(fb); |
2667 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2668 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2669 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2670 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2671 | } |
2672 | ||
29b9bde6 DV |
2673 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2674 | struct drm_framebuffer *fb, | |
2675 | int x, int y) | |
81255565 JB |
2676 | { |
2677 | struct drm_device *dev = crtc->dev; | |
2678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2680 | struct drm_plane *primary = crtc->primary; |
2681 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2682 | struct drm_i915_gem_object *obj; |
81255565 | 2683 | int plane = intel_crtc->plane; |
e506a0c6 | 2684 | unsigned long linear_offset; |
81255565 | 2685 | u32 dspcntr; |
f0f59a00 | 2686 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2687 | int pixel_size; |
f45651ba | 2688 | |
b70709a6 | 2689 | if (!visible || !fb) { |
fdd508a6 VS |
2690 | I915_WRITE(reg, 0); |
2691 | if (INTEL_INFO(dev)->gen >= 4) | |
2692 | I915_WRITE(DSPSURF(plane), 0); | |
2693 | else | |
2694 | I915_WRITE(DSPADDR(plane), 0); | |
2695 | POSTING_READ(reg); | |
2696 | return; | |
2697 | } | |
2698 | ||
c9ba6fad VS |
2699 | obj = intel_fb_obj(fb); |
2700 | if (WARN_ON(obj == NULL)) | |
2701 | return; | |
2702 | ||
2703 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2704 | ||
f45651ba VS |
2705 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2706 | ||
fdd508a6 | 2707 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2708 | |
2709 | if (INTEL_INFO(dev)->gen < 4) { | |
2710 | if (intel_crtc->pipe == PIPE_B) | |
2711 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2712 | ||
2713 | /* pipesrc and dspsize control the size that is scaled from, | |
2714 | * which should always be the user's requested size. | |
2715 | */ | |
2716 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2717 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2718 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2719 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2720 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2721 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2722 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2723 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2724 | I915_WRITE(PRIMPOS(plane), 0); |
2725 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2726 | } |
81255565 | 2727 | |
57779d06 VS |
2728 | switch (fb->pixel_format) { |
2729 | case DRM_FORMAT_C8: | |
81255565 JB |
2730 | dspcntr |= DISPPLANE_8BPP; |
2731 | break; | |
57779d06 | 2732 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2733 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2734 | break; |
57779d06 VS |
2735 | case DRM_FORMAT_RGB565: |
2736 | dspcntr |= DISPPLANE_BGRX565; | |
2737 | break; | |
2738 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2739 | dspcntr |= DISPPLANE_BGRX888; |
2740 | break; | |
2741 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2742 | dspcntr |= DISPPLANE_RGBX888; |
2743 | break; | |
2744 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2745 | dspcntr |= DISPPLANE_BGRX101010; |
2746 | break; | |
2747 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2748 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2749 | break; |
2750 | default: | |
baba133a | 2751 | BUG(); |
81255565 | 2752 | } |
57779d06 | 2753 | |
f45651ba VS |
2754 | if (INTEL_INFO(dev)->gen >= 4 && |
2755 | obj->tiling_mode != I915_TILING_NONE) | |
2756 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2757 | |
de1aa629 VS |
2758 | if (IS_G4X(dev)) |
2759 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2760 | ||
b9897127 | 2761 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2762 | |
c2c75131 DV |
2763 | if (INTEL_INFO(dev)->gen >= 4) { |
2764 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2765 | intel_gen4_compute_page_offset(dev_priv, |
2766 | &x, &y, obj->tiling_mode, | |
b9897127 | 2767 | pixel_size, |
bc752862 | 2768 | fb->pitches[0]); |
c2c75131 DV |
2769 | linear_offset -= intel_crtc->dspaddr_offset; |
2770 | } else { | |
e506a0c6 | 2771 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2772 | } |
e506a0c6 | 2773 | |
8e7d688b | 2774 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2775 | dspcntr |= DISPPLANE_ROTATE_180; |
2776 | ||
6e3c9717 ACO |
2777 | x += (intel_crtc->config->pipe_src_w - 1); |
2778 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2779 | |
2780 | /* Finding the last pixel of the last line of the display | |
2781 | data and adding to linear_offset*/ | |
2782 | linear_offset += | |
6e3c9717 ACO |
2783 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2784 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2785 | } |
2786 | ||
2db3366b PZ |
2787 | intel_crtc->adjusted_x = x; |
2788 | intel_crtc->adjusted_y = y; | |
2789 | ||
48404c1e SJ |
2790 | I915_WRITE(reg, dspcntr); |
2791 | ||
01f2c773 | 2792 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2793 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2794 | I915_WRITE(DSPSURF(plane), |
2795 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2796 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2797 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2798 | } else |
f343c5f6 | 2799 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2800 | POSTING_READ(reg); |
17638cd6 JB |
2801 | } |
2802 | ||
29b9bde6 DV |
2803 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2804 | struct drm_framebuffer *fb, | |
2805 | int x, int y) | |
17638cd6 JB |
2806 | { |
2807 | struct drm_device *dev = crtc->dev; | |
2808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2810 | struct drm_plane *primary = crtc->primary; |
2811 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2812 | struct drm_i915_gem_object *obj; |
17638cd6 | 2813 | int plane = intel_crtc->plane; |
e506a0c6 | 2814 | unsigned long linear_offset; |
17638cd6 | 2815 | u32 dspcntr; |
f0f59a00 | 2816 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2817 | int pixel_size; |
f45651ba | 2818 | |
b70709a6 | 2819 | if (!visible || !fb) { |
fdd508a6 VS |
2820 | I915_WRITE(reg, 0); |
2821 | I915_WRITE(DSPSURF(plane), 0); | |
2822 | POSTING_READ(reg); | |
2823 | return; | |
2824 | } | |
2825 | ||
c9ba6fad VS |
2826 | obj = intel_fb_obj(fb); |
2827 | if (WARN_ON(obj == NULL)) | |
2828 | return; | |
2829 | ||
2830 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2831 | ||
f45651ba VS |
2832 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2833 | ||
fdd508a6 | 2834 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2835 | |
2836 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2837 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2838 | |
57779d06 VS |
2839 | switch (fb->pixel_format) { |
2840 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2841 | dspcntr |= DISPPLANE_8BPP; |
2842 | break; | |
57779d06 VS |
2843 | case DRM_FORMAT_RGB565: |
2844 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2845 | break; |
57779d06 | 2846 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2847 | dspcntr |= DISPPLANE_BGRX888; |
2848 | break; | |
2849 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2850 | dspcntr |= DISPPLANE_RGBX888; |
2851 | break; | |
2852 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2853 | dspcntr |= DISPPLANE_BGRX101010; |
2854 | break; | |
2855 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2856 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2857 | break; |
2858 | default: | |
baba133a | 2859 | BUG(); |
17638cd6 JB |
2860 | } |
2861 | ||
2862 | if (obj->tiling_mode != I915_TILING_NONE) | |
2863 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2864 | |
f45651ba | 2865 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2866 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2867 | |
b9897127 | 2868 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2869 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2870 | intel_gen4_compute_page_offset(dev_priv, |
2871 | &x, &y, obj->tiling_mode, | |
b9897127 | 2872 | pixel_size, |
bc752862 | 2873 | fb->pitches[0]); |
c2c75131 | 2874 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2875 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2876 | dspcntr |= DISPPLANE_ROTATE_180; |
2877 | ||
2878 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2879 | x += (intel_crtc->config->pipe_src_w - 1); |
2880 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2881 | |
2882 | /* Finding the last pixel of the last line of the display | |
2883 | data and adding to linear_offset*/ | |
2884 | linear_offset += | |
6e3c9717 ACO |
2885 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2886 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2887 | } |
2888 | } | |
2889 | ||
2db3366b PZ |
2890 | intel_crtc->adjusted_x = x; |
2891 | intel_crtc->adjusted_y = y; | |
2892 | ||
48404c1e | 2893 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2894 | |
01f2c773 | 2895 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2896 | I915_WRITE(DSPSURF(plane), |
2897 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2898 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2899 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2900 | } else { | |
2901 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2902 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2903 | } | |
17638cd6 | 2904 | POSTING_READ(reg); |
17638cd6 JB |
2905 | } |
2906 | ||
b321803d DL |
2907 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2908 | uint32_t pixel_format) | |
2909 | { | |
2910 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2911 | ||
2912 | /* | |
2913 | * The stride is either expressed as a multiple of 64 bytes | |
2914 | * chunks for linear buffers or in number of tiles for tiled | |
2915 | * buffers. | |
2916 | */ | |
2917 | switch (fb_modifier) { | |
2918 | case DRM_FORMAT_MOD_NONE: | |
2919 | return 64; | |
2920 | case I915_FORMAT_MOD_X_TILED: | |
2921 | if (INTEL_INFO(dev)->gen == 2) | |
2922 | return 128; | |
2923 | return 512; | |
2924 | case I915_FORMAT_MOD_Y_TILED: | |
2925 | /* No need to check for old gens and Y tiling since this is | |
2926 | * about the display engine and those will be blocked before | |
2927 | * we get here. | |
2928 | */ | |
2929 | return 128; | |
2930 | case I915_FORMAT_MOD_Yf_TILED: | |
2931 | if (bits_per_pixel == 8) | |
2932 | return 64; | |
2933 | else | |
2934 | return 128; | |
2935 | default: | |
2936 | MISSING_CASE(fb_modifier); | |
2937 | return 64; | |
2938 | } | |
2939 | } | |
2940 | ||
44eb0cb9 MK |
2941 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2942 | struct drm_i915_gem_object *obj, | |
2943 | unsigned int plane) | |
121920fa | 2944 | { |
ce7f1728 | 2945 | struct i915_ggtt_view view; |
dedf278c | 2946 | struct i915_vma *vma; |
44eb0cb9 | 2947 | u64 offset; |
121920fa | 2948 | |
ce7f1728 DV |
2949 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2950 | intel_plane->base.state); | |
121920fa | 2951 | |
ce7f1728 | 2952 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2953 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2954 | view.type)) |
dedf278c TU |
2955 | return -1; |
2956 | ||
44eb0cb9 | 2957 | offset = vma->node.start; |
dedf278c TU |
2958 | |
2959 | if (plane == 1) { | |
a6d09186 | 2960 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2961 | PAGE_SIZE; |
2962 | } | |
2963 | ||
44eb0cb9 MK |
2964 | WARN_ON(upper_32_bits(offset)); |
2965 | ||
2966 | return lower_32_bits(offset); | |
121920fa TU |
2967 | } |
2968 | ||
e435d6e5 ML |
2969 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2970 | { | |
2971 | struct drm_device *dev = intel_crtc->base.dev; | |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2973 | ||
2974 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2975 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2976 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2977 | } |
2978 | ||
a1b2278e CK |
2979 | /* |
2980 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2981 | */ | |
0583236e | 2982 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2983 | { |
a1b2278e CK |
2984 | struct intel_crtc_scaler_state *scaler_state; |
2985 | int i; | |
2986 | ||
a1b2278e CK |
2987 | scaler_state = &intel_crtc->config->scaler_state; |
2988 | ||
2989 | /* loop through and disable scalers that aren't in use */ | |
2990 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2991 | if (!scaler_state->scalers[i].in_use) |
2992 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2993 | } |
2994 | } | |
2995 | ||
6156a456 | 2996 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2997 | { |
6156a456 | 2998 | switch (pixel_format) { |
d161cf7a | 2999 | case DRM_FORMAT_C8: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3001 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3002 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3003 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3004 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3005 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3006 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3007 | /* |
3008 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3009 | * to be already pre-multiplied. We need to add a knob (or a different | |
3010 | * DRM_FORMAT) for user-space to configure that. | |
3011 | */ | |
f75fb42a | 3012 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3014 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3015 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3017 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3018 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3020 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3021 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3022 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3023 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3024 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3025 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3026 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3027 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3028 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3029 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3030 | default: |
4249eeef | 3031 | MISSING_CASE(pixel_format); |
70d21f0e | 3032 | } |
8cfcba41 | 3033 | |
c34ce3d1 | 3034 | return 0; |
6156a456 | 3035 | } |
70d21f0e | 3036 | |
6156a456 CK |
3037 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3038 | { | |
6156a456 | 3039 | switch (fb_modifier) { |
30af77c4 | 3040 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3041 | break; |
30af77c4 | 3042 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3043 | return PLANE_CTL_TILED_X; |
b321803d | 3044 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3045 | return PLANE_CTL_TILED_Y; |
b321803d | 3046 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3047 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3048 | default: |
6156a456 | 3049 | MISSING_CASE(fb_modifier); |
70d21f0e | 3050 | } |
8cfcba41 | 3051 | |
c34ce3d1 | 3052 | return 0; |
6156a456 | 3053 | } |
70d21f0e | 3054 | |
6156a456 CK |
3055 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3056 | { | |
3b7a5119 | 3057 | switch (rotation) { |
6156a456 CK |
3058 | case BIT(DRM_ROTATE_0): |
3059 | break; | |
1e8df167 SJ |
3060 | /* |
3061 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3062 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3063 | */ | |
3b7a5119 | 3064 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3065 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3066 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3067 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3068 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3069 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3070 | default: |
3071 | MISSING_CASE(rotation); | |
3072 | } | |
3073 | ||
c34ce3d1 | 3074 | return 0; |
6156a456 CK |
3075 | } |
3076 | ||
3077 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3078 | struct drm_framebuffer *fb, | |
3079 | int x, int y) | |
3080 | { | |
3081 | struct drm_device *dev = crtc->dev; | |
3082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3084 | struct drm_plane *plane = crtc->primary; |
3085 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3086 | struct drm_i915_gem_object *obj; |
3087 | int pipe = intel_crtc->pipe; | |
3088 | u32 plane_ctl, stride_div, stride; | |
3089 | u32 tile_height, plane_offset, plane_size; | |
3090 | unsigned int rotation; | |
3091 | int x_offset, y_offset; | |
44eb0cb9 | 3092 | u32 surf_addr; |
6156a456 CK |
3093 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3094 | struct intel_plane_state *plane_state; | |
3095 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3096 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3097 | int scaler_id = -1; | |
3098 | ||
6156a456 CK |
3099 | plane_state = to_intel_plane_state(plane->state); |
3100 | ||
b70709a6 | 3101 | if (!visible || !fb) { |
6156a456 CK |
3102 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3103 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3104 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3105 | return; | |
3b7a5119 | 3106 | } |
70d21f0e | 3107 | |
6156a456 CK |
3108 | plane_ctl = PLANE_CTL_ENABLE | |
3109 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3110 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3111 | ||
3112 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3113 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3114 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3115 | ||
3116 | rotation = plane->state->rotation; | |
3117 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3118 | ||
b321803d DL |
3119 | obj = intel_fb_obj(fb); |
3120 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3121 | fb->pixel_format); | |
dedf278c | 3122 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3123 | |
a42e5a23 PZ |
3124 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3125 | ||
3126 | scaler_id = plane_state->scaler_id; | |
3127 | src_x = plane_state->src.x1 >> 16; | |
3128 | src_y = plane_state->src.y1 >> 16; | |
3129 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3130 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3131 | dst_x = plane_state->dst.x1; | |
3132 | dst_y = plane_state->dst.y1; | |
3133 | dst_w = drm_rect_width(&plane_state->dst); | |
3134 | dst_h = drm_rect_height(&plane_state->dst); | |
3135 | ||
3136 | WARN_ON(x != src_x || y != src_y); | |
6156a456 | 3137 | |
3b7a5119 SJ |
3138 | if (intel_rotation_90_or_270(rotation)) { |
3139 | /* stride = Surface height in tiles */ | |
2614f17d | 3140 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3141 | fb->modifier[0], 0); |
3b7a5119 | 3142 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3143 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3144 | y_offset = x; |
6156a456 | 3145 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3146 | } else { |
3147 | stride = fb->pitches[0] / stride_div; | |
3148 | x_offset = x; | |
3149 | y_offset = y; | |
6156a456 | 3150 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3151 | } |
3152 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3153 | |
2db3366b PZ |
3154 | intel_crtc->adjusted_x = x_offset; |
3155 | intel_crtc->adjusted_y = y_offset; | |
3156 | ||
70d21f0e | 3157 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3158 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3159 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3160 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3161 | |
3162 | if (scaler_id >= 0) { | |
3163 | uint32_t ps_ctrl = 0; | |
3164 | ||
3165 | WARN_ON(!dst_w || !dst_h); | |
3166 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3167 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3168 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3169 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3170 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3171 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3172 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3173 | } else { | |
3174 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3175 | } | |
3176 | ||
121920fa | 3177 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3178 | |
3179 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3180 | } | |
3181 | ||
17638cd6 JB |
3182 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3183 | static int | |
3184 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3185 | int x, int y, enum mode_set_atomic state) | |
3186 | { | |
3187 | struct drm_device *dev = crtc->dev; | |
3188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3189 | |
0e631adc PZ |
3190 | if (dev_priv->fbc.deactivate) |
3191 | dev_priv->fbc.deactivate(dev_priv); | |
81255565 | 3192 | |
29b9bde6 DV |
3193 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3194 | ||
3195 | return 0; | |
81255565 JB |
3196 | } |
3197 | ||
7514747d | 3198 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3199 | { |
96a02917 VS |
3200 | struct drm_crtc *crtc; |
3201 | ||
70e1e0ec | 3202 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3204 | enum plane plane = intel_crtc->plane; | |
3205 | ||
3206 | intel_prepare_page_flip(dev, plane); | |
3207 | intel_finish_page_flip_plane(dev, plane); | |
3208 | } | |
7514747d VS |
3209 | } |
3210 | ||
3211 | static void intel_update_primary_planes(struct drm_device *dev) | |
3212 | { | |
7514747d | 3213 | struct drm_crtc *crtc; |
96a02917 | 3214 | |
70e1e0ec | 3215 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3216 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3217 | struct intel_plane_state *plane_state; | |
96a02917 | 3218 | |
11c22da6 | 3219 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3220 | plane_state = to_intel_plane_state(plane->base.state); |
3221 | ||
f029ee82 | 3222 | if (crtc->state->active && plane_state->base.fb) |
11c22da6 ML |
3223 | plane->commit_plane(&plane->base, plane_state); |
3224 | ||
3225 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3226 | } |
3227 | } | |
3228 | ||
7514747d VS |
3229 | void intel_prepare_reset(struct drm_device *dev) |
3230 | { | |
3231 | /* no reset support for gen2 */ | |
3232 | if (IS_GEN2(dev)) | |
3233 | return; | |
3234 | ||
3235 | /* reset doesn't touch the display */ | |
3236 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3237 | return; | |
3238 | ||
3239 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3240 | /* |
3241 | * Disabling the crtcs gracefully seems nicer. Also the | |
3242 | * g33 docs say we should at least disable all the planes. | |
3243 | */ | |
6b72d486 | 3244 | intel_display_suspend(dev); |
7514747d VS |
3245 | } |
3246 | ||
3247 | void intel_finish_reset(struct drm_device *dev) | |
3248 | { | |
3249 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3250 | ||
3251 | /* | |
3252 | * Flips in the rings will be nuked by the reset, | |
3253 | * so complete all pending flips so that user space | |
3254 | * will get its events and not get stuck. | |
3255 | */ | |
3256 | intel_complete_page_flips(dev); | |
3257 | ||
3258 | /* no reset support for gen2 */ | |
3259 | if (IS_GEN2(dev)) | |
3260 | return; | |
3261 | ||
3262 | /* reset doesn't touch the display */ | |
3263 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3264 | /* | |
3265 | * Flips in the rings have been nuked by the reset, | |
3266 | * so update the base address of all primary | |
3267 | * planes to the the last fb to make sure we're | |
3268 | * showing the correct fb after a reset. | |
11c22da6 ML |
3269 | * |
3270 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3271 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3272 | */ |
3273 | intel_update_primary_planes(dev); | |
3274 | return; | |
3275 | } | |
3276 | ||
3277 | /* | |
3278 | * The display has been reset as well, | |
3279 | * so need a full re-initialization. | |
3280 | */ | |
3281 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3282 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3283 | ||
3284 | intel_modeset_init_hw(dev); | |
3285 | ||
3286 | spin_lock_irq(&dev_priv->irq_lock); | |
3287 | if (dev_priv->display.hpd_irq_setup) | |
3288 | dev_priv->display.hpd_irq_setup(dev); | |
3289 | spin_unlock_irq(&dev_priv->irq_lock); | |
3290 | ||
043e9bda | 3291 | intel_display_resume(dev); |
7514747d VS |
3292 | |
3293 | intel_hpd_init(dev_priv); | |
3294 | ||
3295 | drm_modeset_unlock_all(dev); | |
3296 | } | |
3297 | ||
7d5e3799 CW |
3298 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3299 | { | |
3300 | struct drm_device *dev = crtc->dev; | |
3301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3303 | bool pending; |
3304 | ||
3305 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3306 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3307 | return false; | |
3308 | ||
5e2d7afc | 3309 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3310 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3311 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3312 | |
3313 | return pending; | |
3314 | } | |
3315 | ||
bfd16b2a ML |
3316 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3317 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3318 | { |
3319 | struct drm_device *dev = crtc->base.dev; | |
3320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3321 | struct intel_crtc_state *pipe_config = |
3322 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3323 | |
bfd16b2a ML |
3324 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3325 | crtc->base.mode = crtc->base.state->mode; | |
3326 | ||
3327 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3328 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3329 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3330 | |
44522d85 ML |
3331 | if (HAS_DDI(dev)) |
3332 | intel_set_pipe_csc(&crtc->base); | |
3333 | ||
e30e8f75 GP |
3334 | /* |
3335 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3336 | * that in compute_mode_changes we check the native mode (not the pfit | |
3337 | * mode) to see if we can flip rather than do a full mode set. In the | |
3338 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3339 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3340 | * sized surface. | |
e30e8f75 GP |
3341 | */ |
3342 | ||
e30e8f75 | 3343 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3344 | ((pipe_config->pipe_src_w - 1) << 16) | |
3345 | (pipe_config->pipe_src_h - 1)); | |
3346 | ||
3347 | /* on skylake this is done by detaching scalers */ | |
3348 | if (INTEL_INFO(dev)->gen >= 9) { | |
3349 | skl_detach_scalers(crtc); | |
3350 | ||
3351 | if (pipe_config->pch_pfit.enabled) | |
3352 | skylake_pfit_enable(crtc); | |
3353 | } else if (HAS_PCH_SPLIT(dev)) { | |
3354 | if (pipe_config->pch_pfit.enabled) | |
3355 | ironlake_pfit_enable(crtc); | |
3356 | else if (old_crtc_state->pch_pfit.enabled) | |
3357 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3358 | } |
e30e8f75 GP |
3359 | } |
3360 | ||
5e84e1a4 ZW |
3361 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3362 | { | |
3363 | struct drm_device *dev = crtc->dev; | |
3364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3366 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3367 | i915_reg_t reg; |
3368 | u32 temp; | |
5e84e1a4 ZW |
3369 | |
3370 | /* enable normal train */ | |
3371 | reg = FDI_TX_CTL(pipe); | |
3372 | temp = I915_READ(reg); | |
61e499bf | 3373 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3374 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3375 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3376 | } else { |
3377 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3378 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3379 | } |
5e84e1a4 ZW |
3380 | I915_WRITE(reg, temp); |
3381 | ||
3382 | reg = FDI_RX_CTL(pipe); | |
3383 | temp = I915_READ(reg); | |
3384 | if (HAS_PCH_CPT(dev)) { | |
3385 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3386 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3387 | } else { | |
3388 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3389 | temp |= FDI_LINK_TRAIN_NONE; | |
3390 | } | |
3391 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3392 | ||
3393 | /* wait one idle pattern time */ | |
3394 | POSTING_READ(reg); | |
3395 | udelay(1000); | |
357555c0 JB |
3396 | |
3397 | /* IVB wants error correction enabled */ | |
3398 | if (IS_IVYBRIDGE(dev)) | |
3399 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3400 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3401 | } |
3402 | ||
8db9d77b ZW |
3403 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3404 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3405 | { | |
3406 | struct drm_device *dev = crtc->dev; | |
3407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3409 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3410 | i915_reg_t reg; |
3411 | u32 temp, tries; | |
8db9d77b | 3412 | |
1c8562f6 | 3413 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3414 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3415 | |
e1a44743 AJ |
3416 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3417 | for train result */ | |
5eddb70b CW |
3418 | reg = FDI_RX_IMR(pipe); |
3419 | temp = I915_READ(reg); | |
e1a44743 AJ |
3420 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3421 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3422 | I915_WRITE(reg, temp); |
3423 | I915_READ(reg); | |
e1a44743 AJ |
3424 | udelay(150); |
3425 | ||
8db9d77b | 3426 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3427 | reg = FDI_TX_CTL(pipe); |
3428 | temp = I915_READ(reg); | |
627eb5a3 | 3429 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3430 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3431 | temp &= ~FDI_LINK_TRAIN_NONE; |
3432 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3433 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3434 | |
5eddb70b CW |
3435 | reg = FDI_RX_CTL(pipe); |
3436 | temp = I915_READ(reg); | |
8db9d77b ZW |
3437 | temp &= ~FDI_LINK_TRAIN_NONE; |
3438 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3439 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3440 | ||
3441 | POSTING_READ(reg); | |
8db9d77b ZW |
3442 | udelay(150); |
3443 | ||
5b2adf89 | 3444 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3445 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3447 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3448 | |
5eddb70b | 3449 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3450 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3451 | temp = I915_READ(reg); |
8db9d77b ZW |
3452 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3453 | ||
3454 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3455 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3456 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3457 | break; |
3458 | } | |
8db9d77b | 3459 | } |
e1a44743 | 3460 | if (tries == 5) |
5eddb70b | 3461 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3462 | |
3463 | /* Train 2 */ | |
5eddb70b CW |
3464 | reg = FDI_TX_CTL(pipe); |
3465 | temp = I915_READ(reg); | |
8db9d77b ZW |
3466 | temp &= ~FDI_LINK_TRAIN_NONE; |
3467 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3468 | I915_WRITE(reg, temp); |
8db9d77b | 3469 | |
5eddb70b CW |
3470 | reg = FDI_RX_CTL(pipe); |
3471 | temp = I915_READ(reg); | |
8db9d77b ZW |
3472 | temp &= ~FDI_LINK_TRAIN_NONE; |
3473 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3474 | I915_WRITE(reg, temp); |
8db9d77b | 3475 | |
5eddb70b CW |
3476 | POSTING_READ(reg); |
3477 | udelay(150); | |
8db9d77b | 3478 | |
5eddb70b | 3479 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3480 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3481 | temp = I915_READ(reg); |
8db9d77b ZW |
3482 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3483 | ||
3484 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3485 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3486 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3487 | break; | |
3488 | } | |
8db9d77b | 3489 | } |
e1a44743 | 3490 | if (tries == 5) |
5eddb70b | 3491 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3492 | |
3493 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3494 | |
8db9d77b ZW |
3495 | } |
3496 | ||
0206e353 | 3497 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3498 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3499 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3500 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3501 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3502 | }; | |
3503 | ||
3504 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3505 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3506 | { | |
3507 | struct drm_device *dev = crtc->dev; | |
3508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3510 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3511 | i915_reg_t reg; |
3512 | u32 temp, i, retry; | |
8db9d77b | 3513 | |
e1a44743 AJ |
3514 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3515 | for train result */ | |
5eddb70b CW |
3516 | reg = FDI_RX_IMR(pipe); |
3517 | temp = I915_READ(reg); | |
e1a44743 AJ |
3518 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3519 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3520 | I915_WRITE(reg, temp); |
3521 | ||
3522 | POSTING_READ(reg); | |
e1a44743 AJ |
3523 | udelay(150); |
3524 | ||
8db9d77b | 3525 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3526 | reg = FDI_TX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
627eb5a3 | 3528 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3529 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3530 | temp &= ~FDI_LINK_TRAIN_NONE; |
3531 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3532 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3533 | /* SNB-B */ | |
3534 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3535 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3536 | |
d74cf324 DV |
3537 | I915_WRITE(FDI_RX_MISC(pipe), |
3538 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3539 | ||
5eddb70b CW |
3540 | reg = FDI_RX_CTL(pipe); |
3541 | temp = I915_READ(reg); | |
8db9d77b ZW |
3542 | if (HAS_PCH_CPT(dev)) { |
3543 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3544 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3545 | } else { | |
3546 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3548 | } | |
5eddb70b CW |
3549 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3550 | ||
3551 | POSTING_READ(reg); | |
8db9d77b ZW |
3552 | udelay(150); |
3553 | ||
0206e353 | 3554 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3555 | reg = FDI_TX_CTL(pipe); |
3556 | temp = I915_READ(reg); | |
8db9d77b ZW |
3557 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3558 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3559 | I915_WRITE(reg, temp); |
3560 | ||
3561 | POSTING_READ(reg); | |
8db9d77b ZW |
3562 | udelay(500); |
3563 | ||
fa37d39e SP |
3564 | for (retry = 0; retry < 5; retry++) { |
3565 | reg = FDI_RX_IIR(pipe); | |
3566 | temp = I915_READ(reg); | |
3567 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3568 | if (temp & FDI_RX_BIT_LOCK) { | |
3569 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3570 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3571 | break; | |
3572 | } | |
3573 | udelay(50); | |
8db9d77b | 3574 | } |
fa37d39e SP |
3575 | if (retry < 5) |
3576 | break; | |
8db9d77b ZW |
3577 | } |
3578 | if (i == 4) | |
5eddb70b | 3579 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3580 | |
3581 | /* Train 2 */ | |
5eddb70b CW |
3582 | reg = FDI_TX_CTL(pipe); |
3583 | temp = I915_READ(reg); | |
8db9d77b ZW |
3584 | temp &= ~FDI_LINK_TRAIN_NONE; |
3585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3586 | if (IS_GEN6(dev)) { | |
3587 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3588 | /* SNB-B */ | |
3589 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3590 | } | |
5eddb70b | 3591 | I915_WRITE(reg, temp); |
8db9d77b | 3592 | |
5eddb70b CW |
3593 | reg = FDI_RX_CTL(pipe); |
3594 | temp = I915_READ(reg); | |
8db9d77b ZW |
3595 | if (HAS_PCH_CPT(dev)) { |
3596 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3597 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3598 | } else { | |
3599 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3600 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3601 | } | |
5eddb70b CW |
3602 | I915_WRITE(reg, temp); |
3603 | ||
3604 | POSTING_READ(reg); | |
8db9d77b ZW |
3605 | udelay(150); |
3606 | ||
0206e353 | 3607 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3608 | reg = FDI_TX_CTL(pipe); |
3609 | temp = I915_READ(reg); | |
8db9d77b ZW |
3610 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3611 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3612 | I915_WRITE(reg, temp); |
3613 | ||
3614 | POSTING_READ(reg); | |
8db9d77b ZW |
3615 | udelay(500); |
3616 | ||
fa37d39e SP |
3617 | for (retry = 0; retry < 5; retry++) { |
3618 | reg = FDI_RX_IIR(pipe); | |
3619 | temp = I915_READ(reg); | |
3620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3621 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3622 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3623 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3624 | break; | |
3625 | } | |
3626 | udelay(50); | |
8db9d77b | 3627 | } |
fa37d39e SP |
3628 | if (retry < 5) |
3629 | break; | |
8db9d77b ZW |
3630 | } |
3631 | if (i == 4) | |
5eddb70b | 3632 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3633 | |
3634 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3635 | } | |
3636 | ||
357555c0 JB |
3637 | /* Manual link training for Ivy Bridge A0 parts */ |
3638 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3639 | { | |
3640 | struct drm_device *dev = crtc->dev; | |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3643 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3644 | i915_reg_t reg; |
3645 | u32 temp, i, j; | |
357555c0 JB |
3646 | |
3647 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3648 | for train result */ | |
3649 | reg = FDI_RX_IMR(pipe); | |
3650 | temp = I915_READ(reg); | |
3651 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3652 | temp &= ~FDI_RX_BIT_LOCK; | |
3653 | I915_WRITE(reg, temp); | |
3654 | ||
3655 | POSTING_READ(reg); | |
3656 | udelay(150); | |
3657 | ||
01a415fd DV |
3658 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3659 | I915_READ(FDI_RX_IIR(pipe))); | |
3660 | ||
139ccd3f JB |
3661 | /* Try each vswing and preemphasis setting twice before moving on */ |
3662 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3663 | /* disable first in case we need to retry */ | |
3664 | reg = FDI_TX_CTL(pipe); | |
3665 | temp = I915_READ(reg); | |
3666 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3667 | temp &= ~FDI_TX_ENABLE; | |
3668 | I915_WRITE(reg, temp); | |
357555c0 | 3669 | |
139ccd3f JB |
3670 | reg = FDI_RX_CTL(pipe); |
3671 | temp = I915_READ(reg); | |
3672 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3673 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3674 | temp &= ~FDI_RX_ENABLE; | |
3675 | I915_WRITE(reg, temp); | |
357555c0 | 3676 | |
139ccd3f | 3677 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3678 | reg = FDI_TX_CTL(pipe); |
3679 | temp = I915_READ(reg); | |
139ccd3f | 3680 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3681 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3682 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3683 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3684 | temp |= snb_b_fdi_train_param[j/2]; |
3685 | temp |= FDI_COMPOSITE_SYNC; | |
3686 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3687 | |
139ccd3f JB |
3688 | I915_WRITE(FDI_RX_MISC(pipe), |
3689 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3690 | |
139ccd3f | 3691 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3692 | temp = I915_READ(reg); |
139ccd3f JB |
3693 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3694 | temp |= FDI_COMPOSITE_SYNC; | |
3695 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3696 | |
139ccd3f JB |
3697 | POSTING_READ(reg); |
3698 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3699 | |
139ccd3f JB |
3700 | for (i = 0; i < 4; i++) { |
3701 | reg = FDI_RX_IIR(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3704 | |
139ccd3f JB |
3705 | if (temp & FDI_RX_BIT_LOCK || |
3706 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3707 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3708 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3709 | i); | |
3710 | break; | |
3711 | } | |
3712 | udelay(1); /* should be 0.5us */ | |
3713 | } | |
3714 | if (i == 4) { | |
3715 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3716 | continue; | |
3717 | } | |
357555c0 | 3718 | |
139ccd3f | 3719 | /* Train 2 */ |
357555c0 JB |
3720 | reg = FDI_TX_CTL(pipe); |
3721 | temp = I915_READ(reg); | |
139ccd3f JB |
3722 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3723 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3724 | I915_WRITE(reg, temp); | |
3725 | ||
3726 | reg = FDI_RX_CTL(pipe); | |
3727 | temp = I915_READ(reg); | |
3728 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3729 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3730 | I915_WRITE(reg, temp); |
3731 | ||
3732 | POSTING_READ(reg); | |
139ccd3f | 3733 | udelay(2); /* should be 1.5us */ |
357555c0 | 3734 | |
139ccd3f JB |
3735 | for (i = 0; i < 4; i++) { |
3736 | reg = FDI_RX_IIR(pipe); | |
3737 | temp = I915_READ(reg); | |
3738 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3739 | |
139ccd3f JB |
3740 | if (temp & FDI_RX_SYMBOL_LOCK || |
3741 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3742 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3743 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3744 | i); | |
3745 | goto train_done; | |
3746 | } | |
3747 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3748 | } |
139ccd3f JB |
3749 | if (i == 4) |
3750 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3751 | } |
357555c0 | 3752 | |
139ccd3f | 3753 | train_done: |
357555c0 JB |
3754 | DRM_DEBUG_KMS("FDI train done.\n"); |
3755 | } | |
3756 | ||
88cefb6c | 3757 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3758 | { |
88cefb6c | 3759 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3760 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3761 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3762 | i915_reg_t reg; |
3763 | u32 temp; | |
c64e311e | 3764 | |
c98e9dcf | 3765 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3766 | reg = FDI_RX_CTL(pipe); |
3767 | temp = I915_READ(reg); | |
627eb5a3 | 3768 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3769 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3770 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3771 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3772 | ||
3773 | POSTING_READ(reg); | |
c98e9dcf JB |
3774 | udelay(200); |
3775 | ||
3776 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3777 | temp = I915_READ(reg); |
3778 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3779 | ||
3780 | POSTING_READ(reg); | |
c98e9dcf JB |
3781 | udelay(200); |
3782 | ||
20749730 PZ |
3783 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3784 | reg = FDI_TX_CTL(pipe); | |
3785 | temp = I915_READ(reg); | |
3786 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3787 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3788 | |
20749730 PZ |
3789 | POSTING_READ(reg); |
3790 | udelay(100); | |
6be4a607 | 3791 | } |
0e23b99d JB |
3792 | } |
3793 | ||
88cefb6c DV |
3794 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3795 | { | |
3796 | struct drm_device *dev = intel_crtc->base.dev; | |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3798 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3799 | i915_reg_t reg; |
3800 | u32 temp; | |
88cefb6c DV |
3801 | |
3802 | /* Switch from PCDclk to Rawclk */ | |
3803 | reg = FDI_RX_CTL(pipe); | |
3804 | temp = I915_READ(reg); | |
3805 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3806 | ||
3807 | /* Disable CPU FDI TX PLL */ | |
3808 | reg = FDI_TX_CTL(pipe); | |
3809 | temp = I915_READ(reg); | |
3810 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3811 | ||
3812 | POSTING_READ(reg); | |
3813 | udelay(100); | |
3814 | ||
3815 | reg = FDI_RX_CTL(pipe); | |
3816 | temp = I915_READ(reg); | |
3817 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3818 | ||
3819 | /* Wait for the clocks to turn off. */ | |
3820 | POSTING_READ(reg); | |
3821 | udelay(100); | |
3822 | } | |
3823 | ||
0fc932b8 JB |
3824 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3825 | { | |
3826 | struct drm_device *dev = crtc->dev; | |
3827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3829 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3830 | i915_reg_t reg; |
3831 | u32 temp; | |
0fc932b8 JB |
3832 | |
3833 | /* disable CPU FDI tx and PCH FDI rx */ | |
3834 | reg = FDI_TX_CTL(pipe); | |
3835 | temp = I915_READ(reg); | |
3836 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3837 | POSTING_READ(reg); | |
3838 | ||
3839 | reg = FDI_RX_CTL(pipe); | |
3840 | temp = I915_READ(reg); | |
3841 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3842 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3843 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3844 | ||
3845 | POSTING_READ(reg); | |
3846 | udelay(100); | |
3847 | ||
3848 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3849 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3850 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3851 | |
3852 | /* still set train pattern 1 */ | |
3853 | reg = FDI_TX_CTL(pipe); | |
3854 | temp = I915_READ(reg); | |
3855 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3856 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3857 | I915_WRITE(reg, temp); | |
3858 | ||
3859 | reg = FDI_RX_CTL(pipe); | |
3860 | temp = I915_READ(reg); | |
3861 | if (HAS_PCH_CPT(dev)) { | |
3862 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3863 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3864 | } else { | |
3865 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3866 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3867 | } | |
3868 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3869 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3870 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3871 | I915_WRITE(reg, temp); |
3872 | ||
3873 | POSTING_READ(reg); | |
3874 | udelay(100); | |
3875 | } | |
3876 | ||
5dce5b93 CW |
3877 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3878 | { | |
3879 | struct intel_crtc *crtc; | |
3880 | ||
3881 | /* Note that we don't need to be called with mode_config.lock here | |
3882 | * as our list of CRTC objects is static for the lifetime of the | |
3883 | * device and so cannot disappear as we iterate. Similarly, we can | |
3884 | * happily treat the predicates as racy, atomic checks as userspace | |
3885 | * cannot claim and pin a new fb without at least acquring the | |
3886 | * struct_mutex and so serialising with us. | |
3887 | */ | |
d3fcc808 | 3888 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3889 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3890 | continue; | |
3891 | ||
3892 | if (crtc->unpin_work) | |
3893 | intel_wait_for_vblank(dev, crtc->pipe); | |
3894 | ||
3895 | return true; | |
3896 | } | |
3897 | ||
3898 | return false; | |
3899 | } | |
3900 | ||
d6bbafa1 CW |
3901 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3902 | { | |
3903 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3904 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3905 | ||
3906 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3907 | smp_rmb(); | |
3908 | intel_crtc->unpin_work = NULL; | |
3909 | ||
3910 | if (work->event) | |
3911 | drm_send_vblank_event(intel_crtc->base.dev, | |
3912 | intel_crtc->pipe, | |
3913 | work->event); | |
3914 | ||
3915 | drm_crtc_vblank_put(&intel_crtc->base); | |
3916 | ||
3917 | wake_up_all(&dev_priv->pending_flip_queue); | |
3918 | queue_work(dev_priv->wq, &work->work); | |
3919 | ||
3920 | trace_i915_flip_complete(intel_crtc->plane, | |
3921 | work->pending_flip_obj); | |
3922 | } | |
3923 | ||
5008e874 | 3924 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3925 | { |
0f91128d | 3926 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3927 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3928 | long ret; |
e6c3a2a6 | 3929 | |
2c10d571 | 3930 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3931 | |
3932 | ret = wait_event_interruptible_timeout( | |
3933 | dev_priv->pending_flip_queue, | |
3934 | !intel_crtc_has_pending_flip(crtc), | |
3935 | 60*HZ); | |
3936 | ||
3937 | if (ret < 0) | |
3938 | return ret; | |
3939 | ||
3940 | if (ret == 0) { | |
9c787942 | 3941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3942 | |
5e2d7afc | 3943 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3944 | if (intel_crtc->unpin_work) { |
3945 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3946 | page_flip_completed(intel_crtc); | |
3947 | } | |
5e2d7afc | 3948 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3949 | } |
5bb61643 | 3950 | |
5008e874 | 3951 | return 0; |
e6c3a2a6 CW |
3952 | } |
3953 | ||
060f02d8 VS |
3954 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3955 | { | |
3956 | u32 temp; | |
3957 | ||
3958 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3959 | ||
3960 | mutex_lock(&dev_priv->sb_lock); | |
3961 | ||
3962 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3963 | temp |= SBI_SSCCTL_DISABLE; | |
3964 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3965 | ||
3966 | mutex_unlock(&dev_priv->sb_lock); | |
3967 | } | |
3968 | ||
e615efe4 ED |
3969 | /* Program iCLKIP clock to the desired frequency */ |
3970 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3971 | { | |
3972 | struct drm_device *dev = crtc->dev; | |
3973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3974 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3975 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3976 | u32 temp; | |
3977 | ||
060f02d8 | 3978 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3979 | |
3980 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3981 | if (clock == 20000) { |
e615efe4 ED |
3982 | auxdiv = 1; |
3983 | divsel = 0x41; | |
3984 | phaseinc = 0x20; | |
3985 | } else { | |
3986 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3987 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3988 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3989 | * convert the virtual clock precision to KHz here for higher |
3990 | * precision. | |
3991 | */ | |
3992 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3993 | u32 iclk_pi_range = 64; | |
3994 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3995 | ||
a2572f5c | 3996 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3997 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3998 | pi_value = desired_divisor % iclk_pi_range; | |
3999 | ||
4000 | auxdiv = 0; | |
4001 | divsel = msb_divisor_value - 2; | |
4002 | phaseinc = pi_value; | |
4003 | } | |
4004 | ||
4005 | /* This should not happen with any sane values */ | |
4006 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4007 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4008 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4009 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4010 | ||
4011 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4012 | clock, |
e615efe4 ED |
4013 | auxdiv, |
4014 | divsel, | |
4015 | phasedir, | |
4016 | phaseinc); | |
4017 | ||
060f02d8 VS |
4018 | mutex_lock(&dev_priv->sb_lock); |
4019 | ||
e615efe4 | 4020 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4021 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4022 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4023 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4024 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4025 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4026 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4027 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4028 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4029 | |
4030 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4031 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4032 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4033 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4034 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4035 | |
4036 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4037 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4038 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4039 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4040 | |
060f02d8 VS |
4041 | mutex_unlock(&dev_priv->sb_lock); |
4042 | ||
e615efe4 ED |
4043 | /* Wait for initialization time */ |
4044 | udelay(24); | |
4045 | ||
4046 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4047 | } | |
4048 | ||
275f01b2 DV |
4049 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4050 | enum pipe pch_transcoder) | |
4051 | { | |
4052 | struct drm_device *dev = crtc->base.dev; | |
4053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4054 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4055 | |
4056 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4057 | I915_READ(HTOTAL(cpu_transcoder))); | |
4058 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4059 | I915_READ(HBLANK(cpu_transcoder))); | |
4060 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4061 | I915_READ(HSYNC(cpu_transcoder))); | |
4062 | ||
4063 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4064 | I915_READ(VTOTAL(cpu_transcoder))); | |
4065 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4066 | I915_READ(VBLANK(cpu_transcoder))); | |
4067 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4068 | I915_READ(VSYNC(cpu_transcoder))); | |
4069 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4070 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4071 | } | |
4072 | ||
003632d9 | 4073 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4074 | { |
4075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4076 | uint32_t temp; | |
4077 | ||
4078 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4079 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4080 | return; |
4081 | ||
4082 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4083 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4084 | ||
003632d9 ACO |
4085 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4086 | if (enable) | |
4087 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4088 | ||
4089 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4090 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4091 | POSTING_READ(SOUTH_CHICKEN1); | |
4092 | } | |
4093 | ||
4094 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4095 | { | |
4096 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4097 | |
4098 | switch (intel_crtc->pipe) { | |
4099 | case PIPE_A: | |
4100 | break; | |
4101 | case PIPE_B: | |
6e3c9717 | 4102 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4103 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4104 | else |
003632d9 | 4105 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4106 | |
4107 | break; | |
4108 | case PIPE_C: | |
003632d9 | 4109 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4110 | |
4111 | break; | |
4112 | default: | |
4113 | BUG(); | |
4114 | } | |
4115 | } | |
4116 | ||
c48b5305 VS |
4117 | /* Return which DP Port should be selected for Transcoder DP control */ |
4118 | static enum port | |
4119 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4120 | { | |
4121 | struct drm_device *dev = crtc->dev; | |
4122 | struct intel_encoder *encoder; | |
4123 | ||
4124 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4125 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4126 | encoder->type == INTEL_OUTPUT_EDP) | |
4127 | return enc_to_dig_port(&encoder->base)->port; | |
4128 | } | |
4129 | ||
4130 | return -1; | |
4131 | } | |
4132 | ||
f67a559d JB |
4133 | /* |
4134 | * Enable PCH resources required for PCH ports: | |
4135 | * - PCH PLLs | |
4136 | * - FDI training & RX/TX | |
4137 | * - update transcoder timings | |
4138 | * - DP transcoding bits | |
4139 | * - transcoder | |
4140 | */ | |
4141 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4142 | { |
4143 | struct drm_device *dev = crtc->dev; | |
4144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4146 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4147 | u32 temp; |
2c07245f | 4148 | |
ab9412ba | 4149 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4150 | |
1fbc0d78 DV |
4151 | if (IS_IVYBRIDGE(dev)) |
4152 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4153 | ||
cd986abb DV |
4154 | /* Write the TU size bits before fdi link training, so that error |
4155 | * detection works. */ | |
4156 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4157 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4158 | ||
3860b2ec VS |
4159 | /* |
4160 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4161 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4162 | */ | |
4163 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4164 | ||
c98e9dcf | 4165 | /* For PCH output, training FDI link */ |
674cf967 | 4166 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4167 | |
3ad8a208 DV |
4168 | /* We need to program the right clock selection before writing the pixel |
4169 | * mutliplier into the DPLL. */ | |
303b81e0 | 4170 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4171 | u32 sel; |
4b645f14 | 4172 | |
c98e9dcf | 4173 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4174 | temp |= TRANS_DPLL_ENABLE(pipe); |
4175 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4176 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4177 | temp |= sel; |
4178 | else | |
4179 | temp &= ~sel; | |
c98e9dcf | 4180 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4181 | } |
5eddb70b | 4182 | |
3ad8a208 DV |
4183 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4184 | * transcoder, and we actually should do this to not upset any PCH | |
4185 | * transcoder that already use the clock when we share it. | |
4186 | * | |
4187 | * Note that enable_shared_dpll tries to do the right thing, but | |
4188 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4189 | * the right LVDS enable sequence. */ | |
85b3894f | 4190 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4191 | |
d9b6cb56 JB |
4192 | /* set transcoder timing, panel must allow it */ |
4193 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4194 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4195 | |
303b81e0 | 4196 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4197 | |
3860b2ec VS |
4198 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4199 | ||
c98e9dcf | 4200 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4201 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4202 | const struct drm_display_mode *adjusted_mode = |
4203 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4204 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4205 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4206 | temp = I915_READ(reg); |
4207 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4208 | TRANS_DP_SYNC_MASK | |
4209 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4210 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4211 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4212 | |
9c4edaee | 4213 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4214 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4215 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4216 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4217 | |
4218 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4219 | case PORT_B: |
5eddb70b | 4220 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4221 | break; |
c48b5305 | 4222 | case PORT_C: |
5eddb70b | 4223 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4224 | break; |
c48b5305 | 4225 | case PORT_D: |
5eddb70b | 4226 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4227 | break; |
4228 | default: | |
e95d41e1 | 4229 | BUG(); |
32f9d658 | 4230 | } |
2c07245f | 4231 | |
5eddb70b | 4232 | I915_WRITE(reg, temp); |
6be4a607 | 4233 | } |
b52eb4dc | 4234 | |
b8a4f404 | 4235 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4236 | } |
4237 | ||
1507e5bd PZ |
4238 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4239 | { | |
4240 | struct drm_device *dev = crtc->dev; | |
4241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4243 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4244 | |
ab9412ba | 4245 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4246 | |
8c52b5e8 | 4247 | lpt_program_iclkip(crtc); |
1507e5bd | 4248 | |
0540e488 | 4249 | /* Set transcoder timing. */ |
275f01b2 | 4250 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4251 | |
937bb610 | 4252 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4253 | } |
4254 | ||
190f68c5 ACO |
4255 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4256 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4257 | { |
e2b78267 | 4258 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4259 | struct intel_shared_dpll *pll; |
de419ab6 | 4260 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4261 | enum intel_dpll_id i; |
00490c22 | 4262 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4263 | |
de419ab6 ML |
4264 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4265 | ||
98b6bd99 DV |
4266 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4267 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4268 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4269 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4270 | |
46edb027 DV |
4271 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4272 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4273 | |
de419ab6 | 4274 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4275 | |
98b6bd99 DV |
4276 | goto found; |
4277 | } | |
4278 | ||
bcddf610 S |
4279 | if (IS_BROXTON(dev_priv->dev)) { |
4280 | /* PLL is attached to port in bxt */ | |
4281 | struct intel_encoder *encoder; | |
4282 | struct intel_digital_port *intel_dig_port; | |
4283 | ||
4284 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4285 | if (WARN_ON(!encoder)) | |
4286 | return NULL; | |
4287 | ||
4288 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4289 | /* 1:1 mapping between ports and PLLs */ | |
4290 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4291 | pll = &dev_priv->shared_dplls[i]; | |
4292 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4293 | crtc->base.base.id, pll->name); | |
de419ab6 | 4294 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4295 | |
4296 | goto found; | |
00490c22 ML |
4297 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4298 | /* Do not consider SPLL */ | |
4299 | max = 2; | |
bcddf610 | 4300 | |
00490c22 | 4301 | for (i = 0; i < max; i++) { |
e72f9fbf | 4302 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4303 | |
4304 | /* Only want to check enabled timings first */ | |
de419ab6 | 4305 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4306 | continue; |
4307 | ||
190f68c5 | 4308 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4309 | &shared_dpll[i].hw_state, |
4310 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4311 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4312 | crtc->base.base.id, pll->name, |
de419ab6 | 4313 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4314 | pll->active); |
ee7b9f93 JB |
4315 | goto found; |
4316 | } | |
4317 | } | |
4318 | ||
4319 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4320 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4321 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4322 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4323 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4324 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4325 | goto found; |
4326 | } | |
4327 | } | |
4328 | ||
4329 | return NULL; | |
4330 | ||
4331 | found: | |
de419ab6 ML |
4332 | if (shared_dpll[i].crtc_mask == 0) |
4333 | shared_dpll[i].hw_state = | |
4334 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4335 | |
190f68c5 | 4336 | crtc_state->shared_dpll = i; |
46edb027 DV |
4337 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4338 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4339 | |
de419ab6 | 4340 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4341 | |
ee7b9f93 JB |
4342 | return pll; |
4343 | } | |
4344 | ||
de419ab6 | 4345 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4346 | { |
de419ab6 ML |
4347 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4348 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4349 | struct intel_shared_dpll *pll; |
4350 | enum intel_dpll_id i; | |
4351 | ||
de419ab6 ML |
4352 | if (!to_intel_atomic_state(state)->dpll_set) |
4353 | return; | |
8bd31e67 | 4354 | |
de419ab6 | 4355 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4356 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4357 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4358 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4359 | } |
4360 | } | |
4361 | ||
a1520318 | 4362 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4363 | { |
4364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4365 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4366 | u32 temp; |
4367 | ||
4368 | temp = I915_READ(dslreg); | |
4369 | udelay(500); | |
4370 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4371 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4372 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4373 | } |
4374 | } | |
4375 | ||
86adf9d7 ML |
4376 | static int |
4377 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4378 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4379 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4380 | { |
86adf9d7 ML |
4381 | struct intel_crtc_scaler_state *scaler_state = |
4382 | &crtc_state->scaler_state; | |
4383 | struct intel_crtc *intel_crtc = | |
4384 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4385 | int need_scaling; |
6156a456 CK |
4386 | |
4387 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4388 | (src_h != dst_w || src_w != dst_h): | |
4389 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4390 | |
4391 | /* | |
4392 | * if plane is being disabled or scaler is no more required or force detach | |
4393 | * - free scaler binded to this plane/crtc | |
4394 | * - in order to do this, update crtc->scaler_usage | |
4395 | * | |
4396 | * Here scaler state in crtc_state is set free so that | |
4397 | * scaler can be assigned to other user. Actual register | |
4398 | * update to free the scaler is done in plane/panel-fit programming. | |
4399 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4400 | */ | |
86adf9d7 | 4401 | if (force_detach || !need_scaling) { |
a1b2278e | 4402 | if (*scaler_id >= 0) { |
86adf9d7 | 4403 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4404 | scaler_state->scalers[*scaler_id].in_use = 0; |
4405 | ||
86adf9d7 ML |
4406 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4407 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4408 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4409 | scaler_state->scaler_users); |
4410 | *scaler_id = -1; | |
4411 | } | |
4412 | return 0; | |
4413 | } | |
4414 | ||
4415 | /* range checks */ | |
4416 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4417 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4418 | ||
4419 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4420 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4421 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4422 | "size is out of scaler range\n", |
86adf9d7 | 4423 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4424 | return -EINVAL; |
4425 | } | |
4426 | ||
86adf9d7 ML |
4427 | /* mark this plane as a scaler user in crtc_state */ |
4428 | scaler_state->scaler_users |= (1 << scaler_user); | |
4429 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4430 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4431 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4432 | scaler_state->scaler_users); | |
4433 | ||
4434 | return 0; | |
4435 | } | |
4436 | ||
4437 | /** | |
4438 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4439 | * | |
4440 | * @state: crtc's scaler state | |
86adf9d7 ML |
4441 | * |
4442 | * Return | |
4443 | * 0 - scaler_usage updated successfully | |
4444 | * error - requested scaling cannot be supported or other error condition | |
4445 | */ | |
e435d6e5 | 4446 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4447 | { |
4448 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4449 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4450 | |
4451 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4452 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4453 | ||
e435d6e5 | 4454 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4455 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4456 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4457 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4458 | } |
4459 | ||
4460 | /** | |
4461 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4462 | * | |
4463 | * @state: crtc's scaler state | |
86adf9d7 ML |
4464 | * @plane_state: atomic plane state to update |
4465 | * | |
4466 | * Return | |
4467 | * 0 - scaler_usage updated successfully | |
4468 | * error - requested scaling cannot be supported or other error condition | |
4469 | */ | |
da20eabd ML |
4470 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4471 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4472 | { |
4473 | ||
4474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4475 | struct intel_plane *intel_plane = |
4476 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4477 | struct drm_framebuffer *fb = plane_state->base.fb; |
4478 | int ret; | |
4479 | ||
4480 | bool force_detach = !fb || !plane_state->visible; | |
4481 | ||
4482 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4483 | intel_plane->base.base.id, intel_crtc->pipe, | |
4484 | drm_plane_index(&intel_plane->base)); | |
4485 | ||
4486 | ret = skl_update_scaler(crtc_state, force_detach, | |
4487 | drm_plane_index(&intel_plane->base), | |
4488 | &plane_state->scaler_id, | |
4489 | plane_state->base.rotation, | |
4490 | drm_rect_width(&plane_state->src) >> 16, | |
4491 | drm_rect_height(&plane_state->src) >> 16, | |
4492 | drm_rect_width(&plane_state->dst), | |
4493 | drm_rect_height(&plane_state->dst)); | |
4494 | ||
4495 | if (ret || plane_state->scaler_id < 0) | |
4496 | return ret; | |
4497 | ||
a1b2278e | 4498 | /* check colorkey */ |
818ed961 | 4499 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4500 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4501 | intel_plane->base.base.id); |
a1b2278e CK |
4502 | return -EINVAL; |
4503 | } | |
4504 | ||
4505 | /* Check src format */ | |
86adf9d7 ML |
4506 | switch (fb->pixel_format) { |
4507 | case DRM_FORMAT_RGB565: | |
4508 | case DRM_FORMAT_XBGR8888: | |
4509 | case DRM_FORMAT_XRGB8888: | |
4510 | case DRM_FORMAT_ABGR8888: | |
4511 | case DRM_FORMAT_ARGB8888: | |
4512 | case DRM_FORMAT_XRGB2101010: | |
4513 | case DRM_FORMAT_XBGR2101010: | |
4514 | case DRM_FORMAT_YUYV: | |
4515 | case DRM_FORMAT_YVYU: | |
4516 | case DRM_FORMAT_UYVY: | |
4517 | case DRM_FORMAT_VYUY: | |
4518 | break; | |
4519 | default: | |
4520 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4521 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4522 | return -EINVAL; | |
a1b2278e CK |
4523 | } |
4524 | ||
a1b2278e CK |
4525 | return 0; |
4526 | } | |
4527 | ||
e435d6e5 ML |
4528 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4529 | { | |
4530 | int i; | |
4531 | ||
4532 | for (i = 0; i < crtc->num_scalers; i++) | |
4533 | skl_detach_scaler(crtc, i); | |
4534 | } | |
4535 | ||
4536 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4537 | { |
4538 | struct drm_device *dev = crtc->base.dev; | |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4540 | int pipe = crtc->pipe; | |
a1b2278e CK |
4541 | struct intel_crtc_scaler_state *scaler_state = |
4542 | &crtc->config->scaler_state; | |
4543 | ||
4544 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4545 | ||
6e3c9717 | 4546 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4547 | int id; |
4548 | ||
4549 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4550 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4551 | return; | |
4552 | } | |
4553 | ||
4554 | id = scaler_state->scaler_id; | |
4555 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4556 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4557 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4558 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4559 | ||
4560 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4561 | } |
4562 | } | |
4563 | ||
b074cec8 JB |
4564 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4565 | { | |
4566 | struct drm_device *dev = crtc->base.dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | int pipe = crtc->pipe; | |
4569 | ||
6e3c9717 | 4570 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4571 | /* Force use of hard-coded filter coefficients |
4572 | * as some pre-programmed values are broken, | |
4573 | * e.g. x201. | |
4574 | */ | |
4575 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4576 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4577 | PF_PIPE_SEL_IVB(pipe)); | |
4578 | else | |
4579 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4580 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4581 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4582 | } |
4583 | } | |
4584 | ||
20bc8673 | 4585 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4586 | { |
cea165c3 VS |
4587 | struct drm_device *dev = crtc->base.dev; |
4588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4589 | |
6e3c9717 | 4590 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4591 | return; |
4592 | ||
cea165c3 VS |
4593 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4594 | intel_wait_for_vblank(dev, crtc->pipe); | |
4595 | ||
d77e4531 | 4596 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4597 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4598 | mutex_lock(&dev_priv->rps.hw_lock); |
4599 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4600 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4601 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4602 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4603 | * mailbox." Moreover, the mailbox may return a bogus state, |
4604 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4605 | */ |
4606 | } else { | |
4607 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4608 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4609 | * is essentially intel_wait_for_vblank. If we don't have this | |
4610 | * and don't wait for vblanks until the end of crtc_enable, then | |
4611 | * the HW state readout code will complain that the expected | |
4612 | * IPS_CTL value is not the one we read. */ | |
4613 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4614 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4615 | } | |
d77e4531 PZ |
4616 | } |
4617 | ||
20bc8673 | 4618 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4619 | { |
4620 | struct drm_device *dev = crtc->base.dev; | |
4621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4622 | ||
6e3c9717 | 4623 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4624 | return; |
4625 | ||
4626 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4627 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4628 | mutex_lock(&dev_priv->rps.hw_lock); |
4629 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4630 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4631 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4632 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4633 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4634 | } else { |
2a114cc1 | 4635 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4636 | POSTING_READ(IPS_CTL); |
4637 | } | |
d77e4531 PZ |
4638 | |
4639 | /* We need to wait for a vblank before we can disable the plane. */ | |
4640 | intel_wait_for_vblank(dev, crtc->pipe); | |
4641 | } | |
4642 | ||
4643 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4644 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4645 | { | |
4646 | struct drm_device *dev = crtc->dev; | |
4647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4649 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4650 | int i; |
4651 | bool reenable_ips = false; | |
4652 | ||
4653 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4654 | if (!crtc->state->active) |
d77e4531 PZ |
4655 | return; |
4656 | ||
50360403 | 4657 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4658 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4659 | assert_dsi_pll_enabled(dev_priv); |
4660 | else | |
4661 | assert_pll_enabled(dev_priv, pipe); | |
4662 | } | |
4663 | ||
d77e4531 PZ |
4664 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4665 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4666 | */ | |
6e3c9717 | 4667 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4668 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4669 | GAMMA_MODE_MODE_SPLIT)) { | |
4670 | hsw_disable_ips(intel_crtc); | |
4671 | reenable_ips = true; | |
4672 | } | |
4673 | ||
4674 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4675 | i915_reg_t palreg; |
f65a9c5b VS |
4676 | |
4677 | if (HAS_GMCH_DISPLAY(dev)) | |
4678 | palreg = PALETTE(pipe, i); | |
4679 | else | |
4680 | palreg = LGC_PALETTE(pipe, i); | |
4681 | ||
4682 | I915_WRITE(palreg, | |
d77e4531 PZ |
4683 | (intel_crtc->lut_r[i] << 16) | |
4684 | (intel_crtc->lut_g[i] << 8) | | |
4685 | intel_crtc->lut_b[i]); | |
4686 | } | |
4687 | ||
4688 | if (reenable_ips) | |
4689 | hsw_enable_ips(intel_crtc); | |
4690 | } | |
4691 | ||
7cac945f | 4692 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4693 | { |
7cac945f | 4694 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4695 | struct drm_device *dev = intel_crtc->base.dev; |
4696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4697 | ||
4698 | mutex_lock(&dev->struct_mutex); | |
4699 | dev_priv->mm.interruptible = false; | |
4700 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4701 | dev_priv->mm.interruptible = true; | |
4702 | mutex_unlock(&dev->struct_mutex); | |
4703 | } | |
4704 | ||
4705 | /* Let userspace switch the overlay on again. In most cases userspace | |
4706 | * has to recompute where to put it anyway. | |
4707 | */ | |
4708 | } | |
4709 | ||
87d4300a ML |
4710 | /** |
4711 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4712 | * @crtc: the CRTC whose primary plane was just enabled | |
4713 | * | |
4714 | * Performs potentially sleeping operations that must be done after the primary | |
4715 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4716 | * called due to an explicit primary plane update, or due to an implicit | |
4717 | * re-enable that is caused when a sprite plane is updated to no longer | |
4718 | * completely hide the primary plane. | |
4719 | */ | |
4720 | static void | |
4721 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4722 | { |
4723 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4724 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4726 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4727 | |
87d4300a ML |
4728 | /* |
4729 | * FIXME IPS should be fine as long as one plane is | |
4730 | * enabled, but in practice it seems to have problems | |
4731 | * when going from primary only to sprite only and vice | |
4732 | * versa. | |
4733 | */ | |
a5c4d7bc VS |
4734 | hsw_enable_ips(intel_crtc); |
4735 | ||
f99d7069 | 4736 | /* |
87d4300a ML |
4737 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4738 | * So don't enable underrun reporting before at least some planes | |
4739 | * are enabled. | |
4740 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4741 | * but leave the pipe running. | |
f99d7069 | 4742 | */ |
87d4300a ML |
4743 | if (IS_GEN2(dev)) |
4744 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4745 | ||
aca7b684 VS |
4746 | /* Underruns don't always raise interrupts, so check manually. */ |
4747 | intel_check_cpu_fifo_underruns(dev_priv); | |
4748 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4749 | } |
4750 | ||
87d4300a ML |
4751 | /** |
4752 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4753 | * @crtc: the CRTC whose primary plane is to be disabled | |
4754 | * | |
4755 | * Performs potentially sleeping operations that must be done before the | |
4756 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4757 | * be called due to an explicit primary plane update, or due to an implicit | |
4758 | * disable that is caused when a sprite plane completely hides the primary | |
4759 | * plane. | |
4760 | */ | |
4761 | static void | |
4762 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4763 | { |
4764 | struct drm_device *dev = crtc->dev; | |
4765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4767 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4768 | |
87d4300a ML |
4769 | /* |
4770 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4771 | * So diasble underrun reporting before all the planes get disabled. | |
4772 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4773 | * but leave the pipe running. | |
4774 | */ | |
4775 | if (IS_GEN2(dev)) | |
4776 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4777 | |
87d4300a ML |
4778 | /* |
4779 | * Vblank time updates from the shadow to live plane control register | |
4780 | * are blocked if the memory self-refresh mode is active at that | |
4781 | * moment. So to make sure the plane gets truly disabled, disable | |
4782 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4783 | * will be checked/applied by the HW only at the next frame start | |
4784 | * event which is after the vblank start event, so we need to have a | |
4785 | * wait-for-vblank between disabling the plane and the pipe. | |
4786 | */ | |
262cd2e1 | 4787 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4788 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4789 | dev_priv->wm.vlv.cxsr = false; |
4790 | intel_wait_for_vblank(dev, pipe); | |
4791 | } | |
87d4300a | 4792 | |
87d4300a ML |
4793 | /* |
4794 | * FIXME IPS should be fine as long as one plane is | |
4795 | * enabled, but in practice it seems to have problems | |
4796 | * when going from primary only to sprite only and vice | |
4797 | * versa. | |
4798 | */ | |
a5c4d7bc | 4799 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4800 | } |
4801 | ||
ac21b225 ML |
4802 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4803 | { | |
4804 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4805 | struct intel_crtc_state *pipe_config = |
4806 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4807 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4808 | |
4809 | if (atomic->wait_vblank) | |
4810 | intel_wait_for_vblank(dev, crtc->pipe); | |
4811 | ||
4812 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4813 | ||
ab1d3a0e | 4814 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4815 | |
b9001114 | 4816 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4817 | intel_update_watermarks(&crtc->base); |
4818 | ||
c80ac854 | 4819 | if (atomic->update_fbc) |
754d1133 | 4820 | intel_fbc_update(crtc); |
ac21b225 ML |
4821 | |
4822 | if (atomic->post_enable_primary) | |
4823 | intel_post_enable_primary(&crtc->base); | |
4824 | ||
ac21b225 ML |
4825 | memset(atomic, 0, sizeof(*atomic)); |
4826 | } | |
4827 | ||
4828 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4829 | { | |
4830 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4831 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4832 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4833 | struct intel_crtc_state *pipe_config = |
4834 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4835 | |
c80ac854 | 4836 | if (atomic->disable_fbc) |
d029bcad | 4837 | intel_fbc_deactivate(crtc); |
ac21b225 | 4838 | |
066cf55b RV |
4839 | if (crtc->atomic.disable_ips) |
4840 | hsw_disable_ips(crtc); | |
4841 | ||
ac21b225 ML |
4842 | if (atomic->pre_disable_primary) |
4843 | intel_pre_disable_primary(&crtc->base); | |
852eb00d | 4844 | |
ab1d3a0e | 4845 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4846 | crtc->wm.cxsr_allowed = false; |
4847 | intel_set_memory_cxsr(dev_priv, false); | |
4848 | } | |
92826fcd ML |
4849 | |
4850 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) | |
4851 | intel_update_watermarks(&crtc->base); | |
ac21b225 ML |
4852 | } |
4853 | ||
d032ffa0 | 4854 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4855 | { |
4856 | struct drm_device *dev = crtc->dev; | |
4857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4858 | struct drm_plane *p; |
87d4300a ML |
4859 | int pipe = intel_crtc->pipe; |
4860 | ||
7cac945f | 4861 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4862 | |
d032ffa0 ML |
4863 | drm_for_each_plane_mask(p, dev, plane_mask) |
4864 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4865 | |
f99d7069 DV |
4866 | /* |
4867 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4868 | * to compute the mask of flip planes precisely. For the time being | |
4869 | * consider this a flip to a NULL plane. | |
4870 | */ | |
4871 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4872 | } |
4873 | ||
f67a559d JB |
4874 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4875 | { | |
4876 | struct drm_device *dev = crtc->dev; | |
4877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4879 | struct intel_encoder *encoder; |
f67a559d | 4880 | int pipe = intel_crtc->pipe; |
f67a559d | 4881 | |
53d9f4e9 | 4882 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4883 | return; |
4884 | ||
81b088ca VS |
4885 | if (intel_crtc->config->has_pch_encoder) |
4886 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4887 | ||
6e3c9717 | 4888 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4889 | intel_prepare_shared_dpll(intel_crtc); |
4890 | ||
6e3c9717 | 4891 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4892 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4893 | |
4894 | intel_set_pipe_timings(intel_crtc); | |
4895 | ||
6e3c9717 | 4896 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4897 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4898 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4899 | } |
4900 | ||
4901 | ironlake_set_pipeconf(crtc); | |
4902 | ||
f67a559d | 4903 | intel_crtc->active = true; |
8664281b | 4904 | |
a72e4c9f | 4905 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4906 | |
f6736a1a | 4907 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4908 | if (encoder->pre_enable) |
4909 | encoder->pre_enable(encoder); | |
f67a559d | 4910 | |
6e3c9717 | 4911 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4912 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4913 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4914 | * enabling. */ | |
88cefb6c | 4915 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4916 | } else { |
4917 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4918 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4919 | } | |
f67a559d | 4920 | |
b074cec8 | 4921 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4922 | |
9c54c0dd JB |
4923 | /* |
4924 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4925 | * clocks enabled | |
4926 | */ | |
4927 | intel_crtc_load_lut(crtc); | |
4928 | ||
f37fcc2a | 4929 | intel_update_watermarks(crtc); |
e1fdc473 | 4930 | intel_enable_pipe(intel_crtc); |
f67a559d | 4931 | |
6e3c9717 | 4932 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4933 | ironlake_pch_enable(crtc); |
c98e9dcf | 4934 | |
f9b61ff6 DV |
4935 | assert_vblank_disabled(crtc); |
4936 | drm_crtc_vblank_on(crtc); | |
4937 | ||
fa5c73b1 DV |
4938 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4939 | encoder->enable(encoder); | |
61b77ddd DV |
4940 | |
4941 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4942 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4943 | |
4944 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4945 | if (intel_crtc->config->has_pch_encoder) | |
4946 | intel_wait_for_vblank(dev, pipe); | |
4947 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
4948 | |
4949 | intel_fbc_enable(intel_crtc); | |
6be4a607 JB |
4950 | } |
4951 | ||
42db64ef PZ |
4952 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4953 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4954 | { | |
f5adf94e | 4955 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4956 | } |
4957 | ||
4f771f10 PZ |
4958 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4959 | { | |
4960 | struct drm_device *dev = crtc->dev; | |
4961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4963 | struct intel_encoder *encoder; | |
99d736a2 ML |
4964 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4965 | struct intel_crtc_state *pipe_config = | |
4966 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4967 | |
53d9f4e9 | 4968 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4969 | return; |
4970 | ||
81b088ca VS |
4971 | if (intel_crtc->config->has_pch_encoder) |
4972 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4973 | false); | |
4974 | ||
df8ad70c DV |
4975 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4976 | intel_enable_shared_dpll(intel_crtc); | |
4977 | ||
6e3c9717 | 4978 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4979 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4980 | |
4981 | intel_set_pipe_timings(intel_crtc); | |
4982 | ||
6e3c9717 ACO |
4983 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4984 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4985 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4986 | } |
4987 | ||
6e3c9717 | 4988 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4989 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4990 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4991 | } |
4992 | ||
4993 | haswell_set_pipeconf(crtc); | |
4994 | ||
4995 | intel_set_pipe_csc(crtc); | |
4996 | ||
4f771f10 | 4997 | intel_crtc->active = true; |
8664281b | 4998 | |
6b698516 DV |
4999 | if (intel_crtc->config->has_pch_encoder) |
5000 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5001 | else | |
5002 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5003 | ||
7d4aefd0 | 5004 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5005 | if (encoder->pre_enable) |
5006 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5007 | } |
4f771f10 | 5008 | |
d2d65408 | 5009 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5010 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5011 | |
a65347ba | 5012 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5013 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5014 | |
1c132b44 | 5015 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5016 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5017 | else |
1c132b44 | 5018 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5019 | |
5020 | /* | |
5021 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5022 | * clocks enabled | |
5023 | */ | |
5024 | intel_crtc_load_lut(crtc); | |
5025 | ||
1f544388 | 5026 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5027 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5028 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5029 | |
f37fcc2a | 5030 | intel_update_watermarks(crtc); |
e1fdc473 | 5031 | intel_enable_pipe(intel_crtc); |
42db64ef | 5032 | |
6e3c9717 | 5033 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5034 | lpt_pch_enable(crtc); |
4f771f10 | 5035 | |
a65347ba | 5036 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5037 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5038 | ||
f9b61ff6 DV |
5039 | assert_vblank_disabled(crtc); |
5040 | drm_crtc_vblank_on(crtc); | |
5041 | ||
8807e55b | 5042 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5043 | encoder->enable(encoder); |
8807e55b JN |
5044 | intel_opregion_notify_encoder(encoder, true); |
5045 | } | |
4f771f10 | 5046 | |
6b698516 DV |
5047 | if (intel_crtc->config->has_pch_encoder) { |
5048 | intel_wait_for_vblank(dev, pipe); | |
5049 | intel_wait_for_vblank(dev, pipe); | |
5050 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5051 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5052 | true); | |
6b698516 | 5053 | } |
d2d65408 | 5054 | |
e4916946 PZ |
5055 | /* If we change the relative order between pipe/planes enabling, we need |
5056 | * to change the workaround. */ | |
99d736a2 ML |
5057 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5058 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5059 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5060 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5061 | } | |
d029bcad PZ |
5062 | |
5063 | intel_fbc_enable(intel_crtc); | |
4f771f10 PZ |
5064 | } |
5065 | ||
bfd16b2a | 5066 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5067 | { |
5068 | struct drm_device *dev = crtc->base.dev; | |
5069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5070 | int pipe = crtc->pipe; | |
5071 | ||
5072 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5073 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5074 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5075 | I915_WRITE(PF_CTL(pipe), 0); |
5076 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5077 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5078 | } | |
5079 | } | |
5080 | ||
6be4a607 JB |
5081 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5082 | { | |
5083 | struct drm_device *dev = crtc->dev; | |
5084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5086 | struct intel_encoder *encoder; |
6be4a607 | 5087 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5088 | |
37ca8d4c VS |
5089 | if (intel_crtc->config->has_pch_encoder) |
5090 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5091 | ||
ea9d758d DV |
5092 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5093 | encoder->disable(encoder); | |
5094 | ||
f9b61ff6 DV |
5095 | drm_crtc_vblank_off(crtc); |
5096 | assert_vblank_disabled(crtc); | |
5097 | ||
3860b2ec VS |
5098 | /* |
5099 | * Sometimes spurious CPU pipe underruns happen when the | |
5100 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5101 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5102 | */ | |
5103 | if (intel_crtc->config->has_pch_encoder) | |
5104 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5105 | ||
575f7ab7 | 5106 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5107 | |
bfd16b2a | 5108 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5109 | |
3860b2ec | 5110 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5111 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5112 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5113 | } | |
5a74f70a | 5114 | |
bf49ec8c DV |
5115 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5116 | if (encoder->post_disable) | |
5117 | encoder->post_disable(encoder); | |
2c07245f | 5118 | |
6e3c9717 | 5119 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5120 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5121 | |
d925c59a | 5122 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5123 | i915_reg_t reg; |
5124 | u32 temp; | |
5125 | ||
d925c59a DV |
5126 | /* disable TRANS_DP_CTL */ |
5127 | reg = TRANS_DP_CTL(pipe); | |
5128 | temp = I915_READ(reg); | |
5129 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5130 | TRANS_DP_PORT_SEL_MASK); | |
5131 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5132 | I915_WRITE(reg, temp); | |
5133 | ||
5134 | /* disable DPLL_SEL */ | |
5135 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5136 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5137 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5138 | } |
e3421a18 | 5139 | |
d925c59a DV |
5140 | ironlake_fdi_pll_disable(intel_crtc); |
5141 | } | |
81b088ca VS |
5142 | |
5143 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
5144 | |
5145 | intel_fbc_disable_crtc(intel_crtc); | |
6be4a607 | 5146 | } |
1b3c7a47 | 5147 | |
4f771f10 | 5148 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5149 | { |
4f771f10 PZ |
5150 | struct drm_device *dev = crtc->dev; |
5151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5153 | struct intel_encoder *encoder; |
6e3c9717 | 5154 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5155 | |
d2d65408 VS |
5156 | if (intel_crtc->config->has_pch_encoder) |
5157 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5158 | false); | |
5159 | ||
8807e55b JN |
5160 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5161 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5162 | encoder->disable(encoder); |
8807e55b | 5163 | } |
4f771f10 | 5164 | |
f9b61ff6 DV |
5165 | drm_crtc_vblank_off(crtc); |
5166 | assert_vblank_disabled(crtc); | |
5167 | ||
575f7ab7 | 5168 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5169 | |
6e3c9717 | 5170 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5171 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5172 | ||
a65347ba | 5173 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5174 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5175 | |
1c132b44 | 5176 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5177 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5178 | else |
bfd16b2a | 5179 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5180 | |
a65347ba | 5181 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5182 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5183 | |
97b040aa ID |
5184 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5185 | if (encoder->post_disable) | |
5186 | encoder->post_disable(encoder); | |
81b088ca | 5187 | |
92966a37 VS |
5188 | if (intel_crtc->config->has_pch_encoder) { |
5189 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5190 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5191 | intel_ddi_fdi_disable(crtc); |
5192 | ||
81b088ca VS |
5193 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5194 | true); | |
92966a37 | 5195 | } |
d029bcad PZ |
5196 | |
5197 | intel_fbc_disable_crtc(intel_crtc); | |
4f771f10 PZ |
5198 | } |
5199 | ||
2dd24552 JB |
5200 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5201 | { | |
5202 | struct drm_device *dev = crtc->base.dev; | |
5203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5204 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5205 | |
681a8504 | 5206 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5207 | return; |
5208 | ||
2dd24552 | 5209 | /* |
c0b03411 DV |
5210 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5211 | * according to register description and PRM. | |
2dd24552 | 5212 | */ |
c0b03411 DV |
5213 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5214 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5215 | |
b074cec8 JB |
5216 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5217 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5218 | |
5219 | /* Border color in case we don't scale up to the full screen. Black by | |
5220 | * default, change to something else for debugging. */ | |
5221 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5222 | } |
5223 | ||
d05410f9 DA |
5224 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5225 | { | |
5226 | switch (port) { | |
5227 | case PORT_A: | |
6331a704 | 5228 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5229 | case PORT_B: |
6331a704 | 5230 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5231 | case PORT_C: |
6331a704 | 5232 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5233 | case PORT_D: |
6331a704 | 5234 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5235 | case PORT_E: |
6331a704 | 5236 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5237 | default: |
b9fec167 | 5238 | MISSING_CASE(port); |
d05410f9 DA |
5239 | return POWER_DOMAIN_PORT_OTHER; |
5240 | } | |
5241 | } | |
5242 | ||
25f78f58 VS |
5243 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5244 | { | |
5245 | switch (port) { | |
5246 | case PORT_A: | |
5247 | return POWER_DOMAIN_AUX_A; | |
5248 | case PORT_B: | |
5249 | return POWER_DOMAIN_AUX_B; | |
5250 | case PORT_C: | |
5251 | return POWER_DOMAIN_AUX_C; | |
5252 | case PORT_D: | |
5253 | return POWER_DOMAIN_AUX_D; | |
5254 | case PORT_E: | |
5255 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5256 | return POWER_DOMAIN_AUX_D; | |
5257 | default: | |
b9fec167 | 5258 | MISSING_CASE(port); |
25f78f58 VS |
5259 | return POWER_DOMAIN_AUX_A; |
5260 | } | |
5261 | } | |
5262 | ||
319be8ae ID |
5263 | enum intel_display_power_domain |
5264 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5265 | { | |
5266 | struct drm_device *dev = intel_encoder->base.dev; | |
5267 | struct intel_digital_port *intel_dig_port; | |
5268 | ||
5269 | switch (intel_encoder->type) { | |
5270 | case INTEL_OUTPUT_UNKNOWN: | |
5271 | /* Only DDI platforms should ever use this output type */ | |
5272 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5273 | case INTEL_OUTPUT_DISPLAYPORT: | |
5274 | case INTEL_OUTPUT_HDMI: | |
5275 | case INTEL_OUTPUT_EDP: | |
5276 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5277 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5278 | case INTEL_OUTPUT_DP_MST: |
5279 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5280 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5281 | case INTEL_OUTPUT_ANALOG: |
5282 | return POWER_DOMAIN_PORT_CRT; | |
5283 | case INTEL_OUTPUT_DSI: | |
5284 | return POWER_DOMAIN_PORT_DSI; | |
5285 | default: | |
5286 | return POWER_DOMAIN_PORT_OTHER; | |
5287 | } | |
5288 | } | |
5289 | ||
25f78f58 VS |
5290 | enum intel_display_power_domain |
5291 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5292 | { | |
5293 | struct drm_device *dev = intel_encoder->base.dev; | |
5294 | struct intel_digital_port *intel_dig_port; | |
5295 | ||
5296 | switch (intel_encoder->type) { | |
5297 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5298 | case INTEL_OUTPUT_HDMI: |
5299 | /* | |
5300 | * Only DDI platforms should ever use these output types. | |
5301 | * We can get here after the HDMI detect code has already set | |
5302 | * the type of the shared encoder. Since we can't be sure | |
5303 | * what's the status of the given connectors, play safe and | |
5304 | * run the DP detection too. | |
5305 | */ | |
25f78f58 VS |
5306 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5307 | case INTEL_OUTPUT_DISPLAYPORT: | |
5308 | case INTEL_OUTPUT_EDP: | |
5309 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5310 | return port_to_aux_power_domain(intel_dig_port->port); | |
5311 | case INTEL_OUTPUT_DP_MST: | |
5312 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5313 | return port_to_aux_power_domain(intel_dig_port->port); | |
5314 | default: | |
b9fec167 | 5315 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5316 | return POWER_DOMAIN_AUX_A; |
5317 | } | |
5318 | } | |
5319 | ||
319be8ae | 5320 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5321 | { |
319be8ae ID |
5322 | struct drm_device *dev = crtc->dev; |
5323 | struct intel_encoder *intel_encoder; | |
5324 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5325 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5326 | unsigned long mask; |
1a70a728 | 5327 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5328 | |
292b990e ML |
5329 | if (!crtc->state->active) |
5330 | return 0; | |
5331 | ||
77d22dca ID |
5332 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5333 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5334 | if (intel_crtc->config->pch_pfit.enabled || |
5335 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5336 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5337 | ||
319be8ae ID |
5338 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5339 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5340 | ||
77d22dca ID |
5341 | return mask; |
5342 | } | |
5343 | ||
292b990e | 5344 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5345 | { |
292b990e ML |
5346 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5348 | enum intel_display_power_domain domain; | |
5349 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5350 | |
292b990e ML |
5351 | old_domains = intel_crtc->enabled_power_domains; |
5352 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5353 | |
292b990e ML |
5354 | domains = new_domains & ~old_domains; |
5355 | ||
5356 | for_each_power_domain(domain, domains) | |
5357 | intel_display_power_get(dev_priv, domain); | |
5358 | ||
5359 | return old_domains & ~new_domains; | |
5360 | } | |
5361 | ||
5362 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5363 | unsigned long domains) | |
5364 | { | |
5365 | enum intel_display_power_domain domain; | |
5366 | ||
5367 | for_each_power_domain(domain, domains) | |
5368 | intel_display_power_put(dev_priv, domain); | |
5369 | } | |
77d22dca | 5370 | |
292b990e ML |
5371 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5372 | { | |
1a617b77 | 5373 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5374 | struct drm_device *dev = state->dev; |
5375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5376 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5377 | struct drm_crtc_state *crtc_state; | |
5378 | struct drm_crtc *crtc; | |
5379 | int i; | |
77d22dca | 5380 | |
292b990e ML |
5381 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5382 | if (needs_modeset(crtc->state)) | |
5383 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5384 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5385 | } |
5386 | ||
1a617b77 ML |
5387 | if (dev_priv->display.modeset_commit_cdclk && |
5388 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5389 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5390 | |
292b990e ML |
5391 | for (i = 0; i < I915_MAX_PIPES; i++) |
5392 | if (put_domains[i]) | |
5393 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5394 | } |
5395 | ||
adafdc6f MK |
5396 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5397 | { | |
5398 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5399 | ||
5400 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5401 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5402 | return max_cdclk_freq; | |
5403 | else if (IS_CHERRYVIEW(dev_priv)) | |
5404 | return max_cdclk_freq*95/100; | |
5405 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5406 | return 2*max_cdclk_freq*90/100; | |
5407 | else | |
5408 | return max_cdclk_freq*90/100; | |
5409 | } | |
5410 | ||
560a7ae4 DL |
5411 | static void intel_update_max_cdclk(struct drm_device *dev) |
5412 | { | |
5413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5414 | ||
ef11bdb3 | 5415 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5416 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5417 | ||
5418 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5419 | dev_priv->max_cdclk_freq = 675000; | |
5420 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5421 | dev_priv->max_cdclk_freq = 540000; | |
5422 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5423 | dev_priv->max_cdclk_freq = 450000; | |
5424 | else | |
5425 | dev_priv->max_cdclk_freq = 337500; | |
5426 | } else if (IS_BROADWELL(dev)) { | |
5427 | /* | |
5428 | * FIXME with extra cooling we can allow | |
5429 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5430 | * How can we know if extra cooling is | |
5431 | * available? PCI ID, VTB, something else? | |
5432 | */ | |
5433 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5434 | dev_priv->max_cdclk_freq = 450000; | |
5435 | else if (IS_BDW_ULX(dev)) | |
5436 | dev_priv->max_cdclk_freq = 450000; | |
5437 | else if (IS_BDW_ULT(dev)) | |
5438 | dev_priv->max_cdclk_freq = 540000; | |
5439 | else | |
5440 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5441 | } else if (IS_CHERRYVIEW(dev)) { |
5442 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5443 | } else if (IS_VALLEYVIEW(dev)) { |
5444 | dev_priv->max_cdclk_freq = 400000; | |
5445 | } else { | |
5446 | /* otherwise assume cdclk is fixed */ | |
5447 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5448 | } | |
5449 | ||
adafdc6f MK |
5450 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5451 | ||
560a7ae4 DL |
5452 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5453 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5454 | |
5455 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5456 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5457 | } |
5458 | ||
5459 | static void intel_update_cdclk(struct drm_device *dev) | |
5460 | { | |
5461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5462 | ||
5463 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5464 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5465 | dev_priv->cdclk_freq); | |
5466 | ||
5467 | /* | |
5468 | * Program the gmbus_freq based on the cdclk frequency. | |
5469 | * BSpec erroneously claims we should aim for 4MHz, but | |
5470 | * in fact 1MHz is the correct frequency. | |
5471 | */ | |
666a4537 | 5472 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5473 | /* |
5474 | * Program the gmbus_freq based on the cdclk frequency. | |
5475 | * BSpec erroneously claims we should aim for 4MHz, but | |
5476 | * in fact 1MHz is the correct frequency. | |
5477 | */ | |
5478 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5479 | } | |
5480 | ||
5481 | if (dev_priv->max_cdclk_freq == 0) | |
5482 | intel_update_max_cdclk(dev); | |
5483 | } | |
5484 | ||
70d0c574 | 5485 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5486 | { |
5487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5488 | uint32_t divider; | |
5489 | uint32_t ratio; | |
5490 | uint32_t current_freq; | |
5491 | int ret; | |
5492 | ||
5493 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5494 | switch (frequency) { | |
5495 | case 144000: | |
5496 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5497 | ratio = BXT_DE_PLL_RATIO(60); | |
5498 | break; | |
5499 | case 288000: | |
5500 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5501 | ratio = BXT_DE_PLL_RATIO(60); | |
5502 | break; | |
5503 | case 384000: | |
5504 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5505 | ratio = BXT_DE_PLL_RATIO(60); | |
5506 | break; | |
5507 | case 576000: | |
5508 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5509 | ratio = BXT_DE_PLL_RATIO(60); | |
5510 | break; | |
5511 | case 624000: | |
5512 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5513 | ratio = BXT_DE_PLL_RATIO(65); | |
5514 | break; | |
5515 | case 19200: | |
5516 | /* | |
5517 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5518 | * to suppress GCC warning. | |
5519 | */ | |
5520 | ratio = 0; | |
5521 | divider = 0; | |
5522 | break; | |
5523 | default: | |
5524 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5525 | ||
5526 | return; | |
5527 | } | |
5528 | ||
5529 | mutex_lock(&dev_priv->rps.hw_lock); | |
5530 | /* Inform power controller of upcoming frequency change */ | |
5531 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5532 | 0x80000000); | |
5533 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5534 | ||
5535 | if (ret) { | |
5536 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5537 | ret, frequency); | |
5538 | return; | |
5539 | } | |
5540 | ||
5541 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5542 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5543 | current_freq = current_freq * 500 + 1000; | |
5544 | ||
5545 | /* | |
5546 | * DE PLL has to be disabled when | |
5547 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5548 | * - before setting to 624MHz (PLL needs toggling) | |
5549 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5550 | */ | |
5551 | if (frequency == 19200 || frequency == 624000 || | |
5552 | current_freq == 624000) { | |
5553 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5554 | /* Timeout 200us */ | |
5555 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5556 | 1)) | |
5557 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5558 | } | |
5559 | ||
5560 | if (frequency != 19200) { | |
5561 | uint32_t val; | |
5562 | ||
5563 | val = I915_READ(BXT_DE_PLL_CTL); | |
5564 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5565 | val |= ratio; | |
5566 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5567 | ||
5568 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5569 | /* Timeout 200us */ | |
5570 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5571 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5572 | ||
5573 | val = I915_READ(CDCLK_CTL); | |
5574 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5575 | val |= divider; | |
5576 | /* | |
5577 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5578 | * enable otherwise. | |
5579 | */ | |
5580 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5581 | if (frequency >= 500000) | |
5582 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5583 | ||
5584 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5585 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5586 | val |= (frequency - 1000) / 500; | |
5587 | I915_WRITE(CDCLK_CTL, val); | |
5588 | } | |
5589 | ||
5590 | mutex_lock(&dev_priv->rps.hw_lock); | |
5591 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5592 | DIV_ROUND_UP(frequency, 25000)); | |
5593 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5594 | ||
5595 | if (ret) { | |
5596 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5597 | ret, frequency); | |
5598 | return; | |
5599 | } | |
5600 | ||
a47871bd | 5601 | intel_update_cdclk(dev); |
f8437dd1 VK |
5602 | } |
5603 | ||
5604 | void broxton_init_cdclk(struct drm_device *dev) | |
5605 | { | |
5606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5607 | uint32_t val; | |
5608 | ||
5609 | /* | |
5610 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5611 | * or else the reset will hang because there is no PCH to respond. | |
5612 | * Move the handshake programming to initialization sequence. | |
5613 | * Previously was left up to BIOS. | |
5614 | */ | |
5615 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5616 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5617 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5618 | ||
5619 | /* Enable PG1 for cdclk */ | |
5620 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5621 | ||
5622 | /* check if cd clock is enabled */ | |
5623 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5624 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5625 | return; | |
5626 | } | |
5627 | ||
5628 | /* | |
5629 | * FIXME: | |
5630 | * - The initial CDCLK needs to be read from VBT. | |
5631 | * Need to make this change after VBT has changes for BXT. | |
5632 | * - check if setting the max (or any) cdclk freq is really necessary | |
5633 | * here, it belongs to modeset time | |
5634 | */ | |
5635 | broxton_set_cdclk(dev, 624000); | |
5636 | ||
5637 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5638 | POSTING_READ(DBUF_CTL); |
5639 | ||
f8437dd1 VK |
5640 | udelay(10); |
5641 | ||
5642 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5643 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5644 | } | |
5645 | ||
5646 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5647 | { | |
5648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5649 | ||
5650 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5651 | POSTING_READ(DBUF_CTL); |
5652 | ||
f8437dd1 VK |
5653 | udelay(10); |
5654 | ||
5655 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5656 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5657 | ||
5658 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5659 | broxton_set_cdclk(dev, 19200); | |
5660 | ||
5661 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5662 | } | |
5663 | ||
5d96d8af DL |
5664 | static const struct skl_cdclk_entry { |
5665 | unsigned int freq; | |
5666 | unsigned int vco; | |
5667 | } skl_cdclk_frequencies[] = { | |
5668 | { .freq = 308570, .vco = 8640 }, | |
5669 | { .freq = 337500, .vco = 8100 }, | |
5670 | { .freq = 432000, .vco = 8640 }, | |
5671 | { .freq = 450000, .vco = 8100 }, | |
5672 | { .freq = 540000, .vco = 8100 }, | |
5673 | { .freq = 617140, .vco = 8640 }, | |
5674 | { .freq = 675000, .vco = 8100 }, | |
5675 | }; | |
5676 | ||
5677 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5678 | { | |
5679 | return (freq - 1000) / 500; | |
5680 | } | |
5681 | ||
5682 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5683 | { | |
5684 | unsigned int i; | |
5685 | ||
5686 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5687 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5688 | ||
5689 | if (e->freq == freq) | |
5690 | return e->vco; | |
5691 | } | |
5692 | ||
5693 | return 8100; | |
5694 | } | |
5695 | ||
5696 | static void | |
5697 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5698 | { | |
5699 | unsigned int min_freq; | |
5700 | u32 val; | |
5701 | ||
5702 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5703 | val = I915_READ(CDCLK_CTL); | |
5704 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5705 | val |= CDCLK_FREQ_337_308; | |
5706 | ||
5707 | if (required_vco == 8640) | |
5708 | min_freq = 308570; | |
5709 | else | |
5710 | min_freq = 337500; | |
5711 | ||
5712 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5713 | ||
5714 | I915_WRITE(CDCLK_CTL, val); | |
5715 | POSTING_READ(CDCLK_CTL); | |
5716 | ||
5717 | /* | |
5718 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5719 | * taking into account the VCO required to operate the eDP panel at the | |
5720 | * desired frequency. The usual DP link rates operate with a VCO of | |
5721 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5722 | * The modeset code is responsible for the selection of the exact link | |
5723 | * rate later on, with the constraint of choosing a frequency that | |
5724 | * works with required_vco. | |
5725 | */ | |
5726 | val = I915_READ(DPLL_CTRL1); | |
5727 | ||
5728 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5729 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5730 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5731 | if (required_vco == 8640) | |
5732 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5733 | SKL_DPLL0); | |
5734 | else | |
5735 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5736 | SKL_DPLL0); | |
5737 | ||
5738 | I915_WRITE(DPLL_CTRL1, val); | |
5739 | POSTING_READ(DPLL_CTRL1); | |
5740 | ||
5741 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5742 | ||
5743 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5744 | DRM_ERROR("DPLL0 not locked\n"); | |
5745 | } | |
5746 | ||
5747 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5748 | { | |
5749 | int ret; | |
5750 | u32 val; | |
5751 | ||
5752 | /* inform PCU we want to change CDCLK */ | |
5753 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5754 | mutex_lock(&dev_priv->rps.hw_lock); | |
5755 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5756 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5757 | ||
5758 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5759 | } | |
5760 | ||
5761 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5762 | { | |
5763 | unsigned int i; | |
5764 | ||
5765 | for (i = 0; i < 15; i++) { | |
5766 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5767 | return true; | |
5768 | udelay(10); | |
5769 | } | |
5770 | ||
5771 | return false; | |
5772 | } | |
5773 | ||
5774 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5775 | { | |
560a7ae4 | 5776 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5777 | u32 freq_select, pcu_ack; |
5778 | ||
5779 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5780 | ||
5781 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5782 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5783 | return; | |
5784 | } | |
5785 | ||
5786 | /* set CDCLK_CTL */ | |
5787 | switch(freq) { | |
5788 | case 450000: | |
5789 | case 432000: | |
5790 | freq_select = CDCLK_FREQ_450_432; | |
5791 | pcu_ack = 1; | |
5792 | break; | |
5793 | case 540000: | |
5794 | freq_select = CDCLK_FREQ_540; | |
5795 | pcu_ack = 2; | |
5796 | break; | |
5797 | case 308570: | |
5798 | case 337500: | |
5799 | default: | |
5800 | freq_select = CDCLK_FREQ_337_308; | |
5801 | pcu_ack = 0; | |
5802 | break; | |
5803 | case 617140: | |
5804 | case 675000: | |
5805 | freq_select = CDCLK_FREQ_675_617; | |
5806 | pcu_ack = 3; | |
5807 | break; | |
5808 | } | |
5809 | ||
5810 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5811 | POSTING_READ(CDCLK_CTL); | |
5812 | ||
5813 | /* inform PCU of the change */ | |
5814 | mutex_lock(&dev_priv->rps.hw_lock); | |
5815 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5816 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5817 | |
5818 | intel_update_cdclk(dev); | |
5d96d8af DL |
5819 | } |
5820 | ||
5821 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5822 | { | |
5823 | /* disable DBUF power */ | |
5824 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5825 | POSTING_READ(DBUF_CTL); | |
5826 | ||
5827 | udelay(10); | |
5828 | ||
5829 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5830 | DRM_ERROR("DBuf power disable timeout\n"); | |
5831 | ||
ab96c1ee ID |
5832 | /* disable DPLL0 */ |
5833 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5834 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5835 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5836 | } |
5837 | ||
5838 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5839 | { | |
5d96d8af DL |
5840 | unsigned int required_vco; |
5841 | ||
39d9b85a GW |
5842 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5843 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5844 | /* enable DPLL0 */ | |
5845 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5846 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5847 | } |
5848 | ||
5d96d8af DL |
5849 | /* set CDCLK to the frequency the BIOS chose */ |
5850 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5851 | ||
5852 | /* enable DBUF power */ | |
5853 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5854 | POSTING_READ(DBUF_CTL); | |
5855 | ||
5856 | udelay(10); | |
5857 | ||
5858 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5859 | DRM_ERROR("DBuf power enable timeout\n"); | |
5860 | } | |
5861 | ||
c73666f3 SK |
5862 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5863 | { | |
5864 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5865 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5866 | int freq = dev_priv->skl_boot_cdclk; | |
5867 | ||
f1b391a5 SK |
5868 | /* |
5869 | * check if the pre-os intialized the display | |
5870 | * There is SWF18 scratchpad register defined which is set by the | |
5871 | * pre-os which can be used by the OS drivers to check the status | |
5872 | */ | |
5873 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5874 | goto sanitize; | |
5875 | ||
c73666f3 SK |
5876 | /* Is PLL enabled and locked ? */ |
5877 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5878 | goto sanitize; | |
5879 | ||
5880 | /* DPLL okay; verify the cdclock | |
5881 | * | |
5882 | * Noticed in some instances that the freq selection is correct but | |
5883 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5884 | * enable display. Verify the same as well. | |
5885 | */ | |
5886 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5887 | /* All well; nothing to sanitize */ | |
5888 | return false; | |
5889 | sanitize: | |
5890 | /* | |
5891 | * As of now initialize with max cdclk till | |
5892 | * we get dynamic cdclk support | |
5893 | * */ | |
5894 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5895 | skl_init_cdclk(dev_priv); | |
5896 | ||
5897 | /* we did have to sanitize */ | |
5898 | return true; | |
5899 | } | |
5900 | ||
30a970c6 JB |
5901 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5902 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5903 | { | |
5904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5905 | u32 val, cmd; | |
5906 | ||
164dfd28 VK |
5907 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5908 | != dev_priv->cdclk_freq); | |
d60c4473 | 5909 | |
dfcab17e | 5910 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5911 | cmd = 2; |
dfcab17e | 5912 | else if (cdclk == 266667) |
30a970c6 JB |
5913 | cmd = 1; |
5914 | else | |
5915 | cmd = 0; | |
5916 | ||
5917 | mutex_lock(&dev_priv->rps.hw_lock); | |
5918 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5919 | val &= ~DSPFREQGUAR_MASK; | |
5920 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5921 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5922 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5923 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5924 | 50)) { | |
5925 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5926 | } | |
5927 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5928 | ||
54433e91 VS |
5929 | mutex_lock(&dev_priv->sb_lock); |
5930 | ||
dfcab17e | 5931 | if (cdclk == 400000) { |
6bcda4f0 | 5932 | u32 divider; |
30a970c6 | 5933 | |
6bcda4f0 | 5934 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5935 | |
30a970c6 JB |
5936 | /* adjust cdclk divider */ |
5937 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5938 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5939 | val |= divider; |
5940 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5941 | |
5942 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5943 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5944 | 50)) |
5945 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5946 | } |
5947 | ||
30a970c6 JB |
5948 | /* adjust self-refresh exit latency value */ |
5949 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5950 | val &= ~0x7f; | |
5951 | ||
5952 | /* | |
5953 | * For high bandwidth configs, we set a higher latency in the bunit | |
5954 | * so that the core display fetch happens in time to avoid underruns. | |
5955 | */ | |
dfcab17e | 5956 | if (cdclk == 400000) |
30a970c6 JB |
5957 | val |= 4500 / 250; /* 4.5 usec */ |
5958 | else | |
5959 | val |= 3000 / 250; /* 3.0 usec */ | |
5960 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5961 | |
a580516d | 5962 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5963 | |
b6283055 | 5964 | intel_update_cdclk(dev); |
30a970c6 JB |
5965 | } |
5966 | ||
383c5a6a VS |
5967 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5968 | { | |
5969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5970 | u32 val, cmd; | |
5971 | ||
164dfd28 VK |
5972 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5973 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5974 | |
5975 | switch (cdclk) { | |
383c5a6a VS |
5976 | case 333333: |
5977 | case 320000: | |
383c5a6a | 5978 | case 266667: |
383c5a6a | 5979 | case 200000: |
383c5a6a VS |
5980 | break; |
5981 | default: | |
5f77eeb0 | 5982 | MISSING_CASE(cdclk); |
383c5a6a VS |
5983 | return; |
5984 | } | |
5985 | ||
9d0d3fda VS |
5986 | /* |
5987 | * Specs are full of misinformation, but testing on actual | |
5988 | * hardware has shown that we just need to write the desired | |
5989 | * CCK divider into the Punit register. | |
5990 | */ | |
5991 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5992 | ||
383c5a6a VS |
5993 | mutex_lock(&dev_priv->rps.hw_lock); |
5994 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5995 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5996 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5997 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5998 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5999 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6000 | 50)) { | |
6001 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6002 | } | |
6003 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6004 | ||
b6283055 | 6005 | intel_update_cdclk(dev); |
383c5a6a VS |
6006 | } |
6007 | ||
30a970c6 JB |
6008 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6009 | int max_pixclk) | |
6010 | { | |
6bcda4f0 | 6011 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6012 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6013 | |
30a970c6 JB |
6014 | /* |
6015 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6016 | * 200MHz | |
6017 | * 267MHz | |
29dc7ef3 | 6018 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6019 | * 400MHz (VLV only) |
6020 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6021 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6022 | * |
6023 | * We seem to get an unstable or solid color picture at 200MHz. | |
6024 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6025 | * are off. | |
30a970c6 | 6026 | */ |
6cca3195 VS |
6027 | if (!IS_CHERRYVIEW(dev_priv) && |
6028 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6029 | return 400000; |
6cca3195 | 6030 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6031 | return freq_320; |
e37c67a1 | 6032 | else if (max_pixclk > 0) |
dfcab17e | 6033 | return 266667; |
e37c67a1 VS |
6034 | else |
6035 | return 200000; | |
30a970c6 JB |
6036 | } |
6037 | ||
f8437dd1 VK |
6038 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6039 | int max_pixclk) | |
6040 | { | |
6041 | /* | |
6042 | * FIXME: | |
6043 | * - remove the guardband, it's not needed on BXT | |
6044 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6045 | */ | |
6046 | if (max_pixclk > 576000*9/10) | |
6047 | return 624000; | |
6048 | else if (max_pixclk > 384000*9/10) | |
6049 | return 576000; | |
6050 | else if (max_pixclk > 288000*9/10) | |
6051 | return 384000; | |
6052 | else if (max_pixclk > 144000*9/10) | |
6053 | return 288000; | |
6054 | else | |
6055 | return 144000; | |
6056 | } | |
6057 | ||
a821fc46 ACO |
6058 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6059 | * that's non-NULL, look at current state otherwise. */ | |
6060 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6061 | struct drm_atomic_state *state) | |
30a970c6 | 6062 | { |
565602d7 ML |
6063 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6065 | struct drm_crtc *crtc; | |
6066 | struct drm_crtc_state *crtc_state; | |
6067 | unsigned max_pixclk = 0, i; | |
6068 | enum pipe pipe; | |
30a970c6 | 6069 | |
565602d7 ML |
6070 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6071 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6072 | |
565602d7 ML |
6073 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6074 | int pixclk = 0; | |
6075 | ||
6076 | if (crtc_state->enable) | |
6077 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6078 | |
565602d7 | 6079 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6080 | } |
6081 | ||
565602d7 ML |
6082 | if (!intel_state->active_crtcs) |
6083 | return 0; | |
6084 | ||
6085 | for_each_pipe(dev_priv, pipe) | |
6086 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6087 | ||
30a970c6 JB |
6088 | return max_pixclk; |
6089 | } | |
6090 | ||
27c329ed | 6091 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6092 | { |
27c329ed ML |
6093 | struct drm_device *dev = state->dev; |
6094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6095 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6096 | struct intel_atomic_state *intel_state = |
6097 | to_intel_atomic_state(state); | |
30a970c6 | 6098 | |
304603f4 ACO |
6099 | if (max_pixclk < 0) |
6100 | return max_pixclk; | |
30a970c6 | 6101 | |
1a617b77 | 6102 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6103 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6104 | |
1a617b77 ML |
6105 | if (!intel_state->active_crtcs) |
6106 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6107 | ||
27c329ed ML |
6108 | return 0; |
6109 | } | |
304603f4 | 6110 | |
27c329ed ML |
6111 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6112 | { | |
6113 | struct drm_device *dev = state->dev; | |
6114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6115 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6116 | struct intel_atomic_state *intel_state = |
6117 | to_intel_atomic_state(state); | |
85a96e7a | 6118 | |
27c329ed ML |
6119 | if (max_pixclk < 0) |
6120 | return max_pixclk; | |
85a96e7a | 6121 | |
1a617b77 | 6122 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6123 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6124 | |
1a617b77 ML |
6125 | if (!intel_state->active_crtcs) |
6126 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6127 | ||
27c329ed | 6128 | return 0; |
30a970c6 JB |
6129 | } |
6130 | ||
1e69cd74 VS |
6131 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6132 | { | |
6133 | unsigned int credits, default_credits; | |
6134 | ||
6135 | if (IS_CHERRYVIEW(dev_priv)) | |
6136 | default_credits = PFI_CREDIT(12); | |
6137 | else | |
6138 | default_credits = PFI_CREDIT(8); | |
6139 | ||
bfa7df01 | 6140 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6141 | /* CHV suggested value is 31 or 63 */ |
6142 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6143 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6144 | else |
6145 | credits = PFI_CREDIT(15); | |
6146 | } else { | |
6147 | credits = default_credits; | |
6148 | } | |
6149 | ||
6150 | /* | |
6151 | * WA - write default credits before re-programming | |
6152 | * FIXME: should we also set the resend bit here? | |
6153 | */ | |
6154 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6155 | default_credits); | |
6156 | ||
6157 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6158 | credits | PFI_CREDIT_RESEND); | |
6159 | ||
6160 | /* | |
6161 | * FIXME is this guaranteed to clear | |
6162 | * immediately or should we poll for it? | |
6163 | */ | |
6164 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6165 | } | |
6166 | ||
27c329ed | 6167 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6168 | { |
a821fc46 | 6169 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6170 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6171 | struct intel_atomic_state *old_intel_state = |
6172 | to_intel_atomic_state(old_state); | |
6173 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6174 | |
27c329ed ML |
6175 | /* |
6176 | * FIXME: We can end up here with all power domains off, yet | |
6177 | * with a CDCLK frequency other than the minimum. To account | |
6178 | * for this take the PIPE-A power domain, which covers the HW | |
6179 | * blocks needed for the following programming. This can be | |
6180 | * removed once it's guaranteed that we get here either with | |
6181 | * the minimum CDCLK set, or the required power domains | |
6182 | * enabled. | |
6183 | */ | |
6184 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6185 | |
27c329ed ML |
6186 | if (IS_CHERRYVIEW(dev)) |
6187 | cherryview_set_cdclk(dev, req_cdclk); | |
6188 | else | |
6189 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6190 | |
27c329ed | 6191 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6192 | |
27c329ed | 6193 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6194 | } |
6195 | ||
89b667f8 JB |
6196 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6197 | { | |
6198 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6199 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6201 | struct intel_encoder *encoder; | |
6202 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6203 | |
53d9f4e9 | 6204 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6205 | return; |
6206 | ||
6e3c9717 | 6207 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6208 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6209 | |
6210 | intel_set_pipe_timings(intel_crtc); | |
6211 | ||
c14b0485 VS |
6212 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6214 | ||
6215 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6216 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6217 | } | |
6218 | ||
5b18e57c DV |
6219 | i9xx_set_pipeconf(intel_crtc); |
6220 | ||
89b667f8 | 6221 | intel_crtc->active = true; |
89b667f8 | 6222 | |
a72e4c9f | 6223 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6224 | |
89b667f8 JB |
6225 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6226 | if (encoder->pre_pll_enable) | |
6227 | encoder->pre_pll_enable(encoder); | |
6228 | ||
a65347ba | 6229 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6230 | if (IS_CHERRYVIEW(dev)) { |
6231 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6232 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6233 | } else { |
6234 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6235 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6236 | } |
9d556c99 | 6237 | } |
89b667f8 JB |
6238 | |
6239 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6240 | if (encoder->pre_enable) | |
6241 | encoder->pre_enable(encoder); | |
6242 | ||
2dd24552 JB |
6243 | i9xx_pfit_enable(intel_crtc); |
6244 | ||
63cbb074 VS |
6245 | intel_crtc_load_lut(crtc); |
6246 | ||
e1fdc473 | 6247 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6248 | |
4b3a9526 VS |
6249 | assert_vblank_disabled(crtc); |
6250 | drm_crtc_vblank_on(crtc); | |
6251 | ||
f9b61ff6 DV |
6252 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6253 | encoder->enable(encoder); | |
89b667f8 JB |
6254 | } |
6255 | ||
f13c2ef3 DV |
6256 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6257 | { | |
6258 | struct drm_device *dev = crtc->base.dev; | |
6259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6260 | ||
6e3c9717 ACO |
6261 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6262 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6263 | } |
6264 | ||
0b8765c6 | 6265 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6266 | { |
6267 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6268 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6270 | struct intel_encoder *encoder; |
79e53945 | 6271 | int pipe = intel_crtc->pipe; |
79e53945 | 6272 | |
53d9f4e9 | 6273 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6274 | return; |
6275 | ||
f13c2ef3 DV |
6276 | i9xx_set_pll_dividers(intel_crtc); |
6277 | ||
6e3c9717 | 6278 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6279 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6280 | |
6281 | intel_set_pipe_timings(intel_crtc); | |
6282 | ||
5b18e57c DV |
6283 | i9xx_set_pipeconf(intel_crtc); |
6284 | ||
f7abfe8b | 6285 | intel_crtc->active = true; |
6b383a7f | 6286 | |
4a3436e8 | 6287 | if (!IS_GEN2(dev)) |
a72e4c9f | 6288 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6289 | |
9d6d9f19 MK |
6290 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6291 | if (encoder->pre_enable) | |
6292 | encoder->pre_enable(encoder); | |
6293 | ||
f6736a1a DV |
6294 | i9xx_enable_pll(intel_crtc); |
6295 | ||
2dd24552 JB |
6296 | i9xx_pfit_enable(intel_crtc); |
6297 | ||
63cbb074 VS |
6298 | intel_crtc_load_lut(crtc); |
6299 | ||
f37fcc2a | 6300 | intel_update_watermarks(crtc); |
e1fdc473 | 6301 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6302 | |
4b3a9526 VS |
6303 | assert_vblank_disabled(crtc); |
6304 | drm_crtc_vblank_on(crtc); | |
6305 | ||
f9b61ff6 DV |
6306 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6307 | encoder->enable(encoder); | |
d029bcad PZ |
6308 | |
6309 | intel_fbc_enable(intel_crtc); | |
0b8765c6 | 6310 | } |
79e53945 | 6311 | |
87476d63 DV |
6312 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6313 | { | |
6314 | struct drm_device *dev = crtc->base.dev; | |
6315 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6316 | |
6e3c9717 | 6317 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6318 | return; |
87476d63 | 6319 | |
328d8e82 | 6320 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6321 | |
328d8e82 DV |
6322 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6323 | I915_READ(PFIT_CONTROL)); | |
6324 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6325 | } |
6326 | ||
0b8765c6 JB |
6327 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6328 | { | |
6329 | struct drm_device *dev = crtc->dev; | |
6330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6332 | struct intel_encoder *encoder; |
0b8765c6 | 6333 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6334 | |
6304cd91 VS |
6335 | /* |
6336 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6337 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6338 | * We also need to wait on all gmch platforms because of the |
6339 | * self-refresh mode constraint explained above. | |
6304cd91 | 6340 | */ |
564ed191 | 6341 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6342 | |
4b3a9526 VS |
6343 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6344 | encoder->disable(encoder); | |
6345 | ||
f9b61ff6 DV |
6346 | drm_crtc_vblank_off(crtc); |
6347 | assert_vblank_disabled(crtc); | |
6348 | ||
575f7ab7 | 6349 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6350 | |
87476d63 | 6351 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6352 | |
89b667f8 JB |
6353 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6354 | if (encoder->post_disable) | |
6355 | encoder->post_disable(encoder); | |
6356 | ||
a65347ba | 6357 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6358 | if (IS_CHERRYVIEW(dev)) |
6359 | chv_disable_pll(dev_priv, pipe); | |
6360 | else if (IS_VALLEYVIEW(dev)) | |
6361 | vlv_disable_pll(dev_priv, pipe); | |
6362 | else | |
1c4e0274 | 6363 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6364 | } |
0b8765c6 | 6365 | |
d6db995f VS |
6366 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6367 | if (encoder->post_pll_disable) | |
6368 | encoder->post_pll_disable(encoder); | |
6369 | ||
4a3436e8 | 6370 | if (!IS_GEN2(dev)) |
a72e4c9f | 6371 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
d029bcad PZ |
6372 | |
6373 | intel_fbc_disable_crtc(intel_crtc); | |
0b8765c6 JB |
6374 | } |
6375 | ||
b17d48e2 ML |
6376 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6377 | { | |
6378 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6379 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6380 | enum intel_display_power_domain domain; | |
6381 | unsigned long domains; | |
6382 | ||
6383 | if (!intel_crtc->active) | |
6384 | return; | |
6385 | ||
a539205a | 6386 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6387 | WARN_ON(intel_crtc->unpin_work); |
6388 | ||
a539205a | 6389 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6390 | |
6391 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6392 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6393 | } |
6394 | ||
b17d48e2 | 6395 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6396 | intel_crtc->active = false; |
6397 | intel_update_watermarks(crtc); | |
1f7457b1 | 6398 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6399 | |
6400 | domains = intel_crtc->enabled_power_domains; | |
6401 | for_each_power_domain(domain, domains) | |
6402 | intel_display_power_put(dev_priv, domain); | |
6403 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6404 | |
6405 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6406 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6407 | } |
6408 | ||
6b72d486 ML |
6409 | /* |
6410 | * turn all crtc's off, but do not adjust state | |
6411 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6412 | */ | |
70e0bd74 | 6413 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6414 | { |
70e0bd74 ML |
6415 | struct drm_mode_config *config = &dev->mode_config; |
6416 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6417 | struct drm_atomic_state *state; | |
6b72d486 | 6418 | struct drm_crtc *crtc; |
70e0bd74 ML |
6419 | unsigned crtc_mask = 0; |
6420 | int ret = 0; | |
6421 | ||
6422 | if (WARN_ON(!ctx)) | |
6423 | return 0; | |
6424 | ||
6425 | lockdep_assert_held(&ctx->ww_ctx); | |
6426 | state = drm_atomic_state_alloc(dev); | |
6427 | if (WARN_ON(!state)) | |
6428 | return -ENOMEM; | |
6429 | ||
6430 | state->acquire_ctx = ctx; | |
6431 | state->allow_modeset = true; | |
6432 | ||
6433 | for_each_crtc(dev, crtc) { | |
6434 | struct drm_crtc_state *crtc_state = | |
6435 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6436 | |
70e0bd74 ML |
6437 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6438 | if (ret) | |
6439 | goto free; | |
6440 | ||
6441 | if (!crtc_state->active) | |
6442 | continue; | |
6443 | ||
6444 | crtc_state->active = false; | |
6445 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6446 | } | |
6447 | ||
6448 | if (crtc_mask) { | |
74c090b1 | 6449 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6450 | |
6451 | if (!ret) { | |
6452 | for_each_crtc(dev, crtc) | |
6453 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6454 | crtc->state->active = true; | |
6455 | ||
6456 | return ret; | |
6457 | } | |
6458 | } | |
6459 | ||
6460 | free: | |
6461 | if (ret) | |
6462 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6463 | drm_atomic_state_free(state); | |
6464 | return ret; | |
ee7b9f93 JB |
6465 | } |
6466 | ||
ea5b213a | 6467 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6468 | { |
4ef69c7a | 6469 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6470 | |
ea5b213a CW |
6471 | drm_encoder_cleanup(encoder); |
6472 | kfree(intel_encoder); | |
7e7d76c3 JB |
6473 | } |
6474 | ||
0a91ca29 DV |
6475 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6476 | * internal consistency). */ | |
b980514c | 6477 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6478 | { |
35dd3c64 ML |
6479 | struct drm_crtc *crtc = connector->base.state->crtc; |
6480 | ||
6481 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6482 | connector->base.base.id, | |
6483 | connector->base.name); | |
6484 | ||
0a91ca29 | 6485 | if (connector->get_hw_state(connector)) { |
e85376cb | 6486 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6487 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6488 | |
35dd3c64 ML |
6489 | I915_STATE_WARN(!crtc, |
6490 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6491 | |
35dd3c64 ML |
6492 | if (!crtc) |
6493 | return; | |
6494 | ||
6495 | I915_STATE_WARN(!crtc->state->active, | |
6496 | "connector is active, but attached crtc isn't\n"); | |
6497 | ||
e85376cb | 6498 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6499 | return; |
6500 | ||
e85376cb | 6501 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6502 | "atomic encoder doesn't match attached encoder\n"); |
6503 | ||
e85376cb | 6504 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6505 | "attached encoder crtc differs from connector crtc\n"); |
6506 | } else { | |
4d688a2a ML |
6507 | I915_STATE_WARN(crtc && crtc->state->active, |
6508 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6509 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6510 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6511 | } |
79e53945 JB |
6512 | } |
6513 | ||
08d9bc92 ACO |
6514 | int intel_connector_init(struct intel_connector *connector) |
6515 | { | |
6516 | struct drm_connector_state *connector_state; | |
6517 | ||
6518 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6519 | if (!connector_state) | |
6520 | return -ENOMEM; | |
6521 | ||
6522 | connector->base.state = connector_state; | |
6523 | return 0; | |
6524 | } | |
6525 | ||
6526 | struct intel_connector *intel_connector_alloc(void) | |
6527 | { | |
6528 | struct intel_connector *connector; | |
6529 | ||
6530 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6531 | if (!connector) | |
6532 | return NULL; | |
6533 | ||
6534 | if (intel_connector_init(connector) < 0) { | |
6535 | kfree(connector); | |
6536 | return NULL; | |
6537 | } | |
6538 | ||
6539 | return connector; | |
6540 | } | |
6541 | ||
f0947c37 DV |
6542 | /* Simple connector->get_hw_state implementation for encoders that support only |
6543 | * one connector and no cloning and hence the encoder state determines the state | |
6544 | * of the connector. */ | |
6545 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6546 | { |
24929352 | 6547 | enum pipe pipe = 0; |
f0947c37 | 6548 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6549 | |
f0947c37 | 6550 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6551 | } |
6552 | ||
6d293983 | 6553 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6554 | { |
6d293983 ACO |
6555 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6556 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6557 | |
6558 | return 0; | |
6559 | } | |
6560 | ||
6d293983 | 6561 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6562 | struct intel_crtc_state *pipe_config) |
1857e1da | 6563 | { |
6d293983 ACO |
6564 | struct drm_atomic_state *state = pipe_config->base.state; |
6565 | struct intel_crtc *other_crtc; | |
6566 | struct intel_crtc_state *other_crtc_state; | |
6567 | ||
1857e1da DV |
6568 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6569 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6570 | if (pipe_config->fdi_lanes > 4) { | |
6571 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6572 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6573 | return -EINVAL; |
1857e1da DV |
6574 | } |
6575 | ||
bafb6553 | 6576 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6577 | if (pipe_config->fdi_lanes > 2) { |
6578 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6579 | pipe_config->fdi_lanes); | |
6d293983 | 6580 | return -EINVAL; |
1857e1da | 6581 | } else { |
6d293983 | 6582 | return 0; |
1857e1da DV |
6583 | } |
6584 | } | |
6585 | ||
6586 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6587 | return 0; |
1857e1da DV |
6588 | |
6589 | /* Ivybridge 3 pipe is really complicated */ | |
6590 | switch (pipe) { | |
6591 | case PIPE_A: | |
6d293983 | 6592 | return 0; |
1857e1da | 6593 | case PIPE_B: |
6d293983 ACO |
6594 | if (pipe_config->fdi_lanes <= 2) |
6595 | return 0; | |
6596 | ||
6597 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6598 | other_crtc_state = | |
6599 | intel_atomic_get_crtc_state(state, other_crtc); | |
6600 | if (IS_ERR(other_crtc_state)) | |
6601 | return PTR_ERR(other_crtc_state); | |
6602 | ||
6603 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6604 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6605 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6606 | return -EINVAL; |
1857e1da | 6607 | } |
6d293983 | 6608 | return 0; |
1857e1da | 6609 | case PIPE_C: |
251cc67c VS |
6610 | if (pipe_config->fdi_lanes > 2) { |
6611 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6612 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6613 | return -EINVAL; |
251cc67c | 6614 | } |
6d293983 ACO |
6615 | |
6616 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6617 | other_crtc_state = | |
6618 | intel_atomic_get_crtc_state(state, other_crtc); | |
6619 | if (IS_ERR(other_crtc_state)) | |
6620 | return PTR_ERR(other_crtc_state); | |
6621 | ||
6622 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6623 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6624 | return -EINVAL; |
1857e1da | 6625 | } |
6d293983 | 6626 | return 0; |
1857e1da DV |
6627 | default: |
6628 | BUG(); | |
6629 | } | |
6630 | } | |
6631 | ||
e29c22c0 DV |
6632 | #define RETRY 1 |
6633 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6634 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6635 | { |
1857e1da | 6636 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6637 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6638 | int lane, link_bw, fdi_dotclock, ret; |
6639 | bool needs_recompute = false; | |
877d48d5 | 6640 | |
e29c22c0 | 6641 | retry: |
877d48d5 DV |
6642 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6643 | * each output octet as 10 bits. The actual frequency | |
6644 | * is stored as a divider into a 100MHz clock, and the | |
6645 | * mode pixel clock is stored in units of 1KHz. | |
6646 | * Hence the bw of each lane in terms of the mode signal | |
6647 | * is: | |
6648 | */ | |
6649 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6650 | ||
241bfc38 | 6651 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6652 | |
2bd89a07 | 6653 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6654 | pipe_config->pipe_bpp); |
6655 | ||
6656 | pipe_config->fdi_lanes = lane; | |
6657 | ||
2bd89a07 | 6658 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6659 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6660 | |
6d293983 ACO |
6661 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6662 | intel_crtc->pipe, pipe_config); | |
6663 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6664 | pipe_config->pipe_bpp -= 2*3; |
6665 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6666 | pipe_config->pipe_bpp); | |
6667 | needs_recompute = true; | |
6668 | pipe_config->bw_constrained = true; | |
6669 | ||
6670 | goto retry; | |
6671 | } | |
6672 | ||
6673 | if (needs_recompute) | |
6674 | return RETRY; | |
6675 | ||
6d293983 | 6676 | return ret; |
877d48d5 DV |
6677 | } |
6678 | ||
8cfb3407 VS |
6679 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6680 | struct intel_crtc_state *pipe_config) | |
6681 | { | |
6682 | if (pipe_config->pipe_bpp > 24) | |
6683 | return false; | |
6684 | ||
6685 | /* HSW can handle pixel rate up to cdclk? */ | |
6686 | if (IS_HASWELL(dev_priv->dev)) | |
6687 | return true; | |
6688 | ||
6689 | /* | |
b432e5cf VS |
6690 | * We compare against max which means we must take |
6691 | * the increased cdclk requirement into account when | |
6692 | * calculating the new cdclk. | |
6693 | * | |
6694 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6695 | */ |
6696 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6697 | dev_priv->max_cdclk_freq * 95 / 100; | |
6698 | } | |
6699 | ||
42db64ef | 6700 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6701 | struct intel_crtc_state *pipe_config) |
42db64ef | 6702 | { |
8cfb3407 VS |
6703 | struct drm_device *dev = crtc->base.dev; |
6704 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6705 | ||
d330a953 | 6706 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6707 | hsw_crtc_supports_ips(crtc) && |
6708 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6709 | } |
6710 | ||
39acb4aa VS |
6711 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6712 | { | |
6713 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6714 | ||
6715 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6716 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6717 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6718 | } | |
6719 | ||
a43f6e0f | 6720 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6721 | struct intel_crtc_state *pipe_config) |
79e53945 | 6722 | { |
a43f6e0f | 6723 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6724 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6725 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6726 | |
ad3a4479 | 6727 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6728 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6729 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6730 | |
6731 | /* | |
39acb4aa | 6732 | * Enable double wide mode when the dot clock |
cf532bb2 | 6733 | * is > 90% of the (display) core speed. |
cf532bb2 | 6734 | */ |
39acb4aa VS |
6735 | if (intel_crtc_supports_double_wide(crtc) && |
6736 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6737 | clock_limit *= 2; |
cf532bb2 | 6738 | pipe_config->double_wide = true; |
ad3a4479 VS |
6739 | } |
6740 | ||
39acb4aa VS |
6741 | if (adjusted_mode->crtc_clock > clock_limit) { |
6742 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6743 | adjusted_mode->crtc_clock, clock_limit, | |
6744 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6745 | return -EINVAL; |
39acb4aa | 6746 | } |
2c07245f | 6747 | } |
89749350 | 6748 | |
1d1d0e27 VS |
6749 | /* |
6750 | * Pipe horizontal size must be even in: | |
6751 | * - DVO ganged mode | |
6752 | * - LVDS dual channel mode | |
6753 | * - Double wide pipe | |
6754 | */ | |
a93e255f | 6755 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6756 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6757 | pipe_config->pipe_src_w &= ~1; | |
6758 | ||
8693a824 DL |
6759 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6760 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6761 | */ |
6762 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6763 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6764 | return -EINVAL; |
44f46b42 | 6765 | |
f5adf94e | 6766 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6767 | hsw_compute_ips_config(crtc, pipe_config); |
6768 | ||
877d48d5 | 6769 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6770 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6771 | |
cf5a15be | 6772 | return 0; |
79e53945 JB |
6773 | } |
6774 | ||
1652d19e VS |
6775 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6776 | { | |
6777 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6778 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6779 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6780 | uint32_t linkrate; | |
6781 | ||
414355a7 | 6782 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6783 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6784 | |
6785 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6786 | return 540000; | |
6787 | ||
6788 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6789 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6790 | |
71cd8423 DL |
6791 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6792 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6793 | /* vco 8640 */ |
6794 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6795 | case CDCLK_FREQ_450_432: | |
6796 | return 432000; | |
6797 | case CDCLK_FREQ_337_308: | |
6798 | return 308570; | |
6799 | case CDCLK_FREQ_675_617: | |
6800 | return 617140; | |
6801 | default: | |
6802 | WARN(1, "Unknown cd freq selection\n"); | |
6803 | } | |
6804 | } else { | |
6805 | /* vco 8100 */ | |
6806 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6807 | case CDCLK_FREQ_450_432: | |
6808 | return 450000; | |
6809 | case CDCLK_FREQ_337_308: | |
6810 | return 337500; | |
6811 | case CDCLK_FREQ_675_617: | |
6812 | return 675000; | |
6813 | default: | |
6814 | WARN(1, "Unknown cd freq selection\n"); | |
6815 | } | |
6816 | } | |
6817 | ||
6818 | /* error case, do as if DPLL0 isn't enabled */ | |
6819 | return 24000; | |
6820 | } | |
6821 | ||
acd3f3d3 BP |
6822 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6823 | { | |
6824 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6825 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6826 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6827 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6828 | int cdclk; | |
6829 | ||
6830 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6831 | return 19200; | |
6832 | ||
6833 | cdclk = 19200 * pll_ratio / 2; | |
6834 | ||
6835 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6836 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6837 | return cdclk; /* 576MHz or 624MHz */ | |
6838 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6839 | return cdclk * 2 / 3; /* 384MHz */ | |
6840 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6841 | return cdclk / 2; /* 288MHz */ | |
6842 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6843 | return cdclk / 4; /* 144MHz */ | |
6844 | } | |
6845 | ||
6846 | /* error case, do as if DE PLL isn't enabled */ | |
6847 | return 19200; | |
6848 | } | |
6849 | ||
1652d19e VS |
6850 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6851 | { | |
6852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6853 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6854 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6855 | ||
6856 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6857 | return 800000; | |
6858 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6859 | return 450000; | |
6860 | else if (freq == LCPLL_CLK_FREQ_450) | |
6861 | return 450000; | |
6862 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6863 | return 540000; | |
6864 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6865 | return 337500; | |
6866 | else | |
6867 | return 675000; | |
6868 | } | |
6869 | ||
6870 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6871 | { | |
6872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6873 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6874 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6875 | ||
6876 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6877 | return 800000; | |
6878 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6879 | return 450000; | |
6880 | else if (freq == LCPLL_CLK_FREQ_450) | |
6881 | return 450000; | |
6882 | else if (IS_HSW_ULT(dev)) | |
6883 | return 337500; | |
6884 | else | |
6885 | return 540000; | |
79e53945 JB |
6886 | } |
6887 | ||
25eb05fc JB |
6888 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6889 | { | |
bfa7df01 VS |
6890 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6891 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6892 | } |
6893 | ||
b37a6434 VS |
6894 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6895 | { | |
6896 | return 450000; | |
6897 | } | |
6898 | ||
e70236a8 JB |
6899 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6900 | { | |
6901 | return 400000; | |
6902 | } | |
79e53945 | 6903 | |
e70236a8 | 6904 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6905 | { |
e907f170 | 6906 | return 333333; |
e70236a8 | 6907 | } |
79e53945 | 6908 | |
e70236a8 JB |
6909 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6910 | { | |
6911 | return 200000; | |
6912 | } | |
79e53945 | 6913 | |
257a7ffc DV |
6914 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6915 | { | |
6916 | u16 gcfgc = 0; | |
6917 | ||
6918 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6919 | ||
6920 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6921 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6922 | return 266667; |
257a7ffc | 6923 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6924 | return 333333; |
257a7ffc | 6925 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6926 | return 444444; |
257a7ffc DV |
6927 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6928 | return 200000; | |
6929 | default: | |
6930 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6931 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6932 | return 133333; |
257a7ffc | 6933 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6934 | return 166667; |
257a7ffc DV |
6935 | } |
6936 | } | |
6937 | ||
e70236a8 JB |
6938 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6939 | { | |
6940 | u16 gcfgc = 0; | |
79e53945 | 6941 | |
e70236a8 JB |
6942 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6943 | ||
6944 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6945 | return 133333; |
e70236a8 JB |
6946 | else { |
6947 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6948 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6949 | return 333333; |
e70236a8 JB |
6950 | default: |
6951 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6952 | return 190000; | |
79e53945 | 6953 | } |
e70236a8 JB |
6954 | } |
6955 | } | |
6956 | ||
6957 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6958 | { | |
e907f170 | 6959 | return 266667; |
e70236a8 JB |
6960 | } |
6961 | ||
1b1d2716 | 6962 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6963 | { |
6964 | u16 hpllcc = 0; | |
1b1d2716 | 6965 | |
65cd2b3f VS |
6966 | /* |
6967 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6968 | * encoding is different :( | |
6969 | * FIXME is this the right way to detect 852GM/852GMV? | |
6970 | */ | |
6971 | if (dev->pdev->revision == 0x1) | |
6972 | return 133333; | |
6973 | ||
1b1d2716 VS |
6974 | pci_bus_read_config_word(dev->pdev->bus, |
6975 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6976 | ||
e70236a8 JB |
6977 | /* Assume that the hardware is in the high speed state. This |
6978 | * should be the default. | |
6979 | */ | |
6980 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6981 | case GC_CLOCK_133_200: | |
1b1d2716 | 6982 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6983 | case GC_CLOCK_100_200: |
6984 | return 200000; | |
6985 | case GC_CLOCK_166_250: | |
6986 | return 250000; | |
6987 | case GC_CLOCK_100_133: | |
e907f170 | 6988 | return 133333; |
1b1d2716 VS |
6989 | case GC_CLOCK_133_266: |
6990 | case GC_CLOCK_133_266_2: | |
6991 | case GC_CLOCK_166_266: | |
6992 | return 266667; | |
e70236a8 | 6993 | } |
79e53945 | 6994 | |
e70236a8 JB |
6995 | /* Shouldn't happen */ |
6996 | return 0; | |
6997 | } | |
79e53945 | 6998 | |
e70236a8 JB |
6999 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7000 | { | |
e907f170 | 7001 | return 133333; |
79e53945 JB |
7002 | } |
7003 | ||
34edce2f VS |
7004 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7005 | { | |
7006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7007 | static const unsigned int blb_vco[8] = { | |
7008 | [0] = 3200000, | |
7009 | [1] = 4000000, | |
7010 | [2] = 5333333, | |
7011 | [3] = 4800000, | |
7012 | [4] = 6400000, | |
7013 | }; | |
7014 | static const unsigned int pnv_vco[8] = { | |
7015 | [0] = 3200000, | |
7016 | [1] = 4000000, | |
7017 | [2] = 5333333, | |
7018 | [3] = 4800000, | |
7019 | [4] = 2666667, | |
7020 | }; | |
7021 | static const unsigned int cl_vco[8] = { | |
7022 | [0] = 3200000, | |
7023 | [1] = 4000000, | |
7024 | [2] = 5333333, | |
7025 | [3] = 6400000, | |
7026 | [4] = 3333333, | |
7027 | [5] = 3566667, | |
7028 | [6] = 4266667, | |
7029 | }; | |
7030 | static const unsigned int elk_vco[8] = { | |
7031 | [0] = 3200000, | |
7032 | [1] = 4000000, | |
7033 | [2] = 5333333, | |
7034 | [3] = 4800000, | |
7035 | }; | |
7036 | static const unsigned int ctg_vco[8] = { | |
7037 | [0] = 3200000, | |
7038 | [1] = 4000000, | |
7039 | [2] = 5333333, | |
7040 | [3] = 6400000, | |
7041 | [4] = 2666667, | |
7042 | [5] = 4266667, | |
7043 | }; | |
7044 | const unsigned int *vco_table; | |
7045 | unsigned int vco; | |
7046 | uint8_t tmp = 0; | |
7047 | ||
7048 | /* FIXME other chipsets? */ | |
7049 | if (IS_GM45(dev)) | |
7050 | vco_table = ctg_vco; | |
7051 | else if (IS_G4X(dev)) | |
7052 | vco_table = elk_vco; | |
7053 | else if (IS_CRESTLINE(dev)) | |
7054 | vco_table = cl_vco; | |
7055 | else if (IS_PINEVIEW(dev)) | |
7056 | vco_table = pnv_vco; | |
7057 | else if (IS_G33(dev)) | |
7058 | vco_table = blb_vco; | |
7059 | else | |
7060 | return 0; | |
7061 | ||
7062 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7063 | ||
7064 | vco = vco_table[tmp & 0x7]; | |
7065 | if (vco == 0) | |
7066 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7067 | else | |
7068 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7069 | ||
7070 | return vco; | |
7071 | } | |
7072 | ||
7073 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7074 | { | |
7075 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7076 | uint16_t tmp = 0; | |
7077 | ||
7078 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7079 | ||
7080 | cdclk_sel = (tmp >> 12) & 0x1; | |
7081 | ||
7082 | switch (vco) { | |
7083 | case 2666667: | |
7084 | case 4000000: | |
7085 | case 5333333: | |
7086 | return cdclk_sel ? 333333 : 222222; | |
7087 | case 3200000: | |
7088 | return cdclk_sel ? 320000 : 228571; | |
7089 | default: | |
7090 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7091 | return 222222; | |
7092 | } | |
7093 | } | |
7094 | ||
7095 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7096 | { | |
7097 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7098 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7099 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7100 | const uint8_t *div_table; | |
7101 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7102 | uint16_t tmp = 0; | |
7103 | ||
7104 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7105 | ||
7106 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7107 | ||
7108 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7109 | goto fail; | |
7110 | ||
7111 | switch (vco) { | |
7112 | case 3200000: | |
7113 | div_table = div_3200; | |
7114 | break; | |
7115 | case 4000000: | |
7116 | div_table = div_4000; | |
7117 | break; | |
7118 | case 5333333: | |
7119 | div_table = div_5333; | |
7120 | break; | |
7121 | default: | |
7122 | goto fail; | |
7123 | } | |
7124 | ||
7125 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7126 | ||
caf4e252 | 7127 | fail: |
34edce2f VS |
7128 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7129 | return 200000; | |
7130 | } | |
7131 | ||
7132 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7133 | { | |
7134 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7135 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7136 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7137 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7138 | const uint8_t *div_table; | |
7139 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7140 | uint16_t tmp = 0; | |
7141 | ||
7142 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7143 | ||
7144 | cdclk_sel = (tmp >> 4) & 0x7; | |
7145 | ||
7146 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7147 | goto fail; | |
7148 | ||
7149 | switch (vco) { | |
7150 | case 3200000: | |
7151 | div_table = div_3200; | |
7152 | break; | |
7153 | case 4000000: | |
7154 | div_table = div_4000; | |
7155 | break; | |
7156 | case 4800000: | |
7157 | div_table = div_4800; | |
7158 | break; | |
7159 | case 5333333: | |
7160 | div_table = div_5333; | |
7161 | break; | |
7162 | default: | |
7163 | goto fail; | |
7164 | } | |
7165 | ||
7166 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7167 | ||
caf4e252 | 7168 | fail: |
34edce2f VS |
7169 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7170 | return 190476; | |
7171 | } | |
7172 | ||
2c07245f | 7173 | static void |
a65851af | 7174 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7175 | { |
a65851af VS |
7176 | while (*num > DATA_LINK_M_N_MASK || |
7177 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7178 | *num >>= 1; |
7179 | *den >>= 1; | |
7180 | } | |
7181 | } | |
7182 | ||
a65851af VS |
7183 | static void compute_m_n(unsigned int m, unsigned int n, |
7184 | uint32_t *ret_m, uint32_t *ret_n) | |
7185 | { | |
7186 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7187 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7188 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7189 | } | |
7190 | ||
e69d0bc1 DV |
7191 | void |
7192 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7193 | int pixel_clock, int link_clock, | |
7194 | struct intel_link_m_n *m_n) | |
2c07245f | 7195 | { |
e69d0bc1 | 7196 | m_n->tu = 64; |
a65851af VS |
7197 | |
7198 | compute_m_n(bits_per_pixel * pixel_clock, | |
7199 | link_clock * nlanes * 8, | |
7200 | &m_n->gmch_m, &m_n->gmch_n); | |
7201 | ||
7202 | compute_m_n(pixel_clock, link_clock, | |
7203 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7204 | } |
7205 | ||
a7615030 CW |
7206 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7207 | { | |
d330a953 JN |
7208 | if (i915.panel_use_ssc >= 0) |
7209 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7210 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7211 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7212 | } |
7213 | ||
a93e255f ACO |
7214 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7215 | int num_connectors) | |
c65d77d8 | 7216 | { |
a93e255f | 7217 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7218 | struct drm_i915_private *dev_priv = dev->dev_private; |
7219 | int refclk; | |
7220 | ||
a93e255f ACO |
7221 | WARN_ON(!crtc_state->base.state); |
7222 | ||
666a4537 | 7223 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7224 | refclk = 100000; |
a93e255f | 7225 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7226 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7227 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7228 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7229 | } else if (!IS_GEN2(dev)) { |
7230 | refclk = 96000; | |
7231 | } else { | |
7232 | refclk = 48000; | |
7233 | } | |
7234 | ||
7235 | return refclk; | |
7236 | } | |
7237 | ||
7429e9d4 | 7238 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7239 | { |
7df00d7a | 7240 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7241 | } |
f47709a9 | 7242 | |
7429e9d4 DV |
7243 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7244 | { | |
7245 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7246 | } |
7247 | ||
f47709a9 | 7248 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7249 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7250 | intel_clock_t *reduced_clock) |
7251 | { | |
f47709a9 | 7252 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7253 | u32 fp, fp2 = 0; |
7254 | ||
7255 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7256 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7257 | if (reduced_clock) |
7429e9d4 | 7258 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7259 | } else { |
190f68c5 | 7260 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7261 | if (reduced_clock) |
7429e9d4 | 7262 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7263 | } |
7264 | ||
190f68c5 | 7265 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7266 | |
f47709a9 | 7267 | crtc->lowfreq_avail = false; |
a93e255f | 7268 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7269 | reduced_clock) { |
190f68c5 | 7270 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7271 | crtc->lowfreq_avail = true; |
a7516a05 | 7272 | } else { |
190f68c5 | 7273 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7274 | } |
7275 | } | |
7276 | ||
5e69f97f CML |
7277 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7278 | pipe) | |
89b667f8 JB |
7279 | { |
7280 | u32 reg_val; | |
7281 | ||
7282 | /* | |
7283 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7284 | * and set it to a reasonable value instead. | |
7285 | */ | |
ab3c759a | 7286 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7287 | reg_val &= 0xffffff00; |
7288 | reg_val |= 0x00000030; | |
ab3c759a | 7289 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7290 | |
ab3c759a | 7291 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7292 | reg_val &= 0x8cffffff; |
7293 | reg_val = 0x8c000000; | |
ab3c759a | 7294 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7295 | |
ab3c759a | 7296 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7297 | reg_val &= 0xffffff00; |
ab3c759a | 7298 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7299 | |
ab3c759a | 7300 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7301 | reg_val &= 0x00ffffff; |
7302 | reg_val |= 0xb0000000; | |
ab3c759a | 7303 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7304 | } |
7305 | ||
b551842d DV |
7306 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7307 | struct intel_link_m_n *m_n) | |
7308 | { | |
7309 | struct drm_device *dev = crtc->base.dev; | |
7310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7311 | int pipe = crtc->pipe; | |
7312 | ||
e3b95f1e DV |
7313 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7314 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7315 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7316 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7317 | } |
7318 | ||
7319 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7320 | struct intel_link_m_n *m_n, |
7321 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7322 | { |
7323 | struct drm_device *dev = crtc->base.dev; | |
7324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7325 | int pipe = crtc->pipe; | |
6e3c9717 | 7326 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7327 | |
7328 | if (INTEL_INFO(dev)->gen >= 5) { | |
7329 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7330 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7331 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7332 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7333 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7334 | * for gen < 8) and if DRRS is supported (to make sure the | |
7335 | * registers are not unnecessarily accessed). | |
7336 | */ | |
44395bfe | 7337 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7338 | crtc->config->has_drrs) { |
f769cd24 VK |
7339 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7340 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7341 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7342 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7343 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7344 | } | |
b551842d | 7345 | } else { |
e3b95f1e DV |
7346 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7347 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7348 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7349 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7350 | } |
7351 | } | |
7352 | ||
fe3cd48d | 7353 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7354 | { |
fe3cd48d R |
7355 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7356 | ||
7357 | if (m_n == M1_N1) { | |
7358 | dp_m_n = &crtc->config->dp_m_n; | |
7359 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7360 | } else if (m_n == M2_N2) { | |
7361 | ||
7362 | /* | |
7363 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7364 | * needs to be programmed into M1_N1. | |
7365 | */ | |
7366 | dp_m_n = &crtc->config->dp_m2_n2; | |
7367 | } else { | |
7368 | DRM_ERROR("Unsupported divider value\n"); | |
7369 | return; | |
7370 | } | |
7371 | ||
6e3c9717 ACO |
7372 | if (crtc->config->has_pch_encoder) |
7373 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7374 | else |
fe3cd48d | 7375 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7376 | } |
7377 | ||
251ac862 DV |
7378 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7379 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7380 | { |
7381 | u32 dpll, dpll_md; | |
7382 | ||
7383 | /* | |
7384 | * Enable DPIO clock input. We should never disable the reference | |
7385 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7386 | * on it. | |
7387 | */ | |
60bfe44f VS |
7388 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7389 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7390 | /* We should never disable this, set it here for state tracking */ |
7391 | if (crtc->pipe == PIPE_B) | |
7392 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7393 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7394 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7395 | |
d288f65f | 7396 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7397 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7398 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7399 | } |
7400 | ||
d288f65f | 7401 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7402 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7403 | { |
f47709a9 | 7404 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7405 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7406 | int pipe = crtc->pipe; |
bdd4b6a6 | 7407 | u32 mdiv; |
a0c4da24 | 7408 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7409 | u32 coreclk, reg_val; |
a0c4da24 | 7410 | |
a580516d | 7411 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7412 | |
d288f65f VS |
7413 | bestn = pipe_config->dpll.n; |
7414 | bestm1 = pipe_config->dpll.m1; | |
7415 | bestm2 = pipe_config->dpll.m2; | |
7416 | bestp1 = pipe_config->dpll.p1; | |
7417 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7418 | |
89b667f8 JB |
7419 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7420 | ||
7421 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7422 | if (pipe == PIPE_B) |
5e69f97f | 7423 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7424 | |
7425 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7426 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7427 | |
7428 | /* Disable target IRef on PLL */ | |
ab3c759a | 7429 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7430 | reg_val &= 0x00ffffff; |
ab3c759a | 7431 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7432 | |
7433 | /* Disable fast lock */ | |
ab3c759a | 7434 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7435 | |
7436 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7437 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7438 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7439 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7440 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7441 | |
7442 | /* | |
7443 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7444 | * but we don't support that). | |
7445 | * Note: don't use the DAC post divider as it seems unstable. | |
7446 | */ | |
7447 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7448 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7449 | |
a0c4da24 | 7450 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7451 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7452 | |
89b667f8 | 7453 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7454 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7455 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7456 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7457 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7458 | 0x009f0003); |
89b667f8 | 7459 | else |
ab3c759a | 7460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7461 | 0x00d0000f); |
7462 | ||
681a8504 | 7463 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7464 | /* Use SSC source */ |
bdd4b6a6 | 7465 | if (pipe == PIPE_A) |
ab3c759a | 7466 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7467 | 0x0df40000); |
7468 | else | |
ab3c759a | 7469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7470 | 0x0df70000); |
7471 | } else { /* HDMI or VGA */ | |
7472 | /* Use bend source */ | |
bdd4b6a6 | 7473 | if (pipe == PIPE_A) |
ab3c759a | 7474 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7475 | 0x0df70000); |
7476 | else | |
ab3c759a | 7477 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7478 | 0x0df40000); |
7479 | } | |
a0c4da24 | 7480 | |
ab3c759a | 7481 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7482 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7483 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7484 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7485 | coreclk |= 0x01000000; |
ab3c759a | 7486 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7487 | |
ab3c759a | 7488 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7489 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7490 | } |
7491 | ||
251ac862 DV |
7492 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7493 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7494 | { |
60bfe44f VS |
7495 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7496 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7497 | DPLL_VCO_ENABLE; |
7498 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7499 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7500 | |
d288f65f VS |
7501 | pipe_config->dpll_hw_state.dpll_md = |
7502 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7503 | } |
7504 | ||
d288f65f | 7505 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7506 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7507 | { |
7508 | struct drm_device *dev = crtc->base.dev; | |
7509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7510 | int pipe = crtc->pipe; | |
f0f59a00 | 7511 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7512 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7513 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7514 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7515 | u32 dpio_val; |
9cbe40c1 | 7516 | int vco; |
9d556c99 | 7517 | |
d288f65f VS |
7518 | bestn = pipe_config->dpll.n; |
7519 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7520 | bestm1 = pipe_config->dpll.m1; | |
7521 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7522 | bestp1 = pipe_config->dpll.p1; | |
7523 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7524 | vco = pipe_config->dpll.vco; |
a945ce7e | 7525 | dpio_val = 0; |
9cbe40c1 | 7526 | loopfilter = 0; |
9d556c99 CML |
7527 | |
7528 | /* | |
7529 | * Enable Refclk and SSC | |
7530 | */ | |
a11b0703 | 7531 | I915_WRITE(dpll_reg, |
d288f65f | 7532 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7533 | |
a580516d | 7534 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7535 | |
9d556c99 CML |
7536 | /* p1 and p2 divider */ |
7537 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7538 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7539 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7540 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7541 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7542 | ||
7543 | /* Feedback post-divider - m2 */ | |
7544 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7545 | ||
7546 | /* Feedback refclk divider - n and m1 */ | |
7547 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7548 | DPIO_CHV_M1_DIV_BY_2 | | |
7549 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7550 | ||
7551 | /* M2 fraction division */ | |
25a25dfc | 7552 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7553 | |
7554 | /* M2 fraction division enable */ | |
a945ce7e VP |
7555 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7556 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7557 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7558 | if (bestm2_frac) | |
7559 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7560 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7561 | |
de3a0fde VP |
7562 | /* Program digital lock detect threshold */ |
7563 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7564 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7565 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7566 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7567 | if (!bestm2_frac) | |
7568 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7569 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7570 | ||
9d556c99 | 7571 | /* Loop filter */ |
9cbe40c1 VP |
7572 | if (vco == 5400000) { |
7573 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7574 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7575 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7576 | tribuf_calcntr = 0x9; | |
7577 | } else if (vco <= 6200000) { | |
7578 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7579 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7580 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7581 | tribuf_calcntr = 0x9; | |
7582 | } else if (vco <= 6480000) { | |
7583 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7584 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7585 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7586 | tribuf_calcntr = 0x8; | |
7587 | } else { | |
7588 | /* Not supported. Apply the same limits as in the max case */ | |
7589 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7590 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7591 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7592 | tribuf_calcntr = 0; | |
7593 | } | |
9d556c99 CML |
7594 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7595 | ||
968040b2 | 7596 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7597 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7598 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7599 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7600 | ||
9d556c99 CML |
7601 | /* AFC Recal */ |
7602 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7603 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7604 | DPIO_AFC_RECAL); | |
7605 | ||
a580516d | 7606 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7607 | } |
7608 | ||
d288f65f VS |
7609 | /** |
7610 | * vlv_force_pll_on - forcibly enable just the PLL | |
7611 | * @dev_priv: i915 private structure | |
7612 | * @pipe: pipe PLL to enable | |
7613 | * @dpll: PLL configuration | |
7614 | * | |
7615 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7616 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7617 | * be enabled. | |
7618 | */ | |
7619 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7620 | const struct dpll *dpll) | |
7621 | { | |
7622 | struct intel_crtc *crtc = | |
7623 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7624 | struct intel_crtc_state pipe_config = { |
a93e255f | 7625 | .base.crtc = &crtc->base, |
d288f65f VS |
7626 | .pixel_multiplier = 1, |
7627 | .dpll = *dpll, | |
7628 | }; | |
7629 | ||
7630 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7631 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7632 | chv_prepare_pll(crtc, &pipe_config); |
7633 | chv_enable_pll(crtc, &pipe_config); | |
7634 | } else { | |
251ac862 | 7635 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7636 | vlv_prepare_pll(crtc, &pipe_config); |
7637 | vlv_enable_pll(crtc, &pipe_config); | |
7638 | } | |
7639 | } | |
7640 | ||
7641 | /** | |
7642 | * vlv_force_pll_off - forcibly disable just the PLL | |
7643 | * @dev_priv: i915 private structure | |
7644 | * @pipe: pipe PLL to disable | |
7645 | * | |
7646 | * Disable the PLL for @pipe. To be used in cases where we need | |
7647 | * the PLL enabled even when @pipe is not going to be enabled. | |
7648 | */ | |
7649 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7650 | { | |
7651 | if (IS_CHERRYVIEW(dev)) | |
7652 | chv_disable_pll(to_i915(dev), pipe); | |
7653 | else | |
7654 | vlv_disable_pll(to_i915(dev), pipe); | |
7655 | } | |
7656 | ||
251ac862 DV |
7657 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7658 | struct intel_crtc_state *crtc_state, | |
7659 | intel_clock_t *reduced_clock, | |
7660 | int num_connectors) | |
eb1cbe48 | 7661 | { |
f47709a9 | 7662 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7663 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7664 | u32 dpll; |
7665 | bool is_sdvo; | |
190f68c5 | 7666 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7667 | |
190f68c5 | 7668 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7669 | |
a93e255f ACO |
7670 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7671 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7672 | |
7673 | dpll = DPLL_VGA_MODE_DIS; | |
7674 | ||
a93e255f | 7675 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7676 | dpll |= DPLLB_MODE_LVDS; |
7677 | else | |
7678 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7679 | |
ef1b460d | 7680 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7681 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7682 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7683 | } |
198a037f DV |
7684 | |
7685 | if (is_sdvo) | |
4a33e48d | 7686 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7687 | |
190f68c5 | 7688 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7689 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7690 | |
7691 | /* compute bitmask from p1 value */ | |
7692 | if (IS_PINEVIEW(dev)) | |
7693 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7694 | else { | |
7695 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7696 | if (IS_G4X(dev) && reduced_clock) | |
7697 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7698 | } | |
7699 | switch (clock->p2) { | |
7700 | case 5: | |
7701 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7702 | break; | |
7703 | case 7: | |
7704 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7705 | break; | |
7706 | case 10: | |
7707 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7708 | break; | |
7709 | case 14: | |
7710 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7711 | break; | |
7712 | } | |
7713 | if (INTEL_INFO(dev)->gen >= 4) | |
7714 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7715 | ||
190f68c5 | 7716 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7717 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7718 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7719 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7720 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7721 | else | |
7722 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7723 | ||
7724 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7725 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7726 | |
eb1cbe48 | 7727 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7728 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7729 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7730 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7731 | } |
7732 | } | |
7733 | ||
251ac862 DV |
7734 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7735 | struct intel_crtc_state *crtc_state, | |
7736 | intel_clock_t *reduced_clock, | |
7737 | int num_connectors) | |
eb1cbe48 | 7738 | { |
f47709a9 | 7739 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7740 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7741 | u32 dpll; |
190f68c5 | 7742 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7743 | |
190f68c5 | 7744 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7745 | |
eb1cbe48 DV |
7746 | dpll = DPLL_VGA_MODE_DIS; |
7747 | ||
a93e255f | 7748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7749 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7750 | } else { | |
7751 | if (clock->p1 == 2) | |
7752 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7753 | else | |
7754 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7755 | if (clock->p2 == 4) | |
7756 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7757 | } | |
7758 | ||
a93e255f | 7759 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7760 | dpll |= DPLL_DVO_2X_MODE; |
7761 | ||
a93e255f | 7762 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7763 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7764 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7765 | else | |
7766 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7767 | ||
7768 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7769 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7770 | } |
7771 | ||
8a654f3b | 7772 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7773 | { |
7774 | struct drm_device *dev = intel_crtc->base.dev; | |
7775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7776 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7777 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7778 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7779 | uint32_t crtc_vtotal, crtc_vblank_end; |
7780 | int vsyncshift = 0; | |
4d8a62ea DV |
7781 | |
7782 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7783 | * the hw state checker will get angry at the mismatch. */ | |
7784 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7785 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7786 | |
609aeaca | 7787 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7788 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7789 | crtc_vtotal -= 1; |
7790 | crtc_vblank_end -= 1; | |
609aeaca | 7791 | |
409ee761 | 7792 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7793 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7794 | else | |
7795 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7796 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7797 | if (vsyncshift < 0) |
7798 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7799 | } |
7800 | ||
7801 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7802 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7803 | |
fe2b8f9d | 7804 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7805 | (adjusted_mode->crtc_hdisplay - 1) | |
7806 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7807 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7808 | (adjusted_mode->crtc_hblank_start - 1) | |
7809 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7810 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7811 | (adjusted_mode->crtc_hsync_start - 1) | |
7812 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7813 | ||
fe2b8f9d | 7814 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7815 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7816 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7817 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7818 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7819 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7820 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7821 | (adjusted_mode->crtc_vsync_start - 1) | |
7822 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7823 | ||
b5e508d4 PZ |
7824 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7825 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7826 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7827 | * bits. */ | |
7828 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7829 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7830 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7831 | ||
b0e77b9c PZ |
7832 | /* pipesrc controls the size that is scaled from, which should |
7833 | * always be the user's requested size. | |
7834 | */ | |
7835 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7836 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7837 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7838 | } |
7839 | ||
1bd1bd80 | 7840 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7841 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7842 | { |
7843 | struct drm_device *dev = crtc->base.dev; | |
7844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7845 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7846 | uint32_t tmp; | |
7847 | ||
7848 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7849 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7850 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7851 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7852 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7853 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7854 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7855 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7856 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7857 | |
7858 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7859 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7860 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7861 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7862 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7863 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7864 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7865 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7866 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7867 | |
7868 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7869 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7870 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7871 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7872 | } |
7873 | ||
7874 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7875 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7876 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7877 | ||
2d112de7 ACO |
7878 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7879 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7880 | } |
7881 | ||
f6a83288 | 7882 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7883 | struct intel_crtc_state *pipe_config) |
babea61d | 7884 | { |
2d112de7 ACO |
7885 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7886 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7887 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7888 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7889 | |
2d112de7 ACO |
7890 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7891 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7892 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7893 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7894 | |
2d112de7 | 7895 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7896 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7897 | |
2d112de7 ACO |
7898 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7899 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7900 | |
7901 | mode->hsync = drm_mode_hsync(mode); | |
7902 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7903 | drm_mode_set_name(mode); | |
babea61d JB |
7904 | } |
7905 | ||
84b046f3 DV |
7906 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7907 | { | |
7908 | struct drm_device *dev = intel_crtc->base.dev; | |
7909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7910 | uint32_t pipeconf; | |
7911 | ||
9f11a9e4 | 7912 | pipeconf = 0; |
84b046f3 | 7913 | |
b6b5d049 VS |
7914 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7915 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7916 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7917 | |
6e3c9717 | 7918 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7919 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7920 | |
ff9ce46e | 7921 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7922 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7923 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7924 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7925 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7926 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7927 | |
6e3c9717 | 7928 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7929 | case 18: |
7930 | pipeconf |= PIPECONF_6BPC; | |
7931 | break; | |
7932 | case 24: | |
7933 | pipeconf |= PIPECONF_8BPC; | |
7934 | break; | |
7935 | case 30: | |
7936 | pipeconf |= PIPECONF_10BPC; | |
7937 | break; | |
7938 | default: | |
7939 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7940 | BUG(); | |
84b046f3 DV |
7941 | } |
7942 | } | |
7943 | ||
7944 | if (HAS_PIPE_CXSR(dev)) { | |
7945 | if (intel_crtc->lowfreq_avail) { | |
7946 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7947 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7948 | } else { | |
7949 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7950 | } |
7951 | } | |
7952 | ||
6e3c9717 | 7953 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7954 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7955 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7956 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7957 | else | |
7958 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7959 | } else | |
84b046f3 DV |
7960 | pipeconf |= PIPECONF_PROGRESSIVE; |
7961 | ||
666a4537 WB |
7962 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7963 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7964 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7965 | |
84b046f3 DV |
7966 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7967 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7968 | } | |
7969 | ||
190f68c5 ACO |
7970 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7971 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7972 | { |
c7653199 | 7973 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7974 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7975 | int refclk, num_connectors = 0; |
c329a4ec DV |
7976 | intel_clock_t clock; |
7977 | bool ok; | |
d4906093 | 7978 | const intel_limit_t *limit; |
55bb9992 | 7979 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7980 | struct drm_connector *connector; |
55bb9992 ACO |
7981 | struct drm_connector_state *connector_state; |
7982 | int i; | |
79e53945 | 7983 | |
dd3cd74a ACO |
7984 | memset(&crtc_state->dpll_hw_state, 0, |
7985 | sizeof(crtc_state->dpll_hw_state)); | |
7986 | ||
a65347ba JN |
7987 | if (crtc_state->has_dsi_encoder) |
7988 | return 0; | |
43565a06 | 7989 | |
a65347ba JN |
7990 | for_each_connector_in_state(state, connector, connector_state, i) { |
7991 | if (connector_state->crtc == &crtc->base) | |
7992 | num_connectors++; | |
79e53945 JB |
7993 | } |
7994 | ||
190f68c5 | 7995 | if (!crtc_state->clock_set) { |
a93e255f | 7996 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7997 | |
e9fd1c02 JN |
7998 | /* |
7999 | * Returns a set of divisors for the desired target clock with | |
8000 | * the given refclk, or FALSE. The returned values represent | |
8001 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
8002 | * 2) / p1 / p2. | |
8003 | */ | |
a93e255f ACO |
8004 | limit = intel_limit(crtc_state, refclk); |
8005 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8006 | crtc_state->port_clock, |
e9fd1c02 | 8007 | refclk, NULL, &clock); |
f2335330 | 8008 | if (!ok) { |
e9fd1c02 JN |
8009 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8010 | return -EINVAL; | |
8011 | } | |
79e53945 | 8012 | |
f2335330 | 8013 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8014 | crtc_state->dpll.n = clock.n; |
8015 | crtc_state->dpll.m1 = clock.m1; | |
8016 | crtc_state->dpll.m2 = clock.m2; | |
8017 | crtc_state->dpll.p1 = clock.p1; | |
8018 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8019 | } |
7026d4ac | 8020 | |
e9fd1c02 | 8021 | if (IS_GEN2(dev)) { |
c329a4ec | 8022 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8023 | num_connectors); |
9d556c99 | 8024 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8025 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8026 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8027 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8028 | } else { |
c329a4ec | 8029 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8030 | num_connectors); |
e9fd1c02 | 8031 | } |
79e53945 | 8032 | |
c8f7a0db | 8033 | return 0; |
f564048e EA |
8034 | } |
8035 | ||
2fa2fe9a | 8036 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8037 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8038 | { |
8039 | struct drm_device *dev = crtc->base.dev; | |
8040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8041 | uint32_t tmp; | |
8042 | ||
dc9e7dec VS |
8043 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8044 | return; | |
8045 | ||
2fa2fe9a | 8046 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8047 | if (!(tmp & PFIT_ENABLE)) |
8048 | return; | |
2fa2fe9a | 8049 | |
06922821 | 8050 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8051 | if (INTEL_INFO(dev)->gen < 4) { |
8052 | if (crtc->pipe != PIPE_B) | |
8053 | return; | |
2fa2fe9a DV |
8054 | } else { |
8055 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8056 | return; | |
8057 | } | |
8058 | ||
06922821 | 8059 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8060 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8061 | if (INTEL_INFO(dev)->gen < 5) | |
8062 | pipe_config->gmch_pfit.lvds_border_bits = | |
8063 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8064 | } | |
8065 | ||
acbec814 | 8066 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8067 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8068 | { |
8069 | struct drm_device *dev = crtc->base.dev; | |
8070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8071 | int pipe = pipe_config->cpu_transcoder; | |
8072 | intel_clock_t clock; | |
8073 | u32 mdiv; | |
662c6ecb | 8074 | int refclk = 100000; |
acbec814 | 8075 | |
f573de5a SK |
8076 | /* In case of MIPI DPLL will not even be used */ |
8077 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8078 | return; | |
8079 | ||
a580516d | 8080 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8081 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8082 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8083 | |
8084 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8085 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8086 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8087 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8088 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8089 | ||
dccbea3b | 8090 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8091 | } |
8092 | ||
5724dbd1 DL |
8093 | static void |
8094 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8095 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8096 | { |
8097 | struct drm_device *dev = crtc->base.dev; | |
8098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8099 | u32 val, base, offset; | |
8100 | int pipe = crtc->pipe, plane = crtc->plane; | |
8101 | int fourcc, pixel_format; | |
6761dd31 | 8102 | unsigned int aligned_height; |
b113d5ee | 8103 | struct drm_framebuffer *fb; |
1b842c89 | 8104 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8105 | |
42a7b088 DL |
8106 | val = I915_READ(DSPCNTR(plane)); |
8107 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8108 | return; | |
8109 | ||
d9806c9f | 8110 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8111 | if (!intel_fb) { |
1ad292b5 JB |
8112 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8113 | return; | |
8114 | } | |
8115 | ||
1b842c89 DL |
8116 | fb = &intel_fb->base; |
8117 | ||
18c5247e DV |
8118 | if (INTEL_INFO(dev)->gen >= 4) { |
8119 | if (val & DISPPLANE_TILED) { | |
49af449b | 8120 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8121 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8122 | } | |
8123 | } | |
1ad292b5 JB |
8124 | |
8125 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8126 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8127 | fb->pixel_format = fourcc; |
8128 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8129 | |
8130 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8131 | if (plane_config->tiling) |
1ad292b5 JB |
8132 | offset = I915_READ(DSPTILEOFF(plane)); |
8133 | else | |
8134 | offset = I915_READ(DSPLINOFF(plane)); | |
8135 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8136 | } else { | |
8137 | base = I915_READ(DSPADDR(plane)); | |
8138 | } | |
8139 | plane_config->base = base; | |
8140 | ||
8141 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8142 | fb->width = ((val >> 16) & 0xfff) + 1; |
8143 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8144 | |
8145 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8146 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8147 | |
b113d5ee | 8148 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8149 | fb->pixel_format, |
8150 | fb->modifier[0]); | |
1ad292b5 | 8151 | |
f37b5c2b | 8152 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8153 | |
2844a921 DL |
8154 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8155 | pipe_name(pipe), plane, fb->width, fb->height, | |
8156 | fb->bits_per_pixel, base, fb->pitches[0], | |
8157 | plane_config->size); | |
1ad292b5 | 8158 | |
2d14030b | 8159 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8160 | } |
8161 | ||
70b23a98 | 8162 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8163 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8164 | { |
8165 | struct drm_device *dev = crtc->base.dev; | |
8166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8167 | int pipe = pipe_config->cpu_transcoder; | |
8168 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8169 | intel_clock_t clock; | |
0d7b6b11 | 8170 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8171 | int refclk = 100000; |
8172 | ||
a580516d | 8173 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8174 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8175 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8176 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8177 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8178 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8179 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8180 | |
8181 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8182 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8183 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8184 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8185 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8186 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8187 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8188 | ||
dccbea3b | 8189 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8190 | } |
8191 | ||
0e8ffe1b | 8192 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8193 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8194 | { |
8195 | struct drm_device *dev = crtc->base.dev; | |
8196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8197 | uint32_t tmp; | |
8198 | ||
f458ebbc DV |
8199 | if (!intel_display_power_is_enabled(dev_priv, |
8200 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8201 | return false; |
8202 | ||
e143a21c | 8203 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8204 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8205 | |
0e8ffe1b DV |
8206 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8207 | if (!(tmp & PIPECONF_ENABLE)) | |
8208 | return false; | |
8209 | ||
666a4537 | 8210 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8211 | switch (tmp & PIPECONF_BPC_MASK) { |
8212 | case PIPECONF_6BPC: | |
8213 | pipe_config->pipe_bpp = 18; | |
8214 | break; | |
8215 | case PIPECONF_8BPC: | |
8216 | pipe_config->pipe_bpp = 24; | |
8217 | break; | |
8218 | case PIPECONF_10BPC: | |
8219 | pipe_config->pipe_bpp = 30; | |
8220 | break; | |
8221 | default: | |
8222 | break; | |
8223 | } | |
8224 | } | |
8225 | ||
666a4537 WB |
8226 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8227 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8228 | pipe_config->limited_color_range = true; |
8229 | ||
282740f7 VS |
8230 | if (INTEL_INFO(dev)->gen < 4) |
8231 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8232 | ||
1bd1bd80 DV |
8233 | intel_get_pipe_timings(crtc, pipe_config); |
8234 | ||
2fa2fe9a DV |
8235 | i9xx_get_pfit_config(crtc, pipe_config); |
8236 | ||
6c49f241 DV |
8237 | if (INTEL_INFO(dev)->gen >= 4) { |
8238 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8239 | pipe_config->pixel_multiplier = | |
8240 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8241 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8242 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8243 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8244 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8245 | pipe_config->pixel_multiplier = | |
8246 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8247 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8248 | } else { | |
8249 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8250 | * port and will be fixed up in the encoder->get_config | |
8251 | * function. */ | |
8252 | pipe_config->pixel_multiplier = 1; | |
8253 | } | |
8bcc2795 | 8254 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8255 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8256 | /* |
8257 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8258 | * on 830. Filter it out here so that we don't | |
8259 | * report errors due to that. | |
8260 | */ | |
8261 | if (IS_I830(dev)) | |
8262 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8263 | ||
8bcc2795 DV |
8264 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8265 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8266 | } else { |
8267 | /* Mask out read-only status bits. */ | |
8268 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8269 | DPLL_PORTC_READY_MASK | | |
8270 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8271 | } |
6c49f241 | 8272 | |
70b23a98 VS |
8273 | if (IS_CHERRYVIEW(dev)) |
8274 | chv_crtc_clock_get(crtc, pipe_config); | |
8275 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8276 | vlv_crtc_clock_get(crtc, pipe_config); |
8277 | else | |
8278 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8279 | |
0f64614d VS |
8280 | /* |
8281 | * Normally the dotclock is filled in by the encoder .get_config() | |
8282 | * but in case the pipe is enabled w/o any ports we need a sane | |
8283 | * default. | |
8284 | */ | |
8285 | pipe_config->base.adjusted_mode.crtc_clock = | |
8286 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8287 | ||
0e8ffe1b DV |
8288 | return true; |
8289 | } | |
8290 | ||
dde86e2d | 8291 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8292 | { |
8293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8294 | struct intel_encoder *encoder; |
74cfd7ac | 8295 | u32 val, final; |
13d83a67 | 8296 | bool has_lvds = false; |
199e5d79 | 8297 | bool has_cpu_edp = false; |
199e5d79 | 8298 | bool has_panel = false; |
99eb6a01 KP |
8299 | bool has_ck505 = false; |
8300 | bool can_ssc = false; | |
13d83a67 JB |
8301 | |
8302 | /* We need to take the global config into account */ | |
b2784e15 | 8303 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8304 | switch (encoder->type) { |
8305 | case INTEL_OUTPUT_LVDS: | |
8306 | has_panel = true; | |
8307 | has_lvds = true; | |
8308 | break; | |
8309 | case INTEL_OUTPUT_EDP: | |
8310 | has_panel = true; | |
2de6905f | 8311 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8312 | has_cpu_edp = true; |
8313 | break; | |
6847d71b PZ |
8314 | default: |
8315 | break; | |
13d83a67 JB |
8316 | } |
8317 | } | |
8318 | ||
99eb6a01 | 8319 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8320 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8321 | can_ssc = has_ck505; |
8322 | } else { | |
8323 | has_ck505 = false; | |
8324 | can_ssc = true; | |
8325 | } | |
8326 | ||
2de6905f ID |
8327 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8328 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8329 | |
8330 | /* Ironlake: try to setup display ref clock before DPLL | |
8331 | * enabling. This is only under driver's control after | |
8332 | * PCH B stepping, previous chipset stepping should be | |
8333 | * ignoring this setting. | |
8334 | */ | |
74cfd7ac CW |
8335 | val = I915_READ(PCH_DREF_CONTROL); |
8336 | ||
8337 | /* As we must carefully and slowly disable/enable each source in turn, | |
8338 | * compute the final state we want first and check if we need to | |
8339 | * make any changes at all. | |
8340 | */ | |
8341 | final = val; | |
8342 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8343 | if (has_ck505) | |
8344 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8345 | else | |
8346 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8347 | ||
8348 | final &= ~DREF_SSC_SOURCE_MASK; | |
8349 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8350 | final &= ~DREF_SSC1_ENABLE; | |
8351 | ||
8352 | if (has_panel) { | |
8353 | final |= DREF_SSC_SOURCE_ENABLE; | |
8354 | ||
8355 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8356 | final |= DREF_SSC1_ENABLE; | |
8357 | ||
8358 | if (has_cpu_edp) { | |
8359 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8360 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8361 | else | |
8362 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8363 | } else | |
8364 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8365 | } else { | |
8366 | final |= DREF_SSC_SOURCE_DISABLE; | |
8367 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8368 | } | |
8369 | ||
8370 | if (final == val) | |
8371 | return; | |
8372 | ||
13d83a67 | 8373 | /* Always enable nonspread source */ |
74cfd7ac | 8374 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8375 | |
99eb6a01 | 8376 | if (has_ck505) |
74cfd7ac | 8377 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8378 | else |
74cfd7ac | 8379 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8380 | |
199e5d79 | 8381 | if (has_panel) { |
74cfd7ac CW |
8382 | val &= ~DREF_SSC_SOURCE_MASK; |
8383 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8384 | |
199e5d79 | 8385 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8386 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8387 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8388 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8389 | } else |
74cfd7ac | 8390 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8391 | |
8392 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8393 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8394 | POSTING_READ(PCH_DREF_CONTROL); |
8395 | udelay(200); | |
8396 | ||
74cfd7ac | 8397 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8398 | |
8399 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8400 | if (has_cpu_edp) { |
99eb6a01 | 8401 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8402 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8403 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8404 | } else |
74cfd7ac | 8405 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8406 | } else |
74cfd7ac | 8407 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8408 | |
74cfd7ac | 8409 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8410 | POSTING_READ(PCH_DREF_CONTROL); |
8411 | udelay(200); | |
8412 | } else { | |
8413 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8414 | ||
74cfd7ac | 8415 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8416 | |
8417 | /* Turn off CPU output */ | |
74cfd7ac | 8418 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8419 | |
74cfd7ac | 8420 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8421 | POSTING_READ(PCH_DREF_CONTROL); |
8422 | udelay(200); | |
8423 | ||
8424 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8425 | val &= ~DREF_SSC_SOURCE_MASK; |
8426 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8427 | |
8428 | /* Turn off SSC1 */ | |
74cfd7ac | 8429 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8430 | |
74cfd7ac | 8431 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8432 | POSTING_READ(PCH_DREF_CONTROL); |
8433 | udelay(200); | |
8434 | } | |
74cfd7ac CW |
8435 | |
8436 | BUG_ON(val != final); | |
13d83a67 JB |
8437 | } |
8438 | ||
f31f2d55 | 8439 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8440 | { |
f31f2d55 | 8441 | uint32_t tmp; |
dde86e2d | 8442 | |
0ff066a9 PZ |
8443 | tmp = I915_READ(SOUTH_CHICKEN2); |
8444 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8445 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8446 | |
0ff066a9 PZ |
8447 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8448 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8449 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8450 | |
0ff066a9 PZ |
8451 | tmp = I915_READ(SOUTH_CHICKEN2); |
8452 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8453 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8454 | |
0ff066a9 PZ |
8455 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8456 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8457 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8458 | } |
8459 | ||
8460 | /* WaMPhyProgramming:hsw */ | |
8461 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8462 | { | |
8463 | uint32_t tmp; | |
dde86e2d PZ |
8464 | |
8465 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8466 | tmp &= ~(0xFF << 24); | |
8467 | tmp |= (0x12 << 24); | |
8468 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8469 | ||
dde86e2d PZ |
8470 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8471 | tmp |= (1 << 11); | |
8472 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8473 | ||
8474 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8475 | tmp |= (1 << 11); | |
8476 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8477 | ||
dde86e2d PZ |
8478 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8479 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8480 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8481 | ||
8482 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8483 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8484 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8485 | ||
0ff066a9 PZ |
8486 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8487 | tmp &= ~(7 << 13); | |
8488 | tmp |= (5 << 13); | |
8489 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8490 | |
0ff066a9 PZ |
8491 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8492 | tmp &= ~(7 << 13); | |
8493 | tmp |= (5 << 13); | |
8494 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8495 | |
8496 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8497 | tmp &= ~0xFF; | |
8498 | tmp |= 0x1C; | |
8499 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8500 | ||
8501 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8502 | tmp &= ~0xFF; | |
8503 | tmp |= 0x1C; | |
8504 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8505 | ||
8506 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8507 | tmp &= ~(0xFF << 16); | |
8508 | tmp |= (0x1C << 16); | |
8509 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8510 | ||
8511 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8512 | tmp &= ~(0xFF << 16); | |
8513 | tmp |= (0x1C << 16); | |
8514 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8515 | ||
0ff066a9 PZ |
8516 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8517 | tmp |= (1 << 27); | |
8518 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8519 | |
0ff066a9 PZ |
8520 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8521 | tmp |= (1 << 27); | |
8522 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8523 | |
0ff066a9 PZ |
8524 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8525 | tmp &= ~(0xF << 28); | |
8526 | tmp |= (4 << 28); | |
8527 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8528 | |
0ff066a9 PZ |
8529 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8530 | tmp &= ~(0xF << 28); | |
8531 | tmp |= (4 << 28); | |
8532 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8533 | } |
8534 | ||
2fa86a1f PZ |
8535 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8536 | * Programming" based on the parameters passed: | |
8537 | * - Sequence to enable CLKOUT_DP | |
8538 | * - Sequence to enable CLKOUT_DP without spread | |
8539 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8540 | */ | |
8541 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8542 | bool with_fdi) | |
f31f2d55 PZ |
8543 | { |
8544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8545 | uint32_t reg, tmp; |
8546 | ||
8547 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8548 | with_spread = true; | |
c2699524 | 8549 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8550 | with_fdi = false; |
f31f2d55 | 8551 | |
a580516d | 8552 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8553 | |
8554 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8555 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8556 | tmp |= SBI_SSCCTL_PATHALT; | |
8557 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8558 | ||
8559 | udelay(24); | |
8560 | ||
2fa86a1f PZ |
8561 | if (with_spread) { |
8562 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8563 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8564 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8565 | |
2fa86a1f PZ |
8566 | if (with_fdi) { |
8567 | lpt_reset_fdi_mphy(dev_priv); | |
8568 | lpt_program_fdi_mphy(dev_priv); | |
8569 | } | |
8570 | } | |
dde86e2d | 8571 | |
c2699524 | 8572 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8573 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8574 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8575 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8576 | |
a580516d | 8577 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8578 | } |
8579 | ||
47701c3b PZ |
8580 | /* Sequence to disable CLKOUT_DP */ |
8581 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8582 | { | |
8583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8584 | uint32_t reg, tmp; | |
8585 | ||
a580516d | 8586 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8587 | |
c2699524 | 8588 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8589 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8590 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8591 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8592 | ||
8593 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8594 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8595 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8596 | tmp |= SBI_SSCCTL_PATHALT; | |
8597 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8598 | udelay(32); | |
8599 | } | |
8600 | tmp |= SBI_SSCCTL_DISABLE; | |
8601 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8602 | } | |
8603 | ||
a580516d | 8604 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8605 | } |
8606 | ||
f7be2c21 VS |
8607 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8608 | ||
8609 | static const uint16_t sscdivintphase[] = { | |
8610 | [BEND_IDX( 50)] = 0x3B23, | |
8611 | [BEND_IDX( 45)] = 0x3B23, | |
8612 | [BEND_IDX( 40)] = 0x3C23, | |
8613 | [BEND_IDX( 35)] = 0x3C23, | |
8614 | [BEND_IDX( 30)] = 0x3D23, | |
8615 | [BEND_IDX( 25)] = 0x3D23, | |
8616 | [BEND_IDX( 20)] = 0x3E23, | |
8617 | [BEND_IDX( 15)] = 0x3E23, | |
8618 | [BEND_IDX( 10)] = 0x3F23, | |
8619 | [BEND_IDX( 5)] = 0x3F23, | |
8620 | [BEND_IDX( 0)] = 0x0025, | |
8621 | [BEND_IDX( -5)] = 0x0025, | |
8622 | [BEND_IDX(-10)] = 0x0125, | |
8623 | [BEND_IDX(-15)] = 0x0125, | |
8624 | [BEND_IDX(-20)] = 0x0225, | |
8625 | [BEND_IDX(-25)] = 0x0225, | |
8626 | [BEND_IDX(-30)] = 0x0325, | |
8627 | [BEND_IDX(-35)] = 0x0325, | |
8628 | [BEND_IDX(-40)] = 0x0425, | |
8629 | [BEND_IDX(-45)] = 0x0425, | |
8630 | [BEND_IDX(-50)] = 0x0525, | |
8631 | }; | |
8632 | ||
8633 | /* | |
8634 | * Bend CLKOUT_DP | |
8635 | * steps -50 to 50 inclusive, in steps of 5 | |
8636 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8637 | * change in clock period = -(steps / 10) * 5.787 ps | |
8638 | */ | |
8639 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8640 | { | |
8641 | uint32_t tmp; | |
8642 | int idx = BEND_IDX(steps); | |
8643 | ||
8644 | if (WARN_ON(steps % 5 != 0)) | |
8645 | return; | |
8646 | ||
8647 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8648 | return; | |
8649 | ||
8650 | mutex_lock(&dev_priv->sb_lock); | |
8651 | ||
8652 | if (steps % 10 != 0) | |
8653 | tmp = 0xAAAAAAAB; | |
8654 | else | |
8655 | tmp = 0x00000000; | |
8656 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8657 | ||
8658 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8659 | tmp &= 0xffff0000; | |
8660 | tmp |= sscdivintphase[idx]; | |
8661 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8662 | ||
8663 | mutex_unlock(&dev_priv->sb_lock); | |
8664 | } | |
8665 | ||
8666 | #undef BEND_IDX | |
8667 | ||
bf8fa3d3 PZ |
8668 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8669 | { | |
bf8fa3d3 PZ |
8670 | struct intel_encoder *encoder; |
8671 | bool has_vga = false; | |
8672 | ||
b2784e15 | 8673 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8674 | switch (encoder->type) { |
8675 | case INTEL_OUTPUT_ANALOG: | |
8676 | has_vga = true; | |
8677 | break; | |
6847d71b PZ |
8678 | default: |
8679 | break; | |
bf8fa3d3 PZ |
8680 | } |
8681 | } | |
8682 | ||
f7be2c21 VS |
8683 | if (has_vga) { |
8684 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8685 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8686 | } else { |
47701c3b | 8687 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8688 | } |
bf8fa3d3 PZ |
8689 | } |
8690 | ||
dde86e2d PZ |
8691 | /* |
8692 | * Initialize reference clocks when the driver loads | |
8693 | */ | |
8694 | void intel_init_pch_refclk(struct drm_device *dev) | |
8695 | { | |
8696 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8697 | ironlake_init_pch_refclk(dev); | |
8698 | else if (HAS_PCH_LPT(dev)) | |
8699 | lpt_init_pch_refclk(dev); | |
8700 | } | |
8701 | ||
55bb9992 | 8702 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8703 | { |
55bb9992 | 8704 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8705 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8706 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8707 | struct drm_connector *connector; |
55bb9992 | 8708 | struct drm_connector_state *connector_state; |
d9d444cb | 8709 | struct intel_encoder *encoder; |
55bb9992 | 8710 | int num_connectors = 0, i; |
d9d444cb JB |
8711 | bool is_lvds = false; |
8712 | ||
da3ced29 | 8713 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8714 | if (connector_state->crtc != crtc_state->base.crtc) |
8715 | continue; | |
8716 | ||
8717 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8718 | ||
d9d444cb JB |
8719 | switch (encoder->type) { |
8720 | case INTEL_OUTPUT_LVDS: | |
8721 | is_lvds = true; | |
8722 | break; | |
6847d71b PZ |
8723 | default: |
8724 | break; | |
d9d444cb JB |
8725 | } |
8726 | num_connectors++; | |
8727 | } | |
8728 | ||
8729 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8730 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8731 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8732 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8733 | } |
8734 | ||
8735 | return 120000; | |
8736 | } | |
8737 | ||
6ff93609 | 8738 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8739 | { |
c8203565 | 8740 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8742 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8743 | uint32_t val; |
8744 | ||
78114071 | 8745 | val = 0; |
c8203565 | 8746 | |
6e3c9717 | 8747 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8748 | case 18: |
dfd07d72 | 8749 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8750 | break; |
8751 | case 24: | |
dfd07d72 | 8752 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8753 | break; |
8754 | case 30: | |
dfd07d72 | 8755 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8756 | break; |
8757 | case 36: | |
dfd07d72 | 8758 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8759 | break; |
8760 | default: | |
cc769b62 PZ |
8761 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8762 | BUG(); | |
c8203565 PZ |
8763 | } |
8764 | ||
6e3c9717 | 8765 | if (intel_crtc->config->dither) |
c8203565 PZ |
8766 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8767 | ||
6e3c9717 | 8768 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8769 | val |= PIPECONF_INTERLACED_ILK; |
8770 | else | |
8771 | val |= PIPECONF_PROGRESSIVE; | |
8772 | ||
6e3c9717 | 8773 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8774 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8775 | |
c8203565 PZ |
8776 | I915_WRITE(PIPECONF(pipe), val); |
8777 | POSTING_READ(PIPECONF(pipe)); | |
8778 | } | |
8779 | ||
86d3efce VS |
8780 | /* |
8781 | * Set up the pipe CSC unit. | |
8782 | * | |
8783 | * Currently only full range RGB to limited range RGB conversion | |
8784 | * is supported, but eventually this should handle various | |
8785 | * RGB<->YCbCr scenarios as well. | |
8786 | */ | |
50f3b016 | 8787 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8788 | { |
8789 | struct drm_device *dev = crtc->dev; | |
8790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8792 | int pipe = intel_crtc->pipe; | |
8793 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8794 | ||
8795 | /* | |
8796 | * TODO: Check what kind of values actually come out of the pipe | |
8797 | * with these coeff/postoff values and adjust to get the best | |
8798 | * accuracy. Perhaps we even need to take the bpc value into | |
8799 | * consideration. | |
8800 | */ | |
8801 | ||
6e3c9717 | 8802 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8803 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8804 | ||
8805 | /* | |
8806 | * GY/GU and RY/RU should be the other way around according | |
8807 | * to BSpec, but reality doesn't agree. Just set them up in | |
8808 | * a way that results in the correct picture. | |
8809 | */ | |
8810 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8811 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8812 | ||
8813 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8814 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8815 | ||
8816 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8817 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8818 | ||
8819 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8820 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8821 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8822 | ||
8823 | if (INTEL_INFO(dev)->gen > 6) { | |
8824 | uint16_t postoff = 0; | |
8825 | ||
6e3c9717 | 8826 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8827 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8828 | |
8829 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8830 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8831 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8832 | ||
8833 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8834 | } else { | |
8835 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8836 | ||
6e3c9717 | 8837 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8838 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8839 | ||
8840 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8841 | } | |
8842 | } | |
8843 | ||
6ff93609 | 8844 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8845 | { |
756f85cf PZ |
8846 | struct drm_device *dev = crtc->dev; |
8847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8849 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8850 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8851 | uint32_t val; |
8852 | ||
3eff4faa | 8853 | val = 0; |
ee2b0b38 | 8854 | |
6e3c9717 | 8855 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8856 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8857 | ||
6e3c9717 | 8858 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8859 | val |= PIPECONF_INTERLACED_ILK; |
8860 | else | |
8861 | val |= PIPECONF_PROGRESSIVE; | |
8862 | ||
702e7a56 PZ |
8863 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8864 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8865 | |
8866 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8867 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8868 | |
3cdf122c | 8869 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8870 | val = 0; |
8871 | ||
6e3c9717 | 8872 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8873 | case 18: |
8874 | val |= PIPEMISC_DITHER_6_BPC; | |
8875 | break; | |
8876 | case 24: | |
8877 | val |= PIPEMISC_DITHER_8_BPC; | |
8878 | break; | |
8879 | case 30: | |
8880 | val |= PIPEMISC_DITHER_10_BPC; | |
8881 | break; | |
8882 | case 36: | |
8883 | val |= PIPEMISC_DITHER_12_BPC; | |
8884 | break; | |
8885 | default: | |
8886 | /* Case prevented by pipe_config_set_bpp. */ | |
8887 | BUG(); | |
8888 | } | |
8889 | ||
6e3c9717 | 8890 | if (intel_crtc->config->dither) |
756f85cf PZ |
8891 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8892 | ||
8893 | I915_WRITE(PIPEMISC(pipe), val); | |
8894 | } | |
ee2b0b38 PZ |
8895 | } |
8896 | ||
6591c6e4 | 8897 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8898 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8899 | intel_clock_t *clock, |
8900 | bool *has_reduced_clock, | |
8901 | intel_clock_t *reduced_clock) | |
8902 | { | |
8903 | struct drm_device *dev = crtc->dev; | |
8904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8905 | int refclk; |
d4906093 | 8906 | const intel_limit_t *limit; |
c329a4ec | 8907 | bool ret; |
79e53945 | 8908 | |
55bb9992 | 8909 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8910 | |
d4906093 ML |
8911 | /* |
8912 | * Returns a set of divisors for the desired target clock with the given | |
8913 | * refclk, or FALSE. The returned values represent the clock equation: | |
8914 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8915 | */ | |
a93e255f ACO |
8916 | limit = intel_limit(crtc_state, refclk); |
8917 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8918 | crtc_state->port_clock, |
ee9300bb | 8919 | refclk, NULL, clock); |
6591c6e4 PZ |
8920 | if (!ret) |
8921 | return false; | |
cda4b7d3 | 8922 | |
6591c6e4 PZ |
8923 | return true; |
8924 | } | |
8925 | ||
d4b1931c PZ |
8926 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8927 | { | |
8928 | /* | |
8929 | * Account for spread spectrum to avoid | |
8930 | * oversubscribing the link. Max center spread | |
8931 | * is 2.5%; use 5% for safety's sake. | |
8932 | */ | |
8933 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8934 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8935 | } |
8936 | ||
7429e9d4 | 8937 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8938 | { |
7429e9d4 | 8939 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8940 | } |
8941 | ||
de13a2e3 | 8942 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8943 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8944 | u32 *fp, |
9a7c7890 | 8945 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8946 | { |
de13a2e3 | 8947 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8948 | struct drm_device *dev = crtc->dev; |
8949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8950 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8951 | struct drm_connector *connector; |
55bb9992 ACO |
8952 | struct drm_connector_state *connector_state; |
8953 | struct intel_encoder *encoder; | |
de13a2e3 | 8954 | uint32_t dpll; |
55bb9992 | 8955 | int factor, num_connectors = 0, i; |
09ede541 | 8956 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8957 | |
da3ced29 | 8958 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8959 | if (connector_state->crtc != crtc_state->base.crtc) |
8960 | continue; | |
8961 | ||
8962 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8963 | ||
8964 | switch (encoder->type) { | |
79e53945 JB |
8965 | case INTEL_OUTPUT_LVDS: |
8966 | is_lvds = true; | |
8967 | break; | |
8968 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8969 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8970 | is_sdvo = true; |
79e53945 | 8971 | break; |
6847d71b PZ |
8972 | default: |
8973 | break; | |
79e53945 | 8974 | } |
43565a06 | 8975 | |
c751ce4f | 8976 | num_connectors++; |
79e53945 | 8977 | } |
79e53945 | 8978 | |
c1858123 | 8979 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8980 | factor = 21; |
8981 | if (is_lvds) { | |
8982 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8983 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8984 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8985 | factor = 25; |
190f68c5 | 8986 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8987 | factor = 20; |
c1858123 | 8988 | |
190f68c5 | 8989 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8990 | *fp |= FP_CB_TUNE; |
2c07245f | 8991 | |
9a7c7890 DV |
8992 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8993 | *fp2 |= FP_CB_TUNE; | |
8994 | ||
5eddb70b | 8995 | dpll = 0; |
2c07245f | 8996 | |
a07d6787 EA |
8997 | if (is_lvds) |
8998 | dpll |= DPLLB_MODE_LVDS; | |
8999 | else | |
9000 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9001 | |
190f68c5 | 9002 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9003 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
9004 | |
9005 | if (is_sdvo) | |
4a33e48d | 9006 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 9007 | if (crtc_state->has_dp_encoder) |
4a33e48d | 9008 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9009 | |
a07d6787 | 9010 | /* compute bitmask from p1 value */ |
190f68c5 | 9011 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9012 | /* also FPA1 */ |
190f68c5 | 9013 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9014 | |
190f68c5 | 9015 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9016 | case 5: |
9017 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9018 | break; | |
9019 | case 7: | |
9020 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9021 | break; | |
9022 | case 10: | |
9023 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9024 | break; | |
9025 | case 14: | |
9026 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9027 | break; | |
79e53945 JB |
9028 | } |
9029 | ||
b4c09f3b | 9030 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9031 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9032 | else |
9033 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9034 | ||
959e16d6 | 9035 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9036 | } |
9037 | ||
190f68c5 ACO |
9038 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9039 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9040 | { |
c7653199 | 9041 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9042 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9043 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9044 | bool ok, has_reduced_clock = false; |
8b47047b | 9045 | bool is_lvds = false; |
e2b78267 | 9046 | struct intel_shared_dpll *pll; |
de13a2e3 | 9047 | |
dd3cd74a ACO |
9048 | memset(&crtc_state->dpll_hw_state, 0, |
9049 | sizeof(crtc_state->dpll_hw_state)); | |
9050 | ||
7905df29 | 9051 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9052 | |
5dc5298b PZ |
9053 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9054 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9055 | |
190f68c5 | 9056 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9057 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9058 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9059 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9060 | return -EINVAL; | |
79e53945 | 9061 | } |
f47709a9 | 9062 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9063 | if (!crtc_state->clock_set) { |
9064 | crtc_state->dpll.n = clock.n; | |
9065 | crtc_state->dpll.m1 = clock.m1; | |
9066 | crtc_state->dpll.m2 = clock.m2; | |
9067 | crtc_state->dpll.p1 = clock.p1; | |
9068 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9069 | } |
79e53945 | 9070 | |
5dc5298b | 9071 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9072 | if (crtc_state->has_pch_encoder) { |
9073 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9074 | if (has_reduced_clock) |
7429e9d4 | 9075 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9076 | |
190f68c5 | 9077 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9078 | &fp, &reduced_clock, |
9079 | has_reduced_clock ? &fp2 : NULL); | |
9080 | ||
190f68c5 ACO |
9081 | crtc_state->dpll_hw_state.dpll = dpll; |
9082 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9083 | if (has_reduced_clock) |
190f68c5 | 9084 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9085 | else |
190f68c5 | 9086 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9087 | |
190f68c5 | 9088 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9089 | if (pll == NULL) { |
84f44ce7 | 9090 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9091 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9092 | return -EINVAL; |
9093 | } | |
3fb37703 | 9094 | } |
79e53945 | 9095 | |
ab585dea | 9096 | if (is_lvds && has_reduced_clock) |
c7653199 | 9097 | crtc->lowfreq_avail = true; |
bcd644e0 | 9098 | else |
c7653199 | 9099 | crtc->lowfreq_avail = false; |
e2b78267 | 9100 | |
c8f7a0db | 9101 | return 0; |
79e53945 JB |
9102 | } |
9103 | ||
eb14cb74 VS |
9104 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9105 | struct intel_link_m_n *m_n) | |
9106 | { | |
9107 | struct drm_device *dev = crtc->base.dev; | |
9108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9109 | enum pipe pipe = crtc->pipe; | |
9110 | ||
9111 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9112 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9113 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9114 | & ~TU_SIZE_MASK; | |
9115 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9116 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9117 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9118 | } | |
9119 | ||
9120 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9121 | enum transcoder transcoder, | |
b95af8be VK |
9122 | struct intel_link_m_n *m_n, |
9123 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9124 | { |
9125 | struct drm_device *dev = crtc->base.dev; | |
9126 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9127 | enum pipe pipe = crtc->pipe; |
72419203 | 9128 | |
eb14cb74 VS |
9129 | if (INTEL_INFO(dev)->gen >= 5) { |
9130 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9131 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9132 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9133 | & ~TU_SIZE_MASK; | |
9134 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9135 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9136 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9137 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9138 | * gen < 8) and if DRRS is supported (to make sure the | |
9139 | * registers are not unnecessarily read). | |
9140 | */ | |
9141 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9142 | crtc->config->has_drrs) { |
b95af8be VK |
9143 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9144 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9145 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9146 | & ~TU_SIZE_MASK; | |
9147 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9148 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9149 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9150 | } | |
eb14cb74 VS |
9151 | } else { |
9152 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9153 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9154 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9155 | & ~TU_SIZE_MASK; | |
9156 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9157 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9158 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9159 | } | |
9160 | } | |
9161 | ||
9162 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9163 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9164 | { |
681a8504 | 9165 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9166 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9167 | else | |
9168 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9169 | &pipe_config->dp_m_n, |
9170 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9171 | } |
72419203 | 9172 | |
eb14cb74 | 9173 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9174 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9175 | { |
9176 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9177 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9178 | } |
9179 | ||
bd2e244f | 9180 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9181 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9182 | { |
9183 | struct drm_device *dev = crtc->base.dev; | |
9184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9185 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9186 | uint32_t ps_ctrl = 0; | |
9187 | int id = -1; | |
9188 | int i; | |
bd2e244f | 9189 | |
a1b2278e CK |
9190 | /* find scaler attached to this pipe */ |
9191 | for (i = 0; i < crtc->num_scalers; i++) { | |
9192 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9193 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9194 | id = i; | |
9195 | pipe_config->pch_pfit.enabled = true; | |
9196 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9197 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9198 | break; | |
9199 | } | |
9200 | } | |
bd2e244f | 9201 | |
a1b2278e CK |
9202 | scaler_state->scaler_id = id; |
9203 | if (id >= 0) { | |
9204 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9205 | } else { | |
9206 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9207 | } |
9208 | } | |
9209 | ||
5724dbd1 DL |
9210 | static void |
9211 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9212 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9213 | { |
9214 | struct drm_device *dev = crtc->base.dev; | |
9215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9216 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9217 | int pipe = crtc->pipe; |
9218 | int fourcc, pixel_format; | |
6761dd31 | 9219 | unsigned int aligned_height; |
bc8d7dff | 9220 | struct drm_framebuffer *fb; |
1b842c89 | 9221 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9222 | |
d9806c9f | 9223 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9224 | if (!intel_fb) { |
bc8d7dff DL |
9225 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9226 | return; | |
9227 | } | |
9228 | ||
1b842c89 DL |
9229 | fb = &intel_fb->base; |
9230 | ||
bc8d7dff | 9231 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9232 | if (!(val & PLANE_CTL_ENABLE)) |
9233 | goto error; | |
9234 | ||
bc8d7dff DL |
9235 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9236 | fourcc = skl_format_to_fourcc(pixel_format, | |
9237 | val & PLANE_CTL_ORDER_RGBX, | |
9238 | val & PLANE_CTL_ALPHA_MASK); | |
9239 | fb->pixel_format = fourcc; | |
9240 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9241 | ||
40f46283 DL |
9242 | tiling = val & PLANE_CTL_TILED_MASK; |
9243 | switch (tiling) { | |
9244 | case PLANE_CTL_TILED_LINEAR: | |
9245 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9246 | break; | |
9247 | case PLANE_CTL_TILED_X: | |
9248 | plane_config->tiling = I915_TILING_X; | |
9249 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9250 | break; | |
9251 | case PLANE_CTL_TILED_Y: | |
9252 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9253 | break; | |
9254 | case PLANE_CTL_TILED_YF: | |
9255 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9256 | break; | |
9257 | default: | |
9258 | MISSING_CASE(tiling); | |
9259 | goto error; | |
9260 | } | |
9261 | ||
bc8d7dff DL |
9262 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9263 | plane_config->base = base; | |
9264 | ||
9265 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9266 | ||
9267 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9268 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9269 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9270 | ||
9271 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9272 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9273 | fb->pixel_format); | |
bc8d7dff DL |
9274 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9275 | ||
9276 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9277 | fb->pixel_format, |
9278 | fb->modifier[0]); | |
bc8d7dff | 9279 | |
f37b5c2b | 9280 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9281 | |
9282 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9283 | pipe_name(pipe), fb->width, fb->height, | |
9284 | fb->bits_per_pixel, base, fb->pitches[0], | |
9285 | plane_config->size); | |
9286 | ||
2d14030b | 9287 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9288 | return; |
9289 | ||
9290 | error: | |
9291 | kfree(fb); | |
9292 | } | |
9293 | ||
2fa2fe9a | 9294 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9295 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9296 | { |
9297 | struct drm_device *dev = crtc->base.dev; | |
9298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9299 | uint32_t tmp; | |
9300 | ||
9301 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9302 | ||
9303 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9304 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9305 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9306 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9307 | |
9308 | /* We currently do not free assignements of panel fitters on | |
9309 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9310 | * differentiates them) so just WARN about this case for now. */ | |
9311 | if (IS_GEN7(dev)) { | |
9312 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9313 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9314 | } | |
2fa2fe9a | 9315 | } |
79e53945 JB |
9316 | } |
9317 | ||
5724dbd1 DL |
9318 | static void |
9319 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9320 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9321 | { |
9322 | struct drm_device *dev = crtc->base.dev; | |
9323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9324 | u32 val, base, offset; | |
aeee5a49 | 9325 | int pipe = crtc->pipe; |
4c6baa59 | 9326 | int fourcc, pixel_format; |
6761dd31 | 9327 | unsigned int aligned_height; |
b113d5ee | 9328 | struct drm_framebuffer *fb; |
1b842c89 | 9329 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9330 | |
42a7b088 DL |
9331 | val = I915_READ(DSPCNTR(pipe)); |
9332 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9333 | return; | |
9334 | ||
d9806c9f | 9335 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9336 | if (!intel_fb) { |
4c6baa59 JB |
9337 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9338 | return; | |
9339 | } | |
9340 | ||
1b842c89 DL |
9341 | fb = &intel_fb->base; |
9342 | ||
18c5247e DV |
9343 | if (INTEL_INFO(dev)->gen >= 4) { |
9344 | if (val & DISPPLANE_TILED) { | |
49af449b | 9345 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9346 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9347 | } | |
9348 | } | |
4c6baa59 JB |
9349 | |
9350 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9351 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9352 | fb->pixel_format = fourcc; |
9353 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9354 | |
aeee5a49 | 9355 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9356 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9357 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9358 | } else { |
49af449b | 9359 | if (plane_config->tiling) |
aeee5a49 | 9360 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9361 | else |
aeee5a49 | 9362 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9363 | } |
9364 | plane_config->base = base; | |
9365 | ||
9366 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9367 | fb->width = ((val >> 16) & 0xfff) + 1; |
9368 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9369 | |
9370 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9371 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9372 | |
b113d5ee | 9373 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9374 | fb->pixel_format, |
9375 | fb->modifier[0]); | |
4c6baa59 | 9376 | |
f37b5c2b | 9377 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9378 | |
2844a921 DL |
9379 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9380 | pipe_name(pipe), fb->width, fb->height, | |
9381 | fb->bits_per_pixel, base, fb->pitches[0], | |
9382 | plane_config->size); | |
b113d5ee | 9383 | |
2d14030b | 9384 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9385 | } |
9386 | ||
0e8ffe1b | 9387 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9388 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9389 | { |
9390 | struct drm_device *dev = crtc->base.dev; | |
9391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9392 | uint32_t tmp; | |
9393 | ||
f458ebbc DV |
9394 | if (!intel_display_power_is_enabled(dev_priv, |
9395 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9396 | return false; |
9397 | ||
e143a21c | 9398 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9399 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9400 | |
0e8ffe1b DV |
9401 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9402 | if (!(tmp & PIPECONF_ENABLE)) | |
9403 | return false; | |
9404 | ||
42571aef VS |
9405 | switch (tmp & PIPECONF_BPC_MASK) { |
9406 | case PIPECONF_6BPC: | |
9407 | pipe_config->pipe_bpp = 18; | |
9408 | break; | |
9409 | case PIPECONF_8BPC: | |
9410 | pipe_config->pipe_bpp = 24; | |
9411 | break; | |
9412 | case PIPECONF_10BPC: | |
9413 | pipe_config->pipe_bpp = 30; | |
9414 | break; | |
9415 | case PIPECONF_12BPC: | |
9416 | pipe_config->pipe_bpp = 36; | |
9417 | break; | |
9418 | default: | |
9419 | break; | |
9420 | } | |
9421 | ||
b5a9fa09 DV |
9422 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9423 | pipe_config->limited_color_range = true; | |
9424 | ||
ab9412ba | 9425 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9426 | struct intel_shared_dpll *pll; |
9427 | ||
88adfff1 DV |
9428 | pipe_config->has_pch_encoder = true; |
9429 | ||
627eb5a3 DV |
9430 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9431 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9432 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9433 | |
9434 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9435 | |
c0d43d62 | 9436 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9437 | pipe_config->shared_dpll = |
9438 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9439 | } else { |
9440 | tmp = I915_READ(PCH_DPLL_SEL); | |
9441 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9442 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9443 | else | |
9444 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9445 | } | |
66e985c0 DV |
9446 | |
9447 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9448 | ||
9449 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9450 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9451 | |
9452 | tmp = pipe_config->dpll_hw_state.dpll; | |
9453 | pipe_config->pixel_multiplier = | |
9454 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9455 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9456 | |
9457 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9458 | } else { |
9459 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9460 | } |
9461 | ||
1bd1bd80 DV |
9462 | intel_get_pipe_timings(crtc, pipe_config); |
9463 | ||
2fa2fe9a DV |
9464 | ironlake_get_pfit_config(crtc, pipe_config); |
9465 | ||
0e8ffe1b DV |
9466 | return true; |
9467 | } | |
9468 | ||
be256dc7 PZ |
9469 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9470 | { | |
9471 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9472 | struct intel_crtc *crtc; |
be256dc7 | 9473 | |
d3fcc808 | 9474 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9475 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9476 | pipe_name(crtc->pipe)); |
9477 | ||
e2c719b7 RC |
9478 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9479 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9480 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9481 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9482 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9483 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9484 | "CPU PWM1 enabled\n"); |
c5107b87 | 9485 | if (IS_HASWELL(dev)) |
e2c719b7 | 9486 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9487 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9488 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9489 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9490 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9491 | "Utility pin enabled\n"); |
e2c719b7 | 9492 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9493 | |
9926ada1 PZ |
9494 | /* |
9495 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9496 | * interrupts remain enabled. We used to check for that, but since it's | |
9497 | * gen-specific and since we only disable LCPLL after we fully disable | |
9498 | * the interrupts, the check below should be enough. | |
9499 | */ | |
e2c719b7 | 9500 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9501 | } |
9502 | ||
9ccd5aeb PZ |
9503 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9504 | { | |
9505 | struct drm_device *dev = dev_priv->dev; | |
9506 | ||
9507 | if (IS_HASWELL(dev)) | |
9508 | return I915_READ(D_COMP_HSW); | |
9509 | else | |
9510 | return I915_READ(D_COMP_BDW); | |
9511 | } | |
9512 | ||
3c4c9b81 PZ |
9513 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9514 | { | |
9515 | struct drm_device *dev = dev_priv->dev; | |
9516 | ||
9517 | if (IS_HASWELL(dev)) { | |
9518 | mutex_lock(&dev_priv->rps.hw_lock); | |
9519 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9520 | val)) | |
f475dadf | 9521 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9522 | mutex_unlock(&dev_priv->rps.hw_lock); |
9523 | } else { | |
9ccd5aeb PZ |
9524 | I915_WRITE(D_COMP_BDW, val); |
9525 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9526 | } |
be256dc7 PZ |
9527 | } |
9528 | ||
9529 | /* | |
9530 | * This function implements pieces of two sequences from BSpec: | |
9531 | * - Sequence for display software to disable LCPLL | |
9532 | * - Sequence for display software to allow package C8+ | |
9533 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9534 | * register. Callers should take care of disabling all the display engine | |
9535 | * functions, doing the mode unset, fixing interrupts, etc. | |
9536 | */ | |
6ff58d53 PZ |
9537 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9538 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9539 | { |
9540 | uint32_t val; | |
9541 | ||
9542 | assert_can_disable_lcpll(dev_priv); | |
9543 | ||
9544 | val = I915_READ(LCPLL_CTL); | |
9545 | ||
9546 | if (switch_to_fclk) { | |
9547 | val |= LCPLL_CD_SOURCE_FCLK; | |
9548 | I915_WRITE(LCPLL_CTL, val); | |
9549 | ||
9550 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9551 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9552 | DRM_ERROR("Switching to FCLK failed\n"); | |
9553 | ||
9554 | val = I915_READ(LCPLL_CTL); | |
9555 | } | |
9556 | ||
9557 | val |= LCPLL_PLL_DISABLE; | |
9558 | I915_WRITE(LCPLL_CTL, val); | |
9559 | POSTING_READ(LCPLL_CTL); | |
9560 | ||
9561 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9562 | DRM_ERROR("LCPLL still locked\n"); | |
9563 | ||
9ccd5aeb | 9564 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9565 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9566 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9567 | ndelay(100); |
9568 | ||
9ccd5aeb PZ |
9569 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9570 | 1)) | |
be256dc7 PZ |
9571 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9572 | ||
9573 | if (allow_power_down) { | |
9574 | val = I915_READ(LCPLL_CTL); | |
9575 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9576 | I915_WRITE(LCPLL_CTL, val); | |
9577 | POSTING_READ(LCPLL_CTL); | |
9578 | } | |
9579 | } | |
9580 | ||
9581 | /* | |
9582 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9583 | * source. | |
9584 | */ | |
6ff58d53 | 9585 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9586 | { |
9587 | uint32_t val; | |
9588 | ||
9589 | val = I915_READ(LCPLL_CTL); | |
9590 | ||
9591 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9592 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9593 | return; | |
9594 | ||
a8a8bd54 PZ |
9595 | /* |
9596 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9597 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9598 | */ |
59bad947 | 9599 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9600 | |
be256dc7 PZ |
9601 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9602 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9603 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9604 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9605 | } |
9606 | ||
9ccd5aeb | 9607 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9608 | val |= D_COMP_COMP_FORCE; |
9609 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9610 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9611 | |
9612 | val = I915_READ(LCPLL_CTL); | |
9613 | val &= ~LCPLL_PLL_DISABLE; | |
9614 | I915_WRITE(LCPLL_CTL, val); | |
9615 | ||
9616 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9617 | DRM_ERROR("LCPLL not locked yet\n"); | |
9618 | ||
9619 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9620 | val = I915_READ(LCPLL_CTL); | |
9621 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9622 | I915_WRITE(LCPLL_CTL, val); | |
9623 | ||
9624 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9625 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9626 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9627 | } | |
215733fa | 9628 | |
59bad947 | 9629 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9630 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9631 | } |
9632 | ||
765dab67 PZ |
9633 | /* |
9634 | * Package states C8 and deeper are really deep PC states that can only be | |
9635 | * reached when all the devices on the system allow it, so even if the graphics | |
9636 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9637 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9638 | * | |
9639 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9640 | * well is disabled and most interrupts are disabled, and these are also | |
9641 | * requirements for runtime PM. When these conditions are met, we manually do | |
9642 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9643 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9644 | * hang the machine. | |
9645 | * | |
9646 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9647 | * the state of some registers, so when we come back from PC8+ we need to | |
9648 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9649 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9650 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9651 | * because of the runtime PM support). | |
9652 | * | |
9653 | * For more, read "Display Sequences for Package C8" on the hardware | |
9654 | * documentation. | |
9655 | */ | |
a14cb6fc | 9656 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9657 | { |
c67a470b PZ |
9658 | struct drm_device *dev = dev_priv->dev; |
9659 | uint32_t val; | |
9660 | ||
c67a470b PZ |
9661 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9662 | ||
c2699524 | 9663 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9664 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9665 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9666 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9667 | } | |
9668 | ||
9669 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9670 | hsw_disable_lcpll(dev_priv, true, true); |
9671 | } | |
9672 | ||
a14cb6fc | 9673 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9674 | { |
9675 | struct drm_device *dev = dev_priv->dev; | |
9676 | uint32_t val; | |
9677 | ||
c67a470b PZ |
9678 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9679 | ||
9680 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9681 | lpt_init_pch_refclk(dev); |
9682 | ||
c2699524 | 9683 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9684 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9685 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9686 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9687 | } | |
9688 | ||
9689 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9690 | } |
9691 | ||
27c329ed | 9692 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9693 | { |
a821fc46 | 9694 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9695 | struct intel_atomic_state *old_intel_state = |
9696 | to_intel_atomic_state(old_state); | |
9697 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9698 | |
27c329ed | 9699 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9700 | } |
9701 | ||
b432e5cf | 9702 | /* compute the max rate for new configuration */ |
27c329ed | 9703 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9704 | { |
565602d7 ML |
9705 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9706 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9707 | struct drm_crtc *crtc; | |
9708 | struct drm_crtc_state *cstate; | |
27c329ed | 9709 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9710 | unsigned max_pixel_rate = 0, i; |
9711 | enum pipe pipe; | |
b432e5cf | 9712 | |
565602d7 ML |
9713 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9714 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9715 | |
565602d7 ML |
9716 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9717 | int pixel_rate; | |
27c329ed | 9718 | |
565602d7 ML |
9719 | crtc_state = to_intel_crtc_state(cstate); |
9720 | if (!crtc_state->base.enable) { | |
9721 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9722 | continue; |
565602d7 | 9723 | } |
b432e5cf | 9724 | |
27c329ed | 9725 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9726 | |
9727 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9728 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9729 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9730 | ||
565602d7 | 9731 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9732 | } |
9733 | ||
565602d7 ML |
9734 | if (!intel_state->active_crtcs) |
9735 | return 0; | |
9736 | ||
9737 | for_each_pipe(dev_priv, pipe) | |
9738 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9739 | ||
b432e5cf VS |
9740 | return max_pixel_rate; |
9741 | } | |
9742 | ||
9743 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9744 | { | |
9745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9746 | uint32_t val, data; | |
9747 | int ret; | |
9748 | ||
9749 | if (WARN((I915_READ(LCPLL_CTL) & | |
9750 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9751 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9752 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9753 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9754 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9755 | return; | |
9756 | ||
9757 | mutex_lock(&dev_priv->rps.hw_lock); | |
9758 | ret = sandybridge_pcode_write(dev_priv, | |
9759 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9760 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9761 | if (ret) { | |
9762 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9763 | return; | |
9764 | } | |
9765 | ||
9766 | val = I915_READ(LCPLL_CTL); | |
9767 | val |= LCPLL_CD_SOURCE_FCLK; | |
9768 | I915_WRITE(LCPLL_CTL, val); | |
9769 | ||
9770 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9771 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9772 | DRM_ERROR("Switching to FCLK failed\n"); | |
9773 | ||
9774 | val = I915_READ(LCPLL_CTL); | |
9775 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9776 | ||
9777 | switch (cdclk) { | |
9778 | case 450000: | |
9779 | val |= LCPLL_CLK_FREQ_450; | |
9780 | data = 0; | |
9781 | break; | |
9782 | case 540000: | |
9783 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9784 | data = 1; | |
9785 | break; | |
9786 | case 337500: | |
9787 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9788 | data = 2; | |
9789 | break; | |
9790 | case 675000: | |
9791 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9792 | data = 3; | |
9793 | break; | |
9794 | default: | |
9795 | WARN(1, "invalid cdclk frequency\n"); | |
9796 | return; | |
9797 | } | |
9798 | ||
9799 | I915_WRITE(LCPLL_CTL, val); | |
9800 | ||
9801 | val = I915_READ(LCPLL_CTL); | |
9802 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9803 | I915_WRITE(LCPLL_CTL, val); | |
9804 | ||
9805 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9806 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9807 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9808 | ||
9809 | mutex_lock(&dev_priv->rps.hw_lock); | |
9810 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9811 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9812 | ||
9813 | intel_update_cdclk(dev); | |
9814 | ||
9815 | WARN(cdclk != dev_priv->cdclk_freq, | |
9816 | "cdclk requested %d kHz but got %d kHz\n", | |
9817 | cdclk, dev_priv->cdclk_freq); | |
9818 | } | |
9819 | ||
27c329ed | 9820 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9821 | { |
27c329ed | 9822 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9823 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9824 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9825 | int cdclk; |
9826 | ||
9827 | /* | |
9828 | * FIXME should also account for plane ratio | |
9829 | * once 64bpp pixel formats are supported. | |
9830 | */ | |
27c329ed | 9831 | if (max_pixclk > 540000) |
b432e5cf | 9832 | cdclk = 675000; |
27c329ed | 9833 | else if (max_pixclk > 450000) |
b432e5cf | 9834 | cdclk = 540000; |
27c329ed | 9835 | else if (max_pixclk > 337500) |
b432e5cf VS |
9836 | cdclk = 450000; |
9837 | else | |
9838 | cdclk = 337500; | |
9839 | ||
b432e5cf | 9840 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9841 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9842 | cdclk, dev_priv->max_cdclk_freq); | |
9843 | return -EINVAL; | |
b432e5cf VS |
9844 | } |
9845 | ||
1a617b77 ML |
9846 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9847 | if (!intel_state->active_crtcs) | |
9848 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9849 | |
9850 | return 0; | |
9851 | } | |
9852 | ||
27c329ed | 9853 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9854 | { |
27c329ed | 9855 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9856 | struct intel_atomic_state *old_intel_state = |
9857 | to_intel_atomic_state(old_state); | |
9858 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9859 | |
27c329ed | 9860 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9861 | } |
9862 | ||
190f68c5 ACO |
9863 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9864 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9865 | { |
190f68c5 | 9866 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9867 | return -EINVAL; |
716c2e55 | 9868 | |
c7653199 | 9869 | crtc->lowfreq_avail = false; |
644cef34 | 9870 | |
c8f7a0db | 9871 | return 0; |
79e53945 JB |
9872 | } |
9873 | ||
3760b59c S |
9874 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9875 | enum port port, | |
9876 | struct intel_crtc_state *pipe_config) | |
9877 | { | |
9878 | switch (port) { | |
9879 | case PORT_A: | |
9880 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9881 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9882 | break; | |
9883 | case PORT_B: | |
9884 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9885 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9886 | break; | |
9887 | case PORT_C: | |
9888 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9889 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9890 | break; | |
9891 | default: | |
9892 | DRM_ERROR("Incorrect port type\n"); | |
9893 | } | |
9894 | } | |
9895 | ||
96b7dfb7 S |
9896 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9897 | enum port port, | |
5cec258b | 9898 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9899 | { |
3148ade7 | 9900 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9901 | |
9902 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9903 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9904 | ||
9905 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9906 | case SKL_DPLL0: |
9907 | /* | |
9908 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9909 | * of the shared DPLL framework and thus needs to be read out | |
9910 | * separately | |
9911 | */ | |
9912 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9913 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9914 | break; | |
96b7dfb7 S |
9915 | case SKL_DPLL1: |
9916 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9917 | break; | |
9918 | case SKL_DPLL2: | |
9919 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9920 | break; | |
9921 | case SKL_DPLL3: | |
9922 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9923 | break; | |
96b7dfb7 S |
9924 | } |
9925 | } | |
9926 | ||
7d2c8175 DL |
9927 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9928 | enum port port, | |
5cec258b | 9929 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9930 | { |
9931 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9932 | ||
9933 | switch (pipe_config->ddi_pll_sel) { | |
9934 | case PORT_CLK_SEL_WRPLL1: | |
9935 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9936 | break; | |
9937 | case PORT_CLK_SEL_WRPLL2: | |
9938 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9939 | break; | |
00490c22 ML |
9940 | case PORT_CLK_SEL_SPLL: |
9941 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9942 | break; |
7d2c8175 DL |
9943 | } |
9944 | } | |
9945 | ||
26804afd | 9946 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9947 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9948 | { |
9949 | struct drm_device *dev = crtc->base.dev; | |
9950 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9951 | struct intel_shared_dpll *pll; |
26804afd DV |
9952 | enum port port; |
9953 | uint32_t tmp; | |
9954 | ||
9955 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9956 | ||
9957 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9958 | ||
ef11bdb3 | 9959 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9960 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9961 | else if (IS_BROXTON(dev)) |
9962 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9963 | else |
9964 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9965 | |
d452c5b6 DV |
9966 | if (pipe_config->shared_dpll >= 0) { |
9967 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9968 | ||
9969 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9970 | &pipe_config->dpll_hw_state)); | |
9971 | } | |
9972 | ||
26804afd DV |
9973 | /* |
9974 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9975 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9976 | * the PCH transcoder is on. | |
9977 | */ | |
ca370455 DL |
9978 | if (INTEL_INFO(dev)->gen < 9 && |
9979 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9980 | pipe_config->has_pch_encoder = true; |
9981 | ||
9982 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9983 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9984 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9985 | ||
9986 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9987 | } | |
9988 | } | |
9989 | ||
0e8ffe1b | 9990 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9991 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9992 | { |
9993 | struct drm_device *dev = crtc->base.dev; | |
9994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9995 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9996 | uint32_t tmp; |
9997 | ||
f458ebbc | 9998 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9999 | POWER_DOMAIN_PIPE(crtc->pipe))) |
10000 | return false; | |
10001 | ||
e143a21c | 10002 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
10003 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
10004 | ||
eccb140b DV |
10005 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10006 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10007 | enum pipe trans_edp_pipe; | |
10008 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10009 | default: | |
10010 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10011 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10012 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10013 | trans_edp_pipe = PIPE_A; | |
10014 | break; | |
10015 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10016 | trans_edp_pipe = PIPE_B; | |
10017 | break; | |
10018 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10019 | trans_edp_pipe = PIPE_C; | |
10020 | break; | |
10021 | } | |
10022 | ||
10023 | if (trans_edp_pipe == crtc->pipe) | |
10024 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10025 | } | |
10026 | ||
f458ebbc | 10027 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 10028 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
10029 | return false; |
10030 | ||
eccb140b | 10031 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
10032 | if (!(tmp & PIPECONF_ENABLE)) |
10033 | return false; | |
10034 | ||
26804afd | 10035 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10036 | |
1bd1bd80 DV |
10037 | intel_get_pipe_timings(crtc, pipe_config); |
10038 | ||
a1b2278e CK |
10039 | if (INTEL_INFO(dev)->gen >= 9) { |
10040 | skl_init_scalers(dev, crtc, pipe_config); | |
10041 | } | |
10042 | ||
2fa2fe9a | 10043 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10044 | |
10045 | if (INTEL_INFO(dev)->gen >= 9) { | |
10046 | pipe_config->scaler_state.scaler_id = -1; | |
10047 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10048 | } | |
10049 | ||
bd2e244f | 10050 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10051 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10052 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10053 | else |
1c132b44 | 10054 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10055 | } |
88adfff1 | 10056 | |
e59150dc JB |
10057 | if (IS_HASWELL(dev)) |
10058 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10059 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10060 | |
ebb69c95 CT |
10061 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10062 | pipe_config->pixel_multiplier = | |
10063 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10064 | } else { | |
10065 | pipe_config->pixel_multiplier = 1; | |
10066 | } | |
6c49f241 | 10067 | |
0e8ffe1b DV |
10068 | return true; |
10069 | } | |
10070 | ||
663f3122 | 10071 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
560b85bb CW |
10072 | { |
10073 | struct drm_device *dev = crtc->dev; | |
10074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10076 | uint32_t cntl = 0, size = 0; |
560b85bb | 10077 | |
663f3122 | 10078 | if (on) { |
3dd512fb MR |
10079 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10080 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
10081 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10082 | ||
10083 | switch (stride) { | |
10084 | default: | |
10085 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10086 | width, stride); | |
10087 | stride = 256; | |
10088 | /* fallthrough */ | |
10089 | case 256: | |
10090 | case 512: | |
10091 | case 1024: | |
10092 | case 2048: | |
10093 | break; | |
4b0e333e CW |
10094 | } |
10095 | ||
dc41c154 VS |
10096 | cntl |= CURSOR_ENABLE | |
10097 | CURSOR_GAMMA_ENABLE | | |
10098 | CURSOR_FORMAT_ARGB | | |
10099 | CURSOR_STRIDE(stride); | |
10100 | ||
10101 | size = (height << 12) | width; | |
4b0e333e | 10102 | } |
560b85bb | 10103 | |
dc41c154 VS |
10104 | if (intel_crtc->cursor_cntl != 0 && |
10105 | (intel_crtc->cursor_base != base || | |
10106 | intel_crtc->cursor_size != size || | |
10107 | intel_crtc->cursor_cntl != cntl)) { | |
10108 | /* On these chipsets we can only modify the base/size/stride | |
10109 | * whilst the cursor is disabled. | |
10110 | */ | |
0b87c24e VS |
10111 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10112 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10113 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10114 | } |
560b85bb | 10115 | |
99d1f387 | 10116 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10117 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10118 | intel_crtc->cursor_base = base; |
10119 | } | |
4726e0b0 | 10120 | |
dc41c154 VS |
10121 | if (intel_crtc->cursor_size != size) { |
10122 | I915_WRITE(CURSIZE, size); | |
10123 | intel_crtc->cursor_size = size; | |
4b0e333e | 10124 | } |
560b85bb | 10125 | |
4b0e333e | 10126 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10127 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10128 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10129 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10130 | } |
560b85bb CW |
10131 | } |
10132 | ||
663f3122 | 10133 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
65a21cd6 JB |
10134 | { |
10135 | struct drm_device *dev = crtc->dev; | |
10136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10138 | int pipe = intel_crtc->pipe; | |
663f3122 | 10139 | uint32_t cntl = 0; |
4b0e333e | 10140 | |
663f3122 | 10141 | if (on) { |
4b0e333e | 10142 | cntl = MCURSOR_GAMMA_ENABLE; |
3dd512fb | 10143 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10144 | case 64: |
10145 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10146 | break; | |
10147 | case 128: | |
10148 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10149 | break; | |
10150 | case 256: | |
10151 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10152 | break; | |
10153 | default: | |
3dd512fb | 10154 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10155 | return; |
65a21cd6 | 10156 | } |
4b0e333e | 10157 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10158 | |
fc6f93bc | 10159 | if (HAS_DDI(dev)) |
47bf17a7 | 10160 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4b0e333e | 10161 | } |
65a21cd6 | 10162 | |
8e7d688b | 10163 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10164 | cntl |= CURSOR_ROTATE_180; |
10165 | ||
4b0e333e CW |
10166 | if (intel_crtc->cursor_cntl != cntl) { |
10167 | I915_WRITE(CURCNTR(pipe), cntl); | |
10168 | POSTING_READ(CURCNTR(pipe)); | |
10169 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10170 | } |
4b0e333e | 10171 | |
65a21cd6 | 10172 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10173 | I915_WRITE(CURBASE(pipe), base); |
10174 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10175 | |
10176 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10177 | } |
10178 | ||
cda4b7d3 | 10179 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10180 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10181 | bool on) | |
cda4b7d3 CW |
10182 | { |
10183 | struct drm_device *dev = crtc->dev; | |
10184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10186 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
10187 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
10188 | int x = cursor_state->crtc_x; | |
10189 | int y = cursor_state->crtc_y; | |
d6e4db15 | 10190 | u32 base = 0, pos = 0; |
cda4b7d3 | 10191 | |
663f3122 | 10192 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10193 | |
6e3c9717 | 10194 | if (x >= intel_crtc->config->pipe_src_w) |
663f3122 | 10195 | on = false; |
d6e4db15 | 10196 | |
6e3c9717 | 10197 | if (y >= intel_crtc->config->pipe_src_h) |
663f3122 | 10198 | on = false; |
cda4b7d3 CW |
10199 | |
10200 | if (x < 0) { | |
9b4101be | 10201 | if (x + cursor_state->crtc_w <= 0) |
663f3122 | 10202 | on = false; |
cda4b7d3 CW |
10203 | |
10204 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10205 | x = -x; | |
10206 | } | |
10207 | pos |= x << CURSOR_X_SHIFT; | |
10208 | ||
10209 | if (y < 0) { | |
9b4101be | 10210 | if (y + cursor_state->crtc_h <= 0) |
663f3122 | 10211 | on = false; |
cda4b7d3 CW |
10212 | |
10213 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10214 | y = -y; | |
10215 | } | |
10216 | pos |= y << CURSOR_Y_SHIFT; | |
10217 | ||
5efb3e28 VS |
10218 | I915_WRITE(CURPOS(pipe), pos); |
10219 | ||
4398ad45 VS |
10220 | /* ILK+ do this automagically */ |
10221 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10222 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10223 | base += (cursor_state->crtc_h * |
10224 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10225 | } |
10226 | ||
8ac54669 | 10227 | if (IS_845G(dev) || IS_I865G(dev)) |
663f3122 | 10228 | i845_update_cursor(crtc, base, on); |
5efb3e28 | 10229 | else |
663f3122 | 10230 | i9xx_update_cursor(crtc, base, on); |
cda4b7d3 CW |
10231 | } |
10232 | ||
dc41c154 VS |
10233 | static bool cursor_size_ok(struct drm_device *dev, |
10234 | uint32_t width, uint32_t height) | |
10235 | { | |
10236 | if (width == 0 || height == 0) | |
10237 | return false; | |
10238 | ||
10239 | /* | |
10240 | * 845g/865g are special in that they are only limited by | |
10241 | * the width of their cursors, the height is arbitrary up to | |
10242 | * the precision of the register. Everything else requires | |
10243 | * square cursors, limited to a few power-of-two sizes. | |
10244 | */ | |
10245 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10246 | if ((width & 63) != 0) | |
10247 | return false; | |
10248 | ||
10249 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10250 | return false; | |
10251 | ||
10252 | if (height > 1023) | |
10253 | return false; | |
10254 | } else { | |
10255 | switch (width | height) { | |
10256 | case 256: | |
10257 | case 128: | |
10258 | if (IS_GEN2(dev)) | |
10259 | return false; | |
10260 | case 64: | |
10261 | break; | |
10262 | default: | |
10263 | return false; | |
10264 | } | |
10265 | } | |
10266 | ||
10267 | return true; | |
10268 | } | |
10269 | ||
79e53945 | 10270 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10271 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10272 | { |
7203425a | 10273 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10274 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10275 | |
7203425a | 10276 | for (i = start; i < end; i++) { |
79e53945 JB |
10277 | intel_crtc->lut_r[i] = red[i] >> 8; |
10278 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10279 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10280 | } | |
10281 | ||
10282 | intel_crtc_load_lut(crtc); | |
10283 | } | |
10284 | ||
79e53945 JB |
10285 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10286 | static struct drm_display_mode load_detect_mode = { | |
10287 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10288 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10289 | }; | |
10290 | ||
a8bb6818 DV |
10291 | struct drm_framebuffer * |
10292 | __intel_framebuffer_create(struct drm_device *dev, | |
10293 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10294 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10295 | { |
10296 | struct intel_framebuffer *intel_fb; | |
10297 | int ret; | |
10298 | ||
10299 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10300 | if (!intel_fb) |
d2dff872 | 10301 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10302 | |
10303 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10304 | if (ret) |
10305 | goto err; | |
d2dff872 CW |
10306 | |
10307 | return &intel_fb->base; | |
dcb1394e | 10308 | |
dd4916c5 | 10309 | err: |
dd4916c5 | 10310 | kfree(intel_fb); |
dd4916c5 | 10311 | return ERR_PTR(ret); |
d2dff872 CW |
10312 | } |
10313 | ||
b5ea642a | 10314 | static struct drm_framebuffer * |
a8bb6818 DV |
10315 | intel_framebuffer_create(struct drm_device *dev, |
10316 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10317 | struct drm_i915_gem_object *obj) | |
10318 | { | |
10319 | struct drm_framebuffer *fb; | |
10320 | int ret; | |
10321 | ||
10322 | ret = i915_mutex_lock_interruptible(dev); | |
10323 | if (ret) | |
10324 | return ERR_PTR(ret); | |
10325 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10326 | mutex_unlock(&dev->struct_mutex); | |
10327 | ||
10328 | return fb; | |
10329 | } | |
10330 | ||
d2dff872 CW |
10331 | static u32 |
10332 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10333 | { | |
10334 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10335 | return ALIGN(pitch, 64); | |
10336 | } | |
10337 | ||
10338 | static u32 | |
10339 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10340 | { | |
10341 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10342 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10343 | } |
10344 | ||
10345 | static struct drm_framebuffer * | |
10346 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10347 | struct drm_display_mode *mode, | |
10348 | int depth, int bpp) | |
10349 | { | |
dcb1394e | 10350 | struct drm_framebuffer *fb; |
d2dff872 | 10351 | struct drm_i915_gem_object *obj; |
0fed39bd | 10352 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10353 | |
10354 | obj = i915_gem_alloc_object(dev, | |
10355 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10356 | if (obj == NULL) | |
10357 | return ERR_PTR(-ENOMEM); | |
10358 | ||
10359 | mode_cmd.width = mode->hdisplay; | |
10360 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10361 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10362 | bpp); | |
5ca0c34a | 10363 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10364 | |
dcb1394e LW |
10365 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10366 | if (IS_ERR(fb)) | |
10367 | drm_gem_object_unreference_unlocked(&obj->base); | |
10368 | ||
10369 | return fb; | |
d2dff872 CW |
10370 | } |
10371 | ||
10372 | static struct drm_framebuffer * | |
10373 | mode_fits_in_fbdev(struct drm_device *dev, | |
10374 | struct drm_display_mode *mode) | |
10375 | { | |
0695726e | 10376 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10377 | struct drm_i915_private *dev_priv = dev->dev_private; |
10378 | struct drm_i915_gem_object *obj; | |
10379 | struct drm_framebuffer *fb; | |
10380 | ||
4c0e5528 | 10381 | if (!dev_priv->fbdev) |
d2dff872 CW |
10382 | return NULL; |
10383 | ||
4c0e5528 | 10384 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10385 | return NULL; |
10386 | ||
4c0e5528 DV |
10387 | obj = dev_priv->fbdev->fb->obj; |
10388 | BUG_ON(!obj); | |
10389 | ||
8bcd4553 | 10390 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10391 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10392 | fb->bits_per_pixel)) | |
d2dff872 CW |
10393 | return NULL; |
10394 | ||
01f2c773 | 10395 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10396 | return NULL; |
10397 | ||
10398 | return fb; | |
4520f53a DV |
10399 | #else |
10400 | return NULL; | |
10401 | #endif | |
d2dff872 CW |
10402 | } |
10403 | ||
d3a40d1b ACO |
10404 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10405 | struct drm_crtc *crtc, | |
10406 | struct drm_display_mode *mode, | |
10407 | struct drm_framebuffer *fb, | |
10408 | int x, int y) | |
10409 | { | |
10410 | struct drm_plane_state *plane_state; | |
10411 | int hdisplay, vdisplay; | |
10412 | int ret; | |
10413 | ||
10414 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10415 | if (IS_ERR(plane_state)) | |
10416 | return PTR_ERR(plane_state); | |
10417 | ||
10418 | if (mode) | |
10419 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10420 | else | |
10421 | hdisplay = vdisplay = 0; | |
10422 | ||
10423 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10424 | if (ret) | |
10425 | return ret; | |
10426 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10427 | plane_state->crtc_x = 0; | |
10428 | plane_state->crtc_y = 0; | |
10429 | plane_state->crtc_w = hdisplay; | |
10430 | plane_state->crtc_h = vdisplay; | |
10431 | plane_state->src_x = x << 16; | |
10432 | plane_state->src_y = y << 16; | |
10433 | plane_state->src_w = hdisplay << 16; | |
10434 | plane_state->src_h = vdisplay << 16; | |
10435 | ||
10436 | return 0; | |
10437 | } | |
10438 | ||
d2434ab7 | 10439 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10440 | struct drm_display_mode *mode, |
51fd371b RC |
10441 | struct intel_load_detect_pipe *old, |
10442 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10443 | { |
10444 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10445 | struct intel_encoder *intel_encoder = |
10446 | intel_attached_encoder(connector); | |
79e53945 | 10447 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10448 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10449 | struct drm_crtc *crtc = NULL; |
10450 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10451 | struct drm_framebuffer *fb; |
51fd371b | 10452 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10453 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10454 | struct drm_connector_state *connector_state; |
4be07317 | 10455 | struct intel_crtc_state *crtc_state; |
51fd371b | 10456 | int ret, i = -1; |
79e53945 | 10457 | |
d2dff872 | 10458 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10459 | connector->base.id, connector->name, |
8e329a03 | 10460 | encoder->base.id, encoder->name); |
d2dff872 | 10461 | |
51fd371b RC |
10462 | retry: |
10463 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10464 | if (ret) | |
ad3c558f | 10465 | goto fail; |
6e9f798d | 10466 | |
79e53945 JB |
10467 | /* |
10468 | * Algorithm gets a little messy: | |
7a5e4805 | 10469 | * |
79e53945 JB |
10470 | * - if the connector already has an assigned crtc, use it (but make |
10471 | * sure it's on first) | |
7a5e4805 | 10472 | * |
79e53945 JB |
10473 | * - try to find the first unused crtc that can drive this connector, |
10474 | * and use that if we find one | |
79e53945 JB |
10475 | */ |
10476 | ||
10477 | /* See if we already have a CRTC for this connector */ | |
10478 | if (encoder->crtc) { | |
10479 | crtc = encoder->crtc; | |
8261b191 | 10480 | |
51fd371b | 10481 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10482 | if (ret) |
ad3c558f | 10483 | goto fail; |
4d02e2de | 10484 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10485 | if (ret) |
ad3c558f | 10486 | goto fail; |
7b24056b | 10487 | |
24218aac | 10488 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10489 | old->load_detect_temp = false; |
10490 | ||
10491 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10492 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10493 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10494 | |
7173188d | 10495 | return true; |
79e53945 JB |
10496 | } |
10497 | ||
10498 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10499 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10500 | i++; |
10501 | if (!(encoder->possible_crtcs & (1 << i))) | |
10502 | continue; | |
83d65738 | 10503 | if (possible_crtc->state->enable) |
a459249c | 10504 | continue; |
a459249c VS |
10505 | |
10506 | crtc = possible_crtc; | |
10507 | break; | |
79e53945 JB |
10508 | } |
10509 | ||
10510 | /* | |
10511 | * If we didn't find an unused CRTC, don't use any. | |
10512 | */ | |
10513 | if (!crtc) { | |
7173188d | 10514 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10515 | goto fail; |
79e53945 JB |
10516 | } |
10517 | ||
51fd371b RC |
10518 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10519 | if (ret) | |
ad3c558f | 10520 | goto fail; |
4d02e2de DV |
10521 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10522 | if (ret) | |
ad3c558f | 10523 | goto fail; |
79e53945 JB |
10524 | |
10525 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10526 | old->dpms_mode = connector->dpms; |
8261b191 | 10527 | old->load_detect_temp = true; |
d2dff872 | 10528 | old->release_fb = NULL; |
79e53945 | 10529 | |
83a57153 ACO |
10530 | state = drm_atomic_state_alloc(dev); |
10531 | if (!state) | |
10532 | return false; | |
10533 | ||
10534 | state->acquire_ctx = ctx; | |
10535 | ||
944b0c76 ACO |
10536 | connector_state = drm_atomic_get_connector_state(state, connector); |
10537 | if (IS_ERR(connector_state)) { | |
10538 | ret = PTR_ERR(connector_state); | |
10539 | goto fail; | |
10540 | } | |
10541 | ||
10542 | connector_state->crtc = crtc; | |
10543 | connector_state->best_encoder = &intel_encoder->base; | |
10544 | ||
4be07317 ACO |
10545 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10546 | if (IS_ERR(crtc_state)) { | |
10547 | ret = PTR_ERR(crtc_state); | |
10548 | goto fail; | |
10549 | } | |
10550 | ||
49d6fa21 | 10551 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10552 | |
6492711d CW |
10553 | if (!mode) |
10554 | mode = &load_detect_mode; | |
79e53945 | 10555 | |
d2dff872 CW |
10556 | /* We need a framebuffer large enough to accommodate all accesses |
10557 | * that the plane may generate whilst we perform load detection. | |
10558 | * We can not rely on the fbcon either being present (we get called | |
10559 | * during its initialisation to detect all boot displays, or it may | |
10560 | * not even exist) or that it is large enough to satisfy the | |
10561 | * requested mode. | |
10562 | */ | |
94352cf9 DV |
10563 | fb = mode_fits_in_fbdev(dev, mode); |
10564 | if (fb == NULL) { | |
d2dff872 | 10565 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10566 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10567 | old->release_fb = fb; | |
d2dff872 CW |
10568 | } else |
10569 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10570 | if (IS_ERR(fb)) { |
d2dff872 | 10571 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10572 | goto fail; |
79e53945 | 10573 | } |
79e53945 | 10574 | |
d3a40d1b ACO |
10575 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10576 | if (ret) | |
10577 | goto fail; | |
10578 | ||
8c7b5ccb ACO |
10579 | drm_mode_copy(&crtc_state->base.mode, mode); |
10580 | ||
74c090b1 | 10581 | if (drm_atomic_commit(state)) { |
6492711d | 10582 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10583 | if (old->release_fb) |
10584 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10585 | goto fail; |
79e53945 | 10586 | } |
9128b040 | 10587 | crtc->primary->crtc = crtc; |
7173188d | 10588 | |
79e53945 | 10589 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10590 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10591 | return true; |
412b61d8 | 10592 | |
ad3c558f | 10593 | fail: |
e5d958ef ACO |
10594 | drm_atomic_state_free(state); |
10595 | state = NULL; | |
83a57153 | 10596 | |
51fd371b RC |
10597 | if (ret == -EDEADLK) { |
10598 | drm_modeset_backoff(ctx); | |
10599 | goto retry; | |
10600 | } | |
10601 | ||
412b61d8 | 10602 | return false; |
79e53945 JB |
10603 | } |
10604 | ||
d2434ab7 | 10605 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10606 | struct intel_load_detect_pipe *old, |
10607 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10608 | { |
83a57153 | 10609 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10610 | struct intel_encoder *intel_encoder = |
10611 | intel_attached_encoder(connector); | |
4ef69c7a | 10612 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10613 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10615 | struct drm_atomic_state *state; |
944b0c76 | 10616 | struct drm_connector_state *connector_state; |
4be07317 | 10617 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10618 | int ret; |
79e53945 | 10619 | |
d2dff872 | 10620 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10621 | connector->base.id, connector->name, |
8e329a03 | 10622 | encoder->base.id, encoder->name); |
d2dff872 | 10623 | |
8261b191 | 10624 | if (old->load_detect_temp) { |
83a57153 | 10625 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10626 | if (!state) |
10627 | goto fail; | |
83a57153 ACO |
10628 | |
10629 | state->acquire_ctx = ctx; | |
10630 | ||
944b0c76 ACO |
10631 | connector_state = drm_atomic_get_connector_state(state, connector); |
10632 | if (IS_ERR(connector_state)) | |
10633 | goto fail; | |
10634 | ||
4be07317 ACO |
10635 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10636 | if (IS_ERR(crtc_state)) | |
10637 | goto fail; | |
10638 | ||
944b0c76 ACO |
10639 | connector_state->best_encoder = NULL; |
10640 | connector_state->crtc = NULL; | |
10641 | ||
49d6fa21 | 10642 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10643 | |
d3a40d1b ACO |
10644 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10645 | 0, 0); | |
10646 | if (ret) | |
10647 | goto fail; | |
10648 | ||
74c090b1 | 10649 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10650 | if (ret) |
10651 | goto fail; | |
d2dff872 | 10652 | |
36206361 DV |
10653 | if (old->release_fb) { |
10654 | drm_framebuffer_unregister_private(old->release_fb); | |
10655 | drm_framebuffer_unreference(old->release_fb); | |
10656 | } | |
d2dff872 | 10657 | |
0622a53c | 10658 | return; |
79e53945 JB |
10659 | } |
10660 | ||
c751ce4f | 10661 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10662 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10663 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10664 | |
10665 | return; | |
10666 | fail: | |
10667 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10668 | drm_atomic_state_free(state); | |
79e53945 JB |
10669 | } |
10670 | ||
da4a1efa | 10671 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10672 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10673 | { |
10674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10675 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10676 | ||
10677 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10678 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10679 | else if (HAS_PCH_SPLIT(dev)) |
10680 | return 120000; | |
10681 | else if (!IS_GEN2(dev)) | |
10682 | return 96000; | |
10683 | else | |
10684 | return 48000; | |
10685 | } | |
10686 | ||
79e53945 | 10687 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10688 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10689 | struct intel_crtc_state *pipe_config) |
79e53945 | 10690 | { |
f1f644dc | 10691 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10692 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10693 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10694 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10695 | u32 fp; |
10696 | intel_clock_t clock; | |
dccbea3b | 10697 | int port_clock; |
da4a1efa | 10698 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10699 | |
10700 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10701 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10702 | else |
293623f7 | 10703 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10704 | |
10705 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10706 | if (IS_PINEVIEW(dev)) { |
10707 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10708 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10709 | } else { |
10710 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10711 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10712 | } | |
10713 | ||
a6c45cf0 | 10714 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10715 | if (IS_PINEVIEW(dev)) |
10716 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10717 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10718 | else |
10719 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10720 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10721 | ||
10722 | switch (dpll & DPLL_MODE_MASK) { | |
10723 | case DPLLB_MODE_DAC_SERIAL: | |
10724 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10725 | 5 : 10; | |
10726 | break; | |
10727 | case DPLLB_MODE_LVDS: | |
10728 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10729 | 7 : 14; | |
10730 | break; | |
10731 | default: | |
28c97730 | 10732 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10733 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10734 | return; |
79e53945 JB |
10735 | } |
10736 | ||
ac58c3f0 | 10737 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10738 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10739 | else |
dccbea3b | 10740 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10741 | } else { |
0fb58223 | 10742 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10743 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10744 | |
10745 | if (is_lvds) { | |
10746 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10747 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10748 | |
10749 | if (lvds & LVDS_CLKB_POWER_UP) | |
10750 | clock.p2 = 7; | |
10751 | else | |
10752 | clock.p2 = 14; | |
79e53945 JB |
10753 | } else { |
10754 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10755 | clock.p1 = 2; | |
10756 | else { | |
10757 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10758 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10759 | } | |
10760 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10761 | clock.p2 = 4; | |
10762 | else | |
10763 | clock.p2 = 2; | |
79e53945 | 10764 | } |
da4a1efa | 10765 | |
dccbea3b | 10766 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10767 | } |
10768 | ||
18442d08 VS |
10769 | /* |
10770 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10771 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10772 | * encoder's get_config() function. |
10773 | */ | |
dccbea3b | 10774 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10775 | } |
10776 | ||
6878da05 VS |
10777 | int intel_dotclock_calculate(int link_freq, |
10778 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10779 | { |
f1f644dc JB |
10780 | /* |
10781 | * The calculation for the data clock is: | |
1041a02f | 10782 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10783 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10784 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10785 | * |
10786 | * and the link clock is simpler: | |
1041a02f | 10787 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10788 | */ |
10789 | ||
6878da05 VS |
10790 | if (!m_n->link_n) |
10791 | return 0; | |
f1f644dc | 10792 | |
6878da05 VS |
10793 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10794 | } | |
f1f644dc | 10795 | |
18442d08 | 10796 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10797 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10798 | { |
10799 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10800 | |
18442d08 VS |
10801 | /* read out port_clock from the DPLL */ |
10802 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10803 | |
f1f644dc | 10804 | /* |
18442d08 | 10805 | * This value does not include pixel_multiplier. |
241bfc38 | 10806 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10807 | * agree once we know their relationship in the encoder's |
10808 | * get_config() function. | |
79e53945 | 10809 | */ |
2d112de7 | 10810 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10811 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10812 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10813 | } |
10814 | ||
10815 | /** Returns the currently programmed mode of the given pipe. */ | |
10816 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10817 | struct drm_crtc *crtc) | |
10818 | { | |
548f245b | 10819 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10821 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10822 | struct drm_display_mode *mode; |
5cec258b | 10823 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10824 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10825 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10826 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10827 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10828 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10829 | |
10830 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10831 | if (!mode) | |
10832 | return NULL; | |
10833 | ||
f1f644dc JB |
10834 | /* |
10835 | * Construct a pipe_config sufficient for getting the clock info | |
10836 | * back out of crtc_clock_get. | |
10837 | * | |
10838 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10839 | * to use a real value here instead. | |
10840 | */ | |
293623f7 | 10841 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10842 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10843 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10844 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10845 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10846 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10847 | ||
773ae034 | 10848 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10849 | mode->hdisplay = (htot & 0xffff) + 1; |
10850 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10851 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10852 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10853 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10854 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10855 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10856 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10857 | ||
10858 | drm_mode_set_name(mode); | |
79e53945 JB |
10859 | |
10860 | return mode; | |
10861 | } | |
10862 | ||
f047e395 CW |
10863 | void intel_mark_busy(struct drm_device *dev) |
10864 | { | |
c67a470b PZ |
10865 | struct drm_i915_private *dev_priv = dev->dev_private; |
10866 | ||
f62a0076 CW |
10867 | if (dev_priv->mm.busy) |
10868 | return; | |
10869 | ||
43694d69 | 10870 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10871 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10872 | if (INTEL_INFO(dev)->gen >= 6) |
10873 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10874 | dev_priv->mm.busy = true; |
f047e395 CW |
10875 | } |
10876 | ||
10877 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10878 | { |
c67a470b | 10879 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10880 | |
f62a0076 CW |
10881 | if (!dev_priv->mm.busy) |
10882 | return; | |
10883 | ||
10884 | dev_priv->mm.busy = false; | |
10885 | ||
3d13ef2e | 10886 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10887 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10888 | |
43694d69 | 10889 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10890 | } |
10891 | ||
79e53945 JB |
10892 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10893 | { | |
10894 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10895 | struct drm_device *dev = crtc->dev; |
10896 | struct intel_unpin_work *work; | |
67e77c5a | 10897 | |
5e2d7afc | 10898 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10899 | work = intel_crtc->unpin_work; |
10900 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10901 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10902 | |
10903 | if (work) { | |
10904 | cancel_work_sync(&work->work); | |
10905 | kfree(work); | |
10906 | } | |
79e53945 JB |
10907 | |
10908 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10909 | |
79e53945 JB |
10910 | kfree(intel_crtc); |
10911 | } | |
10912 | ||
6b95a207 KH |
10913 | static void intel_unpin_work_fn(struct work_struct *__work) |
10914 | { | |
10915 | struct intel_unpin_work *work = | |
10916 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10917 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10918 | struct drm_device *dev = crtc->base.dev; | |
10919 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10920 | |
b4a98e57 | 10921 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10922 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10923 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10924 | |
f06cc1b9 | 10925 | if (work->flip_queued_req) |
146d84f0 | 10926 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10927 | mutex_unlock(&dev->struct_mutex); |
10928 | ||
a9ff8714 | 10929 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10930 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10931 | |
a9ff8714 VS |
10932 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10933 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10934 | |
6b95a207 KH |
10935 | kfree(work); |
10936 | } | |
10937 | ||
1afe3e9d | 10938 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10939 | struct drm_crtc *crtc) |
6b95a207 | 10940 | { |
6b95a207 KH |
10941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10942 | struct intel_unpin_work *work; | |
6b95a207 KH |
10943 | unsigned long flags; |
10944 | ||
10945 | /* Ignore early vblank irqs */ | |
10946 | if (intel_crtc == NULL) | |
10947 | return; | |
10948 | ||
f326038a DV |
10949 | /* |
10950 | * This is called both by irq handlers and the reset code (to complete | |
10951 | * lost pageflips) so needs the full irqsave spinlocks. | |
10952 | */ | |
6b95a207 KH |
10953 | spin_lock_irqsave(&dev->event_lock, flags); |
10954 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10955 | |
10956 | /* Ensure we don't miss a work->pending update ... */ | |
10957 | smp_rmb(); | |
10958 | ||
10959 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10960 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10961 | return; | |
10962 | } | |
10963 | ||
d6bbafa1 | 10964 | page_flip_completed(intel_crtc); |
0af7e4df | 10965 | |
6b95a207 | 10966 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10967 | } |
10968 | ||
1afe3e9d JB |
10969 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10970 | { | |
fbee40df | 10971 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10972 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10973 | ||
49b14a5c | 10974 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10975 | } |
10976 | ||
10977 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10978 | { | |
fbee40df | 10979 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10980 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10981 | ||
49b14a5c | 10982 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10983 | } |
10984 | ||
75f7f3ec VS |
10985 | /* Is 'a' after or equal to 'b'? */ |
10986 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10987 | { | |
10988 | return !((a - b) & 0x80000000); | |
10989 | } | |
10990 | ||
10991 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10992 | { | |
10993 | struct drm_device *dev = crtc->base.dev; | |
10994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10995 | ||
bdfa7542 VS |
10996 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10997 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10998 | return true; | |
10999 | ||
75f7f3ec VS |
11000 | /* |
11001 | * The relevant registers doen't exist on pre-ctg. | |
11002 | * As the flip done interrupt doesn't trigger for mmio | |
11003 | * flips on gmch platforms, a flip count check isn't | |
11004 | * really needed there. But since ctg has the registers, | |
11005 | * include it in the check anyway. | |
11006 | */ | |
11007 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11008 | return true; | |
11009 | ||
11010 | /* | |
11011 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11012 | * used the same base address. In that case the mmio flip might | |
11013 | * have completed, but the CS hasn't even executed the flip yet. | |
11014 | * | |
11015 | * A flip count check isn't enough as the CS might have updated | |
11016 | * the base address just after start of vblank, but before we | |
11017 | * managed to process the interrupt. This means we'd complete the | |
11018 | * CS flip too soon. | |
11019 | * | |
11020 | * Combining both checks should get us a good enough result. It may | |
11021 | * still happen that the CS flip has been executed, but has not | |
11022 | * yet actually completed. But in case the base address is the same | |
11023 | * anyway, we don't really care. | |
11024 | */ | |
11025 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11026 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11027 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11028 | crtc->unpin_work->flip_count); |
11029 | } | |
11030 | ||
6b95a207 KH |
11031 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11032 | { | |
fbee40df | 11033 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11034 | struct intel_crtc *intel_crtc = |
11035 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11036 | unsigned long flags; | |
11037 | ||
f326038a DV |
11038 | |
11039 | /* | |
11040 | * This is called both by irq handlers and the reset code (to complete | |
11041 | * lost pageflips) so needs the full irqsave spinlocks. | |
11042 | * | |
11043 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11044 | * generate a page-flip completion irq, i.e. every modeset |
11045 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11046 | */ | |
6b95a207 | 11047 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11048 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11049 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11050 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11051 | } | |
11052 | ||
6042639c | 11053 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11054 | { |
11055 | /* Ensure that the work item is consistent when activating it ... */ | |
11056 | smp_wmb(); | |
6042639c | 11057 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11058 | /* and that it is marked active as soon as the irq could fire. */ |
11059 | smp_wmb(); | |
11060 | } | |
11061 | ||
8c9f3aaf JB |
11062 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11063 | struct drm_crtc *crtc, | |
11064 | struct drm_framebuffer *fb, | |
ed8d1975 | 11065 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11066 | struct drm_i915_gem_request *req, |
ed8d1975 | 11067 | uint32_t flags) |
8c9f3aaf | 11068 | { |
6258fbe2 | 11069 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11071 | u32 flip_mask; |
11072 | int ret; | |
11073 | ||
5fb9de1a | 11074 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11075 | if (ret) |
4fa62c89 | 11076 | return ret; |
8c9f3aaf JB |
11077 | |
11078 | /* Can't queue multiple flips, so wait for the previous | |
11079 | * one to finish before executing the next. | |
11080 | */ | |
11081 | if (intel_crtc->plane) | |
11082 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11083 | else | |
11084 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11085 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11086 | intel_ring_emit(ring, MI_NOOP); | |
11087 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11088 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11089 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11090 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11091 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11092 | |
6042639c | 11093 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11094 | return 0; |
8c9f3aaf JB |
11095 | } |
11096 | ||
11097 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11098 | struct drm_crtc *crtc, | |
11099 | struct drm_framebuffer *fb, | |
ed8d1975 | 11100 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11101 | struct drm_i915_gem_request *req, |
ed8d1975 | 11102 | uint32_t flags) |
8c9f3aaf | 11103 | { |
6258fbe2 | 11104 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11105 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11106 | u32 flip_mask; |
11107 | int ret; | |
11108 | ||
5fb9de1a | 11109 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11110 | if (ret) |
4fa62c89 | 11111 | return ret; |
8c9f3aaf JB |
11112 | |
11113 | if (intel_crtc->plane) | |
11114 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11115 | else | |
11116 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11117 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11118 | intel_ring_emit(ring, MI_NOOP); | |
11119 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11120 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11121 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11122 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11123 | intel_ring_emit(ring, MI_NOOP); |
11124 | ||
6042639c | 11125 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11126 | return 0; |
8c9f3aaf JB |
11127 | } |
11128 | ||
11129 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11130 | struct drm_crtc *crtc, | |
11131 | struct drm_framebuffer *fb, | |
ed8d1975 | 11132 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11133 | struct drm_i915_gem_request *req, |
ed8d1975 | 11134 | uint32_t flags) |
8c9f3aaf | 11135 | { |
6258fbe2 | 11136 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11137 | struct drm_i915_private *dev_priv = dev->dev_private; |
11138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11139 | uint32_t pf, pipesrc; | |
11140 | int ret; | |
11141 | ||
5fb9de1a | 11142 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11143 | if (ret) |
4fa62c89 | 11144 | return ret; |
8c9f3aaf JB |
11145 | |
11146 | /* i965+ uses the linear or tiled offsets from the | |
11147 | * Display Registers (which do not change across a page-flip) | |
11148 | * so we need only reprogram the base address. | |
11149 | */ | |
6d90c952 DV |
11150 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11151 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11152 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11153 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11154 | obj->tiling_mode); |
8c9f3aaf JB |
11155 | |
11156 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11157 | * untested on non-native modes, so ignore it for now. | |
11158 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11159 | */ | |
11160 | pf = 0; | |
11161 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11162 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11163 | |
6042639c | 11164 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11165 | return 0; |
8c9f3aaf JB |
11166 | } |
11167 | ||
11168 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11169 | struct drm_crtc *crtc, | |
11170 | struct drm_framebuffer *fb, | |
ed8d1975 | 11171 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11172 | struct drm_i915_gem_request *req, |
ed8d1975 | 11173 | uint32_t flags) |
8c9f3aaf | 11174 | { |
6258fbe2 | 11175 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11176 | struct drm_i915_private *dev_priv = dev->dev_private; |
11177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11178 | uint32_t pf, pipesrc; | |
11179 | int ret; | |
11180 | ||
5fb9de1a | 11181 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11182 | if (ret) |
4fa62c89 | 11183 | return ret; |
8c9f3aaf | 11184 | |
6d90c952 DV |
11185 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11186 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11187 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11188 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11189 | |
dc257cf1 DV |
11190 | /* Contrary to the suggestions in the documentation, |
11191 | * "Enable Panel Fitter" does not seem to be required when page | |
11192 | * flipping with a non-native mode, and worse causes a normal | |
11193 | * modeset to fail. | |
11194 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11195 | */ | |
11196 | pf = 0; | |
8c9f3aaf | 11197 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11198 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11199 | |
6042639c | 11200 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11201 | return 0; |
8c9f3aaf JB |
11202 | } |
11203 | ||
7c9017e5 JB |
11204 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11205 | struct drm_crtc *crtc, | |
11206 | struct drm_framebuffer *fb, | |
ed8d1975 | 11207 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11208 | struct drm_i915_gem_request *req, |
ed8d1975 | 11209 | uint32_t flags) |
7c9017e5 | 11210 | { |
6258fbe2 | 11211 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11212 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11213 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11214 | int len, ret; |
11215 | ||
eba905b2 | 11216 | switch (intel_crtc->plane) { |
cb05d8de DV |
11217 | case PLANE_A: |
11218 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11219 | break; | |
11220 | case PLANE_B: | |
11221 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11222 | break; | |
11223 | case PLANE_C: | |
11224 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11225 | break; | |
11226 | default: | |
11227 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11228 | return -ENODEV; |
cb05d8de DV |
11229 | } |
11230 | ||
ffe74d75 | 11231 | len = 4; |
f476828a | 11232 | if (ring->id == RCS) { |
ffe74d75 | 11233 | len += 6; |
f476828a DL |
11234 | /* |
11235 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11236 | * 48bits addresses, and we need a NOOP for the batch size to | |
11237 | * stay even. | |
11238 | */ | |
11239 | if (IS_GEN8(dev)) | |
11240 | len += 2; | |
11241 | } | |
ffe74d75 | 11242 | |
f66fab8e VS |
11243 | /* |
11244 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11245 | * "The full packet must be contained within the same cache line." | |
11246 | * | |
11247 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11248 | * cacheline, if we ever start emitting more commands before | |
11249 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11250 | * then do the cacheline alignment, and finally emit the | |
11251 | * MI_DISPLAY_FLIP. | |
11252 | */ | |
bba09b12 | 11253 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11254 | if (ret) |
4fa62c89 | 11255 | return ret; |
f66fab8e | 11256 | |
5fb9de1a | 11257 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11258 | if (ret) |
4fa62c89 | 11259 | return ret; |
7c9017e5 | 11260 | |
ffe74d75 CW |
11261 | /* Unmask the flip-done completion message. Note that the bspec says that |
11262 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11263 | * more than one flip event at any time (or ensure that one flip message | |
11264 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11265 | * Experimentation says that BCS works despite DERRMR masking all | |
11266 | * flip-done completion events and that unmasking all planes at once | |
11267 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11268 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11269 | */ | |
11270 | if (ring->id == RCS) { | |
11271 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11272 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11273 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11274 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11275 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11276 | if (IS_GEN8(dev)) |
f1afe24f | 11277 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11278 | MI_SRM_LRM_GLOBAL_GTT); |
11279 | else | |
f1afe24f | 11280 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11281 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11282 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11283 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11284 | if (IS_GEN8(dev)) { |
11285 | intel_ring_emit(ring, 0); | |
11286 | intel_ring_emit(ring, MI_NOOP); | |
11287 | } | |
ffe74d75 CW |
11288 | } |
11289 | ||
cb05d8de | 11290 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11291 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11292 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11293 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11294 | |
6042639c | 11295 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11296 | return 0; |
7c9017e5 JB |
11297 | } |
11298 | ||
84c33a64 SG |
11299 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11300 | struct drm_i915_gem_object *obj) | |
11301 | { | |
11302 | /* | |
11303 | * This is not being used for older platforms, because | |
11304 | * non-availability of flip done interrupt forces us to use | |
11305 | * CS flips. Older platforms derive flip done using some clever | |
11306 | * tricks involving the flip_pending status bits and vblank irqs. | |
11307 | * So using MMIO flips there would disrupt this mechanism. | |
11308 | */ | |
11309 | ||
8e09bf83 CW |
11310 | if (ring == NULL) |
11311 | return true; | |
11312 | ||
84c33a64 SG |
11313 | if (INTEL_INFO(ring->dev)->gen < 5) |
11314 | return false; | |
11315 | ||
11316 | if (i915.use_mmio_flip < 0) | |
11317 | return false; | |
11318 | else if (i915.use_mmio_flip > 0) | |
11319 | return true; | |
14bf993e OM |
11320 | else if (i915.enable_execlists) |
11321 | return true; | |
fd8e058a AG |
11322 | else if (obj->base.dma_buf && |
11323 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11324 | false)) | |
11325 | return true; | |
84c33a64 | 11326 | else |
b4716185 | 11327 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11328 | } |
11329 | ||
6042639c | 11330 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11331 | unsigned int rotation, |
6042639c | 11332 | struct intel_unpin_work *work) |
ff944564 DL |
11333 | { |
11334 | struct drm_device *dev = intel_crtc->base.dev; | |
11335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11336 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11337 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11338 | u32 ctl, stride, tile_height; |
ff944564 DL |
11339 | |
11340 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11341 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11342 | switch (fb->modifier[0]) { |
11343 | case DRM_FORMAT_MOD_NONE: | |
11344 | break; | |
11345 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11346 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11347 | break; |
11348 | case I915_FORMAT_MOD_Y_TILED: | |
11349 | ctl |= PLANE_CTL_TILED_Y; | |
11350 | break; | |
11351 | case I915_FORMAT_MOD_Yf_TILED: | |
11352 | ctl |= PLANE_CTL_TILED_YF; | |
11353 | break; | |
11354 | default: | |
11355 | MISSING_CASE(fb->modifier[0]); | |
11356 | } | |
ff944564 DL |
11357 | |
11358 | /* | |
11359 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11360 | * linear buffers or in number of tiles for tiled buffers. | |
11361 | */ | |
86efe24a TU |
11362 | if (intel_rotation_90_or_270(rotation)) { |
11363 | /* stride = Surface height in tiles */ | |
11364 | tile_height = intel_tile_height(dev, fb->pixel_format, | |
11365 | fb->modifier[0], 0); | |
11366 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11367 | } else { | |
11368 | stride = fb->pitches[0] / | |
11369 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11370 | fb->pixel_format); | |
11371 | } | |
ff944564 DL |
11372 | |
11373 | /* | |
11374 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11375 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11376 | */ | |
11377 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11378 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11379 | ||
6042639c | 11380 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11381 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11382 | } | |
11383 | ||
6042639c CW |
11384 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11385 | struct intel_unpin_work *work) | |
84c33a64 SG |
11386 | { |
11387 | struct drm_device *dev = intel_crtc->base.dev; | |
11388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11389 | struct intel_framebuffer *intel_fb = | |
11390 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11391 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11392 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11393 | u32 dspcntr; |
84c33a64 | 11394 | |
84c33a64 SG |
11395 | dspcntr = I915_READ(reg); |
11396 | ||
c5d97472 DL |
11397 | if (obj->tiling_mode != I915_TILING_NONE) |
11398 | dspcntr |= DISPPLANE_TILED; | |
11399 | else | |
11400 | dspcntr &= ~DISPPLANE_TILED; | |
11401 | ||
84c33a64 SG |
11402 | I915_WRITE(reg, dspcntr); |
11403 | ||
6042639c | 11404 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11405 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11406 | } |
11407 | ||
11408 | /* | |
11409 | * XXX: This is the temporary way to update the plane registers until we get | |
11410 | * around to using the usual plane update functions for MMIO flips | |
11411 | */ | |
6042639c | 11412 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11413 | { |
6042639c CW |
11414 | struct intel_crtc *crtc = mmio_flip->crtc; |
11415 | struct intel_unpin_work *work; | |
11416 | ||
11417 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11418 | work = crtc->unpin_work; | |
11419 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11420 | if (work == NULL) | |
11421 | return; | |
ff944564 | 11422 | |
6042639c | 11423 | intel_mark_page_flip_active(work); |
ff944564 | 11424 | |
6042639c | 11425 | intel_pipe_update_start(crtc); |
ff944564 | 11426 | |
6042639c | 11427 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11428 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11429 | else |
11430 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11431 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11432 | |
6042639c | 11433 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11434 | } |
11435 | ||
9362c7c5 | 11436 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11437 | { |
b2cfe0ab CW |
11438 | struct intel_mmio_flip *mmio_flip = |
11439 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11440 | struct intel_framebuffer *intel_fb = |
11441 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11442 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11443 | |
6042639c | 11444 | if (mmio_flip->req) { |
eed29a5b | 11445 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11446 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11447 | false, NULL, |
11448 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11449 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11450 | } | |
84c33a64 | 11451 | |
fd8e058a AG |
11452 | /* For framebuffer backed by dmabuf, wait for fence */ |
11453 | if (obj->base.dma_buf) | |
11454 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11455 | false, false, | |
11456 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11457 | ||
6042639c | 11458 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11459 | kfree(mmio_flip); |
84c33a64 SG |
11460 | } |
11461 | ||
11462 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11463 | struct drm_crtc *crtc, | |
86efe24a | 11464 | struct drm_i915_gem_object *obj) |
84c33a64 | 11465 | { |
b2cfe0ab CW |
11466 | struct intel_mmio_flip *mmio_flip; |
11467 | ||
11468 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11469 | if (mmio_flip == NULL) | |
11470 | return -ENOMEM; | |
84c33a64 | 11471 | |
bcafc4e3 | 11472 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11473 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11474 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11475 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11476 | |
b2cfe0ab CW |
11477 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11478 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11479 | |
84c33a64 SG |
11480 | return 0; |
11481 | } | |
11482 | ||
8c9f3aaf JB |
11483 | static int intel_default_queue_flip(struct drm_device *dev, |
11484 | struct drm_crtc *crtc, | |
11485 | struct drm_framebuffer *fb, | |
ed8d1975 | 11486 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11487 | struct drm_i915_gem_request *req, |
ed8d1975 | 11488 | uint32_t flags) |
8c9f3aaf JB |
11489 | { |
11490 | return -ENODEV; | |
11491 | } | |
11492 | ||
d6bbafa1 CW |
11493 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11494 | struct drm_crtc *crtc) | |
11495 | { | |
11496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11498 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11499 | u32 addr; | |
11500 | ||
11501 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11502 | return true; | |
11503 | ||
908565c2 CW |
11504 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11505 | return false; | |
11506 | ||
d6bbafa1 CW |
11507 | if (!work->enable_stall_check) |
11508 | return false; | |
11509 | ||
11510 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11511 | if (work->flip_queued_req && |
11512 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11513 | return false; |
11514 | ||
1e3feefd | 11515 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11516 | } |
11517 | ||
1e3feefd | 11518 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11519 | return false; |
11520 | ||
11521 | /* Potential stall - if we see that the flip has happened, | |
11522 | * assume a missed interrupt. */ | |
11523 | if (INTEL_INFO(dev)->gen >= 4) | |
11524 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11525 | else | |
11526 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11527 | ||
11528 | /* There is a potential issue here with a false positive after a flip | |
11529 | * to the same address. We could address this by checking for a | |
11530 | * non-incrementing frame counter. | |
11531 | */ | |
11532 | return addr == work->gtt_offset; | |
11533 | } | |
11534 | ||
11535 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11536 | { | |
11537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11538 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11540 | struct intel_unpin_work *work; |
f326038a | 11541 | |
6c51d46f | 11542 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11543 | |
11544 | if (crtc == NULL) | |
11545 | return; | |
11546 | ||
f326038a | 11547 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11548 | work = intel_crtc->unpin_work; |
11549 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11550 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11551 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11552 | page_flip_completed(intel_crtc); |
6ad790c0 | 11553 | work = NULL; |
d6bbafa1 | 11554 | } |
6ad790c0 CW |
11555 | if (work != NULL && |
11556 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11557 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11558 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11559 | } |
11560 | ||
6b95a207 KH |
11561 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11562 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11563 | struct drm_pending_vblank_event *event, |
11564 | uint32_t page_flip_flags) | |
6b95a207 KH |
11565 | { |
11566 | struct drm_device *dev = crtc->dev; | |
11567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11568 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11569 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11571 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11572 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11573 | struct intel_unpin_work *work; |
a4872ba6 | 11574 | struct intel_engine_cs *ring; |
cf5d8a46 | 11575 | bool mmio_flip; |
91af127f | 11576 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11577 | int ret; |
6b95a207 | 11578 | |
2ff8fde1 MR |
11579 | /* |
11580 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11581 | * check to be safe. In the future we may enable pageflipping from | |
11582 | * a disabled primary plane. | |
11583 | */ | |
11584 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11585 | return -EBUSY; | |
11586 | ||
e6a595d2 | 11587 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11588 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11589 | return -EINVAL; |
11590 | ||
11591 | /* | |
11592 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11593 | * Note that pitch changes could also affect these register. | |
11594 | */ | |
11595 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11596 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11597 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11598 | return -EINVAL; |
11599 | ||
f900db47 CW |
11600 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11601 | goto out_hang; | |
11602 | ||
b14c5679 | 11603 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11604 | if (work == NULL) |
11605 | return -ENOMEM; | |
11606 | ||
6b95a207 | 11607 | work->event = event; |
b4a98e57 | 11608 | work->crtc = crtc; |
ab8d6675 | 11609 | work->old_fb = old_fb; |
6b95a207 KH |
11610 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11611 | ||
87b6b101 | 11612 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11613 | if (ret) |
11614 | goto free_work; | |
11615 | ||
6b95a207 | 11616 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11617 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11618 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11619 | /* Before declaring the flip queue wedged, check if |
11620 | * the hardware completed the operation behind our backs. | |
11621 | */ | |
11622 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11623 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11624 | page_flip_completed(intel_crtc); | |
11625 | } else { | |
11626 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11627 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11628 | |
d6bbafa1 CW |
11629 | drm_crtc_vblank_put(crtc); |
11630 | kfree(work); | |
11631 | return -EBUSY; | |
11632 | } | |
6b95a207 KH |
11633 | } |
11634 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11635 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11636 | |
b4a98e57 CW |
11637 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11638 | flush_workqueue(dev_priv->wq); | |
11639 | ||
75dfca80 | 11640 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11641 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11642 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11643 | |
f4510a27 | 11644 | crtc->primary->fb = fb; |
afd65eb4 | 11645 | update_state_fb(crtc->primary); |
1ed1f968 | 11646 | |
e1f99ce6 | 11647 | work->pending_flip_obj = obj; |
e1f99ce6 | 11648 | |
89ed88ba CW |
11649 | ret = i915_mutex_lock_interruptible(dev); |
11650 | if (ret) | |
11651 | goto cleanup; | |
11652 | ||
b4a98e57 | 11653 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11654 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11655 | |
75f7f3ec | 11656 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11657 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11658 | |
666a4537 | 11659 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11660 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11661 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11662 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11663 | ring = NULL; | |
48bf5b2d | 11664 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11665 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11666 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11667 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11668 | if (ring == NULL || ring->id != RCS) |
11669 | ring = &dev_priv->ring[BCS]; | |
11670 | } else { | |
11671 | ring = &dev_priv->ring[RCS]; | |
11672 | } | |
11673 | ||
cf5d8a46 CW |
11674 | mmio_flip = use_mmio_flip(ring, obj); |
11675 | ||
11676 | /* When using CS flips, we want to emit semaphores between rings. | |
11677 | * However, when using mmio flips we will create a task to do the | |
11678 | * synchronisation, so all we want here is to pin the framebuffer | |
11679 | * into the display plane and skip any waits. | |
11680 | */ | |
7580d774 ML |
11681 | if (!mmio_flip) { |
11682 | ret = i915_gem_object_sync(obj, ring, &request); | |
11683 | if (ret) | |
11684 | goto cleanup_pending; | |
11685 | } | |
11686 | ||
82bc3b2d | 11687 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11688 | crtc->primary->state); |
8c9f3aaf JB |
11689 | if (ret) |
11690 | goto cleanup_pending; | |
6b95a207 | 11691 | |
dedf278c TU |
11692 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11693 | obj, 0); | |
11694 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11695 | |
cf5d8a46 | 11696 | if (mmio_flip) { |
86efe24a | 11697 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11698 | if (ret) |
11699 | goto cleanup_unpin; | |
11700 | ||
f06cc1b9 JH |
11701 | i915_gem_request_assign(&work->flip_queued_req, |
11702 | obj->last_write_req); | |
d6bbafa1 | 11703 | } else { |
6258fbe2 JH |
11704 | if (!request) { |
11705 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11706 | if (ret) | |
11707 | goto cleanup_unpin; | |
11708 | } | |
11709 | ||
11710 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11711 | page_flip_flags); |
11712 | if (ret) | |
11713 | goto cleanup_unpin; | |
11714 | ||
6258fbe2 | 11715 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11716 | } |
11717 | ||
91af127f | 11718 | if (request) |
75289874 | 11719 | i915_add_request_no_flush(request); |
91af127f | 11720 | |
1e3feefd | 11721 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11722 | work->enable_stall_check = true; |
4fa62c89 | 11723 | |
ab8d6675 | 11724 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11725 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11726 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11727 | |
d029bcad | 11728 | intel_fbc_deactivate(intel_crtc); |
a9ff8714 VS |
11729 | intel_frontbuffer_flip_prepare(dev, |
11730 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11731 | |
e5510fac JB |
11732 | trace_i915_flip_request(intel_crtc->plane, obj); |
11733 | ||
6b95a207 | 11734 | return 0; |
96b099fd | 11735 | |
4fa62c89 | 11736 | cleanup_unpin: |
82bc3b2d | 11737 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11738 | cleanup_pending: |
91af127f JH |
11739 | if (request) |
11740 | i915_gem_request_cancel(request); | |
b4a98e57 | 11741 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11742 | mutex_unlock(&dev->struct_mutex); |
11743 | cleanup: | |
f4510a27 | 11744 | crtc->primary->fb = old_fb; |
afd65eb4 | 11745 | update_state_fb(crtc->primary); |
89ed88ba CW |
11746 | |
11747 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11748 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11749 | |
5e2d7afc | 11750 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11751 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11752 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11753 | |
87b6b101 | 11754 | drm_crtc_vblank_put(crtc); |
7317c75e | 11755 | free_work: |
96b099fd CW |
11756 | kfree(work); |
11757 | ||
f900db47 | 11758 | if (ret == -EIO) { |
02e0efb5 ML |
11759 | struct drm_atomic_state *state; |
11760 | struct drm_plane_state *plane_state; | |
11761 | ||
f900db47 | 11762 | out_hang: |
02e0efb5 ML |
11763 | state = drm_atomic_state_alloc(dev); |
11764 | if (!state) | |
11765 | return -ENOMEM; | |
11766 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11767 | ||
11768 | retry: | |
11769 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11770 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11771 | if (!ret) { | |
11772 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11773 | ||
11774 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11775 | if (!ret) | |
11776 | ret = drm_atomic_commit(state); | |
11777 | } | |
11778 | ||
11779 | if (ret == -EDEADLK) { | |
11780 | drm_modeset_backoff(state->acquire_ctx); | |
11781 | drm_atomic_state_clear(state); | |
11782 | goto retry; | |
11783 | } | |
11784 | ||
11785 | if (ret) | |
11786 | drm_atomic_state_free(state); | |
11787 | ||
f0d3dad3 | 11788 | if (ret == 0 && event) { |
5e2d7afc | 11789 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11790 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11791 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11792 | } |
f900db47 | 11793 | } |
96b099fd | 11794 | return ret; |
6b95a207 KH |
11795 | } |
11796 | ||
da20eabd ML |
11797 | |
11798 | /** | |
11799 | * intel_wm_need_update - Check whether watermarks need updating | |
11800 | * @plane: drm plane | |
11801 | * @state: new plane state | |
11802 | * | |
11803 | * Check current plane state versus the new one to determine whether | |
11804 | * watermarks need to be recalculated. | |
11805 | * | |
11806 | * Returns true or false. | |
11807 | */ | |
11808 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11809 | struct drm_plane_state *state) | |
11810 | { | |
d21fbe87 MR |
11811 | struct intel_plane_state *new = to_intel_plane_state(state); |
11812 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11813 | ||
11814 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11815 | if (new->visible != cur->visible) |
11816 | return true; | |
11817 | ||
11818 | if (!cur->base.fb || !new->base.fb) | |
11819 | return false; | |
11820 | ||
11821 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11822 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11823 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11824 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11825 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11826 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11827 | return true; |
7809e5ae | 11828 | |
2791a16c | 11829 | return false; |
7809e5ae MR |
11830 | } |
11831 | ||
d21fbe87 MR |
11832 | static bool needs_scaling(struct intel_plane_state *state) |
11833 | { | |
11834 | int src_w = drm_rect_width(&state->src) >> 16; | |
11835 | int src_h = drm_rect_height(&state->src) >> 16; | |
11836 | int dst_w = drm_rect_width(&state->dst); | |
11837 | int dst_h = drm_rect_height(&state->dst); | |
11838 | ||
11839 | return (src_w != dst_w || src_h != dst_h); | |
11840 | } | |
11841 | ||
da20eabd ML |
11842 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11843 | struct drm_plane_state *plane_state) | |
11844 | { | |
ab1d3a0e | 11845 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11846 | struct drm_crtc *crtc = crtc_state->crtc; |
11847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11848 | struct drm_plane *plane = plane_state->plane; | |
11849 | struct drm_device *dev = crtc->dev; | |
11850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11851 | struct intel_plane_state *old_plane_state = | |
11852 | to_intel_plane_state(plane->state); | |
11853 | int idx = intel_crtc->base.base.id, ret; | |
11854 | int i = drm_plane_index(plane); | |
11855 | bool mode_changed = needs_modeset(crtc_state); | |
11856 | bool was_crtc_enabled = crtc->state->active; | |
11857 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11858 | bool turn_off, turn_on, visible, was_visible; |
11859 | struct drm_framebuffer *fb = plane_state->fb; | |
11860 | ||
11861 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11862 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11863 | ret = skl_update_scaler_plane( | |
11864 | to_intel_crtc_state(crtc_state), | |
11865 | to_intel_plane_state(plane_state)); | |
11866 | if (ret) | |
11867 | return ret; | |
11868 | } | |
11869 | ||
da20eabd ML |
11870 | was_visible = old_plane_state->visible; |
11871 | visible = to_intel_plane_state(plane_state)->visible; | |
11872 | ||
11873 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11874 | was_visible = false; | |
11875 | ||
35c08f43 ML |
11876 | /* |
11877 | * Visibility is calculated as if the crtc was on, but | |
11878 | * after scaler setup everything depends on it being off | |
11879 | * when the crtc isn't active. | |
11880 | */ | |
11881 | if (!is_crtc_enabled) | |
11882 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11883 | |
11884 | if (!was_visible && !visible) | |
11885 | return 0; | |
11886 | ||
11887 | turn_off = was_visible && (!visible || mode_changed); | |
11888 | turn_on = visible && (!was_visible || mode_changed); | |
11889 | ||
11890 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11891 | plane->base.id, fb ? fb->base.id : -1); | |
11892 | ||
11893 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11894 | plane->base.id, was_visible, visible, | |
11895 | turn_off, turn_on, mode_changed); | |
11896 | ||
92826fcd ML |
11897 | if (turn_on || turn_off) { |
11898 | pipe_config->wm_changed = true; | |
11899 | ||
852eb00d VS |
11900 | /* must disable cxsr around plane enable/disable */ |
11901 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11902 | if (is_crtc_enabled) | |
11903 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11904 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11905 | } |
11906 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11907 | pipe_config->wm_changed = true; |
852eb00d | 11908 | } |
da20eabd | 11909 | |
8be6ca85 | 11910 | if (visible || was_visible) |
a9ff8714 VS |
11911 | intel_crtc->atomic.fb_bits |= |
11912 | to_intel_plane(plane)->frontbuffer_bit; | |
11913 | ||
da20eabd ML |
11914 | switch (plane->type) { |
11915 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11916 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11917 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11918 | ||
066cf55b RV |
11919 | if (turn_off) { |
11920 | /* | |
11921 | * FIXME: Actually if we will still have any other | |
11922 | * plane enabled on the pipe we could let IPS enabled | |
11923 | * still, but for now lets consider that when we make | |
11924 | * primary invisible by setting DSPCNTR to 0 on | |
11925 | * update_primary_plane function IPS needs to be | |
11926 | * disable. | |
11927 | */ | |
11928 | intel_crtc->atomic.disable_ips = true; | |
11929 | ||
da20eabd | 11930 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11931 | } |
da20eabd ML |
11932 | |
11933 | /* | |
11934 | * FBC does not work on some platforms for rotated | |
11935 | * planes, so disable it when rotation is not 0 and | |
11936 | * update it when rotation is set back to 0. | |
11937 | * | |
11938 | * FIXME: This is redundant with the fbc update done in | |
11939 | * the primary plane enable function except that that | |
11940 | * one is done too late. We eventually need to unify | |
11941 | * this. | |
11942 | */ | |
11943 | ||
11944 | if (visible && | |
11945 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11946 | dev_priv->fbc.crtc == intel_crtc && | |
11947 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11948 | intel_crtc->atomic.disable_fbc = true; | |
11949 | ||
11950 | /* | |
11951 | * BDW signals flip done immediately if the plane | |
11952 | * is disabled, even if the plane enable is already | |
11953 | * armed to occur at the next vblank :( | |
11954 | */ | |
11955 | if (turn_on && IS_BROADWELL(dev)) | |
11956 | intel_crtc->atomic.wait_vblank = true; | |
11957 | ||
11958 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11959 | break; | |
11960 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11961 | break; |
11962 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11963 | /* |
11964 | * WaCxSRDisabledForSpriteScaling:ivb | |
11965 | * | |
11966 | * cstate->update_wm was already set above, so this flag will | |
11967 | * take effect when we commit and program watermarks. | |
11968 | */ | |
11969 | if (IS_IVYBRIDGE(dev) && | |
11970 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11971 | !needs_scaling(old_plane_state)) { | |
11972 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11973 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11974 | intel_crtc->atomic.wait_vblank = true; |
11975 | intel_crtc->atomic.update_sprite_watermarks |= | |
11976 | 1 << i; | |
11977 | } | |
d21fbe87 MR |
11978 | |
11979 | break; | |
da20eabd ML |
11980 | } |
11981 | return 0; | |
11982 | } | |
11983 | ||
6d3a1ce7 ML |
11984 | static bool encoders_cloneable(const struct intel_encoder *a, |
11985 | const struct intel_encoder *b) | |
11986 | { | |
11987 | /* masks could be asymmetric, so check both ways */ | |
11988 | return a == b || (a->cloneable & (1 << b->type) && | |
11989 | b->cloneable & (1 << a->type)); | |
11990 | } | |
11991 | ||
11992 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11993 | struct intel_crtc *crtc, | |
11994 | struct intel_encoder *encoder) | |
11995 | { | |
11996 | struct intel_encoder *source_encoder; | |
11997 | struct drm_connector *connector; | |
11998 | struct drm_connector_state *connector_state; | |
11999 | int i; | |
12000 | ||
12001 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12002 | if (connector_state->crtc != &crtc->base) | |
12003 | continue; | |
12004 | ||
12005 | source_encoder = | |
12006 | to_intel_encoder(connector_state->best_encoder); | |
12007 | if (!encoders_cloneable(encoder, source_encoder)) | |
12008 | return false; | |
12009 | } | |
12010 | ||
12011 | return true; | |
12012 | } | |
12013 | ||
12014 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12015 | struct intel_crtc *crtc) | |
12016 | { | |
12017 | struct intel_encoder *encoder; | |
12018 | struct drm_connector *connector; | |
12019 | struct drm_connector_state *connector_state; | |
12020 | int i; | |
12021 | ||
12022 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12023 | if (connector_state->crtc != &crtc->base) | |
12024 | continue; | |
12025 | ||
12026 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12027 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12028 | return false; | |
12029 | } | |
12030 | ||
12031 | return true; | |
12032 | } | |
12033 | ||
12034 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12035 | struct drm_crtc_state *crtc_state) | |
12036 | { | |
cf5a15be | 12037 | struct drm_device *dev = crtc->dev; |
ad421372 | 12038 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12039 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12040 | struct intel_crtc_state *pipe_config = |
12041 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12042 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12043 | int ret; |
6d3a1ce7 ML |
12044 | bool mode_changed = needs_modeset(crtc_state); |
12045 | ||
12046 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12047 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12048 | return -EINVAL; | |
12049 | } | |
12050 | ||
852eb00d | 12051 | if (mode_changed && !crtc_state->active) |
92826fcd | 12052 | pipe_config->wm_changed = true; |
eddfcbcd | 12053 | |
ad421372 ML |
12054 | if (mode_changed && crtc_state->enable && |
12055 | dev_priv->display.crtc_compute_clock && | |
12056 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12057 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12058 | pipe_config); | |
12059 | if (ret) | |
12060 | return ret; | |
12061 | } | |
12062 | ||
e435d6e5 | 12063 | ret = 0; |
86c8bbbe MR |
12064 | if (dev_priv->display.compute_pipe_wm) { |
12065 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
12066 | if (ret) | |
12067 | return ret; | |
12068 | } | |
12069 | ||
e435d6e5 ML |
12070 | if (INTEL_INFO(dev)->gen >= 9) { |
12071 | if (mode_changed) | |
12072 | ret = skl_update_scaler_crtc(pipe_config); | |
12073 | ||
12074 | if (!ret) | |
12075 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12076 | pipe_config); | |
12077 | } | |
12078 | ||
12079 | return ret; | |
6d3a1ce7 ML |
12080 | } |
12081 | ||
65b38e0d | 12082 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12083 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12084 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12085 | .atomic_begin = intel_begin_crtc_commit, |
12086 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12087 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12088 | }; |
12089 | ||
d29b2f9d ACO |
12090 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12091 | { | |
12092 | struct intel_connector *connector; | |
12093 | ||
12094 | for_each_intel_connector(dev, connector) { | |
12095 | if (connector->base.encoder) { | |
12096 | connector->base.state->best_encoder = | |
12097 | connector->base.encoder; | |
12098 | connector->base.state->crtc = | |
12099 | connector->base.encoder->crtc; | |
12100 | } else { | |
12101 | connector->base.state->best_encoder = NULL; | |
12102 | connector->base.state->crtc = NULL; | |
12103 | } | |
12104 | } | |
12105 | } | |
12106 | ||
050f7aeb | 12107 | static void |
eba905b2 | 12108 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12109 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12110 | { |
12111 | int bpp = pipe_config->pipe_bpp; | |
12112 | ||
12113 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12114 | connector->base.base.id, | |
c23cc417 | 12115 | connector->base.name); |
050f7aeb DV |
12116 | |
12117 | /* Don't use an invalid EDID bpc value */ | |
12118 | if (connector->base.display_info.bpc && | |
12119 | connector->base.display_info.bpc * 3 < bpp) { | |
12120 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12121 | bpp, connector->base.display_info.bpc*3); | |
12122 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12123 | } | |
12124 | ||
12125 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
12126 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
12127 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
12128 | bpp); | |
12129 | pipe_config->pipe_bpp = 24; | |
12130 | } | |
12131 | } | |
12132 | ||
4e53c2e0 | 12133 | static int |
050f7aeb | 12134 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12135 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12136 | { |
050f7aeb | 12137 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12138 | struct drm_atomic_state *state; |
da3ced29 ACO |
12139 | struct drm_connector *connector; |
12140 | struct drm_connector_state *connector_state; | |
1486017f | 12141 | int bpp, i; |
4e53c2e0 | 12142 | |
666a4537 | 12143 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12144 | bpp = 10*3; |
d328c9d7 DV |
12145 | else if (INTEL_INFO(dev)->gen >= 5) |
12146 | bpp = 12*3; | |
12147 | else | |
12148 | bpp = 8*3; | |
12149 | ||
4e53c2e0 | 12150 | |
4e53c2e0 DV |
12151 | pipe_config->pipe_bpp = bpp; |
12152 | ||
1486017f ACO |
12153 | state = pipe_config->base.state; |
12154 | ||
4e53c2e0 | 12155 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12156 | for_each_connector_in_state(state, connector, connector_state, i) { |
12157 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12158 | continue; |
12159 | ||
da3ced29 ACO |
12160 | connected_sink_compute_bpp(to_intel_connector(connector), |
12161 | pipe_config); | |
4e53c2e0 DV |
12162 | } |
12163 | ||
12164 | return bpp; | |
12165 | } | |
12166 | ||
644db711 DV |
12167 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12168 | { | |
12169 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12170 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12171 | mode->crtc_clock, |
644db711 DV |
12172 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12173 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12174 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12175 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12176 | } | |
12177 | ||
c0b03411 | 12178 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12179 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12180 | const char *context) |
12181 | { | |
6a60cd87 CK |
12182 | struct drm_device *dev = crtc->base.dev; |
12183 | struct drm_plane *plane; | |
12184 | struct intel_plane *intel_plane; | |
12185 | struct intel_plane_state *state; | |
12186 | struct drm_framebuffer *fb; | |
12187 | ||
12188 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12189 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12190 | |
12191 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12192 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12193 | pipe_config->pipe_bpp, pipe_config->dither); | |
12194 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12195 | pipe_config->has_pch_encoder, | |
12196 | pipe_config->fdi_lanes, | |
12197 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12198 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12199 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12200 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12201 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12202 | pipe_config->lane_count, |
eb14cb74 VS |
12203 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12204 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12205 | pipe_config->dp_m_n.tu); | |
b95af8be | 12206 | |
90a6b7b0 | 12207 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12208 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12209 | pipe_config->lane_count, |
b95af8be VK |
12210 | pipe_config->dp_m2_n2.gmch_m, |
12211 | pipe_config->dp_m2_n2.gmch_n, | |
12212 | pipe_config->dp_m2_n2.link_m, | |
12213 | pipe_config->dp_m2_n2.link_n, | |
12214 | pipe_config->dp_m2_n2.tu); | |
12215 | ||
55072d19 DV |
12216 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12217 | pipe_config->has_audio, | |
12218 | pipe_config->has_infoframe); | |
12219 | ||
c0b03411 | 12220 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12221 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12222 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12223 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12224 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12225 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12226 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12227 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12228 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12229 | crtc->num_scalers, | |
12230 | pipe_config->scaler_state.scaler_users, | |
12231 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12232 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12233 | pipe_config->gmch_pfit.control, | |
12234 | pipe_config->gmch_pfit.pgm_ratios, | |
12235 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12236 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12237 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12238 | pipe_config->pch_pfit.size, |
12239 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12240 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12241 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12242 | |
415ff0f6 | 12243 | if (IS_BROXTON(dev)) { |
05712c15 | 12244 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12245 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12246 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12247 | pipe_config->ddi_pll_sel, |
12248 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12249 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12250 | pipe_config->dpll_hw_state.pll0, |
12251 | pipe_config->dpll_hw_state.pll1, | |
12252 | pipe_config->dpll_hw_state.pll2, | |
12253 | pipe_config->dpll_hw_state.pll3, | |
12254 | pipe_config->dpll_hw_state.pll6, | |
12255 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12256 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12257 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12258 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12259 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12260 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12261 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12262 | pipe_config->ddi_pll_sel, | |
12263 | pipe_config->dpll_hw_state.ctrl1, | |
12264 | pipe_config->dpll_hw_state.cfgcr1, | |
12265 | pipe_config->dpll_hw_state.cfgcr2); | |
12266 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12267 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12268 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12269 | pipe_config->dpll_hw_state.wrpll, |
12270 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12271 | } else { |
12272 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12273 | "fp0: 0x%x, fp1: 0x%x\n", | |
12274 | pipe_config->dpll_hw_state.dpll, | |
12275 | pipe_config->dpll_hw_state.dpll_md, | |
12276 | pipe_config->dpll_hw_state.fp0, | |
12277 | pipe_config->dpll_hw_state.fp1); | |
12278 | } | |
12279 | ||
6a60cd87 CK |
12280 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12281 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12282 | intel_plane = to_intel_plane(plane); | |
12283 | if (intel_plane->pipe != crtc->pipe) | |
12284 | continue; | |
12285 | ||
12286 | state = to_intel_plane_state(plane->state); | |
12287 | fb = state->base.fb; | |
12288 | if (!fb) { | |
12289 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12290 | "disabled, scaler_id = %d\n", | |
12291 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12292 | plane->base.id, intel_plane->pipe, | |
12293 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12294 | drm_plane_index(plane), state->scaler_id); | |
12295 | continue; | |
12296 | } | |
12297 | ||
12298 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12299 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12300 | plane->base.id, intel_plane->pipe, | |
12301 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12302 | drm_plane_index(plane)); | |
12303 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12304 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12305 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12306 | state->scaler_id, | |
12307 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12308 | drm_rect_width(&state->src) >> 16, | |
12309 | drm_rect_height(&state->src) >> 16, | |
12310 | state->dst.x1, state->dst.y1, | |
12311 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12312 | } | |
c0b03411 DV |
12313 | } |
12314 | ||
5448a00d | 12315 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12316 | { |
5448a00d | 12317 | struct drm_device *dev = state->dev; |
da3ced29 | 12318 | struct drm_connector *connector; |
00f0b378 VS |
12319 | unsigned int used_ports = 0; |
12320 | ||
12321 | /* | |
12322 | * Walk the connector list instead of the encoder | |
12323 | * list to detect the problem on ddi platforms | |
12324 | * where there's just one encoder per digital port. | |
12325 | */ | |
0bff4858 VS |
12326 | drm_for_each_connector(connector, dev) { |
12327 | struct drm_connector_state *connector_state; | |
12328 | struct intel_encoder *encoder; | |
12329 | ||
12330 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12331 | if (!connector_state) | |
12332 | connector_state = connector->state; | |
12333 | ||
5448a00d | 12334 | if (!connector_state->best_encoder) |
00f0b378 VS |
12335 | continue; |
12336 | ||
5448a00d ACO |
12337 | encoder = to_intel_encoder(connector_state->best_encoder); |
12338 | ||
12339 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12340 | |
12341 | switch (encoder->type) { | |
12342 | unsigned int port_mask; | |
12343 | case INTEL_OUTPUT_UNKNOWN: | |
12344 | if (WARN_ON(!HAS_DDI(dev))) | |
12345 | break; | |
12346 | case INTEL_OUTPUT_DISPLAYPORT: | |
12347 | case INTEL_OUTPUT_HDMI: | |
12348 | case INTEL_OUTPUT_EDP: | |
12349 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12350 | ||
12351 | /* the same port mustn't appear more than once */ | |
12352 | if (used_ports & port_mask) | |
12353 | return false; | |
12354 | ||
12355 | used_ports |= port_mask; | |
12356 | default: | |
12357 | break; | |
12358 | } | |
12359 | } | |
12360 | ||
12361 | return true; | |
12362 | } | |
12363 | ||
83a57153 ACO |
12364 | static void |
12365 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12366 | { | |
12367 | struct drm_crtc_state tmp_state; | |
663a3640 | 12368 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12369 | struct intel_dpll_hw_state dpll_hw_state; |
12370 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12371 | uint32_t ddi_pll_sel; |
c4e2d043 | 12372 | bool force_thru; |
83a57153 | 12373 | |
7546a384 ACO |
12374 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12375 | * kzalloc'd. Code that depends on any field being zero should be | |
12376 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12377 | * only fields that are know to not cause problems are preserved. */ | |
12378 | ||
83a57153 | 12379 | tmp_state = crtc_state->base; |
663a3640 | 12380 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12381 | shared_dpll = crtc_state->shared_dpll; |
12382 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12383 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12384 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12385 | |
83a57153 | 12386 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12387 | |
83a57153 | 12388 | crtc_state->base = tmp_state; |
663a3640 | 12389 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12390 | crtc_state->shared_dpll = shared_dpll; |
12391 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12392 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12393 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12394 | } |
12395 | ||
548ee15b | 12396 | static int |
b8cecdf5 | 12397 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12398 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12399 | { |
b359283a | 12400 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12401 | struct intel_encoder *encoder; |
da3ced29 | 12402 | struct drm_connector *connector; |
0b901879 | 12403 | struct drm_connector_state *connector_state; |
d328c9d7 | 12404 | int base_bpp, ret = -EINVAL; |
0b901879 | 12405 | int i; |
e29c22c0 | 12406 | bool retry = true; |
ee7b9f93 | 12407 | |
83a57153 | 12408 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12409 | |
e143a21c DV |
12410 | pipe_config->cpu_transcoder = |
12411 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12412 | |
2960bc9c ID |
12413 | /* |
12414 | * Sanitize sync polarity flags based on requested ones. If neither | |
12415 | * positive or negative polarity is requested, treat this as meaning | |
12416 | * negative polarity. | |
12417 | */ | |
2d112de7 | 12418 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12419 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12420 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12421 | |
2d112de7 | 12422 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12423 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12424 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12425 | |
d328c9d7 DV |
12426 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12427 | pipe_config); | |
12428 | if (base_bpp < 0) | |
4e53c2e0 DV |
12429 | goto fail; |
12430 | ||
e41a56be VS |
12431 | /* |
12432 | * Determine the real pipe dimensions. Note that stereo modes can | |
12433 | * increase the actual pipe size due to the frame doubling and | |
12434 | * insertion of additional space for blanks between the frame. This | |
12435 | * is stored in the crtc timings. We use the requested mode to do this | |
12436 | * computation to clearly distinguish it from the adjusted mode, which | |
12437 | * can be changed by the connectors in the below retry loop. | |
12438 | */ | |
2d112de7 | 12439 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12440 | &pipe_config->pipe_src_w, |
12441 | &pipe_config->pipe_src_h); | |
e41a56be | 12442 | |
e29c22c0 | 12443 | encoder_retry: |
ef1b460d | 12444 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12445 | pipe_config->port_clock = 0; |
ef1b460d | 12446 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12447 | |
135c81b8 | 12448 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12449 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12450 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12451 | |
7758a113 DV |
12452 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12453 | * adjust it according to limitations or connector properties, and also | |
12454 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12455 | */ |
da3ced29 | 12456 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12457 | if (connector_state->crtc != crtc) |
7758a113 | 12458 | continue; |
7ae89233 | 12459 | |
0b901879 ACO |
12460 | encoder = to_intel_encoder(connector_state->best_encoder); |
12461 | ||
efea6e8e DV |
12462 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12463 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12464 | goto fail; |
12465 | } | |
ee7b9f93 | 12466 | } |
47f1c6c9 | 12467 | |
ff9a6750 DV |
12468 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12469 | * done afterwards in case the encoder adjusts the mode. */ | |
12470 | if (!pipe_config->port_clock) | |
2d112de7 | 12471 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12472 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12473 | |
a43f6e0f | 12474 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12475 | if (ret < 0) { |
7758a113 DV |
12476 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12477 | goto fail; | |
ee7b9f93 | 12478 | } |
e29c22c0 DV |
12479 | |
12480 | if (ret == RETRY) { | |
12481 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12482 | ret = -EINVAL; | |
12483 | goto fail; | |
12484 | } | |
12485 | ||
12486 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12487 | retry = false; | |
12488 | goto encoder_retry; | |
12489 | } | |
12490 | ||
e8fa4270 DV |
12491 | /* Dithering seems to not pass-through bits correctly when it should, so |
12492 | * only enable it on 6bpc panels. */ | |
12493 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12494 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12495 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12496 | |
7758a113 | 12497 | fail: |
548ee15b | 12498 | return ret; |
ee7b9f93 | 12499 | } |
47f1c6c9 | 12500 | |
ea9d758d | 12501 | static void |
4740b0f2 | 12502 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12503 | { |
0a9ab303 ACO |
12504 | struct drm_crtc *crtc; |
12505 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12506 | int i; |
ea9d758d | 12507 | |
7668851f | 12508 | /* Double check state. */ |
8a75d157 | 12509 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12510 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12511 | |
12512 | /* Update hwmode for vblank functions */ | |
12513 | if (crtc->state->active) | |
12514 | crtc->hwmode = crtc->state->adjusted_mode; | |
12515 | else | |
12516 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12517 | |
12518 | /* | |
12519 | * Update legacy state to satisfy fbc code. This can | |
12520 | * be removed when fbc uses the atomic state. | |
12521 | */ | |
12522 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12523 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12524 | ||
12525 | crtc->primary->fb = plane_state->fb; | |
12526 | crtc->x = plane_state->src_x >> 16; | |
12527 | crtc->y = plane_state->src_y >> 16; | |
12528 | } | |
ea9d758d | 12529 | } |
ea9d758d DV |
12530 | } |
12531 | ||
3bd26263 | 12532 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12533 | { |
3bd26263 | 12534 | int diff; |
f1f644dc JB |
12535 | |
12536 | if (clock1 == clock2) | |
12537 | return true; | |
12538 | ||
12539 | if (!clock1 || !clock2) | |
12540 | return false; | |
12541 | ||
12542 | diff = abs(clock1 - clock2); | |
12543 | ||
12544 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12545 | return true; | |
12546 | ||
12547 | return false; | |
12548 | } | |
12549 | ||
25c5b266 DV |
12550 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12551 | list_for_each_entry((intel_crtc), \ | |
12552 | &(dev)->mode_config.crtc_list, \ | |
12553 | base.head) \ | |
95150bdf | 12554 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12555 | |
cfb23ed6 ML |
12556 | static bool |
12557 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12558 | unsigned int m2, unsigned int n2, | |
12559 | bool exact) | |
12560 | { | |
12561 | if (m == m2 && n == n2) | |
12562 | return true; | |
12563 | ||
12564 | if (exact || !m || !n || !m2 || !n2) | |
12565 | return false; | |
12566 | ||
12567 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12568 | ||
12569 | if (m > m2) { | |
12570 | while (m > m2) { | |
12571 | m2 <<= 1; | |
12572 | n2 <<= 1; | |
12573 | } | |
12574 | } else if (m < m2) { | |
12575 | while (m < m2) { | |
12576 | m <<= 1; | |
12577 | n <<= 1; | |
12578 | } | |
12579 | } | |
12580 | ||
12581 | return m == m2 && n == n2; | |
12582 | } | |
12583 | ||
12584 | static bool | |
12585 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12586 | struct intel_link_m_n *m2_n2, | |
12587 | bool adjust) | |
12588 | { | |
12589 | if (m_n->tu == m2_n2->tu && | |
12590 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12591 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12592 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12593 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12594 | if (adjust) | |
12595 | *m2_n2 = *m_n; | |
12596 | ||
12597 | return true; | |
12598 | } | |
12599 | ||
12600 | return false; | |
12601 | } | |
12602 | ||
0e8ffe1b | 12603 | static bool |
2fa2fe9a | 12604 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12605 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12606 | struct intel_crtc_state *pipe_config, |
12607 | bool adjust) | |
0e8ffe1b | 12608 | { |
cfb23ed6 ML |
12609 | bool ret = true; |
12610 | ||
12611 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12612 | do { \ | |
12613 | if (!adjust) \ | |
12614 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12615 | else \ | |
12616 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12617 | } while (0) | |
12618 | ||
66e985c0 DV |
12619 | #define PIPE_CONF_CHECK_X(name) \ |
12620 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12621 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12622 | "(expected 0x%08x, found 0x%08x)\n", \ |
12623 | current_config->name, \ | |
12624 | pipe_config->name); \ | |
cfb23ed6 | 12625 | ret = false; \ |
66e985c0 DV |
12626 | } |
12627 | ||
08a24034 DV |
12628 | #define PIPE_CONF_CHECK_I(name) \ |
12629 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12630 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12631 | "(expected %i, found %i)\n", \ |
12632 | current_config->name, \ | |
12633 | pipe_config->name); \ | |
cfb23ed6 ML |
12634 | ret = false; \ |
12635 | } | |
12636 | ||
12637 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12638 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12639 | &pipe_config->name,\ | |
12640 | adjust)) { \ | |
12641 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12642 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12643 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12644 | current_config->name.tu, \ | |
12645 | current_config->name.gmch_m, \ | |
12646 | current_config->name.gmch_n, \ | |
12647 | current_config->name.link_m, \ | |
12648 | current_config->name.link_n, \ | |
12649 | pipe_config->name.tu, \ | |
12650 | pipe_config->name.gmch_m, \ | |
12651 | pipe_config->name.gmch_n, \ | |
12652 | pipe_config->name.link_m, \ | |
12653 | pipe_config->name.link_n); \ | |
12654 | ret = false; \ | |
12655 | } | |
12656 | ||
12657 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12658 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12659 | &pipe_config->name, adjust) && \ | |
12660 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12661 | &pipe_config->name, adjust)) { \ | |
12662 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12663 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12664 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12665 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12666 | current_config->name.tu, \ | |
12667 | current_config->name.gmch_m, \ | |
12668 | current_config->name.gmch_n, \ | |
12669 | current_config->name.link_m, \ | |
12670 | current_config->name.link_n, \ | |
12671 | current_config->alt_name.tu, \ | |
12672 | current_config->alt_name.gmch_m, \ | |
12673 | current_config->alt_name.gmch_n, \ | |
12674 | current_config->alt_name.link_m, \ | |
12675 | current_config->alt_name.link_n, \ | |
12676 | pipe_config->name.tu, \ | |
12677 | pipe_config->name.gmch_m, \ | |
12678 | pipe_config->name.gmch_n, \ | |
12679 | pipe_config->name.link_m, \ | |
12680 | pipe_config->name.link_n); \ | |
12681 | ret = false; \ | |
88adfff1 DV |
12682 | } |
12683 | ||
b95af8be VK |
12684 | /* This is required for BDW+ where there is only one set of registers for |
12685 | * switching between high and low RR. | |
12686 | * This macro can be used whenever a comparison has to be made between one | |
12687 | * hw state and multiple sw state variables. | |
12688 | */ | |
12689 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12690 | if ((current_config->name != pipe_config->name) && \ | |
12691 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12692 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12693 | "(expected %i or %i, found %i)\n", \ |
12694 | current_config->name, \ | |
12695 | current_config->alt_name, \ | |
12696 | pipe_config->name); \ | |
cfb23ed6 | 12697 | ret = false; \ |
b95af8be VK |
12698 | } |
12699 | ||
1bd1bd80 DV |
12700 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12701 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12702 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12703 | "(expected %i, found %i)\n", \ |
12704 | current_config->name & (mask), \ | |
12705 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12706 | ret = false; \ |
1bd1bd80 DV |
12707 | } |
12708 | ||
5e550656 VS |
12709 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12710 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12711 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12712 | "(expected %i, found %i)\n", \ |
12713 | current_config->name, \ | |
12714 | pipe_config->name); \ | |
cfb23ed6 | 12715 | ret = false; \ |
5e550656 VS |
12716 | } |
12717 | ||
bb760063 DV |
12718 | #define PIPE_CONF_QUIRK(quirk) \ |
12719 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12720 | ||
eccb140b DV |
12721 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12722 | ||
08a24034 DV |
12723 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12724 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12725 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12726 | |
eb14cb74 | 12727 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12728 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12729 | |
12730 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12731 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12732 | ||
cfb23ed6 ML |
12733 | if (current_config->has_drrs) |
12734 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12735 | } else | |
12736 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12737 | |
a65347ba JN |
12738 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12739 | ||
2d112de7 ACO |
12740 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12741 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12742 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12743 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12744 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12745 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12746 | |
2d112de7 ACO |
12747 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12748 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12749 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12750 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12751 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12752 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12753 | |
c93f54cf | 12754 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12755 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12756 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12757 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12758 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12759 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12760 | |
9ed109a7 DV |
12761 | PIPE_CONF_CHECK_I(has_audio); |
12762 | ||
2d112de7 | 12763 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12764 | DRM_MODE_FLAG_INTERLACE); |
12765 | ||
bb760063 | 12766 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12767 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12768 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12769 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12770 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12771 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12772 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12773 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12774 | DRM_MODE_FLAG_NVSYNC); |
12775 | } | |
045ac3b5 | 12776 | |
333b8ca8 | 12777 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12778 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12779 | if (INTEL_INFO(dev)->gen < 4) | |
12780 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12781 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12782 | |
bfd16b2a ML |
12783 | if (!adjust) { |
12784 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12785 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12786 | ||
12787 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12788 | if (current_config->pch_pfit.enabled) { | |
12789 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12790 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12791 | } | |
2fa2fe9a | 12792 | |
7aefe2b5 ML |
12793 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12794 | } | |
a1b2278e | 12795 | |
e59150dc JB |
12796 | /* BDW+ don't expose a synchronous way to read the state */ |
12797 | if (IS_HASWELL(dev)) | |
12798 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12799 | |
282740f7 VS |
12800 | PIPE_CONF_CHECK_I(double_wide); |
12801 | ||
26804afd DV |
12802 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12803 | ||
c0d43d62 | 12804 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12805 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12806 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12807 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12808 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12809 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12810 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12811 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12812 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12813 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12814 | |
42571aef VS |
12815 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12816 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12817 | ||
2d112de7 | 12818 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12819 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12820 | |
66e985c0 | 12821 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12822 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12823 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12824 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12825 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12826 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12827 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12828 | |
cfb23ed6 | 12829 | return ret; |
0e8ffe1b DV |
12830 | } |
12831 | ||
08db6652 DL |
12832 | static void check_wm_state(struct drm_device *dev) |
12833 | { | |
12834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12835 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12836 | struct intel_crtc *intel_crtc; | |
12837 | int plane; | |
12838 | ||
12839 | if (INTEL_INFO(dev)->gen < 9) | |
12840 | return; | |
12841 | ||
12842 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12843 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12844 | ||
12845 | for_each_intel_crtc(dev, intel_crtc) { | |
12846 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12847 | const enum pipe pipe = intel_crtc->pipe; | |
12848 | ||
12849 | if (!intel_crtc->active) | |
12850 | continue; | |
12851 | ||
12852 | /* planes */ | |
dd740780 | 12853 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12854 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12855 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12856 | ||
12857 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12858 | continue; | |
12859 | ||
12860 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12861 | "(expected (%u,%u), found (%u,%u))\n", | |
12862 | pipe_name(pipe), plane + 1, | |
12863 | sw_entry->start, sw_entry->end, | |
12864 | hw_entry->start, hw_entry->end); | |
12865 | } | |
12866 | ||
12867 | /* cursor */ | |
4969d33e MR |
12868 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12869 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12870 | |
12871 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12872 | continue; | |
12873 | ||
12874 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12875 | "(expected (%u,%u), found (%u,%u))\n", | |
12876 | pipe_name(pipe), | |
12877 | sw_entry->start, sw_entry->end, | |
12878 | hw_entry->start, hw_entry->end); | |
12879 | } | |
12880 | } | |
12881 | ||
91d1b4bd | 12882 | static void |
35dd3c64 ML |
12883 | check_connector_state(struct drm_device *dev, |
12884 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12885 | { |
35dd3c64 ML |
12886 | struct drm_connector_state *old_conn_state; |
12887 | struct drm_connector *connector; | |
12888 | int i; | |
8af6cf88 | 12889 | |
35dd3c64 ML |
12890 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12891 | struct drm_encoder *encoder = connector->encoder; | |
12892 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12893 | |
8af6cf88 DV |
12894 | /* This also checks the encoder/connector hw state with the |
12895 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12896 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12897 | |
ad3c558f | 12898 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12899 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12900 | } |
91d1b4bd DV |
12901 | } |
12902 | ||
12903 | static void | |
12904 | check_encoder_state(struct drm_device *dev) | |
12905 | { | |
12906 | struct intel_encoder *encoder; | |
12907 | struct intel_connector *connector; | |
8af6cf88 | 12908 | |
b2784e15 | 12909 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12910 | bool enabled = false; |
4d20cd86 | 12911 | enum pipe pipe; |
8af6cf88 DV |
12912 | |
12913 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12914 | encoder->base.base.id, | |
8e329a03 | 12915 | encoder->base.name); |
8af6cf88 | 12916 | |
3a3371ff | 12917 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12918 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12919 | continue; |
12920 | enabled = true; | |
ad3c558f ML |
12921 | |
12922 | I915_STATE_WARN(connector->base.state->crtc != | |
12923 | encoder->base.crtc, | |
12924 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12925 | } |
0e32b39c | 12926 | |
e2c719b7 | 12927 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12928 | "encoder's enabled state mismatch " |
12929 | "(expected %i, found %i)\n", | |
12930 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12931 | |
12932 | if (!encoder->base.crtc) { | |
4d20cd86 | 12933 | bool active; |
7c60d198 | 12934 | |
4d20cd86 ML |
12935 | active = encoder->get_hw_state(encoder, &pipe); |
12936 | I915_STATE_WARN(active, | |
12937 | "encoder detached but still enabled on pipe %c.\n", | |
12938 | pipe_name(pipe)); | |
7c60d198 | 12939 | } |
8af6cf88 | 12940 | } |
91d1b4bd DV |
12941 | } |
12942 | ||
12943 | static void | |
4d20cd86 | 12944 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12945 | { |
fbee40df | 12946 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12947 | struct intel_encoder *encoder; |
4d20cd86 ML |
12948 | struct drm_crtc_state *old_crtc_state; |
12949 | struct drm_crtc *crtc; | |
12950 | int i; | |
8af6cf88 | 12951 | |
4d20cd86 ML |
12952 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12954 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12955 | bool active; |
8af6cf88 | 12956 | |
bfd16b2a ML |
12957 | if (!needs_modeset(crtc->state) && |
12958 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12959 | continue; |
045ac3b5 | 12960 | |
4d20cd86 ML |
12961 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12962 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12963 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12964 | pipe_config->base.crtc = crtc; | |
12965 | pipe_config->base.state = old_state; | |
8af6cf88 | 12966 | |
4d20cd86 ML |
12967 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12968 | crtc->base.id); | |
8af6cf88 | 12969 | |
4d20cd86 ML |
12970 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12971 | pipe_config); | |
d62cf62a | 12972 | |
b6b5d049 | 12973 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12974 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12975 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12976 | active = crtc->state->active; | |
6c49f241 | 12977 | |
4d20cd86 | 12978 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12979 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12980 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12981 | |
4d20cd86 | 12982 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12983 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12984 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12985 | ||
12986 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12987 | enum pipe pipe; | |
12988 | ||
12989 | active = encoder->get_hw_state(encoder, &pipe); | |
12990 | I915_STATE_WARN(active != crtc->state->active, | |
12991 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12992 | encoder->base.base.id, active, crtc->state->active); | |
12993 | ||
12994 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12995 | "Encoder connected to wrong pipe %c\n", | |
12996 | pipe_name(pipe)); | |
12997 | ||
12998 | if (active) | |
12999 | encoder->get_config(encoder, pipe_config); | |
13000 | } | |
53d9f4e9 | 13001 | |
4d20cd86 | 13002 | if (!crtc->state->active) |
cfb23ed6 ML |
13003 | continue; |
13004 | ||
4d20cd86 ML |
13005 | sw_config = to_intel_crtc_state(crtc->state); |
13006 | if (!intel_pipe_config_compare(dev, sw_config, | |
13007 | pipe_config, false)) { | |
e2c719b7 | 13008 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 13009 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 13010 | "[hw state]"); |
4d20cd86 | 13011 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
13012 | "[sw state]"); |
13013 | } | |
8af6cf88 DV |
13014 | } |
13015 | } | |
13016 | ||
91d1b4bd DV |
13017 | static void |
13018 | check_shared_dpll_state(struct drm_device *dev) | |
13019 | { | |
fbee40df | 13020 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
13021 | struct intel_crtc *crtc; |
13022 | struct intel_dpll_hw_state dpll_hw_state; | |
13023 | int i; | |
5358901f DV |
13024 | |
13025 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
13026 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13027 | int enabled_crtcs = 0, active_crtcs = 0; | |
13028 | bool active; | |
13029 | ||
13030 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13031 | ||
13032 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13033 | ||
13034 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13035 | ||
e2c719b7 | 13036 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13037 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13038 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13039 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13040 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13041 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13042 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13043 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13044 | "pll on state mismatch (expected %i, found %i)\n", |
13045 | pll->on, active); | |
13046 | ||
d3fcc808 | 13047 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13048 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13049 | enabled_crtcs++; |
13050 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13051 | active_crtcs++; | |
13052 | } | |
e2c719b7 | 13053 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13054 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13055 | pll->active, active_crtcs); | |
e2c719b7 | 13056 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13057 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13058 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13059 | |
e2c719b7 | 13060 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13061 | sizeof(dpll_hw_state)), |
13062 | "pll hw state mismatch\n"); | |
5358901f | 13063 | } |
8af6cf88 DV |
13064 | } |
13065 | ||
ee165b1a ML |
13066 | static void |
13067 | intel_modeset_check_state(struct drm_device *dev, | |
13068 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13069 | { |
08db6652 | 13070 | check_wm_state(dev); |
35dd3c64 | 13071 | check_connector_state(dev, old_state); |
91d1b4bd | 13072 | check_encoder_state(dev); |
4d20cd86 | 13073 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13074 | check_shared_dpll_state(dev); |
13075 | } | |
13076 | ||
5cec258b | 13077 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13078 | int dotclock) |
13079 | { | |
13080 | /* | |
13081 | * FDI already provided one idea for the dotclock. | |
13082 | * Yell if the encoder disagrees. | |
13083 | */ | |
2d112de7 | 13084 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13085 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13086 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13087 | } |
13088 | ||
80715b2f VS |
13089 | static void update_scanline_offset(struct intel_crtc *crtc) |
13090 | { | |
13091 | struct drm_device *dev = crtc->base.dev; | |
13092 | ||
13093 | /* | |
13094 | * The scanline counter increments at the leading edge of hsync. | |
13095 | * | |
13096 | * On most platforms it starts counting from vtotal-1 on the | |
13097 | * first active line. That means the scanline counter value is | |
13098 | * always one less than what we would expect. Ie. just after | |
13099 | * start of vblank, which also occurs at start of hsync (on the | |
13100 | * last active line), the scanline counter will read vblank_start-1. | |
13101 | * | |
13102 | * On gen2 the scanline counter starts counting from 1 instead | |
13103 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13104 | * to keep the value positive), instead of adding one. | |
13105 | * | |
13106 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13107 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13108 | * there's an extra 1 line difference. So we need to add two instead of | |
13109 | * one to the value. | |
13110 | */ | |
13111 | if (IS_GEN2(dev)) { | |
124abe07 | 13112 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13113 | int vtotal; |
13114 | ||
124abe07 VS |
13115 | vtotal = adjusted_mode->crtc_vtotal; |
13116 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13117 | vtotal /= 2; |
13118 | ||
13119 | crtc->scanline_offset = vtotal - 1; | |
13120 | } else if (HAS_DDI(dev) && | |
409ee761 | 13121 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13122 | crtc->scanline_offset = 2; |
13123 | } else | |
13124 | crtc->scanline_offset = 1; | |
13125 | } | |
13126 | ||
ad421372 | 13127 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13128 | { |
225da59b | 13129 | struct drm_device *dev = state->dev; |
ed6739ef | 13130 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13131 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13132 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13133 | struct intel_crtc_state *intel_crtc_state; |
13134 | struct drm_crtc *crtc; | |
13135 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13136 | int i; |
ed6739ef ACO |
13137 | |
13138 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13139 | return; |
ed6739ef | 13140 | |
0a9ab303 | 13141 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13142 | int dpll; |
13143 | ||
0a9ab303 | 13144 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13145 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13146 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13147 | |
ad421372 | 13148 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13149 | continue; |
13150 | ||
ad421372 | 13151 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13152 | |
ad421372 ML |
13153 | if (!shared_dpll) |
13154 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13155 | |
ad421372 ML |
13156 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13157 | } | |
ed6739ef ACO |
13158 | } |
13159 | ||
99d736a2 ML |
13160 | /* |
13161 | * This implements the workaround described in the "notes" section of the mode | |
13162 | * set sequence documentation. When going from no pipes or single pipe to | |
13163 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13164 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13165 | */ | |
13166 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13167 | { | |
13168 | struct drm_crtc_state *crtc_state; | |
13169 | struct intel_crtc *intel_crtc; | |
13170 | struct drm_crtc *crtc; | |
13171 | struct intel_crtc_state *first_crtc_state = NULL; | |
13172 | struct intel_crtc_state *other_crtc_state = NULL; | |
13173 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13174 | int i; | |
13175 | ||
13176 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13177 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13178 | intel_crtc = to_intel_crtc(crtc); | |
13179 | ||
13180 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13181 | continue; | |
13182 | ||
13183 | if (first_crtc_state) { | |
13184 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13185 | break; | |
13186 | } else { | |
13187 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13188 | first_pipe = intel_crtc->pipe; | |
13189 | } | |
13190 | } | |
13191 | ||
13192 | /* No workaround needed? */ | |
13193 | if (!first_crtc_state) | |
13194 | return 0; | |
13195 | ||
13196 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13197 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13198 | struct intel_crtc_state *pipe_config; | |
13199 | ||
13200 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13201 | if (IS_ERR(pipe_config)) | |
13202 | return PTR_ERR(pipe_config); | |
13203 | ||
13204 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13205 | ||
13206 | if (!pipe_config->base.active || | |
13207 | needs_modeset(&pipe_config->base)) | |
13208 | continue; | |
13209 | ||
13210 | /* 2 or more enabled crtcs means no need for w/a */ | |
13211 | if (enabled_pipe != INVALID_PIPE) | |
13212 | return 0; | |
13213 | ||
13214 | enabled_pipe = intel_crtc->pipe; | |
13215 | } | |
13216 | ||
13217 | if (enabled_pipe != INVALID_PIPE) | |
13218 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13219 | else if (other_crtc_state) | |
13220 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13221 | ||
13222 | return 0; | |
13223 | } | |
13224 | ||
27c329ed ML |
13225 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13226 | { | |
13227 | struct drm_crtc *crtc; | |
13228 | struct drm_crtc_state *crtc_state; | |
13229 | int ret = 0; | |
13230 | ||
13231 | /* add all active pipes to the state */ | |
13232 | for_each_crtc(state->dev, crtc) { | |
13233 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13234 | if (IS_ERR(crtc_state)) | |
13235 | return PTR_ERR(crtc_state); | |
13236 | ||
13237 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13238 | continue; | |
13239 | ||
13240 | crtc_state->mode_changed = true; | |
13241 | ||
13242 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13243 | if (ret) | |
13244 | break; | |
13245 | ||
13246 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13247 | if (ret) | |
13248 | break; | |
13249 | } | |
13250 | ||
13251 | return ret; | |
13252 | } | |
13253 | ||
c347a676 | 13254 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13255 | { |
565602d7 ML |
13256 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13257 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13258 | struct drm_crtc *crtc; | |
13259 | struct drm_crtc_state *crtc_state; | |
13260 | int ret = 0, i; | |
054518dd | 13261 | |
b359283a ML |
13262 | if (!check_digital_port_conflicts(state)) { |
13263 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13264 | return -EINVAL; | |
13265 | } | |
13266 | ||
565602d7 ML |
13267 | intel_state->modeset = true; |
13268 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13269 | ||
13270 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13271 | if (crtc_state->active) | |
13272 | intel_state->active_crtcs |= 1 << i; | |
13273 | else | |
13274 | intel_state->active_crtcs &= ~(1 << i); | |
13275 | } | |
13276 | ||
054518dd ACO |
13277 | /* |
13278 | * See if the config requires any additional preparation, e.g. | |
13279 | * to adjust global state with pipes off. We need to do this | |
13280 | * here so we can get the modeset_pipe updated config for the new | |
13281 | * mode set on this crtc. For other crtcs we need to use the | |
13282 | * adjusted_mode bits in the crtc directly. | |
13283 | */ | |
27c329ed | 13284 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13285 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13286 | ||
1a617b77 | 13287 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13288 | ret = intel_modeset_all_pipes(state); |
13289 | ||
13290 | if (ret < 0) | |
054518dd | 13291 | return ret; |
27c329ed | 13292 | } else |
1a617b77 | 13293 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13294 | |
ad421372 | 13295 | intel_modeset_clear_plls(state); |
054518dd | 13296 | |
565602d7 | 13297 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13298 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13299 | |
ad421372 | 13300 | return 0; |
c347a676 ACO |
13301 | } |
13302 | ||
aa363136 MR |
13303 | /* |
13304 | * Handle calculation of various watermark data at the end of the atomic check | |
13305 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13306 | * handlers to ensure that all derived state has been updated. | |
13307 | */ | |
13308 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13309 | { | |
13310 | struct drm_device *dev = state->dev; | |
13311 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13312 | struct drm_crtc *crtc; | |
13313 | struct drm_crtc_state *cstate; | |
13314 | struct drm_plane *plane; | |
13315 | struct drm_plane_state *pstate; | |
13316 | ||
13317 | /* | |
13318 | * Calculate watermark configuration details now that derived | |
13319 | * plane/crtc state is all properly updated. | |
13320 | */ | |
13321 | drm_for_each_crtc(crtc, dev) { | |
13322 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13323 | crtc->state; | |
13324 | ||
13325 | if (cstate->active) | |
13326 | intel_state->wm_config.num_pipes_active++; | |
13327 | } | |
13328 | drm_for_each_legacy_plane(plane, dev) { | |
13329 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13330 | plane->state; | |
13331 | ||
13332 | if (!to_intel_plane_state(pstate)->visible) | |
13333 | continue; | |
13334 | ||
13335 | intel_state->wm_config.sprites_enabled = true; | |
13336 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13337 | pstate->crtc_h != pstate->src_h >> 16) | |
13338 | intel_state->wm_config.sprites_scaled = true; | |
13339 | } | |
13340 | } | |
13341 | ||
74c090b1 ML |
13342 | /** |
13343 | * intel_atomic_check - validate state object | |
13344 | * @dev: drm device | |
13345 | * @state: state to validate | |
13346 | */ | |
13347 | static int intel_atomic_check(struct drm_device *dev, | |
13348 | struct drm_atomic_state *state) | |
c347a676 | 13349 | { |
aa363136 | 13350 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13351 | struct drm_crtc *crtc; |
13352 | struct drm_crtc_state *crtc_state; | |
13353 | int ret, i; | |
61333b60 | 13354 | bool any_ms = false; |
c347a676 | 13355 | |
74c090b1 | 13356 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13357 | if (ret) |
13358 | return ret; | |
13359 | ||
c347a676 | 13360 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13361 | struct intel_crtc_state *pipe_config = |
13362 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13363 | |
ba8af3e5 ML |
13364 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13365 | sizeof(struct intel_crtc_atomic_commit)); | |
13366 | ||
1ed51de9 DV |
13367 | /* Catch I915_MODE_FLAG_INHERITED */ |
13368 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13369 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13370 | |
61333b60 ML |
13371 | if (!crtc_state->enable) { |
13372 | if (needs_modeset(crtc_state)) | |
13373 | any_ms = true; | |
c347a676 | 13374 | continue; |
61333b60 | 13375 | } |
c347a676 | 13376 | |
26495481 | 13377 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13378 | continue; |
13379 | ||
26495481 DV |
13380 | /* FIXME: For only active_changed we shouldn't need to do any |
13381 | * state recomputation at all. */ | |
13382 | ||
1ed51de9 DV |
13383 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13384 | if (ret) | |
13385 | return ret; | |
b359283a | 13386 | |
cfb23ed6 | 13387 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13388 | if (ret) |
13389 | return ret; | |
13390 | ||
73831236 JN |
13391 | if (i915.fastboot && |
13392 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13393 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13394 | pipe_config, true)) { |
26495481 | 13395 | crtc_state->mode_changed = false; |
bfd16b2a | 13396 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13397 | } |
13398 | ||
13399 | if (needs_modeset(crtc_state)) { | |
13400 | any_ms = true; | |
cfb23ed6 ML |
13401 | |
13402 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13403 | if (ret) | |
13404 | return ret; | |
13405 | } | |
61333b60 | 13406 | |
26495481 DV |
13407 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13408 | needs_modeset(crtc_state) ? | |
13409 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13410 | } |
13411 | ||
61333b60 ML |
13412 | if (any_ms) { |
13413 | ret = intel_modeset_checks(state); | |
13414 | ||
13415 | if (ret) | |
13416 | return ret; | |
27c329ed | 13417 | } else |
aa363136 | 13418 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13419 | |
aa363136 MR |
13420 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13421 | if (ret) | |
13422 | return ret; | |
13423 | ||
13424 | calc_watermark_data(state); | |
13425 | ||
13426 | return 0; | |
054518dd ACO |
13427 | } |
13428 | ||
5008e874 ML |
13429 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13430 | struct drm_atomic_state *state, | |
13431 | bool async) | |
13432 | { | |
7580d774 ML |
13433 | struct drm_i915_private *dev_priv = dev->dev_private; |
13434 | struct drm_plane_state *plane_state; | |
5008e874 | 13435 | struct drm_crtc_state *crtc_state; |
7580d774 | 13436 | struct drm_plane *plane; |
5008e874 ML |
13437 | struct drm_crtc *crtc; |
13438 | int i, ret; | |
13439 | ||
13440 | if (async) { | |
13441 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13442 | return -EINVAL; | |
13443 | } | |
13444 | ||
13445 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13446 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13447 | if (ret) | |
13448 | return ret; | |
7580d774 ML |
13449 | |
13450 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13451 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13452 | } |
13453 | ||
f935675f ML |
13454 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13455 | if (ret) | |
13456 | return ret; | |
13457 | ||
5008e874 | 13458 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13459 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13460 | u32 reset_counter; | |
13461 | ||
13462 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13463 | mutex_unlock(&dev->struct_mutex); | |
13464 | ||
13465 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13466 | struct intel_plane_state *intel_plane_state = | |
13467 | to_intel_plane_state(plane_state); | |
13468 | ||
13469 | if (!intel_plane_state->wait_req) | |
13470 | continue; | |
13471 | ||
13472 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13473 | reset_counter, true, | |
13474 | NULL, NULL); | |
13475 | ||
13476 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13477 | if (ret == -EIO) | |
13478 | ret = 0; | |
13479 | ||
13480 | if (ret) | |
13481 | break; | |
13482 | } | |
13483 | ||
13484 | if (!ret) | |
13485 | return 0; | |
13486 | ||
13487 | mutex_lock(&dev->struct_mutex); | |
13488 | drm_atomic_helper_cleanup_planes(dev, state); | |
13489 | } | |
5008e874 | 13490 | |
f935675f | 13491 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13492 | return ret; |
13493 | } | |
13494 | ||
74c090b1 ML |
13495 | /** |
13496 | * intel_atomic_commit - commit validated state object | |
13497 | * @dev: DRM device | |
13498 | * @state: the top-level driver state object | |
13499 | * @async: asynchronous commit | |
13500 | * | |
13501 | * This function commits a top-level state object that has been validated | |
13502 | * with drm_atomic_helper_check(). | |
13503 | * | |
13504 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13505 | * we can only handle plane-related operations and do not yet support | |
13506 | * asynchronous commit. | |
13507 | * | |
13508 | * RETURNS | |
13509 | * Zero for success or -errno. | |
13510 | */ | |
13511 | static int intel_atomic_commit(struct drm_device *dev, | |
13512 | struct drm_atomic_state *state, | |
13513 | bool async) | |
a6778b3c | 13514 | { |
565602d7 | 13515 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13516 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13517 | struct drm_crtc_state *crtc_state; |
7580d774 | 13518 | struct drm_crtc *crtc; |
565602d7 ML |
13519 | int ret = 0, i; |
13520 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13521 | |
5008e874 | 13522 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13523 | if (ret) { |
13524 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13525 | return ret; |
7580d774 | 13526 | } |
d4afb8cc | 13527 | |
1c5e19f8 | 13528 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13529 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13530 | |
565602d7 ML |
13531 | if (intel_state->modeset) { |
13532 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13533 | sizeof(intel_state->min_pixclk)); | |
13534 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13535 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13536 | } |
13537 | ||
0a9ab303 | 13538 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13539 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13540 | ||
61333b60 ML |
13541 | if (!needs_modeset(crtc->state)) |
13542 | continue; | |
13543 | ||
a539205a | 13544 | intel_pre_plane_update(intel_crtc); |
460da916 | 13545 | |
a539205a ML |
13546 | if (crtc_state->active) { |
13547 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13548 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13549 | intel_crtc->active = false; |
13550 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13551 | |
13552 | /* | |
13553 | * Underruns don't always raise | |
13554 | * interrupts, so check manually. | |
13555 | */ | |
13556 | intel_check_cpu_fifo_underruns(dev_priv); | |
13557 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13558 | |
13559 | if (!crtc->state->active) | |
13560 | intel_update_watermarks(crtc); | |
a539205a | 13561 | } |
b8cecdf5 | 13562 | } |
7758a113 | 13563 | |
ea9d758d DV |
13564 | /* Only after disabling all output pipelines that will be changed can we |
13565 | * update the the output configuration. */ | |
4740b0f2 | 13566 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13567 | |
565602d7 | 13568 | if (intel_state->modeset) { |
4740b0f2 ML |
13569 | intel_shared_dpll_commit(state); |
13570 | ||
13571 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13572 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13573 | } |
47fab737 | 13574 | |
a6778b3c | 13575 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13576 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13577 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13578 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13579 | bool update_pipe = !modeset && |
13580 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13581 | unsigned long put_domains = 0; | |
f6ac4b2a | 13582 | |
9f836f90 PJ |
13583 | if (modeset) |
13584 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13585 | ||
f6ac4b2a | 13586 | if (modeset && crtc->state->active) { |
a539205a ML |
13587 | update_scanline_offset(to_intel_crtc(crtc)); |
13588 | dev_priv->display.crtc_enable(crtc); | |
13589 | } | |
80715b2f | 13590 | |
bfd16b2a ML |
13591 | if (update_pipe) { |
13592 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13593 | ||
13594 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13595 | hw_check = true; |
bfd16b2a ML |
13596 | } |
13597 | ||
f6ac4b2a ML |
13598 | if (!modeset) |
13599 | intel_pre_plane_update(intel_crtc); | |
13600 | ||
6173ee28 ML |
13601 | if (crtc->state->active && |
13602 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13603 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13604 | |
13605 | if (put_domains) | |
13606 | modeset_put_power_domains(dev_priv, put_domains); | |
13607 | ||
f6ac4b2a | 13608 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13609 | |
13610 | if (modeset) | |
13611 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13612 | } |
a6778b3c | 13613 | |
a6778b3c | 13614 | /* FIXME: add subpixel order */ |
83a57153 | 13615 | |
74c090b1 | 13616 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13617 | |
13618 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13619 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13620 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13621 | |
565602d7 | 13622 | if (hw_check) |
ee165b1a ML |
13623 | intel_modeset_check_state(dev, state); |
13624 | ||
13625 | drm_atomic_state_free(state); | |
f30da187 | 13626 | |
74c090b1 | 13627 | return 0; |
7f27126e JB |
13628 | } |
13629 | ||
c0c36b94 CW |
13630 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13631 | { | |
83a57153 ACO |
13632 | struct drm_device *dev = crtc->dev; |
13633 | struct drm_atomic_state *state; | |
e694eb02 | 13634 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13635 | int ret; |
83a57153 ACO |
13636 | |
13637 | state = drm_atomic_state_alloc(dev); | |
13638 | if (!state) { | |
e694eb02 | 13639 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13640 | crtc->base.id); |
13641 | return; | |
13642 | } | |
13643 | ||
e694eb02 | 13644 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13645 | |
e694eb02 ML |
13646 | retry: |
13647 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13648 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13649 | if (!ret) { | |
13650 | if (!crtc_state->active) | |
13651 | goto out; | |
83a57153 | 13652 | |
e694eb02 | 13653 | crtc_state->mode_changed = true; |
74c090b1 | 13654 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13655 | } |
13656 | ||
e694eb02 ML |
13657 | if (ret == -EDEADLK) { |
13658 | drm_atomic_state_clear(state); | |
13659 | drm_modeset_backoff(state->acquire_ctx); | |
13660 | goto retry; | |
4ed9fb37 | 13661 | } |
4be07317 | 13662 | |
2bfb4627 | 13663 | if (ret) |
e694eb02 | 13664 | out: |
2bfb4627 | 13665 | drm_atomic_state_free(state); |
c0c36b94 CW |
13666 | } |
13667 | ||
25c5b266 DV |
13668 | #undef for_each_intel_crtc_masked |
13669 | ||
f6e5b160 | 13670 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13671 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13672 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13673 | .destroy = intel_crtc_destroy, |
13674 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13675 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13676 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13677 | }; |
13678 | ||
5358901f DV |
13679 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13680 | struct intel_shared_dpll *pll, | |
13681 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13682 | { |
5358901f | 13683 | uint32_t val; |
ee7b9f93 | 13684 | |
f458ebbc | 13685 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13686 | return false; |
13687 | ||
5358901f | 13688 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13689 | hw_state->dpll = val; |
13690 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13691 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13692 | |
13693 | return val & DPLL_VCO_ENABLE; | |
13694 | } | |
13695 | ||
15bdd4cf DV |
13696 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13697 | struct intel_shared_dpll *pll) | |
13698 | { | |
3e369b76 ACO |
13699 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13700 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13701 | } |
13702 | ||
e7b903d2 DV |
13703 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13704 | struct intel_shared_dpll *pll) | |
13705 | { | |
e7b903d2 | 13706 | /* PCH refclock must be enabled first */ |
89eff4be | 13707 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13708 | |
3e369b76 | 13709 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13710 | |
13711 | /* Wait for the clocks to stabilize. */ | |
13712 | POSTING_READ(PCH_DPLL(pll->id)); | |
13713 | udelay(150); | |
13714 | ||
13715 | /* The pixel multiplier can only be updated once the | |
13716 | * DPLL is enabled and the clocks are stable. | |
13717 | * | |
13718 | * So write it again. | |
13719 | */ | |
3e369b76 | 13720 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13721 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13722 | udelay(200); |
13723 | } | |
13724 | ||
13725 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13726 | struct intel_shared_dpll *pll) | |
13727 | { | |
13728 | struct drm_device *dev = dev_priv->dev; | |
13729 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13730 | |
13731 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13732 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13733 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13734 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13735 | } |
13736 | ||
15bdd4cf DV |
13737 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13738 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13739 | udelay(200); |
13740 | } | |
13741 | ||
46edb027 DV |
13742 | static char *ibx_pch_dpll_names[] = { |
13743 | "PCH DPLL A", | |
13744 | "PCH DPLL B", | |
13745 | }; | |
13746 | ||
7c74ade1 | 13747 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13748 | { |
e7b903d2 | 13749 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13750 | int i; |
13751 | ||
7c74ade1 | 13752 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13753 | |
e72f9fbf | 13754 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13755 | dev_priv->shared_dplls[i].id = i; |
13756 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13757 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13758 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13759 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13760 | dev_priv->shared_dplls[i].get_hw_state = |
13761 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13762 | } |
13763 | } | |
13764 | ||
7c74ade1 DV |
13765 | static void intel_shared_dpll_init(struct drm_device *dev) |
13766 | { | |
e7b903d2 | 13767 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13768 | |
9cd86933 DV |
13769 | if (HAS_DDI(dev)) |
13770 | intel_ddi_pll_init(dev); | |
13771 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13772 | ibx_pch_dpll_init(dev); |
13773 | else | |
13774 | dev_priv->num_shared_dpll = 0; | |
13775 | ||
13776 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13777 | } |
13778 | ||
6beb8c23 MR |
13779 | /** |
13780 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13781 | * @plane: drm plane to prepare for | |
13782 | * @fb: framebuffer to prepare for presentation | |
13783 | * | |
13784 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13785 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13786 | * bits. Some older platforms need special physical address handling for | |
13787 | * cursor planes. | |
13788 | * | |
f935675f ML |
13789 | * Must be called with struct_mutex held. |
13790 | * | |
6beb8c23 MR |
13791 | * Returns 0 on success, negative error code on failure. |
13792 | */ | |
13793 | int | |
13794 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13795 | const struct drm_plane_state *new_state) |
465c120c MR |
13796 | { |
13797 | struct drm_device *dev = plane->dev; | |
844f9111 | 13798 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13799 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13800 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13801 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13802 | int ret = 0; |
465c120c | 13803 | |
1ee49399 | 13804 | if (!obj && !old_obj) |
465c120c MR |
13805 | return 0; |
13806 | ||
5008e874 ML |
13807 | if (old_obj) { |
13808 | struct drm_crtc_state *crtc_state = | |
13809 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13810 | ||
13811 | /* Big Hammer, we also need to ensure that any pending | |
13812 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13813 | * current scanout is retired before unpinning the old | |
13814 | * framebuffer. Note that we rely on userspace rendering | |
13815 | * into the buffer attached to the pipe they are waiting | |
13816 | * on. If not, userspace generates a GPU hang with IPEHR | |
13817 | * point to the MI_WAIT_FOR_EVENT. | |
13818 | * | |
13819 | * This should only fail upon a hung GPU, in which case we | |
13820 | * can safely continue. | |
13821 | */ | |
13822 | if (needs_modeset(crtc_state)) | |
13823 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13824 | ||
13825 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13826 | if (ret && ret != -EIO) | |
f935675f | 13827 | return ret; |
5008e874 ML |
13828 | } |
13829 | ||
3c28ff22 AG |
13830 | /* For framebuffer backed by dmabuf, wait for fence */ |
13831 | if (obj && obj->base.dma_buf) { | |
13832 | ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13833 | false, true, | |
13834 | MAX_SCHEDULE_TIMEOUT); | |
13835 | if (ret == -ERESTARTSYS) | |
13836 | return ret; | |
13837 | ||
13838 | WARN_ON(ret < 0); | |
13839 | } | |
13840 | ||
1ee49399 ML |
13841 | if (!obj) { |
13842 | ret = 0; | |
13843 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13844 | INTEL_INFO(dev)->cursor_needs_physical) { |
13845 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13846 | ret = i915_gem_object_attach_phys(obj, align); | |
13847 | if (ret) | |
13848 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13849 | } else { | |
7580d774 | 13850 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13851 | } |
465c120c | 13852 | |
7580d774 ML |
13853 | if (ret == 0) { |
13854 | if (obj) { | |
13855 | struct intel_plane_state *plane_state = | |
13856 | to_intel_plane_state(new_state); | |
13857 | ||
13858 | i915_gem_request_assign(&plane_state->wait_req, | |
13859 | obj->last_write_req); | |
13860 | } | |
13861 | ||
a9ff8714 | 13862 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13863 | } |
fdd508a6 | 13864 | |
6beb8c23 MR |
13865 | return ret; |
13866 | } | |
13867 | ||
38f3ce3a MR |
13868 | /** |
13869 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13870 | * @plane: drm plane to clean up for | |
13871 | * @fb: old framebuffer that was on plane | |
13872 | * | |
13873 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13874 | * |
13875 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13876 | */ |
13877 | void | |
13878 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13879 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13880 | { |
13881 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13882 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13883 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13884 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13885 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13886 | |
7580d774 ML |
13887 | old_intel_state = to_intel_plane_state(old_state); |
13888 | ||
1ee49399 | 13889 | if (!obj && !old_obj) |
38f3ce3a MR |
13890 | return; |
13891 | ||
1ee49399 ML |
13892 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13893 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13894 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13895 | |
13896 | /* prepare_fb aborted? */ | |
13897 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13898 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13899 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13900 | |
13901 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13902 | ||
465c120c MR |
13903 | } |
13904 | ||
6156a456 CK |
13905 | int |
13906 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13907 | { | |
13908 | int max_scale; | |
13909 | struct drm_device *dev; | |
13910 | struct drm_i915_private *dev_priv; | |
13911 | int crtc_clock, cdclk; | |
13912 | ||
bf8a0af0 | 13913 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13914 | return DRM_PLANE_HELPER_NO_SCALING; |
13915 | ||
13916 | dev = intel_crtc->base.dev; | |
13917 | dev_priv = dev->dev_private; | |
13918 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13919 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13920 | |
54bf1ce6 | 13921 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13922 | return DRM_PLANE_HELPER_NO_SCALING; |
13923 | ||
13924 | /* | |
13925 | * skl max scale is lower of: | |
13926 | * close to 3 but not 3, -1 is for that purpose | |
13927 | * or | |
13928 | * cdclk/crtc_clock | |
13929 | */ | |
13930 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13931 | ||
13932 | return max_scale; | |
13933 | } | |
13934 | ||
465c120c | 13935 | static int |
3c692a41 | 13936 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13937 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13938 | struct intel_plane_state *state) |
13939 | { | |
2b875c22 MR |
13940 | struct drm_crtc *crtc = state->base.crtc; |
13941 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13942 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13943 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13944 | bool can_position = false; | |
465c120c | 13945 | |
061e4b8d ML |
13946 | /* use scaler when colorkey is not required */ |
13947 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13948 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13949 | min_scale = 1; |
13950 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13951 | can_position = true; |
6156a456 | 13952 | } |
d8106366 | 13953 | |
061e4b8d ML |
13954 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13955 | &state->dst, &state->clip, | |
da20eabd ML |
13956 | min_scale, max_scale, |
13957 | can_position, true, | |
13958 | &state->visible); | |
14af293f GP |
13959 | } |
13960 | ||
13961 | static void | |
13962 | intel_commit_primary_plane(struct drm_plane *plane, | |
13963 | struct intel_plane_state *state) | |
13964 | { | |
2b875c22 MR |
13965 | struct drm_crtc *crtc = state->base.crtc; |
13966 | struct drm_framebuffer *fb = state->base.fb; | |
13967 | struct drm_device *dev = plane->dev; | |
14af293f | 13968 | struct drm_i915_private *dev_priv = dev->dev_private; |
14af293f | 13969 | |
ea2c67bb | 13970 | crtc = crtc ? crtc : plane->crtc; |
ccc759dc | 13971 | |
d4b08630 ML |
13972 | dev_priv->display.update_primary_plane(crtc, fb, |
13973 | state->src.x1 >> 16, | |
13974 | state->src.y1 >> 16); | |
465c120c MR |
13975 | } |
13976 | ||
a8ad0d8e ML |
13977 | static void |
13978 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13979 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13980 | { |
13981 | struct drm_device *dev = plane->dev; | |
13982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13983 | ||
a8ad0d8e ML |
13984 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13985 | } | |
13986 | ||
613d2b27 ML |
13987 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13988 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13989 | { |
32b7eeec | 13990 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13991 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13992 | struct intel_crtc_state *old_intel_state = |
13993 | to_intel_crtc_state(old_crtc_state); | |
13994 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13995 | |
c34c9ee4 | 13996 | /* Perform vblank evasion around commit operation */ |
62852622 | 13997 | intel_pipe_update_start(intel_crtc); |
0583236e | 13998 | |
bfd16b2a ML |
13999 | if (modeset) |
14000 | return; | |
14001 | ||
14002 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14003 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14004 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14005 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14006 | } |
14007 | ||
613d2b27 ML |
14008 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14009 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14010 | { |
32b7eeec | 14011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14012 | |
62852622 | 14013 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14014 | } |
14015 | ||
cf4c7c12 | 14016 | /** |
4a3b8769 MR |
14017 | * intel_plane_destroy - destroy a plane |
14018 | * @plane: plane to destroy | |
cf4c7c12 | 14019 | * |
4a3b8769 MR |
14020 | * Common destruction function for all types of planes (primary, cursor, |
14021 | * sprite). | |
cf4c7c12 | 14022 | */ |
4a3b8769 | 14023 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14024 | { |
14025 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14026 | drm_plane_cleanup(plane); | |
14027 | kfree(intel_plane); | |
14028 | } | |
14029 | ||
65a3fea0 | 14030 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14031 | .update_plane = drm_atomic_helper_update_plane, |
14032 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14033 | .destroy = intel_plane_destroy, |
c196e1d6 | 14034 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14035 | .atomic_get_property = intel_plane_atomic_get_property, |
14036 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14037 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14038 | .atomic_destroy_state = intel_plane_destroy_state, | |
14039 | ||
465c120c MR |
14040 | }; |
14041 | ||
14042 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14043 | int pipe) | |
14044 | { | |
14045 | struct intel_plane *primary; | |
8e7d688b | 14046 | struct intel_plane_state *state; |
465c120c | 14047 | const uint32_t *intel_primary_formats; |
45e3743a | 14048 | unsigned int num_formats; |
465c120c MR |
14049 | |
14050 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14051 | if (primary == NULL) | |
14052 | return NULL; | |
14053 | ||
8e7d688b MR |
14054 | state = intel_create_plane_state(&primary->base); |
14055 | if (!state) { | |
ea2c67bb MR |
14056 | kfree(primary); |
14057 | return NULL; | |
14058 | } | |
8e7d688b | 14059 | primary->base.state = &state->base; |
ea2c67bb | 14060 | |
465c120c MR |
14061 | primary->can_scale = false; |
14062 | primary->max_downscale = 1; | |
6156a456 CK |
14063 | if (INTEL_INFO(dev)->gen >= 9) { |
14064 | primary->can_scale = true; | |
af99ceda | 14065 | state->scaler_id = -1; |
6156a456 | 14066 | } |
465c120c MR |
14067 | primary->pipe = pipe; |
14068 | primary->plane = pipe; | |
a9ff8714 | 14069 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
14070 | primary->check_plane = intel_check_primary_plane; |
14071 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 14072 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
14073 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14074 | primary->plane = !pipe; | |
14075 | ||
6c0fd451 DL |
14076 | if (INTEL_INFO(dev)->gen >= 9) { |
14077 | intel_primary_formats = skl_primary_formats; | |
14078 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
14079 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
14080 | intel_primary_formats = i965_primary_formats; |
14081 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
14082 | } else { |
14083 | intel_primary_formats = i8xx_primary_formats; | |
14084 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
14085 | } |
14086 | ||
14087 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14088 | &intel_plane_funcs, |
465c120c MR |
14089 | intel_primary_formats, num_formats, |
14090 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 14091 | |
3b7a5119 SJ |
14092 | if (INTEL_INFO(dev)->gen >= 4) |
14093 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14094 | |
ea2c67bb MR |
14095 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14096 | ||
465c120c MR |
14097 | return &primary->base; |
14098 | } | |
14099 | ||
3b7a5119 SJ |
14100 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14101 | { | |
14102 | if (!dev->mode_config.rotation_property) { | |
14103 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14104 | BIT(DRM_ROTATE_180); | |
14105 | ||
14106 | if (INTEL_INFO(dev)->gen >= 9) | |
14107 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14108 | ||
14109 | dev->mode_config.rotation_property = | |
14110 | drm_mode_create_rotation_property(dev, flags); | |
14111 | } | |
14112 | if (dev->mode_config.rotation_property) | |
14113 | drm_object_attach_property(&plane->base.base, | |
14114 | dev->mode_config.rotation_property, | |
14115 | plane->base.state->rotation); | |
14116 | } | |
14117 | ||
3d7d6510 | 14118 | static int |
852e787c | 14119 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14120 | struct intel_crtc_state *crtc_state, |
852e787c | 14121 | struct intel_plane_state *state) |
3d7d6510 | 14122 | { |
061e4b8d | 14123 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14124 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14125 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14126 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14127 | unsigned stride; |
14128 | int ret; | |
3d7d6510 | 14129 | |
061e4b8d ML |
14130 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14131 | &state->dst, &state->clip, | |
3d7d6510 MR |
14132 | DRM_PLANE_HELPER_NO_SCALING, |
14133 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14134 | true, true, &state->visible); |
757f9a3e GP |
14135 | if (ret) |
14136 | return ret; | |
14137 | ||
757f9a3e GP |
14138 | /* if we want to turn off the cursor ignore width and height */ |
14139 | if (!obj) | |
da20eabd | 14140 | return 0; |
757f9a3e | 14141 | |
757f9a3e | 14142 | /* Check for which cursor types we support */ |
061e4b8d | 14143 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14144 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14145 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14146 | return -EINVAL; |
14147 | } | |
14148 | ||
ea2c67bb MR |
14149 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14150 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14151 | DRM_DEBUG_KMS("buffer is too small\n"); |
14152 | return -ENOMEM; | |
14153 | } | |
14154 | ||
3a656b54 | 14155 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14156 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14157 | return -EINVAL; |
32b7eeec MR |
14158 | } |
14159 | ||
b29ec92c VS |
14160 | /* |
14161 | * There's something wrong with the cursor on CHV pipe C. | |
14162 | * If it straddles the left edge of the screen then | |
14163 | * moving it away from the edge or disabling it often | |
14164 | * results in a pipe underrun, and often that can lead to | |
14165 | * dead pipe (constant underrun reported, and it scans | |
14166 | * out just a solid color). To recover from that, the | |
14167 | * display power well must be turned off and on again. | |
14168 | * Refuse the put the cursor into that compromised position. | |
14169 | */ | |
14170 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14171 | state->visible && state->base.crtc_x < 0) { | |
14172 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14173 | return -EINVAL; | |
14174 | } | |
14175 | ||
da20eabd | 14176 | return 0; |
852e787c | 14177 | } |
3d7d6510 | 14178 | |
a8ad0d8e ML |
14179 | static void |
14180 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14181 | struct drm_crtc *crtc) |
a8ad0d8e | 14182 | { |
a8ad0d8e ML |
14183 | intel_crtc_update_cursor(crtc, false); |
14184 | } | |
14185 | ||
f4a2cf29 | 14186 | static void |
852e787c GP |
14187 | intel_commit_cursor_plane(struct drm_plane *plane, |
14188 | struct intel_plane_state *state) | |
14189 | { | |
2b875c22 | 14190 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
14191 | struct drm_device *dev = plane->dev; |
14192 | struct intel_crtc *intel_crtc; | |
2b875c22 | 14193 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14194 | uint32_t addr; |
852e787c | 14195 | |
ea2c67bb MR |
14196 | crtc = crtc ? crtc : plane->crtc; |
14197 | intel_crtc = to_intel_crtc(crtc); | |
14198 | ||
f4a2cf29 | 14199 | if (!obj) |
a912f12f | 14200 | addr = 0; |
f4a2cf29 | 14201 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14202 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14203 | else |
a912f12f | 14204 | addr = obj->phys_handle->busaddr; |
852e787c | 14205 | |
a912f12f | 14206 | intel_crtc->cursor_addr = addr; |
852e787c | 14207 | |
62852622 | 14208 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14209 | } |
14210 | ||
3d7d6510 MR |
14211 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14212 | int pipe) | |
14213 | { | |
14214 | struct intel_plane *cursor; | |
8e7d688b | 14215 | struct intel_plane_state *state; |
3d7d6510 MR |
14216 | |
14217 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14218 | if (cursor == NULL) | |
14219 | return NULL; | |
14220 | ||
8e7d688b MR |
14221 | state = intel_create_plane_state(&cursor->base); |
14222 | if (!state) { | |
ea2c67bb MR |
14223 | kfree(cursor); |
14224 | return NULL; | |
14225 | } | |
8e7d688b | 14226 | cursor->base.state = &state->base; |
ea2c67bb | 14227 | |
3d7d6510 MR |
14228 | cursor->can_scale = false; |
14229 | cursor->max_downscale = 1; | |
14230 | cursor->pipe = pipe; | |
14231 | cursor->plane = pipe; | |
a9ff8714 | 14232 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14233 | cursor->check_plane = intel_check_cursor_plane; |
14234 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14235 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14236 | |
14237 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14238 | &intel_plane_funcs, |
3d7d6510 MR |
14239 | intel_cursor_formats, |
14240 | ARRAY_SIZE(intel_cursor_formats), | |
14241 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14242 | |
14243 | if (INTEL_INFO(dev)->gen >= 4) { | |
14244 | if (!dev->mode_config.rotation_property) | |
14245 | dev->mode_config.rotation_property = | |
14246 | drm_mode_create_rotation_property(dev, | |
14247 | BIT(DRM_ROTATE_0) | | |
14248 | BIT(DRM_ROTATE_180)); | |
14249 | if (dev->mode_config.rotation_property) | |
14250 | drm_object_attach_property(&cursor->base.base, | |
14251 | dev->mode_config.rotation_property, | |
8e7d688b | 14252 | state->base.rotation); |
4398ad45 VS |
14253 | } |
14254 | ||
af99ceda CK |
14255 | if (INTEL_INFO(dev)->gen >=9) |
14256 | state->scaler_id = -1; | |
14257 | ||
ea2c67bb MR |
14258 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14259 | ||
3d7d6510 MR |
14260 | return &cursor->base; |
14261 | } | |
14262 | ||
549e2bfb CK |
14263 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14264 | struct intel_crtc_state *crtc_state) | |
14265 | { | |
14266 | int i; | |
14267 | struct intel_scaler *intel_scaler; | |
14268 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14269 | ||
14270 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14271 | intel_scaler = &scaler_state->scalers[i]; | |
14272 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14273 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14274 | } | |
14275 | ||
14276 | scaler_state->scaler_id = -1; | |
14277 | } | |
14278 | ||
b358d0a6 | 14279 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14280 | { |
fbee40df | 14281 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14282 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14283 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14284 | struct drm_plane *primary = NULL; |
14285 | struct drm_plane *cursor = NULL; | |
465c120c | 14286 | int i, ret; |
79e53945 | 14287 | |
955382f3 | 14288 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14289 | if (intel_crtc == NULL) |
14290 | return; | |
14291 | ||
f5de6e07 ACO |
14292 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14293 | if (!crtc_state) | |
14294 | goto fail; | |
550acefd ACO |
14295 | intel_crtc->config = crtc_state; |
14296 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14297 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14298 | |
549e2bfb CK |
14299 | /* initialize shared scalers */ |
14300 | if (INTEL_INFO(dev)->gen >= 9) { | |
14301 | if (pipe == PIPE_C) | |
14302 | intel_crtc->num_scalers = 1; | |
14303 | else | |
14304 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14305 | ||
14306 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14307 | } | |
14308 | ||
465c120c | 14309 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14310 | if (!primary) |
14311 | goto fail; | |
14312 | ||
14313 | cursor = intel_cursor_plane_create(dev, pipe); | |
14314 | if (!cursor) | |
14315 | goto fail; | |
14316 | ||
465c120c | 14317 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14318 | cursor, &intel_crtc_funcs); |
14319 | if (ret) | |
14320 | goto fail; | |
79e53945 JB |
14321 | |
14322 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14323 | for (i = 0; i < 256; i++) { |
14324 | intel_crtc->lut_r[i] = i; | |
14325 | intel_crtc->lut_g[i] = i; | |
14326 | intel_crtc->lut_b[i] = i; | |
14327 | } | |
14328 | ||
1f1c2e24 VS |
14329 | /* |
14330 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14331 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14332 | */ |
80824003 JB |
14333 | intel_crtc->pipe = pipe; |
14334 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14335 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14336 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14337 | intel_crtc->plane = !pipe; |
80824003 JB |
14338 | } |
14339 | ||
4b0e333e CW |
14340 | intel_crtc->cursor_base = ~0; |
14341 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14342 | intel_crtc->cursor_size = ~0; |
8d7849db | 14343 | |
852eb00d VS |
14344 | intel_crtc->wm.cxsr_allowed = true; |
14345 | ||
22fd0fab JB |
14346 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14347 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14348 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14349 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14350 | ||
79e53945 | 14351 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14352 | |
14353 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14354 | return; |
14355 | ||
14356 | fail: | |
14357 | if (primary) | |
14358 | drm_plane_cleanup(primary); | |
14359 | if (cursor) | |
14360 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14361 | kfree(crtc_state); |
3d7d6510 | 14362 | kfree(intel_crtc); |
79e53945 JB |
14363 | } |
14364 | ||
752aa88a JB |
14365 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14366 | { | |
14367 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14368 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14369 | |
51fd371b | 14370 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14371 | |
d3babd3f | 14372 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14373 | return INVALID_PIPE; |
14374 | ||
14375 | return to_intel_crtc(encoder->crtc)->pipe; | |
14376 | } | |
14377 | ||
08d7b3d1 | 14378 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14379 | struct drm_file *file) |
08d7b3d1 | 14380 | { |
08d7b3d1 | 14381 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14382 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14383 | struct intel_crtc *crtc; |
08d7b3d1 | 14384 | |
7707e653 | 14385 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14386 | |
7707e653 | 14387 | if (!drmmode_crtc) { |
08d7b3d1 | 14388 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14389 | return -ENOENT; |
08d7b3d1 CW |
14390 | } |
14391 | ||
7707e653 | 14392 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14393 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14394 | |
c05422d5 | 14395 | return 0; |
08d7b3d1 CW |
14396 | } |
14397 | ||
66a9278e | 14398 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14399 | { |
66a9278e DV |
14400 | struct drm_device *dev = encoder->base.dev; |
14401 | struct intel_encoder *source_encoder; | |
79e53945 | 14402 | int index_mask = 0; |
79e53945 JB |
14403 | int entry = 0; |
14404 | ||
b2784e15 | 14405 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14406 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14407 | index_mask |= (1 << entry); |
14408 | ||
79e53945 JB |
14409 | entry++; |
14410 | } | |
4ef69c7a | 14411 | |
79e53945 JB |
14412 | return index_mask; |
14413 | } | |
14414 | ||
4d302442 CW |
14415 | static bool has_edp_a(struct drm_device *dev) |
14416 | { | |
14417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14418 | ||
14419 | if (!IS_MOBILE(dev)) | |
14420 | return false; | |
14421 | ||
14422 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14423 | return false; | |
14424 | ||
e3589908 | 14425 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14426 | return false; |
14427 | ||
14428 | return true; | |
14429 | } | |
14430 | ||
84b4e042 JB |
14431 | static bool intel_crt_present(struct drm_device *dev) |
14432 | { | |
14433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14434 | ||
884497ed DL |
14435 | if (INTEL_INFO(dev)->gen >= 9) |
14436 | return false; | |
14437 | ||
cf404ce4 | 14438 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14439 | return false; |
14440 | ||
14441 | if (IS_CHERRYVIEW(dev)) | |
14442 | return false; | |
14443 | ||
65e472e4 VS |
14444 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14445 | return false; | |
14446 | ||
70ac54d0 VS |
14447 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14448 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14449 | return false; | |
14450 | ||
e4abb733 | 14451 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14452 | return false; |
14453 | ||
14454 | return true; | |
14455 | } | |
14456 | ||
79e53945 JB |
14457 | static void intel_setup_outputs(struct drm_device *dev) |
14458 | { | |
725e30ad | 14459 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14460 | struct intel_encoder *encoder; |
cb0953d7 | 14461 | bool dpd_is_edp = false; |
79e53945 | 14462 | |
c9093354 | 14463 | intel_lvds_init(dev); |
79e53945 | 14464 | |
84b4e042 | 14465 | if (intel_crt_present(dev)) |
79935fca | 14466 | intel_crt_init(dev); |
cb0953d7 | 14467 | |
c776eb2e VK |
14468 | if (IS_BROXTON(dev)) { |
14469 | /* | |
14470 | * FIXME: Broxton doesn't support port detection via the | |
14471 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14472 | * detect the ports. | |
14473 | */ | |
14474 | intel_ddi_init(dev, PORT_A); | |
14475 | intel_ddi_init(dev, PORT_B); | |
14476 | intel_ddi_init(dev, PORT_C); | |
14477 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14478 | int found; |
14479 | ||
de31facd JB |
14480 | /* |
14481 | * Haswell uses DDI functions to detect digital outputs. | |
14482 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14483 | * it's there. | |
14484 | */ | |
77179400 | 14485 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14486 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14487 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14488 | intel_ddi_init(dev, PORT_A); |
14489 | ||
14490 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14491 | * register */ | |
14492 | found = I915_READ(SFUSE_STRAP); | |
14493 | ||
14494 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14495 | intel_ddi_init(dev, PORT_B); | |
14496 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14497 | intel_ddi_init(dev, PORT_C); | |
14498 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14499 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14500 | /* |
14501 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14502 | */ | |
ef11bdb3 | 14503 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14504 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14505 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14506 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14507 | intel_ddi_init(dev, PORT_E); | |
14508 | ||
0e72a5b5 | 14509 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14510 | int found; |
5d8a7752 | 14511 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14512 | |
14513 | if (has_edp_a(dev)) | |
14514 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14515 | |
dc0fa718 | 14516 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14517 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14518 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14519 | if (!found) |
e2debe91 | 14520 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14521 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14522 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14523 | } |
14524 | ||
dc0fa718 | 14525 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14526 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14527 | |
dc0fa718 | 14528 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14529 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14530 | |
5eb08b69 | 14531 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14532 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14533 | |
270b3042 | 14534 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14535 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14536 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14537 | /* |
14538 | * The DP_DETECTED bit is the latched state of the DDC | |
14539 | * SDA pin at boot. However since eDP doesn't require DDC | |
14540 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14541 | * eDP ports may have been muxed to an alternate function. | |
14542 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14543 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14544 | * detect eDP ports. | |
14545 | */ | |
e66eb81d | 14546 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14547 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14548 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14549 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14550 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14551 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14552 | |
e66eb81d | 14553 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14554 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14555 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14556 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14557 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14558 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14559 | |
9418c1f1 | 14560 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14561 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14562 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14563 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14564 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14565 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14566 | } |
14567 | ||
3cfca973 | 14568 | intel_dsi_init(dev); |
09da55dc | 14569 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14570 | bool found = false; |
7d57382e | 14571 | |
e2debe91 | 14572 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14573 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14574 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14575 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14576 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14577 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14578 | } |
27185ae1 | 14579 | |
3fec3d2f | 14580 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14581 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14582 | } |
13520b05 KH |
14583 | |
14584 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14585 | |
e2debe91 | 14586 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14587 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14588 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14589 | } |
27185ae1 | 14590 | |
e2debe91 | 14591 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14592 | |
3fec3d2f | 14593 | if (IS_G4X(dev)) { |
b01f2c3a | 14594 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14595 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14596 | } |
3fec3d2f | 14597 | if (IS_G4X(dev)) |
ab9d7c30 | 14598 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14599 | } |
27185ae1 | 14600 | |
3fec3d2f | 14601 | if (IS_G4X(dev) && |
e7281eab | 14602 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14603 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14604 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14605 | intel_dvo_init(dev); |
14606 | ||
103a196f | 14607 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14608 | intel_tv_init(dev); |
14609 | ||
0bc12bcb | 14610 | intel_psr_init(dev); |
7c8f8a70 | 14611 | |
b2784e15 | 14612 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14613 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14614 | encoder->base.possible_clones = | |
66a9278e | 14615 | intel_encoder_clones(encoder); |
79e53945 | 14616 | } |
47356eb6 | 14617 | |
dde86e2d | 14618 | intel_init_pch_refclk(dev); |
270b3042 DV |
14619 | |
14620 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14621 | } |
14622 | ||
14623 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14624 | { | |
60a5ca01 | 14625 | struct drm_device *dev = fb->dev; |
79e53945 | 14626 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14627 | |
ef2d633e | 14628 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14629 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14630 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14631 | drm_gem_object_unreference(&intel_fb->obj->base); |
14632 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14633 | kfree(intel_fb); |
14634 | } | |
14635 | ||
14636 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14637 | struct drm_file *file, |
79e53945 JB |
14638 | unsigned int *handle) |
14639 | { | |
14640 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14641 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14642 | |
cc917ab4 CW |
14643 | if (obj->userptr.mm) { |
14644 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14645 | return -EINVAL; | |
14646 | } | |
14647 | ||
05394f39 | 14648 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14649 | } |
14650 | ||
86c98588 RV |
14651 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14652 | struct drm_file *file, | |
14653 | unsigned flags, unsigned color, | |
14654 | struct drm_clip_rect *clips, | |
14655 | unsigned num_clips) | |
14656 | { | |
14657 | struct drm_device *dev = fb->dev; | |
14658 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14659 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14660 | ||
14661 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14662 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14663 | mutex_unlock(&dev->struct_mutex); |
14664 | ||
14665 | return 0; | |
14666 | } | |
14667 | ||
79e53945 JB |
14668 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14669 | .destroy = intel_user_framebuffer_destroy, | |
14670 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14671 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14672 | }; |
14673 | ||
b321803d DL |
14674 | static |
14675 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14676 | uint32_t pixel_format) | |
14677 | { | |
14678 | u32 gen = INTEL_INFO(dev)->gen; | |
14679 | ||
14680 | if (gen >= 9) { | |
14681 | /* "The stride in bytes must not exceed the of the size of 8K | |
14682 | * pixels and 32K bytes." | |
14683 | */ | |
14684 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
666a4537 | 14685 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14686 | return 32*1024; |
14687 | } else if (gen >= 4) { | |
14688 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14689 | return 16*1024; | |
14690 | else | |
14691 | return 32*1024; | |
14692 | } else if (gen >= 3) { | |
14693 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14694 | return 8*1024; | |
14695 | else | |
14696 | return 16*1024; | |
14697 | } else { | |
14698 | /* XXX DSPC is limited to 4k tiled */ | |
14699 | return 8*1024; | |
14700 | } | |
14701 | } | |
14702 | ||
b5ea642a DV |
14703 | static int intel_framebuffer_init(struct drm_device *dev, |
14704 | struct intel_framebuffer *intel_fb, | |
14705 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14706 | struct drm_i915_gem_object *obj) | |
79e53945 | 14707 | { |
6761dd31 | 14708 | unsigned int aligned_height; |
79e53945 | 14709 | int ret; |
b321803d | 14710 | u32 pitch_limit, stride_alignment; |
79e53945 | 14711 | |
dd4916c5 DV |
14712 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14713 | ||
2a80eada DV |
14714 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14715 | /* Enforce that fb modifier and tiling mode match, but only for | |
14716 | * X-tiled. This is needed for FBC. */ | |
14717 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14718 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14719 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14720 | return -EINVAL; | |
14721 | } | |
14722 | } else { | |
14723 | if (obj->tiling_mode == I915_TILING_X) | |
14724 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14725 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14726 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14727 | return -EINVAL; | |
14728 | } | |
14729 | } | |
14730 | ||
9a8f0a12 TU |
14731 | /* Passed in modifier sanity checking. */ |
14732 | switch (mode_cmd->modifier[0]) { | |
14733 | case I915_FORMAT_MOD_Y_TILED: | |
14734 | case I915_FORMAT_MOD_Yf_TILED: | |
14735 | if (INTEL_INFO(dev)->gen < 9) { | |
14736 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14737 | mode_cmd->modifier[0]); | |
14738 | return -EINVAL; | |
14739 | } | |
14740 | case DRM_FORMAT_MOD_NONE: | |
14741 | case I915_FORMAT_MOD_X_TILED: | |
14742 | break; | |
14743 | default: | |
c0f40428 JB |
14744 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14745 | mode_cmd->modifier[0]); | |
57cd6508 | 14746 | return -EINVAL; |
c16ed4be | 14747 | } |
57cd6508 | 14748 | |
b321803d DL |
14749 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14750 | mode_cmd->pixel_format); | |
14751 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14752 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14753 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14754 | return -EINVAL; |
c16ed4be | 14755 | } |
57cd6508 | 14756 | |
b321803d DL |
14757 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14758 | mode_cmd->pixel_format); | |
a35cdaa0 | 14759 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14760 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14761 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14762 | "tiled" : "linear", |
a35cdaa0 | 14763 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14764 | return -EINVAL; |
c16ed4be | 14765 | } |
5d7bd705 | 14766 | |
2a80eada | 14767 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14768 | mode_cmd->pitches[0] != obj->stride) { |
14769 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14770 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14771 | return -EINVAL; |
c16ed4be | 14772 | } |
5d7bd705 | 14773 | |
57779d06 | 14774 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14775 | switch (mode_cmd->pixel_format) { |
57779d06 | 14776 | case DRM_FORMAT_C8: |
04b3924d VS |
14777 | case DRM_FORMAT_RGB565: |
14778 | case DRM_FORMAT_XRGB8888: | |
14779 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14780 | break; |
14781 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14782 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14783 | DRM_DEBUG("unsupported pixel format: %s\n", |
14784 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14785 | return -EINVAL; |
c16ed4be | 14786 | } |
57779d06 | 14787 | break; |
57779d06 | 14788 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14789 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14790 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14791 | DRM_DEBUG("unsupported pixel format: %s\n", |
14792 | drm_get_format_name(mode_cmd->pixel_format)); | |
14793 | return -EINVAL; | |
14794 | } | |
14795 | break; | |
14796 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14797 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14798 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14799 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14800 | DRM_DEBUG("unsupported pixel format: %s\n", |
14801 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14802 | return -EINVAL; |
c16ed4be | 14803 | } |
b5626747 | 14804 | break; |
7531208b | 14805 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14806 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14807 | DRM_DEBUG("unsupported pixel format: %s\n", |
14808 | drm_get_format_name(mode_cmd->pixel_format)); | |
14809 | return -EINVAL; | |
14810 | } | |
14811 | break; | |
04b3924d VS |
14812 | case DRM_FORMAT_YUYV: |
14813 | case DRM_FORMAT_UYVY: | |
14814 | case DRM_FORMAT_YVYU: | |
14815 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14816 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14817 | DRM_DEBUG("unsupported pixel format: %s\n", |
14818 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14819 | return -EINVAL; |
c16ed4be | 14820 | } |
57cd6508 CW |
14821 | break; |
14822 | default: | |
4ee62c76 VS |
14823 | DRM_DEBUG("unsupported pixel format: %s\n", |
14824 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14825 | return -EINVAL; |
14826 | } | |
14827 | ||
90f9a336 VS |
14828 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14829 | if (mode_cmd->offsets[0] != 0) | |
14830 | return -EINVAL; | |
14831 | ||
ec2c981e | 14832 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14833 | mode_cmd->pixel_format, |
14834 | mode_cmd->modifier[0]); | |
53155c0a DV |
14835 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14836 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14837 | return -EINVAL; | |
14838 | ||
c7d73f6a DV |
14839 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14840 | intel_fb->obj = obj; | |
80075d49 | 14841 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14842 | |
79e53945 JB |
14843 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14844 | if (ret) { | |
14845 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14846 | return ret; | |
14847 | } | |
14848 | ||
79e53945 JB |
14849 | return 0; |
14850 | } | |
14851 | ||
79e53945 JB |
14852 | static struct drm_framebuffer * |
14853 | intel_user_framebuffer_create(struct drm_device *dev, | |
14854 | struct drm_file *filp, | |
1eb83451 | 14855 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14856 | { |
dcb1394e | 14857 | struct drm_framebuffer *fb; |
05394f39 | 14858 | struct drm_i915_gem_object *obj; |
76dc3769 | 14859 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14860 | |
308e5bcb | 14861 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14862 | mode_cmd.handles[0])); |
c8725226 | 14863 | if (&obj->base == NULL) |
cce13ff7 | 14864 | return ERR_PTR(-ENOENT); |
79e53945 | 14865 | |
92907cbb | 14866 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14867 | if (IS_ERR(fb)) |
14868 | drm_gem_object_unreference_unlocked(&obj->base); | |
14869 | ||
14870 | return fb; | |
79e53945 JB |
14871 | } |
14872 | ||
0695726e | 14873 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14874 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14875 | { |
14876 | } | |
14877 | #endif | |
14878 | ||
79e53945 | 14879 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14880 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14881 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14882 | .atomic_check = intel_atomic_check, |
14883 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14884 | .atomic_state_alloc = intel_atomic_state_alloc, |
14885 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14886 | }; |
14887 | ||
e70236a8 JB |
14888 | /* Set up chip specific display functions */ |
14889 | static void intel_init_display(struct drm_device *dev) | |
14890 | { | |
14891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14892 | ||
ee9300bb DV |
14893 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14894 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14895 | else if (IS_CHERRYVIEW(dev)) |
14896 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14897 | else if (IS_VALLEYVIEW(dev)) |
14898 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14899 | else if (IS_PINEVIEW(dev)) | |
14900 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14901 | else | |
14902 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14903 | ||
bc8d7dff DL |
14904 | if (INTEL_INFO(dev)->gen >= 9) { |
14905 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14906 | dev_priv->display.get_initial_plane_config = |
14907 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14908 | dev_priv->display.crtc_compute_clock = |
14909 | haswell_crtc_compute_clock; | |
14910 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14911 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14912 | dev_priv->display.update_primary_plane = |
14913 | skylake_update_primary_plane; | |
14914 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14915 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14916 | dev_priv->display.get_initial_plane_config = |
14917 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14918 | dev_priv->display.crtc_compute_clock = |
14919 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14920 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14921 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14922 | dev_priv->display.update_primary_plane = |
14923 | ironlake_update_primary_plane; | |
09b4ddf9 | 14924 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14925 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14926 | dev_priv->display.get_initial_plane_config = |
14927 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14928 | dev_priv->display.crtc_compute_clock = |
14929 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14930 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14931 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14932 | dev_priv->display.update_primary_plane = |
14933 | ironlake_update_primary_plane; | |
666a4537 | 14934 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14935 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14936 | dev_priv->display.get_initial_plane_config = |
14937 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14938 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14939 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14940 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14941 | dev_priv->display.update_primary_plane = |
14942 | i9xx_update_primary_plane; | |
f564048e | 14943 | } else { |
0e8ffe1b | 14944 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14945 | dev_priv->display.get_initial_plane_config = |
14946 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14947 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14948 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14949 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14950 | dev_priv->display.update_primary_plane = |
14951 | i9xx_update_primary_plane; | |
f564048e | 14952 | } |
e70236a8 | 14953 | |
e70236a8 | 14954 | /* Returns the core display clock speed */ |
ef11bdb3 | 14955 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14956 | dev_priv->display.get_display_clock_speed = |
14957 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14958 | else if (IS_BROXTON(dev)) |
14959 | dev_priv->display.get_display_clock_speed = | |
14960 | broxton_get_display_clock_speed; | |
1652d19e VS |
14961 | else if (IS_BROADWELL(dev)) |
14962 | dev_priv->display.get_display_clock_speed = | |
14963 | broadwell_get_display_clock_speed; | |
14964 | else if (IS_HASWELL(dev)) | |
14965 | dev_priv->display.get_display_clock_speed = | |
14966 | haswell_get_display_clock_speed; | |
666a4537 | 14967 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14968 | dev_priv->display.get_display_clock_speed = |
14969 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14970 | else if (IS_GEN5(dev)) |
14971 | dev_priv->display.get_display_clock_speed = | |
14972 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14973 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14974 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14975 | dev_priv->display.get_display_clock_speed = |
14976 | i945_get_display_clock_speed; | |
34edce2f VS |
14977 | else if (IS_GM45(dev)) |
14978 | dev_priv->display.get_display_clock_speed = | |
14979 | gm45_get_display_clock_speed; | |
14980 | else if (IS_CRESTLINE(dev)) | |
14981 | dev_priv->display.get_display_clock_speed = | |
14982 | i965gm_get_display_clock_speed; | |
14983 | else if (IS_PINEVIEW(dev)) | |
14984 | dev_priv->display.get_display_clock_speed = | |
14985 | pnv_get_display_clock_speed; | |
14986 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14987 | dev_priv->display.get_display_clock_speed = | |
14988 | g33_get_display_clock_speed; | |
e70236a8 JB |
14989 | else if (IS_I915G(dev)) |
14990 | dev_priv->display.get_display_clock_speed = | |
14991 | i915_get_display_clock_speed; | |
257a7ffc | 14992 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14993 | dev_priv->display.get_display_clock_speed = |
14994 | i9xx_misc_get_display_clock_speed; | |
14995 | else if (IS_I915GM(dev)) | |
14996 | dev_priv->display.get_display_clock_speed = | |
14997 | i915gm_get_display_clock_speed; | |
14998 | else if (IS_I865G(dev)) | |
14999 | dev_priv->display.get_display_clock_speed = | |
15000 | i865_get_display_clock_speed; | |
f0f8a9ce | 15001 | else if (IS_I85X(dev)) |
e70236a8 | 15002 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15003 | i85x_get_display_clock_speed; |
623e01e5 VS |
15004 | else { /* 830 */ |
15005 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15006 | dev_priv->display.get_display_clock_speed = |
15007 | i830_get_display_clock_speed; | |
623e01e5 | 15008 | } |
e70236a8 | 15009 | |
7c10a2b5 | 15010 | if (IS_GEN5(dev)) { |
3bb11b53 | 15011 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15012 | } else if (IS_GEN6(dev)) { |
15013 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15014 | } else if (IS_IVYBRIDGE(dev)) { |
15015 | /* FIXME: detect B0+ stepping and use auto training */ | |
15016 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15017 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15018 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15019 | if (IS_BROADWELL(dev)) { |
15020 | dev_priv->display.modeset_commit_cdclk = | |
15021 | broadwell_modeset_commit_cdclk; | |
15022 | dev_priv->display.modeset_calc_cdclk = | |
15023 | broadwell_modeset_calc_cdclk; | |
15024 | } | |
666a4537 | 15025 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15026 | dev_priv->display.modeset_commit_cdclk = |
15027 | valleyview_modeset_commit_cdclk; | |
15028 | dev_priv->display.modeset_calc_cdclk = | |
15029 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15030 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15031 | dev_priv->display.modeset_commit_cdclk = |
15032 | broxton_modeset_commit_cdclk; | |
15033 | dev_priv->display.modeset_calc_cdclk = | |
15034 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15035 | } |
8c9f3aaf | 15036 | |
8c9f3aaf JB |
15037 | switch (INTEL_INFO(dev)->gen) { |
15038 | case 2: | |
15039 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15040 | break; | |
15041 | ||
15042 | case 3: | |
15043 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15044 | break; | |
15045 | ||
15046 | case 4: | |
15047 | case 5: | |
15048 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15049 | break; | |
15050 | ||
15051 | case 6: | |
15052 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15053 | break; | |
7c9017e5 | 15054 | case 7: |
4e0bbc31 | 15055 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15056 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15057 | break; | |
830c81db | 15058 | case 9: |
ba343e02 TU |
15059 | /* Drop through - unsupported since execlist only. */ |
15060 | default: | |
15061 | /* Default just returns -ENODEV to indicate unsupported */ | |
15062 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15063 | } |
7bd688cd | 15064 | |
e39b999a | 15065 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15066 | } |
15067 | ||
b690e96c JB |
15068 | /* |
15069 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15070 | * resume, or other times. This quirk makes sure that's the case for | |
15071 | * affected systems. | |
15072 | */ | |
0206e353 | 15073 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15074 | { |
15075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15076 | ||
15077 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15078 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15079 | } |
15080 | ||
b6b5d049 VS |
15081 | static void quirk_pipeb_force(struct drm_device *dev) |
15082 | { | |
15083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15084 | ||
15085 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15086 | DRM_INFO("applying pipe b force quirk\n"); | |
15087 | } | |
15088 | ||
435793df KP |
15089 | /* |
15090 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15091 | */ | |
15092 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15093 | { | |
15094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15095 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15096 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15097 | } |
15098 | ||
4dca20ef | 15099 | /* |
5a15ab5b CE |
15100 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15101 | * brightness value | |
4dca20ef CE |
15102 | */ |
15103 | static void quirk_invert_brightness(struct drm_device *dev) | |
15104 | { | |
15105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15106 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15107 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15108 | } |
15109 | ||
9c72cc6f SD |
15110 | /* Some VBT's incorrectly indicate no backlight is present */ |
15111 | static void quirk_backlight_present(struct drm_device *dev) | |
15112 | { | |
15113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15114 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15115 | DRM_INFO("applying backlight present quirk\n"); | |
15116 | } | |
15117 | ||
b690e96c JB |
15118 | struct intel_quirk { |
15119 | int device; | |
15120 | int subsystem_vendor; | |
15121 | int subsystem_device; | |
15122 | void (*hook)(struct drm_device *dev); | |
15123 | }; | |
15124 | ||
5f85f176 EE |
15125 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15126 | struct intel_dmi_quirk { | |
15127 | void (*hook)(struct drm_device *dev); | |
15128 | const struct dmi_system_id (*dmi_id_list)[]; | |
15129 | }; | |
15130 | ||
15131 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15132 | { | |
15133 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15134 | return 1; | |
15135 | } | |
15136 | ||
15137 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15138 | { | |
15139 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15140 | { | |
15141 | .callback = intel_dmi_reverse_brightness, | |
15142 | .ident = "NCR Corporation", | |
15143 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15144 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15145 | }, | |
15146 | }, | |
15147 | { } /* terminating entry */ | |
15148 | }, | |
15149 | .hook = quirk_invert_brightness, | |
15150 | }, | |
15151 | }; | |
15152 | ||
c43b5634 | 15153 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15154 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15155 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15156 | ||
b690e96c JB |
15157 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15158 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15159 | ||
5f080c0f VS |
15160 | /* 830 needs to leave pipe A & dpll A up */ |
15161 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15162 | ||
b6b5d049 VS |
15163 | /* 830 needs to leave pipe B & dpll B up */ |
15164 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15165 | ||
435793df KP |
15166 | /* Lenovo U160 cannot use SSC on LVDS */ |
15167 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15168 | |
15169 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15170 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15171 | |
be505f64 AH |
15172 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15173 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15174 | ||
15175 | /* Acer/eMachines G725 */ | |
15176 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15177 | ||
15178 | /* Acer/eMachines e725 */ | |
15179 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15180 | ||
15181 | /* Acer/Packard Bell NCL20 */ | |
15182 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15183 | ||
15184 | /* Acer Aspire 4736Z */ | |
15185 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15186 | |
15187 | /* Acer Aspire 5336 */ | |
15188 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15189 | |
15190 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15191 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15192 | |
dfb3d47b SD |
15193 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15194 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15195 | ||
b2a9601c | 15196 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15197 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15198 | ||
1b9448b0 JN |
15199 | /* Apple Macbook 4,1 */ |
15200 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15201 | ||
d4967d8c SD |
15202 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15203 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15204 | |
15205 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15206 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15207 | |
15208 | /* Dell Chromebook 11 */ | |
15209 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15210 | |
15211 | /* Dell Chromebook 11 (2015 version) */ | |
15212 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15213 | }; |
15214 | ||
15215 | static void intel_init_quirks(struct drm_device *dev) | |
15216 | { | |
15217 | struct pci_dev *d = dev->pdev; | |
15218 | int i; | |
15219 | ||
15220 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15221 | struct intel_quirk *q = &intel_quirks[i]; | |
15222 | ||
15223 | if (d->device == q->device && | |
15224 | (d->subsystem_vendor == q->subsystem_vendor || | |
15225 | q->subsystem_vendor == PCI_ANY_ID) && | |
15226 | (d->subsystem_device == q->subsystem_device || | |
15227 | q->subsystem_device == PCI_ANY_ID)) | |
15228 | q->hook(dev); | |
15229 | } | |
5f85f176 EE |
15230 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15231 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15232 | intel_dmi_quirks[i].hook(dev); | |
15233 | } | |
b690e96c JB |
15234 | } |
15235 | ||
9cce37f4 JB |
15236 | /* Disable the VGA plane that we never use */ |
15237 | static void i915_disable_vga(struct drm_device *dev) | |
15238 | { | |
15239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15240 | u8 sr1; | |
f0f59a00 | 15241 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15242 | |
2b37c616 | 15243 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15244 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15245 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15246 | sr1 = inb(VGA_SR_DATA); |
15247 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15248 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15249 | udelay(300); | |
15250 | ||
01f5a626 | 15251 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15252 | POSTING_READ(vga_reg); |
15253 | } | |
15254 | ||
f817586c DV |
15255 | void intel_modeset_init_hw(struct drm_device *dev) |
15256 | { | |
1a617b77 ML |
15257 | struct drm_i915_private *dev_priv = dev->dev_private; |
15258 | ||
b6283055 | 15259 | intel_update_cdclk(dev); |
1a617b77 ML |
15260 | |
15261 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15262 | ||
a8f78b58 | 15263 | intel_prepare_ddi(dev); |
f817586c | 15264 | intel_init_clock_gating(dev); |
8090c6b9 | 15265 | intel_enable_gt_powersave(dev); |
f817586c DV |
15266 | } |
15267 | ||
79e53945 JB |
15268 | void intel_modeset_init(struct drm_device *dev) |
15269 | { | |
652c393a | 15270 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15271 | int sprite, ret; |
8cc87b75 | 15272 | enum pipe pipe; |
46f297fb | 15273 | struct intel_crtc *crtc; |
79e53945 JB |
15274 | |
15275 | drm_mode_config_init(dev); | |
15276 | ||
15277 | dev->mode_config.min_width = 0; | |
15278 | dev->mode_config.min_height = 0; | |
15279 | ||
019d96cb DA |
15280 | dev->mode_config.preferred_depth = 24; |
15281 | dev->mode_config.prefer_shadow = 1; | |
15282 | ||
25bab385 TU |
15283 | dev->mode_config.allow_fb_modifiers = true; |
15284 | ||
e6ecefaa | 15285 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15286 | |
b690e96c JB |
15287 | intel_init_quirks(dev); |
15288 | ||
1fa61106 ED |
15289 | intel_init_pm(dev); |
15290 | ||
e3c74757 BW |
15291 | if (INTEL_INFO(dev)->num_pipes == 0) |
15292 | return; | |
15293 | ||
69f92f67 LW |
15294 | /* |
15295 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15296 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15297 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15298 | * indicates as much. | |
15299 | */ | |
15300 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15301 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15302 | DREF_SSC1_ENABLE); | |
15303 | ||
15304 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15305 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15306 | bios_lvds_use_ssc ? "en" : "dis", | |
15307 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15308 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15309 | } | |
15310 | } | |
15311 | ||
e70236a8 | 15312 | intel_init_display(dev); |
7c10a2b5 | 15313 | intel_init_audio(dev); |
e70236a8 | 15314 | |
a6c45cf0 CW |
15315 | if (IS_GEN2(dev)) { |
15316 | dev->mode_config.max_width = 2048; | |
15317 | dev->mode_config.max_height = 2048; | |
15318 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15319 | dev->mode_config.max_width = 4096; |
15320 | dev->mode_config.max_height = 4096; | |
79e53945 | 15321 | } else { |
a6c45cf0 CW |
15322 | dev->mode_config.max_width = 8192; |
15323 | dev->mode_config.max_height = 8192; | |
79e53945 | 15324 | } |
068be561 | 15325 | |
dc41c154 VS |
15326 | if (IS_845G(dev) || IS_I865G(dev)) { |
15327 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15328 | dev->mode_config.cursor_height = 1023; | |
15329 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15330 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15331 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15332 | } else { | |
15333 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15334 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15335 | } | |
15336 | ||
5d4545ae | 15337 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15338 | |
28c97730 | 15339 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15340 | INTEL_INFO(dev)->num_pipes, |
15341 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15342 | |
055e393f | 15343 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15344 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15345 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15346 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15347 | if (ret) |
06da8da2 | 15348 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15349 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15350 | } |
79e53945 JB |
15351 | } |
15352 | ||
bfa7df01 VS |
15353 | intel_update_czclk(dev_priv); |
15354 | intel_update_cdclk(dev); | |
15355 | ||
e72f9fbf | 15356 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15357 | |
9cce37f4 JB |
15358 | /* Just disable it once at startup */ |
15359 | i915_disable_vga(dev); | |
79e53945 | 15360 | intel_setup_outputs(dev); |
11be49eb | 15361 | |
6e9f798d | 15362 | drm_modeset_lock_all(dev); |
043e9bda | 15363 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15364 | drm_modeset_unlock_all(dev); |
46f297fb | 15365 | |
d3fcc808 | 15366 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15367 | struct intel_initial_plane_config plane_config = {}; |
15368 | ||
46f297fb JB |
15369 | if (!crtc->active) |
15370 | continue; | |
15371 | ||
46f297fb | 15372 | /* |
46f297fb JB |
15373 | * Note that reserving the BIOS fb up front prevents us |
15374 | * from stuffing other stolen allocations like the ring | |
15375 | * on top. This prevents some ugliness at boot time, and | |
15376 | * can even allow for smooth boot transitions if the BIOS | |
15377 | * fb is large enough for the active pipe configuration. | |
15378 | */ | |
eeebeac5 ML |
15379 | dev_priv->display.get_initial_plane_config(crtc, |
15380 | &plane_config); | |
15381 | ||
15382 | /* | |
15383 | * If the fb is shared between multiple heads, we'll | |
15384 | * just get the first one. | |
15385 | */ | |
15386 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15387 | } |
2c7111db CW |
15388 | } |
15389 | ||
7fad798e DV |
15390 | static void intel_enable_pipe_a(struct drm_device *dev) |
15391 | { | |
15392 | struct intel_connector *connector; | |
15393 | struct drm_connector *crt = NULL; | |
15394 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15395 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15396 | |
15397 | /* We can't just switch on the pipe A, we need to set things up with a | |
15398 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15399 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15400 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15401 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15402 | crt = &connector->base; | |
15403 | break; | |
15404 | } | |
15405 | } | |
15406 | ||
15407 | if (!crt) | |
15408 | return; | |
15409 | ||
208bf9fd | 15410 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15411 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15412 | } |
15413 | ||
fa555837 DV |
15414 | static bool |
15415 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15416 | { | |
7eb552ae BW |
15417 | struct drm_device *dev = crtc->base.dev; |
15418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15419 | u32 val; |
fa555837 | 15420 | |
7eb552ae | 15421 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15422 | return true; |
15423 | ||
649636ef | 15424 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15425 | |
15426 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15427 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15428 | return false; | |
15429 | ||
15430 | return true; | |
15431 | } | |
15432 | ||
02e93c35 VS |
15433 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15434 | { | |
15435 | struct drm_device *dev = crtc->base.dev; | |
15436 | struct intel_encoder *encoder; | |
15437 | ||
15438 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15439 | return true; | |
15440 | ||
15441 | return false; | |
15442 | } | |
15443 | ||
24929352 DV |
15444 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15445 | { | |
15446 | struct drm_device *dev = crtc->base.dev; | |
15447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15448 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15449 | |
24929352 | 15450 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15451 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15452 | ||
d3eaf884 | 15453 | /* restore vblank interrupts to correct state */ |
9625604c | 15454 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15455 | if (crtc->active) { |
f9cd7b88 VS |
15456 | struct intel_plane *plane; |
15457 | ||
9625604c | 15458 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15459 | |
15460 | /* Disable everything but the primary plane */ | |
15461 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15462 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15463 | continue; | |
15464 | ||
15465 | plane->disable_plane(&plane->base, &crtc->base); | |
15466 | } | |
9625604c | 15467 | } |
d3eaf884 | 15468 | |
24929352 | 15469 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15470 | * disable the crtc (and hence change the state) if it is wrong. Note |
15471 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15472 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15473 | bool plane; |
15474 | ||
24929352 DV |
15475 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15476 | crtc->base.base.id); | |
15477 | ||
15478 | /* Pipe has the wrong plane attached and the plane is active. | |
15479 | * Temporarily change the plane mapping and disable everything | |
15480 | * ... */ | |
15481 | plane = crtc->plane; | |
b70709a6 | 15482 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15483 | crtc->plane = !plane; |
b17d48e2 | 15484 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15485 | crtc->plane = plane; |
24929352 | 15486 | } |
24929352 | 15487 | |
7fad798e DV |
15488 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15489 | crtc->pipe == PIPE_A && !crtc->active) { | |
15490 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15491 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15492 | * call below we restore the pipe to the right state, but leave | |
15493 | * the required bits on. */ | |
15494 | intel_enable_pipe_a(dev); | |
15495 | } | |
15496 | ||
24929352 DV |
15497 | /* Adjust the state of the output pipe according to whether we |
15498 | * have active connectors/encoders. */ | |
02e93c35 | 15499 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15500 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15501 | |
53d9f4e9 | 15502 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15503 | struct intel_encoder *encoder; |
24929352 DV |
15504 | |
15505 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15506 | * functions or because of calls to intel_crtc_disable_noatomic, |
15507 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15508 | * pipe A quirk. */ |
15509 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15510 | crtc->base.base.id, | |
83d65738 | 15511 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15512 | crtc->active ? "enabled" : "disabled"); |
15513 | ||
4be40c98 | 15514 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15515 | crtc->base.state->active = crtc->active; |
24929352 DV |
15516 | crtc->base.enabled = crtc->active; |
15517 | ||
15518 | /* Because we only establish the connector -> encoder -> | |
15519 | * crtc links if something is active, this means the | |
15520 | * crtc is now deactivated. Break the links. connector | |
15521 | * -> encoder links are only establish when things are | |
15522 | * actually up, hence no need to break them. */ | |
15523 | WARN_ON(crtc->active); | |
15524 | ||
2d406bb0 | 15525 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15526 | encoder->base.crtc = NULL; |
24929352 | 15527 | } |
c5ab3bc0 | 15528 | |
a3ed6aad | 15529 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15530 | /* |
15531 | * We start out with underrun reporting disabled to avoid races. | |
15532 | * For correct bookkeeping mark this on active crtcs. | |
15533 | * | |
c5ab3bc0 DV |
15534 | * Also on gmch platforms we dont have any hardware bits to |
15535 | * disable the underrun reporting. Which means we need to start | |
15536 | * out with underrun reporting disabled also on inactive pipes, | |
15537 | * since otherwise we'll complain about the garbage we read when | |
15538 | * e.g. coming up after runtime pm. | |
15539 | * | |
4cc31489 DV |
15540 | * No protection against concurrent access is required - at |
15541 | * worst a fifo underrun happens which also sets this to false. | |
15542 | */ | |
15543 | crtc->cpu_fifo_underrun_disabled = true; | |
15544 | crtc->pch_fifo_underrun_disabled = true; | |
15545 | } | |
24929352 DV |
15546 | } |
15547 | ||
15548 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15549 | { | |
15550 | struct intel_connector *connector; | |
15551 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15552 | bool active = false; |
24929352 DV |
15553 | |
15554 | /* We need to check both for a crtc link (meaning that the | |
15555 | * encoder is active and trying to read from a pipe) and the | |
15556 | * pipe itself being active. */ | |
15557 | bool has_active_crtc = encoder->base.crtc && | |
15558 | to_intel_crtc(encoder->base.crtc)->active; | |
15559 | ||
873ffe69 ML |
15560 | for_each_intel_connector(dev, connector) { |
15561 | if (connector->base.encoder != &encoder->base) | |
15562 | continue; | |
15563 | ||
15564 | active = true; | |
15565 | break; | |
15566 | } | |
15567 | ||
15568 | if (active && !has_active_crtc) { | |
24929352 DV |
15569 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15570 | encoder->base.base.id, | |
8e329a03 | 15571 | encoder->base.name); |
24929352 DV |
15572 | |
15573 | /* Connector is active, but has no active pipe. This is | |
15574 | * fallout from our resume register restoring. Disable | |
15575 | * the encoder manually again. */ | |
15576 | if (encoder->base.crtc) { | |
15577 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15578 | encoder->base.base.id, | |
8e329a03 | 15579 | encoder->base.name); |
24929352 | 15580 | encoder->disable(encoder); |
a62d1497 VS |
15581 | if (encoder->post_disable) |
15582 | encoder->post_disable(encoder); | |
24929352 | 15583 | } |
7f1950fb | 15584 | encoder->base.crtc = NULL; |
24929352 DV |
15585 | |
15586 | /* Inconsistent output/port/pipe state happens presumably due to | |
15587 | * a bug in one of the get_hw_state functions. Or someplace else | |
15588 | * in our code, like the register restore mess on resume. Clamp | |
15589 | * things to off as a safer default. */ | |
3a3371ff | 15590 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15591 | if (connector->encoder != encoder) |
15592 | continue; | |
7f1950fb EE |
15593 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15594 | connector->base.encoder = NULL; | |
24929352 DV |
15595 | } |
15596 | } | |
15597 | /* Enabled encoders without active connectors will be fixed in | |
15598 | * the crtc fixup. */ | |
15599 | } | |
15600 | ||
04098753 | 15601 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15602 | { |
15603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15604 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15605 | |
04098753 ID |
15606 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15607 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15608 | i915_disable_vga(dev); | |
15609 | } | |
15610 | } | |
15611 | ||
15612 | void i915_redisable_vga(struct drm_device *dev) | |
15613 | { | |
15614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15615 | ||
8dc8a27c PZ |
15616 | /* This function can be called both from intel_modeset_setup_hw_state or |
15617 | * at a very early point in our resume sequence, where the power well | |
15618 | * structures are not yet restored. Since this function is at a very | |
15619 | * paranoid "someone might have enabled VGA while we were not looking" | |
15620 | * level, just check if the power well is enabled instead of trying to | |
15621 | * follow the "don't touch the power well if we don't need it" policy | |
15622 | * the rest of the driver uses. */ | |
f458ebbc | 15623 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15624 | return; |
15625 | ||
04098753 | 15626 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15627 | } |
15628 | ||
f9cd7b88 | 15629 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15630 | { |
f9cd7b88 | 15631 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15632 | |
f9cd7b88 | 15633 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15634 | } |
15635 | ||
f9cd7b88 VS |
15636 | /* FIXME read out full plane state for all planes */ |
15637 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15638 | { |
b26d3ea3 | 15639 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15640 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15641 | to_intel_plane_state(primary->state); |
d032ffa0 | 15642 | |
19b8d387 | 15643 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15644 | primary_get_hw_state(to_intel_plane(primary)); |
15645 | ||
15646 | if (plane_state->visible) | |
15647 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15648 | } |
15649 | ||
30e984df | 15650 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15651 | { |
15652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15653 | enum pipe pipe; | |
24929352 DV |
15654 | struct intel_crtc *crtc; |
15655 | struct intel_encoder *encoder; | |
15656 | struct intel_connector *connector; | |
5358901f | 15657 | int i; |
24929352 | 15658 | |
565602d7 ML |
15659 | dev_priv->active_crtcs = 0; |
15660 | ||
d3fcc808 | 15661 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15662 | struct intel_crtc_state *crtc_state = crtc->config; |
15663 | int pixclk = 0; | |
3b117c8f | 15664 | |
565602d7 ML |
15665 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15666 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15667 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15668 | |
565602d7 ML |
15669 | crtc_state->base.active = crtc_state->base.enable = |
15670 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15671 | ||
15672 | crtc->base.enabled = crtc_state->base.enable; | |
15673 | crtc->active = crtc_state->base.active; | |
15674 | ||
15675 | if (crtc_state->base.active) { | |
15676 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15677 | ||
15678 | if (IS_BROADWELL(dev_priv)) { | |
15679 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15680 | ||
15681 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15682 | if (crtc_state->ips_enabled) | |
15683 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15684 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15685 | IS_CHERRYVIEW(dev_priv) || | |
15686 | IS_BROXTON(dev_priv)) | |
15687 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15688 | else | |
15689 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15690 | } | |
15691 | ||
15692 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15693 | |
f9cd7b88 | 15694 | readout_plane_state(crtc); |
24929352 DV |
15695 | |
15696 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15697 | crtc->base.base.id, | |
15698 | crtc->active ? "enabled" : "disabled"); | |
15699 | } | |
15700 | ||
5358901f DV |
15701 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15702 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15703 | ||
3e369b76 ACO |
15704 | pll->on = pll->get_hw_state(dev_priv, pll, |
15705 | &pll->config.hw_state); | |
5358901f | 15706 | pll->active = 0; |
3e369b76 | 15707 | pll->config.crtc_mask = 0; |
d3fcc808 | 15708 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15709 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15710 | pll->active++; |
3e369b76 | 15711 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15712 | } |
5358901f | 15713 | } |
5358901f | 15714 | |
1e6f2ddc | 15715 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15716 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15717 | |
3e369b76 | 15718 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15719 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15720 | } |
15721 | ||
b2784e15 | 15722 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15723 | pipe = 0; |
15724 | ||
15725 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15726 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15727 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15728 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15729 | } else { |
15730 | encoder->base.crtc = NULL; | |
15731 | } | |
15732 | ||
6f2bcceb | 15733 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15734 | encoder->base.base.id, |
8e329a03 | 15735 | encoder->base.name, |
24929352 | 15736 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15737 | pipe_name(pipe)); |
24929352 DV |
15738 | } |
15739 | ||
3a3371ff | 15740 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15741 | if (connector->get_hw_state(connector)) { |
15742 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15743 | connector->base.encoder = &connector->encoder->base; |
15744 | } else { | |
15745 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15746 | connector->base.encoder = NULL; | |
15747 | } | |
15748 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15749 | connector->base.base.id, | |
c23cc417 | 15750 | connector->base.name, |
24929352 DV |
15751 | connector->base.encoder ? "enabled" : "disabled"); |
15752 | } | |
7f4c6284 VS |
15753 | |
15754 | for_each_intel_crtc(dev, crtc) { | |
15755 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15756 | ||
15757 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15758 | if (crtc->base.state->active) { | |
15759 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15760 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15761 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15762 | ||
15763 | /* | |
15764 | * The initial mode needs to be set in order to keep | |
15765 | * the atomic core happy. It wants a valid mode if the | |
15766 | * crtc's enabled, so we do the above call. | |
15767 | * | |
15768 | * At this point some state updated by the connectors | |
15769 | * in their ->detect() callback has not run yet, so | |
15770 | * no recalculation can be done yet. | |
15771 | * | |
15772 | * Even if we could do a recalculation and modeset | |
15773 | * right now it would cause a double modeset if | |
15774 | * fbdev or userspace chooses a different initial mode. | |
15775 | * | |
15776 | * If that happens, someone indicated they wanted a | |
15777 | * mode change, which means it's safe to do a full | |
15778 | * recalculation. | |
15779 | */ | |
15780 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15781 | |
15782 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15783 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15784 | } |
15785 | } | |
30e984df DV |
15786 | } |
15787 | ||
043e9bda ML |
15788 | /* Scan out the current hw modeset state, |
15789 | * and sanitizes it to the current state | |
15790 | */ | |
15791 | static void | |
15792 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15793 | { |
15794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15795 | enum pipe pipe; | |
30e984df DV |
15796 | struct intel_crtc *crtc; |
15797 | struct intel_encoder *encoder; | |
35c95375 | 15798 | int i; |
30e984df DV |
15799 | |
15800 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15801 | |
15802 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15803 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15804 | intel_sanitize_encoder(encoder); |
15805 | } | |
15806 | ||
055e393f | 15807 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15808 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15809 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15810 | intel_dump_pipe_config(crtc, crtc->config, |
15811 | "[setup_hw_state]"); | |
24929352 | 15812 | } |
9a935856 | 15813 | |
d29b2f9d ACO |
15814 | intel_modeset_update_connector_atomic_state(dev); |
15815 | ||
35c95375 DV |
15816 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15817 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15818 | ||
15819 | if (!pll->on || pll->active) | |
15820 | continue; | |
15821 | ||
15822 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15823 | ||
15824 | pll->disable(dev_priv, pll); | |
15825 | pll->on = false; | |
15826 | } | |
15827 | ||
666a4537 | 15828 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15829 | vlv_wm_get_hw_state(dev); |
15830 | else if (IS_GEN9(dev)) | |
3078999f PB |
15831 | skl_wm_get_hw_state(dev); |
15832 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15833 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15834 | |
15835 | for_each_intel_crtc(dev, crtc) { | |
15836 | unsigned long put_domains; | |
15837 | ||
15838 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15839 | if (WARN_ON(put_domains)) | |
15840 | modeset_put_power_domains(dev_priv, put_domains); | |
15841 | } | |
15842 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15843 | } |
7d0bc1ea | 15844 | |
043e9bda ML |
15845 | void intel_display_resume(struct drm_device *dev) |
15846 | { | |
15847 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15848 | struct intel_connector *conn; | |
15849 | struct intel_plane *plane; | |
15850 | struct drm_crtc *crtc; | |
15851 | int ret; | |
f30da187 | 15852 | |
043e9bda ML |
15853 | if (!state) |
15854 | return; | |
15855 | ||
15856 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15857 | ||
15858 | /* preserve complete old state, including dpll */ | |
15859 | intel_atomic_get_shared_dpll_state(state); | |
15860 | ||
15861 | for_each_crtc(dev, crtc) { | |
15862 | struct drm_crtc_state *crtc_state = | |
15863 | drm_atomic_get_crtc_state(state, crtc); | |
15864 | ||
15865 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15866 | if (ret) | |
15867 | goto err; | |
15868 | ||
15869 | /* force a restore */ | |
15870 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15871 | } |
8af6cf88 | 15872 | |
043e9bda ML |
15873 | for_each_intel_plane(dev, plane) { |
15874 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15875 | if (ret) | |
15876 | goto err; | |
15877 | } | |
15878 | ||
15879 | for_each_intel_connector(dev, conn) { | |
15880 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15881 | if (ret) | |
15882 | goto err; | |
15883 | } | |
15884 | ||
15885 | intel_modeset_setup_hw_state(dev); | |
15886 | ||
15887 | i915_redisable_vga(dev); | |
74c090b1 | 15888 | ret = drm_atomic_commit(state); |
043e9bda ML |
15889 | if (!ret) |
15890 | return; | |
15891 | ||
15892 | err: | |
15893 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15894 | drm_atomic_state_free(state); | |
2c7111db CW |
15895 | } |
15896 | ||
15897 | void intel_modeset_gem_init(struct drm_device *dev) | |
15898 | { | |
484b41dd | 15899 | struct drm_crtc *c; |
2ff8fde1 | 15900 | struct drm_i915_gem_object *obj; |
e0d6149b | 15901 | int ret; |
484b41dd | 15902 | |
ae48434c ID |
15903 | mutex_lock(&dev->struct_mutex); |
15904 | intel_init_gt_powersave(dev); | |
15905 | mutex_unlock(&dev->struct_mutex); | |
15906 | ||
1833b134 | 15907 | intel_modeset_init_hw(dev); |
02e792fb DV |
15908 | |
15909 | intel_setup_overlay(dev); | |
484b41dd JB |
15910 | |
15911 | /* | |
15912 | * Make sure any fbs we allocated at startup are properly | |
15913 | * pinned & fenced. When we do the allocation it's too early | |
15914 | * for this. | |
15915 | */ | |
70e1e0ec | 15916 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15917 | obj = intel_fb_obj(c->primary->fb); |
15918 | if (obj == NULL) | |
484b41dd JB |
15919 | continue; |
15920 | ||
e0d6149b TU |
15921 | mutex_lock(&dev->struct_mutex); |
15922 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15923 | c->primary->fb, | |
7580d774 | 15924 | c->primary->state); |
e0d6149b TU |
15925 | mutex_unlock(&dev->struct_mutex); |
15926 | if (ret) { | |
484b41dd JB |
15927 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15928 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15929 | drm_framebuffer_unreference(c->primary->fb); |
15930 | c->primary->fb = NULL; | |
36750f28 | 15931 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15932 | update_state_fb(c->primary); |
36750f28 | 15933 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15934 | } |
15935 | } | |
0962c3c9 VS |
15936 | |
15937 | intel_backlight_register(dev); | |
79e53945 JB |
15938 | } |
15939 | ||
4932e2c3 ID |
15940 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15941 | { | |
15942 | struct drm_connector *connector = &intel_connector->base; | |
15943 | ||
15944 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15945 | drm_connector_unregister(connector); |
4932e2c3 ID |
15946 | } |
15947 | ||
79e53945 JB |
15948 | void intel_modeset_cleanup(struct drm_device *dev) |
15949 | { | |
652c393a | 15950 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15951 | struct intel_connector *connector; |
652c393a | 15952 | |
2eb5252e ID |
15953 | intel_disable_gt_powersave(dev); |
15954 | ||
0962c3c9 VS |
15955 | intel_backlight_unregister(dev); |
15956 | ||
fd0c0642 DV |
15957 | /* |
15958 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15959 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15960 | * experience fancy races otherwise. |
15961 | */ | |
2aeb7d3a | 15962 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15963 | |
fd0c0642 DV |
15964 | /* |
15965 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15966 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15967 | */ | |
f87ea761 | 15968 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15969 | |
723bfd70 JB |
15970 | intel_unregister_dsm_handler(); |
15971 | ||
7733b49b | 15972 | intel_fbc_disable(dev_priv); |
69341a5e | 15973 | |
1630fe75 CW |
15974 | /* flush any delayed tasks or pending work */ |
15975 | flush_scheduled_work(); | |
15976 | ||
db31af1d | 15977 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15978 | for_each_intel_connector(dev, connector) |
15979 | connector->unregister(connector); | |
d9255d57 | 15980 | |
79e53945 | 15981 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15982 | |
15983 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15984 | |
15985 | mutex_lock(&dev->struct_mutex); | |
15986 | intel_cleanup_gt_powersave(dev); | |
15987 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15988 | } |
15989 | ||
f1c79df3 ZW |
15990 | /* |
15991 | * Return which encoder is currently attached for connector. | |
15992 | */ | |
df0e9248 | 15993 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15994 | { |
df0e9248 CW |
15995 | return &intel_attached_encoder(connector)->base; |
15996 | } | |
f1c79df3 | 15997 | |
df0e9248 CW |
15998 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15999 | struct intel_encoder *encoder) | |
16000 | { | |
16001 | connector->encoder = encoder; | |
16002 | drm_mode_connector_attach_encoder(&connector->base, | |
16003 | &encoder->base); | |
79e53945 | 16004 | } |
28d52043 DA |
16005 | |
16006 | /* | |
16007 | * set vga decode state - true == enable VGA decode | |
16008 | */ | |
16009 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16010 | { | |
16011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16012 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16013 | u16 gmch_ctrl; |
16014 | ||
75fa041d CW |
16015 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16016 | DRM_ERROR("failed to read control word\n"); | |
16017 | return -EIO; | |
16018 | } | |
16019 | ||
c0cc8a55 CW |
16020 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16021 | return 0; | |
16022 | ||
28d52043 DA |
16023 | if (state) |
16024 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16025 | else | |
16026 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16027 | |
16028 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16029 | DRM_ERROR("failed to write control word\n"); | |
16030 | return -EIO; | |
16031 | } | |
16032 | ||
28d52043 DA |
16033 | return 0; |
16034 | } | |
c4a1d9e4 | 16035 | |
c4a1d9e4 | 16036 | struct intel_display_error_state { |
ff57f1b0 PZ |
16037 | |
16038 | u32 power_well_driver; | |
16039 | ||
63b66e5b CW |
16040 | int num_transcoders; |
16041 | ||
c4a1d9e4 CW |
16042 | struct intel_cursor_error_state { |
16043 | u32 control; | |
16044 | u32 position; | |
16045 | u32 base; | |
16046 | u32 size; | |
52331309 | 16047 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16048 | |
16049 | struct intel_pipe_error_state { | |
ddf9c536 | 16050 | bool power_domain_on; |
c4a1d9e4 | 16051 | u32 source; |
f301b1e1 | 16052 | u32 stat; |
52331309 | 16053 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16054 | |
16055 | struct intel_plane_error_state { | |
16056 | u32 control; | |
16057 | u32 stride; | |
16058 | u32 size; | |
16059 | u32 pos; | |
16060 | u32 addr; | |
16061 | u32 surface; | |
16062 | u32 tile_offset; | |
52331309 | 16063 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16064 | |
16065 | struct intel_transcoder_error_state { | |
ddf9c536 | 16066 | bool power_domain_on; |
63b66e5b CW |
16067 | enum transcoder cpu_transcoder; |
16068 | ||
16069 | u32 conf; | |
16070 | ||
16071 | u32 htotal; | |
16072 | u32 hblank; | |
16073 | u32 hsync; | |
16074 | u32 vtotal; | |
16075 | u32 vblank; | |
16076 | u32 vsync; | |
16077 | } transcoder[4]; | |
c4a1d9e4 CW |
16078 | }; |
16079 | ||
16080 | struct intel_display_error_state * | |
16081 | intel_display_capture_error_state(struct drm_device *dev) | |
16082 | { | |
fbee40df | 16083 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16084 | struct intel_display_error_state *error; |
63b66e5b CW |
16085 | int transcoders[] = { |
16086 | TRANSCODER_A, | |
16087 | TRANSCODER_B, | |
16088 | TRANSCODER_C, | |
16089 | TRANSCODER_EDP, | |
16090 | }; | |
c4a1d9e4 CW |
16091 | int i; |
16092 | ||
63b66e5b CW |
16093 | if (INTEL_INFO(dev)->num_pipes == 0) |
16094 | return NULL; | |
16095 | ||
9d1cb914 | 16096 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16097 | if (error == NULL) |
16098 | return NULL; | |
16099 | ||
190be112 | 16100 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16101 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16102 | ||
055e393f | 16103 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16104 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16105 | __intel_display_power_is_enabled(dev_priv, |
16106 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16107 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16108 | continue; |
16109 | ||
5efb3e28 VS |
16110 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16111 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16112 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16113 | |
16114 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16115 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16116 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16117 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16118 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16119 | } | |
ca291363 PZ |
16120 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16121 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16122 | if (INTEL_INFO(dev)->gen >= 4) { |
16123 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16124 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16125 | } | |
16126 | ||
c4a1d9e4 | 16127 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16128 | |
3abfce77 | 16129 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16130 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16131 | } |
16132 | ||
16133 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16134 | if (HAS_DDI(dev_priv->dev)) | |
16135 | error->num_transcoders++; /* Account for eDP. */ | |
16136 | ||
16137 | for (i = 0; i < error->num_transcoders; i++) { | |
16138 | enum transcoder cpu_transcoder = transcoders[i]; | |
16139 | ||
ddf9c536 | 16140 | error->transcoder[i].power_domain_on = |
f458ebbc | 16141 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16142 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16143 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16144 | continue; |
16145 | ||
63b66e5b CW |
16146 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16147 | ||
16148 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16149 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16150 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16151 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16152 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16153 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16154 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16155 | } |
16156 | ||
16157 | return error; | |
16158 | } | |
16159 | ||
edc3d884 MK |
16160 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16161 | ||
c4a1d9e4 | 16162 | void |
edc3d884 | 16163 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16164 | struct drm_device *dev, |
16165 | struct intel_display_error_state *error) | |
16166 | { | |
055e393f | 16167 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16168 | int i; |
16169 | ||
63b66e5b CW |
16170 | if (!error) |
16171 | return; | |
16172 | ||
edc3d884 | 16173 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16174 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16175 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16176 | error->power_well_driver); |
055e393f | 16177 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16178 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
16179 | err_printf(m, " Power: %s\n", |
16180 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 16181 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16182 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16183 | |
16184 | err_printf(m, "Plane [%d]:\n", i); | |
16185 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16186 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16187 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16188 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16189 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16190 | } |
4b71a570 | 16191 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16192 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16193 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16194 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16195 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16196 | } |
16197 | ||
edc3d884 MK |
16198 | err_printf(m, "Cursor [%d]:\n", i); |
16199 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16200 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16201 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16202 | } |
63b66e5b CW |
16203 | |
16204 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16205 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16206 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
16207 | err_printf(m, " Power: %s\n", |
16208 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
16209 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16210 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16211 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16212 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16213 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16214 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16215 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16216 | } | |
c4a1d9e4 | 16217 | } |
e2fcdaa9 VS |
16218 | |
16219 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16220 | { | |
16221 | struct intel_crtc *crtc; | |
16222 | ||
16223 | for_each_intel_crtc(dev, crtc) { | |
16224 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16225 | |
5e2d7afc | 16226 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16227 | |
16228 | work = crtc->unpin_work; | |
16229 | ||
16230 | if (work && work->event && | |
16231 | work->event->base.file_priv == file) { | |
16232 | kfree(work->event); | |
16233 | work->event = NULL; | |
16234 | } | |
16235 | ||
5e2d7afc | 16236 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16237 | } |
16238 | } |