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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac | 226 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
227 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
228 | const struct intel_crtc_state *pipe_config) | |
021357ac | 229 | { |
21a727b3 VS |
230 | if (HAS_DDI(dev_priv)) |
231 | return pipe_config->port_clock; /* SPLL */ | |
232 | else if (IS_GEN5(dev_priv)) | |
233 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 234 | else |
21a727b3 | 235 | return 270000; |
021357ac CW |
236 | } |
237 | ||
5d536e28 | 238 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 239 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 240 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 241 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
242 | .m = { .min = 96, .max = 140 }, |
243 | .m1 = { .min = 18, .max = 26 }, | |
244 | .m2 = { .min = 6, .max = 16 }, | |
245 | .p = { .min = 4, .max = 128 }, | |
246 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 165000, |
248 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
249 | }; |
250 | ||
5d536e28 DV |
251 | static const intel_limit_t intel_limits_i8xx_dvo = { |
252 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
260 | .p2 = { .dot_limit = 165000, | |
261 | .p2_slow = 4, .p2_fast = 4 }, | |
262 | }; | |
263 | ||
e4b36699 | 264 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 275 | }; |
273e27ca | 276 | |
e4b36699 | 277 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
278 | .dot = { .min = 20000, .max = 400000 }, |
279 | .vco = { .min = 1400000, .max = 2800000 }, | |
280 | .n = { .min = 1, .max = 6 }, | |
281 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
282 | .m1 = { .min = 8, .max = 18 }, |
283 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
284 | .p = { .min = 5, .max = 80 }, |
285 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 200000, |
287 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
288 | }; |
289 | ||
290 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 7, .max = 98 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 112000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
301 | }; |
302 | ||
273e27ca | 303 | |
e4b36699 | 304 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 270000 }, |
306 | .vco = { .min = 1750000, .max = 3500000}, | |
307 | .n = { .min = 1, .max = 4 }, | |
308 | .m = { .min = 104, .max = 138 }, | |
309 | .m1 = { .min = 17, .max = 23 }, | |
310 | .m2 = { .min = 5, .max = 11 }, | |
311 | .p = { .min = 10, .max = 30 }, | |
312 | .p1 = { .min = 1, .max = 3}, | |
313 | .p2 = { .dot_limit = 270000, | |
314 | .p2_slow = 10, | |
315 | .p2_fast = 10 | |
044c7c41 | 316 | }, |
e4b36699 KP |
317 | }; |
318 | ||
319 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
320 | .dot = { .min = 22000, .max = 400000 }, |
321 | .vco = { .min = 1750000, .max = 3500000}, | |
322 | .n = { .min = 1, .max = 4 }, | |
323 | .m = { .min = 104, .max = 138 }, | |
324 | .m1 = { .min = 16, .max = 23 }, | |
325 | .m2 = { .min = 5, .max = 11 }, | |
326 | .p = { .min = 5, .max = 80 }, | |
327 | .p1 = { .min = 1, .max = 8}, | |
328 | .p2 = { .dot_limit = 165000, | |
329 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
333 | .dot = { .min = 20000, .max = 115000 }, |
334 | .vco = { .min = 1750000, .max = 3500000 }, | |
335 | .n = { .min = 1, .max = 3 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 17, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 28, .max = 112 }, | |
340 | .p1 = { .min = 2, .max = 8 }, | |
341 | .p2 = { .dot_limit = 0, | |
342 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 343 | }, |
e4b36699 KP |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
347 | .dot = { .min = 80000, .max = 224000 }, |
348 | .vco = { .min = 1750000, .max = 3500000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 104, .max = 138 }, | |
351 | .m1 = { .min = 17, .max = 23 }, | |
352 | .m2 = { .min = 5, .max = 11 }, | |
353 | .p = { .min = 14, .max = 42 }, | |
354 | .p1 = { .min = 2, .max = 6 }, | |
355 | .p2 = { .dot_limit = 0, | |
356 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 357 | }, |
e4b36699 KP |
358 | }; |
359 | ||
f2b115e6 | 360 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
361 | .dot = { .min = 20000, .max = 400000}, |
362 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 363 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
364 | .n = { .min = 3, .max = 6 }, |
365 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 366 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
367 | .m1 = { .min = 0, .max = 0 }, |
368 | .m2 = { .min = 0, .max = 254 }, | |
369 | .p = { .min = 5, .max = 80 }, | |
370 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
371 | .p2 = { .dot_limit = 200000, |
372 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
373 | }; |
374 | ||
f2b115e6 | 375 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
376 | .dot = { .min = 20000, .max = 400000 }, |
377 | .vco = { .min = 1700000, .max = 3500000 }, | |
378 | .n = { .min = 3, .max = 6 }, | |
379 | .m = { .min = 2, .max = 256 }, | |
380 | .m1 = { .min = 0, .max = 0 }, | |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 7, .max = 112 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 112000, |
385 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
386 | }; |
387 | ||
273e27ca EA |
388 | /* Ironlake / Sandybridge |
389 | * | |
390 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
391 | * the range value for them is (actual_value - 2). | |
392 | */ | |
b91ad0ec | 393 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
394 | .dot = { .min = 25000, .max = 350000 }, |
395 | .vco = { .min = 1760000, .max = 3510000 }, | |
396 | .n = { .min = 1, .max = 5 }, | |
397 | .m = { .min = 79, .max = 127 }, | |
398 | .m1 = { .min = 12, .max = 22 }, | |
399 | .m2 = { .min = 5, .max = 9 }, | |
400 | .p = { .min = 5, .max = 80 }, | |
401 | .p1 = { .min = 1, .max = 8 }, | |
402 | .p2 = { .dot_limit = 225000, | |
403 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
404 | }; |
405 | ||
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 3 }, | |
410 | .m = { .min = 79, .max = 118 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 28, .max = 112 }, | |
414 | .p1 = { .min = 2, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
417 | }; |
418 | ||
419 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 14, .max = 56 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
273e27ca | 432 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 433 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
434 | .dot = { .min = 25000, .max = 350000 }, |
435 | .vco = { .min = 1760000, .max = 3510000 }, | |
436 | .n = { .min = 1, .max = 2 }, | |
437 | .m = { .min = 79, .max = 126 }, | |
438 | .m1 = { .min = 12, .max = 22 }, | |
439 | .m2 = { .min = 5, .max = 9 }, | |
440 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 441 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
442 | .p2 = { .dot_limit = 225000, |
443 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
444 | }; |
445 | ||
446 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 3 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
457 | }; |
458 | ||
dc730512 | 459 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
460 | /* |
461 | * These are the data rate limits (measured in fast clocks) | |
462 | * since those are the strictest limits we have. The fast | |
463 | * clock and actual rate limits are more relaxed, so checking | |
464 | * them would make no difference. | |
465 | */ | |
466 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 467 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 468 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
469 | .m1 = { .min = 2, .max = 3 }, |
470 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 471 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 472 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
473 | }; |
474 | ||
ef9348c8 CML |
475 | static const intel_limit_t intel_limits_chv = { |
476 | /* | |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 483 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
484 | .n = { .min = 1, .max = 1 }, |
485 | .m1 = { .min = 2, .max = 2 }, | |
486 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
487 | .p1 = { .min = 2, .max = 4 }, | |
488 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
489 | }; | |
490 | ||
5ab7b0b7 ID |
491 | static const intel_limit_t intel_limits_bxt = { |
492 | /* FIXME: find real dot limits */ | |
493 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 494 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
495 | .n = { .min = 1, .max = 1 }, |
496 | .m1 = { .min = 2, .max = 2 }, | |
497 | /* FIXME: find real m2 limits */ | |
498 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
499 | .p1 = { .min = 2, .max = 4 }, | |
500 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
501 | }; | |
502 | ||
cdba954e ACO |
503 | static bool |
504 | needs_modeset(struct drm_crtc_state *state) | |
505 | { | |
fc596660 | 506 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
507 | } |
508 | ||
e0638cdf PZ |
509 | /** |
510 | * Returns whether any output on the specified pipe is of the specified type | |
511 | */ | |
4093561b | 512 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 513 | { |
409ee761 | 514 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
515 | struct intel_encoder *encoder; |
516 | ||
409ee761 | 517 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
518 | if (encoder->type == type) |
519 | return true; | |
520 | ||
521 | return false; | |
522 | } | |
523 | ||
d0737e1d ACO |
524 | /** |
525 | * Returns whether any output on the specified pipe will have the specified | |
526 | * type after a staged modeset is complete, i.e., the same as | |
527 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
528 | * encoder->crtc. | |
529 | */ | |
a93e255f ACO |
530 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
531 | int type) | |
d0737e1d | 532 | { |
a93e255f | 533 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 534 | struct drm_connector *connector; |
a93e255f | 535 | struct drm_connector_state *connector_state; |
d0737e1d | 536 | struct intel_encoder *encoder; |
a93e255f ACO |
537 | int i, num_connectors = 0; |
538 | ||
da3ced29 | 539 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
540 | if (connector_state->crtc != crtc_state->base.crtc) |
541 | continue; | |
542 | ||
543 | num_connectors++; | |
d0737e1d | 544 | |
a93e255f ACO |
545 | encoder = to_intel_encoder(connector_state->best_encoder); |
546 | if (encoder->type == type) | |
d0737e1d | 547 | return true; |
a93e255f ACO |
548 | } |
549 | ||
550 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
551 | |
552 | return false; | |
553 | } | |
554 | ||
a93e255f ACO |
555 | static const intel_limit_t * |
556 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 557 | { |
a93e255f | 558 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 559 | const intel_limit_t *limit; |
b91ad0ec | 560 | |
a93e255f | 561 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 562 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 563 | if (refclk == 100000) |
b91ad0ec ZW |
564 | limit = &intel_limits_ironlake_dual_lvds_100m; |
565 | else | |
566 | limit = &intel_limits_ironlake_dual_lvds; | |
567 | } else { | |
1b894b59 | 568 | if (refclk == 100000) |
b91ad0ec ZW |
569 | limit = &intel_limits_ironlake_single_lvds_100m; |
570 | else | |
571 | limit = &intel_limits_ironlake_single_lvds; | |
572 | } | |
c6bb3538 | 573 | } else |
b91ad0ec | 574 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
575 | |
576 | return limit; | |
577 | } | |
578 | ||
a93e255f ACO |
579 | static const intel_limit_t * |
580 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 581 | { |
a93e255f | 582 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
583 | const intel_limit_t *limit; |
584 | ||
a93e255f | 585 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 586 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 587 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 588 | else |
e4b36699 | 589 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
591 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 592 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 593 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 594 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 595 | } else /* The option is for other outputs */ |
e4b36699 | 596 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
597 | |
598 | return limit; | |
599 | } | |
600 | ||
a93e255f ACO |
601 | static const intel_limit_t * |
602 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 603 | { |
a93e255f | 604 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
605 | const intel_limit_t *limit; |
606 | ||
5ab7b0b7 ID |
607 | if (IS_BROXTON(dev)) |
608 | limit = &intel_limits_bxt; | |
609 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 610 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 611 | else if (IS_G4X(dev)) { |
a93e255f | 612 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 613 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 614 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 615 | limit = &intel_limits_pineview_lvds; |
2177832f | 616 | else |
f2b115e6 | 617 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
618 | } else if (IS_CHERRYVIEW(dev)) { |
619 | limit = &intel_limits_chv; | |
a0c4da24 | 620 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 621 | limit = &intel_limits_vlv; |
a6c45cf0 | 622 | } else if (!IS_GEN2(dev)) { |
a93e255f | 623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
624 | limit = &intel_limits_i9xx_lvds; |
625 | else | |
626 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 627 | } else { |
a93e255f | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 630 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 631 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
632 | else |
633 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
634 | } |
635 | return limit; | |
636 | } | |
637 | ||
dccbea3b ID |
638 | /* |
639 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
640 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
641 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
642 | * The helpers' return value is the rate of the clock that is fed to the | |
643 | * display engine's pipe which can be the above fast dot clock rate or a | |
644 | * divided-down version of it. | |
645 | */ | |
f2b115e6 | 646 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 647 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 648 | { |
2177832f SL |
649 | clock->m = clock->m2 + 2; |
650 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 651 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 652 | return 0; |
fb03ac01 VS |
653 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
654 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
655 | |
656 | return clock->dot; | |
2177832f SL |
657 | } |
658 | ||
7429e9d4 DV |
659 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
660 | { | |
661 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
662 | } | |
663 | ||
dccbea3b | 664 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 665 | { |
7429e9d4 | 666 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 667 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 668 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 669 | return 0; |
fb03ac01 VS |
670 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
671 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
672 | |
673 | return clock->dot; | |
79e53945 JB |
674 | } |
675 | ||
dccbea3b | 676 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
677 | { |
678 | clock->m = clock->m1 * clock->m2; | |
679 | clock->p = clock->p1 * clock->p2; | |
680 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 681 | return 0; |
589eca67 ID |
682 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
683 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
684 | |
685 | return clock->dot / 5; | |
589eca67 ID |
686 | } |
687 | ||
dccbea3b | 688 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
689 | { |
690 | clock->m = clock->m1 * clock->m2; | |
691 | clock->p = clock->p1 * clock->p2; | |
692 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 693 | return 0; |
ef9348c8 CML |
694 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
695 | clock->n << 22); | |
696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
697 | |
698 | return clock->dot / 5; | |
ef9348c8 CML |
699 | } |
700 | ||
7c04d1d9 | 701 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
702 | /** |
703 | * Returns whether the given set of divisors are valid for a given refclk with | |
704 | * the given connectors. | |
705 | */ | |
706 | ||
1b894b59 CW |
707 | static bool intel_PLL_is_valid(struct drm_device *dev, |
708 | const intel_limit_t *limit, | |
709 | const intel_clock_t *clock) | |
79e53945 | 710 | { |
f01b7962 VS |
711 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
712 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 713 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 714 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 716 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 718 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 719 | |
666a4537 WB |
720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
722 | if (clock->m1 <= clock->m2) |
723 | INTELPllInvalid("m1 <= m2\n"); | |
724 | ||
666a4537 | 725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
727 | INTELPllInvalid("p out of range\n"); | |
728 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
729 | INTELPllInvalid("m out of range\n"); | |
730 | } | |
731 | ||
79e53945 | 732 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 733 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
734 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
735 | * connector, etc., rather than just a single range. | |
736 | */ | |
737 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 738 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
739 | |
740 | return true; | |
741 | } | |
742 | ||
3b1429d9 VS |
743 | static int |
744 | i9xx_select_p2_div(const intel_limit_t *limit, | |
745 | const struct intel_crtc_state *crtc_state, | |
746 | int target) | |
79e53945 | 747 | { |
3b1429d9 | 748 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 749 | |
a93e255f | 750 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 751 | /* |
a210b028 DV |
752 | * For LVDS just rely on its current settings for dual-channel. |
753 | * We haven't figured out how to reliably set up different | |
754 | * single/dual channel state, if we even can. | |
79e53945 | 755 | */ |
1974cad0 | 756 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 757 | return limit->p2.p2_fast; |
79e53945 | 758 | else |
3b1429d9 | 759 | return limit->p2.p2_slow; |
79e53945 JB |
760 | } else { |
761 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 762 | return limit->p2.p2_slow; |
79e53945 | 763 | else |
3b1429d9 | 764 | return limit->p2.p2_fast; |
79e53945 | 765 | } |
3b1429d9 VS |
766 | } |
767 | ||
768 | static bool | |
769 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
770 | struct intel_crtc_state *crtc_state, | |
771 | int target, int refclk, intel_clock_t *match_clock, | |
772 | intel_clock_t *best_clock) | |
773 | { | |
774 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
775 | intel_clock_t clock; | |
776 | int err = target; | |
79e53945 | 777 | |
0206e353 | 778 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 779 | |
3b1429d9 VS |
780 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
781 | ||
42158660 ZY |
782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
783 | clock.m1++) { | |
784 | for (clock.m2 = limit->m2.min; | |
785 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 786 | if (clock.m2 >= clock.m1) |
42158660 ZY |
787 | break; |
788 | for (clock.n = limit->n.min; | |
789 | clock.n <= limit->n.max; clock.n++) { | |
790 | for (clock.p1 = limit->p1.min; | |
791 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
792 | int this_err; |
793 | ||
dccbea3b | 794 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
795 | if (!intel_PLL_is_valid(dev, limit, |
796 | &clock)) | |
797 | continue; | |
798 | if (match_clock && | |
799 | clock.p != match_clock->p) | |
800 | continue; | |
801 | ||
802 | this_err = abs(clock.dot - target); | |
803 | if (this_err < err) { | |
804 | *best_clock = clock; | |
805 | err = this_err; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | return (err != target); | |
813 | } | |
814 | ||
815 | static bool | |
a93e255f ACO |
816 | pnv_find_best_dpll(const intel_limit_t *limit, |
817 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
818 | int target, int refclk, intel_clock_t *match_clock, |
819 | intel_clock_t *best_clock) | |
79e53945 | 820 | { |
3b1429d9 | 821 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 822 | intel_clock_t clock; |
79e53945 JB |
823 | int err = target; |
824 | ||
0206e353 | 825 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 826 | |
3b1429d9 VS |
827 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
828 | ||
42158660 ZY |
829 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
830 | clock.m1++) { | |
831 | for (clock.m2 = limit->m2.min; | |
832 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
833 | for (clock.n = limit->n.min; |
834 | clock.n <= limit->n.max; clock.n++) { | |
835 | for (clock.p1 = limit->p1.min; | |
836 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
837 | int this_err; |
838 | ||
dccbea3b | 839 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
840 | if (!intel_PLL_is_valid(dev, limit, |
841 | &clock)) | |
79e53945 | 842 | continue; |
cec2f356 SP |
843 | if (match_clock && |
844 | clock.p != match_clock->p) | |
845 | continue; | |
79e53945 JB |
846 | |
847 | this_err = abs(clock.dot - target); | |
848 | if (this_err < err) { | |
849 | *best_clock = clock; | |
850 | err = this_err; | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return (err != target); | |
858 | } | |
859 | ||
d4906093 | 860 | static bool |
a93e255f ACO |
861 | g4x_find_best_dpll(const intel_limit_t *limit, |
862 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
863 | int target, int refclk, intel_clock_t *match_clock, |
864 | intel_clock_t *best_clock) | |
d4906093 | 865 | { |
3b1429d9 | 866 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
867 | intel_clock_t clock; |
868 | int max_n; | |
3b1429d9 | 869 | bool found = false; |
6ba770dc AJ |
870 | /* approximately equals target * 0.00585 */ |
871 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
872 | |
873 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
874 | |
875 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
876 | ||
d4906093 | 877 | max_n = limit->n.max; |
f77f13e2 | 878 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 880 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
881 | for (clock.m1 = limit->m1.max; |
882 | clock.m1 >= limit->m1.min; clock.m1--) { | |
883 | for (clock.m2 = limit->m2.max; | |
884 | clock.m2 >= limit->m2.min; clock.m2--) { | |
885 | for (clock.p1 = limit->p1.max; | |
886 | clock.p1 >= limit->p1.min; clock.p1--) { | |
887 | int this_err; | |
888 | ||
dccbea3b | 889 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
890 | if (!intel_PLL_is_valid(dev, limit, |
891 | &clock)) | |
d4906093 | 892 | continue; |
1b894b59 CW |
893 | |
894 | this_err = abs(clock.dot - target); | |
d4906093 ML |
895 | if (this_err < err_most) { |
896 | *best_clock = clock; | |
897 | err_most = this_err; | |
898 | max_n = clock.n; | |
899 | found = true; | |
900 | } | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
2c07245f ZW |
905 | return found; |
906 | } | |
907 | ||
d5dd62bd ID |
908 | /* |
909 | * Check if the calculated PLL configuration is more optimal compared to the | |
910 | * best configuration and error found so far. Return the calculated error. | |
911 | */ | |
912 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
913 | const intel_clock_t *calculated_clock, | |
914 | const intel_clock_t *best_clock, | |
915 | unsigned int best_error_ppm, | |
916 | unsigned int *error_ppm) | |
917 | { | |
9ca3ba01 ID |
918 | /* |
919 | * For CHV ignore the error and consider only the P value. | |
920 | * Prefer a bigger P value based on HW requirements. | |
921 | */ | |
922 | if (IS_CHERRYVIEW(dev)) { | |
923 | *error_ppm = 0; | |
924 | ||
925 | return calculated_clock->p > best_clock->p; | |
926 | } | |
927 | ||
24be4e46 ID |
928 | if (WARN_ON_ONCE(!target_freq)) |
929 | return false; | |
930 | ||
d5dd62bd ID |
931 | *error_ppm = div_u64(1000000ULL * |
932 | abs(target_freq - calculated_clock->dot), | |
933 | target_freq); | |
934 | /* | |
935 | * Prefer a better P value over a better (smaller) error if the error | |
936 | * is small. Ensure this preference for future configurations too by | |
937 | * setting the error to 0. | |
938 | */ | |
939 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
940 | *error_ppm = 0; | |
941 | ||
942 | return true; | |
943 | } | |
944 | ||
945 | return *error_ppm + 10 < best_error_ppm; | |
946 | } | |
947 | ||
a0c4da24 | 948 | static bool |
a93e255f ACO |
949 | vlv_find_best_dpll(const intel_limit_t *limit, |
950 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
951 | int target, int refclk, intel_clock_t *match_clock, |
952 | intel_clock_t *best_clock) | |
a0c4da24 | 953 | { |
a93e255f | 954 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 955 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 956 | intel_clock_t clock; |
69e4f900 | 957 | unsigned int bestppm = 1000000; |
27e639bf VS |
958 | /* min update 19.2 MHz */ |
959 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 960 | bool found = false; |
a0c4da24 | 961 | |
6b4bf1c4 VS |
962 | target *= 5; /* fast clock */ |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
965 | |
966 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 967 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 969 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 971 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 972 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 973 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 974 | unsigned int ppm; |
69e4f900 | 975 | |
6b4bf1c4 VS |
976 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
977 | refclk * clock.m1); | |
978 | ||
dccbea3b | 979 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 980 | |
f01b7962 VS |
981 | if (!intel_PLL_is_valid(dev, limit, |
982 | &clock)) | |
43b0ac53 VS |
983 | continue; |
984 | ||
d5dd62bd ID |
985 | if (!vlv_PLL_is_optimal(dev, target, |
986 | &clock, | |
987 | best_clock, | |
988 | bestppm, &ppm)) | |
989 | continue; | |
6b4bf1c4 | 990 | |
d5dd62bd ID |
991 | *best_clock = clock; |
992 | bestppm = ppm; | |
993 | found = true; | |
a0c4da24 JB |
994 | } |
995 | } | |
996 | } | |
997 | } | |
a0c4da24 | 998 | |
49e497ef | 999 | return found; |
a0c4da24 | 1000 | } |
a4fc5ed6 | 1001 | |
ef9348c8 | 1002 | static bool |
a93e255f ACO |
1003 | chv_find_best_dpll(const intel_limit_t *limit, |
1004 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1005 | int target, int refclk, intel_clock_t *match_clock, |
1006 | intel_clock_t *best_clock) | |
1007 | { | |
a93e255f | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1009 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1010 | unsigned int best_error_ppm; |
ef9348c8 CML |
1011 | intel_clock_t clock; |
1012 | uint64_t m2; | |
1013 | int found = false; | |
1014 | ||
1015 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1016 | best_error_ppm = 1000000; |
ef9348c8 CML |
1017 | |
1018 | /* | |
1019 | * Based on hardware doc, the n always set to 1, and m1 always | |
1020 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1021 | * revisit this because n may not 1 anymore. | |
1022 | */ | |
1023 | clock.n = 1, clock.m1 = 2; | |
1024 | target *= 5; /* fast clock */ | |
1025 | ||
1026 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1027 | for (clock.p2 = limit->p2.p2_fast; | |
1028 | clock.p2 >= limit->p2.p2_slow; | |
1029 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1030 | unsigned int error_ppm; |
ef9348c8 CML |
1031 | |
1032 | clock.p = clock.p1 * clock.p2; | |
1033 | ||
1034 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1035 | clock.n) << 22, refclk * clock.m1); | |
1036 | ||
1037 | if (m2 > INT_MAX/clock.m1) | |
1038 | continue; | |
1039 | ||
1040 | clock.m2 = m2; | |
1041 | ||
dccbea3b | 1042 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1043 | |
1044 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1045 | continue; | |
1046 | ||
9ca3ba01 ID |
1047 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1048 | best_error_ppm, &error_ppm)) | |
1049 | continue; | |
1050 | ||
1051 | *best_clock = clock; | |
1052 | best_error_ppm = error_ppm; | |
1053 | found = true; | |
ef9348c8 CML |
1054 | } |
1055 | } | |
1056 | ||
1057 | return found; | |
1058 | } | |
1059 | ||
5ab7b0b7 ID |
1060 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1061 | intel_clock_t *best_clock) | |
1062 | { | |
1063 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1064 | ||
1065 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1066 | target_clock, refclk, NULL, best_clock); | |
1067 | } | |
1068 | ||
20ddf665 VS |
1069 | bool intel_crtc_active(struct drm_crtc *crtc) |
1070 | { | |
1071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1072 | ||
1073 | /* Be paranoid as we can arrive here with only partial | |
1074 | * state retrieved from the hardware during setup. | |
1075 | * | |
241bfc38 | 1076 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1077 | * as Haswell has gained clock readout/fastboot support. |
1078 | * | |
66e514c1 | 1079 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1080 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1081 | * |
1082 | * FIXME: The intel_crtc->active here should be switched to | |
1083 | * crtc->state->active once we have proper CRTC states wired up | |
1084 | * for atomic. | |
20ddf665 | 1085 | */ |
c3d1f436 | 1086 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1087 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1088 | } |
1089 | ||
a5c961d1 PZ |
1090 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1091 | enum pipe pipe) | |
1092 | { | |
1093 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1095 | ||
6e3c9717 | 1096 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1097 | } |
1098 | ||
fbf49ea2 VS |
1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1102 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1103 | u32 line1, line2; |
1104 | u32 line_mask; | |
1105 | ||
1106 | if (IS_GEN2(dev)) | |
1107 | line_mask = DSL_LINEMASK_GEN2; | |
1108 | else | |
1109 | line_mask = DSL_LINEMASK_GEN3; | |
1110 | ||
1111 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1112 | msleep(5); |
fbf49ea2 VS |
1113 | line2 = I915_READ(reg) & line_mask; |
1114 | ||
1115 | return line1 == line2; | |
1116 | } | |
1117 | ||
ab7ad7f6 KP |
1118 | /* |
1119 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1120 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1121 | * |
1122 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1123 | * spinning on the vblank interrupt status bit, since we won't actually | |
1124 | * see an interrupt when the pipe is disabled. | |
1125 | * | |
ab7ad7f6 KP |
1126 | * On Gen4 and above: |
1127 | * wait for the pipe register state bit to turn off | |
1128 | * | |
1129 | * Otherwise: | |
1130 | * wait for the display line value to settle (it usually | |
1131 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1132 | * |
9d0498a2 | 1133 | */ |
575f7ab7 | 1134 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1135 | { |
575f7ab7 | 1136 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1139 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1140 | |
1141 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1143 | |
1144 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1146 | 100)) | |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } else { |
ab7ad7f6 | 1149 | /* Wait for the display line to settle */ |
fbf49ea2 | 1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1151 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1152 | } |
79e53945 JB |
1153 | } |
1154 | ||
b24e7179 | 1155 | /* Only for pre-ILK configs */ |
55607e8a DV |
1156 | void assert_pll(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe, bool state) | |
b24e7179 | 1158 | { |
b24e7179 JB |
1159 | u32 val; |
1160 | bool cur_state; | |
1161 | ||
649636ef | 1162 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1163 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1164 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1165 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1166 | onoff(state), onoff(cur_state)); |
b24e7179 | 1167 | } |
b24e7179 | 1168 | |
23538ef1 JN |
1169 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1170 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1171 | { | |
1172 | u32 val; | |
1173 | bool cur_state; | |
1174 | ||
a580516d | 1175 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1176 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1177 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1178 | |
1179 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1181 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1183 | } |
1184 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1185 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1186 | ||
55607e8a | 1187 | struct intel_shared_dpll * |
e2b78267 DV |
1188 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1189 | { | |
1190 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1191 | ||
6e3c9717 | 1192 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1193 | return NULL; |
1194 | ||
6e3c9717 | 1195 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1196 | } |
1197 | ||
040484af | 1198 | /* For ILK+ */ |
55607e8a DV |
1199 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1200 | struct intel_shared_dpll *pll, | |
1201 | bool state) | |
040484af | 1202 | { |
040484af | 1203 | bool cur_state; |
5358901f | 1204 | struct intel_dpll_hw_state hw_state; |
040484af | 1205 | |
87ad3212 | 1206 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1207 | return; |
ee7b9f93 | 1208 | |
5358901f | 1209 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
5358901f | 1211 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1213 | } |
040484af JB |
1214 | |
1215 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1216 | enum pipe pipe, bool state) | |
1217 | { | |
040484af | 1218 | bool cur_state; |
ad80a810 PZ |
1219 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1220 | pipe); | |
040484af | 1221 | |
affa9354 PZ |
1222 | if (HAS_DDI(dev_priv->dev)) { |
1223 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1224 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1225 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1226 | } else { |
649636ef | 1227 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1228 | cur_state = !!(val & FDI_TX_ENABLE); |
1229 | } | |
e2c719b7 | 1230 | I915_STATE_WARN(cur_state != state, |
040484af | 1231 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1232 | onoff(state), onoff(cur_state)); |
040484af JB |
1233 | } |
1234 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1235 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1236 | ||
1237 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1238 | enum pipe pipe, bool state) | |
1239 | { | |
040484af JB |
1240 | u32 val; |
1241 | bool cur_state; | |
1242 | ||
649636ef | 1243 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1244 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1245 | I915_STATE_WARN(cur_state != state, |
040484af | 1246 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1247 | onoff(state), onoff(cur_state)); |
040484af JB |
1248 | } |
1249 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1250 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1251 | ||
1252 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1253 | enum pipe pipe) | |
1254 | { | |
040484af JB |
1255 | u32 val; |
1256 | ||
1257 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1258 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1259 | return; |
1260 | ||
bf507ef7 | 1261 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1262 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1263 | return; |
1264 | ||
649636ef | 1265 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1266 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1267 | } |
1268 | ||
55607e8a DV |
1269 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1270 | enum pipe pipe, bool state) | |
040484af | 1271 | { |
040484af | 1272 | u32 val; |
55607e8a | 1273 | bool cur_state; |
040484af | 1274 | |
649636ef | 1275 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1276 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1277 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1278 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1279 | onoff(state), onoff(cur_state)); |
040484af JB |
1280 | } |
1281 | ||
b680c37a DV |
1282 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1283 | enum pipe pipe) | |
ea0760cf | 1284 | { |
bedd4dba | 1285 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1286 | i915_reg_t pp_reg; |
ea0760cf JB |
1287 | u32 val; |
1288 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1289 | bool locked = true; |
ea0760cf | 1290 | |
bedd4dba JN |
1291 | if (WARN_ON(HAS_DDI(dev))) |
1292 | return; | |
1293 | ||
1294 | if (HAS_PCH_SPLIT(dev)) { | |
1295 | u32 port_sel; | |
1296 | ||
ea0760cf | 1297 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1298 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1299 | ||
1300 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1301 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1302 | panel_pipe = PIPE_B; | |
1303 | /* XXX: else fix for eDP */ | |
666a4537 | 1304 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1305 | /* presumably write lock depends on pipe, not port select */ |
1306 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1307 | panel_pipe = pipe; | |
ea0760cf JB |
1308 | } else { |
1309 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1310 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1311 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1312 | } |
1313 | ||
1314 | val = I915_READ(pp_reg); | |
1315 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1316 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1317 | locked = false; |
1318 | ||
e2c719b7 | 1319 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1320 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1321 | pipe_name(pipe)); |
ea0760cf JB |
1322 | } |
1323 | ||
93ce0ba6 JN |
1324 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1325 | enum pipe pipe, bool state) | |
1326 | { | |
1327 | struct drm_device *dev = dev_priv->dev; | |
1328 | bool cur_state; | |
1329 | ||
d9d82081 | 1330 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1331 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1332 | else |
5efb3e28 | 1333 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1334 | |
e2c719b7 | 1335 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1336 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1337 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1338 | } |
1339 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1340 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1341 | ||
b840d907 JB |
1342 | void assert_pipe(struct drm_i915_private *dev_priv, |
1343 | enum pipe pipe, bool state) | |
b24e7179 | 1344 | { |
63d7bbe9 | 1345 | bool cur_state; |
702e7a56 PZ |
1346 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1347 | pipe); | |
4feed0eb | 1348 | enum intel_display_power_domain power_domain; |
b24e7179 | 1349 | |
b6b5d049 VS |
1350 | /* if we need the pipe quirk it must be always on */ |
1351 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1352 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1353 | state = true; |
1354 | ||
4feed0eb ID |
1355 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1356 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1357 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1358 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1359 | |
1360 | intel_display_power_put(dev_priv, power_domain); | |
1361 | } else { | |
1362 | cur_state = false; | |
69310161 PZ |
1363 | } |
1364 | ||
e2c719b7 | 1365 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1366 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1367 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1368 | } |
1369 | ||
931872fc CW |
1370 | static void assert_plane(struct drm_i915_private *dev_priv, |
1371 | enum plane plane, bool state) | |
b24e7179 | 1372 | { |
b24e7179 | 1373 | u32 val; |
931872fc | 1374 | bool cur_state; |
b24e7179 | 1375 | |
649636ef | 1376 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1377 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1378 | I915_STATE_WARN(cur_state != state, |
931872fc | 1379 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1380 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1381 | } |
1382 | ||
931872fc CW |
1383 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1384 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1385 | ||
b24e7179 JB |
1386 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1387 | enum pipe pipe) | |
1388 | { | |
653e1026 | 1389 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1390 | int i; |
b24e7179 | 1391 | |
653e1026 VS |
1392 | /* Primary planes are fixed to pipes on gen4+ */ |
1393 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1394 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1395 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1396 | "plane %c assertion failure, should be disabled but not\n", |
1397 | plane_name(pipe)); | |
19ec1358 | 1398 | return; |
28c05794 | 1399 | } |
19ec1358 | 1400 | |
b24e7179 | 1401 | /* Need to check both planes against the pipe */ |
055e393f | 1402 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1403 | u32 val = I915_READ(DSPCNTR(i)); |
1404 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1405 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1406 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1407 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1408 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1409 | } |
1410 | } | |
1411 | ||
19332d7a JB |
1412 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1413 | enum pipe pipe) | |
1414 | { | |
20674eef | 1415 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1416 | int sprite; |
19332d7a | 1417 | |
7feb8b88 | 1418 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1419 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1420 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1421 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1422 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1423 | sprite, pipe_name(pipe)); | |
1424 | } | |
666a4537 | 1425 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1426 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1427 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1428 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1429 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1430 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1431 | } |
1432 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1433 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1436 | plane_name(pipe), pipe_name(pipe)); |
1437 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1438 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1439 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1440 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1441 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1442 | } |
1443 | } | |
1444 | ||
08c71e5e VS |
1445 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1446 | { | |
e2c719b7 | 1447 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1448 | drm_crtc_vblank_put(crtc); |
1449 | } | |
1450 | ||
89eff4be | 1451 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1452 | { |
1453 | u32 val; | |
1454 | bool enabled; | |
1455 | ||
e2c719b7 | 1456 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1457 | |
92f2584a JB |
1458 | val = I915_READ(PCH_DREF_CONTROL); |
1459 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1460 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1461 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1462 | } |
1463 | ||
ab9412ba DV |
1464 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1465 | enum pipe pipe) | |
92f2584a | 1466 | { |
92f2584a JB |
1467 | u32 val; |
1468 | bool enabled; | |
1469 | ||
649636ef | 1470 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1471 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1472 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1473 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1474 | pipe_name(pipe)); | |
92f2584a JB |
1475 | } |
1476 | ||
4e634389 KP |
1477 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1478 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1479 | { |
1480 | if ((val & DP_PORT_EN) == 0) | |
1481 | return false; | |
1482 | ||
1483 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1484 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1485 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1486 | return false; | |
44f37d1f CML |
1487 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1488 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1489 | return false; | |
f0575e92 KP |
1490 | } else { |
1491 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1492 | return false; | |
1493 | } | |
1494 | return true; | |
1495 | } | |
1496 | ||
1519b995 KP |
1497 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1498 | enum pipe pipe, u32 val) | |
1499 | { | |
dc0fa718 | 1500 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1501 | return false; |
1502 | ||
1503 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1504 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1505 | return false; |
44f37d1f CML |
1506 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1507 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1508 | return false; | |
1519b995 | 1509 | } else { |
dc0fa718 | 1510 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1511 | return false; |
1512 | } | |
1513 | return true; | |
1514 | } | |
1515 | ||
1516 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1517 | enum pipe pipe, u32 val) | |
1518 | { | |
1519 | if ((val & LVDS_PORT_EN) == 0) | |
1520 | return false; | |
1521 | ||
1522 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1523 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1524 | return false; | |
1525 | } else { | |
1526 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1527 | return false; | |
1528 | } | |
1529 | return true; | |
1530 | } | |
1531 | ||
1532 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1533 | enum pipe pipe, u32 val) | |
1534 | { | |
1535 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1536 | return false; | |
1537 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1538 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1539 | return false; | |
1540 | } else { | |
1541 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1542 | return false; | |
1543 | } | |
1544 | return true; | |
1545 | } | |
1546 | ||
291906f1 | 1547 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1548 | enum pipe pipe, i915_reg_t reg, |
1549 | u32 port_sel) | |
291906f1 | 1550 | { |
47a05eca | 1551 | u32 val = I915_READ(reg); |
e2c719b7 | 1552 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1553 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1554 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1555 | |
e2c719b7 | 1556 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1557 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1558 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1559 | } |
1560 | ||
1561 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1562 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1563 | { |
47a05eca | 1564 | u32 val = I915_READ(reg); |
e2c719b7 | 1565 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1566 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1567 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1568 | |
e2c719b7 | 1569 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1570 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1571 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1572 | } |
1573 | ||
1574 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1575 | enum pipe pipe) | |
1576 | { | |
291906f1 | 1577 | u32 val; |
291906f1 | 1578 | |
f0575e92 KP |
1579 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1580 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1581 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1582 | |
649636ef | 1583 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1584 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1585 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1586 | pipe_name(pipe)); |
291906f1 | 1587 | |
649636ef | 1588 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1589 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1590 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1591 | pipe_name(pipe)); |
291906f1 | 1592 | |
e2debe91 PZ |
1593 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1594 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1595 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1596 | } |
1597 | ||
d288f65f | 1598 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1599 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1600 | { |
426115cf DV |
1601 | struct drm_device *dev = crtc->base.dev; |
1602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1603 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1604 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1605 | |
426115cf | 1606 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1607 | |
87442f73 | 1608 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1609 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1610 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1611 | |
426115cf DV |
1612 | I915_WRITE(reg, dpll); |
1613 | POSTING_READ(reg); | |
1614 | udelay(150); | |
1615 | ||
1616 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1617 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1618 | ||
d288f65f | 1619 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1620 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1621 | |
1622 | /* We do this three times for luck */ | |
426115cf | 1623 | I915_WRITE(reg, dpll); |
87442f73 DV |
1624 | POSTING_READ(reg); |
1625 | udelay(150); /* wait for warmup */ | |
426115cf | 1626 | I915_WRITE(reg, dpll); |
87442f73 DV |
1627 | POSTING_READ(reg); |
1628 | udelay(150); /* wait for warmup */ | |
426115cf | 1629 | I915_WRITE(reg, dpll); |
87442f73 DV |
1630 | POSTING_READ(reg); |
1631 | udelay(150); /* wait for warmup */ | |
1632 | } | |
1633 | ||
d288f65f | 1634 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1635 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1636 | { |
1637 | struct drm_device *dev = crtc->base.dev; | |
1638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1639 | int pipe = crtc->pipe; | |
1640 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1641 | u32 tmp; |
1642 | ||
1643 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1644 | ||
a580516d | 1645 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1646 | |
1647 | /* Enable back the 10bit clock to display controller */ | |
1648 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1649 | tmp |= DPIO_DCLKP_EN; | |
1650 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1651 | ||
54433e91 VS |
1652 | mutex_unlock(&dev_priv->sb_lock); |
1653 | ||
9d556c99 CML |
1654 | /* |
1655 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1656 | */ | |
1657 | udelay(1); | |
1658 | ||
1659 | /* Enable PLL */ | |
d288f65f | 1660 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1661 | |
1662 | /* Check PLL is locked */ | |
a11b0703 | 1663 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1664 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1665 | ||
a11b0703 | 1666 | /* not sure when this should be written */ |
d288f65f | 1667 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1668 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1669 | } |
1670 | ||
1c4e0274 VS |
1671 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1672 | { | |
1673 | struct intel_crtc *crtc; | |
1674 | int count = 0; | |
1675 | ||
1676 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1677 | count += crtc->base.state->active && |
409ee761 | 1678 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1679 | |
1680 | return count; | |
1681 | } | |
1682 | ||
66e3d5c0 | 1683 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1684 | { |
66e3d5c0 DV |
1685 | struct drm_device *dev = crtc->base.dev; |
1686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1687 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1688 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1689 | |
66e3d5c0 | 1690 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1691 | |
63d7bbe9 | 1692 | /* No really, not for ILK+ */ |
3d13ef2e | 1693 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1694 | |
1695 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1696 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1697 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1698 | |
1c4e0274 VS |
1699 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1700 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1701 | /* | |
1702 | * It appears to be important that we don't enable this | |
1703 | * for the current pipe before otherwise configuring the | |
1704 | * PLL. No idea how this should be handled if multiple | |
1705 | * DVO outputs are enabled simultaneosly. | |
1706 | */ | |
1707 | dpll |= DPLL_DVO_2X_MODE; | |
1708 | I915_WRITE(DPLL(!crtc->pipe), | |
1709 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1710 | } | |
66e3d5c0 | 1711 | |
c2b63374 VS |
1712 | /* |
1713 | * Apparently we need to have VGA mode enabled prior to changing | |
1714 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1715 | * dividers, even though the register value does change. | |
1716 | */ | |
1717 | I915_WRITE(reg, 0); | |
1718 | ||
8e7a65aa VS |
1719 | I915_WRITE(reg, dpll); |
1720 | ||
66e3d5c0 DV |
1721 | /* Wait for the clocks to stabilize. */ |
1722 | POSTING_READ(reg); | |
1723 | udelay(150); | |
1724 | ||
1725 | if (INTEL_INFO(dev)->gen >= 4) { | |
1726 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1727 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1728 | } else { |
1729 | /* The pixel multiplier can only be updated once the | |
1730 | * DPLL is enabled and the clocks are stable. | |
1731 | * | |
1732 | * So write it again. | |
1733 | */ | |
1734 | I915_WRITE(reg, dpll); | |
1735 | } | |
63d7bbe9 JB |
1736 | |
1737 | /* We do this three times for luck */ | |
66e3d5c0 | 1738 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1739 | POSTING_READ(reg); |
1740 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1741 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1742 | POSTING_READ(reg); |
1743 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
1747 | } | |
1748 | ||
1749 | /** | |
50b44a44 | 1750 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1751 | * @dev_priv: i915 private structure |
1752 | * @pipe: pipe PLL to disable | |
1753 | * | |
1754 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1755 | * | |
1756 | * Note! This is for pre-ILK only. | |
1757 | */ | |
1c4e0274 | 1758 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1759 | { |
1c4e0274 VS |
1760 | struct drm_device *dev = crtc->base.dev; |
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1762 | enum pipe pipe = crtc->pipe; | |
1763 | ||
1764 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1765 | if (IS_I830(dev) && | |
409ee761 | 1766 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1767 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1768 | I915_WRITE(DPLL(PIPE_B), |
1769 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1770 | I915_WRITE(DPLL(PIPE_A), | |
1771 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1772 | } | |
1773 | ||
b6b5d049 VS |
1774 | /* Don't disable pipe or pipe PLLs if needed */ |
1775 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1776 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1777 | return; |
1778 | ||
1779 | /* Make sure the pipe isn't still relying on us */ | |
1780 | assert_pipe_disabled(dev_priv, pipe); | |
1781 | ||
b8afb911 | 1782 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1783 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1784 | } |
1785 | ||
f6071166 JB |
1786 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1787 | { | |
b8afb911 | 1788 | u32 val; |
f6071166 JB |
1789 | |
1790 | /* Make sure the pipe isn't still relying on us */ | |
1791 | assert_pipe_disabled(dev_priv, pipe); | |
1792 | ||
e5cbfbfb ID |
1793 | /* |
1794 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1795 | * The latter is needed for VGA hotplug / manual detection. | |
1796 | */ | |
b8afb911 | 1797 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1798 | if (pipe == PIPE_B) |
60bfe44f | 1799 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1800 | I915_WRITE(DPLL(pipe), val); |
1801 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1802 | |
1803 | } | |
1804 | ||
1805 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1806 | { | |
d752048d | 1807 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1808 | u32 val; |
1809 | ||
a11b0703 VS |
1810 | /* Make sure the pipe isn't still relying on us */ |
1811 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1812 | |
a11b0703 | 1813 | /* Set PLL en = 0 */ |
60bfe44f VS |
1814 | val = DPLL_SSC_REF_CLK_CHV | |
1815 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1816 | if (pipe != PIPE_A) |
1817 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1818 | I915_WRITE(DPLL(pipe), val); | |
1819 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1820 | |
a580516d | 1821 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1822 | |
1823 | /* Disable 10bit clock to display controller */ | |
1824 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1825 | val &= ~DPIO_DCLKP_EN; | |
1826 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1827 | ||
a580516d | 1828 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1829 | } |
1830 | ||
e4607fcf | 1831 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1832 | struct intel_digital_port *dport, |
1833 | unsigned int expected_mask) | |
89b667f8 JB |
1834 | { |
1835 | u32 port_mask; | |
f0f59a00 | 1836 | i915_reg_t dpll_reg; |
89b667f8 | 1837 | |
e4607fcf CML |
1838 | switch (dport->port) { |
1839 | case PORT_B: | |
89b667f8 | 1840 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1841 | dpll_reg = DPLL(0); |
e4607fcf CML |
1842 | break; |
1843 | case PORT_C: | |
89b667f8 | 1844 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1845 | dpll_reg = DPLL(0); |
9b6de0a1 | 1846 | expected_mask <<= 4; |
00fc31b7 CML |
1847 | break; |
1848 | case PORT_D: | |
1849 | port_mask = DPLL_PORTD_READY_MASK; | |
1850 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1851 | break; |
1852 | default: | |
1853 | BUG(); | |
1854 | } | |
89b667f8 | 1855 | |
9b6de0a1 VS |
1856 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1857 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1858 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1859 | } |
1860 | ||
b14b1055 DV |
1861 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1862 | { | |
1863 | struct drm_device *dev = crtc->base.dev; | |
1864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1865 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1866 | ||
be19f0ff CW |
1867 | if (WARN_ON(pll == NULL)) |
1868 | return; | |
1869 | ||
3e369b76 | 1870 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1871 | if (pll->active == 0) { |
1872 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1873 | WARN_ON(pll->on); | |
1874 | assert_shared_dpll_disabled(dev_priv, pll); | |
1875 | ||
1876 | pll->mode_set(dev_priv, pll); | |
1877 | } | |
1878 | } | |
1879 | ||
92f2584a | 1880 | /** |
85b3894f | 1881 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1882 | * @dev_priv: i915 private structure |
1883 | * @pipe: pipe PLL to enable | |
1884 | * | |
1885 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1886 | * drives the transcoder clock. | |
1887 | */ | |
85b3894f | 1888 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1889 | { |
3d13ef2e DL |
1890 | struct drm_device *dev = crtc->base.dev; |
1891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1892 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1893 | |
87a875bb | 1894 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1895 | return; |
1896 | ||
3e369b76 | 1897 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1898 | return; |
ee7b9f93 | 1899 | |
74dd6928 | 1900 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1901 | pll->name, pll->active, pll->on, |
e2b78267 | 1902 | crtc->base.base.id); |
92f2584a | 1903 | |
cdbd2316 DV |
1904 | if (pll->active++) { |
1905 | WARN_ON(!pll->on); | |
e9d6944e | 1906 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1907 | return; |
1908 | } | |
f4a091c7 | 1909 | WARN_ON(pll->on); |
ee7b9f93 | 1910 | |
bd2bb1b9 PZ |
1911 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1912 | ||
46edb027 | 1913 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1914 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1915 | pll->on = true; |
92f2584a JB |
1916 | } |
1917 | ||
f6daaec2 | 1918 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1919 | { |
3d13ef2e DL |
1920 | struct drm_device *dev = crtc->base.dev; |
1921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1922 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1923 | |
92f2584a | 1924 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1925 | if (INTEL_INFO(dev)->gen < 5) |
1926 | return; | |
1927 | ||
eddfcbcd ML |
1928 | if (pll == NULL) |
1929 | return; | |
92f2584a | 1930 | |
eddfcbcd | 1931 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1932 | return; |
7a419866 | 1933 | |
46edb027 DV |
1934 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1935 | pll->name, pll->active, pll->on, | |
e2b78267 | 1936 | crtc->base.base.id); |
7a419866 | 1937 | |
48da64a8 | 1938 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1939 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1940 | return; |
1941 | } | |
1942 | ||
e9d6944e | 1943 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1944 | WARN_ON(!pll->on); |
cdbd2316 | 1945 | if (--pll->active) |
7a419866 | 1946 | return; |
ee7b9f93 | 1947 | |
46edb027 | 1948 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1949 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1950 | pll->on = false; |
bd2bb1b9 PZ |
1951 | |
1952 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1953 | } |
1954 | ||
b8a4f404 PZ |
1955 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1956 | enum pipe pipe) | |
040484af | 1957 | { |
23670b32 | 1958 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1959 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1961 | i915_reg_t reg; |
1962 | uint32_t val, pipeconf_val; | |
040484af JB |
1963 | |
1964 | /* PCH only available on ILK+ */ | |
55522f37 | 1965 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1966 | |
1967 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1968 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1969 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1970 | |
1971 | /* FDI must be feeding us bits for PCH ports */ | |
1972 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1973 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1974 | ||
23670b32 DV |
1975 | if (HAS_PCH_CPT(dev)) { |
1976 | /* Workaround: Set the timing override bit before enabling the | |
1977 | * pch transcoder. */ | |
1978 | reg = TRANS_CHICKEN2(pipe); | |
1979 | val = I915_READ(reg); | |
1980 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1981 | I915_WRITE(reg, val); | |
59c859d6 | 1982 | } |
23670b32 | 1983 | |
ab9412ba | 1984 | reg = PCH_TRANSCONF(pipe); |
040484af | 1985 | val = I915_READ(reg); |
5f7f726d | 1986 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1987 | |
1988 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1989 | /* | |
c5de7c6f VS |
1990 | * Make the BPC in transcoder be consistent with |
1991 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1992 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1993 | */ |
dfd07d72 | 1994 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1995 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1996 | val |= PIPECONF_8BPC; | |
1997 | else | |
1998 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1999 | } |
5f7f726d PZ |
2000 | |
2001 | val &= ~TRANS_INTERLACE_MASK; | |
2002 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2003 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2004 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2005 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2006 | else | |
2007 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2008 | else |
2009 | val |= TRANS_PROGRESSIVE; | |
2010 | ||
040484af JB |
2011 | I915_WRITE(reg, val | TRANS_ENABLE); |
2012 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2013 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2014 | } |
2015 | ||
8fb033d7 | 2016 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2017 | enum transcoder cpu_transcoder) |
040484af | 2018 | { |
8fb033d7 | 2019 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2020 | |
2021 | /* PCH only available on ILK+ */ | |
55522f37 | 2022 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2023 | |
8fb033d7 | 2024 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2025 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2026 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2027 | |
223a6fdf | 2028 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2029 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2030 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2031 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2032 | |
25f3ef11 | 2033 | val = TRANS_ENABLE; |
937bb610 | 2034 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2035 | |
9a76b1c6 PZ |
2036 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2037 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2038 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2039 | else |
2040 | val |= TRANS_PROGRESSIVE; | |
2041 | ||
ab9412ba DV |
2042 | I915_WRITE(LPT_TRANSCONF, val); |
2043 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2044 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2045 | } |
2046 | ||
b8a4f404 PZ |
2047 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2048 | enum pipe pipe) | |
040484af | 2049 | { |
23670b32 | 2050 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2051 | i915_reg_t reg; |
2052 | uint32_t val; | |
040484af JB |
2053 | |
2054 | /* FDI relies on the transcoder */ | |
2055 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2056 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2057 | ||
291906f1 JB |
2058 | /* Ports must be off as well */ |
2059 | assert_pch_ports_disabled(dev_priv, pipe); | |
2060 | ||
ab9412ba | 2061 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2062 | val = I915_READ(reg); |
2063 | val &= ~TRANS_ENABLE; | |
2064 | I915_WRITE(reg, val); | |
2065 | /* wait for PCH transcoder off, transcoder state */ | |
2066 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2067 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2068 | |
c465613b | 2069 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2070 | /* Workaround: Clear the timing override chicken bit again. */ |
2071 | reg = TRANS_CHICKEN2(pipe); | |
2072 | val = I915_READ(reg); | |
2073 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2074 | I915_WRITE(reg, val); | |
2075 | } | |
040484af JB |
2076 | } |
2077 | ||
ab4d966c | 2078 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2079 | { |
8fb033d7 PZ |
2080 | u32 val; |
2081 | ||
ab9412ba | 2082 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2083 | val &= ~TRANS_ENABLE; |
ab9412ba | 2084 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2085 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2086 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2087 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2088 | |
2089 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2090 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2091 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2092 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2093 | } |
2094 | ||
b24e7179 | 2095 | /** |
309cfea8 | 2096 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2097 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2098 | * |
0372264a | 2099 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2100 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2101 | */ |
e1fdc473 | 2102 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2103 | { |
0372264a PZ |
2104 | struct drm_device *dev = crtc->base.dev; |
2105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2106 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2107 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2108 | enum pipe pch_transcoder; |
f0f59a00 | 2109 | i915_reg_t reg; |
b24e7179 JB |
2110 | u32 val; |
2111 | ||
9e2ee2dd VS |
2112 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2113 | ||
58c6eaa2 | 2114 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2115 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2116 | assert_sprites_disabled(dev_priv, pipe); |
2117 | ||
681e5811 | 2118 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2119 | pch_transcoder = TRANSCODER_A; |
2120 | else | |
2121 | pch_transcoder = pipe; | |
2122 | ||
b24e7179 JB |
2123 | /* |
2124 | * A pipe without a PLL won't actually be able to drive bits from | |
2125 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2126 | * need the check. | |
2127 | */ | |
50360403 | 2128 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2129 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2130 | assert_dsi_pll_enabled(dev_priv); |
2131 | else | |
2132 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2133 | else { |
6e3c9717 | 2134 | if (crtc->config->has_pch_encoder) { |
040484af | 2135 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2136 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2137 | assert_fdi_tx_pll_enabled(dev_priv, |
2138 | (enum pipe) cpu_transcoder); | |
040484af JB |
2139 | } |
2140 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2141 | } | |
b24e7179 | 2142 | |
702e7a56 | 2143 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2144 | val = I915_READ(reg); |
7ad25d48 | 2145 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2146 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2147 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2148 | return; |
7ad25d48 | 2149 | } |
00d70b15 CW |
2150 | |
2151 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2152 | POSTING_READ(reg); |
b7792d8b VS |
2153 | |
2154 | /* | |
2155 | * Until the pipe starts DSL will read as 0, which would cause | |
2156 | * an apparent vblank timestamp jump, which messes up also the | |
2157 | * frame count when it's derived from the timestamps. So let's | |
2158 | * wait for the pipe to start properly before we call | |
2159 | * drm_crtc_vblank_on() | |
2160 | */ | |
2161 | if (dev->max_vblank_count == 0 && | |
2162 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2163 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2164 | } |
2165 | ||
2166 | /** | |
309cfea8 | 2167 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2168 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2169 | * |
575f7ab7 VS |
2170 | * Disable the pipe of @crtc, making sure that various hardware |
2171 | * specific requirements are met, if applicable, e.g. plane | |
2172 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2173 | * |
2174 | * Will wait until the pipe has shut down before returning. | |
2175 | */ | |
575f7ab7 | 2176 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2177 | { |
575f7ab7 | 2178 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2179 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2180 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2181 | i915_reg_t reg; |
b24e7179 JB |
2182 | u32 val; |
2183 | ||
9e2ee2dd VS |
2184 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2185 | ||
b24e7179 JB |
2186 | /* |
2187 | * Make sure planes won't keep trying to pump pixels to us, | |
2188 | * or we might hang the display. | |
2189 | */ | |
2190 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2191 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2192 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2193 | |
702e7a56 | 2194 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2195 | val = I915_READ(reg); |
00d70b15 CW |
2196 | if ((val & PIPECONF_ENABLE) == 0) |
2197 | return; | |
2198 | ||
67adc644 VS |
2199 | /* |
2200 | * Double wide has implications for planes | |
2201 | * so best keep it disabled when not needed. | |
2202 | */ | |
6e3c9717 | 2203 | if (crtc->config->double_wide) |
67adc644 VS |
2204 | val &= ~PIPECONF_DOUBLE_WIDE; |
2205 | ||
2206 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2207 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2208 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2209 | val &= ~PIPECONF_ENABLE; |
2210 | ||
2211 | I915_WRITE(reg, val); | |
2212 | if ((val & PIPECONF_ENABLE) == 0) | |
2213 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2214 | } |
2215 | ||
693db184 CW |
2216 | static bool need_vtd_wa(struct drm_device *dev) |
2217 | { | |
2218 | #ifdef CONFIG_INTEL_IOMMU | |
2219 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2220 | return true; | |
2221 | #endif | |
2222 | return false; | |
2223 | } | |
2224 | ||
832be82f VS |
2225 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2226 | { | |
2227 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2228 | } | |
2229 | ||
27ba3910 VS |
2230 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2231 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2232 | { |
2233 | switch (fb_modifier) { | |
2234 | case DRM_FORMAT_MOD_NONE: | |
2235 | return cpp; | |
2236 | case I915_FORMAT_MOD_X_TILED: | |
2237 | if (IS_GEN2(dev_priv)) | |
2238 | return 128; | |
2239 | else | |
2240 | return 512; | |
2241 | case I915_FORMAT_MOD_Y_TILED: | |
2242 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2243 | return 128; | |
2244 | else | |
2245 | return 512; | |
2246 | case I915_FORMAT_MOD_Yf_TILED: | |
2247 | switch (cpp) { | |
2248 | case 1: | |
2249 | return 64; | |
2250 | case 2: | |
2251 | case 4: | |
2252 | return 128; | |
2253 | case 8: | |
2254 | case 16: | |
2255 | return 256; | |
2256 | default: | |
2257 | MISSING_CASE(cpp); | |
2258 | return cpp; | |
2259 | } | |
2260 | break; | |
2261 | default: | |
2262 | MISSING_CASE(fb_modifier); | |
2263 | return cpp; | |
2264 | } | |
2265 | } | |
2266 | ||
832be82f VS |
2267 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2268 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2269 | { |
832be82f VS |
2270 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2271 | return 1; | |
2272 | else | |
2273 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2274 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2275 | } |
2276 | ||
8d0deca8 VS |
2277 | /* Return the tile dimensions in pixel units */ |
2278 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2279 | unsigned int *tile_width, | |
2280 | unsigned int *tile_height, | |
2281 | uint64_t fb_modifier, | |
2282 | unsigned int cpp) | |
2283 | { | |
2284 | unsigned int tile_width_bytes = | |
2285 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2286 | ||
2287 | *tile_width = tile_width_bytes / cpp; | |
2288 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2289 | } | |
2290 | ||
6761dd31 TU |
2291 | unsigned int |
2292 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2293 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2294 | { |
832be82f VS |
2295 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2296 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2297 | ||
2298 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2299 | } |
2300 | ||
1663b9d6 VS |
2301 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2302 | { | |
2303 | unsigned int size = 0; | |
2304 | int i; | |
2305 | ||
2306 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2307 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2308 | ||
2309 | return size; | |
2310 | } | |
2311 | ||
75c82a53 | 2312 | static void |
3465c580 VS |
2313 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2314 | const struct drm_framebuffer *fb, | |
2315 | unsigned int rotation) | |
f64b98cd | 2316 | { |
2d7a215f VS |
2317 | if (intel_rotation_90_or_270(rotation)) { |
2318 | *view = i915_ggtt_view_rotated; | |
2319 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2320 | } else { | |
2321 | *view = i915_ggtt_view_normal; | |
2322 | } | |
2323 | } | |
50470bb0 | 2324 | |
2d7a215f VS |
2325 | static void |
2326 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2327 | struct drm_framebuffer *fb) | |
2328 | { | |
2329 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2330 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2331 | |
d9b3288e VS |
2332 | tile_size = intel_tile_size(dev_priv); |
2333 | ||
2334 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2335 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2336 | fb->modifier[0], cpp); | |
d9b3288e | 2337 | |
1663b9d6 VS |
2338 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2339 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2340 | |
89e3e142 | 2341 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2342 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2343 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2344 | fb->modifier[1], cpp); | |
d9b3288e | 2345 | |
2d7a215f | 2346 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2347 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2348 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2349 | } |
f64b98cd TU |
2350 | } |
2351 | ||
603525d7 | 2352 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2353 | { |
2354 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2355 | return 256 * 1024; | |
985b8bb4 | 2356 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2357 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2358 | return 128 * 1024; |
2359 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2360 | return 4 * 1024; | |
2361 | else | |
44c5905e | 2362 | return 0; |
4e9a86b6 VS |
2363 | } |
2364 | ||
603525d7 VS |
2365 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2366 | uint64_t fb_modifier) | |
2367 | { | |
2368 | switch (fb_modifier) { | |
2369 | case DRM_FORMAT_MOD_NONE: | |
2370 | return intel_linear_alignment(dev_priv); | |
2371 | case I915_FORMAT_MOD_X_TILED: | |
2372 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2373 | return 256 * 1024; | |
2374 | return 0; | |
2375 | case I915_FORMAT_MOD_Y_TILED: | |
2376 | case I915_FORMAT_MOD_Yf_TILED: | |
2377 | return 1 * 1024 * 1024; | |
2378 | default: | |
2379 | MISSING_CASE(fb_modifier); | |
2380 | return 0; | |
2381 | } | |
2382 | } | |
2383 | ||
127bd2ac | 2384 | int |
3465c580 VS |
2385 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2386 | unsigned int rotation) | |
6b95a207 | 2387 | { |
850c4cdc | 2388 | struct drm_device *dev = fb->dev; |
ce453d81 | 2389 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2390 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2391 | struct i915_ggtt_view view; |
6b95a207 KH |
2392 | u32 alignment; |
2393 | int ret; | |
2394 | ||
ebcdd39e MR |
2395 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2396 | ||
603525d7 | 2397 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2398 | |
3465c580 | 2399 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2400 | |
693db184 CW |
2401 | /* Note that the w/a also requires 64 PTE of padding following the |
2402 | * bo. We currently fill all unused PTE with the shadow page and so | |
2403 | * we should always have valid PTE following the scanout preventing | |
2404 | * the VT-d warning. | |
2405 | */ | |
2406 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2407 | alignment = 256 * 1024; | |
2408 | ||
d6dd6843 PZ |
2409 | /* |
2410 | * Global gtt pte registers are special registers which actually forward | |
2411 | * writes to a chunk of system memory. Which means that there is no risk | |
2412 | * that the register values disappear as soon as we call | |
2413 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2414 | * pin/unpin/fence and not more. | |
2415 | */ | |
2416 | intel_runtime_pm_get(dev_priv); | |
2417 | ||
7580d774 ML |
2418 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2419 | &view); | |
48b956c5 | 2420 | if (ret) |
b26a6b35 | 2421 | goto err_pm; |
6b95a207 KH |
2422 | |
2423 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2424 | * fence, whereas 965+ only requires a fence if using | |
2425 | * framebuffer compression. For simplicity, we always install | |
2426 | * a fence as the cost is not that onerous. | |
2427 | */ | |
9807216f VK |
2428 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2429 | ret = i915_gem_object_get_fence(obj); | |
2430 | if (ret == -EDEADLK) { | |
2431 | /* | |
2432 | * -EDEADLK means there are no free fences | |
2433 | * no pending flips. | |
2434 | * | |
2435 | * This is propagated to atomic, but it uses | |
2436 | * -EDEADLK to force a locking recovery, so | |
2437 | * change the returned error to -EBUSY. | |
2438 | */ | |
2439 | ret = -EBUSY; | |
2440 | goto err_unpin; | |
2441 | } else if (ret) | |
2442 | goto err_unpin; | |
1690e1eb | 2443 | |
9807216f VK |
2444 | i915_gem_object_pin_fence(obj); |
2445 | } | |
6b95a207 | 2446 | |
d6dd6843 | 2447 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2448 | return 0; |
48b956c5 CW |
2449 | |
2450 | err_unpin: | |
f64b98cd | 2451 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2452 | err_pm: |
d6dd6843 | 2453 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2454 | return ret; |
6b95a207 KH |
2455 | } |
2456 | ||
3465c580 | 2457 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2458 | { |
82bc3b2d | 2459 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2460 | struct i915_ggtt_view view; |
82bc3b2d | 2461 | |
ebcdd39e MR |
2462 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2463 | ||
3465c580 | 2464 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2465 | |
9807216f VK |
2466 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2467 | i915_gem_object_unpin_fence(obj); | |
2468 | ||
f64b98cd | 2469 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2470 | } |
2471 | ||
29cf9491 VS |
2472 | /* |
2473 | * Adjust the tile offset by moving the difference into | |
2474 | * the x/y offsets. | |
2475 | * | |
2476 | * Input tile dimensions and pitch must already be | |
2477 | * rotated to match x and y, and in pixel units. | |
2478 | */ | |
2479 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2480 | unsigned int tile_width, | |
2481 | unsigned int tile_height, | |
2482 | unsigned int tile_size, | |
2483 | unsigned int pitch_tiles, | |
2484 | u32 old_offset, | |
2485 | u32 new_offset) | |
2486 | { | |
2487 | unsigned int tiles; | |
2488 | ||
2489 | WARN_ON(old_offset & (tile_size - 1)); | |
2490 | WARN_ON(new_offset & (tile_size - 1)); | |
2491 | WARN_ON(new_offset > old_offset); | |
2492 | ||
2493 | tiles = (old_offset - new_offset) / tile_size; | |
2494 | ||
2495 | *y += tiles / pitch_tiles * tile_height; | |
2496 | *x += tiles % pitch_tiles * tile_width; | |
2497 | ||
2498 | return new_offset; | |
2499 | } | |
2500 | ||
8d0deca8 VS |
2501 | /* |
2502 | * Computes the linear offset to the base tile and adjusts | |
2503 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2504 | * | |
2505 | * In the 90/270 rotated case, x and y are assumed | |
2506 | * to be already rotated to match the rotated GTT view, and | |
2507 | * pitch is the tile_height aligned framebuffer height. | |
2508 | */ | |
4f2d9934 VS |
2509 | u32 intel_compute_tile_offset(int *x, int *y, |
2510 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2511 | unsigned int pitch, |
2512 | unsigned int rotation) | |
c2c75131 | 2513 | { |
4f2d9934 VS |
2514 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2515 | uint64_t fb_modifier = fb->modifier[plane]; | |
2516 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2517 | u32 offset, offset_aligned, alignment; |
2518 | ||
2519 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2520 | if (alignment) | |
2521 | alignment--; | |
2522 | ||
b5c65338 | 2523 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2524 | unsigned int tile_size, tile_width, tile_height; |
2525 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2526 | |
d843310d | 2527 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2528 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2529 | fb_modifier, cpp); | |
2530 | ||
2531 | if (intel_rotation_90_or_270(rotation)) { | |
2532 | pitch_tiles = pitch / tile_height; | |
2533 | swap(tile_width, tile_height); | |
2534 | } else { | |
2535 | pitch_tiles = pitch / (tile_width * cpp); | |
2536 | } | |
d843310d VS |
2537 | |
2538 | tile_rows = *y / tile_height; | |
2539 | *y %= tile_height; | |
c2c75131 | 2540 | |
8d0deca8 VS |
2541 | tiles = *x / tile_width; |
2542 | *x %= tile_width; | |
bc752862 | 2543 | |
29cf9491 VS |
2544 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2545 | offset_aligned = offset & ~alignment; | |
bc752862 | 2546 | |
29cf9491 VS |
2547 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2548 | tile_size, pitch_tiles, | |
2549 | offset, offset_aligned); | |
2550 | } else { | |
bc752862 | 2551 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2552 | offset_aligned = offset & ~alignment; |
2553 | ||
4e9a86b6 VS |
2554 | *y = (offset & alignment) / pitch; |
2555 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2556 | } |
29cf9491 VS |
2557 | |
2558 | return offset_aligned; | |
c2c75131 DV |
2559 | } |
2560 | ||
b35d63fa | 2561 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2562 | { |
2563 | switch (format) { | |
2564 | case DISPPLANE_8BPP: | |
2565 | return DRM_FORMAT_C8; | |
2566 | case DISPPLANE_BGRX555: | |
2567 | return DRM_FORMAT_XRGB1555; | |
2568 | case DISPPLANE_BGRX565: | |
2569 | return DRM_FORMAT_RGB565; | |
2570 | default: | |
2571 | case DISPPLANE_BGRX888: | |
2572 | return DRM_FORMAT_XRGB8888; | |
2573 | case DISPPLANE_RGBX888: | |
2574 | return DRM_FORMAT_XBGR8888; | |
2575 | case DISPPLANE_BGRX101010: | |
2576 | return DRM_FORMAT_XRGB2101010; | |
2577 | case DISPPLANE_RGBX101010: | |
2578 | return DRM_FORMAT_XBGR2101010; | |
2579 | } | |
2580 | } | |
2581 | ||
bc8d7dff DL |
2582 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2583 | { | |
2584 | switch (format) { | |
2585 | case PLANE_CTL_FORMAT_RGB_565: | |
2586 | return DRM_FORMAT_RGB565; | |
2587 | default: | |
2588 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2589 | if (rgb_order) { | |
2590 | if (alpha) | |
2591 | return DRM_FORMAT_ABGR8888; | |
2592 | else | |
2593 | return DRM_FORMAT_XBGR8888; | |
2594 | } else { | |
2595 | if (alpha) | |
2596 | return DRM_FORMAT_ARGB8888; | |
2597 | else | |
2598 | return DRM_FORMAT_XRGB8888; | |
2599 | } | |
2600 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2601 | if (rgb_order) | |
2602 | return DRM_FORMAT_XBGR2101010; | |
2603 | else | |
2604 | return DRM_FORMAT_XRGB2101010; | |
2605 | } | |
2606 | } | |
2607 | ||
5724dbd1 | 2608 | static bool |
f6936e29 DV |
2609 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2610 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2611 | { |
2612 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2613 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2614 | struct drm_i915_gem_object *obj = NULL; |
2615 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2616 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2617 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2618 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2619 | PAGE_SIZE); | |
2620 | ||
2621 | size_aligned -= base_aligned; | |
46f297fb | 2622 | |
ff2652ea CW |
2623 | if (plane_config->size == 0) |
2624 | return false; | |
2625 | ||
3badb49f PZ |
2626 | /* If the FB is too big, just don't use it since fbdev is not very |
2627 | * important and we should probably use that space with FBC or other | |
2628 | * features. */ | |
2629 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2630 | return false; | |
2631 | ||
12c83d99 TU |
2632 | mutex_lock(&dev->struct_mutex); |
2633 | ||
f37b5c2b DV |
2634 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2635 | base_aligned, | |
2636 | base_aligned, | |
2637 | size_aligned); | |
12c83d99 TU |
2638 | if (!obj) { |
2639 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2640 | return false; |
12c83d99 | 2641 | } |
46f297fb | 2642 | |
49af449b DL |
2643 | obj->tiling_mode = plane_config->tiling; |
2644 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2645 | obj->stride = fb->pitches[0]; |
46f297fb | 2646 | |
6bf129df DL |
2647 | mode_cmd.pixel_format = fb->pixel_format; |
2648 | mode_cmd.width = fb->width; | |
2649 | mode_cmd.height = fb->height; | |
2650 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2651 | mode_cmd.modifier[0] = fb->modifier[0]; |
2652 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2653 | |
6bf129df | 2654 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2655 | &mode_cmd, obj)) { |
46f297fb JB |
2656 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2657 | goto out_unref_obj; | |
2658 | } | |
12c83d99 | 2659 | |
46f297fb | 2660 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2661 | |
f6936e29 | 2662 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2663 | return true; |
46f297fb JB |
2664 | |
2665 | out_unref_obj: | |
2666 | drm_gem_object_unreference(&obj->base); | |
2667 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2668 | return false; |
2669 | } | |
2670 | ||
afd65eb4 MR |
2671 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2672 | static void | |
2673 | update_state_fb(struct drm_plane *plane) | |
2674 | { | |
2675 | if (plane->fb == plane->state->fb) | |
2676 | return; | |
2677 | ||
2678 | if (plane->state->fb) | |
2679 | drm_framebuffer_unreference(plane->state->fb); | |
2680 | plane->state->fb = plane->fb; | |
2681 | if (plane->state->fb) | |
2682 | drm_framebuffer_reference(plane->state->fb); | |
2683 | } | |
2684 | ||
5724dbd1 | 2685 | static void |
f6936e29 DV |
2686 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2687 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2688 | { |
2689 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2690 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2691 | struct drm_crtc *c; |
2692 | struct intel_crtc *i; | |
2ff8fde1 | 2693 | struct drm_i915_gem_object *obj; |
88595ac9 | 2694 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2695 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2696 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2697 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2698 | struct intel_plane_state *intel_state = |
2699 | to_intel_plane_state(plane_state); | |
88595ac9 | 2700 | struct drm_framebuffer *fb; |
484b41dd | 2701 | |
2d14030b | 2702 | if (!plane_config->fb) |
484b41dd JB |
2703 | return; |
2704 | ||
f6936e29 | 2705 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2706 | fb = &plane_config->fb->base; |
2707 | goto valid_fb; | |
f55548b5 | 2708 | } |
484b41dd | 2709 | |
2d14030b | 2710 | kfree(plane_config->fb); |
484b41dd JB |
2711 | |
2712 | /* | |
2713 | * Failed to alloc the obj, check to see if we should share | |
2714 | * an fb with another CRTC instead | |
2715 | */ | |
70e1e0ec | 2716 | for_each_crtc(dev, c) { |
484b41dd JB |
2717 | i = to_intel_crtc(c); |
2718 | ||
2719 | if (c == &intel_crtc->base) | |
2720 | continue; | |
2721 | ||
2ff8fde1 MR |
2722 | if (!i->active) |
2723 | continue; | |
2724 | ||
88595ac9 DV |
2725 | fb = c->primary->fb; |
2726 | if (!fb) | |
484b41dd JB |
2727 | continue; |
2728 | ||
88595ac9 | 2729 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2730 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2731 | drm_framebuffer_reference(fb); |
2732 | goto valid_fb; | |
484b41dd JB |
2733 | } |
2734 | } | |
88595ac9 | 2735 | |
200757f5 MR |
2736 | /* |
2737 | * We've failed to reconstruct the BIOS FB. Current display state | |
2738 | * indicates that the primary plane is visible, but has a NULL FB, | |
2739 | * which will lead to problems later if we don't fix it up. The | |
2740 | * simplest solution is to just disable the primary plane now and | |
2741 | * pretend the BIOS never had it enabled. | |
2742 | */ | |
2743 | to_intel_plane_state(plane_state)->visible = false; | |
2744 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2745 | intel_pre_disable_primary(&intel_crtc->base); | |
2746 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2747 | ||
88595ac9 DV |
2748 | return; |
2749 | ||
2750 | valid_fb: | |
f44e2659 VS |
2751 | plane_state->src_x = 0; |
2752 | plane_state->src_y = 0; | |
be5651f2 ML |
2753 | plane_state->src_w = fb->width << 16; |
2754 | plane_state->src_h = fb->height << 16; | |
2755 | ||
f44e2659 VS |
2756 | plane_state->crtc_x = 0; |
2757 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2758 | plane_state->crtc_w = fb->width; |
2759 | plane_state->crtc_h = fb->height; | |
2760 | ||
0a8d8a86 MR |
2761 | intel_state->src.x1 = plane_state->src_x; |
2762 | intel_state->src.y1 = plane_state->src_y; | |
2763 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2764 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2765 | intel_state->dst.x1 = plane_state->crtc_x; | |
2766 | intel_state->dst.y1 = plane_state->crtc_y; | |
2767 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2768 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2769 | ||
88595ac9 DV |
2770 | obj = intel_fb_obj(fb); |
2771 | if (obj->tiling_mode != I915_TILING_NONE) | |
2772 | dev_priv->preserve_bios_swizzle = true; | |
2773 | ||
be5651f2 ML |
2774 | drm_framebuffer_reference(fb); |
2775 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2776 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2777 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2778 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2779 | } |
2780 | ||
a8d201af ML |
2781 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2782 | const struct intel_crtc_state *crtc_state, | |
2783 | const struct intel_plane_state *plane_state) | |
81255565 | 2784 | { |
a8d201af | 2785 | struct drm_device *dev = primary->dev; |
81255565 | 2786 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2788 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2789 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2790 | int plane = intel_crtc->plane; |
54ea9da8 | 2791 | u32 linear_offset; |
81255565 | 2792 | u32 dspcntr; |
f0f59a00 | 2793 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2794 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2795 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2796 | int x = plane_state->src.x1 >> 16; |
2797 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2798 | |
f45651ba VS |
2799 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2800 | ||
fdd508a6 | 2801 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2802 | |
2803 | if (INTEL_INFO(dev)->gen < 4) { | |
2804 | if (intel_crtc->pipe == PIPE_B) | |
2805 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2806 | ||
2807 | /* pipesrc and dspsize control the size that is scaled from, | |
2808 | * which should always be the user's requested size. | |
2809 | */ | |
2810 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2811 | ((crtc_state->pipe_src_h - 1) << 16) | |
2812 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2813 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2814 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2815 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2816 | ((crtc_state->pipe_src_h - 1) << 16) | |
2817 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2818 | I915_WRITE(PRIMPOS(plane), 0); |
2819 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2820 | } |
81255565 | 2821 | |
57779d06 VS |
2822 | switch (fb->pixel_format) { |
2823 | case DRM_FORMAT_C8: | |
81255565 JB |
2824 | dspcntr |= DISPPLANE_8BPP; |
2825 | break; | |
57779d06 | 2826 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2827 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2828 | break; |
57779d06 VS |
2829 | case DRM_FORMAT_RGB565: |
2830 | dspcntr |= DISPPLANE_BGRX565; | |
2831 | break; | |
2832 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2833 | dspcntr |= DISPPLANE_BGRX888; |
2834 | break; | |
2835 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2836 | dspcntr |= DISPPLANE_RGBX888; |
2837 | break; | |
2838 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2839 | dspcntr |= DISPPLANE_BGRX101010; |
2840 | break; | |
2841 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2842 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2843 | break; |
2844 | default: | |
baba133a | 2845 | BUG(); |
81255565 | 2846 | } |
57779d06 | 2847 | |
f45651ba VS |
2848 | if (INTEL_INFO(dev)->gen >= 4 && |
2849 | obj->tiling_mode != I915_TILING_NONE) | |
2850 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2851 | |
de1aa629 VS |
2852 | if (IS_G4X(dev)) |
2853 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2854 | ||
ac484963 | 2855 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2856 | |
c2c75131 DV |
2857 | if (INTEL_INFO(dev)->gen >= 4) { |
2858 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2859 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2860 | fb->pitches[0], rotation); |
c2c75131 DV |
2861 | linear_offset -= intel_crtc->dspaddr_offset; |
2862 | } else { | |
e506a0c6 | 2863 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2864 | } |
e506a0c6 | 2865 | |
8d0deca8 | 2866 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2867 | dspcntr |= DISPPLANE_ROTATE_180; |
2868 | ||
a8d201af ML |
2869 | x += (crtc_state->pipe_src_w - 1); |
2870 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2871 | |
2872 | /* Finding the last pixel of the last line of the display | |
2873 | data and adding to linear_offset*/ | |
2874 | linear_offset += | |
a8d201af | 2875 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2876 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2877 | } |
2878 | ||
2db3366b PZ |
2879 | intel_crtc->adjusted_x = x; |
2880 | intel_crtc->adjusted_y = y; | |
2881 | ||
48404c1e SJ |
2882 | I915_WRITE(reg, dspcntr); |
2883 | ||
01f2c773 | 2884 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2885 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2886 | I915_WRITE(DSPSURF(plane), |
2887 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2888 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2889 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2890 | } else |
f343c5f6 | 2891 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2892 | POSTING_READ(reg); |
17638cd6 JB |
2893 | } |
2894 | ||
a8d201af ML |
2895 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2896 | struct drm_crtc *crtc) | |
17638cd6 JB |
2897 | { |
2898 | struct drm_device *dev = crtc->dev; | |
2899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2901 | int plane = intel_crtc->plane; |
f45651ba | 2902 | |
a8d201af ML |
2903 | I915_WRITE(DSPCNTR(plane), 0); |
2904 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2905 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2906 | else |
2907 | I915_WRITE(DSPADDR(plane), 0); | |
2908 | POSTING_READ(DSPCNTR(plane)); | |
2909 | } | |
c9ba6fad | 2910 | |
a8d201af ML |
2911 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2912 | const struct intel_crtc_state *crtc_state, | |
2913 | const struct intel_plane_state *plane_state) | |
2914 | { | |
2915 | struct drm_device *dev = primary->dev; | |
2916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2918 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2919 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2920 | int plane = intel_crtc->plane; | |
54ea9da8 | 2921 | u32 linear_offset; |
a8d201af ML |
2922 | u32 dspcntr; |
2923 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2924 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2925 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2926 | int x = plane_state->src.x1 >> 16; |
2927 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2928 | |
f45651ba | 2929 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2930 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2931 | |
2932 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2933 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2934 | |
57779d06 VS |
2935 | switch (fb->pixel_format) { |
2936 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2937 | dspcntr |= DISPPLANE_8BPP; |
2938 | break; | |
57779d06 VS |
2939 | case DRM_FORMAT_RGB565: |
2940 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2941 | break; |
57779d06 | 2942 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2943 | dspcntr |= DISPPLANE_BGRX888; |
2944 | break; | |
2945 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2946 | dspcntr |= DISPPLANE_RGBX888; |
2947 | break; | |
2948 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2949 | dspcntr |= DISPPLANE_BGRX101010; |
2950 | break; | |
2951 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2952 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2953 | break; |
2954 | default: | |
baba133a | 2955 | BUG(); |
17638cd6 JB |
2956 | } |
2957 | ||
2958 | if (obj->tiling_mode != I915_TILING_NONE) | |
2959 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2960 | |
f45651ba | 2961 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2962 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2963 | |
ac484963 | 2964 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2965 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2966 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2967 | fb->pitches[0], rotation); |
c2c75131 | 2968 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2969 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2970 | dspcntr |= DISPPLANE_ROTATE_180; |
2971 | ||
2972 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2973 | x += (crtc_state->pipe_src_w - 1); |
2974 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2975 | |
2976 | /* Finding the last pixel of the last line of the display | |
2977 | data and adding to linear_offset*/ | |
2978 | linear_offset += | |
a8d201af | 2979 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2980 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2981 | } |
2982 | } | |
2983 | ||
2db3366b PZ |
2984 | intel_crtc->adjusted_x = x; |
2985 | intel_crtc->adjusted_y = y; | |
2986 | ||
48404c1e | 2987 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2988 | |
01f2c773 | 2989 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2990 | I915_WRITE(DSPSURF(plane), |
2991 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2992 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2993 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2994 | } else { | |
2995 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2996 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2997 | } | |
17638cd6 | 2998 | POSTING_READ(reg); |
17638cd6 JB |
2999 | } |
3000 | ||
7b49f948 VS |
3001 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3002 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3003 | { |
7b49f948 | 3004 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3005 | return 64; |
7b49f948 VS |
3006 | } else { |
3007 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3008 | ||
27ba3910 | 3009 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3010 | } |
3011 | } | |
3012 | ||
44eb0cb9 MK |
3013 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
3014 | struct drm_i915_gem_object *obj, | |
3015 | unsigned int plane) | |
121920fa | 3016 | { |
ce7f1728 | 3017 | struct i915_ggtt_view view; |
dedf278c | 3018 | struct i915_vma *vma; |
44eb0cb9 | 3019 | u64 offset; |
121920fa | 3020 | |
e7941294 | 3021 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 3022 | intel_plane->base.state->rotation); |
121920fa | 3023 | |
ce7f1728 | 3024 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 3025 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 3026 | view.type)) |
dedf278c TU |
3027 | return -1; |
3028 | ||
44eb0cb9 | 3029 | offset = vma->node.start; |
dedf278c TU |
3030 | |
3031 | if (plane == 1) { | |
7723f47d | 3032 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
3033 | PAGE_SIZE; |
3034 | } | |
3035 | ||
44eb0cb9 MK |
3036 | WARN_ON(upper_32_bits(offset)); |
3037 | ||
3038 | return lower_32_bits(offset); | |
121920fa TU |
3039 | } |
3040 | ||
e435d6e5 ML |
3041 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3042 | { | |
3043 | struct drm_device *dev = intel_crtc->base.dev; | |
3044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3045 | ||
3046 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3047 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3048 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3049 | } |
3050 | ||
a1b2278e CK |
3051 | /* |
3052 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3053 | */ | |
0583236e | 3054 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3055 | { |
a1b2278e CK |
3056 | struct intel_crtc_scaler_state *scaler_state; |
3057 | int i; | |
3058 | ||
a1b2278e CK |
3059 | scaler_state = &intel_crtc->config->scaler_state; |
3060 | ||
3061 | /* loop through and disable scalers that aren't in use */ | |
3062 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3063 | if (!scaler_state->scalers[i].in_use) |
3064 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3065 | } |
3066 | } | |
3067 | ||
6156a456 | 3068 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3069 | { |
6156a456 | 3070 | switch (pixel_format) { |
d161cf7a | 3071 | case DRM_FORMAT_C8: |
c34ce3d1 | 3072 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3073 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3074 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3075 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3076 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3077 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3078 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3079 | /* |
3080 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3081 | * to be already pre-multiplied. We need to add a knob (or a different | |
3082 | * DRM_FORMAT) for user-space to configure that. | |
3083 | */ | |
f75fb42a | 3084 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3085 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3086 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3087 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3088 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3089 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3090 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3091 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3092 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3093 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3094 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3095 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3096 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3097 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3098 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3099 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3100 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3101 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3102 | default: |
4249eeef | 3103 | MISSING_CASE(pixel_format); |
70d21f0e | 3104 | } |
8cfcba41 | 3105 | |
c34ce3d1 | 3106 | return 0; |
6156a456 | 3107 | } |
70d21f0e | 3108 | |
6156a456 CK |
3109 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3110 | { | |
6156a456 | 3111 | switch (fb_modifier) { |
30af77c4 | 3112 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3113 | break; |
30af77c4 | 3114 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3115 | return PLANE_CTL_TILED_X; |
b321803d | 3116 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3117 | return PLANE_CTL_TILED_Y; |
b321803d | 3118 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3119 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3120 | default: |
6156a456 | 3121 | MISSING_CASE(fb_modifier); |
70d21f0e | 3122 | } |
8cfcba41 | 3123 | |
c34ce3d1 | 3124 | return 0; |
6156a456 | 3125 | } |
70d21f0e | 3126 | |
6156a456 CK |
3127 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3128 | { | |
3b7a5119 | 3129 | switch (rotation) { |
6156a456 CK |
3130 | case BIT(DRM_ROTATE_0): |
3131 | break; | |
1e8df167 SJ |
3132 | /* |
3133 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3134 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3135 | */ | |
3b7a5119 | 3136 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3137 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3138 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3139 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3140 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3141 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3142 | default: |
3143 | MISSING_CASE(rotation); | |
3144 | } | |
3145 | ||
c34ce3d1 | 3146 | return 0; |
6156a456 CK |
3147 | } |
3148 | ||
a8d201af ML |
3149 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3150 | const struct intel_crtc_state *crtc_state, | |
3151 | const struct intel_plane_state *plane_state) | |
6156a456 | 3152 | { |
a8d201af | 3153 | struct drm_device *dev = plane->dev; |
6156a456 | 3154 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3156 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3157 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3158 | int pipe = intel_crtc->pipe; |
3159 | u32 plane_ctl, stride_div, stride; | |
3160 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3161 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3162 | int x_offset, y_offset; |
44eb0cb9 | 3163 | u32 surf_addr; |
a8d201af ML |
3164 | int scaler_id = plane_state->scaler_id; |
3165 | int src_x = plane_state->src.x1 >> 16; | |
3166 | int src_y = plane_state->src.y1 >> 16; | |
3167 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3168 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3169 | int dst_x = plane_state->dst.x1; | |
3170 | int dst_y = plane_state->dst.y1; | |
3171 | int dst_w = drm_rect_width(&plane_state->dst); | |
3172 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3173 | |
6156a456 CK |
3174 | plane_ctl = PLANE_CTL_ENABLE | |
3175 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3176 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3177 | ||
3178 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3179 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3180 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3181 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3182 | ||
7b49f948 | 3183 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3184 | fb->pixel_format); |
dedf278c | 3185 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3186 | |
a42e5a23 PZ |
3187 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3188 | ||
3b7a5119 | 3189 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3190 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3191 | ||
3b7a5119 | 3192 | /* stride = Surface height in tiles */ |
832be82f | 3193 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3194 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3195 | x_offset = stride * tile_height - src_y - src_h; |
3196 | y_offset = src_x; | |
6156a456 | 3197 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3198 | } else { |
3199 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3200 | x_offset = src_x; |
3201 | y_offset = src_y; | |
6156a456 | 3202 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3203 | } |
3204 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3205 | |
2db3366b PZ |
3206 | intel_crtc->adjusted_x = x_offset; |
3207 | intel_crtc->adjusted_y = y_offset; | |
3208 | ||
70d21f0e | 3209 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3210 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3211 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3212 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3213 | |
3214 | if (scaler_id >= 0) { | |
3215 | uint32_t ps_ctrl = 0; | |
3216 | ||
3217 | WARN_ON(!dst_w || !dst_h); | |
3218 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3219 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3220 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3221 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3222 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3223 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3224 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3225 | } else { | |
3226 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3227 | } | |
3228 | ||
121920fa | 3229 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3230 | |
3231 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3232 | } | |
3233 | ||
a8d201af ML |
3234 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3235 | struct drm_crtc *crtc) | |
17638cd6 JB |
3236 | { |
3237 | struct drm_device *dev = crtc->dev; | |
3238 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3239 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3240 | |
a8d201af ML |
3241 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3242 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3243 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3244 | } | |
29b9bde6 | 3245 | |
a8d201af ML |
3246 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3247 | static int | |
3248 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3249 | int x, int y, enum mode_set_atomic state) | |
3250 | { | |
3251 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3252 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3253 | ||
3254 | return -ENODEV; | |
81255565 JB |
3255 | } |
3256 | ||
7514747d | 3257 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3258 | { |
96a02917 VS |
3259 | struct drm_crtc *crtc; |
3260 | ||
70e1e0ec | 3261 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3263 | enum plane plane = intel_crtc->plane; | |
3264 | ||
3265 | intel_prepare_page_flip(dev, plane); | |
3266 | intel_finish_page_flip_plane(dev, plane); | |
3267 | } | |
7514747d VS |
3268 | } |
3269 | ||
3270 | static void intel_update_primary_planes(struct drm_device *dev) | |
3271 | { | |
7514747d | 3272 | struct drm_crtc *crtc; |
96a02917 | 3273 | |
70e1e0ec | 3274 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3275 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3276 | struct intel_plane_state *plane_state; | |
96a02917 | 3277 | |
11c22da6 | 3278 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3279 | plane_state = to_intel_plane_state(plane->base.state); |
3280 | ||
a8d201af ML |
3281 | if (plane_state->visible) |
3282 | plane->update_plane(&plane->base, | |
3283 | to_intel_crtc_state(crtc->state), | |
3284 | plane_state); | |
11c22da6 ML |
3285 | |
3286 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3287 | } |
3288 | } | |
3289 | ||
7514747d VS |
3290 | void intel_prepare_reset(struct drm_device *dev) |
3291 | { | |
3292 | /* no reset support for gen2 */ | |
3293 | if (IS_GEN2(dev)) | |
3294 | return; | |
3295 | ||
3296 | /* reset doesn't touch the display */ | |
3297 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3298 | return; | |
3299 | ||
3300 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3301 | /* |
3302 | * Disabling the crtcs gracefully seems nicer. Also the | |
3303 | * g33 docs say we should at least disable all the planes. | |
3304 | */ | |
6b72d486 | 3305 | intel_display_suspend(dev); |
7514747d VS |
3306 | } |
3307 | ||
3308 | void intel_finish_reset(struct drm_device *dev) | |
3309 | { | |
3310 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3311 | ||
3312 | /* | |
3313 | * Flips in the rings will be nuked by the reset, | |
3314 | * so complete all pending flips so that user space | |
3315 | * will get its events and not get stuck. | |
3316 | */ | |
3317 | intel_complete_page_flips(dev); | |
3318 | ||
3319 | /* no reset support for gen2 */ | |
3320 | if (IS_GEN2(dev)) | |
3321 | return; | |
3322 | ||
3323 | /* reset doesn't touch the display */ | |
3324 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3325 | /* | |
3326 | * Flips in the rings have been nuked by the reset, | |
3327 | * so update the base address of all primary | |
3328 | * planes to the the last fb to make sure we're | |
3329 | * showing the correct fb after a reset. | |
11c22da6 ML |
3330 | * |
3331 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3332 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3333 | */ |
3334 | intel_update_primary_planes(dev); | |
3335 | return; | |
3336 | } | |
3337 | ||
3338 | /* | |
3339 | * The display has been reset as well, | |
3340 | * so need a full re-initialization. | |
3341 | */ | |
3342 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3343 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3344 | ||
3345 | intel_modeset_init_hw(dev); | |
3346 | ||
3347 | spin_lock_irq(&dev_priv->irq_lock); | |
3348 | if (dev_priv->display.hpd_irq_setup) | |
3349 | dev_priv->display.hpd_irq_setup(dev); | |
3350 | spin_unlock_irq(&dev_priv->irq_lock); | |
3351 | ||
043e9bda | 3352 | intel_display_resume(dev); |
7514747d VS |
3353 | |
3354 | intel_hpd_init(dev_priv); | |
3355 | ||
3356 | drm_modeset_unlock_all(dev); | |
3357 | } | |
3358 | ||
7d5e3799 CW |
3359 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3360 | { | |
3361 | struct drm_device *dev = crtc->dev; | |
3362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3363 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3364 | bool pending; |
3365 | ||
3366 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3367 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3368 | return false; | |
3369 | ||
5e2d7afc | 3370 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3371 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3372 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3373 | |
3374 | return pending; | |
3375 | } | |
3376 | ||
bfd16b2a ML |
3377 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3378 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3379 | { |
3380 | struct drm_device *dev = crtc->base.dev; | |
3381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3382 | struct intel_crtc_state *pipe_config = |
3383 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3384 | |
bfd16b2a ML |
3385 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3386 | crtc->base.mode = crtc->base.state->mode; | |
3387 | ||
3388 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3389 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3390 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3391 | |
44522d85 ML |
3392 | if (HAS_DDI(dev)) |
3393 | intel_set_pipe_csc(&crtc->base); | |
3394 | ||
e30e8f75 GP |
3395 | /* |
3396 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3397 | * that in compute_mode_changes we check the native mode (not the pfit | |
3398 | * mode) to see if we can flip rather than do a full mode set. In the | |
3399 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3400 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3401 | * sized surface. | |
e30e8f75 GP |
3402 | */ |
3403 | ||
e30e8f75 | 3404 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3405 | ((pipe_config->pipe_src_w - 1) << 16) | |
3406 | (pipe_config->pipe_src_h - 1)); | |
3407 | ||
3408 | /* on skylake this is done by detaching scalers */ | |
3409 | if (INTEL_INFO(dev)->gen >= 9) { | |
3410 | skl_detach_scalers(crtc); | |
3411 | ||
3412 | if (pipe_config->pch_pfit.enabled) | |
3413 | skylake_pfit_enable(crtc); | |
3414 | } else if (HAS_PCH_SPLIT(dev)) { | |
3415 | if (pipe_config->pch_pfit.enabled) | |
3416 | ironlake_pfit_enable(crtc); | |
3417 | else if (old_crtc_state->pch_pfit.enabled) | |
3418 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3419 | } |
e30e8f75 GP |
3420 | } |
3421 | ||
5e84e1a4 ZW |
3422 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3423 | { | |
3424 | struct drm_device *dev = crtc->dev; | |
3425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3427 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3428 | i915_reg_t reg; |
3429 | u32 temp; | |
5e84e1a4 ZW |
3430 | |
3431 | /* enable normal train */ | |
3432 | reg = FDI_TX_CTL(pipe); | |
3433 | temp = I915_READ(reg); | |
61e499bf | 3434 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3435 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3436 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3437 | } else { |
3438 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3439 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3440 | } |
5e84e1a4 ZW |
3441 | I915_WRITE(reg, temp); |
3442 | ||
3443 | reg = FDI_RX_CTL(pipe); | |
3444 | temp = I915_READ(reg); | |
3445 | if (HAS_PCH_CPT(dev)) { | |
3446 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3447 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3448 | } else { | |
3449 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3450 | temp |= FDI_LINK_TRAIN_NONE; | |
3451 | } | |
3452 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3453 | ||
3454 | /* wait one idle pattern time */ | |
3455 | POSTING_READ(reg); | |
3456 | udelay(1000); | |
357555c0 JB |
3457 | |
3458 | /* IVB wants error correction enabled */ | |
3459 | if (IS_IVYBRIDGE(dev)) | |
3460 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3461 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3462 | } |
3463 | ||
8db9d77b ZW |
3464 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3465 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3466 | { | |
3467 | struct drm_device *dev = crtc->dev; | |
3468 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3469 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3470 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3471 | i915_reg_t reg; |
3472 | u32 temp, tries; | |
8db9d77b | 3473 | |
1c8562f6 | 3474 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3475 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3476 | |
e1a44743 AJ |
3477 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3478 | for train result */ | |
5eddb70b CW |
3479 | reg = FDI_RX_IMR(pipe); |
3480 | temp = I915_READ(reg); | |
e1a44743 AJ |
3481 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3482 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3483 | I915_WRITE(reg, temp); |
3484 | I915_READ(reg); | |
e1a44743 AJ |
3485 | udelay(150); |
3486 | ||
8db9d77b | 3487 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3488 | reg = FDI_TX_CTL(pipe); |
3489 | temp = I915_READ(reg); | |
627eb5a3 | 3490 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3491 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3492 | temp &= ~FDI_LINK_TRAIN_NONE; |
3493 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3494 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3495 | |
5eddb70b CW |
3496 | reg = FDI_RX_CTL(pipe); |
3497 | temp = I915_READ(reg); | |
8db9d77b ZW |
3498 | temp &= ~FDI_LINK_TRAIN_NONE; |
3499 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3500 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3501 | ||
3502 | POSTING_READ(reg); | |
8db9d77b ZW |
3503 | udelay(150); |
3504 | ||
5b2adf89 | 3505 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3506 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3507 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3508 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3509 | |
5eddb70b | 3510 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3511 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3512 | temp = I915_READ(reg); |
8db9d77b ZW |
3513 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3514 | ||
3515 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3516 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3517 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3518 | break; |
3519 | } | |
8db9d77b | 3520 | } |
e1a44743 | 3521 | if (tries == 5) |
5eddb70b | 3522 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3523 | |
3524 | /* Train 2 */ | |
5eddb70b CW |
3525 | reg = FDI_TX_CTL(pipe); |
3526 | temp = I915_READ(reg); | |
8db9d77b ZW |
3527 | temp &= ~FDI_LINK_TRAIN_NONE; |
3528 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3529 | I915_WRITE(reg, temp); |
8db9d77b | 3530 | |
5eddb70b CW |
3531 | reg = FDI_RX_CTL(pipe); |
3532 | temp = I915_READ(reg); | |
8db9d77b ZW |
3533 | temp &= ~FDI_LINK_TRAIN_NONE; |
3534 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3535 | I915_WRITE(reg, temp); |
8db9d77b | 3536 | |
5eddb70b CW |
3537 | POSTING_READ(reg); |
3538 | udelay(150); | |
8db9d77b | 3539 | |
5eddb70b | 3540 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3541 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3542 | temp = I915_READ(reg); |
8db9d77b ZW |
3543 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3544 | ||
3545 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3546 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3547 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3548 | break; | |
3549 | } | |
8db9d77b | 3550 | } |
e1a44743 | 3551 | if (tries == 5) |
5eddb70b | 3552 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3553 | |
3554 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3555 | |
8db9d77b ZW |
3556 | } |
3557 | ||
0206e353 | 3558 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3559 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3560 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3561 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3562 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3563 | }; | |
3564 | ||
3565 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3566 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3567 | { | |
3568 | struct drm_device *dev = crtc->dev; | |
3569 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3571 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3572 | i915_reg_t reg; |
3573 | u32 temp, i, retry; | |
8db9d77b | 3574 | |
e1a44743 AJ |
3575 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3576 | for train result */ | |
5eddb70b CW |
3577 | reg = FDI_RX_IMR(pipe); |
3578 | temp = I915_READ(reg); | |
e1a44743 AJ |
3579 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3580 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3581 | I915_WRITE(reg, temp); |
3582 | ||
3583 | POSTING_READ(reg); | |
e1a44743 AJ |
3584 | udelay(150); |
3585 | ||
8db9d77b | 3586 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3587 | reg = FDI_TX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
627eb5a3 | 3589 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3590 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3591 | temp &= ~FDI_LINK_TRAIN_NONE; |
3592 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3593 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3594 | /* SNB-B */ | |
3595 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3596 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3597 | |
d74cf324 DV |
3598 | I915_WRITE(FDI_RX_MISC(pipe), |
3599 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3600 | ||
5eddb70b CW |
3601 | reg = FDI_RX_CTL(pipe); |
3602 | temp = I915_READ(reg); | |
8db9d77b ZW |
3603 | if (HAS_PCH_CPT(dev)) { |
3604 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3605 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3606 | } else { | |
3607 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3608 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3609 | } | |
5eddb70b CW |
3610 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3611 | ||
3612 | POSTING_READ(reg); | |
8db9d77b ZW |
3613 | udelay(150); |
3614 | ||
0206e353 | 3615 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3616 | reg = FDI_TX_CTL(pipe); |
3617 | temp = I915_READ(reg); | |
8db9d77b ZW |
3618 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3619 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3620 | I915_WRITE(reg, temp); |
3621 | ||
3622 | POSTING_READ(reg); | |
8db9d77b ZW |
3623 | udelay(500); |
3624 | ||
fa37d39e SP |
3625 | for (retry = 0; retry < 5; retry++) { |
3626 | reg = FDI_RX_IIR(pipe); | |
3627 | temp = I915_READ(reg); | |
3628 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3629 | if (temp & FDI_RX_BIT_LOCK) { | |
3630 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3631 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3632 | break; | |
3633 | } | |
3634 | udelay(50); | |
8db9d77b | 3635 | } |
fa37d39e SP |
3636 | if (retry < 5) |
3637 | break; | |
8db9d77b ZW |
3638 | } |
3639 | if (i == 4) | |
5eddb70b | 3640 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3641 | |
3642 | /* Train 2 */ | |
5eddb70b CW |
3643 | reg = FDI_TX_CTL(pipe); |
3644 | temp = I915_READ(reg); | |
8db9d77b ZW |
3645 | temp &= ~FDI_LINK_TRAIN_NONE; |
3646 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3647 | if (IS_GEN6(dev)) { | |
3648 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3649 | /* SNB-B */ | |
3650 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3651 | } | |
5eddb70b | 3652 | I915_WRITE(reg, temp); |
8db9d77b | 3653 | |
5eddb70b CW |
3654 | reg = FDI_RX_CTL(pipe); |
3655 | temp = I915_READ(reg); | |
8db9d77b ZW |
3656 | if (HAS_PCH_CPT(dev)) { |
3657 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3658 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3659 | } else { | |
3660 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3661 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3662 | } | |
5eddb70b CW |
3663 | I915_WRITE(reg, temp); |
3664 | ||
3665 | POSTING_READ(reg); | |
8db9d77b ZW |
3666 | udelay(150); |
3667 | ||
0206e353 | 3668 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3669 | reg = FDI_TX_CTL(pipe); |
3670 | temp = I915_READ(reg); | |
8db9d77b ZW |
3671 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3672 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3673 | I915_WRITE(reg, temp); |
3674 | ||
3675 | POSTING_READ(reg); | |
8db9d77b ZW |
3676 | udelay(500); |
3677 | ||
fa37d39e SP |
3678 | for (retry = 0; retry < 5; retry++) { |
3679 | reg = FDI_RX_IIR(pipe); | |
3680 | temp = I915_READ(reg); | |
3681 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3682 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3683 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3684 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3685 | break; | |
3686 | } | |
3687 | udelay(50); | |
8db9d77b | 3688 | } |
fa37d39e SP |
3689 | if (retry < 5) |
3690 | break; | |
8db9d77b ZW |
3691 | } |
3692 | if (i == 4) | |
5eddb70b | 3693 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3694 | |
3695 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3696 | } | |
3697 | ||
357555c0 JB |
3698 | /* Manual link training for Ivy Bridge A0 parts */ |
3699 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3700 | { | |
3701 | struct drm_device *dev = crtc->dev; | |
3702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3704 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3705 | i915_reg_t reg; |
3706 | u32 temp, i, j; | |
357555c0 JB |
3707 | |
3708 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3709 | for train result */ | |
3710 | reg = FDI_RX_IMR(pipe); | |
3711 | temp = I915_READ(reg); | |
3712 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3713 | temp &= ~FDI_RX_BIT_LOCK; | |
3714 | I915_WRITE(reg, temp); | |
3715 | ||
3716 | POSTING_READ(reg); | |
3717 | udelay(150); | |
3718 | ||
01a415fd DV |
3719 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3720 | I915_READ(FDI_RX_IIR(pipe))); | |
3721 | ||
139ccd3f JB |
3722 | /* Try each vswing and preemphasis setting twice before moving on */ |
3723 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3724 | /* disable first in case we need to retry */ | |
3725 | reg = FDI_TX_CTL(pipe); | |
3726 | temp = I915_READ(reg); | |
3727 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3728 | temp &= ~FDI_TX_ENABLE; | |
3729 | I915_WRITE(reg, temp); | |
357555c0 | 3730 | |
139ccd3f JB |
3731 | reg = FDI_RX_CTL(pipe); |
3732 | temp = I915_READ(reg); | |
3733 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3734 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3735 | temp &= ~FDI_RX_ENABLE; | |
3736 | I915_WRITE(reg, temp); | |
357555c0 | 3737 | |
139ccd3f | 3738 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3739 | reg = FDI_TX_CTL(pipe); |
3740 | temp = I915_READ(reg); | |
139ccd3f | 3741 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3742 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3743 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3744 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3745 | temp |= snb_b_fdi_train_param[j/2]; |
3746 | temp |= FDI_COMPOSITE_SYNC; | |
3747 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3748 | |
139ccd3f JB |
3749 | I915_WRITE(FDI_RX_MISC(pipe), |
3750 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3751 | |
139ccd3f | 3752 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3753 | temp = I915_READ(reg); |
139ccd3f JB |
3754 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3755 | temp |= FDI_COMPOSITE_SYNC; | |
3756 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3757 | |
139ccd3f JB |
3758 | POSTING_READ(reg); |
3759 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3760 | |
139ccd3f JB |
3761 | for (i = 0; i < 4; i++) { |
3762 | reg = FDI_RX_IIR(pipe); | |
3763 | temp = I915_READ(reg); | |
3764 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3765 | |
139ccd3f JB |
3766 | if (temp & FDI_RX_BIT_LOCK || |
3767 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3768 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3769 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3770 | i); | |
3771 | break; | |
3772 | } | |
3773 | udelay(1); /* should be 0.5us */ | |
3774 | } | |
3775 | if (i == 4) { | |
3776 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3777 | continue; | |
3778 | } | |
357555c0 | 3779 | |
139ccd3f | 3780 | /* Train 2 */ |
357555c0 JB |
3781 | reg = FDI_TX_CTL(pipe); |
3782 | temp = I915_READ(reg); | |
139ccd3f JB |
3783 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3784 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3785 | I915_WRITE(reg, temp); | |
3786 | ||
3787 | reg = FDI_RX_CTL(pipe); | |
3788 | temp = I915_READ(reg); | |
3789 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3790 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3791 | I915_WRITE(reg, temp); |
3792 | ||
3793 | POSTING_READ(reg); | |
139ccd3f | 3794 | udelay(2); /* should be 1.5us */ |
357555c0 | 3795 | |
139ccd3f JB |
3796 | for (i = 0; i < 4; i++) { |
3797 | reg = FDI_RX_IIR(pipe); | |
3798 | temp = I915_READ(reg); | |
3799 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3800 | |
139ccd3f JB |
3801 | if (temp & FDI_RX_SYMBOL_LOCK || |
3802 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3803 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3804 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3805 | i); | |
3806 | goto train_done; | |
3807 | } | |
3808 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3809 | } |
139ccd3f JB |
3810 | if (i == 4) |
3811 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3812 | } |
357555c0 | 3813 | |
139ccd3f | 3814 | train_done: |
357555c0 JB |
3815 | DRM_DEBUG_KMS("FDI train done.\n"); |
3816 | } | |
3817 | ||
88cefb6c | 3818 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3819 | { |
88cefb6c | 3820 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3821 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3822 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3823 | i915_reg_t reg; |
3824 | u32 temp; | |
c64e311e | 3825 | |
c98e9dcf | 3826 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3827 | reg = FDI_RX_CTL(pipe); |
3828 | temp = I915_READ(reg); | |
627eb5a3 | 3829 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3830 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3831 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3832 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3833 | ||
3834 | POSTING_READ(reg); | |
c98e9dcf JB |
3835 | udelay(200); |
3836 | ||
3837 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3838 | temp = I915_READ(reg); |
3839 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3840 | ||
3841 | POSTING_READ(reg); | |
c98e9dcf JB |
3842 | udelay(200); |
3843 | ||
20749730 PZ |
3844 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3845 | reg = FDI_TX_CTL(pipe); | |
3846 | temp = I915_READ(reg); | |
3847 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3848 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3849 | |
20749730 PZ |
3850 | POSTING_READ(reg); |
3851 | udelay(100); | |
6be4a607 | 3852 | } |
0e23b99d JB |
3853 | } |
3854 | ||
88cefb6c DV |
3855 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3856 | { | |
3857 | struct drm_device *dev = intel_crtc->base.dev; | |
3858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3859 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3860 | i915_reg_t reg; |
3861 | u32 temp; | |
88cefb6c DV |
3862 | |
3863 | /* Switch from PCDclk to Rawclk */ | |
3864 | reg = FDI_RX_CTL(pipe); | |
3865 | temp = I915_READ(reg); | |
3866 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3867 | ||
3868 | /* Disable CPU FDI TX PLL */ | |
3869 | reg = FDI_TX_CTL(pipe); | |
3870 | temp = I915_READ(reg); | |
3871 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3872 | ||
3873 | POSTING_READ(reg); | |
3874 | udelay(100); | |
3875 | ||
3876 | reg = FDI_RX_CTL(pipe); | |
3877 | temp = I915_READ(reg); | |
3878 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3879 | ||
3880 | /* Wait for the clocks to turn off. */ | |
3881 | POSTING_READ(reg); | |
3882 | udelay(100); | |
3883 | } | |
3884 | ||
0fc932b8 JB |
3885 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3886 | { | |
3887 | struct drm_device *dev = crtc->dev; | |
3888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3890 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3891 | i915_reg_t reg; |
3892 | u32 temp; | |
0fc932b8 JB |
3893 | |
3894 | /* disable CPU FDI tx and PCH FDI rx */ | |
3895 | reg = FDI_TX_CTL(pipe); | |
3896 | temp = I915_READ(reg); | |
3897 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3898 | POSTING_READ(reg); | |
3899 | ||
3900 | reg = FDI_RX_CTL(pipe); | |
3901 | temp = I915_READ(reg); | |
3902 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3903 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3904 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3905 | ||
3906 | POSTING_READ(reg); | |
3907 | udelay(100); | |
3908 | ||
3909 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3910 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3911 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3912 | |
3913 | /* still set train pattern 1 */ | |
3914 | reg = FDI_TX_CTL(pipe); | |
3915 | temp = I915_READ(reg); | |
3916 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3917 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3918 | I915_WRITE(reg, temp); | |
3919 | ||
3920 | reg = FDI_RX_CTL(pipe); | |
3921 | temp = I915_READ(reg); | |
3922 | if (HAS_PCH_CPT(dev)) { | |
3923 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3924 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3925 | } else { | |
3926 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3927 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3928 | } | |
3929 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3930 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3931 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3932 | I915_WRITE(reg, temp); |
3933 | ||
3934 | POSTING_READ(reg); | |
3935 | udelay(100); | |
3936 | } | |
3937 | ||
5dce5b93 CW |
3938 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3939 | { | |
3940 | struct intel_crtc *crtc; | |
3941 | ||
3942 | /* Note that we don't need to be called with mode_config.lock here | |
3943 | * as our list of CRTC objects is static for the lifetime of the | |
3944 | * device and so cannot disappear as we iterate. Similarly, we can | |
3945 | * happily treat the predicates as racy, atomic checks as userspace | |
3946 | * cannot claim and pin a new fb without at least acquring the | |
3947 | * struct_mutex and so serialising with us. | |
3948 | */ | |
d3fcc808 | 3949 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3950 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3951 | continue; | |
3952 | ||
3953 | if (crtc->unpin_work) | |
3954 | intel_wait_for_vblank(dev, crtc->pipe); | |
3955 | ||
3956 | return true; | |
3957 | } | |
3958 | ||
3959 | return false; | |
3960 | } | |
3961 | ||
d6bbafa1 CW |
3962 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3963 | { | |
3964 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3965 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3966 | ||
3967 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3968 | smp_rmb(); | |
3969 | intel_crtc->unpin_work = NULL; | |
3970 | ||
3971 | if (work->event) | |
3972 | drm_send_vblank_event(intel_crtc->base.dev, | |
3973 | intel_crtc->pipe, | |
3974 | work->event); | |
3975 | ||
3976 | drm_crtc_vblank_put(&intel_crtc->base); | |
3977 | ||
3978 | wake_up_all(&dev_priv->pending_flip_queue); | |
3979 | queue_work(dev_priv->wq, &work->work); | |
3980 | ||
3981 | trace_i915_flip_complete(intel_crtc->plane, | |
3982 | work->pending_flip_obj); | |
3983 | } | |
3984 | ||
5008e874 | 3985 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3986 | { |
0f91128d | 3987 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3988 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3989 | long ret; |
e6c3a2a6 | 3990 | |
2c10d571 | 3991 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3992 | |
3993 | ret = wait_event_interruptible_timeout( | |
3994 | dev_priv->pending_flip_queue, | |
3995 | !intel_crtc_has_pending_flip(crtc), | |
3996 | 60*HZ); | |
3997 | ||
3998 | if (ret < 0) | |
3999 | return ret; | |
4000 | ||
4001 | if (ret == 0) { | |
9c787942 | 4002 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 4003 | |
5e2d7afc | 4004 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
4005 | if (intel_crtc->unpin_work) { |
4006 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4007 | page_flip_completed(intel_crtc); | |
4008 | } | |
5e2d7afc | 4009 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 4010 | } |
5bb61643 | 4011 | |
5008e874 | 4012 | return 0; |
e6c3a2a6 CW |
4013 | } |
4014 | ||
060f02d8 VS |
4015 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
4016 | { | |
4017 | u32 temp; | |
4018 | ||
4019 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4020 | ||
4021 | mutex_lock(&dev_priv->sb_lock); | |
4022 | ||
4023 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4024 | temp |= SBI_SSCCTL_DISABLE; | |
4025 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4026 | ||
4027 | mutex_unlock(&dev_priv->sb_lock); | |
4028 | } | |
4029 | ||
e615efe4 ED |
4030 | /* Program iCLKIP clock to the desired frequency */ |
4031 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4032 | { | |
64b46a06 | 4033 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4034 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4035 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4036 | u32 temp; | |
4037 | ||
060f02d8 | 4038 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4039 | |
64b46a06 VS |
4040 | /* The iCLK virtual clock root frequency is in MHz, |
4041 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4042 | * divisors, it is necessary to divide one by another, so we | |
4043 | * convert the virtual clock precision to KHz here for higher | |
4044 | * precision. | |
4045 | */ | |
4046 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4047 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4048 | u32 iclk_pi_range = 64; | |
64b46a06 | 4049 | u32 desired_divisor; |
e615efe4 | 4050 | |
64b46a06 VS |
4051 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4052 | clock << auxdiv); | |
4053 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4054 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4055 | |
64b46a06 VS |
4056 | /* |
4057 | * Near 20MHz is a corner case which is | |
4058 | * out of range for the 7-bit divisor | |
4059 | */ | |
4060 | if (divsel <= 0x7f) | |
4061 | break; | |
e615efe4 ED |
4062 | } |
4063 | ||
4064 | /* This should not happen with any sane values */ | |
4065 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4066 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4067 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4068 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4069 | ||
4070 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4071 | clock, |
e615efe4 ED |
4072 | auxdiv, |
4073 | divsel, | |
4074 | phasedir, | |
4075 | phaseinc); | |
4076 | ||
060f02d8 VS |
4077 | mutex_lock(&dev_priv->sb_lock); |
4078 | ||
e615efe4 | 4079 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4080 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4081 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4082 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4083 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4084 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4085 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4086 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4087 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4088 | |
4089 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4090 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4091 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4092 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4093 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4094 | |
4095 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4096 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4097 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4098 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4099 | |
060f02d8 VS |
4100 | mutex_unlock(&dev_priv->sb_lock); |
4101 | ||
e615efe4 ED |
4102 | /* Wait for initialization time */ |
4103 | udelay(24); | |
4104 | ||
4105 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4106 | } | |
4107 | ||
8802e5b6 VS |
4108 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4109 | { | |
4110 | u32 divsel, phaseinc, auxdiv; | |
4111 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4112 | u32 iclk_pi_range = 64; | |
4113 | u32 desired_divisor; | |
4114 | u32 temp; | |
4115 | ||
4116 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4117 | return 0; | |
4118 | ||
4119 | mutex_lock(&dev_priv->sb_lock); | |
4120 | ||
4121 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4122 | if (temp & SBI_SSCCTL_DISABLE) { | |
4123 | mutex_unlock(&dev_priv->sb_lock); | |
4124 | return 0; | |
4125 | } | |
4126 | ||
4127 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4128 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4129 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4130 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4131 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4132 | ||
4133 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4134 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4135 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4136 | ||
4137 | mutex_unlock(&dev_priv->sb_lock); | |
4138 | ||
4139 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4140 | ||
4141 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4142 | desired_divisor << auxdiv); | |
4143 | } | |
4144 | ||
275f01b2 DV |
4145 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4146 | enum pipe pch_transcoder) | |
4147 | { | |
4148 | struct drm_device *dev = crtc->base.dev; | |
4149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4150 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4151 | |
4152 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4153 | I915_READ(HTOTAL(cpu_transcoder))); | |
4154 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4155 | I915_READ(HBLANK(cpu_transcoder))); | |
4156 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4157 | I915_READ(HSYNC(cpu_transcoder))); | |
4158 | ||
4159 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4160 | I915_READ(VTOTAL(cpu_transcoder))); | |
4161 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4162 | I915_READ(VBLANK(cpu_transcoder))); | |
4163 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4164 | I915_READ(VSYNC(cpu_transcoder))); | |
4165 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4166 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4167 | } | |
4168 | ||
003632d9 | 4169 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4170 | { |
4171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4172 | uint32_t temp; | |
4173 | ||
4174 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4175 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4176 | return; |
4177 | ||
4178 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4179 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4180 | ||
003632d9 ACO |
4181 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4182 | if (enable) | |
4183 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4184 | ||
4185 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4186 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4187 | POSTING_READ(SOUTH_CHICKEN1); | |
4188 | } | |
4189 | ||
4190 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4191 | { | |
4192 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4193 | |
4194 | switch (intel_crtc->pipe) { | |
4195 | case PIPE_A: | |
4196 | break; | |
4197 | case PIPE_B: | |
6e3c9717 | 4198 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4199 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4200 | else |
003632d9 | 4201 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4202 | |
4203 | break; | |
4204 | case PIPE_C: | |
003632d9 | 4205 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4206 | |
4207 | break; | |
4208 | default: | |
4209 | BUG(); | |
4210 | } | |
4211 | } | |
4212 | ||
c48b5305 VS |
4213 | /* Return which DP Port should be selected for Transcoder DP control */ |
4214 | static enum port | |
4215 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4216 | { | |
4217 | struct drm_device *dev = crtc->dev; | |
4218 | struct intel_encoder *encoder; | |
4219 | ||
4220 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4221 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4222 | encoder->type == INTEL_OUTPUT_EDP) | |
4223 | return enc_to_dig_port(&encoder->base)->port; | |
4224 | } | |
4225 | ||
4226 | return -1; | |
4227 | } | |
4228 | ||
f67a559d JB |
4229 | /* |
4230 | * Enable PCH resources required for PCH ports: | |
4231 | * - PCH PLLs | |
4232 | * - FDI training & RX/TX | |
4233 | * - update transcoder timings | |
4234 | * - DP transcoding bits | |
4235 | * - transcoder | |
4236 | */ | |
4237 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4238 | { |
4239 | struct drm_device *dev = crtc->dev; | |
4240 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4242 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4243 | u32 temp; |
2c07245f | 4244 | |
ab9412ba | 4245 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4246 | |
1fbc0d78 DV |
4247 | if (IS_IVYBRIDGE(dev)) |
4248 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4249 | ||
cd986abb DV |
4250 | /* Write the TU size bits before fdi link training, so that error |
4251 | * detection works. */ | |
4252 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4253 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4254 | ||
3860b2ec VS |
4255 | /* |
4256 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4257 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4258 | */ | |
4259 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4260 | ||
c98e9dcf | 4261 | /* For PCH output, training FDI link */ |
674cf967 | 4262 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4263 | |
3ad8a208 DV |
4264 | /* We need to program the right clock selection before writing the pixel |
4265 | * mutliplier into the DPLL. */ | |
303b81e0 | 4266 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4267 | u32 sel; |
4b645f14 | 4268 | |
c98e9dcf | 4269 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4270 | temp |= TRANS_DPLL_ENABLE(pipe); |
4271 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4272 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4273 | temp |= sel; |
4274 | else | |
4275 | temp &= ~sel; | |
c98e9dcf | 4276 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4277 | } |
5eddb70b | 4278 | |
3ad8a208 DV |
4279 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4280 | * transcoder, and we actually should do this to not upset any PCH | |
4281 | * transcoder that already use the clock when we share it. | |
4282 | * | |
4283 | * Note that enable_shared_dpll tries to do the right thing, but | |
4284 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4285 | * the right LVDS enable sequence. */ | |
85b3894f | 4286 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4287 | |
d9b6cb56 JB |
4288 | /* set transcoder timing, panel must allow it */ |
4289 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4290 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4291 | |
303b81e0 | 4292 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4293 | |
3860b2ec VS |
4294 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4295 | ||
c98e9dcf | 4296 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4297 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4298 | const struct drm_display_mode *adjusted_mode = |
4299 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4300 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4301 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4302 | temp = I915_READ(reg); |
4303 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4304 | TRANS_DP_SYNC_MASK | |
4305 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4306 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4307 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4308 | |
9c4edaee | 4309 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4310 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4311 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4312 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4313 | |
4314 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4315 | case PORT_B: |
5eddb70b | 4316 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4317 | break; |
c48b5305 | 4318 | case PORT_C: |
5eddb70b | 4319 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4320 | break; |
c48b5305 | 4321 | case PORT_D: |
5eddb70b | 4322 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4323 | break; |
4324 | default: | |
e95d41e1 | 4325 | BUG(); |
32f9d658 | 4326 | } |
2c07245f | 4327 | |
5eddb70b | 4328 | I915_WRITE(reg, temp); |
6be4a607 | 4329 | } |
b52eb4dc | 4330 | |
b8a4f404 | 4331 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4332 | } |
4333 | ||
1507e5bd PZ |
4334 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4335 | { | |
4336 | struct drm_device *dev = crtc->dev; | |
4337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4338 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4339 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4340 | |
ab9412ba | 4341 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4342 | |
8c52b5e8 | 4343 | lpt_program_iclkip(crtc); |
1507e5bd | 4344 | |
0540e488 | 4345 | /* Set transcoder timing. */ |
275f01b2 | 4346 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4347 | |
937bb610 | 4348 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4349 | } |
4350 | ||
190f68c5 ACO |
4351 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4352 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4353 | { |
e2b78267 | 4354 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4355 | struct intel_shared_dpll *pll; |
de419ab6 | 4356 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4357 | enum intel_dpll_id i; |
00490c22 | 4358 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4359 | |
de419ab6 ML |
4360 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4361 | ||
98b6bd99 DV |
4362 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4363 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4364 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4365 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4366 | |
46edb027 DV |
4367 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4368 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4369 | |
de419ab6 | 4370 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4371 | |
98b6bd99 DV |
4372 | goto found; |
4373 | } | |
4374 | ||
bcddf610 S |
4375 | if (IS_BROXTON(dev_priv->dev)) { |
4376 | /* PLL is attached to port in bxt */ | |
4377 | struct intel_encoder *encoder; | |
4378 | struct intel_digital_port *intel_dig_port; | |
4379 | ||
4380 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4381 | if (WARN_ON(!encoder)) | |
4382 | return NULL; | |
4383 | ||
4384 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4385 | /* 1:1 mapping between ports and PLLs */ | |
4386 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4387 | pll = &dev_priv->shared_dplls[i]; | |
4388 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4389 | crtc->base.base.id, pll->name); | |
de419ab6 | 4390 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4391 | |
4392 | goto found; | |
00490c22 ML |
4393 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4394 | /* Do not consider SPLL */ | |
4395 | max = 2; | |
bcddf610 | 4396 | |
00490c22 | 4397 | for (i = 0; i < max; i++) { |
e72f9fbf | 4398 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4399 | |
4400 | /* Only want to check enabled timings first */ | |
de419ab6 | 4401 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4402 | continue; |
4403 | ||
190f68c5 | 4404 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4405 | &shared_dpll[i].hw_state, |
4406 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4407 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4408 | crtc->base.base.id, pll->name, |
de419ab6 | 4409 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4410 | pll->active); |
ee7b9f93 JB |
4411 | goto found; |
4412 | } | |
4413 | } | |
4414 | ||
4415 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4416 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4417 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4418 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4419 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4420 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4421 | goto found; |
4422 | } | |
4423 | } | |
4424 | ||
4425 | return NULL; | |
4426 | ||
4427 | found: | |
de419ab6 ML |
4428 | if (shared_dpll[i].crtc_mask == 0) |
4429 | shared_dpll[i].hw_state = | |
4430 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4431 | |
190f68c5 | 4432 | crtc_state->shared_dpll = i; |
46edb027 DV |
4433 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4434 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4435 | |
de419ab6 | 4436 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4437 | |
ee7b9f93 JB |
4438 | return pll; |
4439 | } | |
4440 | ||
de419ab6 | 4441 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4442 | { |
de419ab6 ML |
4443 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4444 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4445 | struct intel_shared_dpll *pll; |
4446 | enum intel_dpll_id i; | |
4447 | ||
de419ab6 ML |
4448 | if (!to_intel_atomic_state(state)->dpll_set) |
4449 | return; | |
8bd31e67 | 4450 | |
de419ab6 | 4451 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4452 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4453 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4454 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4455 | } |
4456 | } | |
4457 | ||
a1520318 | 4458 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4459 | { |
4460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4461 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4462 | u32 temp; |
4463 | ||
4464 | temp = I915_READ(dslreg); | |
4465 | udelay(500); | |
4466 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4467 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4468 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4469 | } |
4470 | } | |
4471 | ||
86adf9d7 ML |
4472 | static int |
4473 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4474 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4475 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4476 | { |
86adf9d7 ML |
4477 | struct intel_crtc_scaler_state *scaler_state = |
4478 | &crtc_state->scaler_state; | |
4479 | struct intel_crtc *intel_crtc = | |
4480 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4481 | int need_scaling; |
6156a456 CK |
4482 | |
4483 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4484 | (src_h != dst_w || src_w != dst_h): | |
4485 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4486 | |
4487 | /* | |
4488 | * if plane is being disabled or scaler is no more required or force detach | |
4489 | * - free scaler binded to this plane/crtc | |
4490 | * - in order to do this, update crtc->scaler_usage | |
4491 | * | |
4492 | * Here scaler state in crtc_state is set free so that | |
4493 | * scaler can be assigned to other user. Actual register | |
4494 | * update to free the scaler is done in plane/panel-fit programming. | |
4495 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4496 | */ | |
86adf9d7 | 4497 | if (force_detach || !need_scaling) { |
a1b2278e | 4498 | if (*scaler_id >= 0) { |
86adf9d7 | 4499 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4500 | scaler_state->scalers[*scaler_id].in_use = 0; |
4501 | ||
86adf9d7 ML |
4502 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4503 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4504 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4505 | scaler_state->scaler_users); |
4506 | *scaler_id = -1; | |
4507 | } | |
4508 | return 0; | |
4509 | } | |
4510 | ||
4511 | /* range checks */ | |
4512 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4513 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4514 | ||
4515 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4516 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4517 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4518 | "size is out of scaler range\n", |
86adf9d7 | 4519 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4520 | return -EINVAL; |
4521 | } | |
4522 | ||
86adf9d7 ML |
4523 | /* mark this plane as a scaler user in crtc_state */ |
4524 | scaler_state->scaler_users |= (1 << scaler_user); | |
4525 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4526 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4527 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4528 | scaler_state->scaler_users); | |
4529 | ||
4530 | return 0; | |
4531 | } | |
4532 | ||
4533 | /** | |
4534 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4535 | * | |
4536 | * @state: crtc's scaler state | |
86adf9d7 ML |
4537 | * |
4538 | * Return | |
4539 | * 0 - scaler_usage updated successfully | |
4540 | * error - requested scaling cannot be supported or other error condition | |
4541 | */ | |
e435d6e5 | 4542 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4543 | { |
4544 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4545 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4546 | |
4547 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4548 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4549 | ||
e435d6e5 | 4550 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4551 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4552 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4553 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4554 | } |
4555 | ||
4556 | /** | |
4557 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4558 | * | |
4559 | * @state: crtc's scaler state | |
86adf9d7 ML |
4560 | * @plane_state: atomic plane state to update |
4561 | * | |
4562 | * Return | |
4563 | * 0 - scaler_usage updated successfully | |
4564 | * error - requested scaling cannot be supported or other error condition | |
4565 | */ | |
da20eabd ML |
4566 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4567 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4568 | { |
4569 | ||
4570 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4571 | struct intel_plane *intel_plane = |
4572 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4573 | struct drm_framebuffer *fb = plane_state->base.fb; |
4574 | int ret; | |
4575 | ||
4576 | bool force_detach = !fb || !plane_state->visible; | |
4577 | ||
4578 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4579 | intel_plane->base.base.id, intel_crtc->pipe, | |
4580 | drm_plane_index(&intel_plane->base)); | |
4581 | ||
4582 | ret = skl_update_scaler(crtc_state, force_detach, | |
4583 | drm_plane_index(&intel_plane->base), | |
4584 | &plane_state->scaler_id, | |
4585 | plane_state->base.rotation, | |
4586 | drm_rect_width(&plane_state->src) >> 16, | |
4587 | drm_rect_height(&plane_state->src) >> 16, | |
4588 | drm_rect_width(&plane_state->dst), | |
4589 | drm_rect_height(&plane_state->dst)); | |
4590 | ||
4591 | if (ret || plane_state->scaler_id < 0) | |
4592 | return ret; | |
4593 | ||
a1b2278e | 4594 | /* check colorkey */ |
818ed961 | 4595 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4596 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4597 | intel_plane->base.base.id); |
a1b2278e CK |
4598 | return -EINVAL; |
4599 | } | |
4600 | ||
4601 | /* Check src format */ | |
86adf9d7 ML |
4602 | switch (fb->pixel_format) { |
4603 | case DRM_FORMAT_RGB565: | |
4604 | case DRM_FORMAT_XBGR8888: | |
4605 | case DRM_FORMAT_XRGB8888: | |
4606 | case DRM_FORMAT_ABGR8888: | |
4607 | case DRM_FORMAT_ARGB8888: | |
4608 | case DRM_FORMAT_XRGB2101010: | |
4609 | case DRM_FORMAT_XBGR2101010: | |
4610 | case DRM_FORMAT_YUYV: | |
4611 | case DRM_FORMAT_YVYU: | |
4612 | case DRM_FORMAT_UYVY: | |
4613 | case DRM_FORMAT_VYUY: | |
4614 | break; | |
4615 | default: | |
4616 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4617 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4618 | return -EINVAL; | |
a1b2278e CK |
4619 | } |
4620 | ||
a1b2278e CK |
4621 | return 0; |
4622 | } | |
4623 | ||
e435d6e5 ML |
4624 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4625 | { | |
4626 | int i; | |
4627 | ||
4628 | for (i = 0; i < crtc->num_scalers; i++) | |
4629 | skl_detach_scaler(crtc, i); | |
4630 | } | |
4631 | ||
4632 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4633 | { |
4634 | struct drm_device *dev = crtc->base.dev; | |
4635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4636 | int pipe = crtc->pipe; | |
a1b2278e CK |
4637 | struct intel_crtc_scaler_state *scaler_state = |
4638 | &crtc->config->scaler_state; | |
4639 | ||
4640 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4641 | ||
6e3c9717 | 4642 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4643 | int id; |
4644 | ||
4645 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4646 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4647 | return; | |
4648 | } | |
4649 | ||
4650 | id = scaler_state->scaler_id; | |
4651 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4652 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4653 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4654 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4655 | ||
4656 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4657 | } |
4658 | } | |
4659 | ||
b074cec8 JB |
4660 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4661 | { | |
4662 | struct drm_device *dev = crtc->base.dev; | |
4663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4664 | int pipe = crtc->pipe; | |
4665 | ||
6e3c9717 | 4666 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4667 | /* Force use of hard-coded filter coefficients |
4668 | * as some pre-programmed values are broken, | |
4669 | * e.g. x201. | |
4670 | */ | |
4671 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4672 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4673 | PF_PIPE_SEL_IVB(pipe)); | |
4674 | else | |
4675 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4676 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4677 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4678 | } |
4679 | } | |
4680 | ||
20bc8673 | 4681 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4682 | { |
cea165c3 VS |
4683 | struct drm_device *dev = crtc->base.dev; |
4684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4685 | |
6e3c9717 | 4686 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4687 | return; |
4688 | ||
cea165c3 VS |
4689 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4690 | intel_wait_for_vblank(dev, crtc->pipe); | |
4691 | ||
d77e4531 | 4692 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4693 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4694 | mutex_lock(&dev_priv->rps.hw_lock); |
4695 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4696 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4697 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4698 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4699 | * mailbox." Moreover, the mailbox may return a bogus state, |
4700 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4701 | */ |
4702 | } else { | |
4703 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4704 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4705 | * is essentially intel_wait_for_vblank. If we don't have this | |
4706 | * and don't wait for vblanks until the end of crtc_enable, then | |
4707 | * the HW state readout code will complain that the expected | |
4708 | * IPS_CTL value is not the one we read. */ | |
4709 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4710 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4711 | } | |
d77e4531 PZ |
4712 | } |
4713 | ||
20bc8673 | 4714 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4715 | { |
4716 | struct drm_device *dev = crtc->base.dev; | |
4717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4718 | ||
6e3c9717 | 4719 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4720 | return; |
4721 | ||
4722 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4723 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4724 | mutex_lock(&dev_priv->rps.hw_lock); |
4725 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4726 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4727 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4728 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4729 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4730 | } else { |
2a114cc1 | 4731 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4732 | POSTING_READ(IPS_CTL); |
4733 | } | |
d77e4531 PZ |
4734 | |
4735 | /* We need to wait for a vblank before we can disable the plane. */ | |
4736 | intel_wait_for_vblank(dev, crtc->pipe); | |
4737 | } | |
4738 | ||
4739 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4740 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4741 | { | |
4742 | struct drm_device *dev = crtc->dev; | |
4743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4745 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4746 | int i; |
4747 | bool reenable_ips = false; | |
4748 | ||
4749 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4750 | if (!crtc->state->active) |
d77e4531 PZ |
4751 | return; |
4752 | ||
50360403 | 4753 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4754 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4755 | assert_dsi_pll_enabled(dev_priv); |
4756 | else | |
4757 | assert_pll_enabled(dev_priv, pipe); | |
4758 | } | |
4759 | ||
d77e4531 PZ |
4760 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4761 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4762 | */ | |
6e3c9717 | 4763 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4764 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4765 | GAMMA_MODE_MODE_SPLIT)) { | |
4766 | hsw_disable_ips(intel_crtc); | |
4767 | reenable_ips = true; | |
4768 | } | |
4769 | ||
4770 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4771 | i915_reg_t palreg; |
f65a9c5b VS |
4772 | |
4773 | if (HAS_GMCH_DISPLAY(dev)) | |
4774 | palreg = PALETTE(pipe, i); | |
4775 | else | |
4776 | palreg = LGC_PALETTE(pipe, i); | |
4777 | ||
4778 | I915_WRITE(palreg, | |
d77e4531 PZ |
4779 | (intel_crtc->lut_r[i] << 16) | |
4780 | (intel_crtc->lut_g[i] << 8) | | |
4781 | intel_crtc->lut_b[i]); | |
4782 | } | |
4783 | ||
4784 | if (reenable_ips) | |
4785 | hsw_enable_ips(intel_crtc); | |
4786 | } | |
4787 | ||
7cac945f | 4788 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4789 | { |
7cac945f | 4790 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4791 | struct drm_device *dev = intel_crtc->base.dev; |
4792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4793 | ||
4794 | mutex_lock(&dev->struct_mutex); | |
4795 | dev_priv->mm.interruptible = false; | |
4796 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4797 | dev_priv->mm.interruptible = true; | |
4798 | mutex_unlock(&dev->struct_mutex); | |
4799 | } | |
4800 | ||
4801 | /* Let userspace switch the overlay on again. In most cases userspace | |
4802 | * has to recompute where to put it anyway. | |
4803 | */ | |
4804 | } | |
4805 | ||
87d4300a ML |
4806 | /** |
4807 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4808 | * @crtc: the CRTC whose primary plane was just enabled | |
4809 | * | |
4810 | * Performs potentially sleeping operations that must be done after the primary | |
4811 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4812 | * called due to an explicit primary plane update, or due to an implicit | |
4813 | * re-enable that is caused when a sprite plane is updated to no longer | |
4814 | * completely hide the primary plane. | |
4815 | */ | |
4816 | static void | |
4817 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4818 | { |
4819 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4820 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4821 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4822 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4823 | |
87d4300a ML |
4824 | /* |
4825 | * FIXME IPS should be fine as long as one plane is | |
4826 | * enabled, but in practice it seems to have problems | |
4827 | * when going from primary only to sprite only and vice | |
4828 | * versa. | |
4829 | */ | |
a5c4d7bc VS |
4830 | hsw_enable_ips(intel_crtc); |
4831 | ||
f99d7069 | 4832 | /* |
87d4300a ML |
4833 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4834 | * So don't enable underrun reporting before at least some planes | |
4835 | * are enabled. | |
4836 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4837 | * but leave the pipe running. | |
f99d7069 | 4838 | */ |
87d4300a ML |
4839 | if (IS_GEN2(dev)) |
4840 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4841 | ||
aca7b684 VS |
4842 | /* Underruns don't always raise interrupts, so check manually. */ |
4843 | intel_check_cpu_fifo_underruns(dev_priv); | |
4844 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4845 | } |
4846 | ||
87d4300a ML |
4847 | /** |
4848 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4849 | * @crtc: the CRTC whose primary plane is to be disabled | |
4850 | * | |
4851 | * Performs potentially sleeping operations that must be done before the | |
4852 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4853 | * be called due to an explicit primary plane update, or due to an implicit | |
4854 | * disable that is caused when a sprite plane completely hides the primary | |
4855 | * plane. | |
4856 | */ | |
4857 | static void | |
4858 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4859 | { |
4860 | struct drm_device *dev = crtc->dev; | |
4861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4863 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4864 | |
87d4300a ML |
4865 | /* |
4866 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4867 | * So diasble underrun reporting before all the planes get disabled. | |
4868 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4869 | * but leave the pipe running. | |
4870 | */ | |
4871 | if (IS_GEN2(dev)) | |
4872 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4873 | |
87d4300a ML |
4874 | /* |
4875 | * Vblank time updates from the shadow to live plane control register | |
4876 | * are blocked if the memory self-refresh mode is active at that | |
4877 | * moment. So to make sure the plane gets truly disabled, disable | |
4878 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4879 | * will be checked/applied by the HW only at the next frame start | |
4880 | * event which is after the vblank start event, so we need to have a | |
4881 | * wait-for-vblank between disabling the plane and the pipe. | |
4882 | */ | |
262cd2e1 | 4883 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4884 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4885 | dev_priv->wm.vlv.cxsr = false; |
4886 | intel_wait_for_vblank(dev, pipe); | |
4887 | } | |
87d4300a | 4888 | |
87d4300a ML |
4889 | /* |
4890 | * FIXME IPS should be fine as long as one plane is | |
4891 | * enabled, but in practice it seems to have problems | |
4892 | * when going from primary only to sprite only and vice | |
4893 | * versa. | |
4894 | */ | |
a5c4d7bc | 4895 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4896 | } |
4897 | ||
ac21b225 ML |
4898 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4899 | { | |
4900 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4901 | struct intel_crtc_state *pipe_config = |
4902 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4903 | struct drm_device *dev = crtc->base.dev; |
ac21b225 | 4904 | |
ac21b225 ML |
4905 | intel_frontbuffer_flip(dev, atomic->fb_bits); |
4906 | ||
ab1d3a0e | 4907 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4908 | |
b9001114 | 4909 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4910 | intel_update_watermarks(&crtc->base); |
4911 | ||
c80ac854 | 4912 | if (atomic->update_fbc) |
1eb52238 | 4913 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4914 | |
4915 | if (atomic->post_enable_primary) | |
4916 | intel_post_enable_primary(&crtc->base); | |
4917 | ||
ac21b225 ML |
4918 | memset(atomic, 0, sizeof(*atomic)); |
4919 | } | |
4920 | ||
5c74cd73 | 4921 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4922 | { |
5c74cd73 | 4923 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4924 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4925 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4926 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4927 | struct intel_crtc_state *pipe_config = |
4928 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4929 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4930 | struct drm_plane *primary = crtc->base.primary; | |
4931 | struct drm_plane_state *old_pri_state = | |
4932 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4933 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4934 | |
1eb52238 PZ |
4935 | if (atomic->update_fbc) |
4936 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4937 | |
5c74cd73 ML |
4938 | if (old_pri_state) { |
4939 | struct intel_plane_state *primary_state = | |
4940 | to_intel_plane_state(primary->state); | |
4941 | struct intel_plane_state *old_primary_state = | |
4942 | to_intel_plane_state(old_pri_state); | |
4943 | ||
4944 | if (old_primary_state->visible && | |
4945 | (modeset || !primary_state->visible)) | |
4946 | intel_pre_disable_primary(&crtc->base); | |
4947 | } | |
852eb00d | 4948 | |
ab1d3a0e | 4949 | if (pipe_config->disable_cxsr) { |
852eb00d | 4950 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4951 | |
4952 | if (old_crtc_state->base.active) | |
4953 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4954 | } |
92826fcd | 4955 | |
ed4a6a7c MR |
4956 | /* |
4957 | * IVB workaround: must disable low power watermarks for at least | |
4958 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4959 | * when scaling is disabled. | |
4960 | * | |
4961 | * WaCxSRDisabledForSpriteScaling:ivb | |
4962 | */ | |
4963 | if (pipe_config->disable_lp_wm) { | |
4964 | ilk_disable_lp_wm(dev); | |
4965 | intel_wait_for_vblank(dev, crtc->pipe); | |
4966 | } | |
4967 | ||
4968 | /* | |
4969 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4970 | * watermark programming here. | |
4971 | */ | |
4972 | if (needs_modeset(&pipe_config->base)) | |
4973 | return; | |
4974 | ||
4975 | /* | |
4976 | * For platforms that support atomic watermarks, program the | |
4977 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4978 | * will be the intermediate values that are safe for both pre- and | |
4979 | * post- vblank; when vblank happens, the 'active' values will be set | |
4980 | * to the final 'target' values and we'll do this again to get the | |
4981 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4982 | * will be the final target values which will get automatically latched | |
4983 | * at vblank time; no further programming will be necessary. | |
4984 | * | |
4985 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4986 | * we'll continue to update watermarks the old way, if flags tell | |
4987 | * us to. | |
4988 | */ | |
4989 | if (dev_priv->display.initial_watermarks != NULL) | |
4990 | dev_priv->display.initial_watermarks(pipe_config); | |
4991 | else if (pipe_config->wm_changed) | |
92826fcd | 4992 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4993 | } |
4994 | ||
d032ffa0 | 4995 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4996 | { |
4997 | struct drm_device *dev = crtc->dev; | |
4998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4999 | struct drm_plane *p; |
87d4300a ML |
5000 | int pipe = intel_crtc->pipe; |
5001 | ||
7cac945f | 5002 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5003 | |
d032ffa0 ML |
5004 | drm_for_each_plane_mask(p, dev, plane_mask) |
5005 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5006 | |
f99d7069 DV |
5007 | /* |
5008 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5009 | * to compute the mask of flip planes precisely. For the time being | |
5010 | * consider this a flip to a NULL plane. | |
5011 | */ | |
5012 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
5013 | } |
5014 | ||
f67a559d JB |
5015 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
5016 | { | |
5017 | struct drm_device *dev = crtc->dev; | |
5018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5019 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5020 | struct intel_encoder *encoder; |
f67a559d | 5021 | int pipe = intel_crtc->pipe; |
f67a559d | 5022 | |
53d9f4e9 | 5023 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5024 | return; |
5025 | ||
81b088ca VS |
5026 | if (intel_crtc->config->has_pch_encoder) |
5027 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5028 | ||
6e3c9717 | 5029 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5030 | intel_prepare_shared_dpll(intel_crtc); |
5031 | ||
6e3c9717 | 5032 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5033 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5034 | |
5035 | intel_set_pipe_timings(intel_crtc); | |
5036 | ||
6e3c9717 | 5037 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5038 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5039 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5040 | } |
5041 | ||
5042 | ironlake_set_pipeconf(crtc); | |
5043 | ||
f67a559d | 5044 | intel_crtc->active = true; |
8664281b | 5045 | |
a72e4c9f | 5046 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 5047 | |
f6736a1a | 5048 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
5049 | if (encoder->pre_enable) |
5050 | encoder->pre_enable(encoder); | |
f67a559d | 5051 | |
6e3c9717 | 5052 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5053 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5054 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5055 | * enabling. */ | |
88cefb6c | 5056 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5057 | } else { |
5058 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5059 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5060 | } | |
f67a559d | 5061 | |
b074cec8 | 5062 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5063 | |
9c54c0dd JB |
5064 | /* |
5065 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5066 | * clocks enabled | |
5067 | */ | |
5068 | intel_crtc_load_lut(crtc); | |
5069 | ||
1d5bf5d9 ID |
5070 | if (dev_priv->display.initial_watermarks != NULL) |
5071 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5072 | intel_enable_pipe(intel_crtc); |
f67a559d | 5073 | |
6e3c9717 | 5074 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5075 | ironlake_pch_enable(crtc); |
c98e9dcf | 5076 | |
f9b61ff6 DV |
5077 | assert_vblank_disabled(crtc); |
5078 | drm_crtc_vblank_on(crtc); | |
5079 | ||
fa5c73b1 DV |
5080 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5081 | encoder->enable(encoder); | |
61b77ddd DV |
5082 | |
5083 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 5084 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5085 | |
5086 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5087 | if (intel_crtc->config->has_pch_encoder) | |
5088 | intel_wait_for_vblank(dev, pipe); | |
5089 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
5090 | } |
5091 | ||
42db64ef PZ |
5092 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5093 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5094 | { | |
f5adf94e | 5095 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5096 | } |
5097 | ||
4f771f10 PZ |
5098 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5099 | { | |
5100 | struct drm_device *dev = crtc->dev; | |
5101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5103 | struct intel_encoder *encoder; | |
99d736a2 ML |
5104 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
5105 | struct intel_crtc_state *pipe_config = | |
5106 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 5107 | |
53d9f4e9 | 5108 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5109 | return; |
5110 | ||
81b088ca VS |
5111 | if (intel_crtc->config->has_pch_encoder) |
5112 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5113 | false); | |
5114 | ||
df8ad70c DV |
5115 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5116 | intel_enable_shared_dpll(intel_crtc); | |
5117 | ||
6e3c9717 | 5118 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5119 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5120 | |
5121 | intel_set_pipe_timings(intel_crtc); | |
5122 | ||
6e3c9717 ACO |
5123 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5124 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5125 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5126 | } |
5127 | ||
6e3c9717 | 5128 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5129 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5130 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5131 | } |
5132 | ||
5133 | haswell_set_pipeconf(crtc); | |
5134 | ||
5135 | intel_set_pipe_csc(crtc); | |
5136 | ||
4f771f10 | 5137 | intel_crtc->active = true; |
8664281b | 5138 | |
6b698516 DV |
5139 | if (intel_crtc->config->has_pch_encoder) |
5140 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5141 | else | |
5142 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5143 | ||
7d4aefd0 | 5144 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5145 | if (encoder->pre_enable) |
5146 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5147 | } |
4f771f10 | 5148 | |
d2d65408 | 5149 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5150 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5151 | |
a65347ba | 5152 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5153 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5154 | |
1c132b44 | 5155 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5156 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5157 | else |
1c132b44 | 5158 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5159 | |
5160 | /* | |
5161 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5162 | * clocks enabled | |
5163 | */ | |
5164 | intel_crtc_load_lut(crtc); | |
5165 | ||
1f544388 | 5166 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5167 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5168 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5169 | |
1d5bf5d9 ID |
5170 | if (dev_priv->display.initial_watermarks != NULL) |
5171 | dev_priv->display.initial_watermarks(pipe_config); | |
5172 | else | |
5173 | intel_update_watermarks(crtc); | |
e1fdc473 | 5174 | intel_enable_pipe(intel_crtc); |
42db64ef | 5175 | |
6e3c9717 | 5176 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5177 | lpt_pch_enable(crtc); |
4f771f10 | 5178 | |
a65347ba | 5179 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5180 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5181 | ||
f9b61ff6 DV |
5182 | assert_vblank_disabled(crtc); |
5183 | drm_crtc_vblank_on(crtc); | |
5184 | ||
8807e55b | 5185 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5186 | encoder->enable(encoder); |
8807e55b JN |
5187 | intel_opregion_notify_encoder(encoder, true); |
5188 | } | |
4f771f10 | 5189 | |
6b698516 DV |
5190 | if (intel_crtc->config->has_pch_encoder) { |
5191 | intel_wait_for_vblank(dev, pipe); | |
5192 | intel_wait_for_vblank(dev, pipe); | |
5193 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5194 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5195 | true); | |
6b698516 | 5196 | } |
d2d65408 | 5197 | |
e4916946 PZ |
5198 | /* If we change the relative order between pipe/planes enabling, we need |
5199 | * to change the workaround. */ | |
99d736a2 ML |
5200 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5201 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5202 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5203 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5204 | } | |
4f771f10 PZ |
5205 | } |
5206 | ||
bfd16b2a | 5207 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5208 | { |
5209 | struct drm_device *dev = crtc->base.dev; | |
5210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5211 | int pipe = crtc->pipe; | |
5212 | ||
5213 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5214 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5215 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5216 | I915_WRITE(PF_CTL(pipe), 0); |
5217 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5218 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5219 | } | |
5220 | } | |
5221 | ||
6be4a607 JB |
5222 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5223 | { | |
5224 | struct drm_device *dev = crtc->dev; | |
5225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5227 | struct intel_encoder *encoder; |
6be4a607 | 5228 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5229 | |
37ca8d4c VS |
5230 | if (intel_crtc->config->has_pch_encoder) |
5231 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5232 | ||
ea9d758d DV |
5233 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5234 | encoder->disable(encoder); | |
5235 | ||
f9b61ff6 DV |
5236 | drm_crtc_vblank_off(crtc); |
5237 | assert_vblank_disabled(crtc); | |
5238 | ||
3860b2ec VS |
5239 | /* |
5240 | * Sometimes spurious CPU pipe underruns happen when the | |
5241 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5242 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5243 | */ | |
5244 | if (intel_crtc->config->has_pch_encoder) | |
5245 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5246 | ||
575f7ab7 | 5247 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5248 | |
bfd16b2a | 5249 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5250 | |
3860b2ec | 5251 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5252 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5253 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5254 | } | |
5a74f70a | 5255 | |
bf49ec8c DV |
5256 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5257 | if (encoder->post_disable) | |
5258 | encoder->post_disable(encoder); | |
2c07245f | 5259 | |
6e3c9717 | 5260 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5261 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5262 | |
d925c59a | 5263 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5264 | i915_reg_t reg; |
5265 | u32 temp; | |
5266 | ||
d925c59a DV |
5267 | /* disable TRANS_DP_CTL */ |
5268 | reg = TRANS_DP_CTL(pipe); | |
5269 | temp = I915_READ(reg); | |
5270 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5271 | TRANS_DP_PORT_SEL_MASK); | |
5272 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5273 | I915_WRITE(reg, temp); | |
5274 | ||
5275 | /* disable DPLL_SEL */ | |
5276 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5277 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5278 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5279 | } |
e3421a18 | 5280 | |
d925c59a DV |
5281 | ironlake_fdi_pll_disable(intel_crtc); |
5282 | } | |
81b088ca VS |
5283 | |
5284 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5285 | } |
1b3c7a47 | 5286 | |
4f771f10 | 5287 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5288 | { |
4f771f10 PZ |
5289 | struct drm_device *dev = crtc->dev; |
5290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5291 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5292 | struct intel_encoder *encoder; |
6e3c9717 | 5293 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5294 | |
d2d65408 VS |
5295 | if (intel_crtc->config->has_pch_encoder) |
5296 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5297 | false); | |
5298 | ||
8807e55b JN |
5299 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5300 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5301 | encoder->disable(encoder); |
8807e55b | 5302 | } |
4f771f10 | 5303 | |
f9b61ff6 DV |
5304 | drm_crtc_vblank_off(crtc); |
5305 | assert_vblank_disabled(crtc); | |
5306 | ||
575f7ab7 | 5307 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5308 | |
6e3c9717 | 5309 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5310 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5311 | ||
a65347ba | 5312 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5313 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5314 | |
1c132b44 | 5315 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5316 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5317 | else |
bfd16b2a | 5318 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5319 | |
a65347ba | 5320 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5321 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5322 | |
97b040aa ID |
5323 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5324 | if (encoder->post_disable) | |
5325 | encoder->post_disable(encoder); | |
81b088ca | 5326 | |
92966a37 VS |
5327 | if (intel_crtc->config->has_pch_encoder) { |
5328 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5329 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5330 | intel_ddi_fdi_disable(crtc); |
5331 | ||
81b088ca VS |
5332 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5333 | true); | |
92966a37 | 5334 | } |
4f771f10 PZ |
5335 | } |
5336 | ||
2dd24552 JB |
5337 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5338 | { | |
5339 | struct drm_device *dev = crtc->base.dev; | |
5340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5341 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5342 | |
681a8504 | 5343 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5344 | return; |
5345 | ||
2dd24552 | 5346 | /* |
c0b03411 DV |
5347 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5348 | * according to register description and PRM. | |
2dd24552 | 5349 | */ |
c0b03411 DV |
5350 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5351 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5352 | |
b074cec8 JB |
5353 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5354 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5355 | |
5356 | /* Border color in case we don't scale up to the full screen. Black by | |
5357 | * default, change to something else for debugging. */ | |
5358 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5359 | } |
5360 | ||
d05410f9 DA |
5361 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5362 | { | |
5363 | switch (port) { | |
5364 | case PORT_A: | |
6331a704 | 5365 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5366 | case PORT_B: |
6331a704 | 5367 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5368 | case PORT_C: |
6331a704 | 5369 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5370 | case PORT_D: |
6331a704 | 5371 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5372 | case PORT_E: |
6331a704 | 5373 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5374 | default: |
b9fec167 | 5375 | MISSING_CASE(port); |
d05410f9 DA |
5376 | return POWER_DOMAIN_PORT_OTHER; |
5377 | } | |
5378 | } | |
5379 | ||
25f78f58 VS |
5380 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5381 | { | |
5382 | switch (port) { | |
5383 | case PORT_A: | |
5384 | return POWER_DOMAIN_AUX_A; | |
5385 | case PORT_B: | |
5386 | return POWER_DOMAIN_AUX_B; | |
5387 | case PORT_C: | |
5388 | return POWER_DOMAIN_AUX_C; | |
5389 | case PORT_D: | |
5390 | return POWER_DOMAIN_AUX_D; | |
5391 | case PORT_E: | |
5392 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5393 | return POWER_DOMAIN_AUX_D; | |
5394 | default: | |
b9fec167 | 5395 | MISSING_CASE(port); |
25f78f58 VS |
5396 | return POWER_DOMAIN_AUX_A; |
5397 | } | |
5398 | } | |
5399 | ||
319be8ae ID |
5400 | enum intel_display_power_domain |
5401 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5402 | { | |
5403 | struct drm_device *dev = intel_encoder->base.dev; | |
5404 | struct intel_digital_port *intel_dig_port; | |
5405 | ||
5406 | switch (intel_encoder->type) { | |
5407 | case INTEL_OUTPUT_UNKNOWN: | |
5408 | /* Only DDI platforms should ever use this output type */ | |
5409 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5410 | case INTEL_OUTPUT_DISPLAYPORT: | |
5411 | case INTEL_OUTPUT_HDMI: | |
5412 | case INTEL_OUTPUT_EDP: | |
5413 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5414 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5415 | case INTEL_OUTPUT_DP_MST: |
5416 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5417 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5418 | case INTEL_OUTPUT_ANALOG: |
5419 | return POWER_DOMAIN_PORT_CRT; | |
5420 | case INTEL_OUTPUT_DSI: | |
5421 | return POWER_DOMAIN_PORT_DSI; | |
5422 | default: | |
5423 | return POWER_DOMAIN_PORT_OTHER; | |
5424 | } | |
5425 | } | |
5426 | ||
25f78f58 VS |
5427 | enum intel_display_power_domain |
5428 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5429 | { | |
5430 | struct drm_device *dev = intel_encoder->base.dev; | |
5431 | struct intel_digital_port *intel_dig_port; | |
5432 | ||
5433 | switch (intel_encoder->type) { | |
5434 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5435 | case INTEL_OUTPUT_HDMI: |
5436 | /* | |
5437 | * Only DDI platforms should ever use these output types. | |
5438 | * We can get here after the HDMI detect code has already set | |
5439 | * the type of the shared encoder. Since we can't be sure | |
5440 | * what's the status of the given connectors, play safe and | |
5441 | * run the DP detection too. | |
5442 | */ | |
25f78f58 VS |
5443 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5444 | case INTEL_OUTPUT_DISPLAYPORT: | |
5445 | case INTEL_OUTPUT_EDP: | |
5446 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5447 | return port_to_aux_power_domain(intel_dig_port->port); | |
5448 | case INTEL_OUTPUT_DP_MST: | |
5449 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5450 | return port_to_aux_power_domain(intel_dig_port->port); | |
5451 | default: | |
b9fec167 | 5452 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5453 | return POWER_DOMAIN_AUX_A; |
5454 | } | |
5455 | } | |
5456 | ||
74bff5f9 ML |
5457 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5458 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5459 | { |
319be8ae | 5460 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5461 | struct drm_encoder *encoder; |
319be8ae ID |
5462 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5463 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5464 | unsigned long mask; |
74bff5f9 | 5465 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5466 | |
74bff5f9 | 5467 | if (!crtc_state->base.active) |
292b990e ML |
5468 | return 0; |
5469 | ||
77d22dca ID |
5470 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5471 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5472 | if (crtc_state->pch_pfit.enabled || |
5473 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5474 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5475 | ||
74bff5f9 ML |
5476 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5477 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5478 | ||
319be8ae | 5479 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5480 | } |
319be8ae | 5481 | |
77d22dca ID |
5482 | return mask; |
5483 | } | |
5484 | ||
74bff5f9 ML |
5485 | static unsigned long |
5486 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5487 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5488 | { |
292b990e ML |
5489 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5490 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5491 | enum intel_display_power_domain domain; | |
5492 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5493 | |
292b990e | 5494 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5495 | intel_crtc->enabled_power_domains = new_domains = |
5496 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5497 | |
292b990e ML |
5498 | domains = new_domains & ~old_domains; |
5499 | ||
5500 | for_each_power_domain(domain, domains) | |
5501 | intel_display_power_get(dev_priv, domain); | |
5502 | ||
5503 | return old_domains & ~new_domains; | |
5504 | } | |
5505 | ||
5506 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5507 | unsigned long domains) | |
5508 | { | |
5509 | enum intel_display_power_domain domain; | |
5510 | ||
5511 | for_each_power_domain(domain, domains) | |
5512 | intel_display_power_put(dev_priv, domain); | |
5513 | } | |
77d22dca | 5514 | |
adafdc6f MK |
5515 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5516 | { | |
5517 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5518 | ||
5519 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5520 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5521 | return max_cdclk_freq; | |
5522 | else if (IS_CHERRYVIEW(dev_priv)) | |
5523 | return max_cdclk_freq*95/100; | |
5524 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5525 | return 2*max_cdclk_freq*90/100; | |
5526 | else | |
5527 | return max_cdclk_freq*90/100; | |
5528 | } | |
5529 | ||
560a7ae4 DL |
5530 | static void intel_update_max_cdclk(struct drm_device *dev) |
5531 | { | |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5533 | ||
ef11bdb3 | 5534 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5535 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5536 | ||
5537 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5538 | dev_priv->max_cdclk_freq = 675000; | |
5539 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5540 | dev_priv->max_cdclk_freq = 540000; | |
5541 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5542 | dev_priv->max_cdclk_freq = 450000; | |
5543 | else | |
5544 | dev_priv->max_cdclk_freq = 337500; | |
5545 | } else if (IS_BROADWELL(dev)) { | |
5546 | /* | |
5547 | * FIXME with extra cooling we can allow | |
5548 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5549 | * How can we know if extra cooling is | |
5550 | * available? PCI ID, VTB, something else? | |
5551 | */ | |
5552 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5553 | dev_priv->max_cdclk_freq = 450000; | |
5554 | else if (IS_BDW_ULX(dev)) | |
5555 | dev_priv->max_cdclk_freq = 450000; | |
5556 | else if (IS_BDW_ULT(dev)) | |
5557 | dev_priv->max_cdclk_freq = 540000; | |
5558 | else | |
5559 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5560 | } else if (IS_CHERRYVIEW(dev)) { |
5561 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5562 | } else if (IS_VALLEYVIEW(dev)) { |
5563 | dev_priv->max_cdclk_freq = 400000; | |
5564 | } else { | |
5565 | /* otherwise assume cdclk is fixed */ | |
5566 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5567 | } | |
5568 | ||
adafdc6f MK |
5569 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5570 | ||
560a7ae4 DL |
5571 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5572 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5573 | |
5574 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5575 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5576 | } |
5577 | ||
5578 | static void intel_update_cdclk(struct drm_device *dev) | |
5579 | { | |
5580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5581 | ||
5582 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5583 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5584 | dev_priv->cdclk_freq); | |
5585 | ||
5586 | /* | |
5587 | * Program the gmbus_freq based on the cdclk frequency. | |
5588 | * BSpec erroneously claims we should aim for 4MHz, but | |
5589 | * in fact 1MHz is the correct frequency. | |
5590 | */ | |
666a4537 | 5591 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5592 | /* |
5593 | * Program the gmbus_freq based on the cdclk frequency. | |
5594 | * BSpec erroneously claims we should aim for 4MHz, but | |
5595 | * in fact 1MHz is the correct frequency. | |
5596 | */ | |
5597 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5598 | } | |
5599 | ||
5600 | if (dev_priv->max_cdclk_freq == 0) | |
5601 | intel_update_max_cdclk(dev); | |
5602 | } | |
5603 | ||
70d0c574 | 5604 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5605 | { |
5606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5607 | uint32_t divider; | |
5608 | uint32_t ratio; | |
5609 | uint32_t current_freq; | |
5610 | int ret; | |
5611 | ||
5612 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5613 | switch (frequency) { | |
5614 | case 144000: | |
5615 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5616 | ratio = BXT_DE_PLL_RATIO(60); | |
5617 | break; | |
5618 | case 288000: | |
5619 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5620 | ratio = BXT_DE_PLL_RATIO(60); | |
5621 | break; | |
5622 | case 384000: | |
5623 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5624 | ratio = BXT_DE_PLL_RATIO(60); | |
5625 | break; | |
5626 | case 576000: | |
5627 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5628 | ratio = BXT_DE_PLL_RATIO(60); | |
5629 | break; | |
5630 | case 624000: | |
5631 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5632 | ratio = BXT_DE_PLL_RATIO(65); | |
5633 | break; | |
5634 | case 19200: | |
5635 | /* | |
5636 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5637 | * to suppress GCC warning. | |
5638 | */ | |
5639 | ratio = 0; | |
5640 | divider = 0; | |
5641 | break; | |
5642 | default: | |
5643 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5644 | ||
5645 | return; | |
5646 | } | |
5647 | ||
5648 | mutex_lock(&dev_priv->rps.hw_lock); | |
5649 | /* Inform power controller of upcoming frequency change */ | |
5650 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5651 | 0x80000000); | |
5652 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5653 | ||
5654 | if (ret) { | |
5655 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5656 | ret, frequency); | |
5657 | return; | |
5658 | } | |
5659 | ||
5660 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5661 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5662 | current_freq = current_freq * 500 + 1000; | |
5663 | ||
5664 | /* | |
5665 | * DE PLL has to be disabled when | |
5666 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5667 | * - before setting to 624MHz (PLL needs toggling) | |
5668 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5669 | */ | |
5670 | if (frequency == 19200 || frequency == 624000 || | |
5671 | current_freq == 624000) { | |
5672 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5673 | /* Timeout 200us */ | |
5674 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5675 | 1)) | |
5676 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5677 | } | |
5678 | ||
5679 | if (frequency != 19200) { | |
5680 | uint32_t val; | |
5681 | ||
5682 | val = I915_READ(BXT_DE_PLL_CTL); | |
5683 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5684 | val |= ratio; | |
5685 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5686 | ||
5687 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5688 | /* Timeout 200us */ | |
5689 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5690 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5691 | ||
5692 | val = I915_READ(CDCLK_CTL); | |
5693 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5694 | val |= divider; | |
5695 | /* | |
5696 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5697 | * enable otherwise. | |
5698 | */ | |
5699 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5700 | if (frequency >= 500000) | |
5701 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5702 | ||
5703 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5704 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5705 | val |= (frequency - 1000) / 500; | |
5706 | I915_WRITE(CDCLK_CTL, val); | |
5707 | } | |
5708 | ||
5709 | mutex_lock(&dev_priv->rps.hw_lock); | |
5710 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5711 | DIV_ROUND_UP(frequency, 25000)); | |
5712 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5713 | ||
5714 | if (ret) { | |
5715 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5716 | ret, frequency); | |
5717 | return; | |
5718 | } | |
5719 | ||
a47871bd | 5720 | intel_update_cdclk(dev); |
f8437dd1 VK |
5721 | } |
5722 | ||
5723 | void broxton_init_cdclk(struct drm_device *dev) | |
5724 | { | |
5725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5726 | uint32_t val; | |
5727 | ||
5728 | /* | |
5729 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5730 | * or else the reset will hang because there is no PCH to respond. | |
5731 | * Move the handshake programming to initialization sequence. | |
5732 | * Previously was left up to BIOS. | |
5733 | */ | |
5734 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5735 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5736 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5737 | ||
5738 | /* Enable PG1 for cdclk */ | |
5739 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5740 | ||
5741 | /* check if cd clock is enabled */ | |
5742 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5743 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5744 | return; | |
5745 | } | |
5746 | ||
5747 | /* | |
5748 | * FIXME: | |
5749 | * - The initial CDCLK needs to be read from VBT. | |
5750 | * Need to make this change after VBT has changes for BXT. | |
5751 | * - check if setting the max (or any) cdclk freq is really necessary | |
5752 | * here, it belongs to modeset time | |
5753 | */ | |
5754 | broxton_set_cdclk(dev, 624000); | |
5755 | ||
5756 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5757 | POSTING_READ(DBUF_CTL); |
5758 | ||
f8437dd1 VK |
5759 | udelay(10); |
5760 | ||
5761 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5762 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5763 | } | |
5764 | ||
5765 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5766 | { | |
5767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5768 | ||
5769 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5770 | POSTING_READ(DBUF_CTL); |
5771 | ||
f8437dd1 VK |
5772 | udelay(10); |
5773 | ||
5774 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5775 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5776 | ||
5777 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5778 | broxton_set_cdclk(dev, 19200); | |
5779 | ||
5780 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5781 | } | |
5782 | ||
5d96d8af DL |
5783 | static const struct skl_cdclk_entry { |
5784 | unsigned int freq; | |
5785 | unsigned int vco; | |
5786 | } skl_cdclk_frequencies[] = { | |
5787 | { .freq = 308570, .vco = 8640 }, | |
5788 | { .freq = 337500, .vco = 8100 }, | |
5789 | { .freq = 432000, .vco = 8640 }, | |
5790 | { .freq = 450000, .vco = 8100 }, | |
5791 | { .freq = 540000, .vco = 8100 }, | |
5792 | { .freq = 617140, .vco = 8640 }, | |
5793 | { .freq = 675000, .vco = 8100 }, | |
5794 | }; | |
5795 | ||
5796 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5797 | { | |
5798 | return (freq - 1000) / 500; | |
5799 | } | |
5800 | ||
5801 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5802 | { | |
5803 | unsigned int i; | |
5804 | ||
5805 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5806 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5807 | ||
5808 | if (e->freq == freq) | |
5809 | return e->vco; | |
5810 | } | |
5811 | ||
5812 | return 8100; | |
5813 | } | |
5814 | ||
5815 | static void | |
5816 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5817 | { | |
5818 | unsigned int min_freq; | |
5819 | u32 val; | |
5820 | ||
5821 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5822 | val = I915_READ(CDCLK_CTL); | |
5823 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5824 | val |= CDCLK_FREQ_337_308; | |
5825 | ||
5826 | if (required_vco == 8640) | |
5827 | min_freq = 308570; | |
5828 | else | |
5829 | min_freq = 337500; | |
5830 | ||
5831 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5832 | ||
5833 | I915_WRITE(CDCLK_CTL, val); | |
5834 | POSTING_READ(CDCLK_CTL); | |
5835 | ||
5836 | /* | |
5837 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5838 | * taking into account the VCO required to operate the eDP panel at the | |
5839 | * desired frequency. The usual DP link rates operate with a VCO of | |
5840 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5841 | * The modeset code is responsible for the selection of the exact link | |
5842 | * rate later on, with the constraint of choosing a frequency that | |
5843 | * works with required_vco. | |
5844 | */ | |
5845 | val = I915_READ(DPLL_CTRL1); | |
5846 | ||
5847 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5848 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5849 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5850 | if (required_vco == 8640) | |
5851 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5852 | SKL_DPLL0); | |
5853 | else | |
5854 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5855 | SKL_DPLL0); | |
5856 | ||
5857 | I915_WRITE(DPLL_CTRL1, val); | |
5858 | POSTING_READ(DPLL_CTRL1); | |
5859 | ||
5860 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5861 | ||
5862 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5863 | DRM_ERROR("DPLL0 not locked\n"); | |
5864 | } | |
5865 | ||
5866 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5867 | { | |
5868 | int ret; | |
5869 | u32 val; | |
5870 | ||
5871 | /* inform PCU we want to change CDCLK */ | |
5872 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5873 | mutex_lock(&dev_priv->rps.hw_lock); | |
5874 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5875 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5876 | ||
5877 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5878 | } | |
5879 | ||
5880 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5881 | { | |
5882 | unsigned int i; | |
5883 | ||
5884 | for (i = 0; i < 15; i++) { | |
5885 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5886 | return true; | |
5887 | udelay(10); | |
5888 | } | |
5889 | ||
5890 | return false; | |
5891 | } | |
5892 | ||
5893 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5894 | { | |
560a7ae4 | 5895 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5896 | u32 freq_select, pcu_ack; |
5897 | ||
5898 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5899 | ||
5900 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5901 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5902 | return; | |
5903 | } | |
5904 | ||
5905 | /* set CDCLK_CTL */ | |
5906 | switch(freq) { | |
5907 | case 450000: | |
5908 | case 432000: | |
5909 | freq_select = CDCLK_FREQ_450_432; | |
5910 | pcu_ack = 1; | |
5911 | break; | |
5912 | case 540000: | |
5913 | freq_select = CDCLK_FREQ_540; | |
5914 | pcu_ack = 2; | |
5915 | break; | |
5916 | case 308570: | |
5917 | case 337500: | |
5918 | default: | |
5919 | freq_select = CDCLK_FREQ_337_308; | |
5920 | pcu_ack = 0; | |
5921 | break; | |
5922 | case 617140: | |
5923 | case 675000: | |
5924 | freq_select = CDCLK_FREQ_675_617; | |
5925 | pcu_ack = 3; | |
5926 | break; | |
5927 | } | |
5928 | ||
5929 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5930 | POSTING_READ(CDCLK_CTL); | |
5931 | ||
5932 | /* inform PCU of the change */ | |
5933 | mutex_lock(&dev_priv->rps.hw_lock); | |
5934 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5935 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5936 | |
5937 | intel_update_cdclk(dev); | |
5d96d8af DL |
5938 | } |
5939 | ||
5940 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5941 | { | |
5942 | /* disable DBUF power */ | |
5943 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5944 | POSTING_READ(DBUF_CTL); | |
5945 | ||
5946 | udelay(10); | |
5947 | ||
5948 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5949 | DRM_ERROR("DBuf power disable timeout\n"); | |
5950 | ||
ab96c1ee ID |
5951 | /* disable DPLL0 */ |
5952 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5953 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5954 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5955 | } |
5956 | ||
5957 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5958 | { | |
5d96d8af DL |
5959 | unsigned int required_vco; |
5960 | ||
39d9b85a GW |
5961 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5962 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5963 | /* enable DPLL0 */ | |
5964 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5965 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5966 | } |
5967 | ||
5d96d8af DL |
5968 | /* set CDCLK to the frequency the BIOS chose */ |
5969 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5970 | ||
5971 | /* enable DBUF power */ | |
5972 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5973 | POSTING_READ(DBUF_CTL); | |
5974 | ||
5975 | udelay(10); | |
5976 | ||
5977 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5978 | DRM_ERROR("DBuf power enable timeout\n"); | |
5979 | } | |
5980 | ||
c73666f3 SK |
5981 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5982 | { | |
5983 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5984 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5985 | int freq = dev_priv->skl_boot_cdclk; | |
5986 | ||
f1b391a5 SK |
5987 | /* |
5988 | * check if the pre-os intialized the display | |
5989 | * There is SWF18 scratchpad register defined which is set by the | |
5990 | * pre-os which can be used by the OS drivers to check the status | |
5991 | */ | |
5992 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5993 | goto sanitize; | |
5994 | ||
c73666f3 SK |
5995 | /* Is PLL enabled and locked ? */ |
5996 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5997 | goto sanitize; | |
5998 | ||
5999 | /* DPLL okay; verify the cdclock | |
6000 | * | |
6001 | * Noticed in some instances that the freq selection is correct but | |
6002 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6003 | * enable display. Verify the same as well. | |
6004 | */ | |
6005 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
6006 | /* All well; nothing to sanitize */ | |
6007 | return false; | |
6008 | sanitize: | |
6009 | /* | |
6010 | * As of now initialize with max cdclk till | |
6011 | * we get dynamic cdclk support | |
6012 | * */ | |
6013 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
6014 | skl_init_cdclk(dev_priv); | |
6015 | ||
6016 | /* we did have to sanitize */ | |
6017 | return true; | |
6018 | } | |
6019 | ||
30a970c6 JB |
6020 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6021 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6022 | { | |
6023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6024 | u32 val, cmd; | |
6025 | ||
164dfd28 VK |
6026 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6027 | != dev_priv->cdclk_freq); | |
d60c4473 | 6028 | |
dfcab17e | 6029 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6030 | cmd = 2; |
dfcab17e | 6031 | else if (cdclk == 266667) |
30a970c6 JB |
6032 | cmd = 1; |
6033 | else | |
6034 | cmd = 0; | |
6035 | ||
6036 | mutex_lock(&dev_priv->rps.hw_lock); | |
6037 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6038 | val &= ~DSPFREQGUAR_MASK; | |
6039 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6040 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6041 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6042 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6043 | 50)) { | |
6044 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6045 | } | |
6046 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6047 | ||
54433e91 VS |
6048 | mutex_lock(&dev_priv->sb_lock); |
6049 | ||
dfcab17e | 6050 | if (cdclk == 400000) { |
6bcda4f0 | 6051 | u32 divider; |
30a970c6 | 6052 | |
6bcda4f0 | 6053 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6054 | |
30a970c6 JB |
6055 | /* adjust cdclk divider */ |
6056 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6057 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6058 | val |= divider; |
6059 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6060 | |
6061 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6062 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6063 | 50)) |
6064 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6065 | } |
6066 | ||
30a970c6 JB |
6067 | /* adjust self-refresh exit latency value */ |
6068 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6069 | val &= ~0x7f; | |
6070 | ||
6071 | /* | |
6072 | * For high bandwidth configs, we set a higher latency in the bunit | |
6073 | * so that the core display fetch happens in time to avoid underruns. | |
6074 | */ | |
dfcab17e | 6075 | if (cdclk == 400000) |
30a970c6 JB |
6076 | val |= 4500 / 250; /* 4.5 usec */ |
6077 | else | |
6078 | val |= 3000 / 250; /* 3.0 usec */ | |
6079 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6080 | |
a580516d | 6081 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6082 | |
b6283055 | 6083 | intel_update_cdclk(dev); |
30a970c6 JB |
6084 | } |
6085 | ||
383c5a6a VS |
6086 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6087 | { | |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6089 | u32 val, cmd; | |
6090 | ||
164dfd28 VK |
6091 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
6092 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
6093 | |
6094 | switch (cdclk) { | |
383c5a6a VS |
6095 | case 333333: |
6096 | case 320000: | |
383c5a6a | 6097 | case 266667: |
383c5a6a | 6098 | case 200000: |
383c5a6a VS |
6099 | break; |
6100 | default: | |
5f77eeb0 | 6101 | MISSING_CASE(cdclk); |
383c5a6a VS |
6102 | return; |
6103 | } | |
6104 | ||
9d0d3fda VS |
6105 | /* |
6106 | * Specs are full of misinformation, but testing on actual | |
6107 | * hardware has shown that we just need to write the desired | |
6108 | * CCK divider into the Punit register. | |
6109 | */ | |
6110 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6111 | ||
383c5a6a VS |
6112 | mutex_lock(&dev_priv->rps.hw_lock); |
6113 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6114 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6115 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6116 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6117 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6118 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6119 | 50)) { | |
6120 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6121 | } | |
6122 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6123 | ||
b6283055 | 6124 | intel_update_cdclk(dev); |
383c5a6a VS |
6125 | } |
6126 | ||
30a970c6 JB |
6127 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6128 | int max_pixclk) | |
6129 | { | |
6bcda4f0 | 6130 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6131 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6132 | |
30a970c6 JB |
6133 | /* |
6134 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6135 | * 200MHz | |
6136 | * 267MHz | |
29dc7ef3 | 6137 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6138 | * 400MHz (VLV only) |
6139 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6140 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6141 | * |
6142 | * We seem to get an unstable or solid color picture at 200MHz. | |
6143 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6144 | * are off. | |
30a970c6 | 6145 | */ |
6cca3195 VS |
6146 | if (!IS_CHERRYVIEW(dev_priv) && |
6147 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6148 | return 400000; |
6cca3195 | 6149 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6150 | return freq_320; |
e37c67a1 | 6151 | else if (max_pixclk > 0) |
dfcab17e | 6152 | return 266667; |
e37c67a1 VS |
6153 | else |
6154 | return 200000; | |
30a970c6 JB |
6155 | } |
6156 | ||
f8437dd1 VK |
6157 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6158 | int max_pixclk) | |
6159 | { | |
6160 | /* | |
6161 | * FIXME: | |
6162 | * - remove the guardband, it's not needed on BXT | |
6163 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6164 | */ | |
6165 | if (max_pixclk > 576000*9/10) | |
6166 | return 624000; | |
6167 | else if (max_pixclk > 384000*9/10) | |
6168 | return 576000; | |
6169 | else if (max_pixclk > 288000*9/10) | |
6170 | return 384000; | |
6171 | else if (max_pixclk > 144000*9/10) | |
6172 | return 288000; | |
6173 | else | |
6174 | return 144000; | |
6175 | } | |
6176 | ||
e8788cbc | 6177 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6178 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6179 | struct drm_atomic_state *state) | |
30a970c6 | 6180 | { |
565602d7 ML |
6181 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6183 | struct drm_crtc *crtc; | |
6184 | struct drm_crtc_state *crtc_state; | |
6185 | unsigned max_pixclk = 0, i; | |
6186 | enum pipe pipe; | |
30a970c6 | 6187 | |
565602d7 ML |
6188 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6189 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6190 | |
565602d7 ML |
6191 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6192 | int pixclk = 0; | |
6193 | ||
6194 | if (crtc_state->enable) | |
6195 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6196 | |
565602d7 | 6197 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6198 | } |
6199 | ||
565602d7 ML |
6200 | for_each_pipe(dev_priv, pipe) |
6201 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6202 | ||
30a970c6 JB |
6203 | return max_pixclk; |
6204 | } | |
6205 | ||
27c329ed | 6206 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6207 | { |
27c329ed ML |
6208 | struct drm_device *dev = state->dev; |
6209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6210 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6211 | struct intel_atomic_state *intel_state = |
6212 | to_intel_atomic_state(state); | |
30a970c6 | 6213 | |
304603f4 ACO |
6214 | if (max_pixclk < 0) |
6215 | return max_pixclk; | |
30a970c6 | 6216 | |
1a617b77 | 6217 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6218 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6219 | |
1a617b77 ML |
6220 | if (!intel_state->active_crtcs) |
6221 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6222 | ||
27c329ed ML |
6223 | return 0; |
6224 | } | |
304603f4 | 6225 | |
27c329ed ML |
6226 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6227 | { | |
6228 | struct drm_device *dev = state->dev; | |
6229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6230 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6231 | struct intel_atomic_state *intel_state = |
6232 | to_intel_atomic_state(state); | |
85a96e7a | 6233 | |
27c329ed ML |
6234 | if (max_pixclk < 0) |
6235 | return max_pixclk; | |
85a96e7a | 6236 | |
1a617b77 | 6237 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6238 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6239 | |
1a617b77 ML |
6240 | if (!intel_state->active_crtcs) |
6241 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6242 | ||
27c329ed | 6243 | return 0; |
30a970c6 JB |
6244 | } |
6245 | ||
1e69cd74 VS |
6246 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6247 | { | |
6248 | unsigned int credits, default_credits; | |
6249 | ||
6250 | if (IS_CHERRYVIEW(dev_priv)) | |
6251 | default_credits = PFI_CREDIT(12); | |
6252 | else | |
6253 | default_credits = PFI_CREDIT(8); | |
6254 | ||
bfa7df01 | 6255 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6256 | /* CHV suggested value is 31 or 63 */ |
6257 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6258 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6259 | else |
6260 | credits = PFI_CREDIT(15); | |
6261 | } else { | |
6262 | credits = default_credits; | |
6263 | } | |
6264 | ||
6265 | /* | |
6266 | * WA - write default credits before re-programming | |
6267 | * FIXME: should we also set the resend bit here? | |
6268 | */ | |
6269 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6270 | default_credits); | |
6271 | ||
6272 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6273 | credits | PFI_CREDIT_RESEND); | |
6274 | ||
6275 | /* | |
6276 | * FIXME is this guaranteed to clear | |
6277 | * immediately or should we poll for it? | |
6278 | */ | |
6279 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6280 | } | |
6281 | ||
27c329ed | 6282 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6283 | { |
a821fc46 | 6284 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6285 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6286 | struct intel_atomic_state *old_intel_state = |
6287 | to_intel_atomic_state(old_state); | |
6288 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6289 | |
27c329ed ML |
6290 | /* |
6291 | * FIXME: We can end up here with all power domains off, yet | |
6292 | * with a CDCLK frequency other than the minimum. To account | |
6293 | * for this take the PIPE-A power domain, which covers the HW | |
6294 | * blocks needed for the following programming. This can be | |
6295 | * removed once it's guaranteed that we get here either with | |
6296 | * the minimum CDCLK set, or the required power domains | |
6297 | * enabled. | |
6298 | */ | |
6299 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6300 | |
27c329ed ML |
6301 | if (IS_CHERRYVIEW(dev)) |
6302 | cherryview_set_cdclk(dev, req_cdclk); | |
6303 | else | |
6304 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6305 | |
27c329ed | 6306 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6307 | |
27c329ed | 6308 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6309 | } |
6310 | ||
89b667f8 JB |
6311 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6312 | { | |
6313 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6314 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6316 | struct intel_encoder *encoder; | |
6317 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6318 | |
53d9f4e9 | 6319 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6320 | return; |
6321 | ||
6e3c9717 | 6322 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6323 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6324 | |
6325 | intel_set_pipe_timings(intel_crtc); | |
6326 | ||
c14b0485 VS |
6327 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6329 | ||
6330 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6331 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6332 | } | |
6333 | ||
5b18e57c DV |
6334 | i9xx_set_pipeconf(intel_crtc); |
6335 | ||
89b667f8 | 6336 | intel_crtc->active = true; |
89b667f8 | 6337 | |
a72e4c9f | 6338 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6339 | |
89b667f8 JB |
6340 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6341 | if (encoder->pre_pll_enable) | |
6342 | encoder->pre_pll_enable(encoder); | |
6343 | ||
a65347ba | 6344 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6345 | if (IS_CHERRYVIEW(dev)) { |
6346 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6347 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6348 | } else { |
6349 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6350 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6351 | } |
9d556c99 | 6352 | } |
89b667f8 JB |
6353 | |
6354 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6355 | if (encoder->pre_enable) | |
6356 | encoder->pre_enable(encoder); | |
6357 | ||
2dd24552 JB |
6358 | i9xx_pfit_enable(intel_crtc); |
6359 | ||
63cbb074 VS |
6360 | intel_crtc_load_lut(crtc); |
6361 | ||
e1fdc473 | 6362 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6363 | |
4b3a9526 VS |
6364 | assert_vblank_disabled(crtc); |
6365 | drm_crtc_vblank_on(crtc); | |
6366 | ||
f9b61ff6 DV |
6367 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6368 | encoder->enable(encoder); | |
89b667f8 JB |
6369 | } |
6370 | ||
f13c2ef3 DV |
6371 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6372 | { | |
6373 | struct drm_device *dev = crtc->base.dev; | |
6374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6375 | ||
6e3c9717 ACO |
6376 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6377 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6378 | } |
6379 | ||
0b8765c6 | 6380 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6381 | { |
6382 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6383 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6385 | struct intel_encoder *encoder; |
79e53945 | 6386 | int pipe = intel_crtc->pipe; |
79e53945 | 6387 | |
53d9f4e9 | 6388 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6389 | return; |
6390 | ||
f13c2ef3 DV |
6391 | i9xx_set_pll_dividers(intel_crtc); |
6392 | ||
6e3c9717 | 6393 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6394 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6395 | |
6396 | intel_set_pipe_timings(intel_crtc); | |
6397 | ||
5b18e57c DV |
6398 | i9xx_set_pipeconf(intel_crtc); |
6399 | ||
f7abfe8b | 6400 | intel_crtc->active = true; |
6b383a7f | 6401 | |
4a3436e8 | 6402 | if (!IS_GEN2(dev)) |
a72e4c9f | 6403 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6404 | |
9d6d9f19 MK |
6405 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6406 | if (encoder->pre_enable) | |
6407 | encoder->pre_enable(encoder); | |
6408 | ||
f6736a1a DV |
6409 | i9xx_enable_pll(intel_crtc); |
6410 | ||
2dd24552 JB |
6411 | i9xx_pfit_enable(intel_crtc); |
6412 | ||
63cbb074 VS |
6413 | intel_crtc_load_lut(crtc); |
6414 | ||
f37fcc2a | 6415 | intel_update_watermarks(crtc); |
e1fdc473 | 6416 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6417 | |
4b3a9526 VS |
6418 | assert_vblank_disabled(crtc); |
6419 | drm_crtc_vblank_on(crtc); | |
6420 | ||
f9b61ff6 DV |
6421 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6422 | encoder->enable(encoder); | |
0b8765c6 | 6423 | } |
79e53945 | 6424 | |
87476d63 DV |
6425 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6426 | { | |
6427 | struct drm_device *dev = crtc->base.dev; | |
6428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6429 | |
6e3c9717 | 6430 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6431 | return; |
87476d63 | 6432 | |
328d8e82 | 6433 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6434 | |
328d8e82 DV |
6435 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6436 | I915_READ(PFIT_CONTROL)); | |
6437 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6438 | } |
6439 | ||
0b8765c6 JB |
6440 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6441 | { | |
6442 | struct drm_device *dev = crtc->dev; | |
6443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6445 | struct intel_encoder *encoder; |
0b8765c6 | 6446 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6447 | |
6304cd91 VS |
6448 | /* |
6449 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6450 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6451 | * We also need to wait on all gmch platforms because of the |
6452 | * self-refresh mode constraint explained above. | |
6304cd91 | 6453 | */ |
564ed191 | 6454 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6455 | |
4b3a9526 VS |
6456 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6457 | encoder->disable(encoder); | |
6458 | ||
f9b61ff6 DV |
6459 | drm_crtc_vblank_off(crtc); |
6460 | assert_vblank_disabled(crtc); | |
6461 | ||
575f7ab7 | 6462 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6463 | |
87476d63 | 6464 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6465 | |
89b667f8 JB |
6466 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6467 | if (encoder->post_disable) | |
6468 | encoder->post_disable(encoder); | |
6469 | ||
a65347ba | 6470 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6471 | if (IS_CHERRYVIEW(dev)) |
6472 | chv_disable_pll(dev_priv, pipe); | |
6473 | else if (IS_VALLEYVIEW(dev)) | |
6474 | vlv_disable_pll(dev_priv, pipe); | |
6475 | else | |
1c4e0274 | 6476 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6477 | } |
0b8765c6 | 6478 | |
d6db995f VS |
6479 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6480 | if (encoder->post_pll_disable) | |
6481 | encoder->post_pll_disable(encoder); | |
6482 | ||
4a3436e8 | 6483 | if (!IS_GEN2(dev)) |
a72e4c9f | 6484 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6485 | } |
6486 | ||
b17d48e2 ML |
6487 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6488 | { | |
6489 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6490 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6491 | enum intel_display_power_domain domain; | |
6492 | unsigned long domains; | |
6493 | ||
6494 | if (!intel_crtc->active) | |
6495 | return; | |
6496 | ||
a539205a | 6497 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6498 | WARN_ON(intel_crtc->unpin_work); |
6499 | ||
a539205a | 6500 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6501 | |
6502 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6503 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6504 | } |
6505 | ||
b17d48e2 | 6506 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6507 | intel_crtc->active = false; |
58f9c0bc | 6508 | intel_fbc_disable(intel_crtc); |
37d9078b | 6509 | intel_update_watermarks(crtc); |
1f7457b1 | 6510 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6511 | |
6512 | domains = intel_crtc->enabled_power_domains; | |
6513 | for_each_power_domain(domain, domains) | |
6514 | intel_display_power_put(dev_priv, domain); | |
6515 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6516 | |
6517 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6518 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6519 | } |
6520 | ||
6b72d486 ML |
6521 | /* |
6522 | * turn all crtc's off, but do not adjust state | |
6523 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6524 | */ | |
70e0bd74 | 6525 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6526 | { |
e2c8b870 | 6527 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6528 | struct drm_atomic_state *state; |
e2c8b870 | 6529 | int ret; |
70e0bd74 | 6530 | |
e2c8b870 ML |
6531 | state = drm_atomic_helper_suspend(dev); |
6532 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6533 | if (ret) |
6534 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6535 | else |
6536 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6537 | return ret; |
ee7b9f93 JB |
6538 | } |
6539 | ||
ea5b213a | 6540 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6541 | { |
4ef69c7a | 6542 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6543 | |
ea5b213a CW |
6544 | drm_encoder_cleanup(encoder); |
6545 | kfree(intel_encoder); | |
7e7d76c3 JB |
6546 | } |
6547 | ||
0a91ca29 DV |
6548 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6549 | * internal consistency). */ | |
b980514c | 6550 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6551 | { |
35dd3c64 ML |
6552 | struct drm_crtc *crtc = connector->base.state->crtc; |
6553 | ||
6554 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6555 | connector->base.base.id, | |
6556 | connector->base.name); | |
6557 | ||
0a91ca29 | 6558 | if (connector->get_hw_state(connector)) { |
e85376cb | 6559 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6560 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6561 | |
35dd3c64 ML |
6562 | I915_STATE_WARN(!crtc, |
6563 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6564 | |
35dd3c64 ML |
6565 | if (!crtc) |
6566 | return; | |
6567 | ||
6568 | I915_STATE_WARN(!crtc->state->active, | |
6569 | "connector is active, but attached crtc isn't\n"); | |
6570 | ||
e85376cb | 6571 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6572 | return; |
6573 | ||
e85376cb | 6574 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6575 | "atomic encoder doesn't match attached encoder\n"); |
6576 | ||
e85376cb | 6577 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6578 | "attached encoder crtc differs from connector crtc\n"); |
6579 | } else { | |
4d688a2a ML |
6580 | I915_STATE_WARN(crtc && crtc->state->active, |
6581 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6582 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6583 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6584 | } |
79e53945 JB |
6585 | } |
6586 | ||
08d9bc92 ACO |
6587 | int intel_connector_init(struct intel_connector *connector) |
6588 | { | |
5350a031 | 6589 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6590 | |
5350a031 | 6591 | if (!connector->base.state) |
08d9bc92 ACO |
6592 | return -ENOMEM; |
6593 | ||
08d9bc92 ACO |
6594 | return 0; |
6595 | } | |
6596 | ||
6597 | struct intel_connector *intel_connector_alloc(void) | |
6598 | { | |
6599 | struct intel_connector *connector; | |
6600 | ||
6601 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6602 | if (!connector) | |
6603 | return NULL; | |
6604 | ||
6605 | if (intel_connector_init(connector) < 0) { | |
6606 | kfree(connector); | |
6607 | return NULL; | |
6608 | } | |
6609 | ||
6610 | return connector; | |
6611 | } | |
6612 | ||
f0947c37 DV |
6613 | /* Simple connector->get_hw_state implementation for encoders that support only |
6614 | * one connector and no cloning and hence the encoder state determines the state | |
6615 | * of the connector. */ | |
6616 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6617 | { |
24929352 | 6618 | enum pipe pipe = 0; |
f0947c37 | 6619 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6620 | |
f0947c37 | 6621 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6622 | } |
6623 | ||
6d293983 | 6624 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6625 | { |
6d293983 ACO |
6626 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6627 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6628 | |
6629 | return 0; | |
6630 | } | |
6631 | ||
6d293983 | 6632 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6633 | struct intel_crtc_state *pipe_config) |
1857e1da | 6634 | { |
6d293983 ACO |
6635 | struct drm_atomic_state *state = pipe_config->base.state; |
6636 | struct intel_crtc *other_crtc; | |
6637 | struct intel_crtc_state *other_crtc_state; | |
6638 | ||
1857e1da DV |
6639 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6640 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6641 | if (pipe_config->fdi_lanes > 4) { | |
6642 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6643 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6644 | return -EINVAL; |
1857e1da DV |
6645 | } |
6646 | ||
bafb6553 | 6647 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6648 | if (pipe_config->fdi_lanes > 2) { |
6649 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6650 | pipe_config->fdi_lanes); | |
6d293983 | 6651 | return -EINVAL; |
1857e1da | 6652 | } else { |
6d293983 | 6653 | return 0; |
1857e1da DV |
6654 | } |
6655 | } | |
6656 | ||
6657 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6658 | return 0; |
1857e1da DV |
6659 | |
6660 | /* Ivybridge 3 pipe is really complicated */ | |
6661 | switch (pipe) { | |
6662 | case PIPE_A: | |
6d293983 | 6663 | return 0; |
1857e1da | 6664 | case PIPE_B: |
6d293983 ACO |
6665 | if (pipe_config->fdi_lanes <= 2) |
6666 | return 0; | |
6667 | ||
6668 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6669 | other_crtc_state = | |
6670 | intel_atomic_get_crtc_state(state, other_crtc); | |
6671 | if (IS_ERR(other_crtc_state)) | |
6672 | return PTR_ERR(other_crtc_state); | |
6673 | ||
6674 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6675 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6676 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6677 | return -EINVAL; |
1857e1da | 6678 | } |
6d293983 | 6679 | return 0; |
1857e1da | 6680 | case PIPE_C: |
251cc67c VS |
6681 | if (pipe_config->fdi_lanes > 2) { |
6682 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6683 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6684 | return -EINVAL; |
251cc67c | 6685 | } |
6d293983 ACO |
6686 | |
6687 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6688 | other_crtc_state = | |
6689 | intel_atomic_get_crtc_state(state, other_crtc); | |
6690 | if (IS_ERR(other_crtc_state)) | |
6691 | return PTR_ERR(other_crtc_state); | |
6692 | ||
6693 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6694 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6695 | return -EINVAL; |
1857e1da | 6696 | } |
6d293983 | 6697 | return 0; |
1857e1da DV |
6698 | default: |
6699 | BUG(); | |
6700 | } | |
6701 | } | |
6702 | ||
e29c22c0 DV |
6703 | #define RETRY 1 |
6704 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6705 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6706 | { |
1857e1da | 6707 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6708 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6709 | int lane, link_bw, fdi_dotclock, ret; |
6710 | bool needs_recompute = false; | |
877d48d5 | 6711 | |
e29c22c0 | 6712 | retry: |
877d48d5 DV |
6713 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6714 | * each output octet as 10 bits. The actual frequency | |
6715 | * is stored as a divider into a 100MHz clock, and the | |
6716 | * mode pixel clock is stored in units of 1KHz. | |
6717 | * Hence the bw of each lane in terms of the mode signal | |
6718 | * is: | |
6719 | */ | |
21a727b3 | 6720 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6721 | |
241bfc38 | 6722 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6723 | |
2bd89a07 | 6724 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6725 | pipe_config->pipe_bpp); |
6726 | ||
6727 | pipe_config->fdi_lanes = lane; | |
6728 | ||
2bd89a07 | 6729 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6730 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6731 | |
e3b247da | 6732 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6733 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6734 | pipe_config->pipe_bpp -= 2*3; |
6735 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6736 | pipe_config->pipe_bpp); | |
6737 | needs_recompute = true; | |
6738 | pipe_config->bw_constrained = true; | |
6739 | ||
6740 | goto retry; | |
6741 | } | |
6742 | ||
6743 | if (needs_recompute) | |
6744 | return RETRY; | |
6745 | ||
6d293983 | 6746 | return ret; |
877d48d5 DV |
6747 | } |
6748 | ||
8cfb3407 VS |
6749 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6750 | struct intel_crtc_state *pipe_config) | |
6751 | { | |
6752 | if (pipe_config->pipe_bpp > 24) | |
6753 | return false; | |
6754 | ||
6755 | /* HSW can handle pixel rate up to cdclk? */ | |
6756 | if (IS_HASWELL(dev_priv->dev)) | |
6757 | return true; | |
6758 | ||
6759 | /* | |
b432e5cf VS |
6760 | * We compare against max which means we must take |
6761 | * the increased cdclk requirement into account when | |
6762 | * calculating the new cdclk. | |
6763 | * | |
6764 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6765 | */ |
6766 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6767 | dev_priv->max_cdclk_freq * 95 / 100; | |
6768 | } | |
6769 | ||
42db64ef | 6770 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6771 | struct intel_crtc_state *pipe_config) |
42db64ef | 6772 | { |
8cfb3407 VS |
6773 | struct drm_device *dev = crtc->base.dev; |
6774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6775 | ||
d330a953 | 6776 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6777 | hsw_crtc_supports_ips(crtc) && |
6778 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6779 | } |
6780 | ||
39acb4aa VS |
6781 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6782 | { | |
6783 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6784 | ||
6785 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6786 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6787 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6788 | } | |
6789 | ||
a43f6e0f | 6790 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6791 | struct intel_crtc_state *pipe_config) |
79e53945 | 6792 | { |
a43f6e0f | 6793 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6794 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6795 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6796 | |
ad3a4479 | 6797 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6798 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6799 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6800 | |
6801 | /* | |
39acb4aa | 6802 | * Enable double wide mode when the dot clock |
cf532bb2 | 6803 | * is > 90% of the (display) core speed. |
cf532bb2 | 6804 | */ |
39acb4aa VS |
6805 | if (intel_crtc_supports_double_wide(crtc) && |
6806 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6807 | clock_limit *= 2; |
cf532bb2 | 6808 | pipe_config->double_wide = true; |
ad3a4479 VS |
6809 | } |
6810 | ||
39acb4aa VS |
6811 | if (adjusted_mode->crtc_clock > clock_limit) { |
6812 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6813 | adjusted_mode->crtc_clock, clock_limit, | |
6814 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6815 | return -EINVAL; |
39acb4aa | 6816 | } |
2c07245f | 6817 | } |
89749350 | 6818 | |
1d1d0e27 VS |
6819 | /* |
6820 | * Pipe horizontal size must be even in: | |
6821 | * - DVO ganged mode | |
6822 | * - LVDS dual channel mode | |
6823 | * - Double wide pipe | |
6824 | */ | |
a93e255f | 6825 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6826 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6827 | pipe_config->pipe_src_w &= ~1; | |
6828 | ||
8693a824 DL |
6829 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6830 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6831 | */ |
6832 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6833 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6834 | return -EINVAL; |
44f46b42 | 6835 | |
f5adf94e | 6836 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6837 | hsw_compute_ips_config(crtc, pipe_config); |
6838 | ||
877d48d5 | 6839 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6840 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6841 | |
cf5a15be | 6842 | return 0; |
79e53945 JB |
6843 | } |
6844 | ||
1652d19e VS |
6845 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6846 | { | |
6847 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6848 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6849 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6850 | uint32_t linkrate; | |
6851 | ||
414355a7 | 6852 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6853 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6854 | |
6855 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6856 | return 540000; | |
6857 | ||
6858 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6859 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6860 | |
71cd8423 DL |
6861 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6862 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6863 | /* vco 8640 */ |
6864 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6865 | case CDCLK_FREQ_450_432: | |
6866 | return 432000; | |
6867 | case CDCLK_FREQ_337_308: | |
6868 | return 308570; | |
6869 | case CDCLK_FREQ_675_617: | |
6870 | return 617140; | |
6871 | default: | |
6872 | WARN(1, "Unknown cd freq selection\n"); | |
6873 | } | |
6874 | } else { | |
6875 | /* vco 8100 */ | |
6876 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6877 | case CDCLK_FREQ_450_432: | |
6878 | return 450000; | |
6879 | case CDCLK_FREQ_337_308: | |
6880 | return 337500; | |
6881 | case CDCLK_FREQ_675_617: | |
6882 | return 675000; | |
6883 | default: | |
6884 | WARN(1, "Unknown cd freq selection\n"); | |
6885 | } | |
6886 | } | |
6887 | ||
6888 | /* error case, do as if DPLL0 isn't enabled */ | |
6889 | return 24000; | |
6890 | } | |
6891 | ||
acd3f3d3 BP |
6892 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6893 | { | |
6894 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6895 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6896 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6897 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6898 | int cdclk; | |
6899 | ||
6900 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6901 | return 19200; | |
6902 | ||
6903 | cdclk = 19200 * pll_ratio / 2; | |
6904 | ||
6905 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6906 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6907 | return cdclk; /* 576MHz or 624MHz */ | |
6908 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6909 | return cdclk * 2 / 3; /* 384MHz */ | |
6910 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6911 | return cdclk / 2; /* 288MHz */ | |
6912 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6913 | return cdclk / 4; /* 144MHz */ | |
6914 | } | |
6915 | ||
6916 | /* error case, do as if DE PLL isn't enabled */ | |
6917 | return 19200; | |
6918 | } | |
6919 | ||
1652d19e VS |
6920 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6921 | { | |
6922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6923 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6924 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6925 | ||
6926 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6927 | return 800000; | |
6928 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6929 | return 450000; | |
6930 | else if (freq == LCPLL_CLK_FREQ_450) | |
6931 | return 450000; | |
6932 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6933 | return 540000; | |
6934 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6935 | return 337500; | |
6936 | else | |
6937 | return 675000; | |
6938 | } | |
6939 | ||
6940 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6941 | { | |
6942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6943 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6944 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6945 | ||
6946 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6947 | return 800000; | |
6948 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6949 | return 450000; | |
6950 | else if (freq == LCPLL_CLK_FREQ_450) | |
6951 | return 450000; | |
6952 | else if (IS_HSW_ULT(dev)) | |
6953 | return 337500; | |
6954 | else | |
6955 | return 540000; | |
79e53945 JB |
6956 | } |
6957 | ||
25eb05fc JB |
6958 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6959 | { | |
bfa7df01 VS |
6960 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6961 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6962 | } |
6963 | ||
b37a6434 VS |
6964 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6965 | { | |
6966 | return 450000; | |
6967 | } | |
6968 | ||
e70236a8 JB |
6969 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6970 | { | |
6971 | return 400000; | |
6972 | } | |
79e53945 | 6973 | |
e70236a8 | 6974 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6975 | { |
e907f170 | 6976 | return 333333; |
e70236a8 | 6977 | } |
79e53945 | 6978 | |
e70236a8 JB |
6979 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6980 | { | |
6981 | return 200000; | |
6982 | } | |
79e53945 | 6983 | |
257a7ffc DV |
6984 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6985 | { | |
6986 | u16 gcfgc = 0; | |
6987 | ||
6988 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6989 | ||
6990 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6991 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6992 | return 266667; |
257a7ffc | 6993 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6994 | return 333333; |
257a7ffc | 6995 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6996 | return 444444; |
257a7ffc DV |
6997 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6998 | return 200000; | |
6999 | default: | |
7000 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7001 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7002 | return 133333; |
257a7ffc | 7003 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7004 | return 166667; |
257a7ffc DV |
7005 | } |
7006 | } | |
7007 | ||
e70236a8 JB |
7008 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
7009 | { | |
7010 | u16 gcfgc = 0; | |
79e53945 | 7011 | |
e70236a8 JB |
7012 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
7013 | ||
7014 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7015 | return 133333; |
e70236a8 JB |
7016 | else { |
7017 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7018 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7019 | return 333333; |
e70236a8 JB |
7020 | default: |
7021 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7022 | return 190000; | |
79e53945 | 7023 | } |
e70236a8 JB |
7024 | } |
7025 | } | |
7026 | ||
7027 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
7028 | { | |
e907f170 | 7029 | return 266667; |
e70236a8 JB |
7030 | } |
7031 | ||
1b1d2716 | 7032 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
7033 | { |
7034 | u16 hpllcc = 0; | |
1b1d2716 | 7035 | |
65cd2b3f VS |
7036 | /* |
7037 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7038 | * encoding is different :( | |
7039 | * FIXME is this the right way to detect 852GM/852GMV? | |
7040 | */ | |
7041 | if (dev->pdev->revision == 0x1) | |
7042 | return 133333; | |
7043 | ||
1b1d2716 VS |
7044 | pci_bus_read_config_word(dev->pdev->bus, |
7045 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
7046 | ||
e70236a8 JB |
7047 | /* Assume that the hardware is in the high speed state. This |
7048 | * should be the default. | |
7049 | */ | |
7050 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7051 | case GC_CLOCK_133_200: | |
1b1d2716 | 7052 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7053 | case GC_CLOCK_100_200: |
7054 | return 200000; | |
7055 | case GC_CLOCK_166_250: | |
7056 | return 250000; | |
7057 | case GC_CLOCK_100_133: | |
e907f170 | 7058 | return 133333; |
1b1d2716 VS |
7059 | case GC_CLOCK_133_266: |
7060 | case GC_CLOCK_133_266_2: | |
7061 | case GC_CLOCK_166_266: | |
7062 | return 266667; | |
e70236a8 | 7063 | } |
79e53945 | 7064 | |
e70236a8 JB |
7065 | /* Shouldn't happen */ |
7066 | return 0; | |
7067 | } | |
79e53945 | 7068 | |
e70236a8 JB |
7069 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7070 | { | |
e907f170 | 7071 | return 133333; |
79e53945 JB |
7072 | } |
7073 | ||
34edce2f VS |
7074 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7075 | { | |
7076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7077 | static const unsigned int blb_vco[8] = { | |
7078 | [0] = 3200000, | |
7079 | [1] = 4000000, | |
7080 | [2] = 5333333, | |
7081 | [3] = 4800000, | |
7082 | [4] = 6400000, | |
7083 | }; | |
7084 | static const unsigned int pnv_vco[8] = { | |
7085 | [0] = 3200000, | |
7086 | [1] = 4000000, | |
7087 | [2] = 5333333, | |
7088 | [3] = 4800000, | |
7089 | [4] = 2666667, | |
7090 | }; | |
7091 | static const unsigned int cl_vco[8] = { | |
7092 | [0] = 3200000, | |
7093 | [1] = 4000000, | |
7094 | [2] = 5333333, | |
7095 | [3] = 6400000, | |
7096 | [4] = 3333333, | |
7097 | [5] = 3566667, | |
7098 | [6] = 4266667, | |
7099 | }; | |
7100 | static const unsigned int elk_vco[8] = { | |
7101 | [0] = 3200000, | |
7102 | [1] = 4000000, | |
7103 | [2] = 5333333, | |
7104 | [3] = 4800000, | |
7105 | }; | |
7106 | static const unsigned int ctg_vco[8] = { | |
7107 | [0] = 3200000, | |
7108 | [1] = 4000000, | |
7109 | [2] = 5333333, | |
7110 | [3] = 6400000, | |
7111 | [4] = 2666667, | |
7112 | [5] = 4266667, | |
7113 | }; | |
7114 | const unsigned int *vco_table; | |
7115 | unsigned int vco; | |
7116 | uint8_t tmp = 0; | |
7117 | ||
7118 | /* FIXME other chipsets? */ | |
7119 | if (IS_GM45(dev)) | |
7120 | vco_table = ctg_vco; | |
7121 | else if (IS_G4X(dev)) | |
7122 | vco_table = elk_vco; | |
7123 | else if (IS_CRESTLINE(dev)) | |
7124 | vco_table = cl_vco; | |
7125 | else if (IS_PINEVIEW(dev)) | |
7126 | vco_table = pnv_vco; | |
7127 | else if (IS_G33(dev)) | |
7128 | vco_table = blb_vco; | |
7129 | else | |
7130 | return 0; | |
7131 | ||
7132 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7133 | ||
7134 | vco = vco_table[tmp & 0x7]; | |
7135 | if (vco == 0) | |
7136 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7137 | else | |
7138 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7139 | ||
7140 | return vco; | |
7141 | } | |
7142 | ||
7143 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7144 | { | |
7145 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7146 | uint16_t tmp = 0; | |
7147 | ||
7148 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7149 | ||
7150 | cdclk_sel = (tmp >> 12) & 0x1; | |
7151 | ||
7152 | switch (vco) { | |
7153 | case 2666667: | |
7154 | case 4000000: | |
7155 | case 5333333: | |
7156 | return cdclk_sel ? 333333 : 222222; | |
7157 | case 3200000: | |
7158 | return cdclk_sel ? 320000 : 228571; | |
7159 | default: | |
7160 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7161 | return 222222; | |
7162 | } | |
7163 | } | |
7164 | ||
7165 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7166 | { | |
7167 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7168 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7169 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7170 | const uint8_t *div_table; | |
7171 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7172 | uint16_t tmp = 0; | |
7173 | ||
7174 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7175 | ||
7176 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7177 | ||
7178 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7179 | goto fail; | |
7180 | ||
7181 | switch (vco) { | |
7182 | case 3200000: | |
7183 | div_table = div_3200; | |
7184 | break; | |
7185 | case 4000000: | |
7186 | div_table = div_4000; | |
7187 | break; | |
7188 | case 5333333: | |
7189 | div_table = div_5333; | |
7190 | break; | |
7191 | default: | |
7192 | goto fail; | |
7193 | } | |
7194 | ||
7195 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7196 | ||
caf4e252 | 7197 | fail: |
34edce2f VS |
7198 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7199 | return 200000; | |
7200 | } | |
7201 | ||
7202 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7203 | { | |
7204 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7205 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7206 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7207 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7208 | const uint8_t *div_table; | |
7209 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7210 | uint16_t tmp = 0; | |
7211 | ||
7212 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7213 | ||
7214 | cdclk_sel = (tmp >> 4) & 0x7; | |
7215 | ||
7216 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7217 | goto fail; | |
7218 | ||
7219 | switch (vco) { | |
7220 | case 3200000: | |
7221 | div_table = div_3200; | |
7222 | break; | |
7223 | case 4000000: | |
7224 | div_table = div_4000; | |
7225 | break; | |
7226 | case 4800000: | |
7227 | div_table = div_4800; | |
7228 | break; | |
7229 | case 5333333: | |
7230 | div_table = div_5333; | |
7231 | break; | |
7232 | default: | |
7233 | goto fail; | |
7234 | } | |
7235 | ||
7236 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7237 | ||
caf4e252 | 7238 | fail: |
34edce2f VS |
7239 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7240 | return 190476; | |
7241 | } | |
7242 | ||
2c07245f | 7243 | static void |
a65851af | 7244 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7245 | { |
a65851af VS |
7246 | while (*num > DATA_LINK_M_N_MASK || |
7247 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7248 | *num >>= 1; |
7249 | *den >>= 1; | |
7250 | } | |
7251 | } | |
7252 | ||
a65851af VS |
7253 | static void compute_m_n(unsigned int m, unsigned int n, |
7254 | uint32_t *ret_m, uint32_t *ret_n) | |
7255 | { | |
7256 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7257 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7258 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7259 | } | |
7260 | ||
e69d0bc1 DV |
7261 | void |
7262 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7263 | int pixel_clock, int link_clock, | |
7264 | struct intel_link_m_n *m_n) | |
2c07245f | 7265 | { |
e69d0bc1 | 7266 | m_n->tu = 64; |
a65851af VS |
7267 | |
7268 | compute_m_n(bits_per_pixel * pixel_clock, | |
7269 | link_clock * nlanes * 8, | |
7270 | &m_n->gmch_m, &m_n->gmch_n); | |
7271 | ||
7272 | compute_m_n(pixel_clock, link_clock, | |
7273 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7274 | } |
7275 | ||
a7615030 CW |
7276 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7277 | { | |
d330a953 JN |
7278 | if (i915.panel_use_ssc >= 0) |
7279 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7280 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7281 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7282 | } |
7283 | ||
a93e255f ACO |
7284 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7285 | int num_connectors) | |
c65d77d8 | 7286 | { |
a93e255f | 7287 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7288 | struct drm_i915_private *dev_priv = dev->dev_private; |
7289 | int refclk; | |
7290 | ||
a93e255f ACO |
7291 | WARN_ON(!crtc_state->base.state); |
7292 | ||
666a4537 | 7293 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7294 | refclk = 100000; |
a93e255f | 7295 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7296 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7297 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7298 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7299 | } else if (!IS_GEN2(dev)) { |
7300 | refclk = 96000; | |
7301 | } else { | |
7302 | refclk = 48000; | |
7303 | } | |
7304 | ||
7305 | return refclk; | |
7306 | } | |
7307 | ||
7429e9d4 | 7308 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7309 | { |
7df00d7a | 7310 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7311 | } |
f47709a9 | 7312 | |
7429e9d4 DV |
7313 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7314 | { | |
7315 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7316 | } |
7317 | ||
f47709a9 | 7318 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7319 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7320 | intel_clock_t *reduced_clock) |
7321 | { | |
f47709a9 | 7322 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7323 | u32 fp, fp2 = 0; |
7324 | ||
7325 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7326 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7327 | if (reduced_clock) |
7429e9d4 | 7328 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7329 | } else { |
190f68c5 | 7330 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7331 | if (reduced_clock) |
7429e9d4 | 7332 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7333 | } |
7334 | ||
190f68c5 | 7335 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7336 | |
f47709a9 | 7337 | crtc->lowfreq_avail = false; |
a93e255f | 7338 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7339 | reduced_clock) { |
190f68c5 | 7340 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7341 | crtc->lowfreq_avail = true; |
a7516a05 | 7342 | } else { |
190f68c5 | 7343 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7344 | } |
7345 | } | |
7346 | ||
5e69f97f CML |
7347 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7348 | pipe) | |
89b667f8 JB |
7349 | { |
7350 | u32 reg_val; | |
7351 | ||
7352 | /* | |
7353 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7354 | * and set it to a reasonable value instead. | |
7355 | */ | |
ab3c759a | 7356 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7357 | reg_val &= 0xffffff00; |
7358 | reg_val |= 0x00000030; | |
ab3c759a | 7359 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7360 | |
ab3c759a | 7361 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7362 | reg_val &= 0x8cffffff; |
7363 | reg_val = 0x8c000000; | |
ab3c759a | 7364 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7365 | |
ab3c759a | 7366 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7367 | reg_val &= 0xffffff00; |
ab3c759a | 7368 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7369 | |
ab3c759a | 7370 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7371 | reg_val &= 0x00ffffff; |
7372 | reg_val |= 0xb0000000; | |
ab3c759a | 7373 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7374 | } |
7375 | ||
b551842d DV |
7376 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7377 | struct intel_link_m_n *m_n) | |
7378 | { | |
7379 | struct drm_device *dev = crtc->base.dev; | |
7380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7381 | int pipe = crtc->pipe; | |
7382 | ||
e3b95f1e DV |
7383 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7384 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7385 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7386 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7387 | } |
7388 | ||
7389 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7390 | struct intel_link_m_n *m_n, |
7391 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7392 | { |
7393 | struct drm_device *dev = crtc->base.dev; | |
7394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7395 | int pipe = crtc->pipe; | |
6e3c9717 | 7396 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7397 | |
7398 | if (INTEL_INFO(dev)->gen >= 5) { | |
7399 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7400 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7401 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7402 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7403 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7404 | * for gen < 8) and if DRRS is supported (to make sure the | |
7405 | * registers are not unnecessarily accessed). | |
7406 | */ | |
44395bfe | 7407 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7408 | crtc->config->has_drrs) { |
f769cd24 VK |
7409 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7410 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7411 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7412 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7413 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7414 | } | |
b551842d | 7415 | } else { |
e3b95f1e DV |
7416 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7417 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7418 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7419 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7420 | } |
7421 | } | |
7422 | ||
fe3cd48d | 7423 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7424 | { |
fe3cd48d R |
7425 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7426 | ||
7427 | if (m_n == M1_N1) { | |
7428 | dp_m_n = &crtc->config->dp_m_n; | |
7429 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7430 | } else if (m_n == M2_N2) { | |
7431 | ||
7432 | /* | |
7433 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7434 | * needs to be programmed into M1_N1. | |
7435 | */ | |
7436 | dp_m_n = &crtc->config->dp_m2_n2; | |
7437 | } else { | |
7438 | DRM_ERROR("Unsupported divider value\n"); | |
7439 | return; | |
7440 | } | |
7441 | ||
6e3c9717 ACO |
7442 | if (crtc->config->has_pch_encoder) |
7443 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7444 | else |
fe3cd48d | 7445 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7446 | } |
7447 | ||
251ac862 DV |
7448 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7449 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7450 | { |
7451 | u32 dpll, dpll_md; | |
7452 | ||
7453 | /* | |
7454 | * Enable DPIO clock input. We should never disable the reference | |
7455 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7456 | * on it. | |
7457 | */ | |
60bfe44f VS |
7458 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7459 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7460 | /* We should never disable this, set it here for state tracking */ |
7461 | if (crtc->pipe == PIPE_B) | |
7462 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7463 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7464 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7465 | |
d288f65f | 7466 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7467 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7468 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7469 | } |
7470 | ||
d288f65f | 7471 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7472 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7473 | { |
f47709a9 | 7474 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7475 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7476 | int pipe = crtc->pipe; |
bdd4b6a6 | 7477 | u32 mdiv; |
a0c4da24 | 7478 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7479 | u32 coreclk, reg_val; |
a0c4da24 | 7480 | |
a580516d | 7481 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7482 | |
d288f65f VS |
7483 | bestn = pipe_config->dpll.n; |
7484 | bestm1 = pipe_config->dpll.m1; | |
7485 | bestm2 = pipe_config->dpll.m2; | |
7486 | bestp1 = pipe_config->dpll.p1; | |
7487 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7488 | |
89b667f8 JB |
7489 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7490 | ||
7491 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7492 | if (pipe == PIPE_B) |
5e69f97f | 7493 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7494 | |
7495 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7496 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7497 | |
7498 | /* Disable target IRef on PLL */ | |
ab3c759a | 7499 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7500 | reg_val &= 0x00ffffff; |
ab3c759a | 7501 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7502 | |
7503 | /* Disable fast lock */ | |
ab3c759a | 7504 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7505 | |
7506 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7507 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7508 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7509 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7510 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7511 | |
7512 | /* | |
7513 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7514 | * but we don't support that). | |
7515 | * Note: don't use the DAC post divider as it seems unstable. | |
7516 | */ | |
7517 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7518 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7519 | |
a0c4da24 | 7520 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7521 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7522 | |
89b667f8 | 7523 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7524 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7525 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7526 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7527 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7528 | 0x009f0003); |
89b667f8 | 7529 | else |
ab3c759a | 7530 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7531 | 0x00d0000f); |
7532 | ||
681a8504 | 7533 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7534 | /* Use SSC source */ |
bdd4b6a6 | 7535 | if (pipe == PIPE_A) |
ab3c759a | 7536 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7537 | 0x0df40000); |
7538 | else | |
ab3c759a | 7539 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7540 | 0x0df70000); |
7541 | } else { /* HDMI or VGA */ | |
7542 | /* Use bend source */ | |
bdd4b6a6 | 7543 | if (pipe == PIPE_A) |
ab3c759a | 7544 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7545 | 0x0df70000); |
7546 | else | |
ab3c759a | 7547 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7548 | 0x0df40000); |
7549 | } | |
a0c4da24 | 7550 | |
ab3c759a | 7551 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7552 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7553 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7554 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7555 | coreclk |= 0x01000000; |
ab3c759a | 7556 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7557 | |
ab3c759a | 7558 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7559 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7560 | } |
7561 | ||
251ac862 DV |
7562 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7563 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7564 | { |
60bfe44f VS |
7565 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7566 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7567 | DPLL_VCO_ENABLE; |
7568 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7569 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7570 | |
d288f65f VS |
7571 | pipe_config->dpll_hw_state.dpll_md = |
7572 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7573 | } |
7574 | ||
d288f65f | 7575 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7576 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7577 | { |
7578 | struct drm_device *dev = crtc->base.dev; | |
7579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7580 | int pipe = crtc->pipe; | |
f0f59a00 | 7581 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7582 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7583 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7584 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7585 | u32 dpio_val; |
9cbe40c1 | 7586 | int vco; |
9d556c99 | 7587 | |
d288f65f VS |
7588 | bestn = pipe_config->dpll.n; |
7589 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7590 | bestm1 = pipe_config->dpll.m1; | |
7591 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7592 | bestp1 = pipe_config->dpll.p1; | |
7593 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7594 | vco = pipe_config->dpll.vco; |
a945ce7e | 7595 | dpio_val = 0; |
9cbe40c1 | 7596 | loopfilter = 0; |
9d556c99 CML |
7597 | |
7598 | /* | |
7599 | * Enable Refclk and SSC | |
7600 | */ | |
a11b0703 | 7601 | I915_WRITE(dpll_reg, |
d288f65f | 7602 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7603 | |
a580516d | 7604 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7605 | |
9d556c99 CML |
7606 | /* p1 and p2 divider */ |
7607 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7608 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7609 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7610 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7611 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7612 | ||
7613 | /* Feedback post-divider - m2 */ | |
7614 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7615 | ||
7616 | /* Feedback refclk divider - n and m1 */ | |
7617 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7618 | DPIO_CHV_M1_DIV_BY_2 | | |
7619 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7620 | ||
7621 | /* M2 fraction division */ | |
25a25dfc | 7622 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7623 | |
7624 | /* M2 fraction division enable */ | |
a945ce7e VP |
7625 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7626 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7627 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7628 | if (bestm2_frac) | |
7629 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7630 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7631 | |
de3a0fde VP |
7632 | /* Program digital lock detect threshold */ |
7633 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7634 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7635 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7636 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7637 | if (!bestm2_frac) | |
7638 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7639 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7640 | ||
9d556c99 | 7641 | /* Loop filter */ |
9cbe40c1 VP |
7642 | if (vco == 5400000) { |
7643 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7644 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7645 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7646 | tribuf_calcntr = 0x9; | |
7647 | } else if (vco <= 6200000) { | |
7648 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7649 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7650 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7651 | tribuf_calcntr = 0x9; | |
7652 | } else if (vco <= 6480000) { | |
7653 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7654 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7655 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7656 | tribuf_calcntr = 0x8; | |
7657 | } else { | |
7658 | /* Not supported. Apply the same limits as in the max case */ | |
7659 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7660 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7661 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7662 | tribuf_calcntr = 0; | |
7663 | } | |
9d556c99 CML |
7664 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7665 | ||
968040b2 | 7666 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7667 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7668 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7669 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7670 | ||
9d556c99 CML |
7671 | /* AFC Recal */ |
7672 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7673 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7674 | DPIO_AFC_RECAL); | |
7675 | ||
a580516d | 7676 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7677 | } |
7678 | ||
d288f65f VS |
7679 | /** |
7680 | * vlv_force_pll_on - forcibly enable just the PLL | |
7681 | * @dev_priv: i915 private structure | |
7682 | * @pipe: pipe PLL to enable | |
7683 | * @dpll: PLL configuration | |
7684 | * | |
7685 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7686 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7687 | * be enabled. | |
7688 | */ | |
3f36b937 TU |
7689 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7690 | const struct dpll *dpll) | |
d288f65f VS |
7691 | { |
7692 | struct intel_crtc *crtc = | |
7693 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7694 | struct intel_crtc_state *pipe_config; |
7695 | ||
7696 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7697 | if (!pipe_config) | |
7698 | return -ENOMEM; | |
7699 | ||
7700 | pipe_config->base.crtc = &crtc->base; | |
7701 | pipe_config->pixel_multiplier = 1; | |
7702 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7703 | |
7704 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7705 | chv_compute_dpll(crtc, pipe_config); |
7706 | chv_prepare_pll(crtc, pipe_config); | |
7707 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7708 | } else { |
3f36b937 TU |
7709 | vlv_compute_dpll(crtc, pipe_config); |
7710 | vlv_prepare_pll(crtc, pipe_config); | |
7711 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7712 | } |
3f36b937 TU |
7713 | |
7714 | kfree(pipe_config); | |
7715 | ||
7716 | return 0; | |
d288f65f VS |
7717 | } |
7718 | ||
7719 | /** | |
7720 | * vlv_force_pll_off - forcibly disable just the PLL | |
7721 | * @dev_priv: i915 private structure | |
7722 | * @pipe: pipe PLL to disable | |
7723 | * | |
7724 | * Disable the PLL for @pipe. To be used in cases where we need | |
7725 | * the PLL enabled even when @pipe is not going to be enabled. | |
7726 | */ | |
7727 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7728 | { | |
7729 | if (IS_CHERRYVIEW(dev)) | |
7730 | chv_disable_pll(to_i915(dev), pipe); | |
7731 | else | |
7732 | vlv_disable_pll(to_i915(dev), pipe); | |
7733 | } | |
7734 | ||
251ac862 DV |
7735 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7736 | struct intel_crtc_state *crtc_state, | |
7737 | intel_clock_t *reduced_clock, | |
7738 | int num_connectors) | |
eb1cbe48 | 7739 | { |
f47709a9 | 7740 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7741 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7742 | u32 dpll; |
7743 | bool is_sdvo; | |
190f68c5 | 7744 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7745 | |
190f68c5 | 7746 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7747 | |
a93e255f ACO |
7748 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7749 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7750 | |
7751 | dpll = DPLL_VGA_MODE_DIS; | |
7752 | ||
a93e255f | 7753 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7754 | dpll |= DPLLB_MODE_LVDS; |
7755 | else | |
7756 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7757 | |
ef1b460d | 7758 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7759 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7760 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7761 | } |
198a037f DV |
7762 | |
7763 | if (is_sdvo) | |
4a33e48d | 7764 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7765 | |
190f68c5 | 7766 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7767 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7768 | |
7769 | /* compute bitmask from p1 value */ | |
7770 | if (IS_PINEVIEW(dev)) | |
7771 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7772 | else { | |
7773 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7774 | if (IS_G4X(dev) && reduced_clock) | |
7775 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7776 | } | |
7777 | switch (clock->p2) { | |
7778 | case 5: | |
7779 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7780 | break; | |
7781 | case 7: | |
7782 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7783 | break; | |
7784 | case 10: | |
7785 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7786 | break; | |
7787 | case 14: | |
7788 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7789 | break; | |
7790 | } | |
7791 | if (INTEL_INFO(dev)->gen >= 4) | |
7792 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7793 | ||
190f68c5 | 7794 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7795 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7796 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7797 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7798 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7799 | else | |
7800 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7801 | ||
7802 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7803 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7804 | |
eb1cbe48 | 7805 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7806 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7807 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7808 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7809 | } |
7810 | } | |
7811 | ||
251ac862 DV |
7812 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7813 | struct intel_crtc_state *crtc_state, | |
7814 | intel_clock_t *reduced_clock, | |
7815 | int num_connectors) | |
eb1cbe48 | 7816 | { |
f47709a9 | 7817 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7818 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7819 | u32 dpll; |
190f68c5 | 7820 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7821 | |
190f68c5 | 7822 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7823 | |
eb1cbe48 DV |
7824 | dpll = DPLL_VGA_MODE_DIS; |
7825 | ||
a93e255f | 7826 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7827 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7828 | } else { | |
7829 | if (clock->p1 == 2) | |
7830 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7831 | else | |
7832 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7833 | if (clock->p2 == 4) | |
7834 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7835 | } | |
7836 | ||
a93e255f | 7837 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7838 | dpll |= DPLL_DVO_2X_MODE; |
7839 | ||
a93e255f | 7840 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7841 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7842 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7843 | else | |
7844 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7845 | ||
7846 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7847 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7848 | } |
7849 | ||
8a654f3b | 7850 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7851 | { |
7852 | struct drm_device *dev = intel_crtc->base.dev; | |
7853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7854 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7855 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7856 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7857 | uint32_t crtc_vtotal, crtc_vblank_end; |
7858 | int vsyncshift = 0; | |
4d8a62ea DV |
7859 | |
7860 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7861 | * the hw state checker will get angry at the mismatch. */ | |
7862 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7863 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7864 | |
609aeaca | 7865 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7866 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7867 | crtc_vtotal -= 1; |
7868 | crtc_vblank_end -= 1; | |
609aeaca | 7869 | |
409ee761 | 7870 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7871 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7872 | else | |
7873 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7874 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7875 | if (vsyncshift < 0) |
7876 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7877 | } |
7878 | ||
7879 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7880 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7881 | |
fe2b8f9d | 7882 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7883 | (adjusted_mode->crtc_hdisplay - 1) | |
7884 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7885 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7886 | (adjusted_mode->crtc_hblank_start - 1) | |
7887 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7888 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7889 | (adjusted_mode->crtc_hsync_start - 1) | |
7890 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7891 | ||
fe2b8f9d | 7892 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7893 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7894 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7895 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7896 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7897 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7898 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7899 | (adjusted_mode->crtc_vsync_start - 1) | |
7900 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7901 | ||
b5e508d4 PZ |
7902 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7903 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7904 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7905 | * bits. */ | |
7906 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7907 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7908 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7909 | ||
b0e77b9c PZ |
7910 | /* pipesrc controls the size that is scaled from, which should |
7911 | * always be the user's requested size. | |
7912 | */ | |
7913 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7914 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7915 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7916 | } |
7917 | ||
1bd1bd80 | 7918 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7919 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7920 | { |
7921 | struct drm_device *dev = crtc->base.dev; | |
7922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7923 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7924 | uint32_t tmp; | |
7925 | ||
7926 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7927 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7928 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7929 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7930 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7931 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7932 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7933 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7934 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7935 | |
7936 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7937 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7938 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7939 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7940 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7941 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7942 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7943 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7944 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7945 | |
7946 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7947 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7948 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7949 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7950 | } |
7951 | ||
7952 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7953 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7954 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7955 | ||
2d112de7 ACO |
7956 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7957 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7958 | } |
7959 | ||
f6a83288 | 7960 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7961 | struct intel_crtc_state *pipe_config) |
babea61d | 7962 | { |
2d112de7 ACO |
7963 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7964 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7965 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7966 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7967 | |
2d112de7 ACO |
7968 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7969 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7970 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7971 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7972 | |
2d112de7 | 7973 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7974 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7975 | |
2d112de7 ACO |
7976 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7977 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7978 | |
7979 | mode->hsync = drm_mode_hsync(mode); | |
7980 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7981 | drm_mode_set_name(mode); | |
babea61d JB |
7982 | } |
7983 | ||
84b046f3 DV |
7984 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7985 | { | |
7986 | struct drm_device *dev = intel_crtc->base.dev; | |
7987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7988 | uint32_t pipeconf; | |
7989 | ||
9f11a9e4 | 7990 | pipeconf = 0; |
84b046f3 | 7991 | |
b6b5d049 VS |
7992 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7993 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7994 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7995 | |
6e3c9717 | 7996 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7997 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7998 | |
ff9ce46e | 7999 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 8000 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 8001 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8002 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8003 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8004 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8005 | |
6e3c9717 | 8006 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8007 | case 18: |
8008 | pipeconf |= PIPECONF_6BPC; | |
8009 | break; | |
8010 | case 24: | |
8011 | pipeconf |= PIPECONF_8BPC; | |
8012 | break; | |
8013 | case 30: | |
8014 | pipeconf |= PIPECONF_10BPC; | |
8015 | break; | |
8016 | default: | |
8017 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8018 | BUG(); | |
84b046f3 DV |
8019 | } |
8020 | } | |
8021 | ||
8022 | if (HAS_PIPE_CXSR(dev)) { | |
8023 | if (intel_crtc->lowfreq_avail) { | |
8024 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8025 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8026 | } else { | |
8027 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8028 | } |
8029 | } | |
8030 | ||
6e3c9717 | 8031 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8032 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 8033 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8034 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8035 | else | |
8036 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8037 | } else | |
84b046f3 DV |
8038 | pipeconf |= PIPECONF_PROGRESSIVE; |
8039 | ||
666a4537 WB |
8040 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8041 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 8042 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8043 | |
84b046f3 DV |
8044 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8045 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8046 | } | |
8047 | ||
190f68c5 ACO |
8048 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8049 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8050 | { |
c7653199 | 8051 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8052 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 8053 | int refclk, num_connectors = 0; |
c329a4ec DV |
8054 | intel_clock_t clock; |
8055 | bool ok; | |
d4906093 | 8056 | const intel_limit_t *limit; |
55bb9992 | 8057 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8058 | struct drm_connector *connector; |
55bb9992 ACO |
8059 | struct drm_connector_state *connector_state; |
8060 | int i; | |
79e53945 | 8061 | |
dd3cd74a ACO |
8062 | memset(&crtc_state->dpll_hw_state, 0, |
8063 | sizeof(crtc_state->dpll_hw_state)); | |
8064 | ||
a65347ba JN |
8065 | if (crtc_state->has_dsi_encoder) |
8066 | return 0; | |
43565a06 | 8067 | |
a65347ba JN |
8068 | for_each_connector_in_state(state, connector, connector_state, i) { |
8069 | if (connector_state->crtc == &crtc->base) | |
8070 | num_connectors++; | |
79e53945 JB |
8071 | } |
8072 | ||
190f68c5 | 8073 | if (!crtc_state->clock_set) { |
a93e255f | 8074 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 8075 | |
e9fd1c02 JN |
8076 | /* |
8077 | * Returns a set of divisors for the desired target clock with | |
8078 | * the given refclk, or FALSE. The returned values represent | |
8079 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
8080 | * 2) / p1 / p2. | |
8081 | */ | |
a93e255f ACO |
8082 | limit = intel_limit(crtc_state, refclk); |
8083 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8084 | crtc_state->port_clock, |
e9fd1c02 | 8085 | refclk, NULL, &clock); |
f2335330 | 8086 | if (!ok) { |
e9fd1c02 JN |
8087 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8088 | return -EINVAL; | |
8089 | } | |
79e53945 | 8090 | |
f2335330 | 8091 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8092 | crtc_state->dpll.n = clock.n; |
8093 | crtc_state->dpll.m1 = clock.m1; | |
8094 | crtc_state->dpll.m2 = clock.m2; | |
8095 | crtc_state->dpll.p1 = clock.p1; | |
8096 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8097 | } |
7026d4ac | 8098 | |
e9fd1c02 | 8099 | if (IS_GEN2(dev)) { |
c329a4ec | 8100 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8101 | num_connectors); |
9d556c99 | 8102 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8103 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8104 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8105 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8106 | } else { |
c329a4ec | 8107 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8108 | num_connectors); |
e9fd1c02 | 8109 | } |
79e53945 | 8110 | |
c8f7a0db | 8111 | return 0; |
f564048e EA |
8112 | } |
8113 | ||
2fa2fe9a | 8114 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8115 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8116 | { |
8117 | struct drm_device *dev = crtc->base.dev; | |
8118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8119 | uint32_t tmp; | |
8120 | ||
dc9e7dec VS |
8121 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8122 | return; | |
8123 | ||
2fa2fe9a | 8124 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8125 | if (!(tmp & PFIT_ENABLE)) |
8126 | return; | |
2fa2fe9a | 8127 | |
06922821 | 8128 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8129 | if (INTEL_INFO(dev)->gen < 4) { |
8130 | if (crtc->pipe != PIPE_B) | |
8131 | return; | |
2fa2fe9a DV |
8132 | } else { |
8133 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8134 | return; | |
8135 | } | |
8136 | ||
06922821 | 8137 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8138 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8139 | if (INTEL_INFO(dev)->gen < 5) | |
8140 | pipe_config->gmch_pfit.lvds_border_bits = | |
8141 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8142 | } | |
8143 | ||
acbec814 | 8144 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8145 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8146 | { |
8147 | struct drm_device *dev = crtc->base.dev; | |
8148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8149 | int pipe = pipe_config->cpu_transcoder; | |
8150 | intel_clock_t clock; | |
8151 | u32 mdiv; | |
662c6ecb | 8152 | int refclk = 100000; |
acbec814 | 8153 | |
f573de5a SK |
8154 | /* In case of MIPI DPLL will not even be used */ |
8155 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8156 | return; | |
8157 | ||
a580516d | 8158 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8159 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8160 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8161 | |
8162 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8163 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8164 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8165 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8166 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8167 | ||
dccbea3b | 8168 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8169 | } |
8170 | ||
5724dbd1 DL |
8171 | static void |
8172 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8173 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8174 | { |
8175 | struct drm_device *dev = crtc->base.dev; | |
8176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8177 | u32 val, base, offset; | |
8178 | int pipe = crtc->pipe, plane = crtc->plane; | |
8179 | int fourcc, pixel_format; | |
6761dd31 | 8180 | unsigned int aligned_height; |
b113d5ee | 8181 | struct drm_framebuffer *fb; |
1b842c89 | 8182 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8183 | |
42a7b088 DL |
8184 | val = I915_READ(DSPCNTR(plane)); |
8185 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8186 | return; | |
8187 | ||
d9806c9f | 8188 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8189 | if (!intel_fb) { |
1ad292b5 JB |
8190 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8191 | return; | |
8192 | } | |
8193 | ||
1b842c89 DL |
8194 | fb = &intel_fb->base; |
8195 | ||
18c5247e DV |
8196 | if (INTEL_INFO(dev)->gen >= 4) { |
8197 | if (val & DISPPLANE_TILED) { | |
49af449b | 8198 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8199 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8200 | } | |
8201 | } | |
1ad292b5 JB |
8202 | |
8203 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8204 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8205 | fb->pixel_format = fourcc; |
8206 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8207 | |
8208 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8209 | if (plane_config->tiling) |
1ad292b5 JB |
8210 | offset = I915_READ(DSPTILEOFF(plane)); |
8211 | else | |
8212 | offset = I915_READ(DSPLINOFF(plane)); | |
8213 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8214 | } else { | |
8215 | base = I915_READ(DSPADDR(plane)); | |
8216 | } | |
8217 | plane_config->base = base; | |
8218 | ||
8219 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8220 | fb->width = ((val >> 16) & 0xfff) + 1; |
8221 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8222 | |
8223 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8224 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8225 | |
b113d5ee | 8226 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8227 | fb->pixel_format, |
8228 | fb->modifier[0]); | |
1ad292b5 | 8229 | |
f37b5c2b | 8230 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8231 | |
2844a921 DL |
8232 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8233 | pipe_name(pipe), plane, fb->width, fb->height, | |
8234 | fb->bits_per_pixel, base, fb->pitches[0], | |
8235 | plane_config->size); | |
1ad292b5 | 8236 | |
2d14030b | 8237 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8238 | } |
8239 | ||
70b23a98 | 8240 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8241 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8242 | { |
8243 | struct drm_device *dev = crtc->base.dev; | |
8244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8245 | int pipe = pipe_config->cpu_transcoder; | |
8246 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8247 | intel_clock_t clock; | |
0d7b6b11 | 8248 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8249 | int refclk = 100000; |
8250 | ||
a580516d | 8251 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8252 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8253 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8254 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8255 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8256 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8257 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8258 | |
8259 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8260 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8261 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8262 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8263 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8264 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8265 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8266 | ||
dccbea3b | 8267 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8268 | } |
8269 | ||
0e8ffe1b | 8270 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8271 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8272 | { |
8273 | struct drm_device *dev = crtc->base.dev; | |
8274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8275 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8276 | uint32_t tmp; |
1729050e | 8277 | bool ret; |
0e8ffe1b | 8278 | |
1729050e ID |
8279 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8280 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8281 | return false; |
8282 | ||
e143a21c | 8283 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8284 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8285 | |
1729050e ID |
8286 | ret = false; |
8287 | ||
0e8ffe1b DV |
8288 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8289 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8290 | goto out; |
0e8ffe1b | 8291 | |
666a4537 | 8292 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8293 | switch (tmp & PIPECONF_BPC_MASK) { |
8294 | case PIPECONF_6BPC: | |
8295 | pipe_config->pipe_bpp = 18; | |
8296 | break; | |
8297 | case PIPECONF_8BPC: | |
8298 | pipe_config->pipe_bpp = 24; | |
8299 | break; | |
8300 | case PIPECONF_10BPC: | |
8301 | pipe_config->pipe_bpp = 30; | |
8302 | break; | |
8303 | default: | |
8304 | break; | |
8305 | } | |
8306 | } | |
8307 | ||
666a4537 WB |
8308 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8309 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8310 | pipe_config->limited_color_range = true; |
8311 | ||
282740f7 VS |
8312 | if (INTEL_INFO(dev)->gen < 4) |
8313 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8314 | ||
1bd1bd80 DV |
8315 | intel_get_pipe_timings(crtc, pipe_config); |
8316 | ||
2fa2fe9a DV |
8317 | i9xx_get_pfit_config(crtc, pipe_config); |
8318 | ||
6c49f241 DV |
8319 | if (INTEL_INFO(dev)->gen >= 4) { |
8320 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8321 | pipe_config->pixel_multiplier = | |
8322 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8323 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8324 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8325 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8326 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8327 | pipe_config->pixel_multiplier = | |
8328 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8329 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8330 | } else { | |
8331 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8332 | * port and will be fixed up in the encoder->get_config | |
8333 | * function. */ | |
8334 | pipe_config->pixel_multiplier = 1; | |
8335 | } | |
8bcc2795 | 8336 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8337 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8338 | /* |
8339 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8340 | * on 830. Filter it out here so that we don't | |
8341 | * report errors due to that. | |
8342 | */ | |
8343 | if (IS_I830(dev)) | |
8344 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8345 | ||
8bcc2795 DV |
8346 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8347 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8348 | } else { |
8349 | /* Mask out read-only status bits. */ | |
8350 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8351 | DPLL_PORTC_READY_MASK | | |
8352 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8353 | } |
6c49f241 | 8354 | |
70b23a98 VS |
8355 | if (IS_CHERRYVIEW(dev)) |
8356 | chv_crtc_clock_get(crtc, pipe_config); | |
8357 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8358 | vlv_crtc_clock_get(crtc, pipe_config); |
8359 | else | |
8360 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8361 | |
0f64614d VS |
8362 | /* |
8363 | * Normally the dotclock is filled in by the encoder .get_config() | |
8364 | * but in case the pipe is enabled w/o any ports we need a sane | |
8365 | * default. | |
8366 | */ | |
8367 | pipe_config->base.adjusted_mode.crtc_clock = | |
8368 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8369 | ||
1729050e ID |
8370 | ret = true; |
8371 | ||
8372 | out: | |
8373 | intel_display_power_put(dev_priv, power_domain); | |
8374 | ||
8375 | return ret; | |
0e8ffe1b DV |
8376 | } |
8377 | ||
dde86e2d | 8378 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8379 | { |
8380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8381 | struct intel_encoder *encoder; |
74cfd7ac | 8382 | u32 val, final; |
13d83a67 | 8383 | bool has_lvds = false; |
199e5d79 | 8384 | bool has_cpu_edp = false; |
199e5d79 | 8385 | bool has_panel = false; |
99eb6a01 KP |
8386 | bool has_ck505 = false; |
8387 | bool can_ssc = false; | |
13d83a67 JB |
8388 | |
8389 | /* We need to take the global config into account */ | |
b2784e15 | 8390 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8391 | switch (encoder->type) { |
8392 | case INTEL_OUTPUT_LVDS: | |
8393 | has_panel = true; | |
8394 | has_lvds = true; | |
8395 | break; | |
8396 | case INTEL_OUTPUT_EDP: | |
8397 | has_panel = true; | |
2de6905f | 8398 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8399 | has_cpu_edp = true; |
8400 | break; | |
6847d71b PZ |
8401 | default: |
8402 | break; | |
13d83a67 JB |
8403 | } |
8404 | } | |
8405 | ||
99eb6a01 | 8406 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8407 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8408 | can_ssc = has_ck505; |
8409 | } else { | |
8410 | has_ck505 = false; | |
8411 | can_ssc = true; | |
8412 | } | |
8413 | ||
2de6905f ID |
8414 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8415 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8416 | |
8417 | /* Ironlake: try to setup display ref clock before DPLL | |
8418 | * enabling. This is only under driver's control after | |
8419 | * PCH B stepping, previous chipset stepping should be | |
8420 | * ignoring this setting. | |
8421 | */ | |
74cfd7ac CW |
8422 | val = I915_READ(PCH_DREF_CONTROL); |
8423 | ||
8424 | /* As we must carefully and slowly disable/enable each source in turn, | |
8425 | * compute the final state we want first and check if we need to | |
8426 | * make any changes at all. | |
8427 | */ | |
8428 | final = val; | |
8429 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8430 | if (has_ck505) | |
8431 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8432 | else | |
8433 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8434 | ||
8435 | final &= ~DREF_SSC_SOURCE_MASK; | |
8436 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8437 | final &= ~DREF_SSC1_ENABLE; | |
8438 | ||
8439 | if (has_panel) { | |
8440 | final |= DREF_SSC_SOURCE_ENABLE; | |
8441 | ||
8442 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8443 | final |= DREF_SSC1_ENABLE; | |
8444 | ||
8445 | if (has_cpu_edp) { | |
8446 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8447 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8448 | else | |
8449 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8450 | } else | |
8451 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8452 | } else { | |
8453 | final |= DREF_SSC_SOURCE_DISABLE; | |
8454 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8455 | } | |
8456 | ||
8457 | if (final == val) | |
8458 | return; | |
8459 | ||
13d83a67 | 8460 | /* Always enable nonspread source */ |
74cfd7ac | 8461 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8462 | |
99eb6a01 | 8463 | if (has_ck505) |
74cfd7ac | 8464 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8465 | else |
74cfd7ac | 8466 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8467 | |
199e5d79 | 8468 | if (has_panel) { |
74cfd7ac CW |
8469 | val &= ~DREF_SSC_SOURCE_MASK; |
8470 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8471 | |
199e5d79 | 8472 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8473 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8474 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8475 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8476 | } else |
74cfd7ac | 8477 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8478 | |
8479 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8480 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8481 | POSTING_READ(PCH_DREF_CONTROL); |
8482 | udelay(200); | |
8483 | ||
74cfd7ac | 8484 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8485 | |
8486 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8487 | if (has_cpu_edp) { |
99eb6a01 | 8488 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8489 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8490 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8491 | } else |
74cfd7ac | 8492 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8493 | } else |
74cfd7ac | 8494 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8495 | |
74cfd7ac | 8496 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8497 | POSTING_READ(PCH_DREF_CONTROL); |
8498 | udelay(200); | |
8499 | } else { | |
8500 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8501 | ||
74cfd7ac | 8502 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8503 | |
8504 | /* Turn off CPU output */ | |
74cfd7ac | 8505 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8506 | |
74cfd7ac | 8507 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8508 | POSTING_READ(PCH_DREF_CONTROL); |
8509 | udelay(200); | |
8510 | ||
8511 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8512 | val &= ~DREF_SSC_SOURCE_MASK; |
8513 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8514 | |
8515 | /* Turn off SSC1 */ | |
74cfd7ac | 8516 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8517 | |
74cfd7ac | 8518 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8519 | POSTING_READ(PCH_DREF_CONTROL); |
8520 | udelay(200); | |
8521 | } | |
74cfd7ac CW |
8522 | |
8523 | BUG_ON(val != final); | |
13d83a67 JB |
8524 | } |
8525 | ||
f31f2d55 | 8526 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8527 | { |
f31f2d55 | 8528 | uint32_t tmp; |
dde86e2d | 8529 | |
0ff066a9 PZ |
8530 | tmp = I915_READ(SOUTH_CHICKEN2); |
8531 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8532 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8533 | |
0ff066a9 PZ |
8534 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8535 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8536 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8537 | |
0ff066a9 PZ |
8538 | tmp = I915_READ(SOUTH_CHICKEN2); |
8539 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8540 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8541 | |
0ff066a9 PZ |
8542 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8543 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8544 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8545 | } |
8546 | ||
8547 | /* WaMPhyProgramming:hsw */ | |
8548 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8549 | { | |
8550 | uint32_t tmp; | |
dde86e2d PZ |
8551 | |
8552 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8553 | tmp &= ~(0xFF << 24); | |
8554 | tmp |= (0x12 << 24); | |
8555 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8556 | ||
dde86e2d PZ |
8557 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8558 | tmp |= (1 << 11); | |
8559 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8560 | ||
8561 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8562 | tmp |= (1 << 11); | |
8563 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8564 | ||
dde86e2d PZ |
8565 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8566 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8567 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8568 | ||
8569 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8570 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8571 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8572 | ||
0ff066a9 PZ |
8573 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8574 | tmp &= ~(7 << 13); | |
8575 | tmp |= (5 << 13); | |
8576 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8577 | |
0ff066a9 PZ |
8578 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8579 | tmp &= ~(7 << 13); | |
8580 | tmp |= (5 << 13); | |
8581 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8582 | |
8583 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8584 | tmp &= ~0xFF; | |
8585 | tmp |= 0x1C; | |
8586 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8587 | ||
8588 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8589 | tmp &= ~0xFF; | |
8590 | tmp |= 0x1C; | |
8591 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8592 | ||
8593 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8594 | tmp &= ~(0xFF << 16); | |
8595 | tmp |= (0x1C << 16); | |
8596 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8597 | ||
8598 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8599 | tmp &= ~(0xFF << 16); | |
8600 | tmp |= (0x1C << 16); | |
8601 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8602 | ||
0ff066a9 PZ |
8603 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8604 | tmp |= (1 << 27); | |
8605 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8606 | |
0ff066a9 PZ |
8607 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8608 | tmp |= (1 << 27); | |
8609 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8610 | |
0ff066a9 PZ |
8611 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8612 | tmp &= ~(0xF << 28); | |
8613 | tmp |= (4 << 28); | |
8614 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8615 | |
0ff066a9 PZ |
8616 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8617 | tmp &= ~(0xF << 28); | |
8618 | tmp |= (4 << 28); | |
8619 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8620 | } |
8621 | ||
2fa86a1f PZ |
8622 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8623 | * Programming" based on the parameters passed: | |
8624 | * - Sequence to enable CLKOUT_DP | |
8625 | * - Sequence to enable CLKOUT_DP without spread | |
8626 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8627 | */ | |
8628 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8629 | bool with_fdi) | |
f31f2d55 PZ |
8630 | { |
8631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8632 | uint32_t reg, tmp; |
8633 | ||
8634 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8635 | with_spread = true; | |
c2699524 | 8636 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8637 | with_fdi = false; |
f31f2d55 | 8638 | |
a580516d | 8639 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8640 | |
8641 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8642 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8643 | tmp |= SBI_SSCCTL_PATHALT; | |
8644 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8645 | ||
8646 | udelay(24); | |
8647 | ||
2fa86a1f PZ |
8648 | if (with_spread) { |
8649 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8650 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8651 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8652 | |
2fa86a1f PZ |
8653 | if (with_fdi) { |
8654 | lpt_reset_fdi_mphy(dev_priv); | |
8655 | lpt_program_fdi_mphy(dev_priv); | |
8656 | } | |
8657 | } | |
dde86e2d | 8658 | |
c2699524 | 8659 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8660 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8661 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8662 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8663 | |
a580516d | 8664 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8665 | } |
8666 | ||
47701c3b PZ |
8667 | /* Sequence to disable CLKOUT_DP */ |
8668 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8669 | { | |
8670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8671 | uint32_t reg, tmp; | |
8672 | ||
a580516d | 8673 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8674 | |
c2699524 | 8675 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8676 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8677 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8678 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8679 | ||
8680 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8681 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8682 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8683 | tmp |= SBI_SSCCTL_PATHALT; | |
8684 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8685 | udelay(32); | |
8686 | } | |
8687 | tmp |= SBI_SSCCTL_DISABLE; | |
8688 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8689 | } | |
8690 | ||
a580516d | 8691 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8692 | } |
8693 | ||
f7be2c21 VS |
8694 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8695 | ||
8696 | static const uint16_t sscdivintphase[] = { | |
8697 | [BEND_IDX( 50)] = 0x3B23, | |
8698 | [BEND_IDX( 45)] = 0x3B23, | |
8699 | [BEND_IDX( 40)] = 0x3C23, | |
8700 | [BEND_IDX( 35)] = 0x3C23, | |
8701 | [BEND_IDX( 30)] = 0x3D23, | |
8702 | [BEND_IDX( 25)] = 0x3D23, | |
8703 | [BEND_IDX( 20)] = 0x3E23, | |
8704 | [BEND_IDX( 15)] = 0x3E23, | |
8705 | [BEND_IDX( 10)] = 0x3F23, | |
8706 | [BEND_IDX( 5)] = 0x3F23, | |
8707 | [BEND_IDX( 0)] = 0x0025, | |
8708 | [BEND_IDX( -5)] = 0x0025, | |
8709 | [BEND_IDX(-10)] = 0x0125, | |
8710 | [BEND_IDX(-15)] = 0x0125, | |
8711 | [BEND_IDX(-20)] = 0x0225, | |
8712 | [BEND_IDX(-25)] = 0x0225, | |
8713 | [BEND_IDX(-30)] = 0x0325, | |
8714 | [BEND_IDX(-35)] = 0x0325, | |
8715 | [BEND_IDX(-40)] = 0x0425, | |
8716 | [BEND_IDX(-45)] = 0x0425, | |
8717 | [BEND_IDX(-50)] = 0x0525, | |
8718 | }; | |
8719 | ||
8720 | /* | |
8721 | * Bend CLKOUT_DP | |
8722 | * steps -50 to 50 inclusive, in steps of 5 | |
8723 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8724 | * change in clock period = -(steps / 10) * 5.787 ps | |
8725 | */ | |
8726 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8727 | { | |
8728 | uint32_t tmp; | |
8729 | int idx = BEND_IDX(steps); | |
8730 | ||
8731 | if (WARN_ON(steps % 5 != 0)) | |
8732 | return; | |
8733 | ||
8734 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8735 | return; | |
8736 | ||
8737 | mutex_lock(&dev_priv->sb_lock); | |
8738 | ||
8739 | if (steps % 10 != 0) | |
8740 | tmp = 0xAAAAAAAB; | |
8741 | else | |
8742 | tmp = 0x00000000; | |
8743 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8744 | ||
8745 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8746 | tmp &= 0xffff0000; | |
8747 | tmp |= sscdivintphase[idx]; | |
8748 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8749 | ||
8750 | mutex_unlock(&dev_priv->sb_lock); | |
8751 | } | |
8752 | ||
8753 | #undef BEND_IDX | |
8754 | ||
bf8fa3d3 PZ |
8755 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8756 | { | |
bf8fa3d3 PZ |
8757 | struct intel_encoder *encoder; |
8758 | bool has_vga = false; | |
8759 | ||
b2784e15 | 8760 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8761 | switch (encoder->type) { |
8762 | case INTEL_OUTPUT_ANALOG: | |
8763 | has_vga = true; | |
8764 | break; | |
6847d71b PZ |
8765 | default: |
8766 | break; | |
bf8fa3d3 PZ |
8767 | } |
8768 | } | |
8769 | ||
f7be2c21 VS |
8770 | if (has_vga) { |
8771 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8772 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8773 | } else { |
47701c3b | 8774 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8775 | } |
bf8fa3d3 PZ |
8776 | } |
8777 | ||
dde86e2d PZ |
8778 | /* |
8779 | * Initialize reference clocks when the driver loads | |
8780 | */ | |
8781 | void intel_init_pch_refclk(struct drm_device *dev) | |
8782 | { | |
8783 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8784 | ironlake_init_pch_refclk(dev); | |
8785 | else if (HAS_PCH_LPT(dev)) | |
8786 | lpt_init_pch_refclk(dev); | |
8787 | } | |
8788 | ||
55bb9992 | 8789 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8790 | { |
55bb9992 | 8791 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8792 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8793 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8794 | struct drm_connector *connector; |
55bb9992 | 8795 | struct drm_connector_state *connector_state; |
d9d444cb | 8796 | struct intel_encoder *encoder; |
55bb9992 | 8797 | int num_connectors = 0, i; |
d9d444cb JB |
8798 | bool is_lvds = false; |
8799 | ||
da3ced29 | 8800 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8801 | if (connector_state->crtc != crtc_state->base.crtc) |
8802 | continue; | |
8803 | ||
8804 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8805 | ||
d9d444cb JB |
8806 | switch (encoder->type) { |
8807 | case INTEL_OUTPUT_LVDS: | |
8808 | is_lvds = true; | |
8809 | break; | |
6847d71b PZ |
8810 | default: |
8811 | break; | |
d9d444cb JB |
8812 | } |
8813 | num_connectors++; | |
8814 | } | |
8815 | ||
8816 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8817 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8818 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8819 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8820 | } |
8821 | ||
8822 | return 120000; | |
8823 | } | |
8824 | ||
6ff93609 | 8825 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8826 | { |
c8203565 | 8827 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8829 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8830 | uint32_t val; |
8831 | ||
78114071 | 8832 | val = 0; |
c8203565 | 8833 | |
6e3c9717 | 8834 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8835 | case 18: |
dfd07d72 | 8836 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8837 | break; |
8838 | case 24: | |
dfd07d72 | 8839 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8840 | break; |
8841 | case 30: | |
dfd07d72 | 8842 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8843 | break; |
8844 | case 36: | |
dfd07d72 | 8845 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8846 | break; |
8847 | default: | |
cc769b62 PZ |
8848 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8849 | BUG(); | |
c8203565 PZ |
8850 | } |
8851 | ||
6e3c9717 | 8852 | if (intel_crtc->config->dither) |
c8203565 PZ |
8853 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8854 | ||
6e3c9717 | 8855 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8856 | val |= PIPECONF_INTERLACED_ILK; |
8857 | else | |
8858 | val |= PIPECONF_PROGRESSIVE; | |
8859 | ||
6e3c9717 | 8860 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8861 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8862 | |
c8203565 PZ |
8863 | I915_WRITE(PIPECONF(pipe), val); |
8864 | POSTING_READ(PIPECONF(pipe)); | |
8865 | } | |
8866 | ||
86d3efce VS |
8867 | /* |
8868 | * Set up the pipe CSC unit. | |
8869 | * | |
8870 | * Currently only full range RGB to limited range RGB conversion | |
8871 | * is supported, but eventually this should handle various | |
8872 | * RGB<->YCbCr scenarios as well. | |
8873 | */ | |
50f3b016 | 8874 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8875 | { |
8876 | struct drm_device *dev = crtc->dev; | |
8877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8879 | int pipe = intel_crtc->pipe; | |
8880 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8881 | ||
8882 | /* | |
8883 | * TODO: Check what kind of values actually come out of the pipe | |
8884 | * with these coeff/postoff values and adjust to get the best | |
8885 | * accuracy. Perhaps we even need to take the bpc value into | |
8886 | * consideration. | |
8887 | */ | |
8888 | ||
6e3c9717 | 8889 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8890 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8891 | ||
8892 | /* | |
8893 | * GY/GU and RY/RU should be the other way around according | |
8894 | * to BSpec, but reality doesn't agree. Just set them up in | |
8895 | * a way that results in the correct picture. | |
8896 | */ | |
8897 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8898 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8899 | ||
8900 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8901 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8902 | ||
8903 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8904 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8905 | ||
8906 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8907 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8908 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8909 | ||
8910 | if (INTEL_INFO(dev)->gen > 6) { | |
8911 | uint16_t postoff = 0; | |
8912 | ||
6e3c9717 | 8913 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8914 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8915 | |
8916 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8917 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8918 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8919 | ||
8920 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8921 | } else { | |
8922 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8923 | ||
6e3c9717 | 8924 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8925 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8926 | ||
8927 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8928 | } | |
8929 | } | |
8930 | ||
6ff93609 | 8931 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8932 | { |
756f85cf PZ |
8933 | struct drm_device *dev = crtc->dev; |
8934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8936 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8937 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8938 | uint32_t val; |
8939 | ||
3eff4faa | 8940 | val = 0; |
ee2b0b38 | 8941 | |
6e3c9717 | 8942 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8943 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8944 | ||
6e3c9717 | 8945 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8946 | val |= PIPECONF_INTERLACED_ILK; |
8947 | else | |
8948 | val |= PIPECONF_PROGRESSIVE; | |
8949 | ||
702e7a56 PZ |
8950 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8951 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8952 | |
8953 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8954 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8955 | |
3cdf122c | 8956 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8957 | val = 0; |
8958 | ||
6e3c9717 | 8959 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8960 | case 18: |
8961 | val |= PIPEMISC_DITHER_6_BPC; | |
8962 | break; | |
8963 | case 24: | |
8964 | val |= PIPEMISC_DITHER_8_BPC; | |
8965 | break; | |
8966 | case 30: | |
8967 | val |= PIPEMISC_DITHER_10_BPC; | |
8968 | break; | |
8969 | case 36: | |
8970 | val |= PIPEMISC_DITHER_12_BPC; | |
8971 | break; | |
8972 | default: | |
8973 | /* Case prevented by pipe_config_set_bpp. */ | |
8974 | BUG(); | |
8975 | } | |
8976 | ||
6e3c9717 | 8977 | if (intel_crtc->config->dither) |
756f85cf PZ |
8978 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8979 | ||
8980 | I915_WRITE(PIPEMISC(pipe), val); | |
8981 | } | |
ee2b0b38 PZ |
8982 | } |
8983 | ||
6591c6e4 | 8984 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8985 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8986 | intel_clock_t *clock, |
8987 | bool *has_reduced_clock, | |
8988 | intel_clock_t *reduced_clock) | |
8989 | { | |
8990 | struct drm_device *dev = crtc->dev; | |
8991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8992 | int refclk; |
d4906093 | 8993 | const intel_limit_t *limit; |
c329a4ec | 8994 | bool ret; |
79e53945 | 8995 | |
55bb9992 | 8996 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8997 | |
d4906093 ML |
8998 | /* |
8999 | * Returns a set of divisors for the desired target clock with the given | |
9000 | * refclk, or FALSE. The returned values represent the clock equation: | |
9001 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
9002 | */ | |
a93e255f ACO |
9003 | limit = intel_limit(crtc_state, refclk); |
9004 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 9005 | crtc_state->port_clock, |
ee9300bb | 9006 | refclk, NULL, clock); |
6591c6e4 PZ |
9007 | if (!ret) |
9008 | return false; | |
cda4b7d3 | 9009 | |
6591c6e4 PZ |
9010 | return true; |
9011 | } | |
9012 | ||
d4b1931c PZ |
9013 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9014 | { | |
9015 | /* | |
9016 | * Account for spread spectrum to avoid | |
9017 | * oversubscribing the link. Max center spread | |
9018 | * is 2.5%; use 5% for safety's sake. | |
9019 | */ | |
9020 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9021 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9022 | } |
9023 | ||
7429e9d4 | 9024 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9025 | { |
7429e9d4 | 9026 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9027 | } |
9028 | ||
de13a2e3 | 9029 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 9030 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 9031 | u32 *fp, |
9a7c7890 | 9032 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 9033 | { |
de13a2e3 | 9034 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
9035 | struct drm_device *dev = crtc->dev; |
9036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 9037 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 9038 | struct drm_connector *connector; |
55bb9992 ACO |
9039 | struct drm_connector_state *connector_state; |
9040 | struct intel_encoder *encoder; | |
de13a2e3 | 9041 | uint32_t dpll; |
55bb9992 | 9042 | int factor, num_connectors = 0, i; |
09ede541 | 9043 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 9044 | |
da3ced29 | 9045 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
9046 | if (connector_state->crtc != crtc_state->base.crtc) |
9047 | continue; | |
9048 | ||
9049 | encoder = to_intel_encoder(connector_state->best_encoder); | |
9050 | ||
9051 | switch (encoder->type) { | |
79e53945 JB |
9052 | case INTEL_OUTPUT_LVDS: |
9053 | is_lvds = true; | |
9054 | break; | |
9055 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 9056 | case INTEL_OUTPUT_HDMI: |
79e53945 | 9057 | is_sdvo = true; |
79e53945 | 9058 | break; |
6847d71b PZ |
9059 | default: |
9060 | break; | |
79e53945 | 9061 | } |
43565a06 | 9062 | |
c751ce4f | 9063 | num_connectors++; |
79e53945 | 9064 | } |
79e53945 | 9065 | |
c1858123 | 9066 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
9067 | factor = 21; |
9068 | if (is_lvds) { | |
9069 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 9070 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9071 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9072 | factor = 25; |
190f68c5 | 9073 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9074 | factor = 20; |
c1858123 | 9075 | |
190f68c5 | 9076 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 9077 | *fp |= FP_CB_TUNE; |
2c07245f | 9078 | |
9a7c7890 DV |
9079 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
9080 | *fp2 |= FP_CB_TUNE; | |
9081 | ||
5eddb70b | 9082 | dpll = 0; |
2c07245f | 9083 | |
a07d6787 EA |
9084 | if (is_lvds) |
9085 | dpll |= DPLLB_MODE_LVDS; | |
9086 | else | |
9087 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9088 | |
190f68c5 | 9089 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9090 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
9091 | |
9092 | if (is_sdvo) | |
4a33e48d | 9093 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 9094 | if (crtc_state->has_dp_encoder) |
4a33e48d | 9095 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9096 | |
a07d6787 | 9097 | /* compute bitmask from p1 value */ |
190f68c5 | 9098 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9099 | /* also FPA1 */ |
190f68c5 | 9100 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9101 | |
190f68c5 | 9102 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9103 | case 5: |
9104 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9105 | break; | |
9106 | case 7: | |
9107 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9108 | break; | |
9109 | case 10: | |
9110 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9111 | break; | |
9112 | case 14: | |
9113 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9114 | break; | |
79e53945 JB |
9115 | } |
9116 | ||
b4c09f3b | 9117 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9118 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9119 | else |
9120 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9121 | ||
959e16d6 | 9122 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9123 | } |
9124 | ||
190f68c5 ACO |
9125 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9126 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9127 | { |
c7653199 | 9128 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9129 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9130 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9131 | bool ok, has_reduced_clock = false; |
8b47047b | 9132 | bool is_lvds = false; |
e2b78267 | 9133 | struct intel_shared_dpll *pll; |
de13a2e3 | 9134 | |
dd3cd74a ACO |
9135 | memset(&crtc_state->dpll_hw_state, 0, |
9136 | sizeof(crtc_state->dpll_hw_state)); | |
9137 | ||
7905df29 | 9138 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9139 | |
5dc5298b PZ |
9140 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9141 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9142 | |
190f68c5 | 9143 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9144 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9145 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9146 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9147 | return -EINVAL; | |
79e53945 | 9148 | } |
f47709a9 | 9149 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9150 | if (!crtc_state->clock_set) { |
9151 | crtc_state->dpll.n = clock.n; | |
9152 | crtc_state->dpll.m1 = clock.m1; | |
9153 | crtc_state->dpll.m2 = clock.m2; | |
9154 | crtc_state->dpll.p1 = clock.p1; | |
9155 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9156 | } |
79e53945 | 9157 | |
5dc5298b | 9158 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9159 | if (crtc_state->has_pch_encoder) { |
9160 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9161 | if (has_reduced_clock) |
7429e9d4 | 9162 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9163 | |
190f68c5 | 9164 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9165 | &fp, &reduced_clock, |
9166 | has_reduced_clock ? &fp2 : NULL); | |
9167 | ||
190f68c5 ACO |
9168 | crtc_state->dpll_hw_state.dpll = dpll; |
9169 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9170 | if (has_reduced_clock) |
190f68c5 | 9171 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9172 | else |
190f68c5 | 9173 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9174 | |
190f68c5 | 9175 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9176 | if (pll == NULL) { |
84f44ce7 | 9177 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9178 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9179 | return -EINVAL; |
9180 | } | |
3fb37703 | 9181 | } |
79e53945 | 9182 | |
ab585dea | 9183 | if (is_lvds && has_reduced_clock) |
c7653199 | 9184 | crtc->lowfreq_avail = true; |
bcd644e0 | 9185 | else |
c7653199 | 9186 | crtc->lowfreq_avail = false; |
e2b78267 | 9187 | |
c8f7a0db | 9188 | return 0; |
79e53945 JB |
9189 | } |
9190 | ||
eb14cb74 VS |
9191 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9192 | struct intel_link_m_n *m_n) | |
9193 | { | |
9194 | struct drm_device *dev = crtc->base.dev; | |
9195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9196 | enum pipe pipe = crtc->pipe; | |
9197 | ||
9198 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9199 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9200 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9201 | & ~TU_SIZE_MASK; | |
9202 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9203 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9204 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9205 | } | |
9206 | ||
9207 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9208 | enum transcoder transcoder, | |
b95af8be VK |
9209 | struct intel_link_m_n *m_n, |
9210 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9211 | { |
9212 | struct drm_device *dev = crtc->base.dev; | |
9213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9214 | enum pipe pipe = crtc->pipe; |
72419203 | 9215 | |
eb14cb74 VS |
9216 | if (INTEL_INFO(dev)->gen >= 5) { |
9217 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9218 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9219 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9220 | & ~TU_SIZE_MASK; | |
9221 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9222 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9223 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9224 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9225 | * gen < 8) and if DRRS is supported (to make sure the | |
9226 | * registers are not unnecessarily read). | |
9227 | */ | |
9228 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9229 | crtc->config->has_drrs) { |
b95af8be VK |
9230 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9231 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9232 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9233 | & ~TU_SIZE_MASK; | |
9234 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9235 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9236 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9237 | } | |
eb14cb74 VS |
9238 | } else { |
9239 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9240 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9241 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9242 | & ~TU_SIZE_MASK; | |
9243 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9244 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9245 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9246 | } | |
9247 | } | |
9248 | ||
9249 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9250 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9251 | { |
681a8504 | 9252 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9253 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9254 | else | |
9255 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9256 | &pipe_config->dp_m_n, |
9257 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9258 | } |
72419203 | 9259 | |
eb14cb74 | 9260 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9261 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9262 | { |
9263 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9264 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9265 | } |
9266 | ||
bd2e244f | 9267 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9268 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9269 | { |
9270 | struct drm_device *dev = crtc->base.dev; | |
9271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9272 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9273 | uint32_t ps_ctrl = 0; | |
9274 | int id = -1; | |
9275 | int i; | |
bd2e244f | 9276 | |
a1b2278e CK |
9277 | /* find scaler attached to this pipe */ |
9278 | for (i = 0; i < crtc->num_scalers; i++) { | |
9279 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9280 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9281 | id = i; | |
9282 | pipe_config->pch_pfit.enabled = true; | |
9283 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9284 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9285 | break; | |
9286 | } | |
9287 | } | |
bd2e244f | 9288 | |
a1b2278e CK |
9289 | scaler_state->scaler_id = id; |
9290 | if (id >= 0) { | |
9291 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9292 | } else { | |
9293 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9294 | } |
9295 | } | |
9296 | ||
5724dbd1 DL |
9297 | static void |
9298 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9299 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9300 | { |
9301 | struct drm_device *dev = crtc->base.dev; | |
9302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9303 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9304 | int pipe = crtc->pipe; |
9305 | int fourcc, pixel_format; | |
6761dd31 | 9306 | unsigned int aligned_height; |
bc8d7dff | 9307 | struct drm_framebuffer *fb; |
1b842c89 | 9308 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9309 | |
d9806c9f | 9310 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9311 | if (!intel_fb) { |
bc8d7dff DL |
9312 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9313 | return; | |
9314 | } | |
9315 | ||
1b842c89 DL |
9316 | fb = &intel_fb->base; |
9317 | ||
bc8d7dff | 9318 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9319 | if (!(val & PLANE_CTL_ENABLE)) |
9320 | goto error; | |
9321 | ||
bc8d7dff DL |
9322 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9323 | fourcc = skl_format_to_fourcc(pixel_format, | |
9324 | val & PLANE_CTL_ORDER_RGBX, | |
9325 | val & PLANE_CTL_ALPHA_MASK); | |
9326 | fb->pixel_format = fourcc; | |
9327 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9328 | ||
40f46283 DL |
9329 | tiling = val & PLANE_CTL_TILED_MASK; |
9330 | switch (tiling) { | |
9331 | case PLANE_CTL_TILED_LINEAR: | |
9332 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9333 | break; | |
9334 | case PLANE_CTL_TILED_X: | |
9335 | plane_config->tiling = I915_TILING_X; | |
9336 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9337 | break; | |
9338 | case PLANE_CTL_TILED_Y: | |
9339 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9340 | break; | |
9341 | case PLANE_CTL_TILED_YF: | |
9342 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9343 | break; | |
9344 | default: | |
9345 | MISSING_CASE(tiling); | |
9346 | goto error; | |
9347 | } | |
9348 | ||
bc8d7dff DL |
9349 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9350 | plane_config->base = base; | |
9351 | ||
9352 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9353 | ||
9354 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9355 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9356 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9357 | ||
9358 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9359 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9360 | fb->pixel_format); |
bc8d7dff DL |
9361 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9362 | ||
9363 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9364 | fb->pixel_format, |
9365 | fb->modifier[0]); | |
bc8d7dff | 9366 | |
f37b5c2b | 9367 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9368 | |
9369 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9370 | pipe_name(pipe), fb->width, fb->height, | |
9371 | fb->bits_per_pixel, base, fb->pitches[0], | |
9372 | plane_config->size); | |
9373 | ||
2d14030b | 9374 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9375 | return; |
9376 | ||
9377 | error: | |
9378 | kfree(fb); | |
9379 | } | |
9380 | ||
2fa2fe9a | 9381 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9382 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9383 | { |
9384 | struct drm_device *dev = crtc->base.dev; | |
9385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9386 | uint32_t tmp; | |
9387 | ||
9388 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9389 | ||
9390 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9391 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9392 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9393 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9394 | |
9395 | /* We currently do not free assignements of panel fitters on | |
9396 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9397 | * differentiates them) so just WARN about this case for now. */ | |
9398 | if (IS_GEN7(dev)) { | |
9399 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9400 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9401 | } | |
2fa2fe9a | 9402 | } |
79e53945 JB |
9403 | } |
9404 | ||
5724dbd1 DL |
9405 | static void |
9406 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9407 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9408 | { |
9409 | struct drm_device *dev = crtc->base.dev; | |
9410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9411 | u32 val, base, offset; | |
aeee5a49 | 9412 | int pipe = crtc->pipe; |
4c6baa59 | 9413 | int fourcc, pixel_format; |
6761dd31 | 9414 | unsigned int aligned_height; |
b113d5ee | 9415 | struct drm_framebuffer *fb; |
1b842c89 | 9416 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9417 | |
42a7b088 DL |
9418 | val = I915_READ(DSPCNTR(pipe)); |
9419 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9420 | return; | |
9421 | ||
d9806c9f | 9422 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9423 | if (!intel_fb) { |
4c6baa59 JB |
9424 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9425 | return; | |
9426 | } | |
9427 | ||
1b842c89 DL |
9428 | fb = &intel_fb->base; |
9429 | ||
18c5247e DV |
9430 | if (INTEL_INFO(dev)->gen >= 4) { |
9431 | if (val & DISPPLANE_TILED) { | |
49af449b | 9432 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9433 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9434 | } | |
9435 | } | |
4c6baa59 JB |
9436 | |
9437 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9438 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9439 | fb->pixel_format = fourcc; |
9440 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9441 | |
aeee5a49 | 9442 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9443 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9444 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9445 | } else { |
49af449b | 9446 | if (plane_config->tiling) |
aeee5a49 | 9447 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9448 | else |
aeee5a49 | 9449 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9450 | } |
9451 | plane_config->base = base; | |
9452 | ||
9453 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9454 | fb->width = ((val >> 16) & 0xfff) + 1; |
9455 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9456 | |
9457 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9458 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9459 | |
b113d5ee | 9460 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9461 | fb->pixel_format, |
9462 | fb->modifier[0]); | |
4c6baa59 | 9463 | |
f37b5c2b | 9464 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9465 | |
2844a921 DL |
9466 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9467 | pipe_name(pipe), fb->width, fb->height, | |
9468 | fb->bits_per_pixel, base, fb->pitches[0], | |
9469 | plane_config->size); | |
b113d5ee | 9470 | |
2d14030b | 9471 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9472 | } |
9473 | ||
0e8ffe1b | 9474 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9475 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9476 | { |
9477 | struct drm_device *dev = crtc->base.dev; | |
9478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9479 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9480 | uint32_t tmp; |
1729050e | 9481 | bool ret; |
0e8ffe1b | 9482 | |
1729050e ID |
9483 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9484 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9485 | return false; |
9486 | ||
e143a21c | 9487 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9488 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9489 | |
1729050e | 9490 | ret = false; |
0e8ffe1b DV |
9491 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9492 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9493 | goto out; |
0e8ffe1b | 9494 | |
42571aef VS |
9495 | switch (tmp & PIPECONF_BPC_MASK) { |
9496 | case PIPECONF_6BPC: | |
9497 | pipe_config->pipe_bpp = 18; | |
9498 | break; | |
9499 | case PIPECONF_8BPC: | |
9500 | pipe_config->pipe_bpp = 24; | |
9501 | break; | |
9502 | case PIPECONF_10BPC: | |
9503 | pipe_config->pipe_bpp = 30; | |
9504 | break; | |
9505 | case PIPECONF_12BPC: | |
9506 | pipe_config->pipe_bpp = 36; | |
9507 | break; | |
9508 | default: | |
9509 | break; | |
9510 | } | |
9511 | ||
b5a9fa09 DV |
9512 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9513 | pipe_config->limited_color_range = true; | |
9514 | ||
ab9412ba | 9515 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9516 | struct intel_shared_dpll *pll; |
9517 | ||
88adfff1 DV |
9518 | pipe_config->has_pch_encoder = true; |
9519 | ||
627eb5a3 DV |
9520 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9521 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9522 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9523 | |
9524 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9525 | |
c0d43d62 | 9526 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9527 | pipe_config->shared_dpll = |
9528 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9529 | } else { |
9530 | tmp = I915_READ(PCH_DPLL_SEL); | |
9531 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9532 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9533 | else | |
9534 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9535 | } | |
66e985c0 DV |
9536 | |
9537 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9538 | ||
9539 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9540 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9541 | |
9542 | tmp = pipe_config->dpll_hw_state.dpll; | |
9543 | pipe_config->pixel_multiplier = | |
9544 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9545 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9546 | |
9547 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9548 | } else { |
9549 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9550 | } |
9551 | ||
1bd1bd80 DV |
9552 | intel_get_pipe_timings(crtc, pipe_config); |
9553 | ||
2fa2fe9a DV |
9554 | ironlake_get_pfit_config(crtc, pipe_config); |
9555 | ||
1729050e ID |
9556 | ret = true; |
9557 | ||
9558 | out: | |
9559 | intel_display_power_put(dev_priv, power_domain); | |
9560 | ||
9561 | return ret; | |
0e8ffe1b DV |
9562 | } |
9563 | ||
be256dc7 PZ |
9564 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9565 | { | |
9566 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9567 | struct intel_crtc *crtc; |
be256dc7 | 9568 | |
d3fcc808 | 9569 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9570 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9571 | pipe_name(crtc->pipe)); |
9572 | ||
e2c719b7 RC |
9573 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9574 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9575 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9576 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9577 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9578 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9579 | "CPU PWM1 enabled\n"); |
c5107b87 | 9580 | if (IS_HASWELL(dev)) |
e2c719b7 | 9581 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9582 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9583 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9584 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9585 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9586 | "Utility pin enabled\n"); |
e2c719b7 | 9587 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9588 | |
9926ada1 PZ |
9589 | /* |
9590 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9591 | * interrupts remain enabled. We used to check for that, but since it's | |
9592 | * gen-specific and since we only disable LCPLL after we fully disable | |
9593 | * the interrupts, the check below should be enough. | |
9594 | */ | |
e2c719b7 | 9595 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9596 | } |
9597 | ||
9ccd5aeb PZ |
9598 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9599 | { | |
9600 | struct drm_device *dev = dev_priv->dev; | |
9601 | ||
9602 | if (IS_HASWELL(dev)) | |
9603 | return I915_READ(D_COMP_HSW); | |
9604 | else | |
9605 | return I915_READ(D_COMP_BDW); | |
9606 | } | |
9607 | ||
3c4c9b81 PZ |
9608 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9609 | { | |
9610 | struct drm_device *dev = dev_priv->dev; | |
9611 | ||
9612 | if (IS_HASWELL(dev)) { | |
9613 | mutex_lock(&dev_priv->rps.hw_lock); | |
9614 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9615 | val)) | |
f475dadf | 9616 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9617 | mutex_unlock(&dev_priv->rps.hw_lock); |
9618 | } else { | |
9ccd5aeb PZ |
9619 | I915_WRITE(D_COMP_BDW, val); |
9620 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9621 | } |
be256dc7 PZ |
9622 | } |
9623 | ||
9624 | /* | |
9625 | * This function implements pieces of two sequences from BSpec: | |
9626 | * - Sequence for display software to disable LCPLL | |
9627 | * - Sequence for display software to allow package C8+ | |
9628 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9629 | * register. Callers should take care of disabling all the display engine | |
9630 | * functions, doing the mode unset, fixing interrupts, etc. | |
9631 | */ | |
6ff58d53 PZ |
9632 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9633 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9634 | { |
9635 | uint32_t val; | |
9636 | ||
9637 | assert_can_disable_lcpll(dev_priv); | |
9638 | ||
9639 | val = I915_READ(LCPLL_CTL); | |
9640 | ||
9641 | if (switch_to_fclk) { | |
9642 | val |= LCPLL_CD_SOURCE_FCLK; | |
9643 | I915_WRITE(LCPLL_CTL, val); | |
9644 | ||
9645 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9646 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9647 | DRM_ERROR("Switching to FCLK failed\n"); | |
9648 | ||
9649 | val = I915_READ(LCPLL_CTL); | |
9650 | } | |
9651 | ||
9652 | val |= LCPLL_PLL_DISABLE; | |
9653 | I915_WRITE(LCPLL_CTL, val); | |
9654 | POSTING_READ(LCPLL_CTL); | |
9655 | ||
9656 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9657 | DRM_ERROR("LCPLL still locked\n"); | |
9658 | ||
9ccd5aeb | 9659 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9660 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9661 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9662 | ndelay(100); |
9663 | ||
9ccd5aeb PZ |
9664 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9665 | 1)) | |
be256dc7 PZ |
9666 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9667 | ||
9668 | if (allow_power_down) { | |
9669 | val = I915_READ(LCPLL_CTL); | |
9670 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9671 | I915_WRITE(LCPLL_CTL, val); | |
9672 | POSTING_READ(LCPLL_CTL); | |
9673 | } | |
9674 | } | |
9675 | ||
9676 | /* | |
9677 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9678 | * source. | |
9679 | */ | |
6ff58d53 | 9680 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9681 | { |
9682 | uint32_t val; | |
9683 | ||
9684 | val = I915_READ(LCPLL_CTL); | |
9685 | ||
9686 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9687 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9688 | return; | |
9689 | ||
a8a8bd54 PZ |
9690 | /* |
9691 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9692 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9693 | */ |
59bad947 | 9694 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9695 | |
be256dc7 PZ |
9696 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9697 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9698 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9699 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9700 | } |
9701 | ||
9ccd5aeb | 9702 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9703 | val |= D_COMP_COMP_FORCE; |
9704 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9705 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9706 | |
9707 | val = I915_READ(LCPLL_CTL); | |
9708 | val &= ~LCPLL_PLL_DISABLE; | |
9709 | I915_WRITE(LCPLL_CTL, val); | |
9710 | ||
9711 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9712 | DRM_ERROR("LCPLL not locked yet\n"); | |
9713 | ||
9714 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9715 | val = I915_READ(LCPLL_CTL); | |
9716 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9717 | I915_WRITE(LCPLL_CTL, val); | |
9718 | ||
9719 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9720 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9721 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9722 | } | |
215733fa | 9723 | |
59bad947 | 9724 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9725 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9726 | } |
9727 | ||
765dab67 PZ |
9728 | /* |
9729 | * Package states C8 and deeper are really deep PC states that can only be | |
9730 | * reached when all the devices on the system allow it, so even if the graphics | |
9731 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9732 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9733 | * | |
9734 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9735 | * well is disabled and most interrupts are disabled, and these are also | |
9736 | * requirements for runtime PM. When these conditions are met, we manually do | |
9737 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9738 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9739 | * hang the machine. | |
9740 | * | |
9741 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9742 | * the state of some registers, so when we come back from PC8+ we need to | |
9743 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9744 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9745 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9746 | * because of the runtime PM support). | |
9747 | * | |
9748 | * For more, read "Display Sequences for Package C8" on the hardware | |
9749 | * documentation. | |
9750 | */ | |
a14cb6fc | 9751 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9752 | { |
c67a470b PZ |
9753 | struct drm_device *dev = dev_priv->dev; |
9754 | uint32_t val; | |
9755 | ||
c67a470b PZ |
9756 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9757 | ||
c2699524 | 9758 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9759 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9760 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9761 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9762 | } | |
9763 | ||
9764 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9765 | hsw_disable_lcpll(dev_priv, true, true); |
9766 | } | |
9767 | ||
a14cb6fc | 9768 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9769 | { |
9770 | struct drm_device *dev = dev_priv->dev; | |
9771 | uint32_t val; | |
9772 | ||
c67a470b PZ |
9773 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9774 | ||
9775 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9776 | lpt_init_pch_refclk(dev); |
9777 | ||
c2699524 | 9778 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9779 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9780 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9781 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9782 | } | |
c67a470b PZ |
9783 | } |
9784 | ||
27c329ed | 9785 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9786 | { |
a821fc46 | 9787 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9788 | struct intel_atomic_state *old_intel_state = |
9789 | to_intel_atomic_state(old_state); | |
9790 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9791 | |
27c329ed | 9792 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9793 | } |
9794 | ||
b432e5cf | 9795 | /* compute the max rate for new configuration */ |
27c329ed | 9796 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9797 | { |
565602d7 ML |
9798 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9799 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9800 | struct drm_crtc *crtc; | |
9801 | struct drm_crtc_state *cstate; | |
27c329ed | 9802 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9803 | unsigned max_pixel_rate = 0, i; |
9804 | enum pipe pipe; | |
b432e5cf | 9805 | |
565602d7 ML |
9806 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9807 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9808 | |
565602d7 ML |
9809 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9810 | int pixel_rate; | |
27c329ed | 9811 | |
565602d7 ML |
9812 | crtc_state = to_intel_crtc_state(cstate); |
9813 | if (!crtc_state->base.enable) { | |
9814 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9815 | continue; |
565602d7 | 9816 | } |
b432e5cf | 9817 | |
27c329ed | 9818 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9819 | |
9820 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9821 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9822 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9823 | ||
565602d7 | 9824 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9825 | } |
9826 | ||
565602d7 ML |
9827 | for_each_pipe(dev_priv, pipe) |
9828 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9829 | ||
b432e5cf VS |
9830 | return max_pixel_rate; |
9831 | } | |
9832 | ||
9833 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9834 | { | |
9835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9836 | uint32_t val, data; | |
9837 | int ret; | |
9838 | ||
9839 | if (WARN((I915_READ(LCPLL_CTL) & | |
9840 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9841 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9842 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9843 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9844 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9845 | return; | |
9846 | ||
9847 | mutex_lock(&dev_priv->rps.hw_lock); | |
9848 | ret = sandybridge_pcode_write(dev_priv, | |
9849 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9850 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9851 | if (ret) { | |
9852 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9853 | return; | |
9854 | } | |
9855 | ||
9856 | val = I915_READ(LCPLL_CTL); | |
9857 | val |= LCPLL_CD_SOURCE_FCLK; | |
9858 | I915_WRITE(LCPLL_CTL, val); | |
9859 | ||
9860 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9861 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9862 | DRM_ERROR("Switching to FCLK failed\n"); | |
9863 | ||
9864 | val = I915_READ(LCPLL_CTL); | |
9865 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9866 | ||
9867 | switch (cdclk) { | |
9868 | case 450000: | |
9869 | val |= LCPLL_CLK_FREQ_450; | |
9870 | data = 0; | |
9871 | break; | |
9872 | case 540000: | |
9873 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9874 | data = 1; | |
9875 | break; | |
9876 | case 337500: | |
9877 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9878 | data = 2; | |
9879 | break; | |
9880 | case 675000: | |
9881 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9882 | data = 3; | |
9883 | break; | |
9884 | default: | |
9885 | WARN(1, "invalid cdclk frequency\n"); | |
9886 | return; | |
9887 | } | |
9888 | ||
9889 | I915_WRITE(LCPLL_CTL, val); | |
9890 | ||
9891 | val = I915_READ(LCPLL_CTL); | |
9892 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9893 | I915_WRITE(LCPLL_CTL, val); | |
9894 | ||
9895 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9896 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9897 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9898 | ||
9899 | mutex_lock(&dev_priv->rps.hw_lock); | |
9900 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9901 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9902 | ||
9903 | intel_update_cdclk(dev); | |
9904 | ||
9905 | WARN(cdclk != dev_priv->cdclk_freq, | |
9906 | "cdclk requested %d kHz but got %d kHz\n", | |
9907 | cdclk, dev_priv->cdclk_freq); | |
9908 | } | |
9909 | ||
27c329ed | 9910 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9911 | { |
27c329ed | 9912 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9913 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9914 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9915 | int cdclk; |
9916 | ||
9917 | /* | |
9918 | * FIXME should also account for plane ratio | |
9919 | * once 64bpp pixel formats are supported. | |
9920 | */ | |
27c329ed | 9921 | if (max_pixclk > 540000) |
b432e5cf | 9922 | cdclk = 675000; |
27c329ed | 9923 | else if (max_pixclk > 450000) |
b432e5cf | 9924 | cdclk = 540000; |
27c329ed | 9925 | else if (max_pixclk > 337500) |
b432e5cf VS |
9926 | cdclk = 450000; |
9927 | else | |
9928 | cdclk = 337500; | |
9929 | ||
b432e5cf | 9930 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9931 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9932 | cdclk, dev_priv->max_cdclk_freq); | |
9933 | return -EINVAL; | |
b432e5cf VS |
9934 | } |
9935 | ||
1a617b77 ML |
9936 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9937 | if (!intel_state->active_crtcs) | |
9938 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9939 | |
9940 | return 0; | |
9941 | } | |
9942 | ||
27c329ed | 9943 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9944 | { |
27c329ed | 9945 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9946 | struct intel_atomic_state *old_intel_state = |
9947 | to_intel_atomic_state(old_state); | |
9948 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9949 | |
27c329ed | 9950 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9951 | } |
9952 | ||
190f68c5 ACO |
9953 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9954 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9955 | { |
af3997b5 MK |
9956 | struct intel_encoder *intel_encoder = |
9957 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9958 | ||
9959 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9960 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9961 | return -EINVAL; | |
9962 | } | |
716c2e55 | 9963 | |
c7653199 | 9964 | crtc->lowfreq_avail = false; |
644cef34 | 9965 | |
c8f7a0db | 9966 | return 0; |
79e53945 JB |
9967 | } |
9968 | ||
3760b59c S |
9969 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9970 | enum port port, | |
9971 | struct intel_crtc_state *pipe_config) | |
9972 | { | |
9973 | switch (port) { | |
9974 | case PORT_A: | |
9975 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9976 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9977 | break; | |
9978 | case PORT_B: | |
9979 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9980 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9981 | break; | |
9982 | case PORT_C: | |
9983 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9984 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9985 | break; | |
9986 | default: | |
9987 | DRM_ERROR("Incorrect port type\n"); | |
9988 | } | |
9989 | } | |
9990 | ||
96b7dfb7 S |
9991 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9992 | enum port port, | |
5cec258b | 9993 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9994 | { |
3148ade7 | 9995 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9996 | |
9997 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9998 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9999 | ||
10000 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
10001 | case SKL_DPLL0: |
10002 | /* | |
10003 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
10004 | * of the shared DPLL framework and thus needs to be read out | |
10005 | * separately | |
10006 | */ | |
10007 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
10008 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
10009 | break; | |
96b7dfb7 S |
10010 | case SKL_DPLL1: |
10011 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
10012 | break; | |
10013 | case SKL_DPLL2: | |
10014 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
10015 | break; | |
10016 | case SKL_DPLL3: | |
10017 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
10018 | break; | |
96b7dfb7 S |
10019 | } |
10020 | } | |
10021 | ||
7d2c8175 DL |
10022 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10023 | enum port port, | |
5cec258b | 10024 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
10025 | { |
10026 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
10027 | ||
10028 | switch (pipe_config->ddi_pll_sel) { | |
10029 | case PORT_CLK_SEL_WRPLL1: | |
10030 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
10031 | break; | |
10032 | case PORT_CLK_SEL_WRPLL2: | |
10033 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
10034 | break; | |
00490c22 ML |
10035 | case PORT_CLK_SEL_SPLL: |
10036 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 10037 | break; |
7d2c8175 DL |
10038 | } |
10039 | } | |
10040 | ||
26804afd | 10041 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10042 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10043 | { |
10044 | struct drm_device *dev = crtc->base.dev; | |
10045 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 10046 | struct intel_shared_dpll *pll; |
26804afd DV |
10047 | enum port port; |
10048 | uint32_t tmp; | |
10049 | ||
10050 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10051 | ||
10052 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10053 | ||
ef11bdb3 | 10054 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 10055 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
10056 | else if (IS_BROXTON(dev)) |
10057 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
10058 | else |
10059 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10060 | |
d452c5b6 DV |
10061 | if (pipe_config->shared_dpll >= 0) { |
10062 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
10063 | ||
10064 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
10065 | &pipe_config->dpll_hw_state)); | |
10066 | } | |
10067 | ||
26804afd DV |
10068 | /* |
10069 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10070 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10071 | * the PCH transcoder is on. | |
10072 | */ | |
ca370455 DL |
10073 | if (INTEL_INFO(dev)->gen < 9 && |
10074 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10075 | pipe_config->has_pch_encoder = true; |
10076 | ||
10077 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10078 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10079 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10080 | ||
10081 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10082 | } | |
10083 | } | |
10084 | ||
0e8ffe1b | 10085 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10086 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10087 | { |
10088 | struct drm_device *dev = crtc->base.dev; | |
10089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
10090 | enum intel_display_power_domain power_domain; |
10091 | unsigned long power_domain_mask; | |
0e8ffe1b | 10092 | uint32_t tmp; |
1729050e | 10093 | bool ret; |
0e8ffe1b | 10094 | |
1729050e ID |
10095 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10096 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10097 | return false; |
1729050e ID |
10098 | power_domain_mask = BIT(power_domain); |
10099 | ||
10100 | ret = false; | |
b5482bd0 | 10101 | |
e143a21c | 10102 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
10103 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
10104 | ||
eccb140b DV |
10105 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10106 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10107 | enum pipe trans_edp_pipe; | |
10108 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10109 | default: | |
10110 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10111 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10112 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10113 | trans_edp_pipe = PIPE_A; | |
10114 | break; | |
10115 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10116 | trans_edp_pipe = PIPE_B; | |
10117 | break; | |
10118 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10119 | trans_edp_pipe = PIPE_C; | |
10120 | break; | |
10121 | } | |
10122 | ||
10123 | if (trans_edp_pipe == crtc->pipe) | |
10124 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10125 | } | |
10126 | ||
1729050e ID |
10127 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); |
10128 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10129 | goto out; | |
10130 | power_domain_mask |= BIT(power_domain); | |
2bfce950 | 10131 | |
eccb140b | 10132 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b | 10133 | if (!(tmp & PIPECONF_ENABLE)) |
1729050e | 10134 | goto out; |
0e8ffe1b | 10135 | |
26804afd | 10136 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10137 | |
1bd1bd80 DV |
10138 | intel_get_pipe_timings(crtc, pipe_config); |
10139 | ||
a1b2278e CK |
10140 | if (INTEL_INFO(dev)->gen >= 9) { |
10141 | skl_init_scalers(dev, crtc, pipe_config); | |
10142 | } | |
10143 | ||
af99ceda CK |
10144 | if (INTEL_INFO(dev)->gen >= 9) { |
10145 | pipe_config->scaler_state.scaler_id = -1; | |
10146 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10147 | } | |
10148 | ||
1729050e ID |
10149 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10150 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10151 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10152 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10153 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10154 | else |
1c132b44 | 10155 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10156 | } |
88adfff1 | 10157 | |
e59150dc JB |
10158 | if (IS_HASWELL(dev)) |
10159 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10160 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10161 | |
ebb69c95 CT |
10162 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10163 | pipe_config->pixel_multiplier = | |
10164 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10165 | } else { | |
10166 | pipe_config->pixel_multiplier = 1; | |
10167 | } | |
6c49f241 | 10168 | |
1729050e ID |
10169 | ret = true; |
10170 | ||
10171 | out: | |
10172 | for_each_power_domain(power_domain, power_domain_mask) | |
10173 | intel_display_power_put(dev_priv, power_domain); | |
10174 | ||
10175 | return ret; | |
0e8ffe1b DV |
10176 | } |
10177 | ||
55a08b3f ML |
10178 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10179 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10180 | { |
10181 | struct drm_device *dev = crtc->dev; | |
10182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10184 | uint32_t cntl = 0, size = 0; |
560b85bb | 10185 | |
55a08b3f ML |
10186 | if (plane_state && plane_state->visible) { |
10187 | unsigned int width = plane_state->base.crtc_w; | |
10188 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10189 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10190 | ||
10191 | switch (stride) { | |
10192 | default: | |
10193 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10194 | width, stride); | |
10195 | stride = 256; | |
10196 | /* fallthrough */ | |
10197 | case 256: | |
10198 | case 512: | |
10199 | case 1024: | |
10200 | case 2048: | |
10201 | break; | |
4b0e333e CW |
10202 | } |
10203 | ||
dc41c154 VS |
10204 | cntl |= CURSOR_ENABLE | |
10205 | CURSOR_GAMMA_ENABLE | | |
10206 | CURSOR_FORMAT_ARGB | | |
10207 | CURSOR_STRIDE(stride); | |
10208 | ||
10209 | size = (height << 12) | width; | |
4b0e333e | 10210 | } |
560b85bb | 10211 | |
dc41c154 VS |
10212 | if (intel_crtc->cursor_cntl != 0 && |
10213 | (intel_crtc->cursor_base != base || | |
10214 | intel_crtc->cursor_size != size || | |
10215 | intel_crtc->cursor_cntl != cntl)) { | |
10216 | /* On these chipsets we can only modify the base/size/stride | |
10217 | * whilst the cursor is disabled. | |
10218 | */ | |
0b87c24e VS |
10219 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10220 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10221 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10222 | } |
560b85bb | 10223 | |
99d1f387 | 10224 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10225 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10226 | intel_crtc->cursor_base = base; |
10227 | } | |
4726e0b0 | 10228 | |
dc41c154 VS |
10229 | if (intel_crtc->cursor_size != size) { |
10230 | I915_WRITE(CURSIZE, size); | |
10231 | intel_crtc->cursor_size = size; | |
4b0e333e | 10232 | } |
560b85bb | 10233 | |
4b0e333e | 10234 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10235 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10236 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10237 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10238 | } |
560b85bb CW |
10239 | } |
10240 | ||
55a08b3f ML |
10241 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10242 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10243 | { |
10244 | struct drm_device *dev = crtc->dev; | |
10245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10246 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10247 | int pipe = intel_crtc->pipe; | |
663f3122 | 10248 | uint32_t cntl = 0; |
4b0e333e | 10249 | |
55a08b3f | 10250 | if (plane_state && plane_state->visible) { |
4b0e333e | 10251 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10252 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10253 | case 64: |
10254 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10255 | break; | |
10256 | case 128: | |
10257 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10258 | break; | |
10259 | case 256: | |
10260 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10261 | break; | |
10262 | default: | |
55a08b3f | 10263 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10264 | return; |
65a21cd6 | 10265 | } |
4b0e333e | 10266 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10267 | |
fc6f93bc | 10268 | if (HAS_DDI(dev)) |
47bf17a7 | 10269 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10270 | |
55a08b3f ML |
10271 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10272 | cntl |= CURSOR_ROTATE_180; | |
10273 | } | |
4398ad45 | 10274 | |
4b0e333e CW |
10275 | if (intel_crtc->cursor_cntl != cntl) { |
10276 | I915_WRITE(CURCNTR(pipe), cntl); | |
10277 | POSTING_READ(CURCNTR(pipe)); | |
10278 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10279 | } |
4b0e333e | 10280 | |
65a21cd6 | 10281 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10282 | I915_WRITE(CURBASE(pipe), base); |
10283 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10284 | |
10285 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10286 | } |
10287 | ||
cda4b7d3 | 10288 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10289 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10290 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10291 | { |
10292 | struct drm_device *dev = crtc->dev; | |
10293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10295 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10296 | u32 base = intel_crtc->cursor_addr; |
10297 | u32 pos = 0; | |
cda4b7d3 | 10298 | |
55a08b3f ML |
10299 | if (plane_state) { |
10300 | int x = plane_state->base.crtc_x; | |
10301 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10302 | |
55a08b3f ML |
10303 | if (x < 0) { |
10304 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10305 | x = -x; | |
10306 | } | |
10307 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10308 | |
55a08b3f ML |
10309 | if (y < 0) { |
10310 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10311 | y = -y; | |
10312 | } | |
10313 | pos |= y << CURSOR_Y_SHIFT; | |
10314 | ||
10315 | /* ILK+ do this automagically */ | |
10316 | if (HAS_GMCH_DISPLAY(dev) && | |
10317 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10318 | base += (plane_state->base.crtc_h * | |
10319 | plane_state->base.crtc_w - 1) * 4; | |
10320 | } | |
cda4b7d3 | 10321 | } |
cda4b7d3 | 10322 | |
5efb3e28 VS |
10323 | I915_WRITE(CURPOS(pipe), pos); |
10324 | ||
8ac54669 | 10325 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10326 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10327 | else |
55a08b3f | 10328 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10329 | } |
10330 | ||
dc41c154 VS |
10331 | static bool cursor_size_ok(struct drm_device *dev, |
10332 | uint32_t width, uint32_t height) | |
10333 | { | |
10334 | if (width == 0 || height == 0) | |
10335 | return false; | |
10336 | ||
10337 | /* | |
10338 | * 845g/865g are special in that they are only limited by | |
10339 | * the width of their cursors, the height is arbitrary up to | |
10340 | * the precision of the register. Everything else requires | |
10341 | * square cursors, limited to a few power-of-two sizes. | |
10342 | */ | |
10343 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10344 | if ((width & 63) != 0) | |
10345 | return false; | |
10346 | ||
10347 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10348 | return false; | |
10349 | ||
10350 | if (height > 1023) | |
10351 | return false; | |
10352 | } else { | |
10353 | switch (width | height) { | |
10354 | case 256: | |
10355 | case 128: | |
10356 | if (IS_GEN2(dev)) | |
10357 | return false; | |
10358 | case 64: | |
10359 | break; | |
10360 | default: | |
10361 | return false; | |
10362 | } | |
10363 | } | |
10364 | ||
10365 | return true; | |
10366 | } | |
10367 | ||
79e53945 | 10368 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10369 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10370 | { |
7203425a | 10371 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10373 | |
7203425a | 10374 | for (i = start; i < end; i++) { |
79e53945 JB |
10375 | intel_crtc->lut_r[i] = red[i] >> 8; |
10376 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10377 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10378 | } | |
10379 | ||
10380 | intel_crtc_load_lut(crtc); | |
10381 | } | |
10382 | ||
79e53945 JB |
10383 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10384 | static struct drm_display_mode load_detect_mode = { | |
10385 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10386 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10387 | }; | |
10388 | ||
a8bb6818 DV |
10389 | struct drm_framebuffer * |
10390 | __intel_framebuffer_create(struct drm_device *dev, | |
10391 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10392 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10393 | { |
10394 | struct intel_framebuffer *intel_fb; | |
10395 | int ret; | |
10396 | ||
10397 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10398 | if (!intel_fb) |
d2dff872 | 10399 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10400 | |
10401 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10402 | if (ret) |
10403 | goto err; | |
d2dff872 CW |
10404 | |
10405 | return &intel_fb->base; | |
dcb1394e | 10406 | |
dd4916c5 | 10407 | err: |
dd4916c5 | 10408 | kfree(intel_fb); |
dd4916c5 | 10409 | return ERR_PTR(ret); |
d2dff872 CW |
10410 | } |
10411 | ||
b5ea642a | 10412 | static struct drm_framebuffer * |
a8bb6818 DV |
10413 | intel_framebuffer_create(struct drm_device *dev, |
10414 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10415 | struct drm_i915_gem_object *obj) | |
10416 | { | |
10417 | struct drm_framebuffer *fb; | |
10418 | int ret; | |
10419 | ||
10420 | ret = i915_mutex_lock_interruptible(dev); | |
10421 | if (ret) | |
10422 | return ERR_PTR(ret); | |
10423 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10424 | mutex_unlock(&dev->struct_mutex); | |
10425 | ||
10426 | return fb; | |
10427 | } | |
10428 | ||
d2dff872 CW |
10429 | static u32 |
10430 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10431 | { | |
10432 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10433 | return ALIGN(pitch, 64); | |
10434 | } | |
10435 | ||
10436 | static u32 | |
10437 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10438 | { | |
10439 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10440 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10441 | } |
10442 | ||
10443 | static struct drm_framebuffer * | |
10444 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10445 | struct drm_display_mode *mode, | |
10446 | int depth, int bpp) | |
10447 | { | |
dcb1394e | 10448 | struct drm_framebuffer *fb; |
d2dff872 | 10449 | struct drm_i915_gem_object *obj; |
0fed39bd | 10450 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10451 | |
10452 | obj = i915_gem_alloc_object(dev, | |
10453 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10454 | if (obj == NULL) | |
10455 | return ERR_PTR(-ENOMEM); | |
10456 | ||
10457 | mode_cmd.width = mode->hdisplay; | |
10458 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10459 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10460 | bpp); | |
5ca0c34a | 10461 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10462 | |
dcb1394e LW |
10463 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10464 | if (IS_ERR(fb)) | |
10465 | drm_gem_object_unreference_unlocked(&obj->base); | |
10466 | ||
10467 | return fb; | |
d2dff872 CW |
10468 | } |
10469 | ||
10470 | static struct drm_framebuffer * | |
10471 | mode_fits_in_fbdev(struct drm_device *dev, | |
10472 | struct drm_display_mode *mode) | |
10473 | { | |
0695726e | 10474 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10475 | struct drm_i915_private *dev_priv = dev->dev_private; |
10476 | struct drm_i915_gem_object *obj; | |
10477 | struct drm_framebuffer *fb; | |
10478 | ||
4c0e5528 | 10479 | if (!dev_priv->fbdev) |
d2dff872 CW |
10480 | return NULL; |
10481 | ||
4c0e5528 | 10482 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10483 | return NULL; |
10484 | ||
4c0e5528 DV |
10485 | obj = dev_priv->fbdev->fb->obj; |
10486 | BUG_ON(!obj); | |
10487 | ||
8bcd4553 | 10488 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10489 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10490 | fb->bits_per_pixel)) | |
d2dff872 CW |
10491 | return NULL; |
10492 | ||
01f2c773 | 10493 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10494 | return NULL; |
10495 | ||
edde3617 | 10496 | drm_framebuffer_reference(fb); |
d2dff872 | 10497 | return fb; |
4520f53a DV |
10498 | #else |
10499 | return NULL; | |
10500 | #endif | |
d2dff872 CW |
10501 | } |
10502 | ||
d3a40d1b ACO |
10503 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10504 | struct drm_crtc *crtc, | |
10505 | struct drm_display_mode *mode, | |
10506 | struct drm_framebuffer *fb, | |
10507 | int x, int y) | |
10508 | { | |
10509 | struct drm_plane_state *plane_state; | |
10510 | int hdisplay, vdisplay; | |
10511 | int ret; | |
10512 | ||
10513 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10514 | if (IS_ERR(plane_state)) | |
10515 | return PTR_ERR(plane_state); | |
10516 | ||
10517 | if (mode) | |
10518 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10519 | else | |
10520 | hdisplay = vdisplay = 0; | |
10521 | ||
10522 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10523 | if (ret) | |
10524 | return ret; | |
10525 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10526 | plane_state->crtc_x = 0; | |
10527 | plane_state->crtc_y = 0; | |
10528 | plane_state->crtc_w = hdisplay; | |
10529 | plane_state->crtc_h = vdisplay; | |
10530 | plane_state->src_x = x << 16; | |
10531 | plane_state->src_y = y << 16; | |
10532 | plane_state->src_w = hdisplay << 16; | |
10533 | plane_state->src_h = vdisplay << 16; | |
10534 | ||
10535 | return 0; | |
10536 | } | |
10537 | ||
d2434ab7 | 10538 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10539 | struct drm_display_mode *mode, |
51fd371b RC |
10540 | struct intel_load_detect_pipe *old, |
10541 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10542 | { |
10543 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10544 | struct intel_encoder *intel_encoder = |
10545 | intel_attached_encoder(connector); | |
79e53945 | 10546 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10547 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10548 | struct drm_crtc *crtc = NULL; |
10549 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10550 | struct drm_framebuffer *fb; |
51fd371b | 10551 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10552 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10553 | struct drm_connector_state *connector_state; |
4be07317 | 10554 | struct intel_crtc_state *crtc_state; |
51fd371b | 10555 | int ret, i = -1; |
79e53945 | 10556 | |
d2dff872 | 10557 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10558 | connector->base.id, connector->name, |
8e329a03 | 10559 | encoder->base.id, encoder->name); |
d2dff872 | 10560 | |
edde3617 ML |
10561 | old->restore_state = NULL; |
10562 | ||
51fd371b RC |
10563 | retry: |
10564 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10565 | if (ret) | |
ad3c558f | 10566 | goto fail; |
6e9f798d | 10567 | |
79e53945 JB |
10568 | /* |
10569 | * Algorithm gets a little messy: | |
7a5e4805 | 10570 | * |
79e53945 JB |
10571 | * - if the connector already has an assigned crtc, use it (but make |
10572 | * sure it's on first) | |
7a5e4805 | 10573 | * |
79e53945 JB |
10574 | * - try to find the first unused crtc that can drive this connector, |
10575 | * and use that if we find one | |
79e53945 JB |
10576 | */ |
10577 | ||
10578 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10579 | if (connector->state->crtc) { |
10580 | crtc = connector->state->crtc; | |
8261b191 | 10581 | |
51fd371b | 10582 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10583 | if (ret) |
ad3c558f | 10584 | goto fail; |
8261b191 CW |
10585 | |
10586 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10587 | goto found; |
79e53945 JB |
10588 | } |
10589 | ||
10590 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10591 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10592 | i++; |
10593 | if (!(encoder->possible_crtcs & (1 << i))) | |
10594 | continue; | |
edde3617 ML |
10595 | |
10596 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10597 | if (ret) | |
10598 | goto fail; | |
10599 | ||
10600 | if (possible_crtc->state->enable) { | |
10601 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10602 | continue; |
edde3617 | 10603 | } |
a459249c VS |
10604 | |
10605 | crtc = possible_crtc; | |
10606 | break; | |
79e53945 JB |
10607 | } |
10608 | ||
10609 | /* | |
10610 | * If we didn't find an unused CRTC, don't use any. | |
10611 | */ | |
10612 | if (!crtc) { | |
7173188d | 10613 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10614 | goto fail; |
79e53945 JB |
10615 | } |
10616 | ||
edde3617 ML |
10617 | found: |
10618 | intel_crtc = to_intel_crtc(crtc); | |
10619 | ||
4d02e2de DV |
10620 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10621 | if (ret) | |
ad3c558f | 10622 | goto fail; |
79e53945 | 10623 | |
83a57153 | 10624 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10625 | restore_state = drm_atomic_state_alloc(dev); |
10626 | if (!state || !restore_state) { | |
10627 | ret = -ENOMEM; | |
10628 | goto fail; | |
10629 | } | |
83a57153 ACO |
10630 | |
10631 | state->acquire_ctx = ctx; | |
edde3617 | 10632 | restore_state->acquire_ctx = ctx; |
83a57153 | 10633 | |
944b0c76 ACO |
10634 | connector_state = drm_atomic_get_connector_state(state, connector); |
10635 | if (IS_ERR(connector_state)) { | |
10636 | ret = PTR_ERR(connector_state); | |
10637 | goto fail; | |
10638 | } | |
10639 | ||
edde3617 ML |
10640 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10641 | if (ret) | |
10642 | goto fail; | |
944b0c76 | 10643 | |
4be07317 ACO |
10644 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10645 | if (IS_ERR(crtc_state)) { | |
10646 | ret = PTR_ERR(crtc_state); | |
10647 | goto fail; | |
10648 | } | |
10649 | ||
49d6fa21 | 10650 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10651 | |
6492711d CW |
10652 | if (!mode) |
10653 | mode = &load_detect_mode; | |
79e53945 | 10654 | |
d2dff872 CW |
10655 | /* We need a framebuffer large enough to accommodate all accesses |
10656 | * that the plane may generate whilst we perform load detection. | |
10657 | * We can not rely on the fbcon either being present (we get called | |
10658 | * during its initialisation to detect all boot displays, or it may | |
10659 | * not even exist) or that it is large enough to satisfy the | |
10660 | * requested mode. | |
10661 | */ | |
94352cf9 DV |
10662 | fb = mode_fits_in_fbdev(dev, mode); |
10663 | if (fb == NULL) { | |
d2dff872 | 10664 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10665 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10666 | } else |
10667 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10668 | if (IS_ERR(fb)) { |
d2dff872 | 10669 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10670 | goto fail; |
79e53945 | 10671 | } |
79e53945 | 10672 | |
d3a40d1b ACO |
10673 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10674 | if (ret) | |
10675 | goto fail; | |
10676 | ||
edde3617 ML |
10677 | drm_framebuffer_unreference(fb); |
10678 | ||
10679 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10680 | if (ret) | |
10681 | goto fail; | |
10682 | ||
10683 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10684 | if (!ret) | |
10685 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10686 | if (!ret) | |
10687 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10688 | if (ret) { | |
10689 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10690 | goto fail; | |
10691 | } | |
8c7b5ccb | 10692 | |
3ba86073 ML |
10693 | ret = drm_atomic_commit(state); |
10694 | if (ret) { | |
6492711d | 10695 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10696 | goto fail; |
79e53945 | 10697 | } |
edde3617 ML |
10698 | |
10699 | old->restore_state = restore_state; | |
7173188d | 10700 | |
79e53945 | 10701 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10702 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10703 | return true; |
412b61d8 | 10704 | |
ad3c558f | 10705 | fail: |
e5d958ef | 10706 | drm_atomic_state_free(state); |
edde3617 ML |
10707 | drm_atomic_state_free(restore_state); |
10708 | restore_state = state = NULL; | |
83a57153 | 10709 | |
51fd371b RC |
10710 | if (ret == -EDEADLK) { |
10711 | drm_modeset_backoff(ctx); | |
10712 | goto retry; | |
10713 | } | |
10714 | ||
412b61d8 | 10715 | return false; |
79e53945 JB |
10716 | } |
10717 | ||
d2434ab7 | 10718 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10719 | struct intel_load_detect_pipe *old, |
10720 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10721 | { |
d2434ab7 DV |
10722 | struct intel_encoder *intel_encoder = |
10723 | intel_attached_encoder(connector); | |
4ef69c7a | 10724 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10725 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10726 | int ret; |
79e53945 | 10727 | |
d2dff872 | 10728 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10729 | connector->base.id, connector->name, |
8e329a03 | 10730 | encoder->base.id, encoder->name); |
d2dff872 | 10731 | |
edde3617 | 10732 | if (!state) |
0622a53c | 10733 | return; |
79e53945 | 10734 | |
edde3617 ML |
10735 | ret = drm_atomic_commit(state); |
10736 | if (ret) { | |
10737 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10738 | drm_atomic_state_free(state); | |
10739 | } | |
79e53945 JB |
10740 | } |
10741 | ||
da4a1efa | 10742 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10743 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10744 | { |
10745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10746 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10747 | ||
10748 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10749 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10750 | else if (HAS_PCH_SPLIT(dev)) |
10751 | return 120000; | |
10752 | else if (!IS_GEN2(dev)) | |
10753 | return 96000; | |
10754 | else | |
10755 | return 48000; | |
10756 | } | |
10757 | ||
79e53945 | 10758 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10759 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10760 | struct intel_crtc_state *pipe_config) |
79e53945 | 10761 | { |
f1f644dc | 10762 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10763 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10764 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10765 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10766 | u32 fp; |
10767 | intel_clock_t clock; | |
dccbea3b | 10768 | int port_clock; |
da4a1efa | 10769 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10770 | |
10771 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10772 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10773 | else |
293623f7 | 10774 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10775 | |
10776 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10777 | if (IS_PINEVIEW(dev)) { |
10778 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10779 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10780 | } else { |
10781 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10782 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10783 | } | |
10784 | ||
a6c45cf0 | 10785 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10786 | if (IS_PINEVIEW(dev)) |
10787 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10788 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10789 | else |
10790 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10791 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10792 | ||
10793 | switch (dpll & DPLL_MODE_MASK) { | |
10794 | case DPLLB_MODE_DAC_SERIAL: | |
10795 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10796 | 5 : 10; | |
10797 | break; | |
10798 | case DPLLB_MODE_LVDS: | |
10799 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10800 | 7 : 14; | |
10801 | break; | |
10802 | default: | |
28c97730 | 10803 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10804 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10805 | return; |
79e53945 JB |
10806 | } |
10807 | ||
ac58c3f0 | 10808 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10809 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10810 | else |
dccbea3b | 10811 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10812 | } else { |
0fb58223 | 10813 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10814 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10815 | |
10816 | if (is_lvds) { | |
10817 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10818 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10819 | |
10820 | if (lvds & LVDS_CLKB_POWER_UP) | |
10821 | clock.p2 = 7; | |
10822 | else | |
10823 | clock.p2 = 14; | |
79e53945 JB |
10824 | } else { |
10825 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10826 | clock.p1 = 2; | |
10827 | else { | |
10828 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10829 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10830 | } | |
10831 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10832 | clock.p2 = 4; | |
10833 | else | |
10834 | clock.p2 = 2; | |
79e53945 | 10835 | } |
da4a1efa | 10836 | |
dccbea3b | 10837 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10838 | } |
10839 | ||
18442d08 VS |
10840 | /* |
10841 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10842 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10843 | * encoder's get_config() function. |
10844 | */ | |
dccbea3b | 10845 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10846 | } |
10847 | ||
6878da05 VS |
10848 | int intel_dotclock_calculate(int link_freq, |
10849 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10850 | { |
f1f644dc JB |
10851 | /* |
10852 | * The calculation for the data clock is: | |
1041a02f | 10853 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10854 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10855 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10856 | * |
10857 | * and the link clock is simpler: | |
1041a02f | 10858 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10859 | */ |
10860 | ||
6878da05 VS |
10861 | if (!m_n->link_n) |
10862 | return 0; | |
f1f644dc | 10863 | |
6878da05 VS |
10864 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10865 | } | |
f1f644dc | 10866 | |
18442d08 | 10867 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10868 | struct intel_crtc_state *pipe_config) |
6878da05 | 10869 | { |
e3b247da | 10870 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10871 | |
18442d08 VS |
10872 | /* read out port_clock from the DPLL */ |
10873 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10874 | |
f1f644dc | 10875 | /* |
e3b247da VS |
10876 | * In case there is an active pipe without active ports, |
10877 | * we may need some idea for the dotclock anyway. | |
10878 | * Calculate one based on the FDI configuration. | |
79e53945 | 10879 | */ |
2d112de7 | 10880 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10881 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10882 | &pipe_config->fdi_m_n); |
79e53945 JB |
10883 | } |
10884 | ||
10885 | /** Returns the currently programmed mode of the given pipe. */ | |
10886 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10887 | struct drm_crtc *crtc) | |
10888 | { | |
548f245b | 10889 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10891 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10892 | struct drm_display_mode *mode; |
3f36b937 | 10893 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10894 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10895 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10896 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10897 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10898 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10899 | |
10900 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10901 | if (!mode) | |
10902 | return NULL; | |
10903 | ||
3f36b937 TU |
10904 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10905 | if (!pipe_config) { | |
10906 | kfree(mode); | |
10907 | return NULL; | |
10908 | } | |
10909 | ||
f1f644dc JB |
10910 | /* |
10911 | * Construct a pipe_config sufficient for getting the clock info | |
10912 | * back out of crtc_clock_get. | |
10913 | * | |
10914 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10915 | * to use a real value here instead. | |
10916 | */ | |
3f36b937 TU |
10917 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10918 | pipe_config->pixel_multiplier = 1; | |
10919 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10920 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10921 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10922 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10923 | ||
10924 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10925 | mode->hdisplay = (htot & 0xffff) + 1; |
10926 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10927 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10928 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10929 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10930 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10931 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10932 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10933 | ||
10934 | drm_mode_set_name(mode); | |
79e53945 | 10935 | |
3f36b937 TU |
10936 | kfree(pipe_config); |
10937 | ||
79e53945 JB |
10938 | return mode; |
10939 | } | |
10940 | ||
f047e395 CW |
10941 | void intel_mark_busy(struct drm_device *dev) |
10942 | { | |
c67a470b PZ |
10943 | struct drm_i915_private *dev_priv = dev->dev_private; |
10944 | ||
f62a0076 CW |
10945 | if (dev_priv->mm.busy) |
10946 | return; | |
10947 | ||
43694d69 | 10948 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10949 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10950 | if (INTEL_INFO(dev)->gen >= 6) |
10951 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10952 | dev_priv->mm.busy = true; |
f047e395 CW |
10953 | } |
10954 | ||
10955 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10956 | { |
c67a470b | 10957 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10958 | |
f62a0076 CW |
10959 | if (!dev_priv->mm.busy) |
10960 | return; | |
10961 | ||
10962 | dev_priv->mm.busy = false; | |
10963 | ||
3d13ef2e | 10964 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10965 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10966 | |
43694d69 | 10967 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10968 | } |
10969 | ||
79e53945 JB |
10970 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10971 | { | |
10972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10973 | struct drm_device *dev = crtc->dev; |
10974 | struct intel_unpin_work *work; | |
67e77c5a | 10975 | |
5e2d7afc | 10976 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10977 | work = intel_crtc->unpin_work; |
10978 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10979 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10980 | |
10981 | if (work) { | |
10982 | cancel_work_sync(&work->work); | |
10983 | kfree(work); | |
10984 | } | |
79e53945 JB |
10985 | |
10986 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10987 | |
79e53945 JB |
10988 | kfree(intel_crtc); |
10989 | } | |
10990 | ||
6b95a207 KH |
10991 | static void intel_unpin_work_fn(struct work_struct *__work) |
10992 | { | |
10993 | struct intel_unpin_work *work = | |
10994 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10995 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10996 | struct drm_device *dev = crtc->base.dev; | |
10997 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10998 | |
b4a98e57 | 10999 | mutex_lock(&dev->struct_mutex); |
3465c580 | 11000 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 11001 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 11002 | |
f06cc1b9 | 11003 | if (work->flip_queued_req) |
146d84f0 | 11004 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
11005 | mutex_unlock(&dev->struct_mutex); |
11006 | ||
a9ff8714 | 11007 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 11008 | intel_fbc_post_update(crtc); |
89ed88ba | 11009 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 11010 | |
a9ff8714 VS |
11011 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11012 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 11013 | |
6b95a207 KH |
11014 | kfree(work); |
11015 | } | |
11016 | ||
1afe3e9d | 11017 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 11018 | struct drm_crtc *crtc) |
6b95a207 | 11019 | { |
6b95a207 KH |
11020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11021 | struct intel_unpin_work *work; | |
6b95a207 KH |
11022 | unsigned long flags; |
11023 | ||
11024 | /* Ignore early vblank irqs */ | |
11025 | if (intel_crtc == NULL) | |
11026 | return; | |
11027 | ||
f326038a DV |
11028 | /* |
11029 | * This is called both by irq handlers and the reset code (to complete | |
11030 | * lost pageflips) so needs the full irqsave spinlocks. | |
11031 | */ | |
6b95a207 KH |
11032 | spin_lock_irqsave(&dev->event_lock, flags); |
11033 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
11034 | |
11035 | /* Ensure we don't miss a work->pending update ... */ | |
11036 | smp_rmb(); | |
11037 | ||
11038 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
11039 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11040 | return; | |
11041 | } | |
11042 | ||
d6bbafa1 | 11043 | page_flip_completed(intel_crtc); |
0af7e4df | 11044 | |
6b95a207 | 11045 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
11046 | } |
11047 | ||
1afe3e9d JB |
11048 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
11049 | { | |
fbee40df | 11050 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
11051 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11052 | ||
49b14a5c | 11053 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
11054 | } |
11055 | ||
11056 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
11057 | { | |
fbee40df | 11058 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
11059 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
11060 | ||
49b14a5c | 11061 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
11062 | } |
11063 | ||
75f7f3ec VS |
11064 | /* Is 'a' after or equal to 'b'? */ |
11065 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11066 | { | |
11067 | return !((a - b) & 0x80000000); | |
11068 | } | |
11069 | ||
11070 | static bool page_flip_finished(struct intel_crtc *crtc) | |
11071 | { | |
11072 | struct drm_device *dev = crtc->base.dev; | |
11073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11074 | ||
bdfa7542 VS |
11075 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
11076 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
11077 | return true; | |
11078 | ||
75f7f3ec VS |
11079 | /* |
11080 | * The relevant registers doen't exist on pre-ctg. | |
11081 | * As the flip done interrupt doesn't trigger for mmio | |
11082 | * flips on gmch platforms, a flip count check isn't | |
11083 | * really needed there. But since ctg has the registers, | |
11084 | * include it in the check anyway. | |
11085 | */ | |
11086 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11087 | return true; | |
11088 | ||
e8861675 ML |
11089 | /* |
11090 | * BDW signals flip done immediately if the plane | |
11091 | * is disabled, even if the plane enable is already | |
11092 | * armed to occur at the next vblank :( | |
11093 | */ | |
11094 | ||
75f7f3ec VS |
11095 | /* |
11096 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11097 | * used the same base address. In that case the mmio flip might | |
11098 | * have completed, but the CS hasn't even executed the flip yet. | |
11099 | * | |
11100 | * A flip count check isn't enough as the CS might have updated | |
11101 | * the base address just after start of vblank, but before we | |
11102 | * managed to process the interrupt. This means we'd complete the | |
11103 | * CS flip too soon. | |
11104 | * | |
11105 | * Combining both checks should get us a good enough result. It may | |
11106 | * still happen that the CS flip has been executed, but has not | |
11107 | * yet actually completed. But in case the base address is the same | |
11108 | * anyway, we don't really care. | |
11109 | */ | |
11110 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11111 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11112 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11113 | crtc->unpin_work->flip_count); |
11114 | } | |
11115 | ||
6b95a207 KH |
11116 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11117 | { | |
fbee40df | 11118 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11119 | struct intel_crtc *intel_crtc = |
11120 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11121 | unsigned long flags; | |
11122 | ||
f326038a DV |
11123 | |
11124 | /* | |
11125 | * This is called both by irq handlers and the reset code (to complete | |
11126 | * lost pageflips) so needs the full irqsave spinlocks. | |
11127 | * | |
11128 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11129 | * generate a page-flip completion irq, i.e. every modeset |
11130 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11131 | */ | |
6b95a207 | 11132 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11133 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11134 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11135 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11136 | } | |
11137 | ||
6042639c | 11138 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11139 | { |
11140 | /* Ensure that the work item is consistent when activating it ... */ | |
11141 | smp_wmb(); | |
6042639c | 11142 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11143 | /* and that it is marked active as soon as the irq could fire. */ |
11144 | smp_wmb(); | |
11145 | } | |
11146 | ||
8c9f3aaf JB |
11147 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11148 | struct drm_crtc *crtc, | |
11149 | struct drm_framebuffer *fb, | |
ed8d1975 | 11150 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11151 | struct drm_i915_gem_request *req, |
ed8d1975 | 11152 | uint32_t flags) |
8c9f3aaf | 11153 | { |
6258fbe2 | 11154 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11156 | u32 flip_mask; |
11157 | int ret; | |
11158 | ||
5fb9de1a | 11159 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11160 | if (ret) |
4fa62c89 | 11161 | return ret; |
8c9f3aaf JB |
11162 | |
11163 | /* Can't queue multiple flips, so wait for the previous | |
11164 | * one to finish before executing the next. | |
11165 | */ | |
11166 | if (intel_crtc->plane) | |
11167 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11168 | else | |
11169 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11170 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11171 | intel_ring_emit(ring, MI_NOOP); | |
11172 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11173 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11174 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11175 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11176 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11177 | |
6042639c | 11178 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11179 | return 0; |
8c9f3aaf JB |
11180 | } |
11181 | ||
11182 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11183 | struct drm_crtc *crtc, | |
11184 | struct drm_framebuffer *fb, | |
ed8d1975 | 11185 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11186 | struct drm_i915_gem_request *req, |
ed8d1975 | 11187 | uint32_t flags) |
8c9f3aaf | 11188 | { |
6258fbe2 | 11189 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11191 | u32 flip_mask; |
11192 | int ret; | |
11193 | ||
5fb9de1a | 11194 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11195 | if (ret) |
4fa62c89 | 11196 | return ret; |
8c9f3aaf JB |
11197 | |
11198 | if (intel_crtc->plane) | |
11199 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11200 | else | |
11201 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11202 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11203 | intel_ring_emit(ring, MI_NOOP); | |
11204 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11205 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11206 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11207 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11208 | intel_ring_emit(ring, MI_NOOP); |
11209 | ||
6042639c | 11210 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11211 | return 0; |
8c9f3aaf JB |
11212 | } |
11213 | ||
11214 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11215 | struct drm_crtc *crtc, | |
11216 | struct drm_framebuffer *fb, | |
ed8d1975 | 11217 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11218 | struct drm_i915_gem_request *req, |
ed8d1975 | 11219 | uint32_t flags) |
8c9f3aaf | 11220 | { |
6258fbe2 | 11221 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11222 | struct drm_i915_private *dev_priv = dev->dev_private; |
11223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11224 | uint32_t pf, pipesrc; | |
11225 | int ret; | |
11226 | ||
5fb9de1a | 11227 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11228 | if (ret) |
4fa62c89 | 11229 | return ret; |
8c9f3aaf JB |
11230 | |
11231 | /* i965+ uses the linear or tiled offsets from the | |
11232 | * Display Registers (which do not change across a page-flip) | |
11233 | * so we need only reprogram the base address. | |
11234 | */ | |
6d90c952 DV |
11235 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11236 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11237 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11238 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11239 | obj->tiling_mode); |
8c9f3aaf JB |
11240 | |
11241 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11242 | * untested on non-native modes, so ignore it for now. | |
11243 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11244 | */ | |
11245 | pf = 0; | |
11246 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11247 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11248 | |
6042639c | 11249 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11250 | return 0; |
8c9f3aaf JB |
11251 | } |
11252 | ||
11253 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11254 | struct drm_crtc *crtc, | |
11255 | struct drm_framebuffer *fb, | |
ed8d1975 | 11256 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11257 | struct drm_i915_gem_request *req, |
ed8d1975 | 11258 | uint32_t flags) |
8c9f3aaf | 11259 | { |
6258fbe2 | 11260 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11261 | struct drm_i915_private *dev_priv = dev->dev_private; |
11262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11263 | uint32_t pf, pipesrc; | |
11264 | int ret; | |
11265 | ||
5fb9de1a | 11266 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11267 | if (ret) |
4fa62c89 | 11268 | return ret; |
8c9f3aaf | 11269 | |
6d90c952 DV |
11270 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11271 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11272 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11273 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11274 | |
dc257cf1 DV |
11275 | /* Contrary to the suggestions in the documentation, |
11276 | * "Enable Panel Fitter" does not seem to be required when page | |
11277 | * flipping with a non-native mode, and worse causes a normal | |
11278 | * modeset to fail. | |
11279 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11280 | */ | |
11281 | pf = 0; | |
8c9f3aaf | 11282 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11283 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11284 | |
6042639c | 11285 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11286 | return 0; |
8c9f3aaf JB |
11287 | } |
11288 | ||
7c9017e5 JB |
11289 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11290 | struct drm_crtc *crtc, | |
11291 | struct drm_framebuffer *fb, | |
ed8d1975 | 11292 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11293 | struct drm_i915_gem_request *req, |
ed8d1975 | 11294 | uint32_t flags) |
7c9017e5 | 11295 | { |
6258fbe2 | 11296 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11297 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11298 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11299 | int len, ret; |
11300 | ||
eba905b2 | 11301 | switch (intel_crtc->plane) { |
cb05d8de DV |
11302 | case PLANE_A: |
11303 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11304 | break; | |
11305 | case PLANE_B: | |
11306 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11307 | break; | |
11308 | case PLANE_C: | |
11309 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11310 | break; | |
11311 | default: | |
11312 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11313 | return -ENODEV; |
cb05d8de DV |
11314 | } |
11315 | ||
ffe74d75 | 11316 | len = 4; |
f476828a | 11317 | if (ring->id == RCS) { |
ffe74d75 | 11318 | len += 6; |
f476828a DL |
11319 | /* |
11320 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11321 | * 48bits addresses, and we need a NOOP for the batch size to | |
11322 | * stay even. | |
11323 | */ | |
11324 | if (IS_GEN8(dev)) | |
11325 | len += 2; | |
11326 | } | |
ffe74d75 | 11327 | |
f66fab8e VS |
11328 | /* |
11329 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11330 | * "The full packet must be contained within the same cache line." | |
11331 | * | |
11332 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11333 | * cacheline, if we ever start emitting more commands before | |
11334 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11335 | * then do the cacheline alignment, and finally emit the | |
11336 | * MI_DISPLAY_FLIP. | |
11337 | */ | |
bba09b12 | 11338 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11339 | if (ret) |
4fa62c89 | 11340 | return ret; |
f66fab8e | 11341 | |
5fb9de1a | 11342 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11343 | if (ret) |
4fa62c89 | 11344 | return ret; |
7c9017e5 | 11345 | |
ffe74d75 CW |
11346 | /* Unmask the flip-done completion message. Note that the bspec says that |
11347 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11348 | * more than one flip event at any time (or ensure that one flip message | |
11349 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11350 | * Experimentation says that BCS works despite DERRMR masking all | |
11351 | * flip-done completion events and that unmasking all planes at once | |
11352 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11353 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11354 | */ | |
11355 | if (ring->id == RCS) { | |
11356 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11357 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11358 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11359 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11360 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11361 | if (IS_GEN8(dev)) |
f1afe24f | 11362 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11363 | MI_SRM_LRM_GLOBAL_GTT); |
11364 | else | |
f1afe24f | 11365 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11366 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11367 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11368 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11369 | if (IS_GEN8(dev)) { |
11370 | intel_ring_emit(ring, 0); | |
11371 | intel_ring_emit(ring, MI_NOOP); | |
11372 | } | |
ffe74d75 CW |
11373 | } |
11374 | ||
cb05d8de | 11375 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11376 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11377 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11378 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11379 | |
6042639c | 11380 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11381 | return 0; |
7c9017e5 JB |
11382 | } |
11383 | ||
84c33a64 SG |
11384 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11385 | struct drm_i915_gem_object *obj) | |
11386 | { | |
11387 | /* | |
11388 | * This is not being used for older platforms, because | |
11389 | * non-availability of flip done interrupt forces us to use | |
11390 | * CS flips. Older platforms derive flip done using some clever | |
11391 | * tricks involving the flip_pending status bits and vblank irqs. | |
11392 | * So using MMIO flips there would disrupt this mechanism. | |
11393 | */ | |
11394 | ||
8e09bf83 CW |
11395 | if (ring == NULL) |
11396 | return true; | |
11397 | ||
84c33a64 SG |
11398 | if (INTEL_INFO(ring->dev)->gen < 5) |
11399 | return false; | |
11400 | ||
11401 | if (i915.use_mmio_flip < 0) | |
11402 | return false; | |
11403 | else if (i915.use_mmio_flip > 0) | |
11404 | return true; | |
14bf993e OM |
11405 | else if (i915.enable_execlists) |
11406 | return true; | |
fd8e058a AG |
11407 | else if (obj->base.dma_buf && |
11408 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11409 | false)) | |
11410 | return true; | |
84c33a64 | 11411 | else |
b4716185 | 11412 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11413 | } |
11414 | ||
6042639c | 11415 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11416 | unsigned int rotation, |
6042639c | 11417 | struct intel_unpin_work *work) |
ff944564 DL |
11418 | { |
11419 | struct drm_device *dev = intel_crtc->base.dev; | |
11420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11421 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11422 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11423 | u32 ctl, stride, tile_height; |
ff944564 DL |
11424 | |
11425 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11426 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11427 | switch (fb->modifier[0]) { |
11428 | case DRM_FORMAT_MOD_NONE: | |
11429 | break; | |
11430 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11431 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11432 | break; |
11433 | case I915_FORMAT_MOD_Y_TILED: | |
11434 | ctl |= PLANE_CTL_TILED_Y; | |
11435 | break; | |
11436 | case I915_FORMAT_MOD_Yf_TILED: | |
11437 | ctl |= PLANE_CTL_TILED_YF; | |
11438 | break; | |
11439 | default: | |
11440 | MISSING_CASE(fb->modifier[0]); | |
11441 | } | |
ff944564 DL |
11442 | |
11443 | /* | |
11444 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11445 | * linear buffers or in number of tiles for tiled buffers. | |
11446 | */ | |
86efe24a TU |
11447 | if (intel_rotation_90_or_270(rotation)) { |
11448 | /* stride = Surface height in tiles */ | |
832be82f | 11449 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11450 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11451 | } else { | |
11452 | stride = fb->pitches[0] / | |
7b49f948 VS |
11453 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11454 | fb->pixel_format); | |
86efe24a | 11455 | } |
ff944564 DL |
11456 | |
11457 | /* | |
11458 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11459 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11460 | */ | |
11461 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11462 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11463 | ||
6042639c | 11464 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11465 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11466 | } | |
11467 | ||
6042639c CW |
11468 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11469 | struct intel_unpin_work *work) | |
84c33a64 SG |
11470 | { |
11471 | struct drm_device *dev = intel_crtc->base.dev; | |
11472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11473 | struct intel_framebuffer *intel_fb = | |
11474 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11475 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11476 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11477 | u32 dspcntr; |
84c33a64 | 11478 | |
84c33a64 SG |
11479 | dspcntr = I915_READ(reg); |
11480 | ||
c5d97472 DL |
11481 | if (obj->tiling_mode != I915_TILING_NONE) |
11482 | dspcntr |= DISPPLANE_TILED; | |
11483 | else | |
11484 | dspcntr &= ~DISPPLANE_TILED; | |
11485 | ||
84c33a64 SG |
11486 | I915_WRITE(reg, dspcntr); |
11487 | ||
6042639c | 11488 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11489 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11490 | } |
11491 | ||
11492 | /* | |
11493 | * XXX: This is the temporary way to update the plane registers until we get | |
11494 | * around to using the usual plane update functions for MMIO flips | |
11495 | */ | |
6042639c | 11496 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11497 | { |
6042639c CW |
11498 | struct intel_crtc *crtc = mmio_flip->crtc; |
11499 | struct intel_unpin_work *work; | |
11500 | ||
11501 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11502 | work = crtc->unpin_work; | |
11503 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11504 | if (work == NULL) | |
11505 | return; | |
ff944564 | 11506 | |
6042639c | 11507 | intel_mark_page_flip_active(work); |
ff944564 | 11508 | |
6042639c | 11509 | intel_pipe_update_start(crtc); |
ff944564 | 11510 | |
6042639c | 11511 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11512 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11513 | else |
11514 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11515 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11516 | |
6042639c | 11517 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11518 | } |
11519 | ||
9362c7c5 | 11520 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11521 | { |
b2cfe0ab CW |
11522 | struct intel_mmio_flip *mmio_flip = |
11523 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11524 | struct intel_framebuffer *intel_fb = |
11525 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11526 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11527 | |
6042639c | 11528 | if (mmio_flip->req) { |
eed29a5b | 11529 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11530 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11531 | false, NULL, |
11532 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11533 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11534 | } | |
84c33a64 | 11535 | |
fd8e058a AG |
11536 | /* For framebuffer backed by dmabuf, wait for fence */ |
11537 | if (obj->base.dma_buf) | |
11538 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11539 | false, false, | |
11540 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11541 | ||
6042639c | 11542 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11543 | kfree(mmio_flip); |
84c33a64 SG |
11544 | } |
11545 | ||
11546 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11547 | struct drm_crtc *crtc, | |
86efe24a | 11548 | struct drm_i915_gem_object *obj) |
84c33a64 | 11549 | { |
b2cfe0ab CW |
11550 | struct intel_mmio_flip *mmio_flip; |
11551 | ||
11552 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11553 | if (mmio_flip == NULL) | |
11554 | return -ENOMEM; | |
84c33a64 | 11555 | |
bcafc4e3 | 11556 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11557 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11558 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11559 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11560 | |
b2cfe0ab CW |
11561 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11562 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11563 | |
84c33a64 SG |
11564 | return 0; |
11565 | } | |
11566 | ||
8c9f3aaf JB |
11567 | static int intel_default_queue_flip(struct drm_device *dev, |
11568 | struct drm_crtc *crtc, | |
11569 | struct drm_framebuffer *fb, | |
ed8d1975 | 11570 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11571 | struct drm_i915_gem_request *req, |
ed8d1975 | 11572 | uint32_t flags) |
8c9f3aaf JB |
11573 | { |
11574 | return -ENODEV; | |
11575 | } | |
11576 | ||
d6bbafa1 CW |
11577 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11578 | struct drm_crtc *crtc) | |
11579 | { | |
11580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11582 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11583 | u32 addr; | |
11584 | ||
11585 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11586 | return true; | |
11587 | ||
908565c2 CW |
11588 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11589 | return false; | |
11590 | ||
d6bbafa1 CW |
11591 | if (!work->enable_stall_check) |
11592 | return false; | |
11593 | ||
11594 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11595 | if (work->flip_queued_req && |
11596 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11597 | return false; |
11598 | ||
1e3feefd | 11599 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11600 | } |
11601 | ||
1e3feefd | 11602 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11603 | return false; |
11604 | ||
11605 | /* Potential stall - if we see that the flip has happened, | |
11606 | * assume a missed interrupt. */ | |
11607 | if (INTEL_INFO(dev)->gen >= 4) | |
11608 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11609 | else | |
11610 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11611 | ||
11612 | /* There is a potential issue here with a false positive after a flip | |
11613 | * to the same address. We could address this by checking for a | |
11614 | * non-incrementing frame counter. | |
11615 | */ | |
11616 | return addr == work->gtt_offset; | |
11617 | } | |
11618 | ||
11619 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11620 | { | |
11621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11622 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11624 | struct intel_unpin_work *work; |
f326038a | 11625 | |
6c51d46f | 11626 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11627 | |
11628 | if (crtc == NULL) | |
11629 | return; | |
11630 | ||
f326038a | 11631 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11632 | work = intel_crtc->unpin_work; |
11633 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11634 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11635 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11636 | page_flip_completed(intel_crtc); |
6ad790c0 | 11637 | work = NULL; |
d6bbafa1 | 11638 | } |
6ad790c0 CW |
11639 | if (work != NULL && |
11640 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11641 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11642 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11643 | } |
11644 | ||
6b95a207 KH |
11645 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11646 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11647 | struct drm_pending_vblank_event *event, |
11648 | uint32_t page_flip_flags) | |
6b95a207 KH |
11649 | { |
11650 | struct drm_device *dev = crtc->dev; | |
11651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11652 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11653 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11654 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11655 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11656 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11657 | struct intel_unpin_work *work; |
a4872ba6 | 11658 | struct intel_engine_cs *ring; |
cf5d8a46 | 11659 | bool mmio_flip; |
91af127f | 11660 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11661 | int ret; |
6b95a207 | 11662 | |
2ff8fde1 MR |
11663 | /* |
11664 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11665 | * check to be safe. In the future we may enable pageflipping from | |
11666 | * a disabled primary plane. | |
11667 | */ | |
11668 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11669 | return -EBUSY; | |
11670 | ||
e6a595d2 | 11671 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11672 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11673 | return -EINVAL; |
11674 | ||
11675 | /* | |
11676 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11677 | * Note that pitch changes could also affect these register. | |
11678 | */ | |
11679 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11680 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11681 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11682 | return -EINVAL; |
11683 | ||
f900db47 CW |
11684 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11685 | goto out_hang; | |
11686 | ||
b14c5679 | 11687 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11688 | if (work == NULL) |
11689 | return -ENOMEM; | |
11690 | ||
6b95a207 | 11691 | work->event = event; |
b4a98e57 | 11692 | work->crtc = crtc; |
ab8d6675 | 11693 | work->old_fb = old_fb; |
6b95a207 KH |
11694 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11695 | ||
87b6b101 | 11696 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11697 | if (ret) |
11698 | goto free_work; | |
11699 | ||
6b95a207 | 11700 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11701 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11702 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11703 | /* Before declaring the flip queue wedged, check if |
11704 | * the hardware completed the operation behind our backs. | |
11705 | */ | |
11706 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11707 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11708 | page_flip_completed(intel_crtc); | |
11709 | } else { | |
11710 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11711 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11712 | |
d6bbafa1 CW |
11713 | drm_crtc_vblank_put(crtc); |
11714 | kfree(work); | |
11715 | return -EBUSY; | |
11716 | } | |
6b95a207 KH |
11717 | } |
11718 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11719 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11720 | |
b4a98e57 CW |
11721 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11722 | flush_workqueue(dev_priv->wq); | |
11723 | ||
75dfca80 | 11724 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11725 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11726 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11727 | |
f4510a27 | 11728 | crtc->primary->fb = fb; |
afd65eb4 | 11729 | update_state_fb(crtc->primary); |
e8216e50 | 11730 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11731 | |
e1f99ce6 | 11732 | work->pending_flip_obj = obj; |
e1f99ce6 | 11733 | |
89ed88ba CW |
11734 | ret = i915_mutex_lock_interruptible(dev); |
11735 | if (ret) | |
11736 | goto cleanup; | |
11737 | ||
b4a98e57 | 11738 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11739 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11740 | |
75f7f3ec | 11741 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11742 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11743 | |
666a4537 | 11744 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11745 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11746 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11747 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11748 | ring = NULL; | |
48bf5b2d | 11749 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11750 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11751 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11752 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11753 | if (ring == NULL || ring->id != RCS) |
11754 | ring = &dev_priv->ring[BCS]; | |
11755 | } else { | |
11756 | ring = &dev_priv->ring[RCS]; | |
11757 | } | |
11758 | ||
cf5d8a46 CW |
11759 | mmio_flip = use_mmio_flip(ring, obj); |
11760 | ||
11761 | /* When using CS flips, we want to emit semaphores between rings. | |
11762 | * However, when using mmio flips we will create a task to do the | |
11763 | * synchronisation, so all we want here is to pin the framebuffer | |
11764 | * into the display plane and skip any waits. | |
11765 | */ | |
7580d774 ML |
11766 | if (!mmio_flip) { |
11767 | ret = i915_gem_object_sync(obj, ring, &request); | |
11768 | if (ret) | |
11769 | goto cleanup_pending; | |
11770 | } | |
11771 | ||
3465c580 | 11772 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11773 | if (ret) |
11774 | goto cleanup_pending; | |
6b95a207 | 11775 | |
dedf278c TU |
11776 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11777 | obj, 0); | |
11778 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11779 | |
cf5d8a46 | 11780 | if (mmio_flip) { |
86efe24a | 11781 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11782 | if (ret) |
11783 | goto cleanup_unpin; | |
11784 | ||
f06cc1b9 JH |
11785 | i915_gem_request_assign(&work->flip_queued_req, |
11786 | obj->last_write_req); | |
d6bbafa1 | 11787 | } else { |
6258fbe2 | 11788 | if (!request) { |
26827088 DG |
11789 | request = i915_gem_request_alloc(ring, NULL); |
11790 | if (IS_ERR(request)) { | |
11791 | ret = PTR_ERR(request); | |
6258fbe2 | 11792 | goto cleanup_unpin; |
26827088 | 11793 | } |
6258fbe2 JH |
11794 | } |
11795 | ||
11796 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11797 | page_flip_flags); |
11798 | if (ret) | |
11799 | goto cleanup_unpin; | |
11800 | ||
6258fbe2 | 11801 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11802 | } |
11803 | ||
91af127f | 11804 | if (request) |
75289874 | 11805 | i915_add_request_no_flush(request); |
91af127f | 11806 | |
1e3feefd | 11807 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11808 | work->enable_stall_check = true; |
4fa62c89 | 11809 | |
ab8d6675 | 11810 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11811 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11812 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11813 | |
a9ff8714 VS |
11814 | intel_frontbuffer_flip_prepare(dev, |
11815 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11816 | |
e5510fac JB |
11817 | trace_i915_flip_request(intel_crtc->plane, obj); |
11818 | ||
6b95a207 | 11819 | return 0; |
96b099fd | 11820 | |
4fa62c89 | 11821 | cleanup_unpin: |
3465c580 | 11822 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11823 | cleanup_pending: |
0aa498d5 | 11824 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11825 | i915_gem_request_cancel(request); |
b4a98e57 | 11826 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11827 | mutex_unlock(&dev->struct_mutex); |
11828 | cleanup: | |
f4510a27 | 11829 | crtc->primary->fb = old_fb; |
afd65eb4 | 11830 | update_state_fb(crtc->primary); |
89ed88ba CW |
11831 | |
11832 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11833 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11834 | |
5e2d7afc | 11835 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11836 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11837 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11838 | |
87b6b101 | 11839 | drm_crtc_vblank_put(crtc); |
7317c75e | 11840 | free_work: |
96b099fd CW |
11841 | kfree(work); |
11842 | ||
f900db47 | 11843 | if (ret == -EIO) { |
02e0efb5 ML |
11844 | struct drm_atomic_state *state; |
11845 | struct drm_plane_state *plane_state; | |
11846 | ||
f900db47 | 11847 | out_hang: |
02e0efb5 ML |
11848 | state = drm_atomic_state_alloc(dev); |
11849 | if (!state) | |
11850 | return -ENOMEM; | |
11851 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11852 | ||
11853 | retry: | |
11854 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11855 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11856 | if (!ret) { | |
11857 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11858 | ||
11859 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11860 | if (!ret) | |
11861 | ret = drm_atomic_commit(state); | |
11862 | } | |
11863 | ||
11864 | if (ret == -EDEADLK) { | |
11865 | drm_modeset_backoff(state->acquire_ctx); | |
11866 | drm_atomic_state_clear(state); | |
11867 | goto retry; | |
11868 | } | |
11869 | ||
11870 | if (ret) | |
11871 | drm_atomic_state_free(state); | |
11872 | ||
f0d3dad3 | 11873 | if (ret == 0 && event) { |
5e2d7afc | 11874 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11875 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11876 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11877 | } |
f900db47 | 11878 | } |
96b099fd | 11879 | return ret; |
6b95a207 KH |
11880 | } |
11881 | ||
da20eabd ML |
11882 | |
11883 | /** | |
11884 | * intel_wm_need_update - Check whether watermarks need updating | |
11885 | * @plane: drm plane | |
11886 | * @state: new plane state | |
11887 | * | |
11888 | * Check current plane state versus the new one to determine whether | |
11889 | * watermarks need to be recalculated. | |
11890 | * | |
11891 | * Returns true or false. | |
11892 | */ | |
11893 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11894 | struct drm_plane_state *state) | |
11895 | { | |
d21fbe87 MR |
11896 | struct intel_plane_state *new = to_intel_plane_state(state); |
11897 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11898 | ||
11899 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11900 | if (new->visible != cur->visible) |
11901 | return true; | |
11902 | ||
11903 | if (!cur->base.fb || !new->base.fb) | |
11904 | return false; | |
11905 | ||
11906 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11907 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11908 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11909 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11910 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11911 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11912 | return true; |
7809e5ae | 11913 | |
2791a16c | 11914 | return false; |
7809e5ae MR |
11915 | } |
11916 | ||
d21fbe87 MR |
11917 | static bool needs_scaling(struct intel_plane_state *state) |
11918 | { | |
11919 | int src_w = drm_rect_width(&state->src) >> 16; | |
11920 | int src_h = drm_rect_height(&state->src) >> 16; | |
11921 | int dst_w = drm_rect_width(&state->dst); | |
11922 | int dst_h = drm_rect_height(&state->dst); | |
11923 | ||
11924 | return (src_w != dst_w || src_h != dst_h); | |
11925 | } | |
11926 | ||
da20eabd ML |
11927 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11928 | struct drm_plane_state *plane_state) | |
11929 | { | |
ab1d3a0e | 11930 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11931 | struct drm_crtc *crtc = crtc_state->crtc; |
11932 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11933 | struct drm_plane *plane = plane_state->plane; | |
11934 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11935 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11936 | struct intel_plane_state *old_plane_state = |
11937 | to_intel_plane_state(plane->state); | |
11938 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11939 | bool mode_changed = needs_modeset(crtc_state); |
11940 | bool was_crtc_enabled = crtc->state->active; | |
11941 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11942 | bool turn_off, turn_on, visible, was_visible; |
11943 | struct drm_framebuffer *fb = plane_state->fb; | |
11944 | ||
11945 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11946 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11947 | ret = skl_update_scaler_plane( | |
11948 | to_intel_crtc_state(crtc_state), | |
11949 | to_intel_plane_state(plane_state)); | |
11950 | if (ret) | |
11951 | return ret; | |
11952 | } | |
11953 | ||
da20eabd ML |
11954 | was_visible = old_plane_state->visible; |
11955 | visible = to_intel_plane_state(plane_state)->visible; | |
11956 | ||
11957 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11958 | was_visible = false; | |
11959 | ||
35c08f43 ML |
11960 | /* |
11961 | * Visibility is calculated as if the crtc was on, but | |
11962 | * after scaler setup everything depends on it being off | |
11963 | * when the crtc isn't active. | |
11964 | */ | |
11965 | if (!is_crtc_enabled) | |
11966 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11967 | |
11968 | if (!was_visible && !visible) | |
11969 | return 0; | |
11970 | ||
e8861675 ML |
11971 | if (fb != old_plane_state->base.fb) |
11972 | pipe_config->fb_changed = true; | |
11973 | ||
da20eabd ML |
11974 | turn_off = was_visible && (!visible || mode_changed); |
11975 | turn_on = visible && (!was_visible || mode_changed); | |
11976 | ||
11977 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11978 | plane->base.id, fb ? fb->base.id : -1); | |
11979 | ||
11980 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11981 | plane->base.id, was_visible, visible, | |
11982 | turn_off, turn_on, mode_changed); | |
11983 | ||
92826fcd ML |
11984 | if (turn_on || turn_off) { |
11985 | pipe_config->wm_changed = true; | |
11986 | ||
852eb00d | 11987 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11988 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11989 | pipe_config->disable_cxsr = true; |
852eb00d | 11990 | } else if (intel_wm_need_update(plane, plane_state)) { |
92826fcd | 11991 | pipe_config->wm_changed = true; |
852eb00d | 11992 | } |
da20eabd | 11993 | |
ed4a6a7c MR |
11994 | /* Pre-gen9 platforms need two-step watermark updates */ |
11995 | if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 && | |
11996 | dev_priv->display.optimize_watermarks) | |
11997 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; | |
11998 | ||
8be6ca85 | 11999 | if (visible || was_visible) |
a9ff8714 VS |
12000 | intel_crtc->atomic.fb_bits |= |
12001 | to_intel_plane(plane)->frontbuffer_bit; | |
12002 | ||
da20eabd ML |
12003 | switch (plane->type) { |
12004 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 12005 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 12006 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 12007 | |
da20eabd ML |
12008 | break; |
12009 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
12010 | break; |
12011 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
12012 | /* |
12013 | * WaCxSRDisabledForSpriteScaling:ivb | |
12014 | * | |
12015 | * cstate->update_wm was already set above, so this flag will | |
12016 | * take effect when we commit and program watermarks. | |
12017 | */ | |
12018 | if (IS_IVYBRIDGE(dev) && | |
12019 | needs_scaling(to_intel_plane_state(plane_state)) && | |
e8861675 ML |
12020 | !needs_scaling(old_plane_state)) |
12021 | pipe_config->disable_lp_wm = true; | |
d21fbe87 MR |
12022 | |
12023 | break; | |
da20eabd ML |
12024 | } |
12025 | return 0; | |
12026 | } | |
12027 | ||
6d3a1ce7 ML |
12028 | static bool encoders_cloneable(const struct intel_encoder *a, |
12029 | const struct intel_encoder *b) | |
12030 | { | |
12031 | /* masks could be asymmetric, so check both ways */ | |
12032 | return a == b || (a->cloneable & (1 << b->type) && | |
12033 | b->cloneable & (1 << a->type)); | |
12034 | } | |
12035 | ||
12036 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12037 | struct intel_crtc *crtc, | |
12038 | struct intel_encoder *encoder) | |
12039 | { | |
12040 | struct intel_encoder *source_encoder; | |
12041 | struct drm_connector *connector; | |
12042 | struct drm_connector_state *connector_state; | |
12043 | int i; | |
12044 | ||
12045 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12046 | if (connector_state->crtc != &crtc->base) | |
12047 | continue; | |
12048 | ||
12049 | source_encoder = | |
12050 | to_intel_encoder(connector_state->best_encoder); | |
12051 | if (!encoders_cloneable(encoder, source_encoder)) | |
12052 | return false; | |
12053 | } | |
12054 | ||
12055 | return true; | |
12056 | } | |
12057 | ||
12058 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12059 | struct intel_crtc *crtc) | |
12060 | { | |
12061 | struct intel_encoder *encoder; | |
12062 | struct drm_connector *connector; | |
12063 | struct drm_connector_state *connector_state; | |
12064 | int i; | |
12065 | ||
12066 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12067 | if (connector_state->crtc != &crtc->base) | |
12068 | continue; | |
12069 | ||
12070 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12071 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12072 | return false; | |
12073 | } | |
12074 | ||
12075 | return true; | |
12076 | } | |
12077 | ||
12078 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12079 | struct drm_crtc_state *crtc_state) | |
12080 | { | |
cf5a15be | 12081 | struct drm_device *dev = crtc->dev; |
ad421372 | 12082 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12084 | struct intel_crtc_state *pipe_config = |
12085 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12086 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12087 | int ret; |
6d3a1ce7 ML |
12088 | bool mode_changed = needs_modeset(crtc_state); |
12089 | ||
12090 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12091 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12092 | return -EINVAL; | |
12093 | } | |
12094 | ||
852eb00d | 12095 | if (mode_changed && !crtc_state->active) |
92826fcd | 12096 | pipe_config->wm_changed = true; |
eddfcbcd | 12097 | |
ad421372 ML |
12098 | if (mode_changed && crtc_state->enable && |
12099 | dev_priv->display.crtc_compute_clock && | |
12100 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12101 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12102 | pipe_config); | |
12103 | if (ret) | |
12104 | return ret; | |
12105 | } | |
12106 | ||
e435d6e5 | 12107 | ret = 0; |
86c8bbbe MR |
12108 | if (dev_priv->display.compute_pipe_wm) { |
12109 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
ed4a6a7c MR |
12110 | if (ret) { |
12111 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12112 | return ret; | |
12113 | } | |
12114 | } | |
12115 | ||
12116 | if (dev_priv->display.compute_intermediate_wm && | |
12117 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12118 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12119 | return 0; | |
12120 | ||
12121 | /* | |
12122 | * Calculate 'intermediate' watermarks that satisfy both the | |
12123 | * old state and the new state. We can program these | |
12124 | * immediately. | |
12125 | */ | |
12126 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12127 | intel_crtc, | |
12128 | pipe_config); | |
12129 | if (ret) { | |
12130 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12131 | return ret; |
ed4a6a7c | 12132 | } |
86c8bbbe MR |
12133 | } |
12134 | ||
e435d6e5 ML |
12135 | if (INTEL_INFO(dev)->gen >= 9) { |
12136 | if (mode_changed) | |
12137 | ret = skl_update_scaler_crtc(pipe_config); | |
12138 | ||
12139 | if (!ret) | |
12140 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12141 | pipe_config); | |
12142 | } | |
12143 | ||
12144 | return ret; | |
6d3a1ce7 ML |
12145 | } |
12146 | ||
65b38e0d | 12147 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12148 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12149 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12150 | .atomic_begin = intel_begin_crtc_commit, |
12151 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12152 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12153 | }; |
12154 | ||
d29b2f9d ACO |
12155 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12156 | { | |
12157 | struct intel_connector *connector; | |
12158 | ||
12159 | for_each_intel_connector(dev, connector) { | |
12160 | if (connector->base.encoder) { | |
12161 | connector->base.state->best_encoder = | |
12162 | connector->base.encoder; | |
12163 | connector->base.state->crtc = | |
12164 | connector->base.encoder->crtc; | |
12165 | } else { | |
12166 | connector->base.state->best_encoder = NULL; | |
12167 | connector->base.state->crtc = NULL; | |
12168 | } | |
12169 | } | |
12170 | } | |
12171 | ||
050f7aeb | 12172 | static void |
eba905b2 | 12173 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12174 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12175 | { |
12176 | int bpp = pipe_config->pipe_bpp; | |
12177 | ||
12178 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12179 | connector->base.base.id, | |
c23cc417 | 12180 | connector->base.name); |
050f7aeb DV |
12181 | |
12182 | /* Don't use an invalid EDID bpc value */ | |
12183 | if (connector->base.display_info.bpc && | |
12184 | connector->base.display_info.bpc * 3 < bpp) { | |
12185 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12186 | bpp, connector->base.display_info.bpc*3); | |
12187 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12188 | } | |
12189 | ||
013dd9e0 JN |
12190 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12191 | if (connector->base.display_info.bpc == 0) { | |
12192 | int type = connector->base.connector_type; | |
12193 | int clamp_bpp = 24; | |
12194 | ||
12195 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12196 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12197 | type == DRM_MODE_CONNECTOR_eDP) | |
12198 | clamp_bpp = 18; | |
12199 | ||
12200 | if (bpp > clamp_bpp) { | |
12201 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12202 | bpp, clamp_bpp); | |
12203 | pipe_config->pipe_bpp = clamp_bpp; | |
12204 | } | |
050f7aeb DV |
12205 | } |
12206 | } | |
12207 | ||
4e53c2e0 | 12208 | static int |
050f7aeb | 12209 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12210 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12211 | { |
050f7aeb | 12212 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12213 | struct drm_atomic_state *state; |
da3ced29 ACO |
12214 | struct drm_connector *connector; |
12215 | struct drm_connector_state *connector_state; | |
1486017f | 12216 | int bpp, i; |
4e53c2e0 | 12217 | |
666a4537 | 12218 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12219 | bpp = 10*3; |
d328c9d7 DV |
12220 | else if (INTEL_INFO(dev)->gen >= 5) |
12221 | bpp = 12*3; | |
12222 | else | |
12223 | bpp = 8*3; | |
12224 | ||
4e53c2e0 | 12225 | |
4e53c2e0 DV |
12226 | pipe_config->pipe_bpp = bpp; |
12227 | ||
1486017f ACO |
12228 | state = pipe_config->base.state; |
12229 | ||
4e53c2e0 | 12230 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12231 | for_each_connector_in_state(state, connector, connector_state, i) { |
12232 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12233 | continue; |
12234 | ||
da3ced29 ACO |
12235 | connected_sink_compute_bpp(to_intel_connector(connector), |
12236 | pipe_config); | |
4e53c2e0 DV |
12237 | } |
12238 | ||
12239 | return bpp; | |
12240 | } | |
12241 | ||
644db711 DV |
12242 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12243 | { | |
12244 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12245 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12246 | mode->crtc_clock, |
644db711 DV |
12247 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12248 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12249 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12250 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12251 | } | |
12252 | ||
c0b03411 | 12253 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12254 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12255 | const char *context) |
12256 | { | |
6a60cd87 CK |
12257 | struct drm_device *dev = crtc->base.dev; |
12258 | struct drm_plane *plane; | |
12259 | struct intel_plane *intel_plane; | |
12260 | struct intel_plane_state *state; | |
12261 | struct drm_framebuffer *fb; | |
12262 | ||
12263 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12264 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12265 | |
12266 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12267 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12268 | pipe_config->pipe_bpp, pipe_config->dither); | |
12269 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12270 | pipe_config->has_pch_encoder, | |
12271 | pipe_config->fdi_lanes, | |
12272 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12273 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12274 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12275 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12276 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12277 | pipe_config->lane_count, |
eb14cb74 VS |
12278 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12279 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12280 | pipe_config->dp_m_n.tu); | |
b95af8be | 12281 | |
90a6b7b0 | 12282 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12283 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12284 | pipe_config->lane_count, |
b95af8be VK |
12285 | pipe_config->dp_m2_n2.gmch_m, |
12286 | pipe_config->dp_m2_n2.gmch_n, | |
12287 | pipe_config->dp_m2_n2.link_m, | |
12288 | pipe_config->dp_m2_n2.link_n, | |
12289 | pipe_config->dp_m2_n2.tu); | |
12290 | ||
55072d19 DV |
12291 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12292 | pipe_config->has_audio, | |
12293 | pipe_config->has_infoframe); | |
12294 | ||
c0b03411 | 12295 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12296 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12297 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12298 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12299 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12300 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12301 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12302 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12303 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12304 | crtc->num_scalers, | |
12305 | pipe_config->scaler_state.scaler_users, | |
12306 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12307 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12308 | pipe_config->gmch_pfit.control, | |
12309 | pipe_config->gmch_pfit.pgm_ratios, | |
12310 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12311 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12312 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12313 | pipe_config->pch_pfit.size, |
12314 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12315 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12316 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12317 | |
415ff0f6 | 12318 | if (IS_BROXTON(dev)) { |
05712c15 | 12319 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12320 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12321 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12322 | pipe_config->ddi_pll_sel, |
12323 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12324 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12325 | pipe_config->dpll_hw_state.pll0, |
12326 | pipe_config->dpll_hw_state.pll1, | |
12327 | pipe_config->dpll_hw_state.pll2, | |
12328 | pipe_config->dpll_hw_state.pll3, | |
12329 | pipe_config->dpll_hw_state.pll6, | |
12330 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12331 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12332 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12333 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12334 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12335 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12336 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12337 | pipe_config->ddi_pll_sel, | |
12338 | pipe_config->dpll_hw_state.ctrl1, | |
12339 | pipe_config->dpll_hw_state.cfgcr1, | |
12340 | pipe_config->dpll_hw_state.cfgcr2); | |
12341 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12342 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12343 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12344 | pipe_config->dpll_hw_state.wrpll, |
12345 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12346 | } else { |
12347 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12348 | "fp0: 0x%x, fp1: 0x%x\n", | |
12349 | pipe_config->dpll_hw_state.dpll, | |
12350 | pipe_config->dpll_hw_state.dpll_md, | |
12351 | pipe_config->dpll_hw_state.fp0, | |
12352 | pipe_config->dpll_hw_state.fp1); | |
12353 | } | |
12354 | ||
6a60cd87 CK |
12355 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12356 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12357 | intel_plane = to_intel_plane(plane); | |
12358 | if (intel_plane->pipe != crtc->pipe) | |
12359 | continue; | |
12360 | ||
12361 | state = to_intel_plane_state(plane->state); | |
12362 | fb = state->base.fb; | |
12363 | if (!fb) { | |
12364 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12365 | "disabled, scaler_id = %d\n", | |
12366 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12367 | plane->base.id, intel_plane->pipe, | |
12368 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12369 | drm_plane_index(plane), state->scaler_id); | |
12370 | continue; | |
12371 | } | |
12372 | ||
12373 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12374 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12375 | plane->base.id, intel_plane->pipe, | |
12376 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12377 | drm_plane_index(plane)); | |
12378 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12379 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12380 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12381 | state->scaler_id, | |
12382 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12383 | drm_rect_width(&state->src) >> 16, | |
12384 | drm_rect_height(&state->src) >> 16, | |
12385 | state->dst.x1, state->dst.y1, | |
12386 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12387 | } | |
c0b03411 DV |
12388 | } |
12389 | ||
5448a00d | 12390 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12391 | { |
5448a00d | 12392 | struct drm_device *dev = state->dev; |
da3ced29 | 12393 | struct drm_connector *connector; |
00f0b378 VS |
12394 | unsigned int used_ports = 0; |
12395 | ||
12396 | /* | |
12397 | * Walk the connector list instead of the encoder | |
12398 | * list to detect the problem on ddi platforms | |
12399 | * where there's just one encoder per digital port. | |
12400 | */ | |
0bff4858 VS |
12401 | drm_for_each_connector(connector, dev) { |
12402 | struct drm_connector_state *connector_state; | |
12403 | struct intel_encoder *encoder; | |
12404 | ||
12405 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12406 | if (!connector_state) | |
12407 | connector_state = connector->state; | |
12408 | ||
5448a00d | 12409 | if (!connector_state->best_encoder) |
00f0b378 VS |
12410 | continue; |
12411 | ||
5448a00d ACO |
12412 | encoder = to_intel_encoder(connector_state->best_encoder); |
12413 | ||
12414 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12415 | |
12416 | switch (encoder->type) { | |
12417 | unsigned int port_mask; | |
12418 | case INTEL_OUTPUT_UNKNOWN: | |
12419 | if (WARN_ON(!HAS_DDI(dev))) | |
12420 | break; | |
12421 | case INTEL_OUTPUT_DISPLAYPORT: | |
12422 | case INTEL_OUTPUT_HDMI: | |
12423 | case INTEL_OUTPUT_EDP: | |
12424 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12425 | ||
12426 | /* the same port mustn't appear more than once */ | |
12427 | if (used_ports & port_mask) | |
12428 | return false; | |
12429 | ||
12430 | used_ports |= port_mask; | |
12431 | default: | |
12432 | break; | |
12433 | } | |
12434 | } | |
12435 | ||
12436 | return true; | |
12437 | } | |
12438 | ||
83a57153 ACO |
12439 | static void |
12440 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12441 | { | |
12442 | struct drm_crtc_state tmp_state; | |
663a3640 | 12443 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12444 | struct intel_dpll_hw_state dpll_hw_state; |
12445 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12446 | uint32_t ddi_pll_sel; |
c4e2d043 | 12447 | bool force_thru; |
83a57153 | 12448 | |
7546a384 ACO |
12449 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12450 | * kzalloc'd. Code that depends on any field being zero should be | |
12451 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12452 | * only fields that are know to not cause problems are preserved. */ | |
12453 | ||
83a57153 | 12454 | tmp_state = crtc_state->base; |
663a3640 | 12455 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12456 | shared_dpll = crtc_state->shared_dpll; |
12457 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12458 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12459 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12460 | |
83a57153 | 12461 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12462 | |
83a57153 | 12463 | crtc_state->base = tmp_state; |
663a3640 | 12464 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12465 | crtc_state->shared_dpll = shared_dpll; |
12466 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12467 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12468 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12469 | } |
12470 | ||
548ee15b | 12471 | static int |
b8cecdf5 | 12472 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12473 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12474 | { |
b359283a | 12475 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12476 | struct intel_encoder *encoder; |
da3ced29 | 12477 | struct drm_connector *connector; |
0b901879 | 12478 | struct drm_connector_state *connector_state; |
d328c9d7 | 12479 | int base_bpp, ret = -EINVAL; |
0b901879 | 12480 | int i; |
e29c22c0 | 12481 | bool retry = true; |
ee7b9f93 | 12482 | |
83a57153 | 12483 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12484 | |
e143a21c DV |
12485 | pipe_config->cpu_transcoder = |
12486 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12487 | |
2960bc9c ID |
12488 | /* |
12489 | * Sanitize sync polarity flags based on requested ones. If neither | |
12490 | * positive or negative polarity is requested, treat this as meaning | |
12491 | * negative polarity. | |
12492 | */ | |
2d112de7 | 12493 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12494 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12495 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12496 | |
2d112de7 | 12497 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12498 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12499 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12500 | |
d328c9d7 DV |
12501 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12502 | pipe_config); | |
12503 | if (base_bpp < 0) | |
4e53c2e0 DV |
12504 | goto fail; |
12505 | ||
e41a56be VS |
12506 | /* |
12507 | * Determine the real pipe dimensions. Note that stereo modes can | |
12508 | * increase the actual pipe size due to the frame doubling and | |
12509 | * insertion of additional space for blanks between the frame. This | |
12510 | * is stored in the crtc timings. We use the requested mode to do this | |
12511 | * computation to clearly distinguish it from the adjusted mode, which | |
12512 | * can be changed by the connectors in the below retry loop. | |
12513 | */ | |
2d112de7 | 12514 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12515 | &pipe_config->pipe_src_w, |
12516 | &pipe_config->pipe_src_h); | |
e41a56be | 12517 | |
e29c22c0 | 12518 | encoder_retry: |
ef1b460d | 12519 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12520 | pipe_config->port_clock = 0; |
ef1b460d | 12521 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12522 | |
135c81b8 | 12523 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12524 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12525 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12526 | |
7758a113 DV |
12527 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12528 | * adjust it according to limitations or connector properties, and also | |
12529 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12530 | */ |
da3ced29 | 12531 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12532 | if (connector_state->crtc != crtc) |
7758a113 | 12533 | continue; |
7ae89233 | 12534 | |
0b901879 ACO |
12535 | encoder = to_intel_encoder(connector_state->best_encoder); |
12536 | ||
efea6e8e DV |
12537 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12538 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12539 | goto fail; |
12540 | } | |
ee7b9f93 | 12541 | } |
47f1c6c9 | 12542 | |
ff9a6750 DV |
12543 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12544 | * done afterwards in case the encoder adjusts the mode. */ | |
12545 | if (!pipe_config->port_clock) | |
2d112de7 | 12546 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12547 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12548 | |
a43f6e0f | 12549 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12550 | if (ret < 0) { |
7758a113 DV |
12551 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12552 | goto fail; | |
ee7b9f93 | 12553 | } |
e29c22c0 DV |
12554 | |
12555 | if (ret == RETRY) { | |
12556 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12557 | ret = -EINVAL; | |
12558 | goto fail; | |
12559 | } | |
12560 | ||
12561 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12562 | retry = false; | |
12563 | goto encoder_retry; | |
12564 | } | |
12565 | ||
e8fa4270 DV |
12566 | /* Dithering seems to not pass-through bits correctly when it should, so |
12567 | * only enable it on 6bpc panels. */ | |
12568 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12569 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12570 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12571 | |
7758a113 | 12572 | fail: |
548ee15b | 12573 | return ret; |
ee7b9f93 | 12574 | } |
47f1c6c9 | 12575 | |
ea9d758d | 12576 | static void |
4740b0f2 | 12577 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12578 | { |
0a9ab303 ACO |
12579 | struct drm_crtc *crtc; |
12580 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12581 | int i; |
ea9d758d | 12582 | |
7668851f | 12583 | /* Double check state. */ |
8a75d157 | 12584 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12585 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12586 | |
12587 | /* Update hwmode for vblank functions */ | |
12588 | if (crtc->state->active) | |
12589 | crtc->hwmode = crtc->state->adjusted_mode; | |
12590 | else | |
12591 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12592 | |
12593 | /* | |
12594 | * Update legacy state to satisfy fbc code. This can | |
12595 | * be removed when fbc uses the atomic state. | |
12596 | */ | |
12597 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12598 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12599 | ||
12600 | crtc->primary->fb = plane_state->fb; | |
12601 | crtc->x = plane_state->src_x >> 16; | |
12602 | crtc->y = plane_state->src_y >> 16; | |
12603 | } | |
ea9d758d | 12604 | } |
ea9d758d DV |
12605 | } |
12606 | ||
3bd26263 | 12607 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12608 | { |
3bd26263 | 12609 | int diff; |
f1f644dc JB |
12610 | |
12611 | if (clock1 == clock2) | |
12612 | return true; | |
12613 | ||
12614 | if (!clock1 || !clock2) | |
12615 | return false; | |
12616 | ||
12617 | diff = abs(clock1 - clock2); | |
12618 | ||
12619 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12620 | return true; | |
12621 | ||
12622 | return false; | |
12623 | } | |
12624 | ||
25c5b266 DV |
12625 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12626 | list_for_each_entry((intel_crtc), \ | |
12627 | &(dev)->mode_config.crtc_list, \ | |
12628 | base.head) \ | |
95150bdf | 12629 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12630 | |
cfb23ed6 ML |
12631 | static bool |
12632 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12633 | unsigned int m2, unsigned int n2, | |
12634 | bool exact) | |
12635 | { | |
12636 | if (m == m2 && n == n2) | |
12637 | return true; | |
12638 | ||
12639 | if (exact || !m || !n || !m2 || !n2) | |
12640 | return false; | |
12641 | ||
12642 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12643 | ||
31d10b57 ML |
12644 | if (n > n2) { |
12645 | while (n > n2) { | |
cfb23ed6 ML |
12646 | m2 <<= 1; |
12647 | n2 <<= 1; | |
12648 | } | |
31d10b57 ML |
12649 | } else if (n < n2) { |
12650 | while (n < n2) { | |
cfb23ed6 ML |
12651 | m <<= 1; |
12652 | n <<= 1; | |
12653 | } | |
12654 | } | |
12655 | ||
31d10b57 ML |
12656 | if (n != n2) |
12657 | return false; | |
12658 | ||
12659 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12660 | } |
12661 | ||
12662 | static bool | |
12663 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12664 | struct intel_link_m_n *m2_n2, | |
12665 | bool adjust) | |
12666 | { | |
12667 | if (m_n->tu == m2_n2->tu && | |
12668 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12669 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12670 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12671 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12672 | if (adjust) | |
12673 | *m2_n2 = *m_n; | |
12674 | ||
12675 | return true; | |
12676 | } | |
12677 | ||
12678 | return false; | |
12679 | } | |
12680 | ||
0e8ffe1b | 12681 | static bool |
2fa2fe9a | 12682 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12683 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12684 | struct intel_crtc_state *pipe_config, |
12685 | bool adjust) | |
0e8ffe1b | 12686 | { |
cfb23ed6 ML |
12687 | bool ret = true; |
12688 | ||
12689 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12690 | do { \ | |
12691 | if (!adjust) \ | |
12692 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12693 | else \ | |
12694 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12695 | } while (0) | |
12696 | ||
66e985c0 DV |
12697 | #define PIPE_CONF_CHECK_X(name) \ |
12698 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12699 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12700 | "(expected 0x%08x, found 0x%08x)\n", \ |
12701 | current_config->name, \ | |
12702 | pipe_config->name); \ | |
cfb23ed6 | 12703 | ret = false; \ |
66e985c0 DV |
12704 | } |
12705 | ||
08a24034 DV |
12706 | #define PIPE_CONF_CHECK_I(name) \ |
12707 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12708 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12709 | "(expected %i, found %i)\n", \ |
12710 | current_config->name, \ | |
12711 | pipe_config->name); \ | |
cfb23ed6 ML |
12712 | ret = false; \ |
12713 | } | |
12714 | ||
12715 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12716 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12717 | &pipe_config->name,\ | |
12718 | adjust)) { \ | |
12719 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12720 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12721 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12722 | current_config->name.tu, \ | |
12723 | current_config->name.gmch_m, \ | |
12724 | current_config->name.gmch_n, \ | |
12725 | current_config->name.link_m, \ | |
12726 | current_config->name.link_n, \ | |
12727 | pipe_config->name.tu, \ | |
12728 | pipe_config->name.gmch_m, \ | |
12729 | pipe_config->name.gmch_n, \ | |
12730 | pipe_config->name.link_m, \ | |
12731 | pipe_config->name.link_n); \ | |
12732 | ret = false; \ | |
12733 | } | |
12734 | ||
12735 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12736 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12737 | &pipe_config->name, adjust) && \ | |
12738 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12739 | &pipe_config->name, adjust)) { \ | |
12740 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12741 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12742 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12743 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12744 | current_config->name.tu, \ | |
12745 | current_config->name.gmch_m, \ | |
12746 | current_config->name.gmch_n, \ | |
12747 | current_config->name.link_m, \ | |
12748 | current_config->name.link_n, \ | |
12749 | current_config->alt_name.tu, \ | |
12750 | current_config->alt_name.gmch_m, \ | |
12751 | current_config->alt_name.gmch_n, \ | |
12752 | current_config->alt_name.link_m, \ | |
12753 | current_config->alt_name.link_n, \ | |
12754 | pipe_config->name.tu, \ | |
12755 | pipe_config->name.gmch_m, \ | |
12756 | pipe_config->name.gmch_n, \ | |
12757 | pipe_config->name.link_m, \ | |
12758 | pipe_config->name.link_n); \ | |
12759 | ret = false; \ | |
88adfff1 DV |
12760 | } |
12761 | ||
b95af8be VK |
12762 | /* This is required for BDW+ where there is only one set of registers for |
12763 | * switching between high and low RR. | |
12764 | * This macro can be used whenever a comparison has to be made between one | |
12765 | * hw state and multiple sw state variables. | |
12766 | */ | |
12767 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12768 | if ((current_config->name != pipe_config->name) && \ | |
12769 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12770 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12771 | "(expected %i or %i, found %i)\n", \ |
12772 | current_config->name, \ | |
12773 | current_config->alt_name, \ | |
12774 | pipe_config->name); \ | |
cfb23ed6 | 12775 | ret = false; \ |
b95af8be VK |
12776 | } |
12777 | ||
1bd1bd80 DV |
12778 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12779 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12780 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12781 | "(expected %i, found %i)\n", \ |
12782 | current_config->name & (mask), \ | |
12783 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12784 | ret = false; \ |
1bd1bd80 DV |
12785 | } |
12786 | ||
5e550656 VS |
12787 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12788 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12789 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12790 | "(expected %i, found %i)\n", \ |
12791 | current_config->name, \ | |
12792 | pipe_config->name); \ | |
cfb23ed6 | 12793 | ret = false; \ |
5e550656 VS |
12794 | } |
12795 | ||
bb760063 DV |
12796 | #define PIPE_CONF_QUIRK(quirk) \ |
12797 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12798 | ||
eccb140b DV |
12799 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12800 | ||
08a24034 DV |
12801 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12802 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12803 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12804 | |
eb14cb74 | 12805 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12806 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12807 | |
12808 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12809 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12810 | ||
cfb23ed6 ML |
12811 | if (current_config->has_drrs) |
12812 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12813 | } else | |
12814 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12815 | |
a65347ba JN |
12816 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12817 | ||
2d112de7 ACO |
12818 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12819 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12820 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12821 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12822 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12823 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12824 | |
2d112de7 ACO |
12825 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12826 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12827 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12828 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12829 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12830 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12831 | |
c93f54cf | 12832 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12833 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12834 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12835 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12836 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12837 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12838 | |
9ed109a7 DV |
12839 | PIPE_CONF_CHECK_I(has_audio); |
12840 | ||
2d112de7 | 12841 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12842 | DRM_MODE_FLAG_INTERLACE); |
12843 | ||
bb760063 | 12844 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12845 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12846 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12847 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12848 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12849 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12850 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12851 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12852 | DRM_MODE_FLAG_NVSYNC); |
12853 | } | |
045ac3b5 | 12854 | |
333b8ca8 | 12855 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12856 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12857 | if (INTEL_INFO(dev)->gen < 4) | |
12858 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12859 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12860 | |
bfd16b2a ML |
12861 | if (!adjust) { |
12862 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12863 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12864 | ||
12865 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12866 | if (current_config->pch_pfit.enabled) { | |
12867 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12868 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12869 | } | |
2fa2fe9a | 12870 | |
7aefe2b5 ML |
12871 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12872 | } | |
a1b2278e | 12873 | |
e59150dc JB |
12874 | /* BDW+ don't expose a synchronous way to read the state */ |
12875 | if (IS_HASWELL(dev)) | |
12876 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12877 | |
282740f7 VS |
12878 | PIPE_CONF_CHECK_I(double_wide); |
12879 | ||
26804afd DV |
12880 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12881 | ||
c0d43d62 | 12882 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12883 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12884 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12885 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12886 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12887 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12888 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12889 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12890 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12891 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12892 | |
42571aef VS |
12893 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12894 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12895 | ||
2d112de7 | 12896 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12897 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12898 | |
66e985c0 | 12899 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12900 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12901 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12902 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12903 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12904 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12905 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12906 | |
cfb23ed6 | 12907 | return ret; |
0e8ffe1b DV |
12908 | } |
12909 | ||
e3b247da VS |
12910 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12911 | const struct intel_crtc_state *pipe_config) | |
12912 | { | |
12913 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12914 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12915 | &pipe_config->fdi_m_n); |
12916 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12917 | ||
12918 | /* | |
12919 | * FDI already provided one idea for the dotclock. | |
12920 | * Yell if the encoder disagrees. | |
12921 | */ | |
12922 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12923 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12924 | fdi_dotclock, dotclock); | |
12925 | } | |
12926 | } | |
12927 | ||
08db6652 DL |
12928 | static void check_wm_state(struct drm_device *dev) |
12929 | { | |
12930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12931 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12932 | struct intel_crtc *intel_crtc; | |
12933 | int plane; | |
12934 | ||
12935 | if (INTEL_INFO(dev)->gen < 9) | |
12936 | return; | |
12937 | ||
12938 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12939 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12940 | ||
12941 | for_each_intel_crtc(dev, intel_crtc) { | |
12942 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12943 | const enum pipe pipe = intel_crtc->pipe; | |
12944 | ||
12945 | if (!intel_crtc->active) | |
12946 | continue; | |
12947 | ||
12948 | /* planes */ | |
dd740780 | 12949 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12950 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12951 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12952 | ||
12953 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12954 | continue; | |
12955 | ||
12956 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12957 | "(expected (%u,%u), found (%u,%u))\n", | |
12958 | pipe_name(pipe), plane + 1, | |
12959 | sw_entry->start, sw_entry->end, | |
12960 | hw_entry->start, hw_entry->end); | |
12961 | } | |
12962 | ||
12963 | /* cursor */ | |
4969d33e MR |
12964 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12965 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12966 | |
12967 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12968 | continue; | |
12969 | ||
12970 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12971 | "(expected (%u,%u), found (%u,%u))\n", | |
12972 | pipe_name(pipe), | |
12973 | sw_entry->start, sw_entry->end, | |
12974 | hw_entry->start, hw_entry->end); | |
12975 | } | |
12976 | } | |
12977 | ||
91d1b4bd | 12978 | static void |
35dd3c64 ML |
12979 | check_connector_state(struct drm_device *dev, |
12980 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12981 | { |
35dd3c64 ML |
12982 | struct drm_connector_state *old_conn_state; |
12983 | struct drm_connector *connector; | |
12984 | int i; | |
8af6cf88 | 12985 | |
35dd3c64 ML |
12986 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12987 | struct drm_encoder *encoder = connector->encoder; | |
12988 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12989 | |
8af6cf88 DV |
12990 | /* This also checks the encoder/connector hw state with the |
12991 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12992 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12993 | |
ad3c558f | 12994 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12995 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12996 | } |
91d1b4bd DV |
12997 | } |
12998 | ||
12999 | static void | |
13000 | check_encoder_state(struct drm_device *dev) | |
13001 | { | |
13002 | struct intel_encoder *encoder; | |
13003 | struct intel_connector *connector; | |
8af6cf88 | 13004 | |
b2784e15 | 13005 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13006 | bool enabled = false; |
4d20cd86 | 13007 | enum pipe pipe; |
8af6cf88 DV |
13008 | |
13009 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13010 | encoder->base.base.id, | |
8e329a03 | 13011 | encoder->base.name); |
8af6cf88 | 13012 | |
3a3371ff | 13013 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13014 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13015 | continue; |
13016 | enabled = true; | |
ad3c558f ML |
13017 | |
13018 | I915_STATE_WARN(connector->base.state->crtc != | |
13019 | encoder->base.crtc, | |
13020 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13021 | } |
0e32b39c | 13022 | |
e2c719b7 | 13023 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13024 | "encoder's enabled state mismatch " |
13025 | "(expected %i, found %i)\n", | |
13026 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13027 | |
13028 | if (!encoder->base.crtc) { | |
4d20cd86 | 13029 | bool active; |
7c60d198 | 13030 | |
4d20cd86 ML |
13031 | active = encoder->get_hw_state(encoder, &pipe); |
13032 | I915_STATE_WARN(active, | |
13033 | "encoder detached but still enabled on pipe %c.\n", | |
13034 | pipe_name(pipe)); | |
7c60d198 | 13035 | } |
8af6cf88 | 13036 | } |
91d1b4bd DV |
13037 | } |
13038 | ||
13039 | static void | |
4d20cd86 | 13040 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 13041 | { |
fbee40df | 13042 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 13043 | struct intel_encoder *encoder; |
4d20cd86 ML |
13044 | struct drm_crtc_state *old_crtc_state; |
13045 | struct drm_crtc *crtc; | |
13046 | int i; | |
8af6cf88 | 13047 | |
4d20cd86 ML |
13048 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
13049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13050 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 13051 | bool active; |
8af6cf88 | 13052 | |
bfd16b2a ML |
13053 | if (!needs_modeset(crtc->state) && |
13054 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 13055 | continue; |
045ac3b5 | 13056 | |
4d20cd86 ML |
13057 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
13058 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
13059 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13060 | pipe_config->base.crtc = crtc; | |
13061 | pipe_config->base.state = old_state; | |
8af6cf88 | 13062 | |
4d20cd86 ML |
13063 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
13064 | crtc->base.id); | |
8af6cf88 | 13065 | |
4d20cd86 ML |
13066 | active = dev_priv->display.get_pipe_config(intel_crtc, |
13067 | pipe_config); | |
d62cf62a | 13068 | |
b6b5d049 | 13069 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
13070 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
13071 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13072 | active = crtc->state->active; | |
6c49f241 | 13073 | |
4d20cd86 | 13074 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 13075 | "crtc active state doesn't match with hw state " |
4d20cd86 | 13076 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 13077 | |
4d20cd86 | 13078 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 13079 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
13080 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
13081 | ||
13082 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
13083 | enum pipe pipe; | |
13084 | ||
13085 | active = encoder->get_hw_state(encoder, &pipe); | |
13086 | I915_STATE_WARN(active != crtc->state->active, | |
13087 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13088 | encoder->base.base.id, active, crtc->state->active); | |
13089 | ||
13090 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
13091 | "Encoder connected to wrong pipe %c\n", | |
13092 | pipe_name(pipe)); | |
13093 | ||
13094 | if (active) | |
13095 | encoder->get_config(encoder, pipe_config); | |
13096 | } | |
53d9f4e9 | 13097 | |
4d20cd86 | 13098 | if (!crtc->state->active) |
cfb23ed6 ML |
13099 | continue; |
13100 | ||
e3b247da VS |
13101 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
13102 | ||
4d20cd86 ML |
13103 | sw_config = to_intel_crtc_state(crtc->state); |
13104 | if (!intel_pipe_config_compare(dev, sw_config, | |
13105 | pipe_config, false)) { | |
e2c719b7 | 13106 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 13107 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 13108 | "[hw state]"); |
4d20cd86 | 13109 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
13110 | "[sw state]"); |
13111 | } | |
8af6cf88 DV |
13112 | } |
13113 | } | |
13114 | ||
91d1b4bd DV |
13115 | static void |
13116 | check_shared_dpll_state(struct drm_device *dev) | |
13117 | { | |
fbee40df | 13118 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
13119 | struct intel_crtc *crtc; |
13120 | struct intel_dpll_hw_state dpll_hw_state; | |
13121 | int i; | |
5358901f DV |
13122 | |
13123 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
13124 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13125 | int enabled_crtcs = 0, active_crtcs = 0; | |
13126 | bool active; | |
13127 | ||
13128 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13129 | ||
13130 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13131 | ||
13132 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13133 | ||
e2c719b7 | 13134 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13135 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13136 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13137 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13138 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13139 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13140 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13141 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13142 | "pll on state mismatch (expected %i, found %i)\n", |
13143 | pll->on, active); | |
13144 | ||
d3fcc808 | 13145 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13146 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13147 | enabled_crtcs++; |
13148 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13149 | active_crtcs++; | |
13150 | } | |
e2c719b7 | 13151 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13152 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13153 | pll->active, active_crtcs); | |
e2c719b7 | 13154 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13155 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13156 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13157 | |
e2c719b7 | 13158 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13159 | sizeof(dpll_hw_state)), |
13160 | "pll hw state mismatch\n"); | |
5358901f | 13161 | } |
8af6cf88 DV |
13162 | } |
13163 | ||
ee165b1a ML |
13164 | static void |
13165 | intel_modeset_check_state(struct drm_device *dev, | |
13166 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13167 | { |
08db6652 | 13168 | check_wm_state(dev); |
35dd3c64 | 13169 | check_connector_state(dev, old_state); |
91d1b4bd | 13170 | check_encoder_state(dev); |
4d20cd86 | 13171 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13172 | check_shared_dpll_state(dev); |
13173 | } | |
13174 | ||
80715b2f VS |
13175 | static void update_scanline_offset(struct intel_crtc *crtc) |
13176 | { | |
13177 | struct drm_device *dev = crtc->base.dev; | |
13178 | ||
13179 | /* | |
13180 | * The scanline counter increments at the leading edge of hsync. | |
13181 | * | |
13182 | * On most platforms it starts counting from vtotal-1 on the | |
13183 | * first active line. That means the scanline counter value is | |
13184 | * always one less than what we would expect. Ie. just after | |
13185 | * start of vblank, which also occurs at start of hsync (on the | |
13186 | * last active line), the scanline counter will read vblank_start-1. | |
13187 | * | |
13188 | * On gen2 the scanline counter starts counting from 1 instead | |
13189 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13190 | * to keep the value positive), instead of adding one. | |
13191 | * | |
13192 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13193 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13194 | * there's an extra 1 line difference. So we need to add two instead of | |
13195 | * one to the value. | |
13196 | */ | |
13197 | if (IS_GEN2(dev)) { | |
124abe07 | 13198 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13199 | int vtotal; |
13200 | ||
124abe07 VS |
13201 | vtotal = adjusted_mode->crtc_vtotal; |
13202 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13203 | vtotal /= 2; |
13204 | ||
13205 | crtc->scanline_offset = vtotal - 1; | |
13206 | } else if (HAS_DDI(dev) && | |
409ee761 | 13207 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13208 | crtc->scanline_offset = 2; |
13209 | } else | |
13210 | crtc->scanline_offset = 1; | |
13211 | } | |
13212 | ||
ad421372 | 13213 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13214 | { |
225da59b | 13215 | struct drm_device *dev = state->dev; |
ed6739ef | 13216 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13217 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13218 | struct drm_crtc *crtc; |
13219 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13220 | int i; |
ed6739ef ACO |
13221 | |
13222 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13223 | return; |
ed6739ef | 13224 | |
0a9ab303 | 13225 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13227 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13228 | |
fb1a38a9 | 13229 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13230 | continue; |
13231 | ||
fb1a38a9 ML |
13232 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13233 | ||
13234 | if (old_dpll == DPLL_ID_PRIVATE) | |
13235 | continue; | |
0a9ab303 | 13236 | |
ad421372 ML |
13237 | if (!shared_dpll) |
13238 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13239 | |
fb1a38a9 | 13240 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13241 | } |
ed6739ef ACO |
13242 | } |
13243 | ||
99d736a2 ML |
13244 | /* |
13245 | * This implements the workaround described in the "notes" section of the mode | |
13246 | * set sequence documentation. When going from no pipes or single pipe to | |
13247 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13248 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13249 | */ | |
13250 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13251 | { | |
13252 | struct drm_crtc_state *crtc_state; | |
13253 | struct intel_crtc *intel_crtc; | |
13254 | struct drm_crtc *crtc; | |
13255 | struct intel_crtc_state *first_crtc_state = NULL; | |
13256 | struct intel_crtc_state *other_crtc_state = NULL; | |
13257 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13258 | int i; | |
13259 | ||
13260 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13261 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13262 | intel_crtc = to_intel_crtc(crtc); | |
13263 | ||
13264 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13265 | continue; | |
13266 | ||
13267 | if (first_crtc_state) { | |
13268 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13269 | break; | |
13270 | } else { | |
13271 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13272 | first_pipe = intel_crtc->pipe; | |
13273 | } | |
13274 | } | |
13275 | ||
13276 | /* No workaround needed? */ | |
13277 | if (!first_crtc_state) | |
13278 | return 0; | |
13279 | ||
13280 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13281 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13282 | struct intel_crtc_state *pipe_config; | |
13283 | ||
13284 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13285 | if (IS_ERR(pipe_config)) | |
13286 | return PTR_ERR(pipe_config); | |
13287 | ||
13288 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13289 | ||
13290 | if (!pipe_config->base.active || | |
13291 | needs_modeset(&pipe_config->base)) | |
13292 | continue; | |
13293 | ||
13294 | /* 2 or more enabled crtcs means no need for w/a */ | |
13295 | if (enabled_pipe != INVALID_PIPE) | |
13296 | return 0; | |
13297 | ||
13298 | enabled_pipe = intel_crtc->pipe; | |
13299 | } | |
13300 | ||
13301 | if (enabled_pipe != INVALID_PIPE) | |
13302 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13303 | else if (other_crtc_state) | |
13304 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13305 | ||
13306 | return 0; | |
13307 | } | |
13308 | ||
27c329ed ML |
13309 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13310 | { | |
13311 | struct drm_crtc *crtc; | |
13312 | struct drm_crtc_state *crtc_state; | |
13313 | int ret = 0; | |
13314 | ||
13315 | /* add all active pipes to the state */ | |
13316 | for_each_crtc(state->dev, crtc) { | |
13317 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13318 | if (IS_ERR(crtc_state)) | |
13319 | return PTR_ERR(crtc_state); | |
13320 | ||
13321 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13322 | continue; | |
13323 | ||
13324 | crtc_state->mode_changed = true; | |
13325 | ||
13326 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13327 | if (ret) | |
13328 | break; | |
13329 | ||
13330 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13331 | if (ret) | |
13332 | break; | |
13333 | } | |
13334 | ||
13335 | return ret; | |
13336 | } | |
13337 | ||
c347a676 | 13338 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13339 | { |
565602d7 ML |
13340 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13341 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13342 | struct drm_crtc *crtc; | |
13343 | struct drm_crtc_state *crtc_state; | |
13344 | int ret = 0, i; | |
054518dd | 13345 | |
b359283a ML |
13346 | if (!check_digital_port_conflicts(state)) { |
13347 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13348 | return -EINVAL; | |
13349 | } | |
13350 | ||
565602d7 ML |
13351 | intel_state->modeset = true; |
13352 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13353 | ||
13354 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13355 | if (crtc_state->active) | |
13356 | intel_state->active_crtcs |= 1 << i; | |
13357 | else | |
13358 | intel_state->active_crtcs &= ~(1 << i); | |
13359 | } | |
13360 | ||
054518dd ACO |
13361 | /* |
13362 | * See if the config requires any additional preparation, e.g. | |
13363 | * to adjust global state with pipes off. We need to do this | |
13364 | * here so we can get the modeset_pipe updated config for the new | |
13365 | * mode set on this crtc. For other crtcs we need to use the | |
13366 | * adjusted_mode bits in the crtc directly. | |
13367 | */ | |
27c329ed | 13368 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13369 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13370 | ||
1a617b77 | 13371 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13372 | ret = intel_modeset_all_pipes(state); |
13373 | ||
13374 | if (ret < 0) | |
054518dd | 13375 | return ret; |
e8788cbc ML |
13376 | |
13377 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13378 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13379 | } else |
1a617b77 | 13380 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13381 | |
ad421372 | 13382 | intel_modeset_clear_plls(state); |
054518dd | 13383 | |
565602d7 | 13384 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13385 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13386 | |
ad421372 | 13387 | return 0; |
c347a676 ACO |
13388 | } |
13389 | ||
aa363136 MR |
13390 | /* |
13391 | * Handle calculation of various watermark data at the end of the atomic check | |
13392 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13393 | * handlers to ensure that all derived state has been updated. | |
13394 | */ | |
13395 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13396 | { | |
13397 | struct drm_device *dev = state->dev; | |
13398 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13399 | struct drm_crtc *crtc; | |
13400 | struct drm_crtc_state *cstate; | |
13401 | struct drm_plane *plane; | |
13402 | struct drm_plane_state *pstate; | |
13403 | ||
13404 | /* | |
13405 | * Calculate watermark configuration details now that derived | |
13406 | * plane/crtc state is all properly updated. | |
13407 | */ | |
13408 | drm_for_each_crtc(crtc, dev) { | |
13409 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13410 | crtc->state; | |
13411 | ||
13412 | if (cstate->active) | |
13413 | intel_state->wm_config.num_pipes_active++; | |
13414 | } | |
13415 | drm_for_each_legacy_plane(plane, dev) { | |
13416 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13417 | plane->state; | |
13418 | ||
13419 | if (!to_intel_plane_state(pstate)->visible) | |
13420 | continue; | |
13421 | ||
13422 | intel_state->wm_config.sprites_enabled = true; | |
13423 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13424 | pstate->crtc_h != pstate->src_h >> 16) | |
13425 | intel_state->wm_config.sprites_scaled = true; | |
13426 | } | |
13427 | } | |
13428 | ||
74c090b1 ML |
13429 | /** |
13430 | * intel_atomic_check - validate state object | |
13431 | * @dev: drm device | |
13432 | * @state: state to validate | |
13433 | */ | |
13434 | static int intel_atomic_check(struct drm_device *dev, | |
13435 | struct drm_atomic_state *state) | |
c347a676 | 13436 | { |
dd8b3bdb | 13437 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13438 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13439 | struct drm_crtc *crtc; |
13440 | struct drm_crtc_state *crtc_state; | |
13441 | int ret, i; | |
61333b60 | 13442 | bool any_ms = false; |
c347a676 | 13443 | |
74c090b1 | 13444 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13445 | if (ret) |
13446 | return ret; | |
13447 | ||
c347a676 | 13448 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13449 | struct intel_crtc_state *pipe_config = |
13450 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13451 | |
ba8af3e5 ML |
13452 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13453 | sizeof(struct intel_crtc_atomic_commit)); | |
13454 | ||
1ed51de9 DV |
13455 | /* Catch I915_MODE_FLAG_INHERITED */ |
13456 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13457 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13458 | |
61333b60 ML |
13459 | if (!crtc_state->enable) { |
13460 | if (needs_modeset(crtc_state)) | |
13461 | any_ms = true; | |
c347a676 | 13462 | continue; |
61333b60 | 13463 | } |
c347a676 | 13464 | |
26495481 | 13465 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13466 | continue; |
13467 | ||
26495481 DV |
13468 | /* FIXME: For only active_changed we shouldn't need to do any |
13469 | * state recomputation at all. */ | |
13470 | ||
1ed51de9 DV |
13471 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13472 | if (ret) | |
13473 | return ret; | |
b359283a | 13474 | |
cfb23ed6 | 13475 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13476 | if (ret) |
13477 | return ret; | |
13478 | ||
73831236 | 13479 | if (i915.fastboot && |
dd8b3bdb | 13480 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13481 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13482 | pipe_config, true)) { |
26495481 | 13483 | crtc_state->mode_changed = false; |
bfd16b2a | 13484 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13485 | } |
13486 | ||
13487 | if (needs_modeset(crtc_state)) { | |
13488 | any_ms = true; | |
cfb23ed6 ML |
13489 | |
13490 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13491 | if (ret) | |
13492 | return ret; | |
13493 | } | |
61333b60 | 13494 | |
26495481 DV |
13495 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13496 | needs_modeset(crtc_state) ? | |
13497 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13498 | } |
13499 | ||
61333b60 ML |
13500 | if (any_ms) { |
13501 | ret = intel_modeset_checks(state); | |
13502 | ||
13503 | if (ret) | |
13504 | return ret; | |
27c329ed | 13505 | } else |
dd8b3bdb | 13506 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13507 | |
dd8b3bdb | 13508 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13509 | if (ret) |
13510 | return ret; | |
13511 | ||
f51be2e0 | 13512 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13513 | calc_watermark_data(state); |
13514 | ||
13515 | return 0; | |
054518dd ACO |
13516 | } |
13517 | ||
5008e874 ML |
13518 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13519 | struct drm_atomic_state *state, | |
13520 | bool async) | |
13521 | { | |
7580d774 ML |
13522 | struct drm_i915_private *dev_priv = dev->dev_private; |
13523 | struct drm_plane_state *plane_state; | |
5008e874 | 13524 | struct drm_crtc_state *crtc_state; |
7580d774 | 13525 | struct drm_plane *plane; |
5008e874 ML |
13526 | struct drm_crtc *crtc; |
13527 | int i, ret; | |
13528 | ||
13529 | if (async) { | |
13530 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13531 | return -EINVAL; | |
13532 | } | |
13533 | ||
13534 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13535 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13536 | if (ret) | |
13537 | return ret; | |
7580d774 ML |
13538 | |
13539 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13540 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13541 | } |
13542 | ||
f935675f ML |
13543 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13544 | if (ret) | |
13545 | return ret; | |
13546 | ||
5008e874 | 13547 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13548 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13549 | u32 reset_counter; | |
13550 | ||
13551 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13552 | mutex_unlock(&dev->struct_mutex); | |
13553 | ||
13554 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13555 | struct intel_plane_state *intel_plane_state = | |
13556 | to_intel_plane_state(plane_state); | |
13557 | ||
13558 | if (!intel_plane_state->wait_req) | |
13559 | continue; | |
13560 | ||
13561 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13562 | reset_counter, true, | |
13563 | NULL, NULL); | |
13564 | ||
13565 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13566 | if (ret == -EIO) | |
13567 | ret = 0; | |
13568 | ||
13569 | if (ret) | |
13570 | break; | |
13571 | } | |
13572 | ||
13573 | if (!ret) | |
13574 | return 0; | |
13575 | ||
13576 | mutex_lock(&dev->struct_mutex); | |
13577 | drm_atomic_helper_cleanup_planes(dev, state); | |
13578 | } | |
5008e874 | 13579 | |
f935675f | 13580 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13581 | return ret; |
13582 | } | |
13583 | ||
e8861675 ML |
13584 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13585 | struct drm_i915_private *dev_priv, | |
13586 | unsigned crtc_mask) | |
13587 | { | |
13588 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13589 | enum pipe pipe; | |
13590 | int ret; | |
13591 | ||
13592 | if (!crtc_mask) | |
13593 | return; | |
13594 | ||
13595 | for_each_pipe(dev_priv, pipe) { | |
13596 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13597 | ||
13598 | if (!((1 << pipe) & crtc_mask)) | |
13599 | continue; | |
13600 | ||
13601 | ret = drm_crtc_vblank_get(crtc); | |
13602 | if (WARN_ON(ret != 0)) { | |
13603 | crtc_mask &= ~(1 << pipe); | |
13604 | continue; | |
13605 | } | |
13606 | ||
13607 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13608 | } | |
13609 | ||
13610 | for_each_pipe(dev_priv, pipe) { | |
13611 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13612 | long lret; | |
13613 | ||
13614 | if (!((1 << pipe) & crtc_mask)) | |
13615 | continue; | |
13616 | ||
13617 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13618 | last_vblank_count[pipe] != | |
13619 | drm_crtc_vblank_count(crtc), | |
13620 | msecs_to_jiffies(50)); | |
13621 | ||
13622 | WARN_ON(!lret); | |
13623 | ||
13624 | drm_crtc_vblank_put(crtc); | |
13625 | } | |
13626 | } | |
13627 | ||
13628 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13629 | { | |
13630 | /* fb updated, need to unpin old fb */ | |
13631 | if (crtc_state->fb_changed) | |
13632 | return true; | |
13633 | ||
13634 | /* wm changes, need vblank before final wm's */ | |
13635 | if (crtc_state->wm_changed) | |
13636 | return true; | |
13637 | ||
13638 | /* | |
13639 | * cxsr is re-enabled after vblank. | |
13640 | * This is already handled by crtc_state->wm_changed, | |
13641 | * but added for clarity. | |
13642 | */ | |
13643 | if (crtc_state->disable_cxsr) | |
13644 | return true; | |
13645 | ||
13646 | return false; | |
13647 | } | |
13648 | ||
74c090b1 ML |
13649 | /** |
13650 | * intel_atomic_commit - commit validated state object | |
13651 | * @dev: DRM device | |
13652 | * @state: the top-level driver state object | |
13653 | * @async: asynchronous commit | |
13654 | * | |
13655 | * This function commits a top-level state object that has been validated | |
13656 | * with drm_atomic_helper_check(). | |
13657 | * | |
13658 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13659 | * we can only handle plane-related operations and do not yet support | |
13660 | * asynchronous commit. | |
13661 | * | |
13662 | * RETURNS | |
13663 | * Zero for success or -errno. | |
13664 | */ | |
13665 | static int intel_atomic_commit(struct drm_device *dev, | |
13666 | struct drm_atomic_state *state, | |
13667 | bool async) | |
a6778b3c | 13668 | { |
565602d7 | 13669 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13670 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13671 | struct drm_crtc_state *crtc_state; |
7580d774 | 13672 | struct drm_crtc *crtc; |
ed4a6a7c | 13673 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13674 | int ret = 0, i; |
13675 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13676 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13677 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13678 | |
5008e874 | 13679 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13680 | if (ret) { |
13681 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13682 | return ret; |
7580d774 | 13683 | } |
d4afb8cc | 13684 | |
1c5e19f8 | 13685 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13686 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13687 | |
565602d7 ML |
13688 | if (intel_state->modeset) { |
13689 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13690 | sizeof(intel_state->min_pixclk)); | |
13691 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13692 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13693 | |
13694 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13695 | } |
13696 | ||
0a9ab303 | 13697 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13698 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13699 | ||
33c8df89 ML |
13700 | if (needs_modeset(crtc->state) || |
13701 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13702 | hw_check = true; | |
13703 | ||
13704 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13705 | modeset_get_crtc_power_domains(crtc, | |
13706 | to_intel_crtc_state(crtc->state)); | |
13707 | } | |
13708 | ||
61333b60 ML |
13709 | if (!needs_modeset(crtc->state)) |
13710 | continue; | |
13711 | ||
5c74cd73 | 13712 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13713 | |
a539205a ML |
13714 | if (crtc_state->active) { |
13715 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13716 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13717 | intel_crtc->active = false; |
58f9c0bc | 13718 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13719 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13720 | |
13721 | /* | |
13722 | * Underruns don't always raise | |
13723 | * interrupts, so check manually. | |
13724 | */ | |
13725 | intel_check_cpu_fifo_underruns(dev_priv); | |
13726 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13727 | |
13728 | if (!crtc->state->active) | |
13729 | intel_update_watermarks(crtc); | |
a539205a | 13730 | } |
b8cecdf5 | 13731 | } |
7758a113 | 13732 | |
ea9d758d DV |
13733 | /* Only after disabling all output pipelines that will be changed can we |
13734 | * update the the output configuration. */ | |
4740b0f2 | 13735 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13736 | |
565602d7 | 13737 | if (intel_state->modeset) { |
4740b0f2 ML |
13738 | intel_shared_dpll_commit(state); |
13739 | ||
13740 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
33c8df89 ML |
13741 | |
13742 | if (dev_priv->display.modeset_commit_cdclk && | |
13743 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13744 | dev_priv->display.modeset_commit_cdclk(state); | |
4740b0f2 | 13745 | } |
47fab737 | 13746 | |
a6778b3c | 13747 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13748 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13749 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13750 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13751 | struct intel_crtc_state *pipe_config = |
13752 | to_intel_crtc_state(crtc->state); | |
13753 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13754 | |
f6ac4b2a | 13755 | if (modeset && crtc->state->active) { |
a539205a ML |
13756 | update_scanline_offset(to_intel_crtc(crtc)); |
13757 | dev_priv->display.crtc_enable(crtc); | |
13758 | } | |
80715b2f | 13759 | |
f6ac4b2a | 13760 | if (!modeset) |
5c74cd73 | 13761 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13762 | |
49227c4a PZ |
13763 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13764 | intel_fbc_enable(intel_crtc); | |
13765 | ||
6173ee28 ML |
13766 | if (crtc->state->active && |
13767 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13768 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a | 13769 | |
e8861675 ML |
13770 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13771 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13772 | } |
a6778b3c | 13773 | |
a6778b3c | 13774 | /* FIXME: add subpixel order */ |
83a57153 | 13775 | |
e8861675 ML |
13776 | if (!state->legacy_cursor_update) |
13777 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13778 | |
33c8df89 | 13779 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
e8861675 ML |
13780 | intel_post_plane_update(to_intel_crtc(crtc)); |
13781 | ||
33c8df89 ML |
13782 | if (put_domains[i]) |
13783 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
13784 | } | |
13785 | ||
13786 | if (intel_state->modeset) | |
13787 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13788 | ||
ed4a6a7c MR |
13789 | /* |
13790 | * Now that the vblank has passed, we can go ahead and program the | |
13791 | * optimal watermarks on platforms that need two-step watermark | |
13792 | * programming. | |
13793 | * | |
13794 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13795 | */ | |
13796 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13797 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13798 | ||
13799 | if (dev_priv->display.optimize_watermarks) | |
13800 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13801 | } | |
13802 | ||
f935675f | 13803 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13804 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13805 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13806 | |
565602d7 | 13807 | if (hw_check) |
ee165b1a ML |
13808 | intel_modeset_check_state(dev, state); |
13809 | ||
13810 | drm_atomic_state_free(state); | |
f30da187 | 13811 | |
75714940 MK |
13812 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13813 | * of triggering bugs in unclaimed access. After we finish | |
13814 | * modesetting, see if an error has been flagged, and if so | |
13815 | * enable debugging for the next modeset - and hope we catch | |
13816 | * the culprit. | |
13817 | * | |
13818 | * XXX note that we assume display power is on at this point. | |
13819 | * This might hold true now but we need to add pm helper to check | |
13820 | * unclaimed only when the hardware is on, as atomic commits | |
13821 | * can happen also when the device is completely off. | |
13822 | */ | |
13823 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13824 | ||
74c090b1 | 13825 | return 0; |
7f27126e JB |
13826 | } |
13827 | ||
c0c36b94 CW |
13828 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13829 | { | |
83a57153 ACO |
13830 | struct drm_device *dev = crtc->dev; |
13831 | struct drm_atomic_state *state; | |
e694eb02 | 13832 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13833 | int ret; |
83a57153 ACO |
13834 | |
13835 | state = drm_atomic_state_alloc(dev); | |
13836 | if (!state) { | |
e694eb02 | 13837 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13838 | crtc->base.id); |
13839 | return; | |
13840 | } | |
13841 | ||
e694eb02 | 13842 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13843 | |
e694eb02 ML |
13844 | retry: |
13845 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13846 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13847 | if (!ret) { | |
13848 | if (!crtc_state->active) | |
13849 | goto out; | |
83a57153 | 13850 | |
e694eb02 | 13851 | crtc_state->mode_changed = true; |
74c090b1 | 13852 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13853 | } |
13854 | ||
e694eb02 ML |
13855 | if (ret == -EDEADLK) { |
13856 | drm_atomic_state_clear(state); | |
13857 | drm_modeset_backoff(state->acquire_ctx); | |
13858 | goto retry; | |
4ed9fb37 | 13859 | } |
4be07317 | 13860 | |
2bfb4627 | 13861 | if (ret) |
e694eb02 | 13862 | out: |
2bfb4627 | 13863 | drm_atomic_state_free(state); |
c0c36b94 CW |
13864 | } |
13865 | ||
25c5b266 DV |
13866 | #undef for_each_intel_crtc_masked |
13867 | ||
f6e5b160 | 13868 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13869 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13870 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13871 | .destroy = intel_crtc_destroy, |
13872 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13873 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13874 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13875 | }; |
13876 | ||
5358901f DV |
13877 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13878 | struct intel_shared_dpll *pll, | |
13879 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13880 | { |
5358901f | 13881 | uint32_t val; |
ee7b9f93 | 13882 | |
12fda387 | 13883 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13884 | return false; |
13885 | ||
5358901f | 13886 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13887 | hw_state->dpll = val; |
13888 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13889 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f | 13890 | |
12fda387 ID |
13891 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); |
13892 | ||
5358901f DV |
13893 | return val & DPLL_VCO_ENABLE; |
13894 | } | |
13895 | ||
15bdd4cf DV |
13896 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13897 | struct intel_shared_dpll *pll) | |
13898 | { | |
3e369b76 ACO |
13899 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13900 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13901 | } |
13902 | ||
e7b903d2 DV |
13903 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13904 | struct intel_shared_dpll *pll) | |
13905 | { | |
e7b903d2 | 13906 | /* PCH refclock must be enabled first */ |
89eff4be | 13907 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13908 | |
3e369b76 | 13909 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13910 | |
13911 | /* Wait for the clocks to stabilize. */ | |
13912 | POSTING_READ(PCH_DPLL(pll->id)); | |
13913 | udelay(150); | |
13914 | ||
13915 | /* The pixel multiplier can only be updated once the | |
13916 | * DPLL is enabled and the clocks are stable. | |
13917 | * | |
13918 | * So write it again. | |
13919 | */ | |
3e369b76 | 13920 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13921 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13922 | udelay(200); |
13923 | } | |
13924 | ||
13925 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13926 | struct intel_shared_dpll *pll) | |
13927 | { | |
13928 | struct drm_device *dev = dev_priv->dev; | |
13929 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13930 | |
13931 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13932 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13933 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13934 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13935 | } |
13936 | ||
15bdd4cf DV |
13937 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13938 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13939 | udelay(200); |
13940 | } | |
13941 | ||
46edb027 DV |
13942 | static char *ibx_pch_dpll_names[] = { |
13943 | "PCH DPLL A", | |
13944 | "PCH DPLL B", | |
13945 | }; | |
13946 | ||
7c74ade1 | 13947 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13948 | { |
e7b903d2 | 13949 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13950 | int i; |
13951 | ||
7c74ade1 | 13952 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13953 | |
e72f9fbf | 13954 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13955 | dev_priv->shared_dplls[i].id = i; |
13956 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13957 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13958 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13959 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13960 | dev_priv->shared_dplls[i].get_hw_state = |
13961 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13962 | } |
13963 | } | |
13964 | ||
7c74ade1 DV |
13965 | static void intel_shared_dpll_init(struct drm_device *dev) |
13966 | { | |
e7b903d2 | 13967 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13968 | |
9cd86933 DV |
13969 | if (HAS_DDI(dev)) |
13970 | intel_ddi_pll_init(dev); | |
13971 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13972 | ibx_pch_dpll_init(dev); |
13973 | else | |
13974 | dev_priv->num_shared_dpll = 0; | |
13975 | ||
13976 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13977 | } |
13978 | ||
6beb8c23 MR |
13979 | /** |
13980 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13981 | * @plane: drm plane to prepare for | |
13982 | * @fb: framebuffer to prepare for presentation | |
13983 | * | |
13984 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13985 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13986 | * bits. Some older platforms need special physical address handling for | |
13987 | * cursor planes. | |
13988 | * | |
f935675f ML |
13989 | * Must be called with struct_mutex held. |
13990 | * | |
6beb8c23 MR |
13991 | * Returns 0 on success, negative error code on failure. |
13992 | */ | |
13993 | int | |
13994 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13995 | const struct drm_plane_state *new_state) |
465c120c MR |
13996 | { |
13997 | struct drm_device *dev = plane->dev; | |
844f9111 | 13998 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13999 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 14000 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14001 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 14002 | int ret = 0; |
465c120c | 14003 | |
1ee49399 | 14004 | if (!obj && !old_obj) |
465c120c MR |
14005 | return 0; |
14006 | ||
5008e874 ML |
14007 | if (old_obj) { |
14008 | struct drm_crtc_state *crtc_state = | |
14009 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
14010 | ||
14011 | /* Big Hammer, we also need to ensure that any pending | |
14012 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14013 | * current scanout is retired before unpinning the old | |
14014 | * framebuffer. Note that we rely on userspace rendering | |
14015 | * into the buffer attached to the pipe they are waiting | |
14016 | * on. If not, userspace generates a GPU hang with IPEHR | |
14017 | * point to the MI_WAIT_FOR_EVENT. | |
14018 | * | |
14019 | * This should only fail upon a hung GPU, in which case we | |
14020 | * can safely continue. | |
14021 | */ | |
14022 | if (needs_modeset(crtc_state)) | |
14023 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
14024 | ||
14025 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
14026 | if (ret && ret != -EIO) | |
f935675f | 14027 | return ret; |
5008e874 ML |
14028 | } |
14029 | ||
3c28ff22 AG |
14030 | /* For framebuffer backed by dmabuf, wait for fence */ |
14031 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
14032 | long lret; |
14033 | ||
14034 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
14035 | false, true, | |
14036 | MAX_SCHEDULE_TIMEOUT); | |
14037 | if (lret == -ERESTARTSYS) | |
14038 | return lret; | |
3c28ff22 | 14039 | |
bcf8be27 | 14040 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
14041 | } |
14042 | ||
1ee49399 ML |
14043 | if (!obj) { |
14044 | ret = 0; | |
14045 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
14046 | INTEL_INFO(dev)->cursor_needs_physical) { |
14047 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
14048 | ret = i915_gem_object_attach_phys(obj, align); | |
14049 | if (ret) | |
14050 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
14051 | } else { | |
3465c580 | 14052 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 14053 | } |
465c120c | 14054 | |
7580d774 ML |
14055 | if (ret == 0) { |
14056 | if (obj) { | |
14057 | struct intel_plane_state *plane_state = | |
14058 | to_intel_plane_state(new_state); | |
14059 | ||
14060 | i915_gem_request_assign(&plane_state->wait_req, | |
14061 | obj->last_write_req); | |
14062 | } | |
14063 | ||
a9ff8714 | 14064 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 14065 | } |
fdd508a6 | 14066 | |
6beb8c23 MR |
14067 | return ret; |
14068 | } | |
14069 | ||
38f3ce3a MR |
14070 | /** |
14071 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14072 | * @plane: drm plane to clean up for | |
14073 | * @fb: old framebuffer that was on plane | |
14074 | * | |
14075 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14076 | * |
14077 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14078 | */ |
14079 | void | |
14080 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 14081 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
14082 | { |
14083 | struct drm_device *dev = plane->dev; | |
1ee49399 | 14084 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 14085 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14086 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14087 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14088 | |
7580d774 ML |
14089 | old_intel_state = to_intel_plane_state(old_state); |
14090 | ||
1ee49399 | 14091 | if (!obj && !old_obj) |
38f3ce3a MR |
14092 | return; |
14093 | ||
1ee49399 ML |
14094 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14095 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14096 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
14097 | |
14098 | /* prepare_fb aborted? */ | |
14099 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
14100 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
14101 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
14102 | |
14103 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
14104 | } |
14105 | ||
6156a456 CK |
14106 | int |
14107 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14108 | { | |
14109 | int max_scale; | |
14110 | struct drm_device *dev; | |
14111 | struct drm_i915_private *dev_priv; | |
14112 | int crtc_clock, cdclk; | |
14113 | ||
bf8a0af0 | 14114 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14115 | return DRM_PLANE_HELPER_NO_SCALING; |
14116 | ||
14117 | dev = intel_crtc->base.dev; | |
14118 | dev_priv = dev->dev_private; | |
14119 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 14120 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14121 | |
54bf1ce6 | 14122 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14123 | return DRM_PLANE_HELPER_NO_SCALING; |
14124 | ||
14125 | /* | |
14126 | * skl max scale is lower of: | |
14127 | * close to 3 but not 3, -1 is for that purpose | |
14128 | * or | |
14129 | * cdclk/crtc_clock | |
14130 | */ | |
14131 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14132 | ||
14133 | return max_scale; | |
14134 | } | |
14135 | ||
465c120c | 14136 | static int |
3c692a41 | 14137 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14138 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14139 | struct intel_plane_state *state) |
14140 | { | |
2b875c22 MR |
14141 | struct drm_crtc *crtc = state->base.crtc; |
14142 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14143 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14144 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14145 | bool can_position = false; | |
465c120c | 14146 | |
693bdc28 VS |
14147 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
14148 | /* use scaler when colorkey is not required */ | |
14149 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14150 | min_scale = 1; | |
14151 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14152 | } | |
d8106366 | 14153 | can_position = true; |
6156a456 | 14154 | } |
d8106366 | 14155 | |
061e4b8d ML |
14156 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14157 | &state->dst, &state->clip, | |
da20eabd ML |
14158 | min_scale, max_scale, |
14159 | can_position, true, | |
14160 | &state->visible); | |
14af293f GP |
14161 | } |
14162 | ||
613d2b27 ML |
14163 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14164 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 14165 | { |
32b7eeec | 14166 | struct drm_device *dev = crtc->dev; |
3c692a41 | 14167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
14168 | struct intel_crtc_state *old_intel_state = |
14169 | to_intel_crtc_state(old_crtc_state); | |
14170 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 14171 | |
c34c9ee4 | 14172 | /* Perform vblank evasion around commit operation */ |
62852622 | 14173 | intel_pipe_update_start(intel_crtc); |
0583236e | 14174 | |
bfd16b2a ML |
14175 | if (modeset) |
14176 | return; | |
14177 | ||
14178 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14179 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14180 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14181 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14182 | } |
14183 | ||
613d2b27 ML |
14184 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14185 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14186 | { |
32b7eeec | 14187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14188 | |
62852622 | 14189 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14190 | } |
14191 | ||
cf4c7c12 | 14192 | /** |
4a3b8769 MR |
14193 | * intel_plane_destroy - destroy a plane |
14194 | * @plane: plane to destroy | |
cf4c7c12 | 14195 | * |
4a3b8769 MR |
14196 | * Common destruction function for all types of planes (primary, cursor, |
14197 | * sprite). | |
cf4c7c12 | 14198 | */ |
4a3b8769 | 14199 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14200 | { |
14201 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14202 | drm_plane_cleanup(plane); | |
14203 | kfree(intel_plane); | |
14204 | } | |
14205 | ||
65a3fea0 | 14206 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14207 | .update_plane = drm_atomic_helper_update_plane, |
14208 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14209 | .destroy = intel_plane_destroy, |
c196e1d6 | 14210 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14211 | .atomic_get_property = intel_plane_atomic_get_property, |
14212 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14213 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14214 | .atomic_destroy_state = intel_plane_destroy_state, | |
14215 | ||
465c120c MR |
14216 | }; |
14217 | ||
14218 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14219 | int pipe) | |
14220 | { | |
14221 | struct intel_plane *primary; | |
8e7d688b | 14222 | struct intel_plane_state *state; |
465c120c | 14223 | const uint32_t *intel_primary_formats; |
45e3743a | 14224 | unsigned int num_formats; |
465c120c MR |
14225 | |
14226 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14227 | if (primary == NULL) | |
14228 | return NULL; | |
14229 | ||
8e7d688b MR |
14230 | state = intel_create_plane_state(&primary->base); |
14231 | if (!state) { | |
ea2c67bb MR |
14232 | kfree(primary); |
14233 | return NULL; | |
14234 | } | |
8e7d688b | 14235 | primary->base.state = &state->base; |
ea2c67bb | 14236 | |
465c120c MR |
14237 | primary->can_scale = false; |
14238 | primary->max_downscale = 1; | |
6156a456 CK |
14239 | if (INTEL_INFO(dev)->gen >= 9) { |
14240 | primary->can_scale = true; | |
af99ceda | 14241 | state->scaler_id = -1; |
6156a456 | 14242 | } |
465c120c MR |
14243 | primary->pipe = pipe; |
14244 | primary->plane = pipe; | |
a9ff8714 | 14245 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14246 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14247 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14248 | primary->plane = !pipe; | |
14249 | ||
6c0fd451 DL |
14250 | if (INTEL_INFO(dev)->gen >= 9) { |
14251 | intel_primary_formats = skl_primary_formats; | |
14252 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14253 | |
14254 | primary->update_plane = skylake_update_primary_plane; | |
14255 | primary->disable_plane = skylake_disable_primary_plane; | |
14256 | } else if (HAS_PCH_SPLIT(dev)) { | |
14257 | intel_primary_formats = i965_primary_formats; | |
14258 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14259 | ||
14260 | primary->update_plane = ironlake_update_primary_plane; | |
14261 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14262 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14263 | intel_primary_formats = i965_primary_formats; |
14264 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14265 | |
14266 | primary->update_plane = i9xx_update_primary_plane; | |
14267 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14268 | } else { |
14269 | intel_primary_formats = i8xx_primary_formats; | |
14270 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14271 | |
14272 | primary->update_plane = i9xx_update_primary_plane; | |
14273 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14274 | } |
14275 | ||
14276 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14277 | &intel_plane_funcs, |
465c120c | 14278 | intel_primary_formats, num_formats, |
b0b3b795 | 14279 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14280 | |
3b7a5119 SJ |
14281 | if (INTEL_INFO(dev)->gen >= 4) |
14282 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14283 | |
ea2c67bb MR |
14284 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14285 | ||
465c120c MR |
14286 | return &primary->base; |
14287 | } | |
14288 | ||
3b7a5119 SJ |
14289 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14290 | { | |
14291 | if (!dev->mode_config.rotation_property) { | |
14292 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14293 | BIT(DRM_ROTATE_180); | |
14294 | ||
14295 | if (INTEL_INFO(dev)->gen >= 9) | |
14296 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14297 | ||
14298 | dev->mode_config.rotation_property = | |
14299 | drm_mode_create_rotation_property(dev, flags); | |
14300 | } | |
14301 | if (dev->mode_config.rotation_property) | |
14302 | drm_object_attach_property(&plane->base.base, | |
14303 | dev->mode_config.rotation_property, | |
14304 | plane->base.state->rotation); | |
14305 | } | |
14306 | ||
3d7d6510 | 14307 | static int |
852e787c | 14308 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14309 | struct intel_crtc_state *crtc_state, |
852e787c | 14310 | struct intel_plane_state *state) |
3d7d6510 | 14311 | { |
061e4b8d | 14312 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14313 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14314 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14315 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14316 | unsigned stride; |
14317 | int ret; | |
3d7d6510 | 14318 | |
061e4b8d ML |
14319 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14320 | &state->dst, &state->clip, | |
3d7d6510 MR |
14321 | DRM_PLANE_HELPER_NO_SCALING, |
14322 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14323 | true, true, &state->visible); |
757f9a3e GP |
14324 | if (ret) |
14325 | return ret; | |
14326 | ||
757f9a3e GP |
14327 | /* if we want to turn off the cursor ignore width and height */ |
14328 | if (!obj) | |
da20eabd | 14329 | return 0; |
757f9a3e | 14330 | |
757f9a3e | 14331 | /* Check for which cursor types we support */ |
061e4b8d | 14332 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14333 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14334 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14335 | return -EINVAL; |
14336 | } | |
14337 | ||
ea2c67bb MR |
14338 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14339 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14340 | DRM_DEBUG_KMS("buffer is too small\n"); |
14341 | return -ENOMEM; | |
14342 | } | |
14343 | ||
3a656b54 | 14344 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14345 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14346 | return -EINVAL; |
32b7eeec MR |
14347 | } |
14348 | ||
b29ec92c VS |
14349 | /* |
14350 | * There's something wrong with the cursor on CHV pipe C. | |
14351 | * If it straddles the left edge of the screen then | |
14352 | * moving it away from the edge or disabling it often | |
14353 | * results in a pipe underrun, and often that can lead to | |
14354 | * dead pipe (constant underrun reported, and it scans | |
14355 | * out just a solid color). To recover from that, the | |
14356 | * display power well must be turned off and on again. | |
14357 | * Refuse the put the cursor into that compromised position. | |
14358 | */ | |
14359 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14360 | state->visible && state->base.crtc_x < 0) { | |
14361 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14362 | return -EINVAL; | |
14363 | } | |
14364 | ||
da20eabd | 14365 | return 0; |
852e787c | 14366 | } |
3d7d6510 | 14367 | |
a8ad0d8e ML |
14368 | static void |
14369 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14370 | struct drm_crtc *crtc) |
a8ad0d8e | 14371 | { |
f2858021 ML |
14372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14373 | ||
14374 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14375 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14376 | } |
14377 | ||
f4a2cf29 | 14378 | static void |
55a08b3f ML |
14379 | intel_update_cursor_plane(struct drm_plane *plane, |
14380 | const struct intel_crtc_state *crtc_state, | |
14381 | const struct intel_plane_state *state) | |
852e787c | 14382 | { |
55a08b3f ML |
14383 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14385 | struct drm_device *dev = plane->dev; |
2b875c22 | 14386 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14387 | uint32_t addr; |
852e787c | 14388 | |
f4a2cf29 | 14389 | if (!obj) |
a912f12f | 14390 | addr = 0; |
f4a2cf29 | 14391 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14392 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14393 | else |
a912f12f | 14394 | addr = obj->phys_handle->busaddr; |
852e787c | 14395 | |
a912f12f | 14396 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14397 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14398 | } |
14399 | ||
3d7d6510 MR |
14400 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14401 | int pipe) | |
14402 | { | |
14403 | struct intel_plane *cursor; | |
8e7d688b | 14404 | struct intel_plane_state *state; |
3d7d6510 MR |
14405 | |
14406 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14407 | if (cursor == NULL) | |
14408 | return NULL; | |
14409 | ||
8e7d688b MR |
14410 | state = intel_create_plane_state(&cursor->base); |
14411 | if (!state) { | |
ea2c67bb MR |
14412 | kfree(cursor); |
14413 | return NULL; | |
14414 | } | |
8e7d688b | 14415 | cursor->base.state = &state->base; |
ea2c67bb | 14416 | |
3d7d6510 MR |
14417 | cursor->can_scale = false; |
14418 | cursor->max_downscale = 1; | |
14419 | cursor->pipe = pipe; | |
14420 | cursor->plane = pipe; | |
a9ff8714 | 14421 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14422 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14423 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14424 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14425 | |
14426 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14427 | &intel_plane_funcs, |
3d7d6510 MR |
14428 | intel_cursor_formats, |
14429 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14430 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14431 | |
14432 | if (INTEL_INFO(dev)->gen >= 4) { | |
14433 | if (!dev->mode_config.rotation_property) | |
14434 | dev->mode_config.rotation_property = | |
14435 | drm_mode_create_rotation_property(dev, | |
14436 | BIT(DRM_ROTATE_0) | | |
14437 | BIT(DRM_ROTATE_180)); | |
14438 | if (dev->mode_config.rotation_property) | |
14439 | drm_object_attach_property(&cursor->base.base, | |
14440 | dev->mode_config.rotation_property, | |
8e7d688b | 14441 | state->base.rotation); |
4398ad45 VS |
14442 | } |
14443 | ||
af99ceda CK |
14444 | if (INTEL_INFO(dev)->gen >=9) |
14445 | state->scaler_id = -1; | |
14446 | ||
ea2c67bb MR |
14447 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14448 | ||
3d7d6510 MR |
14449 | return &cursor->base; |
14450 | } | |
14451 | ||
549e2bfb CK |
14452 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14453 | struct intel_crtc_state *crtc_state) | |
14454 | { | |
14455 | int i; | |
14456 | struct intel_scaler *intel_scaler; | |
14457 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14458 | ||
14459 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14460 | intel_scaler = &scaler_state->scalers[i]; | |
14461 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14462 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14463 | } | |
14464 | ||
14465 | scaler_state->scaler_id = -1; | |
14466 | } | |
14467 | ||
b358d0a6 | 14468 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14469 | { |
fbee40df | 14470 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14471 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14472 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14473 | struct drm_plane *primary = NULL; |
14474 | struct drm_plane *cursor = NULL; | |
465c120c | 14475 | int i, ret; |
79e53945 | 14476 | |
955382f3 | 14477 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14478 | if (intel_crtc == NULL) |
14479 | return; | |
14480 | ||
f5de6e07 ACO |
14481 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14482 | if (!crtc_state) | |
14483 | goto fail; | |
550acefd ACO |
14484 | intel_crtc->config = crtc_state; |
14485 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14486 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14487 | |
549e2bfb CK |
14488 | /* initialize shared scalers */ |
14489 | if (INTEL_INFO(dev)->gen >= 9) { | |
14490 | if (pipe == PIPE_C) | |
14491 | intel_crtc->num_scalers = 1; | |
14492 | else | |
14493 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14494 | ||
14495 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14496 | } | |
14497 | ||
465c120c | 14498 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14499 | if (!primary) |
14500 | goto fail; | |
14501 | ||
14502 | cursor = intel_cursor_plane_create(dev, pipe); | |
14503 | if (!cursor) | |
14504 | goto fail; | |
14505 | ||
465c120c | 14506 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14507 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14508 | if (ret) |
14509 | goto fail; | |
79e53945 JB |
14510 | |
14511 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14512 | for (i = 0; i < 256; i++) { |
14513 | intel_crtc->lut_r[i] = i; | |
14514 | intel_crtc->lut_g[i] = i; | |
14515 | intel_crtc->lut_b[i] = i; | |
14516 | } | |
14517 | ||
1f1c2e24 VS |
14518 | /* |
14519 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14520 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14521 | */ |
80824003 JB |
14522 | intel_crtc->pipe = pipe; |
14523 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14524 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14525 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14526 | intel_crtc->plane = !pipe; |
80824003 JB |
14527 | } |
14528 | ||
4b0e333e CW |
14529 | intel_crtc->cursor_base = ~0; |
14530 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14531 | intel_crtc->cursor_size = ~0; |
8d7849db | 14532 | |
852eb00d VS |
14533 | intel_crtc->wm.cxsr_allowed = true; |
14534 | ||
22fd0fab JB |
14535 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14536 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14537 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14538 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14539 | ||
79e53945 | 14540 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14541 | |
14542 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14543 | return; |
14544 | ||
14545 | fail: | |
14546 | if (primary) | |
14547 | drm_plane_cleanup(primary); | |
14548 | if (cursor) | |
14549 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14550 | kfree(crtc_state); |
3d7d6510 | 14551 | kfree(intel_crtc); |
79e53945 JB |
14552 | } |
14553 | ||
752aa88a JB |
14554 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14555 | { | |
14556 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14557 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14558 | |
51fd371b | 14559 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14560 | |
d3babd3f | 14561 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14562 | return INVALID_PIPE; |
14563 | ||
14564 | return to_intel_crtc(encoder->crtc)->pipe; | |
14565 | } | |
14566 | ||
08d7b3d1 | 14567 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14568 | struct drm_file *file) |
08d7b3d1 | 14569 | { |
08d7b3d1 | 14570 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14571 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14572 | struct intel_crtc *crtc; |
08d7b3d1 | 14573 | |
7707e653 | 14574 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14575 | |
7707e653 | 14576 | if (!drmmode_crtc) { |
08d7b3d1 | 14577 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14578 | return -ENOENT; |
08d7b3d1 CW |
14579 | } |
14580 | ||
7707e653 | 14581 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14582 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14583 | |
c05422d5 | 14584 | return 0; |
08d7b3d1 CW |
14585 | } |
14586 | ||
66a9278e | 14587 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14588 | { |
66a9278e DV |
14589 | struct drm_device *dev = encoder->base.dev; |
14590 | struct intel_encoder *source_encoder; | |
79e53945 | 14591 | int index_mask = 0; |
79e53945 JB |
14592 | int entry = 0; |
14593 | ||
b2784e15 | 14594 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14595 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14596 | index_mask |= (1 << entry); |
14597 | ||
79e53945 JB |
14598 | entry++; |
14599 | } | |
4ef69c7a | 14600 | |
79e53945 JB |
14601 | return index_mask; |
14602 | } | |
14603 | ||
4d302442 CW |
14604 | static bool has_edp_a(struct drm_device *dev) |
14605 | { | |
14606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14607 | ||
14608 | if (!IS_MOBILE(dev)) | |
14609 | return false; | |
14610 | ||
14611 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14612 | return false; | |
14613 | ||
e3589908 | 14614 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14615 | return false; |
14616 | ||
14617 | return true; | |
14618 | } | |
14619 | ||
84b4e042 JB |
14620 | static bool intel_crt_present(struct drm_device *dev) |
14621 | { | |
14622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14623 | ||
884497ed DL |
14624 | if (INTEL_INFO(dev)->gen >= 9) |
14625 | return false; | |
14626 | ||
cf404ce4 | 14627 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14628 | return false; |
14629 | ||
14630 | if (IS_CHERRYVIEW(dev)) | |
14631 | return false; | |
14632 | ||
65e472e4 VS |
14633 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14634 | return false; | |
14635 | ||
70ac54d0 VS |
14636 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14637 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14638 | return false; | |
14639 | ||
e4abb733 | 14640 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14641 | return false; |
14642 | ||
14643 | return true; | |
14644 | } | |
14645 | ||
79e53945 JB |
14646 | static void intel_setup_outputs(struct drm_device *dev) |
14647 | { | |
725e30ad | 14648 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14649 | struct intel_encoder *encoder; |
cb0953d7 | 14650 | bool dpd_is_edp = false; |
79e53945 | 14651 | |
c9093354 | 14652 | intel_lvds_init(dev); |
79e53945 | 14653 | |
84b4e042 | 14654 | if (intel_crt_present(dev)) |
79935fca | 14655 | intel_crt_init(dev); |
cb0953d7 | 14656 | |
c776eb2e VK |
14657 | if (IS_BROXTON(dev)) { |
14658 | /* | |
14659 | * FIXME: Broxton doesn't support port detection via the | |
14660 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14661 | * detect the ports. | |
14662 | */ | |
14663 | intel_ddi_init(dev, PORT_A); | |
14664 | intel_ddi_init(dev, PORT_B); | |
14665 | intel_ddi_init(dev, PORT_C); | |
14666 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14667 | int found; |
14668 | ||
de31facd JB |
14669 | /* |
14670 | * Haswell uses DDI functions to detect digital outputs. | |
14671 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14672 | * it's there. | |
14673 | */ | |
77179400 | 14674 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14675 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14676 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14677 | intel_ddi_init(dev, PORT_A); |
14678 | ||
14679 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14680 | * register */ | |
14681 | found = I915_READ(SFUSE_STRAP); | |
14682 | ||
14683 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14684 | intel_ddi_init(dev, PORT_B); | |
14685 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14686 | intel_ddi_init(dev, PORT_C); | |
14687 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14688 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14689 | /* |
14690 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14691 | */ | |
ef11bdb3 | 14692 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14693 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14694 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14695 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14696 | intel_ddi_init(dev, PORT_E); | |
14697 | ||
0e72a5b5 | 14698 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14699 | int found; |
5d8a7752 | 14700 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14701 | |
14702 | if (has_edp_a(dev)) | |
14703 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14704 | |
dc0fa718 | 14705 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14706 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14707 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14708 | if (!found) |
e2debe91 | 14709 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14710 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14711 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14712 | } |
14713 | ||
dc0fa718 | 14714 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14715 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14716 | |
dc0fa718 | 14717 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14718 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14719 | |
5eb08b69 | 14720 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14721 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14722 | |
270b3042 | 14723 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14724 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14725 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14726 | /* |
14727 | * The DP_DETECTED bit is the latched state of the DDC | |
14728 | * SDA pin at boot. However since eDP doesn't require DDC | |
14729 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14730 | * eDP ports may have been muxed to an alternate function. | |
14731 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14732 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14733 | * detect eDP ports. | |
14734 | */ | |
e66eb81d | 14735 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14736 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14737 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14738 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14739 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14740 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14741 | |
e66eb81d | 14742 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14743 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14744 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14745 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14746 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14747 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14748 | |
9418c1f1 | 14749 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14750 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14751 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14752 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14753 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14754 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14755 | } |
14756 | ||
3cfca973 | 14757 | intel_dsi_init(dev); |
09da55dc | 14758 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14759 | bool found = false; |
7d57382e | 14760 | |
e2debe91 | 14761 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14762 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14763 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14764 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14765 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14766 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14767 | } |
27185ae1 | 14768 | |
3fec3d2f | 14769 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14770 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14771 | } |
13520b05 KH |
14772 | |
14773 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14774 | |
e2debe91 | 14775 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14776 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14777 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14778 | } |
27185ae1 | 14779 | |
e2debe91 | 14780 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14781 | |
3fec3d2f | 14782 | if (IS_G4X(dev)) { |
b01f2c3a | 14783 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14784 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14785 | } |
3fec3d2f | 14786 | if (IS_G4X(dev)) |
ab9d7c30 | 14787 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14788 | } |
27185ae1 | 14789 | |
3fec3d2f | 14790 | if (IS_G4X(dev) && |
e7281eab | 14791 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14792 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14793 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14794 | intel_dvo_init(dev); |
14795 | ||
103a196f | 14796 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14797 | intel_tv_init(dev); |
14798 | ||
0bc12bcb | 14799 | intel_psr_init(dev); |
7c8f8a70 | 14800 | |
b2784e15 | 14801 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14802 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14803 | encoder->base.possible_clones = | |
66a9278e | 14804 | intel_encoder_clones(encoder); |
79e53945 | 14805 | } |
47356eb6 | 14806 | |
dde86e2d | 14807 | intel_init_pch_refclk(dev); |
270b3042 DV |
14808 | |
14809 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14810 | } |
14811 | ||
14812 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14813 | { | |
60a5ca01 | 14814 | struct drm_device *dev = fb->dev; |
79e53945 | 14815 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14816 | |
ef2d633e | 14817 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14818 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14819 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14820 | drm_gem_object_unreference(&intel_fb->obj->base); |
14821 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14822 | kfree(intel_fb); |
14823 | } | |
14824 | ||
14825 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14826 | struct drm_file *file, |
79e53945 JB |
14827 | unsigned int *handle) |
14828 | { | |
14829 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14830 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14831 | |
cc917ab4 CW |
14832 | if (obj->userptr.mm) { |
14833 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14834 | return -EINVAL; | |
14835 | } | |
14836 | ||
05394f39 | 14837 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14838 | } |
14839 | ||
86c98588 RV |
14840 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14841 | struct drm_file *file, | |
14842 | unsigned flags, unsigned color, | |
14843 | struct drm_clip_rect *clips, | |
14844 | unsigned num_clips) | |
14845 | { | |
14846 | struct drm_device *dev = fb->dev; | |
14847 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14848 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14849 | ||
14850 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14851 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14852 | mutex_unlock(&dev->struct_mutex); |
14853 | ||
14854 | return 0; | |
14855 | } | |
14856 | ||
79e53945 JB |
14857 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14858 | .destroy = intel_user_framebuffer_destroy, | |
14859 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14860 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14861 | }; |
14862 | ||
b321803d DL |
14863 | static |
14864 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14865 | uint32_t pixel_format) | |
14866 | { | |
14867 | u32 gen = INTEL_INFO(dev)->gen; | |
14868 | ||
14869 | if (gen >= 9) { | |
ac484963 VS |
14870 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14871 | ||
b321803d DL |
14872 | /* "The stride in bytes must not exceed the of the size of 8K |
14873 | * pixels and 32K bytes." | |
14874 | */ | |
ac484963 | 14875 | return min(8192 * cpp, 32768); |
666a4537 | 14876 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14877 | return 32*1024; |
14878 | } else if (gen >= 4) { | |
14879 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14880 | return 16*1024; | |
14881 | else | |
14882 | return 32*1024; | |
14883 | } else if (gen >= 3) { | |
14884 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14885 | return 8*1024; | |
14886 | else | |
14887 | return 16*1024; | |
14888 | } else { | |
14889 | /* XXX DSPC is limited to 4k tiled */ | |
14890 | return 8*1024; | |
14891 | } | |
14892 | } | |
14893 | ||
b5ea642a DV |
14894 | static int intel_framebuffer_init(struct drm_device *dev, |
14895 | struct intel_framebuffer *intel_fb, | |
14896 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14897 | struct drm_i915_gem_object *obj) | |
79e53945 | 14898 | { |
7b49f948 | 14899 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14900 | unsigned int aligned_height; |
79e53945 | 14901 | int ret; |
b321803d | 14902 | u32 pitch_limit, stride_alignment; |
79e53945 | 14903 | |
dd4916c5 DV |
14904 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14905 | ||
2a80eada DV |
14906 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14907 | /* Enforce that fb modifier and tiling mode match, but only for | |
14908 | * X-tiled. This is needed for FBC. */ | |
14909 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14910 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14911 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14912 | return -EINVAL; | |
14913 | } | |
14914 | } else { | |
14915 | if (obj->tiling_mode == I915_TILING_X) | |
14916 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14917 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14918 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14919 | return -EINVAL; | |
14920 | } | |
14921 | } | |
14922 | ||
9a8f0a12 TU |
14923 | /* Passed in modifier sanity checking. */ |
14924 | switch (mode_cmd->modifier[0]) { | |
14925 | case I915_FORMAT_MOD_Y_TILED: | |
14926 | case I915_FORMAT_MOD_Yf_TILED: | |
14927 | if (INTEL_INFO(dev)->gen < 9) { | |
14928 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14929 | mode_cmd->modifier[0]); | |
14930 | return -EINVAL; | |
14931 | } | |
14932 | case DRM_FORMAT_MOD_NONE: | |
14933 | case I915_FORMAT_MOD_X_TILED: | |
14934 | break; | |
14935 | default: | |
c0f40428 JB |
14936 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14937 | mode_cmd->modifier[0]); | |
57cd6508 | 14938 | return -EINVAL; |
c16ed4be | 14939 | } |
57cd6508 | 14940 | |
7b49f948 VS |
14941 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14942 | mode_cmd->modifier[0], | |
b321803d DL |
14943 | mode_cmd->pixel_format); |
14944 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14945 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14946 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14947 | return -EINVAL; |
c16ed4be | 14948 | } |
57cd6508 | 14949 | |
b321803d DL |
14950 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14951 | mode_cmd->pixel_format); | |
a35cdaa0 | 14952 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14953 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14954 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14955 | "tiled" : "linear", |
a35cdaa0 | 14956 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14957 | return -EINVAL; |
c16ed4be | 14958 | } |
5d7bd705 | 14959 | |
2a80eada | 14960 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14961 | mode_cmd->pitches[0] != obj->stride) { |
14962 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14963 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14964 | return -EINVAL; |
c16ed4be | 14965 | } |
5d7bd705 | 14966 | |
57779d06 | 14967 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14968 | switch (mode_cmd->pixel_format) { |
57779d06 | 14969 | case DRM_FORMAT_C8: |
04b3924d VS |
14970 | case DRM_FORMAT_RGB565: |
14971 | case DRM_FORMAT_XRGB8888: | |
14972 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14973 | break; |
14974 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14975 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14976 | DRM_DEBUG("unsupported pixel format: %s\n", |
14977 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14978 | return -EINVAL; |
c16ed4be | 14979 | } |
57779d06 | 14980 | break; |
57779d06 | 14981 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14982 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14983 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14984 | DRM_DEBUG("unsupported pixel format: %s\n", |
14985 | drm_get_format_name(mode_cmd->pixel_format)); | |
14986 | return -EINVAL; | |
14987 | } | |
14988 | break; | |
14989 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14990 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14991 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14992 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14993 | DRM_DEBUG("unsupported pixel format: %s\n", |
14994 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14995 | return -EINVAL; |
c16ed4be | 14996 | } |
b5626747 | 14997 | break; |
7531208b | 14998 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14999 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
15000 | DRM_DEBUG("unsupported pixel format: %s\n", |
15001 | drm_get_format_name(mode_cmd->pixel_format)); | |
15002 | return -EINVAL; | |
15003 | } | |
15004 | break; | |
04b3924d VS |
15005 | case DRM_FORMAT_YUYV: |
15006 | case DRM_FORMAT_UYVY: | |
15007 | case DRM_FORMAT_YVYU: | |
15008 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15009 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
15010 | DRM_DEBUG("unsupported pixel format: %s\n", |
15011 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 15012 | return -EINVAL; |
c16ed4be | 15013 | } |
57cd6508 CW |
15014 | break; |
15015 | default: | |
4ee62c76 VS |
15016 | DRM_DEBUG("unsupported pixel format: %s\n", |
15017 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
15018 | return -EINVAL; |
15019 | } | |
15020 | ||
90f9a336 VS |
15021 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15022 | if (mode_cmd->offsets[0] != 0) | |
15023 | return -EINVAL; | |
15024 | ||
ec2c981e | 15025 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
15026 | mode_cmd->pixel_format, |
15027 | mode_cmd->modifier[0]); | |
53155c0a DV |
15028 | /* FIXME drm helper for size checks (especially planar formats)? */ |
15029 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
15030 | return -EINVAL; | |
15031 | ||
c7d73f6a DV |
15032 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15033 | intel_fb->obj = obj; | |
15034 | ||
2d7a215f VS |
15035 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
15036 | ||
79e53945 JB |
15037 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15038 | if (ret) { | |
15039 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15040 | return ret; | |
15041 | } | |
15042 | ||
0b05e1e0 VS |
15043 | intel_fb->obj->framebuffer_references++; |
15044 | ||
79e53945 JB |
15045 | return 0; |
15046 | } | |
15047 | ||
79e53945 JB |
15048 | static struct drm_framebuffer * |
15049 | intel_user_framebuffer_create(struct drm_device *dev, | |
15050 | struct drm_file *filp, | |
1eb83451 | 15051 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15052 | { |
dcb1394e | 15053 | struct drm_framebuffer *fb; |
05394f39 | 15054 | struct drm_i915_gem_object *obj; |
76dc3769 | 15055 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15056 | |
308e5bcb | 15057 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 15058 | mode_cmd.handles[0])); |
c8725226 | 15059 | if (&obj->base == NULL) |
cce13ff7 | 15060 | return ERR_PTR(-ENOENT); |
79e53945 | 15061 | |
92907cbb | 15062 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
15063 | if (IS_ERR(fb)) |
15064 | drm_gem_object_unreference_unlocked(&obj->base); | |
15065 | ||
15066 | return fb; | |
79e53945 JB |
15067 | } |
15068 | ||
0695726e | 15069 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 15070 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
15071 | { |
15072 | } | |
15073 | #endif | |
15074 | ||
79e53945 | 15075 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15076 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15077 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15078 | .atomic_check = intel_atomic_check, |
15079 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15080 | .atomic_state_alloc = intel_atomic_state_alloc, |
15081 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15082 | }; |
15083 | ||
e70236a8 JB |
15084 | /* Set up chip specific display functions */ |
15085 | static void intel_init_display(struct drm_device *dev) | |
15086 | { | |
15087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15088 | ||
ee9300bb DV |
15089 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
15090 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
15091 | else if (IS_CHERRYVIEW(dev)) |
15092 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
15093 | else if (IS_VALLEYVIEW(dev)) |
15094 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
15095 | else if (IS_PINEVIEW(dev)) | |
15096 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
15097 | else | |
15098 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
15099 | ||
bc8d7dff DL |
15100 | if (INTEL_INFO(dev)->gen >= 9) { |
15101 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
15102 | dev_priv->display.get_initial_plane_config = |
15103 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15104 | dev_priv->display.crtc_compute_clock = |
15105 | haswell_crtc_compute_clock; | |
15106 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15107 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 15108 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 15109 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15110 | dev_priv->display.get_initial_plane_config = |
15111 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15112 | dev_priv->display.crtc_compute_clock = |
15113 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15114 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15115 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 15116 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 15117 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15118 | dev_priv->display.get_initial_plane_config = |
15119 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15120 | dev_priv->display.crtc_compute_clock = |
15121 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15122 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15123 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 15124 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 15125 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15126 | dev_priv->display.get_initial_plane_config = |
15127 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15128 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
15129 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15130 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15131 | } else { |
0e8ffe1b | 15132 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15133 | dev_priv->display.get_initial_plane_config = |
15134 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15135 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15136 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15137 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15138 | } |
e70236a8 | 15139 | |
e70236a8 | 15140 | /* Returns the core display clock speed */ |
ef11bdb3 | 15141 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
15142 | dev_priv->display.get_display_clock_speed = |
15143 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
15144 | else if (IS_BROXTON(dev)) |
15145 | dev_priv->display.get_display_clock_speed = | |
15146 | broxton_get_display_clock_speed; | |
1652d19e VS |
15147 | else if (IS_BROADWELL(dev)) |
15148 | dev_priv->display.get_display_clock_speed = | |
15149 | broadwell_get_display_clock_speed; | |
15150 | else if (IS_HASWELL(dev)) | |
15151 | dev_priv->display.get_display_clock_speed = | |
15152 | haswell_get_display_clock_speed; | |
666a4537 | 15153 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
15154 | dev_priv->display.get_display_clock_speed = |
15155 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
15156 | else if (IS_GEN5(dev)) |
15157 | dev_priv->display.get_display_clock_speed = | |
15158 | ilk_get_display_clock_speed; | |
a7c66cd8 | 15159 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 15160 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
15161 | dev_priv->display.get_display_clock_speed = |
15162 | i945_get_display_clock_speed; | |
34edce2f VS |
15163 | else if (IS_GM45(dev)) |
15164 | dev_priv->display.get_display_clock_speed = | |
15165 | gm45_get_display_clock_speed; | |
15166 | else if (IS_CRESTLINE(dev)) | |
15167 | dev_priv->display.get_display_clock_speed = | |
15168 | i965gm_get_display_clock_speed; | |
15169 | else if (IS_PINEVIEW(dev)) | |
15170 | dev_priv->display.get_display_clock_speed = | |
15171 | pnv_get_display_clock_speed; | |
15172 | else if (IS_G33(dev) || IS_G4X(dev)) | |
15173 | dev_priv->display.get_display_clock_speed = | |
15174 | g33_get_display_clock_speed; | |
e70236a8 JB |
15175 | else if (IS_I915G(dev)) |
15176 | dev_priv->display.get_display_clock_speed = | |
15177 | i915_get_display_clock_speed; | |
257a7ffc | 15178 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
15179 | dev_priv->display.get_display_clock_speed = |
15180 | i9xx_misc_get_display_clock_speed; | |
15181 | else if (IS_I915GM(dev)) | |
15182 | dev_priv->display.get_display_clock_speed = | |
15183 | i915gm_get_display_clock_speed; | |
15184 | else if (IS_I865G(dev)) | |
15185 | dev_priv->display.get_display_clock_speed = | |
15186 | i865_get_display_clock_speed; | |
f0f8a9ce | 15187 | else if (IS_I85X(dev)) |
e70236a8 | 15188 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15189 | i85x_get_display_clock_speed; |
623e01e5 VS |
15190 | else { /* 830 */ |
15191 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15192 | dev_priv->display.get_display_clock_speed = |
15193 | i830_get_display_clock_speed; | |
623e01e5 | 15194 | } |
e70236a8 | 15195 | |
7c10a2b5 | 15196 | if (IS_GEN5(dev)) { |
3bb11b53 | 15197 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15198 | } else if (IS_GEN6(dev)) { |
15199 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15200 | } else if (IS_IVYBRIDGE(dev)) { |
15201 | /* FIXME: detect B0+ stepping and use auto training */ | |
15202 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15203 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15204 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15205 | if (IS_BROADWELL(dev)) { |
15206 | dev_priv->display.modeset_commit_cdclk = | |
15207 | broadwell_modeset_commit_cdclk; | |
15208 | dev_priv->display.modeset_calc_cdclk = | |
15209 | broadwell_modeset_calc_cdclk; | |
15210 | } | |
666a4537 | 15211 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15212 | dev_priv->display.modeset_commit_cdclk = |
15213 | valleyview_modeset_commit_cdclk; | |
15214 | dev_priv->display.modeset_calc_cdclk = | |
15215 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15216 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15217 | dev_priv->display.modeset_commit_cdclk = |
15218 | broxton_modeset_commit_cdclk; | |
15219 | dev_priv->display.modeset_calc_cdclk = | |
15220 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15221 | } |
8c9f3aaf | 15222 | |
8c9f3aaf JB |
15223 | switch (INTEL_INFO(dev)->gen) { |
15224 | case 2: | |
15225 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15226 | break; | |
15227 | ||
15228 | case 3: | |
15229 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15230 | break; | |
15231 | ||
15232 | case 4: | |
15233 | case 5: | |
15234 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15235 | break; | |
15236 | ||
15237 | case 6: | |
15238 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15239 | break; | |
7c9017e5 | 15240 | case 7: |
4e0bbc31 | 15241 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15242 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15243 | break; | |
830c81db | 15244 | case 9: |
ba343e02 TU |
15245 | /* Drop through - unsupported since execlist only. */ |
15246 | default: | |
15247 | /* Default just returns -ENODEV to indicate unsupported */ | |
15248 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15249 | } |
7bd688cd | 15250 | |
e39b999a | 15251 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15252 | } |
15253 | ||
b690e96c JB |
15254 | /* |
15255 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15256 | * resume, or other times. This quirk makes sure that's the case for | |
15257 | * affected systems. | |
15258 | */ | |
0206e353 | 15259 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15260 | { |
15261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15262 | ||
15263 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15264 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15265 | } |
15266 | ||
b6b5d049 VS |
15267 | static void quirk_pipeb_force(struct drm_device *dev) |
15268 | { | |
15269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15270 | ||
15271 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15272 | DRM_INFO("applying pipe b force quirk\n"); | |
15273 | } | |
15274 | ||
435793df KP |
15275 | /* |
15276 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15277 | */ | |
15278 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15279 | { | |
15280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15281 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15282 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15283 | } |
15284 | ||
4dca20ef | 15285 | /* |
5a15ab5b CE |
15286 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15287 | * brightness value | |
4dca20ef CE |
15288 | */ |
15289 | static void quirk_invert_brightness(struct drm_device *dev) | |
15290 | { | |
15291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15292 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15293 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15294 | } |
15295 | ||
9c72cc6f SD |
15296 | /* Some VBT's incorrectly indicate no backlight is present */ |
15297 | static void quirk_backlight_present(struct drm_device *dev) | |
15298 | { | |
15299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15300 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15301 | DRM_INFO("applying backlight present quirk\n"); | |
15302 | } | |
15303 | ||
b690e96c JB |
15304 | struct intel_quirk { |
15305 | int device; | |
15306 | int subsystem_vendor; | |
15307 | int subsystem_device; | |
15308 | void (*hook)(struct drm_device *dev); | |
15309 | }; | |
15310 | ||
5f85f176 EE |
15311 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15312 | struct intel_dmi_quirk { | |
15313 | void (*hook)(struct drm_device *dev); | |
15314 | const struct dmi_system_id (*dmi_id_list)[]; | |
15315 | }; | |
15316 | ||
15317 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15318 | { | |
15319 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15320 | return 1; | |
15321 | } | |
15322 | ||
15323 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15324 | { | |
15325 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15326 | { | |
15327 | .callback = intel_dmi_reverse_brightness, | |
15328 | .ident = "NCR Corporation", | |
15329 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15330 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15331 | }, | |
15332 | }, | |
15333 | { } /* terminating entry */ | |
15334 | }, | |
15335 | .hook = quirk_invert_brightness, | |
15336 | }, | |
15337 | }; | |
15338 | ||
c43b5634 | 15339 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15340 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15341 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15342 | ||
b690e96c JB |
15343 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15344 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15345 | ||
5f080c0f VS |
15346 | /* 830 needs to leave pipe A & dpll A up */ |
15347 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15348 | ||
b6b5d049 VS |
15349 | /* 830 needs to leave pipe B & dpll B up */ |
15350 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15351 | ||
435793df KP |
15352 | /* Lenovo U160 cannot use SSC on LVDS */ |
15353 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15354 | |
15355 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15356 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15357 | |
be505f64 AH |
15358 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15359 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15360 | ||
15361 | /* Acer/eMachines G725 */ | |
15362 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15363 | ||
15364 | /* Acer/eMachines e725 */ | |
15365 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15366 | ||
15367 | /* Acer/Packard Bell NCL20 */ | |
15368 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15369 | ||
15370 | /* Acer Aspire 4736Z */ | |
15371 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15372 | |
15373 | /* Acer Aspire 5336 */ | |
15374 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15375 | |
15376 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15377 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15378 | |
dfb3d47b SD |
15379 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15380 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15381 | ||
b2a9601c | 15382 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15383 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15384 | ||
1b9448b0 JN |
15385 | /* Apple Macbook 4,1 */ |
15386 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15387 | ||
d4967d8c SD |
15388 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15389 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15390 | |
15391 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15392 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15393 | |
15394 | /* Dell Chromebook 11 */ | |
15395 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15396 | |
15397 | /* Dell Chromebook 11 (2015 version) */ | |
15398 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15399 | }; |
15400 | ||
15401 | static void intel_init_quirks(struct drm_device *dev) | |
15402 | { | |
15403 | struct pci_dev *d = dev->pdev; | |
15404 | int i; | |
15405 | ||
15406 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15407 | struct intel_quirk *q = &intel_quirks[i]; | |
15408 | ||
15409 | if (d->device == q->device && | |
15410 | (d->subsystem_vendor == q->subsystem_vendor || | |
15411 | q->subsystem_vendor == PCI_ANY_ID) && | |
15412 | (d->subsystem_device == q->subsystem_device || | |
15413 | q->subsystem_device == PCI_ANY_ID)) | |
15414 | q->hook(dev); | |
15415 | } | |
5f85f176 EE |
15416 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15417 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15418 | intel_dmi_quirks[i].hook(dev); | |
15419 | } | |
b690e96c JB |
15420 | } |
15421 | ||
9cce37f4 JB |
15422 | /* Disable the VGA plane that we never use */ |
15423 | static void i915_disable_vga(struct drm_device *dev) | |
15424 | { | |
15425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15426 | u8 sr1; | |
f0f59a00 | 15427 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15428 | |
2b37c616 | 15429 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15430 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15431 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15432 | sr1 = inb(VGA_SR_DATA); |
15433 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15434 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15435 | udelay(300); | |
15436 | ||
01f5a626 | 15437 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15438 | POSTING_READ(vga_reg); |
15439 | } | |
15440 | ||
f817586c DV |
15441 | void intel_modeset_init_hw(struct drm_device *dev) |
15442 | { | |
1a617b77 ML |
15443 | struct drm_i915_private *dev_priv = dev->dev_private; |
15444 | ||
b6283055 | 15445 | intel_update_cdclk(dev); |
1a617b77 ML |
15446 | |
15447 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15448 | ||
f817586c | 15449 | intel_init_clock_gating(dev); |
8090c6b9 | 15450 | intel_enable_gt_powersave(dev); |
f817586c DV |
15451 | } |
15452 | ||
d93c0372 MR |
15453 | /* |
15454 | * Calculate what we think the watermarks should be for the state we've read | |
15455 | * out of the hardware and then immediately program those watermarks so that | |
15456 | * we ensure the hardware settings match our internal state. | |
15457 | * | |
15458 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15459 | * current state (which was constructed during hardware readout) and running it | |
15460 | * through the atomic check code to calculate new watermark values in the | |
15461 | * state object. | |
15462 | */ | |
15463 | static void sanitize_watermarks(struct drm_device *dev) | |
15464 | { | |
15465 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15466 | struct drm_atomic_state *state; | |
15467 | struct drm_crtc *crtc; | |
15468 | struct drm_crtc_state *cstate; | |
15469 | struct drm_modeset_acquire_ctx ctx; | |
15470 | int ret; | |
15471 | int i; | |
15472 | ||
15473 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15474 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15475 | return; |
15476 | ||
15477 | /* | |
15478 | * We need to hold connection_mutex before calling duplicate_state so | |
15479 | * that the connector loop is protected. | |
15480 | */ | |
15481 | drm_modeset_acquire_init(&ctx, 0); | |
15482 | retry: | |
0cd1262d | 15483 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15484 | if (ret == -EDEADLK) { |
15485 | drm_modeset_backoff(&ctx); | |
15486 | goto retry; | |
15487 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15488 | goto fail; |
d93c0372 MR |
15489 | } |
15490 | ||
15491 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15492 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15493 | goto fail; |
d93c0372 | 15494 | |
ed4a6a7c MR |
15495 | /* |
15496 | * Hardware readout is the only time we don't want to calculate | |
15497 | * intermediate watermarks (since we don't trust the current | |
15498 | * watermarks). | |
15499 | */ | |
15500 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15501 | ||
d93c0372 MR |
15502 | ret = intel_atomic_check(dev, state); |
15503 | if (ret) { | |
15504 | /* | |
15505 | * If we fail here, it means that the hardware appears to be | |
15506 | * programmed in a way that shouldn't be possible, given our | |
15507 | * understanding of watermark requirements. This might mean a | |
15508 | * mistake in the hardware readout code or a mistake in the | |
15509 | * watermark calculations for a given platform. Raise a WARN | |
15510 | * so that this is noticeable. | |
15511 | * | |
15512 | * If this actually happens, we'll have to just leave the | |
15513 | * BIOS-programmed watermarks untouched and hope for the best. | |
15514 | */ | |
15515 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15516 | goto fail; |
d93c0372 MR |
15517 | } |
15518 | ||
15519 | /* Write calculated watermark values back */ | |
15520 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15521 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15522 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15523 | ||
ed4a6a7c MR |
15524 | cs->wm.need_postvbl_update = true; |
15525 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15526 | } |
15527 | ||
15528 | drm_atomic_state_free(state); | |
0cd1262d | 15529 | fail: |
d93c0372 MR |
15530 | drm_modeset_drop_locks(&ctx); |
15531 | drm_modeset_acquire_fini(&ctx); | |
15532 | } | |
15533 | ||
79e53945 JB |
15534 | void intel_modeset_init(struct drm_device *dev) |
15535 | { | |
652c393a | 15536 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15537 | int sprite, ret; |
8cc87b75 | 15538 | enum pipe pipe; |
46f297fb | 15539 | struct intel_crtc *crtc; |
79e53945 JB |
15540 | |
15541 | drm_mode_config_init(dev); | |
15542 | ||
15543 | dev->mode_config.min_width = 0; | |
15544 | dev->mode_config.min_height = 0; | |
15545 | ||
019d96cb DA |
15546 | dev->mode_config.preferred_depth = 24; |
15547 | dev->mode_config.prefer_shadow = 1; | |
15548 | ||
25bab385 TU |
15549 | dev->mode_config.allow_fb_modifiers = true; |
15550 | ||
e6ecefaa | 15551 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15552 | |
b690e96c JB |
15553 | intel_init_quirks(dev); |
15554 | ||
1fa61106 ED |
15555 | intel_init_pm(dev); |
15556 | ||
e3c74757 BW |
15557 | if (INTEL_INFO(dev)->num_pipes == 0) |
15558 | return; | |
15559 | ||
69f92f67 LW |
15560 | /* |
15561 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15562 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15563 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15564 | * indicates as much. | |
15565 | */ | |
15566 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15567 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15568 | DREF_SSC1_ENABLE); | |
15569 | ||
15570 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15571 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15572 | bios_lvds_use_ssc ? "en" : "dis", | |
15573 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15574 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15575 | } | |
15576 | } | |
15577 | ||
e70236a8 | 15578 | intel_init_display(dev); |
7c10a2b5 | 15579 | intel_init_audio(dev); |
e70236a8 | 15580 | |
a6c45cf0 CW |
15581 | if (IS_GEN2(dev)) { |
15582 | dev->mode_config.max_width = 2048; | |
15583 | dev->mode_config.max_height = 2048; | |
15584 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15585 | dev->mode_config.max_width = 4096; |
15586 | dev->mode_config.max_height = 4096; | |
79e53945 | 15587 | } else { |
a6c45cf0 CW |
15588 | dev->mode_config.max_width = 8192; |
15589 | dev->mode_config.max_height = 8192; | |
79e53945 | 15590 | } |
068be561 | 15591 | |
dc41c154 VS |
15592 | if (IS_845G(dev) || IS_I865G(dev)) { |
15593 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15594 | dev->mode_config.cursor_height = 1023; | |
15595 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15596 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15597 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15598 | } else { | |
15599 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15600 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15601 | } | |
15602 | ||
5d4545ae | 15603 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15604 | |
28c97730 | 15605 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15606 | INTEL_INFO(dev)->num_pipes, |
15607 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15608 | |
055e393f | 15609 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15610 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15611 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15612 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15613 | if (ret) |
06da8da2 | 15614 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15615 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15616 | } |
79e53945 JB |
15617 | } |
15618 | ||
bfa7df01 VS |
15619 | intel_update_czclk(dev_priv); |
15620 | intel_update_cdclk(dev); | |
15621 | ||
e72f9fbf | 15622 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15623 | |
9cce37f4 JB |
15624 | /* Just disable it once at startup */ |
15625 | i915_disable_vga(dev); | |
79e53945 | 15626 | intel_setup_outputs(dev); |
11be49eb | 15627 | |
6e9f798d | 15628 | drm_modeset_lock_all(dev); |
043e9bda | 15629 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15630 | drm_modeset_unlock_all(dev); |
46f297fb | 15631 | |
d3fcc808 | 15632 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15633 | struct intel_initial_plane_config plane_config = {}; |
15634 | ||
46f297fb JB |
15635 | if (!crtc->active) |
15636 | continue; | |
15637 | ||
46f297fb | 15638 | /* |
46f297fb JB |
15639 | * Note that reserving the BIOS fb up front prevents us |
15640 | * from stuffing other stolen allocations like the ring | |
15641 | * on top. This prevents some ugliness at boot time, and | |
15642 | * can even allow for smooth boot transitions if the BIOS | |
15643 | * fb is large enough for the active pipe configuration. | |
15644 | */ | |
eeebeac5 ML |
15645 | dev_priv->display.get_initial_plane_config(crtc, |
15646 | &plane_config); | |
15647 | ||
15648 | /* | |
15649 | * If the fb is shared between multiple heads, we'll | |
15650 | * just get the first one. | |
15651 | */ | |
15652 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15653 | } |
d93c0372 MR |
15654 | |
15655 | /* | |
15656 | * Make sure hardware watermarks really match the state we read out. | |
15657 | * Note that we need to do this after reconstructing the BIOS fb's | |
15658 | * since the watermark calculation done here will use pstate->fb. | |
15659 | */ | |
15660 | sanitize_watermarks(dev); | |
2c7111db CW |
15661 | } |
15662 | ||
7fad798e DV |
15663 | static void intel_enable_pipe_a(struct drm_device *dev) |
15664 | { | |
15665 | struct intel_connector *connector; | |
15666 | struct drm_connector *crt = NULL; | |
15667 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15668 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15669 | |
15670 | /* We can't just switch on the pipe A, we need to set things up with a | |
15671 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15672 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15673 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15674 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15675 | crt = &connector->base; | |
15676 | break; | |
15677 | } | |
15678 | } | |
15679 | ||
15680 | if (!crt) | |
15681 | return; | |
15682 | ||
208bf9fd | 15683 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15684 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15685 | } |
15686 | ||
fa555837 DV |
15687 | static bool |
15688 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15689 | { | |
7eb552ae BW |
15690 | struct drm_device *dev = crtc->base.dev; |
15691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15692 | u32 val; |
fa555837 | 15693 | |
7eb552ae | 15694 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15695 | return true; |
15696 | ||
649636ef | 15697 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15698 | |
15699 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15700 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15701 | return false; | |
15702 | ||
15703 | return true; | |
15704 | } | |
15705 | ||
02e93c35 VS |
15706 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15707 | { | |
15708 | struct drm_device *dev = crtc->base.dev; | |
15709 | struct intel_encoder *encoder; | |
15710 | ||
15711 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15712 | return true; | |
15713 | ||
15714 | return false; | |
15715 | } | |
15716 | ||
dd756198 VS |
15717 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15718 | { | |
15719 | struct drm_device *dev = encoder->base.dev; | |
15720 | struct intel_connector *connector; | |
15721 | ||
15722 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15723 | return true; | |
15724 | ||
15725 | return false; | |
15726 | } | |
15727 | ||
24929352 DV |
15728 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15729 | { | |
15730 | struct drm_device *dev = crtc->base.dev; | |
15731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15732 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15733 | |
24929352 | 15734 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15735 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15736 | ||
d3eaf884 | 15737 | /* restore vblank interrupts to correct state */ |
9625604c | 15738 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15739 | if (crtc->active) { |
f9cd7b88 VS |
15740 | struct intel_plane *plane; |
15741 | ||
9625604c | 15742 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15743 | |
15744 | /* Disable everything but the primary plane */ | |
15745 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15746 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15747 | continue; | |
15748 | ||
15749 | plane->disable_plane(&plane->base, &crtc->base); | |
15750 | } | |
9625604c | 15751 | } |
d3eaf884 | 15752 | |
24929352 | 15753 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15754 | * disable the crtc (and hence change the state) if it is wrong. Note |
15755 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15756 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15757 | bool plane; |
15758 | ||
24929352 DV |
15759 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15760 | crtc->base.base.id); | |
15761 | ||
15762 | /* Pipe has the wrong plane attached and the plane is active. | |
15763 | * Temporarily change the plane mapping and disable everything | |
15764 | * ... */ | |
15765 | plane = crtc->plane; | |
b70709a6 | 15766 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15767 | crtc->plane = !plane; |
b17d48e2 | 15768 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15769 | crtc->plane = plane; |
24929352 | 15770 | } |
24929352 | 15771 | |
7fad798e DV |
15772 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15773 | crtc->pipe == PIPE_A && !crtc->active) { | |
15774 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15775 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15776 | * call below we restore the pipe to the right state, but leave | |
15777 | * the required bits on. */ | |
15778 | intel_enable_pipe_a(dev); | |
15779 | } | |
15780 | ||
24929352 DV |
15781 | /* Adjust the state of the output pipe according to whether we |
15782 | * have active connectors/encoders. */ | |
02e93c35 | 15783 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15784 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15785 | |
53d9f4e9 | 15786 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15787 | struct intel_encoder *encoder; |
24929352 DV |
15788 | |
15789 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15790 | * functions or because of calls to intel_crtc_disable_noatomic, |
15791 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15792 | * pipe A quirk. */ |
15793 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15794 | crtc->base.base.id, | |
83d65738 | 15795 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15796 | crtc->active ? "enabled" : "disabled"); |
15797 | ||
4be40c98 | 15798 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15799 | crtc->base.state->active = crtc->active; |
24929352 | 15800 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15801 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15802 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15803 | |
15804 | /* Because we only establish the connector -> encoder -> | |
15805 | * crtc links if something is active, this means the | |
15806 | * crtc is now deactivated. Break the links. connector | |
15807 | * -> encoder links are only establish when things are | |
15808 | * actually up, hence no need to break them. */ | |
15809 | WARN_ON(crtc->active); | |
15810 | ||
2d406bb0 | 15811 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15812 | encoder->base.crtc = NULL; |
24929352 | 15813 | } |
c5ab3bc0 | 15814 | |
a3ed6aad | 15815 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15816 | /* |
15817 | * We start out with underrun reporting disabled to avoid races. | |
15818 | * For correct bookkeeping mark this on active crtcs. | |
15819 | * | |
c5ab3bc0 DV |
15820 | * Also on gmch platforms we dont have any hardware bits to |
15821 | * disable the underrun reporting. Which means we need to start | |
15822 | * out with underrun reporting disabled also on inactive pipes, | |
15823 | * since otherwise we'll complain about the garbage we read when | |
15824 | * e.g. coming up after runtime pm. | |
15825 | * | |
4cc31489 DV |
15826 | * No protection against concurrent access is required - at |
15827 | * worst a fifo underrun happens which also sets this to false. | |
15828 | */ | |
15829 | crtc->cpu_fifo_underrun_disabled = true; | |
15830 | crtc->pch_fifo_underrun_disabled = true; | |
15831 | } | |
24929352 DV |
15832 | } |
15833 | ||
15834 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15835 | { | |
15836 | struct intel_connector *connector; | |
15837 | struct drm_device *dev = encoder->base.dev; | |
15838 | ||
15839 | /* We need to check both for a crtc link (meaning that the | |
15840 | * encoder is active and trying to read from a pipe) and the | |
15841 | * pipe itself being active. */ | |
15842 | bool has_active_crtc = encoder->base.crtc && | |
15843 | to_intel_crtc(encoder->base.crtc)->active; | |
15844 | ||
dd756198 | 15845 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15846 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15847 | encoder->base.base.id, | |
8e329a03 | 15848 | encoder->base.name); |
24929352 DV |
15849 | |
15850 | /* Connector is active, but has no active pipe. This is | |
15851 | * fallout from our resume register restoring. Disable | |
15852 | * the encoder manually again. */ | |
15853 | if (encoder->base.crtc) { | |
15854 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15855 | encoder->base.base.id, | |
8e329a03 | 15856 | encoder->base.name); |
24929352 | 15857 | encoder->disable(encoder); |
a62d1497 VS |
15858 | if (encoder->post_disable) |
15859 | encoder->post_disable(encoder); | |
24929352 | 15860 | } |
7f1950fb | 15861 | encoder->base.crtc = NULL; |
24929352 DV |
15862 | |
15863 | /* Inconsistent output/port/pipe state happens presumably due to | |
15864 | * a bug in one of the get_hw_state functions. Or someplace else | |
15865 | * in our code, like the register restore mess on resume. Clamp | |
15866 | * things to off as a safer default. */ | |
3a3371ff | 15867 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15868 | if (connector->encoder != encoder) |
15869 | continue; | |
7f1950fb EE |
15870 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15871 | connector->base.encoder = NULL; | |
24929352 DV |
15872 | } |
15873 | } | |
15874 | /* Enabled encoders without active connectors will be fixed in | |
15875 | * the crtc fixup. */ | |
15876 | } | |
15877 | ||
04098753 | 15878 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15879 | { |
15880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15881 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15882 | |
04098753 ID |
15883 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15884 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15885 | i915_disable_vga(dev); | |
15886 | } | |
15887 | } | |
15888 | ||
15889 | void i915_redisable_vga(struct drm_device *dev) | |
15890 | { | |
15891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15892 | ||
8dc8a27c PZ |
15893 | /* This function can be called both from intel_modeset_setup_hw_state or |
15894 | * at a very early point in our resume sequence, where the power well | |
15895 | * structures are not yet restored. Since this function is at a very | |
15896 | * paranoid "someone might have enabled VGA while we were not looking" | |
15897 | * level, just check if the power well is enabled instead of trying to | |
15898 | * follow the "don't touch the power well if we don't need it" policy | |
15899 | * the rest of the driver uses. */ | |
6392f847 | 15900 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15901 | return; |
15902 | ||
04098753 | 15903 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15904 | |
15905 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15906 | } |
15907 | ||
f9cd7b88 | 15908 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15909 | { |
f9cd7b88 | 15910 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15911 | |
f9cd7b88 | 15912 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15913 | } |
15914 | ||
f9cd7b88 VS |
15915 | /* FIXME read out full plane state for all planes */ |
15916 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15917 | { |
b26d3ea3 | 15918 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15919 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15920 | to_intel_plane_state(primary->state); |
d032ffa0 | 15921 | |
19b8d387 | 15922 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15923 | primary_get_hw_state(to_intel_plane(primary)); |
15924 | ||
15925 | if (plane_state->visible) | |
15926 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15927 | } |
15928 | ||
30e984df | 15929 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15930 | { |
15931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15932 | enum pipe pipe; | |
24929352 DV |
15933 | struct intel_crtc *crtc; |
15934 | struct intel_encoder *encoder; | |
15935 | struct intel_connector *connector; | |
5358901f | 15936 | int i; |
24929352 | 15937 | |
565602d7 ML |
15938 | dev_priv->active_crtcs = 0; |
15939 | ||
d3fcc808 | 15940 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15941 | struct intel_crtc_state *crtc_state = crtc->config; |
15942 | int pixclk = 0; | |
3b117c8f | 15943 | |
565602d7 ML |
15944 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15945 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15946 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15947 | |
565602d7 ML |
15948 | crtc_state->base.active = crtc_state->base.enable = |
15949 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15950 | ||
15951 | crtc->base.enabled = crtc_state->base.enable; | |
15952 | crtc->active = crtc_state->base.active; | |
15953 | ||
15954 | if (crtc_state->base.active) { | |
15955 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15956 | ||
15957 | if (IS_BROADWELL(dev_priv)) { | |
15958 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15959 | ||
15960 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15961 | if (crtc_state->ips_enabled) | |
15962 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15963 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15964 | IS_CHERRYVIEW(dev_priv) || | |
15965 | IS_BROXTON(dev_priv)) | |
15966 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15967 | else | |
15968 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15969 | } | |
15970 | ||
15971 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15972 | |
f9cd7b88 | 15973 | readout_plane_state(crtc); |
24929352 DV |
15974 | |
15975 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15976 | crtc->base.base.id, | |
15977 | crtc->active ? "enabled" : "disabled"); | |
15978 | } | |
15979 | ||
5358901f DV |
15980 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15981 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15982 | ||
3e369b76 ACO |
15983 | pll->on = pll->get_hw_state(dev_priv, pll, |
15984 | &pll->config.hw_state); | |
5358901f | 15985 | pll->active = 0; |
3e369b76 | 15986 | pll->config.crtc_mask = 0; |
d3fcc808 | 15987 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15988 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15989 | pll->active++; |
3e369b76 | 15990 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15991 | } |
5358901f | 15992 | } |
5358901f | 15993 | |
1e6f2ddc | 15994 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15995 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15996 | |
3e369b76 | 15997 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15998 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15999 | } |
16000 | ||
b2784e15 | 16001 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16002 | pipe = 0; |
16003 | ||
16004 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
16005 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16006 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 16007 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16008 | } else { |
16009 | encoder->base.crtc = NULL; | |
16010 | } | |
16011 | ||
6f2bcceb | 16012 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16013 | encoder->base.base.id, |
8e329a03 | 16014 | encoder->base.name, |
24929352 | 16015 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16016 | pipe_name(pipe)); |
24929352 DV |
16017 | } |
16018 | ||
3a3371ff | 16019 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16020 | if (connector->get_hw_state(connector)) { |
16021 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16022 | |
16023 | encoder = connector->encoder; | |
16024 | connector->base.encoder = &encoder->base; | |
16025 | ||
16026 | if (encoder->base.crtc && | |
16027 | encoder->base.crtc->state->active) { | |
16028 | /* | |
16029 | * This has to be done during hardware readout | |
16030 | * because anything calling .crtc_disable may | |
16031 | * rely on the connector_mask being accurate. | |
16032 | */ | |
16033 | encoder->base.crtc->state->connector_mask |= | |
16034 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16035 | encoder->base.crtc->state->encoder_mask |= |
16036 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16037 | } |
16038 | ||
24929352 DV |
16039 | } else { |
16040 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16041 | connector->base.encoder = NULL; | |
16042 | } | |
16043 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16044 | connector->base.base.id, | |
c23cc417 | 16045 | connector->base.name, |
24929352 DV |
16046 | connector->base.encoder ? "enabled" : "disabled"); |
16047 | } | |
7f4c6284 VS |
16048 | |
16049 | for_each_intel_crtc(dev, crtc) { | |
16050 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16051 | ||
16052 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16053 | if (crtc->base.state->active) { | |
16054 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16055 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16056 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16057 | ||
16058 | /* | |
16059 | * The initial mode needs to be set in order to keep | |
16060 | * the atomic core happy. It wants a valid mode if the | |
16061 | * crtc's enabled, so we do the above call. | |
16062 | * | |
16063 | * At this point some state updated by the connectors | |
16064 | * in their ->detect() callback has not run yet, so | |
16065 | * no recalculation can be done yet. | |
16066 | * | |
16067 | * Even if we could do a recalculation and modeset | |
16068 | * right now it would cause a double modeset if | |
16069 | * fbdev or userspace chooses a different initial mode. | |
16070 | * | |
16071 | * If that happens, someone indicated they wanted a | |
16072 | * mode change, which means it's safe to do a full | |
16073 | * recalculation. | |
16074 | */ | |
16075 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16076 | |
16077 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16078 | update_scanline_offset(crtc); | |
7f4c6284 | 16079 | } |
e3b247da VS |
16080 | |
16081 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16082 | } |
30e984df DV |
16083 | } |
16084 | ||
043e9bda ML |
16085 | /* Scan out the current hw modeset state, |
16086 | * and sanitizes it to the current state | |
16087 | */ | |
16088 | static void | |
16089 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
16090 | { |
16091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
16092 | enum pipe pipe; | |
30e984df DV |
16093 | struct intel_crtc *crtc; |
16094 | struct intel_encoder *encoder; | |
35c95375 | 16095 | int i; |
30e984df DV |
16096 | |
16097 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16098 | |
16099 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16100 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16101 | intel_sanitize_encoder(encoder); |
16102 | } | |
16103 | ||
055e393f | 16104 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
16105 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
16106 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
16107 | intel_dump_pipe_config(crtc, crtc->config, |
16108 | "[setup_hw_state]"); | |
24929352 | 16109 | } |
9a935856 | 16110 | |
d29b2f9d ACO |
16111 | intel_modeset_update_connector_atomic_state(dev); |
16112 | ||
35c95375 DV |
16113 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16114 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16115 | ||
16116 | if (!pll->on || pll->active) | |
16117 | continue; | |
16118 | ||
16119 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16120 | ||
16121 | pll->disable(dev_priv, pll); | |
16122 | pll->on = false; | |
16123 | } | |
16124 | ||
666a4537 | 16125 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
16126 | vlv_wm_get_hw_state(dev); |
16127 | else if (IS_GEN9(dev)) | |
3078999f PB |
16128 | skl_wm_get_hw_state(dev); |
16129 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 16130 | ilk_wm_get_hw_state(dev); |
292b990e ML |
16131 | |
16132 | for_each_intel_crtc(dev, crtc) { | |
16133 | unsigned long put_domains; | |
16134 | ||
74bff5f9 | 16135 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
16136 | if (WARN_ON(put_domains)) |
16137 | modeset_put_power_domains(dev_priv, put_domains); | |
16138 | } | |
16139 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
16140 | |
16141 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 16142 | } |
7d0bc1ea | 16143 | |
043e9bda ML |
16144 | void intel_display_resume(struct drm_device *dev) |
16145 | { | |
e2c8b870 ML |
16146 | struct drm_i915_private *dev_priv = to_i915(dev); |
16147 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
16148 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 16149 | int ret; |
e2c8b870 | 16150 | bool setup = false; |
f30da187 | 16151 | |
e2c8b870 | 16152 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 16153 | |
ea49c9ac ML |
16154 | /* |
16155 | * This is a cludge because with real atomic modeset mode_config.mutex | |
16156 | * won't be taken. Unfortunately some probed state like | |
16157 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
16158 | * it here for now. | |
16159 | */ | |
16160 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 16161 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 16162 | |
e2c8b870 ML |
16163 | retry: |
16164 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 16165 | |
e2c8b870 ML |
16166 | if (ret == 0 && !setup) { |
16167 | setup = true; | |
043e9bda | 16168 | |
e2c8b870 ML |
16169 | intel_modeset_setup_hw_state(dev); |
16170 | i915_redisable_vga(dev); | |
45e2b5f6 | 16171 | } |
8af6cf88 | 16172 | |
e2c8b870 ML |
16173 | if (ret == 0 && state) { |
16174 | struct drm_crtc_state *crtc_state; | |
16175 | struct drm_crtc *crtc; | |
16176 | int i; | |
043e9bda | 16177 | |
e2c8b870 ML |
16178 | state->acquire_ctx = &ctx; |
16179 | ||
16180 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
16181 | /* | |
16182 | * Force recalculation even if we restore | |
16183 | * current state. With fast modeset this may not result | |
16184 | * in a modeset when the state is compatible. | |
16185 | */ | |
16186 | crtc_state->mode_changed = true; | |
16187 | } | |
16188 | ||
16189 | ret = drm_atomic_commit(state); | |
043e9bda ML |
16190 | } |
16191 | ||
e2c8b870 ML |
16192 | if (ret == -EDEADLK) { |
16193 | drm_modeset_backoff(&ctx); | |
16194 | goto retry; | |
16195 | } | |
043e9bda | 16196 | |
e2c8b870 ML |
16197 | drm_modeset_drop_locks(&ctx); |
16198 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 16199 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 16200 | |
e2c8b870 ML |
16201 | if (ret) { |
16202 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16203 | drm_atomic_state_free(state); | |
16204 | } | |
2c7111db CW |
16205 | } |
16206 | ||
16207 | void intel_modeset_gem_init(struct drm_device *dev) | |
16208 | { | |
484b41dd | 16209 | struct drm_crtc *c; |
2ff8fde1 | 16210 | struct drm_i915_gem_object *obj; |
e0d6149b | 16211 | int ret; |
484b41dd | 16212 | |
ae48434c | 16213 | intel_init_gt_powersave(dev); |
ae48434c | 16214 | |
1833b134 | 16215 | intel_modeset_init_hw(dev); |
02e792fb DV |
16216 | |
16217 | intel_setup_overlay(dev); | |
484b41dd JB |
16218 | |
16219 | /* | |
16220 | * Make sure any fbs we allocated at startup are properly | |
16221 | * pinned & fenced. When we do the allocation it's too early | |
16222 | * for this. | |
16223 | */ | |
70e1e0ec | 16224 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16225 | obj = intel_fb_obj(c->primary->fb); |
16226 | if (obj == NULL) | |
484b41dd JB |
16227 | continue; |
16228 | ||
e0d6149b | 16229 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
16230 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
16231 | c->primary->state->rotation); | |
e0d6149b TU |
16232 | mutex_unlock(&dev->struct_mutex); |
16233 | if (ret) { | |
484b41dd JB |
16234 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16235 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16236 | drm_framebuffer_unreference(c->primary->fb); |
16237 | c->primary->fb = NULL; | |
36750f28 | 16238 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16239 | update_state_fb(c->primary); |
36750f28 | 16240 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16241 | } |
16242 | } | |
0962c3c9 VS |
16243 | |
16244 | intel_backlight_register(dev); | |
79e53945 JB |
16245 | } |
16246 | ||
4932e2c3 ID |
16247 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16248 | { | |
16249 | struct drm_connector *connector = &intel_connector->base; | |
16250 | ||
16251 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16252 | drm_connector_unregister(connector); |
4932e2c3 ID |
16253 | } |
16254 | ||
79e53945 JB |
16255 | void intel_modeset_cleanup(struct drm_device *dev) |
16256 | { | |
652c393a | 16257 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16258 | struct intel_connector *connector; |
652c393a | 16259 | |
2eb5252e ID |
16260 | intel_disable_gt_powersave(dev); |
16261 | ||
0962c3c9 VS |
16262 | intel_backlight_unregister(dev); |
16263 | ||
fd0c0642 DV |
16264 | /* |
16265 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16266 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16267 | * experience fancy races otherwise. |
16268 | */ | |
2aeb7d3a | 16269 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16270 | |
fd0c0642 DV |
16271 | /* |
16272 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16273 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16274 | */ | |
f87ea761 | 16275 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16276 | |
723bfd70 JB |
16277 | intel_unregister_dsm_handler(); |
16278 | ||
c937ab3e | 16279 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16280 | |
1630fe75 CW |
16281 | /* flush any delayed tasks or pending work */ |
16282 | flush_scheduled_work(); | |
16283 | ||
db31af1d | 16284 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16285 | for_each_intel_connector(dev, connector) |
16286 | connector->unregister(connector); | |
d9255d57 | 16287 | |
79e53945 | 16288 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16289 | |
16290 | intel_cleanup_overlay(dev); | |
ae48434c | 16291 | |
ae48434c | 16292 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16293 | |
16294 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16295 | } |
16296 | ||
f1c79df3 ZW |
16297 | /* |
16298 | * Return which encoder is currently attached for connector. | |
16299 | */ | |
df0e9248 | 16300 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16301 | { |
df0e9248 CW |
16302 | return &intel_attached_encoder(connector)->base; |
16303 | } | |
f1c79df3 | 16304 | |
df0e9248 CW |
16305 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16306 | struct intel_encoder *encoder) | |
16307 | { | |
16308 | connector->encoder = encoder; | |
16309 | drm_mode_connector_attach_encoder(&connector->base, | |
16310 | &encoder->base); | |
79e53945 | 16311 | } |
28d52043 DA |
16312 | |
16313 | /* | |
16314 | * set vga decode state - true == enable VGA decode | |
16315 | */ | |
16316 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16317 | { | |
16318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16319 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16320 | u16 gmch_ctrl; |
16321 | ||
75fa041d CW |
16322 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16323 | DRM_ERROR("failed to read control word\n"); | |
16324 | return -EIO; | |
16325 | } | |
16326 | ||
c0cc8a55 CW |
16327 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16328 | return 0; | |
16329 | ||
28d52043 DA |
16330 | if (state) |
16331 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16332 | else | |
16333 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16334 | |
16335 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16336 | DRM_ERROR("failed to write control word\n"); | |
16337 | return -EIO; | |
16338 | } | |
16339 | ||
28d52043 DA |
16340 | return 0; |
16341 | } | |
c4a1d9e4 | 16342 | |
c4a1d9e4 | 16343 | struct intel_display_error_state { |
ff57f1b0 PZ |
16344 | |
16345 | u32 power_well_driver; | |
16346 | ||
63b66e5b CW |
16347 | int num_transcoders; |
16348 | ||
c4a1d9e4 CW |
16349 | struct intel_cursor_error_state { |
16350 | u32 control; | |
16351 | u32 position; | |
16352 | u32 base; | |
16353 | u32 size; | |
52331309 | 16354 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16355 | |
16356 | struct intel_pipe_error_state { | |
ddf9c536 | 16357 | bool power_domain_on; |
c4a1d9e4 | 16358 | u32 source; |
f301b1e1 | 16359 | u32 stat; |
52331309 | 16360 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16361 | |
16362 | struct intel_plane_error_state { | |
16363 | u32 control; | |
16364 | u32 stride; | |
16365 | u32 size; | |
16366 | u32 pos; | |
16367 | u32 addr; | |
16368 | u32 surface; | |
16369 | u32 tile_offset; | |
52331309 | 16370 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16371 | |
16372 | struct intel_transcoder_error_state { | |
ddf9c536 | 16373 | bool power_domain_on; |
63b66e5b CW |
16374 | enum transcoder cpu_transcoder; |
16375 | ||
16376 | u32 conf; | |
16377 | ||
16378 | u32 htotal; | |
16379 | u32 hblank; | |
16380 | u32 hsync; | |
16381 | u32 vtotal; | |
16382 | u32 vblank; | |
16383 | u32 vsync; | |
16384 | } transcoder[4]; | |
c4a1d9e4 CW |
16385 | }; |
16386 | ||
16387 | struct intel_display_error_state * | |
16388 | intel_display_capture_error_state(struct drm_device *dev) | |
16389 | { | |
fbee40df | 16390 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16391 | struct intel_display_error_state *error; |
63b66e5b CW |
16392 | int transcoders[] = { |
16393 | TRANSCODER_A, | |
16394 | TRANSCODER_B, | |
16395 | TRANSCODER_C, | |
16396 | TRANSCODER_EDP, | |
16397 | }; | |
c4a1d9e4 CW |
16398 | int i; |
16399 | ||
63b66e5b CW |
16400 | if (INTEL_INFO(dev)->num_pipes == 0) |
16401 | return NULL; | |
16402 | ||
9d1cb914 | 16403 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16404 | if (error == NULL) |
16405 | return NULL; | |
16406 | ||
190be112 | 16407 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16408 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16409 | ||
055e393f | 16410 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16411 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16412 | __intel_display_power_is_enabled(dev_priv, |
16413 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16414 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16415 | continue; |
16416 | ||
5efb3e28 VS |
16417 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16418 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16419 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16420 | |
16421 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16422 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16423 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16424 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16425 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16426 | } | |
ca291363 PZ |
16427 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16428 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16429 | if (INTEL_INFO(dev)->gen >= 4) { |
16430 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16431 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16432 | } | |
16433 | ||
c4a1d9e4 | 16434 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16435 | |
3abfce77 | 16436 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16437 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16438 | } |
16439 | ||
16440 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16441 | if (HAS_DDI(dev_priv->dev)) | |
16442 | error->num_transcoders++; /* Account for eDP. */ | |
16443 | ||
16444 | for (i = 0; i < error->num_transcoders; i++) { | |
16445 | enum transcoder cpu_transcoder = transcoders[i]; | |
16446 | ||
ddf9c536 | 16447 | error->transcoder[i].power_domain_on = |
f458ebbc | 16448 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16449 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16450 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16451 | continue; |
16452 | ||
63b66e5b CW |
16453 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16454 | ||
16455 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16456 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16457 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16458 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16459 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16460 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16461 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16462 | } |
16463 | ||
16464 | return error; | |
16465 | } | |
16466 | ||
edc3d884 MK |
16467 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16468 | ||
c4a1d9e4 | 16469 | void |
edc3d884 | 16470 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16471 | struct drm_device *dev, |
16472 | struct intel_display_error_state *error) | |
16473 | { | |
055e393f | 16474 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16475 | int i; |
16476 | ||
63b66e5b CW |
16477 | if (!error) |
16478 | return; | |
16479 | ||
edc3d884 | 16480 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16481 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16482 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16483 | error->power_well_driver); |
055e393f | 16484 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16485 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16486 | err_printf(m, " Power: %s\n", |
87ad3212 | 16487 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16488 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16489 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16490 | |
16491 | err_printf(m, "Plane [%d]:\n", i); | |
16492 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16493 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16494 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16495 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16496 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16497 | } |
4b71a570 | 16498 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16499 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16500 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16501 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16502 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16503 | } |
16504 | ||
edc3d884 MK |
16505 | err_printf(m, "Cursor [%d]:\n", i); |
16506 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16507 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16508 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16509 | } |
63b66e5b CW |
16510 | |
16511 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16512 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16513 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16514 | err_printf(m, " Power: %s\n", |
87ad3212 | 16515 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16516 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16517 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16518 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16519 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16520 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16521 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16522 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16523 | } | |
c4a1d9e4 | 16524 | } |